diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..1b653cfb --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "tools/superpowers"] + path = tools/superpowers + url = https://github.com/obra/superpowers.git diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-11-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-11-report.md new file mode 100644 index 00000000..a6dd9e4e --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-11-report.md @@ -0,0 +1,432 @@ +# Task 11 Report: Canonical OOO D3/S1 Production Cutover + +## Result + +Task 11 cuts the public `linxcore.ooo.OOO` module onto one canonical +D1-through-S1 owner graph. RENU, ROB, BROB, Dispatch, CommitControl, and +RecoveryControl now share the one D3 publication boundary; the production +graph does not instantiate `OooO3RenameCoordinator` or any displaced legacy +ROB/BROB/rename/recovery wrapper. + +Baseline LinxCore commit: `5f80ea0ba0dc563f097082f2f0cf59d42b816e16`. +Baseline superproject commit: `54635e8cb1119e5f199228cb7db330b168bf7dc0`. +Baseline LinxCoreModel commit: `31555fbcb147db4bba20ab7031c40a4800635306`. +Baseline QEMU commit: `c9f9570aa70da7e193ff8857bd9bde2cf052e546`. + +Final commit SHA is reported from `git rev-parse HEAD` after commit creation; +it cannot be embedded self-referentially in the same commit object. + +## RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec` failed at + compile with `not found: type Dispatch`, proving the canonical D3/S1 public + boundary did not exist before implementation. + +## Canonical Mapping + +- `D3RenameGroup` is retained only after the caller-controlled common ROB, + BROB, and dispatch publication fire. Exact ROB/BROB prepared counts and + lane identities are required before dispatch reports ready. +- The ROB-prepared `RobIdentity` replaces the provisional identity in every + active retained uop; all other renamed uop fields are preserved. +- `OooHierarchicalFreeSlotSelect` is in the live `OooDispatch` graph and + selects the oldest active suffix lane. It now supports the canonical W6 + non-power-of-two width while retaining power-of-two group sizing. +- Dispatch drains one continuous oldest-first prefix. Backpressure retains + only the undispatched suffix and preserves transaction IDs. +- Stores require atomic AGU and STD credit and send identical transactions to + both channels. CMD remains independent from system/multicycle dispatch. +- Early-complete and boundary lanes consume no dispatch channel; completion + remains owned by the Task-9 ROB publication path. +- Recovery apply suppresses coincident traffic and removes only a matching + target-STID retained suffix. Abort is non-mutating. + +## Displaced Entry-Point Audit + +| Displaced production surface | Canonical owner / surviving coverage | +| --- | --- | +| `OooO3RenameCoordinator`, `OooO3IexStorePipeline` | public `OOO` + `Dispatch`; `OOODispatchSpec`, `OOOIntegrationSpec` | +| `OooD3ReservationAllocator` legacy reservation protocol, legacy `OooDispatch` protocol | mechanisms refactored in place onto canonical payloads; exact prepare reject, suffix retry, atomic credit, recovery, width, and selector tests migrated to `OOODispatchSpec` and `OooHierarchicalFreeSlotSelectSpec` | +| `OooS1GroupedRob`, `OooBrob`, `OooRobBrobPcCoordinator` | `ROB` + `BROB`; `OOORobCommitSpec`, `OOORecoverySpec`, `OOOIntegrationSpec` | +| `OooRobStoreCommitOwner` | `CommitControl` + `ROB`; `OOORobCommitSpec` | +| `OooPRename`, `OooTURename` | `RENU` / `PRename` / `TURename`; `RENUSpec`, `RENUAtomicSpec`, `TURenameSequenceSpec` | +| `OooCtuIngressBridge`, `OooIfuD1Ingress`, `OooIfuRawIngress` | `CTU` / `OOOD1D2Stage` / canonical public interfaces; `CTUOOOIntegrationSpec`, `OOODecodeSpec`, `OOOIntegrationSpec` | +| `OooFrontendRecoveryBridge` | `RecoveryControl` plus typed `RecoveryTargetIO`; `OOORecoverySpec` and public graph elaboration | + +The manifest deletes the displaced public wrappers and their wrapper-specific +tests. Still-reused mechanism coverage is retained under the canonical tests +listed above; no legacy public owner is kept solely for test compatibility. + +## Production Inventory + +- The production-owner manifest now records public `OOO` as the active caller + for canonical rename, ROB, BROB, commit, and recovery owners, and records + `Dispatch` as the caller for the dispatch-reservation mechanisms. +- The exact managed-boundary inventory removes the deleted CTU ingress and + frontend recovery adapters. Checker fixtures were updated to use a still + planned-active deletion target rather than the completed dispatch cutover. +- `OooFrontendRecoveryContract.scala` retains only the stateless recovery-plan + projection helper still used by the later composition graph; it is not an + owner or payload adapter. + +## Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec` - PASS, 5 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OooHierarchicalFreeSlotSelectSpec` - PASS, 3 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec` - PASS, 4 tests including adjacent CTU integration and W2/W4/W6/W8 public graph elaboration. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 43 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `python3 tools/chisel/check_production_owner_manifest.py` - PASS, 23 closed owners, 40 classified emitters, 10 declared adapters, NDF roles mapped. +- `python3 -m unittest tests.test_production_owner_manifest` - PASS, 40 tests. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=116 l1_must=53 verified=61 open_questions=0 references=2`. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, manifest up to date. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS, Verilator 5.044, 67 modules, zero errors. +- `git diff --check` - PASS. + +## Self-Review + +- The public graph contains one instance of each canonical state owner and no + O3 rename coordinator. +- The dispatch allocator owns only one retained published packet, suffix + cursor, transaction sequence, and local recovery acknowledgement state; it + does not duplicate architectural or residency ownership. +- The free-slot selector is reachable from canonical production dispatch and + has explicit W6 coverage. +- Deleted wrapper tests were checked against canonical replacement suites; + coverage tied only to displaced payloads or duplicate owners was removed. +- No generated interface drift, temporary adapter, debug output, new + dependency, or unrelated source change remains. +- `skill-evolve: no-update` - the canonical ownership and verification rules + are already captured by the LinxCore skill and Task-11 NDF clauses. + +## Fix Round 1 + +This round supersedes the original dispatch-handshake, production-evidence, +and test-count statements above where they conflict. + +### RED evidence + +- New valid-independent dispatch checks failed because ALU/store `valid` was + suppressed while `ready` was low, and the retained packet was not observable + to a wait-for-valid consumer. +- A focused allocator check failed because an accepted `io.in.fire` could be + discarded when the separate `publishFire` input was false. +- The four-STID integration test initially failed to compile because no + canonical D3-through-S1 production graph existed as a reusable test target; + subsequent runs exposed and removed a RENU ready/recovery combinational cycle + and corrected the external recovery-target test handshake. +- Two new manifest-checker tests failed because invented declared callers and + undeclared real main-Scala constructors were both accepted. +- A bounded documentation search found the deleted + `OooO3RenameCoordinator` and `OooO3IexStorePipeline` still described as live + production owners with commands for deleted suites. + +### Corrections + +- Every dispatch output now asserts `valid` from retained state independently + of its own `ready` and keeps payload stable until acceptance. Stores use one + paired `StoreDispatchTxn` acceptance carrying identical STA/STD transactions + and selected AGU/STD pipe indices, so no partial store side effect is visible + at the OOO/IEX boundary. +- `OooD3ReservationAllocator` retains exactly on `io.in.fire`; the redundant + `publishFire` qualifier was removed. The canonical graph exposes Dispatch + input only after side-effect-free ROB/BROB prepare readiness, so that one + Decoupled fire is also the common D3 publication fire. +- `OOOD3S1Graph` is the exact production child instantiated by public `OOO` and + by the bounded behavioral integration test. The test publishes two + operations on each of four STIDs across P/T/U/zero destinations, checks + owner snapshots, applies Branch survivor and MemoryOrder trigger-kill + recovery, and proves unrelated-STID isolation. Public `OOO` elaboration at + W2/W4/W6/W8 proves every canonical owner is reachable and displaced owners + are absent. +- The production-owner checker now discovers the exact main-Scala constructor + callers for each canonical owner, including companion class/object + definitions. Test fixtures remain only under `verification_fixtures`. + Standalone rename evidence is reported as `standalone-verified`. +- The displaced wrapper pages and module-index row were deleted or rewritten; + Task-12 handoff now points at the surviving execution/store mechanisms until + public `IEX` exists. + +### Verification + +- `LINX_CHISEL_SBT_MEM_MB=4096 ... --only OOOIntegrationSpec` - PASS, 5 total: + `OOOIntegrationSpec` 2 and separately selected adjacent + `CTUOOOIntegrationSpec` 3. +- `... --only OOODispatchSpec` - PASS, 7 tests. +- `... --only OOORecoverySpec` - PASS, 43 tests. +- `... --only OOORobCommitSpec` - PASS, 21 tests. +- `... --only RENUAtomicSpec` - PASS, 7 tests. +- `... --only RENUSpec` - PASS, 15 tests. +- `... --only OooHierarchicalFreeSlotSelectSpec` - PASS, 3 tests. +- `... --only TopInterfaceSpec` - PASS, 9 tests. +- `... --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 -m unittest tests.test_production_owner_manifest` - PASS, 42 tests. +- `python3 tools/chisel/check_production_owner_manifest.py` - PASS, 23 closed + owners, 40 classified emitters, 10 declared adapters. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=116 l1_must=53 verified=61 open_questions=0 references=2`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS, Verilator 5.044, + 67 modules, zero errors. +- `git diff --check` - PASS. + +## Fix Round 2 + +This round supersedes the original documentation-reference and commit-control +evidence statements above where they conflict. + +### RED evidence + +- `python3 tools/chisel/check_deleted_ooo_doc_references.py` initially found 23 + live documentation lines that still named deleted + `OooO3RenameCoordinator` or `OooO3IexStorePipeline` wrappers. +- A new manifest unit test failed because the checker accepted an invented + behavioral evidence case that did not exist in its declared fixture. +- The new canonical completion-to-commit integration case first exposed a + one-uop fixture bug: the generalized publisher still advertised a two-row + packet. After that was corrected, exact completion was accepted and ROB + produced a commit preview, but public commit remained blocked because ROB + release preflight required the row to be retired before the common commit + fire that performs retirement. +- An earlier oversized W2 simulation was terminated as a resource-only run and + is excluded from behavioral evidence; every result below is from a fresh + bounded run. + +### Corrections + +- All requested live documentation now routes through public `OOO`, + `OOOD3S1Graph`, `RecoveryControl`, RENU/Dispatch, or the surviving + `OooIexExecutionStorePipeline`. Historical `agent-loop.md` records remain + unchanged. The persistent documentation gate rejects future live references + to either deleted wrapper while allowing explicitly historical records. +- Production evidence may name an exact ScalaTest case. The owner checker now + verifies that the declared fixture contains the exact `test("...")`, and + CommitControl L3 evidence names the canonical behavioral integration case. +- `OOOIntegrationSpec` publishes one ordinary GPR-destination ALU uop through + `OOOD3S1Graph`, supplies its exact dispatched ROB identity on the public + completion port, proves the commit is stable under backpressure, accepts one + ordered commit, and proves no duplicate appears. +- ROB release preflight now validates the exact live completed head instead of + requiring a retirement that cannot occur until the same common fire. + `OOOD3S1Graph` asserts that every non-empty commit fire has ROB, rename, and + BROB release readiness, and the ROB unit test proves preflight is + non-mutating before simultaneous commit/release apply. + +### Verification + +- `LINX_CHISEL_SBT_MEM_MB=4096 ... --only OOOIntegrationSpec` - PASS, 6 tests. +- `LINX_CHISEL_SBT_MEM_MB=4096 ... --only OOORobCommitSpec` - PASS, 21 tests. +- `LINX_CHISEL_SBT_MEM_MB=4096 ... --only OOORecoverySpec` - PASS, 43 tests. +- `python3 -m unittest tests.test_production_owner_manifest` - PASS, 43 tests. +- `python3 tools/chisel/check_production_owner_manifest.py` - PASS, 23 closed + owners, 40 classified emitters, 10 declared adapters. +- `python3 tools/chisel/check_deleted_ooo_doc_references.py` - PASS, no live + deleted-wrapper references. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=116 l1_must=53 verified=61 open_questions=0 references=2`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS, Verilator 5.044, + 67 modules, zero errors. +- `git diff --check` - PASS. + +## Fix Round 3 + +This round supersedes the Fix Round 2 documentation-inventory and four-STID +debug-observation statements where they conflict. + +### RED evidence + +- New documentation-checker fixtures containing every owner and test suite + deleted by `5f80ea0b..1375436f` initially passed because the checker knew + only two wrappers. An arbitrary line containing the word `historical` also + bypassed the old marker-based exemption. +- Exact-location fixtures initially showed that the checker had no + `--doc-root` seam and no path-plus-heading allowlist. A surviving prefixed + type fixture then exposed false positives from substring matching. +- Removing `debugPMap`, `debugTCount`, `debugUCount`, `debugBrobUsed`, and + `debugDispatchPending` from `OOOD3S1GraphIO` produced the expected compile + failure in the old four-STID test at every debug observation. +- The first public-only rewrite passed five of six integration tests and + localized its remaining failures to over-demanded post-recovery and + multi-entry retirement observations. The final scenario uses only public + protocol outcomes required by this integration boundary. + +### Corrections + +- The documentation gate now carries the exact 12-owner and 23-suite deleted + Task 11 inventory. Exact Scala identifiers are rejected in live prose; + stripped suite names are rejected only in `--only` runner commands, so live + owners and prefixed bundle types remain legal. +- Historical exemptions are limited to `agent-loop.md` under + `## Suggested Next Packets` and `mainline-loop-ledger.md` under the exact + Loop 9 heading. Tests prove that the same headings at another path, or other + headings at those paths, do not bypass the gate. +- Live documentation now names the canonical `OOO`/`OOOD3S1Graph`, `ROB`, + `BROB`, `RENU`/`PRename`/`TURename`, `CommitControl`, `RecoveryControl`, CTU, + and current replacement suites. Five displaced wrapper pages were renamed + to their canonical owner names. +- `OOOD3S1Graph` no longer exports or wires any of the five test-only debug + signals. The four-STID integration captures public dispatch identities and + P/T/U tags, proves valid/payload stability under stall, completes and commits + exact peer/survivor identities, checks killed completions produce no commit, + verifies peer tail isolation, and uses post-recovery dispatch tag reuse to + prove target rollback. + +### Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec` - PASS, + 6 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 43 tests. +- `python3 -m unittest tests.test_production_owner_manifest` - PASS, 43 tests. +- `python3 tools/chisel/check_production_owner_manifest.py` - PASS, 23 closed + owners, 40 classified emitters, 10 declared adapters. +- `python3 -m unittest tests.test_deleted_ooo_doc_references` - PASS, 7 tests. +- `python3 tools/chisel/check_deleted_ooo_doc_references.py` - PASS, no live + deleted Task 11 references. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=116 l1_must=53 verified=61 open_questions=0 references=2`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS, Verilator 5.044, + 67 modules, zero errors. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + manifest up to date. +- `git diff --check` - PASS. + +## Fix Round 4 + +This round supersedes the Fix Round 2 commit-coherency evidence and the Fix +Round 3 documentation-scope and four-STID peer-survival evidence where they +conflict. + +### RED evidence + +- The new canonical graph regression completed row 0, held its one-row public + commit under backpressure, completed row 1 while stalled, and then timed out + waiting for row 1 after accepting row 0 (`64 was not less than 64`). The live + ROB preview had expanded to two rows while `CommitControl` retained one row, + and ROB apply consumed the live count instead of the retained transaction. +- After ROB apply was switched to the retained release prefix, the same test + localized a second coherency defect: ROB and BROB release preflights were + ready, but RENU remained blocked. Bounded diagnostic evidence showed the P + MapQ retained row 1 with row 0's provisional BID identity while the retained + commit carried row 1's ROB/BROB-prepared full identity. Temporary diagnostic + prints were removed before GREEN. +- The nested `docs/architecture` unit fixture failed with checker argument + status 2 because the gate had no repository-root/default `docs/**` scan and + still defaulted to `docs/chisel`. +- The first peer-survival rewrite caught its own stale tail expectation after + publishing a post-recovery peer probe; the corrected scenario snapshots the + peer tail after that accepted publication. + +### Corrections + +- `CommitControl`'s retained `CommitControlTxn` is the authoritative public and + owner-apply transaction. ROB retirement uses its exact ROB release prefix + when the canonical common apply is present, rather than the possibly newer + live preview count. Standalone ROB tests retain their direct-preview fallback. + The graph asserts equal commit/rename/ROB/BROB release counts and full + `RobIdentity` equality for every active lane; ROB additionally asserts that + the authoritative prefix is an exact live-preview prefix before mutation. +- RENU now receives the ROB-prepared publication identity sidecar at canonical + D3 fire and publishes those full identities into both P and T/U MapQ owners. + This closes the provisional-BID mismatch without adding another owner or + changing standalone RENU semantics. +- `OOOIntegrationSpec` proves the canonical failure sequence end to end: + complete row 0, stall its one-row commit, complete row 1, accept row 0, then + accept row 1 exactly once. The same public graph proves synchronized ROB, + RENU, and BROB release through the absence of a stranded row. +- The four-STID scenario now leaves peer rows resident across both Branch and + MemoryOrder recovery. After each recovery it completes and commits the + captured peer head, publishes another peer row, and proves the still-resident + peer tail's physical tag was not rolled back or reallocated. +- The deleted-reference gate defaults to all `docs/**`, supports a repository + root seam for nested fixtures, and keeps exemptions limited to exact + path-plus-heading historical allowlists. Live + `docs/architecture/code_template_unit.md` now names `CTU`, `OOOD1D2Stage`, + `RecoveryControl`, and `ROB`; the stale `OooTURename` ownership comment now + names `TURename`. Exact identifier boundaries continue to allow surviving + current and prefixed names. + +### Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec` - PASS, + 7 tests total: 4 canonical OOO integration tests plus 3 adjacent CTU tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 43 tests. +- `python3 -m unittest tests.test_production_owner_manifest` - PASS, 43 tests. +- `python3 tools/chisel/check_production_owner_manifest.py` - PASS, 23 closed + owners, 40 classified emitters, 10 declared adapters, NDF roles mapped. +- `python3 -m unittest tests.test_deleted_ooo_doc_references` - PASS, 8 tests. +- `python3 tools/chisel/check_deleted_ooo_doc_references.py` - PASS, no live + deleted Task 11 references under `docs/**`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=116 l1_must=53 verified=61 open_questions=0 references=2`. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + manifest up to date. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS, Verilator 5.044, + 67 modules, zero errors. +- `git diff --check` - PASS. + +### Self-review + +- Public dispatch valid remains independent of ready and stable until fire; + every allocator `in.fire` remains retained; paired stores remain one atomic + `StoreDispatchTxn`; exact caller/evidence checking remains enforced. +- The only new identity seam is a side-effect-free ROB-prepared publication + sidecar into the existing RENU owner. It adds no ROB, BROB, rename, commit, + recovery, or dispatch residency owner. +- No debug/test-only production IO or diagnostic print remains. The parent-owned + unstaged NDF plan was not edited or staged by this round. +- `skill-evolve: no-update` - the LinxCore skill already requires exact retained + identity, atomic terminal publication, target-only recovery, focused owner + gates, and wrapper-based verification; this fix adds no reusable workflow + rule beyond those contracts. + +## Fix Round 5 + +This round corrects only the Branch unrelated-peer U-tag evidence in the +four-STID public integration scenario. All Task 11 production behavior and the +existing peer residency completion/commit and MemoryOrder proofs are unchanged. + +### RED evidence + +- The old assertion compared `stid1PeerProbe.u` against `rows(1)(1).u`. + `stid1PeerProbe.u` is present because the probe shape allocates U, while + `rows(1)(1).u` is necessarily absent because that retained row's shape has + `u = false`; `Some != None` therefore passed independently of Branch recovery + correctness. +- Replacing that comparison with the missing baseline presence requirement and + running `bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec` + produced the expected RED result: 7 tests ran, 6 passed, and the four-STID + case failed at `OOOIntegrationSpec.scala:393` with `None was empty`. + +### Correction + +- The scenario now captures `rows(1).head.u` before recovery, explicitly + requires that pre-recovery peer U tag and the post-Branch peer probe U tag to + both be present, and compares their concrete tag values. +- A Branch recovery bug that rolls back unrelated STID1 U rename state can now + reallocate the captured tag to the probe and fail the assertion. No production + file, public IO, residency/commit sequence, or MemoryOrder peer proof changed. + +### Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec` - PASS, + 7 tests total across 2 suites: 4 canonical OOO integration tests and 3 + adjacent CTU integration tests. +- `git diff --check` - PASS. +- `skill-evolve: no-update` - this is a test-evidence correction already + covered by the LinxCore requirement for exact recovery and public integration + proof; it adds no reusable domain workflow rule. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-12-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-12-report.md new file mode 100644 index 00000000..dcf564d5 --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-12-report.md @@ -0,0 +1,474 @@ +# Task 12 Report: Private IEX Mechanism Preparation + +## Status + +COMPLETE — private IEX mechanisms are prepared and all Task 12 Step 4 gates +pass. The public-box cutover remains exclusively assigned to Task 13. + +## Baseline + +- LinxCore: `f89c38fb9c2eb299681c447b8e00cfe4db82824d` +- Superproject: `54635e8cb1119e5f199228cb7db330b168bf7dc0` +- LinxCoreModel: `31555f49dbb020c8eb9f26f7df98310a7415b69d` +- QEMU: `c9f9570aa70da7e193ff8857bd9bde2cf052e546` +- Scope source: `.superpowers/sdd/2026-07-31-core-mainline-restructure/task-12-brief.md` + +## RED Evidence + +1. Baseline selector: + `bash tools/chisel/run_chisel_tests.sh --only IEXProductionMechanismSpec` + failed with `No tests match the patterns: *IEXProductionMechanismSpec*`. +2. After introducing the first topology fixture, the suite failed to compile + because `OooIexProductionPhysicalProfile` did not exist. +3. After adding the value-only profile, real-child elaboration failed with + `execution cluster requires the formal Linx scalar/control profile`. + This exposed the real canonical/profile mismatch rather than a test-only + absence: `IEXParams` specifies 2 ALU, 1 BRU, 2 AGU, 2 STD, 1 shared + system/multicycle queue, and 1 CMD queue, while the private execution child + was fixed to 6 ALU, 2 BRU, 3 AGU, and 14 picker lanes. +4. The first canonical-topology check then failed because no ALU-class + residency owner exposed `MultiCycleAlu`. The opcode recipe table classifies + DIV/REM as ALU-class work requiring that capability. The final profile + therefore dedicates one ALU IQ bank to the system/multicycle owner while + retaining two simple-ALU execution pipes and disjoint full ALU coverage. + +The unchanged legacy/default structural baseline +`bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionPipeline` +passed 1/1 after the implementation in 2 minutes 25 seconds. + +## Owner and File Decisions + +- `OooIexIssue` remains the sole IQ/residency owner. No public `IEX` module was + created and no canonical payload adapter was added. +- `OooIexOperandFiles` remains the sole P/T/U data/readiness owner. +- `OooIexExecutionPipeline` and `OooIexTerminalFabric` remain the execution + and terminal owners; their private dimensions now derive from an + `OooIexPhysicalProfile` instead of scattered 6/2/3 constants. +- `OooIexProductionPhysicalProfile` is a value-only conversion from canonical + `linxcore.params.CoreParams`. It owns no hardware state. It preserves the + requested 2/1/2/2 topology for W2/W4/W6/W8, gives system/multicycle and CMD + distinct residency owners, and leaves the old formal profile as the default + until Task 13 performs the one-time public cutover. +- The load-allocation and load-terminal helpers now accept any positive AGU + count covered by canonical LSU return-pipe identities. This removes the + private three-AGU constant without changing load lifecycle ownership. +- Terminal lanes may have no source from one execution family (for example, + one BRU across two terminal lanes). Such absent family/lane projections are + explicitly tied off; existing sources retain stable modulo ownership. +- The manifest adds the new aggregate L3 fixture to the three IEX mechanism + rows while retaining `public_box_status=pending`, `cutover_task=13`, and + `mechanism-verified-cutover-pending`. + +## GREEN Evidence + +- `IEXProductionMechanismSpec`: 6/6 passed. It proves W2/W4/W6/W8 profile + construction, W4 real-child 2 ALU/1 BRU/2 AGU elaboration, per-class + residency, same-STID age, cross-STID fairness, scoped recovery, complete + P/T/U read admission, exact retry, and atomic terminal retention. +- Existing-profile regressions recorded so far: + - `OooIexPhysicalProfileSpec`: 3/3 passed. + - `OooIexTerminalFabricSpec`: 3/3 passed. + - `OooIexExecutionClusterSpec`: 4/4 passed. + - `OooIexLoadLiqAllocAdapterSpec`: 5/5 passed. + - `OooIexLoadTerminalMetadataSpec`: 3/3 passed. + - `OooIexCanonicalLoadOwnershipSpec`: 7/7 passed. +- `OooOpcodeRecipeTableSpec`: 4/4 passed, including generated classification + and hardware decode agreement for the ALU/multicycle recipe surface. +- Required Step 4 gates: + - `bash tools/chisel/run_chisel_tests.sh --only IEXProductionMechanismSpec`: + 6/6 passed. + - `bash tools/chisel/run_chisel_tests.sh --only OooIexPhysicalProfileSpec`: + 3/3 passed. + - `bash tools/chisel/build_chisel.sh`: passed. + - `bash tools/chisel/run_chisel_verilator_lint.sh`: passed with Verilator + 5.044 over 67 generated modules. + - `python3 tools/chisel/check_production_owner_manifest.py`: passed with + 23 closed owners, 40 classified emitters, 10 declared adapters, and all + NDF L1/L2/L3 roles mapped. + - `git diff --check`: passed. + +## Self-review + +- No public `IEX` owner or emitter exists in this change. +- No `Reduced*` source is deleted or rewired; that remains Task 13. +- No parent plan is modified. +- The new expected topology is derived from canonical parameter literals, not + from the legacy profile under test. +- Existing formal/default profile behavior remains under its original focused + suites, preventing Task 12 from silently changing the live boundary. + +## Untested Risks + +- Task 12 does not prove OOO public `DispatchTxn` traffic through a public IEX + box; Task 13 owns that atomic boundary cutover and its adapter deletion. +- This task does not provide workload, timing, physical-memory, or synthesis + evidence. Those are later integration/promotion gates. +- The real W4 child topology is elaborated at canonical capacity for the + execution cluster. Whole-pipeline composition is checked with the same + topology and compact storage capacities because a full-capacity monolithic + CHIRRTL attempt exhausted the local approximately 4 GiB JVM heap. This is + not claimed as full-capacity whole-core elaboration evidence. +- The value-only profile currently rejects pipe-count combinations other than + the approved 2/1/2/2/1/1 mechanism topology; W2/W4/W6/W8 refer to width, not + to independently variable physical pipe counts. + +## Skill Evolution + +`skill-evolve: no-update` — the installed `linx-core` skill already requires +explicit physical topology, sole state ownership, generation-qualified load +identity, retained backpressure, common recovery, and honest separation of +standalone mechanism evidence from public-box promotion. + +## Fix Round 1/5 + +### Status + +COMPLETE — all four independent-review findings are addressed without a +public `IEX` owner, public-boundary cutover, `Reduced*` deletion, parent-plan +edit, or push. + +### Finding 1 — canonical IEX conversion + +RED: + +- Literal W2/W4/W6/W8 assertions observed the inherited legacy geometry + `iqBankCount=8` instead of canonical `scalarIssueBanks=2`; the aggregate + suite failed 5/6 at the exact bank-count assertion. +- Restoring multicycle ALU coverage after the 2-bank mapping initially failed + profile construction because the old validator rejected even + capability-disjoint logical owner projections on the same class/bank. + +GREEN: + +- `canonicalIexParams` is the dedicated value-only canonical IEX projection. + `issueWidth` must equal `WidthParams.issueWidth`, `WidthParams.dispatchWidth`, + and `OOOParams.dispatchWidth`; it defines S1/dispatch admission rather than + physical picker count. +- `scalarIssueEntries` is total capacity, must divide evenly by + `scalarIssueBanks`, and maps to + `iqBankCount=scalarIssueBanks` plus + `iqEntriesPerBank=scalarIssueEntries/scalarIssueBanks`. +- `integerReadPorts` and `integerWritePorts` map exactly to `iexPReadPorts` + and `iexPWritePorts`. +- Every remaining `IEXParams` field is explicit: 2 ALU, 1 BRU, 2 AGU, 2 STD, + 1 system/multicycle, and 1 CMD are required and used to construct distinct + owners/pickers. No canonical IEX field is silently ignored. +- With only two physical IQ banks, simple-ALU and multicycle owners may project + the same class/bank only when their capability masks are disjoint. The + profile still rejects every class/bank/capability overlap. This preserves + ALU-class DIV/REM routing while keeping system/multicycle ownership separate. +- W2/W4/W6/W8 assert exact `2 x 32 = 64` IQ geometry, 6 P-read ports, 5 + P-write ports, 10 picker domains, and 2/1/2/2/1/1 topology. + +### Finding 2 — real owner behavior and honest L3 evidence + +RED: + +- The original aggregate suite instantiated `OooIexOldestReadyPicker`, not + the real `OooIexIssue`; it also contained no two-AGU canonical load-owner + lifecycle. +- A full 10-domain `OooIexIssue` behavioral model remained in Verilator + generation for more than 15 minutes at about 3.5 GiB RSS. A 5-domain retry + still took 15m35s and exposed a test bug: AGU required-capability bit 0 was + `SimpleAlu`, so the real LDA picker correctly remained invalid. +- The first two-AGU test assumed lane 0 won reset arbitration; `RRArbiter` + correctly selected lane 1 first. A later return was also rejected because + the fixture reused lane-2 destination tags for lane 1. + +GREEN: + +- Evidence is deliberately split. Exact 10-domain structural assertions prove + the canonical LDA/STA/STD/system/CMD owner and capability projections. + A sustainable real `OooIexIssue` fixture uses their exact capability union + and proves AGU load/store-address rows, STD, system, and CMD allocate into + disjoint real rows, retain under backpressure, claim atomically, and accept + one exact retry. It does not claim cross-domain arbitration. +- `OooIexCanonicalLoadOwnership(..., laneCount=2)` now receives both AGUs + simultaneously, accepts the real RR order, and proves return-pipe 1/0 + separation, full LSID, PE/STID, native BID, BROB generation, RID slot and + generation, member index, resident generation, and attempt generation. + Rebind backpressure holds both leases, stale completion is rejected, the + peer lane returns without identity confusion, and scoped recovery removes + only the remaining lease. +- The manifest retains aggregate L3 only for real issue behavior. The previous + aggregate claims for operand-file and execution ownership were removed; + execution L3 now cites the real terminal and canonical load-owner fixtures. + +### Finding 3 — multi-cycle terminal retention + +RED: + +- The original aggregate test drove `OooIexTerminalPublish` combinationally + and released backpressure in the same cycle; it did not cross + `OooIexTerminalFabric` or retain a W-stage owner for multiple clocks. + +GREEN: + +- `OooIexTerminalFabricSpec` drives a real ALU W-stage transaction through the + fabric for three backpressured cycles. Every cycle preserves full PE/STID, + RID slot/generation, BID/BROB generation, member/resident generation and + destination identity; terminal fire is zero and no P-write, trace, or BCTRL + endpoint partially publishes. +- Releasing completion backpressure produces exactly one atomic terminal fire, + P-write, wake/trace/completion publication; removing producer valid yields + no duplicate fire over the following cycles. + +### Finding 4 — width warnings + +RED: + +- The initial aggregate elaboration reported 100 W002/W004 warnings from + singleton `stidCount=1` and `iqEntriesPerBank=1` fixture geometry. + +GREEN: + +- The aggregate fixture now uses `stidCount=2`, `iqBankCount=2`, and + `iqEntriesPerBank=4`. Final aggregate and focused-owner runs report zero + W002/W004 hardware warnings. The only remaining warning is sbt's existing + `multiple main classes detected` message. + +### Verification + +- `IEXProductionMechanismSpec`: 7/7 passed in 4m36s after the final + class/bank/capability fix. +- `OooIexCanonicalLoadOwnershipSpec`: 8/8 passed. +- `OooIexTerminalFabricSpec`: 4/4 passed. +- `OooIexPhysicalProfileSpec`: 4/4 passed. +- `OooIexExecutionClusterSpec`: 4/4 passed. +- `OooIexLoadLiqAllocAdapterSpec`: 5/5 passed. +- `OooIexLoadTerminalMetadataSpec`: 3/3 passed. +- `OooOpcodeRecipeTableSpec`: 4/4 passed after the final profile fix. +- `bash tools/chisel/build_chisel.sh`: passed. +- `bash tools/chisel/run_chisel_verilator_lint.sh`: passed with Verilator + 5.044 over 67 generated modules. +- `python3 tools/chisel/check_production_owner_manifest.py`: passed with 23 + closed owners, 40 classified emitters, 10 declared adapters, and all NDF + L1/L2/L3 roles mapped. +- `git diff --check` and `git diff --cached --check`: passed. + +### Self-review + +- The canonical profile no longer self-proves against legacy IQ defaults. +- Logical owner overlap is permitted only when capability-disjoint; hardware + residency remains solely in `OooIexIssue`. +- Test expected identities are lane-specific literals, not values derived by + the implementation under test. +- No public `IEX`, public emitter, live-boundary rewiring, `Reduced*` deletion, + parent-plan edit, or push is present. + +### Skill Evolution + +`skill-evolve: no-update` — the existing `linx-core` workflow already requires +explicit parameter domains, sole state ownership, full generation-qualified +identity, honest evidence levels, retained backpressure, and common recovery. + +## Fix Round 2/5 + +### Status + +COMPLETE — the three rereview findings are closed with test-only evidence. +No production RTL, manifest path, parent plan, public boundary, or live owner +was changed. + +### Finding 1 — complete canonical capability behavior + +RED: + +- The real one-domain `OooIexIssue` fixture advertised only load address, + store address, store data, system, and engine-command capabilities. It did + not behaviorally exercise simple ALU, multicycle ALU, pointer-auth, branch, + or floating/vector residency. +- The first expanded fixture still claimed and retried only the first selected + row. Final diff review rejected that partial proof before commit. + +GREEN: + +- The sustainable one-domain fixture derives its capability mask from the OR + of every canonical picker and independently checks it against the OR of + every canonical residency owner and the full ten-bit valid mask. +- Literal representative rows cover simple ALU, multicycle ALU, BRU, AGU LDA, + AGU STA, STD, FSU, system, pointer-auth, and CMD. Each row independently + allocates into real `OooIexIssue` state, remains stable for three blocked + cycles, claims atomically, accepts an exact retry, reclaims, and releases by + exact identity. The separate ten-domain structural proof remains unchanged. + +### Finding 2 — literal two-AGU identity proof + +RED: + +- The prior two-AGU fixture checked only selected RID/LSID fields and derived + attempt generations by peeking the DUT. It therefore could not prove full + identity stability during rebind or retained return. +- Literal-first assertions exposed the actual global attempt-generation order: + lane 1 allocates generation 1, lane 0 allocates generation 2, and lane 0 + rebinds to generation 3. + +GREEN: + +- A hand-authored expected-lease helper checks PE/STID, native BID validity and + value, BROB generation, RID slot and generation, member index, resident + generation, full LSID, load/attempt generation, return pipe, and destination + tags without constructing expected values from DUT outputs. +- Both rebind-stall cycles verify current and next canonical identities. The + accepted cancel, stale-return rejection, and every peer-return backpressure + cycle preserve the corresponding full literal identity. + +### Finding 3 — real ALU pipeline to terminal retention + +RED: + +- The prior terminal testbench held `OooIexTerminalFabric.alu` directly. It did + not prove that a real `OooIexAluPipeline` W1/W2 owner retained the row. +- The first real-pipeline run rejected the old direct-fixture data constant + `0x103`; the real `ADDI 41, 1` transaction correctly produced `42`. + +GREEN: + +- A test-only harness connects real `OooIexAluPipeline.w2` directly to + `OooIexTerminalFabric.alu(0)` and ties off the unused BRU/load families. +- Completion backpressure is held for three cycles. Every cycle checks the + full ROB-member identity, retained destination atag/PTAG/generation/local + identity, writeback data, W2 ownership, zero terminal fire, and zero partial + P/T/U write, wakeup, trace, or BCTRL publication. +- Releasing completion produces exactly one atomic fire. W2 then withdraws, + and later cycles show no duplicate completion or writeback. + +### Verification + +- `IEXProductionMechanismSpec`: 7/7 passed in 4m47s after the final per-row + claim/retry/release tightening. +- `OooIexCanonicalLoadOwnershipSpec`: 8/8 passed in 44.1s. +- `OooIexTerminalFabricSpec`: 4/4 passed in 32.1s. +- `OooIexPhysicalProfileSpec`: 4/4 passed. +- `python3 tools/chisel/check_production_owner_manifest.py`: passed with 23 + closed owners, 40 classified emitters, 10 declared adapters, and all NDF + L1/L2/L3 roles mapped. +- `bash tools/chisel/build_chisel.sh`: passed. +- `bash tools/chisel/run_chisel_verilator_lint.sh`: passed with Verilator + 5.044 over 67 generated modules. +- `git diff --check` and `git diff --cached --check`: passed. + +### Warnings and self-review + +- The only tool warning is sbt's existing `multiple main classes detected`. +- No production source, manifest, parent plan, public `IEX`, live boundary, + `Reduced*` source, or generated artifact is modified. +- All three expected-value surfaces are literal or independently derived from + canonical topology; none reconstructs expected identity from DUT output. + +### Skill Evolution + +`skill-evolve: no-update` — this round strengthens local tests but introduces +no new reusable LinxCore ownership, identity, recovery, or gate invariant. + +## Fix Round 3/5 + +### Status + +COMPLETE — the remaining terminal-retention evidence gap is closed in the +test-only harness. No production RTL, manifest, parent plan, or public boundary +is changed. + +### RED + +- Round 2 checked the completion member directly but did not independently + inspect the retained W2 member on every blocked cycle. +- Completion omitted explicit `group.valid` and `bid.valid` checks. The fire + cycle and two post-fire cycles did not enumerate every applicable endpoint, + leaving room for a partial or duplicate publication to escape the fixture. + +### GREEN + +- Each of three blocked cycles now checks the complete retained W2 and + completion identity: group validity, PE/STID, RID slot/generation, BID + validity/value, BROB generation, member index, and resident generation. +- The retained W2 writeback checks destination valid/kind, atag, PTAG, + PTAG generation, local tag, local-sequence valid/index/generation, and data + `42` every blocked cycle. +- Blocked cycles require zero terminal fire and zero P/T/U write, wakeup, + trace, or BCTRL publication on every exposed port. Only the blocked + completion advertises valid, with ready low; peer completion lanes are + invalid. +- The release cycle explicitly proves completion, P-write, wakeup, and trace + valid together with the full completion identity, retained W2 identity, + destination, and data. All peer P-write/wakeup/trace lanes and every T/U and + BCTRL endpoint remain invalid. +- Both following cycles require W2 empty, retained W2 invalid, terminal fire + zero, and every completion/write/wakeup/trace/BCTRL endpoint invalid. This + is the direct exactly-once/no-duplicate proof. + +### Verification + +- `OooIexTerminalFabricSpec`: 4/4 passed in 29.96s. +- `bash tools/chisel/build_chisel.sh`: passed. +- `bash tools/chisel/run_chisel_verilator_lint.sh`: passed with Verilator + 5.044 over 67 generated modules. +- `python3 tools/chisel/check_production_owner_manifest.py`: passed with 23 + closed owners, 40 classified emitters, 10 declared adapters, and all NDF + L1/L2/L3 roles mapped. +- `git diff --check` and `git diff --cached --check`: passed. + +### Warnings and self-review + +- The only tool warning is sbt's existing `multiple main classes detected`. +- The diff is limited to `OooIexTerminalFabricSpec.scala` and this report. +- No expected identity or data field is read back from the DUT to construct an + expected value. + +### Skill Evolution + +`skill-evolve: no-update` — this is a local evidence-completeness correction; +the existing LinxCore retained-owner and atomic-publication invariants already +cover the reusable rule. + +## Fix Round 4/5 + +### Status + +COMPLETE — the terminal fire cycle now has full literal payload evidence. +The change remains test-only and does not modify production RTL, the manifest, +the parent plan, or a public boundary. + +### RED + +- Round 3 proved atomic endpoint validity and retained ownership but checked + only a subset of each fire-cycle payload. A wrong commit bit, scope, wakeup + class, empty load token, trace opcode, trace writeback, or trap payload could + still pass. + +### GREEN + +- Completion checks valid, the complete member key, `faultValid=false`, and + `faultCause=0`. +- P-write checks valid, literal `commit=true` as assigned by the terminal + publisher, STID 1, epoch 9, PTAG 37, generation 3, and data 42. +- Wakeup checks `Committed`, STID 1, epoch 9, operand class P, PTAG 37, + generation 3, zero local tag/sequence, and a fully empty load identity. +- Trace checks source ALU, the complete member, primary-parent valid/PE/STID/ + instruction ID/epoch, uop ordinal/count, literal opcode 62, the complete + first destination and data 42, every remaining writeback invalid, an empty + load identity, and disabled zero trap state. +- Round 3 blocked-cycle and two-cycle no-duplicate assertions remain intact. + Every expected value is a handwritten literal; no DUT output constructs an + expectation. + +### Verification + +- `OooIexTerminalFabricSpec`: 4/4 passed in 31.21s. +- `bash tools/chisel/build_chisel.sh`: passed. +- `bash tools/chisel/run_chisel_verilator_lint.sh`: passed with Verilator + 5.044 over 67 generated modules. +- `python3 tools/chisel/check_production_owner_manifest.py`: passed with 23 + closed owners, 40 classified emitters, 10 declared adapters, and all NDF + L1/L2/L3 roles mapped. +- `git diff --check` and `git diff --cached --check`: passed. + +### Warnings and self-review + +- The only tool warning is sbt's existing `multiple main classes detected`. +- The diff is limited to `OooIexTerminalFabricSpec.scala` and this report. + +### Skill Evolution + +`skill-evolve: no-update` — this is a local test-evidence refinement; no new +cross-module LinxCore invariant or verification gate was discovered. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-report.md new file mode 100644 index 00000000..e84757a3 --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-report.md @@ -0,0 +1,110 @@ +# Task 17 report: distributed control and DTU observation + +## Outcome + +Task 17 adds one typed DTU observation boundary without moving commit, +trap, interrupt, debug-boundary, or recovery decisions out of OOO. DTU now +transports external halt/resume requests to the OOO owner, exports a +loss-tolerant trace stream, and publishes monotonic observation counters. + +OOO retains halt requests until the requested STID reaches a precise commit +boundary. Synchronous faults take priority over debug and interrupts, and +interrupt selection excludes requests for another STID. Recovery continues to +use one common Prepare/Prepared/Apply barrier, while CTU fences only the target +STID so unrelated work can progress. + +No displaced stateful debug, trace, or system-control wrapper was named by the +closed-owner inventory. `CommitTraceMonitor` remains a stateless checker used +by legacy ROB fixtures and is not a competing DTU or commit owner, so this task +deleted no wrapper. + +## Implementation + +- Added `DTU`, `DebugControl`, `TraceExport`, and `PerformanceCounters`. + `DebugControl` is a one-entry typed transport queue; it does not interpret a + command or select a boundary. `TraceExport` always accepts observations and + retains at most one externally visible packet. Counters never qualify a + control ready/valid path. +- Extended `DTUIO` with the owner-facing debug channel, trace export, and + counter vector. Extended `OOOIO` and the D3/S1 graph with the matching typed + debug channel. +- Added OOO-owned halt state and debug response generation to + `CommitControl`. A pending halt survives a higher-priority synchronous fault + and is applied at the next matching precise boundary. Resume clears the + halted state. +- Qualified both commit and recovery interrupt arbitration by the boundary + STID before priority reduction. +- Made CTU recovery admission, buffered output, and trace fences local to the + plan target STID. +- Instantiated DTU in the canonical OOO/IEX/LSU activation graph and connected + commit, trace, and debug control paths without adding an adapter owner. +- Updated the interface manifest, closed-owner manifest, checker tests, and + L1/L2/L3 behavior contracts. + +## TDD evidence + +The initial `DTUSpec` and `RecoveryIntegrationSpec` failed to compile because +`linxcore.dtu.DTU` and its mechanisms did not exist. The first behavior run +then exposed two distributed-control failures: interrupt reduction selected a +higher-priority request for the wrong STID, and CTU recovery fencing blocked +unrelated-STID admission. A separate debug-boundary RED proved that +`CommitControl` had no typed halt/resume input or OOO-owned halted state. + +The focused fixes closed those failures without changing public identity +widths or the memory attempt-ownership contract. + +## Verification + +- `DTUSpec` — PASS, 4/4. Artifact size 167,214,581 bytes under a + 300,000,000-byte cap. +- `RecoveryIntegrationSpec` — PASS, 5/5. Artifact size 382,485,994 bytes under + the task's 900,000,000-byte cap. +- `CommitControlDebugSpec` — PASS, 1/1. One simulation covers normal commit, + precise same-STID interrupt selection, synchronous-fault priority over a + pending halt and interrupt, debug halt, and resume. Artifact size 87,755,548 + bytes under a 300,000,000-byte cap. +- `RecoveryControlBarrierSpec` — PASS, 1/1. One simulation covers single + prepare fanout, missing-acknowledgement stall, and common apply. Artifact + size 60,756,922 bytes under a 300,000,000-byte cap. +- `CTUSpec` — PASS, 11/11. +- `OOOCommitApplyPolicySpec` — PASS, 1/1. +- `bash tests/test_trace_schema_and_mem.sh` — PASS. Its negative-path fixture + intentionally prints `error: missing trace output`. +- `python3 tools/chisel/trace_schema_adapter.py --self-test` — PASS. +- `python3 tools/chisel/render_top_interface_manifest.py --check` — PASS; the + checked-in manifest is current. +- `python3 tools/chisel/check_production_owner_manifest.py` — PASS: 27 closed + owners, 24 classified emitters, 6 declared adapters, and L1/L2/L3 roles + mapped. +- `python3 -m unittest tests.test_production_owner_manifest -v` — PASS, 46/46. +- `git diff --check` — PASS. + +`OOORobCommitSpec` was stopped as a resource failure rather than classified as +a test failure: status 130, child status -9, 1,832,601,201 artifact bytes, and +3,490,054,144 peak process-tree RSS. It was not rerun. Inspection found that +`chisel_test_supervisor.py` checks the artifact budget only after a successful +child exit, so the configured cap reports an excess but does not enforce it +during elaboration. The supervisor was not changed because no independent RED +for that tool is part of Task 17. + +The NDF local-reference checker still reports the pre-existing unrelated gap +`docs/spec/40-constraints/parameters.md:72: missing verifies edge for L1 MUST +PRM-LSU-SIZING-001`. Task 17 did not modify that parameter contract. + +## Source identities + +- LinxCore baseline: `ff02aefaba8822b53f6fecf40e941017973ab961` +- LinxISA superproject: `54635e8cb111` +- LinxCoreModel reference: `3ca25e05d2a2` +- QEMU reference: `c9f9570aa70d` + +## Assumptions and limits + +- Trace export is deliberately loss-tolerant. A retained packet remains stable + while stalled; a newer observation may be counted and dropped. +- The existing OOO/IEX/LSU activation graph is the smallest live caller before + Task 18 assembles TOP. DTU ownership and wiring therefore remain explicit + without prematurely creating the final top-level composition. +- Six pre-existing x86 firtool processes remain in kernel-uninterruptible + state. They are unrelated to Task 17; reproducible Task 17 build artifacts + are removed before handoff. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-1-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-1-report.md new file mode 100644 index 00000000..414cf081 --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-1-report.md @@ -0,0 +1,77 @@ +# Task 17 review fixes — round 1 + +## Finding addressed + +The activation caller previously connected DTU to the permanently invalid OOO +trace output while the live IEX trace bypassed DTU and inherited external +backpressure. `IEX` also generated its public terminal PWrite observation from +the trace arbiter output fire, so that observation disappeared when the trace +consumer stalled. + +## RED evidence + +`DTUActivationTraceSpec` initially stalled the activation probe's external IEX +trace consumer and issued terminal operations. The test failed with +`rfWriteCount=0` where two terminal PWrite observations were required. + +The first elaboration attempt also exposed stale activation-harness tie-offs +for the existing LSU maintenance and memory-fault ports. Those ports were tied +to inert values before recapturing the behavioral RED. They are unrelated to +the trace ownership change. + +The precise behavioral RED used 595,635,289 artifact bytes and failed only on +the expected terminal PWrite suppression. + +## Ownership correction + +- The only live trace producer in the OOO/IEX/LSU activation graph is IEX; + current OOO and LSU trace outputs are explicitly invalid. The caller now + connects `iex.io.trace` directly to DTU's always-accepting trace ingress. +- The former `iexTraceReady` activation input now controls DTU's external trace + export only. Stalling it can retain or drop observations but cannot + backpressure IEX. +- DTU remains the sole loss-tolerant export owner. No trace adapter or second + trace state owner was added. +- `IEX` records a typed terminal PWrite observation when the corresponding + terminal source actually fires. Per-source pending observations are selected + independently of trace-arbiter fire and trace output readiness. This retains + the exact ROB, tag, generation, and value without deriving architectural + progress from an observational handshake. + +## Behavioral proof + +The compact W4 activation test uses four ROB groups and four BROB entries while +preserving all public identity widths. It issues one valid closed block: + +`BSTART_FALL -> ADDI -> ADDI -> BSTOP` + +The external DTU trace export remains stalled throughout. The first packet is +retained and checked stable for three cycles. The second packet overflows the +one-slot exporter and is counted as dropped while both terminal writes, +completion publication, and commit continue. + +Final exact counters: + +- terminal PWrite observations: 2 +- resolve completions: 2 +- commit transactions: 1 +- DTU accepted trace observations: 2 +- DTU dropped trace observations: 1 + +## Verification + +- `DTUActivationTraceSpec` — PASS, 1/1; 586,754,201 artifact bytes, 564 + files, 145.464 seconds, peak process-tree RSS 7,593,181,184 bytes. +- `DTUSpec` — PASS, 4/4; 167,214,581 artifact bytes under a + 300,000,000-byte cap. +- New IEX elaboration warnings — none. The final selector emitted only the + repository's generic multiple-main-class warnings. +- `python3 tools/chisel/check_production_owner_manifest.py` — PASS: 27 closed + owners, 24 classified emitters, 6 declared adapters, and L1/L2/L3 roles + mapped. +- `python3 -m unittest tests.test_production_owner_manifest -v` — PASS, 46/46. +- `git diff --check` — PASS. + +The owner manifest was updated only after the activation behavior passed. It +now names `DTUActivationTraceSpec` as activation-level evidence for the live +DTU caller. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-2-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-2-report.md new file mode 100644 index 00000000..5034fb44 --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-17-review-fixes-round-2-report.md @@ -0,0 +1,79 @@ +# Task 17 review fixes — round 2 + +## Findings addressed + +`OooIexTerminalPublish` previously included trace readiness in the atomic +terminal rendezvous. The IEX boundary also derived its public terminal PWrite +observation from trace-source fire and fed observation capacity backward into +that source's ready signal. A stalled or full observation path could therefore +delay architectural completion. + +## RED evidence + +The focused `IEXTerminalTraceIndependenceSpec` held `trace.ready` low while +every required architectural sink was ready. Against the round-1 base it +failed at the first architectural check: `alu.ready` was zero instead of one. +The focused behavioral RED used 113,563,306 artifact bytes across 110 files, +below its 200,000,000-byte cap. + +After the first independence repair, the exact activation assertions exposed +a second behavioral RED: `rf=1 resolve=2 commit=1 accepted=2 dropped=1`. Two +architectural terminal lanes completed together, but a combinational +single-output observation selector retained only one PWrite observation. + +An earlier attempt to use the full legacy terminal suite was stopped after its +one-simulator-per-case shape exceeded the compact resource target. A separate +setup attempt passed an executable instead of the firtool directory to +`CHISEL_FIRTOOL_PATH`. Neither attempt is classified as behavioral evidence. + +## Architectural acceptance + +- `OooIexTerminalPublish` now defines `architecturalReady` solely from the + required ROB resolve, physical-file write, wakeup, recovery-event, and BCTRL + endpoints. Trace ready, trace queue state, DTU state, and export state do not + participate. +- One `architecturalFire` releases the selected terminal owner and atomically + drives required architectural completion, PWrite, wakeup, recovery, and + BCTRL outputs. The terminal trace valid pulse is generated from that event + as a best-effort observation; trace acceptance is not asserted as part of + architectural fire. +- A private typed `architecturalAccepted` observation carries the exact + accepted request through TerminalFabric, ExecutionCluster, and + ExecutionPipeline. IEX no longer reconstructs terminal PWrite observation + from trace fire. +- Trace-source ready is hard true at the IEX observation boundary. Local trace + queues may miss a pulse when full, but cannot stall architectural acceptance; + DTU remains the sole external loss/accounting owner. + +`IEXIO.terminalPWrite` is explicitly a `Valid[IEXTerminalPWriteObservation]`, +not an RF mutation port or state owner. The real architectural PWrite ports +remain the Decoupled outputs of `OooIexTerminalPublish` connected to the +operand files. Per-lane retained observations serialize simultaneous terminal +events without feeding capacity into architectural readiness. Consume and +same-lane replacement are atomic, and an assertion forbids silent observation +overflow. + +## GREEN evidence + +- `IEXTerminalTraceIndependenceSpec` — PASS, 1/1. With trace ready low, one ALU + owner acceptance, exact PWrite data, wakeup, ROB resolve, and terminal fire + occur once; the following three cycles contain no duplicate. Final artifact + size was 115,360,634 bytes across 110 files under the 200,000,000-byte cap; + elapsed time was 13.180 seconds and peak process-tree RSS was 2,736,242,688 + bytes. +- `DTUActivationTraceSpec` — PASS, 1/1. With the external DTU export stalled, + the retained packet remains stable and final counters are exact: + `rf=2 resolve=2 commit=1 accepted=2 dropped=1`. Final artifact size was + 586,772,137 bytes across 564 files under the 900,000,000-byte cap; elapsed + time was 147.043 seconds and peak process-tree RSS was 7,541,555,200 bytes. +- `DTUSpec` — PASS, 4/4. Artifact size was 167,214,581 bytes across 198 + files under the 300,000,000-byte cap; elapsed time was 14.575 seconds and + peak process-tree RSS was 1,667,006,464 bytes. +- The closed-owner manifest checker passed with 27 closed owners, 24 + classified emitters, 6 declared adapters, and all L1/L2/L3 roles mapped. + Its 46-case unit suite, the top-interface manifest check, and + `git diff --check` also passed. + +Both final suites used the repository wrapper, one job, a clean build +directory, and the native arm64 firtool override. `OOORobCommitSpec` was not +run. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-18-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-18-report.md new file mode 100644 index 00000000..c3278bf6 --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-18-report.md @@ -0,0 +1,683 @@ +# Task 18 implementation report + +## Baseline and audit + +- Task baseline: `e0c90c2c75942b01b3a175fbdc916a04cc83b0c2`. + Fix-round baseline: `8697fa1a`. +- Callable legacy tops: `LinxCoreFrontendTraceTop`, + `LinxCoreFrontendFetchTraceTop`, and the older `LinxCoreComposition` graph. +- Current emitted build/lint top: `OOOIEXLSUActivationProbe` through + `tools/chisel/emit_verilog.sh` and `run_chisel_verilator_lint.sh`. +- Reusable wiring source: `EmitOOOIEXLSUActivationProbe.scala` already connects + OOO, IEX, LSU, recovery, bootstrap, DTU observation, and CMD backpressure. +- Existing natural runner: `run_chisel_benchmark_autonomous_top_natural.sh` + with `benchmark_autonomous_top_natural_tb.cpp`; it is not the Task-18 TOP + harness. +- `TOPIO` initially had one data-memory lane despite LSU exposing independent + load/store lanes, no boot/configuration projection, and no projections for + remaining LSU/system leaves. +- `MemoryRequestTxn.sizeBytes` was a four-bit literal. LSU assigned the + 64-byte line size to it, which truncates to zero. The external contract needs + a typed size encoding and the NDF verification graph needs an explicit edge + back to `PRM-LSU-SIZING-001`. + +## Wished-for RED tests + +- `TOPSpec`: exactly one IFU/CTU/OOO/IEX/LSU/DTU, no TOP-owned Reg/Queue/Mem, + no IEX-to-IFU control path, real CMD backpressure, loss-tolerant trace intake. +- `TOPWidthProfilesSpec`: independent W2/W4/W6/W8 elaboration. +- `TopInterfaceSpec`: typed external memory size including 64 bytes, independent + data-memory lanes, one typed clock/reset boundary, and no raw reset leaf. +- `InterfaceManifestSpec`: `TOPIO` endpoint plus every external leaf mapped to + an `IFC-TOP-EXT-*` clause without payload duplication. +- `tests.test_top_natural`: executable self-test manifest, exact harness owner + list, typed size mapping, and absence of instruction/commit replay inputs. + +## RED evidence + +- `TOPSpec` initially did not compile because `TOP`, `TOPIO` leaves, and + `MemorySize` did not exist. After the first direct OOO/IEX connection, + FIRRTL rejected a combinational cycle through OOO dispatch admission and + IEX ready. The final repair removes the generic boundary queues: presented + dispatch valid/payload is structural, every visible group uses one common + ready, and typed retained owners remain at the semantic producer. +- `TOPWidthProfilesSpec` initially rejected W2 because its two-entry directed + fetch buffer could not accept the fixed four-instruction I-side ingress. + The directed profile now keeps a four-entry minimum without changing any + public width. +- `InterfaceManifestSpec` initially rejected the checked-in JSON/Markdown + because they lacked `top_io` and the typed memory-size leaves. +- `tests.test_top_natural` initially failed because the Task-18 runner and C++ + harness did not exist. +- Fix-round combinational-cycle audit found two exact ready-to-valid edges. + `OooDispatch.prefixComplete(offset)` consumed the prior lane's IEX `ready` + and drove the next lane's `valid`, while `OooIexIssue.admissionReady` consumed + that lane's classification payload to drive `ready`. Separately, + `OOOD3S1Graph.fastWriteback.valid` consumed `fastWakeup.ready` and + `fastCompletion.ready`, while `fastWakeup.valid` consumed + `fastWriteback.ready`. The repair makes dispatch `valid/bits` depend only on + the retained D3 group plus static port geometry, gives every presented IEX + admission one common ready, and replaces the split public fast-result fork + with one typed `FastResultTxn`; the retained `OooD3FastResultQueue` remains + the only fast-result owner and ROB completion shares the same fire. +- Fix-round simulation-profile RED was 7/9: W2/W4/W6/W8 inherited the semantic + template graph but overwrote `maxTemplateUops` with two, below + `TemplateD3Constants.MaxRows` (28). The profile now inherits main semantic + capability and only bounds physical capacities; the selector is 9/9 green. + +## Changes + +- Added the state-free `TOP` and its sole `EmitTOP` entry point. It instantiates + one IFU, CTU, OOO, IEX, LSU, and DTU and routes typed recovery, memory, + bootstrap, debug, system/CMD, LSU control, commit/trap, and observation + channels. +- TOP itself contains no `Reg`, `Mem`, or `Queue`. The fix round removes the + generic OOO/IEX cycle-cut queues. `OooFastResultAtomicPublish` performs one + stateless common-fire fork from the existing retained fast-result owner to + IEX writeback/wakeup and ROB completion. +- Replaced external `sizeBytes: UInt(4.W)` with typed log2-byte `MemorySize`; + `Bytes64` is exactly value six. Updated IFU/LSU producers, tests, manifests, + parameter verification, and external-interface documentation. +- Expanded `TOPIO` to one data-memory channel per LSU lane and the remaining + typed platform endpoints. Trace inputs are always accepted; CMD remains a + real backpressured ready/valid output. +- Added a no-oracle natural runner, four-lane sparse-memory responder, + UART/finisher handling, boot map initialization, activation accounting, run + manifest, dual benchmark wrapper, and VPI port-validation mode. The natural + loop has configurable heartbeat and architectural-progress deadlock windows; + zero disables either watchdog, while the port-validation fast path remains + outside the natural loop and writes a `port_validation_pass` manifest after + bootstrap validation succeeds. +- Removed the callable `LinxCore*Top` sources/emitters, their top-only specs, + old trace and autonomous harness entry points, and stale benchmark callers. + The old activation graph is test-scope only and no longer has an emitter. +- Cut the emitter, lint, owner-manifest, and cross-check dependency gates to + `EmitTOP`/`TOP`. +- Simulation W2/W4/W6/W8 profiles retain the main CTU template capability, + all public identity/tag/LSID widths, and the 2/1/2/2 IEX plus 2-load/2-store + topology. Only physical ROB/IQ/cache/queue capacity is reduced. The + centralized `OOOParams.storeCommitBufferEntries` is the minimum power of two + covering `retireWidth * maxMemoryRequestsPerInstruction` in each simulation + profile; main profiles retain their default capacity. +- IEX remains the sole Option-A author of each initial memory transaction and + attempt. Full transaction value+generation crosses `StoreReservationTxn` and + exact `StoreTransactionBindingTxn`; LSU owns only replay/rebind. ROB binding + is fail-closed on the complete resident identity and memory-order metadata. +- W4 accepts both store dispatch/reservation lanes as one continuous prefix. + IEX atomically forks each lane to LSU reservation and ROB binding. ROB accepts + both distinct exact bindings in one cycle; the canonical STQ owner compacts + both lanes into one atomic multi-beat reservation batch under its existing + Prepare/Apply/Abort recovery fencing. No speculative ingress queue exists. +- Store authorization and translation classification are internal. A complete + store-token batch has zero LSU visibility during prepare, is atomically + captured into the OOO-owned buffer only on the common architectural commit + fire, and drains to LSU exactly once afterward. Recovery cannot cancel an + already accepted committed token. +- LSU refill responses preserve the complete cache line. Generic LSU and width + profiles default to no PMA regions; the natural platform profile alone marks + the UART and finisher pages as devices. Concurrent trace sources use a + deterministic prefix packer and exact accepted/dropped event counts. +- `EmitTOP` emits profile metadata used by the natural testbench. Port + validation initializes every configured P-map entry, uses the configured SP + architectural tag, pulses bootstrap completion, and observes bootstrap + readiness instead of relying on fixed W4/STID/GPR constants. + +## Fix-round 1 root-cause closure + +- The first controlled W4 run stopped at the first elaboration failure: the + two STD lanes can reserve two memory beats each, but the simulation STQ had + only two entries. RED reported an atomic reserve width of four against STQ + capacity two. The minimum GREEN repair centralizes + `stdPipes == storePipes` and requires + `storeQueueEntries >= stdPipes * maxMemoryRequestsPerInstruction`. + Simulation and activation W4 use four STQ entries; the two-entry commit queue + and four-entry SCB/lower-memory ledger remain unchanged. The run stopped in + 9.684 seconds with 2,382,921,728-byte peak RSS and 105 artifact bytes. +- The second controlled W4 run passed the STQ gate and stopped at the next + firtool failure: public `OOO` omitted both IEX store-binding Decoupled lanes. + The minimum GREEN repair wires both lanes' `valid` and complete `bits` inward + and `ready` outward with no Queue, register, or new state. The public OOO + FIRRTL round-trip and canonical exactly-once commit selectors passed. The run + stopped in 18.057 seconds with 4,148,314,112-byte peak RSS and 105 artifact + bytes. +- The next controlled W4 run emitted and built the VPI model, then failed + `bootstrap validation never observed bootstrapReady`. RTL dataflow was + intact: TOP directly projects IEX ready, while IEX registers + `bootstrapDone` on the rising edge where `bootstrapComplete` and the complete + P-map coincide. The harness sampled ready before that edge and cleared + completion without a post-edge sample. The new regression failed because no + ready sample existed between the completion edge and completion clear. GREEN + adds exactly one post-edge sample. The failed run took 796.478 seconds, + peaked at 7,166,525,440-byte RSS, and retained 959,769,017 bytes. +- The same run exposed an independent artifact-form issue. The clock/reset-only + wrapper required VPI access to nested CoreTOP ports, but global + `--public-flat-rw` exported 222,287 variables. Generated C++ occupied + 546,208,679 bytes and two nonreusable precompiled headers occupied + 202,356,768 bytes. RED contracts rejected global public exposure and required + linked PCH removal. GREEN uses `top_natural.vlt` to select only + `CoreTOP` ports matching `io_*`, retains the working wrapper topology, and + deletes PCH files after link. The runner already recreates `obj_dir`, so the + removed PCH files had no incremental reuse. +- A temporary two-port SV microproof validated Verilator 5.044 selective VPI: + the wrapper-path `io_write` deposit crossed a rising edge and appeared on + `io_read`, while an internal `hidden` signal had no `varInsert`. It printed + `selective-vpi-port-write=pass`. A direct-CoreTOP-top experiment was rejected + because writing the module-side alias was overwritten by the top input; + production therefore retains `CoreTOPHarness`. The temporary proof directory + was deleted after the test. +- Simulation-only physical capacities were reduced without changing semantic + widths, identity widths, lane counts, or main profiles. The literal RED was + `(16,64,8,8,256) != (4,4,4,4,4)` for + `(ITLB,L1I sets,miss,join,trace buffer)`. The GREEN table is: + + | Profile | Principal/trace width | ITLB | L1I sets | Miss | Join | Trace buffer | + | --- | ---: | ---: | ---: | ---: | ---: | ---: | + | W2 | 2 | 4 | 4 | 4 | 4 | 4 | + | W4 | 4 | 4 | 4 | 4 | 4 | 4 | + | W6 | 6 | 4 | 4 | 4 | 4 | 4 | + | W8 | 8 | 4 | 4 | 4 | 4 | 4 | + + Every profile retains `maxGroupsPerTransaction=8`, + `performanceCounterCount=32`, `maxTemplateUops=32`, and + ALU/BRU/AGU/STD/load/store lane counts `2/1/2/2/2/2`. The focused contract + runs `ParamChecks.validate` and compares public STID, RID slot, ROB member, + BID, P/T/U tag, LSID, transaction, and memory-identity widths with the main + profile for W2/W4/W6/W8. + +## Fix-round 2 root-cause closure + +- Direct no-Queue D2-to-D3-to-IEX activation exposed the dual-store deadlock at + the exact ROB binding boundary. IEX reconstructed only part of + `MemoryOrderMeta` and unconditionally computed `yostSid = firstSid - 1`; + the first store therefore underflowed the invalid payload while ROB retained + canonical zero. The repair preserves `yostSid` and the youngest-load triplet + in the private issue-row allocation and copies the complete public boundary. + ROB continues to compare full identity and `memoryOrder.asUInt`; no comparator + was weakened. The dedicated W4 regression proves two dispatch fires, two LSU + reservations, and two exact ROB bindings. +- Simulation profiles no longer shorten the MDB failed-wait timeout. A literal + W2/W4/W6/W8 RED observed `8 != 300`; GREEN inherits the main-profile value + while leaving all physical capacity reductions intact. +- `LSUParams.physicalMemoryRegions` now defaults empty. The params-folder + `NaturalPlatformParams` owns noncacheable, non-device normal RAM plus the + UART `0x10000000` and finisher `0x10009000` device-region overrides, and + EmitTOP applies them only for the simulation-natural selection. +- EmitTOP metadata now records the configured system-issue and retire widths. + The natural runner requires and forwards both values. The C++ harness drives + exactly `systemIssueLanes` ready pins; a missing configured pin is fatal, and + the previous hard-coded eight-lane catch-and-break probe is gone. +- Natural execution accepts an optional observation-only `--commit-trace` + JSONL sink. On each fired public `CommitTxn`, it serializes the bounded prefix + fields `pc`, `insn`, `wb_valid`, `wb_data`, `mem_valid`, `mem_is_store`, and + transaction value/generation; the observation never drives the DUT. The LR/SC cross-check now + requests this trace, runs the existing `summarize_trace`, and fails on a + nonzero natural-runner return code even when the emitted rows are valid. + +## Verification + +### Fix-round 3 exact committed-store observation + +- RED proved that an ordinary committed SWI does not carry the STD payload on + the public commit prefix while the accepted external `Write` carries the real + nonzero STD data. The Python summarizer initially could not join those two + observations. Its focused RED also covered a missing exact request, the + right transaction value with the wrong generation, a duplicate exact + request, and a nonzero natural-runner exit. +- The natural harness now emits separate bounded `commit` and + `memory_request` JSONL events. Every accepted external `Write` records its + exact transaction value/generation, address, data, and mask. The summarizer + performs an order-independent exact value-plus-generation join, obtains + ordinary-store data only from the accepted request, and rejects missing, + generation-mismatched, or duplicate matches. SC still consumes the commit + result and is not counted again as an ordinary store. +- The exact LSU regression first reproduced the RTL root cause: + `storeMemory.bits.identity.value` was `0` instead of the IEX-authored commit + transaction value `11`. LSU had zero-initialized the ROB-to-STQ commit token + and copied only logical/owner fields, so the serialized transport exposed + its private local counter. The repair preserves the IEX-authored transaction + in an STQ-indexed backend sidecar, projects that identity on the external + request, validates the exact external response, and maps it back to the + serializer's internal replay transport identity. IEX remains the owner of + transaction allocation/initial attempt; LSU only retains and rebinds it. +- GREEN used only + `LSUIntegrationSpec -z translated_committed_store_projects_exact_transaction_data_and_mask` + with the explicit arm64 firtool, jobs=1, and a 900,000,000-byte supervisor + budget. Exactly one test passed, proving `Write`, transaction value `11`, + generation `1`, address, nonzero STD data `0x1122334455667788`, and mask + `0xff`. The run completed in 14.063 seconds, peaked at 3,464,871,936-byte + RSS, and produced 115,111,958 bytes in the owned artifact directory. +- Fresh fix-round 3 checks passed: `Test/compile`; LR/SC Python 9/9; natural + harness Python 9/9; runner shell syntax; Python bytecode compilation; C++ + retained-header stub syntax; and scoped `git diff --check`. External AVS + execution remains `BLOCKED_EXTERNAL_ARTIFACT`; no external architectural + pass is claimed. Fix-round 3 is internally verified and awaits independent + re-review. + +### Fix-round 4 natural RAM transport closure + +- Independent review found that the fix-round 3 LSU test proved the serialized + transport mechanics using a device translation, but the LR/SC workload data + at `0x11000` still inherited generic `cacheable=true`. Its ordinary SWI would + therefore use SCB `AcquireWrite` (command 3), while the natural harness + correctly writes memory and records data only for serialized `Write` + (command 1). Treating `AcquireWrite` as store data would be semantically + false because the ownership request does not carry the STD payload. +- RED required a natural-platform normal-RAM attribute owner and failed because + none existed. GREEN sets only the simulation-natural default memory + attributes to readable/writable, noncacheable, and non-device. UART and + finisher retain explicit noncacheable device overrides. Generic + `LSUParams`, W2/W4/W6/W8 simulation profiles, public identity widths, and the + IEX-authored transaction/initial-attempt boundary are unchanged. +- The real-command source contract proves that only command 1 is recorded as a + `memory_request` and applied to sparse memory; command 3 is neither forged + nor interpreted as a data write. Natural/LRSC Python passed 19/19. The sole + focused Scala invocation was + `SimulationParamProfilesSpec -z natural_platform_normal_ram_noncacheable_devices_mmio` + with explicit arm64 firtool, jobs=1, and a 900,000,000-byte budget: 1/1 + passed in 11.309 seconds, peak RSS was 2,017,263,616 bytes, and it generated + zero artifact bytes. Shell/Python syntax and scoped diff checks passed. + Fix-round 4 is internally verified and awaits independent re-review; external + AVS execution remains `BLOCKED_EXTERNAL_ARTIFACT`. + +### Post-fix trace-schema cleanup + +- Chisel natural `event:"commit"` rows no longer emit the constant-zero + `mem_wdata` pseudo-field, and synthetic commit helpers/tests no longer create + or require it. Exact ordinary-store data continues to come only from the + accepted `event:"memory_request"` joined by transaction value/generation. +- Legacy/QEMU rows remain explicitly distinguished by the absence of + `event:"commit"`; only that direct-row path may consume `mem_wdata`. +- With `PYTHONDONTWRITEBYTECODE=1`, the focused natural plus LR/SC Python suites + passed 19/19. Retained-header C++ syntax and scoped diff checks passed; the + temporary stub and task-owned Python bytecode were removed. No Chisel, SBT, + firtool, or Verilator command ran for this cleanup. + +### Bounded parallel natural build control + +- Behavioral RED invoked the real runner self-test. The default manifest had + no `build_jobs`, explicit `--build-jobs 3` failed as an unknown option, and + invalid `0` lacked the required positive-integer diagnostic. +- GREEN adds one bounded control: default `build_jobs=2`, while explicit `1` + remains the low-memory fallback. `--build-jobs N` accepts only positive + decimal integers, is passed exactly to Verilator `--build-jobs`, and is + recorded in both self-test and every natural manifest produced before runner + exit, including a nonzero harness result. No profile, + capacity, width, or generated-file type changed. +- With `PYTHONDONTWRITEBYTECODE=1`, focused runner tests passed 12/12, including + real CLI invocations for default 2, explicit 3, and invalid 0. `bash -n` and + scoped diff checks passed. No Chisel, SBT, firtool, or Verilator command ran. + Skill evolution: `no-update`; existing LinxCore workflow guidance already + covers bounded build-resource controls. + +- Fresh fix-round `Test/compile` passed with the explicit native arm64 firtool + path. The generated JSON/Markdown interface manifest is current; + `InterfaceManifestSpec` plus `TopInterfaceSpec` passed 18/18. +- Focused behavior passed: simulation profiles 9/9; all public CTU template + forms across W2/W4/W6/W8 3/3 selected; fast-result peer-block atomicity 1/1; + commit-token common-fire capture/backpressure/exactly-once 1/1; W4 dual-store + dispatch 1/1; W4 canonical dual-lane STQ reservation 1/1; exact/max-generation + and dual-lane ROB binding 3/3 selected; STQ recovery Prepare/Abort 2/2 plus + peer-STID Apply 1/1; IEX lane-1 transaction sharing 1/1; canonical graph + common commit exactly once 1/1; full nonuniform refill line 1/1; concurrent + trace overflow 2/2 selected; derived device-store request 2/2 selected. +- Active natural/cutover/LRSC/IPC, production-owner-manifest, and NDF Python + checks passed 72/72, including the single-emit VPI/lint reuse contract and + heartbeat/deadlock CLI/source contract. Runner shell syntax and the natural + testbench C++ syntax check passed. A deadlock records + `terminal_status=deadlock` and returns nonzero. + `git diff --check` passed. +- The final focused parameter suite passed 10/10 with the explicit arm64 + firtool path. Natural-harness Python tests passed 7/7; runner shell syntax, + retained-header C++ syntax, and diff checks passed. +- Exactly one final controlled W4 verification used jobs=1, 30-second + heartbeat, 900-second stall, 1800-second wall, and a 900,000,000-byte + artifact budget with the explicit arm64 firtool. EmitTOP completed; the VPI + model built from 5,812.549 MB of sources in 192 modules into 279.872 MB and + 122 C++ files in 245.850 seconds. Runtime stdout reported + `top-vpi-port-validation=pass` and + `top-vpi-bootstrap-validation=pass entries=24`. +- Lint completed from 5,812.743 MB of sources in 192 modules into 181.870 MB + and 92 C++ files in 34.620 seconds. Supervisor result was + `return_status=0`, `child_status=0`, `reason=child-exit`, elapsed 321.041 + seconds, peak RSS 5,755,518,976 bytes, and 377,134,902 artifact bytes in 593 + files. No PCH files remained; artifact headroom was 522,865,098 bytes. +- The final manifest records `terminal_status=port_validation_pass`, 30 cycles, + zero loaded bytes, `comparison_kind=none`, no instruction or commit oracle, + zero captured mismatch, and expected zero IFU/CTU/OOO/IEX/LSU activation for + the port-validation fast path. Profile metadata records `stidCount=1`, + `gprArchRegs=24`, `spAtag=1`, `traceWidth=4`, `loadLanes=2`, and + `storeLanes=2`. +- Scalar linx-avs natural smoke: `BLOCKED_EXTERNAL_ARTIFACT`. Canonical source + entry is `/Users/zhoubot/linx-isa/avs/compiler/linx-llvm/tests/run.sh`; its + pinned compiler path `compiler/llvm/build-linxisa-clang/bin/clang` is absent, + no executable clang is present under `compiler/llvm`, and `avs` contains + zero `.elf` files. Task 18 did not build LLVM or substitute another ELF. + Consequently no architectural mismatch result is claimed; natural manifests + explicitly record `comparison_kind=none`. No CoreMark or Dhrystone natural + pass is claimed from the port-validation result. +- Fix-round 2 focused verification used the explicit native arm64 firtool. + `OOOIEXDirectDualStoreBoundarySpec` passed 1/1 with two dispatch, + reservation, and binding fires plus zero exact metadata mismatches + (`return_status=0`, elapsed 66.899 seconds, peak RSS 5,635,112,960 bytes). + `SimulationParamProfilesSpec` passed 13/13 (`return_status=0`, elapsed 5.505 + seconds, peak RSS 970,555,392 bytes, zero artifacts). `Test/compile` passed + without a firtool override. The combined natural harness and LR/SC Python + suites passed 14/14; runner shell syntax, Python bytecode compilation, C++ + stub syntax, `git diff --check`, and the NDF local-reference check passed + (`clauses=157`, `l1_must=74`, `verified=83`, `open_questions=0`). No full TOP Verilator run was started in this + round. The AVS smoke remains `BLOCKED_EXTERNAL_ARTIFACT`, so no external + architectural result is claimed. + +### Fix-round 5 Option-A structural replay and bounded W2 evidence + +- Option A remains the frozen ownership contract: IEX allocates the memory + transaction and initial load attempt; LSU owns every later replay/rebind. + A private TOP probe found one violation in the integrated structural-forward + path: `LoadStructuralBlockPolicy` drove LIQ `structuralRetry` directly. LIQ + advanced to attempt generation 2 while the retained IEX terminal metadata + remained at generation 1, so the generation-2 result failed the exact + completion match and left its ROB destination unresolved. +- RED required the emitted public LSU to carry structural replay through + `loadRepick` and return it through `loadRebindApply`, and rejected a direct + policy-to-LIQ retry connection. GREEN adds the typed structural disposition + and exact wait-store key to `LoadRepickTxn`/`LoadReissueTxn`; the IEX metadata + rebind, selected LIQ mutation, and old-attempt cancel now share one common + fire. Ordinary replay retains the existing `attemptRebind` path, while a + structural replay selects `structuralRetry` only after the IEX round trip. + No physical LIQ row is exposed on the public interface. +- Focused evidence with a 2048 MiB SBT heap: structural integration 1/1, + TOP interface contract 13/13, and IEX/LSU integration 2/2 passed. The TOP + contract checks every structural wait-store field and width. Temporary + private-root C++ probes were removed before the fresh build. +- The fresh natural W2 run used only width 2, Verilator build jobs 2, disabled + waveform/coverage generation, a 20,000-cycle ceiling, and a 5,000-cycle + deadlock window. Verilator built 5,451.550 MB of sources into 266.283 MB in + 681.959 seconds; the owned temporary directory reached about 438 MiB. The + run advanced to 19 OOO commits and terminated `deadlock` at cycle 5,460 + after last progress at cycle 460. Activation was IFU 93, CTU 2, OOO 19, + IEX 8, and LSU 8. This is forward-progress evidence over the previous + attempt-generation failure, not an architectural or benchmark pass. +- W2/W4/W6/W8 public width identities and the fixed 2/1/2/2 execution plus + 2-load/2-store topology remain unchanged. Only simulation capacities, + default SBT heap (2048 MiB), full-build concurrency (2), and watchdog bounds + are reduced. No full W4/W6/W8 model was generated in this round. +- After evidence capture, the owned W2 model, Chisel simulation output, SBT + targets, BSP metadata, PCH/object files, and Python bytecode caches were + removed. No ignored Chisel/SBT/Verilator output remains in the repository. + +### Fix-round 6 branch feedback, BROB-bounded commit, and rename floor + +- The frozen memory ownership decision is explicitly Option A: IEX allocates + the transaction plus initial attempt, while LSU owns replay/rebind only. + Branch terminal publication now preserves fetch/prediction identity through + DEC and IEX, validates it on one typed B-SIDE transaction, sends the resolved + prediction to IFU, and emits exact ROB recovery atomically on mismatch. +- Natural W2 first exposed an unsupported `C_SEXT_W`; the ALU now implements + the byte/half/word sign-extension family. It next exposed branch-control + outputs tied permanently not-ready in IEX. Removing those sinks and adding + one depth-one queue per terminal lane breaks the bctrl/recovery ready cycle + without dropping branch validation. The prior `C_SETC_EQ` row now reaches + terminal publication and ROB completion. +- The next exact deadlock had five completed ROB rows but no public commit. + Read-only state showed `ROB valid/count=1/2` and all release owners ready + except BROB. The prefix crossed BID 3 to BID 4, while BROB correctly accepts + release only for its current head block. RED observed count two; GREEN makes + ROB commit preview stop at BID/BROB-generation boundaries. The focused test + also proves the next block appears after the first prefix applies. +- A fresh width-2 natural build used a 2048 MiB SBT heap, one Verilator build + job, no lint/waveform/coverage, a 20,000-cycle ceiling, and a 3,000-cycle + deadlock window. Verilator built 5,972.485 MB of sources in 199 modules into + 284.105 MB and 114 C++ files in 492.633 seconds, allocating 2,822.375 MB. + Natural execution advanced from the previous 21-commit gate to 25 commits + and then reported the next independent deadlock at cycle 3,472 after progress + at cycle 472. Activation was IFU 93, CTU 2, OOO 25, IEX 10, and LSU 8. +- The final retained row was a completed early `opcode 0x12` in an open BID 5. + The next D2 group was valid but rename was not ready: the aggressively + reduced W2 P-MapQ was 4/4 full and only one of 32 physical GPRs remained + free, so the younger suffix could not rename to close the block. Simulation + rename capacity now has a 16-row forward-progress floor and at least 16 + speculative physical GPRs beyond the 24 architectural registers. This is + still one quarter of the main MapQ depth; public W2/W4/W6/W8 identities and + 2/1/2/2 plus 2-load/2-store topology remain unchanged. +- Focused verification: branch feedback 2/2, interface plus profile 28/28, + terminal identity 1/1, ALU sign extension 1/1, and the BROB-bounded ROB + preview 1/1 passed. After the rename-floor correction, + `SimulationParamProfilesSpec` passed 16/16 with zero Chisel simulation + artifacts, a 536,870,912-byte budget, one job, and 1,614,921,728-byte peak + RSS. The 25-commit model predates the rename-floor correction; no benchmark + pass is claimed from it. + +### Fix-round 7 Option-A IQ progress and low-artifact W2 closure + +- The forced decision remains Option A: IEX allocates the memory transaction + and initial attempt; LSU owns replay/rebind. No ownership field or allocation + point moved in this round. +- Resource validation was intentionally limited to W2, a 2048 MiB SBT heap, + one outer test/build job, a 20,000-cycle ceiling, and a 3,000-cycle deadlock + window. W4/W6/W8 were not generated. The simulation rename/ROB capacity + remains at the previously proven 16-row forward-progress floor; reducing it + further would reintroduce the already reproduced open-block deadlock. +- The first W2 deadlock retained two ALU admissions in bank 0 while bank 1 was + empty because each ALU dispatch lane was pinned to a lane-derived bank mask. + RED rejected a third admission after filling bank 0. GREEN permits every ALU + lane to select any eligible bank and proved spill into bank 1. The natural + run then increased IFU requests from 73 to 81 and trace events from 37 to 48, + but architectural commit remained 27, so this was progress rather than a + benchmark pass. +- A temporary read-only root probe identified the next exact owner: ROB + `rid=3/member=1`, ALU transaction 27, waited on P source `ptag=26`, generation + 1. Its physical-file owner was valid and ready with the same stid/generation, + but the producer epoch was 5 and consumer epoch was 7. Resident committed + and speculative wakeup matching incorrectly required equal frontend epochs + for P operands. RED/GREEN now proves both cross-epoch wakeup kinds; P uses + stid plus PTag generation, while T/U retain epoch plus local-sequence checks. +- The cross-epoch repair alone left the same natural state because a file write + and row admission can cross one edge after the one-cycle wakeup pulse. A + second RED changed the exact operand-file readiness after the row became + resident and observed readiness remain zero. GREEN makes resident rows + converge from the complete centralized ready identity: P checks + `{stid, ptag, generation}` and T/U check + `{stid, epoch, localTag, localSequence}`. Recovery-fenced rows remain blocked. +- Focused W2 evidence passed `Test/compile` and the one selected + `IEXPrivateIngressSpec` test covering committed wakeup, speculative-load + wakeup, and post-admission file-readiness convergence. The final GREEN ran + 1/1 in 211 seconds; the supervisor measured 703,081,306 artifact bytes and + 9,702,883,328-byte peak RSS. ChiselSim output was deleted immediately after + capture. Temporary C++ root probes were removed before the fresh TOP build. +- A further RED showed that a source could become exactly ready after the IQ + query or P1 capture while the saved speculative-ready snapshot had already + expired. GREEN refreshes exact file readiness both when forwarding the IQ + query and in I1. The I1 test preserves the captured P identity, then makes + `{stid, ptag, generation}` ready and proves that the lane issues an RF read; + T/U use `{stid, epoch, localTag, localSequence}`. The focused I1 test passed + 1/1 in 12 seconds with 153,893,985 artifact bytes and about 3.0 GiB peak RSS. + Its fixture was also aligned with the current three D3 PC-write ports and + four PC banks. `Test/compile` passed after the final static-index cleanup. +- The final W2 TOP build used only a 2048 MiB SBT heap and one build job. It + emitted 199 modules / 6,653.193 MB of sources, generated 123 C++ files / + 336.545 MB, and completed in 439.991 seconds with 3,474.516 MB allocated by + the build tool. The bounded run used 20,000 maximum cycles, 2,000-cycle + heartbeat, and 3,000-cycle deadlock detection. W4/W6/W8 were not generated. +- Natural execution still stopped at 27 commits at cycle 3,473 after progress + at cycle 473; therefore no benchmark pass is claimed. A read-only probe of + that exact retained model proved that the readiness repair worked: + transaction 27 left its IQ/I1 row and occupied the ALU E1 transfer slot, + while transaction 36 advanced behind it into I2. +- The next independent owner is ALU execution coverage. Transaction 27 is + normal scalar `OP_SLL` (`0x119`) with two P sources in the exact recipe, but + `OooIexAluPipeline.SupportedOpcodes` does not include `OP_SLL`; its expected + source count remains zero, so exact E1 admission is rejected. This is the + next implementation gap, not a reason to weaken recipe validation. +- ChiselSim's outer job count was one, but its internal Verilator invocation + still used `-j 0`; the 9.7 GiB focused-test peak is therefore a remaining + resource-control gap. Final validation artifacts are removed after evidence + capture; the repository retains only source, tests, and reports. + +### Fix-round 8 scalar ALU coverage under the low-resource W2 iteration profile + +- The architectural ownership decision remains Option A: IEX allocates the + memory transaction and initial attempt; LSU owns replay and rebind. This + round changes scalar ALU coverage only and does not move transaction or + attempt ownership. +- Iteration stayed on the low-resource W2 profile: W2 only, a 2048 MiB SBT + heap, one outer build job, 20,000 maximum cycles, a 2,000-cycle heartbeat, + and a 3,000-cycle deadlock window. W4/W6/W8 were not generated. The existing + 16-row simulation rename/ROB floor was retained because the earlier 4-row + profile was already proven unable to close an open block. +- Those bounds are now the natural runner defaults instead of command-line + discipline only: width 2, one build job, 20,000 maximum cycles, 2,000-cycle + heartbeat, and 3,000-cycle deadlock detection. Every value remains explicitly + overridable for final benchmark and width-matrix gates. RED observed the old + W4/two-job/million-cycle defaults; GREEN passed four focused Python checks, + including the default self-test manifest and explicit parallel override. +- A directed RED rejected `OP_SLL` in E1. The implementation now covers the + complete base scalar shift family rather than special-casing the observed + opcode: `SLL/SRL/SRA`, `SLLI/SRLI/SRAI`, `SLLW/SRLW/SRAW`, and + `SLLIW/SRLIW/SRAIW`. Register shifts require exactly two sources, immediate + shifts exactly one, shift amounts use the architectural 6-bit or 5-bit mask, + and word results are sign-extended. The 12-case focused GREEN passed 1/1 in + 11.145 seconds (33.099 seconds total), retained 117,403,177 artifact bytes + before cleanup, and measured 3,694,411,776-byte peak RSS. +- The fresh W2 TOP elaboration completed in approximately 649 seconds. Its + interrupted outer wrapper left both large generated objects intact; a + single-job make recovered and linked the exact model without regenerating + RTL. The generated directory was approximately 534 MB before cleanup. +- Natural execution reached a heartbeat at cycle 2,000 with 36 commits, 81 + instruction requests, 9 data requests, and 54 trace events. It stopped at + cycle 3,497 after last progress at cycle 496. Activation was IFU 116, CTU 5, + OOO 36, IEX 14, and LSU 9. Commit progress from 27 to 36 proves the previous + `OP_SLL` owner is resolved, but the terminal state remains deadlock and no + benchmark pass is claimed. +- A temporary read-only root probe identified the next exact retained owner as + ROB `rid=12/member=0`, ALU transaction 36, `OP_HL_LUI` (`0xa4`), with zero + sources. A younger retained slot held `OP_LUI` (`0x10c`). The probe was + removed after capture and is not part of the delivered harness. +- Frontend decode already publishes a normalized immediate for `OP_LUI`, + `OP_HL_LUI`, `OP_HL_LIS`, and `OP_HL_LIU`; IEX must consume that value + without re-decoding instruction bits. A directed RED observed `OP_LUI` + rejected in E1. GREEN adds the four zero-source load-immediate opcodes and + returns the normalized immediate. The focused test passed 1/1 in 5.964 + seconds (18.279 seconds total), retained 117,262,350 artifact bytes before + cleanup, and measured 3,677,093,888-byte peak RSS. +- A second fresh W2 model containing the load-immediate repair elaborated in + 72 seconds with cache reuse. Verilator built 6,653.496 MB of sources in 199 + modules into 123 C++ files / 336.590 MB in 470.597 seconds on one thread; + the complete disposable build directory occupied 494 MB at evidence + capture. Natural execution advanced from 36 to 37 commits, with activation + IFU 114, CTU 5, OOO 37, IEX 14, and LSU 9. It stopped at cycle 3,488 after + last progress at cycle 488; terminal status therefore remains deadlock and + no benchmark pass is claimed. The trace contains `OP_HL_LUI` in IEX after + the repair, confirming the previously rejected owner advanced. +- A proposed temporary root probe would have caused make to rebuild the large + generated translation unit because of PCH dependency invalidation. That + rebuild was stopped immediately, and the temporary source probe was removed. + The next loop must locate the new exact owner without regenerating RTL merely + for diagnostics. No W4/W6/W8 generation is warranted until W2 advances. + ChiselSim's internal Verilator `-j 0`, PCH invalidation, and the generated + model's large translation unit remain resource-control gaps despite the + one-job outer wrappers. + +### Fix-round 9 compact memory decode and smaller W2 IQ + +- Option A remains authoritative and unchanged: IEX allocates the memory + transaction and initial attempt; LSU owns replay, reissue, repick, rebind, + and every subsequent attempt. Compact-memory support reuses that ownership + boundary and does not introduce a second allocator. +- A catalog regression exposed all four compact memory forms as generic + compressed ALU operations. `C.LWI/C.LDI` now generate load recipes and + `C.SWI/C.SDI` generate store recipes while their stable opcode IDs remain + unchanged. D1 normalizes the encoded compact offset exactly once according + to access size, compact loads allocate a T destination, and compact stores + consume the encoded base plus T source. +- The IEX-to-LSU-to-IEX return path now preserves GPR/T/U destination kind and + its matching PTag/TTag/UTag rather than rewriting every load destination to + GPR. Focused regressions pass for frontend offset preservation, all four D1 + compact-memory forms, AGU T destination admission, LIQ T destination + binding, and terminal T metadata. The generated catalog form suite passes + 8/8 and the deterministic recipe audit passes 689 entries. +- The fresh low-resource W2 natural build used one configuration, one build + job, and a 2048 MiB SBT heap. Verilator processed 199 modules, reported + 6,662.148 MB of generated source, emitted 123 C++ files / 336.664 MB, and + completed in 839.007 seconds. The disposable directory occupied 532 MB. + Natural execution advanced from 37 to 40 commits, reached a cycle-2,000 + heartbeat with 89 instruction and 10 data requests, and stopped at cycle + 3,522 after last progress at cycle 522. Activation was IFU 135, CTU 5, OOO + 40, IEX 21, and LSU 10. This proves the compact-memory owner advanced; the + terminal state remains deadlock and no benchmark pass is claimed. +- Static ELF decode places the next architectural instruction after the last + committed `OP_C_SEXT_W` at `pc=0x10100`: `OP_C_SETC_NE`, followed by the + next block boundary. That is the next independent execution/control owner + to diagnose; this inference is not yet a retained-state root probe. +- W2 no longer retains an unnecessary second row in each scalar IQ bank. Its + bounded capacity changes from four total entries to two total entries while + preserving both banks, the 2-ALU/1-BRU/2-AGU/2-STD/1-system/1-CMD physical + topology, two load/two store pipes, rename/ROB forward-progress floors, and + every fixed identity width. The parameter regression first failed 4 != 2 + and then passed all 16 cases after the capacity change. A fresh W2 RTL-only + emission completed in 71 seconds and reduced emitted SV from 63,896,864 to + 55,722,033 bytes (12.8%) and from 198 to 194 files. A size-one Vec selector + removes the 21 dynamic-index warnings introduced by one row per bank; only + the two pre-existing trace-enum cast warnings remain. + +### Fix-round 10 exact local-owner epoch and bounded W2 progress + +- Option A remains frozen: IEX allocates the memory transaction and initial + attempt; LSU owns replay, reissue, repick, rebind, and every subsequent + attempt. No transaction or attempt owner moved in this round. +- The retained W2 `OP_C_SETC_NE` row named T tag 4 / sequence `{4, 0}`. A + read-only probe showed that exact T-file row allocated and ready with owner + epoch 9, while issue incorrectly qualified it with the consumer frontend + epoch 11. The former producer-commit reclamation hypothesis was disproved by + a fresh natural run and its temporary code and tests were removed. +- Rename now carries the producer allocation epoch as part of every T/U source + identity. TURename retains it in the ordered MapQ, RENU preserves it across + D2-D3, and IEX uses it for admission readiness, resident wakeup, bypass, + P1 readiness, and T/U operand-file reads. The consuming row epoch remains + unchanged for recovery and row ownership. +- Directed RED/GREEN evidence passed the TURename producer-to-consumer epoch + case 1/1, the RENU seam case 1/1, and the IEX exact local-owner readiness + case 1/1. The latter passed on W4; a W2 rerun exposed only ChiselSim access + to legal zero-width minimum-profile fields, so the shared test helpers now + avoid touching invalid payloads and derive query geometry from the DUT. +- Iteration remained W2-only with a 2048 MiB SBT heap, one build job, 20,000 + maximum cycles, a 2,000-cycle heartbeat, and a 3,000-cycle deadlock window. + The two-entry scalar IQ profile was retained. Verilator processed 196 + modules / 5,829.528 MB of sources, emitted 116 C++ files / 291.136 MB, and + completed in 485.346 seconds on one thread. The disposable directory was + approximately 466 MB before cleanup; W4/W6/W8 TOP models were not generated. +- Natural execution advanced from 40 to 46 commits. `OP_C_SETC_NE` at + `pc=0x10100` reached IEX at cycle 235, proving the exact local-owner epoch + repair removed the previous deadlock. The run stopped at cycle 3,273 after + last progress at cycle 273, with 89 instruction requests, 12 data requests, + and 74 trace events. No benchmark pass is claimed. +- The new independent retained head is transaction 46 at `pc=0x10110`, opcode + 7 (`OP_BSTART_FP_FALL`), instruction ID 66, epoch 12. The BRU has transaction + 49 in flight and transaction 57 resident on T tag 6 / sequence `{6, 0}` with + that source not ready. This control/BROB/BCTRL owner needs a separate exact + diagnosis; the evidence does not justify increasing W2 capacity. + +## Initial pre-review resource evidence + +- The following measurements belong to the initial implementation before the + fix-round review; they are not claimed as final fix-round evidence. +- Focused selectors used repository wrappers, jobs=1, native arm64 firtool, + and a 900,000,000-byte artifact budget. All reported zero retained artifact + bytes. Peak RSS: TOP topology SV 6,353,977,344 bytes; width CHIRRTL + 4,903,763,968 bytes; interface 999,899,136 bytes; manifest 1,027,358,720 + bytes. +- Initial pre-review bounded W4 emit: 40 seconds, max RSS 3,859,513,344 bytes. +- Verilator VPI build: 646.9 seconds, max RSS 6,536,298,496 bytes, jobs=1. +- Verilator lint: 12.6 seconds, max RSS 3,059,433,472 bytes. +- Verilator 5.044 reserves the identifier `TOP` internally. The lint/harness + path therefore makes a simulation-only textual copy named `CoreTOP` and + wraps it with `CoreTOPHarness`; the delivered emitted module remains `TOP`. + +## Concerns and review handoff + +- All fix-round 4 review findings within repository control have focused + dynamic or static closure. The only external workload gap is the unavailable canonical + AVS compiler/ELF described above; no substitute architectural oracle is + claimed. Fix-round 4 implementation and focused verification are complete; + Task 18 remains awaiting independent re-review and is not finally approved. +- Skill evolution: `no-update`; the LinxCore workflow already covers this + topology/interface/harness cutover and no reusable gap was found. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-6-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-6-report.md new file mode 100644 index 00000000..08b3d88b --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-6-report.md @@ -0,0 +1,173 @@ +# Task 6 Report - B-SIDE Prediction and IFU Recovery + +## Outcome + +Task 6 is complete on branch `codex/chisel-gap-superpowers`. + +Prediction now has a public `linxcore.ifu.BSide` boundary that reuses the existing retained predictor/history implementation, so BTB/TAGE/BIM/RAS/loop/history state still has one owner. Recovery now has public `linxcore.ifu.IFURecovery` and `linxcore.ifu.IFUBackendFeedback` boundaries over the canonical redirect and OOO-authored backend feedback mechanisms. `LinxCoreIfu` instantiates the public boundaries directly. Public `IFU` W2/W4/W6/W8 elaboration keeps the fixed-width IFU-to-CTU payload unchanged and does not instantiate a tied-off backend feedback queue without a live TOP/OOO producer. + +## Files Changed + +- `chisel/src/main/scala/linxcore/ifu/BSide.scala` - added the public B-SIDE prediction owner boundary over `BSidePredictionPipeline`. +- `chisel/src/main/scala/linxcore/ifu/Prediction.scala` - added side-effect-free provider rank helper documenting speculative provider order; backend recovery is intentionally absent. +- `chisel/src/main/scala/linxcore/ifu/IFURecovery.scala` - added public recovery and backend feedback boundaries over the existing redirect arbiter and feedback bridge. +- `chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala` - wired production IFU composition through `linxcore.ifu.BSide` and `linxcore.ifu.IFURecovery`. +- `chisel/src/main/scala/linxcore/ifu/ISide.scala` - factored canonical `InterfaceParams` construction into `ISide.interfaceParams`. +- `chisel/src/main/scala/linxcore/frontend/ISideF0PcSelect.scala` - replaced Bundle-wide `Mux1H` over prediction contexts with field-safe selected record wiring to remove retained enum-cast warnings. +- `chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala` - added B-SIDE provider, stale training, and public-boundary elaboration coverage. +- `chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala` - added backend priority, redirect hold, feedback-port, and atomic feedback/recovery coverage. +- `chisel/src/test/scala/linxcore/ifu/IFUCTUIntegrationSpec.scala` - added public IFU integration coverage for CTU backpressure, scoped recovery, and W2/W4/W6/W8 elaboration. +- `docs/spec/20-behavior/ifu.md` - added `IFU-008` and `MEC-IFU-006`. +- `docs/spec/50-verification/ifu-conformance.md` - added `VER-IFU-005`. +- `docs/chisel/modules/frontend/LinxCoreIfu.md` - documented public B-SIDE/recovery ownership and Loop 6 verification. +- `docs/chisel/mainline-loop-ledger.md` - recorded Loop 6 scope, identity baselines, evidence, remaining gap, and skill-evolve decision. + +## RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` failed before implementation with missing public boundary symbols: `BSide`, `IFURecovery`, and `IFUBackendFeedback`. +- `bash tools/chisel/run_chisel_tests.sh --only IFURecoverySpec` failed before implementation with the same missing boundary symbols. + +## GREEN Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 0; 3 tests passed: + - B-SIDE provider order prefers B-F4 final prediction over lower speculative providers. + - Stale training is rejected without mutating provider history. + - Public `linxcore.ifu.BSide` elaborates as `module BSide`. +- `bash tools/chisel/run_chisel_tests.sh --only IFURecoverySpec` -> exit 0; 4 tests passed: + - Backend typed recovery overrides held prediction correction. + - Redirect priority and retained hold preserve backpressure. + - Backend feedback accepts OOO-authored validation and emits no IEX control port. + - Mispredict training and backend recovery remain atomic at the feedback boundary. +- `bash tools/chisel/run_chisel_tests.sh --only IFUCTUIntegrationSpec` -> exit 0; 2 tests passed: + - Public IFU retains IFU-to-CTU backpressure while exposing one B-SIDE and one recovery authority. + - W2/W4/W6/W8 IFU elaboration exposes `module IFU`, `module BSide`, and `module IFURecovery`. + +## Adjacent Verification + +- `bash tools/chisel/run_chisel_tests.sh --only IFUISideSpec` -> exit 0; 4 tests passed after the PC-select enum-cast warning fix. +- `bash tools/chisel/run_chisel_tests.sh --only CTUSpec` -> exit 0; 11 tests passed. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles` -> exit 0; 9 tests passed. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` -> exit 0; 8 tests passed. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` -> exit 0; 2 tests passed. +- `python3 tools/chisel/render_top_interface_manifest.py --check` -> exit 0; `top-interface-manifest: up to date`. +- `python3 -m unittest tests.test_ndf_profile -v` -> exit 0; 10 tests passed. +- `python3 tools/spec/check_ndf_profile.py docs/spec` -> exit 0; `clauses=89 l1_must=38 verified=41 open_questions=0 references=2`. +- `bash tools/chisel/build_chisel.sh` -> exit 0; Chisel build completed successfully. +- `bash tools/chisel/run_chisel_verilator_lint.sh` -> exit 0; Verilator 5.044 lint completed successfully. +- `git diff --check` -> exit 0; no whitespace errors. + +## Self-Review + +- The public B-SIDE class is a wrapper, not a new predictor body. This preserves the single owner for predictor and history state. +- Recovery authority remains singular through the canonical redirect arbiter. Backend recovery is not modeled as a prediction provider and takes priority through the backend redirect path. +- Public IFU still exposes typed recovery but does not allocate an unused backend feedback queue until TOP/OOO supplies a real validation producer. +- The IFU-to-CTU interface manifest remains up to date; Bundle shape did not change. +- The retained enum-cast warnings observed in the first post-change `IFUISideSpec` run were removed by replacing Bundle-wide enum muxing in `ISideF0PcSelect`. + +## Remaining Risks / Deferred Work + +- Live TOP/OOO backend-validation wiring is deferred to the later TOP/OOO integration packet; `IFUBackendFeedback` is available as the public boundary but is not tied off below public IFU. +- Natural ELF/commit evidence remains in Tasks 18-19. +- `IFUCTUIntegrationSpec` and `IFUISideSpec` are slow wrappers but completed green; no lingering SBT/Java/Verilator processes remained after verification. + +## Skill-Evolve Decision + +No skill update is required. The reusable invariants exercised here are already covered by the LinxCore workflow: exact identity matching, single state owner, retained ready/valid behavior, and OOO-owned recovery authority. + +## Review Fixes + +Round 1 Important findings are fixed in the follow-up coverage commit. + +- `IFUPredictionSpec` now keeps the original provider-order requirement but proves more than the prior B-F4-only body: + - Public `Prediction.providerRank` is asserted for Sequential=0, B-F0=1, B-F1=2, B-F2=3, B-F3=4, and B-F4=5. + - Sequential behavior is driven with an explicit no-boundary B-F4 completion. + - B-F0, B-F1, and B-F2 are isolated with trained-table and table-conflict cases. + - B-F4 final LongTAGE-over-static behavior remains covered. +- `IFUPredictionSpec` now adds public B-SIDE checkpoint/state coverage: + - Exact keyed canonical prune restores older GHR state and kills younger history. + - RAS state remains unchanged until canonical prune, then feeds a later B-F4 return prediction. + - BTB/TAGE/BIM/loop state is trained only through exact public B-SIDE resolution, and an inexact follow-up resolve is rejected as stale without changing the later loop prediction. +- `IFUCTUIntegrationSpec` now runs the traffic, retained backpressure, scoped recovery fence/apply, and fixed 64-bit instruction payload checks across W2, W4, W6, and W8. +- Minor no-IEX issue: `IFURecoverySpec` now checks the public `IFUBackendFeedback` IO element names structurally (`validation`, `resolve`, `backendRecovery`, and no IO name containing `iex`) before keeping the emitted-SystemVerilog substring sanity check as secondary evidence. + +Review-fix RED evidence: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1 on the first review-fix run. The new loop/BTB/TAGE exact-training test failed at `IFUPredictionSpec.scala:475` because stale training was injected while a final correction was still pending; observed `staleTraining=0`, expected `1`. The test was corrected to apply the canonical prune before injecting the inexact resolve. + +Review-fix GREEN evidence: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 0; 6 tests passed: + - Provider rank/order, stale training, checkpoint-owned GHR recovery, canonical RAS recovery, exact public B-SIDE training, and public B-SIDE elaboration. +- `bash tools/chisel/run_chisel_tests.sh --only IFURecoverySpec` -> exit 0; 4 tests passed: + - Includes the structural public-IO no-IEX assertion. +- `bash tools/chisel/run_chisel_tests.sh --only IFUCTUIntegrationSpec` -> exit 0; 2 tests passed in 4 minutes 57 seconds: + - W2/W4/W6/W8 traffic/backpressure/scoped-recovery behavior and W2/W4/W6/W8 elaboration both passed. +- `bash tools/chisel/run_chisel_tests.sh --only IFUISideSpec` -> exit 0; 4 tests passed. +- `bash tools/chisel/run_chisel_tests.sh --only CTUSpec` -> exit 0; 11 tests passed. +- `bash tools/chisel/build_chisel.sh` -> exit 0; Chisel build completed successfully. +- `git diff --check` -> exit 0; no whitespace errors. + +No production code changed in the review-fix round. The remaining TOP/OOO backend-validation wiring gap is unchanged and remains deferred to the later integration packet. + +## Review Fixes Round 2 + +Round 2 found one remaining Important issue: BF3 was still covered only by `Prediction.providerRank`, not by a real public `BSide` simulation. + +I attempted to add that simulation without production-only hooks. The public behavior did not produce an observable BF3 response under multiple real and public-path setups, so I stopped test tweaking per instruction and did not leave a failing test in the branch. + +Round-2 RED evidence: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1; compile failed because the first reset helper used nonexistent `IfuInnerFlushReason.Start`. +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1; BF3 setup with trained ShortTage, overwritten lower BTBs, and seeded BF2 sidecar produced no response within 24 cycles. +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1; manual epoch-0 ShortTage training then drain failed the existing assertion `prediction correction must restore an exact B-F0 history checkpoint`, proving the training request had already released its checkpoint before a late correction. +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1; normal public training plus alias/seeded sidecar produced no response within 24 cycles. +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1; real-pipeline BF2/BIM-then-BF3 setup produced no response within 128 cycles. + +Round-2 conclusion: + +- The seeded-sidecar attempts were invalid because `BSidePredictionPipeline` deliberately overwrites incoming request prediction with the Sequential initial payload. +- The real-pipeline attempt should have left pBTB/BIM trained for B-F2 and ShortTage trained for B-F3 through public `BSide` behavior, then reset GHR before a new target request. The request still produced no progressive response within 128 cycles. +- This is no longer just a coverage-gap edit. It needs a production investigation/fix lane for BF3 observability/arbitration before a passing BF3 simulation can be committed. + +Round-2 GREEN evidence after removing the failing exploratory test edits: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 0; 6 tests passed. +- `bash tools/chisel/build_chisel.sh` -> exit 0; Chisel build completed successfully. + +## Review Fixes Round 2 Correction + +This section supersedes the earlier Round 2 conclusion and commit +`983abd8f`. The earlier "production observability gap" conclusion was wrong: +BF3 is intentionally silent when ShortTage agrees with the current effective +tuple, and BF4 waits for an exact boundary/no-boundary event. + +The authentic public `BSide` BF3 regression is now committed in +`IFUPredictionSpec`: + +- Target conditional `0x5300` is first trained not-taken at request-owned + GHR 0, establishing the target ShortTage tag/counter. +- Alias conditionals `0x5310`, `0x5330`, and `0x5350` share a one-entry BIM + but use different pBTB and ShortTage slots, driving BIM taken without + overwriting the target ShortTage slot. +- A public `KillAllThreadState` prune with GHR/RAS reset returns the target + request's future `ghrBefore` to 0 while predictor tables remain intact. +- The target request then observes a real BF2/BIM taken progressive response, + accepts the canonical prune for that correction, and then observes a real + BF3/ShortTage not-taken progressive response with `finalResponse=false`. + +Round-2 correction RED evidence: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 1 + with the first authentic stimulus attempt. BF2/BIM was observed, but the next + response was BF4 final rather than BF3 because alias `0x5320` evicted the + target ShortTage slot. The alias set was corrected to avoid the target + ShortTage index for each current GHR value. + +Round-2 correction GREEN evidence: + +- `bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec` -> exit 0; + 6 tests passed, including the authentic BF3/ShortTage public `BSide` + simulation. +- `bash tools/chisel/build_chisel.sh` -> exit 0; Chisel build completed + successfully. +- `git diff --check` -> exit 0; no whitespace errors. diff --git a/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-9-report.md b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-9-report.md new file mode 100644 index 00000000..363b52bf --- /dev/null +++ b/.superpowers/sdd/2026-07-31-core-mainline-restructure/task-9-report.md @@ -0,0 +1,952 @@ +# Task 9 Report: Canonical ROB/BROB Commit and Recovery Owners + +## Result + +Task 9 added canonical `CoreParams`-based ROB, BROB, commit-control, and recovery-control owners without instantiating the legacy `Ooo*`, `rob`, `bctrl`, or recovery wrappers. Public OOORob/recovery interfaces now expose the compact exact-suffix recovery contract, commit/release payloads, and probe helpers used by downstream owners and tests. + +Final commit SHA: reported by `git rev-parse HEAD` after commit creation; the hash cannot be embedded self-referentially inside the same commit object. + +## Changed Files + +- `chisel/src/main/scala/linxcore/top/interface/OOORob.scala` - public ROB/BROB/commit/recovery payloads and `RecoveryPlanContract`. +- `chisel/src/main/scala/linxcore/ooo/ROB.scala` - canonical ROB owner with D3 prepare, semantic completion reporting, commit preview, release, and exact recovery apply. +- `chisel/src/main/scala/linxcore/ooo/BROB.scala` - canonical per-STID branch ROB owner with generation-checked release. +- `chisel/src/main/scala/linxcore/ooo/CommitControl.scala` - commit-control owner retaining releases until ROB, rename, and BROB acknowledgements complete. +- `chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala` - recovery-control owner with three-target identical-prepare barrier and abort handling. +- `chisel/src/main/scala/linxcore/top/interface/Identity.scala` - made `InterfaceWidth` available to public interface and OOO modules. +- `chisel/src/main/scala/linxcore/top/interface/Recovery.scala` - added compact exact-suffix fields to `RecoveryPlan`. +- `chisel/src/main/scala/linxcore/ooo/RENU.scala` - switched recovery equality to the shared contract helper so added fields cannot be ignored. +- `chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala` - RED-first commit/BROB/commit-control coverage. +- `chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala` - RED-first ROB recovery/recovery-control contract coverage. +- `docs/chisel/generated/top-interface-manifest.json` and `.md` - regenerated public interface manifest. +- `docs/spec/20-behavior/ooo.md`, `docs/spec/30-interfaces/commit.md`, `docs/spec/30-interfaces/recovery.md`, `docs/spec/50-verification/contract-spine.md` - Task 9 clauses and verification notes. +- `docs/superpowers/plans/2026-07-31-core-mainline-restructure.md` - Task 9 progress updated through implementation and verification. + +## RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` failed at compile because canonical `ROB`, `BROB`, `CommitControl`, and `RecoveryPlanContractProbe` did not exist. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed at compile because canonical `ROB`, `RecoveryControl`, and `RecoveryPlanContractProbe` did not exist. + +## Design Decisions + +- Completion handshakes are always consumed at ROB input; semantic acceptance or rejection is reported independently with `completionAccepted` and `completionRejected`. +- Branch recovery preserves the trigger and kills only younger members. Memory-order recovery kills the trigger and younger suffix. +- `RecoveryPlanContract.suffixMember` compares exact STID, slot, generation, and member ordinal; phase is the only ignored field in same-transaction recovery comparison. +- CommitControl holds one release transaction until ROB release, rename release, and BROB release acknowledgements all complete; trap release takes priority over interrupt release. +- The public interface manifest is generated from the new canonical public OOORob interfaces instead of hand-edited. + +## Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 5 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests after regenerating the manifest. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, manifest up to date. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. + +## Notes + +- Work-order wrappers `tools/chisel/check_interface_manifest.sh --update` and `tools/ndf/check_ndf.sh` were absent in this checkout. The equivalent available gates were `python3 tools/chisel/render_top_interface_manifest.py --check` and `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec`. +- A generated side-effect diff in `src/common/opcode_meta_gen.py` was restored before staging because it was unrelated to Task 9. + +## Fix Round 1 + +Review verdict `SPEC FAIL / CHANGES_REQUESTED` identified six HIGH findings plus controller blockers. This round added RED tests for the missing protocol surfaces and repaired the canonical Task-9 owners without wrapping legacy owners. + +### Fix-Round RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` failed at compile after RED tests because `D3RenameLane.blockStart/blockStop`, `CommitControlIO.robReleaseReady/renameReleaseReady/brobReleaseReady/interruptBoundaryValid`, `ROBIO.brobPrepared/releaseReady/releaseApply/ridHeadSlot`, and `BROBIO.releaseReady/recoveryPrepare.ready` did not exist. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed at compile after RED tests because `ROBIO.releaseApply/brobPrepared`, `RecoveryControlIO.robPrepared/interruptBoundaryValid/interruptBoundary`, and `RecoveryControl.robPrepare.valid` request semantics did not exist. + +### Fix-Round Repairs + +- Commit fire is now gated by side-effect-free ROB, RENU, and BROB release readiness; `CommitControl` retains the candidate and suppresses repeated fire while a `Valid` ROB preview remains asserted after the common fire. +- RENU exposes exact release readiness and mutates only when the common `releaseApply` input is asserted. Existing standalone RENU specs now drive `releaseApply=true`. +- ROB prepare validates continuous D3 shape, ROB-owned RID tail/generation, same-STID lanes, group/member order, free resident rows, and BROB prepared bindings. ROB release computes side-effect-free readiness for the whole prefix and mutates only on `releaseApply`. +- BROB uses typed `blockStart` and `blockStop`, records closed-block final ROB member identity, rejects release until the final member is present, and makes recovery prepare non-mutating with matching apply. +- RecoveryControl now retains producer events, arbitrates source 0/source 1/interrupt with trap priority, drives an explicit ROB prepare request, consumes the ROB-prepared plan, tracks per-target prepare-sent and matching-ack masks, ignores mismatched acknowledgements, and emits one common apply or non-mutating abort. +- Public decoded/D3 payloads now carry typed block start/stop facts. DEC maps legacy boundary sidecar start/stop and template `VFORM`/`FINAL` facts into those fields. +- Interface docs and NDF clauses were updated for side-effect-free readiness, typed block facts, exact release prefixes, and retained recovery request/barrier behavior. + +### Fix-Round Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 11 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 8 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - initially FAIL due stale generated manifest after new fields; PASS, 2 tests after `python3 tools/chisel/render_top_interface_manifest.py`. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS after the fix-round doc update, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. + +### Fix-Round Notes + +- `bash tools/chisel/run_chisel_tests.sh --only OooD3S1BrobIntegrationSpec` was run as an exploratory legacy D3/S1/BROB check and failed twice at `commitValid.expect(true.B)`. That spec instantiates legacy `OooBrob` and `OooS1GroupedRob`, not the canonical Task-9 owners. It is recorded here as a legacy non-gate observation and was not repaired in this Task-9 fix scope. +- `src/common/opcode_meta_gen.py` again acquired an unrelated generated side-effect diff during gates; it was restored before staging. + +## Fix Round 2 + +Review round 2 identified six HIGH blockers in the canonical owners. This +round added behavior RED tests against commit +`95126c0e290b04a36dec013dcf3128ff7ad514d6` and repaired only the Task-9 +canonical owner path. The legacy `OooD3S1BrobIntegration` path remains outside +this fix scope. + +### Fix-Round-2 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` failed + behaviorally after the new tests: zero-lane trap/interrupt transactions did + not assert `out.valid` without ordinary release readiness, and observing a + ROB preview made `releaseReady` true before any common commit-apply boundary. +- The initial nontrivial-bank RED test used an illegal W4/2 parameter profile + and failed during `CoreParams` validation; it was corrected to legal W2/2 + and W4/4 profiles while preserving unsupported-geometry coverage. + +### Fix-Round-2 Repairs + +- `CommitControl` now bypasses ordinary release readiness only for zero-lane + trap/interrupt transactions, so head traps and interrupt boundaries can fire + exactly once without fabricated owner releases. +- `ROB` exposes `commitApply` and mutates `Completed -> Retired`, + `orderCommitHead`, and `orderCommitCount` only on that common apply pulse. + A preview handshake remains side-effect-free. +- `ROB` storage is physically banked by `robBankCount` with bank/row helpers + and a divisible geometry guard. The tests cover legal 8/2 and 8/4 profiles + and an unsupported geometry. +- `ROB` recovery prepare derives killed members and killed groups from the + ordered live-member suffix, preserves the exact survivor tail, and recovery + apply invalidates the matching order suffix before repairing tail/count + state. +- `BROB` recovery apply uses an exact suffix kill mask, subtracts only the + killed blocks from `used`, preserves older blocks and unrelated STIDs, and + clears the current block only when that current block is killed. +- `RecoveryControl` no longer lets the `Exception` enum value outrank an older + event unless the exception event carries a precise trap. Its age key now + includes STID. + +### Fix-Round-2 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 14 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 12 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. + +### Fix-Round-2 Notes + +- `src/common/opcode_meta_gen.py` acquired the known unrelated generated + side-effect diff during gates; it was restored before staging. +- No `.ninja_lock` files were left in the worktree. + +## Fix Round 3 + +Review round 3 identified five HIGH blockers and one MEDIUM bank-coverage +blocker in the Task-9 canonical path. This round added behavior RED tests +against `01e8dc4b7c4da8a22df5fc0909c98ee69a2a5356`, then repaired the +canonical owners without touching legacy owners or Task 10. + +### Fix-Round-3 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` failed + behaviorally after the new tests: CommitControl suppressed a distinct second + preview while `rob.valid` stayed high, and ROB kept a retained two-entry + commit preview after recovery killed its suffix. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed + behaviorally after the new tests: BROB allowed release between recovery + prepare and apply, and RecoveryControl remained stuck on stale source 0 + instead of progressing with an eligible source 1. + +### Fix-Round-3 Repairs + +- Added public `RecoveryCandidateLookup` and `RecoveryCandidateStatus` Bundles + under `linxcore.top.interface`. +- ROB now answers candidate status with exact live/non-retired residency, + rejected state, synchronous head-trap proof, and a monotonically assigned + global allocation-age token. +- RecoveryControl selects only among matching eligible ROB statuses, discards + matching rejected statuses, and no longer derives global age from STID/RID. +- ROB recovery apply conservatively clears retained commit previews and repairs + commit-view count/head state for killed suffix entries. +- BROB recovery prepare retains an exact local action: full-block kill mask, + killed count, repaired used/tail/current state, and partial-current rewind + state. Prepare/release are blocked while the retained action is pending, and + apply uses only the retained action. +- CommitControl duplicate suppression is keyed to the accepted ROB/trap + identity, allowing a distinct next prefix while `rob.valid` remains asserted. +- Bank coverage now exercises 8/2 and 8/4 same-bank/different-row behavior, + stale completion rejection, occupied-slot rejection, wrap, and + resident-generation reuse. + +### Fix-Round-3 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 16 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. + +### Fix-Round-3 Notes + +- The known unrelated `src/common/opcode_meta_gen.py` generated side effect + was restored before staging. +- No `.ninja_lock` files were left in the worktree. + +## Fix Round 4 + +Review round 4 identified four HIGH blockers and one MEDIUM age-token blocker +in the canonical Task-9 path. This round added RED-first owner tests against +`a0fb4ea9254609fdd1a2364097e54597bd8b716e`, then repaired only canonical +Task-9 owners, public interfaces, tests, and docs. + +### Fix-Round-4 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` failed at + compile after the RED tests because `ROBIO.recoveryAbort` and + `BROBIO.recoveryAbort` did not exist. This covered the required ROB/BROB + abort-terminal contract before production IO was added. +- The same RED test patch added behavior cases for delayed and retained + RecoveryControl ROB status arbitration, interrupt holdoff behind unresolved + producers, stale/wrong-phase ROB apply rejection, duplicate apply + non-mutation, full CommitControl transaction-signature suppression, and an + unsafe recovery age-token width guard. The abort compile failure was the + first observed failing gate and masked later behavior tests on the unmodified + base. +- After the first repair exposed full-signature comparison, the added inactive + lane regression failed behaviorally in + `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec`: changing + only inactive lane payloads with the same active `count=1` produced + `out.valid=1` at `OOORobCommitSpec.scala:534`, proving inactive lanes were + not canonicalized. +- The same rerun proved the standalone age guard gap: unsafe + `RecoveryControl` elaboration did not throw at `OOORobCommitSpec.scala:791` + when only ROB enforced the token-width invariant. + +### Fix-Round-4 Repairs + +- Added explicit matching `recoveryAbort: Valid[RecoveryPlan]` inputs to + canonical ROB and BROB owner IOs. Matching abort clears only the retained + transaction/action and does not mutate resident tables, previews, counts, + head/tail, or generation state. +- ROB recovery apply now requires a retained pending transaction, `Apply` + phase, and exact transaction match; stale, duplicate, mismatched, or + wrong-phase apply is non-mutating. +- BROB retains the same exact apply gating and now has a matching abort + terminal for retained local recovery actions. +- RecoveryControl now snapshots the complete producer contender set for an + arbitration boundary, retains per-source matching eligible/rejected status, + waits for every active producer to resolve, retains pulsed early statuses, + and admits interrupts only after unresolved producers are resolved. Fully + resolved same-cycle contender sets still take the fast path. +- CommitControl duplicate suppression now compares the complete accepted + canonical `CommitControlTxn` structural signature rather than a single ROB + identity. Inactive lanes are zeroed before signature comparison, while + expanded prefixes, changed trap cause/kind, and ordinary/trap transitions + are accepted exactly once. +- Added public `RecoveryAge` helper/invariant beside the candidate-status + contract. ROB and standalone RecoveryControl reject configurations whose age + token space is not more than twice the global live ROB-member window + (`stidCount * robCapacityPerStid`), and RecoveryControl uses the wrap-safe + modular older relation. + +### Fix-Round-4 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. + +### Fix-Round-4 Notes + +- Work-order wrappers `tools/chisel/check_interface_manifest.sh` and + `tools/ndf/check_ndf.sh` are absent in this checkout; the equivalent + available gates were `python3 tools/chisel/render_top_interface_manifest.py + --check` and `python3 tools/spec/check_ndf_profile.py + --verify-local-references docs/spec`. +- The known unrelated `src/common/opcode_meta_gen.py` generated side effect + was restored before staging. +- No `.ninja_lock` files were left in the worktree. +- `skill-evolve: no-update` - round 4 did not add a reusable LinxCore workflow + invariant beyond the Task-9 spec/docs changes already recorded. + +## Fix Round 5 + +Review round 5 identified two remaining HIGH blockers in the canonical +Task-9 recovery terminal protocol. This round added RED-first tests against +`0ccbd2d5a29444870998ca4754361f634c4c2d74`, then repaired only canonical +Task-9 recovery source, tests, and docs. + +### Fix-Round-5 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed at + compile after the RED tests because `RecoveryControlIO.robAbort` did not + exist. This proved the missing exact ROB request-abort terminal before + production IO was added. +- The same RED patch added behavior cases for abort before `robPrepare.fire`, + abort after `robPrepare.fire` while waiting for `robPrepared`, final target + acknowledgement with same-cycle abort, abort during visible Apply, and + simultaneous matching Apply/Abort on ROB and BROB. +- After adding the IO and first production repair, the owner spec exposed + test/setup and behavior timing gaps: the old retained-abort test had not + actually reached target-prepare state, the new event helper mismatched ROB + status `peId`, and the round-5 regressions then passed after the fixtures + targeted the intended protocol phases. + +### Fix-Round-5 Repairs + +- `RecoveryControlIO` now exposes `robAbort: Valid[RecoveryPlan]` for the ROB + request side of the recovery protocol. +- Abort in `RequestRob` before `robPrepare.fire` cancels locally with no ROB + or target terminal. Abort after `robPrepare.fire` but before + `robPrepared.fire` moves to a retained wait state, accepts only the exact + ROB response, and emits the matching ROB abort without broadcasting a + default or stale target plan. +- Abort after the ROB-authored plan is retained emits the exact retained plan + to target abort ports and the ROB abort port exactly once. Abort coincident + with the final target acknowledgement has non-mutating priority over Apply, + while abort during an already visible Apply is ignored for that committed + plan. +- ROB and BROB standalone terminal arbitration now gate suffix mutation with + `!recoveryAbortHit`; simultaneous matching Apply and Abort clears the + retained transaction through Abort without mutating resident state. +- Recovery interface and OOO behavior docs now describe the request-side ROB + abort terminal, abort priority at target-prepare completion, visible-Apply + irrevocability, and fail-closed simultaneous terminal behavior. + +### Fix-Round-5 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 27 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. + +### Fix-Round-5 Notes + +- `python3 tools/chisel/render_top_interface_manifest.py` was run after adding + `robAbort`; the emitted top-interface manifest had no diff because + `RecoveryControlIO` is not part of that manifest surface. +- Work-order wrappers `tools/chisel/check_interface_manifest.sh` and + `tools/ndf/check_ndf.sh` remain absent in this checkout; equivalent gates + were run as listed above. +- `skill-evolve: no-update` - round 5 did not add a reusable LinxCore workflow + invariant beyond the Task-9 recovery contract/docs changes. + +## Fix Round 6 + +Review round 6 identified one remaining HIGH blocker in the canonical +Task-9 recovery request/response protocol. This round added RED-first tests +against `da5e8500c55f4edbae73ed8f807006fe7172dc65`, then repaired only +canonical Task-9 recovery interfaces/control, tests, docs, and this report. + +### Fix-Round-6 RED Evidence + +- The first RED attempt in + `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed before + the intended point because the new seed event fixture set trigger fields not + mirrored by the existing candidate-status helper. The fixture was corrected + before production edits. +- The corrected RED run failed behaviorally in the new round-6 tests: + unsolicited `robPrepared` before `robPrepare.fire` consumed the request path + and cleared `robPrepare.valid`; a mismatched `WaitRob` response entered + target prepare; and a mismatched `WaitRobAbort` response emitted `robAbort`. + The failures were observed at `OOORecoverySpec.scala:1166`, + `OOORecoverySpec.scala:1217`, and `OOORecoverySpec.scala:1265`. + +### Fix-Round-6 Repairs + +- Added public `RecoveryPlanContract.sameRobRequest`, which requires Prepare + phase plus matching transaction ID, cause, full trigger identity, redirect + PC, and new epoch while deliberately ignoring only the ROB-authored + survivor-tail and killed-suffix fields. +- `RecoveryControl` now retains the exact seed request when + `robPrepare.fire` occurs. In `RequestRob`, a response is accepted only when + it correlates to the same fired seed in the same cycle; an unsolicited or + mismatched response no longer consumes the request or prevents the request + from firing once. +- In `WaitRob` and `WaitRobAbort`, `robPrepared` is accepted only when it + correlates with the retained request. Stale, unrelated, wrong-phase, and + mismatched responses do not overwrite the retained plan, enter target + prepare, or emit `robAbort`. +- The round-6 tests cover wrong transaction ID, cause, trigger PE/STID/RID + slot/RID generation/member/resident generation/BID/BROB generation, + redirect PC, new epoch, and phase in both non-abort and abort-pending wait + states, plus matching progress with different ROB-authored suffix fields. +- Recovery behavior and interface docs now describe request correlation and + the exact set of fields ignored from ROB-authored responses. + +### Fix-Round-6 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, 30 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. + +### Fix-Round-6 Notes + +- `RecoveryPlanContract.sameRobRequest` is a public helper only; no public + Bundle shape changed, and the manifest check remained up to date. +- Work-order wrappers `tools/chisel/check_interface_manifest.sh` and + `tools/ndf/check_ndf.sh` remain absent in this checkout; equivalent gates + were run as listed above. +- `skill-evolve: no-update` - round 6 did not add a reusable LinxCore workflow + invariant beyond the Task-9 recovery contract/docs changes. + +## Fix Round 7 + +Review round 7 identified one remaining HIGH blocker in the canonical +Task-9 recovery request/response Decoupled protocol. This round added +RED-first legal-stability tests against +`64b54afb5f2250a33adb396448121588ad043b84`, then repaired only canonical +Task-9 RecoveryControl, recovery tests, docs, and this report. + +### Fix-Round-7 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed + behaviorally after the RED tests because a stable same-cycle mismatched + `robPrepared` response saw `ready=0` while `robPrepare.fire` was possible, + at `OOORecoverySpec.scala:1207`. +- The same RED run failed for stable mismatched `WaitRob` and `WaitRobAbort` + responses at the shared helper assertion `OOORecoverySpec.scala:258`, + proving mismatches were permanently backpressured instead of legally + drained. + +### Fix-Round-7 Repairs + +- `RecoveryControl` now splits ROB response channel fire from semantic + correlated acceptance. `robPrepared.ready` is asserted in legal response + windows independent of request-identity match, while only + `robPrepared.fire && sameRobRequest(...)` may load the retained plan, + enter target prepare, emit the ROB abort terminal, or clear abort-pending + state. +- A same-cycle mismatched response with `robPrepare.fire` is drained while the + request is retained and the controller moves to `WaitRob` without reissuing. + Mismatches in `WaitRob` and `WaitRobAbort` fire legally and leave recovery + state unchanged until a later correlated response arrives. +- The round-6 mismatch tests now hold `robPrepared.valid` and `bits` stable + until `ready` is observed before presenting the next response. +- Recovery behavior and interface docs now state that mismatched ROB responses + in a legal response window are drained from Decoupled without semantic + acceptance. + +### Fix-Round-7 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 31 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, + 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, + 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; + `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; + `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS + 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; + `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. + +### Fix-Round-7 Notes + +- The known unrelated `src/common/opcode_meta_gen.py` generated side effect + was restored before staging. +- No `.ninja_lock` files were left in the worktree. +- `skill-evolve: no-update` - round 7 did not add a reusable LinxCore workflow + invariant beyond the Task-9 recovery Decoupled contract/docs changes. + +## Fix Round 8 + +Review round 8 identified one remaining HIGH blocker in the canonical +Task-9 recovery request/response Decoupled protocol. This round added +RED-first stable pre-request response tests against +`f46c6a44a7912350ee8d29e96a1c5c5cdec3628f`, then repaired only canonical +Task-9 RecoveryControl, recovery tests, docs, and this report. + +### Fix-Round-8 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed + behaviorally after the RED tests because the stable pre-request + `robPrepared` response saw `ready=0` at the bounded helper assertion + `OOORecoverySpec.scala:258`. +- The same RED run failed for the abort-before-request held response at the + same bounded helper assertion, proving the beat could not legally drain + without being withdrawn or changed by the producer. + +### Fix-Round-8 Repairs + +- `RecoveryControl` now drains `robPrepared` beats in no-request states, + `RequestRob`, `WaitRob`, and `WaitRobAbort`, while semantic acceptance still + requires either same-cycle `robPrepare.fire` plus `sameRobRequest(...)` or a + retained wait-state correlated response. +- A response held before `robPrepare.fire` drains as stale and cannot become + the later request's ROB-authored plan, even if its fields match that seed. + If abort suppresses the request, the held beat drains without any target + prepare, ROB abort, state advance, or association with a later request. +- The stable response helper now uses a bounded wait while holding + `robPrepared.valid` and `bits` unchanged, so future tests cannot silently + withdraw or mutate an unaccepted Decoupled beat. +- Recovery behavior and interface docs now distinguish pre-request drain from + later legal response-window semantic acceptance. + +### Fix-Round-8 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 32 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, + 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, + 7 tests. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; + `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; + `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS + 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; + `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `git diff --check` - PASS. +- Forbidden external-reference scan over `docs/spec` and this report - PASS, + no matches. + +### Fix-Round-8 Notes + +- The known unrelated `src/common/opcode_meta_gen.py` generated side effect + was restored before staging. +- No `.ninja_lock` files were left in the worktree. +- `skill-evolve: no-update` - round 8 did not add a reusable LinxCore workflow + invariant beyond the Task-9 recovery Decoupled contract/docs changes. + +## Fix Round 9 + +Review round 9 identified one remaining HIGH blocker in canonical `BROB` +recovery. A closed block could straddle the recovery suffix, with its first +member surviving and its recorded last member killed, but the retained BROB +action only shortened open current blocks. This round added RED-first +closed-block straddling coverage against +`c92ff9e8ab73afb046d065d3a11c1b911de3c2f1`, then repaired only canonical +`BROB`, affected recovery tests, docs, and this report. + +### Fix-Round-9 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed + behaviorally after the RED test: + `BROB recovery shortens a closed block that straddles the killed suffix`. + The next allocation reused BID `0` where the survivor block still owned BID + `0`, failing at `OOORecoverySpec.scala:645` with expected BID `1`. +- RED run summary: 33 tests run, 32 passed, 1 failed. + +### Fix-Round-9 Repairs + +- `BROB` recovery prepare now detects any valid target-STID block whose first + member survives and whose recorded last member lies in the compact killed + suffix, whether the block is closed or currently open. +- The retained recovery action preserves the exact straddling BID/generation, + preserves `used`, tail, and generation state for the live block, and on + matching Apply shortens only `tableLastRob` to the ROB-authored surviving + tail. Whole blocks whose first member is killed are still invalidated and + counted as killed. +- Abort remains non-mutating for a prepared straddling closed block; matching + abort clears the retained transaction and leaves the original two-member + release ready. +- Behavior and interface docs now state the owner-local straddling-block + contract for compact suffix recovery. + +### Fix-Round-9 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 34 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - + PASS, 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, + 7 tests. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; + `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; + `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS + 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; + `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. + +### Fix-Round-9 Notes + +- `skill-evolve: no-update` - round 9 did not add a reusable LinxCore + workflow invariant beyond the Task-9 BROB compact-suffix recovery contract. + +## Fix Round 10 + +Review round 10 identified three remaining HIGH blockers in canonical Task-9 +BROB recovery and parameter validation. This round added RED-first coverage +against `ae2fb07144368a70b3aa1c83fd90fff8a0773085`, then repaired only +canonical `BROB`, central parameter validation, affected tests, docs, and this +report. + +### Fix-Round-10 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec` failed + after the singleton-BROB RED test because `brobEntriesPerStid = 1` threw no + configuration error at `CoreConfigurationSpec.scala:90`. RED summary: + 13 tests run, 12 passed, 1 failed. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed after + the BROB RED tests in four places: + - non-wrap closed straddler plus a wholly killed younger block selected BID + `2` instead of expected BID `1` at `OOORecoverySpec.scala:705`; + - wrapped closed straddler selected BID `1` instead of expected BID `0` at + `OOORecoverySpec.scala:790`; + - malformed first/last BID or generation plans still reported + `recoveryPrepare.ready = 1` at `OOORecoverySpec.scala:939`; + - stale reused-BID last generation after wrap still reported + `recoveryPrepare.ready = 1` at `OOORecoverySpec.scala:1035`. + RED summary: 38 tests run, 34 passed, 4 failed. + +### Fix-Round-10 Repairs + +- `BROB` recovery prepare now validates the compact suffix against the exact + live local projection before asserting ready: legal suffix shape, target + STID, endpoint BID/generation, stored endpoint ROB identities, and selected + whole-kill or straddling entry identity. +- Straddling-block recovery now restores the next-free tail to the modulo + successor of the retained straddling BID and increments generation exactly + when that successor wraps. Whole killed younger blocks are removed from + `used` and become reachable allocation slots without selecting the live + survivor slot. +- Same-prefix publication now records `tableLastRob` for a block opened earlier + in the same D3 prefix, preserving the existing open-current partial recovery + behavior under the stricter endpoint validation. +- `ParamChecks` now rejects singleton BROB rings centrally so native BID width + remains nonzero. `CoreConfigurationSpec` covers the rejection, a legal + 4-entry ring, and the default 256-entry ring. +- Behavior, recovery-interface, and parameter docs now state exact BROB suffix + validation, straddler successor-tail repair, and the non-singleton BROB + parameter contract. + +### Fix-Round-10 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec` - PASS, + 13 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 38 tests. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, + 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. An earlier parallel attempt collided + with an sbt boot socket; the sequential rerun passed. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` - PASS, 15 tests. +- `bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec` - PASS, + 7 tests. +- Affected decode/D1-D3/config checks: `OOODecodeSpec` PASS 8 tests; + `OooD1DecodeSpec` PASS 12 tests; `OooD2GroupPlannerSpec` PASS 6 tests; + `OooD2StageSpec` PASS 3 tests; `OooD3ReservationAllocatorSpec` PASS + 9 tests; `OooD3S1GroupedRobIntegrationSpec` PASS 1 test; + `OooParamsSpec` PASS 4 tests; `OooIexPhysicalProfileSpec` PASS 3 tests. +- `bash tests/test_rob_bookkeeping.sh` - PASS, `rob bookkeeping test: ok`. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. +- `bash tests/test_chisel_architecture_adapter.sh` - PASS, + `ok: Chisel architecture evidence adapter passed`. +- `python3 tools/generate/lint_stage_spec_ownership.py` - PASS, + `stage spec ownership lint passed`. +- `python3 tools/generate/lint_engine_ownership.py` - PASS, + `engine ownership lint passed`. + +### Fix-Round-10 Notes + +- `skill-evolve: no-update` - round 10 added Task-9-specific compact-suffix + BROB recovery detail and a central parameter guard already captured by the + local docs and existing LinxCore BID guidance; no reusable skill edit was in + scope. + +## Fix Round 11 + +Review round 11 identified two HIGH blockers in canonical Task-9 ownership: +`BROB` stored raw D3 ROB identities after computing allocator-bound +BID/generation values, leaving resident generation and BROB identity fields +unbound for later release/recovery checks; and `RecoveryControl` let stale or +wrong-phase target `prepared` beats satisfy the target acknowledgement barrier +before the corresponding target Prepare request had fired. The fix scope stayed +within canonical `BROB`, `RecoveryControl`, directly affected tests, behavior +and recovery-interface docs, and this report. + +### Fix-Round-11 RED Evidence + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` failed after + the RED tests with 41 tests run, 38 passed, 3 failed: + - `BROB publishes allocator-bound identities when D3 residency is unbound` + observed `releaseReady = 0` after recovery even though the bound survivor + endpoint was live. + - `RecoveryControl ignores target acknowledgements before prepare fires` + observed `apply.valid = 1` before the target Prepare request fired. + - `RecoveryControl does not carry stale target acknowledgements across abort + retry` initially exposed a stale-ack retry gap, then was narrowed to a + corrected retry trigger after the RTL fixes showed the remaining failure was + in the test harness setup. + +### Fix-Round-11 Repairs + +- `BROB` now receives the ROB-prepared publication row explicitly, validates + every active lane against the raw D3 PE/STID/RID/member fields and the + BROB-prepared BID/BROB generation, and stores the bound ROB identity in the + block table. Publication backpressures instead of recording unbound D3 + BID/BROB/resident defaults. +- `RecoveryControl` now counts a target acknowledgement only when the target + `prepared` beat fires in `Prepare` phase, the retained transaction matches, + and that target's Prepare request already fired or fires in the same cycle. + Stale, pre-prepare, wrong-phase, and mismatched target beats continue to + drain without setting the acknowledgement mask. +- `OOORecoverySpec` covers unbound D3 residency with ROB-prepared BROB + publication identities, pre-prepare target acknowledgement rejection, + wrong-phase target acknowledgement rejection, and stale acknowledgement + isolation across an abort/retry. `OOORobCommitSpec` standalone BROB tests now + publish through the same ROB-prepared binding helper. +- Behavior and recovery-interface docs now state the ROB-prepared BROB + publication authority and causal target acknowledgement contract. + +### Fix-Round-11 Verification + +- RED baseline: `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` + - FAIL, 41 tests, 38 passed, 3 failed before the round-11 repairs. +- `source tools/chisel/chisel_env.sh && cd chisel && sbt --server --batch --no-colors --mem "${LINX_CHISEL_SBT_MEM_MB}" 'testOnly linxcore.ooo.OOORecoverySpec -- -z stale'` + - PASS, 3 tests, including the stale target-ack retry regression after the + final test-only trigger correction. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, + 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 ROBID tests. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS. + +The latest full `OOORecoverySpec` rerun after the RTL fixes reached 40/41 +passing with only the retry-harness trigger mismatch remaining. After the +test-only correction, the narrowed stale subset passed; the full +`OOORecoverySpec` was not rerun again per the round-11 instruction to avoid +another full rerun without RTL changes. + +### Fix-Round-11 Notes + +- `skill-evolve: no-update` - round 11 reinforced existing LinxCore identity + and recovery sequencing invariants already captured in the domain skill: + BROB table authority comes from the ROB-prepared exact identity, and recovery + barriers must be causally tied to owner prepare ownership. No reusable skill + update was required. + +## Fix Round 12 + +Review round 12 found two HIGH blockers left by round 11. Canonical ROB stamped +BROB BID/generation only when the incoming D3 row already asserted +`brobBound`, although the real OOO D3 producer deliberately publishes unbound +rows. The standalone BROB test fabricated `robPrepared`, so it did not expose +the resulting first-nonzero-BID backpressure. RecoveryControl also accepted +target prepared beats only in `PrepareTargets`; a matching beat held before +that state could remain valid and be counted on entry or after an abort/retry. + +### Fix-Round-12 RED Evidence + +- The real ROB/BROB coordinator test first failed behaviorally with + `prepare.ready = 0` on an unbound D3 publication. After repairing test-only + compile/literal issues, the RED was observed at + `OOORecoverySpec.scala:1373` before RTL changes. +- The held-target regression failed behaviorally with `apply.valid = 1` where + no causal target acknowledgement had occurred, at the then-current + `OOORecoverySpec.scala:1835`. +- A final bound-residency negative test observed `prepare.ready = 1` for a D3 + row with `residentBound = true` and a stale resident generation. The focused + malformed-binding test turned RED before the ROB validation was added. +- The first full-suite rerun correctly exposed seven old standalone ROB cases + whose fixtures did not provide any BROB binding. After adding explicit + binding, six cases still exposed a fixture error that assigned different + BIDs to different ROB groups inside one block. The fixture now follows the + real BROB rule: only `blockStart` allocates a new BID; later lanes retain the + block binding. + +### Fix-Round-12 Repairs + +- ROB now validates `BROBPrepared` for every active lane, independent of raw + `brobBound`, and stamps allocator-authored BID/BROB generation plus + ROB-owned resident generation into every prepared identity. Count, + active/inactive lane validity, STID, allocation marker, already-bound raw + BID/generation, already-bound resident generation, and same-block continuity + mismatches all backpressure before the common publication fire. +- The focused coordinator wires the real `BROB.prepared -> ROB.brobPrepared` + and `ROB.prepared -> BROB.robPrepared` graph. It proves BID 0/1/2/3, + same-packet first/last members, BID3-to-BID0 generation wrap, resident + generation reuse, commit/release, and compact suffix recovery without a + fabricated ROB-prepared helper. +- RecoveryControl now keeps every target `prepared.ready` open so stale or + early Decoupled beats drain in all states. An acknowledgement can set its + mask only while the controller is already in `PrepareTargets`, after or in + the same cycle as the corresponding target Prepare fire, and with exact + transaction/phase equality. +- The same-DUT abort/retry regression holds a matching target beat before + Prepare, proves it drains without acknowledgement, aborts, retries the same + transaction identity, and requires a fresh causal target response before + Apply. +- Behavior and recovery-interface NDF clauses now state both contracts. + +### Fix-Round-12 Verification + +- `bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec` - PASS, + 43 tests in 3 minutes 41 seconds. +- `bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec` - PASS, + 21 tests in 3 minutes 46 seconds after the final bound-resident-generation + validation. +- Focused RED-to-GREEN filters for coordinator publication, held drain, + suffix, member, and apply/abort behavior all pass. +- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` - PASS, + `ROBID semantic check: ok`, 3 tests. +- `bash tools/chisel/run_chisel_brob_order_state_probe.sh` - PASS, + `brob-order-state-probe: PASS`. +- `bash tests/test_rob_bookkeeping.sh` - PASS, + `rob bookkeeping ok: commits=4623`. +- `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` - PASS, + 9 tests. +- `bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec` - PASS, + 2 tests. +- `python3 tools/chisel/render_top_interface_manifest.py --check` - PASS, + `top-interface-manifest: up to date`. +- `python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec` + - PASS, `clauses=113 l1_must=52 verified=59 open_questions=0 references=2`. +- Forbidden external-narrative scan under `docs/spec` - PASS, no matches. +- `bash tools/chisel/build_chisel.sh` - PASS. +- `bash tools/chisel/run_chisel_verilator_lint.sh` - PASS with Verilator 5.044. +- `bash tests/test_chisel_architecture_adapter.sh` - PASS. +- `python3 tools/generate/lint_stage_spec_ownership.py` - PASS, + 39 trace stages and 37 canonical coordinates. +- `python3 tools/generate/lint_engine_ownership.py` - PASS. +- `git diff --check` - PASS. + +### Fix-Round-12 Notes + +- Independent review initially found one HIGH test-strength blocker: the held + target beat helper adapted to `prepared.ready` instead of asserting the + outside-`PrepareTargets` drain contract. The helper now requires ready before + the transition, steps the exact drain, and unconditionally withdraws the + consumed beat. The focused drain subset passes 3/3, and re-review reports + zero remaining findings with verdict `APPROVE`. +- The standard build again removed the generated `xb` opcode row as an + unrelated side effect; the row was restored before staging. +- `skill-evolve: no-update` - round 12 applies existing exact-identity, + allocator-authority, causal-handshake, and retained-Decoupled rules already + present in the LinxCore domain skill. No reusable workflow invariant changed. diff --git a/AGENTS.md b/AGENTS.md new file mode 100644 index 00000000..0d5a406c --- /dev/null +++ b/AGENTS.md @@ -0,0 +1,27 @@ +# LinxCore Agent Bootstrap + +This repository uses the pinned Superpowers workflow under +`tools/superpowers` together with the LinxCore domain skill. + +At the start of every agent session, before responding or taking an action: + +1. Read `tools/superpowers/skills/using-superpowers/SKILL.md` completely. +2. Follow its platform guidance in + `tools/superpowers/skills/using-superpowers/references/codex-tools.md` when + running under Codex. +3. Invoke every applicable Superpowers process skill before implementation. +4. For Chisel/LinxCore work, also invoke the installed `linx-core` domain + skill. Its ownership, identity, verification, cross-model, and + superproject-pin gates remain authoritative for hardware acceptance. + +Direct user instructions and parent-repository instructions take precedence. +Do not edit the vendored Superpowers checkout in a LinxCore change. Update it +only by changing the pinned submodule revision and recording the upstream +release in `docs/flows/superpowers.md`. + +If the submodule is not initialized, report that fact and continue with the +available LinxCore workflow; initialize it with: + +```bash +git submodule update --init --recursive tools/superpowers +``` diff --git a/README.md b/README.md index 9f013df4..13d4e363 100644 --- a/README.md +++ b/README.md @@ -16,6 +16,7 @@ Run from `/Users/zhoubot/linx-isa/rtl/LinxCore`. ```bash +bash tools/setup_superpowers.sh cmake -S . -B build cmake --build build -j"$(sysctl -n hw.ncpu 2>/dev/null || nproc)" @@ -34,4 +35,6 @@ bash tests/test_trace_schema_and_mem.sh - `/Users/zhoubot/linx-isa/docs/bringup/` - `/Users/zhoubot/linx-isa/docs/bringup/contracts/trace_schema.md` - `docs/chisel/integrated-development-flow.md` +- `docs/chisel/microarchitecture-cross-stack-audit.md` - `docs/chisel/modules/recovery/RecoveryFabric.md` +- `docs/flows/superpowers.md` diff --git a/chisel/build.sbt b/chisel/build.sbt index fcdd2810..c035c487 100644 --- a/chisel/build.sbt +++ b/chisel/build.sbt @@ -2,6 +2,12 @@ ThisBuild / scalaVersion := "2.13.17" ThisBuild / organization := "org.linxisa" val chiselVersion = "7.3.0" +val chiselTestJobs = sys.env.get("LINX_CHISEL_TEST_JOBS") match { + case None => 2 + case Some(text) => + text.toIntOption.filter(_ > 0).getOrElse( + sys.error("LINX_CHISEL_TEST_JOBS must be a positive integer")) +} lazy val linxcore = (project in file(".")) .settings( @@ -18,5 +24,7 @@ lazy val linxcore = (project in file(".")) "-feature", "-unchecked", "-Xfatal-warnings" - ) + ), + Test / parallelExecution := true, + Global / concurrentRestrictions += Tags.limit(Tags.Test, chiselTestJobs) ) diff --git a/chisel/src/main/scala/linxcore/backend/ReducedRobCompletionArbiter.scala b/chisel/src/main/scala/linxcore/backend/ReducedRobCompletionArbiter.scala deleted file mode 100644 index edae4f4a..00000000 --- a/chisel/src/main/scala/linxcore/backend/ReducedRobCompletionArbiter.scala +++ /dev/null @@ -1,159 +0,0 @@ -package linxcore.backend - -import chisel3._ -import chisel3.util.Cat - -import linxcore.commit.{CommitTraceParams, CommitTraceRow} - -class ReducedRobCompletionArbiterIO( - val ptrWidth: Int, - val traceParams: CommitTraceParams = CommitTraceParams()) - extends Bundle { - val executeCompleteValid = Input(Bool()) - val executeCompleteRobValue = Input(UInt(ptrWidth.W)) - val executeCompleteRowValid = Input(Bool()) - val executeCompleteRow = Input(new CommitTraceRow(traceParams)) - - val replayCompleteValid = Input(Bool()) - val replayCompleteRobValue = Input(UInt(ptrWidth.W)) - val replayCompleteRowValid = Input(Bool()) - val replayCompleteRow = Input(new CommitTraceRow(traceParams)) - - val serviceCompleteValid = Input(Bool()) - val serviceCompleteRobValue = Input(UInt(ptrWidth.W)) - val serviceCompleteRowValid = Input(Bool()) - val serviceCompleteRow = Input(new CommitTraceRow(traceParams)) - - val templateCompleteValid = Input(Bool()) - val templateCompleteRobValue = Input(UInt(ptrWidth.W)) - val templateCompleteRowValid = Input(Bool()) - val templateCompleteRow = Input(new CommitTraceRow(traceParams)) - val templateCompleteParentSlot = Input(UInt(ptrWidth.W)) - - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(ptrWidth.W)) - val completeRowValid = Output(Bool()) - val completeRow = Output(new CommitTraceRow(traceParams)) - val selectedExecute = Output(Bool()) - val selectedReplay = Output(Bool()) - val selectedService = Output(Bool()) - val selectedTemplate = Output(Bool()) - val selectedSourceMask = Output(UInt(4.W)) - val replayBlockedByExecute = Output(Bool()) - val serviceBlockedByExecute = Output(Bool()) - val serviceBlockedByReplay = Output(Bool()) - val templateBlockedByExecute = Output(Bool()) - val templateBlockedByReplay = Output(Bool()) - val completionContended = Output(Bool()) - val sameRobCompletionContention = Output(Bool()) - val differentRobCompletionContention = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ReducedRobCompletionArbiter( - val ptrWidth: Int, - val traceParams: CommitTraceParams = CommitTraceParams(), - val robEntries: Int = -1) - extends Module { - require(ptrWidth > 0, "ptrWidth must be positive") - private val effectiveRobEntries = if (robEntries < 0) 1 << ptrWidth else robEntries - require(effectiveRobEntries > 0, "robEntries must be positive") - require(effectiveRobEntries <= (1 << ptrWidth), "robEntries must fit in ptrWidth") - - val io = IO(new ReducedRobCompletionArbiterIO(ptrWidth, traceParams)) - - private val executeRidInvalid = io.executeCompleteValid && - (io.executeCompleteRobValue >= effectiveRobEntries.U) - private val replayRidInvalid = io.replayCompleteValid && - (io.replayCompleteRobValue >= effectiveRobEntries.U) - private val serviceRidInvalid = io.serviceCompleteValid && - (io.serviceCompleteRobValue >= effectiveRobEntries.U) - private val templateRidInvalid = io.templateCompleteValid && - (io.templateCompleteRobValue >= effectiveRobEntries.U) - - private val executeCandidate = io.executeCompleteValid && !executeRidInvalid - private val replayCandidate = io.replayCompleteValid && !replayRidInvalid - private val serviceCandidate = io.serviceCompleteValid && !serviceRidInvalid - private val templateCandidate = io.templateCompleteValid && !templateRidInvalid - - val selectedExecute = executeCandidate - val selectedReplay = replayCandidate && !executeCandidate - val selectedService = serviceCandidate && !executeCandidate && !replayCandidate - val selectedTemplate = - templateCandidate && !executeCandidate && !replayCandidate && !serviceCandidate - - io.selectedExecute := selectedExecute - io.selectedReplay := selectedReplay - io.selectedService := selectedService - io.selectedTemplate := selectedTemplate - io.selectedSourceMask := - Cat(selectedTemplate, selectedService, selectedReplay, selectedExecute) - io.replayBlockedByExecute := io.replayCompleteValid && io.executeCompleteValid - io.serviceBlockedByExecute := io.serviceCompleteValid && io.executeCompleteValid - io.serviceBlockedByReplay := - io.serviceCompleteValid && !io.executeCompleteValid && io.replayCompleteValid - io.templateBlockedByExecute := io.templateCompleteValid && io.executeCompleteValid - io.templateBlockedByReplay := - io.templateCompleteValid && !io.executeCompleteValid && io.replayCompleteValid - io.completeValid := selectedExecute || selectedReplay || selectedService || selectedTemplate - io.completeRobValue := Mux( - selectedExecute, - io.executeCompleteRobValue, - Mux( - selectedReplay, - io.replayCompleteRobValue, - Mux( - selectedService, - io.serviceCompleteRobValue, - Mux(selectedTemplate, io.templateCompleteRobValue, 0.U)))) - io.completeRowValid := Mux( - selectedExecute, - io.executeCompleteRowValid, - Mux( - selectedReplay, - io.replayCompleteRowValid, - Mux(selectedService, io.serviceCompleteRowValid, Mux(selectedTemplate, io.templateCompleteRowValid, false.B)))) - io.completeRow := Mux( - selectedExecute, - io.executeCompleteRow, - Mux( - selectedReplay, - io.replayCompleteRow, - Mux( - selectedService, - io.serviceCompleteRow, - Mux( - selectedTemplate, - io.templateCompleteRow, - 0.U.asTypeOf(new CommitTraceRow(traceParams)))))) - - private val executeReplayContend = io.executeCompleteValid && io.replayCompleteValid - private val executeServiceContend = io.executeCompleteValid && io.serviceCompleteValid - private val replayServiceContend = io.replayCompleteValid && io.serviceCompleteValid - private val executeTemplateContend = io.executeCompleteValid && io.templateCompleteValid - private val replayTemplateContend = io.replayCompleteValid && io.templateCompleteValid - private val serviceTemplateContend = io.serviceCompleteValid && io.templateCompleteValid - private val anyContention = - executeReplayContend || executeServiceContend || replayServiceContend || - executeTemplateContend || replayTemplateContend || serviceTemplateContend - private val differentRidContention = - (executeReplayContend && (io.executeCompleteRobValue =/= io.replayCompleteRobValue)) || - (executeServiceContend && (io.executeCompleteRobValue =/= io.serviceCompleteRobValue)) || - (replayServiceContend && (io.replayCompleteRobValue =/= io.serviceCompleteRobValue)) || - (executeTemplateContend && (io.executeCompleteRobValue =/= io.templateCompleteRobValue)) || - (replayTemplateContend && (io.replayCompleteRobValue =/= io.templateCompleteRobValue)) || - (serviceTemplateContend && (io.serviceCompleteRobValue =/= io.templateCompleteRobValue)) - private val invalidRid = - executeRidInvalid || replayRidInvalid || serviceRidInvalid || templateRidInvalid - - io.completionContended := anyContention - io.sameRobCompletionContention := anyContention && !differentRidContention - io.differentRobCompletionContention := differentRidContention - io.protocolError := invalidRid || differentRidContention - - when(io.templateCompleteValid) { - assert( - io.templateCompleteParentSlot === io.templateCompleteRobValue, - "template completion parent slot must match its slot-valued completion payload") - } -} diff --git a/chisel/src/main/scala/linxcore/common/CoreParams.scala b/chisel/src/main/scala/linxcore/common/CoreParams.scala index ffd213f8..bd8575ea 100644 --- a/chisel/src/main/scala/linxcore/common/CoreParams.scala +++ b/chisel/src/main/scala/linxcore/common/CoreParams.scala @@ -11,6 +11,55 @@ final case class CoreParams( require((robEntries & (robEntries - 1)) == 0, "robEntries must be a power of two") require(commitWidth > 0, "commitWidth must be positive") require(lsidWidth >= 32, "lsidWidth must preserve the Linx 32-bit memory-order contract") + + /** Temporary value-only bridge into the centralized parameter hierarchy. + * + * This preserves legacy sizing where an equivalent field exists. It owns no + * hardware state and is removed with the old top chain. + */ + def toMainline(profileWidth: Int = 4): linxcore.params.CoreParams = { + val base = linxcore.params.ParamProfiles.forWidth(profileWidth) + base.copy( + widths = base.widths.copy(retireWidth = commitWidth), + ooo = base.ooo.copy( + stidCount = scalarLsu.stidCount, + retireWidth = commitWidth, + robGroupsPerStid = robEntries, + maxInstructionsPerRobGroup = 1, + gprArchRegs = scalarBackend.gprArchRegs, + gprPhysRegs = scalarBackend.gprPhysRegs, + gprMapQDepthPerStid = scalarBackend.gprMapQDepth, + tuMapQDepthPerStid = scalarLsu.mapQDepth), + iex = base.iex.copy( + scalarIssueBanks = scalarBackend.scalarIssueBanks, + integerReadPorts = scalarBackend.gprReadPorts, + integerWritePorts = scalarBackend.gprWritePorts), + lsu = base.lsu.copy( + loadQueueEntries = scalarLsu.liqEntries, + storeQueueEntries = scalarLsu.stqEntries, + loadReturnQueueEntries = scalarLsu.loadReturnQueueEntries, + storeCommitQueueEntries = scalarLsu.commitQueueEntries, + scbEntries = scalarLsu.scbEntries, + lineBytes = scalarLsu.lineBytes), + lsidWidth = lsidWidth) + } +} + +object CoreParams { + /** Temporary constructor bridge for legacy modules awaiting migration. */ + def fromMainline(p: linxcore.params.CoreParams): CoreParams = + CoreParams( + robEntries = p.ooo.robCapacityPerStid, + commitWidth = p.widths.retireWidth, + scalarLsu = ScalarLsuParams.fromMainline(p), + scalarBackend = ScalarBackendParams( + gprArchRegs = p.ooo.gprArchRegs, + gprPhysRegs = p.ooo.gprPhysRegs, + gprMapQDepth = p.ooo.gprMapQDepthPerStid, + gprWritePorts = p.iex.integerWritePorts, + scalarIssueBanks = p.iex.scalarIssueBanks, + gprReadPorts = p.iex.integerReadPorts), + lsidWidth = p.lsidWidth) } final case class ScalarBackendParams( @@ -133,3 +182,36 @@ final case class ScalarLsuParams( require(mapQDepth > 1 && (mapQDepth & (mapQDepth - 1)) == 0, "mapQDepth must be a power of two greater than one") } + +object ScalarLsuParams { + /** Immutable projection from the centralized parameter hierarchy. + * + * This helper owns no hardware state. It keeps the private scalar LSU + * mechanisms on the same load/store topology and capacity values as the + * public parameter source until their Task-15 boundary cutover. + */ + def fromMainline(p: linxcore.params.CoreParams): ScalarLsuParams = + ScalarLsuParams( + stqEntries = p.lsu.storeQueueEntries, + commitQueueEntries = p.lsu.storeCommitQueueEntries, + commitIssueWidth = p.lsu.storePipes, + scbEntries = p.lsu.scbEntries, + scbResponseBufferDepth = p.lsu.scbResponseBufferDepth, + liqEntries = p.lsu.loadQueueEntries, + loadMissQueueEntries = p.lsu.loadMissQueueEntries, + loadRefillQueueEntries = p.lsu.loadRefillQueueEntries, + resolveQueueEntries = p.lsu.resolveQueueEntries, + mdbSsitEntries = p.lsu.mdbSsitEntries, + mdbCommandQueueEntries = p.lsu.mdbCommandQueueEntries, + mdbOutputQueueEntries = p.lsu.mdbOutputQueueEntries, + mdbWaitPlanQueueEntries = p.lsu.mdbWaitPlanQueueEntries, + mdbRecoveryQueueEntries = p.lsu.mdbRecoveryQueueEntries, + mdbFailedWaitTimeoutCycles = p.lsu.mdbFailedWaitTimeoutCycles, + loadReturnQueueEntries = p.lsu.loadReturnQueueEntries, + loadReturnPipeCount = p.lsu.loadPipes, + l1dSets = p.lsu.l1dSets, + l1dWays = p.lsu.l1dWays, + lineBytes = p.lsu.lineBytes, + mapQDepth = p.ooo.tuMapQDepthPerStid, + stidCount = p.ooo.stidCount) +} diff --git a/chisel/src/main/scala/linxcore/common/InterfaceBundles.scala b/chisel/src/main/scala/linxcore/common/InterfaceBundles.scala index 7726e6f4..4a3e524a 100644 --- a/chisel/src/main/scala/linxcore/common/InterfaceBundles.scala +++ b/chisel/src/main/scala/linxcore/common/InterfaceBundles.scala @@ -52,7 +52,9 @@ final case class InterfaceParams( require(blockUidWidth >= 64, "block UID must preserve the 64-bit DFX namespace") require(uopUidWidth >= 64, "uop UID must preserve the 64-bit DFX namespace") require(lsidWidth >= 32, "load/store ID must preserve the 32-bit backend contract") - require(checkpointWidth == 6, "checkpoint ID follows the current decode contract") + require( + checkpointWidth > 0 && checkpointWidth <= uopUidWidth, + "checkpoint ID must be positive and fit the transaction identity") require(peIdWidth > 0, "scalar PE id width must be positive") require(threadIdWidth > 0, "thread/STID width must be positive") diff --git a/chisel/src/main/scala/linxcore/ctu/CTU.scala b/chisel/src/main/scala/linxcore/ctu/CTU.scala new file mode 100644 index 00000000..7a17981b --- /dev/null +++ b/chisel/src/main/scala/linxcore/ctu/CTU.scala @@ -0,0 +1,264 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.util.{Decoupled, MuxCase, PopCount, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +/** Mainline CTU owner for template description and retained D1 packetization. */ +class CTU(val p: CoreParams) extends Module { + val io = IO(new CTUIO(p)) + private val packetIndexWidth = + math.max(1, log2Ceil(p.widths.fetchWidth)) + + private def packetIndex(value: UInt): UInt = + if (value.getWidth > packetIndexWidth) + value(packetIndexWidth - 1, 0) + else + value.pad(packetIndexWidth) + + val packetValid = RegInit(false.B) + val packet = RegInit(0.U.asTypeOf(new FetchedPacket(p))) + val parentIndex = RegInit( + 0.U(PrefixPacketContract.countWidth(p.widths.fetchWidth).W)) + val templateOrdinal = RegInit(0.U(8.W)) + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + private def terminalMatches(candidate: RecoveryPlan): Bool = + candidate.transactionId === recoveryPlan.transactionId && + candidate.cause === recoveryPlan.cause && + candidate.trigger.asUInt === recoveryPlan.trigger.asUInt && + candidate.survivingTailValid === recoveryPlan.survivingTailValid && + candidate.survivingTail.asUInt === recoveryPlan.survivingTail.asUInt && + candidate.redirectPc === recoveryPlan.redirectPc && + candidate.newEpoch === recoveryPlan.newEpoch + + val recoveryTxMatch = terminalMatches(io.recovery.apply.bits) + val abortTxMatch = terminalMatches(io.recovery.abort.bits) + val preparedCompletes = + !preparedValid || io.recovery.prepared.fire + val applyHit = recoveryPending && io.recovery.apply.valid && + preparedCompletes && recoveryTxMatch && + io.recovery.apply.bits.phase === RecoveryPhase.Apply + val abortHit = recoveryPending && io.recovery.abort.valid && + preparedCompletes && abortTxMatch && + io.recovery.abort.bits.phase === RecoveryPhase.Abort + + io.recovery.prepare.ready := !recoveryPending + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan + val prepareFire = io.recovery.prepare.fire + + when(io.recovery.prepare.fire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(applyHit || abortHit) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + val buffer = Module(new InstructionBuffer( + p, depth = p.ctu.instructionBufferEntries)) + buffer.io.prune.valid := applyHit + buffer.io.prune.bits := io.recovery.apply.bits + val bufferedStid = buffer.io.deq.bits.entries(0).parent.identity.stid + val bufferedRecoveryFence = buffer.io.deq.valid && + ((recoveryPending && bufferedStid === recoveryPlan.trigger.stid) || + (prepareFire && bufferedStid === io.recovery.prepare.bits.trigger.stid) || + (applyHit && bufferedStid === io.recovery.apply.bits.trigger.stid)) + io.toOoo.valid := buffer.io.deq.valid && !bufferedRecoveryFence + io.toOoo.bits := buffer.io.deq.bits + buffer.io.deq.ready := io.toOoo.ready && !bufferedRecoveryFence + + val decoders = Seq.fill(p.widths.fetchWidth)(Module(new TemplateDecode(p))) + val decodeResults = Wire(Vec( + p.widths.fetchWidth, new TemplateDecodeResult(p))) + for (lane <- 0 until p.widths.fetchWidth) { + decoders(lane).io.in := packet.entries(lane) + decodeResults(lane) := decoders(lane).io.out + } + + val current = packet.entries(packetIndex(parentIndex)) + val currentDecode = decodeResults(packetIndex(parentIndex)) + val currentTemplate = + currentDecode.isTemplate && currentDecode.supported + + val ordinaryValid = Wire(Vec(p.widths.ctuOutputWidth, Bool())) + val ordinaryIndex = Wire(Vec( + p.widths.ctuOutputWidth, + UInt(PrefixPacketContract.countWidth(p.widths.fetchWidth).W))) + var ordinaryPrefix: Bool = true.B + for (lane <- 0 until p.widths.ctuOutputWidth) { + val index = parentIndex + lane.U + ordinaryIndex(lane) := index + val inRange = index < packet.count + val laneTemplate = Mux( + inRange, + decodeResults(packetIndex(index)).isTemplate && + decodeResults(packetIndex(index)).supported, + false.B) + ordinaryValid(lane) := ordinaryPrefix && inRange && !laneTemplate + ordinaryPrefix = ordinaryValid(lane) + } + val ordinaryCount = PopCount(ordinaryValid) + val remainingTemplate = currentDecode.rowCount - templateOrdinal + val templateCount = Mux( + remainingTemplate > p.widths.ctuOutputWidth.U, + p.widths.ctuOutputWidth.U, + remainingTemplate) + + val expanders = + Seq.fill(p.widths.ctuOutputWidth)(Module(new TemplateExpand(p))) + val generated = Wire(Decoupled(new D1Packet(p))) + generated.bits := 0.U.asTypeOf(generated.bits) + generated.bits.count := + Mux(currentTemplate, templateCount, ordinaryCount) + for (lane <- 0 until p.widths.ctuOutputWidth) { + expanders(lane).io.active := currentTemplate && lane.U < templateCount + expanders(lane).io.parent := current + expanders(lane).io.decode := currentDecode + expanders(lane).io.ordinal := templateOrdinal + lane.U + when(currentTemplate && lane.U < templateCount) { + generated.bits.entries(lane) := expanders(lane).io.out + }.elsewhen(!currentTemplate && ordinaryValid(lane)) { + generated.bits.entries(lane).kind := FrontEndOpKind.Encoded64 + generated.bits.entries(lane).parent := + packet.entries(packetIndex(ordinaryIndex(lane))) + } + } + + val traceValid = RegInit(false.B) + val tracePacket = RegInit(0.U.asTypeOf(new TracePacket(p))) + val firstTemplateChunk = currentTemplate && templateOrdinal === 0.U + val traceCapacity = !firstTemplateChunk || !traceValid || io.trace.ready + val packetStid = current.identity.stid + val packetRecoveryFence = packetValid && + ((recoveryPending && packetStid === recoveryPlan.trigger.stid) || + (prepareFire && packetStid === io.recovery.prepare.bits.trigger.stid) || + (applyHit && packetStid === io.recovery.apply.bits.trigger.stid)) + generated.valid := packetValid && !packetRecoveryFence && + generated.bits.count.orR && traceCapacity + buffer.io.enq <> generated + + val traceRecoveryFence = traceValid && + ((recoveryPending && tracePacket.entries(0).instruction.stid === + recoveryPlan.trigger.stid) || + (prepareFire && tracePacket.entries(0).instruction.stid === + io.recovery.prepare.bits.trigger.stid) || + (applyHit && tracePacket.entries(0).instruction.stid === + io.recovery.apply.bits.trigger.stid)) + io.trace.valid := traceValid && !traceRecoveryFence + io.trace.bits := tracePacket + + val traceFires = io.trace.fire + val newTrace = generated.fire && firstTemplateChunk + when(traceFires && !newTrace) { + traceValid := false.B + } + when(newTrace) { + traceValid := true.B + tracePacket := 0.U.asTypeOf(tracePacket) + tracePacket.count := 1.U + tracePacket.entries(0).source := TraceSource.Ctu + tracePacket.entries(0).kind := TraceKind.Pipeline + tracePacket.entries(0).instructionValid := true.B + tracePacket.entries(0).instruction := current.identity + tracePacket.entries(0).pc := current.pc + tracePacket.entries(0).opcode := currentDecode.opcode + tracePacket.entries(0).payload := currentDecode.rowCount + } + + val inputStid = io.fromIfu.bits.entries(0).identity.stid + val inputBlocked = + (recoveryPending && inputStid === recoveryPlan.trigger.stid) || + (prepareFire && inputStid === io.recovery.prepare.bits.trigger.stid) || + (applyHit && inputStid === io.recovery.apply.bits.trigger.stid) + io.fromIfu.ready := !packetValid && !inputBlocked + when(io.fromIfu.fire) { + packetValid := io.fromIfu.bits.count.orR + packet := io.fromIfu.bits + parentIndex := 0.U + templateOrdinal := 0.U + } + + when(generated.fire) { + when(currentTemplate) { + val nextOrdinal = templateOrdinal + templateCount + when(nextOrdinal === currentDecode.rowCount) { + val nextParent = parentIndex + 1.U + parentIndex := nextParent + templateOrdinal := 0.U + when(nextParent === packet.count) { + packetValid := false.B + } + }.otherwise { + templateOrdinal := nextOrdinal + } + }.otherwise { + val nextParent = parentIndex + ordinaryCount + parentIndex := nextParent + templateOrdinal := 0.U + when(nextParent === packet.count) { + packetValid := false.B + } + } + } + + val packetSurvivor = Wire(Vec(p.widths.fetchWidth, Bool())) + for (lane <- 0 until p.widths.fetchWidth) { + packetSurvivor(lane) := packetValid && lane.U >= parentIndex && + lane.U < packet.count && + packet.entries(lane).identity.stid =/= + io.recovery.apply.bits.trigger.stid + } + val packetSurvivorCount = PopCount(packetSurvivor) + val currentParentSurvives = packetValid && + current.identity.stid =/= io.recovery.apply.bits.trigger.stid + val compactedPacket = Wire(new FetchedPacket(p)) + compactedPacket := 0.U.asTypeOf(compactedPacket) + compactedPacket.count := packetSurvivorCount + for (dst <- 0 until p.widths.fetchWidth) { + val candidates = (0 until p.widths.fetchWidth).map { lane => + val rank = + if (lane == 0) 0.U else PopCount(packetSurvivor.take(lane)) + (packetSurvivor(lane) && rank === dst.U) -> packet.entries(lane) + } + compactedPacket.entries(dst) := MuxCase( + 0.U.asTypeOf(new FetchedInstruction(p)), + candidates) + } + + when(applyHit) { + packet := compactedPacket + packetValid := packetSurvivorCount.orR + parentIndex := 0.U + templateOrdinal := Mux(currentParentSurvives, templateOrdinal, 0.U) + when( + traceValid && + tracePacket.entries(0).instruction.stid === + io.recovery.apply.bits.trigger.stid) { + traceValid := false.B + } + } + + when(io.recovery.prepare.fire) { + assert(io.recovery.prepare.bits.phase === RecoveryPhase.Prepare) + } + when(io.recovery.apply.valid && recoveryPending) { + assert(recoveryTxMatch) + assert(preparedCompletes) + } + when(io.recovery.abort.valid && recoveryPending) { + assert(abortTxMatch) + assert(preparedCompletes) + } + when(io.fromIfu.fire) { + assert(io.fromIfu.bits.count <= p.widths.fetchWidth.U) + } + assert(!packetValid || parentIndex < packet.count) +} diff --git a/chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala b/chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala new file mode 100644 index 00000000..d8755481 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala @@ -0,0 +1,134 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.util.{Decoupled, PriorityEncoder, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.{D1Packet, FrontEndOp, RecoveryPlan} + +class InstructionBufferIO(val p: CoreParams, val depth: Int) extends Bundle { + val enq = Flipped(Decoupled(new D1Packet(p))) + val deq = Decoupled(new D1Packet(p)) + val prune = Flipped(Valid(new RecoveryPlan(p))) + val occupancy = Output(UInt(log2Ceil(depth + 1).W)) +} + +/** Retained CTU-to-D1 boundary with no downstream-ready bypass to IFU. */ +class InstructionBuffer(val p: CoreParams, val depth: Int) extends Module { + require(depth >= p.widths.ctuOutputWidth) + + val io = IO(new InstructionBufferIO(p, depth)) + private val countWidth = log2Ceil(depth + 1) + private val entryIndexWidth = math.max(1, log2Ceil(depth)) + private val orderWidth = 64 + + val valid = RegInit(VecInit(Seq.fill(depth)(false.B))) + val entries = Reg(Vec(depth, new FrontEndOp(p))) + val order = Reg(Vec(depth, UInt(orderWidth.W))) + val count = RegInit(0.U(countWidth.W)) + val nextOrder = RegInit(0.U(orderWidth.W)) + + val outputCount = Mux( + count > p.widths.ctuOutputWidth.U, + p.widths.ctuOutputWidth.U, + count) + io.deq.valid := count.orR && !io.prune.valid + io.deq.bits := 0.U.asTypeOf(io.deq.bits) + io.deq.bits.count := outputCount + + val selectedValid = Wire(Vec(p.widths.ctuOutputWidth, Bool())) + val selectedIndex = Wire(Vec( + p.widths.ctuOutputWidth, UInt(entryIndexWidth.W))) + var remainingMask: UInt = valid.asUInt + for (lane <- 0 until p.widths.ctuOutputWidth) { + var found: Bool = false.B + var oldestIndex: UInt = 0.U(entryIndexWidth.W) + var oldestOrder: UInt = 0.U(orderWidth.W) + for (slot <- 0 until depth) { + val choose = remainingMask(slot) && + (!found || order(slot) < oldestOrder) + oldestIndex = Mux(choose, slot.U, oldestIndex) + oldestOrder = Mux(choose, order(slot), oldestOrder) + found = found || remainingMask(slot) + } + selectedValid(lane) := found + selectedIndex(lane) := oldestIndex + when(found) { + io.deq.bits.entries(lane) := entries(oldestIndex) + } + val selectedBit = Mux( + found, + (1.U(depth.W) << oldestIndex)(depth - 1, 0), + 0.U(depth.W)) + remainingMask = remainingMask & ~selectedBit + } + + val enqCount = io.enq.bits.count + val freeCount = depth.U - count + io.enq.ready := !io.prune.valid && enqCount <= freeCount + io.occupancy := count + + val insertValid = Wire(Vec(p.widths.ctuOutputWidth, Bool())) + val insertIndex = Wire(Vec( + p.widths.ctuOutputWidth, UInt(entryIndexWidth.W))) + var freeMask: UInt = ~valid.asUInt + for (lane <- 0 until p.widths.ctuOutputWidth) { + val found = freeMask.orR + val index = PriorityEncoder(freeMask) + insertValid(lane) := found && lane.U < enqCount + insertIndex(lane) := index + val claimedBit = Mux( + found, + (1.U(depth.W) << index)(depth - 1, 0), + 0.U(depth.W)) + freeMask = freeMask & ~claimedBit + } + + val killed = Wire(Vec(depth, Bool())) + for (slot <- 0 until depth) { + killed(slot) := valid(slot) && + entries(slot).parent.identity.stid === io.prune.bits.trigger.stid + } + val killedCount = chisel3.util.PopCount(killed) + + when(io.prune.valid) { + for (slot <- 0 until depth) { + when(killed(slot)) { + valid(slot) := false.B + } + } + count := count - killedCount + }.otherwise { + when(io.deq.fire) { + for (lane <- 0 until p.widths.ctuOutputWidth) { + when(selectedValid(lane) && lane.U < outputCount) { + valid(selectedIndex(lane)) := false.B + } + } + } + when(io.enq.fire) { + for (lane <- 0 until p.widths.ctuOutputWidth) { + when(insertValid(lane)) { + valid(insertIndex(lane)) := true.B + entries(insertIndex(lane)) := io.enq.bits.entries(lane) + order(insertIndex(lane)) := nextOrder + lane.U + } + } + nextOrder := nextOrder + enqCount + } + count := count - + Mux(io.deq.fire, outputCount, 0.U) + + Mux(io.enq.fire, enqCount, 0.U) + } + + assert(count <= depth.U) + assert(count === chisel3.util.PopCount(valid)) + assert(!io.enq.valid || io.enq.bits.count <= p.widths.ctuOutputWidth.U) + assert(!io.enq.fire || insertValid.asUInt === + ((1.U << enqCount) - 1.U)) + when(io.enq.fire) { + assert(nextOrder + enqCount >= nextOrder) + } + for (lane <- 0 until p.widths.ctuOutputWidth) { + assert(!selectedValid(lane) || lane.U < count) + } +} diff --git a/chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala b/chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala new file mode 100644 index 00000000..97c7c577 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala @@ -0,0 +1,99 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.util.{is, switch} +import linxcore.common.{InterfaceParams, TemplateD3Constants, TemplateForm} +import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.CoreParams +import linxcore.top.interface.FetchedInstruction + +class TemplateDecodeResult(val p: CoreParams) extends Bundle { + val isTemplate = Bool() + val supported = Bool() + val form = TemplateForm() + val opcode = UInt(p.opcodeWidth.W) + val rangeStart = UInt(p.archRegWidth.W) + val rangeEnd = UInt(p.archRegWidth.W) + val rangeCount = UInt(5.W) + val rowCount = UInt(6.W) + val frameImmediate = UInt(p.dataWidth.W) +} + +class TemplateDecodeIO(val p: CoreParams) extends Bundle { + val in = Input(new FetchedInstruction(p)) + val out = Output(new TemplateDecodeResult(p)) +} + +/** Generated-catalog-backed recognition of the architectural template forms. + * + * This owner extracts only the information needed to describe canonical + * children. It does not allocate ROB, rename, issue, or memory state. + */ +class TemplateDecode(val p: CoreParams) extends Module { + val io = IO(new TemplateDecodeIO(p)) + + private val catalogP = InterfaceParams() + require(catalogP.opcodeWidth == p.opcodeWidth) + private val templateOpcodes = Set( + FrontendOpcodeDecodeTable.OP_FENTRY, + FrontendOpcodeDecodeTable.OP_FEXIT, + FrontendOpcodeDecodeTable.OP_FRET_RA, + FrontendOpcodeDecodeTable.OP_FRET_STK) + private val templateRules = + FrontendOpcodeDecodeTable.Rules.filter(rule => + templateOpcodes.contains(rule.opcode)) + + var matched: Bool = false.B + var opcode: UInt = 0.U(p.opcodeWidth.W) + for (rule <- templateRules) { + val hit = !matched && + io.in.lengthBytes === rule.lenBytes.U && + ((io.in.instruction & rule.mask.U(p.instructionWidth.W)) === + rule.value.U(p.instructionWidth.W)) + opcode = Mux(hit, rule.opcode.U, opcode) + matched = matched || hit + } + + val form = WireDefault(TemplateForm.Invalid) + switch(opcode) { + is(FrontendOpcodeDecodeTable.OP_FENTRY.U) { + form := TemplateForm.FENTRY + } + is(FrontendOpcodeDecodeTable.OP_FEXIT.U) { + form := TemplateForm.FEXIT + } + is(FrontendOpcodeDecodeTable.OP_FRET_RA.U) { + form := TemplateForm.FRET_RA + } + is(FrontendOpcodeDecodeTable.OP_FRET_STK.U) { + form := TemplateForm.FRET_STK + } + } + + val rangeStart = io.in.instruction(19, 15) + val rangeEnd = io.in.instruction(24, 20) + val legalStart = rangeStart >= 2.U && rangeStart <= 23.U + val legalEnd = rangeEnd >= 2.U && rangeEnd <= 23.U + val normalCount = rangeEnd - rangeStart + 1.U + val wrappedCount = (24.U - rangeStart) + (rangeEnd - 1.U) + val rangeCount = Mux(rangeStart <= rangeEnd, normalCount, wrappedCount) + val supported = matched && legalStart && legalEnd && + TemplateD3Constants.encodedNSupported(rangeCount) + + val frameImmediate = + (io.in.instruction(11, 7).pad(p.dataWidth) << 10) | + (io.in.instruction(31, 25).pad(p.dataWidth) << 3) + + io.out := 0.U.asTypeOf(io.out) + io.out.isTemplate := matched + io.out.supported := supported + io.out.form := form + io.out.opcode := opcode + io.out.rangeStart := rangeStart + io.out.rangeEnd := rangeEnd + io.out.rangeCount := rangeCount + io.out.rowCount := TemplateD3Constants.rowCount(form.asUInt, rangeCount) + io.out.frameImmediate := frameImmediate + + assert(!io.out.supported || io.out.rowCount <= p.ctu.maxTemplateUops.U) +} diff --git a/chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala b/chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala new file mode 100644 index 00000000..8597b1f0 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala @@ -0,0 +1,84 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.util.{Cat, is, switch} +import linxcore.common.{TemplateD3Constants, TemplateForm, TemplateRowKind} +import linxcore.params.CoreParams +import linxcore.top.interface.{FetchedInstruction, FrontEndOp, FrontEndOpKind} + +class TemplateExpandIO(val p: CoreParams) extends Bundle { + val active = Input(Bool()) + val parent = Input(new FetchedInstruction(p)) + val decode = Input(new TemplateDecodeResult(p)) + val ordinal = Input(UInt(8.W)) + val out = Output(new FrontEndOp(p)) +} + +/** Pure child descriptor builder. + * + * The parent raw encoding remains attached so D1/D2 can validate every child + * before D3 reserves backend resources atomically. + */ +class TemplateExpand(val p: CoreParams) extends Module { + val io = IO(new TemplateExpandIO(p)) + + val rowKind = TemplateD3Constants.rowKind( + io.decode.form.asUInt, + io.decode.rangeCount, + io.ordinal) + + val registerOrdinal = WireDefault(0.U(8.W)) + switch(io.decode.form) { + is(TemplateForm.FENTRY) { + registerOrdinal := Mux(io.ordinal >= 2.U, io.ordinal - 2.U, 0.U) + } + is(TemplateForm.FEXIT) { + registerOrdinal := Mux(io.ordinal >= 2.U, io.ordinal - 2.U, 0.U) + } + is(TemplateForm.FRET_RA) { + registerOrdinal := Mux(io.ordinal >= 4.U, io.ordinal - 4.U, 0.U) + } + is(TemplateForm.FRET_STK) { + // Ordinal 1 already consumes range element zero through VLOAD and + // RESTORE_R10. LOAD rows therefore resume at range element one. + registerOrdinal := Mux(io.ordinal >= 6.U, io.ordinal - 5.U, 0.U) + } + } + val linearRegister = + io.decode.rangeStart - 2.U + registerOrdinal + val childRegister = + 2.U + Mux(linearRegister >= 22.U, linearRegister - 22.U, linearRegister) + val isMemoryRow = + rowKind === TemplateRowKind.STORE.asUInt || + rowKind === TemplateRowKind.LOAD.asUInt || + rowKind === TemplateRowKind.VLOAD.asUInt + val isStackRow = + rowKind === TemplateRowKind.SP_SUB.asUInt || + rowKind === TemplateRowKind.SP_ADD.asUInt + + io.out := 0.U.asTypeOf(io.out) + io.out.kind := FrontEndOpKind.TemplateUop + io.out.parent := io.parent + io.out.templateOrdinal := io.ordinal + io.out.templateCount := io.decode.rowCount + io.out.templateOpcode := rowKind + io.out.templateRegister := childRegister + val memoryOrdinal = Mux( + rowKind === TemplateRowKind.VLOAD.asUInt, + 0.U, + registerOrdinal) + val memoryByteOffset = (memoryOrdinal + 1.U).pad(p.dataWidth) << 3 + val memoryImmediate = Mux( + io.decode.form === TemplateForm.FENTRY, + io.decode.frameImmediate - memoryByteOffset, + 0.U(p.dataWidth.W) - memoryByteOffset) + io.out.templateImmediate := Mux( + isMemoryRow, + memoryImmediate, + Mux( + isStackRow, + io.decode.frameImmediate, + Cat(io.decode.rangeStart, io.decode.rangeEnd))) + + assert(!io.active || !io.decode.supported || io.ordinal < io.decode.rowCount) +} diff --git a/chisel/src/main/scala/linxcore/dtu/DTU.scala b/chisel/src/main/scala/linxcore/dtu/DTU.scala new file mode 100644 index 00000000..c9909a91 --- /dev/null +++ b/chisel/src/main/scala/linxcore/dtu/DTU.scala @@ -0,0 +1,34 @@ +package linxcore.dtu + +import chisel3._ +import linxcore.params.CoreParams +import linxcore.top.interface.DTUIO + +/** Debug, trace, and performance observation boundary. + * + * Architectural commit, trap, interrupt, and recovery decisions remain in + * OOO. DTU only transports requests and observes already-selected events. + */ +class DTU(val p: CoreParams) extends Module { + val io = IO(new DTUIO(p)) + + private val debug = Module(new DebugControl(p)) + private val trace = Module(new TraceExport(p)) + private val counters = Module(new PerformanceCounters(p)) + + debug.io.externalRequest <> io.debugRequest + io.controlRequest <> debug.io.ownerRequest + debug.io.ownerResponse <> io.controlResponse + io.debugResponse <> debug.io.externalResponse + + trace.io.in <> io.traceIn + io.traceOut <> trace.io.out + + io.commitIn.ready := true.B + counters.io.traceAccepted := trace.io.accepted + counters.io.traceDropped := trace.io.dropped + io.traceOverflowDropped + counters.io.commitObserved := io.commitIn.fire + counters.io.commitCount := io.commitIn.bits.count + counters.io.debugRequestAccepted := io.debugRequest.fire + io.performanceCounters := counters.io.values +} diff --git a/chisel/src/main/scala/linxcore/dtu/DebugControl.scala b/chisel/src/main/scala/linxcore/dtu/DebugControl.scala new file mode 100644 index 00000000..86611f31 --- /dev/null +++ b/chisel/src/main/scala/linxcore/dtu/DebugControl.scala @@ -0,0 +1,27 @@ +package linxcore.dtu + +import chisel3._ +import chisel3.util.{Decoupled, Queue} +import linxcore.params.CoreParams +import linxcore.top.interface.{DebugRequest, DebugResponse} + +class DebugControlIO(val p: CoreParams) extends Bundle { + val externalRequest = Flipped(Decoupled(new DebugRequest(p))) + val ownerRequest = Decoupled(new DebugRequest(p)) + val ownerResponse = Flipped(Decoupled(new DebugResponse(p))) + val externalResponse = Decoupled(new DebugResponse(p)) +} + +/** Retains debug transport while the OOO control owner is unavailable. + * + * This module does not interpret commands or select a commit boundary. + */ +class DebugControl(val p: CoreParams) extends Module { + val io = IO(new DebugControlIO(p)) + + private val requests = Module(new Queue(new DebugRequest(p), 1, + pipe = false, flow = false)) + requests.io.enq <> io.externalRequest + io.ownerRequest <> requests.io.deq + io.externalResponse <> io.ownerResponse +} diff --git a/chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala b/chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala new file mode 100644 index 00000000..2ea4de5e --- /dev/null +++ b/chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala @@ -0,0 +1,52 @@ +package linxcore.dtu + +import chisel3._ +import linxcore.params.CoreParams + +object PerformanceCounterIndex { + val TraceAccepted = 0 + val TraceDropped = 1 + val CommitTransactions = 2 + val CommittedInstructions = 3 + val DebugRequests = 4 + val RequiredCount = 5 +} + +class PerformanceCountersIO(val p: CoreParams) extends Bundle { + val traceAccepted = Input(UInt(64.W)) + val traceDropped = Input(UInt(64.W)) + val commitObserved = Input(Bool()) + val commitCount = Input(UInt( + linxcore.top.interface.PrefixPacketContract.countWidth( + p.widths.retireWidth).W)) + val debugRequestAccepted = Input(Bool()) + val values = Output(Vec(p.dtu.performanceCounterCount, UInt(64.W))) +} + +/** Monotonic observations only; no counter participates in control. */ +class PerformanceCounters(val p: CoreParams) extends Module { + require(p.dtu.performanceCounterCount >= PerformanceCounterIndex.RequiredCount) + val io = IO(new PerformanceCountersIO(p)) + + private val counters = RegInit(VecInit( + Seq.fill(p.dtu.performanceCounterCount)(0.U(64.W)))) + when(io.traceAccepted.orR) { + counters(PerformanceCounterIndex.TraceAccepted) := + counters(PerformanceCounterIndex.TraceAccepted) + io.traceAccepted + } + when(io.traceDropped.orR) { + counters(PerformanceCounterIndex.TraceDropped) := + counters(PerformanceCounterIndex.TraceDropped) + io.traceDropped + } + when(io.commitObserved) { + counters(PerformanceCounterIndex.CommitTransactions) := + counters(PerformanceCounterIndex.CommitTransactions) + 1.U + counters(PerformanceCounterIndex.CommittedInstructions) := + counters(PerformanceCounterIndex.CommittedInstructions) + io.commitCount + } + when(io.debugRequestAccepted) { + counters(PerformanceCounterIndex.DebugRequests) := + counters(PerformanceCounterIndex.DebugRequests) + 1.U + } + io.values := counters +} diff --git a/chisel/src/main/scala/linxcore/dtu/TraceExport.scala b/chisel/src/main/scala/linxcore/dtu/TraceExport.scala new file mode 100644 index 00000000..aad24e3e --- /dev/null +++ b/chisel/src/main/scala/linxcore/dtu/TraceExport.scala @@ -0,0 +1,41 @@ +package linxcore.dtu + +import chisel3._ +import chisel3.util.Decoupled +import linxcore.params.CoreParams +import linxcore.top.interface.TracePacket + +class TraceExportIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new TracePacket(p))) + val out = Decoupled(new TracePacket(p)) + val accepted = Output(UInt(64.W)) + val dropped = Output(UInt(64.W)) +} + +/** One-slot, loss-tolerant trace observer. + * + * Input is always accepted. A packet arriving while the retained packet is + * externally stalled is counted and dropped, leaving the visible packet + * stable until its consumer accepts it. + */ +class TraceExport(val p: CoreParams) extends Module { + val io = IO(new TraceExportIO(p)) + + private val occupied = RegInit(false.B) + private val packet = Reg(new TracePacket(p)) + + io.in.ready := true.B + io.out.valid := occupied + io.out.bits := packet + io.accepted := Mux(io.in.fire && (!occupied || io.out.ready), + io.in.bits.count, 0.U) + io.dropped := Mux(io.in.fire && occupied && !io.out.ready, + io.in.bits.count, 0.U) + + when(io.in.fire && (!occupied || io.out.ready)) { + packet := io.in.bits + occupied := true.B + }.elsewhen(io.out.fire) { + occupied := false.B + } +} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala deleted file mode 100644 index d41acf8a..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala +++ /dev/null @@ -1,2716 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{Cat, Fill, PopCount, PriorityEncoder, Reverse, is, log2Ceil, switch} - -import linxcore.commit.{CommitOperandTrace, CommitTraceParams, CommitTraceRow} -import linxcore.common.{DestinationKind, InterfaceParams, OperandClass, RenamedDestination, RenamedUop, ScalarSpAccess, ScalarSpTransaction} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rob.ROBID - -class ReducedScalarAluExecuteIO( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams()) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - - val inValid = Input(Bool()) - val inReady = Output(Bool()) - val in = Input(new RenamedUop(p)) - val srcData = Input(Vec(3, UInt(p.immWidth.W))) - val loadLookupData = Input(UInt(p.immWidth.W)) - val loadPairFirstLookupData = Input(UInt(p.immWidth.W)) - val loadLookupWaitBlocked = Input(Bool()) - val loadLiqEnable = Input(Bool()) - val loadLiqAccepted = Input(Bool()) - val stackPointerData = Input(UInt(p.immWidth.W)) - val flushValid = Input(Bool()) - val fretStkFallbackTargetValid = Input(Bool()) - val fretStkFallbackTarget = Input(UInt(p.pcWidth.W)) - val fretStkConditionValid = Input(Bool()) - val fretStkConditionTaken = Input(Bool()) - - val completeReady = Input(Bool()) - val completeValid = Output(Bool()) - val completeFire = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeRobValue = Output(UInt(ptrWidth.W)) - val completePeId = Output(UInt(p.peIdWidth.W)) - val completeStid = Output(UInt(p.threadIdWidth.W)) - val completeTid = Output(UInt(p.threadIdWidth.W)) - val completeUop = Output(new RenamedUop(p)) - val completeRow = Output(new CommitTraceRow(traceParams)) - val completeLsId = Output(UInt(p.lsidWidth.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(p.physRegWidth.W)) - val completeDstData = Output(UInt(p.immWidth.W)) - val completePairFirstDstPhysValid = Output(Bool()) - val completePairFirstDstPhysTag = Output(UInt(p.physRegWidth.W)) - val completePairFirstDstData = Output(UInt(p.immWidth.W)) - val completeSrcPhysValid = Output(Vec(3, Bool())) - val completeSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val branchConditionValid = Output(Bool()) - val branchConditionTaken = Output(Bool()) - val branchConditionIsTarget = Output(Bool()) - val branchConditionTarget = Output(UInt(p.pcWidth.W)) - val branchConditionUop = Output(new RenamedUop(p)) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(p.immWidth.W)) - val loadPairFirstLookupValid = Output(Bool()) - val loadPairFirstLookupAddr = Output(UInt(p.immWidth.W)) - val loadLookupSize = Output(UInt(p.memSizeWidth.W)) - val loadLookupReturnSignExtend = Output(Bool()) - val loadLiqEligible = Output(Bool()) - val loadLookupPc = Output(UInt(p.pcWidth.W)) - val loadLookupBid = Output(new ROBID(p.robEntries)) - val loadLookupGid = Output(new ROBID(p.robEntries)) - val loadLookupRid = Output(new ROBID(p.robEntries)) - val loadLookupLsId = Output(UInt(p.lsidWidth.W)) - val loadLookupDst = Output(new RenamedDestination(p)) - val loadLookupSourceTraceValid = Output(Bool()) - val loadLookupSource0 = Output(new CommitOperandTrace(traceParams)) - val loadLookupSource1 = Output(new CommitOperandTrace(traceParams)) - val fretStkSpRestoreValid = Output(Bool()) - val fretStkSpRestoreData = Output(UInt(p.immWidth.W)) - val scalarSpTerminalValid = Output(Bool()) - val scalarSpTerminal = Output(new ScalarSpTransaction(p)) - val scalarSpProducedValid = Output(Bool()) - val scalarSpProducedData = Output(UInt(p.immWidth.W)) - val redirectValid = Output(Bool()) - val redirectPc = Output(UInt(p.pcWidth.W)) - val redirectOrder = Output(UInt(p.uopUidWidth.W)) - - val releaseValid = Output(Bool()) - val releaseBid = Output(new ROBID(p.robEntries)) - val releaseGid = Output(new ROBID(p.robEntries)) - val releaseRid = Output(new ROBID(p.robEntries)) - val releaseStid = Output(UInt(p.threadIdWidth.W)) - val earlyReleaseValid = Output(Bool()) - val earlyReleaseBid = Output(new ROBID(p.robEntries)) - val earlyReleaseGid = Output(new ROBID(p.robEntries)) - val earlyReleaseRid = Output(new ROBID(p.robEntries)) - val earlyReleaseStid = Output(UInt(p.threadIdWidth.W)) - val liqReleaseValid = Output(Bool()) - val liqReleaseBid = Output(new ROBID(p.robEntries)) - val liqReleaseRid = Output(new ROBID(p.robEntries)) - val liqReleaseStid = Output(UInt(p.threadIdWidth.W)) - - val accepted = Output(Bool()) - val busy = Output(Bool()) - val loadWaitHold = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(p.opcodeWidth.W)) -} - -class ReducedScalarAluExecute( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams()) - extends Module { - require(traceParams.robValueWidth >= p.robIndexWidth, "trace ROB value must hold execute completion index") - require(traceParams.regWidth >= p.archRegWidth, "trace register field must hold architectural register tags") - require(traceParams.dataWidth == p.immWidth, "reduced ALU trace data follows InterfaceParams immediate/data width") - - val io = IO(new ReducedScalarAluExecuteIO(p, traceParams)) - - private def opcode(value: Int): UInt = - value.U(p.opcodeWidth.W) - - private def isSupported(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_ADD) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDW) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDTPC) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDTPC) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETRET) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETRET) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVR) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SETRET) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_AND) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_OR) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SUB) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_B) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_H) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_W) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_B) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_H) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_W) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_LDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_EQ) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_NE) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_TGT) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_CMP_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_CMP_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_AND) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_EQ) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GE) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEU) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LT) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTU) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_NE) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_OR) || - op === opcode(FrontendOpcodeDecodeTable.OP_CMP_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_CSEL) || - op === opcode(FrontendOpcodeDecodeTable.OP_FRET_STK) || - op === opcode(FrontendOpcodeDecodeTable.OP_FENTRY) || - op === opcode(FrontendOpcodeDecodeTable.OP_AND) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDW) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_BCNT) || - op === opcode(FrontendOpcodeDecodeTable.OP_BIC) || - op === opcode(FrontendOpcodeDecodeTable.OP_BIS) || - op === opcode(FrontendOpcodeDecodeTable.OP_BXS) || - op === opcode(FrontendOpcodeDecodeTable.OP_BXU) || - op === opcode(FrontendOpcodeDecodeTable.OP_CLZ) || - op === opcode(FrontendOpcodeDecodeTable.OP_CTZ) || - op === opcode(FrontendOpcodeDecodeTable.OP_LUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIS) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIU) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWU_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PO) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_PO) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_LB) || - op === opcode(FrontendOpcodeDecodeTable.OP_LBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LBU) || - op === opcode(FrontendOpcodeDecodeTable.OP_LBUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_LD) || - op === opcode(FrontendOpcodeDecodeTable.OP_LH) || - op === opcode(FrontendOpcodeDecodeTable.OP_LHU) || - op === opcode(FrontendOpcodeDecodeTable.OP_LW) || - op === opcode(FrontendOpcodeDecodeTable.OP_LR_W) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LHUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIV) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVU) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVW) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVUW) || - op === opcode(FrontendOpcodeDecodeTable.OP_MUL) || - op === opcode(FrontendOpcodeDecodeTable.OP_MULU) || - op === opcode(FrontendOpcodeDecodeTable.OP_MULUW) || - op === opcode(FrontendOpcodeDecodeTable.OP_MULW) || - op === opcode(FrontendOpcodeDecodeTable.OP_MADD) || - op === opcode(FrontendOpcodeDecodeTable.OP_MAX) || - op === opcode(FrontendOpcodeDecodeTable.OP_MAXU) || - op === opcode(FrontendOpcodeDecodeTable.OP_MIN) || - op === opcode(FrontendOpcodeDecodeTable.OP_MINU) || - op === opcode(FrontendOpcodeDecodeTable.OP_FEQ) || - op === opcode(FrontendOpcodeDecodeTable.OP_FCVT) || - op === opcode(FrontendOpcodeDecodeTable.OP_UCVTF) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SB) || - op === opcode(FrontendOpcodeDecodeTable.OP_SH) || - op === opcode(FrontendOpcodeDecodeTable.OP_SW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_AND) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_EQ) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GE) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEU) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LT) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTU) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_NE) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_OR) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_TGT) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SD) || - op === opcode(FrontendOpcodeDecodeTable.OP_SDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLL) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRL) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRA) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REM) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMU) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMUW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SSRSET) || - op === opcode(FrontendOpcodeDecodeTable.OP_SSRGET) || - op === opcode(FrontendOpcodeDecodeTable.OP_OR) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORW) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ADD) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ADDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SLLI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SRLI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUB) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBW) || - op === opcode(FrontendOpcodeDecodeTable.OP_XOR) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORIW) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORW) - - private def isDivideOrRemainder(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_DIV) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVU) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVW) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVUW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REM) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMU) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMUW) - - private def isScalarFp(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_FEQ) || - op === opcode(FrontendOpcodeDecodeTable.OP_FCVT) || - op === opcode(FrontendOpcodeDecodeTable.OP_UCVTF) - - private def isSignedDivideOrRemainder(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_DIV) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REM) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMW) - - private def isSetcEqImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_EQI) - - private def isSetcNeImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_NEI) - - private def isSetcAndImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI) - - private def isSetcOrImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_ORI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ORI) - - private def isSetcLtImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTI) - - private def isSetcGeImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEI) - - private def isSetcLtuImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI) - - private def isSetcGeuImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI) - - private def isHlSetcImmediate(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_EQI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_NEI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETC_ORI) - - private def isWordDivideOrRemainder(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_DIVW) || - op === opcode(FrontendOpcodeDecodeTable.OP_DIVUW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMUW) - - private def isRemainder(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_REM) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMU) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMW) || - op === opcode(FrontendOpcodeDecodeTable.OP_REMUW) - - private def ldiScaledOffset(imm: UInt): UInt = - (imm << 3)(p.immWidth - 1, 0) - - private def cLdiAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + imm - - private def cLwiAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ((imm << 2)(p.immWidth - 1, 0)) - - private def cSdiAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ((imm << 3)(p.immWidth - 1, 0)) - - private def cSwiAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ((imm << 2)(p.immWidth - 1, 0)) - - private def ldiAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ldiScaledOffset(imm) - - private def lwiScaledAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ((imm << 2)(p.immWidth - 1, 0)) - - private def lwiUnscaledAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + imm - - private def loadByteImmAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + imm - - private def loadByteRegAddr(srcData: Vec[UInt], insnRaw: UInt): UInt = - srcData(0) + addSubSrcR(insnRaw, srcData(1)) - - private def loadHalfImmAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(0) + ((imm << 1)(p.immWidth - 1, 0)) - - private def loadRegAddr(srcData: Vec[UInt], insnRaw: UInt): UInt = - srcData(0) + addSubSrcR(insnRaw, srcData(1)) - - private def pcrLoadAddr(pc: UInt, imm: UInt): UInt = - pc + imm - - private def isHlStorePair(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDIP_U) - - private def hlStorePairIsWord(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP_U) - - private def hlStorePairIsUnscaled(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDIP_U) - - private def hlStorePairAddr(op: UInt, srcData: Vec[UInt], imm: UInt): UInt = { - val scaled = Mux( - hlStorePairIsWord(op), - (imm << 2)(p.immWidth - 1, 0), - (imm << 3)(p.immWidth - 1, 0)) - srcData(2) + Mux(hlStorePairIsUnscaled(op), imm, scaled) - } - - private def isHlImmediateLoadPair(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDIP_U) - - private def hlImmediateLoadPairIsByte(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBUIP) - - private def hlImmediateLoadPairIsHalf(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP_U) - - private def hlImmediateLoadPairIsWord(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP_U) - - private def hlImmediateLoadPairIsUnscaled(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDIP_U) - - private def hlImmediateLoadPairSize(op: UInt): UInt = - Mux( - hlImmediateLoadPairIsByte(op), - 1.U(p.memSizeWidth.W), - Mux( - hlImmediateLoadPairIsHalf(op), - 2.U(p.memSizeWidth.W), - Mux(hlImmediateLoadPairIsWord(op), 4.U(p.memSizeWidth.W), 8.U(p.memSizeWidth.W)))) - - private def hlImmediateLoadPairSecondAddr(op: UInt, srcData: Vec[UInt], imm: UInt): UInt = { - val size = hlImmediateLoadPairSize(op) - val shift = Mux( - hlImmediateLoadPairIsByte(op), - 0.U, - Mux(hlImmediateLoadPairIsHalf(op), 1.U, Mux(hlImmediateLoadPairIsWord(op), 2.U, 3.U))) - val scaledOffset = (imm << shift)(p.immWidth - 1, 0) - srcData(0) + Mux(hlImmediateLoadPairIsUnscaled(op), imm, scaledOffset) + size - } - - private def hlImmediateLoadPairFirstAddr(op: UInt, srcData: Vec[UInt], imm: UInt): UInt = - hlImmediateLoadPairSecondAddr(op, srcData, imm) - hlImmediateLoadPairSize(op) - - private def isHlLongOffsetLoad(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUI_U) - - private def hlLongOffsetLoadIsByte(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBUI) - - private def hlLongOffsetLoadIsHalf(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUI_U) - - private def hlLongOffsetLoadIsWord(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUI_U) - - private def hlLongOffsetLoadIsUnscaled(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LDI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHUI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWUI_U) - - private def hlLongOffsetLoadSize(op: UInt): UInt = - Mux( - hlLongOffsetLoadIsByte(op), - 1.U(p.memSizeWidth.W), - Mux( - hlLongOffsetLoadIsHalf(op), - 2.U(p.memSizeWidth.W), - Mux(hlLongOffsetLoadIsWord(op), 4.U(p.memSizeWidth.W), 8.U(p.memSizeWidth.W)))) - - private def hlLongOffsetLoadAddr(op: UInt, srcData: Vec[UInt], imm: UInt): UInt = { - val scaled = Mux( - hlLongOffsetLoadIsByte(op), - imm, - Mux( - hlLongOffsetLoadIsHalf(op), - (imm << 1)(p.immWidth - 1, 0), - Mux( - hlLongOffsetLoadIsWord(op), - (imm << 2)(p.immWidth - 1, 0), - (imm << 3)(p.immWidth - 1, 0)))) - srcData(0) + Mux(hlLongOffsetLoadIsUnscaled(op), imm, scaled) - } - - private def isHlLongOffsetStore(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_U) - - private def hlLongOffsetStoreIsByte(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SBI) - - private def hlLongOffsetStoreIsHalf(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SHI_U) - - private def hlLongOffsetStoreIsWord(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_U) - - private def hlLongOffsetStoreIsUnscaled(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_U) - - private def hlLongOffsetStoreSize(op: UInt): UInt = - Mux( - hlLongOffsetStoreIsByte(op), - 1.U(p.memSizeWidth.W), - Mux( - hlLongOffsetStoreIsHalf(op), - 2.U(p.memSizeWidth.W), - Mux(hlLongOffsetStoreIsWord(op), 4.U(p.memSizeWidth.W), 8.U(p.memSizeWidth.W)))) - - private def hlLongOffsetStoreAddr(op: UInt, srcData: Vec[UInt], imm: UInt): UInt = { - val scaled = Mux( - hlLongOffsetStoreIsByte(op), - imm, - Mux( - hlLongOffsetStoreIsHalf(op), - (imm << 1)(p.immWidth - 1, 0), - Mux( - hlLongOffsetStoreIsWord(op), - (imm << 2)(p.immWidth - 1, 0), - (imm << 3)(p.immWidth - 1, 0)))) - srcData(1) + Mux(hlLongOffsetStoreIsUnscaled(op), imm, scaled) - } - - private def pcrStoreSize(op: UInt): UInt = - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR), - 1.U, - Mux(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR), 2.U, Mux(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR), 4.U, 8.U))) - - private def traceUsesSrc1(op: UInt): Bool = - !(op === opcode(FrontendOpcodeDecodeTable.OP_ADDI) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ADDI)) - - private def loadReturnSignExtend(op: UInt): Bool = - op === opcode(FrontendOpcodeDecodeTable.OP_LB) || - op === opcode(FrontendOpcodeDecodeTable.OP_LBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_LH) || - op === opcode(FrontendOpcodeDecodeTable.OP_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_LH_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_LW) || - op === opcode(FrontendOpcodeDecodeTable.OP_LR_W) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_LW_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_LWI) - - private def sext32(value: UInt): UInt = - Cat(Fill(p.immWidth - 32, value(31)), value(31, 0)) - - private def sext16(value: UInt): UInt = - Cat(Fill(p.immWidth - 16, value(15)), value(15, 0)) - - private def sext8(value: UInt): UInt = - Cat(Fill(p.immWidth - 8, value(7)), value(7, 0)) - - private def zext32(value: UInt): UInt = - value(31, 0).pad(p.immWidth) - - private def zext16(value: UInt): UInt = - value(15, 0).pad(p.immWidth) - - private def zext8(value: UInt): UInt = - value(7, 0).pad(p.immWidth) - - private def srcRType(insn: UInt): UInt = - insn(26, 25) - - private def srcRShamt(insn: UInt): UInt = - insn(31, 27) - - private def setcImmediateShamt(op: UInt, insn: UInt): UInt = - Mux(isHlSetcImmediate(op), insn(27, 23), insn(11, 7)) - - private def setcShiftedImmediate(op: UInt, insn: UInt, imm: UInt): UInt = - (imm << setcImmediateShamt(op, insn))(p.immWidth - 1, 0) - - private def shiftedSrcR(value: UInt, shamt: UInt): UInt = - (value << shamt)(p.immWidth - 1, 0) - - private def boolResult(value: Bool): UInt = - Mux(value, 1.U(p.immWidth.W), 0.U(p.immWidth.W)) - - private def rotateRight(value: UInt, amount: UInt): UInt = { - val inverse = p.immWidth.U((log2Ceil(p.immWidth) + 1).W) - amount - ((value >> amount) | (value << inverse))(p.immWidth - 1, 0) - } - - private def rotateLeft(value: UInt, amount: UInt): UInt = { - val inverse = p.immWidth.U((log2Ceil(p.immWidth) + 1).W) - amount - ((value << amount) | (value >> inverse))(p.immWidth - 1, 0) - } - - private def bitField(insn: UInt, value: UInt): (UInt, UInt, Bool) = { - val lsb = insn(31, 26) - val width = Cat(0.U(1.W), insn(25, 20)) + 1.U - val legal = width <= p.immWidth.U - val wideMask = (1.U((p.immWidth + 1).W) << width) - 1.U - val mask = Mux(width === p.immWidth.U, Fill(p.immWidth, 1.U(1.W)), wideMask(p.immWidth - 1, 0)) - val field = Mux(legal, rotateRight(value, lsb) & mask, 0.U) - (field, width, legal) - } - - private def bitFieldMask(insn: UInt): UInt = { - val lsb = insn(31, 26) - val width = Cat(0.U(1.W), insn(25, 20)) + 1.U - val wideMask = (1.U((p.immWidth + 1).W) << width) - 1.U - val lowMask = - Mux(width === p.immWidth.U, Fill(p.immWidth, 1.U(1.W)), wideMask(p.immWidth - 1, 0)) - rotateLeft(lowMask, lsb) - } - - private def bitExtractSigned(insn: UInt, value: UInt): UInt = { - val (field, width, legal) = bitField(insn, value) - val sign = (field >> (width - 1.U))(0) - val wideMask = (1.U((p.immWidth + 1).W) << width) - 1.U - val mask = Mux(width === p.immWidth.U, Fill(p.immWidth, 1.U(1.W)), wideMask(p.immWidth - 1, 0)) - Mux(legal && sign, field | ~mask, field) - } - - private def countLeadingZerosField(insn: UInt, value: UInt): UInt = { - val (field, width, legal) = bitField(insn, value) - val aligned = (field << (p.immWidth.U - width))(p.immWidth - 1, 0) - Mux(!legal, 0.U, Mux(field === 0.U, width, PriorityEncoder(Reverse(aligned)))).pad(p.immWidth) - } - - private def countTrailingZerosField(insn: UInt, value: UInt): UInt = { - val (field, width, legal) = bitField(insn, value) - Mux(!legal, 0.U, Mux(field === 0.U, width, PriorityEncoder(field))).pad(p.immWidth) - } - - private def addSubSrcR(insn: UInt, value: UInt): UInt = { - val converted = Wire(UInt(p.immWidth.W)) - converted := value - switch(srcRType(insn)) { - is(0.U) { converted := sext32(value) } - is(1.U) { converted := zext32(value) } - is(2.U) { converted := (0.U(p.immWidth.W) - value)(p.immWidth - 1, 0) } - } - shiftedSrcR(converted, srcRShamt(insn)) - } - - private def storeRegSrcR(insn: UInt, value: UInt): UInt = { - val converted = Wire(UInt(p.immWidth.W)) - converted := value - switch(srcRType(insn)) { - is(0.U) { converted := sext32(value) } - is(1.U) { converted := zext32(value) } - is(2.U) { converted := (0.U(p.immWidth.W) - value)(p.immWidth - 1, 0) } - } - converted - } - - private def logicSrcR(insn: UInt, value: UInt): UInt = { - val converted = Wire(UInt(p.immWidth.W)) - converted := value - switch(srcRType(insn)) { - is(0.U) { converted := sext32(value) } - is(1.U) { converted := zext32(value) } - is(2.U) { converted := ~value } - } - shiftedSrcR(converted, srcRShamt(insn)) - } - - private def setcRegisterSrcR(insn: UInt, value: UInt): UInt = { - val converted = Wire(UInt(p.immWidth.W)) - converted := value - switch(srcRType(insn)) { - is(1.U) { converted := sext32(value) } - is(2.U) { converted := zext32(value) } - } - converted - } - - private def macroRangeContains(insn: UInt, reg: UInt): Bool = { - val begin = insn(19, 15) - val end = insn(24, 20) - Mux(end >= begin, reg >= begin && reg <= end, reg >= begin || reg <= end) - } - - private def fretStkRestoresRa(insn: UInt): Bool = - macroRangeContains(insn, 10.U) - - private def fretStkRaLoadAddr(stackPointerData: UInt, imm: UInt): UInt = - stackPointerData + imm - 8.U - - private def sdIndexedAddr(srcData: Vec[UInt]): UInt = - srcData(1) + ((srcData(2) << 3)(p.immWidth - 1, 0)) - - private def storeRegAddr(srcData: Vec[UInt], insnRaw: UInt, scale: Int): UInt = - srcData(1) + ((storeRegSrcR(insnRaw, srcData(2)) << scale)(p.immWidth - 1, 0)) - - private def storeByteImmAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(1) + imm - - private def storeByteRegAddr(srcData: Vec[UInt], insnRaw: UInt): UInt = - srcData(1) + storeRegSrcR(insnRaw, srcData(2)) - - private def storeHalfImmAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(1) + ((imm << 1)(p.immWidth - 1, 0)) - - private def storeWordImmAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(1) + ((imm << 2)(p.immWidth - 1, 0)) - - private def hlSdiPrAddr(srcData: Vec[UInt], imm: UInt): UInt = - srcData(1) + ((imm << 3)(p.immWidth - 1, 0)) - - private def resultFor( - op: UInt, - pc: UInt, - insnRaw: UInt, - srcData: Vec[UInt], - imm: UInt, - loadData: UInt, - stackPointerData: UInt): UInt = { - val addSubR = addSubSrcR(insnRaw, srcData(1)) - val logicR = logicSrcR(insnRaw, srcData(1)) - val out = Wire(UInt(p.immWidth.W)) - out := 0.U - when(op === opcode(FrontendOpcodeDecodeTable.OP_ADD)) { - out := srcData(0) + addSubR - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ADDW)) { - out := sext32(srcData(0) + addSubR) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SUB)) { - out := srcData(0) - addSubR - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SUBW)) { - out := sext32(srcData(0) - addSubR) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ADDI)) { - out := srcData(0) + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ADDIW)) { - out := sext32(srcData(0)(31, 0) + imm(11, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SUBI)) { - out := srcData(0) - imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SUBIW)) { - out := sext32(srcData(0)(31, 0) - imm(11, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_AND)) { - out := srcData(0) & logicR - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ANDW)) { - out := sext32(srcData(0) & logicR) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ANDI)) { - out := srcData(0) & imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ANDIW)) { - out := sext32(srcData(0) & imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ADDTPC)) { - out := (pc & "hffff_ffff_ffff_f000".U(p.immWidth.W)) + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETRET)) { - out := pc + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SETRET)) { - out := pc + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVI)) { - out := imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVR)) { - out := srcData(0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_ADD)) { - out := srcData(0) + srcData(1) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_ADDI)) { - out := srcData(0) + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SLLI)) { - out := srcData(0) << imm(4, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SRLI)) { - out := srcData(0) >> imm(4, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_AND)) { - out := srcData(0) & srcData(1) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_OR)) { - out := srcData(0) | srcData(1) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SUB)) { - out := srcData(0) - srcData(1) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_B)) { - out := sext8(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_H)) { - out := sext16(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_W)) { - out := sext32(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_B)) { - out := zext8(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_H)) { - out := zext16(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_W)) { - out := zext32(srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SETRET)) { - out := pc + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_CMP_EQI)) { - out := boolResult(srcData(0) === imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_CMP_NEI)) { - out := boolResult(srcData(0) =/= imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_AND)) { - out := boolResult((srcData(0) & logicSrcR(insnRaw, srcData(1))) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_ANDI)) { - out := boolResult((srcData(0) & imm) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_EQ)) { - out := boolResult(srcData(0) === addSubSrcR(insnRaw, srcData(1))) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_EQI)) { - out := boolResult(srcData(0) === imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GE)) { - out := boolResult(srcData(0).asSInt >= addSubSrcR(insnRaw, srcData(1)).asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEI)) { - out := boolResult(srcData(0).asSInt >= imm.asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEU)) { - out := boolResult(srcData(0) >= addSubSrcR(insnRaw, srcData(1))) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_GEUI)) { - out := boolResult(srcData(0) >= imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LT)) { - out := boolResult(srcData(0).asSInt < addSubSrcR(insnRaw, srcData(1)).asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTI)) { - out := boolResult(srcData(0).asSInt < imm.asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTU)) { - out := boolResult(srcData(0) < addSubSrcR(insnRaw, srcData(1))) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_LTUI)) { - out := boolResult(srcData(0) < imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_NE)) { - out := boolResult(srcData(0) =/= addSubSrcR(insnRaw, srcData(1))) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_NEI)) { - out := boolResult(srcData(0) =/= imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_OR)) { - out := boolResult((srcData(0) | logicSrcR(insnRaw, srcData(1))) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CMP_ORI)) { - out := boolResult((srcData(0) | imm) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CSEL)) { - out := Mux(srcData(2) =/= 0.U, srcData(0), srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_BCNT)) { - out := PopCount(bitField(insnRaw, srcData(0))._1).pad(p.immWidth) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_BIC)) { - out := srcData(0) & ~bitFieldMask(insnRaw) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_BIS)) { - out := srcData(0) | bitFieldMask(insnRaw) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_BXS)) { - out := bitExtractSigned(insnRaw, srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_BXU)) { - out := bitField(insnRaw, srcData(0))._1 - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CLZ)) { - out := countLeadingZerosField(insnRaw, srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_CTZ)) { - out := countTrailingZerosField(insnRaw, srcData(0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_LDI)) { - out := loadData - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_LWI)) { - out := sext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LB)) { - out := sext8(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LBI)) { - out := sext8(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LBU)) { - out := loadData(7, 0).pad(p.immWidth) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LBUI)) { - out := loadData(7, 0).pad(p.immWidth) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LD)) { - out := loadData - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LH)) { - out := sext16(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LHU)) { - out := zext16(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LW)) { - out := sext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LR_W)) { - out := sext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LWUI)) { - out := zext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LDI)) { - out := loadData - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LHI)) { - out := sext16(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LHUI)) { - out := zext16(loadData) - }.elsewhen( - op === opcode(FrontendOpcodeDecodeTable.OP_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_LWI_U)) { - out := sext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SDI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SWI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_EQ)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_NE)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_TGT)) { - out := 0.U - }.elsewhen(isSetcAndImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_EQ)) { - out := 0.U - }.elsewhen(isSetcEqImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_NE)) { - out := 0.U - }.elsewhen(isSetcNeImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LT)) { - out := 0.U - }.elsewhen(isSetcLtImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GE)) { - out := 0.U - }.elsewhen(isSetcGeImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTU)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEU)) { - out := 0.U - }.elsewhen(isSetcGeuImmediate(op)) { - out := 0.U - }.elsewhen(isSetcLtuImmediate(op)) { - out := 0.U - }.elsewhen(isSetcOrImmediate(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SETC_TGT)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_FRET_STK)) { - out := loadData - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_FENTRY)) { - out := stackPointerData - imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_LUI)) { - out := imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LUI)) { - out := imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIS)) { - out := imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIU)) { - out := imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDI)) { - out := srcData(0) + imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDIW)) { - out := sext32(srcData(0) + imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDI)) { - out := srcData(0) & imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDIW)) { - out := sext32(srcData(0) & imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_ANDI)) { - out := boolResult((srcData(0) & imm) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_EQI)) { - out := boolResult(srcData(0) === imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_GEI)) { - out := boolResult(srcData(0).asSInt >= imm.asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_GEUI)) { - out := boolResult(srcData(0) >= imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_LTI)) { - out := boolResult(srcData(0).asSInt < imm.asSInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_LTUI)) { - out := boolResult(srcData(0) < imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_NEI)) { - out := boolResult(srcData(0) =/= imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_CMP_ORI)) { - out := boolResult((srcData(0) | imm) =/= 0.U) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORI)) { - out := srcData(0) | imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORIW)) { - out := sext32(srcData(0) | imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBI)) { - out := srcData(0) - imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBIW)) { - out := sext32(srcData(0) - imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORI)) { - out := srcData(0) ^ imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORIW)) { - out := sext32(srcData(0) ^ imm) - }.elsewhen( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_LD_PCR)) { - out := loadData - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR)) { - out := sext8(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR)) { - out := zext8(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR)) { - out := sext32(loadData) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWU_PCR)) { - out := zext32(loadData) - }.elsewhen(isHlImmediateLoadPair(op)) { - out := Mux( - hlImmediateLoadPairIsByte(op), - Mux(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBIP), sext8(loadData), zext8(loadData)), - Mux( - hlImmediateLoadPairIsHalf(op), - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHIP_U), - sext16(loadData), - zext16(loadData)), - Mux( - hlImmediateLoadPairIsWord(op), - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWIP_U), - sext32(loadData), - zext32(loadData)), - loadData))) - }.elsewhen(isHlLongOffsetLoad(op)) { - out := Mux( - hlLongOffsetLoadIsByte(op), - Mux(op === opcode(FrontendOpcodeDecodeTable.OP_HL_LBI), sext8(loadData), zext8(loadData)), - Mux( - hlLongOffsetLoadIsHalf(op), - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LHI_U), - sext16(loadData), - zext16(loadData)), - Mux( - hlLongOffsetLoadIsWord(op), - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LWI_U), - sext32(loadData), - zext32(loadData)), - loadData))) - }.elsewhen( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR)) { - out := 0.U - }.elsewhen( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PO) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PR)) { - out := hlSdiPrAddr(srcData, imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_PO)) { - // Store-post-index uses the old base as the memory address and writes - // base + (signed encoded immediate << log2(word bytes)) to RegDst. - out := srcData(1) + ((imm << 2)(p.immWidth - 1, 0)) - }.elsewhen(isHlStorePair(op)) { - out := 0.U - }.elsewhen(isHlLongOffsetStore(op)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SB)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SH)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SW)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SBI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SD)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SDI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SHI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SWI)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MUL)) { - out := (srcData(0) * srcData(1))(p.immWidth - 1, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MULU)) { - out := (srcData(0) * srcData(1))(p.immWidth - 1, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MULW)) { - out := sext32(srcData(0) * srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MULUW)) { - out := sext32(srcData(0) * srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MADD)) { - out := srcData(2) + (srcData(0) * srcData(1))(p.immWidth - 1, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MAX)) { - out := Mux(srcData(0).asSInt >= srcData(1).asSInt, srcData(0), srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MAXU)) { - out := Mux(srcData(0) >= srcData(1), srcData(0), srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MIN)) { - out := Mux(srcData(0).asSInt <= srcData(1).asSInt, srcData(0), srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_MINU)) { - out := Mux(srcData(0) <= srcData(1), srcData(0), srcData(1)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLL)) { - out := (srcData(0) << srcData(1)(5, 0))(p.immWidth - 1, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLLI)) { - out := (srcData(0) << imm(5, 0))(p.immWidth - 1, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLLW)) { - out := sext32(srcData(0)(31, 0) << srcData(1)(4, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLLIW)) { - out := sext32(srcData(0)(31, 0) << imm(4, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRL)) { - out := srcData(0) >> srcData(1)(5, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRLI)) { - out := srcData(0) >> imm(5, 0) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRLW)) { - out := sext32(srcData(0)(31, 0) >> srcData(1)(4, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRLIW)) { - out := sext32(srcData(0)(31, 0) >> imm(4, 0)) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRA)) { - out := (srcData(0).asSInt >> srcData(1)(5, 0)).asUInt - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRAI)) { - out := (srcData(0).asSInt >> imm(5, 0)).asUInt - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRAW)) { - out := sext32((srcData(0)(31, 0).asSInt >> srcData(1)(4, 0)).asUInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRAIW)) { - out := sext32((srcData(0)(31, 0).asSInt >> imm(4, 0)).asUInt) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SSRSET)) { - out := 0.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_OR)) { - out := srcData(0) | logicR - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ORW)) { - out := sext32(srcData(0) | logicR) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ORI)) { - out := srcData(0) | imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_ORIW)) { - out := sext32(srcData(0) | imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_XOR)) { - out := srcData(0) ^ logicR - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_XORI)) { - out := srcData(0) ^ imm - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_XORIW)) { - out := sext32(srcData(0) ^ imm) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_XORW)) { - out := sext32(srcData(0) ^ logicR) - } - out - } - - private def fitReg(tag: UInt): UInt = - tag.pad(traceParams.regWidth)(traceParams.regWidth - 1, 0) - - private def robIdValue(id: ROBID): UInt = - id.value.pad(32)(31, 0) - - private def completionRow( - uop: RenamedUop, - srcData: Vec[UInt], - result: UInt, - valid: Bool, - setcTargetValid: Bool, - setcTarget: UInt, - fallbackTargetValid: Bool, - fallbackTarget: UInt, - fretStkLoadReturn: Bool, - stackPointerData: UInt): CommitTraceRow = { - val row = Wire(new CommitTraceRow(traceParams)) - row := 0.U.asTypeOf(row) - row.valid := valid - row.identity.bid := robIdValue(uop.bid) - row.identity.gid := robIdValue(uop.gid) - row.identity.rid := robIdValue(uop.rid) - row.rob.valid := uop.rid.valid - row.rob.wrap := uop.rid.wrap - row.rob.value := uop.rid.value - row.blockBidValid := uop.blockBidValid - row.blockBid := uop.blockBid - row.pc := uop.pc - row.insn := uop.insnRaw - row.len := uop.insnLen - row.nextPc := uop.pc + uop.insnLen - row.src0.valid := valid && uop.src(0).valid && (uop.src(0).operandClass === OperandClass.P) - row.src0.reg := fitReg(uop.src(0).archTag) - row.src0.data := srcData(0) - row.src1.valid := valid && traceUsesSrc1(uop.opcode) && uop.src(1).valid && (uop.src(1).operandClass === OperandClass.P) - row.src1.reg := fitReg(uop.src(1).archTag) - row.src1.data := srcData(1) - when(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SD)) { - row.src0.valid := valid && uop.src(1).valid && (uop.src(1).operandClass === OperandClass.P) - row.src0.reg := fitReg(uop.src(1).archTag) - row.src0.data := srcData(1) - row.src1.valid := valid && uop.src(2).valid && (uop.src(2).operandClass === OperandClass.P) - row.src1.reg := fitReg(uop.src(2).archTag) - row.src1.data := srcData(2) - } - row.dst.valid := valid && uop.dst(0).valid - row.dst.reg := fitReg(uop.dst(0).archTag) - row.dst.data := result - row.wb.valid := valid && uop.dst(0).valid - row.wb.reg := fitReg(uop.dst(0).archTag) - row.wb.data := result - when(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_FRET_STK)) { - row.nextPc := Mux( - fretStkLoadReturn, - result, - Mux(setcTargetValid, setcTarget, Mux(fallbackTargetValid, fallbackTarget, uop.pc + uop.insnLen))) - row.src0.valid := false.B - row.src0.reg := 0.U - row.src0.data := 0.U - row.src1.valid := false.B - row.src1.reg := 0.U - row.src1.data := 0.U - when(fretStkLoadReturn) { - row.dst.valid := valid - row.dst.reg := 10.U - row.dst.data := result - row.wb.valid := valid - row.wb.reg := 10.U - row.wb.data := result - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := fretStkRaLoadAddr(stackPointerData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 8.U - }.otherwise { - row.dst.valid := false.B - row.dst.reg := 0.U - row.dst.data := 0.U - row.wb.valid := false.B - row.wb.reg := 0.U - row.wb.data := 0.U - } - } - when(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_FENTRY)) { - row.src0.valid := false.B - row.src1.valid := false.B - row.mem.valid := valid - row.mem.isStore := true.B - // The register ring starts at slot zero, which is always oldSP-8. - // Later serialized D3 STORE rows walk downward by another eight bytes. - row.mem.addr := result + uop.imm - 8.U - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 8.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LDI) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LWI)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LWI), cLwiAddr(srcData, uop.imm), cLdiAddr(srcData, uop.imm)) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LWI), 4.U, 8.U) - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LB) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBI) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBU) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBUI)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := Mux( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LB) || uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBU), - loadByteRegAddr(srcData, uop.insnRaw), - loadByteImmAddr(srcData, uop.imm)) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 1.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LD) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LH) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHU) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LW) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LR_W)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := loadRegAddr(srcData, uop.insnRaw) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := Mux( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LD), - 8.U, - Mux( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LH) || uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHU), - 2.U, - 4.U)) - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LDI)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := ldiAddr(srcData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 8.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHI) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHUI)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := loadHalfImmAddr(srcData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 2.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWI) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWI_U)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWI), lwiScaledAddr(srcData, uop.imm), lwiUnscaledAddr(srcData, uop.imm)) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 4.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWUI)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := lwiScaledAddr(srcData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 4.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LD_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LD_PCR)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := pcrLoadAddr(uop.pc, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := 8.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LWU_PCR)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := pcrLoadAddr(uop.pc, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := Mux( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR), - 1.U, - 4.U) - }.elsewhen(isHlImmediateLoadPair(uop.opcode)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := hlImmediateLoadPairSecondAddr(uop.opcode, srcData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := hlImmediateLoadPairSize(uop.opcode) - }.elsewhen(isHlLongOffsetLoad(uop.opcode)) { - row.mem.valid := valid - row.mem.isStore := false.B - row.mem.addr := hlLongOffsetLoadAddr(uop.opcode, srcData, uop.imm) - row.mem.wdata := 0.U - row.mem.rdata := result - row.mem.size := hlLongOffsetLoadSize(uop.opcode) - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SD_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := pcrLoadAddr(uop.pc, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := pcrStoreSize(uop.opcode) - }.elsewhen(isHlStorePair(uop.opcode)) { - // A pair is one architectural instruction with two adjacent memory - // writes. This row carries the first lane; the autonomous integration - // publishes the second lane from src1 on its paired observation port. - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := hlStorePairAddr(uop.opcode, srcData, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := Mux(hlStorePairIsWord(uop.opcode), 4.U, 8.U) - }.elsewhen(isHlLongOffsetStore(uop.opcode)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := hlLongOffsetStoreAddr(uop.opcode, srcData, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := hlLongOffsetStoreSize(uop.opcode) - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PO)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := srcData(1) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 8.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PR)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := result - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 8.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_SWI_PO)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := srcData(1) - row.mem.wdata := srcData(0)(31, 0).pad(p.immWidth) - row.mem.rdata := 0.U - row.mem.size := 4.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SDI) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SWI)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SWI), cSwiAddr(srcData, uop.imm), cSdiAddr(srcData, uop.imm)) - row.mem.wdata := srcData(1) - row.mem.rdata := 0.U - row.mem.size := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SWI), 4.U, 8.U) - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SDI)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := srcData(1) + ((uop.imm << 3)(p.immWidth - 1, 0)) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 8.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SBI)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := storeByteImmAddr(srcData, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 1.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SHI)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := storeHalfImmAddr(srcData, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 2.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SB)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := storeByteRegAddr(srcData, uop.insnRaw) - row.mem.wdata := srcData(0)(7, 0).pad(p.immWidth) - row.mem.rdata := 0.U - row.mem.size := 1.U - }.elsewhen( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SH) || - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SW)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := Mux( - uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SH), - storeRegAddr(srcData, uop.insnRaw, 1), - storeRegAddr(srcData, uop.insnRaw, 2)) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := Mux(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SH), 2.U, 4.U) - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SWI)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := storeWordImmAddr(srcData, uop.imm) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 4.U - }.elsewhen(uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SD)) { - row.mem.valid := valid - row.mem.isStore := true.B - row.mem.addr := sdIndexedAddr(srcData) - row.mem.wdata := srcData(0) - row.mem.rdata := 0.U - row.mem.size := 8.U - } - row - } - - val eValid = RegInit(false.B) - val eUop = Reg(new RenamedUop(p)) - val eSrcData = Reg(Vec(3, UInt(p.immWidth.W))) - val eStackPointerData = Reg(UInt(p.immWidth.W)) - val eEarlyReleased = RegInit(false.B) - // TIME is architecturally monotonic. The autonomous core has no external - // wall-clock port yet, so expose a deterministic hardware cycle timebase; - // software uses only monotonic deltas in the frozen benchmark profile. - val cycleCounter = RegInit(0.U(p.immWidth.W)) - cycleCounter := cycleCounter + 1.U - - val w1Valid = RegInit(false.B) - val w1Uop = Reg(new RenamedUop(p)) - val w1SrcData = Reg(Vec(3, UInt(p.immWidth.W))) - val w1Result = Reg(UInt(p.immWidth.W)) - val w1PairFirstResult = Reg(UInt(p.immWidth.W)) - val w1Supported = Reg(Bool()) - val w1StackPointerData = Reg(UInt(p.immWidth.W)) - val w1FretStkLoadReturn = Reg(Bool()) - // FRET.STK consumes the block SETC condition in E1. Keep that decision - // with the uop through W1/W2: fetch may cross a later BSTART and clear the - // shared block-condition latch before this older return completes. - val w1FretStkConditionValid = RegInit(false.B) - val w1FretStkConditionTaken = RegInit(false.B) - val w1FretStkFallbackTargetValid = RegInit(false.B) - val w1FretStkFallbackTarget = RegInit(0.U(p.pcWidth.W)) - val w1EarlyReleased = RegInit(false.B) - - val w2Valid = RegInit(false.B) - val w2Uop = Reg(new RenamedUop(p)) - val w2SrcData = Reg(Vec(3, UInt(p.immWidth.W))) - val w2Result = Reg(UInt(p.immWidth.W)) - val w2PairFirstResult = Reg(UInt(p.immWidth.W)) - val w2Supported = Reg(Bool()) - val w2StackPointerData = Reg(UInt(p.immWidth.W)) - val w2FretStkLoadReturn = Reg(Bool()) - val w2FretStkConditionValid = RegInit(false.B) - val w2FretStkConditionTaken = RegInit(false.B) - val w2FretStkFallbackTargetValid = RegInit(false.B) - val w2FretStkFallbackTarget = RegInit(0.U(p.pcWidth.W)) - val w2EarlyReleased = RegInit(false.B) - val setcTargetValid = RegInit(false.B) - val setcTarget = RegInit(0.U(p.pcWidth.W)) - val setcTargetBlockBidValid = RegInit(false.B) - val setcTargetBlockBid = RegInit(0.U(p.blockBidWidth.W)) - val earlyReleasePendingValid = RegInit(false.B) - val earlyReleasePendingBid = RegInit(ROBID.disabled(p.robEntries)) - val earlyReleasePendingGid = RegInit(ROBID.disabled(p.robEntries)) - val earlyReleasePendingRid = RegInit(ROBID.disabled(p.robEntries)) - val earlyReleasePendingStid = RegInit(0.U(p.threadIdWidth.W)) - - val accept = io.inValid && io.inReady - val eLoadCLdi = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LDI) - val eLoadCLwi = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_LWI) - val eLoadC = eLoadCLdi || eLoadCLwi - val eLoadByteR = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LB) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBU) - val eLoadByteI = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBI) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBUI) - val eLoadByte = eLoadByteR || eLoadByteI - val eLoadReg = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LD) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LH) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHU) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LW) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LR_W) - val eLoadI = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LDI) - val eLoadLhi = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHI) - val eLoadLhui = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHUI) - val eLoadHalfI = eLoadLhi || eLoadLhui - val eLoadLwi = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWI) - val eLoadLwiU = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWI_U) - val eLoadLwui = eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LWUI) - val eLoadWordI = eLoadLwi || eLoadLwiU || eLoadLwui - val eLoadPcr = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LD_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LWU_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LD_PCR) - val eLoadPairSecond = isHlImmediateLoadPair(eUop.opcode) - val eLoadHlLongOffset = isHlLongOffsetLoad(eUop.opcode) - val w2CompleteValid = !io.flushValid && w2Valid && w2Supported - val w2CompleteFire = w2CompleteValid && io.completeReady - val w2RetainForCompletion = w2CompleteValid && !io.completeReady - val w2UnsupportedDrain = !io.flushValid && w2Valid && !w2Supported - val w2IsFretStk = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_FRET_STK) - val branchSrc0 = Mux(w2Uop.src(0).valid, w2SrcData(0), 0.U) - val branchSrc1 = Mux(w2Uop.src(1).valid, w2SrcData(1), 0.U) - val branchSetcRegisterSrc1 = setcRegisterSrcR(w2Uop.insnRaw, branchSrc1) - val branchSetcImmediate = setcShiftedImmediate(w2Uop.opcode, w2Uop.insnRaw, w2Uop.imm) - val branchTargetValid = branchSrc0 =/= 0.U - val branchIsSetcEqCompressed = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_EQ) - val branchIsSetcEqRegister = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_EQ) - val branchIsSetcEqImmediate = isSetcEqImmediate(w2Uop.opcode) - val branchIsSetcEq = branchIsSetcEqCompressed || branchIsSetcEqRegister || branchIsSetcEqImmediate - val branchIsSetcNeCompressed = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_NE) - val branchIsSetcNeRegister = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_NE) - val branchIsSetcNeImmediate = isSetcNeImmediate(w2Uop.opcode) - val branchIsSetcNe = branchIsSetcNeCompressed || branchIsSetcNeRegister || branchIsSetcNeImmediate - val branchIsSetcAndi = isSetcAndImmediate(w2Uop.opcode) - val branchIsSetcOri = isSetcOrImmediate(w2Uop.opcode) - val branchIsSetcLt = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_LT) - val branchIsSetcLti = isSetcLtImmediate(w2Uop.opcode) - val branchIsSetcLtAny = branchIsSetcLt || branchIsSetcLti - val branchIsSetcGeRegister = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_GE) - val branchIsSetcGeImmediate = isSetcGeImmediate(w2Uop.opcode) - val branchIsSetcGe = branchIsSetcGeRegister || branchIsSetcGeImmediate - val branchIsSetcLtu = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_LTU) - val branchIsSetcGeuRegister = w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_GEU) - val branchIsSetcGeuImmediate = isSetcGeuImmediate(w2Uop.opcode) - val branchIsSetcGeu = branchIsSetcGeuRegister || branchIsSetcGeuImmediate - val branchIsSetcLtui = isSetcLtuImmediate(w2Uop.opcode) - val branchIsSetcTgt = - w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_TGT) || - w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SETC_TGT) - val w2BranchConditionValid = - w2CompleteFire && ( - branchIsSetcEq || branchIsSetcNe || branchIsSetcAndi || branchIsSetcOri || - branchIsSetcLtAny || branchIsSetcGe || branchIsSetcLtu || branchIsSetcGeu || - branchIsSetcLtui || branchIsSetcTgt) - val branchEqNeSrc1 = - Mux(branchIsSetcEqImmediate || branchIsSetcNeImmediate, - branchSetcImmediate, - Mux(branchIsSetcEqRegister || branchIsSetcNeRegister, branchSetcRegisterSrc1, branchSrc1)) - val w2BranchConditionTaken = Wire(Bool()) - w2BranchConditionTaken := false.B - when(branchIsSetcTgt) { - w2BranchConditionTaken := branchTargetValid - }.elsewhen(branchIsSetcEq) { - w2BranchConditionTaken := branchSrc0 === branchEqNeSrc1 - }.elsewhen(branchIsSetcNe) { - w2BranchConditionTaken := branchSrc0 =/= branchEqNeSrc1 - }.elsewhen(branchIsSetcAndi) { - w2BranchConditionTaken := (branchSrc0 & branchSetcImmediate) =/= 0.U - }.elsewhen(branchIsSetcOri) { - w2BranchConditionTaken := (branchSrc0 | branchSetcImmediate) =/= 0.U - }.elsewhen(branchIsSetcLt) { - w2BranchConditionTaken := branchSrc0.asSInt < branchSetcRegisterSrc1.asSInt - }.elsewhen(branchIsSetcLti) { - w2BranchConditionTaken := branchSrc0.asSInt < branchSetcImmediate.asSInt - }.elsewhen(branchIsSetcGe) { - w2BranchConditionTaken := branchSrc0.asSInt >= Mux(branchIsSetcGeImmediate, branchSetcImmediate, branchSetcRegisterSrc1).asSInt - }.elsewhen(branchIsSetcLtu) { - w2BranchConditionTaken := branchSrc0 < branchSetcRegisterSrc1 - }.elsewhen(branchIsSetcGeu) { - w2BranchConditionTaken := branchSrc0 >= Mux(branchIsSetcGeuImmediate, branchSetcImmediate, branchSetcRegisterSrc1) - }.elsewhen(branchIsSetcLtui) { - w2BranchConditionTaken := branchSrc0 < branchSetcImmediate - } - // An explicit not-taken condition selects the synthetic RA-load form. An - // absent condition instead keeps a live SETC/marker target authoritative; - // if neither target owner exists, the only defined FRET.STK continuation is - // the synthetic RA return. - val eFretStkContextValid = eUop.fretStkContextValid - val eFretStkLiveConditionValid = io.fretStkConditionValid || w2BranchConditionValid - val eFretStkLiveConditionTaken = Mux(w2BranchConditionValid, w2BranchConditionTaken, io.fretStkConditionTaken) - val eFretStkConditionValid = Mux(eFretStkContextValid, eUop.fretStkConditionValid, eFretStkLiveConditionValid) - val eFretStkConditionTaken = Mux(eFretStkContextValid, eUop.fretStkConditionTaken, eFretStkLiveConditionTaken) - val eFretStkFallbackTargetValid = - Mux(eFretStkContextValid, eUop.fretStkFallbackTargetValid, io.fretStkFallbackTargetValid) - val eFretStkFallbackTarget = - Mux(eFretStkContextValid, eUop.fretStkFallbackTarget, io.fretStkFallbackTarget) - val eSetcTargetValid = - setcTargetValid && setcTargetBlockBidValid && eUop.blockBidValid && - setcTargetBlockBid === eUop.blockBid - val eFretStkHasRedirectTarget = eSetcTargetValid || eFretStkFallbackTargetValid - val eFretStkConditionAllowsLoad = - (eFretStkConditionValid && !eFretStkConditionTaken) || - (!eFretStkConditionValid && !eFretStkHasRedirectTarget) - val eFretStkLoadReturn = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_FRET_STK) && - eFretStkConditionAllowsLoad && - fretStkRestoresRa(eUop.insnRaw) - val eLoadLookupValid = - !io.flushValid && eValid && - (eLoadC || eLoadByte || eLoadReg || eLoadI || eLoadHalfI || eLoadWordI || - eLoadPcr || eLoadPairSecond || eLoadHlLongOffset || eFretStkLoadReturn) - val eLoadLookupAddr = Mux( - eFretStkLoadReturn, - fretStkRaLoadAddr(eStackPointerData, eUop.imm), - Mux( - eLoadPcr, - pcrLoadAddr(eUop.pc, eUop.imm), - Mux( - eLoadPairSecond, - hlImmediateLoadPairSecondAddr(eUop.opcode, eSrcData, eUop.imm), - Mux( - eLoadHlLongOffset, - hlLongOffsetLoadAddr(eUop.opcode, eSrcData, eUop.imm), - Mux( - eLoadReg, - loadRegAddr(eSrcData, eUop.insnRaw), - Mux( - eLoadByte, - Mux(eLoadByteR, loadByteRegAddr(eSrcData, eUop.insnRaw), loadByteImmAddr(eSrcData, eUop.imm)), - Mux( - eLoadWordI, - Mux(eLoadLwi || eLoadLwui, lwiScaledAddr(eSrcData, eUop.imm), lwiUnscaledAddr(eSrcData, eUop.imm)), - Mux( - eLoadHalfI, - loadHalfImmAddr(eSrcData, eUop.imm), - Mux( - eLoadI, - ldiAddr(eSrcData, eUop.imm), - Mux(eLoadCLwi, cLwiAddr(eSrcData, eUop.imm), cLdiAddr(eSrcData, eUop.imm))))))))))) - val eLoadPcrByte = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LB_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LBU_PCR) - val eLoadPcrWord = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LW_PCR) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_HL_LWU_PCR) - val eLoadRegHalf = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LH) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LHU) - val eLoadRegWord = - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LW) || - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LR_W) - val eLoadLookupSize = - Mux( - eLoadByte || eLoadPcrByte, - 1.U(p.memSizeWidth.W), - Mux( - eLoadHalfI || eLoadRegHalf, - 2.U(p.memSizeWidth.W), - Mux( - eLoadPairSecond, - hlImmediateLoadPairSize(eUop.opcode), - Mux( - eLoadHlLongOffset, - hlLongOffsetLoadSize(eUop.opcode), - Mux( - eLoadCLwi || eLoadWordI || eLoadRegWord || eLoadPcrWord, - 4.U(p.memSizeWidth.W), - 8.U(p.memSizeWidth.W)))))) - val w2LoadByteRLookup = - w2CompleteValid && - (w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LB) || - w2Uop.opcode === opcode(FrontendOpcodeDecodeTable.OP_LBU)) - // E1 consumes the returned lookup data combinationally when it advances to - // W1, so an older W2 byte-replay must never steal the single external read - // port from a younger E1 load. This matters for adjacent loads: otherwise - // E1 can latch the older address's byte while still reporting its own - // address in the completion row. - val lookupReplayValid = !io.flushValid && w2LoadByteRLookup && !eLoadLookupValid - val lookupValid = eLoadLookupValid || lookupReplayValid - val lookupUop = Wire(new RenamedUop(p)) - lookupUop := Mux(lookupReplayValid, w2Uop, eUop) - val lookupSrcData = Wire(Vec(3, UInt(p.immWidth.W))) - for (idx <- 0 until 3) { - lookupSrcData(idx) := Mux(lookupReplayValid, w2SrcData(idx), eSrcData(idx)) - } - val lookupAddr = Mux(lookupReplayValid, loadByteRegAddr(w2SrcData, w2Uop.insnRaw), eLoadLookupAddr) - val lookupSize = Mux(lookupReplayValid, 1.U(p.memSizeWidth.W), eLoadLookupSize) - val lookupFretStkLoadReturn = eFretStkLoadReturn && !lookupReplayValid - io.loadLookupValid := lookupValid - io.loadLookupAddr := Mux(lookupValid, lookupAddr, 0.U) - io.loadPairFirstLookupValid := eLoadLookupValid && eLoadPairSecond - io.loadPairFirstLookupAddr := - Mux(io.loadPairFirstLookupValid, - hlImmediateLoadPairFirstAddr(eUop.opcode, eSrcData, eUop.imm), - 0.U) - io.loadLookupSize := Mux(io.loadLookupValid, lookupSize, 0.U) - io.loadLookupReturnSignExtend := io.loadLookupValid && loadReturnSignExtend(lookupUop.opcode) - // FRET.STK's optional RA read has architectural effects beyond a normal - // load: it synthesizes the RA destination, restores SP, and redirects. - // Keep that return on the direct execute path until LIQ owns all of those - // effects as one transaction. - val eLoadLiqEligible = - eLoadLookupValid && - !eFretStkLoadReturn && - !eLoadPairSecond && - (eUop.opcode =/= opcode(FrontendOpcodeDecodeTable.OP_LR_W)) - io.loadLiqEligible := eLoadLiqEligible || lookupReplayValid - io.loadLookupPc := Mux(io.loadLookupValid, lookupUop.pc, 0.U) - io.loadLookupBid := Mux(io.loadLookupValid, lookupUop.bid, ROBID.disabled(p.robEntries)) - io.loadLookupGid := Mux(io.loadLookupValid, lookupUop.gid, ROBID.disabled(p.robEntries)) - io.loadLookupRid := Mux(io.loadLookupValid, lookupUop.rid, ROBID.disabled(p.robEntries)) - io.loadLookupLsId := Mux(io.loadLookupValid, lookupUop.lsid, 0.U) - val noLoadLookupDst = Wire(new RenamedDestination(p)) - noLoadLookupDst := 0.U.asTypeOf(noLoadLookupDst) - noLoadLookupDst.kind := DestinationKind.None - io.loadLookupDst := Mux(io.loadLookupValid, lookupUop.dst(0), noLoadLookupDst) - val loadLookupSourceTraceValid = io.loadLookupValid && !lookupFretStkLoadReturn - io.loadLookupSourceTraceValid := loadLookupSourceTraceValid - io.loadLookupSource0 := 0.U.asTypeOf(io.loadLookupSource0) - io.loadLookupSource1 := 0.U.asTypeOf(io.loadLookupSource1) - when(loadLookupSourceTraceValid) { - io.loadLookupSource0.valid := lookupUop.src(0).valid && (lookupUop.src(0).operandClass === OperandClass.P) - io.loadLookupSource0.reg := fitReg(lookupUop.src(0).archTag) - io.loadLookupSource0.data := lookupSrcData(0) - io.loadLookupSource1.valid := lookupUop.src(1).valid && (lookupUop.src(1).operandClass === OperandClass.P) - io.loadLookupSource1.reg := fitReg(lookupUop.src(1).archTag) - io.loadLookupSource1.data := lookupSrcData(1) - } - // A live-LIQ load is retired from E1 only after the allocator handshake. - // In that mode LIQ, not the direct execute lookup, owns store-forward waits. - val eLoadLiqRetire = eLoadLiqEligible && io.loadLiqEnable && io.loadLiqAccepted - val eLoadWaitHold = - eLoadLookupValid && Mux(eLoadLiqEligible && io.loadLiqEnable, !io.loadLiqAccepted, io.loadLookupWaitBlocked) - val eIsDivideOrRemainder = eValid && isDivideOrRemainder(eUop.opcode) - val divider = Module(new ReducedScalarDivider) - divider.io.reqValid := eIsDivideOrRemainder - divider.io.lhs := eSrcData(0) - divider.io.rhs := eSrcData(1) - divider.io.signed := isSignedDivideOrRemainder(eUop.opcode) - divider.io.word := isWordDivideOrRemainder(eUop.opcode) - divider.io.remainder := isRemainder(eUop.opcode) - divider.io.flush := io.flushValid - val eDivideComplete = eIsDivideOrRemainder && divider.io.respValid - divider.io.respReady := eDivideComplete - val eDivideHold = eIsDivideOrRemainder && !divider.io.respValid - val scalarFp = Module(new ReducedScalarFpExecute) - val eIsScalarFp = eValid && isScalarFp(eUop.opcode) - scalarFp.io.inValid := eIsScalarFp - scalarFp.io.opcode := eUop.opcode - scalarFp.io.insnRaw := eUop.insnRaw(31, 0) - scalarFp.io.srcL := eSrcData(0) - scalarFp.io.srcR := eSrcData(1) - scalarFp.io.flush := io.flushValid - scalarFp.io.outReady := true.B - val eResult = Mux( - eIsDivideOrRemainder, - divider.io.result, - Mux( - eIsScalarFp, - scalarFp.io.outData, - Mux( - eUop.opcode === opcode(FrontendOpcodeDecodeTable.OP_SSRGET), - cycleCounter, - resultFor(eUop.opcode, eUop.pc, eUop.insnRaw, eSrcData, eUop.imm, io.loadLookupData, eStackPointerData)))) - val ePairFirstResult = - resultFor( - eUop.opcode, - eUop.pc, - eUop.insnRaw, - eSrcData, - eUop.imm, - io.loadPairFirstLookupData, - eStackPointerData) - val eSupported = eValid && isSupported(eUop.opcode) && (!eIsScalarFp || !scalarFp.io.unsupported) - val eCanAdvanceToW1 = !eLoadWaitHold && !eDivideHold - val pipeSafeAdvanceReady = - eValid && eCanAdvanceToW1 && ScalarPipeSafety.fixedScalarAlu(eUop) && ScalarPipeSafety.fixedScalarAlu(io.in) - val earlyReleaseCapture = accept && ScalarPipeSafety.fixedScalarAlu(io.in) - - when(io.flushValid) { - eValid := false.B - w1Valid := false.B - w2Valid := false.B - eEarlyReleased := false.B - w1EarlyReleased := false.B - w2EarlyReleased := false.B - setcTargetValid := false.B - setcTarget := 0.U - setcTargetBlockBidValid := false.B - setcTargetBlockBid := 0.U - }.elsewhen(w2RetainForCompletion) { - w2Valid := w2Valid - w2EarlyReleased := w2EarlyReleased - }.otherwise { - w2Valid := w1Valid - w2Uop := w1Uop - w2SrcData := w1SrcData - w2Result := w1Result - w2PairFirstResult := w1PairFirstResult - w2Supported := w1Supported - w2StackPointerData := w1StackPointerData - w2FretStkLoadReturn := w1FretStkLoadReturn - w2FretStkConditionValid := w1FretStkConditionValid - w2FretStkConditionTaken := w1FretStkConditionTaken - w2FretStkFallbackTargetValid := w1FretStkFallbackTargetValid - w2FretStkFallbackTarget := w1FretStkFallbackTarget - w2EarlyReleased := w1EarlyReleased - - when(!eCanAdvanceToW1) { - w1Valid := false.B - w1EarlyReleased := false.B - }.otherwise { - w1Valid := eValid && !eLoadLiqRetire - w1Uop := eUop - w1SrcData := eSrcData - w1Result := eResult - w1PairFirstResult := ePairFirstResult - w1Supported := eSupported - w1StackPointerData := eStackPointerData - w1FretStkLoadReturn := eFretStkLoadReturn - w1FretStkConditionValid := eFretStkConditionValid - w1FretStkConditionTaken := eFretStkConditionTaken - w1FretStkFallbackTargetValid := eFretStkFallbackTargetValid - w1FretStkFallbackTarget := eFretStkFallbackTarget - w1EarlyReleased := eEarlyReleased && !eLoadLiqRetire - - eValid := accept - when(accept) { - eUop := io.in - eSrcData := io.srcData - eStackPointerData := io.stackPointerData - eEarlyReleased := earlyReleaseCapture - }.otherwise { - eEarlyReleased := false.B - } - } - } - - when(io.flushValid) { - earlyReleasePendingValid := false.B - earlyReleasePendingBid := ROBID.disabled(p.robEntries) - earlyReleasePendingGid := ROBID.disabled(p.robEntries) - earlyReleasePendingRid := ROBID.disabled(p.robEntries) - earlyReleasePendingStid := 0.U - }.elsewhen(w2RetainForCompletion) { - earlyReleasePendingValid := false.B - }.otherwise { - earlyReleasePendingValid := earlyReleaseCapture - when(earlyReleaseCapture) { - earlyReleasePendingBid := io.in.bid - earlyReleasePendingGid := io.in.gid - earlyReleasePendingRid := io.in.rid - earlyReleasePendingStid := io.in.threadId - } - } - - io.inReady := - !io.flushValid && !w2RetainForCompletion && (!eValid || eLoadLiqRetire || eDivideComplete || pipeSafeAdvanceReady) - io.accepted := accept - io.busy := !io.flushValid && (eValid || w1Valid || w2Valid) - io.loadWaitHold := !io.flushValid && eLoadWaitHold - io.completeValid := w2CompleteValid - io.completeFire := w2CompleteFire - io.completeAccepted := w2CompleteFire - io.completeRobValue := w2Uop.rid.value - io.completePeId := Mux(io.completeValid, w2Uop.peId, 0.U) - io.completeStid := Mux(io.completeValid, w2Uop.threadId, 0.U) - io.completeTid := Mux(io.completeValid, w2Uop.threadId, 0.U) - io.completeUop := w2Uop - io.completeLsId := Mux(io.completeValid, w2Uop.lsid, 0.U) - val w2FretStkConditionAllowsTarget = !w2FretStkConditionValid || w2FretStkConditionTaken - val w2SetcTargetValid = - setcTargetValid && setcTargetBlockBidValid && w2Uop.blockBidValid && - setcTargetBlockBid === w2Uop.blockBid - val w2FretStkTargetTaken = - (w2SetcTargetValid || w2FretStkFallbackTargetValid) && w2FretStkConditionAllowsTarget - val w2FretStkTarget = Mux(w2SetcTargetValid, setcTarget, w2FretStkFallbackTarget) - io.completeRow := completionRow( - w2Uop, - w2SrcData, - w2Result, - io.completeValid, - w2SetcTargetValid && w2FretStkConditionAllowsTarget, - setcTarget, - w2FretStkFallbackTargetValid && w2FretStkConditionAllowsTarget, - w2FretStkFallbackTarget, - w2FretStkLoadReturn, - w2StackPointerData) - io.completeDstPhysValid := - io.completeFire && - Mux(w2FretStkLoadReturn, true.B, w2Uop.dst(0).valid && (w2Uop.dst(0).kind === DestinationKind.Gpr)) - io.completeDstPhysTag := Mux(w2FretStkLoadReturn, 10.U(p.physRegWidth.W), w2Uop.dst(0).physTag) - io.completeDstData := w2Result - io.completePairFirstDstPhysValid := - io.completeFire && - w2Uop.pairFirstDst.valid && - (w2Uop.pairFirstDst.kind === DestinationKind.Gpr) - io.completePairFirstDstPhysTag := w2Uop.pairFirstDst.physTag - io.completePairFirstDstData := w2PairFirstResult - for (idx <- 0 until 3) { - io.completeSrcPhysValid(idx) := - io.completeFire && w2Uop.src(idx).valid && (w2Uop.src(idx).operandClass === OperandClass.P) && - (idx.U =/= 1.U || traceUsesSrc1(w2Uop.opcode)) - io.completeSrcPhysTag(idx) := w2Uop.src(idx).physTag - } - io.fretStkSpRestoreValid := io.completeFire && w2FretStkLoadReturn - io.fretStkSpRestoreData := w2StackPointerData + w2Uop.imm - val w2ScalarSpAccess = ScalarSpAccess.classify(w2Uop) - io.scalarSpTerminalValid := io.completeFire && w2ScalarSpAccess.valid - io.scalarSpTerminal := 0.U.asTypeOf(new ScalarSpTransaction(p)) - io.scalarSpTerminal.access := w2ScalarSpAccess - io.scalarSpTerminal.stid := w2Uop.threadId - io.scalarSpTerminal.bid := w2Uop.bid - io.scalarSpTerminal.rid := w2Uop.rid - io.scalarSpTerminal.epoch := 0.U - io.scalarSpProducedValid := io.scalarSpTerminalValid && w2ScalarSpAccess.write - io.scalarSpProducedData := Mux( - w2IsFretStk, - Mux(w2FretStkLoadReturn, w2StackPointerData + w2Uop.imm, w2StackPointerData), - Mux( - w2Uop.pairFirstDst.valid && (w2Uop.pairFirstDst.archTag === 1.U), - w2PairFirstResult, - w2Result)) - // A resident W2 row may be held while ROB completion is backpressured. - // Branch resolution is an architectural side effect and must publish once, - // together with the accepted completion, rather than once per held cycle. - io.branchConditionValid := io.completeFire && w2BranchConditionValid - io.branchConditionTaken := w2BranchConditionTaken - io.branchConditionIsTarget := w2BranchConditionValid && branchIsSetcTgt - io.branchConditionTarget := branchSrc0(p.pcWidth - 1, 0) - io.branchConditionUop := w2Uop - io.redirectValid := io.completeFire && w2IsFretStk && (w2FretStkLoadReturn || w2FretStkTargetTaken) - io.redirectPc := Mux(w2FretStkLoadReturn, w2Result(p.pcWidth - 1, 0), w2FretStkTarget) - io.redirectOrder := w2Uop.uid.uid - when(io.completeFire && branchIsSetcTgt) { - setcTargetValid := branchTargetValid - setcTarget := branchSrc0(p.pcWidth - 1, 0) - setcTargetBlockBidValid := w2Uop.blockBidValid - setcTargetBlockBid := w2Uop.blockBid - }.elsewhen(io.completeFire && w2IsFretStk) { - setcTargetValid := false.B - setcTarget := 0.U - setcTargetBlockBidValid := false.B - setcTargetBlockBid := 0.U - } - io.releaseValid := (io.completeFire && !w2EarlyReleased) || w2UnsupportedDrain - io.releaseBid := w2Uop.bid - io.releaseGid := w2Uop.gid - io.releaseRid := w2Uop.rid - io.releaseStid := w2Uop.threadId - io.earlyReleaseValid := !io.flushValid && earlyReleasePendingValid - io.earlyReleaseBid := Mux(io.earlyReleaseValid, earlyReleasePendingBid, ROBID.disabled(p.robEntries)) - io.earlyReleaseGid := Mux(io.earlyReleaseValid, earlyReleasePendingGid, ROBID.disabled(p.robEntries)) - io.earlyReleaseRid := Mux(io.earlyReleaseValid, earlyReleasePendingRid, ROBID.disabled(p.robEntries)) - io.earlyReleaseStid := Mux(io.earlyReleaseValid, earlyReleasePendingStid, 0.U) - // A first-pass live load hands its completion ownership to LIQ in E1, so - // it must release its issue-queue residency there rather than waiting for a - // W2 row that will intentionally never exist. Keep this a separate port: - // a W2 completion and an E1 LIQ handoff may occur in the same cycle. - io.liqReleaseValid := !io.flushValid && eLoadLiqRetire - io.liqReleaseBid := Mux(io.liqReleaseValid, eUop.bid, ROBID.disabled(p.robEntries)) - io.liqReleaseRid := Mux(io.liqReleaseValid, eUop.rid, ROBID.disabled(p.robEntries)) - io.liqReleaseStid := Mux(io.liqReleaseValid, eUop.threadId, 0.U) - io.unsupported := w2UnsupportedDrain - io.unsupportedOpcode := w2Uop.opcode -} - -object ReducedScalarAluExecute { - private val Mask64 = (BigInt(1) << 64) - 1 - private val Mask32 = (BigInt(1) << 32) - 1 - private val SignBit64 = BigInt(1) << 63 - private val SignBit32 = BigInt(1) << 31 - private val NoModifierInsn = BigInt(3) << 25 - - def referenceLoadLookupOwner(e1LoadValid: Boolean, w2ByteReplayValid: Boolean): String = - if (e1LoadValid) "e1" else if (w2ByteReplayValid) "w2-replay" else "none" - - def referenceHlImmediateLoadPairSecondAddress(opcode: Int, base: BigInt, imm: BigInt): BigInt = { - val size = - if (Set(FrontendOpcodeDecodeTable.OP_HL_LBIP, FrontendOpcodeDecodeTable.OP_HL_LBUIP).contains(opcode)) 1 - else if (Set( - FrontendOpcodeDecodeTable.OP_HL_LHIP, - FrontendOpcodeDecodeTable.OP_HL_LHIP_U, - FrontendOpcodeDecodeTable.OP_HL_LHUIP, - FrontendOpcodeDecodeTable.OP_HL_LHUIP_U).contains(opcode)) 2 - else if (Set( - FrontendOpcodeDecodeTable.OP_HL_LWIP, - FrontendOpcodeDecodeTable.OP_HL_LWIP_U, - FrontendOpcodeDecodeTable.OP_HL_LWUIP, - FrontendOpcodeDecodeTable.OP_HL_LWUIP_U).contains(opcode)) 4 - else 8 - val unscaled = Set( - FrontendOpcodeDecodeTable.OP_HL_LHIP_U, - FrontendOpcodeDecodeTable.OP_HL_LHUIP_U, - FrontendOpcodeDecodeTable.OP_HL_LWIP_U, - FrontendOpcodeDecodeTable.OP_HL_LWUIP_U, - FrontendOpcodeDecodeTable.OP_HL_LDIP_U).contains(opcode) - (base + (if (unscaled) signed64(imm) else signed64(imm) * size) + size) & Mask64 - } - - private def signed64(value: BigInt): BigInt = { - val masked = value & Mask64 - if ((masked & SignBit64) != 0) masked - (BigInt(1) << 64) else masked - } - - private def signedN(value: BigInt, width: Int): BigInt = { - val mask = (BigInt(1) << width) - 1 - val signBit = BigInt(1) << (width - 1) - val masked = value & mask - if ((masked & signBit) != 0) masked - (BigInt(1) << width) else masked - } - - private def signed32(value: BigInt): BigInt = { - signedN(value, 32) - } - - private def divisionResult( - src0: BigInt, - src1: BigInt, - signedOperation: Boolean, - wordOperation: Boolean, - remainderOperation: Boolean): BigInt = { - val width = if (wordOperation) 32 else 64 - val mask = (BigInt(1) << width) - 1 - val lhsBits = src0 & mask - val rhsBits = src1 & mask - val lhs = if (signedOperation) signedN(lhsBits, width) else lhsBits - val rhs = if (signedOperation) signedN(rhsBits, width) else rhsBits - val domainResult = - if (rhsBits == 0) { - if (remainderOperation) lhsBits else BigInt(0) - } else if (remainderOperation) { - lhs - ((lhs / rhs) * rhs) - } else { - lhs / rhs - } - val resultBits = domainResult & mask - if (wordOperation) signed32(resultBits) & Mask64 else resultBits & Mask64 - } - - def referenceResult( - opcode: Int, - src0: BigInt, - src1: BigInt, - imm: BigInt): Option[BigInt] = - referenceResultWithLoad(opcode, src0, src1, imm, loadData = 0) - - def referenceResultWithLoad( - opcode: Int, - src0: BigInt, - src1: BigInt, - imm: BigInt, - loadData: BigInt): Option[BigInt] = - referenceResultWithInsn(opcode, NoModifierInsn, src0, src1, imm, loadData) - - def referenceResultWithInsn( - opcode: Int, - insnRaw: BigInt, - src0: BigInt, - src1: BigInt, - imm: BigInt, - loadData: BigInt = 0): Option[BigInt] = { - val addSubR = addSubSrcR(insnRaw, src1) - val logicR = logicSrcR(insnRaw, src1) - opcode match { - case FrontendOpcodeDecodeTable.OP_ADD => Some((src0 + addSubR) & Mask64) - case FrontendOpcodeDecodeTable.OP_ADDW => - val low32 = (src0 + addSubR) & ((BigInt(1) << 32) - 1) - Some(signed32(low32) & Mask64) - case FrontendOpcodeDecodeTable.OP_SUB => Some((src0 - addSubR) & Mask64) - case FrontendOpcodeDecodeTable.OP_SUBW => Some(signed32((src0 - addSubR) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_ADDI => Some((src0 + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_ADDIW => - val low32 = ((src0 & ((BigInt(1) << 32) - 1)) + (imm & 0xfff)) & ((BigInt(1) << 32) - 1) - Some(signed32(low32) & Mask64) - case FrontendOpcodeDecodeTable.OP_SUBI => Some((src0 - imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_SUBIW => - Some(signed32(((src0 & Mask32) - (imm & 0xfff)) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_AND => Some((src0 & logicR) & Mask64) - case FrontendOpcodeDecodeTable.OP_ANDW => - val low32 = (src0 & logicR) & ((BigInt(1) << 32) - 1) - Some(signed32(low32) & Mask64) - case FrontendOpcodeDecodeTable.OP_ANDI => Some((src0 & imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_ANDIW => - val low32 = (src0 & imm) & ((BigInt(1) << 32) - 1) - Some(signed32(low32) & Mask64) - case FrontendOpcodeDecodeTable.OP_ADDTPC => None - case FrontendOpcodeDecodeTable.OP_SETRET => None - case FrontendOpcodeDecodeTable.OP_HL_SETRET => None - case FrontendOpcodeDecodeTable.OP_C_MOVI => Some(imm & Mask64) - case FrontendOpcodeDecodeTable.OP_C_MOVR => Some(src0 & Mask64) - case FrontendOpcodeDecodeTable.OP_C_ADD => Some((src0 + src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_ADDI => Some((src0 + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SLLI => Some((src0 << (imm.toInt & 0x1f)) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SRLI => Some((src0 & Mask64) >> (imm.toInt & 0x1f)) - case FrontendOpcodeDecodeTable.OP_C_AND => Some((src0 & src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_OR => Some((src0 | src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SUB => Some((src0 - src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SEXT_B => Some(signedN(src0, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SEXT_H => Some(signedN(src0, 16) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SEXT_W => Some(signed32(src0) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_ZEXT_B => Some(src0 & 0xff) - case FrontendOpcodeDecodeTable.OP_C_ZEXT_H => Some(src0 & 0xffff) - case FrontendOpcodeDecodeTable.OP_C_ZEXT_W => Some(src0 & ((BigInt(1) << 32) - 1)) - case FrontendOpcodeDecodeTable.OP_C_SETRET => None - case FrontendOpcodeDecodeTable.OP_C_CMP_EQI => Some(if ((src0 & Mask64) == (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_C_CMP_NEI => Some(if ((src0 & Mask64) != (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_AND => Some(if (((src0 & logicR) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_ANDI => Some(if (((src0 & imm) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_EQ => Some(if ((src0 & Mask64) == (addSubR & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_EQI => Some(if ((src0 & Mask64) == (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_GE => Some(if (signed64(src0) >= signed64(addSubR)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_GEI => Some(if (signed64(src0) >= signed64(imm)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_GEU => Some(if ((src0 & Mask64) >= (addSubR & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_GEUI => Some(if ((src0 & Mask64) >= (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_LT => Some(if (signed64(src0) < signed64(addSubR)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_LTI => Some(if (signed64(src0) < signed64(imm)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_LTU => Some(if ((src0 & Mask64) < (addSubR & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_LTUI => Some(if ((src0 & Mask64) < (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_NE => Some(if ((src0 & Mask64) != (addSubR & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_NEI => Some(if ((src0 & Mask64) != (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_OR => Some(if (((src0 | logicR) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_CMP_ORI => Some(if (((src0 | imm) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_C_LDI => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_C_LWI => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_LB => Some(signedN(loadData, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_LBI => Some(signedN(loadData, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_LBU => Some(loadData & 0xFF) - case FrontendOpcodeDecodeTable.OP_LBUI => Some(loadData & 0xFF) - case FrontendOpcodeDecodeTable.OP_LD => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_LH => Some(signedN(loadData, 16) & Mask64) - case FrontendOpcodeDecodeTable.OP_LHU => Some(loadData & 0xffff) - case FrontendOpcodeDecodeTable.OP_LW => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_LR_W => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_LWUI => Some(loadData & Mask32) - case FrontendOpcodeDecodeTable.OP_HL_LBIP => Some(signedN(loadData, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LBUIP => Some(loadData & 0xff) - case FrontendOpcodeDecodeTable.OP_HL_LHIP | FrontendOpcodeDecodeTable.OP_HL_LHIP_U => - Some(signedN(loadData, 16) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LHUIP | FrontendOpcodeDecodeTable.OP_HL_LHUIP_U => - Some(loadData & 0xffff) - case FrontendOpcodeDecodeTable.OP_HL_LWIP | FrontendOpcodeDecodeTable.OP_HL_LWIP_U => - Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LWUIP | FrontendOpcodeDecodeTable.OP_HL_LWUIP_U => - Some(loadData & Mask32) - case FrontendOpcodeDecodeTable.OP_HL_LDIP | FrontendOpcodeDecodeTable.OP_HL_LDIP_U => - Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LBI => Some(signedN(loadData, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LBUI => Some(loadData & 0xff) - case FrontendOpcodeDecodeTable.OP_HL_LHI | FrontendOpcodeDecodeTable.OP_HL_LHI_U => - Some(signedN(loadData, 16) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LHUI | FrontendOpcodeDecodeTable.OP_HL_LHUI_U => - Some(loadData & 0xffff) - case FrontendOpcodeDecodeTable.OP_HL_LWI | FrontendOpcodeDecodeTable.OP_HL_LWI_U => - Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LWUI | FrontendOpcodeDecodeTable.OP_HL_LWUI_U => - Some(loadData & Mask32) - case FrontendOpcodeDecodeTable.OP_HL_LDI | FrontendOpcodeDecodeTable.OP_HL_LDI_U => - Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SDI => Some(0) - case FrontendOpcodeDecodeTable.OP_C_SWI => Some(0) - case FrontendOpcodeDecodeTable.OP_C_SETC_EQ => Some(0) - case FrontendOpcodeDecodeTable.OP_C_SETC_NE => Some(0) - case FrontendOpcodeDecodeTable.OP_C_SETC_TGT => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_ANDI | FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_EQ => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_EQI | FrontendOpcodeDecodeTable.OP_HL_SETC_EQI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_NE => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_NEI | FrontendOpcodeDecodeTable.OP_HL_SETC_NEI => Some(0) - case FrontendOpcodeDecodeTable.OP_FRET_STK => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_SETC_LT => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_LTI | FrontendOpcodeDecodeTable.OP_HL_SETC_LTI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_GE => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_GEI | FrontendOpcodeDecodeTable.OP_HL_SETC_GEI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_LTU => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_GEU => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_GEUI | FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_LTUI | FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_ORI | FrontendOpcodeDecodeTable.OP_HL_SETC_ORI => Some(0) - case FrontendOpcodeDecodeTable.OP_SETC_TGT => Some(0) - case FrontendOpcodeDecodeTable.OP_FENTRY => Some((src1 - imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_LUI => Some(imm & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LUI => Some(imm & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LIS => Some(imm & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LIU => Some(imm & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_ADDI => Some((src0 + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_ADDIW => Some(signed32((src0 + imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_ANDI => Some((src0 & imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_ANDIW => Some(signed32((src0 & imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_CMP_ANDI => Some(if (((src0 & imm) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_EQI => Some(if ((src0 & Mask64) == (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_GEI => Some(if (signed64(src0) >= signed64(imm)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_GEUI => Some(if ((src0 & Mask64) >= (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_LTI => Some(if (signed64(src0) < signed64(imm)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_LTUI => Some(if ((src0 & Mask64) < (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_NEI => Some(if ((src0 & Mask64) != (imm & Mask64)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_CMP_ORI => Some(if (((src0 | imm) & Mask64) != 0) 1 else 0) - case FrontendOpcodeDecodeTable.OP_HL_ORI => Some((src0 | imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_ORIW => Some(signed32((src0 | imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SUBI => Some((src0 - imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SUBIW => Some(signed32((src0 - imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_XORI => Some((src0 ^ imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_XORIW => Some(signed32((src0 ^ imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LD_PCR => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LB_PCR => Some(signedN(loadData, 8) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LBU_PCR => Some(loadData & 0xff) - case FrontendOpcodeDecodeTable.OP_HL_LW_PCR => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_LWU_PCR => Some(loadData & Mask32) - case FrontendOpcodeDecodeTable.OP_HL_SB_PCR => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SD_PCR => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SH_PCR => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SW_PCR => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SDI_PO => Some((src1 + ((imm << 3) & Mask64)) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SDI_PR => Some((src1 + ((imm << 3) & Mask64)) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SWI_PO => Some((src1 + ((imm << 2) & Mask64)) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SWIP => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SWIP_U => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SDIP => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SDIP_U => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SBI => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SDI => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SDI_U => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SHI => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SHI_U => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SWI => Some(0) - case FrontendOpcodeDecodeTable.OP_HL_SWI_U => Some(0) - case FrontendOpcodeDecodeTable.OP_LD_PCR => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_LDI => Some(loadData & Mask64) - case FrontendOpcodeDecodeTable.OP_LHI => Some(signedN(loadData, 16) & Mask64) - case FrontendOpcodeDecodeTable.OP_LHUI => Some(loadData & 0xffff) - case FrontendOpcodeDecodeTable.OP_LWI => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_LWI_U => Some(signed32(loadData) & Mask64) - case FrontendOpcodeDecodeTable.OP_DIV => Some(divisionResult(src0, src1, signedOperation = true, wordOperation = false, remainderOperation = false)) - case FrontendOpcodeDecodeTable.OP_DIVU => Some(divisionResult(src0, src1, signedOperation = false, wordOperation = false, remainderOperation = false)) - case FrontendOpcodeDecodeTable.OP_DIVW => Some(divisionResult(src0, src1, signedOperation = true, wordOperation = true, remainderOperation = false)) - case FrontendOpcodeDecodeTable.OP_DIVUW => Some(divisionResult(src0, src1, signedOperation = false, wordOperation = true, remainderOperation = false)) - case FrontendOpcodeDecodeTable.OP_MUL => Some((src0 * src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_MULU => Some((src0 * src1) & Mask64) - case FrontendOpcodeDecodeTable.OP_MULW => - val low32 = (src0 * src1) & ((BigInt(1) << 32) - 1) - Some(signed32(low32) & Mask64) - case FrontendOpcodeDecodeTable.OP_MULUW => - val low32 = (src0 * src1) & Mask32 - Some(signed32(low32) & Mask64) - // The public two-source reference helper cannot express MADD's SrcD; - // use referenceMadd for that three-source instruction. - case FrontendOpcodeDecodeTable.OP_BCNT => Some(BigInt(bitField(insnRaw, src0).bitCount) & Mask64) - case FrontendOpcodeDecodeTable.OP_BIC => Some((src0 & ~bitFieldMask(insnRaw)) & Mask64) - case FrontendOpcodeDecodeTable.OP_BIS => Some((src0 | bitFieldMask(insnRaw)) & Mask64) - case FrontendOpcodeDecodeTable.OP_BXS => - val (field, width) = bitFieldWithWidth(insnRaw, src0) - Some(signedN(field, width) & Mask64) - case FrontendOpcodeDecodeTable.OP_BXU => Some(bitField(insnRaw, src0) & Mask64) - case FrontendOpcodeDecodeTable.OP_CLZ => - val (field, width) = bitFieldWithWidth(insnRaw, src0) - Some(BigInt(if (field == 0) width else width - field.bitLength) & Mask64) - case FrontendOpcodeDecodeTable.OP_CTZ => - val (field, width) = bitFieldWithWidth(insnRaw, src0) - Some(BigInt(if (field == 0) width else field.lowestSetBit) & Mask64) - case FrontendOpcodeDecodeTable.OP_MAX => - Some(if (signed64(src0) >= signed64(src1)) src0 & Mask64 else src1 & Mask64) - case FrontendOpcodeDecodeTable.OP_MAXU => - Some(if ((src0 & Mask64) >= (src1 & Mask64)) src0 & Mask64 else src1 & Mask64) - case FrontendOpcodeDecodeTable.OP_MIN => - Some(if (signed64(src0) <= signed64(src1)) src0 & Mask64 else src1 & Mask64) - case FrontendOpcodeDecodeTable.OP_MINU => - Some(if ((src0 & Mask64) <= (src1 & Mask64)) src0 & Mask64 else src1 & Mask64) - case FrontendOpcodeDecodeTable.OP_SB => Some(0) - case FrontendOpcodeDecodeTable.OP_SH => Some(0) - case FrontendOpcodeDecodeTable.OP_SW => Some(0) - case FrontendOpcodeDecodeTable.OP_SBI => Some(0) - case FrontendOpcodeDecodeTable.OP_SD => Some(0) - case FrontendOpcodeDecodeTable.OP_SDI => Some(0) - case FrontendOpcodeDecodeTable.OP_SHI => Some(0) - case FrontendOpcodeDecodeTable.OP_SWI => Some(0) - case FrontendOpcodeDecodeTable.OP_SLL => Some((src0 << ((src1 & 0x3f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SLLI => Some((src0 << ((imm & 0x3f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SLLW => - Some(signed32(((src0 & Mask32) << ((src1 & 0x1f).toInt)) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_SLLIW => - Some(signed32(((src0 & Mask32) << ((imm & 0x1f).toInt)) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRL => Some((src0 & Mask64) >> ((src1 & 0x3f).toInt)) - case FrontendOpcodeDecodeTable.OP_SRLI => Some((src0 & Mask64) >> ((imm & 0x3f).toInt)) - case FrontendOpcodeDecodeTable.OP_SRLW => - Some(signed32((src0 & Mask32) >> ((src1 & 0x1f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRLIW => - Some(signed32((src0 & Mask32) >> ((imm & 0x1f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRA => Some((signed64(src0) >> ((src1 & 0x3f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRAI => Some((signed64(src0) >> ((imm & 0x3f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRAW => - Some((signed32(src0) >> ((src1 & 0x1f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_SRAIW => - Some((signed32(src0) >> ((imm & 0x1f).toInt)) & Mask64) - case FrontendOpcodeDecodeTable.OP_REM => Some(divisionResult(src0, src1, signedOperation = true, wordOperation = false, remainderOperation = true)) - case FrontendOpcodeDecodeTable.OP_REMU => Some(divisionResult(src0, src1, signedOperation = false, wordOperation = false, remainderOperation = true)) - case FrontendOpcodeDecodeTable.OP_REMW => Some(divisionResult(src0, src1, signedOperation = true, wordOperation = true, remainderOperation = true)) - case FrontendOpcodeDecodeTable.OP_REMUW => Some(divisionResult(src0, src1, signedOperation = false, wordOperation = true, remainderOperation = true)) - case FrontendOpcodeDecodeTable.OP_SSRSET => Some(0) - case FrontendOpcodeDecodeTable.OP_SSRGET => None - case FrontendOpcodeDecodeTable.OP_OR => Some((src0 | logicR) & Mask64) - case FrontendOpcodeDecodeTable.OP_ORW => Some(signed32((src0 | logicR) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_ORI => Some((src0 | imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_ORIW => Some(signed32((src0 | imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_XOR => Some((src0 ^ logicR) & Mask64) - case FrontendOpcodeDecodeTable.OP_XORI => Some((src0 ^ imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_XORIW => Some(signed32((src0 ^ imm) & Mask32) & Mask64) - case FrontendOpcodeDecodeTable.OP_XORW => Some(signed32((src0 ^ logicR) & Mask32) & Mask64) - case _ => None - } - } - - private def srcRType(insnRaw: BigInt): Int = - ((insnRaw >> 25) & 0x3).toInt - - private def srcRShamt(insnRaw: BigInt): Int = - ((insnRaw >> 27) & 0x1f).toInt - - private def isHlSetcImmediate(opcode: Int): Boolean = - Set( - FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI, - FrontendOpcodeDecodeTable.OP_HL_SETC_EQI, - FrontendOpcodeDecodeTable.OP_HL_SETC_GEI, - FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI, - FrontendOpcodeDecodeTable.OP_HL_SETC_LTI, - FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI, - FrontendOpcodeDecodeTable.OP_HL_SETC_NEI, - FrontendOpcodeDecodeTable.OP_HL_SETC_ORI).contains(opcode) - - private def setcImmediateShamt(opcode: Int, insnRaw: BigInt): Int = - if (isHlSetcImmediate(opcode)) ((insnRaw >> 23) & 0x1f).toInt - else ((insnRaw >> 7) & 0x1f).toInt - - private def setcShiftedImmediate(opcode: Int, insnRaw: BigInt, imm: BigInt): BigInt = - (imm << setcImmediateShamt(opcode, insnRaw)) & Mask64 - - private def addSubSrcR(insnRaw: BigInt, value: BigInt): BigInt = { - val converted = srcRType(insnRaw) match { - case 0 => signed32(value) & Mask64 - case 1 => value & ((BigInt(1) << 32) - 1) - case 2 => (-value) & Mask64 - case _ => value & Mask64 - } - (converted << srcRShamt(insnRaw)) & Mask64 - } - - private def logicSrcR(insnRaw: BigInt, value: BigInt): BigInt = { - val converted = srcRType(insnRaw) match { - case 0 => signed32(value) & Mask64 - case 1 => value & ((BigInt(1) << 32) - 1) - case 2 => (~value) & Mask64 - case _ => value & Mask64 - } - (converted << srcRShamt(insnRaw)) & Mask64 - } - - private def bitFieldWithWidth(insnRaw: BigInt, value: BigInt): (BigInt, Int) = { - val lsb = ((insnRaw >> 26) & 0x3f).toInt - val width = (((insnRaw >> 20) & 0x3f) + 1).toInt - val rotated = rotateRight64(value, lsb) - (rotated & ((BigInt(1) << width) - 1), width) - } - - private def bitField(insnRaw: BigInt, value: BigInt): BigInt = - bitFieldWithWidth(insnRaw, value)._1 - - private def bitFieldMask(insnRaw: BigInt): BigInt = { - val lsb = ((insnRaw >> 26) & 0x3f).toInt - val width = (((insnRaw >> 20) & 0x3f) + 1).toInt - rotateLeft64((BigInt(1) << width) - 1, lsb) - } - - private def rotateRight64(value: BigInt, amount: Int): BigInt = { - val shift = amount & 0x3f - if (shift == 0) value & Mask64 - else (((value & Mask64) >> shift) | ((value & Mask64) << (64 - shift))) & Mask64 - } - - private def rotateLeft64(value: BigInt, amount: Int): BigInt = { - val shift = amount & 0x3f - if (shift == 0) value & Mask64 - else (((value & Mask64) << shift) | ((value & Mask64) >> (64 - shift))) & Mask64 - } - - def referenceMadd(srcD: BigInt, srcL: BigInt, srcR: BigInt): BigInt = - (srcD + (srcL * srcR)) & Mask64 - - private def setcRegisterSrcR(insnRaw: BigInt, value: BigInt): BigInt = - srcRType(insnRaw) match { - case 1 => signed32(value) & Mask64 - case 2 => value & ((BigInt(1) << 32) - 1) - case _ => value & Mask64 - } - - def referenceCsel(srcL: BigInt, srcR: BigInt, srcP: BigInt): BigInt = - if ((srcP & Mask64) != 0) srcL & Mask64 else srcR & Mask64 - - def referenceSdIndexedAddress(srcL: BigInt, srcR: BigInt): BigInt = - (srcL + ((srcR & Mask64) << 3)) & Mask64 - - def referenceSdIndexedData(srcD: BigInt): BigInt = - srcD & Mask64 - - def referenceShiAddress(srcR: BigInt, imm: BigInt): BigInt = - (srcR + ((imm << 1) & Mask64)) & Mask64 - - def referenceShiData(srcL: BigInt): BigInt = - srcL & Mask64 - - def referenceHlSwiPoAddress(srcR: BigInt): BigInt = - srcR & Mask64 - - def referenceHlSwiPoData(srcD: BigInt): BigInt = - srcD & Mask32 - - def referenceHlSdiPoAddress(srcR: BigInt): BigInt = - srcR & Mask64 - - def referenceHlSdiPoData(srcD: BigInt): BigInt = - srcD & Mask64 - - def referenceFentryFirstSaveAddress(oldSp: BigInt): BigInt = - (oldSp - 8) & Mask64 - - def referenceLwiAddress(srcL: BigInt, imm: BigInt): BigInt = - (srcL + ((imm << 2) & Mask64)) & Mask64 - - def referenceLwiUAddress(srcL: BigInt, imm: BigInt): BigInt = - (srcL + imm) & Mask64 - - def referenceLhiAddress(srcL: BigInt, imm: BigInt): BigInt = - (srcL + ((imm << 1) & Mask64)) & Mask64 - - def referenceHlLongOffsetLoadAddress(opcode: Int, srcL: BigInt, imm: BigInt): BigInt = { - val size = - if (Set(FrontendOpcodeDecodeTable.OP_HL_LBI, FrontendOpcodeDecodeTable.OP_HL_LBUI).contains(opcode)) 1 - else if (Set( - FrontendOpcodeDecodeTable.OP_HL_LHI, - FrontendOpcodeDecodeTable.OP_HL_LHI_U, - FrontendOpcodeDecodeTable.OP_HL_LHUI, - FrontendOpcodeDecodeTable.OP_HL_LHUI_U).contains(opcode)) 2 - else if (Set( - FrontendOpcodeDecodeTable.OP_HL_LWI, - FrontendOpcodeDecodeTable.OP_HL_LWI_U, - FrontendOpcodeDecodeTable.OP_HL_LWUI, - FrontendOpcodeDecodeTable.OP_HL_LWUI_U).contains(opcode)) 4 - else 8 - val unscaled = Set( - FrontendOpcodeDecodeTable.OP_HL_LDI_U, - FrontendOpcodeDecodeTable.OP_HL_LHI_U, - FrontendOpcodeDecodeTable.OP_HL_LHUI_U, - FrontendOpcodeDecodeTable.OP_HL_LWI_U, - FrontendOpcodeDecodeTable.OP_HL_LWUI_U).contains(opcode) - (srcL + (if (unscaled) signed64(imm) else signed64(imm) * size)) & Mask64 - } - - def referenceHlLongOffsetStoreAddress(opcode: Int, srcR: BigInt, imm: BigInt): BigInt = { - val size = - if (opcode == FrontendOpcodeDecodeTable.OP_HL_SBI) 1 - else if (Set(FrontendOpcodeDecodeTable.OP_HL_SHI, FrontendOpcodeDecodeTable.OP_HL_SHI_U).contains(opcode)) 2 - else if (Set(FrontendOpcodeDecodeTable.OP_HL_SWI, FrontendOpcodeDecodeTable.OP_HL_SWI_U).contains(opcode)) 4 - else 8 - val unscaled = Set( - FrontendOpcodeDecodeTable.OP_HL_SDI_U, - FrontendOpcodeDecodeTable.OP_HL_SHI_U, - FrontendOpcodeDecodeTable.OP_HL_SWI_U).contains(opcode) - (srcR + (if (unscaled) signed64(imm) else signed64(imm) * size)) & Mask64 - } - - def referenceResult(opcode: Int, pc: BigInt, src0: BigInt, src1: BigInt, imm: BigInt): Option[BigInt] = - opcode match { - case FrontendOpcodeDecodeTable.OP_ADDTPC => Some(((pc & ~BigInt(0xfff)) + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_SETRET => Some((pc + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_HL_SETRET => Some((pc + imm) & Mask64) - case FrontendOpcodeDecodeTable.OP_C_SETRET => Some((pc + imm) & Mask64) - case _ => referenceResult(opcode, src0, src1, imm) - } - - def referenceBranchCondition( - opcode: Int, - src0: BigInt, - src1: BigInt, - src0Valid: Boolean = true, - src1Valid: Boolean = true): Option[Boolean] = - referenceBranchConditionWithInsn(opcode, NoModifierInsn, src0, src1, src0Valid, src1Valid) - - def referenceBranchConditionWithInsn( - opcode: Int, - insnRaw: BigInt, - src0: BigInt, - src1: BigInt, - src0Valid: Boolean = true, - src1Valid: Boolean = true): Option[Boolean] = - opcode match { - case FrontendOpcodeDecodeTable.OP_C_SETC_EQ => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) src1 & Mask64 else BigInt(0) - Some(lhs == rhs) - case FrontendOpcodeDecodeTable.OP_C_SETC_NE => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) src1 & Mask64 else BigInt(0) - Some(lhs != rhs) - case FrontendOpcodeDecodeTable.OP_C_SETC_TGT => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs != 0) - case FrontendOpcodeDecodeTable.OP_SETC_EQ => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) setcRegisterSrcR(insnRaw, src1) else BigInt(0) - Some(lhs == rhs) - case FrontendOpcodeDecodeTable.OP_SETC_NE => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) setcRegisterSrcR(insnRaw, src1) else BigInt(0) - Some(lhs != rhs) - case FrontendOpcodeDecodeTable.OP_SETC_EQI | FrontendOpcodeDecodeTable.OP_HL_SETC_EQI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs == setcShiftedImmediate(opcode, insnRaw, src1)) - case FrontendOpcodeDecodeTable.OP_SETC_NEI | FrontendOpcodeDecodeTable.OP_HL_SETC_NEI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs != setcShiftedImmediate(opcode, insnRaw, src1)) - case FrontendOpcodeDecodeTable.OP_SETC_ANDI | FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some((lhs & setcShiftedImmediate(opcode, insnRaw, src1)) != 0) - case FrontendOpcodeDecodeTable.OP_SETC_ORI | FrontendOpcodeDecodeTable.OP_HL_SETC_ORI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some((lhs | setcShiftedImmediate(opcode, insnRaw, src1)) != 0) - case FrontendOpcodeDecodeTable.OP_SETC_LT => - val lhs = if (src0Valid) signed64(src0) else BigInt(0) - val rhs = if (src1Valid) signed64(setcRegisterSrcR(insnRaw, src1)) else BigInt(0) - Some(lhs < rhs) - case FrontendOpcodeDecodeTable.OP_SETC_LTI | FrontendOpcodeDecodeTable.OP_HL_SETC_LTI => - val lhs = if (src0Valid) signed64(src0) else BigInt(0) - Some(lhs < signed64(setcShiftedImmediate(opcode, insnRaw, src1))) - case FrontendOpcodeDecodeTable.OP_SETC_GE => - val lhs = if (src0Valid) signed64(src0) else BigInt(0) - val rhs = if (src1Valid) signed64(setcRegisterSrcR(insnRaw, src1)) else BigInt(0) - Some(lhs >= rhs) - case FrontendOpcodeDecodeTable.OP_SETC_GEI | FrontendOpcodeDecodeTable.OP_HL_SETC_GEI => - val lhs = if (src0Valid) signed64(src0) else BigInt(0) - Some(lhs >= signed64(setcShiftedImmediate(opcode, insnRaw, src1))) - case FrontendOpcodeDecodeTable.OP_SETC_LTU => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) setcRegisterSrcR(insnRaw, src1) else BigInt(0) - Some(lhs < rhs) - case FrontendOpcodeDecodeTable.OP_SETC_GEU => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - val rhs = if (src1Valid) setcRegisterSrcR(insnRaw, src1) else BigInt(0) - Some(lhs >= rhs) - case FrontendOpcodeDecodeTable.OP_SETC_LTUI | FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs < setcShiftedImmediate(opcode, insnRaw, src1)) - case FrontendOpcodeDecodeTable.OP_SETC_GEUI | FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs >= setcShiftedImmediate(opcode, insnRaw, src1)) - case FrontendOpcodeDecodeTable.OP_SETC_TGT => - val lhs = if (src0Valid) src0 & Mask64 else BigInt(0) - Some(lhs != 0) - case _ => None - } - - def referenceFretStkNextPc( - pc: BigInt, - lenBytes: Int, - setcTarget: Option[BigInt], - fallbackTarget: Option[BigInt]): BigInt = - (setcTarget.orElse(fallbackTarget).getOrElse(pc + lenBytes)) & Mask64 - - def referenceFretStkLoadsReturn( - restoresRa: Boolean, - conditionValid: Boolean, - conditionTaken: Boolean, - targetPending: Boolean = false): Boolean = { - restoresRa && ((conditionValid && !conditionTaken) || (!conditionValid && !targetPending)) - } - - def referenceFretStkSnapshotLoadsReturn( - restoresRa: Boolean, - contextValid: Boolean, - snapshotConditionValid: Boolean, - snapshotConditionTaken: Boolean, - snapshotTargetPending: Boolean, - liveConditionValid: Boolean, - liveConditionTaken: Boolean, - liveTargetPending: Boolean): Boolean = { - val conditionValid = if (contextValid) snapshotConditionValid else liveConditionValid - val conditionTaken = if (contextValid) snapshotConditionTaken else liveConditionTaken - val targetPending = if (contextValid) snapshotTargetPending else liveTargetPending - referenceFretStkLoadsReturn(restoresRa, conditionValid, conditionTaken, targetPending) - } - - def referenceFretStkDecodeContextValid( - isFretStk: Boolean, - activeBlockConditional: Boolean, - conditionValid: Boolean): Boolean = - isFretStk && (!activeBlockConditional || conditionValid) - - def referenceFretStkProducedSp( - stackPointerData: BigInt, - frameSize: BigInt, - loadsReturn: Boolean): BigInt = - (if (loadsReturn) stackPointerData + frameSize else stackPointerData) & Mask64 -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarDivider.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarDivider.scala deleted file mode 100644 index a07b451a..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarDivider.scala +++ /dev/null @@ -1,111 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{Cat, Fill} - -class ReducedScalarDividerIO extends Bundle { - val reqValid = Input(Bool()) - val reqReady = Output(Bool()) - val lhs = Input(UInt(64.W)) - val rhs = Input(UInt(64.W)) - val signed = Input(Bool()) - val word = Input(Bool()) - val remainder = Input(Bool()) - - val respValid = Output(Bool()) - val respReady = Input(Bool()) - val result = Output(UInt(64.W)) - val flush = Input(Bool()) -} - -/** Area-oriented radix-2 divider for the reduced scalar execution path. - * - * One quotient bit is produced per cycle. Word operations run for 32 cycles - * and full-width operations run for 64 cycles. The request records all sign - * information up front, so the iterative datapath itself is unsigned and has - * only one 65-bit compare/subtract path. - */ -class ReducedScalarDivider extends Module { - val io = IO(new ReducedScalarDividerIO) - - val busy = RegInit(false.B) - val resultValid = RegInit(false.B) - val divisor = Reg(UInt(64.W)) - val quotient = Reg(UInt(64.W)) - val partialRemainder = Reg(UInt(65.W)) - val iterationsLeft = Reg(UInt(7.W)) - val resultIsWord = Reg(Bool()) - val resultIsRemainder = Reg(Bool()) - val quotientNegative = Reg(Bool()) - val remainderNegative = Reg(Bool()) - val result = Reg(UInt(64.W)) - - io.reqReady := !io.flush && !busy && !resultValid - io.respValid := !io.flush && resultValid - io.result := result - - val requestAccepted = io.reqValid && io.reqReady - val lhsWord = io.lhs(31, 0) - val rhsWord = io.rhs(31, 0) - val lhsNegative = io.signed && Mux(io.word, lhsWord(31), io.lhs(63)) - val rhsNegative = io.signed && Mux(io.word, rhsWord(31), io.rhs(63)) - val lhsDomain = Mux(io.word, lhsWord.pad(64), io.lhs) - val rhsDomain = Mux(io.word, rhsWord.pad(64), io.rhs) - val lhsWordMagnitude = Mux(lhsNegative, (~lhsWord + 1.U)(31, 0), lhsWord) - val rhsWordMagnitude = Mux(rhsNegative, (~rhsWord + 1.U)(31, 0), rhsWord) - val lhsMagnitude = Mux(io.word, lhsWordMagnitude.pad(64), Mux(lhsNegative, (~io.lhs + 1.U)(63, 0), io.lhs)) - val rhsMagnitude = Mux(io.word, rhsWordMagnitude.pad(64), Mux(rhsNegative, (~io.rhs + 1.U)(63, 0), io.rhs)) - val divisorIsZero = rhsDomain === 0.U - - val shiftedRemainder64 = Cat(partialRemainder(63, 0), quotient(63)) - val shiftedRemainder32 = Cat(partialRemainder(63, 0), quotient(31)) - val shiftedRemainder = Mux(resultIsWord, shiftedRemainder32, shiftedRemainder64) - val subtract = shiftedRemainder >= divisor.pad(65) - val nextRemainder = Mux(subtract, shiftedRemainder - divisor.pad(65), shiftedRemainder) - val shiftedQuotient64 = Cat(quotient(62, 0), 0.U(1.W)) - val shiftedQuotient32 = Cat(0.U(32.W), quotient(30, 0), 0.U(1.W)) - val shiftedQuotient = Mux(resultIsWord, shiftedQuotient32, shiftedQuotient64) - val nextQuotient = shiftedQuotient | subtract.asUInt - val magnitudeResult = Mux(resultIsRemainder, nextRemainder(63, 0), nextQuotient) - val resultNegative = Mux(resultIsRemainder, remainderNegative, quotientNegative) - val signedResult = Mux(resultNegative, (~magnitudeResult + 1.U)(63, 0), magnitudeResult) - val formattedResult = Mux(resultIsWord, Cat(Fill(32, signedResult(31)), signedResult(31, 0)), signedResult) - - when(io.flush) { - busy := false.B - resultValid := false.B - }.otherwise { - when(resultValid && io.respReady) { - resultValid := false.B - } - - when(requestAccepted) { - resultIsWord := io.word - resultIsRemainder := io.remainder - quotientNegative := lhsNegative ^ rhsNegative - remainderNegative := lhsNegative - - when(divisorIsZero) { - val zeroRemainder = Mux(io.word, Cat(Fill(32, lhsWord(31)), lhsWord), io.lhs) - result := Mux(io.remainder, zeroRemainder, 0.U) - resultValid := true.B - busy := false.B - }.otherwise { - divisor := rhsMagnitude - quotient := lhsMagnitude - partialRemainder := 0.U - iterationsLeft := Mux(io.word, 32.U, 64.U) - busy := true.B - } - }.elsewhen(busy) { - quotient := nextQuotient - partialRemainder := nextRemainder - iterationsLeft := iterationsLeft - 1.U - when(iterationsLeft === 1.U) { - result := formattedResult - resultValid := true.B - busy := false.B - } - } - } -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarFpExecute.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarFpExecute.scala deleted file mode 100644 index d91eeca2..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarFpExecute.scala +++ /dev/null @@ -1,229 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{Cat, PriorityEncoder, Reverse} - -import linxcore.frontend.FrontendOpcodeDecodeTable - -class ReducedScalarFpExecuteIO extends Bundle { - val inValid = Input(Bool()) - val inReady = Output(Bool()) - val opcode = Input(UInt(10.W)) - val insnRaw = Input(UInt(32.W)) - val srcL = Input(UInt(64.W)) - val srcR = Input(UInt(64.W)) - val flush = Input(Bool()) - - val outReady = Input(Bool()) - val outValid = Output(Bool()) - val outData = Output(UInt(64.W)) - val unsupported = Output(Bool()) -} - -class ReducedScalarFpExecute extends Module { - val io = IO(new ReducedScalarFpExecuteIO) - - private def opcode(value: Int): UInt = - value.U(io.opcode.getWidth.W) - - private val dstType = io.insnRaw(31, 27) - private val srcType = io.insnRaw(26, 25) - private val isFeq = io.opcode === opcode(FrontendOpcodeDecodeTable.OP_FEQ) - private val isFcvtFsToFd = - io.opcode === opcode(FrontendOpcodeDecodeTable.OP_FCVT) && srcType === 1.U && dstType === 0.U - private val isUcvtfUdToFs = - io.opcode === opcode(FrontendOpcodeDecodeTable.OP_UCVTF) && srcType === 0.U && dstType === 1.U - private val isFeqFd = isFeq && srcType === 0.U - private val isFeqFs = isFeq && srcType === 1.U - private val supported = isFeqFd || isFeqFs || isFcvtFsToFd || isUcvtfUdToFs - - private def fp32IsNaN(x: UInt): Bool = - x(30, 23) === 0xff.U && x(22, 0) =/= 0.U - - private def fp64IsNaN(x: UInt): Bool = - x(62, 52) === 0x7ff.U && x(51, 0) =/= 0.U - - private def fp32IsZero(x: UInt): Bool = - x(30, 0) === 0.U - - private def fp64IsZero(x: UInt): Bool = - x(62, 0) === 0.U - - private def fp32Eq(a: UInt, b: UInt): Bool = - !fp32IsNaN(a) && !fp32IsNaN(b) && (a === b || (fp32IsZero(a) && fp32IsZero(b))) - - private def fp64Eq(a: UInt, b: UInt): Bool = - !fp64IsNaN(a) && !fp64IsNaN(b) && (a === b || (fp64IsZero(a) && fp64IsZero(b))) - - private def fp32ToFp64(a: UInt): UInt = { - val sign = a(31) - val exp = a(30, 23) - val frac = a(22, 0) - val out = Wire(UInt(64.W)) - out := 0.U - - when(exp === 0xff.U) { - val isNaN = frac =/= 0.U - val frac64 = Cat(isNaN, frac, 0.U(28.W)) - out := Cat(sign, 0x7ff.U(11.W), frac64) - }.elsewhen(exp === 0.U) { - when(frac === 0.U) { - out := Cat(sign, 0.U(63.W)) - }.otherwise { - val leadingZeros = PriorityEncoder(Reverse(frac)) - val msbIndex = 22.U(5.W) - leadingZeros - val normalizedFrac = (frac << (23.U - msbIndex))(22, 0) - val exp64 = 1023.U(11.W) - 149.U(11.W) + msbIndex - out := Cat(sign, exp64, normalizedFrac, 0.U(29.W)) - } - }.otherwise { - val exp64 = exp.zext.asSInt + (1023 - 127).S - out := Cat(sign, exp64.asUInt(10, 0), frac, 0.U(29.W)) - } - out - } - - private def uint64ToFp32(a: UInt): UInt = { - val out = Wire(UInt(32.W)) - out := 0.U - when(a =/= 0.U) { - val leadingZeros = PriorityEncoder(Reverse(a)) - val msbIndex = 63.U(6.W) - leadingZeros - val unrounded = Wire(UInt(24.W)) - unrounded := 0.U - val shift = Mux(msbIndex > 23.U, msbIndex - 23.U, 0.U) - when(msbIndex <= 23.U) { - unrounded := (a << (23.U - msbIndex))(23, 0) - }.otherwise { - unrounded := (a >> shift)(23, 0) - } - - val guardShift = shift - 1.U - val guard = shift =/= 0.U && ((a >> guardShift)(0) === 1.U) - val stickyMask = (1.U(64.W) << guardShift) - 1.U - val sticky = shift > 1.U && ((a & stickyMask) =/= 0.U) - val roundUp = guard && (sticky || unrounded(0)) - val rounded = Cat(0.U(1.W), unrounded) + roundUp - val carry = rounded(24) - val exp = 127.U(8.W) + msbIndex + carry - val frac = Mux(carry, rounded(23, 1), rounded(22, 0)) - out := Cat(0.U(1.W), exp, frac) - } - out - } - - private val feqResult = Mux(isFeqFs, fp32Eq(io.srcL(31, 0), io.srcR(31, 0)), fp64Eq(io.srcL, io.srcR)) - private val result = Wire(UInt(64.W)) - result := 0.U - when(isFeqFd || isFeqFs) { - result := Mux(feqResult, 1.U(64.W), 0.U(64.W)) - }.elsewhen(isFcvtFsToFd) { - result := fp32ToFp64(io.srcL(31, 0)) - }.elsewhen(isUcvtfUdToFs) { - result := uint64ToFp32(io.srcL).pad(64) - } - - io.inReady := io.outReady - io.outValid := io.inValid && !io.flush - io.outData := result - io.unsupported := io.inValid && !supported -} - -object ReducedScalarFpExecute { - val SrcTypeFd = 0 - val SrcTypeFs = 1 - val DstTypeFd = 0 - val DstTypeFs = 1 - - private val Mask64 = (BigInt(1) << 64) - 1 - private val Mask32 = (BigInt(1) << 32) - 1 - - def scalarFpInsn(dstType: Int, srcType: Int): BigInt = - (BigInt(dstType & 0x1f) << 27) | (BigInt(srcType & 0x3) << 25) - - def referenceResult(opcode: Int, insnRaw: BigInt, srcL: BigInt, srcR: BigInt): Option[BigInt] = { - val srcType = ((insnRaw >> 25) & 0x3).toInt - val dstType = ((insnRaw >> 27) & 0x1f).toInt - opcode match { - case FrontendOpcodeDecodeTable.OP_FEQ if srcType == SrcTypeFd => - Some(if (fp64Eq(srcL, srcR)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_FEQ if srcType == SrcTypeFs => - Some(if (fp32Eq(srcL, srcR)) 1 else 0) - case FrontendOpcodeDecodeTable.OP_FCVT if srcType == SrcTypeFs && dstType == DstTypeFd => - Some(fp32ToFp64(srcL)) - case FrontendOpcodeDecodeTable.OP_UCVTF if srcType == SrcTypeFd && dstType == DstTypeFs => - Some(uint64ToFp32(srcL)) - case _ => None - } - } - - private def fp32Eq(a: BigInt, b: BigInt): Boolean = { - val aa = a & Mask32 - val bb = b & Mask32 - !fp32IsNaN(aa) && !fp32IsNaN(bb) && (aa == bb || (fp32IsZero(aa) && fp32IsZero(bb))) - } - - private def fp64Eq(a: BigInt, b: BigInt): Boolean = { - val aa = a & Mask64 - val bb = b & Mask64 - !fp64IsNaN(aa) && !fp64IsNaN(bb) && (aa == bb || (fp64IsZero(aa) && fp64IsZero(bb))) - } - - private def fp32IsNaN(a: BigInt): Boolean = - ((a >> 23) & 0xff) == 0xff && (a & 0x7fffff) != 0 - - private def fp64IsNaN(a: BigInt): Boolean = - ((a >> 52) & 0x7ff) == 0x7ff && (a & ((BigInt(1) << 52) - 1)) != 0 - - private def fp32IsZero(a: BigInt): Boolean = - (a & 0x7fffffffL) == 0 - - private def fp64IsZero(a: BigInt): Boolean = - (a & BigInt("7fffffffffffffff", 16)) == 0 - - private def fp32ToFp64(a: BigInt): BigInt = { - val bits = a & Mask32 - val sign = (bits >> 31) & 1 - val exp = (bits >> 23) & 0xff - val frac = bits & 0x7fffff - if (exp == 0xff) { - val frac64 = if (frac == 0) BigInt(0) else (BigInt(1) << 51) | (frac << 28) - (sign << 63) | (BigInt(0x7ff) << 52) | frac64 - } else if (exp == 0) { - if (frac == 0) { - sign << 63 - } else { - val msbIndex = frac.bitLength - 1 - val exp64 = 1023 - 149 + msbIndex - val normalizedFrac = (frac << (23 - msbIndex)) & 0x7fffff - (sign << 63) | (BigInt(exp64) << 52) | (normalizedFrac << 29) - } - } else { - (sign << 63) | ((exp + (1023 - 127)) << 52) | (frac << 29) - } - } - - private def uint64ToFp32(a: BigInt): BigInt = { - val value = a & Mask64 - if (value == 0) { - 0 - } else { - val msbIndex = value.bitLength - 1 - val (unrounded, roundUp) = - if (msbIndex <= 23) { - ((value << (23 - msbIndex)) & 0xffffff, false) - } else { - val shift = msbIndex - 23 - val kept = (value >> shift) & 0xffffff - val guard = ((value >> (shift - 1)) & 1) != 0 - val sticky = (value & ((BigInt(1) << (shift - 1)) - 1)) != 0 - (kept, guard && (sticky || (kept & 1) != 0)) - } - val rounded = unrounded + (if (roundUp) 1 else 0) - val carry = (rounded >> 24) != 0 - val exp = 127 + msbIndex + (if (carry) 1 else 0) - val frac = if (carry) (rounded >> 1) & 0x7fffff else rounded & 0x7fffff - (BigInt(exp) << 23) | frac - } - } -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala deleted file mode 100644 index 55cca200..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala +++ /dev/null @@ -1,159 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{PriorityEncoder, log2Ceil} - -import linxcore.common.{InterfaceParams, OperandClass, RenamedUop} - -class ReducedScalarIssuePickIO( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 4) - extends Bundle { - private val countWidth = log2Ceil(depth + 1) - private val indexWidth = log2Ceil(depth) - - val selectableMask = Input(UInt(depth.W)) - val entries = Input(Vec(depth, new RenamedUop(p))) - val headValid = Input(Bool()) - val headIssued = Input(Bool()) - val notIssuedCount = Input(UInt(countWidth.W)) - val flushValid = Input(Bool()) - - val readValid = Output(Vec(3, Bool())) - val readTags = Output(Vec(3, UInt(p.physRegWidth.W))) - val readOperandClass = Output(Vec(3, OperandClass())) - val readRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val readData = Input(Vec(3, UInt(p.immWidth.W))) - val readGrant = Input(Bool()) - val readAttemptValid = Output(Bool()) - val readFire = Output(Bool()) - val readUop = Output(new RenamedUop(p)) - - val issueValid = Output(Bool()) - val issueReady = Input(Bool()) - val issueFire = Output(Bool()) - val issueUop = Output(new RenamedUop(p)) - val issueSrcData = Output(Vec(3, UInt(p.immWidth.W))) - - val pickFire = Output(Bool()) - val cancelFire = Output(Bool()) - val cancelIndex = Output(UInt(indexWidth.W)) - val i1Valid = Output(Bool()) - val i2Valid = Output(Bool()) - val stageBusy = Output(Bool()) - - val selectedValid = Output(Bool()) - val selectedIndex = Output(UInt(indexWidth.W)) - val selectedReadReady = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByRead = Output(Bool()) - val blockedByOutput = Output(Bool()) - val blockedByIssued = Output(Bool()) -} - -class ReducedScalarIssuePick( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 4) - extends Module { - require(depth > 1, "reduced scalar issue pick needs at least two entries") - require((depth & (depth - 1)) == 0, "reduced scalar issue pick depth must be a power of two") - - val io = IO(new ReducedScalarIssuePickIO(p, depth)) - - private val indexWidth = log2Ceil(depth) - val rrBase = RegInit(0.U(indexWidth.W)) - val perStidOldest = Wire(Vec(depth, Bool())) - for (idx <- 0 until depth) { - val earlierSameStid = - if (idx == 0) false.B - else VecInit((0 until idx).map { earlier => - io.selectableMask(earlier) && - (io.entries(earlier).threadId === io.entries(idx).threadId) - }).asUInt.orR - perStidOldest(idx) := io.selectableMask(idx) && !earlierSameStid - } - val scanValid = Wire(Vec(depth, Bool())) - for (offset <- 0 until depth) { - val idx = (rrBase + offset.U)(indexWidth - 1, 0) - scanValid(offset) := perStidOldest(idx) - } - val selectedValid = scanValid.asUInt.orR - val selectedIndex = (rrBase + PriorityEncoder(scanValid.asUInt))(indexWidth - 1, 0) - - val selectedUop = Mux(selectedValid, io.entries(selectedIndex), 0.U.asTypeOf(new RenamedUop(p))) - - val i1Valid = RegInit(false.B) - val i1Index = RegInit(0.U(log2Ceil(depth).W)) - val i1Uop = RegInit(0.U.asTypeOf(new RenamedUop(p))) - val i2Valid = RegInit(false.B) - val i2Uop = RegInit(0.U.asTypeOf(new RenamedUop(p))) - val i2SrcData = RegInit(VecInit(Seq.fill(3)(0.U(p.immWidth.W)))) - val active = !io.flushValid - - val issueValid = active && i2Valid - val issueFire = issueValid && io.issueReady - val i2CanAccept = !i2Valid || issueFire - val readAttemptValid = active && i1Valid && i2CanAccept - - for (idx <- 0 until 3) { - io.readValid(idx) := readAttemptValid && i1Uop.src(idx).valid - io.readTags(idx) := i1Uop.src(idx).physTag - io.readOperandClass(idx) := i1Uop.src(idx).operandClass - io.readRelTag(idx) := i1Uop.src(idx).relTag - io.issueSrcData(idx) := i2SrcData(idx) - } - - // The reduced RF read data is combinational; once the queue selected a ready - // uop, later ready-bit drops must not cancel the already-picked read. - val i1ReadReady = io.readGrant - val i1Advance = readAttemptValid && i1ReadReady - val i1Cancel = readAttemptValid && !i1ReadReady - val i1WillClear = i1Advance || i1Cancel - val i1CanAccept = !i1Valid || i1WillClear - val pickFire = active && selectedValid && i1CanAccept - val stageBusy = i1Valid || i2Valid - - io.issueValid := issueValid - io.issueFire := issueFire - io.issueUop := i2Uop - io.pickFire := pickFire - io.cancelFire := active && i1Cancel - io.cancelIndex := i1Index - io.readAttemptValid := readAttemptValid - io.readFire := i1Advance - io.readUop := i1Uop - io.i1Valid := i1Valid - io.i2Valid := i2Valid - io.stageBusy := stageBusy - io.selectedValid := selectedValid - io.selectedIndex := selectedIndex - io.selectedReadReady := Mux(i1Valid, !readAttemptValid || i1ReadReady, selectedValid) - io.blockedBySource := !stageBusy && io.headValid && (io.notIssuedCount =/= 0.U) && !selectedValid - io.blockedByRead := i1Cancel - io.blockedByOutput := issueValid && !io.issueReady - io.blockedByIssued := io.headIssued && !selectedValid - - when(io.flushValid) { - i1Valid := false.B - i2Valid := false.B - }.otherwise { - when(pickFire) { - rrBase := selectedIndex + 1.U - } - when(i1Advance) { - i2Valid := true.B - i2Uop := i1Uop - i2SrcData := io.readData - }.elsewhen(issueFire) { - i2Valid := false.B - } - - when(pickFire) { - i1Valid := true.B - i1Index := selectedIndex - i1Uop := selectedUop - }.elsewhen(i1WillClear) { - i1Valid := false.B - } - } -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala deleted file mode 100644 index db0601fe..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala +++ /dev/null @@ -1,391 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{log2Ceil, PopCount} - -import linxcore.common.{DestinationKind, DispatchTarget, InterfaceParams, OperandClass, RenamedOperand, RenamedUop, ScalarSpAccess} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rob.{ROBID} - -class ReducedScalarIssueQueueIO( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 4, - val stidCount: Int = 1) - extends Bundle { - private val countWidth = log2Ceil(depth + 1) - private val indexWidth = log2Ceil(depth) - - val inValid = Input(Bool()) - val inReady = Output(Bool()) - val in = Input(new RenamedUop(p)) - val flushValid = Input(Bool()) - - val releaseValid = Input(Bool()) - val releaseBid = Input(new ROBID(p.robEntries)) - val releaseRid = Input(new ROBID(p.robEntries)) - val releaseStid = Input(UInt(p.threadIdWidth.W)) - val secondaryReleaseValid = Input(Bool()) - val secondaryReleaseBid = Input(new ROBID(p.robEntries)) - val secondaryReleaseRid = Input(new ROBID(p.robEntries)) - val secondaryReleaseStid = Input(UInt(p.threadIdWidth.W)) - val tertiaryReleaseValid = Input(Bool()) - val tertiaryReleaseBid = Input(new ROBID(p.robEntries)) - val tertiaryReleaseRid = Input(new ROBID(p.robEntries)) - val tertiaryReleaseStid = Input(UInt(p.threadIdWidth.W)) - val scalarSpHeadValidByStid = Input(Vec(stidCount, Bool())) - val scalarSpHeadBidByStid = Input(Vec(stidCount, new ROBID(p.robEntries))) - val scalarSpHeadRidByStid = Input(Vec(stidCount, new ROBID(p.robEntries))) - - val readyMask = Input(UInt((1 << p.physRegWidth).W)) - val pWakeupValid = Input(Bool()) - val pWakeupTag = Input(UInt(p.physRegWidth.W)) - val localTReadyMask = Input(UInt(4.W)) - val localUReadyMask = Input(UInt(4.W)) - val readValid = Output(Vec(3, Bool())) - val readTags = Output(Vec(3, UInt(p.physRegWidth.W))) - val readOperandClass = Output(Vec(3, OperandClass())) - val readRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val readData = Input(Vec(3, UInt(p.immWidth.W))) - val readGrant = Input(Bool()) - val readAttemptValid = Output(Bool()) - val readFire = Output(Bool()) - val readUop = Output(new RenamedUop(p)) - - val issueValid = Output(Bool()) - val issueReady = Input(Bool()) - val issueUop = Output(new RenamedUop(p)) - val issueSrcData = Output(Vec(3, UInt(p.immWidth.W))) - - val enqueueFire = Output(Bool()) - val pickFire = Output(Bool()) - val issueFire = Output(Bool()) - val cancelFire = Output(Bool()) - val releaseFire = Output(Bool()) - val enqueueDstValid = Output(Bool()) - val enqueueDstTag = Output(UInt(p.physRegWidth.W)) - - val empty = Output(Bool()) - val full = Output(Bool()) - val count = Output(UInt(countWidth.W)) - val issuedCount = Output(UInt(countWidth.W)) - val notIssuedCount = Output(UInt(countWidth.W)) - val headValid = Output(Bool()) - val headIssued = Output(Bool()) - val headPc = Output(UInt(p.pcWidth.W)) - val headOpcode = Output(UInt(p.opcodeWidth.W)) - val headStid = Output(UInt(p.threadIdWidth.W)) - val headBid = Output(new ROBID(p.robEntries)) - val headRid = Output(new ROBID(p.robEntries)) - val headSrcValidMask = Output(UInt(3.W)) - val headSrcOperandClass = Output(Vec(3, OperandClass())) - val headSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val headSrcRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val sourceReadyMask = Output(UInt(3.W)) - val allSourcesReady = Output(Bool()) - val pWakeupMatched = Output(Bool()) - val pWakeupMatchCount = Output(UInt(log2Ceil(depth * 3 + 1).W)) - val selectedValid = Output(Bool()) - val selectedIndex = Output(UInt(indexWidth.W)) - val selectedReadReady = Output(Bool()) - val i1Valid = Output(Bool()) - val i2Valid = Output(Bool()) - val stageBusy = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByRead = Output(Bool()) - val blockedByOutput = Output(Bool()) - val blockedByIssued = Output(Bool()) - val residentControlValid = Output(Vec(depth, Bool())) - val residentControlUop = Output(Vec(depth, new RenamedUop(p))) - val residentStoreValid = Output(Vec(depth, Bool())) - val residentStoreUop = Output(Vec(depth, new RenamedUop(p))) -} - -class ReducedScalarIssueQueue( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 4, - val stidCount: Int = 1) - extends Module { - require(depth > 1, "reduced scalar issue queue needs at least two entries") - require((depth & (depth - 1)) == 0, "reduced scalar issue queue depth must be a power of two") - require(stidCount > 0, "reduced scalar issue queue must expose at least one STID") - - private val countWidth = log2Ceil(depth + 1) - private val stidIndexWidth = math.max(1, log2Ceil(stidCount)) - private def stidIndex(stid: UInt): UInt = - if (stidCount == 1) 0.U(stidIndexWidth.W) else stid(stidIndexWidth - 1, 0) - - val io = IO(new ReducedScalarIssueQueueIO(p, depth, stidCount)) - - private def sameRobId(lhs: ROBID, rhs: ROBID): Bool = - ROBID.equal(lhs, rhs) - - private def scalarSpHeadMatch(uop: RenamedUop): Bool = { - val entryStid = stidIndex(uop.threadId) - io.scalarSpHeadValidByStid(entryStid) && - ROBID.equal(uop.bid, io.scalarSpHeadBidByStid(entryStid)) && - ROBID.equal(uop.rid, io.scalarSpHeadRidByStid(entryStid)) - } - - private def explicitScalarSpSource(src: RenamedOperand): Bool = - src.valid && (src.operandClass === OperandClass.P) && (src.archTag === 1.U) - - val entries = RegInit(VecInit(Seq.fill(depth)(0.U.asTypeOf(new RenamedUop(p))))) - val valid = RegInit(VecInit(Seq.fill(depth)(false.B))) - val issued = RegInit(VecInit(Seq.fill(depth)(false.B))) - val srcReady = RegInit(VecInit(Seq.fill(depth)(VecInit(Seq.fill(3)(false.B))))) - val count = RegInit(0.U(countWidth.W)) - - val headValid = count =/= 0.U - val headIssued = headValid && issued(0) - val headUop = entries(0) - - private def localSourceReady(src: RenamedOperand): Bool = { - val rel = src.relTag(1, 0) - Mux( - src.operandClass === OperandClass.T, - io.localTReadyMask(rel), - Mux(src.operandClass === OperandClass.U, io.localUReadyMask(rel), false.B) - ) - } - - private def laneReadyFromMask(uop: RenamedUop, lane: Int): Bool = { - val src = uop.src(lane) - val isLocal = src.operandClass === OperandClass.T || src.operandClass === OperandClass.U - val isScalarSp = explicitScalarSpSource(src) - val pWakeup = io.pWakeupValid && (src.operandClass === OperandClass.P) && - (src.physTag === io.pWakeupTag) - !src.valid || Mux( - isLocal, - localSourceReady(src), - Mux(isScalarSp, scalarSpHeadMatch(uop), io.readyMask(src.physTag) || pWakeup) - ) - } - - val pWakeupMatches = Wire(Vec(depth, Vec(3, Bool()))) - for (entryIdx <- 0 until depth; lane <- 0 until 3) { - val src = entries(entryIdx).src(lane) - pWakeupMatches(entryIdx)(lane) := io.pWakeupValid && valid(entryIdx) && !issued(entryIdx) && - src.valid && (src.operandClass === OperandClass.P) && (src.physTag === io.pWakeupTag) - } - val pWakeupMatchCount = PopCount(pWakeupMatches.asUInt) - - val rawReleaseMatches = Wire(Vec(depth, Bool())) - val primaryReleaseMatches = Wire(Vec(depth, Bool())) - val rawSecondaryReleaseMatches = Wire(Vec(depth, Bool())) - val secondaryReleaseMatches = Wire(Vec(depth, Bool())) - val rawTertiaryReleaseMatches = Wire(Vec(depth, Bool())) - val tertiaryReleaseMatches = Wire(Vec(depth, Bool())) - val releaseMatches = Wire(Vec(depth, Bool())) - for (idx <- 0 until depth) { - rawReleaseMatches(idx) := valid(idx) && issued(idx) && - sameRobId(entries(idx).bid, io.releaseBid) && - sameRobId(entries(idx).rid, io.releaseRid) && - (entries(idx).threadId === io.releaseStid) - val earlierPrimaryMatch = - if (idx == 0) false.B else VecInit((0 until idx).map(rawReleaseMatches(_))).asUInt.orR - primaryReleaseMatches(idx) := io.releaseValid && rawReleaseMatches(idx) && !earlierPrimaryMatch - - rawSecondaryReleaseMatches(idx) := valid(idx) && issued(idx) && - sameRobId(entries(idx).bid, io.secondaryReleaseBid) && - sameRobId(entries(idx).rid, io.secondaryReleaseRid) && - (entries(idx).threadId === io.secondaryReleaseStid) && - !primaryReleaseMatches(idx) - val earlierSecondaryMatch = - if (idx == 0) false.B else VecInit((0 until idx).map(rawSecondaryReleaseMatches(_))).asUInt.orR - secondaryReleaseMatches(idx) := - io.secondaryReleaseValid && rawSecondaryReleaseMatches(idx) && !earlierSecondaryMatch - - rawTertiaryReleaseMatches(idx) := valid(idx) && issued(idx) && - sameRobId(entries(idx).bid, io.tertiaryReleaseBid) && - sameRobId(entries(idx).rid, io.tertiaryReleaseRid) && - (entries(idx).threadId === io.tertiaryReleaseStid) && - !primaryReleaseMatches(idx) && - !secondaryReleaseMatches(idx) - val earlierTertiaryMatch = - if (idx == 0) false.B else VecInit((0 until idx).map(rawTertiaryReleaseMatches(_))).asUInt.orR - tertiaryReleaseMatches(idx) := - io.tertiaryReleaseValid && rawTertiaryReleaseMatches(idx) && !earlierTertiaryMatch - - releaseMatches(idx) := primaryReleaseMatches(idx) || secondaryReleaseMatches(idx) || tertiaryReleaseMatches(idx) - } - val releaseCount = PopCount(releaseMatches.asUInt) - val releaseFire = releaseMatches.asUInt.orR - - val entrySourceReady = Wire(Vec(depth, Vec(3, Bool()))) - val entryAllSourcesReady = Wire(Vec(depth, Bool())) - val entryScalarSpHeadEligible = Wire(Vec(depth, Bool())) - val entrySelectable = Wire(Vec(depth, Bool())) - for (entryIdx <- 0 until depth) { - val access = ScalarSpAccess.classify(entries(entryIdx)) - for (lane <- 0 until 3) { - entrySourceReady(entryIdx)(lane) := - !valid(entryIdx) || issued(entryIdx) || srcReady(entryIdx)(lane) - } - entryAllSourcesReady(entryIdx) := entrySourceReady(entryIdx).reduce(_ && _) - entryScalarSpHeadEligible(entryIdx) := - !access.valid || scalarSpHeadMatch(entries(entryIdx)) - entrySelectable(entryIdx) := - valid(entryIdx) && !issued(entryIdx) && entryAllSourcesReady(entryIdx) && - entryScalarSpHeadEligible(entryIdx) - } - - val issuedVec = VecInit((0 until depth).map(idx => valid(idx) && issued(idx))) - val issuedCount = PopCount(issuedVec.asUInt) - val headSourceReady = entrySourceReady(0) - val headAllSourcesReady = headSourceReady.reduce(_ && _) - val enqueueFire = io.inValid && io.inReady - val notIssuedCount = count - issuedCount - - val pick = Module(new ReducedScalarIssuePick(p, depth)) - pick.io.selectableMask := entrySelectable.asUInt - pick.io.entries := entries - pick.io.headValid := headValid - pick.io.headIssued := headIssued - pick.io.notIssuedCount := notIssuedCount - pick.io.flushValid := io.flushValid - pick.io.readData := io.readData - pick.io.readGrant := io.readGrant - pick.io.issueReady := io.issueReady - val pickFire = pick.io.pickFire - val issueFire = pick.io.issueFire - val cancelFire = pick.io.cancelFire - - io.inReady := (count =/= depth.U) || releaseFire - io.issueValid := pick.io.issueValid - io.issueUop := pick.io.issueUop - for (idx <- 0 until 3) { - io.readValid(idx) := pick.io.readValid(idx) - io.readTags(idx) := pick.io.readTags(idx) - io.readOperandClass(idx) := pick.io.readOperandClass(idx) - io.readRelTag(idx) := pick.io.readRelTag(idx) - io.issueSrcData(idx) := pick.io.issueSrcData(idx) - } - io.readAttemptValid := pick.io.readAttemptValid - io.readFire := pick.io.readFire - io.readUop := pick.io.readUop - - io.enqueueFire := enqueueFire - io.pickFire := pickFire - io.issueFire := issueFire - io.cancelFire := cancelFire - io.releaseFire := releaseFire - io.enqueueDstValid := enqueueFire && io.in.dst(0).valid && (io.in.dst(0).kind === DestinationKind.Gpr) - io.enqueueDstTag := io.in.dst(0).physTag - io.empty := count === 0.U - io.full := count === depth.U - io.count := count - io.issuedCount := issuedCount - io.notIssuedCount := notIssuedCount - io.headValid := headValid - io.headIssued := headIssued - io.headPc := Mux(headValid, headUop.pc, 0.U) - io.headOpcode := Mux(headValid, headUop.opcode, 0.U) - io.headStid := Mux(headValid, headUop.threadId, 0.U) - io.headBid := Mux(headValid, headUop.bid, ROBID.disabled(p.robEntries)) - io.headRid := Mux(headValid, headUop.rid, ROBID.disabled(p.robEntries)) - io.headSrcValidMask := VecInit((0 until 3).map(lane => headValid && headUop.src(lane).valid)).asUInt - for (idx <- 0 until 3) { - io.headSrcOperandClass(idx) := headUop.src(idx).operandClass - io.headSrcPhysTag(idx) := Mux(headValid, headUop.src(idx).physTag, 0.U) - io.headSrcRelTag(idx) := Mux(headValid, headUop.src(idx).relTag, 0.U) - } - io.sourceReadyMask := headSourceReady.asUInt - io.allSourcesReady := headAllSourcesReady - io.pWakeupMatched := pWakeupMatchCount =/= 0.U - io.pWakeupMatchCount := pWakeupMatchCount - io.selectedValid := pick.io.selectedValid - io.selectedIndex := pick.io.selectedIndex - io.selectedReadReady := pick.io.selectedReadReady - io.i1Valid := pick.io.i1Valid - io.i2Valid := pick.io.i2Valid - io.stageBusy := pick.io.stageBusy - io.blockedBySource := pick.io.blockedBySource - io.blockedByRead := pick.io.blockedByRead - io.blockedByOutput := pick.io.blockedByOutput - io.blockedByIssued := pick.io.blockedByIssued - for (idx <- 0 until depth) { - val redirectsBlockFlow = - entries(idx).opcode === FrontendOpcodeDecodeTable.OP_FRET_STK.U(p.opcodeWidth.W) - io.residentControlValid(idx) := valid(idx) && - ((entries(idx).dispatchTarget === DispatchTarget.Bru) || redirectsBlockFlow) - io.residentControlUop(idx) := entries(idx) - io.residentStoreValid(idx) := valid(idx) && entries(idx).isStore - io.residentStoreUop(idx) := entries(idx) - } - - val rawCancelIdentityMatches = Wire(Vec(depth, Bool())) - for (idx <- 0 until depth) { - rawCancelIdentityMatches(idx) := cancelFire && valid(idx) && issued(idx) && - (entries(idx).threadId === pick.io.readUop.threadId) && - (entries(idx).bid.valid === pick.io.readUop.bid.valid) && - sameRobId(entries(idx).bid, pick.io.readUop.bid) && - (entries(idx).rid.valid === pick.io.readUop.rid.valid) && - sameRobId(entries(idx).rid, pick.io.readUop.rid) - } - val cancelIdentityIsUnique = PopCount(rawCancelIdentityMatches.asUInt) === 1.U - - val preIssued = Wire(Vec(depth, Bool())) - for (idx <- 0 until depth) { - preIssued(idx) := - (issued(idx) || (pickFire && pick.io.selectedIndex === idx.U)) && - !(cancelIdentityIsUnique && rawCancelIdentityMatches(idx)) - } - - val preSrcReady = Wire(Vec(depth, Vec(3, Bool()))) - for (entryIdx <- 0 until depth) { - for (lane <- 0 until 3) { - preSrcReady(entryIdx)(lane) := - srcReady(entryIdx)(lane) || (valid(entryIdx) && laneReadyFromMask(entries(entryIdx), lane)) - } - } - - val keep = Wire(Vec(depth, Bool())) - for (idx <- 0 until depth) { - keep(idx) := valid(idx) && !releaseMatches(idx) - } - - val baseCount = count - releaseCount - val nextEntries = Wire(Vec(depth, new RenamedUop(p))) - val nextValid = Wire(Vec(depth, Bool())) - val nextIssued = Wire(Vec(depth, Bool())) - val nextSrcReady = Wire(Vec(depth, Vec(3, Bool()))) - for (dst <- 0 until depth) { - nextEntries(dst) := 0.U.asTypeOf(new RenamedUop(p)) - nextValid(dst) := false.B - nextIssued(dst) := false.B - nextSrcReady(dst) := VecInit(Seq.fill(3)(false.B)) - - for (src <- 0 until depth) { - val keptBefore = - if (src == 0) 0.U(countWidth.W) else PopCount(VecInit((0 until src).map(keep(_))).asUInt) - when(keep(src) && keptBefore === dst.U) { - nextEntries(dst) := entries(src) - nextValid(dst) := true.B - nextIssued(dst) := preIssued(src) - nextSrcReady(dst) := preSrcReady(src) - } - } - - when(enqueueFire && baseCount === dst.U) { - nextEntries(dst) := io.in - nextValid(dst) := true.B - nextIssued(dst) := false.B - nextSrcReady(dst) := VecInit((0 until 3).map(lane => laneReadyFromMask(io.in, lane))) - } - } - - when(io.flushValid) { - for (idx <- 0 until depth) { - valid(idx) := false.B - issued(idx) := false.B - srcReady(idx) := VecInit(Seq.fill(3)(false.B)) - } - count := 0.U - }.otherwise { - entries := nextEntries - valid := nextValid - issued := nextIssued - srcReady := nextSrcReady - count := baseCount + enqueueFire.asUInt - } -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedScalarWritebackArbiter.scala b/chisel/src/main/scala/linxcore/execute/ReducedScalarWritebackArbiter.scala deleted file mode 100644 index a216e2f5..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedScalarWritebackArbiter.scala +++ /dev/null @@ -1,94 +0,0 @@ -package linxcore.execute - -import chisel3._ - -class ReducedScalarWritebackArbiterIO( - val dataWidth: Int = 64, - val physRegWidth: Int = 6) - extends Bundle { - val executeValid = Input(Bool()) - val executeTag = Input(UInt(physRegWidth.W)) - val executeData = Input(UInt(dataWidth.W)) - - val replayEnable = Input(Bool()) - val replayValid = Input(Bool()) - val replayTag = Input(UInt(physRegWidth.W)) - val replayData = Input(UInt(dataWidth.W)) - - val serviceEnable = Input(Bool()) - val serviceValid = Input(Bool()) - val serviceTag = Input(UInt(physRegWidth.W)) - val serviceData = Input(UInt(dataWidth.W)) - - val templateEnable = Input(Bool()) - val templateValid = Input(Bool()) - val templateTag = Input(UInt(physRegWidth.W)) - val templateData = Input(UInt(dataWidth.W)) - - val writeValid = Output(Bool()) - val writeTag = Output(UInt(physRegWidth.W)) - val writeData = Output(UInt(dataWidth.W)) - - val selectedExecute = Output(Bool()) - val selectedReplay = Output(Bool()) - val selectedService = Output(Bool()) - val selectedTemplate = Output(Bool()) - val replayBlockedByDisabled = Output(Bool()) - val replayBlockedByExecute = Output(Bool()) - val serviceBlockedByDisabled = Output(Bool()) - val serviceBlockedByExecute = Output(Bool()) - val serviceBlockedByReplay = Output(Bool()) - val templateBlockedByDisabled = Output(Bool()) - val templateBlockedByExecute = Output(Bool()) - val templateBlockedByReplay = Output(Bool()) - val templateBlockedByService = Output(Bool()) -} - -class ReducedScalarWritebackArbiter( - val dataWidth: Int = 64, - val physRegWidth: Int = 6) - extends Module { - require(dataWidth > 0, "dataWidth must be positive") - require(physRegWidth > 0, "physRegWidth must be positive") - - val io = IO(new ReducedScalarWritebackArbiterIO(dataWidth, physRegWidth)) - - val replayCandidate = io.replayEnable && io.replayValid - val serviceCandidate = io.serviceEnable && io.serviceValid - val templateCandidate = io.templateEnable && io.templateValid - val selectedExecute = io.executeValid - val selectedReplay = replayCandidate && !io.executeValid - val selectedService = serviceCandidate && !io.executeValid && !replayCandidate - val selectedTemplate = templateCandidate && !io.executeValid && !replayCandidate && !serviceCandidate - - io.selectedExecute := selectedExecute - io.selectedReplay := selectedReplay - io.selectedService := selectedService - io.selectedTemplate := selectedTemplate - io.replayBlockedByDisabled := !io.replayEnable && io.replayValid - io.replayBlockedByExecute := replayCandidate && io.executeValid - io.serviceBlockedByDisabled := !io.serviceEnable && io.serviceValid - io.serviceBlockedByExecute := serviceCandidate && io.executeValid - io.serviceBlockedByReplay := serviceCandidate && !io.executeValid && replayCandidate - io.templateBlockedByDisabled := !io.templateEnable && io.templateValid - io.templateBlockedByExecute := templateCandidate && io.executeValid - io.templateBlockedByReplay := templateCandidate && !io.executeValid && replayCandidate - io.templateBlockedByService := - templateCandidate && !io.executeValid && !replayCandidate && serviceCandidate - - io.writeValid := selectedExecute || selectedReplay || selectedService || selectedTemplate - io.writeTag := Mux( - selectedExecute, - io.executeTag, - Mux( - selectedReplay, - io.replayTag, - Mux(selectedService, io.serviceTag, Mux(selectedTemplate, io.templateTag, 0.U)))) - io.writeData := Mux( - selectedExecute, - io.executeData, - Mux( - selectedReplay, - io.replayData, - Mux(selectedService, io.serviceData, Mux(selectedTemplate, io.templateData, 0.U)))) -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedTemplateContextStack.scala b/chisel/src/main/scala/linxcore/execute/ReducedTemplateContextStack.scala deleted file mode 100644 index d1a88727..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedTemplateContextStack.scala +++ /dev/null @@ -1,181 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.log2Ceil - -class ReducedTemplateContextStackIO( - val archRegs: Int, - val physRegWidth: Int, - val dataWidth: Int, - val frameDepth: Int) - extends Bundle { - val flush = Input(Bool()) - val cancel = Input(Bool()) - - val captureStart = Input(Bool()) - val captureStartArch = Input(UInt(log2Ceil(archRegs).W)) - val captureEndArch = Input(UInt(log2Ceil(archRegs).W)) - val captureMap = Input(Vec(archRegs, UInt(physRegWidth.W))) - val captureReadValid = Output(Bool()) - val captureReadTag = Output(UInt(physRegWidth.W)) - val captureReadReady = Input(Bool()) - val captureReadData = Input(UInt(dataWidth.W)) - - val restoreStart = Input(Bool()) - val restoreMap = Input(Vec(archRegs, UInt(physRegWidth.W))) - val restoreWriteValid = Output(Bool()) - val restoreWriteTag = Output(UInt(physRegWidth.W)) - val restoreWriteData = Output(UInt(dataWidth.W)) - val restoreWriteReady = Input(Bool()) - - val captureBusy = Output(Bool()) - val restoreBusy = Output(Bool()) - val restoreDone = Output(Bool()) - val frameCount = Output(UInt(log2Ceil(frameDepth + 1).W)) - val overflow = Output(Bool()) - val underflow = Output(Bool()) -} - -/** - * Serialized register-context sidecar for the reduced template path. - * - * The architectural register ring follows LinxCoreModel: 2..23, wrapping - * from 23 back to 2. FENTRY captures the physical-map snapshot in ring - * order; a returning FRET writes the saved values into its own rename-time - * physical-map snapshot before the parent macro is allowed to execute. - * - * This sidecar is deliberately single-ported. It makes the hardware timing - * and ownership explicit while the production D3 path grows the equivalent - * STORE/LOAD children and routes them through the LSU. - */ -class ReducedTemplateContextStack( - val archRegs: Int = 24, - val physRegWidth: Int = 6, - val dataWidth: Int = 64, - val frameDepth: Int = 32, - val maxSavedRegs: Int = 22) - extends Module { - require(archRegs == 24, "Linx scalar template register ring is r2..r23") - require(frameDepth > 1, "template context stack must hold nested frames") - require(maxSavedRegs == 22, "template register ring contains 22 registers") - - private val archWidth = log2Ceil(archRegs) - private val frameWidth = log2Ceil(frameDepth) - private val countWidth = log2Ceil(frameDepth + 1) - private val ordinalWidth = log2Ceil(maxSavedRegs) - - val io = IO(new ReducedTemplateContextStackIO(archRegs, physRegWidth, dataWidth, frameDepth)) - - private def nextRingArch(arch: UInt): UInt = - Mux(arch === 23.U, 2.U(archWidth.W), arch + 1.U) - - val contexts = Reg(Vec(frameDepth, Vec(maxSavedRegs, UInt(dataWidth.W)))) - val frameStartArch = Reg(Vec(frameDepth, UInt(archWidth.W))) - val frameSavedCount = Reg(Vec(frameDepth, UInt((ordinalWidth + 1).W))) - val frameCountReg = RegInit(0.U(countWidth.W)) - - val captureBusyReg = RegInit(false.B) - val captureFrame = Reg(UInt(frameWidth.W)) - val captureArch = Reg(UInt(archWidth.W)) - val captureEnd = Reg(UInt(archWidth.W)) - val captureOrdinal = Reg(UInt(ordinalWidth.W)) - val captureMapReg = Reg(Vec(archRegs, UInt(physRegWidth.W))) - - val restoreBusyReg = RegInit(false.B) - val restoreFrame = Reg(UInt(frameWidth.W)) - val restoreArch = Reg(UInt(archWidth.W)) - val restoreOrdinal = Reg(UInt(ordinalWidth.W)) - val restoreCount = Reg(UInt((ordinalWidth + 1).W)) - val restoreMapReg = Reg(Vec(archRegs, UInt(physRegWidth.W))) - val restoreDoneReg = RegInit(false.B) - val overflowReg = RegInit(false.B) - val underflowReg = RegInit(false.B) - - val captureAccepted = - io.captureStart && !captureBusyReg && !restoreBusyReg && frameCountReg =/= frameDepth.U - val restoreAccepted = - io.restoreStart && !captureBusyReg && !restoreBusyReg && frameCountReg =/= 0.U - - io.captureReadValid := captureBusyReg - io.captureReadTag := Mux(captureBusyReg, captureMapReg(captureArch), 0.U) - val captureFire = io.captureReadValid && io.captureReadReady - val captureLast = captureArch === captureEnd || captureOrdinal === (maxSavedRegs - 1).U - - io.restoreWriteValid := restoreBusyReg - io.restoreWriteTag := Mux(restoreBusyReg, restoreMapReg(restoreArch), 0.U) - io.restoreWriteData := Mux(restoreBusyReg, contexts(restoreFrame)(restoreOrdinal), 0.U) - val restoreFire = io.restoreWriteValid && io.restoreWriteReady - val restoreLast = restoreOrdinal + 1.U === restoreCount - - when(io.flush) { - frameCountReg := 0.U - captureBusyReg := false.B - restoreBusyReg := false.B - restoreDoneReg := false.B - overflowReg := false.B - underflowReg := false.B - }.elsewhen(io.cancel) { - // A suffix recovery may kill an in-flight FENTRY/FRET without changing - // the committed template stack. Capture publishes a frame only on its - // final read and restore pops a frame only on its final write, so aborting - // the serialized transaction here preserves the previous frameCount. - captureBusyReg := false.B - restoreBusyReg := false.B - restoreDoneReg := false.B - }.otherwise { - restoreDoneReg := false.B - - when(io.captureStart && frameCountReg === frameDepth.U) { - overflowReg := true.B - } - when(io.restoreStart && frameCountReg === 0.U) { - underflowReg := true.B - } - - when(captureAccepted) { - captureBusyReg := true.B - captureFrame := frameCountReg(frameWidth - 1, 0) - captureArch := io.captureStartArch - captureEnd := io.captureEndArch - captureOrdinal := 0.U - captureMapReg := io.captureMap - frameStartArch(frameCountReg(frameWidth - 1, 0)) := io.captureStartArch - }.elsewhen(captureFire) { - contexts(captureFrame)(captureOrdinal) := io.captureReadData - when(captureLast) { - frameSavedCount(captureFrame) := captureOrdinal + 1.U - frameCountReg := frameCountReg + 1.U - captureBusyReg := false.B - }.otherwise { - captureArch := nextRingArch(captureArch) - captureOrdinal := captureOrdinal + 1.U - } - } - - when(restoreAccepted) { - val topFrame = frameCountReg - 1.U - restoreBusyReg := true.B - restoreFrame := topFrame(frameWidth - 1, 0) - restoreArch := frameStartArch(topFrame(frameWidth - 1, 0)) - restoreOrdinal := 0.U - restoreCount := frameSavedCount(topFrame(frameWidth - 1, 0)) - restoreMapReg := io.restoreMap - }.elsewhen(restoreFire) { - when(restoreLast) { - frameCountReg := frameCountReg - 1.U - restoreBusyReg := false.B - restoreDoneReg := true.B - }.otherwise { - restoreArch := nextRingArch(restoreArch) - restoreOrdinal := restoreOrdinal + 1.U - } - } - } - - io.captureBusy := captureBusyReg - io.restoreBusy := restoreBusyReg - io.restoreDone := restoreDoneReg - io.frameCount := frameCountReg - io.overflow := overflowReg - io.underflow := underflowReg -} diff --git a/chisel/src/main/scala/linxcore/execute/ReducedTemplateSnapshotTable.scala b/chisel/src/main/scala/linxcore/execute/ReducedTemplateSnapshotTable.scala deleted file mode 100644 index 6591f13e..00000000 --- a/chisel/src/main/scala/linxcore/execute/ReducedTemplateSnapshotTable.scala +++ /dev/null @@ -1,51 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.log2Ceil - -class ReducedTemplateSnapshotTableIO( - val entries: Int, - val archRegs: Int, - val physRegWidth: Int) - extends Bundle { - private val indexWidth = log2Ceil(entries) - - val flush = Input(Bool()) - val writeValid = Input(Bool()) - val writeRid = Input(UInt(indexWidth.W)) - val writeMap = Input(Vec(archRegs, UInt(physRegWidth.W))) - - val captureRid = Input(UInt(indexWidth.W)) - val captureValid = Output(Bool()) - val captureMap = Output(Vec(archRegs, UInt(physRegWidth.W))) - - val restoreRid = Input(UInt(indexWidth.W)) - val restoreValid = Output(Bool()) - val restoreMap = Output(Vec(archRegs, UInt(physRegWidth.W))) -} - -class ReducedTemplateSnapshotTable( - val entries: Int = 32, - val archRegs: Int = 24, - val physRegWidth: Int = 6) - extends Module { - require(entries > 1 && (entries & (entries - 1)) == 0, - "template snapshot table follows power-of-two ROB indexing") - require(archRegs == 24, "Linx scalar template snapshot contains 24 GPR mappings") - - val io = IO(new ReducedTemplateSnapshotTableIO(entries, archRegs, physRegWidth)) - val valid = RegInit(VecInit(Seq.fill(entries)(false.B))) - val maps = Reg(Vec(entries, Vec(archRegs, UInt(physRegWidth.W)))) - - when(io.flush) { - valid := VecInit(Seq.fill(entries)(false.B)) - }.elsewhen(io.writeValid) { - valid(io.writeRid) := true.B - maps(io.writeRid) := io.writeMap - } - - io.captureValid := valid(io.captureRid) - io.captureMap := maps(io.captureRid) - io.restoreValid := valid(io.restoreRid) - io.restoreMap := maps(io.restoreRid) -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala b/chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala deleted file mode 100644 index 8322a9f6..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala +++ /dev/null @@ -1,127 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.log2Ceil - -class ScalarGPRWritePort(val tagWidth: Int, val dataWidth: Int) extends Bundle { - val requestValid = Input(Bool()) - val commit = Input(Bool()) - val tag = Input(UInt(tagWidth.W)) - val data = Input(UInt(dataWidth.W)) - val ready = Output(Bool()) - val fire = Output(Bool()) - val blockedByHigherSameTag = Output(Bool()) -} - -class ScalarGPRFileIO( - val archRegs: Int, - val physRegs: Int, - val dataWidth: Int, - val readPorts: Int, - val writePorts: Int) - extends Bundle { - private val tagWidth = log2Ceil(physRegs) - - val readValid = Input(Vec(readPorts, Bool())) - val readTag = Input(Vec(readPorts, UInt(tagWidth.W))) - val readData = Output(Vec(readPorts, UInt(dataWidth.W))) - val readReady = Output(Vec(readPorts, Bool())) - - val initValid = Input(Bool()) - val initTag = Input(UInt(tagWidth.W)) - val initData = Input(UInt(dataWidth.W)) - val clearValid = Input(Bool()) - val clearTag = Input(UInt(tagWidth.W)) - val clearSecondValid = Input(Bool()) - val clearSecondTag = Input(UInt(tagWidth.W)) - - val write = Vec(writePorts, new ScalarGPRWritePort(tagWidth, dataWidth)) - - val readyMask = Output(UInt(physRegs.W)) - val clearWriteCollision = Output(Bool()) - val duplicateWriteCommit = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ScalarGPRFile( - val archRegs: Int = 24, - val physRegs: Int = 128, - val dataWidth: Int = 64, - val readPorts: Int = 1, - val writePorts: Int = 2) - extends Module { - require(archRegs == 24, - "LinxCoreModel scalar GPR namespace has 24 architectural registers") - require(physRegs > archRegs && (physRegs & (physRegs - 1)) == 0, - "physical GPR capacity must be a power of two above the architectural namespace") - require(dataWidth > 0, "GPR data width must be positive") - require(readPorts > 0, "GPR read-port count must be positive") - require(writePorts > 0, "GPR write-port count must be positive") - - private val tagWidth = log2Ceil(physRegs) - val io = IO(new ScalarGPRFileIO(archRegs, physRegs, dataWidth, readPorts, writePorts)) - - val data = RegInit(VecInit(Seq.fill(physRegs)(0.U(dataWidth.W)))) - val ready = RegInit(VecInit((0 until physRegs).map(idx => (idx < archRegs).B))) - - for (port <- 0 until readPorts) { - io.readData(port) := data(io.readTag(port)) - io.readReady(port) := !io.readValid(port) || ready(io.readTag(port)) - } - - val blockedByHigher = Wire(Vec(writePorts, Bool())) - val writeFire = Wire(Vec(writePorts, Bool())) - for (port <- 0 until writePorts) { - val higherSameTag = - if (port == 0) false.B - else VecInit((0 until port).map(higher => - io.write(higher).requestValid && (io.write(higher).tag === io.write(port).tag))).asUInt.orR - blockedByHigher(port) := io.write(port).requestValid && higherSameTag - io.write(port).ready := !higherSameTag - writeFire(port) := io.write(port).requestValid && io.write(port).commit && !higherSameTag - io.write(port).fire := writeFire(port) - io.write(port).blockedByHigherSameTag := blockedByHigher(port) - } - - val anyWriteFire = writeFire.asUInt.orR - val clearWriteCollision = - (io.clearValid && VecInit((0 until writePorts).map(port => - writeFire(port) && (io.write(port).tag === io.clearTag))).asUInt.orR) || - (io.clearSecondValid && VecInit((0 until writePorts).map(port => - writeFire(port) && (io.write(port).tag === io.clearSecondTag))).asUInt.orR) - val duplicateClear = - io.clearValid && io.clearSecondValid && (io.clearTag === io.clearSecondTag) - val duplicateWriteCommit = - if (writePorts == 1) false.B - else VecInit((0 until writePorts).flatMap(lhs => - (lhs + 1 until writePorts).map(rhs => - writeFire(lhs) && writeFire(rhs) && (io.write(lhs).tag === io.write(rhs).tag)))).asUInt.orR - val commitWithoutRequest = VecInit((0 until writePorts).map(port => - io.write(port).commit && !io.write(port).requestValid)).asUInt.orR - - when(io.initValid) { - data(io.initTag) := io.initData - ready(io.initTag) := true.B - } - when(io.clearValid) { - ready(io.clearTag) := false.B - } - when(io.clearSecondValid) { - ready(io.clearSecondTag) := false.B - } - for (port <- 0 until writePorts) { - when(writeFire(port)) { - data(io.write(port).tag) := io.write(port).data - ready(io.write(port).tag) := true.B - } - } - - io.readyMask := ready.asUInt - io.clearWriteCollision := clearWriteCollision - io.duplicateWriteCommit := duplicateWriteCommit - io.protocolError := clearWriteCollision || duplicateClear || duplicateWriteCommit || commitWithoutRequest || - (io.initValid && anyWriteFire) - - assert(!io.protocolError, - "scalar GPR state mutation requires unique committed write ownership") -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarGPRIssueWakeupProbe.scala b/chisel/src/main/scala/linxcore/execute/ScalarGPRIssueWakeupProbe.scala deleted file mode 100644 index a0a4d7c0..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarGPRIssueWakeupProbe.scala +++ /dev/null @@ -1,122 +0,0 @@ -package linxcore.execute - -import chisel3._ -import circt.stage.ChiselStage - -import linxcore.common.{DestinationKind, InterfaceParams, OperandClass, RenamedUop} -import linxcore.rob.ROBID - -class ScalarGPRIssueWakeupProbeIO extends Bundle { - val enqueueValid = Input(Bool()) - val enqueueReady = Output(Bool()) - val sourceTag = Input(UInt(6.W)) - - val writeRequest = Input(Bool()) - val writeCommit = Input(Bool()) - val writeTag = Input(UInt(6.W)) - val writeData = Input(UInt(64.W)) - val writeReady = Output(Bool()) - val writeFire = Output(Bool()) - - val issueReady = Input(Bool()) - val sourceReady = Output(Bool()) - val wakeupMatched = Output(Bool()) - val wakeupMatchCount = Output(UInt(4.W)) - val selectedValid = Output(Bool()) - val pickFire = Output(Bool()) - val issueValid = Output(Bool()) - val issueFire = Output(Bool()) - val issueData = Output(UInt(64.W)) - val readyMask = Output(UInt(64.W)) - val protocolError = Output(Bool()) -} - -class ScalarGPRIssueWakeupProbe extends Module { - private val p = InterfaceParams(robEntries = 8, iqEntries = 4) - val io = IO(new ScalarGPRIssueWakeupProbeIO) - - val gpr = Module(new ScalarGPRFile( - archRegs = 24, - physRegs = 64, - dataWidth = 64, - readPorts = 3, - writePorts = 1 - )) - val issue = Module(new ReducedScalarIssueQueue(p, depth = 4)) - - val uop = Wire(new RenamedUop(p)) - uop := 0.U.asTypeOf(uop) - uop.valid := true.B - uop.src(0).valid := true.B - uop.src(0).operandClass := OperandClass.P - uop.src(0).relTag := 2.U - uop.src(0).physTag := io.sourceTag - uop.dst(0).valid := false.B - uop.dst(0).kind := DestinationKind.None - uop.rid := ROBID.zero(p.robEntries) - uop.bid := ROBID.zero(p.robEntries) - uop.gid := ROBID.zero(p.robEntries) - - issue.io.inValid := io.enqueueValid - issue.io.in := uop - issue.io.flushValid := false.B - issue.io.releaseValid := false.B - issue.io.releaseBid := ROBID.disabled(p.robEntries) - issue.io.releaseRid := ROBID.disabled(p.robEntries) - issue.io.releaseStid := 0.U - issue.io.secondaryReleaseValid := false.B - issue.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - issue.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - issue.io.secondaryReleaseStid := 0.U - issue.io.tertiaryReleaseValid := false.B - issue.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - issue.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - issue.io.tertiaryReleaseStid := 0.U - issue.io.readyMask := gpr.io.readyMask - issue.io.pWakeupValid := gpr.io.write(0).fire - issue.io.pWakeupTag := gpr.io.write(0).tag - issue.io.localTReadyMask := 0.U - issue.io.localUReadyMask := 0.U - issue.io.issueReady := io.issueReady - - gpr.io.initValid := false.B - gpr.io.initTag := 0.U - gpr.io.initData := 0.U - gpr.io.clearValid := false.B - gpr.io.clearTag := 0.U - gpr.io.clearSecondValid := false.B - gpr.io.clearSecondTag := 0.U - gpr.io.write(0).requestValid := io.writeRequest - gpr.io.write(0).commit := io.writeCommit - gpr.io.write(0).tag := io.writeTag - gpr.io.write(0).data := io.writeData - - for (lane <- 0 until 3) { - gpr.io.readValid(lane) := issue.io.readValid(lane) - gpr.io.readTag(lane) := issue.io.readTags(lane) - issue.io.readData(lane) := gpr.io.readData(lane) - } - issue.io.readGrant := true.B - - io.enqueueReady := issue.io.inReady - io.writeReady := gpr.io.write(0).ready - io.writeFire := gpr.io.write(0).fire - io.sourceReady := issue.io.allSourcesReady - io.wakeupMatched := issue.io.pWakeupMatched - io.wakeupMatchCount := issue.io.pWakeupMatchCount - io.selectedValid := issue.io.selectedValid - io.pickFire := issue.io.pickFire - io.issueValid := issue.io.issueValid - io.issueFire := issue.io.issueFire - io.issueData := issue.io.issueSrcData(0) - io.readyMask := gpr.io.readyMask - io.protocolError := gpr.io.protocolError -} - -object EmitScalarGPRIssueWakeupProbe extends App { - ChiselStage.emitSystemVerilogFile( - new ScalarGPRIssueWakeupProbe, - args, - firtoolOpts = Array("--disable-all-randomization", "--strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarIssueCandidateArbiter.scala b/chisel/src/main/scala/linxcore/execute/ScalarIssueCandidateArbiter.scala deleted file mode 100644 index ec71b702..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarIssueCandidateArbiter.scala +++ /dev/null @@ -1,78 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{PopCount, PriorityEncoder, UIntToOH, log2Ceil} - -import linxcore.common.InterfaceParams -import linxcore.rob.ROBID - -class ScalarIssueCandidateArbiterIO( - val p: InterfaceParams = InterfaceParams(), - val candidates: Int = 2) - extends Bundle { - private val indexWidth = log2Ceil(candidates) - - val valid = Input(Vec(candidates, Bool())) - val stid = Input(Vec(candidates, UInt(p.threadIdWidth.W))) - val rid = Input(Vec(candidates, new ROBID(p.robEntries))) - val advance = Input(Bool()) - - val grant = Output(Vec(candidates, Bool())) - val selectedValid = Output(Bool()) - val selectedIndex = Output(UInt(indexWidth.W)) - val contended = Output(Bool()) - val candidateCount = Output(UInt(log2Ceil(candidates + 1).W)) - val invalidRid = Output(Bool()) - val rrBase = Output(UInt(indexWidth.W)) -} - -class ScalarIssueCandidateArbiter( - val p: InterfaceParams = InterfaceParams(), - val candidates: Int = 2) - extends Module { - require(candidates > 1, "scalar issue arbitration needs at least two candidates") - require((candidates & (candidates - 1)) == 0, - "scalar issue candidate count must be a power of two") - - private val indexWidth = log2Ceil(candidates) - val io = IO(new ScalarIssueCandidateArbiterIO(p, candidates)) - - val rrBase = RegInit(0.U(indexWidth.W)) - val perStidOldest = Wire(Vec(candidates, Bool())) - for (candidate <- 0 until candidates) { - val olderPeer = VecInit((0 until candidates).filter(_ != candidate).map { peer => - val peerWinsTie = peer < candidate - io.valid(peer) && - (io.stid(peer) === io.stid(candidate)) && - (ROBID.less(io.rid(peer), io.rid(candidate)) || - (ROBID.equal(io.rid(peer), io.rid(candidate)) && peerWinsTie.B)) - }).asUInt.orR - perStidOldest(candidate) := io.valid(candidate) && !olderPeer - } - - val scanValid = Wire(Vec(candidates, Bool())) - for (offset <- 0 until candidates) { - val candidate = (rrBase + offset.U)(indexWidth - 1, 0) - scanValid(offset) := perStidOldest(candidate) - } - val selectedValid = scanValid.asUInt.orR - val selectedOffset = PriorityEncoder(scanValid.asUInt) - val selectedIndex = (rrBase + selectedOffset)(indexWidth - 1, 0) - val grantMask = Mux(selectedValid, UIntToOH(selectedIndex, candidates), 0.U) - val candidateCount = PopCount(io.valid) - val invalidRid = VecInit((0 until candidates).map(idx => io.valid(idx) && !io.rid(idx).valid)).asUInt.orR - - io.grant := VecInit(grantMask.asBools) - io.selectedValid := selectedValid - io.selectedIndex := selectedIndex - io.contended := candidateCount > 1.U - io.candidateCount := candidateCount - io.invalidRid := invalidRid - io.rrBase := rrBase - - when(io.advance && selectedValid) { - rrBase := selectedIndex + 1.U - } - - assert(!invalidRid, "scalar issue arbitration requires a valid RID for every candidate") -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarIssueExternalControlFence.scala b/chisel/src/main/scala/linxcore/execute/ScalarIssueExternalControlFence.scala deleted file mode 100644 index 5d9fa946..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarIssueExternalControlFence.scala +++ /dev/null @@ -1,46 +0,0 @@ -package linxcore.execute - -import chisel3._ - -import linxcore.common.InterfaceParams -import linxcore.rob.ROBID - -class ScalarIssueExternalControlFenceIO(val p: InterfaceParams) extends Bundle { - val captureValid = Input(Bool()) - val captureBid = Input(new ROBID(p.robEntries)) - val captureRid = Input(new ROBID(p.robEntries)) - val captureStid = Input(UInt(p.threadIdWidth.W)) - val clear = Input(Bool()) - - val valid = Output(Bool()) - val bid = Output(new ROBID(p.robEntries)) - val rid = Output(new ROBID(p.robEntries)) - val stid = Output(UInt(p.threadIdWidth.W)) -} - -/** Retains a resolved redirect identity until central recovery accepts cleanup. */ -class ScalarIssueExternalControlFence(val p: InterfaceParams = InterfaceParams()) extends Module { - val io = IO(new ScalarIssueExternalControlFenceIO(p)) - - val valid = RegInit(false.B) - val bid = RegInit(0.U.asTypeOf(new ROBID(p.robEntries))) - val rid = RegInit(0.U.asTypeOf(new ROBID(p.robEntries))) - val stid = RegInit(0.U(p.threadIdWidth.W)) - - when(io.clear) { - valid := false.B - }.elsewhen(io.captureValid) { - valid := true.B - bid := io.captureBid - rid := io.captureRid - stid := io.captureStid - } - - io.valid := valid - io.bid := bid - io.rid := rid - io.stid := stid - - assert(!valid || (bid.valid && rid.valid), - "retained scalar issue control fence requires exact BID/RID identity") -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala b/chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala deleted file mode 100644 index 43ee846d..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala +++ /dev/null @@ -1,407 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{Mux1H, PopCount, PriorityEncoder, log2Ceil} - -import linxcore.common.{InterfaceParams, OperandClass, RenamedUop, ScalarSpAccess} -import linxcore.rob.ROBID - -class ScalarIssueFabricIO( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 8, - val bankCount: Int = 2, - val stidCount: Int = 1) - extends Bundle { - private val countWidth = log2Ceil(depth + 1) - private val indexWidth = log2Ceil(depth) - private val bankWidth = log2Ceil(bankCount) - - val inValid = Input(Bool()) - val inReady = Output(Bool()) - val in = Input(new RenamedUop(p)) - val flushValid = Input(Bool()) - - val releaseValid = Input(Bool()) - val releaseBid = Input(new ROBID(p.robEntries)) - val releaseRid = Input(new ROBID(p.robEntries)) - val releaseStid = Input(UInt(p.threadIdWidth.W)) - val secondaryReleaseValid = Input(Bool()) - val secondaryReleaseBid = Input(new ROBID(p.robEntries)) - val secondaryReleaseRid = Input(new ROBID(p.robEntries)) - val secondaryReleaseStid = Input(UInt(p.threadIdWidth.W)) - val tertiaryReleaseValid = Input(Bool()) - val tertiaryReleaseBid = Input(new ROBID(p.robEntries)) - val tertiaryReleaseRid = Input(new ROBID(p.robEntries)) - val tertiaryReleaseStid = Input(UInt(p.threadIdWidth.W)) - val externalControlFenceValid = Input(Bool()) - val externalControlFenceBid = Input(new ROBID(p.robEntries)) - val externalControlFenceRid = Input(new ROBID(p.robEntries)) - val externalControlFenceStid = Input(UInt(p.threadIdWidth.W)) - val scalarSpHeadValidByStid = Input(Vec(stidCount, Bool())) - val scalarSpHeadBidByStid = Input(Vec(stidCount, new ROBID(p.robEntries))) - val scalarSpHeadRidByStid = Input(Vec(stidCount, new ROBID(p.robEntries))) - val scalarSpSnapshotByStid = Input(Vec(stidCount, UInt(p.immWidth.W))) - - val readyMask = Input(UInt((1 << p.physRegWidth).W)) - val pWakeupValid = Input(Bool()) - val pWakeupTag = Input(UInt(p.physRegWidth.W)) - val localTReadyMask = Input(UInt(4.W)) - val localUReadyMask = Input(UInt(4.W)) - val readValid = Output(Vec(3, Bool())) - val readTags = Output(Vec(3, UInt(p.physRegWidth.W))) - val readOperandClass = Output(Vec(3, OperandClass())) - val readRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val readData = Input(Vec(3, UInt(p.immWidth.W))) - - val issueValid = Output(Bool()) - val issueReady = Input(Bool()) - val issueUop = Output(new RenamedUop(p)) - val issueSrcData = Output(Vec(3, UInt(p.immWidth.W))) - val scalarSpReadSnapshot = Output(UInt(p.immWidth.W)) - val scalarSpIssueSnapshot = Output(UInt(p.immWidth.W)) - - val inputAcceptFire = Output(Bool()) - val inputAcceptUop = Output(new RenamedUop(p)) - val inputAcceptDstValid = Output(Bool()) - val inputAcceptDstTag = Output(UInt(p.physRegWidth.W)) - val enqueueFire = Output(Bool()) - val enqueueCount = Output(UInt(log2Ceil(bankCount + 1).W)) - val bankEnqueueFireMask = Output(UInt(bankCount.W)) - val bankEnqueueUop = Output(Vec(bankCount, new RenamedUop(p))) - val pickFire = Output(Bool()) - val issueFire = Output(Bool()) - val cancelFire = Output(Bool()) - val releaseFire = Output(Bool()) - val enqueueDstValid = Output(Bool()) - val enqueueDstTag = Output(UInt(p.physRegWidth.W)) - - val empty = Output(Bool()) - val full = Output(Bool()) - val count = Output(UInt(countWidth.W)) - val issuedCount = Output(UInt(countWidth.W)) - val notIssuedCount = Output(UInt(countWidth.W)) - val headValid = Output(Bool()) - val headIssued = Output(Bool()) - val headPc = Output(UInt(p.pcWidth.W)) - val headOpcode = Output(UInt(p.opcodeWidth.W)) - val headStid = Output(UInt(p.threadIdWidth.W)) - val headBid = Output(new ROBID(p.robEntries)) - val headRid = Output(new ROBID(p.robEntries)) - val headSrcValidMask = Output(UInt(3.W)) - val headSrcOperandClass = Output(Vec(3, OperandClass())) - val headSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val headSrcRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val sourceReadyMask = Output(UInt(3.W)) - val allSourcesReady = Output(Bool()) - val pWakeupMatched = Output(Bool()) - val pWakeupMatchCount = Output(UInt(log2Ceil(depth * 3 + 1).W)) - val selectedValid = Output(Bool()) - val selectedIndex = Output(UInt(indexWidth.W)) - val selectedReadReady = Output(Bool()) - val i1Valid = Output(Bool()) - val i2Valid = Output(Bool()) - val stageBusy = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByRead = Output(Bool()) - val blockedByOutput = Output(Bool()) - val blockedByIssued = Output(Bool()) - - val enqueueBank = Output(UInt(bankWidth.W)) - val readGrantBank = Output(UInt(bankWidth.W)) - val issueGrantBank = Output(UInt(bankWidth.W)) - val bankOccupancy = Output(Vec(bankCount, UInt(log2Ceil(depth / bankCount + 1).W))) - val bankPickMask = Output(UInt(bankCount.W)) - val bankReadAttemptMask = Output(UInt(bankCount.W)) - val bankReadGrantMask = Output(UInt(bankCount.W)) - val bankIssueValidMask = Output(UInt(bankCount.W)) - val bankIssueGrantMask = Output(UInt(bankCount.W)) - val simultaneousPick = Output(Bool()) - val readContention = Output(Bool()) - val readArbitrationLoss = Output(Bool()) - val issueContention = Output(Bool()) - val controlFenceActive = Output(Bool()) - val controlFenceBlocked = Output(Bool()) - val bankControlBlockedMask = Output(UInt(bankCount.W)) - val storeOrderBlocked = Output(Bool()) - val bankStoreOrderBlockedMask = Output(UInt(bankCount.W)) - val scalarSpOrderBlocked = Output(Bool()) - val bankScalarSpOrderBlockedMask = Output(UInt(bankCount.W)) - val protocolError = Output(Bool()) -} - -class ScalarIssueFabric( - val p: InterfaceParams = InterfaceParams(), - val depth: Int = 8, - val bankCount: Int = 2, - val stidCount: Int = 1) - extends Module { - require(depth >= bankCount * 2, "each scalar issue bank needs at least two entries") - require((depth & (depth - 1)) == 0, "scalar issue fabric depth must be a power of two") - require(bankCount > 1 && (bankCount & (bankCount - 1)) == 0, - "scalar issue bank count must be a power of two greater than one") - require(bankCount == 2, "scalar issue ingress skid currently supports exactly two banks") - require(depth % bankCount == 0, "scalar issue depth must divide evenly across banks") - require(stidCount > 0, "scalar issue fabric must expose at least one STID") - - private val bankDepth = depth / bankCount - private val bankWidth = log2Ceil(bankCount) - private val countWidth = log2Ceil(depth + 1) - private val indexWidth = log2Ceil(depth) - private val stidIndexWidth = math.max(1, log2Ceil(stidCount)) - private def stidIndex(stid: UInt): UInt = - if (stidCount == 1) 0.U(stidIndexWidth.W) else stid(stidIndexWidth - 1, 0) - - val io = IO(new ScalarIssueFabricIO(p, depth, bankCount, stidCount)) - - val banks = Seq.fill(bankCount)(Module(new ReducedScalarIssueQueue(p, bankDepth, stidCount))) - val ingress = Module(new ScalarIssueIngressSkid2(p)) - for (bank <- banks) { - bank.io.flushValid := io.flushValid - bank.io.releaseValid := io.releaseValid - bank.io.releaseBid := io.releaseBid - bank.io.releaseRid := io.releaseRid - bank.io.releaseStid := io.releaseStid - bank.io.secondaryReleaseValid := io.secondaryReleaseValid - bank.io.secondaryReleaseBid := io.secondaryReleaseBid - bank.io.secondaryReleaseRid := io.secondaryReleaseRid - bank.io.secondaryReleaseStid := io.secondaryReleaseStid - bank.io.tertiaryReleaseValid := io.tertiaryReleaseValid - bank.io.tertiaryReleaseBid := io.tertiaryReleaseBid - bank.io.tertiaryReleaseRid := io.tertiaryReleaseRid - bank.io.tertiaryReleaseStid := io.tertiaryReleaseStid - bank.io.scalarSpHeadValidByStid := io.scalarSpHeadValidByStid - bank.io.scalarSpHeadBidByStid := io.scalarSpHeadBidByStid - bank.io.scalarSpHeadRidByStid := io.scalarSpHeadRidByStid - bank.io.readyMask := io.readyMask - bank.io.pWakeupValid := io.pWakeupValid - bank.io.pWakeupTag := io.pWakeupTag - bank.io.localTReadyMask := io.localTReadyMask - bank.io.localUReadyMask := io.localUReadyMask - } - - val routeValidStages = Wire(Vec(bankCount + 1, Bool())) - val routeBankStages = Wire(Vec(bankCount + 1, UInt(bankWidth.W))) - val routeCountStages = Wire(Vec(bankCount + 1, UInt(log2Ceil(depth + 1).W))) - routeValidStages(0) := false.B - routeBankStages(0) := 0.U - routeCountStages(0) := depth.U - for (idx <- 0 until bankCount) { - val effectiveCount = - (banks(idx).io.count.pad(countWidth) + ingress.io.bankOccupancy(idx).pad(countWidth))(countWidth - 1, 0) - val take = !routeValidStages(idx) || effectiveCount < routeCountStages(idx) - routeValidStages(idx + 1) := true.B - routeBankStages(idx + 1) := Mux(take, idx.U, routeBankStages(idx)) - routeCountStages(idx + 1) := Mux(take, effectiveCount, routeCountStages(idx)) - } - val routeBank = routeBankStages(bankCount) - - ingress.io.inValid := io.inValid - ingress.io.in := io.in - ingress.io.inBank := routeBank - ingress.io.flushValid := io.flushValid - for (idx <- 0 until bankCount) { - ingress.io.drainCanConsume(idx) := banks(idx).io.inReady - banks(idx).io.inValid := ingress.io.drainFire(idx) - banks(idx).io.in := ingress.io.drainPreview(idx) - } - io.inReady := ingress.io.inReady - - val readArbiter = Module(new ScalarIssueCandidateArbiter(p, bankCount)) - val issueArbiter = Module(new ScalarIssueCandidateArbiter(p, bankCount)) - val controlBlocked = Wire(Vec(bankCount, Bool())) - val storeOrderBlocked = Wire(Vec(bankCount, Bool())) - val scalarSpOrderBlocked = Wire(Vec(bankCount, Bool())) - for (idx <- 0 until bankCount) { - val candidate = banks(idx).io.readUop - val candidateRedirectsControl = - candidate.dispatchTarget === linxcore.common.DispatchTarget.Bru || - candidate.opcode === linxcore.frontend.FrontendOpcodeDecodeTable.OP_FRET_STK.U(p.opcodeWidth.W) - val candidateSpAccess = ScalarSpAccess.classify(candidate) - val candidateStid = stidIndex(candidate.threadId) - val candidateMatchesScalarSpHead = - !candidateSpAccess.valid || - (io.scalarSpHeadValidByStid(candidateStid) && - ROBID.equal(candidate.bid, io.scalarSpHeadBidByStid(candidateStid)) && - ROBID.equal(candidate.rid, io.scalarSpHeadRidByStid(candidateStid))) - val blockedByOlderControl = VecInit(banks.flatMap { bank => - (0 until bankDepth).map { row => - val control = bank.io.residentControlUop(row) - bank.io.residentControlValid(row) && - (control.threadId === candidate.threadId) && - ROBID.greater(candidate.rid, control.rid) - } - }).asUInt.orR || - (io.externalControlFenceValid && - (io.externalControlFenceStid === candidate.threadId) && - ROBID.greater(candidate.rid, io.externalControlFenceRid)) - // A redirecting uop is also the tail of its own recovery boundary. It - // must not bypass an older resident row in another bank: otherwise the - // redirect flush can discard that already-issued older row before it - // reaches writeback. RID is the global order within one STID, so this - // comparison remains valid across BID changes and RID wrap-around. - // - // This reduced guard intentionally observes only each physical FIFO head. - // That is complete for the current single-STID natural top because every - // bank head is the oldest resident row in that bank. With multiple STIDs, - // an older same-STID row can sit behind another STID's head; full multi-STID - // closure therefore needs a per-STID oldest-resident export from each bank. - val redirectBlockedByOlderResident = candidateRedirectsControl && VecInit(banks.map { bank => - bank.io.headValid && - (bank.io.headStid === candidate.threadId) && - ROBID.greater(candidate.rid, bank.io.headRid) - }).asUInt.orR - controlBlocked(idx) := - banks(idx).io.readAttemptValid && (blockedByOlderControl || redirectBlockedByOlderResident) - val blockedByOlderStore = candidate.isStore && VecInit(banks.flatMap { bank => - (0 until bankDepth).map { row => - val store = bank.io.residentStoreUop(row) - bank.io.residentStoreValid(row) && - (store.threadId === candidate.threadId) && - ROBID.greater(candidate.rid, store.rid) - } - }).asUInt.orR - storeOrderBlocked(idx) := banks(idx).io.readAttemptValid && blockedByOlderStore - scalarSpOrderBlocked(idx) := banks(idx).io.readAttemptValid && candidateSpAccess.valid && !candidateMatchesScalarSpHead - readArbiter.io.valid(idx) := banks(idx).io.readAttemptValid && - !blockedByOlderControl && !redirectBlockedByOlderResident && - !blockedByOlderStore && !scalarSpOrderBlocked(idx) - readArbiter.io.stid(idx) := banks(idx).io.readUop.threadId - readArbiter.io.rid(idx) := banks(idx).io.readUop.rid - banks(idx).io.readGrant := readArbiter.io.grant(idx) - - issueArbiter.io.valid(idx) := banks(idx).io.issueValid - issueArbiter.io.stid(idx) := banks(idx).io.issueUop.threadId - issueArbiter.io.rid(idx) := banks(idx).io.issueUop.rid - banks(idx).io.issueReady := issueArbiter.io.grant(idx) && io.issueReady - } - readArbiter.io.advance := VecInit(banks.map(_.io.readFire)).asUInt.orR - issueArbiter.io.advance := VecInit(banks.map(_.io.issueFire)).asUInt.orR - - for (lane <- 0 until 3) { - io.readValid(lane) := Mux1H(readArbiter.io.grant, banks.map(_.io.readValid(lane))) - io.readTags(lane) := Mux1H(readArbiter.io.grant, banks.map(_.io.readTags(lane))) - io.readOperandClass(lane) := OperandClass.P - io.readRelTag(lane) := Mux1H(readArbiter.io.grant, banks.map(_.io.readRelTag(lane))) - for (idx <- 0 until bankCount) { - when(readArbiter.io.grant(idx)) { - io.readOperandClass(lane) := banks(idx).io.readOperandClass(lane) - } - banks(idx).io.readData(lane) := Mux(readArbiter.io.grant(idx), io.readData(lane), 0.U) - } - io.issueSrcData(lane) := Mux1H(issueArbiter.io.grant, banks.map(_.io.issueSrcData(lane))) - } - io.scalarSpReadSnapshot := Mux1H((0 until bankCount).map { idx => - readArbiter.io.grant(idx) -> io.scalarSpSnapshotByStid(stidIndex(banks(idx).io.readUop.threadId)) - }) - io.scalarSpIssueSnapshot := Mux1H((0 until bankCount).map { idx => - issueArbiter.io.grant(idx) -> io.scalarSpSnapshotByStid(stidIndex(banks(idx).io.issueUop.threadId)) - }) - io.issueValid := issueArbiter.io.selectedValid - io.issueUop := 0.U.asTypeOf(new RenamedUop(p)) - for (idx <- 0 until bankCount) { - when(issueArbiter.io.grant(idx)) { - io.issueUop := banks(idx).io.issueUop - } - } - - val headBankValid = VecInit(banks.map(_.io.headValid)) - val headBank = PriorityEncoder(headBankValid.asUInt) - val headSelect = VecInit((0 until bankCount).map(idx => headBankValid(idx) && headBank === idx.U)) - val selectedBankValid = VecInit(banks.map(_.io.selectedValid)) - val selectedBank = PriorityEncoder(selectedBankValid.asUInt) - val selectedSelect = VecInit((0 until bankCount).map(idx => selectedBankValid(idx) && selectedBank === idx.U)) - - val totalCount = banks.map(_.io.count.pad(countWidth)).reduce(_ + _) - val totalIssued = banks.map(_.io.issuedCount.pad(countWidth)).reduce(_ + _) - val totalNotIssued = banks.map(_.io.notIssuedCount.pad(countWidth)).reduce(_ + _) - val wakeupCount = banks.map(_.io.pWakeupMatchCount.pad(log2Ceil(depth * 3 + 1))).reduce(_ + _) - val pickMask = VecInit(banks.map(_.io.pickFire)).asUInt - val readAttemptMask = VecInit(banks.map(_.io.readAttemptValid)).asUInt - val issueValidMask = VecInit(banks.map(_.io.issueValid)).asUInt - - val bankEnqueueMask = VecInit(banks.map(_.io.enqueueFire)).asUInt - val inputAcceptFire = io.inValid && io.inReady - io.inputAcceptFire := inputAcceptFire - io.inputAcceptUop := io.in - io.inputAcceptDstValid := inputAcceptFire && io.in.dst(0).valid && (io.in.dst(0).kind === linxcore.common.DestinationKind.Gpr) - io.inputAcceptDstTag := io.in.dst(0).physTag - io.enqueueFire := io.inputAcceptFire - io.enqueueCount := PopCount(bankEnqueueMask) - io.bankEnqueueFireMask := bankEnqueueMask - for (idx <- 0 until bankCount) { - io.bankEnqueueUop(idx) := Mux(banks(idx).io.enqueueFire, banks(idx).io.in, 0.U.asTypeOf(new RenamedUop(p))) - } - io.pickFire := pickMask.orR - io.issueFire := VecInit(banks.map(_.io.issueFire)).asUInt.orR - io.cancelFire := VecInit(banks.map(_.io.cancelFire)).asUInt.orR - io.releaseFire := VecInit(banks.map(_.io.releaseFire)).asUInt.orR - io.enqueueDstValid := io.inputAcceptDstValid - io.enqueueDstTag := io.inputAcceptDstTag - io.empty := totalCount === 0.U && ingress.io.empty - io.full := ingress.io.full - io.count := totalCount + ingress.io.count.pad(countWidth) - io.issuedCount := totalIssued - io.notIssuedCount := totalNotIssued - io.headValid := headBankValid.asUInt.orR - io.headIssued := Mux1H(headSelect, banks.map(_.io.headIssued)) - io.headPc := Mux1H(headSelect, banks.map(_.io.headPc)) - io.headOpcode := Mux1H(headSelect, banks.map(_.io.headOpcode)) - io.headStid := Mux1H(headSelect, banks.map(_.io.headStid)) - io.headBid := Mux1H(headSelect, banks.map(_.io.headBid)) - io.headRid := Mux1H(headSelect, banks.map(_.io.headRid)) - io.headSrcValidMask := Mux1H(headSelect, banks.map(_.io.headSrcValidMask)) - for (lane <- 0 until 3) { - io.headSrcOperandClass(lane) := OperandClass.P - for (idx <- 0 until bankCount) { - when(headSelect(idx)) { - io.headSrcOperandClass(lane) := banks(idx).io.headSrcOperandClass(lane) - } - } - io.headSrcPhysTag(lane) := Mux1H(headSelect, banks.map(_.io.headSrcPhysTag(lane))) - io.headSrcRelTag(lane) := Mux1H(headSelect, banks.map(_.io.headSrcRelTag(lane))) - } - io.sourceReadyMask := Mux1H(headSelect, banks.map(_.io.sourceReadyMask)) - io.allSourcesReady := Mux1H(headSelect, banks.map(_.io.allSourcesReady)) - io.pWakeupMatched := wakeupCount =/= 0.U - io.pWakeupMatchCount := wakeupCount - io.selectedValid := selectedBankValid.asUInt.orR - io.selectedIndex := Mux1H(selectedSelect, (0 until bankCount).map { idx => - (idx * bankDepth).U(indexWidth.W) + banks(idx).io.selectedIndex.pad(indexWidth) - }) - io.selectedReadReady := Mux1H(selectedSelect, banks.map(_.io.selectedReadReady)) - io.i1Valid := VecInit(banks.map(_.io.i1Valid)).asUInt.orR - io.i2Valid := VecInit(banks.map(_.io.i2Valid)).asUInt.orR - io.stageBusy := VecInit(banks.map(_.io.stageBusy)).asUInt.orR - io.blockedBySource := VecInit(banks.map(_.io.blockedBySource)).asUInt.orR - io.blockedByRead := VecInit(banks.map(_.io.blockedByRead)).asUInt.orR - io.blockedByOutput := VecInit(banks.map(_.io.blockedByOutput)).asUInt.orR - io.blockedByIssued := VecInit(banks.map(_.io.blockedByIssued)).asUInt.orR - - io.enqueueBank := routeBank - io.readGrantBank := readArbiter.io.selectedIndex - io.issueGrantBank := issueArbiter.io.selectedIndex - for (idx <- 0 until bankCount) { - io.bankOccupancy(idx) := banks(idx).io.count - } - io.bankPickMask := pickMask - io.bankReadAttemptMask := readAttemptMask - io.bankReadGrantMask := readArbiter.io.grant.asUInt - io.bankIssueValidMask := issueValidMask - io.bankIssueGrantMask := issueArbiter.io.grant.asUInt - io.simultaneousPick := PopCount(pickMask) > 1.U - io.readContention := readArbiter.io.contended - io.readArbitrationLoss := readArbiter.io.contended && readArbiter.io.selectedValid - io.issueContention := issueArbiter.io.contended - io.controlFenceActive := io.externalControlFenceValid || VecInit(banks.flatMap { bank => - (0 until bankDepth).map(bank.io.residentControlValid(_)) - }).asUInt.orR - io.controlFenceBlocked := controlBlocked.asUInt.orR - io.bankControlBlockedMask := controlBlocked.asUInt - io.storeOrderBlocked := storeOrderBlocked.asUInt.orR - io.bankStoreOrderBlockedMask := storeOrderBlocked.asUInt - io.scalarSpOrderBlocked := scalarSpOrderBlocked.asUInt.orR - io.bankScalarSpOrderBlockedMask := scalarSpOrderBlocked.asUInt - io.protocolError := readArbiter.io.invalidRid || issueArbiter.io.invalidRid || - (io.externalControlFenceValid && - (!io.externalControlFenceBid.valid || !io.externalControlFenceRid.valid)) -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarIssueFabricProbe.scala b/chisel/src/main/scala/linxcore/execute/ScalarIssueFabricProbe.scala deleted file mode 100644 index ad27c0e2..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarIssueFabricProbe.scala +++ /dev/null @@ -1,190 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.common.{DestinationKind, DispatchTarget, InterfaceParams, OperandClass, RenamedUop} -import linxcore.rob.ROBID - -class ScalarIssueFabricProbeIO(val p: InterfaceParams, val depth: Int, val banks: Int) extends Bundle { - val enqueueValid = Input(Bool()) - val enqueueReady = Output(Bool()) - val enqueueStid = Input(UInt(p.threadIdWidth.W)) - val enqueueRid = Input(UInt(log2Ceil(p.robEntries).W)) - val enqueuePc = Input(UInt(p.pcWidth.W)) - val enqueueBru = Input(Bool()) - val enqueueStore = Input(Bool()) - val sourceTag = Input(UInt(p.physRegWidth.W)) - val wakeupValid = Input(Bool()) - val issueReady = Input(Bool()) - val flush = Input(Bool()) - val releaseValid = Input(Bool()) - val releaseStid = Input(UInt(p.threadIdWidth.W)) - val releaseRid = Input(UInt(log2Ceil(p.robEntries).W)) - - val count = Output(UInt(log2Ceil(depth + 1).W)) - val inputAcceptFire = Output(Bool()) - val inputAcceptRid = Output(UInt(log2Ceil(p.robEntries).W)) - val inputAcceptDstValid = Output(Bool()) - val inputAcceptDstTag = Output(UInt(p.physRegWidth.W)) - val enqueueBank = Output(UInt(log2Ceil(banks).W)) - val enqueueCount = Output(UInt(log2Ceil(banks + 1).W)) - val bankEnqueueFireMask = Output(UInt(banks.W)) - val bankEnqueueRid = Output(Vec(banks, UInt(log2Ceil(p.robEntries).W))) - val bankOccupancy = Output(Vec(banks, UInt(log2Ceil(depth / banks + 1).W))) - val bankPickMask = Output(UInt(banks.W)) - val bankReadAttemptMask = Output(UInt(banks.W)) - val bankReadGrantMask = Output(UInt(banks.W)) - val bankIssueValidMask = Output(UInt(banks.W)) - val bankIssueGrantMask = Output(UInt(banks.W)) - val simultaneousPick = Output(Bool()) - val readContention = Output(Bool()) - val readArbitrationLoss = Output(Bool()) - val cancelFire = Output(Bool()) - val issueContention = Output(Bool()) - val controlFenceActive = Output(Bool()) - val controlFenceBlocked = Output(Bool()) - val bankControlBlockedMask = Output(UInt(banks.W)) - val storeOrderBlocked = Output(Bool()) - val bankStoreOrderBlockedMask = Output(UInt(banks.W)) - val issueFire = Output(Bool()) - val issueStid = Output(UInt(p.threadIdWidth.W)) - val issueRid = Output(UInt(log2Ceil(p.robEntries).W)) - val issueData = Output(UInt(p.immWidth.W)) - val protocolError = Output(Bool()) - - val policyValidMask = Input(UInt(banks.W)) - val policyStid = Input(Vec(banks, UInt(p.threadIdWidth.W))) - val policyRid = Input(Vec(banks, UInt(log2Ceil(p.robEntries).W))) - val policyAdvance = Input(Bool()) - val policyGrantMask = Output(UInt(banks.W)) - val policySelectedIndex = Output(UInt(log2Ceil(banks).W)) - val policyContended = Output(Bool()) - val policyRrBase = Output(UInt(log2Ceil(banks).W)) -} - -class ScalarIssueFabricProbe( - val p: InterfaceParams = InterfaceParams(robEntries = 8), - val depth: Int = 4, - val banks: Int = 2) - extends Module { - val io = IO(new ScalarIssueFabricProbeIO(p, depth, banks)) - val fabric = Module(new ScalarIssueFabric(p, depth, banks)) - val policy = Module(new ScalarIssueCandidateArbiter(p, banks)) - - val enqueue = Wire(new RenamedUop(p)) - enqueue := 0.U.asTypeOf(enqueue) - enqueue.valid := true.B - enqueue.pc := io.enqueuePc - enqueue.threadId := io.enqueueStid - enqueue.dispatchTarget := Mux(io.enqueueBru, DispatchTarget.Bru, DispatchTarget.Alu) - enqueue.isStore := io.enqueueStore - enqueue.bid.valid := true.B - enqueue.bid.wrap := false.B - enqueue.bid.value := 0.U - enqueue.rid.valid := true.B - enqueue.rid.wrap := false.B - enqueue.rid.value := io.enqueueRid - enqueue.src(0).valid := true.B - enqueue.src(0).operandClass := OperandClass.P - enqueue.src(0).relTag := 2.U - enqueue.src(0).physTag := io.sourceTag - enqueue.dst(0).valid := false.B - enqueue.dst(0).kind := DestinationKind.None - - fabric.io.inValid := io.enqueueValid - fabric.io.in := enqueue - fabric.io.flushValid := io.flush - fabric.io.releaseValid := io.releaseValid - fabric.io.releaseBid.valid := true.B - fabric.io.releaseBid.wrap := false.B - fabric.io.releaseBid.value := 0.U - fabric.io.releaseRid.valid := io.releaseValid - fabric.io.releaseRid.wrap := false.B - fabric.io.releaseRid.value := io.releaseRid - fabric.io.releaseStid := io.releaseStid - fabric.io.secondaryReleaseValid := false.B - fabric.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseStid := 0.U - fabric.io.tertiaryReleaseValid := false.B - fabric.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseStid := 0.U - fabric.io.externalControlFenceValid := false.B - fabric.io.externalControlFenceBid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceRid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceStid := 0.U - fabric.io.scalarSpHeadValidByStid(0) := true.B - fabric.io.scalarSpHeadBidByStid(0).valid := true.B - fabric.io.scalarSpHeadBidByStid(0).wrap := false.B - fabric.io.scalarSpHeadBidByStid(0).value := 0.U - fabric.io.scalarSpHeadRidByStid(0).valid := true.B - fabric.io.scalarSpHeadRidByStid(0).wrap := false.B - fabric.io.scalarSpHeadRidByStid(0).value := io.enqueueRid - fabric.io.scalarSpSnapshotByStid(0) := 0.U - fabric.io.readyMask := 0.U - fabric.io.pWakeupValid := io.wakeupValid - fabric.io.pWakeupTag := io.sourceTag - fabric.io.localTReadyMask := 0.U - fabric.io.localUReadyMask := 0.U - for (lane <- 0 until 3) { - fabric.io.readData(lane) := fabric.io.readTags(lane) + (0x100 + lane).U - } - fabric.io.issueReady := io.issueReady - - for (idx <- 0 until banks) { - policy.io.valid(idx) := io.policyValidMask(idx) - policy.io.stid(idx) := io.policyStid(idx) - policy.io.rid(idx).valid := true.B - policy.io.rid(idx).wrap := false.B - policy.io.rid(idx).value := io.policyRid(idx) - } - policy.io.advance := io.policyAdvance - - io.enqueueReady := fabric.io.inReady - io.count := fabric.io.count - io.inputAcceptFire := fabric.io.inputAcceptFire - io.inputAcceptRid := fabric.io.inputAcceptUop.rid.value - io.inputAcceptDstValid := fabric.io.inputAcceptDstValid - io.inputAcceptDstTag := fabric.io.inputAcceptDstTag - io.enqueueBank := fabric.io.enqueueBank - io.enqueueCount := fabric.io.enqueueCount - io.bankEnqueueFireMask := fabric.io.bankEnqueueFireMask - for (idx <- 0 until banks) { - io.bankEnqueueRid(idx) := fabric.io.bankEnqueueUop(idx).rid.value - } - io.bankOccupancy := fabric.io.bankOccupancy - io.bankPickMask := fabric.io.bankPickMask - io.bankReadAttemptMask := fabric.io.bankReadAttemptMask - io.bankReadGrantMask := fabric.io.bankReadGrantMask - io.bankIssueValidMask := fabric.io.bankIssueValidMask - io.bankIssueGrantMask := fabric.io.bankIssueGrantMask - io.simultaneousPick := fabric.io.simultaneousPick - io.readContention := fabric.io.readContention - io.readArbitrationLoss := fabric.io.readArbitrationLoss - io.cancelFire := fabric.io.cancelFire - io.issueContention := fabric.io.issueContention - io.controlFenceActive := fabric.io.controlFenceActive - io.controlFenceBlocked := fabric.io.controlFenceBlocked - io.bankControlBlockedMask := fabric.io.bankControlBlockedMask - io.storeOrderBlocked := fabric.io.storeOrderBlocked - io.bankStoreOrderBlockedMask := fabric.io.bankStoreOrderBlockedMask - io.issueFire := fabric.io.issueFire - io.issueStid := fabric.io.issueUop.threadId - io.issueRid := fabric.io.issueUop.rid.value - io.issueData := fabric.io.issueSrcData(0) - io.protocolError := fabric.io.protocolError - io.policyGrantMask := policy.io.grant.asUInt - io.policySelectedIndex := policy.io.selectedIndex - io.policyContended := policy.io.contended - io.policyRrBase := policy.io.rrBase -} - -object ElaborateScalarIssueFabricProbe extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new ScalarIssueFabricProbe(), - args, - Array("--strip-debug-info", "--disable-all-randomization") - ) -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarIssueIngressSkid2.scala b/chisel/src/main/scala/linxcore/execute/ScalarIssueIngressSkid2.scala deleted file mode 100644 index 4d67f3f6..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarIssueIngressSkid2.scala +++ /dev/null @@ -1,165 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{PopCount, log2Ceil} - -import linxcore.common.{InterfaceParams, RenamedUop} - -/** Two-entry registered issue-ingress skid. - * - * `drainPresent`/`drainPreview` are presentation-only: they may expose a - * younger dual-eligible row even when that bank cannot consume it yet. - * `drainCanConsume` is the downstream bank's consume credit, and only - * `drainFire` is the accepted dequeue event that may mutate downstream state. - */ -class ScalarIssueIngressSkid2IO(val p: InterfaceParams = InterfaceParams()) extends Bundle { - val inValid = Input(Bool()) - val inReady = Output(Bool()) - val in = Input(new RenamedUop(p)) - val inBank = Input(UInt(1.W)) - val flushValid = Input(Bool()) - - val drainCanConsume = Input(Vec(2, Bool())) - val drainPresent = Output(Vec(2, Bool())) - val drainPreview = Output(Vec(2, new RenamedUop(p))) - val drainFire = Output(Vec(2, Bool())) - - val empty = Output(Bool()) - val full = Output(Bool()) - val count = Output(UInt(log2Ceil(3).W)) - val bankOccupancy = Output(Vec(2, UInt(log2Ceil(3).W))) - val dualDrainEligible = Output(Bool()) - val dualDrainFire = Output(Bool()) - val olderOnlyFire = Output(Bool()) -} - -class ScalarIssueIngressSkid2(val p: InterfaceParams = InterfaceParams()) extends Module { - val io = IO(new ScalarIssueIngressSkid2IO(p)) - - private val depth = 2 - private val countWidth = log2Ceil(depth + 1) - - val entries = RegInit(VecInit(Seq.fill(depth)(0.U.asTypeOf(new RenamedUop(p))))) - val banks = RegInit(VecInit(Seq.fill(depth)(0.U(1.W)))) - val count = RegInit(0.U(countWidth.W)) - - val active = !io.flushValid - val enqueueFire = io.inValid && io.inReady - val candidateCount = count + Mux(enqueueFire, 1.U(countWidth.W), 0.U(countWidth.W)) - val hasOlder = active && candidateCount =/= 0.U - val hasYounger = active && candidateCount === 2.U - val older = Mux(count === 0.U, io.in, entries(0)) - val younger = Mux(count === 0.U, 0.U.asTypeOf(new RenamedUop(p)), Mux(count === 1.U, io.in, entries(1))) - val olderBank = Mux(count === 0.U, io.inBank, banks(0)) - val youngerBank = Mux(count === 1.U, io.inBank, banks(1)) - val olderSafe = ScalarPipeSafety.fixedScalarAlu(older) - val youngerSafe = ScalarPipeSafety.fixedScalarAlu(younger) - val dualEligible = - hasYounger && olderSafe && youngerSafe && (olderBank =/= youngerBank) - val dualFire = - dualEligible && io.drainCanConsume(olderBank) && io.drainCanConsume(youngerBank) - val olderOnlyFire = - hasOlder && !dualFire && io.drainCanConsume(olderBank) - - for (bank <- 0 until 2) { - val olderToBank = hasOlder && olderBank === bank.U - val youngerToBank = hasYounger && youngerBank === bank.U - io.drainPresent(bank) := - Mux(dualEligible, olderToBank || youngerToBank, olderToBank) - io.drainPreview(bank) := Mux( - dualEligible && youngerToBank, - younger, - Mux(olderToBank, older, 0.U.asTypeOf(new RenamedUop(p))) - ) - io.drainFire(bank) := Mux(dualFire, olderToBank || youngerToBank, olderOnlyFire && olderToBank) - } - - io.inReady := active && count < depth.U - io.empty := count === 0.U - io.full := count === depth.U - io.count := count - for (bank <- 0 until 2) { - io.bankOccupancy(bank) := PopCount((0 until depth).map { idx => - count > idx.U && banks(idx) === bank.U - }) - } - io.dualDrainEligible := dualEligible - io.dualDrainFire := dualFire - io.olderOnlyFire := olderOnlyFire - - when(io.flushValid) { - count := 0.U - entries := VecInit(Seq.fill(depth)(0.U.asTypeOf(new RenamedUop(p)))) - banks := VecInit(Seq.fill(depth)(0.U(1.W))) - }.otherwise { - val nextEntries = Wire(Vec(depth, new RenamedUop(p))) - val nextBanks = Wire(Vec(depth, UInt(1.W))) - val nextCount = Wire(UInt(countWidth.W)) - - nextEntries := entries - nextBanks := banks - nextCount := count - - when(count === 0.U) { - when(enqueueFire) { - when(olderOnlyFire) { - nextEntries(0) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := 0.U - nextCount := 0.U - }.otherwise { - nextEntries(0) := io.in - nextBanks(0) := io.inBank - nextCount := 1.U - } - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(1) := 0.U - } - }.elsewhen(count === 1.U) { - when(enqueueFire) { - when(dualFire) { - nextEntries(0) := 0.U.asTypeOf(new RenamedUop(p)) - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := 0.U - nextBanks(1) := 0.U - nextCount := 0.U - }.elsewhen(olderOnlyFire) { - nextEntries(0) := io.in - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := io.inBank - nextBanks(1) := 0.U - nextCount := 1.U - }.otherwise { - nextEntries(0) := entries(0) - nextEntries(1) := io.in - nextBanks(0) := banks(0) - nextBanks(1) := io.inBank - nextCount := 2.U - } - }.elsewhen(olderOnlyFire) { - nextEntries(0) := 0.U.asTypeOf(new RenamedUop(p)) - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := 0.U - nextBanks(1) := 0.U - nextCount := 0.U - } - }.otherwise { - when(dualFire) { - nextEntries(0) := 0.U.asTypeOf(new RenamedUop(p)) - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := 0.U - nextBanks(1) := 0.U - nextCount := 0.U - }.elsewhen(olderOnlyFire) { - nextEntries(0) := entries(1) - nextEntries(1) := 0.U.asTypeOf(new RenamedUop(p)) - nextBanks(0) := banks(1) - nextBanks(1) := 0.U - nextCount := 1.U - } - } - - entries := nextEntries - banks := nextBanks - count := nextCount - } -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarPipeSafety.scala b/chisel/src/main/scala/linxcore/execute/ScalarPipeSafety.scala deleted file mode 100644 index bbe2a3a7..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarPipeSafety.scala +++ /dev/null @@ -1,94 +0,0 @@ -package linxcore.execute - -import chisel3._ - -import linxcore.common.{DispatchTarget, RenamedUop, ScalarSpAccess} -import linxcore.frontend.FrontendOpcodeDecodeTable - -object ScalarPipeSafety { - private def opcode(value: Int, width: Int): UInt = - value.U(width.W) - - private def isFixedScalarAluOpcode(op: UInt): Bool = { - val width = op.getWidth - op === opcode(FrontendOpcodeDecodeTable.OP_ADD, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ADDIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUB, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SUBIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_AND, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ANDIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_OR, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_ORIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_XOR, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_XORIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLL, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SLLIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRL, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRLIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRA, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_SRAIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_LUI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LUI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIS, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_LIU, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ADDIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ANDIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_ORIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SUBIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_XORIW, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ADD, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ADDI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_AND, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_OR, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SUB, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVR, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SLLI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SRLI, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_B, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_H, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_W, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_B, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_H, width) || - op === opcode(FrontendOpcodeDecodeTable.OP_C_ZEXT_W, width) - } - - def fixedScalarAlu(uop: RenamedUop): Bool = { - val spAccess = ScalarSpAccess.classify(uop) - isFixedScalarAluOpcode(uop.opcode) && - (uop.dispatchTarget === DispatchTarget.Alu) && - !uop.isLoad && - !uop.isStore && - !uop.storeSplitIntent && - !uop.isLoadStorePair && - !uop.isStorePcr && - !uop.cacheMaintainNoSplit && - !uop.pairFirstDst.valid && - !spAccess.valid && - !uop.fretStkContextValid && - !uop.fretStkConditionValid && - !uop.fretStkFallbackTargetValid - } - -} diff --git a/chisel/src/main/scala/linxcore/execute/ScalarSpOrderOwner.scala b/chisel/src/main/scala/linxcore/execute/ScalarSpOrderOwner.scala deleted file mode 100644 index e6a97d2b..00000000 --- a/chisel/src/main/scala/linxcore/execute/ScalarSpOrderOwner.scala +++ /dev/null @@ -1,199 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.util.{Mux1H, PopCount, log2Ceil} - -import linxcore.commit.{CommitTraceParams, CommitTracePort} -import linxcore.common.{InterfaceParams, ScalarSpAccess, ScalarSpTransaction} -import linxcore.rob.ROBID - -class ScalarSpOrderOwnerIO( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams(), - val depth: Int = 64, - val stidCount: Int = 1) - extends Bundle { - private val stidIndexWidth = math.max(1, log2Ceil(stidCount)) - - val flushValid = Input(Bool()) - val initValid = Input(Bool()) - val initData = Input(UInt(p.immWidth.W)) - val recoveryRestoreValid = Input(Bool()) - val recoveryRestoreStid = Input(UInt(p.threadIdWidth.W)) - val recoveryRestoreData = Input(UInt(p.immWidth.W)) - - val reserveValid = Input(Bool()) - val reserve = Input(new ScalarSpTransaction(p)) - val reserveReady = Output(Bool()) - - val issueHeadValid = Output(Bool()) - val issueHeadValidByStid = Output(Vec(stidCount, Bool())) - val issueHeadBidByStid = Output(Vec(stidCount, new ROBID(p.robEntries))) - val issueHeadRidByStid = Output(Vec(stidCount, new ROBID(p.robEntries))) - val issueSnapshot = Output(UInt(p.immWidth.W)) - val issueSnapshotByStid = Output(Vec(stidCount, UInt(p.immWidth.W))) - - val terminalValid = Input(Bool()) - val terminal = Input(new ScalarSpTransaction(p)) - val terminalProducedValid = Input(Bool()) - val terminalProducedData = Input(UInt(p.immWidth.W)) - - val commit = Input(new CommitTracePort(traceParams)) - val commitValidMask = Input(UInt(traceParams.commitWidth.W)) - - val currentSp = Output(UInt(p.immWidth.W)) - val currentSpByStid = Output(Vec(stidCount, UInt(p.immWidth.W))) - val publishValid = Output(Bool()) - val publishData = Output(UInt(p.immWidth.W)) - val protocolError = Output(Bool()) -} - -class ScalarSpOrderOwner( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams(), - val depth: Int = 64, - val stidCount: Int = 1) - extends Module { - require(depth > 1, "scalar SP owner reservation depth must hold at least two transactions") - require(stidCount > 0, "scalar SP owner must expose at least one STID") - - private val countWidth = log2Ceil(depth + 1) - private val ptrWidth = log2Ceil(depth) - private val stidIndexWidth = math.max(1, log2Ceil(stidCount)) - - val io = IO(new ScalarSpOrderOwnerIO(p, traceParams, depth, stidCount)) - - private def stidIndex(stid: UInt): UInt = - if (stidCount == 1) 0.U(stidIndexWidth.W) else stid(stidIndexWidth - 1, 0) - - private def sameRobId(lhs: ROBID, rhs: ROBID): Bool = - ROBID.equal(lhs, rhs) - - private def sameTransaction(lhs: ScalarSpTransaction, rhs: ScalarSpTransaction): Bool = - lhs.access.valid && rhs.access.valid && - lhs.stid === rhs.stid && - lhs.epoch === rhs.epoch && - sameRobId(lhs.bid, rhs.bid) && - sameRobId(lhs.rid, rhs.rid) - - val committedSp = RegInit(VecInit(Seq.fill(stidCount)(0.U(p.immWidth.W)))) - val queue = RegInit(VecInit(Seq.fill(stidCount)(VecInit(Seq.fill(depth)(0.U.asTypeOf(new ScalarSpTransaction(p))))))) - val head = RegInit(VecInit(Seq.fill(stidCount)(0.U(ptrWidth.W)))) - val tail = RegInit(VecInit(Seq.fill(stidCount)(0.U(ptrWidth.W)))) - val count = RegInit(VecInit(Seq.fill(stidCount)(0.U(countWidth.W)))) - val completedValid = RegInit(VecInit(Seq.fill(stidCount)(false.B))) - val completedData = RegInit(VecInit(Seq.fill(stidCount)(0.U(p.immWidth.W)))) - - val reserveStid = stidIndex(io.reserve.stid) - val reserveReady = !io.reserve.access.valid || count(reserveStid) =/= depth.U - io.reserveReady := reserveReady - val reserveFire = io.reserveValid && io.reserve.access.valid && reserveReady - - val headTxn = Wire(Vec(stidCount, new ScalarSpTransaction(p))) - for (stid <- 0 until stidCount) { - headTxn(stid) := queue(stid)(head(stid)) - } - val anyHead = VecInit((0 until stidCount).map(stid => count(stid) =/= 0.U)).asUInt.orR - val firstHead = chisel3.util.PriorityEncoder(VecInit((0 until stidCount).map(stid => count(stid) =/= 0.U)).asUInt) - val headSelect = VecInit((0 until stidCount).map(stid => anyHead && firstHead === stid.U)) - io.issueHeadValid := anyHead - io.issueHeadValidByStid := VecInit((0 until stidCount).map(stid => count(stid) =/= 0.U)) - io.issueHeadBidByStid := VecInit(headTxn.map(_.bid)) - io.issueHeadRidByStid := VecInit(headTxn.map(_.rid)) - io.issueSnapshotByStid := committedSp - io.issueSnapshot := Mux1H(headSelect, committedSp) - io.currentSpByStid := committedSp - io.currentSp := committedSp(0) - - val terminalStid = stidIndex(io.terminal.stid) - val terminalHeadValid = count(terminalStid) =/= 0.U - val terminalMatchesHead = - io.terminalValid && terminalHeadValid && sameTransaction(io.terminal, headTxn(terminalStid)) - val terminalReadOnly = terminalMatchesHead && !headTxn(terminalStid).access.write - val terminalWriter = terminalMatchesHead && headTxn(terminalStid).access.write - val terminalProtocolError = - io.terminalValid && (!terminalMatchesHead || (terminalWriter && (!io.terminalProducedValid || completedValid(terminalStid)))) - - val commitMatches = Wire(Vec(stidCount, Bool())) - val commitBeforeComplete = Wire(Vec(stidCount, Bool())) - for (stid <- 0 until stidCount) { - val rowMatches = Wire(Vec(traceParams.commitWidth, Bool())) - for (slot <- 0 until traceParams.commitWidth) { - val row = io.commit.rows(slot) - rowMatches(slot) := - io.commitValidMask(slot) && - row.valid && - count(stid) =/= 0.U && - headTxn(stid).access.write && - row.rob.valid === headTxn(stid).rid.valid && - row.rob.wrap === headTxn(stid).rid.wrap && - row.rob.value(p.robIndexWidth - 1, 0) === headTxn(stid).rid.value && - row.identity.bid === headTxn(stid).bid.value && - row.identity.rid === headTxn(stid).rid.value - } - commitMatches(stid) := rowMatches.asUInt.orR && completedValid(stid) - commitBeforeComplete(stid) := rowMatches.asUInt.orR && !completedValid(stid) - } - val publishAny = commitMatches.asUInt.orR - io.publishValid := publishAny - io.publishData := Mux1H(commitMatches, completedData) - - val protocolErrorReg = RegInit(false.B) - io.protocolError := protocolErrorReg || terminalProtocolError || commitBeforeComplete.asUInt.orR - - when(io.flushValid || io.initValid) { - for (stid <- 0 until stidCount) { - head(stid) := 0.U - tail(stid) := 0.U - count(stid) := 0.U - completedValid(stid) := false.B - for (idx <- 0 until depth) { - queue(stid)(idx) := 0.U.asTypeOf(new ScalarSpTransaction(p)) - } - } - when(io.initValid) { - for (stid <- 0 until stidCount) { - committedSp(stid) := io.initData - } - }.elsewhen(io.recoveryRestoreValid) { - // A returning FRET.STK produces its architectural SP value one cycle - // before redirect recovery flushes younger reservations. Preserve that - // exact redirect-owner value while discarding the speculative queue. - committedSp(stidIndex(io.recoveryRestoreStid)) := io.recoveryRestoreData - } - protocolErrorReg := false.B - }.otherwise { - when(terminalProtocolError || commitBeforeComplete.asUInt.orR) { - protocolErrorReg := true.B - } - - for (stid <- 0 until stidCount) { - val doTerminalReadOnly = terminalReadOnly && terminalStid === stid.U - val doTerminalWriter = terminalWriter && terminalStid === stid.U - val doCommit = commitMatches(stid) - val doReserve = reserveFire && reserveStid === stid.U - val pop = doTerminalReadOnly || doCommit - val nextHead = head(stid) + pop.asUInt - val nextTail = tail(stid) + doReserve.asUInt - val nextCount = count(stid) + doReserve.asUInt - pop.asUInt - - when(doTerminalWriter) { - completedValid(stid) := true.B - completedData(stid) := io.terminalProducedData - } - when(doCommit) { - committedSp(stid) := completedData(stid) - completedValid(stid) := false.B - } - when(doReserve) { - queue(stid)(tail(stid)) := io.reserve - } - when(pop) { - queue(stid)(head(stid)) := 0.U.asTypeOf(new ScalarSpTransaction(p)) - } - head(stid) := nextHead - tail(stid) := nextTail - count(stid) := nextCount - } - } -} diff --git a/chisel/src/main/scala/linxcore/frontend/FrontendOpcodeDecodeTable.scala b/chisel/src/main/scala/linxcore/frontend/FrontendOpcodeDecodeTable.scala index 9cc6655c..b4d94e80 100644 --- a/chisel/src/main/scala/linxcore/frontend/FrontendOpcodeDecodeTable.scala +++ b/chisel/src/main/scala/linxcore/frontend/FrontendOpcodeDecodeTable.scala @@ -654,7 +654,6 @@ object FrontendOpcodeDecodeTable { val OP_FSQRT: Int = 624 val OP_IC_IALL: Int = 625 val OP_IC_IVA: Int = 626 - val OP_XB: Int = 627 val OP_J: Int = 628 val OP_JR: Int = 629 val OP_LR_B: Int = 630 @@ -740,7 +739,7 @@ object FrontendOpcodeDecodeTable { val ImmUIMM24: Int = 33 val ImmUIMM5: Int = 34 - val RuleCount: Int = 687 + val RuleCount: Int = 686 val Rules: Seq[Rule] = Seq( Rule(symbol = "OP_HL_QPUSH", opcode = 201, lenBytes = 6, mask = BigInt("fffff000707fffff", 16), value = BigInt("107d000e", 16), category = CatALU_INT, dispatch = 2, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), @@ -879,11 +878,11 @@ object FrontendOpcodeDecodeTable { Rule(symbol = "OP_B_ARG_NORM", opcode = 46, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("fa023", 16), category = CatBLOCK_ARGS_DESC, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_B_ARG_NZ2DN", opcode = 47, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("20fae23", 16), category = CatBLOCK_ARGS_DESC, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_BC_IALL", opcode = 588, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("10402b", 16), category = CatMISC, dispatch = 1, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = true, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_BSTART_FP_ICALL", opcode = 8, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("6101", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 6, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), - Rule(symbol = "OP_BSTART_FP_IND", opcode = 9, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("5101", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 5, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_BSTART_FP_ICALL", opcode = 8, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("6101", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 2, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_BSTART_FP_IND", opcode = 9, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("5101", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_BSTART_FP_RET", opcode = 10, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("7101", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 3, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), - Rule(symbol = "OP_BSTART_ICALL", opcode = 11, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("6001", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 6, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), - Rule(symbol = "OP_BSTART_IND", opcode = 12, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("5001", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 5, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_BSTART_ICALL", opcode = 11, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("6001", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 2, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_BSTART_IND", opcode = 12, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("5001", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_BSTART_RET", opcode = 15, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("7001", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 3, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_BSTOP", opcode = 591, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("1", 16), category = CatMISC, dispatch = 1, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = true), Rule(symbol = "OP_DC_IALL", opcode = 601, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("10602b", 16), category = CatMISC, dispatch = 1, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = true, isBlockBoundary = false, isBlockStop = false), @@ -1189,8 +1188,8 @@ object FrontendOpcodeDecodeTable { Rule(symbol = "OP_C_BSTART_STD_COND", opcode = 32, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("1800", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 1, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_STD_DIRECT", opcode = 33, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("1000", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 4, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_STD_FALL", opcode = 34, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("800", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), - Rule(symbol = "OP_C_BSTART_STD_ICALL", opcode = 35, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("3000", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 6, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), - Rule(symbol = "OP_C_BSTART_STD_IND", opcode = 36, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("2800", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 5, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_C_BSTART_STD_ICALL", opcode = 35, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("3000", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 2, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), + Rule(symbol = "OP_C_BSTART_STD_IND", opcode = 36, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("2800", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_STD_RET", opcode = 37, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("3800", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 3, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_SYS", opcode = 38, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("840", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_VPAR", opcode = 39, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("88c0", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), @@ -1249,7 +1248,6 @@ object FrontendOpcodeDecodeTable { Rule(symbol = "OP_SW", opcode = 407, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("2049", 16), category = CatSTORE, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = true, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_SW_U", opcode = 420, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("6049", 16), category = CatSTORE, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = true, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_UCVTF", opcode = 658, lenBytes = 4, mask = BigInt("1f0707f", 16), value = BigInt("706b", 16), category = CatMISC, dispatch = 1, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_XB", opcode = 627, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("6f81", 16), category = CatCMD_PIPE, dispatch = 5, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_LD_ADD", opcode = 353, lenBytes = 4, mask = BigInt("f000707f", 16), value = BigInt("400b", 16), category = CatLOAD, dispatch = 4, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = true, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_LD_AND", opcode = 354, lenBytes = 4, mask = BigInt("f000707f", 16), value = BigInt("1000400b", 16), category = CatLOAD, dispatch = 4, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = true, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_LD_OR", opcode = 355, lenBytes = 4, mask = BigInt("f000707f", 16), value = BigInt("2000400b", 16), category = CatLOAD, dispatch = 4, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = true, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), @@ -1418,16 +1416,16 @@ object FrontendOpcodeDecodeTable { Rule(symbol = "OP_C_ADDI", opcode = 565, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("c", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_AND", opcode = 566, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("28", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_B_DIMI", opcode = 568, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3c", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmIMM8, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_C_LDI", opcode = 570, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("1a", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_C_LWI", opcode = 571, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("a", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), + Rule(symbol = "OP_C_LDI", opcode = 570, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("1a", 16), category = CatLOAD, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = true, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), + Rule(symbol = "OP_C_LWI", opcode = 571, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("a", 16), category = CatLOAD, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = true, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_MOVI", opcode = 572, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("16", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandREG, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmSIMM5_6_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_MOVR", opcode = 573, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("6", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandREG, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_OR", opcode = 574, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("38", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_C_SDI", opcode = 575, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3a", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), + Rule(symbol = "OP_C_SDI", opcode = 575, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3a", 16), category = CatSTORE, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = true, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_SETC_EQ", opcode = 322, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("26", 16), category = CatBRU_SETC_CMP, dispatch = 3, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_SETC_NE", opcode = 323, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("36", 16), category = CatBRU_SETC_CMP, dispatch = 3, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_SUB", opcode = 582, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("18", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandREG, immKind = ImmNONE, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), - Rule(symbol = "OP_C_SWI", opcode = 583, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("2a", 16), category = CatCOMPRESSED, dispatch = 2, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), + Rule(symbol = "OP_C_SWI", opcode = 583, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("2a", 16), category = CatSTORE, dispatch = 4, boundary = 0, rdKind = OperandNONE, rs1Kind = OperandREG, rs2Kind = OperandNONE, immKind = ImmSIMM5_11_S5, isLoad = false, isStore = true, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = false, isBlockStop = false), Rule(symbol = "OP_C_BSTART_COND", opcode = 26, lenBytes = 2, mask = BigInt("f", 16), value = BigInt("4", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 1, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmSIMM12, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false), Rule(symbol = "OP_C_BSTART_DIRECT", opcode = 27, lenBytes = 2, mask = BigInt("f", 16), value = BigInt("2", 16), category = CatBLOCK_BOUNDARY, dispatch = 5, boundary = 4, rdKind = OperandNONE, rs1Kind = OperandNONE, rs2Kind = OperandNONE, immKind = ImmSIMM12, isLoad = false, isStore = false, isLoadStorePair = false, isStorePcr = false, cacheMaintainNoSplit = false, isBlockBoundary = true, isBlockStop = false) ) diff --git a/chisel/src/main/scala/linxcore/frontend/FrontendOperandDecode.scala b/chisel/src/main/scala/linxcore/frontend/FrontendOperandDecode.scala index c8ba333d..aeb79de3 100644 --- a/chisel/src/main/scala/linxcore/frontend/FrontendOperandDecode.scala +++ b/chisel/src/main/scala/linxcore/frontend/FrontendOperandDecode.scala @@ -114,6 +114,8 @@ class FrontendOperandDecode(val p: InterfaceParams = InterfaceParams()) extends val simm12Split = sext(Cat(insn32(11, 7), insn32(31, 25)), 12) val simm17Raw = sext(insn32(31, 15), 17) val simm17Off = fitImm(simm17Raw << 1) + val simm22Raw = sext(Cat(insn32(11, 7), insn32(31, 15)), 22) + val simm22Off = fitImm(simm22Raw << 1) val simm25 = sext(insn32(31, 7), 25) val simm25Off = fitImm(simm25 << 1) val simm5_11 = sext(insn16(15, 11), 5) @@ -363,6 +365,9 @@ class FrontendOperandDecode(val p: InterfaceParams = InterfaceParams()) extends setImm(simm17Off) } } + when(io.meta.immKind === FrontendOpcodeDecodeTable.ImmSIMM22.U) { + setImm(simm22Off) + } when(io.meta.immKind === FrontendOpcodeDecodeTable.ImmSIMM25.U) { when(opcodeIs( FrontendOpcodeDecodeTable.OP_BSTART_SPLIT_COND, @@ -375,9 +380,6 @@ class FrontendOperandDecode(val p: InterfaceParams = InterfaceParams()) extends when(io.meta.immKind === FrontendOpcodeDecodeTable.ImmSIMM5_11_S5.U) { setImm(simm5_11) } - when(opcodeIs(FrontendOpcodeDecodeTable.OP_C_LDI)) { - setImm(fitImm(simm5_11 << 3)) - } when(io.meta.immKind === FrontendOpcodeDecodeTable.ImmSIMM5_6_S5.U) { setImm(simm5_6) } diff --git a/chisel/src/main/scala/linxcore/frontend/ISideF0PcSelect.scala b/chisel/src/main/scala/linxcore/frontend/ISideF0PcSelect.scala index d713a749..ac28df54 100644 --- a/chisel/src/main/scala/linxcore/frontend/ISideF0PcSelect.scala +++ b/chisel/src/main/scala/linxcore/frontend/ISideF0PcSelect.scala @@ -108,12 +108,15 @@ class ISideF0PcSelect( Mux1H( (0 until threadCount).map(thread => (selectedThread === thread.U) -> predictionContextValid(thread))) - val selectedPredictionContext = - if (threadCount == 1) predictionContexts(0) - else - Mux1H( - (0 until threadCount).map(thread => - (selectedThread === thread.U) -> predictionContexts(thread))) + val selectedPredictionContext = Wire(new BranchPredictionRecord(p)) + selectedPredictionContext := predictionContexts(0) + if (threadCount > 1) { + for (thread <- 1 until threadCount) { + when(selectedThread === thread.U) { + selectedPredictionContext := predictionContexts(thread) + } + } + } val predictionQueue = Module(new Queue(new ISideFetchRequest(p, lineBytes), predictionQueueDepth, pipe = true, flow = false)) diff --git a/chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala b/chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala index 03403345..1ad90f9d 100644 --- a/chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala +++ b/chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala @@ -3,6 +3,7 @@ package linxcore.frontend import chisel3._ import chisel3.util.{Decoupled, Valid, log2Ceil} import linxcore.common.InterfaceParams +import linxcore.ifu.{BSide, IFURecovery} class LinxCoreIfuIO( val p: InterfaceParams = InterfaceParams(), @@ -66,7 +67,8 @@ class LinxCoreIfu( val missEntries: Int = 8, val joinEntries: Int = 8, val maxGroupsPerTransaction: Int = 8, - val instructionBufferDepth: Int = 16) + val instructionBufferDepth: Int = 16, + val externalFetchBuffer: Boolean = false) extends Module { require(p.fetchWidth == 4) require(p.decodeWidth == 4) @@ -94,13 +96,16 @@ class LinxCoreIfu( val lineContexts = Module(new ISideLineContextQueue(p, lineBytes, joinEntries)) val f3 = Module(new ISideF3LineAssembler(p, lineBytes)) val f4 = Module(new ISideF4Predecode(p, threadCount)) - val bSide = Module(new BSidePredictionPipeline(p, lineBytes, threadCount)) - val redirects = Module(new IfuRedirectArbiter(p, threadCount)) + val bSide = Module(new BSide(p, lineBytes, threadCount)) + val redirects = Module(new IFURecovery(p, threadCount)) val join = Module(new IfuPredictionJoin(p, lineBytes, joinEntries, maxGroupsPerTransaction)) val instructionBuffer = - Module(new InstructionBuffer(p, instructionBufferDepth, threadCount)) - val d1 = Module(new D1DecodeGroupGather(p)) + if (externalFetchBuffer) None + else Some(Module(new InstructionBuffer(p, instructionBufferDepth, threadCount))) + val d1Gather = + if (externalFetchBuffer) None + else Some(Module(new D1DecodeGroupGather(p))) val noFlush = 0.U.asTypeOf(new IfuInnerFlush(p)) val acceptedRedirect = Wire(new IfuInnerFlush(p)) @@ -165,8 +170,8 @@ class LinxCoreIfu( f4.io.flush := stateFlush bSide.io.prune := stateFlush join.io.flush := stateFlush - instructionBuffer.io.flush := stateFlush - d1.io.flush := stateFlush + instructionBuffer.foreach(_.io.flush := stateFlush) + d1Gather.foreach(_.io.flush := stateFlush) itlb.io.invalidate := io.invalidateItlb itlb.io.refill := io.ptwRefill @@ -468,10 +473,20 @@ class LinxCoreIfu( assert(!lineContexts.io.out.fire, "control prediction fence must hold younger lines before BF4") } - instructionBuffer.io.enq <> join.io.out - instructionBuffer.io.deqThreadId := io.d1ThreadId - d1.io.in <> instructionBuffer.io.deq - io.d1 <> d1.io.out + if (externalFetchBuffer) { + io.d1.valid := join.io.out.valid + io.d1.bits := 0.U.asTypeOf(io.d1.bits) + io.d1.bits.validMask := join.io.out.bits.validMask + io.d1.bits.entries := join.io.out.bits.entries + join.io.out.ready := io.d1.ready + } else { + val retained = instructionBuffer.get + val gather = d1Gather.get + retained.io.enq <> join.io.out + retained.io.deqThreadId := io.d1ThreadId + gather.io.in <> retained.io.deq + io.d1 <> gather.io.out + } // A start/restart is the same state-destroying event at every IFU seam as // an accepted inner redirect. Export the selected state flush so the D1 diff --git a/chisel/src/main/scala/linxcore/frontend/OooIfuBranchFeedbackBridge.scala b/chisel/src/main/scala/linxcore/frontend/OooIfuBranchFeedbackBridge.scala new file mode 100644 index 00000000..db22b568 --- /dev/null +++ b/chisel/src/main/scala/linxcore/frontend/OooIfuBranchFeedbackBridge.scala @@ -0,0 +1,90 @@ +package linxcore.frontend + +import chisel3._ +import chisel3.util.{Decoupled, Queue} +import linxcore.common.BoundaryKind +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class OooIfuBranchFeedbackBridgeIO(val p: CoreParams) extends Bundle { + val validation = Flipped(Decoupled(new BranchValidationTxn(p))) + val resolve = Decoupled(new BranchResolveTxn(p)) + val recovery = Decoupled(new RecoveryEvent(p)) +} + +/** Retains one exact BRU validation until B-SIDE training and any required + * precise recovery are accepted atomically. + */ +class OooIfuBranchFeedbackBridge( + val p: CoreParams, + val entries: Int = 2) extends Module { + require(entries > 0) + val io = IO(new OooIfuBranchFeedbackBridgeIO(p)) + + private val queue = Module(new Queue(new BranchValidationTxn(p), entries, + pipe = true, flow = false)) + queue.io.enq <> io.validation + private val event = queue.io.deq.bits + private val comparesTarget = + event.actualKind === BoundaryKind.Direct || + event.actualKind === BoundaryKind.Call || + event.actualKind === BoundaryKind.Ind || + event.actualKind === BoundaryKind.ICall || + event.actualKind === BoundaryKind.Ret + private val comparesFallthrough = event.actualKind === BoundaryKind.Fall + private val mispredict = + event.predictedTaken =/= event.actualTaken || + event.predictedKind =/= event.actualKind || + event.predictedBranchPc =/= event.actualBranchPc || + (comparesTarget && event.predictedTarget =/= event.actualTarget) || + (comparesFallthrough && + event.predictedFallthroughPc =/= event.actualFallthroughPc) + + io.resolve.bits := 0.U.asTypeOf(io.resolve.bits) + io.resolve.bits.peId := event.instruction.peId + io.resolve.bits.transactionId := event.predictionTransactionId + io.resolve.bits.predictionTag := event.predictionTag + io.resolve.bits.stid := event.instruction.stid + io.resolve.bits.fetchPacketUid := event.fetchPacketUid + io.resolve.bits.fetchSeq := event.fetchSeq + io.resolve.bits.epoch := event.predictionEpoch + io.resolve.bits.checkpointId := event.checkpointId + io.resolve.bits.requestPc := event.requestPc + io.resolve.bits.branchPc := event.actualBranchPc + io.resolve.bits.fallthroughPc := event.actualFallthroughPc + io.resolve.bits.taken := event.actualTaken + io.resolve.bits.target := event.actualTarget + io.resolve.bits.kind := event.actualKind + io.resolve.bits.mispredict := mispredict + + io.recovery.bits := 0.U.asTypeOf(io.recovery.bits) + io.recovery.bits.transactionId := event.executionTransactionId + io.recovery.bits.cause := RecoveryCause.Branch + io.recovery.bits.trigger := event.rob + io.recovery.bits.instruction := event.instruction + io.recovery.bits.redirectPc := Mux( + event.actualTaken, event.actualTarget, event.actualFallthroughPc) + + private val pairReady = io.resolve.ready && + (!mispredict || io.recovery.ready) + io.resolve.valid := queue.io.deq.valid && + (!mispredict || io.recovery.ready) + io.recovery.valid := queue.io.deq.valid && mispredict && io.resolve.ready + queue.io.deq.ready := pairReady + + when(queue.io.deq.valid) { + assert(event.predictionValid, + "backend branch validation requires a final prediction") + when(event.kind === BranchValidationKind.Condition) { + assert(event.actualKind === BoundaryKind.Cond, + "condition validation must resolve a conditional boundary") + }.otherwise { + assert(event.actualKind === BoundaryKind.Ind || + event.actualKind === BoundaryKind.ICall || + event.actualKind === BoundaryKind.Ret, + "target validation must resolve an indirect/call/return boundary") + assert(event.actualTaken, + "indirect/call/return target validation is unconditionally taken") + } + } +} diff --git a/chisel/src/main/scala/linxcore/iex/IEX.scala b/chisel/src/main/scala/linxcore/iex/IEX.scala new file mode 100644 index 00000000..07d6cc81 --- /dev/null +++ b/chisel/src/main/scala/linxcore/iex/IEX.scala @@ -0,0 +1,895 @@ +package linxcore.iex + +import chisel3._ +import chisel3.util.{DecoupledIO, Fill, Mux1H, MuxLookup, PriorityEncoderOH, + Queue, RRArbiter, UIntToOH, is, switch} +import linxcore.common.{BoundaryKind, DestinationKind, OperandClass} +import linxcore.frontend.OooIfuBranchFeedbackBridge +import linxcore.lsu.{LoadAttemptIdentity, LoadCanonicalRowIdentity} +import linxcore.ooo.{OooIexExecuteTransaction, OooIexExecutionPipeline, + OooIexIssuePolicy, OooIexWakeupKind, OooMemoryAddressMode, + OooMemoryIndexMode} +import linxcore.params.CoreParams +import linxcore.top.interface.{IEXIO, LoadReissueTxn, OperandKind, + BranchValidationKind, RecoveryEvent, TraceKind, TraceSource} + +/** Public state-free composition boundary for the canonical issue/execute graph. + * + * Architectural state remains in the retained private IQ, operand-file, + * execution, terminal, and load-metadata owners instantiated below. + */ +private final class OooIexBoundaryOwner(val p: CoreParams) extends Module { + val io = IO(new IEXIO(p)) + private val implementation = Module(new OooIexExecutionPipeline( + p, requireStoreReservation = true)) + + private val committedPTagCount = p.ooo.stidCount * p.ooo.gprArchRegs + private val bootstrapSeen = RegInit(0.U(committedPTagCount.W)) + private val bootstrapEpochValid = RegInit(VecInit(Seq.fill( + p.ooo.stidCount)(false.B))) + private val bootstrapEpoch = Reg(Vec(p.ooo.stidCount, + UInt(p.epochWidth.W))) + private val bootstrapDone = RegInit(false.B) + private val initStidInRange = io.pInit.bits.stid < p.ooo.stidCount.U + private val initAtagInRange = io.pInit.bits.atag < p.ooo.gprArchRegs.U + private val expectedPTag = io.pInit.bits.stid * p.ooo.gprArchRegs.U + + io.pInit.bits.atag + private val initPTagExact = initStidInRange && initAtagInRange && + io.pInit.bits.ptag === expectedPTag && io.pInit.bits.generation === 0.U + private val safeInitPTag = Mux(initPTagExact, expectedPTag, 0.U) + private val initPTagOH = UIntToOH(safeInitPTag, committedPTagCount) + private val initUnseen = !(bootstrapSeen & initPTagOH).orR + private val initEpochExact = if (p.ooo.stidCount == 1) { + !bootstrapEpochValid.head || bootstrapEpoch.head === io.pInit.bits.epoch + } else { + !bootstrapEpochValid(io.pInit.bits.stid) || + bootstrapEpoch(io.pInit.bits.stid) === io.pInit.bits.epoch + } + io.pInit.ready := !bootstrapDone && initPTagExact && initUnseen && + initEpochExact + implementation.io.pInit.valid := io.pInit.fire + implementation.io.pInit.bits := 0.U.asTypeOf(implementation.io.pInit.bits) + implementation.io.pInit.bits.key.stid := io.pInit.bits.stid + implementation.io.pInit.bits.key.epoch := io.pInit.bits.epoch + implementation.io.pInit.bits.key.ptag := io.pInit.bits.ptag + implementation.io.pInit.bits.key.generation := io.pInit.bits.generation + implementation.io.pInit.bits.data := io.pInit.bits.value + when(io.pInit.fire) { + bootstrapSeen := bootstrapSeen | initPTagOH + if (p.ooo.stidCount == 1) { + bootstrapEpochValid.head := true.B + bootstrapEpoch.head := io.pInit.bits.epoch + } else { + bootstrapEpochValid(io.pInit.bits.stid) := true.B + bootstrapEpoch(io.pInit.bits.stid) := io.pInit.bits.epoch + } + } + val completeMapSeen = bootstrapSeen.andR + when(io.bootstrapComplete && completeMapSeen) { bootstrapDone := true.B } + io.bootstrapReady := bootstrapDone + assert(!(io.bootstrapComplete && !completeMapSeen), + "IEX bootstrap cannot complete before every committed P map row is initialized") + assert(!(io.pInit.valid && !io.pInit.ready), + "IEX P initialization must be exact, unique, epoch-consistent, and boot-only") + + private def bootGated[T <: Data](source: DecoupledIO[T], + sink: DecoupledIO[T]): Unit = { + sink.valid := source.valid && bootstrapDone + sink.bits := source.bits + source.ready := sink.ready && bootstrapDone + } + for (lane <- io.ooo.aluDispatch.indices) { + bootGated(io.ooo.aluDispatch(lane), + implementation.io.dispatch.aluDispatch(lane)) + } + for (lane <- io.ooo.bruDispatch.indices) { + bootGated(io.ooo.bruDispatch(lane), + implementation.io.dispatch.bruDispatch(lane)) + } + for (lane <- io.ooo.aguDispatch.indices) { + bootGated(io.ooo.aguDispatch(lane), + implementation.io.dispatch.aguDispatch(lane)) + } + for (lane <- io.ooo.storeDispatch.indices) { + bootGated(io.ooo.storeDispatch(lane), + implementation.io.dispatch.storeDispatch(lane)) + } + for (lane <- io.ooo.systemDispatch.indices) { + bootGated(io.ooo.systemDispatch(lane), + implementation.io.dispatch.systemDispatch(lane)) + } + for (lane <- io.ooo.cmdDispatch.indices) { + bootGated(io.ooo.cmdDispatch(lane), + implementation.io.dispatch.cmdDispatch(lane)) + } + implementation.io.recovery <> io.ooo.recovery + implementation.io.issuePolicy := 0.U.asTypeOf(new OooIexIssuePolicy( + implementation.p)) + + require(io.ooo.allocationClear.length == implementation.io.pClear.length) + for (port <- io.ooo.allocationClear.indices) { + val clear = io.ooo.allocationClear(port) + val destination = clear.bits.destination + + implementation.io.pClear(port).valid := clear.valid && + destination.kind === OperandKind.Gpr && destination.ptagValid + implementation.io.pClear(port).bits.stid := clear.bits.rob.stid + implementation.io.pClear(port).bits.epoch := clear.bits.epoch + implementation.io.pClear(port).bits.ptag := destination.ptag + implementation.io.pClear(port).bits.generation := destination.pGeneration + + implementation.io.tClear(port).valid := clear.valid && + destination.kind === OperandKind.T && destination.ttagValid + implementation.io.tClear(port).bits.stid := clear.bits.rob.stid + implementation.io.tClear(port).bits.epoch := clear.bits.epoch + implementation.io.tClear(port).bits.tag := destination.ttag + implementation.io.tClear(port).bits.sequence.valid := true.B + implementation.io.tClear(port).bits.sequence.index := + destination.tSeqIndex + implementation.io.tClear(port).bits.sequence.generation := + destination.tSeqGeneration + + implementation.io.uClear(port).valid := clear.valid && + destination.kind === OperandKind.U && destination.utagValid + implementation.io.uClear(port).bits.stid := clear.bits.rob.stid + implementation.io.uClear(port).bits.epoch := clear.bits.epoch + implementation.io.uClear(port).bits.tag := destination.utag + implementation.io.uClear(port).bits.sequence.valid := true.B + implementation.io.uClear(port).bits.sequence.index := + destination.uSeqIndex + implementation.io.uClear(port).bits.sequence.generation := + destination.uSeqGeneration + } + assert(!io.ooo.allocationClear.map(_.valid).reduce(_ || _) || bootstrapDone, + "rename allocation clears are the only post-bootstrap P ownership changes") + private def projectMember( + target: linxcore.ooo.RobMemberKey, + source: linxcore.top.interface.RobIdentity): Unit = { + target.group.valid := true.B + target.group.peId := source.peId + target.group.stid := source.stid + target.group.ridSlot := source.ridSlot + target.group.ridGeneration := source.ridGeneration + target.bid.valid := true.B + target.bid.value := source.bid + target.brobGeneration := source.brobGeneration + target.memberIndex := source.memberIndex + target.residentGeneration := source.residentGeneration + } + implementation.io.fastWriteback.valid := io.ooo.fastResult.valid + implementation.io.fastWriteback.bits := + 0.U.asTypeOf(implementation.io.fastWriteback.bits) + projectMember(implementation.io.fastWriteback.bits.member, + io.ooo.fastResult.bits.writeback.rob) + implementation.io.fastWriteback.bits.stid := + io.ooo.fastResult.bits.writeback.rob.stid + implementation.io.fastWriteback.bits.epoch := + io.ooo.fastResult.bits.writeback.epoch + implementation.io.fastWriteback.bits.ptag := + io.ooo.fastResult.bits.writeback.destination.ptag + implementation.io.fastWriteback.bits.ptagGeneration := + io.ooo.fastResult.bits.writeback.destination.pGeneration + implementation.io.fastWriteback.bits.data := + io.ooo.fastResult.bits.writeback.value + + implementation.io.fastWakeup.valid := io.ooo.fastResult.valid + implementation.io.fastWakeup.bits := + 0.U.asTypeOf(implementation.io.fastWakeup.bits) + implementation.io.fastWakeup.bits.kind := OooIexWakeupKind.Committed + implementation.io.fastWakeup.bits.stid := + io.ooo.fastResult.bits.writeback.rob.stid + implementation.io.fastWakeup.bits.epoch := + io.ooo.fastResult.bits.writeback.epoch + implementation.io.fastWakeup.bits.operandClass := OperandClass.P + implementation.io.fastWakeup.bits.ptag := + io.ooo.fastResult.bits.writeback.destination.ptag + implementation.io.fastWakeup.bits.ptagGeneration := + io.ooo.fastResult.bits.writeback.destination.pGeneration + io.ooo.fastResult.ready := implementation.io.fastWriteback.ready && + implementation.io.fastWakeup.ready + implementation.io.stageCancels.foreach(_.foreach { cancel => + cancel.valid := false.B + cancel.bits := 0.U.asTypeOf(cancel.bits) + }) + + for (port <- io.ooo.pcBufferReadAddress.indices) { + io.ooo.pcBufferReadAddress(port) := + implementation.io.pcReadRequests(port).bits + io.ooo.pcBufferReadAddress(port).valid := + implementation.io.pcReadRequests(port).valid + implementation.io.pcReadResponses(port) := + io.ooo.pcBufferReadPcBase(port) + } + + io.ooo.robNoflushReady <> implementation.io.robNoflushReady + implementation.io.robNoflush <> io.ooo.robNoflush + for (port <- io.ooo.systemIssue.indices) { + io.ooo.systemIssue(port) <> implementation.io.systemIssue(port) + } + + for (port <- io.ooo.robResolve.indices) { + io.ooo.robResolve(port).valid := false.B + io.ooo.robResolve(port).bits := 0.U.asTypeOf(io.ooo.robResolve(port).bits) + } + private val resolveTransport = Seq.fill(implementation.io.robResolve.length)( + Module(new Queue(chiselTypeOf(implementation.io.robResolve.head.bits), 1, + pipe = false, flow = false))) + for (port <- implementation.io.robResolve.indices) { + resolveTransport(port).io.enq <> implementation.io.robResolve(port) + io.ooo.robResolve(port) <> resolveTransport(port).io.deq + } + val systemResolvePort = implementation.io.robResolve.length + if (systemResolvePort < io.ooo.robResolve.length) { + io.ooo.robResolve(systemResolvePort) <> + implementation.io.systemCmdResolve + } else { + implementation.io.systemCmdResolve.ready := false.B + } + + private val bctrlArbiter = Module(new RRArbiter( + chiselTypeOf(implementation.io.bctrl.head.bits), + implementation.io.bctrl.length)) + private val bctrlTransport = Seq.fill(implementation.io.bctrl.length)( + Module(new Queue(chiselTypeOf(implementation.io.bctrl.head.bits), 1, + pipe = false, flow = false))) + for (lane <- implementation.io.bctrl.indices) { + bctrlTransport(lane).io.enq <> implementation.io.bctrl(lane) + bctrlArbiter.io.in(lane) <> bctrlTransport(lane).io.deq + } + private val branchFeedback = Module(new OooIfuBranchFeedbackBridge(p)) + private val bctrl = bctrlArbiter.io.out.bits + private val prediction = bctrl.prediction + private val conditionUpdate = + bctrl.update.kind === linxcore.ooo.OooIexBctrlUpdateKind.Condition + private val targetKind = Mux( + prediction.kind === BoundaryKind.Ind || + prediction.kind === BoundaryKind.ICall || + prediction.kind === BoundaryKind.Ret, + prediction.kind, + BoundaryKind.Ind) + branchFeedback.io.validation.valid := bctrlArbiter.io.out.valid + bctrlArbiter.io.out.ready := branchFeedback.io.validation.ready + branchFeedback.io.validation.bits := + 0.U.asTypeOf(branchFeedback.io.validation.bits) + branchFeedback.io.validation.bits.executionTransactionId := + bctrl.transactionId + branchFeedback.io.validation.bits.rob.peId := bctrl.member.group.peId + branchFeedback.io.validation.bits.rob.stid := bctrl.member.group.stid + branchFeedback.io.validation.bits.rob.ridSlot := bctrl.member.group.ridSlot + branchFeedback.io.validation.bits.rob.ridGeneration := + bctrl.member.group.ridGeneration + branchFeedback.io.validation.bits.rob.memberIndex := + bctrl.member.memberIndex + branchFeedback.io.validation.bits.rob.residentGeneration := + bctrl.member.residentGeneration + branchFeedback.io.validation.bits.rob.bid := bctrl.member.bid.value + branchFeedback.io.validation.bits.rob.brobGeneration := + bctrl.member.brobGeneration + branchFeedback.io.validation.bits.instruction.peId := + bctrl.uopKey.primaryParent.peId + branchFeedback.io.validation.bits.instruction.stid := + bctrl.uopKey.primaryParent.stid + branchFeedback.io.validation.bits.instruction.instructionId := + bctrl.uopKey.primaryParent.instructionId + branchFeedback.io.validation.bits.instruction.epoch := + bctrl.uopKey.primaryParent.epoch + branchFeedback.io.validation.bits.kind := Mux( + conditionUpdate, BranchValidationKind.Condition, + BranchValidationKind.Target) + branchFeedback.io.validation.bits.predictionValid := prediction.valid + branchFeedback.io.validation.bits.predictionTag := prediction.predictionTag + branchFeedback.io.validation.bits.predictionTransactionId := + prediction.transactionId + branchFeedback.io.validation.bits.fetchPacketUid := prediction.fetchPacketUid + branchFeedback.io.validation.bits.fetchSeq := prediction.fetchSeq + branchFeedback.io.validation.bits.predictionEpoch := prediction.epoch + branchFeedback.io.validation.bits.checkpointId := prediction.checkpointId + branchFeedback.io.validation.bits.requestPc := prediction.requestPc + branchFeedback.io.validation.bits.predictedTaken := prediction.taken + branchFeedback.io.validation.bits.predictedBranchPc := prediction.branchPc + branchFeedback.io.validation.bits.predictedTarget := prediction.target + branchFeedback.io.validation.bits.predictedFallthroughPc := + prediction.fallthroughPc + branchFeedback.io.validation.bits.predictedKind := prediction.kind + branchFeedback.io.validation.bits.actualTaken := Mux( + conditionUpdate, bctrl.update.condition, bctrl.update.targetValid) + branchFeedback.io.validation.bits.actualBranchPc := prediction.branchPc + branchFeedback.io.validation.bits.actualTarget := Mux( + conditionUpdate, prediction.target, bctrl.update.target) + branchFeedback.io.validation.bits.actualFallthroughPc := + prediction.fallthroughPc + branchFeedback.io.validation.bits.actualKind := Mux( + conditionUpdate, BoundaryKind.Cond, targetKind) + io.branchResolve <> branchFeedback.io.resolve + + private val recoveryArbiter = Module(new RRArbiter( + new RecoveryEvent(p), implementation.io.recoveryEvent.length + 1)) + for (lane <- implementation.io.recoveryEvent.indices) { + recoveryArbiter.io.in(lane) <> implementation.io.recoveryEvent(lane) + } + recoveryArbiter.io.in(implementation.io.recoveryEvent.length) <> + branchFeedback.io.recovery + io.ooo.recoveryEvent <> recoveryArbiter.io.out + + io.cmdIssue <> implementation.io.cmdIssue + private val terminalTraceSources = + implementation.io.trace.toSeq :+ implementation.io.systemCmdTrace + private val traceArbiter = Module(new RRArbiter( + chiselTypeOf(implementation.io.trace.head.bits), + terminalTraceSources.length)) + private val traceTransport = Seq.fill(terminalTraceSources.length)( + Module(new Queue(chiselTypeOf(implementation.io.trace.head.bits), 1, + pipe = false, flow = false))) + private val terminalAcceptedSources = + implementation.io.architecturalAccepted.toSeq + private val pwritePending = RegInit(VecInit( + Seq.fill(terminalAcceptedSources.length)(false.B))) + private val pwriteRows = Reg(Vec(terminalAcceptedSources.length, + chiselTypeOf(io.terminalPWrite.bits))) + private val incomingPwrite = Wire(Vec( + terminalAcceptedSources.length, Bool())) + private val incomingPwriteRows = Wire(Vec(terminalAcceptedSources.length, + chiselTypeOf(io.terminalPWrite.bits))) + for (lane <- terminalTraceSources.indices) { + val source = terminalTraceSources(lane) + traceTransport(lane).io.enq.valid := source.valid + traceTransport(lane).io.enq.bits := source.bits + source.ready := true.B + traceArbiter.io.in(lane) <> traceTransport(lane).io.deq + } + io.trace.valid := traceArbiter.io.out.valid + traceArbiter.io.out.ready := io.trace.ready + io.trace.bits := 0.U.asTypeOf(io.trace.bits) + io.trace.bits.count := 1.U + private val terminalTrace = traceArbiter.io.out.bits + private val terminalTraceEntry = io.trace.bits.entries.head + private val gprWriteMask = VecInit(terminalTrace.writebacks.map(writeback => + writeback.valid && writeback.destination.kind === DestinationKind.Gpr)) + terminalTraceEntry.source := TraceSource.Iex + terminalTraceEntry.kind := Mux(terminalTrace.trapValid, TraceKind.Trap, + Mux(gprWriteMask.asUInt.orR, TraceKind.Commit, TraceKind.Pipeline)) + terminalTraceEntry.instructionValid := + terminalTrace.uopKey.primaryParent.valid + terminalTraceEntry.instruction.peId := + terminalTrace.uopKey.primaryParent.peId + terminalTraceEntry.instruction.stid := + terminalTrace.uopKey.primaryParent.stid + terminalTraceEntry.instruction.instructionId := + terminalTrace.uopKey.primaryParent.instructionId + terminalTraceEntry.instruction.epoch := + terminalTrace.uopKey.primaryParent.epoch + terminalTraceEntry.robValid := terminalTrace.member.group.valid && + terminalTrace.member.bid.valid + terminalTraceEntry.rob.peId := terminalTrace.member.group.peId + terminalTraceEntry.rob.stid := terminalTrace.member.group.stid + terminalTraceEntry.rob.ridSlot := terminalTrace.member.group.ridSlot + terminalTraceEntry.rob.ridGeneration := + terminalTrace.member.group.ridGeneration + terminalTraceEntry.rob.memberIndex := terminalTrace.member.memberIndex + terminalTraceEntry.rob.residentGeneration := + terminalTrace.member.residentGeneration + terminalTraceEntry.rob.bid := terminalTrace.member.bid.value + terminalTraceEntry.rob.brobGeneration := terminalTrace.member.brobGeneration + terminalTraceEntry.opcode := terminalTrace.opcode + terminalTraceEntry.payload := Mux(gprWriteMask.asUInt.orR, + Mux1H(gprWriteMask, terminalTrace.writebacks.map(_.data)), 0.U) + for (lane <- terminalAcceptedSources.indices) { + val accepted = terminalAcceptedSources(lane) + val incomingGprMask = VecInit(accepted.bits.writebacks.map(writeback => + writeback.valid && writeback.destination.kind === DestinationKind.Gpr)) + incomingPwrite(lane) := accepted.valid && incomingGprMask.asUInt.orR + incomingPwriteRows(lane) := 0.U.asTypeOf(incomingPwriteRows(lane)) + incomingPwriteRows(lane).rob.peId := accepted.bits.member.group.peId + incomingPwriteRows(lane).rob.stid := accepted.bits.member.group.stid + incomingPwriteRows(lane).rob.ridSlot := accepted.bits.member.group.ridSlot + incomingPwriteRows(lane).rob.ridGeneration := + accepted.bits.member.group.ridGeneration + incomingPwriteRows(lane).rob.memberIndex := accepted.bits.member.memberIndex + incomingPwriteRows(lane).rob.residentGeneration := + accepted.bits.member.residentGeneration + incomingPwriteRows(lane).rob.bid := accepted.bits.member.bid.value + incomingPwriteRows(lane).rob.brobGeneration := + accepted.bits.member.brobGeneration + incomingPwriteRows(lane).ptag := Mux1H(incomingGprMask, + accepted.bits.writebacks.map(_.destination.ptag)) + incomingPwriteRows(lane).generation := Mux1H(incomingGprMask, + accepted.bits.writebacks.map(_.destination.ptagGeneration)) + incomingPwriteRows(lane).value := Mux1H(incomingGprMask, + accepted.bits.writebacks.map(_.data)) + } + private val replaceablePwrite = pwritePending.asUInt & incomingPwrite.asUInt + private val pwriteGrant = Mux(replaceablePwrite.orR, + PriorityEncoderOH(replaceablePwrite), + PriorityEncoderOH(pwritePending.asUInt)) + io.terminalPWrite.valid := pwritePending.asUInt.orR + io.terminalPWrite.bits := Mux1H(pwriteGrant, pwriteRows) + for (lane <- terminalAcceptedSources.indices) { + val observationOverflow = incomingPwrite(lane) && pwritePending(lane) && + !pwriteGrant(lane) + assert(!observationOverflow, + "terminal PWrite observation must never silently overflow") + when(incomingPwrite(lane)) { + pwritePending(lane) := true.B + pwriteRows(lane) := incomingPwriteRows(lane) + }.elsewhen(pwriteGrant(lane)) { + pwritePending(lane) := false.B + } + } + + // Reservation is the same acceptance dependency used by the retained IQ + // owner; it cannot fire separately from the logical STA/STD pair. + private val reservations = implementation.io.storeReserve.get + for (lane <- reservations.indices) { + val reservation = reservations(lane) + val publicReservation = io.lsu.storeReservation(lane) + val binding = io.ooo.storeBinding(lane) + publicReservation.valid := reservation.valid && binding.ready + binding.valid := reservation.valid && publicReservation.ready + reservation.ready := publicReservation.ready && binding.ready + publicReservation.bits := 0.U.asTypeOf(publicReservation.bits) + publicReservation.bits.transactionId := reservation.bits.transactionId + publicReservation.bits.transaction.value := + reservation.bits.memoryTransaction.value + publicReservation.bits.transaction.generation := + reservation.bits.memoryTransaction.generation + publicReservation.bits.rob.peId := reservation.bits.member.group.peId + publicReservation.bits.rob.stid := reservation.bits.member.group.stid + publicReservation.bits.rob.ridSlot := reservation.bits.member.group.ridSlot + publicReservation.bits.rob.ridGeneration := + reservation.bits.member.group.ridGeneration + publicReservation.bits.rob.memberIndex := + reservation.bits.member.memberIndex + publicReservation.bits.rob.residentGeneration := + reservation.bits.member.residentGeneration + publicReservation.bits.rob.bid := reservation.bits.member.bid.value + publicReservation.bits.rob.brobGeneration := + reservation.bits.member.brobGeneration + publicReservation.bits.memoryOrder.requestCount := + reservation.bits.memoryOrder.requestCount + publicReservation.bits.memoryOrder.firstLsid := + reservation.bits.memoryOrder.firstLsid + publicReservation.bits.memoryOrder.firstLid := + reservation.bits.memoryOrder.before.loadId + publicReservation.bits.memoryOrder.firstSid := + reservation.bits.memoryOrder.before.storeId + publicReservation.bits.memoryOrder.yostValid := + reservation.bits.memoryOrder.before.youngestStoreLsidValid + publicReservation.bits.memoryOrder.yostLsid := + reservation.bits.memoryOrder.before.youngestStoreLsid + publicReservation.bits.memoryOrder.yostSid := + reservation.bits.memoryOrder.yostSid + publicReservation.bits.memoryOrder.yoldValid := + reservation.bits.memoryOrder.yoldValid + publicReservation.bits.memoryOrder.yoldLsid := + reservation.bits.memoryOrder.yoldLsid + publicReservation.bits.memoryOrder.yoldLid := + reservation.bits.memoryOrder.yoldLid + publicReservation.bits.requestCount := + reservation.bits.memoryOrder.requestCount + publicReservation.bits.pair := + reservation.bits.memoryOrder.requestCount === 2.U + publicReservation.bits.sizeBytes := reservation.bits.memory.accessBytes + publicReservation.bits.aguPipe := lane.U + publicReservation.bits.stdPipe := lane.U + binding.bits.rob := publicReservation.bits.rob + binding.bits.transaction := publicReservation.bits.transaction + binding.bits.memoryOrder := publicReservation.bits.memoryOrder + when(reservation.valid) { + assert(reservation.fire === publicReservation.fire && + reservation.fire === binding.fire, + "store reservation and exact ROB transaction binding require one fire") + } + } + + private def projectRob(target: linxcore.top.interface.RobIdentity, + execute: OooIexExecuteTransaction): Unit = { + val member = execute.i2.row.member + target.peId := member.group.peId + target.stid := member.group.stid + target.ridSlot := member.group.ridSlot + target.ridGeneration := member.group.ridGeneration + target.memberIndex := member.memberIndex + target.residentGeneration := member.residentGeneration + target.bid := member.bid.value + target.brobGeneration := member.brobGeneration + } + + private def projectMemoryIdentity( + target: linxcore.top.interface.MemoryIdentity, + execute: OooIexExecuteTransaction, pipe: Int): Unit = { + val row = execute.i2.row + target := 0.U.asTypeOf(target) + projectRob(target.rob, execute) + target.transaction.value := row.memoryTransaction.value + target.transaction.generation := row.memoryTransaction.generation + target.lsid := row.memoryOrder.firstLsid + target.attemptGeneration := row.initialLoadAttemptGeneration + target.pipeId := pipe.U + } + + private def projectMemoryOrder( + target: linxcore.top.interface.MemoryOrderMeta, + execute: OooIexExecuteTransaction): Unit = { + val order = execute.i2.row.memoryOrder + target := 0.U.asTypeOf(target) + target.requestCount := order.requestCount + target.firstLsid := order.firstLsid + target.firstSid := order.firstTypeId + target.yostValid := order.before.youngestStoreLsidValid + target.yostLsid := order.before.youngestStoreLsid + target.yostSid := order.before.storeId - 1.U + } + + private def maskedValue(mask: UInt, values: Vec[UInt], second: Bool): UInt = { + val first = PriorityEncoderOH(mask) + Mux1H(Mux(second, PriorityEncoderOH(mask & ~first), first), values) + } + + private def transformedIndex(execute: OooIexExecuteTransaction, + raw: UInt): UInt = { + val memory = execute.i2.row.memory + val transformed = WireDefault(raw) + switch(memory.indexMode) { + is(OooMemoryIndexMode.SignExtend32) { + transformed := Fill(p.pcWidth - 32, raw(31)) ## raw(31, 0) + } + is(OooMemoryIndexMode.ZeroExtend32) { + transformed := raw(31, 0).pad(p.pcWidth) + } + is(OooMemoryIndexMode.Negate) { + transformed := 0.U(p.pcWidth.W) - raw + } + } + (transformed << memory.indexShift)(p.pcWidth - 1, 0) + } + + private def storeBaseAddress(execute: OooIexExecuteTransaction): UInt = { + val memory = execute.i2.row.memory + val base = maskedValue(memory.addressSourceMask, + execute.i2.sourceData, false.B) + val index = maskedValue(memory.addressSourceMask, + execute.i2.sourceData, true.B) + MuxLookup(memory.addressMode.asUInt, 0.U)(Seq( + OooMemoryAddressMode.BaseIndex.asUInt -> + (base + transformedIndex(execute, index)), + OooMemoryAddressMode.BaseOffset.asUInt -> (base + memory.offset), + OooMemoryAddressMode.PcOffset.asUInt -> + (execute.i2.pc + memory.offset))) + } + + // Publish semantic store halves. Pair expansion and physical lease lookup + // remain exclusively inside LSU. + io.lsu.loadAddress.foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + val privateLoad = implementation.io.load.liqAlloc + val publicLoadBits = Wire(chiselTypeOf(io.lsu.loadAddress.head.bits)) + publicLoadBits := 0.U.asTypeOf(publicLoadBits) + publicLoadBits.identity.rob.peId := privateLoad.bits.attempt.producer.peId + publicLoadBits.identity.rob.stid := privateLoad.bits.attempt.producer.stid + publicLoadBits.identity.rob.ridSlot := + privateLoad.bits.attempt.producer.ridSlot + publicLoadBits.identity.rob.ridGeneration := + privateLoad.bits.attempt.producer.ridGeneration + publicLoadBits.identity.rob.memberIndex := + privateLoad.bits.attempt.producer.memberIndex + publicLoadBits.identity.rob.residentGeneration := + privateLoad.bits.attempt.producer.residentGeneration + publicLoadBits.identity.rob.bid := privateLoad.bits.attempt.producer.nativeBid + publicLoadBits.identity.rob.brobGeneration := + privateLoad.bits.attempt.producer.brobGeneration + publicLoadBits.identity.lsid := privateLoad.bits.loadLsIdFull + publicLoadBits.identity.transaction.value := privateLoad.bits.attempt.transactionValue + publicLoadBits.identity.transaction.generation := + privateLoad.bits.attempt.transactionGeneration + publicLoadBits.identity.attemptGeneration := privateLoad.bits.attempt.generation + publicLoadBits.identity.pipeId := privateLoad.bits.returnPipeIndex + publicLoadBits.pc := privateLoad.bits.pc + publicLoadBits.address := privateLoad.bits.addr + publicLoadBits.sizeBytes := privateLoad.bits.size + publicLoadBits.signed := privateLoad.bits.returnSignExtend + publicLoadBits.destination.valid := privateLoad.bits.dst.valid + publicLoadBits.destination.kind := Mux( + privateLoad.bits.dst.kind === DestinationKind.Gpr, + OperandKind.Gpr, + Mux(privateLoad.bits.dst.kind === DestinationKind.T, + OperandKind.T, OperandKind.U)) + publicLoadBits.destination.atag := privateLoad.bits.dst.archTag + publicLoadBits.destination.ptag := Mux( + privateLoad.bits.dst.kind === DestinationKind.Gpr, + privateLoad.bits.dst.physTag, 0.U) + publicLoadBits.destination.previousPtag := Mux( + privateLoad.bits.dst.kind === DestinationKind.Gpr, + privateLoad.bits.dst.oldPhysTag, 0.U) + publicLoadBits.destination.previousPtagValid := privateLoad.bits.dst.valid && + privateLoad.bits.dst.kind === DestinationKind.Gpr + publicLoadBits.destination.ptagValid := privateLoad.bits.dst.valid && + privateLoad.bits.dst.kind === DestinationKind.Gpr + publicLoadBits.destination.ttag := Mux( + privateLoad.bits.dst.kind === DestinationKind.T, + privateLoad.bits.dst.physTag, 0.U) + publicLoadBits.destination.ttagValid := privateLoad.bits.dst.valid && + privateLoad.bits.dst.kind === DestinationKind.T + publicLoadBits.destination.utag := Mux( + privateLoad.bits.dst.kind === DestinationKind.U, + privateLoad.bits.dst.physTag, 0.U) + publicLoadBits.destination.utagValid := privateLoad.bits.dst.valid && + privateLoad.bits.dst.kind === DestinationKind.U + publicLoadBits.destinationRelativeIndex := privateLoad.bits.dst.relTag + publicLoadBits.youngestStoreValid := + privateLoad.bits.youngestStoreLsIdFullValid + publicLoadBits.youngestStoreLsid := privateLoad.bits.youngestStoreLsIdFull + publicLoadBits.youngestStoreId := privateLoad.bits.youngestStoreId.value + for (lane <- io.lsu.loadAddress.indices) { + val publicLoad = io.lsu.loadAddress(lane) + publicLoad.valid := privateLoad.valid && + privateLoad.bits.returnPipeIndex === lane.U + publicLoad.bits := publicLoadBits + } + privateLoad.ready := Mux1H( + UIntToOH(privateLoad.bits.returnPipeIndex, p.lsu.loadPipes), + io.lsu.loadAddress.map(_.ready)) + + // LSU's allocation ID is a combinational preview beside alloc-ready. It is + // meaningful before the request is asserted, which lets metadata validate + // the prospective row without making request-valid depend on the returned + // Valid marker and forming an IEX/LSU combinational cycle. + val selectedLoadAllocation = Mux1H( + UIntToOH(privateLoad.bits.returnPipeIndex, p.lsu.loadPipes), + io.lsu.loadAllocation.map(_.bits)) + implementation.io.load.liqAllocLoadId.valid := true.B + implementation.io.load.liqAllocLoadId.value := + selectedLoadAllocation.allocationId.value + implementation.io.load.liqAllocLoadId.wrap := + selectedLoadAllocation.allocationId.generation(0) + + val loadLaunchValid = VecInit(io.lsu.loadLaunch.map(_.valid)) + val selectedLoadLaunch = Mux1H(loadLaunchValid, + io.lsu.loadLaunch.map(_.bits)) + implementation.io.load.attemptLaunch.valid := loadLaunchValid.asUInt.orR + implementation.io.load.attemptLaunch.bits := 0.U.asTypeOf( + implementation.io.load.attemptLaunch.bits) + implementation.io.load.attemptLaunch.bits.loadId.valid := + loadLaunchValid.asUInt.orR + implementation.io.load.attemptLaunch.bits.loadId.slot := + selectedLoadLaunch.allocationId.value + implementation.io.load.attemptLaunch.bits.loadId.generation := + selectedLoadLaunch.allocationId.generation + implementation.io.load.attemptLaunch.bits.attempt.valid := true.B + implementation.io.load.attemptLaunch.bits.attempt.producer.valid := true.B + implementation.io.load.attemptLaunch.bits.attempt.producer.peId := + selectedLoadLaunch.identity.rob.peId + implementation.io.load.attemptLaunch.bits.attempt.producer.stid := + selectedLoadLaunch.identity.rob.stid + implementation.io.load.attemptLaunch.bits.attempt.producer.nativeBidValid := true.B + implementation.io.load.attemptLaunch.bits.attempt.producer.nativeBid := + selectedLoadLaunch.identity.rob.bid + implementation.io.load.attemptLaunch.bits.attempt.producer.brobGeneration := + selectedLoadLaunch.identity.rob.brobGeneration + implementation.io.load.attemptLaunch.bits.attempt.producer.ridSlot := + selectedLoadLaunch.identity.rob.ridSlot + implementation.io.load.attemptLaunch.bits.attempt.producer.ridGeneration := + selectedLoadLaunch.identity.rob.ridGeneration + implementation.io.load.attemptLaunch.bits.attempt.producer.memberIndex := + selectedLoadLaunch.identity.rob.memberIndex + implementation.io.load.attemptLaunch.bits.attempt.producer.residentGeneration := + selectedLoadLaunch.identity.rob.residentGeneration + implementation.io.load.attemptLaunch.bits.attempt.transactionValue := + selectedLoadLaunch.identity.transaction.value + implementation.io.load.attemptLaunch.bits.attempt.transactionGeneration := + selectedLoadLaunch.identity.transaction.generation + implementation.io.load.attemptLaunch.bits.attempt.generation := + selectedLoadLaunch.identity.attemptGeneration + for (lane <- io.lsu.storeAddress.indices) { + val privateAddress = implementation.io.storeAddress(lane) + val publicAddress = io.lsu.storeAddress(lane) + publicAddress.valid := privateAddress.valid + privateAddress.ready := publicAddress.ready + publicAddress.bits := 0.U.asTypeOf(publicAddress.bits) + projectMemoryIdentity(publicAddress.bits.identity, + privateAddress.bits, lane) + projectMemoryOrder(publicAddress.bits.memoryOrder, privateAddress.bits) + publicAddress.bits.requestCount := + privateAddress.bits.i2.row.memoryOrder.requestCount + publicAddress.bits.pair := publicAddress.bits.requestCount === 2.U + publicAddress.bits.address := storeBaseAddress(privateAddress.bits) + publicAddress.bits.sizeBytes := + privateAddress.bits.i2.row.memory.accessBytes + } + for (lane <- io.lsu.storeData.indices) { + val privateData = implementation.io.storeData(lane) + val publicData = io.lsu.storeData(lane) + publicData.valid := privateData.valid + privateData.ready := publicData.ready + publicData.bits := 0.U.asTypeOf(publicData.bits) + projectMemoryIdentity(publicData.bits.identity, privateData.bits, lane) + projectMemoryOrder(publicData.bits.memoryOrder, privateData.bits) + publicData.bits.requestCount := privateData.bits.i2.row.memoryOrder.requestCount + publicData.bits.pair := publicData.bits.requestCount === 2.U + publicData.bits.sizeBytes := privateData.bits.i2.row.memory.accessBytes + for (beat <- 0 until p.maxMemoryRequestsPerInstruction) { + publicData.bits.data(beat) := maskedValue( + privateData.bits.i2.row.memory.dataSourceMask, + privateData.bits.i2.sourceData, beat.U === 1.U) + val bytes = privateData.bits.i2.row.memory.accessBytes + publicData.bits.byteMask(beat) := + ((1.U << bytes) - 1.U)(p.dataWidth / 8 - 1, 0) + } + } + val loadReturnArbiter = Module(new RRArbiter( + chiselTypeOf(io.lsu.loadResult.head.bits), p.lsu.loadPipes)) + for (lane <- io.lsu.loadResult.indices) { + loadReturnArbiter.io.in(lane) <> io.lsu.loadResult(lane) + } + implementation.io.load.completion.valid := loadReturnArbiter.io.out.valid + loadReturnArbiter.io.out.ready := implementation.io.load.completion.ready + implementation.io.load.completion.bits := 0.U.asTypeOf( + implementation.io.load.completion.bits) + val returned = loadReturnArbiter.io.out.bits + implementation.io.load.completion.bits.peId := returned.identity.rob.peId + implementation.io.load.completion.bits.stid := returned.identity.rob.stid + implementation.io.load.completion.bits.tid := returned.identity.rob.stid + implementation.io.load.completion.bits.payload.valid := true.B + implementation.io.load.completion.bits.payload.loadId.valid := true.B + implementation.io.load.completion.bits.payload.loadId.slot := + returned.allocationId.value + implementation.io.load.completion.bits.payload.loadId.generation := + returned.allocationId.generation + implementation.io.load.completion.bits.payload.attempt.valid := true.B + implementation.io.load.completion.bits.payload.attempt.producer.valid := true.B + implementation.io.load.completion.bits.payload.attempt.producer.peId := + returned.identity.rob.peId + implementation.io.load.completion.bits.payload.attempt.producer.stid := + returned.identity.rob.stid + implementation.io.load.completion.bits.payload.attempt.producer.nativeBidValid := true.B + implementation.io.load.completion.bits.payload.attempt.producer.nativeBid := + returned.identity.rob.bid + implementation.io.load.completion.bits.payload.attempt.producer.brobGeneration := + returned.identity.rob.brobGeneration + implementation.io.load.completion.bits.payload.attempt.producer.ridSlot := + returned.identity.rob.ridSlot + implementation.io.load.completion.bits.payload.attempt.producer.ridGeneration := + returned.identity.rob.ridGeneration + implementation.io.load.completion.bits.payload.attempt.producer.memberIndex := + returned.identity.rob.memberIndex + implementation.io.load.completion.bits.payload.attempt.producer.residentGeneration := + returned.identity.rob.residentGeneration + implementation.io.load.completion.bits.payload.attempt.transactionValue := + returned.identity.transaction.value + implementation.io.load.completion.bits.payload.attempt.transactionGeneration := + returned.identity.transaction.generation + implementation.io.load.completion.bits.payload.attempt.generation := + returned.identity.attemptGeneration + implementation.io.load.completion.bits.payload.transactionValid := true.B + implementation.io.load.completion.bits.payload.transactionValue := + returned.identity.transaction.value + implementation.io.load.completion.bits.payload.transactionGeneration := + returned.identity.transaction.generation + implementation.io.load.completion.bits.payload.pipeIndex := + returned.identity.pipeId + implementation.io.load.completion.bits.payload.dst.valid := + returned.destination.valid + implementation.io.load.completion.bits.payload.dst.kind := Mux( + returned.destination.kind === OperandKind.Gpr, + DestinationKind.Gpr, + Mux(returned.destination.kind === OperandKind.T, + DestinationKind.T, DestinationKind.U)) + implementation.io.load.completion.bits.payload.dst.archTag := + returned.destination.atag + implementation.io.load.completion.bits.payload.dst.relTag := + returned.destinationRelativeIndex + implementation.io.load.completion.bits.payload.dst.physTag := Mux( + returned.destination.kind === OperandKind.Gpr, + returned.destination.ptag, + Mux(returned.destination.kind === OperandKind.T, + returned.destination.ttag, returned.destination.utag)) + implementation.io.load.completion.bits.payload.dst.oldPhysTag := Mux( + returned.destination.kind === OperandKind.Gpr, + returned.destination.previousPtag, + 0.U) + implementation.io.load.completion.bits.payload.data := returned.data + implementation.io.load.completion.bits.payload.faultValid := returned.trap.valid + implementation.io.load.completion.bits.payload.faultCause := returned.trap.cause + private def projectAttempt(target: LoadAttemptIdentity, + source: linxcore.top.interface.MemoryIdentity): Unit = { + target := 0.U.asTypeOf(target) + target.valid := true.B + target.producer.valid := true.B + target.producer.peId := source.rob.peId + target.producer.stid := source.rob.stid + target.producer.nativeBidValid := true.B + target.producer.nativeBid := source.rob.bid + target.producer.brobGeneration := source.rob.brobGeneration + target.producer.ridSlot := source.rob.ridSlot + target.producer.ridGeneration := source.rob.ridGeneration + target.producer.memberIndex := source.rob.memberIndex + target.producer.residentGeneration := source.rob.residentGeneration + target.transactionValue := source.transaction.value + target.transactionGeneration := source.transaction.generation + target.generation := source.attemptGeneration + } + private def projectLoad(target: linxcore.ooo.OooIexLoadGeneration, + source: linxcore.top.interface.MemoryIdentity): Unit = { + target := 0.U.asTypeOf(target) + target.valid := true.B + projectMember(target.producer, source.rob) + target.transaction.value := source.transaction.value + target.transaction.generation := source.transaction.generation + target.generation := source.attemptGeneration + } + io.lsu.loadRebindApply.foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + val reissueArbiter = Module(new RRArbiter( + new LoadReissueTxn(p), p.lsu.loadPipes * 2)) + for (lane <- 0 until p.lsu.loadPipes) { + reissueArbiter.io.in(lane) <> io.lsu.loadReissue(lane) + val repick = io.lsu.loadRepick(lane) + val repickTransition = reissueArbiter.io.in(p.lsu.loadPipes + lane) + repickTransition.valid := repick.valid + repickTransition.bits := 0.U.asTypeOf(repickTransition.bits) + repickTransition.bits.allocationId := repick.bits.allocationId + repickTransition.bits.currentIdentity := repick.bits.currentIdentity + repickTransition.bits.nextIdentity := repick.bits.nextIdentity + repickTransition.bits.structural := repick.bits.structural + repickTransition.bits.waitStore := repick.bits.waitStore + repick.ready := repickTransition.ready + } + val publicReissue = reissueArbiter.io.out + val selectedRebindLane = Mux( + reissueArbiter.io.chosen < p.lsu.loadPipes.U, + reissueArbiter.io.chosen, + reissueArbiter.io.chosen - p.lsu.loadPipes.U) + val selectedRebindReady = Mux1H( + UIntToOH(selectedRebindLane, p.lsu.loadPipes), + io.lsu.loadRebindApply.map(_.ready)) + implementation.io.load.rebind.valid := publicReissue.valid + publicReissue.ready := implementation.io.load.rebind.ready && + selectedRebindReady + implementation.io.load.rebind.bits := 0.U.asTypeOf( + implementation.io.load.rebind.bits) + implementation.io.load.rebind.bits.loadId.valid := true.B + implementation.io.load.rebind.bits.loadId.slot := + publicReissue.bits.allocationId.value + implementation.io.load.rebind.bits.loadId.generation := + publicReissue.bits.allocationId.generation + projectAttempt(implementation.io.load.rebind.bits.currentAttempt, + publicReissue.bits.currentIdentity) + projectAttempt(implementation.io.load.rebind.bits.nextAttempt, + publicReissue.bits.nextIdentity) + projectLoad(implementation.io.load.rebind.bits.currentLoad, + publicReissue.bits.currentIdentity) + projectLoad(implementation.io.load.rebind.bits.nextLoad, + publicReissue.bits.nextIdentity) + for (lane <- 0 until p.lsu.loadPipes) { + val publicRebind = io.lsu.loadRebindApply(lane) + publicRebind.valid := implementation.io.load.liqRebind.valid && + selectedRebindLane === lane.U + publicRebind.bits := publicReissue.bits + } + implementation.io.load.liqRebind.ready := selectedRebindReady + val publicRebindFire = VecInit(io.lsu.loadRebindApply.map(_.fire)).asUInt.orR + when(publicReissue.fire || implementation.io.load.rebind.fire || + implementation.io.load.liqRebind.fire || publicRebindFire) { + assert(publicReissue.fire && implementation.io.load.rebind.fire && + implementation.io.load.liqRebind.fire && publicRebindFire, + "load lifecycle transition must atomically rebind metadata and LIQ") + } + io.lsu.loadCancel.foreach(_.ready := true.B) + io.lsu.recoveryEvent.ready := true.B + + implementation.io.multiCycleAlu.foreach(_.ready := false.B) + implementation.io.pointerAuth.foreach(_.ready := false.B) + implementation.io.floatingVector.ready := false.B +} + +/** Stable public IEX box. All retained state and arbitration live below this + * wiring-only shell in the private canonical boundary owner. + */ +class IEX(val p: CoreParams) extends Module { + val io = IO(new IEXIO(p)) + private val owner = Module(new OooIexBoundaryOwner(p)) + io <> owner.io +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexLoadLiqAllocAdapter.scala b/chisel/src/main/scala/linxcore/iex/LoadIexIssuePipeline.scala similarity index 63% rename from chisel/src/main/scala/linxcore/ooo/OooIexLoadLiqAllocAdapter.scala rename to chisel/src/main/scala/linxcore/iex/LoadIexIssuePipeline.scala index 95889e0b..38f5f664 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexLoadLiqAllocAdapter.scala +++ b/chisel/src/main/scala/linxcore/iex/LoadIexIssuePipeline.scala @@ -1,13 +1,17 @@ -package linxcore.ooo +package linxcore.iex import chisel3._ import chisel3.util.{Decoupled, RRArbiter, Valid, log2Ceil} import linxcore.common.{CoreParams, DestinationKind} import linxcore.lsu.{LoadAttemptIdentity, LoadInflightAlloc} +import linxcore.ooo._ +import linxcore.params.{CoreParams => MainlineCoreParams} import linxcore.rob.ROBID +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan, + RecoveryPlanContract, RecoveryTargetIO} -class OooIexLoadLiqAllocReject(val p: OooParams = OooParams()) +class LoadIexIssueReject(val p: OooParams = OooParams()) extends Bundle { val member = new RobMemberKey(p) val identityExact = Bool() @@ -16,7 +20,6 @@ class OooIexLoadLiqAllocReject(val p: OooParams = OooParams()) val destinationExact = Bool() val pcExact = Bool() val killed = Bool() - val flushed = Bool() } /** Exact OOO identity returned beside one accepted canonical LIQ allocation. @@ -25,18 +28,19 @@ class OooIexLoadLiqAllocReject(val p: OooParams = OooParams()) * allocation response. This sideband only reports the OOO lane and attempt * which participated in that same ready/valid fire. */ -class OooIexLoadLiqAllocAccepted( +class LoadIexIssueAccepted( val p: OooParams = OooParams(), - val laneCount: Int = 3) extends Bundle { + val laneCount: Int = 2) extends Bundle { val lane = UInt(math.max(1, log2Ceil(laneCount)).W) val load = new OooIexLoadGeneration(p) val request = new OooIexAguLoadRequest(p) } -class OooIexLoadLiqAllocAdapterIO( +class LoadIexIssuePipelineIO( val p: OooParams, val coreParams: CoreParams, - val laneCount: Int) extends Bundle { + val laneCount: Int, + val recoveryParams: MainlineCoreParams) extends Bundle { private val lsu = coreParams.scalarLsu val agu = Flipped(Vec(laneCount, @@ -55,33 +59,40 @@ class OooIexLoadLiqAllocAdapterIO( lsu.loadReturnPipeCount, coreParams.lsidWidth)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val flush = Input(Bool()) - val accepted = Valid(new OooIexLoadLiqAllocAccepted(p, laneCount)) + val recovery = Flipped(new RecoveryTargetIO(recoveryParams)) + val accepted = Valid(new LoadIexIssueAccepted(p, laneCount)) val rejected = Output(Vec(laneCount, - Valid(new OooIexLoadLiqAllocReject(p)))) + Valid(new LoadIexIssueReject(p)))) } -/** Three-AGU to one-canonical-LIQ allocation bridge. +/** Multi-AGU load issue pipeline into the canonical LIQ allocation port. * - * The bridge is deliberately non-resident: AGU lanes retain their requests + * The pipeline is deliberately non-resident: AGU lanes retain their requests * under backpressure and the canonical LIQ becomes the sole load-lifecycle - * owner on `alloc.fire`. A global accepted-allocation serial creates - * producer-qualified attempt generations; the counter is never reset by - * recovery, so a stale return cannot alias a later request after a flush. + * owner on `alloc.fire`. The Dispatch-to-IQ owner has already allocated and + * retained the memory transaction and initial producer-qualified load + * attempt. This bridge copies them exactly into LIQ; later replay generations + * are allocated only by LSU through the exact rebind contract. */ -class OooIexLoadLiqAllocAdapter( +class LoadIexIssuePipeline( val p: OooParams = OooParams(), val coreParams: CoreParams = CoreParams( - scalarLsu = linxcore.common.ScalarLsuParams(loadReturnPipeCount = 3)), - val laneCount: Int = 3) extends Module { + scalarLsu = linxcore.common.ScalarLsuParams(loadReturnPipeCount = 2)), + val laneCount: Int = 2, + val recoveryParams: MainlineCoreParams) extends Module { + def this(p: OooParams, coreParams: CoreParams) = + this(p, coreParams, coreParams.scalarLsu.loadReturnPipeCount, + OooRecoveryMembership.coreParams(p)) + + def this(p: OooParams, coreParams: CoreParams, laneCount: Int) = + this(p, coreParams, laneCount, OooRecoveryMembership.coreParams(p)) private val lsu = coreParams.scalarLsu - require(laneCount == 3, - "the Linx scalar execution profile has exactly three load-address lanes") + require(laneCount > 0, + "the Linx scalar execution profile needs at least one load-address lane") require(lsu.loadReturnPipeCount >= laneCount, "each physical load lane needs a canonical LSU return-pipe identity") - require(p.robGroupsPerStid <= coreParams.robEntries, + require(p.robIdentityGroupsPerStid <= coreParams.robEntries, "OOO RID slots must fit the canonical LSU ROB projection") require(p.nativeBidWidth <= log2Ceil(coreParams.robEntries) + 1, "native BID must fit the canonical LSU value-plus-wrap projection") @@ -101,21 +112,59 @@ class OooIexLoadLiqAllocAdapter( p.robMemberIndexWidth, p.residentGenerationWidth, p.loadGenerationWidth) + OooRecoveryMembership.requireCompatible(p, recoveryParams) + + val io = IO(new LoadIexIssuePipelineIO( + p, coreParams, laneCount, recoveryParams)) + + private val recoveryPending = RegInit(false.B) + private val preparedValid = RegInit(false.B) + private val recoveryPlan = Reg(new RecoveryPlan(recoveryParams)) - val io = IO(new OooIexLoadLiqAllocAdapterIO(p, coreParams, laneCount)) + private val prepareExact = + io.recovery.prepare.bits.phase === RecoveryPhase.Prepare && + RecoveryPlanContract.legalSuffixWindow(io.recovery.prepare.bits) && + io.recovery.prepare.bits.trigger.stid < p.stidCount.U + io.recovery.prepare.ready := !recoveryPending && prepareExact + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan - // Allocation is currently one-wide, so one global serial avoids making the - // attempt generation depend on which physical AGU happened to win. Replay - // generations advance later through the exact LIQ rebind contract. - private val generation = RegInit(0.U(p.loadGenerationWidth.W)) + private val terminalConflict = + io.recovery.apply.valid && io.recovery.abort.valid + private val sameApply = recoveryPending && !terminalConflict && + io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, recoveryPlan) + private val sameAbort = recoveryPending && !terminalConflict && + io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, recoveryPlan) - private def killed(member: RobMemberKey): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, member) + when(io.recovery.prepare.fire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(sameApply || sameAbort) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + when(io.recovery.apply.valid) { + assert(sameApply, + "load issue Apply must match the exact prepared recovery plan") + } + when(io.recovery.abort.valid) { + assert(sameAbort, + "load issue Abort must match the exact prepared recovery plan") + } private def identityExact(request: OooIexAguLoadRequest): Bool = { val row = request.execute.i2.row row.valid && row.member.group.valid && row.member.bid.valid && + row.memoryTransactionValid && row.stid < p.stidCount.U && row.member.group.peId === row.peId && row.member.group.stid === row.stid } @@ -134,6 +183,7 @@ class OooIexLoadLiqAllocAdapter( row.recipe.dispatchClass === OooDispatchClass.Agu.U && row.recipe.sideEffectOwner === OooSideEffectOwner.Lsu.U && row.recipe.memoryRequestCount === 1.U && row.memory.valid && + row.initialLoadAttemptValid && row.memory.isLoad && !row.memory.isStore && bytesExact } @@ -153,12 +203,15 @@ class OooIexLoadLiqAllocAdapter( private def destinationExact(request: OooIexAguLoadRequest): Bool = { val destination = request.destination val previous = request.execute.i2.row.payload.previousPDestinations(0) - destination.valid && destination.kind === DestinationKind.Gpr && + val pExact = destination.kind === DestinationKind.Gpr && destination.ptag < p.pPhysRegs.U && previous.valid && previous.ptag < p.pPhysRegs.U && - previous.ptag =/= destination.ptag && - destination.asUInt === - request.execute.i2.row.destinations(0).asUInt + previous.ptag =/= destination.ptag + val tExact = destination.kind === DestinationKind.T && + destination.localTag < p.tPhysRegs.U && + destination.localSequence.valid && !previous.valid + destination.valid && (pExact || tExact) && destination.asUInt === + request.execute.i2.row.destinations(0).asUInt } val exact = Wire(Vec(laneCount, Bool())) @@ -172,21 +225,31 @@ class OooIexLoadLiqAllocAdapter( val order = memoryOrderExact(request) val destination = destinationExact(request) val pc = request.pcValid - killedLane(lane) := killed(request.execute.i2.row.member) + val requestStid = request.execute.i2.row.member.group.stid + val preparingTarget = io.recovery.prepare.valid && prepareExact && + io.recovery.prepare.bits.trigger.stid === requestStid + val pendingTarget = recoveryPending && + recoveryPlan.trigger.stid === requestStid + killedLane(lane) := sameApply && + OooRecoveryMembership.memberKilled( + p, recoveryParams, recoveryPlan, request.execute.i2.row.member) exact(lane) := identity && shape && order && destination && pc - val drop = killedLane(lane) || io.flush - arbiter.io.in(lane).valid := io.agu(lane).valid && exact(lane) && !drop + val drop = killedLane(lane) + val fenced = preparingTarget || pendingTarget + arbiter.io.in(lane).valid := + io.agu(lane).valid && exact(lane) && !drop && !fenced arbiter.io.in(lane).bits := request // Recovery is a destructive cancellation handshake at this non-resident // boundary. Draining the visible producer request while allocation is // masked prevents the same pre-recovery request from allocating after the // recovery pulse disappears. Malformed non-killed requests remain held // for fail-closed diagnostics. - io.agu(lane).ready := drop || (arbiter.io.in(lane).ready && exact(lane)) + io.agu(lane).ready := drop || + (!fenced && arbiter.io.in(lane).ready && exact(lane)) io.rejected(lane).valid := io.agu(lane).valid && - (!exact(lane) || killedLane(lane) || io.flush) + (!exact(lane) || killedLane(lane)) io.rejected(lane).bits.member := request.execute.i2.row.member io.rejected(lane).bits.identityExact := identity io.rejected(lane).bits.loadShapeExact := shape @@ -194,7 +257,6 @@ class OooIexLoadLiqAllocAdapter( io.rejected(lane).bits.destinationExact := destination io.rejected(lane).bits.pcExact := pc io.rejected(lane).bits.killed := killedLane(lane) - io.rejected(lane).bits.flushed := io.flush } val selectedLane = arbiter.io.chosen @@ -202,7 +264,7 @@ class OooIexLoadLiqAllocAdapter( val row = request.execute.i2.row val member = row.member val order = row.memoryOrder - val attemptGeneration = generation + 1.U + val attemptGeneration = row.initialLoadAttemptGeneration val hasOlderStore = order.before.youngestStoreLsidValid val youngestStoreIdFull = order.before.storeId - 1.U val youngestStoreLsidFull = order.before.youngestStoreLsid @@ -216,7 +278,7 @@ class OooIexLoadLiqAllocAdapter( private def projectBid(target: ROBID): Unit = { val valueWidth = log2Ceil(target.entries) target.valid := member.bid.valid - target.value := member.bid.value(valueWidth - 1, 0) + target.value := member.bid.value.pad(valueWidth)(valueWidth - 1, 0) target.wrap := (if (p.nativeBidWidth > valueWidth) member.bid.value(valueWidth) else member.brobGeneration(0)) } @@ -247,6 +309,8 @@ class OooIexLoadLiqAllocAdapter( alloc.attempt.producer.ridGeneration := member.group.ridGeneration alloc.attempt.producer.memberIndex := member.memberIndex alloc.attempt.producer.residentGeneration := member.residentGeneration + alloc.attempt.transactionValue := row.memoryTransaction.value + alloc.attempt.transactionGeneration := row.memoryTransaction.generation alloc.attempt.generation := attemptGeneration alloc.peId := row.peId alloc.stid := row.stid @@ -259,8 +323,14 @@ class OooIexLoadLiqAllocAdapter( alloc.dst.kind := request.destination.kind alloc.dst.archTag := request.destination.atag alloc.dst.relTag := request.destination.relativeIndex - alloc.dst.physTag := request.destination.ptag - alloc.dst.oldPhysTag := row.payload.previousPDestinations(0).ptag + alloc.dst.physTag := Mux( + request.destination.kind === DestinationKind.Gpr, + request.destination.ptag, + request.destination.localTag) + alloc.dst.oldPhysTag := Mux( + request.destination.kind === DestinationKind.Gpr, + row.payload.previousPDestinations(0).ptag, + 0.U) alloc.sourceTraceValid := false.B alloc.source0 := 0.U.asTypeOf(alloc.source0) alloc.source1 := 0.U.asTypeOf(alloc.source1) @@ -281,13 +351,17 @@ class OooIexLoadLiqAllocAdapter( arbiter.io.out.ready := io.alloc.ready io.accepted.valid := io.alloc.fire io.accepted.bits.lane := selectedLane - io.accepted.bits.load.valid := io.alloc.fire + // Candidate bits remain well formed before ready so a downstream atomic + // composition can include its own readiness without a combinational + // `fire -> valid -> ready` cycle. `accepted.valid` still denotes the only + // architecturally accepted allocation event. + io.accepted.bits.load.valid := arbiter.io.out.valid io.accepted.bits.load.producer := member + io.accepted.bits.load.transaction := row.memoryTransaction io.accepted.bits.load.generation := attemptGeneration io.accepted.bits.request := request when(io.alloc.fire) { - generation := attemptGeneration assert(LoadAttemptIdentity.wellFormed(io.alloc.bits.attempt), "OOO-to-LIQ allocation must carry one well-formed exact attempt") } diff --git a/chisel/src/main/scala/linxcore/iex/OooIexLoadTerminalMetadata.scala b/chisel/src/main/scala/linxcore/iex/OooIexLoadTerminalMetadata.scala new file mode 100644 index 00000000..b77f11d4 --- /dev/null +++ b/chisel/src/main/scala/linxcore/iex/OooIexLoadTerminalMetadata.scala @@ -0,0 +1,601 @@ +package linxcore.iex + +import chisel3._ +import chisel3.util.{Decoupled, PopCount, Valid, log2Ceil} + +import linxcore.common.{CoreParams, DestinationKind, OperandClass} +import linxcore.lsu.{LoadAttemptIdentity, LoadCanonicalRowIdentity, + LoadReplayDestination, LoadTerminalFault, ScalarLSULoadReturnEntry} +import linxcore.ooo._ +import linxcore.params.{CoreParams => MainlineCoreParams} +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan, + RecoveryPlanContract} + +/** Metadata installed atomically beside one canonical LIQ allocation. + * + * Address, miss, replay, data, and request residency remain solely in the + * scalar LSU. This sidecar retains only the typed OOO execution context that + * the architectural terminal sink must revalidate after the LIQ row has + * transferred into LRET/W1/W2. + */ +class OooIexLoadTerminalMetadataAlloc( + val p: OooParams, + val coreParams: CoreParams, + val laneCount: Int = 2) extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val attempt = new LoadAttemptIdentity + val load = new OooIexLoadGeneration(p) + val request = new OooIexAguLoadRequest(p) + val lane = UInt(math.max(1, log2Ceil(laneCount)).W) +} + +/** Exact canonical launch event after one LIQ attempt enters execution. */ +class OooIexLoadAttemptLaunch extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val attempt = new LoadAttemptIdentity +} + +/** Exact replay-generation update for one still-live terminal sidecar. */ +class OooIexLoadTerminalMetadataRebind( + val p: OooParams, + val coreParams: CoreParams) extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val currentAttempt = new LoadAttemptIdentity + val nextAttempt = new LoadAttemptIdentity + val currentLoad = new OooIexLoadGeneration(p) + val nextLoad = new OooIexLoadGeneration(p) +} + +class OooIexLoadTerminalMetadataReject( + val p: OooParams, + val coreParams: CoreParams) extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val member = new RobMemberKey(p) + val rowIdExact = Bool() + val resident = Bool() + val producerExact = Bool() + val attemptExact = Bool() + val transactionExact = Bool() + val pipeExact = Bool() + val destinationExact = Bool() + val outcomeExact = Bool() +} + +class OooIexLoadTerminalMetadataEntry( + val p: OooParams, + val coreParams: CoreParams, + val laneCount: Int = 2) extends Bundle { + val valid = Bool() + val loadId = new LoadCanonicalRowIdentity + val attempt = new LoadAttemptIdentity + val load = new OooIexLoadGeneration(p) + val request = new OooIexAguLoadRequest(p) + val lane = UInt(math.max(1, log2Ceil(laneCount)).W) + val faultCancelSent = Bool() +} + +class OooIexLoadTerminalMetadataIO( + val p: OooParams, + val coreParams: CoreParams, + val laneCount: Int = 2, + val recoveryParams: MainlineCoreParams) extends Bundle { + private val lsu = coreParams.scalarLsu + private def completionType = new ScalarLSULoadReturnEntry( + coreParams.robEntries, + lsu.addrWidth, + lsu.pcWidth, + lsu.dataWidth, + lsu.loadSizeWidth, + lsu.loadReturnPipeCount, + lsu.archRegWidth, + lsu.physRegWidth, + lsu.peIdWidth, + lsu.stidWidth, + lsu.tidWidth, + coreParams.lsidWidth) + + val alloc = Flipped(Decoupled( + new OooIexLoadTerminalMetadataAlloc(p, coreParams, laneCount))) + val rebind = Flipped(Decoupled( + new OooIexLoadTerminalMetadataRebind(p, coreParams))) + val attemptLaunch = Flipped(Valid( + new OooIexLoadAttemptLaunch)) + val completion = Flipped(Decoupled(completionType)) + val result = Decoupled(new OooIexLoadResult(p)) + val resultLane = Output(UInt(math.max(1, log2Ceil(laneCount)).W)) + val speculativeWakeup = Output(Vec(laneCount, + Valid(new OooIexWakeup(p)))) + val loadCancel = Output(Vec(laneCount, + Valid(new OooIexLoadCancel(p)))) + val loadBypass = Output(Vec(laneCount, + Valid(new OooIexBypassCandidate(p)))) + + val recoveryPrepare = Flipped(Valid(new RecoveryPlan(recoveryParams))) + val recoveryPrepareReady = Output(Bool()) + val recoveryPrepared = Valid(new RecoveryPlan(recoveryParams)) + val recoveryRejected = Output(Bool()) + val recoveryKilledMask = Output(UInt(lsu.liqEntries.W)) + val recoveryApply = Flipped(Valid(new RecoveryPlan(recoveryParams))) + val recoveryApplyAccepted = Output(Bool()) + val recoveryApplyRejected = Output(Bool()) + val recoveryAbort = Flipped(Valid(new RecoveryPlan(recoveryParams))) + val recoveryAbortAccepted = Output(Bool()) + val recoveryAbortRejected = Output(Bool()) + + val allocRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) + val rebindRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) + val attemptLaunchAccepted = Output(Bool()) + val attemptLaunchRejected = Valid( + new OooIexLoadTerminalMetadataReject(p, coreParams)) + val completionRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) + val cancelCollision = Output(Bool()) + val occupied = Output(UInt(log2Ceil(lsu.liqEntries + 1).W)) + val empty = Output(Bool()) +} + +/** Exact metadata-only owner joining canonical LSU attempts to OOO policy and + * terminal publication. + * + * A sidecar row remains occupied after LIQ resolution and is released only + * by the same `result.fire` that releases the LSU W2 transaction. Therefore + * the corresponding LIQ slot cannot be rebound to another producer while a + * delayed terminal transaction still names its old physical row lease. + */ +class OooIexLoadTerminalMetadata( + val p: OooParams = OooParams(), + val coreParams: CoreParams = CoreParams( + scalarLsu = linxcore.common.ScalarLsuParams( + stidCount = 4, loadReturnPipeCount = 2)), + val laneCount: Int = 2, + val recoveryParams: MainlineCoreParams) extends Module { + def this(p: OooParams, coreParams: CoreParams) = + this(p, coreParams, coreParams.scalarLsu.loadReturnPipeCount, + OooRecoveryMembership.coreParams(p)) + + def this(p: OooParams, coreParams: CoreParams, laneCount: Int) = + this(p, coreParams, laneCount, OooRecoveryMembership.coreParams(p)) + private val lsu = coreParams.scalarLsu + private val entriesCount = lsu.liqEntries + + require(lsu.stidCount == p.stidCount, + "OOO and canonical scalar LSU must share the STID population") + require(coreParams.robEntries >= p.robIdentityGroupsPerStid, + "canonical LSU ROB projection must cover every OOO RID slot") + require(p.pcWidth <= lsu.pcWidth && p.peIdWidth <= lsu.peIdWidth && + p.stidWidth <= lsu.stidWidth && p.archRegWidth <= lsu.archRegWidth && + p.pTagWidth <= lsu.physRegWidth, + "OOO terminal metadata must fit the canonical scalar LSU payload") + require(p.trapCauseWidth <= LoadTerminalFault.CauseWidth, + "OOO trap cause must fit the canonical load terminal fault payload") + require(laneCount > 0 && lsu.loadReturnPipeCount >= laneCount, + "terminal metadata requires every configured load lane") + LoadCanonicalRowIdentity.requireBridgeFits(entriesCount) + LoadAttemptIdentity.requireBridgeFits( + p.peIdWidth, + p.stidWidth, + p.nativeBidWidth, + p.ridSlotWidth, + p.brobGenerationWidth, + p.ridGenerationWidth, + p.robMemberIndexWidth, + p.residentGenerationWidth, + p.loadGenerationWidth) + OooRecoveryMembership.requireCompatible(p, recoveryParams) + + val io = IO(new OooIexLoadTerminalMetadataIO( + p, coreParams, laneCount, recoveryParams)) + + private def zeroEntry: OooIexLoadTerminalMetadataEntry = { + val entry = Wire(new OooIexLoadTerminalMetadataEntry( + p, coreParams, laneCount)) + entry := 0.U.asTypeOf(entry) + entry.loadId := LoadCanonicalRowIdentity.none + entry.attempt := LoadAttemptIdentity.none + entry + } + + private def toAttempt(load: OooIexLoadGeneration): LoadAttemptIdentity = { + val attempt = Wire(new LoadAttemptIdentity) + attempt := 0.U.asTypeOf(attempt) + attempt.valid := load.valid + attempt.producer.valid := load.producer.group.valid + attempt.producer.peId := load.producer.group.peId + attempt.producer.stid := load.producer.group.stid + attempt.producer.nativeBidValid := load.producer.bid.valid + attempt.producer.nativeBid := load.producer.bid.value + attempt.producer.brobGeneration := load.producer.brobGeneration + attempt.producer.ridSlot := load.producer.group.ridSlot + attempt.producer.ridGeneration := load.producer.group.ridGeneration + attempt.producer.memberIndex := load.producer.memberIndex + attempt.producer.residentGeneration := load.producer.residentGeneration + attempt.transactionValue := load.transaction.value + attempt.transactionGeneration := load.transaction.generation + attempt.generation := load.generation + attempt + } + + private def producerExact( + load: OooIexLoadGeneration, + request: OooIexAguLoadRequest): Bool = { + val row = request.execute.i2.row + load.valid && row.valid && row.member.group.valid && row.member.bid.valid && + row.memoryTransactionValid && + load.producer.asUInt === row.member.asUInt && + load.transaction.asUInt === row.memoryTransaction.asUInt && + row.member.group.peId === row.peId && + row.member.group.stid === row.stid && row.stid < p.stidCount.U + } + + private def projectedDestinationExact( + destination: LoadReplayDestination, + request: OooIexAguLoadRequest): Bool = { + val previous = request.execute.i2.row.payload.previousPDestinations(0) + val pExact = destination.kind === DestinationKind.Gpr && + request.destination.kind === DestinationKind.Gpr && + destination.physTag === request.destination.ptag && + destination.oldPhysTag === previous.ptag + val tExact = destination.kind === DestinationKind.T && + request.destination.kind === DestinationKind.T && + destination.physTag === request.destination.localTag && + destination.oldPhysTag === 0.U + destination.valid && request.destination.valid && (pExact || tExact) && + destination.archTag === request.destination.atag && + destination.relTag === request.destination.relativeIndex && + destination.kind === request.destination.kind + } + + private def operandClass(destination: OooIexDestinationState): OperandClass.Type = + Mux(destination.kind === DestinationKind.Gpr, OperandClass.P, + Mux(destination.kind === DestinationKind.T, OperandClass.T, + Mux(destination.kind === DestinationKind.U, OperandClass.U, + OperandClass.Invalid))) + + private def sidecarExact( + entry: OooIexLoadTerminalMetadataEntry, + index: Int): Bool = + !entry.valid || ( + LoadCanonicalRowIdentity.wellFormed(entry.loadId, entriesCount) && + entry.loadId.valid && entry.loadId.slot === index.U && + entry.lane < laneCount.U && + LoadAttemptIdentity.equal(entry.attempt, toAttempt(entry.load)) && + producerExact(entry.load, entry.request)) + + val entries = RegInit(VecInit(Seq.fill(entriesCount)(zeroEntry))) + val preparedValid = RegInit(false.B) + val preparedPlan = Reg(new RecoveryPlan(recoveryParams)) + val preparedKilledMask = Reg(UInt(entriesCount.W)) + + val entryExact = VecInit(entries.zipWithIndex.map { + case (entry, index) => sidecarExact(entry, index) + }) + val recoveryPlanExact = + io.recoveryPrepare.bits.phase === RecoveryPhase.Prepare && + RecoveryPlanContract.legalSuffixWindow(io.recoveryPrepare.bits) && + io.recoveryPrepare.bits.trigger.stid < p.stidCount.U && + entryExact.asUInt.andR + io.recoveryPrepareReady := !preparedValid && recoveryPlanExact + val recoveryPrepareFire = + io.recoveryPrepare.valid && io.recoveryPrepareReady + val recoveryKill = VecInit(entries.map(entry => + entry.valid && recoveryPlanExact && + OooRecoveryMembership.memberKilled( + p, recoveryParams, io.recoveryPrepare.bits, entry.load.producer))) + + private def recoveryFences(stid: UInt): Bool = + (recoveryPrepareFire && + io.recoveryPrepare.bits.trigger.stid === stid) || + (preparedValid && preparedPlan.trigger.stid === stid) + + val allocIdWellFormed = + LoadCanonicalRowIdentity.wellFormed(io.alloc.bits.loadId, entriesCount) + val allocIdValid = allocIdWellFormed && io.alloc.bits.loadId.valid + val allocIndex = io.alloc.bits.loadId.slot(log2Ceil(entriesCount) - 1, 0) + val allocResident = allocIdValid && entries(allocIndex).valid + val allocProducerExact = producerExact(io.alloc.bits.load, io.alloc.bits.request) + val allocAttemptExact = LoadAttemptIdentity.equal( + io.alloc.bits.attempt, toAttempt(io.alloc.bits.load)) + val allocInitialAttemptExact = + io.alloc.bits.request.execute.i2.row.initialLoadAttemptValid && + io.alloc.bits.load.generation === + io.alloc.bits.request.execute.i2.row.initialLoadAttemptGeneration + val allocLaneExact = io.alloc.bits.lane < laneCount.U + val allocExact = allocIdValid && allocProducerExact && allocAttemptExact && + allocInitialAttemptExact && allocLaneExact + val allocFence = recoveryFences(io.alloc.bits.load.producer.group.stid) + io.alloc.ready := !allocFence && allocExact && !allocResident + + val completionId = io.completion.bits.payload.loadId + val completionIdWellFormed = + LoadCanonicalRowIdentity.wellFormed(completionId, entriesCount) + val completionIdValid = completionIdWellFormed && completionId.valid + val completionIndex = completionId.slot(log2Ceil(entriesCount) - 1, 0) + val completionEntry = entries(completionIndex) + val completionResident = completionIdValid && completionEntry.valid && + LoadCanonicalRowIdentity.equal(completionEntry.loadId, completionId) + val completionProducerExact = completionResident && + producerExact(completionEntry.load, completionEntry.request) && + io.completion.bits.peId === completionEntry.request.execute.i2.row.peId && + io.completion.bits.stid === completionEntry.request.execute.i2.row.stid && + io.completion.bits.tid === completionEntry.request.execute.i2.row.stid + val completionAttemptExact = completionResident && + LoadAttemptIdentity.equal(io.completion.bits.payload.attempt, + completionEntry.attempt) + val completionTransactionExact = completionResident && + io.completion.bits.payload.transactionValid && + io.completion.bits.payload.transactionValue === + completionEntry.load.transaction.value && + io.completion.bits.payload.transactionGeneration === + completionEntry.load.transaction.generation + val completionPipeExact = completionResident && + io.completion.bits.payload.pipeIndex === completionEntry.lane + val completionDestinationExact = completionResident && + projectedDestinationExact(io.completion.bits.payload.dst, + completionEntry.request) + val completionOutcomeExact = io.completion.bits.payload.valid && + (!io.completion.bits.payload.faultValid || + io.completion.bits.payload.data === 0.U) + val completionExact = completionIdValid && completionProducerExact && + completionAttemptExact && completionTransactionExact && + completionPipeExact && completionDestinationExact && completionOutcomeExact + val completionFence = recoveryFences(io.completion.bits.stid) + io.result.valid := io.completion.valid && completionExact && !completionFence + io.result.bits := 0.U.asTypeOf(io.result.bits) + io.result.bits.agu := completionEntry.request + io.result.bits.load := completionEntry.load + io.result.bits.data := io.completion.bits.payload.data + io.result.bits.faultValid := io.completion.bits.payload.faultValid + io.result.bits.faultCause := io.completion.bits.payload.faultCause + io.completion.ready := !completionFence && + (!completionExact || io.result.ready) + io.resultLane := completionEntry.lane + + val launchId = io.attemptLaunch.bits.loadId + val launchIdWellFormed = + LoadCanonicalRowIdentity.wellFormed(launchId, entriesCount) + val launchIdValid = launchIdWellFormed && launchId.valid + val launchIndex = launchId.slot(log2Ceil(entriesCount) - 1, 0) + val launchEntry = entries(launchIndex) + val launchResident = launchIdValid && launchEntry.valid && + LoadCanonicalRowIdentity.equal(launchEntry.loadId, launchId) + val launchAttemptExact = launchResident && + LoadAttemptIdentity.equal(io.attemptLaunch.bits.attempt, + launchEntry.attempt) + val launchProducerExact = launchResident && + producerExact(launchEntry.load, launchEntry.request) + val launchExact = launchIdValid && launchResident && launchAttemptExact && + launchProducerExact + val launchFence = recoveryFences( + io.attemptLaunch.bits.attempt.producer.stid) + io.attemptLaunchAccepted := + io.attemptLaunch.valid && launchExact && !launchFence + + io.speculativeWakeup.foreach(_ := 0.U.asTypeOf( + io.speculativeWakeup.head)) + for (lane <- 0 until laneCount) { + when(io.attemptLaunchAccepted && launchEntry.lane === lane.U) { + val destination = launchEntry.request.destination + io.speculativeWakeup(lane).valid := true.B + io.speculativeWakeup(lane).bits.kind := + OooIexWakeupKind.SpeculativeLoad + io.speculativeWakeup(lane).bits.stid := + launchEntry.request.execute.i2.row.stid + io.speculativeWakeup(lane).bits.epoch := + launchEntry.request.execute.i2.row.epoch + io.speculativeWakeup(lane).bits.operandClass := + operandClass(destination) + io.speculativeWakeup(lane).bits.ptag := destination.ptag + io.speculativeWakeup(lane).bits.ptagGeneration := + destination.ptagGeneration + io.speculativeWakeup(lane).bits.localTag := destination.localTag + io.speculativeWakeup(lane).bits.localSequence := + destination.localSequence + io.speculativeWakeup(lane).bits.load := launchEntry.load + } + } + + val rebindId = io.rebind.bits.loadId + val rebindIdWellFormed = + LoadCanonicalRowIdentity.wellFormed(rebindId, entriesCount) + val rebindIdValid = rebindIdWellFormed && rebindId.valid + val rebindIndex = rebindId.slot(log2Ceil(entriesCount) - 1, 0) + val rebindEntry = entries(rebindIndex) + val rebindResident = rebindIdValid && rebindEntry.valid && + LoadCanonicalRowIdentity.equal(rebindEntry.loadId, rebindId) + val rebindCurrentExact = rebindResident && + rebindEntry.load.asUInt === io.rebind.bits.currentLoad.asUInt && + LoadAttemptIdentity.equal(rebindEntry.attempt, + io.rebind.bits.currentAttempt) && + LoadAttemptIdentity.equal(io.rebind.bits.currentAttempt, + toAttempt(io.rebind.bits.currentLoad)) + val rebindNextExact = rebindResident && + io.rebind.bits.nextLoad.valid && + io.rebind.bits.nextLoad.producer.asUInt === rebindEntry.load.producer.asUInt && + io.rebind.bits.nextLoad.transaction.asUInt === + rebindEntry.load.transaction.asUInt && + io.rebind.bits.nextLoad.generation === rebindEntry.load.generation + 1.U && + LoadAttemptIdentity.equal(io.rebind.bits.nextAttempt, + toAttempt(io.rebind.bits.nextLoad)) + val completionTargetsRebind = io.completion.valid && completionIdValid && + LoadCanonicalRowIdentity.equal(completionId, rebindId) + val rebindExact = rebindCurrentExact && rebindNextExact + val rebindFence = recoveryFences( + io.rebind.bits.currentLoad.producer.group.stid) + val faultCancelPublish = io.completion.valid && completionExact && + io.completion.bits.payload.faultValid && + !completionEntry.faultCancelSent && !completionFence + val cancelCollisionCandidate = rebindExact && + faultCancelPublish && + rebindEntry.lane === completionEntry.lane + val cancelCollision = io.rebind.valid && cancelCollisionCandidate + io.cancelCollision := cancelCollision + io.rebind.ready := !rebindFence && rebindExact && !completionTargetsRebind && + !cancelCollisionCandidate + + io.loadCancel.foreach(_ := 0.U.asTypeOf(io.loadCancel.head)) + for (lane <- 0 until laneCount) { + when(io.rebind.fire && rebindEntry.lane === lane.U) { + io.loadCancel(lane).valid := true.B + io.loadCancel(lane).bits.stid := rebindEntry.request.execute.i2.row.stid + io.loadCancel(lane).bits.epoch := rebindEntry.request.execute.i2.row.epoch + io.loadCancel(lane).bits.load := io.rebind.bits.currentLoad + } + when(faultCancelPublish && + completionEntry.lane === lane.U) { + io.loadCancel(lane).valid := true.B + io.loadCancel(lane).bits.stid := + completionEntry.request.execute.i2.row.stid + io.loadCancel(lane).bits.epoch := + completionEntry.request.execute.i2.row.epoch + io.loadCancel(lane).bits.load := completionEntry.load + } + } + + io.loadBypass.foreach(_ := 0.U.asTypeOf(io.loadBypass.head)) + for (lane <- 0 until laneCount) { + when(io.result.valid && !io.result.bits.faultValid && + completionEntry.lane === lane.U) { + val destination = completionEntry.request.destination + io.loadBypass(lane).valid := true.B + io.loadBypass(lane).bits.stid := + completionEntry.request.execute.i2.row.stid + io.loadBypass(lane).bits.epoch := + completionEntry.request.execute.i2.row.epoch + io.loadBypass(lane).bits.producer := completionEntry.load.producer + io.loadBypass(lane).bits.operandClass := operandClass(destination) + io.loadBypass(lane).bits.ptag := destination.ptag + io.loadBypass(lane).bits.ptagGeneration := + destination.ptagGeneration + io.loadBypass(lane).bits.localTag := destination.localTag + io.loadBypass(lane).bits.localSequence := destination.localSequence + io.loadBypass(lane).bits.load := completionEntry.load + io.loadBypass(lane).bits.stage := OooIexBypassStage.W1 + io.loadBypass(lane).bits.data := io.result.bits.data + } + } + + io.recoveryPrepared.valid := preparedValid + io.recoveryPrepared.bits := preparedPlan + io.recoveryRejected := + io.recoveryPrepare.valid && !io.recoveryPrepareReady + io.recoveryKilledMask := Mux(preparedValid, + preparedKilledMask, Mux(recoveryPrepareFire, + recoveryKill.asUInt, 0.U)) + + val recoveryTerminalConflict = + io.recoveryApply.valid && io.recoveryAbort.valid + val recoveryApplyExact = preparedValid && !recoveryTerminalConflict && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryApply.bits, preparedPlan) + io.recoveryApplyAccepted := io.recoveryApply.valid && recoveryApplyExact + io.recoveryApplyRejected := io.recoveryApply.valid && !recoveryApplyExact + + val recoveryAbortExact = preparedValid && !recoveryTerminalConflict && + io.recoveryAbort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryAbort.bits, preparedPlan) + io.recoveryAbortAccepted := io.recoveryAbort.valid && recoveryAbortExact + io.recoveryAbortRejected := io.recoveryAbort.valid && !recoveryAbortExact + + private def rejectDefaults( + out: Valid[OooIexLoadTerminalMetadataReject]): Unit = { + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + out.bits.loadId := LoadCanonicalRowIdentity.none + } + rejectDefaults(io.allocRejected) + rejectDefaults(io.rebindRejected) + rejectDefaults(io.attemptLaunchRejected) + rejectDefaults(io.completionRejected) + + io.allocRejected.valid := io.alloc.valid && !allocFence && !io.alloc.ready + io.allocRejected.bits.loadId := io.alloc.bits.loadId + io.allocRejected.bits.member := io.alloc.bits.load.producer + io.allocRejected.bits.rowIdExact := allocIdValid + io.allocRejected.bits.resident := allocResident + io.allocRejected.bits.producerExact := allocProducerExact + io.allocRejected.bits.attemptExact := + allocAttemptExact && allocInitialAttemptExact + io.allocRejected.bits.destinationExact := true.B + io.allocRejected.bits.outcomeExact := allocLaneExact + + io.rebindRejected.valid := + io.rebind.valid && !rebindFence && !io.rebind.ready + io.rebindRejected.bits.loadId := rebindId + io.rebindRejected.bits.member := io.rebind.bits.currentLoad.producer + io.rebindRejected.bits.rowIdExact := rebindIdValid + io.rebindRejected.bits.resident := rebindResident + io.rebindRejected.bits.producerExact := rebindCurrentExact + io.rebindRejected.bits.attemptExact := rebindNextExact + io.rebindRejected.bits.destinationExact := true.B + io.rebindRejected.bits.outcomeExact := + !completionTargetsRebind && !cancelCollisionCandidate + + io.attemptLaunchRejected.valid := io.attemptLaunch.valid && + !launchFence && !launchExact + io.attemptLaunchRejected.bits.loadId := launchId + io.attemptLaunchRejected.bits.member := launchEntry.load.producer + io.attemptLaunchRejected.bits.rowIdExact := launchIdValid + io.attemptLaunchRejected.bits.resident := launchResident + io.attemptLaunchRejected.bits.producerExact := launchProducerExact + io.attemptLaunchRejected.bits.attemptExact := launchAttemptExact + io.attemptLaunchRejected.bits.destinationExact := true.B + io.attemptLaunchRejected.bits.outcomeExact := true.B + + io.completionRejected.valid := + io.completion.valid && !completionFence && !completionExact + io.completionRejected.bits.loadId := completionId + io.completionRejected.bits.member := completionEntry.load.producer + io.completionRejected.bits.rowIdExact := completionIdValid + io.completionRejected.bits.resident := completionResident + io.completionRejected.bits.producerExact := completionProducerExact + io.completionRejected.bits.attemptExact := completionAttemptExact + io.completionRejected.bits.transactionExact := completionTransactionExact + io.completionRejected.bits.pipeExact := completionPipeExact + io.completionRejected.bits.destinationExact := completionDestinationExact + io.completionRejected.bits.outcomeExact := completionOutcomeExact + + when(recoveryPrepareFire) { + preparedValid := true.B + preparedPlan := io.recoveryPrepare.bits + preparedKilledMask := recoveryKill.asUInt + } + when(io.recoveryApplyAccepted || io.recoveryAbortAccepted) { + preparedValid := false.B + } + when(io.result.fire) { + entries(completionIndex) := zeroEntry + } + when(io.rebind.fire) { + entries(rebindIndex).attempt := io.rebind.bits.nextAttempt + entries(rebindIndex).load := io.rebind.bits.nextLoad + entries(rebindIndex).faultCancelSent := false.B + } + when(faultCancelPublish && !io.result.fire) { + entries(completionIndex).faultCancelSent := true.B + } + when(io.alloc.fire) { + entries(allocIndex).valid := true.B + entries(allocIndex).loadId := io.alloc.bits.loadId + entries(allocIndex).attempt := io.alloc.bits.attempt + entries(allocIndex).load := io.alloc.bits.load + entries(allocIndex).request := io.alloc.bits.request + entries(allocIndex).lane := io.alloc.bits.lane + entries(allocIndex).faultCancelSent := false.B + } + when(io.recoveryApplyAccepted) { + for (index <- 0 until entriesCount) { + when(preparedKilledMask(index)) { + entries(index) := zeroEntry + } + } + } + + io.occupied := PopCount(VecInit(entries.map(_.valid))) + io.empty := !VecInit(entries.map(_.valid)).asUInt.orR + + when(io.result.fire) { + assert(io.completion.fire, + "canonical LSU completion and OOO terminal result must share owner release") + } +} diff --git a/chisel/src/main/scala/linxcore/ifu/BSide.scala b/chisel/src/main/scala/linxcore/ifu/BSide.scala new file mode 100644 index 00000000..cbf54aa3 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/BSide.scala @@ -0,0 +1,42 @@ +package linxcore.ifu + +import linxcore.common.InterfaceParams +import linxcore.frontend.BSidePredictionPipeline + +/** Public B-SIDE prediction owner boundary. + * + * This module intentionally reuses the existing prediction pipeline as its + * implementation body so BTB/TAGE/BIM/RAS/loop/history state has one owner. + */ +class BSide( + p: InterfaceParams = InterfaceParams(), + lineBytes: Int = 64, + threadCount: Int = 1, + boundaryEntries: Int = 16, + responseEntries: Int = 16, + trainingEntries: Int = 8, + historyEntries: Int = 16, + nanoEntries: Int = 8, + ubtbEntries: Int = 16, + pbtbEntries: Int = 32, + bimEntries: Int = 64, + tageEntries: Int = 32, + ibtbEntries: Int = 16, + loopEntries: Int = 16, + rasDepth: Int = 8) + extends BSidePredictionPipeline( + p = p, + lineBytes = lineBytes, + threadCount = threadCount, + boundaryEntries = boundaryEntries, + responseEntries = responseEntries, + trainingEntries = trainingEntries, + historyEntries = historyEntries, + nanoEntries = nanoEntries, + ubtbEntries = ubtbEntries, + pbtbEntries = pbtbEntries, + bimEntries = bimEntries, + tageEntries = tageEntries, + ibtbEntries = ibtbEntries, + loopEntries = loopEntries, + rasDepth = rasDepth) diff --git a/chisel/src/main/scala/linxcore/ifu/FetchBuffer.scala b/chisel/src/main/scala/linxcore/ifu/FetchBuffer.scala new file mode 100644 index 00000000..8071689f --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/FetchBuffer.scala @@ -0,0 +1,150 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.util.{Decoupled, PopCount, PriorityEncoder, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.{FetchedInstruction, FetchedPacket, RecoveryPlan} + +class FetchBufferIngress(val p: CoreParams, val ingressWidth: Int) extends Bundle { + val count = UInt(log2Ceil(ingressWidth + 1).W) + val entries = Vec(ingressWidth, new FetchedInstruction(p)) +} + +class FetchBufferIO( + val p: CoreParams, + val ingressWidth: Int, + val depth: Int) + extends Bundle { + val enq = Flipped(Decoupled(new FetchBufferIngress(p, ingressWidth))) + val deq = Decoupled(new FetchedPacket(p)) + val prune = Flipped(Valid(new RecoveryPlan(p))) + val occupancy = Output(UInt(log2Ceil(depth + 1).W)) +} + +/** Retained width converter between the I-SIDE fetch geometry and CTU. + * + * Each accepted instruction receives a monotonic local order. The configured + * IFU width controls only the oldest continuous prefix presented to CTU; it + * does not leak into cache-line lookup or instruction assembly geometry. + */ +class FetchBuffer( + val p: CoreParams, + val ingressWidth: Int = 4, + val depth: Int = -1) + extends Module { + private val resolvedDepth = if (depth > 0) depth else p.ifu.fetchBufferEntries + require(ingressWidth > 0) + require(resolvedDepth >= math.max(ingressWidth, p.widths.fetchWidth)) + + val io = IO(new FetchBufferIO(p, ingressWidth, resolvedDepth)) + + private val countWidth = log2Ceil(resolvedDepth + 1) + private val indexWidth = math.max(1, log2Ceil(resolvedDepth)) + private val orderWidth = 64 + + val valid = RegInit(VecInit(Seq.fill(resolvedDepth)(false.B))) + val entries = Reg(Vec(resolvedDepth, new FetchedInstruction(p))) + val order = Reg(Vec(resolvedDepth, UInt(orderWidth.W))) + val count = RegInit(0.U(countWidth.W)) + val nextOrder = RegInit(0.U(orderWidth.W)) + + val outputCount = Mux( + count > p.widths.fetchWidth.U, + p.widths.fetchWidth.U, + count) + io.deq.valid := count.orR && !io.prune.valid + io.deq.bits := 0.U.asTypeOf(io.deq.bits) + io.deq.bits.count := outputCount + + val selectedValid = Wire(Vec(p.widths.fetchWidth, Bool())) + val selectedIndex = + Wire(Vec(p.widths.fetchWidth, UInt(indexWidth.W))) + var remainingMask: UInt = valid.asUInt + for (lane <- 0 until p.widths.fetchWidth) { + var found: Bool = false.B + var oldestIndex: UInt = 0.U(indexWidth.W) + var oldestOrder: UInt = 0.U(orderWidth.W) + for (slot <- 0 until resolvedDepth) { + val choose = remainingMask(slot) && + (!found || order(slot) < oldestOrder) + oldestIndex = Mux(choose, slot.U, oldestIndex) + oldestOrder = Mux(choose, order(slot), oldestOrder) + found = found || remainingMask(slot) + } + selectedValid(lane) := found + selectedIndex(lane) := oldestIndex + when(found) { + io.deq.bits.entries(lane) := entries(oldestIndex) + } + val selectedBit = Mux( + found, + (1.U(resolvedDepth.W) << oldestIndex)(resolvedDepth - 1, 0), + 0.U(resolvedDepth.W)) + remainingMask = remainingMask & ~selectedBit + } + + val enqCount = io.enq.bits.count + val freeCount = resolvedDepth.U - count + io.enq.ready := !io.prune.valid && enqCount.orR && enqCount <= freeCount + io.occupancy := count + + val insertValid = Wire(Vec(ingressWidth, Bool())) + val insertIndex = Wire(Vec(ingressWidth, UInt(indexWidth.W))) + var freeMask: UInt = ~valid.asUInt + for (lane <- 0 until ingressWidth) { + val found = freeMask.orR + val index = PriorityEncoder(freeMask) + insertValid(lane) := found && lane.U < enqCount + insertIndex(lane) := index + val claimedBit = Mux( + found, + (1.U(resolvedDepth.W) << index)(resolvedDepth - 1, 0), + 0.U(resolvedDepth.W)) + freeMask = freeMask & ~claimedBit + } + + val killed = Wire(Vec(resolvedDepth, Bool())) + for (slot <- 0 until resolvedDepth) { + killed(slot) := valid(slot) && + entries(slot).identity.stid === io.prune.bits.trigger.stid + } + val killedCount = PopCount(killed) + + when(io.prune.valid) { + for (slot <- 0 until resolvedDepth) { + when(killed(slot)) { + valid(slot) := false.B + } + } + count := count - killedCount + }.otherwise { + when(io.deq.fire) { + for (lane <- 0 until p.widths.fetchWidth) { + when(selectedValid(lane) && lane.U < outputCount) { + valid(selectedIndex(lane)) := false.B + } + } + } + when(io.enq.fire) { + for (lane <- 0 until ingressWidth) { + when(insertValid(lane)) { + valid(insertIndex(lane)) := true.B + entries(insertIndex(lane)) := io.enq.bits.entries(lane) + order(insertIndex(lane)) := nextOrder + lane.U + } + } + nextOrder := nextOrder + enqCount + } + count := count - + Mux(io.deq.fire, outputCount, 0.U) + + Mux(io.enq.fire, enqCount, 0.U) + } + + assert(count === PopCount(valid)) + assert(count <= resolvedDepth.U) + assert(!io.enq.valid || io.enq.bits.count <= ingressWidth.U) + when(io.enq.fire) { + assert(nextOrder + enqCount >= nextOrder) + assert(insertValid.asUInt === ((1.U << enqCount) - 1.U)) + } +} diff --git a/chisel/src/main/scala/linxcore/ifu/IFU.scala b/chisel/src/main/scala/linxcore/ifu/IFU.scala new file mode 100644 index 00000000..23a987d9 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/IFU.scala @@ -0,0 +1,23 @@ +package linxcore.ifu + +import chisel3._ +import linxcore.params.CoreParams +import linxcore.top.interface.IFUIO + +/** Public IFU box. All implementation state remains below this typed shell. */ +class IFU(val p: CoreParams) extends Module { + val io = IO(new IFUIO(p)) + val iSide = Module(new ISide(p)) + + io.toCtu <> iSide.io.toCtu + io.memoryRequest <> iSide.io.memoryRequest + iSide.io.memoryResponse <> io.memoryResponse + iSide.io.branchResolve <> io.branchResolve + + iSide.io.recovery.prepare <> io.recovery.prepare + io.recovery.prepared <> iSide.io.recovery.prepared + iSide.io.recovery.apply := io.recovery.apply + iSide.io.recovery.abort := io.recovery.abort + + io.trace <> iSide.io.trace +} diff --git a/chisel/src/main/scala/linxcore/ifu/IFURecovery.scala b/chisel/src/main/scala/linxcore/ifu/IFURecovery.scala new file mode 100644 index 00000000..01e6043b --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/IFURecovery.scala @@ -0,0 +1,21 @@ +package linxcore.ifu + +import linxcore.common.InterfaceParams +import linxcore.frontend.{IfuBackendFeedbackBridge, IfuRedirectArbiter} + +/** Canonical IFU redirect arbiter. + * + * Backend typed recovery enters through the backend redirect input and + * supersedes speculative prediction correction. It is not a prediction + * provider and it does not expose an IEX control port. + */ +class IFURecovery( + p: InterfaceParams = InterfaceParams(), + threadCount: Int = 1) + extends IfuRedirectArbiter(p, threadCount) + +/** OOO-authored backend feedback boundary for IFU training and recovery. */ +class IFUBackendFeedback( + p: InterfaceParams = InterfaceParams(), + entries: Int = 2) + extends IfuBackendFeedbackBridge(p, entries) diff --git a/chisel/src/main/scala/linxcore/ifu/ISide.scala b/chisel/src/main/scala/linxcore/ifu/ISide.scala new file mode 100644 index 00000000..d3b50bce --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/ISide.scala @@ -0,0 +1,563 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.util.{Cat, Decoupled, MuxCase, PopCount, Valid, is, log2Ceil, switch} +import linxcore.common.{BoundaryKind, InterfaceParams} +import linxcore.frontend._ +import linxcore.params.CoreParams +import linxcore.top.interface._ + +private object ISideMemoryKind extends ChiselEnum { + val Line, Translation = Value +} + +object ISide { + def interfaceParams(p: CoreParams): InterfaceParams = { + val ingressWidth = 4 + val checkpointWidth = + math.max(1, log2Ceil(p.ifu.predictionCheckpointEntries)) + val threadWidth = p.ooo.stidWidth + InterfaceParams( + fetchWidth = ingressWidth, + decodeWidth = ingressWidth, + issueWidth = 4, + commitWidth = 4, + pcWidth = p.pcWidth, + windowWidth = 64, + opcodeWidth = p.opcodeWidth, + insnWidth = p.instructionWidth, + lenWidth = 4, + archRegWidth = p.archRegWidth, + physRegWidth = math.max(6, p.ooo.gprTagWidth), + robEntries = p.ooo.robGroupsPerStid, + iqEntries = p.iex.scalarIssueEntries, + blockBidWidth = 64, + blockUidWidth = p.instructionIdWidth, + uopUidWidth = p.transactionIdWidth, + lsidWidth = p.lsidWidth, + checkpointWidth = checkpointWidth, + peIdWidth = p.peIdWidth, + threadIdWidth = threadWidth, + trapCauseWidth = p.trapCauseWidth, + blockEpochWidth = p.epochWidth) + } +} + +private class ISideMemoryFault( + val p: CoreParams, + val fp: InterfaceParams) + extends Bundle { + val request = + new ISideFetchRequest(fp, p.ifu.lineBytes) + val cause = UInt(p.trapCauseWidth.W) +} + +private class ISideMemoryAdapterIO( + val p: CoreParams, + val fp: InterfaceParams) + extends Bundle { + val lineRequest = + Flipped(Decoupled(new ISideLineReadRequest(fp, p.ifu.lineBytes))) + val lineRefill = + Decoupled(new ISideLineResponse(fp, p.ifu.lineBytes)) + val translationRequest = + Flipped(Decoupled( + new ISidePtwRequest(fp, p.ifu.lineBytes, p.ifu.pageBytes))) + val translationRefill = + Valid(new ISideItlbRefill(fp, p.ifu.pageBytes)) + val lineFault = Decoupled(new ISideMemoryFault(p, fp)) + val memoryRequest = Decoupled(new MemoryRequestTxn(p)) + val memoryResponse = Flipped(Decoupled(new MemoryResponseTxn(p))) + val staleResponse = Output(Bool()) +} + +/** Exact-identity adapter from retained IFU line/PTW traffic to 64-bit beats. */ +private class ISideMemoryAdapter( + val p: CoreParams, + val fp: InterfaceParams) + extends Module { + private val beatBytes = p.dataWidth / 8 + private val beatsPerLine = p.ifu.lineBytes / beatBytes + private val beatWidth = math.max(1, log2Ceil(beatsPerLine)) + private val pageOffsetBits = log2Ceil(p.ifu.pageBytes) + private val ppnWidth = p.pcWidth - pageOffsetBits + + require(p.ifu.lineBytes % beatBytes == 0) + require(beatsPerLine > 0) + + val io = IO(new ISideMemoryAdapterIO(p, fp)) + + val active = RegInit(false.B) + val kind = RegInit(ISideMemoryKind.Line) + val lineRequest = + RegInit(0.U.asTypeOf(new ISideLineReadRequest(fp, p.ifu.lineBytes))) + val translationRequest = + RegInit(0.U.asTypeOf( + new ISidePtwRequest(fp, p.ifu.lineBytes, p.ifu.pageBytes))) + val beat = RegInit(0.U(beatWidth.W)) + val lineBeats = + RegInit(VecInit(Seq.fill(beatsPerLine)(0.U(p.dataWidth.W)))) + + val requestOutstanding = RegInit(false.B) + val outstandingIdentity = + RegInit(0.U.asTypeOf(new MemoryTransactionIdentity(p))) + val nextValue = RegInit(0.U(p.memoryTransactionIdWidth.W)) + val nextGeneration = RegInit(0.U(p.memoryTransactionGenerationWidth.W)) + + val lineRefillValid = RegInit(false.B) + val lineRefillData = + RegInit(0.U((p.ifu.lineBytes * 8).W)) + val lineFaultValid = RegInit(false.B) + val lineFaultRequest = + RegInit(0.U.asTypeOf( + new ISideFetchRequest(fp, p.ifu.lineBytes))) + val lineFaultCause = RegInit(0.U(p.trapCauseWidth.W)) + + val idle = !active && !lineRefillValid && !lineFaultValid + io.translationRequest.ready := idle + io.lineRequest.ready := idle && !io.translationRequest.valid + + when(io.translationRequest.fire) { + active := true.B + kind := ISideMemoryKind.Translation + translationRequest := io.translationRequest.bits + beat := 0.U + }.elsewhen(io.lineRequest.fire) { + active := true.B + kind := ISideMemoryKind.Line + lineRequest := io.lineRequest.bits + beat := 0.U + } + + io.memoryRequest.valid := active && !requestOutstanding + io.memoryRequest.bits := 0.U.asTypeOf(io.memoryRequest.bits) + io.memoryRequest.bits.identity.value := nextValue + io.memoryRequest.bits.identity.generation := nextGeneration + io.memoryRequest.bits.command := MemoryCommand.Read + io.memoryRequest.bits.accessKind := Mux( + kind === ISideMemoryKind.Translation, + MemoryAccessKind.InstructionTranslation, + MemoryAccessKind.InstructionLine) + io.memoryRequest.bits.address := Mux( + kind === ISideMemoryKind.Translation, + translationRequest.vpn << pageOffsetBits, + lineRequest.linePa + beat * beatBytes.U) + io.memoryRequest.bits.size := MemorySize.fromBytes(beatBytes.U) + io.memoryRequest.bits.instructionSide := true.B + + val requestFire = io.memoryRequest.fire + val responseExpected = requestOutstanding || requestFire + val expectedIdentity = Wire(new MemoryTransactionIdentity(p)) + expectedIdentity := Mux( + requestFire, + io.memoryRequest.bits.identity, + outstandingIdentity) + val responseMatches = + responseExpected && + io.memoryResponse.bits.identity.value === expectedIdentity.value && + io.memoryResponse.bits.identity.generation === expectedIdentity.generation + + io.memoryResponse.ready := true.B + io.staleResponse := io.memoryResponse.valid && !responseMatches + + when(requestFire) { + requestOutstanding := true.B + outstandingIdentity := io.memoryRequest.bits.identity + val valueWrap = nextValue.andR + nextValue := nextValue + 1.U + when(valueWrap) { + nextGeneration := nextGeneration + 1.U + } + } + + io.translationRefill.valid := false.B + io.translationRefill.bits := 0.U.asTypeOf(io.translationRefill.bits) + when(io.memoryResponse.fire && responseMatches) { + requestOutstanding := false.B + when(kind === ISideMemoryKind.Translation) { + io.translationRefill.valid := true.B + io.translationRefill.bits.vpn := translationRequest.vpn + io.translationRefill.bits.ppn := + io.memoryResponse.bits.data(ppnWidth - 1, 0) + io.translationRefill.bits.executable := + !io.memoryResponse.bits.denied && !io.memoryResponse.bits.corrupt + active := false.B + }.otherwise { + when(io.memoryResponse.bits.denied || io.memoryResponse.bits.corrupt) { + lineFaultValid := true.B + lineFaultRequest := lineRequest.request + lineFaultCause := io.memoryResponse.bits.errorCause + active := false.B + }.otherwise { + val assembled = Wire(Vec(beatsPerLine, UInt(p.dataWidth.W))) + assembled := lineBeats + assembled(beat) := io.memoryResponse.bits.data + lineBeats(beat) := assembled(beat) + when(beat === (beatsPerLine - 1).U) { + lineRefillData := Cat(assembled.reverse) + lineRefillValid := true.B + active := false.B + }.otherwise { + beat := beat + 1.U + } + } + } + } + + io.lineRefill.valid := lineRefillValid + io.lineRefill.bits := 0.U.asTypeOf(io.lineRefill.bits) + io.lineRefill.bits.peId := lineRequest.request.identity.peId + io.lineRefill.bits.transactionId := lineRequest.request.transactionId + io.lineRefill.bits.threadId := lineRequest.request.identity.threadId + io.lineRefill.bits.fetchPacketUid := + lineRequest.request.identity.fetchPacketUid + io.lineRefill.bits.fetchSeq := lineRequest.request.identity.fetchSeq + io.lineRefill.bits.checkpointId := + lineRequest.request.identity.checkpointId + io.lineRefill.bits.epoch := lineRequest.request.identity.epoch + io.lineRefill.bits.lineVa := lineRequest.request.lineVa + io.lineRefill.bits.linePa := lineRequest.linePa + io.lineRefill.bits.lineData := lineRefillData + + when(io.lineRefill.fire) { + lineRefillValid := false.B + } + + io.lineFault.valid := lineFaultValid + io.lineFault.bits.request := lineFaultRequest + io.lineFault.bits.cause := lineFaultCause + when(io.lineFault.fire) { + lineFaultValid := false.B + } + + when(io.memoryResponse.fire && responseMatches) { + assert(requestOutstanding || requestFire) + } +} + +/** Canonical IFU I-SIDE owner and fixed-64-bit delivery boundary. */ +class ISide(val p: CoreParams) extends Module { + private val ingressWidth = 4 + private val fp = ISide.interfaceParams(p) + + val io = IO(new IFUIO(p)) + + val engine = Module(new LinxCoreIfu( + fp, + threadCount = p.ooo.stidCount, + lineBytes = p.ifu.lineBytes, + pageBytes = p.ifu.pageBytes, + itlbEntries = p.ifu.itlbEntries, + l1iSets = p.ifu.l1iSets, + missEntries = p.ifu.missEntries, + joinEntries = p.ifu.joinEntries, + maxGroupsPerTransaction = p.ifu.maxGroupsPerTransaction, + instructionBufferDepth = ingressWidth, + externalFetchBuffer = true)) + private val memory = Module(new ISideMemoryAdapter(p, fp)) + val fetchBuffer = Module(new FetchBuffer(p, ingressWidth)) + + memory.io.lineRequest <> engine.io.lineRead + engine.io.lineRefill <> memory.io.lineRefill + memory.io.translationRequest <> engine.io.ptwRequest + engine.io.ptwRefill := memory.io.translationRefill + io.memoryRequest <> memory.io.memoryRequest + memory.io.memoryResponse <> io.memoryResponse + + engine.io.invalidateItlb := false.B + engine.io.invalidateL1I := false.B + engine.io.branchResolve.valid := io.branchResolve.valid + engine.io.branchResolve.bits := 0.U.asTypeOf(engine.io.branchResolve.bits) + engine.io.branchResolve.bits.peId := io.branchResolve.bits.peId + engine.io.branchResolve.bits.transactionId := + io.branchResolve.bits.transactionId + engine.io.branchResolve.bits.predictionTag := + io.branchResolve.bits.predictionTag + engine.io.branchResolve.bits.threadId := io.branchResolve.bits.stid + engine.io.branchResolve.bits.fetchPacketUid := + io.branchResolve.bits.fetchPacketUid + engine.io.branchResolve.bits.fetchSeq := io.branchResolve.bits.fetchSeq + engine.io.branchResolve.bits.epoch := io.branchResolve.bits.epoch + engine.io.branchResolve.bits.checkpointId := + io.branchResolve.bits.checkpointId + engine.io.branchResolve.bits.requestPc := io.branchResolve.bits.requestPc + engine.io.branchResolve.bits.branchPc := io.branchResolve.bits.branchPc + engine.io.branchResolve.bits.fallthroughPc := + io.branchResolve.bits.fallthroughPc + engine.io.branchResolve.bits.taken := io.branchResolve.bits.taken + engine.io.branchResolve.bits.target := io.branchResolve.bits.target + engine.io.branchResolve.bits.kind := io.branchResolve.bits.kind + engine.io.branchResolve.bits.mispredict := io.branchResolve.bits.mispredict + io.branchResolve.ready := engine.io.branchResolve.ready + engine.io.d1ThreadId := 0.U + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val redirectQueued = RegInit(false.B) + val redirectPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + + def sameRecovery(lhs: RecoveryPlan, rhs: RecoveryPlan): Bool = + lhs.transactionId === rhs.transactionId && + lhs.cause === rhs.cause && + lhs.trigger.asUInt === rhs.trigger.asUInt && + lhs.survivingTailValid === rhs.survivingTailValid && + lhs.survivingTail.asUInt === rhs.survivingTail.asUInt && + lhs.redirectPc === rhs.redirectPc && + lhs.newEpoch === rhs.newEpoch + + io.recovery.prepare.ready := !recoveryPending && !redirectQueued + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan + val prepareFire = io.recovery.prepare.fire + val preparedCompletes = + !preparedValid || io.recovery.prepared.fire + val applyMatches = sameRecovery(io.recovery.apply.bits, recoveryPlan) + val abortMatches = sameRecovery(io.recovery.abort.bits, recoveryPlan) + val applyHit = + recoveryPending && io.recovery.apply.valid && preparedCompletes && + applyMatches && io.recovery.apply.bits.phase === RecoveryPhase.Apply + val abortHit = + recoveryPending && io.recovery.abort.valid && preparedCompletes && + abortMatches && io.recovery.abort.bits.phase === RecoveryPhase.Abort + + when(prepareFire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(applyHit) { + preparedValid := false.B + redirectQueued := true.B + redirectPlan := io.recovery.apply.bits + }.elsewhen(abortHit) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + engine.io.backendRedirect.valid := redirectQueued + engine.io.backendRedirect.bits := + 0.U.asTypeOf(engine.io.backendRedirect.bits) + engine.io.backendRedirect.bits.valid := redirectQueued + engine.io.backendRedirect.bits.peId := redirectPlan.trigger.peId + engine.io.backendRedirect.bits.threadId := redirectPlan.trigger.stid + engine.io.backendRedirect.bits.transactionId := redirectPlan.transactionId + engine.io.backendRedirect.bits.fetchSeq := 0.U + engine.io.backendRedirect.bits.oldEpoch := + (if (p.ooo.stidCount == 1) { + engine.io.epochs(0) + } else { + engine.io.epochs(redirectPlan.trigger.stid) + }) + engine.io.backendRedirect.bits.restartPc := redirectPlan.redirectPc + engine.io.backendRedirect.bits.checkpointId := 0.U + engine.io.backendRedirect.bits.newEpoch := redirectPlan.newEpoch + engine.io.backendRedirect.bits.reason := IfuInnerFlushReason.OooRecovery + engine.io.backendRedirect.bits.scope := IfuPruneScope.KillAllThreadState + engine.io.backendRedirect.bits.fetchPacketUid := 0.U + engine.io.backendRedirect.bits.ghrAction := GhrRecoveryAction.Reset + engine.io.backendRedirect.bits.rasAction := RasRecoveryAction.Reset + + when(engine.io.backendRedirect.fire) { + redirectQueued := false.B + recoveryPending := false.B + } + + val bootPending = RegInit(true.B) + engine.io.start.valid := bootPending && !recoveryPending && !redirectQueued + engine.io.start.bits := 0.U.asTypeOf(engine.io.start.bits) + engine.io.start.bits.peId := 0.U + engine.io.start.bits.threadId := 0.U + engine.io.start.bits.pc := p.ifu.resetVector.U(p.pcWidth.W) + when(engine.io.start.valid) { + bootPending := false.B + } + + val recoveryFence = + recoveryPending || redirectQueued || prepareFire || applyHit || abortHit + + val ingress = Wire(Decoupled(new FetchBufferIngress(p, ingressWidth))) + ingress.bits := 0.U.asTypeOf(ingress.bits) + + val lineFaultEpoch = + (if (p.ooo.stidCount == 1) { + engine.io.epochs(0) + } else { + engine.io.epochs(memory.io.lineFault.bits.request.identity.threadId) + }) + val lineFaultStale = + memory.io.lineFault.valid && + memory.io.lineFault.bits.request.identity.epoch =/= lineFaultEpoch + val memoryFaultValid = memory.io.lineFault.valid && !lineFaultStale + val faultValid = memoryFaultValid || engine.io.fetchFault.valid + val d1Valid = engine.io.d1.valid && engine.io.d1.bits.validMask.orR + val compactedD1 = Wire(Vec(ingressWidth, new InstructionBufferEntry(fp))) + val d1Count = PopCount(engine.io.d1.bits.validMask) + for (dst <- 0 until ingressWidth) { + val candidates = (0 until ingressWidth).map { lane => + val rank = + if (lane == 0) 0.U else PopCount(engine.io.d1.bits.validMask(lane - 1, 0)) + (engine.io.d1.bits.validMask(lane) && rank === dst.U) -> + engine.io.d1.bits.entries(lane) + } + compactedD1(dst) := MuxCase( + 0.U.asTypeOf(new InstructionBufferEntry(fp)), + candidates) + } + + ingress.valid := !recoveryFence && (faultValid || d1Valid) + ingress.bits.count := Mux(faultValid, 1.U, d1Count) + memory.io.lineFault.ready := + lineFaultStale || (!recoveryFence && fetchBuffer.io.enq.ready) + engine.io.fetchFault.ready := + !memoryFaultValid && !recoveryFence && fetchBuffer.io.enq.ready + engine.io.d1.ready := + !recoveryFence && !faultValid && fetchBuffer.io.enq.ready + + def mapIdentity( + out: InstructionIdentity, + in: IfuFetchIdentity, + instructionId: UInt): Unit = { + out.peId := in.peId + out.stid := in.threadId + out.instructionId := instructionId + out.epoch := in.epoch + } + + def mapPrediction( + out: PredictionMeta, + in: BranchPredictionRecord, + identity: IfuFetchIdentity, + transactionId: UInt): Unit = { + out.valid := in.valid + out.predictionTag := in.predictionTag + out.transactionId := transactionId + out.fetchPacketUid := identity.fetchPacketUid + out.fetchSeq := identity.fetchSeq + out.checkpointId := in.checkpointId + out.requestPc := in.requestPc + out.taken := in.taken + out.branchPc := in.branchPc + out.target := in.target + out.fallthroughPc := in.fallthroughPc + out.kind := PredictionKind.None + switch(in.kind) { + is(BoundaryKind.Fall) { out.kind := PredictionKind.Fall } + is(BoundaryKind.Cond) { out.kind := PredictionKind.Conditional } + is(BoundaryKind.Call) { out.kind := PredictionKind.Call } + is(BoundaryKind.Ret) { out.kind := PredictionKind.Return } + is(BoundaryKind.Direct) { out.kind := PredictionKind.Direct } + is(BoundaryKind.Ind) { out.kind := PredictionKind.Indirect } + is(BoundaryKind.ICall) { out.kind := PredictionKind.Indirect } + } + out.provider := in.provider.asUInt + out.stage := in.stage.asUInt + out.confidence := in.confidence + out.epoch := in.epoch + } + + for (lane <- 0 until ingressWidth) { + val source = compactedD1(lane) + val out = ingress.bits.entries(lane) + mapIdentity(out.identity, source.identity, source.instructionUid) + out.pc := source.pc + out.instruction := source.insn + out.lengthBytes := source.lenBytes + mapPrediction( + out.prediction, + source.prediction, + source.identity, + source.transactionId) + out.fetchFault := false.B + out.fetchFaultCause := 0.U + } + when(memoryFaultValid) { + val out = ingress.bits.entries(0) + mapIdentity( + out.identity, + memory.io.lineFault.bits.request.identity, + memory.io.lineFault.bits.request.transactionId) + out.pc := memory.io.lineFault.bits.request.pc + out.instruction := 0.U + out.lengthBytes := 0.U + mapPrediction( + out.prediction, + memory.io.lineFault.bits.request.prediction, + memory.io.lineFault.bits.request.identity, + memory.io.lineFault.bits.request.transactionId) + out.fetchFault := true.B + out.fetchFaultCause := memory.io.lineFault.bits.cause + }.elsewhen(engine.io.fetchFault.valid) { + val out = ingress.bits.entries(0) + mapIdentity( + out.identity, + engine.io.fetchFault.bits.request.identity, + engine.io.fetchFault.bits.request.transactionId) + out.pc := engine.io.fetchFault.bits.request.pc + out.instruction := 0.U + out.lengthBytes := 0.U + mapPrediction( + out.prediction, + engine.io.fetchFault.bits.request.prediction, + engine.io.fetchFault.bits.request.identity, + engine.io.fetchFault.bits.request.transactionId) + out.fetchFault := true.B + out.fetchFaultCause := 1.U + } + + fetchBuffer.io.enq <> ingress + fetchBuffer.io.prune.valid := applyHit + fetchBuffer.io.prune.bits := io.recovery.apply.bits + + val traceValid = RegInit(false.B) + val tracePacket = RegInit(0.U.asTypeOf(new TracePacket(p))) + val traceCapacity = !traceValid || io.trace.ready + io.toCtu.valid := + fetchBuffer.io.deq.valid && !recoveryFence + io.toCtu.bits := fetchBuffer.io.deq.bits + fetchBuffer.io.deq.ready := + io.toCtu.ready && !recoveryFence + + io.trace.valid := traceValid + io.trace.bits := tracePacket + val traceFires = io.trace.fire + val packetFires = io.toCtu.fire + val traceCapture = packetFires && traceCapacity + when(traceFires && !traceCapture) { + traceValid := false.B + } + when(traceCapture) { + traceValid := true.B + tracePacket := 0.U.asTypeOf(tracePacket) + tracePacket.count := io.toCtu.bits.count + for (lane <- 0 until p.widths.fetchWidth) { + when(lane.U < io.toCtu.bits.count) { + tracePacket.entries(lane).source := TraceSource.Ifu + tracePacket.entries(lane).kind := TraceKind.Pipeline + tracePacket.entries(lane).instructionValid := true.B + tracePacket.entries(lane).instruction := + io.toCtu.bits.entries(lane).identity + tracePacket.entries(lane).pc := io.toCtu.bits.entries(lane).pc + tracePacket.entries(lane).payload := + io.toCtu.bits.entries(lane).lengthBytes + } + } + } + + when(prepareFire) { + assert(io.recovery.prepare.bits.phase === RecoveryPhase.Prepare) + } + when(io.recovery.apply.valid && recoveryPending) { + assert(applyMatches) + assert(preparedCompletes) + } + when(io.recovery.abort.valid && recoveryPending) { + assert(abortMatches) + assert(preparedCompletes) + } + when(ingress.fire) { + assert(ingress.bits.count =/= 0.U) + assert(ingress.bits.count <= ingressWidth.U) + } +} diff --git a/chisel/src/main/scala/linxcore/ifu/Prediction.scala b/chisel/src/main/scala/linxcore/ifu/Prediction.scala new file mode 100644 index 00000000..c7b7a285 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ifu/Prediction.scala @@ -0,0 +1,25 @@ +package linxcore.ifu + +import chisel3._ +import linxcore.frontend.BSideStage + +/** Side-effect-free prediction helpers for the public IFU package. */ +object Prediction { + val ProviderRankWidth = 3 + + /** Higher rank wins. Backend recovery is intentionally absent from this list. */ + def providerRank(stage: BSideStage.Type): UInt = + Mux( + stage === BSideStage.BF4, + 5.U(ProviderRankWidth.W), + Mux( + stage === BSideStage.BF3, + 4.U(ProviderRankWidth.W), + Mux( + stage === BSideStage.BF2, + 3.U(ProviderRankWidth.W), + Mux( + stage === BSideStage.BF1, + 2.U(ProviderRankWidth.W), + Mux(stage === BSideStage.BF0, 1.U(ProviderRankWidth.W), 0.U(ProviderRankWidth.W)))))) +} diff --git a/chisel/src/main/scala/linxcore/lsu/LSU.scala b/chisel/src/main/scala/linxcore/lsu/LSU.scala new file mode 100644 index 00000000..a10f9e9b --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/LSU.scala @@ -0,0 +1,1219 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{Cat, Fill, Mux1H, MuxLookup, PopCount, PriorityEncoder, + Queue, RRArbiter, UIntToOH, Valid, log2Ceil} +import linxcore.common.{CoreParams => ScalarCoreParams, DestinationKind, + ScalarLsuParams} +import linxcore.ooo._ +import linxcore.params.CoreParams +import linxcore.recovery.{ExecEngineType, FlushType} +import linxcore.top.interface.{LSUIO, OperandKind, RecoveryPhase, + MemoryAccessKind, MemoryCommand, RecoveryCause, RecoveryPlan, + RecoveryPlanContract, StoreMemoryClass, LSUMemoryFaultCause, + LSUMaintenanceCommand, MemorySize, StoreMemoryClassifyTxn} + +/** Public state-free composition boundary for the canonical LSU graph. + * + * Physical STQ/data rows belong to `OooIexStoreStqFabric`; committed-store + * attributes, CommitQ and SCB state belong to `STQSCBCommitBackend`; LIQ, + * MDB, L1D and load-return state belong to `ScalarLSULoadPath`. + */ +private final class LSUCanonicalOwner(val p: CoreParams) extends Module { + val io = IO(new LSUIO(p)) + private val profile = OooIexPhysicalProfile.fromCoreParams(p) + private val op = profile.params + private val scalarLsu = ScalarLsuParams.fromMainline(p) + private val scalarRobIdentityEntries = math.max( + op.robIdentityGroupsPerStid, 1 << (op.nativeBidWidth - 1)) + private val scalar = ScalarCoreParams( + robEntries = scalarRobIdentityEntries, + commitWidth = p.widths.retireWidth, + scalarLsu = scalarLsu, + lsidWidth = p.lsidWidth) + private val stqEntries = scalarLsu.stqEntries + + private val store = Module(new OooIexStoreStqFabric(p, stqEntries)) + io.storeResolve <> store.io.completion + private val backend = Module(new STQSCBCommitBackend( + entries = stqEntries, + queueEntries = scalarLsu.commitQueueEntries, + issueWidth = scalarLsu.commitIssueWidth, + scbEntries = scalarLsu.scbEntries, + scbResponseBufferDepth = scalarLsu.scbResponseBufferDepth, + addrWidth = scalarLsu.addrWidth, + dataWidth = scalarLsu.dataWidth, + peIdWidth = op.peIdWidth, + stidWidth = op.stidWidth, + tidWidth = op.stidWidth, + sizeWidth = scalarLsu.sizeWidth, + simtLaneWidth = scalarLsu.simtLaneWidth, + lineBytes = scalarLsu.lineBytes, + mapQDepth = op.tuMapQDepthPerStid, + robEntries = op.robIdentityGroupsPerStid, + lsidWidth = op.lsidWidth, + nativeBidWidth = op.nativeBidWidth, + ridGenerationWidth = op.ridGenerationWidth, + brobGenerationWidth = op.brobGenerationWidth, + memberIndexWidth = op.robMemberIndexWidth, + residentGenerationWidth = op.residentGenerationWidth, + leaseGenerationWidth = op.executeSlotGenerationWidth, + memoryTransactionIdWidth = p.memoryTransactionIdWidth, + memoryTransactionGenerationWidth = p.memoryTransactionGenerationWidth)) + private val load = Module(new ScalarLSULoadPath( + scalar, useExternalStqForwarding = true, + stqForwardRobEntries = op.robIdentityGroupsPerStid, + stqForwardTokenWidth = op.transactionIdWidth, + useExternalLaunchPermit = true)) + private val structuralBlock = Module(new LoadStructuralBlockPolicy( + robEntries = op.robIdentityGroupsPerStid, + liqEntries = scalarLsu.liqEntries, + stqEntries = stqEntries, + addrWidth = scalarLsu.addrWidth, + stidWidth = op.stidWidth, + pcWidth = scalarLsu.pcWidth, + lineBytes = scalarLsu.lineBytes, + lsidWidth = op.lsidWidth, + tokenWidth = op.transactionIdWidth)) + private val translation = Module(new DSideTranslation( + p = p, + entries = p.lsu.dTranslationEntries, + pageBytes = p.lsu.dTranslationPageBytes)) + private val lowerRecovery = Module(new LSULowerTransactionRecovery( + p = p, + lanes = p.lsu.loadPipes + p.lsu.storePipes, + entries = p.lsu.lowerMemoryTransactionsPerLane * + (p.lsu.loadPipes + p.lsu.storePipes))) + lowerRecovery.io.requestFire := 0.U.asTypeOf(lowerRecovery.io.requestFire) + lowerRecovery.io.requestIdentity := + 0.U.asTypeOf(lowerRecovery.io.requestIdentity) + lowerRecovery.io.responseFire := + 0.U.asTypeOf(lowerRecovery.io.responseFire) + lowerRecovery.io.responseIdentity := + 0.U.asTypeOf(lowerRecovery.io.responseIdentity) + lowerRecovery.io.prepareFire := false.B + lowerRecovery.io.applyFire := false.B + lowerRecovery.io.abortFire := false.B + translation.io.invalidate := false.B + + val faultValid = RegInit(false.B) + val faultBits = Reg(chiselTypeOf(io.memoryFault.bits)) + io.memoryFault.valid := faultValid + io.memoryFault.bits := faultBits + when(io.memoryFault.fire) { faultValid := false.B } + + val maintenancePending = RegInit(false.B) + val maintenanceCommand = Reg(LSUMaintenanceCommand()) + val maintenanceAddress = Reg(UInt(p.physicalAddressWidth.W)) + val maintenanceResultValid = RegInit(false.B) + val maintenanceResultSuccess = RegInit(false.B) + val protocolErrorSticky = RegInit(false.B) + io.maintenance.ready := !maintenancePending && !maintenanceResultValid && + !protocolErrorSticky + when(io.maintenance.fire) { + maintenancePending := true.B + maintenanceCommand := io.maintenance.bits.command + maintenanceAddress := io.maintenance.bits.address + } + io.maintenanceResult.valid := maintenanceResultValid + io.maintenanceResult.bits.command := maintenanceCommand + io.maintenanceResult.bits.address := maintenanceAddress + io.maintenanceResult.bits.success := maintenanceResultSuccess + when(io.maintenanceResult.fire) { maintenanceResultValid := false.B } + io.protocolError := protocolErrorSticky + val derivedStoreClassEmpty = Wire(Bool()) + val operationFenced = lowerRecovery.io.fenced || io.maintenance.valid || + maintenancePending || maintenanceResultValid || protocolErrorSticky + + private def projectMember(target: RobMemberKey, + source: linxcore.top.interface.RobIdentity): Unit = { + target := 0.U.asTypeOf(target) + target.group.valid := true.B + target.group.peId := source.peId + target.group.stid := source.stid + target.group.ridSlot := source.ridSlot + target.group.ridGeneration := source.ridGeneration + target.bid.valid := true.B + target.bid.value := source.bid + target.brobGeneration := source.brobGeneration + target.memberIndex := source.memberIndex + target.residentGeneration := source.residentGeneration + } + + private def projectCommonRow(target: OooIexIssueRow, + source: linxcore.top.interface.MemoryIdentity, + order: linxcore.top.interface.MemoryOrderMeta, + requestCount: UInt, pair: Bool, child: Int): Unit = { + target := 0.U.asTypeOf(target) + target.schedule.valid := true.B + target.schedule.peId := source.rob.peId + target.schedule.stid := source.rob.stid + target.schedule.transactionId := source.transaction.value + target.schedule.memoryTransactionValid := true.B + target.schedule.memoryTransaction.value := source.transaction.value + target.schedule.memoryTransaction.generation := source.transaction.generation + target.schedule.childIndex := child.U + projectMember(target.schedule.member, source.rob) + target.schedule.reservation.uopClass := + Mux(child.U === 0.U, OooUopClass.Agu, OooUopClass.Std) + target.payload.recipe.valid := true.B + target.payload.recipe.disposition := OooOpcodeDisposition.Dispatch.U + target.payload.recipe.sideEffectOwner := OooSideEffectOwner.Lsu.U + target.payload.recipe.recipeKind := Mux(pair, + OooOpcodeRecipeKind.PairStore.U, + OooOpcodeRecipeKind.ScalarStore.U) + target.payload.recipe.lateSplitKind := Mux(pair, + OooLateSplitKind.PairStoreAddressData.U, + OooLateSplitKind.StoreAddressData.U) + target.payload.memory.valid := true.B + target.payload.memory.isStore := true.B + target.payload.memory.isLoad := false.B + target.payload.memory.accessBytes := 0.U + target.payload.memoryOrder.valid := true.B + target.payload.memoryOrder.memoryValid := true.B + target.payload.memoryOrder.isStore := true.B + target.payload.memoryOrder.isLoad := false.B + target.payload.memoryOrder.requestCount := requestCount + target.payload.memoryOrder.firstLsid := order.firstLsid + target.payload.memoryOrder.firstTypeId := order.firstSid + target.payload.memoryOrder.before.youngestStoreLsidValid := order.yostValid + target.payload.memoryOrder.before.youngestStoreLsid := order.yostLsid + target.payload.memoryOrder.before.storeId := order.yostSid + 1.U + } + + private def makeExecute(source: linxcore.top.interface.MemoryIdentity, + order: linxcore.top.interface.MemoryOrderMeta, requestCount: UInt, + pair: Bool, address: UInt, sizeBytes: UInt, data: Vec[UInt], + child: Int, lane: Int): OooIexExecuteTransaction = { + val out = Wire(new OooIexExecuteTransaction(op)) + out := 0.U.asTypeOf(out) + projectCommonRow(out.i2.row, source, order, requestCount, pair, child) + out.ownerClass := Mux(child.U === 0.U, OooUopClass.Agu, OooUopClass.Std) + out.ownerLane := lane.U + out.slotGeneration := 0.U + out.i2.row.payload.memory.accessBytes := sizeBytes + out.i2.row.payload.memory.addressMode := OooMemoryAddressMode.BaseOffset + out.i2.row.payload.memory.indexMode := OooMemoryIndexMode.Identity + out.i2.row.payload.memory.addressSourceMask := 1.U + out.i2.row.payload.memory.dataSourceMask := + Mux(requestCount === 2.U, 3.U, 1.U) + out.i2.sourceMask := Mux(child.U === 0.U, + out.i2.row.payload.memory.addressSourceMask, + out.i2.row.payload.memory.dataSourceMask) + out.i2.sourceData := 0.U.asTypeOf(out.i2.sourceData) + out.i2.sourceData(0) := Mux(child.U === 0.U, address, data(0)) + if (op.maxSourceOperands > 1) { + out.i2.sourceData(1) := data(1) + } + out.i2.pcValid := false.B + out.i2.pc := 0.U + out + } + + for (lane <- io.iex.storeReservation.indices) { + val reservation = io.iex.storeReservation(lane) + val reservationIdentity = Wire( + new linxcore.top.interface.MemoryIdentity(p)) + reservationIdentity := 0.U.asTypeOf(reservationIdentity) + reservationIdentity.rob := reservation.bits.rob + reservationIdentity.transaction := reservation.bits.transaction + reservationIdentity.lsid := reservation.bits.memoryOrder.firstLsid + val reserveRow = Wire(new OooIexIssueRow(op)) + projectCommonRow(reserveRow, reservationIdentity, + reservation.bits.memoryOrder, reservation.bits.requestCount, + reservation.bits.pair, 0) + reserveRow.schedule.transactionId := reservation.bits.transactionId + reserveRow.payload.memory.accessBytes := reservation.bits.sizeBytes + store.io.reserve(lane).valid := reservation.valid && !operationFenced + store.io.reserve(lane).bits := reserveRow + reservation.ready := !operationFenced && store.io.reserve(lane).ready + } + + val storeTranslationSelected = Wire(Vec(p.lsu.storePipes, Bool())) + val storeTranslationReady = Wire(Bool()) + val storeTranslationFault = Wire(Bool()) + val storeTranslationTxn = Wire(chiselTypeOf(io.iex.storeAddress.head.bits)) + val storeTranslationCacheable = Wire(Bool()) + val storeTranslationDevice = Wire(Bool()) + val storeAddressInputReady = Wire(Vec(p.lsu.storePipes, Bool())) + val faultSlotReady = !faultValid || io.memoryFault.ready + val storeTranslatedAddress = Wire(UInt(p.physicalAddressWidth.W)) + for (lane <- 0 until p.lsu.storePipes) { + val address = io.iex.storeAddress(lane) + val zeroData = Wire(Vec(p.maxMemoryRequestsPerInstruction, + UInt(p.dataWidth.W))) + zeroData := 0.U.asTypeOf(zeroData) + store.io.storeAddress(lane).valid := + storeTranslationSelected(lane) && storeTranslationReady && + !storeTranslationFault + store.io.storeAddress(lane).bits := makeExecute( + storeTranslationTxn.identity, storeTranslationTxn.memoryOrder, + storeTranslationTxn.requestCount, storeTranslationTxn.pair, + storeTranslatedAddress, storeTranslationTxn.sizeBytes, zeroData, 0, lane) + address.ready := storeAddressInputReady(lane) + + val data = io.iex.storeData(lane) + store.io.storeData(lane).valid := data.valid + store.io.storeData(lane).bits := makeExecute( + data.bits.identity, data.bits.memoryOrder, + data.bits.requestCount, data.bits.pair, 0.U, + data.bits.sizeBytes, data.bits.data, 1, lane) + data.ready := store.io.storeData(lane).ready + } + + private val loadRecoveryBoundaryMatch = VecInit(load.io.liqRows.map { row => + val firstKilled = io.recovery.prepare.bits.firstKilled + row.valid && row.loadLsIdFullValid && row.attempt.valid && + row.attempt.producer.valid && row.attempt.producer.nativeBidValid && + row.attempt.producer.peId === firstKilled.peId && + row.attempt.producer.stid === firstKilled.stid && + row.attempt.producer.nativeBid === firstKilled.bid && + row.attempt.producer.brobGeneration === firstKilled.brobGeneration && + row.attempt.producer.ridSlot === firstKilled.ridSlot && + row.attempt.producer.ridGeneration === firstKilled.ridGeneration && + row.attempt.producer.memberIndex === firstKilled.memberIndex && + row.attempt.producer.residentGeneration === + firstKilled.residentGeneration + }) + private val loadRecoveryBoundaryExact = + !io.recovery.prepare.bits.firstKilledValid || + PopCount(loadRecoveryBoundaryMatch) === 1.U + private val selectedLoadRecoveryLsId = Mux1H( + loadRecoveryBoundaryMatch, load.io.liqRows.map(_.loadLsIdFull)) + + // Recovery preparation is one common store/load transaction. A killed + // boundary that cannot be resolved to exactly one authoritative LIQ full + // LSID fails closed: neither sub-owner mutates nor publishes prepared. + store.io.recovery.prepare.valid := + io.recovery.prepare.valid && loadRecoveryBoundaryExact + store.io.recovery.prepare.bits := io.recovery.prepare.bits + io.recovery.prepare.ready := + store.io.recovery.prepare.ready && loadRecoveryBoundaryExact + private val lowerDrainQuiescent = lowerRecovery.io.quiescent && + translation.io.quiescent && load.io.transientEmpty && backend.io.empty && + derivedStoreClassEmpty + io.recovery.prepared.valid := store.io.recovery.prepared.valid && + lowerDrainQuiescent + io.recovery.prepared.bits := store.io.recovery.prepared.bits + store.io.recovery.prepared.ready := io.recovery.prepared.ready && + lowerDrainQuiescent + store.io.recovery.apply := io.recovery.apply + store.io.recovery.abort := io.recovery.abort + private val loadRecoveryPending = RegInit(false.B) + private val loadRecoveryPlan = Reg(new RecoveryPlan(p)) + private val loadRecoveryLsIdFull = Reg(UInt(p.lsidWidth.W)) + when(io.recovery.prepare.fire) { + loadRecoveryPending := true.B + loadRecoveryPlan := io.recovery.prepare.bits + loadRecoveryLsIdFull := selectedLoadRecoveryLsId + } + private val loadRecoveryApply = loadRecoveryPending && + io.recovery.apply.valid && io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, loadRecoveryPlan) + private val loadRecoveryAbort = loadRecoveryPending && + io.recovery.abort.valid && io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, loadRecoveryPlan) + when(loadRecoveryApply || loadRecoveryAbort) { + loadRecoveryPending := false.B + } + lowerRecovery.io.prepareFire := io.recovery.prepare.fire + lowerRecovery.io.applyFire := loadRecoveryApply + lowerRecovery.io.abortFire := loadRecoveryAbort + store.io.loadCancel := 0.U.asTypeOf(store.io.loadCancel) + store.io.lateStaPermit := load.mdbStore.probeReady + load.mdbStore.probe := store.io.lateStaCandidate.bits + load.mdbStore.probe.valid := store.io.lateStaCandidate.valid + load.mdbStore.probeCommit := store.io.lateStaProbe.valid + + backend.io.rows := store.io.rows + backend.io.recoveryActive := !store.io.recovery.prepare.ready + store.io.markCommitValid := backend.io.markCommitValid + store.io.markCommitIndex := backend.io.markCommitIndex + backend.io.markCommitAccepted := store.io.markCommitAccepted + store.io.commitFreeMaskValid := backend.io.commitFreeMaskValid + store.io.commitFreeMask := backend.io.commitFreeMask + backend.io.commitFreeAcceptedMask := store.io.commitFreeAcceptedMask + + private def projectExactOwner(target: STQExactOwner, + source: linxcore.top.interface.RobIdentity): Unit = { + target.valid := true.B + target.peId := source.peId + target.stid := source.stid + target.nativeBidValid := true.B + target.nativeBid := source.bid + target.brobGeneration := source.brobGeneration + target.ridSlot := source.ridSlot + target.ridGeneration := source.ridGeneration + target.memberIndex := source.memberIndex + target.residentGeneration := source.residentGeneration + } + + backend.io.robStoreCommit.valid := io.storeCommit.valid + backend.io.robStoreCommit.bits := 0.U.asTypeOf(backend.io.robStoreCommit.bits) + backend.io.robStoreCommit.bits.logicalFirstLsid := + io.storeCommit.bits.logicalFirstLsid + backend.io.robStoreCommit.bits.logicalFirstStoreId := + io.storeCommit.bits.logicalFirstStoreId + backend.io.robStoreCommit.bits.logicalRequestCount := + io.storeCommit.bits.requestCount + backend.io.robStoreCommit.bits.logicalBeat := io.storeCommit.bits.beat + backend.io.robStoreCommit.bits.transactionValue := + io.storeCommit.bits.transaction.value + backend.io.robStoreCommit.bits.transactionGeneration := + io.storeCommit.bits.transaction.generation + projectExactOwner(backend.io.robStoreCommit.bits.exactOwner, + io.storeCommit.bits.rob) + io.storeCommit.ready := backend.io.robStoreCommit.ready + + val classifyMatches = Wire(Vec(stqEntries, Bool())) + val derivedStoreClass = Module(new Queue( + new StoreMemoryClassifyTxn(p), stqEntries, flow = false, + pipe = false)) + derivedStoreClassEmpty := derivedStoreClass.io.count === 0.U + val derivedStoreAddress = storeTranslationTxn + derivedStoreClass.io.enq.valid := !storeTranslationFault && + VecInit(store.io.storeAddress.map(_.fire)).asUInt.orR + derivedStoreClass.io.enq.bits := 0.U.asTypeOf( + derivedStoreClass.io.enq.bits) + derivedStoreClass.io.enq.bits.rob := derivedStoreAddress.identity.rob + derivedStoreClass.io.enq.bits.transaction := + derivedStoreAddress.identity.transaction + derivedStoreClass.io.enq.bits.logicalFirstLsid := + derivedStoreAddress.memoryOrder.firstLsid + derivedStoreClass.io.enq.bits.logicalFirstStoreId := + derivedStoreAddress.memoryOrder.firstSid + derivedStoreClass.io.enq.bits.requestCount := + derivedStoreAddress.requestCount + derivedStoreClass.io.enq.bits.memoryClass := Mux(storeTranslationDevice, + StoreMemoryClass.Device, Mux(storeTranslationCacheable, + StoreMemoryClass.NormalCacheable, + StoreMemoryClass.NormalNonCacheable)) + when(derivedStoreClass.io.enq.valid) { + assert(derivedStoreClass.io.enq.ready, + "accepted store translations must retain their derived memory class") + } + for (index <- 0 until stqEntries) { + val row = store.io.rows(index) + val source = derivedStoreClass.io.deq.bits + classifyMatches(index) := row.valid && row.exactOwner.valid && + row.exactOwner.peId === source.rob.peId && + row.exactOwner.stid === source.rob.stid && + row.exactOwner.nativeBid === source.rob.bid && + row.exactOwner.brobGeneration === source.rob.brobGeneration && + row.exactOwner.ridSlot === source.rob.ridSlot && + row.exactOwner.ridGeneration === source.rob.ridGeneration && + row.exactOwner.memberIndex === source.rob.memberIndex && + row.exactOwner.residentGeneration === source.rob.residentGeneration && + row.logicalFirstLsid === source.logicalFirstLsid && + row.logicalFirstStoreId === source.logicalFirstStoreId && + row.logicalRequestCount === source.requestCount && + row.logicalBeat === source.beat + } + val classifyUnique = PopCount(classifyMatches) === 1.U + val classifyIndex = PriorityEncoder(classifyMatches) + backend.io.memoryClassify.valid := derivedStoreClass.io.deq.valid && + classifyUnique + backend.io.memoryClassify.bits := 0.U.asTypeOf(backend.io.memoryClassify.bits) + backend.io.memoryClassify.bits.lease.valid := classifyUnique + backend.io.memoryClassify.bits.lease.index := classifyIndex + backend.io.memoryClassify.bits.lease.generation := + store.io.rows(classifyIndex).leaseGeneration + projectExactOwner(backend.io.memoryClassify.bits.exactOwner, + derivedStoreClass.io.deq.bits.rob) + backend.io.memoryClassify.bits.logicalBeat := + derivedStoreClass.io.deq.bits.beat + backend.io.memoryClassify.bits.memoryClass := MuxLookup( + derivedStoreClass.io.deq.bits.memoryClass.asUInt, + STQMemoryClass.Fault)(Seq( + StoreMemoryClass.NormalCacheable.asUInt -> STQMemoryClass.NormalCacheable, + StoreMemoryClass.NormalNonCacheable.asUInt -> STQMemoryClass.NormalNonCacheable, + StoreMemoryClass.Device.asUInt -> STQMemoryClass.DeviceMmio, + StoreMemoryClass.Fault.asUInt -> STQMemoryClass.Fault)) + derivedStoreClass.io.deq.ready := classifyUnique && + backend.io.memoryClassify.ready + + // Canonical committed-store transport occupies the store lanes immediately + // after the load lanes: serialized writes first, cache ownership second. + backend.io.issueEnable := true.B + backend.io.evictEnable := true.B + backend.io.dcacheReady := load.scbCache.ready + backend.io.dcacheTagHit := load.scbCache.tagHit + backend.io.dcacheWriteHit := load.scbCache.writeHit + val serializedMemory = io.memoryRequest(p.lsu.loadPipes) + serializedMemory.valid := backend.io.serializedRequest.valid + serializedMemory.bits := 0.U.asTypeOf(serializedMemory.bits) + serializedMemory.bits.identity.value := + backend.io.serializedRequest.bits.transactionId + serializedMemory.bits.identity.generation := + backend.io.serializedRequest.bits.transactionGeneration + serializedMemory.bits.command := MemoryCommand.Write + serializedMemory.bits.accessKind := Mux( + backend.io.serializedRequest.bits.memoryClass === STQMemoryClass.DeviceMmio, + MemoryAccessKind.Device, MemoryAccessKind.Data) + serializedMemory.bits.address := backend.io.serializedRequest.bits.fragment.addr + serializedMemory.bits.data := backend.io.serializedRequest.bits.fragment.data + serializedMemory.bits.size := MemorySize.fromBytes( + backend.io.serializedRequest.bits.fragment.size) + private val publicDataBytes = p.dataWidth / 8 + private val serializedByteOffsetWidth = log2Ceil(publicDataBytes) + private val serializedByteCount = + (1.U((publicDataBytes + 1).W) << + backend.io.serializedRequest.bits.fragment.size) - 1.U + serializedMemory.bits.byteMask := + (serializedByteCount << + backend.io.serializedRequest.bits.fragment.addr( + serializedByteOffsetWidth - 1, 0))(publicDataBytes - 1, 0) + backend.io.serializedRequest.ready := serializedMemory.ready + + val ownershipMemory = io.memoryRequest(p.lsu.loadPipes + 1) + ownershipMemory.valid := backend.io.l2Request.valid + ownershipMemory.bits := 0.U.asTypeOf(ownershipMemory.bits) + ownershipMemory.bits.identity.value := + backend.io.l2Request.transactionValue + ownershipMemory.bits.identity.generation := + backend.io.l2Request.transactionGeneration + ownershipMemory.bits.command := MemoryCommand.AcquireWrite + ownershipMemory.bits.accessKind := MemoryAccessKind.Data + ownershipMemory.bits.address := backend.io.l2Request.lineAddr + ownershipMemory.bits.size := MemorySize.fromBytes(backend.io.l2Request.size) + backend.io.l2RequestReady := ownershipMemory.ready + + val serializedResponse = io.memoryResponse(p.lsu.loadPipes) + backend.io.serializedResponse.valid := serializedResponse.valid + backend.io.serializedResponse.bits.transactionId := + serializedResponse.bits.identity.value + backend.io.serializedResponse.bits.transactionGeneration := + serializedResponse.bits.identity.generation + backend.io.serializedResponse.bits.error := serializedResponse.bits.denied || + serializedResponse.bits.corrupt + serializedResponse.ready := backend.io.serializedResponse.ready + + val ownershipResponse = io.memoryResponse(p.lsu.loadPipes + 1) + backend.io.rawRespValid := ownershipResponse.valid + backend.io.rawRespTxnId := ownershipResponse.bits.identity.value + backend.io.rawRespTransactionValue := + ownershipResponse.bits.identity.value + backend.io.rawRespTransactionGeneration := + ownershipResponse.bits.identity.generation + backend.io.rawRespError := ownershipResponse.bits.denied || + ownershipResponse.bits.corrupt + backend.io.rawRespWrite := true.B + backend.io.rawRespUpgrade := false.B + ownershipResponse.ready := backend.io.rawRespReady + load.scbCache.lookupValid := backend.io.dcacheLookupValid + load.scbCache.lookupLineAddr := backend.io.dcacheLookupLineAddr + load.scbCache.update := backend.io.dcacheUpdate + load.scbCache.grantWriteValid := backend.io.rawRespSucceeded + load.scbCache.grantWriteLineAddr := backend.io.rawRespLineAddr + load.scbCache.grantWriteData := ownershipResponse.bits.lineData + + // Every load-owner input is assigned explicitly below. No unknown value may + // enter the canonical LIQ/MDB/cache graph through the public LSU boundary. + load.launchPermit.get := !operationFenced + load.stqForward.get.queries <> store.io.loadForwardQuery + load.stqForward.get.responses <> store.io.loadForwardResponse + structuralBlock.io.hardBlock <> load.stqForward.get.hardBlock + structuralBlock.io.hardFlush := false.B + structuralBlock.io.recoveryFire := loadRecoveryApply + private val structuralRecoveryMatches = VecInit( + load.io.liqRows.zipWithIndex.map { case (row, index) => + row.valid && structuralBlock.io.loadId.valid && + LoadCanonicalRowIdentity.equal( + structuralBlock.io.loadId, + LoadCanonicalRowIdentity.fromRobId(row.loadId)) && + load.io.liqFlushPruneMask(index) + }) + structuralBlock.io.recoveryKill := structuralRecoveryMatches.asUInt.orR + for (index <- 0 until stqEntries) { + load.mdbStore.rows(index) := 0.U.asTypeOf(load.mdbStore.rows(index)) + load.mdbStore.rows(index).valid := store.io.rows(index).valid + load.mdbStore.rows(index).storeIndex := index.U + load.mdbStore.rows(index).pc := store.io.rows(index).pc + load.mdbStore.rows(index).bid := store.io.rows(index).bid + load.mdbStore.rows(index).lsId := store.io.rows(index).lsId + load.mdbStore.rows(index).stid := store.io.rows(index).stid + load.mdbStore.rows(index).addr := store.io.rows(index).addr + load.mdbStore.rows(index).size := store.io.rows(index).size + load.mdbStore.rows(index).addrReady := store.io.rows(index).addrReady + load.mdbStore.rows(index).dataReady := store.io.rows(index).dataReady + load.mdbStore.rows(index).isTile := !store.io.rows(index).scalarIex + } + + private def projectRobId(target: linxcore.rob.ROBID, value: UInt, + valid: Bool = true.B): Unit = { + val width = log2Ceil(target.entries) + target.valid := valid + target.value := value.pad(width)(width - 1, 0) + target.wrap := value.pad(width + 1)(width) + } + + val loadIssueArbiter = Module(new RRArbiter( + chiselTypeOf(io.iex.loadAddress.head.bits), p.lsu.loadPipes)) + for (lane <- 0 until p.lsu.loadPipes) { + loadIssueArbiter.io.in(lane).valid := io.iex.loadAddress(lane).valid + loadIssueArbiter.io.in(lane).bits := io.iex.loadAddress(lane).bits + io.iex.loadAddress(lane).ready := loadIssueArbiter.io.in(lane).ready + } + val incomingLoad = loadIssueArbiter.io.out + val storeTranslationCandidates = VecInit( + io.iex.storeAddress.map(_.valid)) + val storeTranslationIndex = PriorityEncoder(storeTranslationCandidates) + val storeTranslationRequest = storeTranslationCandidates.asUInt.orR + val loadTranslationSelected = incomingLoad.valid + for (lane <- 0 until p.lsu.storePipes) { + storeAddressInputReady(lane) := !operationFenced && + !loadTranslationSelected && storeTranslationIndex === lane.U && + translation.io.lookup.ready + } + val selectedStoreAddress = io.iex.storeAddress(storeTranslationIndex) + translation.io.lookup.valid := !operationFenced && + (incomingLoad.valid || storeTranslationRequest) + translation.io.lookup.bits := 0.U.asTypeOf(translation.io.lookup.bits) + translation.io.lookup.bits.isStore := !loadTranslationSelected + translation.io.lookup.bits.load := incomingLoad.bits + translation.io.lookup.bits.store := selectedStoreAddress.bits + incomingLoad.ready := !operationFenced && loadTranslationSelected && + translation.io.lookup.ready + + val translated = translation.io.result + val translatedLoad = translated.valid && !translated.bits.request.isStore + val translatedStore = translated.valid && translated.bits.request.isStore + val loadIssue = Wire(Valid(chiselTypeOf(io.iex.loadAddress.head.bits))) + loadIssue.valid := translatedLoad + loadIssue.bits := translated.bits.request.load + val translatedStoreLane = translated.bits.request.store.identity.pipeId + for (lane <- 0 until p.lsu.storePipes) { + storeTranslationSelected(lane) := translated.valid && + translated.bits.request.isStore && translatedStoreLane === lane.U + } + storeTranslationTxn := translated.bits.request.store + storeTranslationReady := translated.valid + storeTranslationFault := translated.bits.alignmentFault || + translated.bits.accessFault + storeTranslatedAddress := translated.bits.physicalAddress + storeTranslationCacheable := translated.bits.cacheable + storeTranslationDevice := translated.bits.device + val translatedLoadFault = translatedLoad && storeTranslationFault + val translatedStoreFault = translatedStore && storeTranslationFault + val translatedStoreReady = Mux1H(storeTranslationSelected, + store.io.storeAddress.map(_.ready)) + translated.ready := Mux(storeTranslationFault, faultSlotReady, + Mux(translated.bits.request.isStore, translatedStoreReady, + load.io.allocReady)) + + load.io.allocValid := translatedLoad && !storeTranslationFault + load.io.alloc := 0.U.asTypeOf(load.io.alloc) + projectRobId(load.io.alloc.bid, loadIssue.bits.identity.rob.bid) + projectRobId(load.io.alloc.gid, loadIssue.bits.identity.rob.ridSlot) + projectRobId(load.io.alloc.rid, loadIssue.bits.identity.rob.ridSlot) + projectRobId(load.io.alloc.loadLsId, loadIssue.bits.identity.lsid) + load.io.alloc.loadLsIdFullValid := true.B + load.io.alloc.loadLsIdFull := loadIssue.bits.identity.lsid + load.io.alloc.attempt.valid := true.B + load.io.alloc.attempt.producer.valid := true.B + load.io.alloc.attempt.producer.peId := loadIssue.bits.identity.rob.peId + load.io.alloc.attempt.producer.stid := loadIssue.bits.identity.rob.stid + load.io.alloc.attempt.producer.nativeBidValid := true.B + load.io.alloc.attempt.producer.nativeBid := loadIssue.bits.identity.rob.bid + load.io.alloc.attempt.producer.brobGeneration := + loadIssue.bits.identity.rob.brobGeneration + load.io.alloc.attempt.producer.ridSlot := loadIssue.bits.identity.rob.ridSlot + load.io.alloc.attempt.producer.ridGeneration := + loadIssue.bits.identity.rob.ridGeneration + load.io.alloc.attempt.producer.memberIndex := + loadIssue.bits.identity.rob.memberIndex + load.io.alloc.attempt.producer.residentGeneration := + loadIssue.bits.identity.rob.residentGeneration + load.io.alloc.attempt.transactionValue := + loadIssue.bits.identity.transaction.value + load.io.alloc.attempt.transactionGeneration := + loadIssue.bits.identity.transaction.generation + load.io.alloc.attempt.generation := + loadIssue.bits.identity.attemptGeneration + load.io.alloc.peId := loadIssue.bits.identity.rob.peId + load.io.alloc.stid := loadIssue.bits.identity.rob.stid + load.io.alloc.tid := loadIssue.bits.identity.rob.stid + load.io.alloc.pc := loadIssue.bits.pc + load.io.alloc.addr := translated.bits.physicalAddress + load.io.alloc.size := loadIssue.bits.sizeBytes + load.io.alloc.returnSignExtend := loadIssue.bits.signed + load.io.alloc.dst.valid := loadIssue.bits.destination.valid + load.io.alloc.dst.kind := Mux( + loadIssue.bits.destination.kind === OperandKind.Gpr, + DestinationKind.Gpr, + Mux(loadIssue.bits.destination.kind === OperandKind.T, + DestinationKind.T, DestinationKind.U)) + load.io.alloc.dst.archTag := loadIssue.bits.destination.atag + load.io.alloc.dst.relTag := loadIssue.bits.destinationRelativeIndex + load.io.alloc.dst.physTag := Mux( + loadIssue.bits.destination.kind === OperandKind.Gpr, + loadIssue.bits.destination.ptag, + Mux(loadIssue.bits.destination.kind === OperandKind.T, + loadIssue.bits.destination.ttag, loadIssue.bits.destination.utag)) + load.io.alloc.dst.oldPhysTag := Mux( + loadIssue.bits.destination.kind === OperandKind.Gpr, + loadIssue.bits.destination.previousPtag, + 0.U) + projectRobId(load.io.alloc.youngestStoreId, + loadIssue.bits.youngestStoreId, loadIssue.bits.youngestStoreValid) + projectRobId(load.io.alloc.youngestStoreLsId, + loadIssue.bits.youngestStoreLsid, loadIssue.bits.youngestStoreValid) + load.io.alloc.youngestStoreLsIdFullValid := + loadIssue.bits.youngestStoreValid + load.io.alloc.youngestStoreLsIdFull := loadIssue.bits.youngestStoreLsid + load.io.alloc.returnPipeIndex := loadIssue.bits.identity.pipeId + io.iex.loadAllocation.foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + for (lane <- 0 until p.lsu.loadPipes) { + val allocation = io.iex.loadAllocation(lane) + allocation.valid := translatedLoad && !storeTranslationFault && + translated.ready && loadIssue.bits.identity.pipeId === lane.U + allocation.bits.identity := loadIssue.bits.identity + allocation.bits.allocationId.value := load.io.allocLoadId.value + allocation.bits.allocationId.generation := + load.io.allocLoadId.wrap.asUInt + } + + val loadFaultFire = translated.fire && translatedLoadFault + val storeFaultFire = translated.fire && translatedStoreFault + when(loadFaultFire || storeFaultFire) { + faultValid := true.B + faultBits := 0.U.asTypeOf(faultBits) + faultBits.identity := Mux(loadFaultFire, loadIssue.bits.identity, + translated.bits.request.store.identity) + faultBits.address := Mux(loadFaultFire, loadIssue.bits.address, + translated.bits.request.store.address) + faultBits.write := storeFaultFire + faultBits.cause := Mux(translated.bits.alignmentFault, + LSUMemoryFaultCause.Alignment, LSUMemoryFaultCause.Access) + } + + val launchIndex = PriorityEncoder(load.io.liqWaitMask) + val launchRow = load.io.liqRows(launchIndex) + private val lineOffsetWidth = log2Ceil(scalarLsu.lineBytes) + val launchLineAddress = Cat( + launchRow.addr(p.physicalAddressWidth - 1, lineOffsetWidth), + 0.U(lineOffsetWidth.W)) + val scbSnapshot = Module(new SCBLoadSnapshotLookup( + scalarLsu.scbEntries, p.physicalAddressWidth, scalarLsu.lineBytes)) + scbSnapshot.io.rows := backend.io.scbRows + scbSnapshot.io.lineAddress := launchLineAddress + load.stqForward.get.scb.returned := scbSnapshot.io.returned + load.stqForward.get.scb.validMask := scbSnapshot.io.validMask + load.stqForward.get.scb.data := scbSnapshot.io.data + assert(!scbSnapshot.io.ambiguous, + "one load line may match at most one canonical SCB row") + load.io.launchValid := load.io.liqWaitMask.orR + load.io.launchIndex := launchIndex + io.iex.loadLaunch.foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + for (lane <- 0 until p.lsu.loadPipes) { + val launch = io.iex.loadLaunch(lane) + launch.valid := load.io.launchAccepted && launchRow.returnPipeIndex === lane.U + launch.bits.identity.rob.peId := launchRow.peId + launch.bits.identity.rob.stid := launchRow.stid + launch.bits.identity.rob.ridSlot := launchRow.attempt.producer.ridSlot + launch.bits.identity.rob.ridGeneration := + launchRow.attempt.producer.ridGeneration + launch.bits.identity.rob.memberIndex := + launchRow.attempt.producer.memberIndex + launch.bits.identity.rob.residentGeneration := + launchRow.attempt.producer.residentGeneration + launch.bits.identity.rob.bid := launchRow.attempt.producer.nativeBid + launch.bits.identity.rob.brobGeneration := + launchRow.attempt.producer.brobGeneration + launch.bits.identity.lsid := launchRow.loadLsIdFull + launch.bits.identity.transaction.value := + launchRow.attempt.transactionValue + launch.bits.identity.transaction.generation := + launchRow.attempt.transactionGeneration + launch.bits.identity.attemptGeneration := launchRow.attempt.generation + launch.bits.identity.pipeId := launchRow.returnPipeIndex + launch.bits.allocationId.value := launchRow.loadId.value + launch.bits.allocationId.generation := launchRow.loadId.wrap.asUInt + } + + io.iex.loadResult.foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + val completion = load.io.loadReturn.completion + val completionLane = completion.payload.pipeIndex + for (lane <- 0 until p.lsu.loadPipes) { + val result = io.iex.loadResult(lane) + result.valid := load.io.loadReturn.completionCandidateValid && + completionLane === lane.U + result.bits.identity.rob.peId := completion.peId + result.bits.identity.rob.stid := completion.stid + result.bits.identity.rob.ridSlot := + completion.payload.attempt.producer.ridSlot + result.bits.identity.rob.ridGeneration := + completion.payload.attempt.producer.ridGeneration + result.bits.identity.rob.memberIndex := + completion.payload.attempt.producer.memberIndex + result.bits.identity.rob.residentGeneration := + completion.payload.attempt.producer.residentGeneration + result.bits.identity.rob.bid := completion.payload.attempt.producer.nativeBid + result.bits.identity.rob.brobGeneration := + completion.payload.attempt.producer.brobGeneration + result.bits.identity.lsid := completion.payload.loadLsIdFull + result.bits.identity.transaction.value := + completion.payload.attempt.transactionValue + result.bits.identity.transaction.generation := + completion.payload.attempt.transactionGeneration + result.bits.identity.attemptGeneration := completion.payload.attempt.generation + result.bits.identity.pipeId := completion.payload.pipeIndex + result.bits.allocationId.value := completion.payload.loadId.slot + result.bits.allocationId.generation := completion.payload.loadId.generation + result.bits.data := completion.payload.data + result.bits.destination.valid := completion.payload.dst.valid + result.bits.destination.kind := Mux( + completion.payload.dst.kind === DestinationKind.Gpr, + OperandKind.Gpr, + Mux(completion.payload.dst.kind === DestinationKind.T, + OperandKind.T, OperandKind.U)) + result.bits.destination.atag := completion.payload.dst.archTag + result.bits.destination.ptag := Mux( + completion.payload.dst.kind === DestinationKind.Gpr, + completion.payload.dst.physTag, 0.U) + result.bits.destination.previousPtag := Mux( + completion.payload.dst.kind === DestinationKind.Gpr, + completion.payload.dst.oldPhysTag, 0.U) + result.bits.destination.previousPtagValid := completion.payload.dst.valid && + completion.payload.dst.kind === DestinationKind.Gpr + result.bits.destination.ptagValid := completion.payload.dst.valid && + completion.payload.dst.kind === DestinationKind.Gpr + result.bits.destination.ttag := Mux( + completion.payload.dst.kind === DestinationKind.T, + completion.payload.dst.physTag, 0.U) + result.bits.destination.ttagValid := completion.payload.dst.valid && + completion.payload.dst.kind === DestinationKind.T + result.bits.destination.utag := Mux( + completion.payload.dst.kind === DestinationKind.U, + completion.payload.dst.physTag, 0.U) + result.bits.destination.utagValid := completion.payload.dst.valid && + completion.payload.dst.kind === DestinationKind.U + result.bits.destinationRelativeIndex := completion.payload.dst.relTag + result.bits.trap.valid := completion.payload.faultValid + result.bits.trap.cause := completion.payload.faultCause + } + val completionReady = Mux1H( + UIntToOH(completionLane, p.lsu.loadPipes), + io.iex.loadResult.map(_.ready)) + load.io.loadReturn.robRowValid := true.B + load.io.loadReturn.robRowNeedFlush := false.B + load.io.loadReturn.resolveReady := completionReady + load.io.loadReturn.writebackReady := completionReady + load.io.loadReturn.wakeupReady := completionReady + + load.io.flush := false.B + load.io.preciseFlush := 0.U.asTypeOf(load.io.preciseFlush) + when(loadRecoveryApply && loadRecoveryPlan.firstKilledValid) { + load.io.preciseFlush.req.valid := true.B + load.io.preciseFlush.req.typ := FlushType.NukeFlush + load.io.preciseFlush.req.peId := loadRecoveryPlan.firstKilled.peId + load.io.preciseFlush.req.stid := loadRecoveryPlan.firstKilled.stid + load.io.preciseFlush.req.tid := loadRecoveryPlan.firstKilled.stid + projectRobId(load.io.preciseFlush.req.bid, + loadRecoveryPlan.firstKilled.bid) + projectRobId(load.io.preciseFlush.req.gid, + loadRecoveryPlan.firstKilled.ridSlot) + projectRobId(load.io.preciseFlush.req.rid, + loadRecoveryPlan.firstKilled.ridSlot) + projectRobId(load.io.preciseFlush.req.lsId, loadRecoveryLsIdFull) + load.io.preciseFlush.req.lsIdFullValid := true.B + load.io.preciseFlush.req.lsIdFull := loadRecoveryLsIdFull + load.io.preciseFlush.req.execEngine := ExecEngineType.Mem + load.io.preciseFlush.req.fetchTpcValid := false.B + load.io.preciseFlush.req.fetchTpc := loadRecoveryPlan.redirectPc + load.io.preciseFlush.req.immediateFlush := false.B + load.io.preciseFlush.baseOnBid := false.B + load.io.preciseFlush.baseOnGroup := true.B + load.io.preciseFlush.baseOnPE := true.B + load.io.preciseFlush.baseOnThread := true.B + } + val reissueRequest = io.loadReissueRequest + val reissueMatches = Wire(Vec(scalarLsu.liqEntries, Bool())) + for (index <- 0 until scalarLsu.liqEntries) { + val row = load.io.liqRows(index) + val current = reissueRequest.bits.currentIdentity + reissueMatches(index) := row.valid && row.loadId.valid && + row.loadId.value === reissueRequest.bits.allocationId.value && + row.loadId.wrap.asUInt === reissueRequest.bits.allocationId.generation && + row.attempt.valid && row.attempt.producer.valid && + row.attempt.producer.peId === current.rob.peId && + row.attempt.producer.stid === current.rob.stid && + row.attempt.producer.nativeBid === current.rob.bid && + row.attempt.producer.brobGeneration === current.rob.brobGeneration && + row.attempt.producer.ridSlot === current.rob.ridSlot && + row.attempt.producer.ridGeneration === current.rob.ridGeneration && + row.attempt.producer.memberIndex === current.rob.memberIndex && + row.attempt.producer.residentGeneration === current.rob.residentGeneration && + row.attempt.transactionValue === current.transaction.value && + row.attempt.transactionGeneration === current.transaction.generation && + row.attempt.generation === current.attemptGeneration && + row.loadLsIdFull === current.lsid && + row.returnPipeIndex === current.pipeId + } + val reissueUnique = PopCount(reissueMatches) === 1.U + val reissueRow = load.io.liqRows(PriorityEncoder(reissueMatches)) + val nextIdentity = Wire(chiselTypeOf(reissueRequest.bits.currentIdentity)) + nextIdentity := reissueRequest.bits.currentIdentity + nextIdentity.attemptGeneration := + reissueRequest.bits.currentIdentity.attemptGeneration + 1.U + val reissueLaneReady = Wire(Vec(p.lsu.loadPipes, Bool())) + for (lane <- 0 until p.lsu.loadPipes) { + val notice = io.iex.loadReissue(lane) + notice.valid := reissueRequest.valid && reissueUnique && + reissueRow.returnPipeIndex === lane.U + notice.bits := 0.U.asTypeOf(notice.bits) + notice.bits.allocationId := reissueRequest.bits.allocationId + notice.bits.currentIdentity := reissueRequest.bits.currentIdentity + notice.bits.nextIdentity := nextIdentity + notice.bits.address := reissueRequest.bits.address + reissueLaneReady(lane) := notice.ready && + reissueRow.returnPipeIndex === lane.U + } + // A malformed, stale, or future replay request is a permanent protocol + // rejection, not backpressure. Consume it without publishing a transition. + reissueRequest.ready := Mux( + reissueUnique, reissueLaneReady.asUInt.orR, reissueRequest.valid) + + val rebindArbiter = Module(new RRArbiter( + chiselTypeOf(io.iex.loadRebindApply.head.bits), p.lsu.loadPipes)) + for (lane <- 0 until p.lsu.loadPipes) { + rebindArbiter.io.in(lane) <> io.iex.loadRebindApply(lane) + } + val rebindApply = rebindArbiter.io.out + val selectedCancelReady = Mux1H( + UIntToOH(rebindArbiter.io.chosen, p.lsu.loadPipes), + io.iex.loadCancel.map(_.ready)) + load.io.attemptRebind := 0.U.asTypeOf(load.io.attemptRebind) + projectRobId(load.io.attemptRebind.loadId, + rebindApply.bits.allocationId.value) + load.io.attemptRebind.loadId.wrap := + rebindApply.bits.allocationId.generation(0) + private def projectAttempt(target: linxcore.lsu.LoadAttemptIdentity, + source: linxcore.top.interface.MemoryIdentity): Unit = { + target := 0.U.asTypeOf(target) + target.valid := true.B + target.producer.valid := true.B + target.producer.peId := source.rob.peId + target.producer.stid := source.rob.stid + target.producer.nativeBidValid := true.B + target.producer.nativeBid := source.rob.bid + target.producer.brobGeneration := source.rob.brobGeneration + target.producer.ridSlot := source.rob.ridSlot + target.producer.ridGeneration := source.rob.ridGeneration + target.producer.memberIndex := source.rob.memberIndex + target.producer.residentGeneration := source.rob.residentGeneration + target.transactionValue := source.transaction.value + target.transactionGeneration := source.transaction.generation + target.generation := source.attemptGeneration + } + projectAttempt(load.io.attemptRebind.current, + rebindApply.bits.currentIdentity) + projectAttempt(load.io.attemptRebind.next, + rebindApply.bits.nextIdentity) + val structuralRebind = rebindApply.bits.structural + load.io.structuralRetryValid := rebindApply.valid && selectedCancelReady && + structuralRebind + load.io.structuralRetry := 0.U.asTypeOf(load.io.structuralRetry) + load.io.structuralRetry.loadId.valid := true.B + load.io.structuralRetry.loadId.slot := + rebindApply.bits.allocationId.value + load.io.structuralRetry.loadId.generation := + rebindApply.bits.allocationId.generation + projectAttempt(load.io.structuralRetry.current, + rebindApply.bits.currentIdentity) + projectAttempt(load.io.structuralRetry.next, + rebindApply.bits.nextIdentity) + load.io.structuralRetry.returnPipeIndex := + rebindApply.bits.currentIdentity.pipeId + load.io.structuralRetry.waitStore := rebindApply.bits.waitStore.valid + load.io.structuralRetry.waitStoreInfo.valid := + rebindApply.bits.waitStore.valid + load.io.structuralRetry.waitStoreInfo.storeIndex := + rebindApply.bits.waitStore.storeIndex + load.io.structuralRetry.waitStoreInfo.storeId.valid := + rebindApply.bits.waitStore.storeIdValid + load.io.structuralRetry.waitStoreInfo.storeId.value := + rebindApply.bits.waitStore.storeIdValue + load.io.structuralRetry.waitStoreInfo.storeId.wrap := + rebindApply.bits.waitStore.storeIdWrap + load.io.structuralRetry.waitStoreInfo.storeLsId.valid := + rebindApply.bits.waitStore.storeLsidValid + load.io.structuralRetry.waitStoreInfo.storeLsId.value := + rebindApply.bits.waitStore.storeLsidValue + load.io.structuralRetry.waitStoreInfo.storeLsId.wrap := + rebindApply.bits.waitStore.storeLsidWrap + load.io.structuralRetry.waitStoreInfo.storeLsIdFullValid := + rebindApply.bits.waitStore.storeLsidFullValid + load.io.structuralRetry.waitStoreInfo.storeLsIdFull := + rebindApply.bits.waitStore.storeLsidFull + load.io.structuralRetry.waitStoreInfo.pc := rebindApply.bits.waitStore.pc + val selectedMutationReady = Mux( + structuralRebind, load.io.structuralRetryReady, + load.io.attemptRebindReady) + load.io.attemptRebindValid := rebindApply.valid && selectedCancelReady && + !structuralRebind + rebindApply.ready := selectedCancelReady && selectedMutationReady + val repickIndex = PriorityEncoder(load.io.liqRepickMask) + val repickRow = load.io.liqRows(repickIndex) + load.io.pickValid := false.B + load.io.pickIndex := repickIndex + load.io.scbReturnValid := false.B + load.io.scbReturnIndex := 0.U + load.io.e2Stores := 0.U.asTypeOf(load.io.e2Stores) + load.io.e2ScbReturned := false.B + load.io.e2StqReturned := false.B + load.io.l1dEvictionReady := false.B + load.io.l1dInvalidateAll := false.B + load.io.l1dInvalidateLineValid := false.B + load.io.l1dInvalidateLineAddress := 0.U + load.io.replayWakeValid := false.B + load.io.replayWake := 0.U.asTypeOf(load.io.replayWake) + load.io.refillValid := false.B + load.io.refill := 0.U.asTypeOf(load.io.refill) + val missLane = if (p.lsu.loadPipes == 1) 0.U else + load.io.missRequest.missId.value(log2Ceil(p.lsu.loadPipes) - 1, 0) + val missLaneReady = Wire(Vec(p.lsu.loadPipes, Bool())) + translation.io.memoryRequest.ready := false.B + for (lane <- 0 until p.lsu.loadPipes) { + val request = io.memoryRequest(lane) + val translationSelected = lane == 0 + val dataRequest = Wire(chiselTypeOf(request.bits)) + dataRequest := 0.U.asTypeOf(dataRequest) + dataRequest.identity.value := load.io.missRequest.missId.value + dataRequest.identity.generation := load.io.missRequest.missId.wrap.asUInt + dataRequest.command := MemoryCommand.Read + dataRequest.accessKind := Mux( + load.io.missRequest.lineAddr(p.physicalAddressWidth - 1, + p.physicalAddressWidth - 8).andR, + MemoryAccessKind.Device, MemoryAccessKind.Data) + dataRequest.address := load.io.missRequest.lineAddr + dataRequest.size := MemorySize.fromBytes(scalarLsu.lineBytes.U) + val translationValid = if (translationSelected) + translation.io.memoryRequest.valid else false.B + val dataValid = load.io.missRequestValid && missLane === lane.U + request.valid := translationValid || dataValid + request.bits := Mux(translationValid, + translation.io.memoryRequest.bits, dataRequest) + if (translationSelected) { + translation.io.memoryRequest.ready := request.ready + } + missLaneReady(lane) := request.ready && !translationValid && + missLane === lane.U + } + load.io.missRequestReady := missLaneReady.asUInt.orR + + val loadResponseArbiter = Module(new RRArbiter( + chiselTypeOf(io.memoryResponse.head.bits), p.lsu.loadPipes)) + for (lane <- 0 until p.lsu.loadPipes) { + loadResponseArbiter.io.in(lane) <> io.memoryResponse(lane) + } + val publicLoadResponse = loadResponseArbiter.io.out + translation.io.memoryResponse.bits := publicLoadResponse.bits + val translationResponse = translation.io.responseOwned + translation.io.memoryResponse.valid := publicLoadResponse.valid && + translationResponse + load.io.missResponseValid := publicLoadResponse.valid && + !translationResponse + publicLoadResponse.ready := Mux(translationResponse, + translation.io.memoryResponse.ready, load.io.missResponseReady) + load.io.missResponse := 0.U.asTypeOf(load.io.missResponse) + load.io.missResponse.missId.valid := publicLoadResponse.valid + load.io.missResponse.missId.value := publicLoadResponse.bits.identity.value + load.io.missResponse.missId.wrap := + publicLoadResponse.bits.identity.generation(0) + load.io.missResponse.lineAddr := publicLoadResponse.bits.address + load.io.missResponse.isRead := true.B + val refillLineData = Module(new LSURefillLineData(p)) + refillLineData.io.response := publicLoadResponse.bits + load.io.missResponse.data := refillLineData.io.lineData + load.io.missResponse.l2Miss := publicLoadResponse.bits.denied || + publicLoadResponse.bits.corrupt + load.io.resolveRetireValid := load.io.loadReturn.completionCandidateValid && + completionReady + load.io.resolveRetireBid := completion.payload.bid + load.io.resolveRetireLsId := completion.payload.loadLsId + load.io.resolveRetireLsIdFullValid := + completion.payload.loadLsIdFullValid + load.io.resolveRetireLsIdFull := completion.payload.loadLsIdFull + load.recovery.ready := io.iex.recoveryEvent.ready + for (lane <- 0 until p.lsu.loadPipes) { + val repick = io.iex.loadRepick(lane) + val structuralForLane = structuralBlock.io.retry.valid && + structuralBlock.io.retry.bits.returnPipeIndex === lane.U + val ordinaryForLane = load.io.liqRepickMask.orR && + repickRow.returnPipeIndex === lane.U + repick.valid := structuralForLane || ordinaryForLane + repick.bits := 0.U.asTypeOf(repick.bits) + val structuralIndex = structuralBlock.io.retry.bits.loadId.slot( + log2Ceil(scalarLsu.liqEntries) - 1, 0) + val structuralRow = load.io.liqRows(structuralIndex) + val selectedRow = Mux(structuralForLane, structuralRow, repickRow) + val selectedLoadId = Mux(structuralForLane, + structuralBlock.io.retry.bits.loadId, + LoadCanonicalRowIdentity.fromRobId(repickRow.loadId)) + val selectedCurrentAttempt = Mux(structuralForLane, + structuralBlock.io.retry.bits.current, repickRow.attempt) + val ordinaryNextAttempt = Wire(chiselTypeOf(repickRow.attempt)) + ordinaryNextAttempt := repickRow.attempt + ordinaryNextAttempt.generation := repickRow.attempt.generation +% 1.U + val selectedNextAttempt = Mux(structuralForLane, + structuralBlock.io.retry.bits.next, + ordinaryNextAttempt) + repick.bits.allocationId.value := selectedLoadId.slot + repick.bits.allocationId.generation := selectedLoadId.generation + repick.bits.currentIdentity.rob.peId := selectedCurrentAttempt.producer.peId + repick.bits.currentIdentity.rob.stid := selectedCurrentAttempt.producer.stid + repick.bits.currentIdentity.rob.ridSlot := + selectedCurrentAttempt.producer.ridSlot + repick.bits.currentIdentity.rob.ridGeneration := + selectedCurrentAttempt.producer.ridGeneration + repick.bits.currentIdentity.rob.memberIndex := + selectedCurrentAttempt.producer.memberIndex + repick.bits.currentIdentity.rob.residentGeneration := + selectedCurrentAttempt.producer.residentGeneration + repick.bits.currentIdentity.rob.bid := + selectedCurrentAttempt.producer.nativeBid + repick.bits.currentIdentity.rob.brobGeneration := + selectedCurrentAttempt.producer.brobGeneration + repick.bits.currentIdentity.lsid := selectedRow.loadLsIdFull + repick.bits.currentIdentity.transaction.value := + selectedCurrentAttempt.transactionValue + repick.bits.currentIdentity.transaction.generation := + selectedCurrentAttempt.transactionGeneration + repick.bits.currentIdentity.attemptGeneration := + selectedCurrentAttempt.generation + repick.bits.currentIdentity.pipeId := selectedRow.returnPipeIndex + repick.bits.nextIdentity := repick.bits.currentIdentity + repick.bits.nextIdentity.attemptGeneration := + selectedNextAttempt.generation + repick.bits.structural := structuralForLane + repick.bits.waitStore.valid := structuralForLane && + structuralBlock.io.retry.bits.waitStore + repick.bits.waitStore.storeIndex := + structuralBlock.io.retry.bits.waitStoreInfo.storeIndex + repick.bits.waitStore.storeIdValid := + structuralBlock.io.retry.bits.waitStoreInfo.storeId.valid + repick.bits.waitStore.storeIdValue := + structuralBlock.io.retry.bits.waitStoreInfo.storeId.value + repick.bits.waitStore.storeIdWrap := + structuralBlock.io.retry.bits.waitStoreInfo.storeId.wrap + repick.bits.waitStore.storeLsidValid := + structuralBlock.io.retry.bits.waitStoreInfo.storeLsId.valid + repick.bits.waitStore.storeLsidValue := + structuralBlock.io.retry.bits.waitStoreInfo.storeLsId.value + repick.bits.waitStore.storeLsidWrap := + structuralBlock.io.retry.bits.waitStoreInfo.storeLsId.wrap + repick.bits.waitStore.storeLsidFullValid := + structuralBlock.io.retry.bits.waitStoreInfo.storeLsIdFullValid + repick.bits.waitStore.storeLsidFull := + structuralBlock.io.retry.bits.waitStoreInfo.storeLsIdFull + repick.bits.waitStore.pc := + structuralBlock.io.retry.bits.waitStoreInfo.pc + } + structuralBlock.io.retry.ready := Mux1H( + UIntToOH(structuralBlock.io.retry.bits.returnPipeIndex, + p.lsu.loadPipes), io.iex.loadRepick.map(_.ready)) + for (lane <- 0 until p.lsu.loadPipes) { + val cancel = io.iex.loadCancel(lane) + cancel.valid := rebindApply.valid && selectedMutationReady && + rebindArbiter.io.chosen === lane.U + cancel.bits := 0.U.asTypeOf(cancel.bits) + cancel.bits.currentIdentity := rebindApply.bits.currentIdentity + } + val cancelFire = VecInit(io.iex.loadCancel.map(_.fire)).asUInt.orR + val selectedMutationAccepted = Mux( + structuralRebind, load.io.structuralRetryAccepted, + load.io.attemptRebindAccepted) + when(rebindApply.fire || selectedMutationAccepted || cancelFire) { + assert(rebindApply.fire && selectedMutationAccepted && cancelFire, + "LSU rebind, selected LIQ mutation, and old-attempt cancel must share one fire") + } + io.iex.recoveryEvent.valid := load.recovery.valid + io.iex.recoveryEvent.bits := 0.U.asTypeOf(io.iex.recoveryEvent.bits) + io.iex.recoveryEvent.bits.transactionId := load.recovery.flush.req.lsIdFull + io.iex.recoveryEvent.bits.cause := RecoveryCause.MemoryOrder + io.iex.recoveryEvent.bits.trigger.peId := load.recovery.flush.req.peId + io.iex.recoveryEvent.bits.trigger.stid := load.recovery.flush.req.stid + io.iex.recoveryEvent.bits.trigger.bid := load.recovery.flush.req.bid.value + io.iex.recoveryEvent.bits.trigger.ridSlot := load.recovery.flush.req.gid.value + io.iex.recoveryEvent.bits.instruction.peId := load.recovery.flush.req.peId + io.iex.recoveryEvent.bits.instruction.stid := load.recovery.flush.req.stid + io.iex.recoveryEvent.bits.redirectPc := load.recovery.flush.req.fetchTpc + + io.memoryRequest.drop(p.lsu.loadPipes + 2).foreach { out => + out.valid := false.B + out.bits := 0.U.asTypeOf(out.bits) + } + io.memoryResponse.drop(p.lsu.loadPipes + 2).foreach(_.ready := false.B) + for (lane <- io.memoryRequest.indices) { + lowerRecovery.io.requestFire(lane) := io.memoryRequest(lane).fire + lowerRecovery.io.requestIdentity(lane) := + io.memoryRequest(lane).bits.identity + lowerRecovery.io.responseFire(lane) := io.memoryResponse(lane).fire + lowerRecovery.io.responseIdentity(lane) := + io.memoryResponse(lane).bits.identity + } + val maintenanceDrainReadyNow = store.io.empty && backend.io.empty && + load.io.empty && translation.io.quiescent && lowerRecovery.io.quiescent && + !loadRecoveryPending && !faultValid && derivedStoreClassEmpty + val maintenanceDrainObserved = RegInit(false.B) + when(io.maintenance.fire) { + maintenanceDrainObserved := false.B + }.elsewhen(maintenancePending) { + maintenanceDrainObserved := maintenanceDrainReadyNow + }.otherwise { + maintenanceDrainObserved := false.B + } + // The sample is taken only after the acceptance edge, while incoming valid + // and retained pending state fence normal admission. Registering it also + // breaks the L1D maintenance-to-empty feedback path. + val maintenanceExecute = maintenancePending && maintenanceDrainObserved + val executingMaintenanceCommand = maintenanceCommand + val executingMaintenanceAddress = maintenanceAddress + load.io.l1dInvalidateAll := maintenanceExecute && + executingMaintenanceCommand === LSUMaintenanceCommand.InvalidateAll + load.io.l1dInvalidateLineValid := maintenanceExecute && + executingMaintenanceCommand === LSUMaintenanceCommand.InvalidateLine + load.io.l1dInvalidateLineAddress := executingMaintenanceAddress + when(maintenanceExecute) { + when(executingMaintenanceCommand === + LSUMaintenanceCommand.InvalidateTranslation || + executingMaintenanceCommand === LSUMaintenanceCommand.InvalidateAll) { + translation.io.invalidate := true.B + } + maintenancePending := false.B + maintenanceResultValid := true.B + maintenanceResultSuccess := !load.io.l1dMaintenanceError + } + when(backend.io.protocolError || lowerRecovery.io.protocolError || + structuralBlock.io.protocolError || + load.io.l1dMaintenanceError) { + protocolErrorSticky := true.B + } + io.quiescent := store.io.empty && backend.io.empty && load.io.empty && + translation.io.quiescent && lowerRecovery.io.quiescent && + !loadRecoveryPending && !faultValid && !maintenancePending && + !maintenanceResultValid && !protocolErrorSticky && derivedStoreClassEmpty + io.trace.valid := false.B + io.trace.bits := 0.U.asTypeOf(io.trace.bits) +} + +/** Stable public LSU box. All retained state and arbitration live below this + * wiring-only shell in the private canonical owner graph. + */ +class LSU(val p: CoreParams) extends Module { + val io = IO(new LSUIO(p)) + private val owner = Module(new LSUCanonicalOwner(p)) + io <> owner.io +} diff --git a/chisel/src/main/scala/linxcore/lsu/LSURecovery.scala b/chisel/src/main/scala/linxcore/lsu/LSURecovery.scala new file mode 100644 index 00000000..dbd805d9 --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/LSURecovery.scala @@ -0,0 +1,136 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{PopCount, PriorityEncoder, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.MemoryTransactionIdentity + +class LSULowerTransactionRecoveryIO( + val p: CoreParams, + val lanes: Int, + val entries: Int) + extends Bundle { + private val countWidth = log2Ceil(entries + 1) + + val prepareFire = Input(Bool()) + val applyFire = Input(Bool()) + val abortFire = Input(Bool()) + val requestFire = Input(Vec(lanes, Bool())) + val requestIdentity = Input(Vec(lanes, + new MemoryTransactionIdentity(p))) + val responseFire = Input(Vec(lanes, Bool())) + val responseIdentity = Input(Vec(lanes, + new MemoryTransactionIdentity(p))) + + val fenced = Output(Bool()) + val quiescent = Output(Bool()) + val outstandingCount = Output(UInt(countWidth.W)) + val staleResponse = Output(Bool()) + val protocolError = Output(Bool()) +} + +/** Exact lower-memory transaction ledger used by LSU recovery. + * + * Prepare fences new request fire without deleting accepted transactions. + * Only a full value-plus-generation response match drains a ledger row; + * therefore an Apply can never publish quiescence while an old response can + * still mutate MissQ/refill/store-drain state. + */ +class LSULowerTransactionRecovery( + val p: CoreParams, + val lanes: Int, + val entries: Int) + extends Module { + require(lanes > 0) + require(entries >= lanes) + require(entries % lanes == 0) + + val io = IO(new LSULowerTransactionRecoveryIO(p, lanes, entries)) + + val valid = RegInit(VecInit(Seq.fill(entries)(false.B))) + val identity = Reg(Vec(entries, new MemoryTransactionIdentity(p))) + val fenced = RegInit(false.B) + val failed = RegInit(false.B) + + when(io.prepareFire) { fenced := true.B } + when(io.applyFire || io.abortFire) { fenced := false.B } + + private val entriesPerLane = entries / lanes + private val entryIndexWidth = log2Ceil(entries) + val duplicateRequest = Wire(Vec(lanes, Bool())) + val allocationFailure = Wire(Vec(lanes, Bool())) + val staleResponse = Wire(Vec(lanes, Bool())) + duplicateRequest := VecInit(Seq.fill(lanes)(false.B)) + allocationFailure := VecInit(Seq.fill(lanes)(false.B)) + staleResponse := VecInit(Seq.fill(lanes)(false.B)) + + val responseMatches = Wire(Vec(lanes, Vec(entries, Bool()))) + for (lane <- 0 until lanes; index <- 0 until entries) { + responseMatches(lane)(index) := valid(index) && + identity(index).value === io.responseIdentity(lane).value && + identity(index).generation === io.responseIdentity(lane).generation + } + val responseClear = Wire(Vec(entries, Bool())) + val duplicateResponse = Wire(Vec(entries, Bool())) + for (index <- 0 until entries) { + val clearingLanes = VecInit((0 until lanes).map(lane => + io.responseFire(lane) && responseMatches(lane)(index))) + responseClear(index) := clearingLanes.asUInt.orR + duplicateResponse(index) := PopCount(clearingLanes) > 1.U + } + val postResponseValid = Wire(Vec(entries, Bool())) + for (index <- 0 until entries) { + postResponseValid(index) := valid(index) && !responseClear(index) + when(responseClear(index)) { valid(index) := false.B } + } + + for (lane <- 0 until lanes) { + val base = lane * entriesPerLane + val responseMatchCount = PopCount(responseMatches(lane)) + val sameCycleCompletion = io.requestFire(lane) && + io.responseFire(lane) && responseMatchCount === 0.U && + io.requestIdentity(lane).value === io.responseIdentity(lane).value && + io.requestIdentity(lane).generation === + io.responseIdentity(lane).generation + when(io.responseFire(lane)) { + when(responseMatchCount =/= 1.U && !sameCycleCompletion) { + staleResponse(lane) := true.B + } + } + + val requestMatches = VecInit((0 until entriesPerLane).map { offset => + val index = base + offset + postResponseValid(index) && + identity(index).value === io.requestIdentity(lane).value && + identity(index).generation === io.requestIdentity(lane).generation + }) + val free = VecInit((0 until entriesPerLane).map(offset => + !postResponseValid(base + offset))) + when(io.requestFire(lane) && !sameCycleCompletion) { + when(requestMatches.asUInt.orR) { + duplicateRequest(lane) := true.B + }.elsewhen(free.asUInt.orR) { + val index = base.U(entryIndexWidth.W) + + PriorityEncoder(free).pad(entryIndexWidth) + valid(index) := true.B + identity(index) := io.requestIdentity(lane) + }.otherwise { + allocationFailure(lane) := true.B + } + } + } + + + when(duplicateRequest.asUInt.orR || allocationFailure.asUInt.orR || + duplicateResponse.asUInt.orR) { + failed := true.B + fenced := true.B + } + + io.fenced := fenced || failed + io.quiescent := !valid.asUInt.orR && !failed + io.outstandingCount := PopCount(valid) + io.staleResponse := staleResponse.asUInt.orR + io.protocolError := failed || duplicateRequest.asUInt.orR || + allocationFailure.asUInt.orR || duplicateResponse.asUInt.orR +} diff --git a/chisel/src/main/scala/linxcore/lsu/LSURefillLineData.scala b/chisel/src/main/scala/linxcore/lsu/LSURefillLineData.scala new file mode 100644 index 00000000..fd4ba83d --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/LSURefillLineData.scala @@ -0,0 +1,16 @@ +package linxcore.lsu + +import chisel3._ +import linxcore.params.CoreParams +import linxcore.top.interface.MemoryResponseTxn + +class LSURefillLineDataIO(val p: CoreParams) extends Bundle { + val response = Input(new MemoryResponseTxn(p)) + val lineData = Output(UInt((p.lsu.lineBytes * 8).W)) +} + +/** Public lower-memory responses carry the authoritative complete line. */ +class LSURefillLineData(val p: CoreParams) extends Module { + val io = IO(new LSURefillLineDataIO(p)) + io.lineData := io.response.lineData +} diff --git a/chisel/src/main/scala/linxcore/lsu/LoadAttemptIdentity.scala b/chisel/src/main/scala/linxcore/lsu/LoadAttemptIdentity.scala index 4e4271ac..548cdf6c 100644 --- a/chisel/src/main/scala/linxcore/lsu/LoadAttemptIdentity.scala +++ b/chisel/src/main/scala/linxcore/lsu/LoadAttemptIdentity.scala @@ -33,6 +33,8 @@ class LoadAttemptProducer extends Bundle { class LoadAttemptIdentity extends Bundle { val valid = Bool() val producer = new LoadAttemptProducer + val transactionValue = UInt(LoadAttemptIdentity.TransactionWidth.W) + val transactionGeneration = UInt(LoadAttemptIdentity.GenerationWidth.W) val generation = UInt(LoadAttemptIdentity.GenerationWidth.W) } @@ -43,6 +45,7 @@ object LoadAttemptIdentity { val ScopeWidth = 16 val IndexWidth = 16 val GenerationWidth = 32 + val TransactionWidth = 64 /** Prove that an integration bridge can zero-extend every native identity * field into this protocol without truncation. @@ -58,7 +61,9 @@ object LoadAttemptIdentity { ridGenerationWidth: Int, memberIndexWidth: Int, residentGenerationWidth: Int, - attemptGenerationWidth: Int): Unit = { + attemptGenerationWidth: Int, + transactionWidth: Int = TransactionWidth, + transactionGenerationWidth: Int = GenerationWidth): Unit = { def requireWidth(name: String, width: Int, capacity: Int): Unit = require(width > 0 && width <= capacity, s"$name width $width must fit in the positive $capacity-bit LoadAttemptIdentity field") @@ -72,12 +77,17 @@ object LoadAttemptIdentity { requireWidth("memberIndex", memberIndexWidth, IndexWidth) requireWidth("residentGeneration", residentGenerationWidth, GenerationWidth) requireWidth("attemptGeneration", attemptGenerationWidth, GenerationWidth) + requireWidth("transaction", transactionWidth, TransactionWidth) + requireWidth("transactionGeneration", transactionGenerationWidth, + GenerationWidth) } def none: LoadAttemptIdentity = { val out = Wire(new LoadAttemptIdentity) out.valid := false.B out.producer := 0.U.asTypeOf(out.producer) + out.transactionValue := 0.U + out.transactionGeneration := 0.U out.generation := 0.U out } @@ -85,6 +95,8 @@ object LoadAttemptIdentity { def equal(lhs: LoadAttemptIdentity, rhs: LoadAttemptIdentity): Bool = lhs.valid === rhs.valid && lhs.producer.asUInt === rhs.producer.asUInt && + lhs.transactionValue === rhs.transactionValue && + lhs.transactionGeneration === rhs.transactionGeneration && lhs.generation === rhs.generation def wellFormed(value: LoadAttemptIdentity): Bool = diff --git a/chisel/src/main/scala/linxcore/lsu/LoadForwardResultRetainer.scala b/chisel/src/main/scala/linxcore/lsu/LoadForwardResultRetainer.scala new file mode 100644 index 00000000..a74e68ce --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/LoadForwardResultRetainer.scala @@ -0,0 +1,75 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{Decoupled, PopCount, Queue, log2Ceil} + +class LoadForwardResultRetainerIO( + val idEntries: Int, + val storeEntries: Int, + val pcWidth: Int, + val lineBytes: Int, + val lsidWidth: Int, + val depth: Int) + extends Bundle { + val flush = Input(Bool()) + val in = Flipped(Decoupled(new LoadInflightForwardResult( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth))) + val outValid = Output(Bool()) + val out = Output(new LoadInflightForwardResult( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth)) + val sinkAccepted = Input(Bool()) + val sinkRejectedPermanent = Input(Bool()) + val sinkRetryRequired = Input(Bool()) + val count = Output(UInt(log2Ceil(depth + 1).W)) + val pending = Output(Bool()) + val protocolError = Output(Bool()) +} + +/** Retains classified STQ E4 results until the canonical LIQ reaches a + * terminal decision. + * + * Recovery and competing LIQ mutations are retryable owner conflicts. They + * hold the FIFO head unchanged. Exact acceptance or a typed permanent stale + * rejection is terminal and dequeues exactly one result. + */ +class LoadForwardResultRetainer( + val idEntries: Int, + val storeEntries: Int, + val pcWidth: Int = 64, + val lineBytes: Int = 64, + val lsidWidth: Int = 32, + val depth: Int = 4) + extends Module { + require(depth >= 2, + "forward-result retention must cover registered E3/E4 traffic") + + val io = IO(new LoadForwardResultRetainerIO( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth, depth)) + + val queue = withReset(reset.asBool || io.flush) { + Module(new Queue(new LoadInflightForwardResult( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth), + depth, pipe = true, flow = false)) + } + queue.io.enq <> io.in + + val terminal = io.sinkAccepted || io.sinkRejectedPermanent + queue.io.deq.ready := terminal + io.outValid := queue.io.deq.valid + io.out := queue.io.deq.bits + io.count := queue.io.count + io.pending := queue.io.deq.valid + + val protocolError = RegInit(false.B) + val decisions = VecInit(Seq( + io.sinkAccepted, + io.sinkRejectedPermanent, + io.sinkRetryRequired)) + when(io.flush) { + protocolError := false.B + }.elsewhen(PopCount(decisions) > 1.U || + ((terminal || io.sinkRetryRequired) && !queue.io.deq.valid)) { + protocolError := true.B + } + io.protocolError := protocolError +} diff --git a/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala b/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala index 2797c5a7..5ec21092 100644 --- a/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala +++ b/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala @@ -11,6 +11,45 @@ object LoadInflightStatus extends ChiselEnum { val Idle, Wait, Repick, L1DcMiss, L2Wait, Resolved = Value } +private[lsu] object LoadAttemptRebindTransition { + def lifecycleReady(status: LoadInflightStatus.Type): Bool = + status === LoadInflightStatus.Wait || + status === LoadInflightStatus.L1DcMiss || + status === LoadInflightStatus.L2Wait + + def next(current: LoadInflightRow, + attempt: LoadAttemptIdentity): LoadInflightRow = { + val result = Wire(chiselTypeOf(current)) + result := current + result.status := LoadInflightStatus.Wait + result.attempt := attempt + result.repickRequired := false.B + result.forwardPending := false.B + result.lineData := 0.U + result.validMask := 0.U + result.loadByteMask := 0.U + result.forwardMask := 0.U + result.waitMask := 0.U + result.secondSegmentActive := false.B + result.firstSegmentDone := false.B + result.firstLineData := 0.U + result.firstValidMask := 0.U + result.firstLoadByteMask := 0.U + result.firstForwardMask := 0.U + result.waitStore := false.B + result.waitStoreInfo := 0.U.asTypeOf(result.waitStoreInfo) + result.storeBypass := false.B + result.dataComplete := false.B + result.sourcesReturned := false.B + result.scbReturned := false.B + result.stqReturned := false.B + result.l1Hit := false.B + result.l1Miss := false.B + result.missKind := LoadForwardMissKind.NoMiss + result + } +} + class LoadInflightAlloc( val liqEntries: Int, val idEntries: Int, @@ -106,6 +145,8 @@ class LoadInflightRow( val specWakeup = Bool() val stackValid = Bool() val returnPipeIndex = UInt(returnPipeIndexWidth.W) + val forwardPending = Bool() + val repickRequired = Bool() val lineData = UInt((lineBytes * 8).W) val validMask = UInt(lineBytes.W) @@ -159,6 +200,30 @@ class LoadHitRecord( val forwardedMask = UInt(lineBytes.W) } +/** One fully classified forwarding result presented to the canonical LIQ. */ +class LoadInflightForwardResult( + val idEntries: Int, + val storeEntries: Int, + val pcWidth: Int = 64, + val lineBytes: Int = 64, + val lsidWidth: Int = 32) + extends Bundle { + val identity = new STQLoadForwardResultIdentity + val lineData = UInt((lineBytes * 8).W) + val validMask = UInt(lineBytes.W) + val loadByteMask = UInt(lineBytes.W) + val forwardMask = UInt(lineBytes.W) + val waitMask = UInt(lineBytes.W) + val dataComplete = Bool() + val sourcesReturned = Bool() + val scbReturned = Bool() + val stqReturned = Bool() + val wakeupValid = Bool() + val waitStore = new LoadStoreForwardWait( + idEntries, storeEntries, pcWidth, lsidWidth) + val missKind = LoadForwardMissKind() +} + class LoadInflightQueueIO( val liqEntries: Int, val idEntries: Int, @@ -215,8 +280,26 @@ class LoadInflightQueueIO( val attemptRebindBlockedByStaleAttempt = Output(Bool()) val attemptRebindBlockedByNextAttempt = Output(Bool()) + val structuralRetryValid = Input(Bool()) + val structuralRetry = Input(new LoadStructuralBlockRetry( + idEntries, storeEntries, pcWidth, lsidWidth)) + val structuralRetryReady = Output(Bool()) + val structuralRetryAccepted = Output(Bool()) + val structuralRetryBlockedByLoadId = Output(Bool()) + val structuralRetryBlockedByAttempt = Output(Bool()) + val structuralRetryBlockedByNextAttempt = Output(Bool()) + val structuralRetryBlockedByPipe = Output(Bool()) + val structuralRetryBlockedByLifecycle = Output(Bool()) + val structuralRetryBlockedByWaitStore = Output(Bool()) + val structuralRetryBlockedByMutation = Output(Bool()) + val launchValid = Input(Bool()) val launchIndex = Input(UInt(liqPtrWidth.W)) + // Raw launch intent is kept separate from the credit-qualified launch + // request. Replay rebind arbitration must conservatively exclude a + // same-row launch without depending on downstream return-path readiness. + val launchIntentValid = Input(Bool()) + val launchIntentIndex = Input(UInt(liqPtrWidth.W)) val launchReady = Output(Bool()) val launchAccepted = Output(Bool()) @@ -244,6 +327,20 @@ class LoadInflightQueueIO( val e2StqReturned = Input(Bool()) val e2ReturnReady = Input(Bool()) + val forwardResultValid = Input(Bool()) + val forwardResult = Input(new LoadInflightForwardResult( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth)) + val forwardResultAccepted = Output(Bool()) + val forwardResultRejected = Output(Bool()) + val forwardResultRejectedByLoadId = Output(Bool()) + val forwardResultRejectedByAttempt = Output(Bool()) + val forwardResultRejectedByPipe = Output(Bool()) + val forwardResultRejectedByLifecycle = Output(Bool()) + val forwardResultRejectedPermanent = Output(Bool()) + val forwardResultRetryRequired = Output(Bool()) + val forwardResultRetryByRecovery = Output(Bool()) + val forwardResultRetryByMutationConflict = Output(Bool()) + val replayWakeValid = Input(Bool()) val replayWake = Input(new LoadReplayWakeupRequest(idEntries, addrWidth, pcWidth, lineBytes, lsidWidth)) val replayWakeWaitStoreClearMask = Output(UInt(liqEntries.W)) @@ -351,7 +448,8 @@ class LoadInflightQueue( val stidWidth: Int = 8, val tidWidth: Int = 8, val returnPipeCount: Int = 1, - val lsidWidth: Int = 32) + val lsidWidth: Int = 32, + val useExternalForwardResult: Boolean = false) extends Module { require(liqEntries > 1, "LIQ entries must be greater than one") require((liqEntries & (liqEntries - 1)) == 0, "LIQ entries must be a power of two") @@ -477,15 +575,6 @@ class LoadInflightQueue( val residentCount = RegInit(0.U(countWidth.W)) val flushCycle = io.flush || io.preciseFlush.req.valid - val pipeline = Module(new LoadForwardPipeline( - idEntries, storeEntries, addrWidth, pcWidth, lineBytes, sizeWidth, lsidWidth)) - pipeline.io.flush := flushCycle - pipeline.io.e2Stores := io.e2Stores - pipeline.io.e2LoadDataReturned := io.e2LoadDataReturned - pipeline.io.e2ScbReturned := io.e2ScbReturned - pipeline.io.e2StqReturned := io.e2StqReturned - pipeline.io.e2ReturnReady := io.e2ReturnReady - val launchRow = rows(io.launchIndex) val launchReady = !flushCycle && launchRow.valid && (launchRow.status === LoadInflightStatus.Wait) && !launchRow.waitStore @@ -514,9 +603,6 @@ class LoadInflightQueue( markResolvedRequestComplete val markResolvedAccepted = io.markResolvedValid && markResolvedReady - pipeline.io.e2BaseData := Mux(launchUsesRowData, launchRow.lineData, io.e2BaseData) - pipeline.io.e2BaseValidMask := Mux(launchUsesRowData, launchRow.validMask, io.e2BaseValidMask) - val query = Wire(new LoadStoreForwardQuery(idEntries, addrWidth, lineBytes, sizeWidth, lsidWidth)) query := 0.U.asTypeOf(query) query.valid := launchAccepted @@ -529,8 +615,78 @@ class LoadInflightQueue( query.youngestStoreLsIdFull := launchRow.youngestStoreLsIdFull query.isTile := launchRow.isTile - pipeline.io.e2Valid := launchAccepted - pipeline.io.e2Query := query + val selectedForwardResult = Wire(new LoadInflightForwardResult( + idEntries, storeEntries, pcWidth, lineBytes, lsidWidth)) + selectedForwardResult := 0.U.asTypeOf(selectedForwardResult) + val selectedForwardResultValid = WireDefault(false.B) + val forwardPipelineResidentMask = WireDefault(0.U(liqEntries.W)) + + if (useExternalForwardResult) { + selectedForwardResult := io.forwardResult + selectedForwardResultValid := io.forwardResultValid + } else { + val pipeline = Module(new LoadForwardPipeline( + idEntries, storeEntries, addrWidth, pcWidth, lineBytes, sizeWidth, + lsidWidth)) + pipeline.io.flush := flushCycle + pipeline.io.e2Stores := io.e2Stores + pipeline.io.e2LoadDataReturned := io.e2LoadDataReturned + pipeline.io.e2ScbReturned := io.e2ScbReturned + pipeline.io.e2StqReturned := io.e2StqReturned + pipeline.io.e2ReturnReady := io.e2ReturnReady + pipeline.io.e2BaseData := Mux( + launchUsesRowData, launchRow.lineData, io.e2BaseData) + pipeline.io.e2BaseValidMask := Mux( + launchUsesRowData, launchRow.validMask, io.e2BaseValidMask) + pipeline.io.e2Valid := launchAccepted + pipeline.io.e2Query := query + + val e3Identity = RegInit(0.U.asTypeOf( + new STQLoadForwardResultIdentity)) + val e4Identity = RegInit(0.U.asTypeOf( + new STQLoadForwardResultIdentity)) + when(flushCycle) { + e3Identity := 0.U.asTypeOf(e3Identity) + e4Identity := 0.U.asTypeOf(e4Identity) + }.otherwise { + e4Identity := e3Identity + when(launchAccepted) { + e3Identity.loadId := + LoadCanonicalRowIdentity.fromRobId(launchRow.loadId) + e3Identity.attempt := launchRow.attempt + e3Identity.returnPipeIndex := launchRow.returnPipeIndex + } + } + + selectedForwardResultValid := pipeline.io.e4Valid + selectedForwardResult.identity := e4Identity + selectedForwardResult.lineData := pipeline.io.e4LineData + selectedForwardResult.validMask := pipeline.io.e4ValidMask + selectedForwardResult.loadByteMask := pipeline.io.e4LoadByteMask + selectedForwardResult.forwardMask := pipeline.io.e4ForwardMask + selectedForwardResult.waitMask := pipeline.io.e4WaitMask + selectedForwardResult.dataComplete := pipeline.io.e4DataComplete + selectedForwardResult.sourcesReturned := pipeline.io.e4SourcesReturned + selectedForwardResult.scbReturned := pipeline.io.e4ScbReturned + selectedForwardResult.stqReturned := pipeline.io.e4StqReturned + selectedForwardResult.wakeupValid := pipeline.io.e4WakeupValid + selectedForwardResult.waitStore := pipeline.io.e4WaitStore + selectedForwardResult.missKind := pipeline.io.e4MissKind + + val e3IdentityWellFormed = e3Identity.loadId.valid && + LoadCanonicalRowIdentity.wellFormed(e3Identity.loadId, liqEntries) + val e4IdentityWellFormed = e4Identity.loadId.valid && + LoadCanonicalRowIdentity.wellFormed(e4Identity.loadId, liqEntries) + val e3ResidentMask = Mux( + pipeline.io.e3Valid && e3IdentityWellFormed, + UIntToOH(e3Identity.loadId.slot(liqPtrWidth - 1, 0), liqEntries), + 0.U(liqEntries.W)) + val e4ResidentMask = Mux( + pipeline.io.e4Valid && e4IdentityWellFormed, + UIntToOH(e4Identity.loadId.slot(liqPtrWidth - 1, 0), liqEntries), + 0.U(liqEntries.W)) + forwardPipelineResidentMask := e3ResidentMask | e4ResidentMask + } val replayWakeup = Module(new LoadReplayWakeup( liqEntries, idEntries, storeEntries, addrWidth, pcWidth, lineBytes, sizeWidth, lsidWidth)) @@ -543,11 +699,6 @@ class LoadInflightQueue( refillWakeup.io.refill := io.refill refillWakeup.io.rows := rows - val e3IndexValid = RegInit(false.B) - val e3Index = RegInit(0.U(liqPtrWidth.W)) - val e4IndexValid = RegInit(false.B) - val e4Index = RegInit(0.U(liqPtrWidth.W)) - val allocLoadId = currentLoadId val allocAttemptWellFormed = LoadAttemptIdentity.wellFormed(io.alloc.attempt) val allocReady = @@ -565,13 +716,16 @@ class LoadInflightQueue( val attemptRebindNextExact = io.attemptRebind.next.valid && (io.attemptRebind.next.producer.asUInt === io.attemptRebind.current.producer.asUInt) && + (io.attemptRebind.next.transactionValue === + io.attemptRebind.current.transactionValue) && + (io.attemptRebind.next.transactionGeneration === + io.attemptRebind.current.transactionGeneration) && (io.attemptRebind.next.generation === (io.attemptRebind.current.generation +% 1.U)) val attemptRebindLifecycleReady = - (attemptRebindRow.status === LoadInflightStatus.Wait) || - (attemptRebindRow.status === LoadInflightStatus.L1DcMiss) || - (attemptRebindRow.status === LoadInflightStatus.L2Wait) + LoadAttemptRebindTransition.lifecycleReady(attemptRebindRow.status) val attemptRebindLaunchConflict = - (launchAccepted && (io.launchIndex === io.attemptRebind.loadId.value)) || + (io.launchIntentValid && + (io.launchIntentIndex === io.attemptRebind.loadId.value)) || (pickAccepted && (io.pickIndex === io.attemptRebind.loadId.value)) val attemptRebindReady = !flushCycle && @@ -597,39 +751,180 @@ class LoadInflightQueue( ((clearResolvedRow.status === LoadInflightStatus.Resolved) || clearResolvedCompleteRepick) val clearResolvedAccepted = io.clearResolvedValid && clearResolvedReady + val forwardResultLoadIdWellFormed = + selectedForwardResult.identity.loadId.valid && + LoadCanonicalRowIdentity.wellFormed( + selectedForwardResult.identity.loadId, liqEntries) + val forwardResultIndex = + selectedForwardResult.identity.loadId.slot(liqPtrWidth - 1, 0) + val forwardResultRow = rows(forwardResultIndex) + val forwardResultLoadIdExact = forwardResultLoadIdWellFormed && + forwardResultRow.valid && LoadCanonicalRowIdentity.equal( + selectedForwardResult.identity.loadId, + LoadCanonicalRowIdentity.fromRobId(forwardResultRow.loadId)) + val forwardResultAttemptExact = + selectedForwardResult.identity.attempt.valid && + LoadAttemptIdentity.wellFormed( + selectedForwardResult.identity.attempt) && + forwardResultRow.attempt.valid && LoadAttemptIdentity.equal( + selectedForwardResult.identity.attempt, forwardResultRow.attempt) + val forwardResultPipeExact = + selectedForwardResult.identity.returnPipeIndex === + forwardResultRow.returnPipeIndex + val forwardResultLifecycleReady = + (forwardResultRow.status === LoadInflightStatus.Repick) && + forwardResultRow.forwardPending + val forwardResultExactCandidate = selectedForwardResultValid && + forwardResultLoadIdExact && forwardResultAttemptExact && + forwardResultPipeExact && forwardResultLifecycleReady + val externalForwardResultMutationConflict = + useExternalForwardResult.B && + ((clearResolvedAccepted && + (io.clearResolvedIndex === forwardResultIndex)) || + (io.rowMutationValid && + (io.rowMutationTargetIndex === forwardResultIndex)) || + (io.replayWakeValid && + replayWakeup.io.waitStoreClearMask(forwardResultIndex)) || + (io.replayWakeValid && + replayWakeup.io.mergeMask(forwardResultIndex)) || + (io.refillValid && refillWakeup.io.wakeMask(forwardResultIndex))) val e4UpdateValid = - e4IndexValid && pipeline.io.e4Valid && rows(e4Index).valid && (rows(e4Index).status === LoadInflightStatus.Repick) + forwardResultExactCandidate && !flushCycle && + !externalForwardResultMutationConflict val e4SegmentResolved = - e4UpdateValid && pipeline.io.e4WakeupValid && (pipeline.io.e4MissKind === LoadForwardMissKind.NoMiss) + e4UpdateValid && selectedForwardResult.wakeupValid && + (selectedForwardResult.missKind === LoadForwardMissKind.NoMiss) val e4FirstSegmentResolved = - e4SegmentResolved && rows(e4Index).crossLine && !rows(e4Index).secondSegmentActive + e4SegmentResolved && forwardResultRow.crossLine && + !forwardResultRow.secondSegmentActive val e4Resolved = - e4SegmentResolved && (!rows(e4Index).crossLine || rows(e4Index).secondSegmentActive) - val e4StoreWait = e4UpdateValid && (pipeline.io.e4MissKind === LoadForwardMissKind.StoreDataNotReady) - val e4DataMiss = e4UpdateValid && (pipeline.io.e4MissKind === LoadForwardMissKind.DataNotComplete) + e4SegmentResolved && (!forwardResultRow.crossLine || + forwardResultRow.secondSegmentActive) + val e4StoreWait = e4UpdateValid && + (selectedForwardResult.missKind === + LoadForwardMissKind.StoreDataNotReady) + val e4DataMiss = e4UpdateValid && + (selectedForwardResult.missKind === LoadForwardMissKind.DataNotComplete) val e4ReplayWait = e4UpdateValid && - ((pipeline.io.e4MissKind === LoadForwardMissKind.AwaitingSources) || - (pipeline.io.e4MissKind === LoadForwardMissKind.ReturnPortBlocked)) + ((selectedForwardResult.missKind === + LoadForwardMissKind.AwaitingSources) || + (selectedForwardResult.missKind === + LoadForwardMissKind.ReturnPortBlocked)) + + val structuralRetryLoadIdWellFormed = + io.structuralRetry.loadId.valid && + LoadCanonicalRowIdentity.wellFormed( + io.structuralRetry.loadId, liqEntries) + val structuralRetryIndex = + io.structuralRetry.loadId.slot(liqPtrWidth - 1, 0) + val structuralRetryRow = rows(structuralRetryIndex) + val structuralRetryLoadIdExact = structuralRetryLoadIdWellFormed && + structuralRetryRow.valid && LoadCanonicalRowIdentity.equal( + io.structuralRetry.loadId, + LoadCanonicalRowIdentity.fromRobId(structuralRetryRow.loadId)) + val structuralRetryAttemptExact = + io.structuralRetry.current.valid && + LoadAttemptIdentity.wellFormed(io.structuralRetry.current) && + structuralRetryRow.attempt.valid && + LoadAttemptIdentity.equal( + io.structuralRetry.current, structuralRetryRow.attempt) + val structuralRetryNextExact = + io.structuralRetry.next.valid && + LoadAttemptIdentity.wellFormed(io.structuralRetry.next) && + (io.structuralRetry.next.producer.asUInt === + io.structuralRetry.current.producer.asUInt) && + (io.structuralRetry.next.generation === + (io.structuralRetry.current.generation +% 1.U)) + val structuralRetryPipeExact = + io.structuralRetry.returnPipeIndex === + structuralRetryRow.returnPipeIndex + val structuralRetryLifecycleExact = + structuralRetryRow.valid && + (structuralRetryRow.status === LoadInflightStatus.Repick) && + structuralRetryRow.forwardPending + val structuralRetryWaitStoreExact = Mux( + io.structuralRetry.waitStore, + io.structuralRetry.waitStoreInfo.valid && + io.structuralRetry.waitStoreInfo.storeId.valid && + io.structuralRetry.waitStoreInfo.storeLsId.valid && + io.structuralRetry.waitStoreInfo.storeLsIdFullValid, + !io.structuralRetry.waitStoreInfo.valid) + val structuralRetryMutationConflict = + (io.launchIntentValid && + (io.launchIntentIndex === structuralRetryIndex)) || + (io.pickValid && (io.pickIndex === structuralRetryIndex)) || + (io.scbReturnValid && + (io.scbReturnIndex === structuralRetryIndex)) || + (io.markResolvedValid && + (io.markResolvedIndex === structuralRetryIndex)) || + (io.clearResolvedValid && + (io.clearResolvedIndex === structuralRetryIndex)) || + (io.rowMutationValid && + (io.rowMutationTargetIndex === structuralRetryIndex)) || + (io.replayWakeValid && + (replayWakeup.io.waitStoreClearMask(structuralRetryIndex) || + replayWakeup.io.mergeMask(structuralRetryIndex))) || + (io.refillValid && refillWakeup.io.wakeMask(structuralRetryIndex)) || + (selectedForwardResultValid && + (forwardResultIndex === structuralRetryIndex)) + val structuralRetryReady = !flushCycle && + structuralRetryLoadIdExact && structuralRetryAttemptExact && + structuralRetryNextExact && structuralRetryPipeExact && + structuralRetryLifecycleExact && structuralRetryWaitStoreExact && + !structuralRetryMutationConflict + val structuralRetryAccepted = + io.structuralRetryValid && structuralRetryReady + assert(!(io.structuralRetryValid && io.attemptRebindValid), + "ordinary and structural load rebind requests must be arbitrated upstream") + + val externalForwardResultActive = + useExternalForwardResult.B && io.forwardResultValid + val forwardResultRetryByRecovery = externalForwardResultActive && + forwardResultExactCandidate && flushCycle + val forwardResultRetryByMutationConflict = externalForwardResultActive && + forwardResultExactCandidate && !flushCycle && + externalForwardResultMutationConflict + val forwardResultRetryRequired = + forwardResultRetryByRecovery || forwardResultRetryByMutationConflict + io.forwardResultAccepted := externalForwardResultActive && e4UpdateValid + io.forwardResultRejected := externalForwardResultActive && !e4UpdateValid + io.forwardResultRejectedByLoadId := externalForwardResultActive && + (!forwardResultLoadIdWellFormed || !forwardResultLoadIdExact) + io.forwardResultRejectedByAttempt := externalForwardResultActive && + forwardResultLoadIdExact && !forwardResultAttemptExact + io.forwardResultRejectedByPipe := externalForwardResultActive && + forwardResultLoadIdExact && forwardResultAttemptExact && + !forwardResultPipeExact + io.forwardResultRejectedByLifecycle := externalForwardResultActive && + forwardResultLoadIdExact && forwardResultAttemptExact && + forwardResultPipeExact && (!forwardResultLifecycleReady || flushCycle || + externalForwardResultMutationConflict) + io.forwardResultRejectedPermanent := io.forwardResultRejected && + !forwardResultRetryRequired + io.forwardResultRetryRequired := forwardResultRetryRequired + io.forwardResultRetryByRecovery := forwardResultRetryByRecovery + io.forwardResultRetryByMutationConflict := + forwardResultRetryByMutationConflict val lhqRecord = Wire(new LoadHitRecord( liqEntries, idEntries, addrWidth, lineBytes, sizeWidth, pcWidth, lsidWidth)) lhqRecord := zeroHitRecord - lhqRecord.loadId := rows(e4Index).loadId - lhqRecord.bid := rows(e4Index).bid - lhqRecord.gid := rows(e4Index).gid - lhqRecord.rid := rows(e4Index).rid - lhqRecord.loadLsId := rows(e4Index).loadLsId - lhqRecord.loadLsIdFullValid := rows(e4Index).loadLsIdFullValid - lhqRecord.loadLsIdFull := rows(e4Index).loadLsIdFull - lhqRecord.attempt := rows(e4Index).attempt - lhqRecord.pc := rows(e4Index).pc - lhqRecord.addr := rows(e4Index).addr - lhqRecord.lineAddr := lineAddr(activeAddr(rows(e4Index))) - lhqRecord.size := rows(e4Index).size - lhqRecord.byteMask := pipeline.io.e4LoadByteMask - lhqRecord.data := pipeline.io.e4LineData - lhqRecord.forwardedMask := pipeline.io.e4ForwardMask + lhqRecord.loadId := forwardResultRow.loadId + lhqRecord.bid := forwardResultRow.bid + lhqRecord.gid := forwardResultRow.gid + lhqRecord.rid := forwardResultRow.rid + lhqRecord.loadLsId := forwardResultRow.loadLsId + lhqRecord.loadLsIdFullValid := forwardResultRow.loadLsIdFullValid + lhqRecord.loadLsIdFull := forwardResultRow.loadLsIdFull + lhqRecord.attempt := forwardResultRow.attempt + lhqRecord.pc := forwardResultRow.pc + lhqRecord.addr := forwardResultRow.addr + lhqRecord.lineAddr := lineAddr(activeAddr(forwardResultRow)) + lhqRecord.size := forwardResultRow.size + lhqRecord.byteMask := selectedForwardResult.loadByteMask + lhqRecord.data := selectedForwardResult.lineData + lhqRecord.forwardedMask := selectedForwardResult.forwardMask val rowMutationPath = Module(new LoadInflightRowMutationPath( liqEntries = liqEntries, @@ -673,7 +968,8 @@ class LoadInflightQueue( rowMutationPath.io.nextStoreSourceReturned := io.rowMutationNextStoreSourceReturned rowMutationPath.io.allowWaitTarget := io.rowMutationAllowWaitTarget rowMutationPath.io.requireScbReturned := io.rowMutationRequireScbReturned - rowMutationPath.io.e4UpdateConflict := e4UpdateValid && (e4Index === io.rowMutationTargetIndex) + rowMutationPath.io.e4UpdateConflict := + e4UpdateValid && (forwardResultIndex === io.rowMutationTargetIndex) rowMutationPath.io.clearResolvedConflict := clearResolvedAccepted && (io.clearResolvedIndex === io.rowMutationTargetIndex) rowMutationPath.io.replayWakeConflict := io.replayWakeValid && rowMutationReplayConflictVec(io.rowMutationTargetIndex) rowMutationPath.io.refillConflict := io.refillValid && rowMutationRefillConflictVec(io.rowMutationTargetIndex) @@ -705,97 +1001,107 @@ class LoadInflightQueue( residentCount := 0.U allocPtr := 0.U allocWrap := false.B - e3IndexValid := false.B - e4IndexValid := false.B }.otherwise { - e4IndexValid := e3IndexValid - e4Index := e3Index - e3IndexValid := launchAccepted - e3Index := io.launchIndex - when(e4UpdateValid) { - rows(e4Index).lineData := pipeline.io.e4LineData - rows(e4Index).validMask := pipeline.io.e4ValidMask - rows(e4Index).loadByteMask := pipeline.io.e4LoadByteMask - rows(e4Index).forwardMask := pipeline.io.e4ForwardMask - rows(e4Index).waitMask := pipeline.io.e4WaitMask - rows(e4Index).dataComplete := pipeline.io.e4DataComplete - rows(e4Index).sourcesReturned := pipeline.io.e4SourcesReturned - rows(e4Index).scbReturned := pipeline.io.e4ScbReturned - rows(e4Index).stqReturned := pipeline.io.e4StqReturned - rows(e4Index).missKind := pipeline.io.e4MissKind - rows(e4Index).storeBypass := pipeline.io.e4ForwardMask.orR + rows(forwardResultIndex).forwardPending := false.B + rows(forwardResultIndex).lineData := selectedForwardResult.lineData + rows(forwardResultIndex).validMask := selectedForwardResult.validMask + rows(forwardResultIndex).loadByteMask := + selectedForwardResult.loadByteMask + rows(forwardResultIndex).forwardMask := + selectedForwardResult.forwardMask + rows(forwardResultIndex).waitMask := selectedForwardResult.waitMask + rows(forwardResultIndex).dataComplete := + selectedForwardResult.dataComplete + rows(forwardResultIndex).sourcesReturned := + selectedForwardResult.sourcesReturned + rows(forwardResultIndex).scbReturned := + selectedForwardResult.scbReturned + rows(forwardResultIndex).stqReturned := + selectedForwardResult.stqReturned + rows(forwardResultIndex).missKind := selectedForwardResult.missKind + rows(forwardResultIndex).storeBypass := + selectedForwardResult.forwardMask.orR when(e4FirstSegmentResolved) { - rows(e4Index).status := LoadInflightStatus.Wait - rows(e4Index).secondSegmentActive := true.B - rows(e4Index).firstSegmentDone := true.B - rows(e4Index).firstLineData := pipeline.io.e4LineData - rows(e4Index).firstValidMask := pipeline.io.e4ValidMask - rows(e4Index).firstLoadByteMask := pipeline.io.e4LoadByteMask - rows(e4Index).firstForwardMask := pipeline.io.e4ForwardMask - rows(e4Index).lineData := 0.U - rows(e4Index).validMask := 0.U - rows(e4Index).loadByteMask := 0.U - rows(e4Index).forwardMask := 0.U - rows(e4Index).waitMask := 0.U - rows(e4Index).dataComplete := false.B - rows(e4Index).sourcesReturned := false.B - rows(e4Index).scbReturned := false.B - rows(e4Index).stqReturned := false.B - rows(e4Index).waitStore := false.B - rows(e4Index).waitStoreInfo := zeroWait - rows(e4Index).l1Hit := false.B - rows(e4Index).l1Miss := false.B - rows(e4Index).missKind := LoadForwardMissKind.NoMiss + rows(forwardResultIndex).status := LoadInflightStatus.Wait + rows(forwardResultIndex).repickRequired := false.B + rows(forwardResultIndex).secondSegmentActive := true.B + rows(forwardResultIndex).firstSegmentDone := true.B + rows(forwardResultIndex).firstLineData := selectedForwardResult.lineData + rows(forwardResultIndex).firstValidMask := + selectedForwardResult.validMask + rows(forwardResultIndex).firstLoadByteMask := + selectedForwardResult.loadByteMask + rows(forwardResultIndex).firstForwardMask := + selectedForwardResult.forwardMask + rows(forwardResultIndex).lineData := 0.U + rows(forwardResultIndex).validMask := 0.U + rows(forwardResultIndex).loadByteMask := 0.U + rows(forwardResultIndex).forwardMask := 0.U + rows(forwardResultIndex).waitMask := 0.U + rows(forwardResultIndex).dataComplete := false.B + rows(forwardResultIndex).sourcesReturned := false.B + rows(forwardResultIndex).scbReturned := false.B + rows(forwardResultIndex).stqReturned := false.B + rows(forwardResultIndex).waitStore := false.B + rows(forwardResultIndex).waitStoreInfo := zeroWait + rows(forwardResultIndex).l1Hit := false.B + rows(forwardResultIndex).l1Miss := false.B + rows(forwardResultIndex).missKind := LoadForwardMissKind.NoMiss }.elsewhen(e4Resolved) { // Preserve the E4 hit as Repick until the return owner publishes its // LRET and markResolved accepts the terminal row state. - rows(e4Index).status := LoadInflightStatus.Repick - rows(e4Index).waitStore := false.B - rows(e4Index).waitStoreInfo := zeroWait - rows(e4Index).l1Hit := false.B - rows(e4Index).l1Miss := false.B + rows(forwardResultIndex).status := LoadInflightStatus.Repick + rows(forwardResultIndex).repickRequired := false.B + rows(forwardResultIndex).waitStore := false.B + rows(forwardResultIndex).waitStoreInfo := zeroWait + rows(forwardResultIndex).l1Hit := false.B + rows(forwardResultIndex).l1Miss := false.B }.elsewhen(e4StoreWait) { - rows(e4Index).status := LoadInflightStatus.Wait - rows(e4Index).waitStore := true.B - rows(e4Index).waitStoreInfo := pipeline.io.e4WaitStore - rows(e4Index).validMask := 0.U - rows(e4Index).loadByteMask := 0.U - rows(e4Index).forwardMask := 0.U - rows(e4Index).waitMask := 0.U - rows(e4Index).dataComplete := false.B - rows(e4Index).sourcesReturned := false.B - rows(e4Index).scbReturned := false.B - rows(e4Index).stqReturned := false.B - rows(e4Index).l1Hit := false.B + rows(forwardResultIndex).status := LoadInflightStatus.Wait + rows(forwardResultIndex).repickRequired := false.B + rows(forwardResultIndex).waitStore := true.B + rows(forwardResultIndex).waitStoreInfo := + selectedForwardResult.waitStore + rows(forwardResultIndex).validMask := 0.U + rows(forwardResultIndex).loadByteMask := 0.U + rows(forwardResultIndex).forwardMask := 0.U + rows(forwardResultIndex).waitMask := 0.U + rows(forwardResultIndex).dataComplete := false.B + rows(forwardResultIndex).sourcesReturned := false.B + rows(forwardResultIndex).scbReturned := false.B + rows(forwardResultIndex).stqReturned := false.B + rows(forwardResultIndex).l1Hit := false.B }.elsewhen(e4DataMiss) { - rows(e4Index).status := LoadInflightStatus.L1DcMiss - rows(e4Index).waitStore := false.B - rows(e4Index).waitStoreInfo := zeroWait - rows(e4Index).validMask := 0.U - rows(e4Index).loadByteMask := 0.U - rows(e4Index).forwardMask := 0.U - rows(e4Index).waitMask := 0.U - rows(e4Index).dataComplete := false.B - rows(e4Index).sourcesReturned := false.B - rows(e4Index).scbReturned := false.B - rows(e4Index).stqReturned := false.B - rows(e4Index).l1Hit := false.B - rows(e4Index).l1Miss := true.B + rows(forwardResultIndex).status := LoadInflightStatus.L1DcMiss + rows(forwardResultIndex).repickRequired := false.B + rows(forwardResultIndex).waitStore := false.B + rows(forwardResultIndex).waitStoreInfo := zeroWait + rows(forwardResultIndex).validMask := 0.U + rows(forwardResultIndex).loadByteMask := 0.U + rows(forwardResultIndex).forwardMask := 0.U + rows(forwardResultIndex).waitMask := 0.U + rows(forwardResultIndex).dataComplete := false.B + rows(forwardResultIndex).sourcesReturned := false.B + rows(forwardResultIndex).scbReturned := false.B + rows(forwardResultIndex).stqReturned := false.B + rows(forwardResultIndex).l1Hit := false.B + rows(forwardResultIndex).l1Miss := true.B }.elsewhen(e4ReplayWait) { - rows(e4Index).status := LoadInflightStatus.Wait - rows(e4Index).waitStore := false.B - rows(e4Index).waitStoreInfo := zeroWait - rows(e4Index).validMask := 0.U - rows(e4Index).loadByteMask := 0.U - rows(e4Index).forwardMask := 0.U - rows(e4Index).waitMask := 0.U - rows(e4Index).dataComplete := false.B - rows(e4Index).sourcesReturned := false.B - rows(e4Index).scbReturned := false.B - rows(e4Index).stqReturned := false.B - rows(e4Index).l1Hit := false.B + rows(forwardResultIndex).status := LoadInflightStatus.Wait + rows(forwardResultIndex).repickRequired := true.B + rows(forwardResultIndex).waitStore := false.B + rows(forwardResultIndex).waitStoreInfo := zeroWait + rows(forwardResultIndex).validMask := 0.U + rows(forwardResultIndex).loadByteMask := 0.U + rows(forwardResultIndex).forwardMask := 0.U + rows(forwardResultIndex).waitMask := 0.U + rows(forwardResultIndex).dataComplete := false.B + rows(forwardResultIndex).sourcesReturned := false.B + rows(forwardResultIndex).scbReturned := false.B + rows(forwardResultIndex).stqReturned := false.B + rows(forwardResultIndex).l1Hit := false.B } } @@ -833,9 +1139,11 @@ class LoadInflightQueue( when(io.refillValid) { for (idx <- 0 until liqEntries) { - val sameRowResolvedAtE4 = e4SegmentResolved && (e4Index === idx.U) + val sameRowResolvedAtE4 = + e4SegmentResolved && (forwardResultIndex === idx.U) when(refillWakeup.io.wakeMask(idx) && !sameRowResolvedAtE4) { rows(idx).status := LoadInflightStatus.Wait + rows(idx).repickRequired := false.B rows(idx).lineData := io.refill.data rows(idx).validMask := refillWakeup.io.lineValidMask rows(idx).loadByteMask := refillWakeup.io.requestByteMasks(idx) @@ -853,12 +1161,15 @@ class LoadInflightQueue( when(launchAccepted) { rows(io.launchIndex).status := LoadInflightStatus.Repick + rows(io.launchIndex).repickRequired := false.B rows(io.launchIndex).waitStore := false.B rows(io.launchIndex).missKind := LoadForwardMissKind.NoMiss + rows(io.launchIndex).forwardPending := true.B } when(pickAccepted && !(launchAccepted && (io.launchIndex === io.pickIndex))) { rows(io.pickIndex).status := LoadInflightStatus.Repick + rows(io.pickIndex).repickRequired := false.B rows(io.pickIndex).waitStore := false.B rows(io.pickIndex).missKind := LoadForwardMissKind.NoMiss } @@ -869,6 +1180,7 @@ class LoadInflightQueue( when(markResolvedAccepted) { rows(io.markResolvedIndex).status := LoadInflightStatus.Resolved + rows(io.markResolvedIndex).repickRequired := false.B rows(io.markResolvedIndex).waitStore := false.B rows(io.markResolvedIndex).missKind := LoadForwardMissKind.NoMiss } @@ -924,19 +1236,46 @@ class LoadInflightQueue( } when(attemptRebindAccepted) { - rows(io.attemptRebind.loadId.value).attempt := io.attemptRebind.next + val index = io.attemptRebind.loadId.value + rows(index) := LoadAttemptRebindTransition.next( + rows(index), io.attemptRebind.next) + } + + when(structuralRetryAccepted) { + rows(structuralRetryIndex).status := LoadInflightStatus.Wait + rows(structuralRetryIndex).repickRequired := false.B + rows(structuralRetryIndex).attempt := io.structuralRetry.next + rows(structuralRetryIndex).forwardPending := false.B + rows(structuralRetryIndex).lineData := 0.U + rows(structuralRetryIndex).validMask := 0.U + rows(structuralRetryIndex).loadByteMask := 0.U + rows(structuralRetryIndex).forwardMask := 0.U + rows(structuralRetryIndex).waitMask := 0.U + rows(structuralRetryIndex).waitStore := io.structuralRetry.waitStore + rows(structuralRetryIndex).waitStoreInfo := + Mux(io.structuralRetry.waitStore, + io.structuralRetry.waitStoreInfo, zeroWait) + rows(structuralRetryIndex).storeBypass := false.B + rows(structuralRetryIndex).dataComplete := false.B + rows(structuralRetryIndex).sourcesReturned := false.B + rows(structuralRetryIndex).scbReturned := false.B + rows(structuralRetryIndex).stqReturned := false.B + rows(structuralRetryIndex).l1Hit := false.B + rows(structuralRetryIndex).l1Miss := false.B + rows(structuralRetryIndex).missKind := LoadForwardMissKind.NoMiss } residentCount := residentCount + allocAccepted.asUInt - clearResolvedAccepted.asUInt when(io.preciseFlush.req.valid) { for (idx <- 0 until liqEntries) { - val pipelineResident = - (e3IndexValid && (e3Index === idx.U)) || (e4IndexValid && (e4Index === idx.U)) + val pipelineResident = forwardPipelineResidentMask(idx) when(flushPruneVec(idx)) { rows(idx) := zeroRow }.elsewhen(pipelineResident && rows(idx).valid && (rows(idx).status === LoadInflightStatus.Repick)) { rows(idx).status := LoadInflightStatus.Wait + rows(idx).repickRequired := false.B + rows(idx).forwardPending := false.B rows(idx).dataComplete := false.B rows(idx).sourcesReturned := false.B rows(idx).scbReturned := false.B @@ -952,8 +1291,6 @@ class LoadInflightQueue( } } residentCount := residentCount - flushPruneCount - e3IndexValid := false.B - e4IndexValid := false.B when(flushPruneMask.orR) { val firstPruned = PriorityEncoder(flushPruneMask) allocPtr := firstPruned @@ -976,8 +1313,10 @@ class LoadInflightQueue( assert(!rows(idx).valid || !rows(idx).firstSegmentDone || rows(idx).crossLine, "first-segment completion is legal only for a cross-line scalar load") occupiedVec(idx) := rows(idx).valid - waitVec(idx) := rows(idx).valid && (status === LoadInflightStatus.Wait) - repickVec(idx) := rows(idx).valid && (status === LoadInflightStatus.Repick) + waitVec(idx) := rows(idx).valid && + (status === LoadInflightStatus.Wait) && !rows(idx).repickRequired + repickVec(idx) := rows(idx).valid && + (status === LoadInflightStatus.Wait) && rows(idx).repickRequired missVec(idx) := rows(idx).valid && ((status === LoadInflightStatus.L1DcMiss) || (status === LoadInflightStatus.L2Wait)) resolvedVec(idx) := rows(idx).valid && (status === LoadInflightStatus.Resolved) waitStoreVec(idx) := rows(idx).valid && rows(idx).waitStore @@ -1008,6 +1347,34 @@ class LoadInflightQueue( io.attemptRebindValid && !flushCycle && attemptRebindRow.valid && attemptRebindLoadIdValid && attemptRebindLifecycleReady && !attemptRebindLaunchConflict && attemptRebindCurrentExact && !attemptRebindNextExact + io.structuralRetryReady := structuralRetryReady + io.structuralRetryAccepted := structuralRetryAccepted + io.structuralRetryBlockedByLoadId := io.structuralRetryValid && + !flushCycle && !structuralRetryLoadIdExact + io.structuralRetryBlockedByAttempt := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + !structuralRetryAttemptExact + io.structuralRetryBlockedByNextAttempt := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + structuralRetryAttemptExact && !structuralRetryNextExact + io.structuralRetryBlockedByPipe := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + structuralRetryAttemptExact && structuralRetryNextExact && + !structuralRetryPipeExact + io.structuralRetryBlockedByLifecycle := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + structuralRetryAttemptExact && structuralRetryNextExact && + structuralRetryPipeExact && !structuralRetryLifecycleExact + io.structuralRetryBlockedByWaitStore := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + structuralRetryAttemptExact && structuralRetryNextExact && + structuralRetryPipeExact && structuralRetryLifecycleExact && + !structuralRetryWaitStoreExact + io.structuralRetryBlockedByMutation := io.structuralRetryValid && + !flushCycle && structuralRetryLoadIdExact && + structuralRetryAttemptExact && structuralRetryNextExact && + structuralRetryPipeExact && structuralRetryLifecycleExact && + structuralRetryWaitStoreExact && structuralRetryMutationConflict io.launchReady := launchReady io.launchAccepted := launchAccepted io.pickReady := pickReady @@ -1045,11 +1412,12 @@ class LoadInflightQueue( io.refillAccepted := refillWakeup.io.refillAccepted io.refillWakeMask := refillWakeup.io.wakeMask io.e4UpdateValid := e4UpdateValid - io.e4UpdateIndex := e4Index - io.e4MissKind := pipeline.io.e4MissKind + io.e4UpdateIndex := forwardResultIndex + io.e4MissKind := selectedForwardResult.missKind io.e4WakeupValid := e4Resolved io.lhqRecordValid := e4Resolved - assert(!e4Resolved || !rows(e4Index).crossLine || rows(e4Index).firstSegmentDone, + assert(!e4Resolved || !forwardResultRow.crossLine || + forwardResultRow.firstSegmentDone, "cross-line scalar publication requires a retained first segment") io.lhqRecord := lhqRecord io.occupiedMask := occupiedVec.asUInt diff --git a/chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala b/chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala index 4bcc056e..de4f1163 100644 --- a/chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala +++ b/chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala @@ -17,6 +17,8 @@ class LoadMissDependent( val valid = Bool() val loadIndex = UInt(log2Ceil(liqEntries).W) val loadId = new ROBID(liqEntries) + val attempt = new LoadAttemptIdentity + val returnPipeIndex = UInt(LoadAttemptIdentity.IndexWidth.W) val peId = UInt(peIdWidth.W) val stid = UInt(stidWidth.W) val tid = UInt(tidWidth.W) @@ -90,6 +92,13 @@ class LoadMissQueueIO( val flush = Input(Bool()) val preciseFlush = Input(new FlushBus(idEntries, peIdWidth, stidWidth, tidWidth, lsidWidth)) + val cancelValid = Input(Bool()) + val cancelLoadId = Input(new ROBID(liqEntries)) + val cancelAttempt = Input(new LoadAttemptIdentity) + val cancelReturnPipeIndex = Input(UInt(LoadAttemptIdentity.IndexWidth.W)) + val cancelReady = Output(Bool()) + val cancelAccepted = Output(Bool()) + val missValid = Input(Bool()) val missIndex = Input(UInt(log2Ceil(liqEntries).W)) val missRow = Input(new LoadInflightRow( @@ -226,6 +235,8 @@ class LoadMissQueue( a.valid && a.loadIndex === index && ROBID.equal(a.loadId, row.loadId) && + LoadAttemptIdentity.equal(a.attempt, row.attempt) && + a.returnPipeIndex === row.returnPipeIndex && a.peId === row.peId && a.stid === row.stid && a.tid === row.tid && @@ -264,16 +275,38 @@ class LoadMissQueue( val responseMatchCount = PopCount(responseMatchVec) val responseUniqueMatch = responseMatchCount === 1.U val responseMatchIndex = PriorityEncoder(responseMatchMask) - val responseNeedsRefill = io.responseValid && responseUniqueMatch && io.response.isRead + val responseEntryHasDependents = responseUniqueMatch && + entries(responseMatchIndex).dependents.map(_.valid).reduce(_ || _) + val responseNeedsRefill = io.responseValid && responseUniqueMatch && + responseEntryHasDependents && io.response.isRead val responseAccepted = io.responseValid && io.responseReady - val responseReadMatch = responseAccepted && responseUniqueMatch && io.response.isRead - val responseFree = responseReadMatch + val responseReadAccepted = responseAccepted && responseUniqueMatch && io.response.isRead + val responseReadMatch = responseReadAccepted && responseEntryHasDependents + val responseFree = responseReadAccepted + + val cancelMatchVec = Wire(Vec(missEntries, Bool())) + for (idx <- 0 until missEntries) { + val dependent = entries(idx).dependents(io.cancelLoadId.value) + cancelMatchVec(idx) := io.cancelLoadId.valid && dependent.valid && + ROBID.equal(dependent.loadId, io.cancelLoadId) && + LoadAttemptIdentity.equal(dependent.attempt, io.cancelAttempt) && + dependent.returnPipeIndex === io.cancelReturnPipeIndex + } + val cancelMatchCount = PopCount(cancelMatchVec) + val cancelMatchIndex = PriorityEncoder(cancelMatchVec) + val cancelResponseConflict = io.responseValid && responseUniqueMatch && + responseMatchIndex === cancelMatchIndex + val cancelReady = !flushCycle && cancelMatchCount === 1.U && + !cancelResponseConflict + val cancelAccepted = io.cancelValid && cancelReady val existingVec = Wire(Vec(missEntries, Bool())) val freeVec = Wire(Vec(missEntries, Bool())) for (idx <- 0 until missEntries) { + val hasDependents = entries(idx).dependents.map(_.valid).reduce(_ || _) existingVec(idx) := entries(idx).valid && + hasDependents && entries(idx).lineAddr === candidateLineAddr && !(responseFree && responseMatchIndex === idx.U) freeVec(idx) := !entries(idx).valid @@ -292,6 +325,8 @@ class LoadMissQueue( candidateDependent.valid := candidateUsable candidateDependent.loadIndex := io.missIndex candidateDependent.loadId := io.missRow.loadId + candidateDependent.attempt := io.missRow.attempt + candidateDependent.returnPipeIndex := io.missRow.returnPipeIndex candidateDependent.peId := io.missRow.peId candidateDependent.stid := io.missRow.stid candidateDependent.tid := io.missRow.tid @@ -385,6 +420,10 @@ class LoadMissQueue( } } }.otherwise { + when(cancelAccepted) { + entries(cancelMatchIndex).dependents(io.cancelLoadId.value).valid := false.B + } + when(requestAccepted) { entries(issueHeadIndex).issued := true.B } @@ -446,6 +485,8 @@ class LoadMissQueue( io.missBlockedByCapacity := candidateUsable && !flushCycle && !indexCollision && !responseSatisfiesCandidate && !canCoalesce && !canAllocate io.missBlockedByIndexCollision := candidateUsable && indexCollision + io.cancelReady := cancelReady + io.cancelAccepted := cancelAccepted io.requestAccepted := requestAccepted io.requestDroppedNoDependents := requestDropped && issueHead.valid && !issueHead.issued io.responseAccepted := responseAccepted diff --git a/chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala b/chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala index bf15a537..5377f0a3 100644 --- a/chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala +++ b/chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala @@ -17,11 +17,18 @@ class LoadMissQueueProbeIO extends Bundle { val missStid = Input(UInt(2.W)) val missBid = Input(UInt(3.W)) val missLsIdFull = Input(UInt(40.W)) + val missAttemptGeneration = Input(UInt(32.W)) val missReady = Output(Bool()) val missAccepted = Output(Bool()) val missAllocated = Output(Bool()) val missCoalesced = Output(Bool()) + val cancelValid = Input(Bool()) + val cancelIndex = Input(UInt(3.W)) + val cancelAttemptGeneration = Input(UInt(32.W)) + val cancelReady = Output(Bool()) + val cancelAccepted = Output(Bool()) + val requestReady = Input(Bool()) val requestValid = Output(Bool()) val requestAccepted = Output(Bool()) @@ -76,6 +83,16 @@ class LoadMissQueueProbe extends Module { preciseFlush.baseOnBid := true.B queue.io.flush := io.hardFlush queue.io.preciseFlush := preciseFlush + queue.io.cancelValid := io.cancelValid + queue.io.cancelLoadId := 0.U.asTypeOf(queue.io.cancelLoadId) + queue.io.cancelLoadId.valid := io.cancelValid + queue.io.cancelLoadId.value := io.cancelIndex + queue.io.cancelAttempt := 0.U.asTypeOf(queue.io.cancelAttempt) + queue.io.cancelAttempt.valid := true.B + queue.io.cancelAttempt.producer.valid := true.B + queue.io.cancelAttempt.producer.nativeBidValid := true.B + queue.io.cancelAttempt.generation := io.cancelAttemptGeneration + queue.io.cancelReturnPipeIndex := 0.U val row = Wire(chiselTypeOf(queue.io.missRow)) row := 0.U.asTypeOf(row) @@ -84,6 +101,10 @@ class LoadMissQueueProbe extends Module { row.loadId.valid := io.missValid row.loadId.wrap := false.B row.loadId.value := io.missIndex + row.attempt.valid := true.B + row.attempt.producer.valid := true.B + row.attempt.producer.nativeBidValid := true.B + row.attempt.generation := io.missAttemptGeneration row.peId := 0.U row.stid := io.missStid row.tid := io.missStid @@ -120,6 +141,8 @@ class LoadMissQueueProbe extends Module { io.missAccepted := queue.io.missAccepted io.missAllocated := queue.io.missAllocated io.missCoalesced := queue.io.missCoalesced + io.cancelReady := queue.io.cancelReady + io.cancelAccepted := queue.io.cancelAccepted io.requestValid := queue.io.requestValid io.requestAccepted := queue.io.requestAccepted io.requestMissSlot := queue.io.request.missId.value diff --git a/chisel/src/main/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControl.scala b/chisel/src/main/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControl.scala deleted file mode 100644 index 0240b309..00000000 --- a/chisel/src/main/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControl.scala +++ /dev/null @@ -1,48 +0,0 @@ -package linxcore.lsu - -import chisel3._ - -class LoadReplayReturnReducedScalarShapeControlIO(val countWidth: Int = 8) - extends Bundle { - val enable = Input(Bool()) - val flush = Input(Bool()) - - val active = Output(Bool()) - val reducedScalarShapeValid = Output(Bool()) - val reducedSingleLane = Output(Bool()) - val scalarLoadPair = Output(Bool()) - val vectorOrMemMultiLane = Output(Bool()) - val retLaneBefore = Output(UInt(countWidth.W)) - val returnedLaneCount = Output(UInt(countWidth.W)) - val realReqCnt = Output(UInt(countWidth.W)) - val isMemIex = Output(Bool()) - val isTload = Output(Bool()) - val subInstCntBefore = Output(UInt(countWidth.W)) - val isVectorMachine = Output(Bool()) - val blockedByDisabled = Output(Bool()) - val blockedByFlush = Output(Bool()) -} - -class LoadReplayReturnReducedScalarShapeControl(val countWidth: Int = 8) - extends Module { - require(countWidth > 0, "countWidth must be positive") - - val io = IO(new LoadReplayReturnReducedScalarShapeControlIO(countWidth)) - - val active = io.enable && !io.flush - - io.active := active - io.reducedScalarShapeValid := active - io.reducedSingleLane := true.B - io.scalarLoadPair := false.B - io.vectorOrMemMultiLane := false.B - io.retLaneBefore := 0.U - io.returnedLaneCount := 1.U - io.realReqCnt := 1.U - io.isMemIex := false.B - io.isTload := false.B - io.subInstCntBefore := 0.U - io.isVectorMachine := false.B - io.blockedByDisabled := !io.enable - io.blockedByFlush := io.enable && io.flush -} diff --git a/chisel/src/main/scala/linxcore/lsu/LoadStructuralBlockPolicy.scala b/chisel/src/main/scala/linxcore/lsu/LoadStructuralBlockPolicy.scala new file mode 100644 index 00000000..37138c9e --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/LoadStructuralBlockPolicy.scala @@ -0,0 +1,207 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{Decoupled, log2Ceil} + +object LoadStructuralBlockDisposition extends ChiselEnum { + val WaitStore, RetrySnapshot, Unsupported = Value +} + +object LoadStructuralBlockReason { + val Width = 8 + val UnknownOlder = 0 + val StaleSnapshot = 1 + val FullLsIdMissing = 2 + val FullLsIdAmbiguous = 3 + val CrossLineStore = 4 + val QueryIdentityInvalid = 5 + val LoadCrossesLine = 6 + val InvalidStructuralShape = 7 +} + +/** Compact retry transaction produced from one retained structural forwarding + * result. It carries only lifecycle identity and the optional exact store + * wakeup key; forwarding data remains owned by the normal E3/E4 path. + */ +class LoadStructuralBlockRetry( + val robEntries: Int, + val stqEntries: Int, + val pcWidth: Int = 64, + val lsidWidth: Int = 32) extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val current = new LoadAttemptIdentity + val next = new LoadAttemptIdentity + val returnPipeIndex = UInt(STQLoadForwardQuery.ReturnPipeIndexWidth.W) + val waitStore = Bool() + val waitStoreInfo = new LoadStoreForwardWait( + robEntries, stqEntries, pcWidth, lsidWidth) +} + +class LoadStructuralBlockPolicyIO( + val robEntries: Int, + val stqEntries: Int, + val addrWidth: Int, + val stidWidth: Int, + val pcWidth: Int, + val lineBytes: Int, + val lsidWidth: Int, + val tokenWidth: Int) extends Bundle { + val hardFlush = Input(Bool()) + val recoveryKill = Input(Bool()) + val recoveryFire = Input(Bool()) + val hardBlock = Flipped(Decoupled(new STQLoadForwardResponse( + robEntries, stqEntries, addrWidth, stidWidth, pcWidth, lineBytes, + lsidWidth, tokenWidth))) + val retry = Decoupled(new LoadStructuralBlockRetry( + robEntries, stqEntries, pcWidth, lsidWidth)) + + val pending = Output(Bool()) + val unsupported = Output(Bool()) + val disposition = Output(LoadStructuralBlockDisposition()) + val reason = Output(UInt(LoadStructuralBlockReason.Width.W)) + val loadId = Output(new LoadCanonicalRowIdentity) + val attempt = Output(new LoadAttemptIdentity) + val recoveryReady = Output(Bool()) + val empty = Output(Bool()) + val protocolError = Output(Bool()) +} + +/** Sole retained consumer of structural STQ forwarding uncertainty. + * + * Retryable records can leave only through the canonical OOO/LIQ rebind + * transaction. Unsupported records remain fail closed until hard flush or an + * exact typed recovery proves that their owning load is killed. + */ +class LoadStructuralBlockPolicy( + val robEntries: Int = 64, + val liqEntries: Int = 16, + val stqEntries: Int = 16, + val addrWidth: Int = 64, + val stidWidth: Int = 8, + val pcWidth: Int = 64, + val lineBytes: Int = 64, + val lsidWidth: Int = 32, + val tokenWidth: Int = 64) extends Module { + require(robEntries > 1 && (robEntries & (robEntries - 1)) == 0, + "structural-block policy ROB projection must be a power of two") + LoadCanonicalRowIdentity.requireBridgeFits(liqEntries) + require(stqEntries > 1 && (stqEntries & (stqEntries - 1)) == 0, + "structural-block policy STQ capacity must be a power of two") + require(log2Ceil(stqEntries) <= LoadAttemptIdentity.IndexWidth, + "structural-block store index must fit canonical identity protocol") + + val io = IO(new LoadStructuralBlockPolicyIO( + robEntries, stqEntries, addrWidth, stidWidth, pcWidth, lineBytes, + lsidWidth, tokenWidth)) + + val residentValid = RegInit(false.B) + val residentRetry = Reg(new LoadStructuralBlockRetry( + robEntries, stqEntries, pcWidth, lsidWidth)) + val residentDisposition = RegInit(LoadStructuralBlockDisposition.Unsupported) + val residentReason = RegInit(0.U(LoadStructuralBlockReason.Width.W)) + + val response = io.hardBlock.bits + val unknownOlder = response.unknownOlderMask.orR + val staleSnapshot = response.staleSnapshotMask.orR + val fullLsIdMissing = response.fullLsIdMissingMask.orR + val fullLsIdAmbiguous = response.fullLsIdAmbiguousMask.orR + val crossLineStore = response.crossLineStoreMask.orR + val queryIdentityInvalid = response.queryIdentityInvalid || + !response.query.loadId.valid || + !LoadCanonicalRowIdentity.wellFormed(response.query.loadId, liqEntries) || + !response.query.attempt.valid || + !LoadAttemptIdentity.wellFormed(response.query.attempt) + val unknownWaitExact = response.unknownWaitStore.valid && + response.unknownWaitStore.storeId.valid && + response.unknownWaitStore.storeLsId.valid && + response.unknownWaitStore.storeLsIdFullValid + val invalidStructuralShape = + (unknownOlder && !unknownWaitExact) || + !(unknownOlder || staleSnapshot || fullLsIdMissing || + fullLsIdAmbiguous || crossLineStore || response.loadCrossesLine || + queryIdentityInvalid) + val unsupportedNow = fullLsIdMissing || fullLsIdAmbiguous || + crossLineStore || response.loadCrossesLine || queryIdentityInvalid || + invalidStructuralShape + val dispositionNow = Mux(unsupportedNow, + LoadStructuralBlockDisposition.Unsupported, + Mux(staleSnapshot, + LoadStructuralBlockDisposition.RetrySnapshot, + LoadStructuralBlockDisposition.WaitStore)) + + val reasonNow = Wire(Vec(LoadStructuralBlockReason.Width, Bool())) + reasonNow := VecInit(Seq.fill(LoadStructuralBlockReason.Width)(false.B)) + reasonNow(LoadStructuralBlockReason.UnknownOlder) := unknownOlder + reasonNow(LoadStructuralBlockReason.StaleSnapshot) := staleSnapshot + reasonNow(LoadStructuralBlockReason.FullLsIdMissing) := fullLsIdMissing + reasonNow(LoadStructuralBlockReason.FullLsIdAmbiguous) := fullLsIdAmbiguous + reasonNow(LoadStructuralBlockReason.CrossLineStore) := crossLineStore + reasonNow(LoadStructuralBlockReason.QueryIdentityInvalid) := + queryIdentityInvalid + reasonNow(LoadStructuralBlockReason.LoadCrossesLine) := + response.loadCrossesLine + reasonNow(LoadStructuralBlockReason.InvalidStructuralShape) := + invalidStructuralShape + + io.hardBlock.ready := !residentValid && !io.hardFlush && !io.recoveryFire + io.retry.valid := residentValid && + (residentDisposition =/= LoadStructuralBlockDisposition.Unsupported) && + !io.hardFlush && !io.recoveryFire + io.retry.bits := residentRetry + + when(io.hardFlush) { + residentValid := false.B + }.elsewhen(io.recoveryFire && io.recoveryKill) { + residentValid := false.B + }.elsewhen(io.retry.fire) { + residentValid := false.B + }.elsewhen(io.hardBlock.fire) { + residentValid := true.B + residentDisposition := dispositionNow + residentReason := reasonNow.asUInt + residentRetry := 0.U.asTypeOf(residentRetry) + residentRetry.loadId := response.query.loadId + residentRetry.current := response.query.attempt + residentRetry.next := response.query.attempt + residentRetry.next.generation := response.query.attempt.generation +% 1.U + residentRetry.returnPipeIndex := response.query.returnPipeIndex + residentRetry.waitStore := + dispositionNow === LoadStructuralBlockDisposition.WaitStore + when(dispositionNow === LoadStructuralBlockDisposition.WaitStore) { + residentRetry.waitStoreInfo := response.unknownWaitStore + } + } + + io.pending := residentValid + io.unsupported := residentValid && + residentDisposition === LoadStructuralBlockDisposition.Unsupported + io.disposition := residentDisposition + io.reason := residentReason + io.loadId := residentRetry.loadId + io.attempt := residentRetry.current + io.recoveryReady := !residentValid || io.recoveryKill + io.empty := !residentValid + io.protocolError := io.unsupported + + when(io.retry.valid) { + assert(LoadCanonicalRowIdentity.wellFormed( + io.retry.bits.loadId, liqEntries), + "structural retry must retain a well-formed canonical load ID") + assert(LoadAttemptIdentity.wellFormed(io.retry.bits.current) && + LoadAttemptIdentity.wellFormed(io.retry.bits.next), + "structural retry attempts must remain well formed") + assert(io.retry.bits.next.producer.asUInt === + io.retry.bits.current.producer.asUInt && + io.retry.bits.next.generation === + (io.retry.bits.current.generation +% 1.U), + "structural retry must preserve producer and increment generation once") + assert(!io.retry.bits.waitStore || + (io.retry.bits.waitStoreInfo.valid && + io.retry.bits.waitStoreInfo.storeId.valid && + io.retry.bits.waitStoreInfo.storeLsId.valid && + io.retry.bits.waitStoreInfo.storeLsIdFullValid), + "wait-store structural retry requires an exact full-LSID wakeup key") + } + assert(!io.unsupported || !io.retry.valid, + "unsupported structural state must never dequeue as an ordinary retry") +} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLiveLoadLiqCapture.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLiveLoadLiqCapture.scala deleted file mode 100644 index c7ea0aeb..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLiveLoadLiqCapture.scala +++ /dev/null @@ -1,125 +0,0 @@ -package linxcore.lsu - -import chisel3._ - -import linxcore.commit.{CommitOperandTrace, CommitTraceParams} -import linxcore.rob.ROBID - -/** E1 admission adapter for ordinary scalar loads entering the reduced LIQ. */ -class ReducedLiveLoadLiqCaptureIO( - val idEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - private val sourceTraceParams = - CommitTraceParams(regWidth = math.max(8, archRegWidth), dataWidth = addrWidth) - - val captureEnable = Input(Bool()) - val flush = Input(Bool()) - val loadValid = Input(Bool()) - val loadPc = Input(UInt(pcWidth.W)) - val loadAddr = Input(UInt(addrWidth.W)) - val loadSize = Input(UInt(sizeWidth.W)) - val loadReturnSignExtend = Input(Bool()) - val loadDst = Input(new LoadReplayDestination(archRegWidth, physRegWidth)) - val loadSourceTraceValid = Input(Bool()) - val loadSource0 = Input(new CommitOperandTrace(sourceTraceParams)) - val loadSource1 = Input(new CommitOperandTrace(sourceTraceParams)) - val loadBid = Input(new ROBID(idEntries)) - val loadGid = Input(new ROBID(idEntries)) - val loadRid = Input(new ROBID(idEntries)) - val loadLsId = Input(new ROBID(idEntries)) - val loadLsIdFullValid = Input(Bool()) - val loadLsIdFull = Input(UInt(lsidWidth.W)) - val youngestStoreId = Input(new ROBID(idEntries)) - val youngestStoreLsId = Input(new ROBID(idEntries)) - val youngestStoreLsIdFullValid = Input(Bool()) - val youngestStoreLsIdFull = Input(UInt(lsidWidth.W)) - val allocReady = Input(Bool()) - - val candidateValid = Output(Bool()) - val candidate = Output(new ReducedLoadReplayCandidate( - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth)) - val captureAccepted = Output(Bool()) - val blockedByAlloc = Output(Bool()) -} - -class ReducedLiveLoadLiqCapture( - val idEntries: Int = 16, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Module { - require(idEntries > 1, "idEntries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "idEntries must be a power of two") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - val io = IO(new ReducedLiveLoadLiqCaptureIO( - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth)) - - private def disabledId: ROBID = ROBID.disabled(idEntries) - - val candidate = Wire(new ReducedLoadReplayCandidate( - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth)) - candidate := 0.U.asTypeOf(candidate) - candidate.dst := LoadReplayDestination.none(archRegWidth, physRegWidth) - candidate.bid := disabledId - candidate.gid := disabledId - candidate.rid := disabledId - candidate.loadLsId := disabledId - candidate.youngestStoreId := disabledId - candidate.youngestStoreLsId := disabledId - - val candidateValid = io.captureEnable && !io.flush && io.loadValid - when(candidateValid) { - candidate.valid := true.B - candidate.pc := io.loadPc - candidate.addr := io.loadAddr - candidate.size := io.loadSize - candidate.returnSignExtend := io.loadReturnSignExtend - candidate.dst := io.loadDst - candidate.sourceTraceValid := io.loadSourceTraceValid - candidate.source0 := io.loadSource0 - candidate.source1 := io.loadSource1 - candidate.bid := io.loadBid - candidate.gid := io.loadGid - candidate.rid := io.loadRid - candidate.loadLsId := io.loadLsId - candidate.loadLsIdFullValid := io.loadLsIdFullValid - candidate.loadLsIdFull := io.loadLsIdFull - candidate.youngestStoreId := io.youngestStoreId - candidate.youngestStoreLsId := io.youngestStoreLsId - candidate.youngestStoreLsIdFullValid := io.youngestStoreLsIdFullValid - candidate.youngestStoreLsIdFull := io.youngestStoreLsIdFull - } - - io.candidateValid := candidateValid - io.candidate := candidate - io.captureAccepted := candidateValid && io.allocReady - io.blockedByAlloc := candidateValid && !io.allocReady -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayCompletionDrain.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayCompletionDrain.scala deleted file mode 100644 index 4e1e9002..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayCompletionDrain.scala +++ /dev/null @@ -1,91 +0,0 @@ -package linxcore.lsu - -import chisel3._ - -import linxcore.rob.ROBID - -class ReducedLoadReplayCompletionDrainIO( - val idEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val lsidWidth: Int = 32) - extends Bundle { - val candidateValid = Input(Bool()) - val candidate = Input(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, lsidWidth = lsidWidth)) - - val completeValid = Input(Bool()) - val completeMemLoad = Input(Bool()) - val completePc = Input(UInt(pcWidth.W)) - val completeAddr = Input(UInt(addrWidth.W)) - val completeSize = Input(UInt(sizeWidth.W)) - val completeBid = Input(new ROBID(idEntries)) - val completeGid = Input(new ROBID(idEntries)) - val completeRid = Input(new ROBID(idEntries)) - val completeLsId = Input(new ROBID(idEntries)) - - val consumeReady = Output(Bool()) - val matchValid = Output(Bool()) - val mismatch = Output(Bool()) - val pcMismatch = Output(Bool()) - val addrMismatch = Output(Bool()) - val sizeMismatch = Output(Bool()) - val bidMismatch = Output(Bool()) - val gidMismatch = Output(Bool()) - val ridMismatch = Output(Bool()) - val lsIdMismatch = Output(Bool()) -} - -class ReducedLoadReplayCompletionDrain( - val idEntries: Int = 16, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val lsidWidth: Int = 32) - extends Module { - require(idEntries > 1, "idEntries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "idEntries must be a power of two") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - val io = IO(new ReducedLoadReplayCompletionDrainIO(idEntries, addrWidth, pcWidth, sizeWidth, lsidWidth)) - - val completionEligible = io.completeValid && io.completeMemLoad - val pcMismatch = io.candidate.pc =/= io.completePc - val addrMismatch = io.candidate.addr =/= io.completeAddr - val sizeMismatch = io.candidate.size =/= io.completeSize - val bidMismatch = Seq( - io.candidate.bid.valid =/= io.completeBid.valid, - io.candidate.bid.wrap =/= io.completeBid.wrap, - io.candidate.bid.value =/= io.completeBid.value - ).reduce(_ || _) - val gidMismatch = Seq( - io.candidate.gid.valid =/= io.completeGid.valid, - io.candidate.gid.wrap =/= io.completeGid.wrap, - io.candidate.gid.value =/= io.completeGid.value - ).reduce(_ || _) - val ridMismatch = Seq( - io.candidate.rid.valid =/= io.completeRid.valid, - io.candidate.rid.wrap =/= io.completeRid.wrap, - io.candidate.rid.value =/= io.completeRid.value - ).reduce(_ || _) - val lsIdMismatch = Seq( - io.candidate.loadLsId.valid =/= io.completeLsId.valid, - io.candidate.loadLsId.wrap =/= io.completeLsId.wrap, - io.candidate.loadLsId.value =/= io.completeLsId.value - ).reduce(_ || _) - val anyMismatch = - pcMismatch || addrMismatch || sizeMismatch || bidMismatch || gidMismatch || ridMismatch || lsIdMismatch - val comparable = io.candidateValid && io.candidate.valid && completionEligible - - io.matchValid := comparable && !anyMismatch - io.mismatch := comparable && anyMismatch - io.consumeReady := io.matchValid - io.pcMismatch := comparable && pcMismatch - io.addrMismatch := comparable && addrMismatch - io.sizeMismatch := comparable && sizeMismatch - io.bidMismatch := comparable && bidMismatch - io.gidMismatch := comparable && gidMismatch - io.ridMismatch := comparable && ridMismatch - io.lsIdMismatch := comparable && lsIdMismatch -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala deleted file mode 100644 index e1ca1dd3..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala +++ /dev/null @@ -1,109 +0,0 @@ -package linxcore.lsu - -import chisel3._ - -import linxcore.rob.ROBID - -class ReducedLoadReplayLiqAllocAdapterIO( - val liqEntries: Int, - val idEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - val flush = Input(Bool()) - val candidateValid = Input(Bool()) - val candidate = Input(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - val allocReady = Input(Bool()) - - val allocValid = Output(Bool()) - val alloc = Output(new LoadInflightAlloc( - liqEntries, idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, - lsidWidth = lsidWidth)) - val consumeReady = Output(Bool()) - val blockedByAlloc = Output(Bool()) - val candidateUsable = Output(Bool()) -} - -class ReducedLoadReplayLiqAllocAdapter( - val liqEntries: Int = 16, - val idEntries: Int = 16, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Module { - require(liqEntries > 1, "LIQ entries must be greater than one") - require((liqEntries & (liqEntries - 1)) == 0, "LIQ entries must be a power of two") - require(idEntries > 1, "ID entries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "ID entries must be a power of two") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - val io = IO(new ReducedLoadReplayLiqAllocAdapterIO( - liqEntries, - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth - )) - - private def zeroAlloc: LoadInflightAlloc = { - val alloc = Wire(new LoadInflightAlloc( - liqEntries, idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, - lsidWidth = lsidWidth)) - alloc := 0.U.asTypeOf(alloc) - alloc.dst := LoadReplayDestination.none(archRegWidth, physRegWidth) - alloc.bid := ROBID.disabled(idEntries) - alloc.gid := ROBID.disabled(idEntries) - alloc.rid := ROBID.disabled(idEntries) - alloc.loadLsId := ROBID.disabled(idEntries) - alloc.youngestStoreId := ROBID.disabled(idEntries) - alloc.youngestStoreLsId := ROBID.disabled(idEntries) - alloc - } - - val candidateUsable = io.candidateValid && io.candidate.valid && !io.flush - val alloc = Wire(new LoadInflightAlloc( - liqEntries, idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, - lsidWidth = lsidWidth)) - alloc := zeroAlloc - - when(candidateUsable) { - alloc.dst := io.candidate.dst - alloc.bid := io.candidate.bid - alloc.gid := io.candidate.gid - alloc.rid := io.candidate.rid - alloc.loadLsId := io.candidate.loadLsId - alloc.loadLsIdFullValid := io.candidate.loadLsIdFullValid - alloc.loadLsIdFull := io.candidate.loadLsIdFull - alloc.pc := io.candidate.pc - alloc.addr := io.candidate.addr - alloc.size := io.candidate.size - alloc.returnSignExtend := io.candidate.returnSignExtend - alloc.sourceTraceValid := io.candidate.sourceTraceValid - alloc.source0 := io.candidate.source0 - alloc.source1 := io.candidate.source1 - alloc.youngestStoreId := io.candidate.youngestStoreId - alloc.youngestStoreLsId := io.candidate.youngestStoreLsId - alloc.youngestStoreLsIdFullValid := io.candidate.youngestStoreLsIdFullValid - alloc.youngestStoreLsIdFull := io.candidate.youngestStoreLsIdFull - alloc.isTile := false.B - alloc.specWakeup := false.B - alloc.stackValid := false.B - } - - io.allocValid := candidateUsable - io.alloc := alloc - io.consumeReady := candidateUsable && io.allocReady - io.blockedByAlloc := candidateUsable && !io.allocReady - io.candidateUsable := candidateUsable -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala deleted file mode 100644 index 1a8ea187..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala +++ /dev/null @@ -1,533 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.commit.{CommitOperandTrace, CommitTraceParams} -import linxcore.rob.ROBID -import linxcore.recovery.FlushBus - -class ReducedLoadReplayLiqAllocPathIO( - val liqEntries: Int, - val idEntries: Int, - val storeEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - private val liqPtrWidth = log2Ceil(liqEntries) - private val countWidth = log2Ceil(liqEntries + 1) - private val sourceTraceParams = - CommitTraceParams(regWidth = math.max(8, archRegWidth), dataWidth = addrWidth) - - val flush = Input(Bool()) - val preciseFlush = Input(new FlushBus(idEntries, lsidWidth = lsidWidth)) - val flushPruneMask = Output(UInt(liqEntries.W)) - val flushPruneCount = Output(UInt(countWidth.W)) - val candidateValid = Input(Bool()) - val candidate = Input(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - val allocExternalReady = Input(Bool()) - - val launchEnable = Input(Bool()) - val pickValid = Input(Bool()) - val pickIndex = Input(UInt(liqPtrWidth.W)) - val scbReturnValid = Input(Bool()) - val scbReturnIndex = Input(UInt(liqPtrWidth.W)) - val markResolvedValid = Input(Bool()) - val markResolvedIndex = Input(UInt(liqPtrWidth.W)) - val e2Stores = Input(Vec(storeEntries, new LoadStoreForwardStore( - idEntries, storeEntries, addrWidth, pcWidth, lineBytes, lsidWidth))) - val e2BaseData = Input(UInt((lineBytes * 8).W)) - val e2BaseValidMask = Input(UInt(lineBytes.W)) - val e2LoadDataReturned = Input(Bool()) - val e2ScbReturned = Input(Bool()) - val e2StqReturned = Input(Bool()) - val e2ReturnReady = Input(Bool()) - val replayWakeValid = Input(Bool()) - val replayWake = Input(new LoadReplayWakeupRequest(idEntries, addrWidth, pcWidth, lineBytes, lsidWidth)) - val replayWakeWaitStoreCandidateMask = Output(UInt(liqEntries.W)) - val replayWakeBidMatchMask = Output(UInt(liqEntries.W)) - val replayWakeLsIdMatchMask = Output(UInt(liqEntries.W)) - val replayWakePcMatchMask = Output(UInt(liqEntries.W)) - val replayWakeFullMatchMask = Output(UInt(liqEntries.W)) - val replayWakeStoreUnit = Output(Bool()) - val replayWakeStoreUnitFullMatchMask = Output(UInt(liqEntries.W)) - val replayWakeWaitStoreClearMask = Output(UInt(liqEntries.W)) - val replayWakeMergeMask = Output(UInt(liqEntries.W)) - val replayWakeCompletedMask = Output(UInt(liqEntries.W)) - - val clearResolvedValid = Input(Bool()) - val clearResolvedIndex = Input(UInt(liqPtrWidth.W)) - - val rowMutationRequestValid = Input(Bool()) - val rowMutationRequestTargetMask = Input(UInt(liqEntries.W)) - val rowMutationRequestTargetIndex = Input(UInt(liqPtrWidth.W)) - val rowMutationSetWaitStatus = Input(Bool()) - val rowMutationKeepRepickStatus = Input(Bool()) - val rowMutationClearReturnState = Input(Bool()) - val rowMutationLineWrite = Input(Bool()) - val rowMutationWaitStoreWrite = Input(Bool()) - val rowMutationNextWaitStore = Input(Bool()) - val rowMutationNextWaitStoreInfo = Input(new LoadStoreForwardWait( - idEntries, storeEntries, pcWidth, lsidWidth)) - val rowMutationNextLineData = Input(UInt((lineBytes * 8).W)) - val rowMutationNextValidMask = Input(UInt(lineBytes.W)) - val rowMutationNextDataComplete = Input(Bool()) - val rowMutationNextScbReturned = Input(Bool()) - val rowMutationNextStqReturned = Input(Bool()) - val rowMutationNextStoreSourceReturned = Input(Bool()) - val rowMutationAllowWaitTarget = Input(Bool()) - val rowMutationRequireScbReturned = Input(Bool()) - - val refillValid = Input(Bool()) - val refill = Input(new LoadRefillWakeupRequest(addrWidth, lineBytes)) - val refillAccepted = Output(Bool()) - val refillWakeMask = Output(UInt(liqEntries.W)) - - val rowMutationBridgeValid = Output(Bool()) - val rowMutationSourceStoreIndexFits = Output(Bool()) - val rowMutationInvalidStoreIndexOutOfRange = Output(Bool()) - val rowMutationInvalidConflictingStatusWrite = Output(Bool()) - val rowMutationInvalidWaitStoreWithoutWaitStatus = Output(Bool()) - val rowMutationInvalidReturnWithoutSplitSources = Output(Bool()) - val rowMutationWriteEnable = Output(Bool()) - val rowMutationApplyValid = Output(Bool()) - val rowMutationTargetEvidenceValid = Output(Bool()) - val rowMutationWriteConflict = Output(Bool()) - val rowMutationBlockedByBridge = Output(Bool()) - val rowMutationBlockedByControl = Output(Bool()) - val rowMutationControlBlockedByInvalidRow = Output(Bool()) - val rowMutationControlBlockedByNotRepick = Output(Bool()) - val rowMutationControlBlockedByScbNotReturned = Output(Bool()) - val rowMutationControlBlockedByE4UpdateConflict = Output(Bool()) - val rowMutationControlBlockedByClearResolvedConflict = Output(Bool()) - val rowMutationControlBlockedByReplayWakeConflict = Output(Bool()) - val rowMutationControlBlockedByRefillConflict = Output(Bool()) - val rowMutationControlBlockedByLaunchConflict = Output(Bool()) - val rowMutationControlBlockedByAllocationConflict = Output(Bool()) - - val candidateConsumeReady = Output(Bool()) - val candidateUsable = Output(Bool()) - val candidateBlockedByAlloc = Output(Bool()) - - val allocValid = Output(Bool()) - val allocReady = Output(Bool()) - val allocAccepted = Output(Bool()) - val allocIndex = Output(UInt(liqPtrWidth.W)) - val allocLoadId = Output(new ROBID(liqEntries)) - val allocPayload = Output(new LoadInflightAlloc( - liqEntries, - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - - val rows = Output(Vec( - liqEntries, - new LoadInflightRow( - liqEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - ) - )) - val occupiedMask = Output(UInt(liqEntries.W)) - val waitMask = Output(UInt(liqEntries.W)) - val waitStoreMask = Output(UInt(liqEntries.W)) - val launchWaitMask = Output(UInt(liqEntries.W)) - val launchWaitStoreBlockedMask = Output(UInt(liqEntries.W)) - val launchTileBlockedMask = Output(UInt(liqEntries.W)) - val launchUnblockedWaitMask = Output(UInt(liqEntries.W)) - val launchRequestCompleteMask = Output(UInt(liqEntries.W)) - val launchDataHitMask = Output(UInt(liqEntries.W)) - val launchCandidateMask = Output(UInt(liqEntries.W)) - val launchMask = Output(UInt(liqEntries.W)) - val launchValid = Output(Bool()) - val launchIndex = Output(UInt(liqPtrWidth.W)) - val launchCandidateCount = Output(UInt(countWidth.W)) - val launchSelectedLoadId = Output(new ROBID(liqEntries)) - val launchSelectedBid = Output(new ROBID(idEntries)) - val launchSelectedGid = Output(new ROBID(idEntries)) - val launchSelectedRid = Output(new ROBID(idEntries)) - val launchSelectedLoadLsId = Output(new ROBID(idEntries)) - val launchSelectedPc = Output(UInt(pcWidth.W)) - val launchSelectedAddr = Output(UInt(addrWidth.W)) - val launchSelectedSize = Output(UInt(sizeWidth.W)) - val launchSelectedReturnSignExtend = Output(Bool()) - val launchSelectedDst = Output(new LoadReplayDestination(archRegWidth, physRegWidth)) - val launchSelectedSourceTraceValid = Output(Bool()) - val launchSelectedSource0 = Output(new CommitOperandTrace(sourceTraceParams)) - val launchSelectedSource1 = Output(new CommitOperandTrace(sourceTraceParams)) - val launchSelectedRequestByteMask = Output(UInt(lineBytes.W)) - val launchSelectedSpecWakeup = Output(Bool()) - val launchSelectedStackValid = Output(Bool()) - val launchDriveValid = Output(Bool()) - val launchReady = Output(Bool()) - val launchAccepted = Output(Bool()) - val pickReady = Output(Bool()) - val pickAccepted = Output(Bool()) - val scbReturnReady = Output(Bool()) - val scbReturnAccepted = Output(Bool()) - val markResolvedReady = Output(Bool()) - val markResolvedAccepted = Output(Bool()) - val returnCompleteRepickMask = Output(UInt(liqEntries.W)) - val returnCompleteSourceReturnedMask = Output(UInt(liqEntries.W)) - val returnCompleteDataCompleteMask = Output(UInt(liqEntries.W)) - val returnCompleteRequestCompleteMask = Output(UInt(liqEntries.W)) - val returnCompleteCandidateMask = Output(UInt(liqEntries.W)) - val returnCompleteMask = Output(UInt(liqEntries.W)) - val returnCompleteValid = Output(Bool()) - val returnCompleteIndex = Output(UInt(liqPtrWidth.W)) - val returnCompleteCandidateCount = Output(UInt(countWidth.W)) - val returnCompleteSelectedLoadId = Output(new ROBID(liqEntries)) - val returnCompleteSelectedBid = Output(new ROBID(idEntries)) - val returnCompleteSelectedGid = Output(new ROBID(idEntries)) - val returnCompleteSelectedRid = Output(new ROBID(idEntries)) - val returnCompleteSelectedLoadLsId = Output(new ROBID(idEntries)) - val returnCompleteSelectedPc = Output(UInt(pcWidth.W)) - val returnCompleteSelectedAddr = Output(UInt(addrWidth.W)) - val returnCompleteSelectedSize = Output(UInt(sizeWidth.W)) - val returnCompleteSelectedReturnSignExtend = Output(Bool()) - val returnCompleteSelectedDst = Output(new LoadReplayDestination(archRegWidth, physRegWidth)) - val returnCompleteSelectedSourceTraceValid = Output(Bool()) - val returnCompleteSelectedSource0 = Output(new CommitOperandTrace(sourceTraceParams)) - val returnCompleteSelectedSource1 = Output(new CommitOperandTrace(sourceTraceParams)) - val returnCompleteSelectedRequestByteMask = Output(UInt(lineBytes.W)) - val returnCompleteSelectedLineData = Output(UInt((lineBytes * 8).W)) - val returnCompleteSelectedValidMask = Output(UInt(lineBytes.W)) - val returnCompleteSelectedSpecWakeup = Output(Bool()) - val returnCompleteSelectedStackValid = Output(Bool()) - val repickMask = Output(UInt(liqEntries.W)) - val missMask = Output(UInt(liqEntries.W)) - val resolvedMask = Output(UInt(liqEntries.W)) - val e4UpdateValid = Output(Bool()) - val e4UpdateIndex = Output(UInt(liqPtrWidth.W)) - val e4MissKind = Output(LoadForwardMissKind()) - val e4WakeupValid = Output(Bool()) - val lhqRecordValid = Output(Bool()) - val lhqRecord = Output(new LoadHitRecord( - liqEntries, idEntries, addrWidth, lineBytes, sizeWidth, pcWidth, lsidWidth)) - val residentCount = Output(UInt(countWidth.W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val missPending = Output(Bool()) - val clearResolvedAccepted = Output(Bool()) -} - -class ReducedLoadReplayLiqAllocPath( - val liqEntries: Int = 4, - val idEntries: Int = 16, - val storeEntries: Int = 16, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Module { - require(liqEntries > 1, "LIQ entries must be greater than one") - require((liqEntries & (liqEntries - 1)) == 0, "LIQ entries must be a power of two") - require(idEntries > 1, "ID entries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "ID entries must be a power of two") - require(storeEntries > 1, "storeEntries must be greater than one") - require((storeEntries & (storeEntries - 1)) == 0, "storeEntries must be a power of two") - require(lineBytes == 64, "ReducedLoadReplayLiqAllocPath currently models 64-byte scalar cachelines") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - private val liqPtrWidth = log2Ceil(liqEntries) - - val io = IO(new ReducedLoadReplayLiqAllocPathIO( - liqEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - - val adapter = Module(new ReducedLoadReplayLiqAllocAdapter( - liqEntries, - idEntries, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - val liq = Module(new LoadInflightQueue( - liqEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - val launchSelect = Module(new LoadInflightLaunchSelect( - liqEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth - )) - val completeRepickSelect = Module(new LoadReplayReturnCompleteRepickSelect( - liqEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth - )) - val rowMutationBridge = Module(new LoadInflightRowMutationRequestBridge( - liqEntries = liqEntries, - idEntries = idEntries, - sourceStoreEntries = idEntries, - storeEntries = storeEntries, - pcWidth = pcWidth, - lineBytes = lineBytes, - lsidWidth = lsidWidth - )) - - adapter.io.flush := io.flush - adapter.io.candidateValid := io.candidateValid - adapter.io.candidate := io.candidate - adapter.io.allocReady := liq.io.allocReady && io.allocExternalReady - - liq.io.flush := io.flush - liq.io.preciseFlush := io.preciseFlush - liq.io.allocValid := adapter.io.allocValid && io.allocExternalReady - liq.io.alloc := adapter.io.alloc - liq.io.attemptRebindValid := false.B - liq.io.attemptRebind := 0.U.asTypeOf(liq.io.attemptRebind) - - liq.io.launchValid := io.launchEnable && launchSelect.io.launchValid - liq.io.launchIndex := launchSelect.io.launchIndex - liq.io.pickValid := io.pickValid - liq.io.pickIndex := io.pickIndex - liq.io.scbReturnValid := io.scbReturnValid - liq.io.scbReturnIndex := io.scbReturnIndex - liq.io.markResolvedValid := io.markResolvedValid - liq.io.markResolvedIndex := io.markResolvedIndex - liq.io.e2Stores := io.e2Stores - liq.io.e2BaseData := io.e2BaseData - liq.io.e2BaseValidMask := io.e2BaseValidMask - liq.io.e2LoadDataReturned := io.e2LoadDataReturned - liq.io.e2ScbReturned := io.e2ScbReturned - liq.io.e2StqReturned := io.e2StqReturned - liq.io.e2ReturnReady := io.e2ReturnReady - liq.io.replayWakeValid := io.replayWakeValid - liq.io.replayWake := io.replayWake - liq.io.refillValid := io.refillValid - liq.io.refill := io.refill - liq.io.clearResolvedValid := io.clearResolvedValid - liq.io.clearResolvedIndex := io.clearResolvedIndex - - rowMutationBridge.io.enable := !io.flush - rowMutationBridge.io.flush := io.flush - rowMutationBridge.io.requestValid := io.rowMutationRequestValid - rowMutationBridge.io.requestTargetMask := io.rowMutationRequestTargetMask - rowMutationBridge.io.requestTargetIndex := io.rowMutationRequestTargetIndex - rowMutationBridge.io.setWaitStatus := io.rowMutationSetWaitStatus - rowMutationBridge.io.keepRepickStatus := io.rowMutationKeepRepickStatus - rowMutationBridge.io.clearReturnState := io.rowMutationClearReturnState - rowMutationBridge.io.lineWrite := io.rowMutationLineWrite - rowMutationBridge.io.waitStoreWrite := io.rowMutationWaitStoreWrite - rowMutationBridge.io.nextWaitStore := io.rowMutationNextWaitStore - rowMutationBridge.io.nextWaitStoreInfo := io.rowMutationNextWaitStoreInfo - rowMutationBridge.io.nextLineData := io.rowMutationNextLineData - rowMutationBridge.io.nextValidMask := io.rowMutationNextValidMask - rowMutationBridge.io.nextDataComplete := io.rowMutationNextDataComplete - rowMutationBridge.io.nextScbReturned := io.rowMutationNextScbReturned - rowMutationBridge.io.nextStqReturned := io.rowMutationNextStqReturned - rowMutationBridge.io.nextStoreSourceReturned := io.rowMutationNextStoreSourceReturned - - liq.io.rowMutationValid := rowMutationBridge.io.bridgeValid - liq.io.rowMutationTargetIndex := rowMutationBridge.io.requestTargetIndexOut - liq.io.rowMutationSetWaitStatus := rowMutationBridge.io.setWaitStatusOut - liq.io.rowMutationKeepRepickStatus := rowMutationBridge.io.keepRepickStatusOut - liq.io.rowMutationClearReturnState := rowMutationBridge.io.clearReturnStateOut - liq.io.rowMutationLineWrite := rowMutationBridge.io.lineWriteOut - liq.io.rowMutationWaitStoreWrite := rowMutationBridge.io.waitStoreWriteOut - liq.io.rowMutationNextWaitStore := rowMutationBridge.io.nextWaitStoreOut - liq.io.rowMutationNextWaitStoreInfo := rowMutationBridge.io.nativeNextWaitStoreInfoOut - liq.io.rowMutationNextLineData := rowMutationBridge.io.nextLineDataOut - liq.io.rowMutationNextValidMask := rowMutationBridge.io.nextValidMaskOut - liq.io.rowMutationNextDataComplete := rowMutationBridge.io.nextDataCompleteOut - liq.io.rowMutationNextScbReturned := rowMutationBridge.io.nextScbReturnedOut - liq.io.rowMutationNextStqReturned := rowMutationBridge.io.nextStqReturnedOut - liq.io.rowMutationNextStoreSourceReturned := rowMutationBridge.io.nextStoreSourceReturnedOut - liq.io.rowMutationAllowWaitTarget := io.rowMutationAllowWaitTarget - liq.io.rowMutationRequireScbReturned := io.rowMutationRequireScbReturned - - launchSelect.io.enable := !io.flush - launchSelect.io.rows := liq.io.rows - completeRepickSelect.io.enable := !io.flush - completeRepickSelect.io.rows := liq.io.rows - - val replayWakeDiagnostics = - Module(new LoadReplayWakeMatchDiagnostics( - liqEntries, idEntries, storeEntries, addrWidth, pcWidth, lineBytes, sizeWidth, - archRegWidth, physRegWidth, lsidWidth)) - replayWakeDiagnostics.io.wakeValid := io.replayWakeValid - replayWakeDiagnostics.io.wake := io.replayWake - replayWakeDiagnostics.io.rows := liq.io.rows - - io.candidateConsumeReady := adapter.io.consumeReady - io.candidateUsable := adapter.io.candidateUsable - io.candidateBlockedByAlloc := adapter.io.blockedByAlloc - io.allocValid := adapter.io.allocValid - io.allocReady := liq.io.allocReady && io.allocExternalReady - io.allocAccepted := liq.io.allocAccepted - io.allocIndex := liq.io.allocIndex - io.allocLoadId := liq.io.allocLoadId - io.allocPayload := adapter.io.alloc - io.rows := liq.io.rows - io.occupiedMask := liq.io.occupiedMask - io.waitMask := liq.io.waitMask - io.waitStoreMask := liq.io.waitStoreMask - io.launchWaitMask := launchSelect.io.waitMask - io.launchWaitStoreBlockedMask := launchSelect.io.waitStoreBlockedMask - io.launchTileBlockedMask := launchSelect.io.tileBlockedMask - io.launchUnblockedWaitMask := launchSelect.io.unblockedWaitMask - io.launchRequestCompleteMask := launchSelect.io.requestCompleteMask - io.launchDataHitMask := launchSelect.io.dataHitMask - io.launchCandidateMask := launchSelect.io.launchCandidateMask - io.launchMask := launchSelect.io.launchMask - io.launchValid := launchSelect.io.launchValid - io.launchIndex := launchSelect.io.launchIndex - io.launchCandidateCount := launchSelect.io.candidateCount - io.launchSelectedLoadId := launchSelect.io.selectedLoadId - io.launchSelectedBid := launchSelect.io.selectedBid - io.launchSelectedGid := launchSelect.io.selectedGid - io.launchSelectedRid := launchSelect.io.selectedRid - io.launchSelectedLoadLsId := launchSelect.io.selectedLoadLsId - io.launchSelectedPc := launchSelect.io.selectedPc - io.launchSelectedAddr := launchSelect.io.selectedAddr - io.launchSelectedSize := launchSelect.io.selectedSize - io.launchSelectedReturnSignExtend := launchSelect.io.selectedReturnSignExtend - io.launchSelectedDst := launchSelect.io.selectedDst - io.launchSelectedSourceTraceValid := launchSelect.io.selectedSourceTraceValid - io.launchSelectedSource0 := launchSelect.io.selectedSource0 - io.launchSelectedSource1 := launchSelect.io.selectedSource1 - io.launchSelectedRequestByteMask := launchSelect.io.selectedRequestByteMask - io.launchSelectedSpecWakeup := launchSelect.io.selectedSpecWakeup - io.launchSelectedStackValid := launchSelect.io.selectedStackValid - io.launchDriveValid := io.launchEnable && launchSelect.io.launchValid - io.launchReady := launchSelect.io.launchValid && liq.io.launchReady - io.launchAccepted := liq.io.launchAccepted - io.pickReady := liq.io.pickReady - io.pickAccepted := liq.io.pickAccepted - io.scbReturnReady := liq.io.scbReturnReady - io.scbReturnAccepted := liq.io.scbReturnAccepted - io.markResolvedReady := liq.io.markResolvedReady - io.markResolvedAccepted := liq.io.markResolvedAccepted - io.returnCompleteRepickMask := completeRepickSelect.io.repickMask - io.returnCompleteSourceReturnedMask := completeRepickSelect.io.sourceReturnedMask - io.returnCompleteDataCompleteMask := completeRepickSelect.io.dataCompleteMask - io.returnCompleteRequestCompleteMask := completeRepickSelect.io.requestCompleteMask - io.returnCompleteCandidateMask := completeRepickSelect.io.returnCandidateMask - io.returnCompleteMask := completeRepickSelect.io.returnMask - io.returnCompleteValid := completeRepickSelect.io.returnValid - io.returnCompleteIndex := completeRepickSelect.io.returnIndex - io.returnCompleteCandidateCount := completeRepickSelect.io.candidateCount - io.returnCompleteSelectedLoadId := completeRepickSelect.io.selectedLoadId - io.returnCompleteSelectedBid := completeRepickSelect.io.selectedBid - io.returnCompleteSelectedGid := completeRepickSelect.io.selectedGid - io.returnCompleteSelectedRid := completeRepickSelect.io.selectedRid - io.returnCompleteSelectedLoadLsId := completeRepickSelect.io.selectedLoadLsId - io.returnCompleteSelectedPc := completeRepickSelect.io.selectedPc - io.returnCompleteSelectedAddr := completeRepickSelect.io.selectedAddr - io.returnCompleteSelectedSize := completeRepickSelect.io.selectedSize - io.returnCompleteSelectedReturnSignExtend := completeRepickSelect.io.selectedReturnSignExtend - io.returnCompleteSelectedDst := completeRepickSelect.io.selectedDst - io.returnCompleteSelectedSourceTraceValid := completeRepickSelect.io.selectedSourceTraceValid - io.returnCompleteSelectedSource0 := completeRepickSelect.io.selectedSource0 - io.returnCompleteSelectedSource1 := completeRepickSelect.io.selectedSource1 - io.returnCompleteSelectedRequestByteMask := completeRepickSelect.io.selectedRequestByteMask - io.returnCompleteSelectedLineData := completeRepickSelect.io.selectedLineData - io.returnCompleteSelectedValidMask := completeRepickSelect.io.selectedValidMask - io.returnCompleteSelectedSpecWakeup := completeRepickSelect.io.selectedSpecWakeup - io.returnCompleteSelectedStackValid := completeRepickSelect.io.selectedStackValid - io.repickMask := liq.io.repickMask - io.missMask := liq.io.missMask - io.resolvedMask := liq.io.resolvedMask - io.e4UpdateValid := liq.io.e4UpdateValid - io.e4UpdateIndex := liq.io.e4UpdateIndex - io.e4MissKind := liq.io.e4MissKind - io.e4WakeupValid := liq.io.e4WakeupValid - io.replayWakeWaitStoreCandidateMask := replayWakeDiagnostics.io.waitStoreCandidateMask - io.replayWakeBidMatchMask := replayWakeDiagnostics.io.bidMatchMask - io.replayWakeLsIdMatchMask := replayWakeDiagnostics.io.lsIdMatchMask - io.replayWakePcMatchMask := replayWakeDiagnostics.io.pcMatchMask - io.replayWakeFullMatchMask := replayWakeDiagnostics.io.fullMatchMask - io.replayWakeStoreUnit := replayWakeDiagnostics.io.storeUnit - io.replayWakeStoreUnitFullMatchMask := replayWakeDiagnostics.io.storeUnitFullMatchMask - io.replayWakeWaitStoreClearMask := liq.io.replayWakeWaitStoreClearMask - io.replayWakeMergeMask := liq.io.replayWakeMergeMask - io.replayWakeCompletedMask := liq.io.replayWakeCompletedMask - io.refillAccepted := liq.io.refillAccepted - io.refillWakeMask := liq.io.refillWakeMask - io.lhqRecordValid := liq.io.lhqRecordValid - io.lhqRecord := liq.io.lhqRecord - io.residentCount := liq.io.residentCount - io.empty := liq.io.empty - io.full := liq.io.full - io.missPending := liq.io.missPending - io.clearResolvedAccepted := liq.io.clearResolvedAccepted - io.flushPruneMask := liq.io.flushPruneMask - io.flushPruneCount := liq.io.flushPruneCount - io.rowMutationBridgeValid := rowMutationBridge.io.bridgeValid - io.rowMutationSourceStoreIndexFits := rowMutationBridge.io.sourceStoreIndexFits - io.rowMutationInvalidStoreIndexOutOfRange := rowMutationBridge.io.invalidStoreIndexOutOfRange - io.rowMutationInvalidConflictingStatusWrite := rowMutationBridge.io.invalidConflictingStatusWrite - io.rowMutationInvalidWaitStoreWithoutWaitStatus := rowMutationBridge.io.invalidWaitStoreWithoutWaitStatus - io.rowMutationInvalidReturnWithoutSplitSources := rowMutationBridge.io.invalidReturnWithoutSplitSources - io.rowMutationWriteEnable := liq.io.rowMutationWriteEnable - io.rowMutationApplyValid := liq.io.rowMutationApplyValid - io.rowMutationTargetEvidenceValid := liq.io.rowMutationTargetEvidenceValid - io.rowMutationWriteConflict := liq.io.rowMutationWriteConflict - io.rowMutationBlockedByBridge := io.rowMutationRequestValid && !rowMutationBridge.io.bridgeValid - io.rowMutationBlockedByControl := liq.io.rowMutationBlockedByControl - io.rowMutationControlBlockedByInvalidRow := liq.io.rowMutationControlBlockedByInvalidRow - io.rowMutationControlBlockedByNotRepick := liq.io.rowMutationControlBlockedByNotRepick - io.rowMutationControlBlockedByScbNotReturned := liq.io.rowMutationControlBlockedByScbNotReturned - io.rowMutationControlBlockedByE4UpdateConflict := liq.io.rowMutationControlBlockedByE4UpdateConflict - io.rowMutationControlBlockedByClearResolvedConflict := liq.io.rowMutationControlBlockedByClearResolvedConflict - io.rowMutationControlBlockedByReplayWakeConflict := liq.io.rowMutationControlBlockedByReplayWakeConflict - io.rowMutationControlBlockedByRefillConflict := liq.io.rowMutationControlBlockedByRefillConflict - io.rowMutationControlBlockedByLaunchConflict := liq.io.rowMutationControlBlockedByLaunchConflict - io.rowMutationControlBlockedByAllocationConflict := liq.io.rowMutationControlBlockedByAllocationConflict -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala deleted file mode 100644 index d02509bb..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala +++ /dev/null @@ -1,135 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.rob.ROBID - -class ReducedLoadReplayRelaunchQueueIO( - val idEntries: Int, - val depth: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - private val countWidth = log2Ceil(depth + 1) - - val flush = Input(Bool()) - val enqueueValid = Input(Bool()) - val enqueue = Input(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - val outReady = Input(Bool()) - - val enqueueReady = Output(Bool()) - val enqueueAccepted = Output(Bool()) - val enqueueDropped = Output(Bool()) - val outValid = Output(Bool()) - val out = Output(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - val outFire = Output(Bool()) - val pending = Output(Bool()) - val full = Output(Bool()) - val empty = Output(Bool()) - val count = Output(UInt(countWidth.W)) -} - -class ReducedLoadReplayRelaunchQueue( - val idEntries: Int = 16, - val depth: Int = 2, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Module { - require(idEntries > 1, "idEntries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "idEntries must be a power of two") - require(depth > 0, "relaunch queue depth must be nonzero") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - private val ptrWidth = math.max(1, log2Ceil(depth)) - private val countWidth = log2Ceil(depth + 1) - - val io = IO(new ReducedLoadReplayRelaunchQueueIO( - idEntries, - depth, - addrWidth, - pcWidth, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth - )) - - private def zeroCandidate: ReducedLoadReplayCandidate = { - val candidate = Wire(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - candidate := 0.U.asTypeOf(candidate) - candidate.dst := LoadReplayDestination.none(archRegWidth, physRegWidth) - candidate.bid := ROBID.disabled(idEntries) - candidate.gid := ROBID.disabled(idEntries) - candidate.rid := ROBID.disabled(idEntries) - candidate.loadLsId := ROBID.disabled(idEntries) - candidate.youngestStoreId := ROBID.disabled(idEntries) - candidate.youngestStoreLsId := ROBID.disabled(idEntries) - candidate - } - - private def inc(ptr: UInt): UInt = - if (depth == 1) 0.U(ptrWidth.W) else Mux(ptr === (depth - 1).U, 0.U, ptr + 1.U) - - val entries = RegInit(VecInit(Seq.fill(depth)(zeroCandidate))) - val headPtr = RegInit(0.U(ptrWidth.W)) - val tailPtr = RegInit(0.U(ptrWidth.W)) - val count = RegInit(0.U(countWidth.W)) - - val inputValid = io.enqueueValid && io.enqueue.valid - val outValid = (count =/= 0.U) && !io.flush - val outFire = outValid && io.outReady - val enqueueReady = !io.flush && ((count =/= depth.U) || outFire) - val enqueueAccepted = inputValid && enqueueReady - val enqueueDropped = inputValid && !io.flush && !enqueueReady - - val enqueuePayload = Wire(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - enqueuePayload := io.enqueue - enqueuePayload.valid := true.B - - when(io.flush) { - for (idx <- 0 until depth) { - entries(idx) := zeroCandidate - } - headPtr := 0.U - tailPtr := 0.U - count := 0.U - }.otherwise { - when(outFire) { - headPtr := inc(headPtr) - } - when(enqueueAccepted) { - entries(tailPtr) := enqueuePayload - tailPtr := inc(tailPtr) - } - - when(enqueueAccepted && !outFire) { - count := count + 1.U - }.elsewhen(!enqueueAccepted && outFire) { - count := count - 1.U - } - } - - io.enqueueReady := enqueueReady - io.enqueueAccepted := enqueueAccepted - io.enqueueDropped := enqueueDropped - io.outValid := outValid - io.out := Mux(outValid, entries(headPtr), zeroCandidate) - io.outFire := outFire - io.pending := count =/= 0.U - io.full := count === depth.U - io.empty := count === 0.U - io.count := count -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala b/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala deleted file mode 100644 index c9efce57..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala +++ /dev/null @@ -1,298 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import linxcore.commit.{CommitOperandTrace, CommitTraceParams} -import linxcore.rob.ROBID - -class ReducedLoadReplayCandidate( - val idEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - private val sourceTraceParams = - CommitTraceParams(regWidth = math.max(8, archRegWidth), dataWidth = addrWidth) - - val valid = Bool() - val pc = UInt(pcWidth.W) - val addr = UInt(addrWidth.W) - val size = UInt(sizeWidth.W) - val returnSignExtend = Bool() - val dst = new LoadReplayDestination(archRegWidth, physRegWidth) - val sourceTraceValid = Bool() - val source0 = new CommitOperandTrace(sourceTraceParams) - val source1 = new CommitOperandTrace(sourceTraceParams) - val bid = new ROBID(idEntries) - val gid = new ROBID(idEntries) - val rid = new ROBID(idEntries) - val loadLsId = new ROBID(idEntries) - val loadLsIdFullValid = Bool() - val loadLsIdFull = UInt(lsidWidth.W) - val youngestStoreId = new ROBID(idEntries) - val youngestStoreLsId = new ROBID(idEntries) - val youngestStoreLsIdFullValid = Bool() - val youngestStoreLsIdFull = UInt(lsidWidth.W) -} - -class ReducedLoadWaitReplaySlotIO( - val idEntries: Int, - val storeEntries: Int, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Bundle { - private val slotEntries = 2 - - val flush = Input(Bool()) - val captureValid = Input(Bool()) - val capturePc = Input(UInt(pcWidth.W)) - val captureAddr = Input(UInt(addrWidth.W)) - val captureSize = Input(UInt(sizeWidth.W)) - val captureReturnSignExtend = Input(Bool()) - val captureDst = Input(new LoadReplayDestination(archRegWidth, physRegWidth)) - val captureSourceTraceValid = Input(Bool()) - val captureSource0 = Input(new CommitOperandTrace(CommitTraceParams(regWidth = math.max(8, archRegWidth), dataWidth = addrWidth))) - val captureSource1 = Input(new CommitOperandTrace(CommitTraceParams(regWidth = math.max(8, archRegWidth), dataWidth = addrWidth))) - val captureBid = Input(new ROBID(idEntries)) - val captureGid = Input(new ROBID(idEntries)) - val captureRid = Input(new ROBID(idEntries)) - val captureLsId = Input(new ROBID(idEntries)) - val captureLsIdFullValid = Input(Bool()) - val captureLsIdFull = Input(UInt(lsidWidth.W)) - val captureYoungestStoreId = Input(new ROBID(idEntries)) - val captureYoungestStoreLsId = Input(new ROBID(idEntries)) - val captureYoungestStoreLsIdFullValid = Input(Bool()) - val captureYoungestStoreLsIdFull = Input(UInt(lsidWidth.W)) - val captureWaitStore = Input(new LoadStoreForwardWait(idEntries, storeEntries, pcWidth, lsidWidth)) - - val replayWakeValid = Input(Bool()) - val replayWake = Input(new LoadReplayWakeupRequest(idEntries, addrWidth, pcWidth, lineBytes, lsidWidth)) - - val active = Output(Bool()) - val captureAccepted = Output(Bool()) - val waitStoreClear = Output(Bool()) - val waitStoreClearMask = Output(UInt(slotEntries.W)) - val storedWaitStore = Output(new LoadStoreForwardWait(idEntries, storeEntries, pcWidth, lsidWidth)) - val relaunch = Output(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - val slotPc = Output(UInt(pcWidth.W)) - val slotAddr = Output(UInt(addrWidth.W)) -} - -class ReducedLoadWaitReplaySlot( - val idEntries: Int = 16, - val storeEntries: Int = 16, - val addrWidth: Int = 64, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val sizeWidth: Int = 7, - val archRegWidth: Int = 6, - val physRegWidth: Int = 6, - val lsidWidth: Int = 32) - extends Module { - private val slotEntries = 2 - - require(idEntries > 1, "idEntries must be greater than one") - require((idEntries & (idEntries - 1)) == 0, "idEntries must be a power of two") - require(storeEntries > 1, "storeEntries must be greater than one") - require((storeEntries & (storeEntries - 1)) == 0, "storeEntries must be a power of two") - require(addrWidth >= 7, "ReducedLoadWaitReplaySlot needs 64-byte line addresses") - require(lineBytes == 64, "ReducedLoadWaitReplaySlot currently models 64-byte scalar cachelines") - require(sizeWidth >= 7, "sizeWidth must cover 64-byte scalar lines") - - val io = IO(new ReducedLoadWaitReplaySlotIO( - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth - )) - - private def zeroWait: LoadStoreForwardWait = { - val wait = Wire(new LoadStoreForwardWait(idEntries, storeEntries, pcWidth, lsidWidth)) - wait := 0.U.asTypeOf(wait) - wait.storeId := ROBID.disabled(idEntries) - wait.storeLsId := ROBID.disabled(idEntries) - wait - } - - private def zeroRow: LoadInflightRow = { - val row = Wire(new LoadInflightRow( - slotEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - row := 0.U.asTypeOf(row) - row.status := LoadInflightStatus.Idle - row.loadId := ROBID.disabled(slotEntries) - row.dst := LoadReplayDestination.none(archRegWidth, physRegWidth) - row.bid := ROBID.disabled(idEntries) - row.gid := ROBID.disabled(idEntries) - row.rid := ROBID.disabled(idEntries) - row.loadLsId := ROBID.disabled(idEntries) - row.youngestStoreId := ROBID.disabled(idEntries) - row.youngestStoreLsId := ROBID.disabled(idEntries) - row.waitStoreInfo := zeroWait - row.missKind := LoadForwardMissKind.NoMiss - row - } - - private def zeroCandidate: ReducedLoadReplayCandidate = { - val candidate = Wire(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - candidate := 0.U.asTypeOf(candidate) - candidate.dst := LoadReplayDestination.none(archRegWidth, physRegWidth) - candidate.bid := ROBID.disabled(idEntries) - candidate.gid := ROBID.disabled(idEntries) - candidate.rid := ROBID.disabled(idEntries) - candidate.loadLsId := ROBID.disabled(idEntries) - candidate.youngestStoreId := ROBID.disabled(idEntries) - candidate.youngestStoreLsId := ROBID.disabled(idEntries) - candidate - } - - private def capturedRow: LoadInflightRow = { - val row = Wire(new LoadInflightRow( - slotEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - )) - row := zeroRow - row.valid := true.B - row.status := LoadInflightStatus.Wait - row.loadId := ROBID.zero(slotEntries) - row.dst := io.captureDst - row.bid := io.captureBid - row.gid := io.captureGid - row.rid := io.captureRid - row.loadLsId := io.captureLsId - row.loadLsIdFullValid := io.captureLsIdFullValid - row.loadLsIdFull := io.captureLsIdFull - row.pc := io.capturePc - row.addr := io.captureAddr - row.size := io.captureSize - row.returnSignExtend := io.captureReturnSignExtend - row.youngestStoreId := io.captureYoungestStoreId - row.youngestStoreLsId := io.captureYoungestStoreLsId - row.youngestStoreLsIdFullValid := io.captureYoungestStoreLsIdFullValid - row.youngestStoreLsIdFull := io.captureYoungestStoreLsIdFull - row.sourceTraceValid := io.captureSourceTraceValid - row.source0 := io.captureSource0 - row.source1 := io.captureSource1 - row.waitStore := true.B - row.waitStoreInfo := io.captureWaitStore - row - } - - val activeReg = RegInit(false.B) - val slotReg = RegInit(zeroRow) - val loadLsIdReg = RegInit(ROBID.disabled(idEntries)) - val emptyRow = zeroRow - - val rows = Wire(Vec( - slotEntries, - new LoadInflightRow( - slotEntries, - idEntries, - storeEntries, - addrWidth, - pcWidth, - lineBytes, - sizeWidth, - archRegWidth, - physRegWidth, - lsidWidth = lsidWidth - ) - )) - rows(0) := slotReg - rows(1) := emptyRow - - val replay = Module(new LoadReplayWakeup( - slotEntries, idEntries, storeEntries, addrWidth, pcWidth, lineBytes, sizeWidth, lsidWidth)) - replay.io.wakeValid := io.replayWakeValid && activeReg && !io.flush - replay.io.wake := io.replayWake - replay.io.rows := rows - - val captureAccepted = io.captureValid && io.captureWaitStore.valid && !io.flush - val waitStoreClear = activeReg && replay.io.waitStoreClearMask(0) - val relaunchValid = waitStoreClear && !captureAccepted - - when(io.flush) { - activeReg := false.B - slotReg := zeroRow - loadLsIdReg := ROBID.disabled(idEntries) - }.elsewhen(captureAccepted) { - activeReg := true.B - slotReg := capturedRow - loadLsIdReg := io.captureLsId - }.elsewhen(waitStoreClear) { - activeReg := false.B - slotReg := zeroRow - loadLsIdReg := ROBID.disabled(idEntries) - } - - val storedWait = Wire(new LoadStoreForwardWait(idEntries, storeEntries, pcWidth, lsidWidth)) - storedWait := zeroWait - when(activeReg) { - storedWait := slotReg.waitStoreInfo - } - - val relaunch = Wire(new ReducedLoadReplayCandidate( - idEntries, addrWidth, pcWidth, sizeWidth, archRegWidth, physRegWidth, lsidWidth)) - relaunch := zeroCandidate - when(relaunchValid) { - relaunch.valid := true.B - relaunch.pc := slotReg.pc - relaunch.addr := slotReg.addr - relaunch.size := slotReg.size - relaunch.returnSignExtend := slotReg.returnSignExtend - relaunch.dst := slotReg.dst - relaunch.sourceTraceValid := slotReg.sourceTraceValid - relaunch.source0 := slotReg.source0 - relaunch.source1 := slotReg.source1 - relaunch.bid := slotReg.bid - relaunch.gid := slotReg.gid - relaunch.rid := slotReg.rid - relaunch.loadLsId := loadLsIdReg - relaunch.loadLsIdFullValid := slotReg.loadLsIdFullValid - relaunch.loadLsIdFull := slotReg.loadLsIdFull - relaunch.youngestStoreId := slotReg.youngestStoreId - relaunch.youngestStoreLsId := slotReg.youngestStoreLsId - relaunch.youngestStoreLsIdFullValid := slotReg.youngestStoreLsIdFullValid - relaunch.youngestStoreLsIdFull := slotReg.youngestStoreLsIdFull - } - - io.active := activeReg - io.captureAccepted := captureAccepted - io.waitStoreClear := waitStoreClear - io.waitStoreClearMask := replay.io.waitStoreClearMask - io.storedWaitStore := storedWait - io.relaunch := relaunch - io.slotPc := slotReg.pc - io.slotAddr := slotReg.addr -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreCommitFreeOwner.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreCommitFreeOwner.scala deleted file mode 100644 index 693f19db..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreCommitFreeOwner.scala +++ /dev/null @@ -1,402 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.{log2Ceil, PopCount, PriorityEncoder, PriorityEncoderOH, UIntToOH} - -import linxcore.commit.{CommitTraceParams, CommitTracePort, CommitTraceRow} -import linxcore.common.LSIDOrder -import linxcore.rob.{ROBID, ROBMemoryOrderCommit} - -class ReducedStoreCommitFreeOwnerIO( - val entries: Int, - val traceParams: CommitTraceParams = CommitTraceParams(), - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8, - val mapQDepth: Int = 32, - val lsidWidth: Int = 32, - val robEntries: Int = 0) - extends Bundle { - private val identityEntries = if (robEntries > 0) robEntries else entries - private val ptrWidth = log2Ceil(entries) - private val countWidth = log2Ceil(entries + 1) - - val enable = Input(Bool()) - val directFreeEnable = Input(Bool()) - val flushValid = Input(Bool()) - val activeStid = Input(UInt(stidWidth.W)) - val nonFlushValid = Input(Bool()) - val nonFlushHeadBid = Input(UInt(traceParams.blockBidWidth.W)) - val nonFlushPrefixCount = Input(UInt(countWidth.W)) - val oldestBlockValid = Input(Bool()) - val oldestBlockBid = Input(UInt(traceParams.blockBidWidth.W)) - val oldestRobValid = Input(Bool()) - val oldestRobBid = Input(new ROBID(identityEntries)) - val oldestRobLsId = Input(UInt(lsidWidth.W)) - val oldestRobStid = Input(UInt(stidWidth.W)) - - val commit = Input(new CommitTracePort(traceParams)) - val commitValidMask = Input(UInt(traceParams.commitWidth.W)) - val commitMemoryOrder = Input(Vec(traceParams.commitWidth, new ROBMemoryOrderCommit(identityEntries, lsidWidth))) - val stqRows = Input(Vec(entries, new STQEntryBankRow(identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth))) - - val markCommitValid = Output(Bool()) - val markCommitIndex = Output(UInt(ptrWidth.W)) - val markCommitAccepted = Input(Bool()) - val markCommitIgnored = Input(Bool()) - - val commitFreeValid = Output(Bool()) - val commitFreeIndex = Output(UInt(ptrWidth.W)) - val commitFreeAccepted = Input(Bool()) - val commitFreeIgnored = Input(Bool()) - val commitFreeAcceptedMask = Input(UInt(entries.W)) - val commitFreeIgnoredMask = Input(UInt(entries.W)) - - val commitStoreSeen = Output(Bool()) - val commitStoreMatched = Output(Bool()) - val commitStoreUnmatched = Output(Bool()) - val commitStoreBlockedByNonFlush = Output(Bool()) - val commitStoreReleasedByEarlySafe = Output(Bool()) - val matchMask = Output(UInt(entries.W)) - val earlySafeMatchMask = Output(UInt(entries.W)) - val pendingCommitIdentityMask = Output(UInt(entries.W)) - val pendingCommitEarlySafeMask = Output(UInt(entries.W)) - val residentEarlySafeMask = Output(UInt(entries.W)) - val pendingMarkMask = Output(UInt(entries.W)) - val pendingFreeMask = Output(UInt(entries.W)) - val pendingMarkCount = Output(UInt(countWidth.W)) - val pendingFreeCount = Output(UInt(countWidth.W)) - val markBlocked = Output(Bool()) - val freeBlocked = Output(Bool()) - val idle = Output(Bool()) -} - -class ReducedStoreCommitFreeOwner( - val entries: Int = 16, - val traceParams: CommitTraceParams = CommitTraceParams(), - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8, - val mapQDepth: Int = 32, - val lsidWidth: Int = 32, - val robEntries: Int = 0) - extends Module { - private val identityEntries = if (robEntries > 0) robEntries else entries - require(entries > 1, "reduced store commit/free owner needs at least two STQ entries") - require((entries & (entries - 1)) == 0, "reduced store commit/free owner entries must be a power of two") - require(identityEntries > 1, "reduced store commit/free owner needs at least two ROB entries") - require((identityEntries & (identityEntries - 1)) == 0, - "reduced store commit/free owner ROB entries must be a power of two") - require(traceParams.robValueWidth >= log2Ceil(identityEntries), "commit ROB value width must cover ROB identities") - - private val ptrWidth = log2Ceil(entries) - private val identityWidth = log2Ceil(identityEntries) - - val io = IO(new ReducedStoreCommitFreeOwnerIO( - entries, - traceParams, - addrWidth, - dataWidth, - peIdWidth, - stidWidth, - tidWidth, - sizeWidth, - simtLaneWidth, - mapQDepth, - lsidWidth, - identityEntries - )) - - private def resize(value: UInt, width: Int): UInt = - if (width <= value.getWidth) value(width - 1, 0) else value.pad(width) - - private def commitStore(slot: Int): Bool = { - val row = io.commit.rows(slot) - io.enable && - io.commitValidMask(slot) && - row.valid && - row.mem.valid && - row.mem.isStore - } - - private def stqRowIdentityValid(stqRow: STQEntryBankRow): Bool = - stqRow.bid.valid && - stqRow.gid.valid && - stqRow.rid.valid - - private def sameCommitIdentity(commitRow: CommitTraceRow, stqRow: STQEntryBankRow): Bool = - stqRowIdentityValid(stqRow) && - resize(commitRow.identity.bid, identityWidth) === stqRow.bid.value && - resize(commitRow.identity.gid, identityWidth) === stqRow.gid.value && - resize(commitRow.identity.rid, identityWidth) === stqRow.rid.value - - private def markable(row: STQEntryBankRow): Bool = - row.valid && - row.rid.valid && - row.status === STQEntryStatus.Wait && - row.storeType === STQStoreType.All && - row.addrReady && - row.dataReady && - row.stid === resize(io.activeStid, stidWidth) - - private def blockInNonFlushPrefix(row: CommitTraceRow): Bool = { - val distance = row.blockBid - io.nonFlushHeadBid - io.nonFlushValid && row.blockBidValid && - distance < io.nonFlushPrefixCount.pad(traceParams.blockBidWidth) - } - - private def scalarEarlySafe( - blockBidValid: Bool, - blockBid: UInt, - storeLsIdValid: Bool, - storeLsId: UInt): Bool = - io.oldestBlockValid && blockBidValid && storeLsIdValid && - blockBid === io.oldestBlockBid && - VecInit((0 until traceParams.commitWidth).map { slot => - val frontier = io.commitMemoryOrder(slot) - frontier.valid && io.commitValidMask(slot) && - io.commit.rows(slot).valid && io.commit.rows(slot).blockBidValid && - io.commit.rows(slot).blockBid === blockBid && - LSIDOrder.less(storeLsId, frontier.lsId) - }).asUInt.orR - - val pendingMark = RegInit(0.U(entries.W)) - val pendingFree = RegInit(0.U(entries.W)) - val pendingCommitValid = RegInit(VecInit(Seq.fill(entries)(false.B))) - val pendingCommitBid = Reg(Vec(entries, UInt(identityWidth.W))) - val pendingCommitGid = Reg(Vec(entries, UInt(identityWidth.W))) - val pendingCommitRid = Reg(Vec(entries, UInt(identityWidth.W))) - val pendingCommitStid = Reg(Vec(entries, UInt(stidWidth.W))) - val pendingCommitBlockBidValid = RegInit(VecInit(Seq.fill(entries)(false.B))) - val pendingCommitBlockBid = Reg(Vec(entries, UInt(traceParams.blockBidWidth.W))) - val pendingCommitLsId = Reg(Vec(entries, UInt(lsidWidth.W))) - val pendingCommitEarlySafe = RegInit(VecInit(Seq.fill(entries)(false.B))) - - private def pendingBlockInNonFlushPrefix(idx: Int): Bool = { - val distance = pendingCommitBlockBid(idx) - io.nonFlushHeadBid - io.nonFlushValid && pendingCommitBlockBidValid(idx) && - pendingCommitStid(idx) === io.activeStid && - distance < io.nonFlushPrefixCount.pad(traceParams.blockBidWidth) - } - - private def pendingAuthorized(idx: Int, row: STQEntryBankRow): Bool = - pendingBlockInNonFlushPrefix(idx) || - (row.scalarIex && (pendingCommitEarlySafe(idx) || scalarEarlySafe( - pendingCommitBlockBidValid(idx), pendingCommitBlockBid(idx), pendingCommitValid(idx), pendingCommitLsId(idx)))) - - private def pendingEarlySafe(idx: Int, row: STQEntryBankRow): Bool = - !pendingBlockInNonFlushPrefix(idx) && row.scalarIex && - (pendingCommitEarlySafe(idx) || scalarEarlySafe( - pendingCommitBlockBidValid(idx), pendingCommitBlockBid(idx), pendingCommitValid(idx), pendingCommitLsId(idx))) - - private def samePendingIdentity(idx: Int, row: STQEntryBankRow): Bool = - pendingCommitValid(idx) && - pendingCommitStid(idx) === row.stid && - pendingAuthorized(idx, row) && - stqRowIdentityValid(row) && - pendingCommitBid(idx) === row.bid.value && - pendingCommitGid(idx) === row.gid.value && - pendingCommitRid(idx) === row.rid.value - - private def samePendingCommit(idx: Int, commitRow: CommitTraceRow): Bool = - pendingCommitValid(idx) && - pendingCommitStid(idx) === io.activeStid && - pendingCommitBlockBidValid(idx) && commitRow.blockBidValid && - pendingCommitBlockBid(idx) === commitRow.blockBid && - pendingCommitBid(idx) === resize(commitRow.identity.bid, identityWidth) && - pendingCommitGid(idx) === resize(commitRow.identity.gid, identityWidth) && - pendingCommitRid(idx) === resize(commitRow.identity.rid, identityWidth) - - val commitStoreVec = VecInit((0 until traceParams.commitWidth).map(commitStore)) - val currentStoreLsId = Wire(Vec(traceParams.commitWidth, UInt(lsidWidth.W))) - val currentStoreEarlySafe = Wire(Vec(traceParams.commitWidth, Bool())) - for (slot <- 0 until traceParams.commitWidth) { - currentStoreLsId(slot) := io.commitMemoryOrder(slot).lsId - currentStoreEarlySafe(slot) := scalarEarlySafe( - io.commit.rows(slot).blockBidValid, - io.commit.rows(slot).blockBid, - io.commitMemoryOrder(slot).valid && io.commitMemoryOrder(slot).isStore, - currentStoreLsId(slot)) - } - val slotMatchVec = Wire(Vec(traceParams.commitWidth, Bool())) - for (slot <- 0 until traceParams.commitWidth) { - slotMatchVec(slot) := - commitStoreVec(slot) && - VecInit((0 until entries).map { idx => - val row = io.stqRows(idx) - markable(row) && sameCommitIdentity(io.commit.rows(slot), row) && - (blockInNonFlushPrefix(io.commit.rows(slot)) || (row.scalarIex && currentStoreEarlySafe(slot))) - }).asUInt.orR - } - - val matchVec = Wire(Vec(entries, Bool())) - val residentEarlySafeVec = Wire(Vec(entries, Bool())) - for (idx <- 0 until entries) { - residentEarlySafeVec(idx) := - markable(io.stqRows(idx)) && io.stqRows(idx).scalarIex && - io.oldestRobValid && io.oldestRobBid.valid && - io.oldestRobStid === io.activeStid && - ROBID.equal(io.stqRows(idx).bid, io.oldestRobBid) && - LSIDOrder.less(io.stqRows(idx).lsIdFull, io.oldestRobLsId) - matchVec(idx) := - markable(io.stqRows(idx)) && - (residentEarlySafeVec(idx) || VecInit((0 until traceParams.commitWidth).map { slot => - commitStoreVec(slot) && - sameCommitIdentity(io.commit.rows(slot), io.stqRows(idx)) && - (blockInNonFlushPrefix(io.commit.rows(slot)) || - (io.stqRows(idx).scalarIex && currentStoreEarlySafe(slot))) - }).asUInt.orR || - VecInit((0 until entries).map(pendingIdx => samePendingIdentity(pendingIdx, io.stqRows(idx)))).asUInt.orR) - } - val matchMask = matchVec.asUInt - val earlySafeMatchVec = Wire(Vec(entries, Bool())) - for (idx <- 0 until entries) { - earlySafeMatchVec(idx) := - markable(io.stqRows(idx)) && - (VecInit((0 until traceParams.commitWidth).map { slot => - commitStoreVec(slot) && sameCommitIdentity(io.commit.rows(slot), io.stqRows(idx)) && - !blockInNonFlushPrefix(io.commit.rows(slot)) && - io.stqRows(idx).scalarIex && currentStoreEarlySafe(slot) - }).asUInt.orR || - VecInit((0 until entries).map(pendingIdx => - pendingCommitValid(pendingIdx) && - pendingCommitStid(pendingIdx) === io.stqRows(idx).stid && - stqRowIdentityValid(io.stqRows(idx)) && - pendingCommitBid(pendingIdx) === io.stqRows(idx).bid.value && - pendingCommitGid(pendingIdx) === io.stqRows(idx).gid.value && - pendingCommitRid(pendingIdx) === io.stqRows(idx).rid.value && - pendingEarlySafe(pendingIdx, io.stqRows(idx)))).asUInt.orR) - } - - val pendingMatchedVec = Wire(Vec(entries, Bool())) - for (pendingIdx <- 0 until entries) { - pendingMatchedVec(pendingIdx) := - pendingCommitValid(pendingIdx) && - VecInit((0 until entries).map(rowIdx => markable(io.stqRows(rowIdx)) && samePendingIdentity(pendingIdx, io.stqRows(rowIdx)))).asUInt.orR - } - val bufferStoreVec = Wire(Vec(traceParams.commitWidth, Bool())) - for (slot <- 0 until traceParams.commitWidth) { - val alreadyPending = - VecInit((0 until entries).map(idx => samePendingCommit(idx, io.commit.rows(slot)))).asUInt.orR - bufferStoreVec(slot) := commitStoreVec(slot) && !slotMatchVec(slot) && !alreadyPending - } - val bufferStoreMask = bufferStoreVec.asUInt - val bufferStoreValid = bufferStoreMask.orR - val bufferStoreSlot = PriorityEncoder(bufferStoreMask) - - val markIndex = PriorityEncoder(pendingMark) - val markValid = io.enable && !io.flushValid && pendingMark.orR - val markOH = Mux(markValid, UIntToOH(markIndex, entries), 0.U(entries.W)) - - val freeIndex = PriorityEncoder(pendingFree) - val freeValid = io.enable && io.directFreeEnable && !io.flushValid && pendingFree.orR - val freeOH = Mux(freeValid, UIntToOH(freeIndex, entries), 0.U(entries.W)) - - io.markCommitValid := markValid - io.markCommitIndex := markIndex - io.commitFreeValid := freeValid - io.commitFreeIndex := freeIndex - - val markAccepted = markValid && io.markCommitAccepted - val freeAccepted = freeValid && io.commitFreeAccepted - - when(!io.enable || io.flushValid) { - pendingMark := 0.U - pendingFree := 0.U - for (idx <- 0 until entries) { - pendingCommitValid(idx) := false.B - } - }.otherwise { - val nextMark = (pendingMark | matchMask) & ~Mux(markAccepted, markOH, 0.U(entries.W)) - val nextFree = Mux( - io.directFreeEnable, - (pendingFree | Mux(markAccepted, markOH, 0.U(entries.W))) & ~Mux(freeAccepted, freeOH, 0.U(entries.W)), - 0.U(entries.W)) - pendingMark := nextMark - pendingFree := nextFree - - val basePendingValid = Wire(Vec(entries, Bool())) - val nextPendingValid = Wire(Vec(entries, Bool())) - val nextPendingBid = Wire(Vec(entries, UInt(identityWidth.W))) - val nextPendingGid = Wire(Vec(entries, UInt(identityWidth.W))) - val nextPendingRid = Wire(Vec(entries, UInt(identityWidth.W))) - val nextPendingStid = Wire(Vec(entries, UInt(stidWidth.W))) - val nextPendingBlockBidValid = Wire(Vec(entries, Bool())) - val nextPendingBlockBid = Wire(Vec(entries, UInt(traceParams.blockBidWidth.W))) - val nextPendingLsId = Wire(Vec(entries, UInt(lsidWidth.W))) - val nextPendingEarlySafe = Wire(Vec(entries, Bool())) - for (idx <- 0 until entries) { - basePendingValid(idx) := pendingCommitValid(idx) && !pendingMatchedVec(idx) - nextPendingValid(idx) := basePendingValid(idx) - nextPendingBid(idx) := pendingCommitBid(idx) - nextPendingGid(idx) := pendingCommitGid(idx) - nextPendingRid(idx) := pendingCommitRid(idx) - nextPendingStid(idx) := pendingCommitStid(idx) - nextPendingBlockBidValid(idx) := pendingCommitBlockBidValid(idx) - nextPendingBlockBid(idx) := pendingCommitBlockBid(idx) - nextPendingLsId(idx) := pendingCommitLsId(idx) - nextPendingEarlySafe(idx) := pendingCommitEarlySafe(idx) || scalarEarlySafe( - pendingCommitBlockBidValid(idx), pendingCommitBlockBid(idx), - pendingCommitValid(idx), pendingCommitLsId(idx)) - } - val pendingIdentityFreeMask = VecInit((0 until entries).map(idx => !basePendingValid(idx))).asUInt - val pendingIdentityFreeOH = PriorityEncoderOH(pendingIdentityFreeMask) - val bufferRow = io.commit.rows(bufferStoreSlot) - for (idx <- 0 until entries) { - when(bufferStoreValid && pendingIdentityFreeOH(idx)) { - nextPendingValid(idx) := true.B - nextPendingBid(idx) := resize(bufferRow.identity.bid, identityWidth) - nextPendingGid(idx) := resize(bufferRow.identity.gid, identityWidth) - nextPendingRid(idx) := resize(bufferRow.identity.rid, identityWidth) - nextPendingStid(idx) := io.activeStid - nextPendingBlockBidValid(idx) := bufferRow.blockBidValid - nextPendingBlockBid(idx) := bufferRow.blockBid - nextPendingLsId(idx) := currentStoreLsId(bufferStoreSlot) - nextPendingEarlySafe(idx) := currentStoreEarlySafe(bufferStoreSlot) - } - } - for (idx <- 0 until entries) { - pendingCommitValid(idx) := nextPendingValid(idx) - pendingCommitBid(idx) := nextPendingBid(idx) - pendingCommitGid(idx) := nextPendingGid(idx) - pendingCommitRid(idx) := nextPendingRid(idx) - pendingCommitStid(idx) := nextPendingStid(idx) - pendingCommitBlockBidValid(idx) := nextPendingBlockBidValid(idx) - pendingCommitBlockBid(idx) := nextPendingBlockBid(idx) - pendingCommitLsId(idx) := nextPendingLsId(idx) - pendingCommitEarlySafe(idx) := nextPendingEarlySafe(idx) - } - } - - val unmatchedSlotVec = VecInit((0 until traceParams.commitWidth).map(slot => commitStoreVec(slot) && !slotMatchVec(slot))) - io.commitStoreSeen := commitStoreVec.asUInt.orR - io.commitStoreMatched := slotMatchVec.asUInt.orR - io.commitStoreUnmatched := unmatchedSlotVec.asUInt.orR - io.commitStoreBlockedByNonFlush := VecInit((0 until traceParams.commitWidth).map { slot => - commitStoreVec(slot) && !blockInNonFlushPrefix(io.commit.rows(slot)) && !currentStoreEarlySafe(slot) - }).asUInt.orR - io.commitStoreReleasedByEarlySafe := VecInit((0 until traceParams.commitWidth).map { slot => - commitStoreVec(slot) && !blockInNonFlushPrefix(io.commit.rows(slot)) && currentStoreEarlySafe(slot) - }).asUInt.orR - io.matchMask := matchMask - io.earlySafeMatchMask := earlySafeMatchVec.asUInt - io.pendingCommitIdentityMask := pendingCommitValid.asUInt - io.pendingCommitEarlySafeMask := VecInit((0 until entries).map(idx => - pendingCommitValid(idx) && pendingCommitEarlySafe(idx))).asUInt - io.residentEarlySafeMask := residentEarlySafeVec.asUInt - io.pendingMarkMask := pendingMark - io.pendingFreeMask := pendingFree - io.pendingMarkCount := PopCount(pendingMark) - io.pendingFreeCount := PopCount(pendingFree) - io.markBlocked := markValid && !io.markCommitAccepted - io.freeBlocked := freeValid && !io.commitFreeAccepted - io.idle := !pendingMark.orR && (!io.directFreeEnable || !pendingFree.orR) -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreExecResultBridge.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreExecResultBridge.scala deleted file mode 100644 index 5bbe989b..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreExecResultBridge.scala +++ /dev/null @@ -1,256 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.{log2Ceil, Mux1H, PopCount, PriorityEncoder} - -import linxcore.commit.{CommitTraceParams, CommitTraceRow} -import linxcore.common.InterfaceParams -import linxcore.rename.{StoreSplitIssuePayload, StoreSplitStoreType} -import linxcore.rob.ROBID - -class ReducedStoreExecResultEntry( - val robEntries: Int, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val stidWidth: Int = 8, - val sizeWidth: Int = 4) - extends Bundle { - val valid = Bool() - val bid = new ROBID(robEntries) - val rid = new ROBID(robEntries) - val stid = UInt(stidWidth.W) - val addr = UInt(addrWidth.W) - val data = UInt(dataWidth.W) - val size = UInt(sizeWidth.W) -} - -class ReducedStoreExecResultBridgeIO( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams(), - val bufferEntries: Int = 4, - val mapQDepth: Int = 32, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8) - extends Bundle { - private val countWidth = log2Ceil(bufferEntries + 1) - - val flushValid = Input(Bool()) - val completeValid = Input(Bool()) - val completeStoreDispatch = Input(Bool()) - val completeRow = Input(new CommitTraceRow(traceParams)) - val completeBid = Input(new ROBID(p.robEntries)) - val completeRid = Input(new ROBID(p.robEntries)) - val completeStid = Input(UInt(stidWidth.W)) - - val staQueueValid = Input(Bool()) - val staQueue = Input(new StoreSplitIssuePayload(p, mapQDepth)) - val stdQueueValid = Input(Bool()) - val stdQueue = Input(new StoreSplitIssuePayload(p, mapQDepth)) - val staConsumed = Input(Bool()) - val stdConsumed = Input(Bool()) - - val staExec = Output(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - val stdExec = Output(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - val completeStoreValid = Output(Bool()) - val captureFire = Output(Bool()) - val captureBlocked = Output(Bool()) - val captureDuplicate = Output(Bool()) - val staMatch = Output(Bool()) - val stdMatch = Output(Bool()) - val validMask = Output(UInt(bufferEntries.W)) - val bufferCount = Output(UInt(countWidth.W)) -} - -class ReducedStoreExecResultBridge( - val p: InterfaceParams = InterfaceParams(), - val traceParams: CommitTraceParams = CommitTraceParams(), - val bufferEntries: Int = 4, - val mapQDepth: Int = 32, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8, - val stdDelayCycles: Int = 0) - extends Module { - require(bufferEntries > 1, "reduced store exec bridge needs at least two result entries") - require((bufferEntries & (bufferEntries - 1)) == 0, "reduced store exec bridge depth must be a power of two") - require(traceParams.dataWidth >= dataWidth, "commit trace data must hold store data") - require(traceParams.dataWidth >= addrWidth, "commit trace data must hold store address") - require(traceParams.robValueWidth >= p.robIndexWidth, "commit trace ROB width must cover ROB ids") - require(stdDelayCycles >= 0, "STD delay cycles must be nonnegative") - - val io = IO(new ReducedStoreExecResultBridgeIO( - p, - traceParams, - bufferEntries, - mapQDepth, - addrWidth, - dataWidth, - peIdWidth, - stidWidth, - tidWidth, - sizeWidth, - simtLaneWidth - )) - - private def resize(value: UInt, width: Int): UInt = - if (width <= value.getWidth) value(width - 1, 0) else value.pad(width) - - private def zeroEntry: ReducedStoreExecResultEntry = { - val entry = Wire(new ReducedStoreExecResultEntry(p.robEntries, addrWidth, dataWidth, stidWidth, sizeWidth)) - entry := 0.U.asTypeOf(entry) - entry.bid := ROBID.disabled(p.robEntries) - entry.rid := ROBID.disabled(p.robEntries) - entry - } - - private def zeroExec: StoreDispatchExecResult = { - val exec = Wire(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - exec := 0.U.asTypeOf(exec) - exec - } - - private def samePayload(entry: ReducedStoreExecResultEntry, payload: StoreSplitIssuePayload): Bool = - entry.valid && - payload.valid && - ROBID.equal(entry.bid, payload.uop.bid) && - ROBID.equal(entry.rid, payload.uop.rid) && - entry.stid === resize(payload.uop.threadId, stidWidth) - - private def sameComplete(entry: ReducedStoreExecResultEntry): Bool = - entry.valid && - ROBID.equal(entry.bid, io.completeBid) && - ROBID.equal(entry.rid, io.completeRid) && - entry.stid === io.completeStid - - private def execFromEntry(entry: ReducedStoreExecResultEntry, payload: StoreSplitIssuePayload): StoreDispatchExecResult = { - val exec = Wire(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - exec := 0.U.asTypeOf(exec) - exec.valid := entry.valid && payload.valid - exec.addr := entry.addr - exec.data := entry.data - exec.size := entry.size - exec.peId := resize(payload.uop.peId, peIdWidth) - exec.stid := resize(payload.uop.threadId, stidWidth) - exec.tid := resize(payload.uop.threadId, tidWidth) - exec.stackValid := false.B - exec.scalarIex := true.B - exec.simtLane := 0.U - exec - } - - val entries = RegInit(VecInit(Seq.fill(bufferEntries)(zeroEntry))) - - // Commit rows also describe implicit architectural memory effects such as - // CALL/ICALL return-stack writes. Those effects never allocate STA/STD - // payloads and therefore must not consume this queue-matching result buffer. - // The renamed-uop store classification is the ownership bit shared with the - // StoreSplitPayload producer; mem.isStore alone is deliberately insufficient. - val completeStoreValid = - !io.flushValid && io.completeValid && io.completeStoreDispatch && - io.completeRow.mem.valid && io.completeRow.mem.isStore - val completeEntry = Wire(new ReducedStoreExecResultEntry(p.robEntries, addrWidth, dataWidth, stidWidth, sizeWidth)) - completeEntry := zeroEntry - completeEntry.valid := true.B - completeEntry.bid := io.completeBid - completeEntry.rid := io.completeRid - completeEntry.stid := io.completeStid - completeEntry.addr := resize(io.completeRow.mem.addr, addrWidth) - completeEntry.data := resize(io.completeRow.mem.wdata, dataWidth) - completeEntry.size := resize(io.completeRow.mem.size, sizeWidth) - - val staHitVec = VecInit((0 until bufferEntries).map(idx => - io.staQueueValid && samePayload(entries(idx), io.staQueue))) - val stdHitVec = VecInit((0 until bufferEntries).map(idx => - io.stdQueueValid && samePayload(entries(idx), io.stdQueue))) - val staHit = staHitVec.asUInt.orR - val stdHit = stdHitVec.asUInt.orR - val staIndex = PriorityEncoder(staHitVec.asUInt) - val stdIndex = PriorityEncoder(stdHitVec.asUInt) - - val duplicateVec = VecInit((0 until bufferEntries).map(idx => sameComplete(entries(idx)))) - val duplicateCapture = completeStoreValid && duplicateVec.asUInt.orR - val clearVec = Wire(Vec(bufferEntries, Bool())) - for (idx <- 0 until bufferEntries) { - val staClearsUnsplit = - io.staConsumed && staHitVec(idx) && (io.staQueue.storeType === StoreSplitStoreType.All) - val stdClearsSplit = io.stdConsumed && stdHitVec(idx) - clearVec(idx) := staClearsUnsplit || stdClearsSplit - } - - io.staExec := Mux(staHit, execFromEntry(entries(staIndex), io.staQueue), zeroExec) - val rawStdExec = Mux(stdHit, execFromEntry(entries(stdIndex), io.stdQueue), zeroExec) - val stdDelayActiveVec = - if (stdDelayCycles > 0) { - val width = math.max(1, log2Ceil(stdDelayCycles + 1)) - val counters = RegInit(VecInit(Seq.fill(bufferEntries)(0.U(width.W)))) - val activeVec = VecInit((0 until bufferEntries).map(idx => counters(idx) =/= 0.U)) - val staArmsDelayVec = VecInit((0 until bufferEntries).map(idx => - io.staConsumed && staHitVec(idx) && (io.staQueue.storeType === StoreSplitStoreType.Addr))) - - when(io.flushValid) { - for (idx <- 0 until bufferEntries) { - counters(idx) := 0.U - } - }.otherwise { - for (idx <- 0 until bufferEntries) { - when(clearVec(idx)) { - counters(idx) := 0.U - }.elsewhen(staArmsDelayVec(idx)) { - counters(idx) := stdDelayCycles.U - }.elsewhen(counters(idx) =/= 0.U) { - counters(idx) := counters(idx) - 1.U - } - } - } - - activeVec - } else { - VecInit(Seq.fill(bufferEntries)(false.B)) - } - val stdExec = Wire(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - stdExec := rawStdExec - when(stdHit && stdDelayActiveVec(stdIndex)) { - stdExec.valid := false.B - } - io.stdExec := stdExec - io.staMatch := staHit - io.stdMatch := stdHit - - val freeVec = VecInit((0 until bufferEntries).map(idx => !entries(idx).valid || clearVec(idx))) - val freeMask = freeVec.asUInt - val firstFreeValid = freeMask.orR - val firstFreeIndex = PriorityEncoder(freeMask) - val captureFire = completeStoreValid && !duplicateCapture && firstFreeValid - - when(io.flushValid) { - for (idx <- 0 until bufferEntries) { - entries(idx) := zeroEntry - } - }.otherwise { - for (idx <- 0 until bufferEntries) { - when(clearVec(idx)) { - entries(idx) := zeroEntry - } - } - when(captureFire) { - entries(firstFreeIndex) := completeEntry - } - } - - val validVec = VecInit(entries.map(_.valid)) - io.completeStoreValid := completeStoreValid - io.captureFire := captureFire - io.captureBlocked := completeStoreValid && !duplicateCapture && !firstFreeValid - io.captureDuplicate := duplicateCapture - io.validMask := validVec.asUInt - io.bufferCount := PopCount(validVec.asUInt) -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreMemoryOverlay.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreMemoryOverlay.scala deleted file mode 100644 index e966e719..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreMemoryOverlay.scala +++ /dev/null @@ -1,184 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.{Cat, OHToUInt, PopCount, PriorityEncoderOH, log2Ceil} - -class ReducedStoreMemoryOverlayLine(val addrWidth: Int = 64, val lineBytes: Int = 64) extends Bundle { - val valid = Bool() - val lineAddr = UInt(addrWidth.W) - val byteMask = UInt(lineBytes.W) - val data = UInt((lineBytes * 8).W) -} - -class ReducedStoreMemoryOverlayIO( - val stqEntries: Int, - val requestCount: Int, - val lineEntries: Int, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val sizeWidth: Int = 4, - val lineBytes: Int = 64, - val robEntries: Int = 0, - val lsidWidth: Int = 32) - extends Bundle { - private val identityEntries = if (robEntries > 0) robEntries else stqEntries - private val lineCountWidth = log2Ceil(lineEntries + 1) - - val flush = Input(Bool()) - val storeReqs = Input(Vec(requestCount, - new STQCommitDrainRequest(stqEntries, addrWidth, dataWidth, sizeWidth, identityEntries, lsidWidth))) - val storeAcceptedMask = Input(UInt(requestCount.W)) - - val loadValid = Input(Bool()) - val loadAddr = Input(UInt(addrWidth.W)) - val baseLoadData = Input(UInt(dataWidth.W)) - val loadData = Output(UInt(dataWidth.W)) - val loadForwardMask = Output(UInt((dataWidth / 8).W)) - - val lines = Output(Vec(lineEntries, new ReducedStoreMemoryOverlayLine(addrWidth, lineBytes))) - val validMask = Output(UInt(lineEntries.W)) - val lineCount = Output(UInt(lineCountWidth.W)) - val storeDroppedMask = Output(UInt(requestCount.W)) -} - -class ReducedStoreMemoryOverlay( - val stqEntries: Int = 16, - val requestCount: Int = 4, - val lineEntries: Int = 16, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val sizeWidth: Int = 4, - val lineBytes: Int = 64, - val robEntries: Int = 0, - val lsidWidth: Int = 32) - extends Module { - private val identityEntries = if (robEntries > 0) robEntries else stqEntries - require(stqEntries > 1, "STQ entries must be greater than one") - require(identityEntries > 1 && (identityEntries & (identityEntries - 1)) == 0, - "ROB entries must be a power of two greater than one") - require(requestCount > 0, "store overlay request count must be nonzero") - require(lineEntries > 0, "store overlay line entries must be nonzero") - require(addrWidth >= 7, "store overlay needs 64-byte line addresses") - require(dataWidth == 64, "store overlay currently serves 64-bit scalar load lookups") - require(sizeWidth >= 4, "store overlay scalar store sizes require at least 4 bits") - require(lineBytes == 64, "store overlay currently models 64-byte scalar cachelines") - - private val loadBytes = dataWidth / 8 - private val offsetWidth = log2Ceil(lineBytes) - private val lineCountWidth = log2Ceil(lineEntries + 1) - - val io = IO(new ReducedStoreMemoryOverlayIO( - stqEntries, - requestCount, - lineEntries, - addrWidth, - dataWidth, - sizeWidth, - lineBytes, - identityEntries, - lsidWidth)) - - private def zeroLine: ReducedStoreMemoryOverlayLine = { - val line = Wire(new ReducedStoreMemoryOverlayLine(addrWidth, lineBytes)) - line := 0.U.asTypeOf(line) - line - } - - private def lineAddr(addr: UInt): UInt = - Cat(addr(addrWidth - 1, offsetWidth), 0.U(offsetWidth.W)) - - private def requestByteMask(addr: UInt, size: UInt): UInt = { - val mask = Wire(Vec(lineBytes, Bool())) - val offset = Wire(UInt(7.W)) - val sizeWide = Wire(UInt(7.W)) - offset := addr(offsetWidth - 1, 0) - sizeWide := size - val end = offset +& sizeWide - for (byte <- 0 until lineBytes) { - val byteIdx = byte.U(7.W) - mask(byte) := (sizeWide =/= 0.U) && (byteIdx >= offset) && (byteIdx < end) - } - mask.asUInt - } - - private def mergeData(oldData: UInt, req: STQCommitDrainRequest, byteMask: UInt): UInt = { - val mergedBytes = Wire(Vec(lineBytes, UInt(8.W))) - val offset = Wire(UInt(7.W)) - offset := req.addr(offsetWidth - 1, 0) - for (byte <- 0 until lineBytes) { - val byteIdx = byte.U(7.W) - val reqByteOffset = byteIdx - offset - val reqByte = (req.data >> (reqByteOffset << 3))(7, 0) - val oldByte = oldData((byte * 8) + 7, byte * 8) - mergedBytes(byte) := Mux(byteMask(byte), reqByte, oldByte) - } - Cat(mergedBytes.reverse) - } - - val lines = RegInit(VecInit(Seq.fill(lineEntries)(zeroLine))) - val ingressStages = Seq.fill(requestCount + 1)(Wire(Vec(lineEntries, new ReducedStoreMemoryOverlayLine(addrWidth, lineBytes)))) - ingressStages.head := lines - - val droppedVec = Wire(Vec(requestCount, Bool())) - for (lane <- 0 until requestCount) { - val req = io.storeReqs(lane) - val accepted = io.storeAcceptedMask(lane) && req.valid - val reqLine = lineAddr(req.addr) - val hitVec = VecInit((0 until lineEntries).map(idx => - ingressStages(lane)(idx).valid && ingressStages(lane)(idx).lineAddr === reqLine)) - val freeVec = VecInit((0 until lineEntries).map(idx => !ingressStages(lane)(idx).valid)) - val hit = hitVec.asUInt.orR - val free = freeVec.asUInt.orR - val targetValid = hit || free - val targetIndex = OHToUInt(PriorityEncoderOH(Mux(hit, hitVec.asUInt, freeVec.asUInt))) - val byteMask = requestByteMask(req.addr, req.size) - val oldLine = ingressStages(lane)(targetIndex) - val nextLine = Wire(new ReducedStoreMemoryOverlayLine(addrWidth, lineBytes)) - - ingressStages(lane + 1) := ingressStages(lane) - nextLine := oldLine - nextLine.valid := true.B - nextLine.lineAddr := reqLine - nextLine.byteMask := oldLine.byteMask | byteMask - nextLine.data := mergeData(oldLine.data, req, byteMask) - droppedVec(lane) := accepted && !targetValid - - when(accepted && targetValid) { - ingressStages(lane + 1)(targetIndex) := nextLine - } - } - - when(io.flush) { - for (idx <- 0 until lineEntries) { - lines(idx) := zeroLine - } - }.otherwise { - lines := ingressStages.last - } - - val outBytes = Wire(Vec(loadBytes, UInt(8.W))) - val forwardVec = Wire(Vec(loadBytes, Bool())) - for (byte <- 0 until loadBytes) { - val byteAddr = io.loadAddr + byte.U(addrWidth.W) - val byteLineAddr = lineAddr(byteAddr) - val byteOffset = byteAddr(offsetWidth - 1, 0) - var selectedByte: UInt = io.baseLoadData((byte * 8) + 7, byte * 8) - var selectedHit: Bool = false.B - for (idx <- 0 until lineEntries) { - val hit = io.loadValid && lines(idx).valid && lines(idx).lineAddr === byteLineAddr && lines(idx).byteMask(byteOffset) - val lineByte = (lines(idx).data >> (byteOffset << 3))(7, 0) - selectedByte = Mux(hit, lineByte, selectedByte) - selectedHit = selectedHit || hit - } - outBytes(byte) := selectedByte - forwardVec(byte) := selectedHit - } - - val validVec = VecInit(lines.map(_.valid)) - io.loadData := Cat(outBytes.reverse) - io.loadForwardMask := forwardVec.asUInt - io.lines := lines - io.validMask := validVec.asUInt - io.lineCount := PopCount(validVec.asUInt)(lineCountWidth - 1, 0) - io.storeDroppedMask := droppedVec.asUInt -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreNonFlushGateProbe.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreNonFlushGateProbe.scala deleted file mode 100644 index c860f243..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreNonFlushGateProbe.scala +++ /dev/null @@ -1,113 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import circt.stage.ChiselStage -import linxcore.commit.CommitTraceParams - -class ReducedStoreNonFlushGateProbeIO extends Bundle { - val flushValid = Input(Bool()) - val commitValid = Input(Bool()) - val commitStore = Input(Bool()) - val commitBlockBid = Input(UInt(64.W)) - val commitLsId = Input(UInt(32.W)) - val rowValid = Input(Bool()) - val rowScalarIex = Input(Bool()) - val nonFlushValid = Input(Bool()) - val nonFlushHeadBid = Input(UInt(64.W)) - val nonFlushPrefixCount = Input(UInt(3.W)) - val oldestBlockValid = Input(Bool()) - val oldestBlockBid = Input(UInt(64.W)) - val oldestRobValid = Input(Bool()) - val oldestRobBid = Input(UInt(2.W)) - val oldestRobLsId = Input(UInt(32.W)) - - val blockedByNonFlush = Output(Bool()) - val pendingMarkMask = Output(UInt(4.W)) - val earlySafeMatchMask = Output(UInt(4.W)) - val residentEarlySafeMask = Output(UInt(4.W)) - val markValid = Output(Bool()) - val markIndex = Output(UInt(2.W)) -} - -class ReducedStoreNonFlushGateProbe extends Module { - private val traceParams = CommitTraceParams(commitWidth = 1, robValueWidth = 2) - val io = IO(new ReducedStoreNonFlushGateProbeIO) - val owner = Module(new ReducedStoreCommitFreeOwner( - entries = 4, - traceParams = traceParams, - stidWidth = 2, - tidWidth = 2, - mapQDepth = 4)) - - owner.io.enable := true.B - owner.io.directFreeEnable := false.B - owner.io.flushValid := io.flushValid - owner.io.activeStid := 0.U - owner.io.nonFlushValid := io.nonFlushValid - owner.io.nonFlushHeadBid := io.nonFlushHeadBid - owner.io.nonFlushPrefixCount := io.nonFlushPrefixCount - owner.io.oldestBlockValid := io.oldestBlockValid - owner.io.oldestBlockBid := io.oldestBlockBid - owner.io.oldestRobValid := io.oldestRobValid - owner.io.oldestRobBid.valid := io.oldestRobValid - owner.io.oldestRobBid.wrap := false.B - owner.io.oldestRobBid.value := io.oldestRobBid - owner.io.oldestRobLsId := io.oldestRobLsId - owner.io.oldestRobStid := 0.U - - owner.io.commit := 0.U.asTypeOf(owner.io.commit) - owner.io.commit.rows(0).valid := io.commitValid - owner.io.commit.rows(0).identity.bid := 1.U - owner.io.commit.rows(0).identity.gid := 2.U - owner.io.commit.rows(0).identity.rid := 3.U - owner.io.commit.rows(0).blockBidValid := io.commitValid - owner.io.commit.rows(0).blockBid := io.commitBlockBid - owner.io.commit.rows(0).mem.valid := io.commitValid && io.commitStore - owner.io.commit.rows(0).mem.isStore := io.commitStore - owner.io.commitValidMask := io.commitValid - owner.io.commitMemoryOrder := 0.U.asTypeOf(owner.io.commitMemoryOrder) - owner.io.commitMemoryOrder(0).valid := io.commitValid - owner.io.commitMemoryOrder(0).isLoadStore := io.commitStore - owner.io.commitMemoryOrder(0).isStore := io.commitStore - owner.io.commitMemoryOrder(0).lsId := io.commitLsId - - val rows = Wire(Vec(4, new STQEntryBankRow(4, stidWidth = 2, tidWidth = 2, mapQDepth = 4))) - rows := 0.U.asTypeOf(rows) - rows(0).valid := io.rowValid - rows(0).status := STQEntryStatus.Wait - rows(0).storeType := STQStoreType.All - rows(0).stid := 0.U - rows(0).bid.valid := io.rowValid - rows(0).bid.value := 1.U - rows(0).gid.valid := io.rowValid - rows(0).gid.value := 2.U - rows(0).rid.valid := io.rowValid - rows(0).rid.value := 3.U - rows(0).addrReady := io.rowValid - rows(0).dataReady := io.rowValid - rows(0).scalarIex := io.rowScalarIex - rows(0).lsId.valid := io.rowValid - rows(0).lsId.value := 1.U - owner.io.stqRows := rows - - owner.io.markCommitAccepted := false.B - owner.io.markCommitIgnored := false.B - owner.io.commitFreeAccepted := false.B - owner.io.commitFreeIgnored := false.B - owner.io.commitFreeAcceptedMask := 0.U - owner.io.commitFreeIgnoredMask := 0.U - - io.blockedByNonFlush := owner.io.commitStoreBlockedByNonFlush - io.pendingMarkMask := owner.io.pendingMarkMask - io.earlySafeMatchMask := owner.io.earlySafeMatchMask - io.residentEarlySafeMask := owner.io.residentEarlySafeMask - io.markValid := owner.io.markCommitValid - io.markIndex := owner.io.markCommitIndex -} - -object EmitReducedStoreNonFlushGateProbe extends App { - ChiselStage.emitSystemVerilogFile( - new ReducedStoreNonFlushGateProbe, - args, - firtoolOpts = Array("--disable-all-randomization", "--strip-debug-info")) -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreResidentForward.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreResidentForward.scala deleted file mode 100644 index 34a81d69..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreResidentForward.scala +++ /dev/null @@ -1,186 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.{Cat, log2Ceil} - -import linxcore.rob.ROBID - -class ReducedStoreResidentForwardIO( - val entries: Int, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8, - val mapQDepth: Int = 32, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val robEntries: Int = 0, - val lsidWidth: Int = 32) - extends Bundle { - private val identityEntries = if (robEntries > 0) robEntries else entries - val enable = Input(Bool()) - val loadValid = Input(Bool()) - val loadAddr = Input(UInt(addrWidth.W)) - val loadSize = Input(UInt(sizeWidth.W)) - val loadBid = Input(new ROBID(identityEntries)) - val loadLsId = Input(new ROBID(identityEntries)) - val loadLsIdFullValid = Input(Bool()) - val loadLsIdFull = Input(UInt(lsidWidth.W)) - val baseLoadData = Input(UInt(dataWidth.W)) - val rows = Input(Vec(entries, new STQEntryBankRow( - identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, - sizeWidth, simtLaneWidth, mapQDepth, pcWidth, lsidWidth))) - - val loadData = Output(UInt(dataWidth.W)) - val loadForwardMask = Output(UInt((dataWidth / 8).W)) - val waitMask = Output(UInt((dataWidth / 8).W)) - val eligibleStoreMask = Output(UInt(entries.W)) - val fullLsIdMissingMask = Output(UInt(entries.W)) - val fullLsIdAmbiguousMask = Output(UInt(entries.W)) - val waitStore = Output(new LoadStoreForwardWait(identityEntries, entries, pcWidth, lsidWidth)) - val readyForward = Output(Bool()) - val waitBlocked = Output(Bool()) - val loadCrossesLine = Output(Bool()) -} - -class ReducedStoreResidentForward( - val entries: Int = 16, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8, - val mapQDepth: Int = 32, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val robEntries: Int = 0, - val lsidWidth: Int = 32) - extends Module { - private val identityEntries = if (robEntries > 0) robEntries else entries - require(entries > 1, "resident store forwarding needs at least two STQ entries") - require((entries & (entries - 1)) == 0, "resident store forwarding STQ entries must be a power of two") - require(addrWidth >= 7, "resident store forwarding needs 64-byte line addresses") - require(dataWidth == 64, "resident store forwarding currently serves 64-bit scalar load lookups") - require(sizeWidth >= 4, "resident store forwarding scalar load/store sizes require at least 4 bits") - require(lineBytes == 64, "resident store forwarding currently models 64-byte scalar cachelines") - - private val loadBytes = dataWidth / 8 - private val offsetWidth = log2Ceil(lineBytes) - - val io = IO(new ReducedStoreResidentForwardIO( - entries, - addrWidth, - dataWidth, - peIdWidth, - stidWidth, - tidWidth, - sizeWidth, - simtLaneWidth, - mapQDepth, - pcWidth, - lineBytes, - identityEntries, - lsidWidth - )) - - private def lineAddr(addr: UInt): UInt = - Cat(addr(addrWidth - 1, offsetWidth), 0.U(offsetWidth.W)) - - private def crossesLine(addr: UInt, size: UInt): Bool = { - val offset = Wire(UInt(7.W)) - val sizeWide = Wire(UInt(7.W)) - offset := addr(offsetWidth - 1, 0) - sizeWide := size - (offset +& sizeWide) > lineBytes.U - } - - private def baseLineData(loadAddr: UInt, baseLoadData: UInt): UInt = { - val bytes = Wire(Vec(lineBytes, UInt(8.W))) - for (byte <- 0 until lineBytes) { - bytes(byte) := 0.U - } - val offset = Wire(UInt(7.W)) - offset := loadAddr(offsetWidth - 1, 0) - for (loadByte <- 0 until loadBytes) { - val target = offset + loadByte.U(7.W) - for (byte <- 0 until lineBytes) { - when(target === byte.U) { - bytes(byte) := baseLoadData((loadByte * 8) + 7, loadByte * 8) - } - } - } - Cat(bytes.reverse) - } - - val loadCrosses = crossesLine(io.loadAddr, io.loadSize) - val queryValid = io.enable && io.loadValid && (io.loadSize =/= 0.U) && !loadCrosses - val storeSnapshot = Module(new ResidentStoreForwardStoreSnapshot( - entries, - addrWidth, - dataWidth, - peIdWidth, - stidWidth, - tidWidth, - sizeWidth, - simtLaneWidth, - mapQDepth, - pcWidth, - lineBytes, - identityEntries, - lsidWidth - )) - val forward = Module(new LoadStoreForwarding( - identityEntries, entries, addrWidth, pcWidth, lineBytes, sizeWidth = 7, - lsidWidth = lsidWidth)) - - storeSnapshot.io.enable := io.enable - storeSnapshot.io.rows := io.rows - - forward.io.query.valid := queryValid - forward.io.query.lineAddr := lineAddr(io.loadAddr) - forward.io.query.byteOffset := io.loadAddr(offsetWidth - 1, 0) - forward.io.query.size := io.loadSize - forward.io.query.youngestStoreId := io.loadBid - forward.io.query.youngestStoreLsId := io.loadLsId - forward.io.query.youngestStoreLsIdFullValid := io.loadLsIdFullValid - forward.io.query.youngestStoreLsIdFull := io.loadLsIdFull - forward.io.query.isTile := false.B - forward.io.cacheData := baseLineData(io.loadAddr, io.baseLoadData) - - for (idx <- 0 until entries) { - forward.io.stores(idx) := storeSnapshot.io.stores(idx) - } - - val loadOffset = Wire(UInt(7.W)) - loadOffset := io.loadAddr(offsetWidth - 1, 0) - val outBytes = Wire(Vec(loadBytes, UInt(8.W))) - val forwardVec = Wire(Vec(loadBytes, Bool())) - val waitVec = Wire(Vec(loadBytes, Bool())) - for (byte <- 0 until loadBytes) { - val lineByte = loadOffset + byte.U(7.W) - outBytes(byte) := (forward.io.mergedData >> (lineByte << 3))(7, 0) - forwardVec(byte) := (forward.io.forwardMask >> lineByte)(0) - waitVec(byte) := (forward.io.waitMask >> lineByte)(0) - } - - val windowForwardMask = forwardVec.asUInt - val windowWaitMask = waitVec.asUInt - val waitBlocked = queryValid && windowWaitMask.orR - val readyForward = queryValid && !waitBlocked && windowForwardMask.orR - - io.loadData := Mux(queryValid && !waitBlocked, Cat(outBytes.reverse), io.baseLoadData) - io.loadForwardMask := Mux(queryValid && !waitBlocked, windowForwardMask, 0.U) - io.waitMask := Mux(queryValid, windowWaitMask, 0.U) - io.eligibleStoreMask := forward.io.eligibleStoreMask - io.fullLsIdMissingMask := forward.io.fullLsIdMissingMask - io.fullLsIdAmbiguousMask := forward.io.fullLsIdAmbiguousMask - io.waitStore := forward.io.waitStore - io.readyForward := readyForward - io.waitBlocked := waitBlocked - io.loadCrossesLine := io.enable && io.loadValid && loadCrosses -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreStaAddressExecBridge.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreStaAddressExecBridge.scala deleted file mode 100644 index 4df3bdf5..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreStaAddressExecBridge.scala +++ /dev/null @@ -1,203 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util._ - -import linxcore.common.InterfaceParams -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rename.{StoreSplitIssuePayload, StoreSplitStoreType} - -class ReducedStoreStaAddressExecBridgeIO( - val p: InterfaceParams = InterfaceParams(), - val mapQDepth: Int = 32, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8) - extends Bundle { - val enable = Input(Bool()) - val queueValid = Input(Bool()) - val queue = Input(new StoreSplitIssuePayload(p, mapQDepth)) - val srcReadReady = Input(Vec(3, Bool())) - val srcReadData = Input(Vec(3, UInt(dataWidth.W))) - - val exec = Output(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - val candidate = Output(Bool()) - val supportedOpcode = Output(Bool()) - val addrSourceMask = Output(UInt(3.W)) - val addrSourceReady = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByUnsupported = Output(Bool()) -} - -class ReducedStoreStaAddressExecBridge( - val p: InterfaceParams = InterfaceParams(), - val mapQDepth: Int = 32, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val peIdWidth: Int = 8, - val stidWidth: Int = 8, - val tidWidth: Int = 8, - val sizeWidth: Int = 4, - val simtLaneWidth: Int = 8) - extends Module { - require(addrWidth == dataWidth, "reduced STA bridge expects address and data operands to share a width") - require(p.immWidth <= addrWidth, "reduced STA bridge expects immediates to fit in the address width") - - val io = IO(new ReducedStoreStaAddressExecBridgeIO( - p, - mapQDepth, - addrWidth, - dataWidth, - peIdWidth, - stidWidth, - tidWidth, - sizeWidth, - simtLaneWidth - )) - - private def opcode(value: Int): UInt = - value.U(p.opcodeWidth.W) - - private def resize(value: UInt, width: Int): UInt = - if (width <= value.getWidth) value(width - 1, 0) else value.pad(width) - - private def scaledImm(shift: Int): UInt = - resize(io.queue.uop.imm << shift, addrWidth) - - private def sext32(value: UInt): UInt = - if (addrWidth == 32) value(31, 0) else Cat(Fill(addrWidth - 32, value(31)), value(31, 0)) - - private def zext32(value: UInt): UInt = - value(31, 0).pad(addrWidth) - - private def storeRegSrcR(insn: UInt, value: UInt): UInt = { - val converted = Wire(UInt(addrWidth.W)) - converted := value - switch(insn(26, 25)) { - is(0.U) { converted := sext32(value) } - is(1.U) { converted := zext32(value) } - is(2.U) { converted := (0.U(addrWidth.W) - value)(addrWidth - 1, 0) } - } - converted - } - - private def pcrStoreSize(op: UInt): UInt = - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR), - 1.U(sizeWidth.W), - Mux( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR), - 2.U(sizeWidth.W), - Mux(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR), 4.U(sizeWidth.W), 8.U(sizeWidth.W)))) - - private def zeroExec: StoreDispatchExecResult = { - val exec = Wire(new StoreDispatchExecResult(addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth)) - exec := 0.U.asTypeOf(exec) - exec - } - - val op = io.queue.uop.opcode - val src0 = resize(io.srcReadData(0), addrWidth) - val src1 = resize(io.srcReadData(1), addrWidth) - val src2 = resize(io.srcReadData(2), addrWidth) - - val supportedOpcode = WireDefault(false.B) - val addrSourceMask = WireDefault(0.U(3.W)) - val addr = WireDefault(0.U(addrWidth.W)) - val size = WireDefault(0.U(sizeWidth.W)) - - when( - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SB_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SD_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SH_PCR) || - op === opcode(FrontendOpcodeDecodeTable.OP_HL_SW_PCR)) { - supportedOpcode := true.B - addr := resize(io.queue.uop.pc + io.queue.uop.imm, addrWidth) - size := pcrStoreSize(op) - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SDI)) { - supportedOpcode := true.B - addrSourceMask := "b010".U - addr := src1 + scaledImm(3) - size := 8.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_HL_SDI_PR)) { - supportedOpcode := true.B - addrSourceMask := "b010".U - addr := src1 + scaledImm(3) - size := 8.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SWI)) { - supportedOpcode := true.B - addrSourceMask := "b010".U - addr := src1 + scaledImm(2) - size := 4.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SHI)) { - supportedOpcode := true.B - addrSourceMask := "b010".U - addr := src1 + scaledImm(1) - size := 2.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SBI)) { - supportedOpcode := true.B - addrSourceMask := "b010".U - addr := src1 + resize(io.queue.uop.imm, addrWidth) - size := 1.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SB)) { - supportedOpcode := true.B - addrSourceMask := "b110".U - addr := src1 + storeRegSrcR(io.queue.uop.insnRaw, src2) - size := 1.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SC_W)) { - supportedOpcode := true.B - addrSourceMask := "b011".U - addr := src1 - size := 4.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SD)) { - supportedOpcode := true.B - addrSourceMask := "b110".U - addr := src1 + resize(src2 << 3, addrWidth) - size := 8.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SDI)) { - supportedOpcode := true.B - addrSourceMask := "b001".U - addr := src0 + scaledImm(3) - size := 8.U - }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SWI)) { - supportedOpcode := true.B - addrSourceMask := "b001".U - addr := src0 + scaledImm(2) - size := 4.U - } - - val candidate = - io.enable && - io.queueValid && - io.queue.valid && - ((io.queue.storeType === StoreSplitStoreType.Addr) || - (io.queue.storeType === StoreSplitStoreType.All)) - val srcReadyVec = VecInit((0 until 3).map { idx => - !addrSourceMask(idx) || (io.queue.uop.src(idx).valid && io.srcReadReady(idx)) - }) - val addrSourceReady = srcReadyVec.reduce(_ && _) - - val exec = zeroExec - exec.valid := candidate && supportedOpcode && addrSourceReady - exec.addr := addr - exec.data := Mux(op === opcode(FrontendOpcodeDecodeTable.OP_SC_W), src0, 0.U) - exec.size := size - exec.peId := resize(io.queue.uop.peId, peIdWidth) - exec.stid := resize(io.queue.uop.threadId, stidWidth) - exec.tid := resize(io.queue.uop.threadId, tidWidth) - exec.stackValid := false.B - exec.scalarIex := true.B - exec.simtLane := 0.U - - io.exec := exec - io.candidate := candidate - io.supportedOpcode := supportedOpcode - io.addrSourceMask := addrSourceMask - io.addrSourceReady := addrSourceReady - io.blockedBySource := candidate && supportedOpcode && !addrSourceReady - io.blockedByUnsupported := candidate && !supportedOpcode -} diff --git a/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala b/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala deleted file mode 100644 index 342316b8..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala +++ /dev/null @@ -1,644 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.rob.ROBID - -class ReducedStoreWaitReplayChiselPathProbeIO( - val entries: Int, - val liqEntries: Int, - val addrWidth: Int, - val dataWidth: Int, - val pcWidth: Int, - val lineBytes: Int, - val sizeWidth: Int, - val lsidWidth: Int) - extends Bundle { - val flush = Input(Bool()) - - val storeInsertValid = Input(Bool()) - val storeInsert = Input(new STQStoreRequest( - entries, addrWidth, dataWidth, sizeWidth = 4, pcWidth = pcWidth, lsidWidth = lsidWidth)) - val storeInsertAccepted = Output(Bool()) - val stqOccupiedMask = Output(UInt(entries.W)) - val stqAddrReadyMask = Output(UInt(entries.W)) - val stqDataReadyMask = Output(UInt(entries.W)) - - val loadValid = Input(Bool()) - val loadAddr = Input(UInt(addrWidth.W)) - val loadSize = Input(UInt(sizeWidth.W)) - val loadBid = Input(new ROBID(entries)) - val loadLsId = Input(new ROBID(entries)) - val loadLsIdFullValid = Input(Bool()) - val loadLsIdFull = Input(UInt(lsidWidth.W)) - val baseLoadData = Input(UInt(dataWidth.W)) - val captureEnable = Input(Bool()) - - val forwardWaitBlocked = Output(Bool()) - val forwardReady = Output(Bool()) - val forwardWaitStoreValid = Output(Bool()) - val forwardWaitStoreIndex = Output(UInt(log2Ceil(entries).W)) - - val waitSlotCaptureAccepted = Output(Bool()) - val waitSlotActive = Output(Bool()) - val waitStoreClear = Output(Bool()) - val wakeValid = Output(Bool()) - val wakeIdentityMatch = Output(Bool()) - val wakeSelectedRowReady = Output(Bool()) - - val relaunchQueuePending = Output(Bool()) - val relaunchQueueOutValid = Output(Bool()) - val relaunchQueueOutFire = Output(Bool()) - - val liqCandidateConsumeReady = Output(Bool()) - val liqAllocAccepted = Output(Bool()) - val liqRefillValid = Input(Bool()) - val liqRefillLineAddr = Input(UInt(addrWidth.W)) - val liqRefillData = Input(UInt((lineBytes * 8).W)) - val liqRefillAccepted = Output(Bool()) - val liqRefillWakeMask = Output(UInt(liqEntries.W)) - val liqLaunchEnable = Input(Bool()) - val liqE2LoadDataReturned = Input(Bool()) - val liqE2ScbReturned = Input(Bool()) - val liqE2StqReturned = Input(Bool()) - val liqE2ReturnReady = Input(Bool()) - val liqReplayWakeValid = Input(Bool()) - val liqReplayWake = Input(new LoadReplayWakeupRequest( - entries, addrWidth, pcWidth, lineBytes, lsidWidth)) - val liqReplayWakeMergeMask = Output(UInt(liqEntries.W)) - val liqReplayWakeCompletedMask = Output(UInt(liqEntries.W)) - val liqLaunchValid = Output(Bool()) - val liqLaunchDriveValid = Output(Bool()) - val liqLaunchReady = Output(Bool()) - val liqLaunchAccepted = Output(Bool()) - val liqLaunchIndex = Output(UInt(log2Ceil(liqEntries).W)) - val liqLaunchSelectedLoadLsId = Output(new ROBID(entries)) - val liqE4UpdateValid = Output(Bool()) - val liqE4UpdateIndex = Output(UInt(log2Ceil(liqEntries).W)) - val liqE4WakeupValid = Output(Bool()) - val liqLhqRecordValid = Output(Bool()) - val liqLhqRecordLoadLsId = Output(new ROBID(entries)) - val liqLhqRecordData = Output(UInt((lineBytes * 8).W)) - val resolveQueuePushAccepted = Output(Bool()) - val resolveQueueRetireValid = Input(Bool()) - val resolveQueueRetireBid = Input(new ROBID(entries)) - val resolveQueueRetireLsId = Input(new ROBID(entries)) - val resolveQueueRetireMask = Output(UInt(liqEntries.W)) - val resolveQueueRetireCount = Output(UInt(log2Ceil(liqEntries + 1).W)) - val resolveQueueValidMask = Output(UInt(liqEntries.W)) - val resolveQueueCount = Output(UInt(log2Ceil(liqEntries + 1).W)) - val resolveQueueFirstLoadLsId = Output(new ROBID(entries)) - val mdbStore = Input(new MDBConflictStoreProbe( - entries, addrWidth = addrWidth, pcWidth = pcWidth, sizeWidth = sizeWidth, - lsidWidth = lsidWidth)) - val mdbLookupValid = Input(Bool()) - val mdbLookupUseLiveLoad = Input(Bool()) - val mdbDeleteValid = Input(Bool()) - val mdbDeleteWaitStorePc = Input(UInt(pcWidth.W)) - val mdbResolveCandidateMask = Output(UInt(liqEntries.W)) - val mdbConflictValid = Output(Bool()) - val mdbConflictFromResolveQueue = Output(Bool()) - val mdbConflictResolveIndex = Output(UInt(log2Ceil(liqEntries.max(2)).W)) - val mdbInnerFlush = Output(Bool()) - val mdbNukeFlush = Output(Bool()) - val mdbConflictLoadLsId = Output(new ROBID(entries)) - val mdbConflictLoadPc = Output(UInt(pcWidth.W)) - val mdbFanoutRecordReady = Output(Bool()) - val mdbFanoutRecordAccepted = Output(Bool()) - val mdbFanoutRecordProcessed = Output(Bool()) - val mdbFanoutBmdbReportValid = Output(Bool()) - val mdbFanoutBmdbLoadBid = Output(new ROBID(entries)) - val mdbFanoutBmdbStoreBid = Output(new ROBID(entries)) - val mdbFanoutBmdbStoreStid = Output(UInt(8.W)) - val mdbFanoutSsitValidMask = Output(UInt(liqEntries.W)) - val mdbFanoutLookupReady = Output(Bool()) - val mdbFanoutLookupAccepted = Output(Bool()) - val mdbFanoutLookupProcessed = Output(Bool()) - val mdbFanoutDeleteReady = Output(Bool()) - val mdbFanoutDeleteAccepted = Output(Bool()) - val mdbFanoutDeleteProcessed = Output(Bool()) - val mdbFanoutDeleteMatched = Output(Bool()) - val mdbFanoutDeleteReleased = Output(Bool()) - val mdbFanoutDeleteDroppedBelowStall = Output(Bool()) - val mdbFanoutLuOutDequeued = Output(Bool()) - val mdbFanoutLuOutHit = Output(Bool()) - val mdbFanoutSuOutDequeued = Output(Bool()) - val mdbFanoutSuOutHit = Output(Bool()) - val mdbFanoutSuMatchedStore = Output(Bool()) - val mdbFanoutSuStorePending = Output(Bool()) - val mdbFanoutSuWakeupValid = Output(Bool()) - val mdbFanoutSuWakeupStoreIndex = Output(UInt(log2Ceil(entries).W)) - val mdbFanoutSuWakeupBid = Output(new ROBID(entries)) - val mdbLookupWaitPlanLookupHit = Output(Bool()) - val mdbLookupWaitPlanCandidateMask = Output(UInt(liqEntries.W)) - val mdbLookupWaitPlanTargetIndex = Output(UInt(log2Ceil(liqEntries).W)) - val mdbLookupWaitPlanWaitIntentValid = Output(Bool()) - val mdbLookupWaitPlanRequestValid = Output(Bool()) - val mdbLookupWaitPlanBlockedByNoTarget = Output(Bool()) - val mdbLookupWaitPlanBlockedByMissingStoreIndex = Output(Bool()) - val mdbLookupWaitPlanBlockedByMissingStoreLsId = Output(Bool()) - val rowMutationBridgeValid = Output(Bool()) - val rowMutationTargetEvidenceValid = Output(Bool()) - val rowMutationWriteEnable = Output(Bool()) - val rowMutationApplyValid = Output(Bool()) - val rowMutationBlockedByControl = Output(Bool()) - val rowMutationControlBlockedByScbNotReturned = Output(Bool()) - val rowMutationControlBlockedByE4UpdateConflict = Output(Bool()) - val liqClearResolvedPending = Output(Bool()) - val liqClearResolvedAccepted = Output(Bool()) - val liqResidentCount = Output(UInt(log2Ceil(liqEntries + 1).W)) - val liqOccupiedMask = Output(UInt(liqEntries.W)) - val liqWaitMask = Output(UInt(liqEntries.W)) - val liqWaitStoreMask = Output(UInt(liqEntries.W)) - val liqRepickMask = Output(UInt(liqEntries.W)) - val liqResolvedMask = Output(UInt(liqEntries.W)) - val liqSourcesReturnedMask = Output(UInt(liqEntries.W)) - val liqScbReturnedMask = Output(UInt(liqEntries.W)) - val liqStqReturnedMask = Output(UInt(liqEntries.W)) - val liqFirstYoungestStoreLsId = Output(new ROBID(entries)) -} - -class ReducedStoreWaitReplayChiselPathProbe( - val entries: Int = 8, - val liqEntries: Int = 4, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val pcWidth: Int = 64, - val lineBytes: Int = 64, - val sizeWidth: Int = 7, - val lsidWidth: Int = 40) - extends Module { - require(entries > 1 && (entries & (entries - 1)) == 0) - require(liqEntries > 1 && (liqEntries & (liqEntries - 1)) == 0) - - val io = IO(new ReducedStoreWaitReplayChiselPathProbeIO( - entries, - liqEntries, - addrWidth, - dataWidth, - pcWidth, - lineBytes, - sizeWidth, - lsidWidth - )) - - val stq = Module(new STQEntryBank( - entries, addrWidth, dataWidth, sizeWidth = 4, lsidWidth = lsidWidth)) - STQEntryBank.disableCanonicalPorts(stq.io) - stq.io.flush := 0.U.asTypeOf(stq.io.flush) - stq.io.flush.req.valid := io.flush - stq.io.insertValid := io.storeInsertValid && !io.flush - stq.io.insert := io.storeInsert - stq.io.markCommitValid := false.B - stq.io.markCommitIndex := 0.U - stq.io.commitFreeValid := false.B - stq.io.commitFreeIndex := 0.U - stq.io.commitFreeMaskValid := false.B - stq.io.commitFreeMask := 0.U - - val forward = Module(new ReducedStoreResidentForward( - entries, addrWidth, dataWidth, sizeWidth = 4, pcWidth = pcWidth, - lineBytes = lineBytes, lsidWidth = lsidWidth)) - forward.io.enable := !io.flush - forward.io.loadValid := io.loadValid - forward.io.loadAddr := io.loadAddr - forward.io.loadSize := io.loadSize - forward.io.loadBid := io.loadBid - forward.io.loadLsId := io.loadLsId - forward.io.loadLsIdFullValid := io.loadLsIdFullValid - forward.io.loadLsIdFull := io.loadLsIdFull - forward.io.baseLoadData := io.baseLoadData - forward.io.rows := stq.io.rows - - val waitSlot = Module(new ReducedLoadWaitReplaySlot( - entries, entries, addrWidth, pcWidth, lineBytes, sizeWidth, lsidWidth = lsidWidth)) - waitSlot.io.flush := io.flush - waitSlot.io.captureValid := io.captureEnable && forward.io.waitBlocked - waitSlot.io.capturePc := 0.U - waitSlot.io.captureAddr := io.loadAddr - waitSlot.io.captureSize := io.loadSize - waitSlot.io.captureReturnSignExtend := false.B - waitSlot.io.captureDst := LoadReplayDestination.none() - waitSlot.io.captureSourceTraceValid := false.B - waitSlot.io.captureSource0 := 0.U.asTypeOf(waitSlot.io.captureSource0) - waitSlot.io.captureSource1 := 0.U.asTypeOf(waitSlot.io.captureSource1) - waitSlot.io.captureBid := io.loadBid - waitSlot.io.captureGid := ROBID.zero(entries) - waitSlot.io.captureRid := ROBID.zero(entries) - waitSlot.io.captureLsId := io.loadLsId - waitSlot.io.captureLsIdFullValid := io.loadLsIdFullValid - waitSlot.io.captureLsIdFull := io.loadLsIdFull - waitSlot.io.captureYoungestStoreId := forward.io.waitStore.storeId - waitSlot.io.captureYoungestStoreLsId := forward.io.waitStore.storeLsId - waitSlot.io.captureYoungestStoreLsIdFullValid := forward.io.waitStore.storeLsIdFullValid - waitSlot.io.captureYoungestStoreLsIdFull := forward.io.waitStore.storeLsIdFull - waitSlot.io.captureWaitStore := forward.io.waitStore - - val wake = Module(new ResidentStoreReplayWakeup( - entries, addrWidth, dataWidth, sizeWidth = 4, pcWidth = pcWidth, - lineBytes = lineBytes, lsidWidth = lsidWidth)) - wake.io.enable := !io.flush - wake.io.waitStore := waitSlot.io.storedWaitStore - wake.io.rows := stq.io.rows - waitSlot.io.replayWakeValid := wake.io.wakeValid - waitSlot.io.replayWake := wake.io.wake - - val capturedLoadLsIdFullValid = RegInit(false.B) - val capturedLoadLsIdFull = RegInit(0.U(lsidWidth.W)) - when(io.flush) { - capturedLoadLsIdFullValid := false.B - capturedLoadLsIdFull := 0.U - }.elsewhen(waitSlot.io.captureAccepted) { - capturedLoadLsIdFullValid := io.loadLsIdFullValid - capturedLoadLsIdFull := io.loadLsIdFull - } - - val relaunchQueue = Module(new ReducedLoadReplayRelaunchQueue(entries, depth = 2, addrWidth, pcWidth, sizeWidth)) - relaunchQueue.io.flush := io.flush - relaunchQueue.io.enqueueValid := waitSlot.io.relaunch.valid - relaunchQueue.io.enqueue := waitSlot.io.relaunch - - val liq = Module(new ReducedLoadReplayLiqAllocPath( - liqEntries, entries, entries, addrWidth, pcWidth, lineBytes, sizeWidth, - lsidWidth = lsidWidth)) - val liqLoadLsIdFullValid = RegInit(VecInit(Seq.fill(liqEntries)(false.B))) - val liqLoadLsIdFull = RegInit(VecInit(Seq.fill(liqEntries)(0.U(lsidWidth.W)))) - liq.io.preciseFlush := 0.U.asTypeOf(liq.io.preciseFlush) - val resolveQueue = Module(new LoadResolveQueue( - queueEntries = liqEntries, liqEntries = liqEntries, idEntries = entries, - addrWidth = addrWidth, pcWidth = pcWidth, lineBytes = lineBytes, - sizeWidth = sizeWidth, lsidWidth = lsidWidth)) - val clearResolvedPending = RegInit(false.B) - val clearResolvedIndex = RegInit(0.U(log2Ceil(liqEntries).W)) - val markResolvedPending = RegInit(false.B) - val markResolvedIndex = RegInit(0.U(log2Ceil(liqEntries).W)) - - liq.io.flush := io.flush - liq.io.candidateValid := relaunchQueue.io.outValid - liq.io.candidate := relaunchQueue.io.out - liq.io.allocExternalReady := true.B - liq.io.rowMutationAllowWaitTarget := false.B - liq.io.rowMutationRequireScbReturned := true.B - liq.io.launchEnable := io.liqLaunchEnable - liq.io.pickValid := false.B - liq.io.pickIndex := 0.U - liq.io.scbReturnValid := false.B - liq.io.scbReturnIndex := 0.U - liq.io.markResolvedValid := markResolvedPending - liq.io.markResolvedIndex := markResolvedIndex - liq.io.e2Stores := 0.U.asTypeOf(liq.io.e2Stores) - liq.io.e2BaseData := 0.U - liq.io.e2BaseValidMask := 0.U - liq.io.e2LoadDataReturned := io.liqE2LoadDataReturned - liq.io.e2ScbReturned := io.liqE2ScbReturned - liq.io.e2StqReturned := io.liqE2StqReturned - liq.io.e2ReturnReady := io.liqE2ReturnReady - liq.io.replayWakeValid := io.liqReplayWakeValid - liq.io.replayWake := io.liqReplayWake - liq.io.refillValid := io.liqRefillValid - liq.io.refill.isRead := true.B - liq.io.refill.lineAddr := io.liqRefillLineAddr - liq.io.refill.data := io.liqRefillData - liq.io.refill.l2Miss := false.B - liq.io.clearResolvedValid := clearResolvedPending - liq.io.clearResolvedIndex := clearResolvedIndex - relaunchQueue.io.outReady := liq.io.candidateConsumeReady - - resolveQueue.io.flush := io.flush - resolveQueue.io.preciseFlush := 0.U.asTypeOf(resolveQueue.io.preciseFlush) - resolveQueue.io.pushValid := liq.io.lhqRecordValid - resolveQueue.io.pushPeId := 0.U - resolveQueue.io.pushStid := 0.U - resolveQueue.io.pushTid := 0.U - val resolvePushRecord = Wire(chiselTypeOf(liq.io.lhqRecord)) - resolvePushRecord := liq.io.lhqRecord - resolvePushRecord.loadLsIdFullValid := liqLoadLsIdFullValid(liq.io.lhqRecord.loadId.value) - resolvePushRecord.loadLsIdFull := liqLoadLsIdFull(liq.io.lhqRecord.loadId.value) - resolveQueue.io.pushRecord := resolvePushRecord - resolveQueue.io.retireValid := io.resolveQueueRetireValid - resolveQueue.io.retireBid := io.resolveQueueRetireBid - resolveQueue.io.retireLsId := io.resolveQueueRetireLsId - resolveQueue.io.retireLsIdFullValid := false.B - resolveQueue.io.retireLsIdFull := 0.U - - val mdbDetect = Module(new MDBConflictDetect( - entries = entries, - loadEntries = liqEntries, - resolveEntries = liqEntries, - addrWidth = addrWidth, - pcWidth = pcWidth, - sizeWidth = sizeWidth, - lsidWidth = lsidWidth - )) - mdbDetect.io.store := io.mdbStore - mdbDetect.io.activeLoads := 0.U.asTypeOf(mdbDetect.io.activeLoads) - mdbDetect.io.resolvedQueue := resolveQueue.io.conflictRows - - val mdbFanout = Module(new MDBQueueFanout( - entries = entries, - ssitEntries = liqEntries, - commandQueueEntries = liqEntries, - outputQueueEntries = liqEntries, - storeEntries = entries, - addrWidth = addrWidth, - pcWidth = pcWidth, - sizeWidth = sizeWidth, - lsidWidth = lsidWidth - )) - mdbFanout.io.flush := io.flush - val mdbZeroBus = Wire(new MDBQueueBus( - entries, addrWidth = addrWidth, pcWidth = pcWidth, sizeWidth = sizeWidth, - lsidWidth = lsidWidth)) - mdbZeroBus := 0.U.asTypeOf(mdbZeroBus) - mdbZeroBus.ldInfo.bid := ROBID.disabled(entries) - mdbZeroBus.ldInfo.lsId := ROBID.disabled(entries) - mdbZeroBus.stInfo.bid := ROBID.disabled(entries) - mdbZeroBus.stInfo.lsId := ROBID.disabled(entries) - - val mdbRecordBus = Wire(chiselTypeOf(mdbZeroBus)) - mdbRecordBus := mdbZeroBus - mdbRecordBus.valid := mdbDetect.io.conflictValid - mdbRecordBus.ldInfo.valid := mdbDetect.io.conflictValid - mdbRecordBus.ldInfo.pc := mdbDetect.io.record.load.pc - mdbRecordBus.ldInfo.bid := mdbDetect.io.record.load.bid - mdbRecordBus.ldInfo.lsId := mdbDetect.io.record.load.lsId - mdbRecordBus.ldInfo.lsIdFullValid := mdbDetect.io.record.load.lsIdFullValid - mdbRecordBus.ldInfo.lsIdFull := mdbDetect.io.record.load.lsIdFull - mdbRecordBus.ldInfo.stid := mdbDetect.io.record.load.stid - mdbRecordBus.ldInfo.addr := mdbDetect.io.record.load.addr - mdbRecordBus.ldInfo.size := mdbDetect.io.record.load.size - mdbRecordBus.ldInfo.isTile := mdbDetect.io.record.load.isTile - mdbRecordBus.stInfo.valid := mdbDetect.io.conflictValid - mdbRecordBus.stInfo.pc := mdbDetect.io.record.store.pc - mdbRecordBus.stInfo.bid := mdbDetect.io.record.store.bid - mdbRecordBus.stInfo.lsId := mdbDetect.io.record.store.lsId - mdbRecordBus.stInfo.lsIdFullValid := mdbDetect.io.record.store.lsIdFullValid - mdbRecordBus.stInfo.lsIdFull := mdbDetect.io.record.store.lsIdFull - mdbRecordBus.stInfo.stid := mdbDetect.io.record.store.stid - mdbRecordBus.stInfo.addr := mdbDetect.io.record.store.addr - mdbRecordBus.stInfo.size := mdbDetect.io.record.store.size - mdbRecordBus.stInfo.isTile := mdbDetect.io.record.store.isTile - mdbRecordBus.conf := 1.U - - val mdbLookupBus = Wire(chiselTypeOf(mdbZeroBus)) - mdbLookupBus := mdbZeroBus - mdbLookupBus.valid := io.mdbLookupValid - mdbLookupBus.ldInfo.valid := io.mdbLookupValid - mdbLookupBus.ldInfo.pc := Mux(io.mdbLookupUseLiveLoad, 0.U, resolveQueue.io.entries(0).record.pc) - mdbLookupBus.ldInfo.bid := Mux(io.mdbLookupUseLiveLoad, io.loadBid, resolveQueue.io.entries(0).record.bid) - mdbLookupBus.ldInfo.lsId := Mux(io.mdbLookupUseLiveLoad, io.loadLsId, resolveQueue.io.entries(0).record.loadLsId) - mdbLookupBus.ldInfo.lsIdFullValid := Mux( - io.mdbLookupUseLiveLoad, - io.loadLsIdFullValid, - resolveQueue.io.entries(0).record.loadLsIdFullValid) - mdbLookupBus.ldInfo.lsIdFull := Mux( - io.mdbLookupUseLiveLoad, - io.loadLsIdFull, - resolveQueue.io.entries(0).record.loadLsIdFull) - mdbLookupBus.ldInfo.stid := resolveQueue.io.entries(0).stid - mdbLookupBus.ldInfo.addr := Mux(io.mdbLookupUseLiveLoad, io.loadAddr, resolveQueue.io.entries(0).record.addr) - mdbLookupBus.ldInfo.size := Mux(io.mdbLookupUseLiveLoad, io.loadSize, resolveQueue.io.entries(0).record.size) - mdbLookupBus.ldInfo.isTile := false.B - mdbLookupBus.conf := 1.U - - val mdbDeleteBus = Wire(chiselTypeOf(mdbZeroBus)) - mdbDeleteBus := mdbZeroBus - mdbDeleteBus.valid := io.mdbDeleteValid - mdbDeleteBus.ldInfo.valid := io.mdbDeleteValid - mdbDeleteBus.ldInfo.pc := resolveQueue.io.entries(0).record.pc - mdbDeleteBus.ldInfo.bid := resolveQueue.io.entries(0).record.bid - mdbDeleteBus.ldInfo.lsId := resolveQueue.io.entries(0).record.loadLsId - mdbDeleteBus.ldInfo.lsIdFullValid := resolveQueue.io.entries(0).record.loadLsIdFullValid - mdbDeleteBus.ldInfo.lsIdFull := resolveQueue.io.entries(0).record.loadLsIdFull - mdbDeleteBus.ldInfo.stid := resolveQueue.io.entries(0).stid - mdbDeleteBus.ldInfo.waitStorePc := io.mdbDeleteWaitStorePc - mdbDeleteBus.conf := 1.U - - val mdbFanoutStoreRows = Wire(Vec( - entries, - new MDBStoreWakeupEntry( - entries, entries, addrWidth = addrWidth, pcWidth = pcWidth, - sizeWidth = sizeWidth, lsidWidth = lsidWidth) - )) - for (idx <- 0 until entries) { - val stqRow = stq.io.rows(idx) - val wakeRow = Wire(chiselTypeOf(mdbFanoutStoreRows(idx))) - wakeRow := 0.U.asTypeOf(wakeRow) - wakeRow.bid := ROBID.disabled(entries) - wakeRow.lsId := ROBID.disabled(entries) - wakeRow.valid := stqRow.valid - wakeRow.storeIndex := idx.U - wakeRow.pc := stqRow.pc - wakeRow.bid := stqRow.bid - wakeRow.lsId := stqRow.lsId - wakeRow.lsIdFullValid := stqRow.valid - wakeRow.lsIdFull := stqRow.lsIdFull - wakeRow.stid := stqRow.stid - wakeRow.addr := stqRow.addr - wakeRow.size := stqRow.size.pad(sizeWidth) - wakeRow.addrReady := stqRow.addrReady - wakeRow.dataReady := stqRow.dataReady - wakeRow.isTile := !stqRow.scalarIex - mdbFanoutStoreRows(idx) := wakeRow - } - - mdbFanout.io.lookupIn := mdbLookupBus - mdbFanout.io.lookupInValid := io.mdbLookupValid - mdbFanout.io.deleteIn := mdbDeleteBus - mdbFanout.io.deleteInValid := io.mdbDeleteValid - mdbFanout.io.recordIn := mdbRecordBus - mdbFanout.io.recordInValid := mdbDetect.io.conflictValid - mdbFanout.io.luDequeueReady := true.B - mdbFanout.io.suCheckReady := true.B - mdbFanout.io.storeRows := mdbFanoutStoreRows - - val mdbLookupWaitPlan = Module(new LoadReplayMdbLookupWaitPlan( - liqEntries = liqEntries, - idEntries = entries, - storeEntries = entries, - addrWidth = addrWidth, - pcWidth = pcWidth, - lineBytes = lineBytes, - sizeWidth = sizeWidth, - lsidWidth = lsidWidth - )) - mdbLookupWaitPlan.io.enable := true.B - mdbLookupWaitPlan.io.flush := io.flush - mdbLookupWaitPlan.io.luOutValid := mdbFanout.io.luOutValid - mdbLookupWaitPlan.io.luOut := mdbFanout.io.luOut - val mdbPlannerRows = Wire(chiselTypeOf(liq.io.rows)) - mdbPlannerRows := liq.io.rows - for (idx <- 0 until liqEntries) { - mdbPlannerRows(idx).loadLsIdFullValid := liqLoadLsIdFullValid(idx) - mdbPlannerRows(idx).loadLsIdFull := liqLoadLsIdFull(idx) - } - mdbLookupWaitPlan.io.rows := mdbPlannerRows - mdbLookupWaitPlan.io.storeIndexValid := mdbFanout.io.suMatchedStore - mdbLookupWaitPlan.io.storeIndex := mdbFanout.io.suMatchedStoreIndex - mdbLookupWaitPlan.io.storeLsIdValid := mdbFanout.io.suMatchedStore - mdbLookupWaitPlan.io.storeLsId := mdbFanout.io.suMatchedStoreLsId - mdbLookupWaitPlan.io.storeLsIdFullValid := mdbFanout.io.suMatchedStoreLsIdFullValid - mdbLookupWaitPlan.io.storeLsIdFull := mdbFanout.io.suMatchedStoreLsIdFull - - liq.io.rowMutationRequestValid := mdbLookupWaitPlan.io.requestValid - liq.io.rowMutationRequestTargetMask := mdbLookupWaitPlan.io.requestTargetMask - liq.io.rowMutationRequestTargetIndex := mdbLookupWaitPlan.io.requestTargetIndex - liq.io.rowMutationSetWaitStatus := mdbLookupWaitPlan.io.setWaitStatus - liq.io.rowMutationKeepRepickStatus := mdbLookupWaitPlan.io.keepRepickStatus - liq.io.rowMutationClearReturnState := mdbLookupWaitPlan.io.clearReturnState - liq.io.rowMutationLineWrite := mdbLookupWaitPlan.io.lineWrite - liq.io.rowMutationWaitStoreWrite := mdbLookupWaitPlan.io.waitStoreWrite - liq.io.rowMutationNextWaitStore := mdbLookupWaitPlan.io.nextWaitStore - liq.io.rowMutationNextWaitStoreInfo := mdbLookupWaitPlan.io.nextWaitStoreInfo - liq.io.rowMutationNextLineData := mdbLookupWaitPlan.io.nextLineData - liq.io.rowMutationNextValidMask := mdbLookupWaitPlan.io.nextValidMask - liq.io.rowMutationNextDataComplete := mdbLookupWaitPlan.io.nextDataComplete - liq.io.rowMutationNextScbReturned := mdbLookupWaitPlan.io.nextScbReturned - liq.io.rowMutationNextStqReturned := mdbLookupWaitPlan.io.nextStqReturned - liq.io.rowMutationNextStoreSourceReturned := mdbLookupWaitPlan.io.nextStoreSourceReturned - - when(io.flush) { - clearResolvedPending := false.B - clearResolvedIndex := 0.U - markResolvedPending := false.B - markResolvedIndex := 0.U - for (idx <- 0 until liqEntries) { - liqLoadLsIdFullValid(idx) := false.B - liqLoadLsIdFull(idx) := 0.U - } - }.otherwise { - when(liq.io.allocAccepted) { - liqLoadLsIdFullValid(liq.io.allocIndex) := capturedLoadLsIdFullValid - liqLoadLsIdFull(liq.io.allocIndex) := capturedLoadLsIdFull - } - when(clearResolvedPending && liq.io.clearResolvedAccepted) { - clearResolvedPending := false.B - liqLoadLsIdFullValid(clearResolvedIndex) := false.B - liqLoadLsIdFull(clearResolvedIndex) := 0.U - } - when(markResolvedPending && liq.io.markResolvedAccepted) { - markResolvedPending := false.B - clearResolvedPending := true.B - clearResolvedIndex := markResolvedIndex - } - when(resolveQueue.io.pushAccepted) { - markResolvedPending := true.B - markResolvedIndex := liq.io.lhqRecord.loadId.value - } - } - - io.storeInsertAccepted := stq.io.insertAccepted - io.stqOccupiedMask := stq.io.occupiedMask - io.stqAddrReadyMask := stq.io.addrReadyMask - io.stqDataReadyMask := stq.io.dataReadyMask - io.forwardWaitBlocked := forward.io.waitBlocked - io.forwardReady := forward.io.readyForward - io.forwardWaitStoreValid := forward.io.waitStore.valid - io.forwardWaitStoreIndex := forward.io.waitStore.storeIndex - io.waitSlotCaptureAccepted := waitSlot.io.captureAccepted - io.waitSlotActive := waitSlot.io.active - io.waitStoreClear := waitSlot.io.waitStoreClear - io.wakeValid := wake.io.wakeValid - io.wakeIdentityMatch := wake.io.identityMatch - io.wakeSelectedRowReady := wake.io.selectedRowReady - io.relaunchQueuePending := relaunchQueue.io.pending - io.relaunchQueueOutValid := relaunchQueue.io.outValid - io.relaunchQueueOutFire := relaunchQueue.io.outFire - io.liqCandidateConsumeReady := liq.io.candidateConsumeReady - io.liqAllocAccepted := liq.io.allocAccepted - io.liqRefillAccepted := liq.io.refillAccepted - io.liqRefillWakeMask := liq.io.refillWakeMask - io.liqReplayWakeMergeMask := liq.io.replayWakeMergeMask - io.liqReplayWakeCompletedMask := liq.io.replayWakeCompletedMask - io.liqLaunchValid := liq.io.launchValid - io.liqLaunchDriveValid := liq.io.launchDriveValid - io.liqLaunchReady := liq.io.launchReady - io.liqLaunchAccepted := liq.io.launchAccepted - io.liqLaunchIndex := liq.io.launchIndex - io.liqLaunchSelectedLoadLsId := liq.io.launchSelectedLoadLsId - io.liqE4UpdateValid := liq.io.e4UpdateValid - io.liqE4UpdateIndex := liq.io.e4UpdateIndex - io.liqE4WakeupValid := liq.io.e4WakeupValid - io.liqLhqRecordValid := liq.io.lhqRecordValid - io.liqLhqRecordLoadLsId := liq.io.lhqRecord.loadLsId - io.liqLhqRecordData := liq.io.lhqRecord.data - io.resolveQueuePushAccepted := resolveQueue.io.pushAccepted - io.resolveQueueRetireMask := resolveQueue.io.retireMask - io.resolveQueueRetireCount := resolveQueue.io.retireCount - io.resolveQueueValidMask := resolveQueue.io.validMask - io.resolveQueueCount := resolveQueue.io.count - io.resolveQueueFirstLoadLsId := resolveQueue.io.entries(0).record.loadLsId - io.mdbResolveCandidateMask := mdbDetect.io.resolveCandidateMask - io.mdbConflictValid := mdbDetect.io.conflictValid - io.mdbConflictFromResolveQueue := mdbDetect.io.conflictFromResolveQueue - io.mdbConflictResolveIndex := mdbDetect.io.conflictResolveIndex - io.mdbInnerFlush := mdbDetect.io.innerFlush - io.mdbNukeFlush := mdbDetect.io.nukeFlush - io.mdbConflictLoadLsId := mdbDetect.io.record.load.lsId - io.mdbConflictLoadPc := mdbDetect.io.record.load.pc - io.mdbFanoutRecordReady := mdbFanout.io.recordInReady - io.mdbFanoutRecordAccepted := mdbFanout.io.recordInAccepted - io.mdbFanoutRecordProcessed := mdbFanout.io.recordProcessed - io.mdbFanoutBmdbReportValid := mdbFanout.io.bmdbReportValid - io.mdbFanoutBmdbLoadBid := mdbFanout.io.bmdbLoadBid - io.mdbFanoutBmdbStoreBid := mdbFanout.io.bmdbStoreBid - io.mdbFanoutBmdbStoreStid := mdbFanout.io.bmdbStoreStid - io.mdbFanoutSsitValidMask := mdbFanout.io.ssitValidMask - io.mdbFanoutLookupReady := mdbFanout.io.lookupInReady - io.mdbFanoutLookupAccepted := mdbFanout.io.lookupInAccepted - io.mdbFanoutLookupProcessed := mdbFanout.io.lookupProcessed - io.mdbFanoutDeleteReady := mdbFanout.io.deleteInReady - io.mdbFanoutDeleteAccepted := mdbFanout.io.deleteInAccepted - io.mdbFanoutDeleteProcessed := mdbFanout.io.deleteProcessed - io.mdbFanoutDeleteMatched := mdbFanout.io.deleteMatched - io.mdbFanoutDeleteReleased := mdbFanout.io.deleteReleased - io.mdbFanoutDeleteDroppedBelowStall := mdbFanout.io.deleteDroppedBelowStall - io.mdbFanoutLuOutDequeued := mdbFanout.io.luOutDequeued - io.mdbFanoutLuOutHit := mdbFanout.io.luOut.hit - io.mdbFanoutSuOutDequeued := mdbFanout.io.suOutDequeued - io.mdbFanoutSuOutHit := mdbFanout.io.suOut.hit - io.mdbFanoutSuMatchedStore := mdbFanout.io.suMatchedStore - io.mdbFanoutSuStorePending := mdbFanout.io.suStorePending - io.mdbFanoutSuWakeupValid := mdbFanout.io.suWakeup.valid - io.mdbFanoutSuWakeupStoreIndex := mdbFanout.io.suWakeup.storeIndex - io.mdbFanoutSuWakeupBid := mdbFanout.io.suWakeup.bid - io.mdbLookupWaitPlanLookupHit := mdbLookupWaitPlan.io.lookupHit - io.mdbLookupWaitPlanCandidateMask := mdbLookupWaitPlan.io.candidateMask - io.mdbLookupWaitPlanTargetIndex := mdbLookupWaitPlan.io.targetIndex - io.mdbLookupWaitPlanWaitIntentValid := mdbLookupWaitPlan.io.waitIntentValid - io.mdbLookupWaitPlanRequestValid := mdbLookupWaitPlan.io.requestValid - io.mdbLookupWaitPlanBlockedByNoTarget := mdbLookupWaitPlan.io.blockedByNoTarget - io.mdbLookupWaitPlanBlockedByMissingStoreIndex := mdbLookupWaitPlan.io.blockedByMissingStoreIndex - io.mdbLookupWaitPlanBlockedByMissingStoreLsId := mdbLookupWaitPlan.io.blockedByMissingStoreLsId - io.rowMutationBridgeValid := liq.io.rowMutationBridgeValid - io.rowMutationTargetEvidenceValid := liq.io.rowMutationTargetEvidenceValid - io.rowMutationWriteEnable := liq.io.rowMutationWriteEnable - io.rowMutationApplyValid := liq.io.rowMutationApplyValid - io.rowMutationBlockedByControl := liq.io.rowMutationBlockedByControl - io.rowMutationControlBlockedByScbNotReturned := liq.io.rowMutationControlBlockedByScbNotReturned - io.rowMutationControlBlockedByE4UpdateConflict := liq.io.rowMutationControlBlockedByE4UpdateConflict - io.liqClearResolvedPending := clearResolvedPending - io.liqClearResolvedAccepted := liq.io.clearResolvedAccepted - io.liqResidentCount := liq.io.residentCount - io.liqOccupiedMask := liq.io.occupiedMask - io.liqWaitMask := liq.io.waitMask - io.liqWaitStoreMask := liq.io.waitStoreMask - io.liqRepickMask := liq.io.repickMask - io.liqResolvedMask := liq.io.resolvedMask - io.liqSourcesReturnedMask := - VecInit((0 until liqEntries).map(idx => liq.io.rows(idx).valid && liq.io.rows(idx).sourcesReturned)).asUInt - io.liqScbReturnedMask := - VecInit((0 until liqEntries).map(idx => liq.io.rows(idx).valid && liq.io.rows(idx).scbReturned)).asUInt - io.liqStqReturnedMask := - VecInit((0 until liqEntries).map(idx => liq.io.rows(idx).valid && liq.io.rows(idx).stqReturned)).asUInt - io.liqFirstYoungestStoreLsId := liq.io.rows(0).youngestStoreLsId -} - -object EmitReducedStoreWaitReplayChiselPathProbe extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new ReducedStoreWaitReplayChiselPathProbe(entries = 8, liqEntries = 4), - args = Array("--target-dir", "../generated/chisel-verilog/reduced-store-wait-replay-chisel-path"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/lsu/SCBCommitBridge.scala b/chisel/src/main/scala/linxcore/lsu/SCBCommitBridge.scala deleted file mode 100644 index e15519b3..00000000 --- a/chisel/src/main/scala/linxcore/lsu/SCBCommitBridge.scala +++ /dev/null @@ -1,99 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.{log2Ceil, PopCount} - -class SCBCommitBridgeIO( - val stqEntries: Int, - val scbEntries: Int, - val requestCount: Int, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val sizeWidth: Int = 4, - val lineBytes: Int = 64) - extends Bundle { - private val scbCountWidth = log2Ceil(scbEntries + 1) - private val freeCountWidth = log2Ceil(requestCount + 1) - - val reqs = Input(Vec(requestCount, new STQCommitDrainRequest(stqEntries, addrWidth, dataWidth, sizeWidth))) - - val modelBatchReady = Output(Bool()) - val modelFull = Output(Bool()) - val acceptedMask = Output(UInt(requestCount.W)) - val stalledMask = Output(UInt(requestCount.W)) - val structuralBlockedMask = Output(UInt(requestCount.W)) - - val commitFreeMaskValid = Output(Bool()) - val commitFreeMask = Output(UInt(stqEntries.W)) - val commitFreeCount = Output(UInt(freeCountWidth.W)) - - val wakeups = Output(Vec(requestCount, new SCBCommitWakeup(addrWidth, lineBytes))) - val entries = Output(Vec(scbEntries, new SCBLineEntry(addrWidth, lineBytes))) - val validMask = Output(UInt(scbEntries.W)) - val fullLineMask = Output(UInt(scbEntries.W)) - val entryCount = Output(UInt(scbCountWidth.W)) - val freeCount = Output(UInt(scbCountWidth.W)) - val ingressFull = Output(Bool()) -} - -class SCBCommitBridge( - val stqEntries: Int = 16, - val scbEntries: Int = 16, - val requestCount: Int = 4, - val addrWidth: Int = 64, - val dataWidth: Int = 64, - val sizeWidth: Int = 4, - val lineBytes: Int = 64) - extends Module { - require(stqEntries > 1, "STQ entries must be greater than one") - require(scbEntries > 0, "SCB entries must be nonzero") - require(requestCount > 0, "SCB bridge request count must be nonzero") - require(requestCount <= scbEntries, "SCB bridge model batch width cannot exceed SCB depth") - require(addrWidth >= 7, "SCB bridge needs at least 7 address bits for 64-byte lines") - require(dataWidth == 64, "SCB bridge currently models scalar 64-bit store fragments") - require(sizeWidth >= 4, "SCB bridge scalar store sizes require at least 4 size bits") - require(lineBytes == 64, "SCB bridge currently models 64-byte scalar cachelines") - - private val scbCountWidth = log2Ceil(scbEntries + 1) - private val freeCountWidth = log2Ceil(requestCount + 1) - - val io = IO(new SCBCommitBridgeIO(stqEntries, scbEntries, requestCount, addrWidth, dataWidth, sizeWidth, lineBytes)) - - val ingress = Module(new SCBCommitIngress(stqEntries, scbEntries, requestCount, addrWidth, dataWidth, sizeWidth, lineBytes)) - - val validReqMask = VecInit(io.reqs.map(_.valid)).asUInt - val modelBatchReady = ingress.io.freeCount >= requestCount.U(scbCountWidth.W) - - for (lane <- 0 until requestCount) { - ingress.io.reqs(lane) := io.reqs(lane) - ingress.io.reqs(lane).valid := io.reqs(lane).valid && modelBatchReady - } - - val commitFreeVec = Wire(Vec(stqEntries, Bool())) - for (idx <- 0 until stqEntries) { - commitFreeVec(idx) := - (0 until requestCount) - .map(lane => - ingress.io.acceptedMask(lane) && - io.reqs(lane).ownsStqRow && - io.reqs(lane).last && - (io.reqs(lane).stqIndex === idx.U)) - .reduce(_ || _) - } - - io.modelBatchReady := modelBatchReady - io.modelFull := !modelBatchReady - io.acceptedMask := ingress.io.acceptedMask - io.structuralBlockedMask := ingress.io.blockedMask - io.stalledMask := validReqMask & ~ingress.io.acceptedMask - io.commitFreeMask := commitFreeVec.asUInt - io.commitFreeMaskValid := commitFreeVec.asUInt.orR - io.commitFreeCount := PopCount(commitFreeVec)(freeCountWidth - 1, 0) - io.wakeups := ingress.io.wakeups - io.entries := ingress.io.entries - io.validMask := ingress.io.validMask - io.fullLineMask := ingress.io.fullLineMask - io.entryCount := ingress.io.entryCount - io.freeCount := ingress.io.freeCount - io.ingressFull := ingress.io.full -} diff --git a/chisel/src/main/scala/linxcore/lsu/SCBLoadSnapshotLookup.scala b/chisel/src/main/scala/linxcore/lsu/SCBLoadSnapshotLookup.scala new file mode 100644 index 00000000..33e5210e --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/SCBLoadSnapshotLookup.scala @@ -0,0 +1,36 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{Mux1H, PopCount} + +class SCBLoadSnapshotLookupIO( + val scbEntries: Int, + val addrWidth: Int, + val lineBytes: Int) extends Bundle { + val rows = Input(Vec(scbEntries, new SCBLineEntry(addrWidth, lineBytes))) + val lineAddress = Input(UInt(addrWidth.W)) + val returned = Output(Bool()) + val validMask = Output(UInt(lineBytes.W)) + val data = Output(UInt((lineBytes * 8).W)) + val ambiguous = Output(Bool()) +} + +/** Combinational view of the retained SCB owner for one aligned load line. + * Stale rows are ignored. Multiple live rows are rejected instead of + * selecting an arbitrary snapshot. + */ +class SCBLoadSnapshotLookup( + val scbEntries: Int, + val addrWidth: Int, + val lineBytes: Int) extends Module { + require(scbEntries > 0) + val io = IO(new SCBLoadSnapshotLookupIO(scbEntries, addrWidth, lineBytes)) + + val matches = VecInit(io.rows.map(row => row.valid && + row.state === SCBEntryState.Valid && row.lineAddr === io.lineAddress)) + val unique = PopCount(matches) === 1.U + io.ambiguous := PopCount(matches) > 1.U + io.returned := !io.ambiguous + io.validMask := Mux(unique, Mux1H(matches, io.rows.map(_.byteMask)), 0.U) + io.data := Mux(unique, Mux1H(matches, io.rows.map(_.data)), 0.U) +} diff --git a/chisel/src/main/scala/linxcore/lsu/SCBLookupControl.scala b/chisel/src/main/scala/linxcore/lsu/SCBLookupControl.scala index 67a5186b..41c7a1af 100644 --- a/chisel/src/main/scala/linxcore/lsu/SCBLookupControl.scala +++ b/chisel/src/main/scala/linxcore/lsu/SCBLookupControl.scala @@ -21,7 +21,9 @@ class SCBDCacheUpdate( class SCBL2OwnershipRequest( val scbEntries: Int, val addrWidth: Int = 64, - val lineBytes: Int = 64) + val lineBytes: Int = 64, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { private val entryIndexWidth = math.max(1, log2Ceil(scbEntries)) @@ -30,6 +32,8 @@ class SCBL2OwnershipRequest( val lineAddr = UInt(addrWidth.W) val size = UInt(7.W) val txnTid = UInt((entryIndexWidth + 2).W) + val transactionValue = UInt(memoryTransactionIdWidth.W) + val transactionGeneration = UInt(memoryTransactionGenerationWidth.W) val write = Bool() val upgrade = Bool() } @@ -37,7 +41,9 @@ class SCBL2OwnershipRequest( class SCBLookupControlIO( val scbEntries: Int, val addrWidth: Int = 64, - val lineBytes: Int = 64) + val lineBytes: Int = 64, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { val lookupRequest = Input(new SCBEgressLookupRequest(scbEntries, addrWidth, lineBytes)) val dcacheReady = Input(Bool()) @@ -52,13 +58,17 @@ class SCBLookupControlIO( val missMask = Output(UInt(scbEntries.W)) val freeMask = Output(UInt(scbEntries.W)) val dcacheUpdate = Output(new SCBDCacheUpdate(scbEntries, addrWidth, lineBytes)) - val l2Request = Output(new SCBL2OwnershipRequest(scbEntries, addrWidth, lineBytes)) + val l2Request = Output(new SCBL2OwnershipRequest( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) } class SCBLookupControl( val scbEntries: Int = 16, val addrWidth: Int = 64, - val lineBytes: Int = 64) + val lineBytes: Int = 64, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Module { require(scbEntries > 0, "SCB lookup control requires at least one entry") require(addrWidth >= 7, "SCB lookup control needs at least 7 address bits for 64-byte lines") @@ -66,7 +76,9 @@ class SCBLookupControl( private val entryIndexWidth = math.max(1, log2Ceil(scbEntries)) - val io = IO(new SCBLookupControlIO(scbEntries, addrWidth, lineBytes)) + val io = IO(new SCBLookupControlIO( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) val needsL2 = !io.dcacheWriteHit val lookupReady = io.dcacheReady && (!needsL2 || io.l2RequestReady) @@ -85,7 +97,9 @@ class SCBLookupControl( dcacheUpdate.data := io.lookupRequest.data dcacheUpdate.broadcastUpgrade := dcacheUpdate.valid - val l2Request = Wire(new SCBL2OwnershipRequest(scbEntries, addrWidth, lineBytes)) + val l2Request = Wire(new SCBL2OwnershipRequest( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) l2Request := 0.U.asTypeOf(l2Request) l2Request.valid := missPath l2Request.entryIndex := io.lookupRequest.entryIndex diff --git a/chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala b/chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala index b5b727fd..f9c20dd8 100644 --- a/chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala +++ b/chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala @@ -13,7 +13,9 @@ class SCBRowBankIO( val sizeWidth: Int = 4, val lineBytes: Int = 64, val robEntries: Int = 0, - val lsidWidth: Int = 32) + val lsidWidth: Int = 32, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { private val identityEntries = if (robEntries > 0) robEntries else stqEntries private val scbCountWidth = log2Ceil(scbEntries + 1) @@ -32,9 +34,16 @@ class SCBRowBankIO( val l2RequestReady = Input(Bool()) val rawRespValid = Input(Bool()) val rawRespTxnId = Input(UInt(responseTxnIdWidth.W)) + val rawRespTransactionValue = Input(UInt(memoryTransactionIdWidth.W)) + val rawRespTransactionGeneration = + Input(UInt(memoryTransactionGenerationWidth.W)) + val rawRespError = Input(Bool()) val rawRespWrite = Input(Bool()) val rawRespUpgrade = Input(Bool()) val rawRespReady = Output(Bool()) + val rawRespAccepted = Output(Bool()) + val rawRespSucceeded = Output(Bool()) + val rawRespLineAddr = Output(UInt(addrWidth.W)) val modelBatchReady = Output(Bool()) val modelFull = Output(Bool()) @@ -83,7 +92,11 @@ class SCBRowBankIO( val lookupFire = Output(Bool()) val lookupStall = Output(Bool()) val dcacheUpdate = Output(new SCBDCacheUpdate(scbEntries, addrWidth, lineBytes)) - val l2Request = Output(new SCBL2OwnershipRequest(scbEntries, addrWidth, lineBytes)) + val l2Request = Output(new SCBL2OwnershipRequest( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) + val quiescent = Output(Bool()) + val protocolError = Output(Bool()) val stateAcceptedToLookupMask = Output(UInt(scbEntries.W)) val stateMissMask = Output(UInt(scbEntries.W)) @@ -120,7 +133,9 @@ class SCBRowBank( val sizeWidth: Int = 4, val lineBytes: Int = 64, val robEntries: Int = 0, - val lsidWidth: Int = 32) + val lsidWidth: Int = 32, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Module { private val identityEntries = if (robEntries > 0) robEntries else stqEntries require(stqEntries > 1, "STQ entries must be greater than one") @@ -137,6 +152,7 @@ class SCBRowBank( private val scbCountWidth = log2Ceil(scbEntries + 1) private val freeCountWidth = log2Ceil(requestCount + 1) + private val responseTxnIdWidth = math.max(1, log2Ceil(scbEntries)) + 2 val io = IO(new SCBRowBankIO( stqEntries, @@ -148,7 +164,9 @@ class SCBRowBank( sizeWidth, lineBytes, identityEntries, - lsidWidth)) + lsidWidth, + memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) private def zeroEntry: SCBLineEntry = { val entry = Wire(new SCBLineEntry(addrWidth, lineBytes)) @@ -266,18 +284,59 @@ class SCBRowBank( retrySelect.io.retryHeadValid := responseRetryQueue.io.headValid retrySelect.io.retryHeadEntryIndex := responseRetryQueue.io.headEntryIndex - val lookup = Module(new SCBLookupControl(scbEntries, addrWidth, lineBytes)) + val lookup = Module(new SCBLookupControl( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) lookup.io.lookupRequest := retrySelect.io.lookupRequest lookup.io.dcacheReady := io.dcacheReady lookup.io.dcacheWriteHit := io.dcacheWriteHit lookup.io.dcacheTagHit := io.dcacheTagHit lookup.io.l2RequestReady := io.l2RequestReady + val outstandingValid = RegInit(VecInit(Seq.fill(scbEntries)(false.B))) + val outstandingValue = Reg(Vec(scbEntries, + UInt(memoryTransactionIdWidth.W))) + val outstandingGeneration = Reg(Vec(scbEntries, + UInt(memoryTransactionGenerationWidth.W))) + val outstandingWrite = Reg(Vec(scbEntries, Bool())) + val outstandingUpgrade = Reg(Vec(scbEntries, Bool())) + val nextTransactionGeneration = + RegInit(0.U(memoryTransactionGenerationWidth.W)) + val rawResponseIndex = io.rawRespTxnId(responseTxnIdWidth - 1, 2) + val rawResponseIndexInRange = rawResponseIndex < scbEntries.U + val rawResponseExact = rawResponseIndexInRange && + outstandingValid(rawResponseIndex) && + outstandingValue(rawResponseIndex) === io.rawRespTransactionValue && + outstandingGeneration(rawResponseIndex) === + io.rawRespTransactionGeneration + val staleRawResponse = io.rawRespValid && !rawResponseExact + io.rawRespAccepted := io.rawRespValid && io.rawRespReady && rawResponseExact + io.rawRespSucceeded := io.rawRespAccepted && !io.rawRespError + io.rawRespLineAddr := Mux(rawResponseExact, + ingressEntries(rawResponseIndex).lineAddr, 0.U) + val responseBuffer = Module(new SCBResponseBuffer(scbEntries, responseBufferDepth)) - responseBuffer.io.rawValid := io.rawRespValid + responseBuffer.io.rawValid := io.rawRespValid && rawResponseExact && + !io.rawRespError responseBuffer.io.rawTxnId := io.rawRespTxnId - responseBuffer.io.rawWriteResp := io.rawRespWrite - responseBuffer.io.rawUpgradeResp := io.rawRespUpgrade + responseBuffer.io.rawWriteResp := Mux(rawResponseExact, + outstandingWrite(rawResponseIndex), io.rawRespWrite) + responseBuffer.io.rawUpgradeResp := Mux(rawResponseExact, + outstandingUpgrade(rawResponseIndex), io.rawRespUpgrade) + + val l2RequestFire = lookup.io.l2Request.valid && io.l2RequestReady + when(l2RequestFire) { + val entry = lookup.io.l2Request.entryIndex + outstandingValid(entry) := true.B + outstandingValue(entry) := lookup.io.l2Request.txnTid + outstandingGeneration(entry) := nextTransactionGeneration + outstandingWrite(entry) := lookup.io.l2Request.write + outstandingUpgrade(entry) := lookup.io.l2Request.upgrade + nextTransactionGeneration := nextTransactionGeneration + 1.U + } + when(io.rawRespValid && io.rawRespReady && rawResponseExact) { + outstandingValid(rawResponseIndex) := false.B + } val responseDecode = Module(new SCBResponseDecode(scbEntries, addrWidth, lineBytes)) responseDecode.io.entries := ingressEntries @@ -316,14 +375,15 @@ class SCBRowBank( io.modelBatchReady := modelBatchReady io.modelFull := !modelBatchReady - io.rawRespReady := responseBuffer.io.rawReady + io.rawRespReady := Mux(rawResponseExact && !io.rawRespError, + responseBuffer.io.rawReady, true.B) io.acceptedMask := acceptedVec.asUInt io.acceptedReqs := acceptedReqs io.structuralBlockedMask := blockedVec.asUInt io.stalledMask := validReqMask & ~acceptedVec.asUInt io.commitFreeMask := commitFreeVec.asUInt io.commitFreeMaskValid := commitFreeVec.asUInt.orR - io.commitFreeCount := PopCount(commitFreeVec)(freeCountWidth - 1, 0) + io.commitFreeCount := PopCount(commitFreeVec).pad(freeCountWidth) io.wakeups := wakeups io.entries := entries io.nextEntries := state.io.nextEntries @@ -360,6 +420,8 @@ class SCBRowBank( io.lookupStall := lookup.io.lookupStall io.dcacheUpdate := lookup.io.dcacheUpdate io.l2Request := lookup.io.l2Request + io.l2Request.transactionValue := lookup.io.l2Request.txnTid + io.l2Request.transactionGeneration := nextTransactionGeneration io.stateAcceptedToLookupMask := state.io.acceptedToLookupMask io.stateMissMask := state.io.missStateMask @@ -387,4 +449,11 @@ class SCBRowBank( io.respBufferFull := responseBuffer.io.full io.respBufferEmpty := responseBuffer.io.empty io.respBufferCount := responseBuffer.io.count + io.protocolError := staleRawResponse || + (io.rawRespAccepted && io.rawRespError) + io.quiescent := !currentValidVec.asUInt.orR && + !outstandingValid.asUInt.orR && responseBuffer.io.empty && + responseRetryQueue.io.empty && !responseDecode.io.memRespValid && + !retrySelect.io.lookupRequest.valid && !lookup.io.dcacheUpdate.valid && + !lookup.io.l2Request.valid } diff --git a/chisel/src/main/scala/linxcore/lsu/STQCommittedStoreSerializer.scala b/chisel/src/main/scala/linxcore/lsu/STQCommittedStoreSerializer.scala index 6ca3c275..1261255d 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQCommittedStoreSerializer.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQCommittedStoreSerializer.scala @@ -50,9 +50,11 @@ class STQSerializedStoreRequest( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val transactionIdWidth: Int = 8) + val transactionIdWidth: Int = 8, + val transactionGenerationWidth: Int = 8) extends Bundle { val transactionId = UInt(transactionIdWidth.W) + val transactionGeneration = UInt(transactionGenerationWidth.W) val memoryClass = STQMemoryClass() val issue = new STQCommitIssue( robEntries, stqEntries, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, @@ -63,9 +65,12 @@ class STQSerializedStoreRequest( stidWidth) } -class STQSerializedStoreResponse(val transactionIdWidth: Int = 8) +class STQSerializedStoreResponse( + val transactionIdWidth: Int = 8, + val transactionGenerationWidth: Int = 8) extends Bundle { val transactionId = UInt(transactionIdWidth.W) + val transactionGeneration = UInt(transactionGenerationWidth.W) val error = Bool() } @@ -85,7 +90,8 @@ class STQCommittedStoreSerializerIO( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val transactionIdWidth: Int = 8) + val transactionIdWidth: Int = 8, + val transactionGenerationWidth: Int = 8) extends Bundle { val batch = Flipped(Decoupled(new STQSerializedStoreBatch( stqEntries, robEntries, issueWidth, addrWidth, dataWidth, sizeWidth, @@ -96,9 +102,10 @@ class STQCommittedStoreSerializerIO( stqEntries, robEntries, addrWidth, dataWidth, sizeWidth, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, residentGenerationWidth, - leaseGenerationWidth, transactionIdWidth)) + leaseGenerationWidth, transactionIdWidth, transactionGenerationWidth)) val response = Flipped(Decoupled( - new STQSerializedStoreResponse(transactionIdWidth))) + new STQSerializedStoreResponse( + transactionIdWidth, transactionGenerationWidth))) /** Ordinary recovery fences only new committed work. An accepted batch is * already architectural and must run to its exact response. */ @@ -141,7 +148,8 @@ class STQCommittedStoreSerializer( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val transactionIdWidth: Int = 8) + val transactionIdWidth: Int = 8, + val transactionGenerationWidth: Int = 8) extends Module { require(stqEntries > 1 && (stqEntries & (stqEntries - 1)) == 0, "serialized stores require a power-of-two physical STQ") @@ -150,6 +158,8 @@ class STQCommittedStoreSerializer( require(issueWidth > 0, "serialized store issue width must be nonzero") require(transactionIdWidth > 1, "serialized response identity needs a generation-capable transaction ID") + require(transactionGenerationWidth > 0, + "serialized response identity needs a transaction generation") private val requestCount = issueWidth * 2 private val requestCountWidth = log2Ceil(requestCount + 1) @@ -158,7 +168,7 @@ class STQCommittedStoreSerializer( stqEntries, robEntries, issueWidth, addrWidth, dataWidth, sizeWidth, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, residentGenerationWidth, - leaseGenerationWidth, transactionIdWidth)) + leaseGenerationWidth, transactionIdWidth, transactionGenerationWidth)) val busy = RegInit(false.B) val waitingResponse = RegInit(false.B) @@ -172,7 +182,11 @@ class STQCommittedStoreSerializer( stqEntries, addrWidth, dataWidth, sizeWidth, robEntries, lsidWidth, stidWidth))) val nextTransactionId = RegInit(0.U(transactionIdWidth.W)) + val nextTransactionGeneration = + RegInit(0.U(transactionGenerationWidth.W)) val outstandingTransactionId = Reg(UInt(transactionIdWidth.W)) + val outstandingTransactionGeneration = + Reg(UInt(transactionGenerationWidth.W)) val accumulatedError = RegInit(false.B) val acceptedRequestCount = RegInit(0.U(requestCountWidth.W)) @@ -219,12 +233,14 @@ class STQCommittedStoreSerializer( val currentIssue = retainedIssues(currentIndex >> 1) io.request.valid := busy && !waitingResponse && pendingMask.orR io.request.bits.transactionId := nextTransactionId + io.request.bits.transactionGeneration := nextTransactionGeneration io.request.bits.memoryClass := retainedClass io.request.bits.issue := currentIssue io.request.bits.fragment := currentRequest val responseExact = waitingResponse && - io.response.bits.transactionId === outstandingTransactionId + io.response.bits.transactionId === outstandingTransactionId && + io.response.bits.transactionGeneration === outstandingTransactionGeneration io.response.ready := responseExact io.staleResponse := io.response.valid && !responseExact @@ -270,6 +286,10 @@ class STQCommittedStoreSerializer( when(requestFire) { waitingResponse := true.B outstandingTransactionId := nextTransactionId + outstandingTransactionGeneration := nextTransactionGeneration + when(nextTransactionId.andR) { + nextTransactionGeneration := nextTransactionGeneration + 1.U + } nextTransactionId := nextTransactionId + 1.U acceptedRequestCount := acceptedRequestCount + 1.U } @@ -288,9 +308,14 @@ class STQCommittedStoreSerializer( when(io.request.valid && !io.request.ready) { assert(io.request.bits.transactionId === nextTransactionId, "serialized store transaction identity must remain stable") + assert(io.request.bits.transactionGeneration === nextTransactionGeneration, + "serialized store transaction generation must remain stable") } when(responseFire) { assert(io.response.bits.transactionId === outstandingTransactionId, "only the exact serialized-store response may advance state") + assert(io.response.bits.transactionGeneration === + outstandingTransactionGeneration, + "serialized-store response generation must match exactly") } } diff --git a/chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala b/chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala index a136d7b8..74a1bfe1 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala @@ -68,10 +68,12 @@ class STQStoreRequest( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val physicalStqEntries: Int = 0) + val physicalStqEntries: Int = 0, + val transactionIdWidth: Int = 64) extends Bundle { private val ridSlotWidth = log2Ceil(entries) private val leaseEntries = if (physicalStqEntries > 0) physicalStqEntries else entries + val transactionId = UInt(transactionIdWidth.W) val storeType = STQStoreType() val peId = UInt(peIdWidth.W) val stid = UInt(stidWidth.W) @@ -123,9 +125,11 @@ class STQEntryBankRow( val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, - val leaseGenerationWidth: Int = 8) + val leaseGenerationWidth: Int = 8, + val transactionIdWidth: Int = 64) extends Bundle { private val ridSlotWidth = log2Ceil(entries) + val transactionId = UInt(transactionIdWidth.W) val valid = Bool() val status = STQEntryStatus() val storeType = STQStoreType() @@ -206,7 +210,8 @@ class STQEntryBankIO( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val maxReserveBeats: Int = 2) + val maxReserveBeats: Int = 2, + val transactionIdWidth: Int = 64) extends Bundle { private val identityEntries = if (robEntries > 0) robEntries else entries private val ptrWidth = log2Ceil(entries) @@ -226,7 +231,8 @@ class STQEntryBankIO( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth, entries)) + residentGenerationWidth, leaseGenerationWidth, entries, + transactionIdWidth)) val insertReady = Output(Bool()) val insertAccepted = Output(Bool()) val insertAllocated = Output(Bool()) @@ -243,7 +249,8 @@ class STQEntryBankIO( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth, entries)) + residentGenerationWidth, leaseGenerationWidth, entries, + transactionIdWidth)) val reserveReady = Output(Bool()) val reserveAccepted = Output(Bool()) val reserveConflict = Output(Bool()) @@ -255,7 +262,8 @@ class STQEntryBankIO( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth, entries))) + residentGenerationWidth, leaseGenerationWidth, entries, + transactionIdWidth))) val reserveBatchReady = Output(Bool()) val reserveBatchAccepted = Output(Bool()) val reserveBatchConflict = Output(Bool()) @@ -267,7 +275,8 @@ class STQEntryBankIO( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth, entries)) + residentGenerationWidth, leaseGenerationWidth, entries, + transactionIdWidth)) val fillReady = Output(Bool()) val fillAccepted = Output(Bool()) val fillConflict = Output(Bool()) @@ -315,7 +324,7 @@ class STQEntryBankIO( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth))) + residentGenerationWidth, leaseGenerationWidth, transactionIdWidth))) val occupiedMask = Output(UInt(entries.W)) val waitMask = Output(UInt(entries.W)) val commitMask = Output(UInt(entries.W)) @@ -365,7 +374,8 @@ class STQEntryBank( val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, val leaseGenerationWidth: Int = 8, - val maxReserveBeats: Int = 2) + val maxReserveBeats: Int = 2, + val transactionIdWidth: Int = 64) extends Module { private val identityEntries = if (robEntries > 0) robEntries else entries require(entries > 1, "STQ entries must be greater than one") @@ -374,8 +384,8 @@ class STQEntryBank( require((identityEntries & (identityEntries - 1)) == 0, "ROB entries must be a power of two") require(lsidWidth >= 2, "LSID width must support modular serial ordering") require(leaseGenerationWidth > 0, "STQ lease generation width must be positive") - require(maxReserveBeats == 2, - "canonical scalar STQ currently supports one or two atomic store beats") + require(maxReserveBeats >= 2 && maxReserveBeats <= entries, + "canonical scalar STQ atomic reservation width must fit its capacity") private val countWidth = log2Ceil(entries + 1) @@ -385,14 +395,15 @@ class STQEntryBank( entries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, identityEntries, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth, maxReserveBeats)) + residentGenerationWidth, leaseGenerationWidth, maxReserveBeats, + transactionIdWidth)) private def rowBundle: STQEntryBankRow = new STQEntryBankRow( identityEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth, leaseGenerationWidth) + residentGenerationWidth, leaseGenerationWidth, transactionIdWidth) private def zeroRow: STQEntryBankRow = { val row = Wire(rowBundle) @@ -413,6 +424,7 @@ class STQEntryBank( reserved: Bool = false.B): STQEntryBankRow = { val row = Wire(rowBundle) row := 0.U.asTypeOf(row) + row.transactionId := req.transactionId row.valid := true.B row.status := STQEntryStatus.Wait row.storeType := req.storeType @@ -690,38 +702,44 @@ class STQEntryBank( (row.storeIdFull === req.storeIdFull) }).asUInt.orR - val batchMaskLegal = - (io.reserveBatchMask === 1.U) || (io.reserveBatchMask === 3.U) + val batchMaskLegal = io.reserveBatchMask.orR && + (io.reserveBatchMask & (io.reserveBatchMask + 1.U)) === 0.U val batchIdentityValid = VecInit((0 until maxReserveBeats).map { beat => !io.reserveBatchMask(beat) || exactRequestIdentityValid(io.reserveBatch(beat)) }).asUInt.andR - val batchOwnerExact = - !io.reserveBatchMask(1) || - (io.reserveBatch(0).exactOwner.asUInt === - io.reserveBatch(1).exactOwner.asUInt) - val batchLogicalExact = - !io.reserveBatchMask(1) || - (io.reserveBatch(0).logicalFirstLsid === - io.reserveBatch(1).logicalFirstLsid) && - (io.reserveBatch(0).logicalFirstStoreId === - io.reserveBatch(1).logicalFirstStoreId) && - (io.reserveBatch(0).logicalRequestCount === 2.U) && - (io.reserveBatch(1).logicalRequestCount === 2.U) && - (io.reserveBatch(0).logicalBeat === 0.U) && - (io.reserveBatch(1).logicalBeat === 1.U) - val batchSerialConsecutive = - !io.reserveBatchMask(1) || - ((io.reserveBatch(1).lsIdFull === io.reserveBatch(0).lsIdFull + 1.U) && - (io.reserveBatch(1).storeIdFull === - io.reserveBatch(0).storeIdFull + 1.U)) + val batchLogicalExact = (1 until maxReserveBeats).map { beat => + val current = io.reserveBatch(beat) + val previous = io.reserveBatch(beat - 1) + val continuesLogical = current.exactOwner.asUInt === + previous.exactOwner.asUInt + !io.reserveBatchMask(beat) || Mux(continuesLogical, + current.logicalFirstLsid === previous.logicalFirstLsid && + current.logicalFirstStoreId === previous.logicalFirstStoreId && + current.logicalRequestCount === previous.logicalRequestCount && + current.logicalBeat === previous.logicalBeat + 1.U, + current.logicalBeat === 0.U) + }.reduce(_ && _) + val batchSerialConsecutive = (1 until maxReserveBeats).map { beat => + !io.reserveBatchMask(beat) || + (io.reserveBatch(beat).lsIdFull === + io.reserveBatch(beat - 1).lsIdFull + 1.U) && + (io.reserveBatch(beat).storeIdFull === + io.reserveBatch(beat - 1).storeIdFull + 1.U) + }.reduce(_ && _) val batchDuplicatesResident = VecInit((0 until maxReserveBeats).map { beat => io.reserveBatchMask(beat) && duplicatesResident(io.reserveBatch(beat)) }).asUInt.orR - val batchInternalDuplicate = io.reserveBatchMask(1) && - (io.reserveBatch(0).lsIdFull === io.reserveBatch(1).lsIdFull) && - (io.reserveBatch(0).storeIdFull === io.reserveBatch(1).storeIdFull) + val batchInternalDuplicate = (for { + left <- 0 until maxReserveBeats + right <- left + 1 until maxReserveBeats + } yield io.reserveBatchMask(left) && io.reserveBatchMask(right) && + io.reserveBatch(left).exactOwner.asUInt === + io.reserveBatch(right).exactOwner.asUInt && + io.reserveBatch(left).lsIdFull === io.reserveBatch(right).lsIdFull && + io.reserveBatch(left).storeIdFull === + io.reserveBatch(right).storeIdFull).reduce(_ || _) val batchShapeValid = batchMaskLegal && batchIdentityValid && - batchOwnerExact && batchLogicalExact && batchSerialConsecutive && + batchLogicalExact && batchSerialConsecutive && !batchDuplicatesResident && !batchInternalDuplicate val batchFreeEnough = PopCount(freeMask) >= PopCount(io.reserveBatchMask) io.reserveBatchReady := @@ -729,9 +747,12 @@ class STQEntryBank( io.reserveBatchAccepted := io.reserveBatchValid && io.reserveBatchReady io.reserveBatchConflict := io.reserveBatchValid && !batchShapeValid val batchIndices = Wire(Vec(maxReserveBeats, UInt(log2Ceil(entries).W))) - batchIndices(0) := freeIndex - batchIndices(1) := secondFreeIndex + val batchRemainingFree = Wire(Vec(maxReserveBeats + 1, UInt(entries.W))) + batchRemainingFree(0) := freeMask for (beat <- 0 until maxReserveBeats) { + batchIndices(beat) := PriorityEncoder(batchRemainingFree(beat)) + batchRemainingFree(beat + 1) := batchRemainingFree(beat) & + ~UIntToOH(batchIndices(beat), entries) val generation = leaseGenerations(batchIndices(beat)) + 1.U io.reserveBatchLeases(beat).valid := io.reserveBatchAccepted && io.reserveBatchMask(beat) diff --git a/chisel/src/main/scala/linxcore/lsu/STQLoadForwardResultPipeline.scala b/chisel/src/main/scala/linxcore/lsu/STQLoadForwardResultPipeline.scala index ad8760b3..be9fa688 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQLoadForwardResultPipeline.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQLoadForwardResultPipeline.scala @@ -60,6 +60,7 @@ class STQLoadForwardResultPipelineIO( val response = Flipped(Decoupled(new STQLoadForwardResponse( robEntries, stqEntries, addrWidth, stidWidth, pcWidth, lineBytes, lsidWidth, tokenWidth))) + val normalReady = Input(Bool()) val returnReady = Input(Bool()) val hardBlock = Decoupled(new STQLoadForwardResponse( @@ -69,12 +70,14 @@ class STQLoadForwardResultPipelineIO( val hardBlockAccepted = Output(Bool()) val e3Valid = Output(Bool()) + val e3Identity = Output(new STQLoadForwardResultIdentity) val e3LoadByteMask = Output(UInt(lineBytes.W)) val e3ForwardMask = Output(UInt(lineBytes.W)) val e3WaitMask = Output(UInt(lineBytes.W)) val e3MergedData = Output(UInt((lineBytes * 8).W)) val e4Valid = Output(Bool()) + val e4Identity = Output(new STQLoadForwardResultIdentity) val e4LineData = Output(UInt((lineBytes * 8).W)) val e4ValidMask = Output(UInt(lineBytes.W)) val e4LoadByteMask = Output(UInt(lineBytes.W)) @@ -82,6 +85,8 @@ class STQLoadForwardResultPipelineIO( val e4WaitMask = Output(UInt(lineBytes.W)) val e4DataComplete = Output(Bool()) val e4SourcesReturned = Output(Bool()) + val e4ScbReturned = Output(Bool()) + val e4StqReturned = Output(Bool()) val e4WakeupValid = Output(Bool()) val e4WaitStore = Output(new LoadStoreForwardWait( robEntries, stqEntries, pcWidth, lsidWidth)) @@ -128,7 +133,7 @@ class STQLoadForwardResultPipeline( io.hardBlock.valid := io.response.valid && hardBlocked && !io.flush io.hardBlock.bits := io.response.bits io.response.ready := !io.flush && Mux(hardBlocked, - io.hardBlock.ready, true.B) + io.hardBlock.ready, io.normalReady) io.accepted := io.response.fire && !hardBlocked io.hardBlockAccepted := io.hardBlock.fire @@ -147,12 +152,31 @@ class STQLoadForwardResultPipeline( result.io.e2StqReturned := io.accepted result.io.e2ReturnReady := io.returnReady + val acceptedIdentity = Wire(new STQLoadForwardResultIdentity) + acceptedIdentity.loadId := io.response.bits.query.loadId + acceptedIdentity.attempt := io.response.bits.query.attempt + acceptedIdentity.returnPipeIndex := + io.response.bits.query.returnPipeIndex + val e3Identity = RegInit(0.U.asTypeOf(acceptedIdentity)) + val e4Identity = RegInit(0.U.asTypeOf(acceptedIdentity)) + when(io.flush) { + e3Identity := 0.U.asTypeOf(e3Identity) + e4Identity := 0.U.asTypeOf(e4Identity) + }.otherwise { + e4Identity := e3Identity + when(io.accepted) { + e3Identity := acceptedIdentity + } + } + io.e3Valid := result.io.e3Valid + io.e3Identity := e3Identity io.e3LoadByteMask := result.io.e3LoadByteMask io.e3ForwardMask := result.io.e3ForwardMask io.e3WaitMask := result.io.e3WaitMask io.e3MergedData := result.io.e3MergedData io.e4Valid := result.io.e4Valid + io.e4Identity := e4Identity io.e4LineData := result.io.e4LineData io.e4ValidMask := result.io.e4ValidMask io.e4LoadByteMask := result.io.e4LoadByteMask @@ -160,6 +184,8 @@ class STQLoadForwardResultPipeline( io.e4WaitMask := result.io.e4WaitMask io.e4DataComplete := result.io.e4DataComplete io.e4SourcesReturned := result.io.e4SourcesReturned + io.e4ScbReturned := result.io.e4ScbReturned + io.e4StqReturned := result.io.e4StqReturned io.e4WakeupValid := result.io.e4WakeupValid io.e4WaitStore := result.io.e4WaitStore io.e4MissKind := result.io.e4MissKind diff --git a/chisel/src/main/scala/linxcore/lsu/STQLoadForwardingPipeline.scala b/chisel/src/main/scala/linxcore/lsu/STQLoadForwardingPipeline.scala index 571e7e23..abad718b 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQLoadForwardingPipeline.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQLoadForwardingPipeline.scala @@ -6,6 +6,11 @@ import chisel3.util.{Cat, Decoupled, log2Ceil} import linxcore.common.LSIDOrder import linxcore.rob.ROBID +object STQLoadForwardQuery { + // Protocol width, deliberately independent of a concrete LSU pipe count. + val ReturnPipeIndexWidth = 8 +} + /** One production load lookup presented to the canonical STQ image. */ class STQLoadForwardQuery( val robEntries: Int, @@ -16,6 +21,9 @@ class STQLoadForwardQuery( val tokenWidth: Int = 64) extends Bundle { val token = UInt(tokenWidth.W) + val loadId = new LoadCanonicalRowIdentity + val attempt = new LoadAttemptIdentity + val returnPipeIndex = UInt(STQLoadForwardQuery.ReturnPipeIndexWidth.W) val stid = UInt(stidWidth.W) val loadBid = new ROBID(robEntries) val loadLsIdFullValid = Bool() @@ -29,6 +37,13 @@ class STQLoadForwardQuery( val scbReturned = Bool() } +/** Minimal identity retained beside one asynchronous forwarding result. */ +class STQLoadForwardResultIdentity extends Bundle { + val loadId = new LoadCanonicalRowIdentity + val attempt = new LoadAttemptIdentity + val returnPipeIndex = UInt(STQLoadForwardQuery.ReturnPipeIndexWidth.W) +} + /** Retained E3 result from one replicated STQ load lookup pipe. */ class STQLoadForwardResponse( val robEntries: Int, @@ -146,6 +161,10 @@ class STQLoadForwardingPipeline( "production scalar STQ forwarding currently consumes 64-bit stores") require(lsidWidth >= 2, "full LSID must support modular serial ordering") + require(stidWidth <= LoadAttemptIdentity.ScopeWidth, + "STQ query STID must fit the canonical load-attempt producer scope") + require(loadPipes <= (1 << STQLoadForwardQuery.ReturnPipeIndexWidth), + "STQ load-pipe index must fit the canonical query protocol field") private val lineOffsetWidth = log2Ceil(lineBytes) @@ -298,7 +317,14 @@ class STQLoadForwardingPipeline( unknownWait.pc := unknownPc val computed = Wire(chiselTypeOf(io.responses(pipe).bits)) - val queryIdentityInvalid = !query.loadBid.valid || + val loadIdInvalid = !query.loadId.valid || + query.loadId.generation( + LoadAttemptIdentity.GenerationWidth - 1, 1).orR + val attemptInvalid = !query.attempt.valid || + !LoadAttemptIdentity.wellFormed(query.attempt) || + query.attempt.producer.stid =/= query.stid + val queryIdentityInvalid = loadIdInvalid || attemptInvalid || + query.returnPipeIndex =/= pipe.U || !query.loadBid.valid || !query.loadLsIdFullValid || query.size === 0.U val loadCrossesLine = (query.address(lineOffsetWidth - 1, 0) +& query.size) > lineBytes.U diff --git a/chisel/src/main/scala/linxcore/lsu/STQRobCommitIngress.scala b/chisel/src/main/scala/linxcore/lsu/STQRobCommitIngress.scala index 860fc99d..874b8669 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQRobCommitIngress.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQRobCommitIngress.scala @@ -19,12 +19,16 @@ class STQRobCommitToken( val ridGenerationWidth: Int = 8, val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, - val residentGenerationWidth: Int = 8) + val residentGenerationWidth: Int = 8, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { val logicalFirstLsid = UInt(lsidWidth.W) val logicalFirstStoreId = UInt(lsidWidth.W) val logicalRequestCount = UInt(2.W) val logicalBeat = UInt(1.W) + val transactionValue = UInt(memoryTransactionIdWidth.W) + val transactionGeneration = UInt(memoryTransactionGenerationWidth.W) val exactOwner = new STQExactOwner( peIdWidth, stidWidth, nativeBidWidth, log2Ceil(robEntries), ridGenerationWidth, brobGenerationWidth, memberIndexWidth, @@ -48,14 +52,17 @@ class STQRobCommitIngressIO( val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, - val leaseGenerationWidth: Int = 8) + val leaseGenerationWidth: Int = 8, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { private val ptrWidth = log2Ceil(entries) val commit = Flipped(Decoupled(new STQRobCommitToken( robEntries, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth))) + residentGenerationWidth, memoryTransactionIdWidth, + memoryTransactionGenerationWidth))) val rows = Input(Vec(entries, new STQEntryBankRow( robEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, 64, lsidWidth, nativeBidWidth, @@ -99,7 +106,9 @@ class STQRobCommitIngress( val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, - val leaseGenerationWidth: Int = 8) + val leaseGenerationWidth: Int = 8, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Module { require(entries > 1 && (entries & (entries - 1)) == 0, "STQ ROB-commit ingress requires a power-of-two physical STQ") @@ -110,7 +119,8 @@ class STQRobCommitIngress( entries, robEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, - memberIndexWidth, residentGenerationWidth, leaseGenerationWidth)) + memberIndexWidth, residentGenerationWidth, leaseGenerationWidth, + memoryTransactionIdWidth, memoryTransactionGenerationWidth)) val token = io.commit.bits val tokenShapeExact = token.exactOwner.valid && diff --git a/chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala b/chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala index 64e32500..db71af59 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala @@ -33,7 +33,9 @@ class STQSCBCommitBackendIO( val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, - val leaseGenerationWidth: Int = 8) + val leaseGenerationWidth: Int = 8, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Bundle { private val ptrWidth = log2Ceil(entries) private val queueCountWidth = log2Ceil(queueEntries + 1) @@ -52,7 +54,8 @@ class STQSCBCommitBackendIO( val robStoreCommit = Flipped(Decoupled(new STQRobCommitToken( robEntries, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, - residentGenerationWidth))) + residentGenerationWidth, memoryTransactionIdWidth, + memoryTransactionGenerationWidth))) val memoryClassify = Flipped(Decoupled(new STQMemoryClassifyToken( entries, robEntries, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, @@ -70,20 +73,36 @@ class STQSCBCommitBackendIO( val dcacheReady = Input(Bool()) val dcacheWriteHit = Input(Bool()) val dcacheTagHit = Input(Bool()) + val dcacheLookupValid = Output(Bool()) + val dcacheLookupLineAddr = Output(UInt(addrWidth.W)) + val dcacheUpdate = Output(new SCBDCacheUpdate( + scbEntries, addrWidth, lineBytes)) val l2RequestReady = Input(Bool()) + val l2Request = Output(new SCBL2OwnershipRequest( + scbEntries, addrWidth, lineBytes, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) val rawRespValid = Input(Bool()) val rawRespTxnId = Input(UInt(scbResponseTxnIdWidth.W)) + val rawRespTransactionValue = Input(UInt(memoryTransactionIdWidth.W)) + val rawRespTransactionGeneration = + Input(UInt(memoryTransactionGenerationWidth.W)) + val rawRespError = Input(Bool()) val rawRespWrite = Input(Bool()) val rawRespUpgrade = Input(Bool()) val rawRespReady = Output(Bool()) + val rawRespAccepted = Output(Bool()) + val rawRespSucceeded = Output(Bool()) + val rawRespLineAddr = Output(UInt(addrWidth.W)) val serializedRequest = Decoupled(new STQSerializedStoreRequest( entries, robEntries, addrWidth, dataWidth, sizeWidth, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, residentGenerationWidth, - leaseGenerationWidth)) + leaseGenerationWidth, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) val serializedResponse = Flipped(Decoupled( - new STQSerializedStoreResponse())) + new STQSerializedStoreResponse( + memoryTransactionIdWidth, memoryTransactionGenerationWidth))) val robStoreCommitAccepted = Output(Bool()) val robStoreCommitMissing = Output(Bool()) @@ -104,6 +123,8 @@ class STQSCBCommitBackendIO( val drainIssueCount = Output(UInt(issueCountWidth.W)) val scbAcceptedMask = Output(UInt(requestCount.W)) val scbValidMask = Output(UInt(scbEntries.W)) + val scbRows = Output(Vec(scbEntries, + new SCBLineEntry(addrWidth, lineBytes))) val logicalCompletions = Output(Vec(issueWidth, new STQCommitLogicalCompletion( robEntries, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, @@ -137,7 +158,9 @@ class STQSCBCommitBackend( val brobGenerationWidth: Int = 8, val memberIndexWidth: Int = 8, val residentGenerationWidth: Int = 8, - val leaseGenerationWidth: Int = 8) + val leaseGenerationWidth: Int = 8, + val memoryTransactionIdWidth: Int = 8, + val memoryTransactionGenerationWidth: Int = 8) extends Module { require(entries > 1 && (entries & (entries - 1)) == 0, "commit backend requires a power-of-two STQ") @@ -154,7 +177,8 @@ class STQSCBCommitBackend( addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, lineBytes, mapQDepth, robEntries, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, - memberIndexWidth, residentGenerationWidth, leaseGenerationWidth)) + memberIndexWidth, residentGenerationWidth, leaseGenerationWidth, + memoryTransactionIdWidth, memoryTransactionGenerationWidth)) val memoryAttributes = Module(new STQMemoryAttributeOwner( entries, robEntries, addrWidth, dataWidth, peIdWidth, stidWidth, @@ -175,7 +199,13 @@ class STQSCBCommitBackend( entries, robEntries, addrWidth, dataWidth, peIdWidth, stidWidth, tidWidth, sizeWidth, simtLaneWidth, mapQDepth, lsidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, - memberIndexWidth, residentGenerationWidth, leaseGenerationWidth)) + memberIndexWidth, residentGenerationWidth, leaseGenerationWidth, + memoryTransactionIdWidth, memoryTransactionGenerationWidth)) + val committedTransactionValid = RegInit(VecInit(Seq.fill(entries)(false.B))) + val committedTransactionValue = Reg(Vec(entries, + UInt(memoryTransactionIdWidth.W))) + val committedTransactionGeneration = Reg(Vec(entries, + UInt(memoryTransactionGenerationWidth.W))) ingress.io.commit <> io.robStoreCommit ingress.io.rows := io.rows ingress.io.memoryAttributes := memoryAttributes.io.attributes @@ -196,10 +226,12 @@ class STQSCBCommitBackend( entries, robEntries, issueWidth, addrWidth, dataWidth, sizeWidth, lsidWidth, peIdWidth, stidWidth, nativeBidWidth, ridGenerationWidth, brobGenerationWidth, memberIndexWidth, residentGenerationWidth, - leaseGenerationWidth)) + leaseGenerationWidth, memoryTransactionIdWidth, + memoryTransactionGenerationWidth)) val scb = Module(new SCBRowBank( entries, scbEntries, requestCount, scbResponseBufferDepth, addrWidth, - dataWidth, sizeWidth, lineBytes, robEntries, lsidWidth)) + dataWidth, sizeWidth, lineBytes, robEntries, lsidWidth, + memoryTransactionIdWidth, memoryTransactionGenerationWidth)) val terminalFreeValid = scb.io.commitFreeMaskValid || serializer.io.freeMask.valid @@ -246,14 +278,69 @@ class STQSCBCommitBackend( scb.io.dcacheWriteHit := io.dcacheWriteHit scb.io.dcacheTagHit := io.dcacheTagHit scb.io.l2RequestReady := io.l2RequestReady + io.l2Request := scb.io.l2Request + io.dcacheLookupValid := scb.io.lookupRequest.valid + io.dcacheLookupLineAddr := scb.io.lookupRequest.lineAddr + io.dcacheUpdate := scb.io.dcacheUpdate scb.io.rawRespValid := io.rawRespValid scb.io.rawRespTxnId := io.rawRespTxnId + scb.io.rawRespTransactionValue := io.rawRespTransactionValue + scb.io.rawRespTransactionGeneration := io.rawRespTransactionGeneration + scb.io.rawRespError := io.rawRespError scb.io.rawRespWrite := io.rawRespWrite scb.io.rawRespUpgrade := io.rawRespUpgrade io.rawRespReady := scb.io.rawRespReady + io.rawRespAccepted := scb.io.rawRespAccepted + io.rawRespSucceeded := scb.io.rawRespSucceeded + io.rawRespLineAddr := scb.io.rawRespLineAddr - io.serializedRequest <> serializer.io.request - serializer.io.response <> io.serializedResponse + val serializedRequestIndex = serializer.io.request.bits.issue.stqIndex + val serializedRequestTransactionValid = + committedTransactionValid(serializedRequestIndex) + io.serializedRequest.valid := serializer.io.request.valid && + serializedRequestTransactionValid + io.serializedRequest.bits := serializer.io.request.bits + io.serializedRequest.bits.transactionId := + committedTransactionValue(serializedRequestIndex) + io.serializedRequest.bits.transactionGeneration := + committedTransactionGeneration(serializedRequestIndex) + serializer.io.request.ready := io.serializedRequest.ready && + serializedRequestTransactionValid + + val serializedExternalOutstanding = RegInit(false.B) + val serializedExternalTransactionId = Reg(UInt(memoryTransactionIdWidth.W)) + val serializedExternalTransactionGeneration = + Reg(UInt(memoryTransactionGenerationWidth.W)) + val serializedInternalTransactionId = Reg(UInt(memoryTransactionIdWidth.W)) + val serializedInternalTransactionGeneration = + Reg(UInt(memoryTransactionGenerationWidth.W)) + when(io.serializedRequest.fire) { + serializedExternalOutstanding := true.B + serializedExternalTransactionId := io.serializedRequest.bits.transactionId + serializedExternalTransactionGeneration := + io.serializedRequest.bits.transactionGeneration + serializedInternalTransactionId := serializer.io.request.bits.transactionId + serializedInternalTransactionGeneration := + serializer.io.request.bits.transactionGeneration + } + val serializedExternalResponseExact = serializedExternalOutstanding && + io.serializedResponse.bits.transactionId === + serializedExternalTransactionId && + io.serializedResponse.bits.transactionGeneration === + serializedExternalTransactionGeneration + serializer.io.response.valid := io.serializedResponse.valid && + serializedExternalResponseExact + serializer.io.response.bits := io.serializedResponse.bits + serializer.io.response.bits.transactionId := serializedInternalTransactionId + serializer.io.response.bits.transactionGeneration := + serializedInternalTransactionGeneration + io.serializedResponse.ready := serializer.io.response.ready && + serializedExternalResponseExact + when(serializer.io.response.fire) { + serializedExternalOutstanding := false.B + } + val serializedExternalStaleResponse = io.serializedResponse.valid && + !serializedExternalResponseExact io.commitFreeMaskValid := pendingFreeValid || terminalFreeValid io.commitFreeMask := Mux(pendingFreeValid, pendingFreeMask, @@ -261,6 +348,19 @@ class STQSCBCommitBackend( val offeredFreeAccepted = io.commitFreeMaskValid && (io.commitFreeAcceptedMask & io.commitFreeMask) === io.commitFreeMask + for (index <- 0 until entries) { + when(io.commitFreeAcceptedMask(index)) { + committedTransactionValid(index) := false.B + } + } + when(io.robStoreCommit.fire) { + committedTransactionValid(ingress.io.markIndex) := true.B + committedTransactionValue(ingress.io.markIndex) := + io.robStoreCommit.bits.transactionValue + committedTransactionGeneration(ingress.io.markIndex) := + io.robStoreCommit.bits.transactionGeneration + } + when(pendingFreeValid) { when(offeredFreeAccepted) { pendingFreeValid := false.B @@ -289,6 +389,7 @@ class STQSCBCommitBackend( io.drainIssueCount := drain.io.issueCount io.scbAcceptedMask := scb.io.acceptedMask io.scbValidMask := scb.io.validMask + io.scbRows := scb.io.entries io.logicalCompletions := drain.io.logicalCompletions when(serializer.io.logicalCompletion.valid) { io.logicalCompletions(0) := serializer.io.logicalCompletion.bits @@ -298,14 +399,24 @@ class STQSCBCommitBackend( io.serializedBusy := serializer.io.busy io.protocolError := drain.io.orderError || drain.io.queuedIdentityError || drain.io.retainedIdentityError || serializer.io.batchMalformed || - serializer.io.staleResponse || serializer.io.terminalError || - scb.io.stateError || scb.io.respDecodeError - io.empty := drain.io.empty && !serializer.io.busy && !pendingFreeValid + serializer.io.staleResponse || serializedExternalStaleResponse || + serializer.io.terminalError || + scb.io.stateError || scb.io.respDecodeError || scb.io.protocolError + io.empty := drain.io.empty && !serializer.io.busy && !pendingFreeValid && + scb.io.quiescent when(io.robStoreCommit.fire) { assert(io.markCommitAccepted && drain.io.enqueueAccepted, "ROB store commit must atomically mark the canonical STQ and enqueue CommitQ") } + when(serializer.io.request.valid) { + assert(serializedRequestTransactionValid, + "serialized committed store must retain its architectural transaction") + } + when(io.serializedRequest.fire) { + assert(!serializedExternalOutstanding, + "serialized transport supports only one external request at a time") + } when(io.markCommitAccepted) { assert(drain.io.enqueueAccepted, "canonical STQ WAIT-to-COMMIT must have the matching CommitQ token") diff --git a/chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala b/chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala index e58a7ef9..84f10d38 100644 --- a/chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala +++ b/chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala @@ -450,6 +450,7 @@ class STQSCBCommitPath( scb.io.l2RequestReady := io.l2RequestReady scb.io.rawRespValid := io.rawRespValid scb.io.rawRespTxnId := io.rawRespTxnId + scb.io.rawRespError := false.B scb.io.rawRespWrite := io.rawRespWrite scb.io.rawRespUpgrade := io.rawRespUpgrade diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala b/chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala index e1ef3e23..e46337ff 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala @@ -45,6 +45,7 @@ class ScalarL1DIO( val storeLookup = Output(new ScalarL1DLookupResult(addrWidth, lineBytes, ways)) val grantWriteValid = Input(Bool()) val grantWriteLineAddr = Input(UInt(addrWidth.W)) + val grantWriteData = Input(UInt((lineBytes * 8).W)) val storeUpdate = Input(new SCBDCacheUpdate(scbEntries, addrWidth, lineBytes)) val refill = Input(new ScalarL1DRefill(addrWidth, lineBytes)) @@ -55,6 +56,10 @@ class ScalarL1DIO( val eviction = Output(new ScalarL1DEviction(addrWidth, lineBytes)) val evictionReady = Input(Bool()) + val invalidateAll = Input(Bool()) + val invalidateLineValid = Input(Bool()) + val invalidateLineAddr = Input(UInt(addrWidth.W)) + val arrayReady = Output(Bool()) val residentCount = Output(UInt(residentWidth.W)) val dirtyCount = Output(UInt(residentWidth.W)) @@ -124,6 +129,15 @@ class ScalarL1D( valid(refillSet)(way) && tags(refillSet)(way) === aligned(io.refill.lineAddr))) val refillDuplicate = refillHits.asUInt.orR val refillHitWay = PriorityEncoder(refillHits) + val invalidateLineSet = setIndex(io.invalidateLineAddr) + val invalidateLineHits = VecInit((0 until ways).map(way => + valid(invalidateLineSet)(way) && + tags(invalidateLineSet)(way) === aligned(io.invalidateLineAddr))) + val invalidateLineDirty = VecInit((0 until ways).map(way => + invalidateLineHits(way) && dirty(invalidateLineSet)(way))).asUInt.orR + val anyDirty = VecInit((0 until sets).flatMap(set => + (0 until ways).map(way => valid(set)(way) && dirty(set)(way)))).asUInt.orR + val maintenanceActive = io.invalidateAll || io.invalidateLineValid val invalidWays = VecInit((0 until ways).map(way => !valid(refillSet)(way))) val hasInvalid = invalidWays.asUInt.orR val invalidWay = PriorityEncoder(invalidWays) @@ -131,10 +145,11 @@ class ScalarL1D( val oldestWay = PriorityEncoder(oldestWays) val victimWay = Mux(hasInvalid, invalidWay, oldestWay) val replacementNeedsEviction = !refillDuplicate && !hasInvalid && valid(refillSet)(victimWay) - val refillReady = refillDuplicate || !replacementNeedsEviction || io.evictionReady + val refillReady = !maintenanceActive && + (refillDuplicate || !replacementNeedsEviction || io.evictionReady) val refillAccepted = io.refill.valid && refillReady - io.eviction.valid := io.refill.valid && replacementNeedsEviction + io.eviction.valid := io.refill.valid && replacementNeedsEviction && !maintenanceActive io.eviction.lineAddr := tags(refillSet)(victimWay) io.eviction.data := data(refillSet)(victimWay) io.eviction.dirty := dirty(refillSet)(victimWay) @@ -142,25 +157,54 @@ class ScalarL1D( io.refillAccepted := refillAccepted io.refillDuplicate := io.refill.valid && refillDuplicate io.refillData := Mux(refillDuplicate, data(refillSet)(refillHitWay), io.refill.data) - io.arrayReady := !io.refill.valid + io.arrayReady := !io.refill.valid && !maintenanceActive val storeUpdateSet = setIndex(io.storeUpdate.lineAddr) val storeUpdateHits = VecInit((0 until ways).map(way => valid(storeUpdateSet)(way) && tags(storeUpdateSet)(way) === aligned(io.storeUpdate.lineAddr))) val storeUpdateWay = PriorityEncoder(storeUpdateHits) val storeUpdateLegal = io.storeUpdate.valid && storeUpdateHits.asUInt.orR && - writable(storeUpdateSet)(storeUpdateWay) && io.storeUpdate.byteMask.orR && !io.refill.valid + writable(storeUpdateSet)(storeUpdateWay) && io.storeUpdate.byteMask.orR && + !io.refill.valid && !maintenanceActive val grantWriteSet = setIndex(io.grantWriteLineAddr) val grantWriteHits = VecInit((0 until ways).map(way => valid(grantWriteSet)(way) && tags(grantWriteSet)(way) === aligned(io.grantWriteLineAddr))) - val grantWriteWay = PriorityEncoder(grantWriteHits) - val grantWriteLegal = io.grantWriteValid && grantWriteHits.asUInt.orR && !io.refill.valid + val grantWriteHit = grantWriteHits.asUInt.orR + val grantWriteHitWay = PriorityEncoder(grantWriteHits) + val grantInvalidWays = VecInit((0 until ways).map(way => + !valid(grantWriteSet)(way))) + val grantHasInvalid = grantInvalidWays.asUInt.orR + val grantInvalidWay = PriorityEncoder(grantInvalidWays) + val grantOldestWays = VecInit((0 until ways).map(way => + age(grantWriteSet)(way) === (ways - 1).U)) + val grantOldestWay = PriorityEncoder(grantOldestWays) + val grantAllocateWay = Mux(grantHasInvalid, grantInvalidWay, grantOldestWay) + val grantCanAllocate = grantHasInvalid || + !dirty(grantWriteSet)(grantOldestWay) + val grantWriteWay = Mux(grantWriteHit, grantWriteHitWay, grantAllocateWay) + val grantWriteLegal = io.grantWriteValid && + (grantWriteHit || grantCanAllocate) && + !io.refill.valid && !maintenanceActive val touchValid = WireDefault(false.B) val touchNewLine = WireDefault(false.B) val touchSet = WireDefault(0.U(setWidth.W)) val touchWay = WireDefault(0.U(wayWidth.W)) - when(refillAccepted) { + when(io.invalidateAll && !anyDirty) { + for (set <- 0 until sets; way <- 0 until ways) { + valid(set)(way) := false.B + writable(set)(way) := false.B + dirty(set)(way) := false.B + } + }.elsewhen(io.invalidateLineValid && !invalidateLineDirty) { + for (way <- 0 until ways) { + when(invalidateLineHits(way)) { + valid(invalidateLineSet)(way) := false.B + writable(invalidateLineSet)(way) := false.B + dirty(invalidateLineSet)(way) := false.B + } + } + }.elsewhen(refillAccepted) { touchValid := true.B touchNewLine := !refillDuplicate touchSet := refillSet @@ -171,6 +215,7 @@ class ScalarL1D( touchWay := storeUpdateWay }.elsewhen(grantWriteLegal) { touchValid := true.B + touchNewLine := !grantWriteHit touchSet := grantWriteSet touchWay := grantWriteWay }.elsewhen(io.storeLookupValid && storeResult.tagHit) { @@ -209,6 +254,12 @@ class ScalarL1D( } when(grantWriteLegal) { + when(!grantWriteHit) { + valid(grantWriteSet)(grantWriteWay) := true.B + dirty(grantWriteSet)(grantWriteWay) := false.B + tags(grantWriteSet)(grantWriteWay) := aligned(io.grantWriteLineAddr) + data(grantWriteSet)(grantWriteWay) := io.grantWriteData + } writable(grantWriteSet)(grantWriteWay) := true.B } @@ -233,7 +284,10 @@ class ScalarL1D( io.protocolError := (io.storeUpdate.valid && !storeUpdateLegal) || (io.grantWriteValid && !grantWriteLegal) || + (io.invalidateAll && anyDirty) || + (io.invalidateLineValid && invalidateLineDirty) || PopCount(refillHits) > 1.U || + PopCount(invalidateLineHits) > 1.U || PopCount(grantWriteHits) > 1.U || PopCount(storeUpdateHits) > 1.U || (io.loadLookupValid && PopCount(VecInit((0 until ways).map(way => diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarL1DProbe.scala b/chisel/src/main/scala/linxcore/lsu/ScalarL1DProbe.scala deleted file mode 100644 index 5314e73f..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ScalarL1DProbe.scala +++ /dev/null @@ -1,90 +0,0 @@ -package linxcore.lsu - -import chisel3._ -import chisel3.util.Fill -import circt.stage.ChiselStage - -class ScalarL1DProbeIO extends Bundle { - val hardFlush = Input(Bool()) - val preciseFlush = Input(Bool()) - val loadValid = Input(Bool()) - val loadLineAddr = Input(UInt(64.W)) - val loadHit = Output(Bool()) - val loadData = Output(UInt(64.W)) - val refillValid = Input(Bool()) - val refillLineAddr = Input(UInt(64.W)) - val refillData = Input(UInt(64.W)) - val refillWritable = Input(Bool()) - val refillReady = Output(Bool()) - val refillAccepted = Output(Bool()) - val refillDuplicate = Output(Bool()) - val refillReturnData = Output(UInt(64.W)) - val evictionReady = Input(Bool()) - val evictionValid = Output(Bool()) - val evictionLineAddr = Output(UInt(64.W)) - val evictionData = Output(UInt(64.W)) - val evictionDirty = Output(Bool()) - val storeLookupValid = Input(Bool()) - val storeLineAddr = Input(UInt(64.W)) - val storeTagHit = Output(Bool()) - val storeWriteHit = Output(Bool()) - val grantWriteValid = Input(Bool()) - val storeUpdateValid = Input(Bool()) - val storeByteMask = Input(UInt(64.W)) - val storeData = Input(UInt(512.W)) - val arrayReady = Output(Bool()) - val residentCount = Output(UInt(3.W)) - val dirtyCount = Output(UInt(3.W)) - val protocolError = Output(Bool()) -} - -class ScalarL1DProbe extends Module { - val io = IO(new ScalarL1DProbeIO) - val cache = Module(new ScalarL1D(sets = 2, ways = 2, scbEntries = 4)) - - cache.io.loadLookupValid := io.loadValid - cache.io.loadLookupLineAddr := io.loadLineAddr - cache.io.storeLookupValid := io.storeLookupValid - cache.io.storeLookupLineAddr := io.storeLineAddr - cache.io.grantWriteValid := io.grantWriteValid - cache.io.grantWriteLineAddr := io.storeLineAddr - cache.io.storeUpdate := 0.U.asTypeOf(cache.io.storeUpdate) - cache.io.storeUpdate.valid := io.storeUpdateValid - cache.io.storeUpdate.lineAddr := io.storeLineAddr - cache.io.storeUpdate.byteMask := io.storeByteMask - cache.io.storeUpdate.data := io.storeData - cache.io.refill.valid := io.refillValid - cache.io.refill.lineAddr := io.refillLineAddr - cache.io.refill.data := Fill(8, io.refillData) - cache.io.refill.writable := io.refillWritable - cache.io.evictionReady := io.evictionReady - - // Cache state is physical and intentionally has no Linx recovery input. - dontTouch(io.hardFlush) - dontTouch(io.preciseFlush) - - io.loadHit := cache.io.loadLookup.readHit - io.loadData := cache.io.loadLookup.data(63, 0) - io.refillReady := cache.io.refillReady - io.refillAccepted := cache.io.refillAccepted - io.refillDuplicate := cache.io.refillDuplicate - io.refillReturnData := cache.io.refillData(63, 0) - io.evictionValid := cache.io.eviction.valid - io.evictionLineAddr := cache.io.eviction.lineAddr - io.evictionData := cache.io.eviction.data(63, 0) - io.evictionDirty := cache.io.eviction.dirty - io.storeTagHit := cache.io.storeLookup.tagHit - io.storeWriteHit := cache.io.storeLookup.writeHit - io.arrayReady := cache.io.arrayReady - io.residentCount := cache.io.residentCount - io.dirtyCount := cache.io.dirtyCount - io.protocolError := cache.io.protocolError -} - -object EmitScalarL1DProbe extends App { - ChiselStage.emitSystemVerilogFile( - new ScalarL1DProbe, - args, - firtoolOpts = Array("--disable-all-randomization", "--strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala b/chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala index 47357ee1..63a38717 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala @@ -66,6 +66,7 @@ class ScalarL1DScbProbe extends Module { scb.io.l2RequestReady := io.l2Ready scb.io.rawRespValid := io.rawRespValid scb.io.rawRespTxnId := io.rawRespTxnId + scb.io.rawRespError := false.B scb.io.rawRespWrite := false.B scb.io.rawRespUpgrade := io.rawRespUpgrade @@ -76,11 +77,15 @@ class ScalarL1DScbProbe extends Module { cache.io.storeUpdate := scb.io.dcacheUpdate cache.io.grantWriteValid := scb.io.respDecodedUpgrade cache.io.grantWriteLineAddr := scb.io.entries(scb.io.respDecodedEntryIndex).lineAddr + cache.io.grantWriteData := 0.U cache.io.refill.valid := io.refillValid cache.io.refill.lineAddr := io.refillLineAddr cache.io.refill.data := Fill(8, io.refillData) cache.io.refill.writable := io.refillWritable cache.io.evictionReady := io.evictionReady + cache.io.invalidateAll := false.B + cache.io.invalidateLineValid := false.B + cache.io.invalidateLineAddr := 0.U io.requestAccepted := scb.io.acceptedMask(0) io.l2Valid := scb.io.l2Request.valid diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala deleted file mode 100644 index f473bda3..00000000 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala +++ /dev/null @@ -1,188 +0,0 @@ -package linxcore.lsu - -import chisel3._ - -import linxcore.bctrl.BID -import linxcore.common.{CoreParams, ScalarLsuParams} -import linxcore.recovery.FullBidFlushReq -import linxcore.rob.{ROBFullBidLookupRequest, ROBFullBidLookupResult, ROBID} - -class ScalarLSURecoverySourcePortIO(val coreParams: CoreParams, val p: ScalarLsuParams) extends Bundle { - val source = Output(new FullBidFlushReq( - coreParams.robEntries, - BID.DefaultWidth, - p.peIdWidth, - p.stidWidth, - p.tidWidth, - coreParams.lsidWidth - )) - val sourceReady = Input(Bool()) - val oldestValid = Input(Vec(p.stidCount, Bool())) - val oldestBid = Input(Vec(p.stidCount, new ROBID(coreParams.robEntries))) - val oldestRid = Input(Vec(p.stidCount, new ROBID(coreParams.robEntries))) - val fullBidLookupRequest = Output(new ROBFullBidLookupRequest( - coreParams.robEntries, - p.peIdWidth, - p.stidWidth, - p.tidWidth - )) - val fullBidLookup = Input(new ROBFullBidLookupResult( - coreParams.robEntries, - BID.DefaultWidth, - p.peIdWidth, - p.stidWidth, - p.tidWidth - )) - val sourcePending = Output(Bool()) - val sourceEligible = Output(Bool()) - val sourceAccepted = Output(Bool()) - val sourceBlockedByNoOldest = Output(Bool()) - val sourceBlockedByAge = Output(Bool()) - val sourceLookupMatched = Output(Bool()) - val sourceBlockedByLookupMiss = Output(Bool()) - val sourceBlockedByStaleLookup = Output(Bool()) - val sourceBlockedByRingProjection = Output(Bool()) - val sourceStidInRange = Output(Bool()) -} - -class ScalarLSUIO(val coreParams: CoreParams, val lsuParams: ScalarLsuParams) extends Bundle { - val store = ScalarLSU.storePathIO(coreParams, lsuParams) - val load = new ScalarLSULoadPathIO(coreParams, lsuParams) - val recovery = new ScalarLSURecoverySourcePortIO(coreParams, lsuParams) -} - -class ScalarLSU(val coreParams: CoreParams = CoreParams()) extends Module { - private val lsuParams = coreParams.scalarLsu - val io = IO(new ScalarLSUIO(coreParams, lsuParams)) - - val storeCommitPath = Module(ScalarLSU.storeCommitPath(coreParams, lsuParams)) - val loadPath = Module(new ScalarLSULoadPath(coreParams)) - val recoveryBoundary = Module(new ScalarLSURecoveryBoundary( - coreParams.robEntries, - lsuParams.stidCount, - BID.DefaultWidth, - lsuParams.peIdWidth, - lsuParams.stidWidth, - lsuParams.tidWidth, - coreParams.lsidWidth - )) - storeCommitPath.io <> io.store - loadPath.io <> io.load - - loadPath.scbCache.lookupValid := storeCommitPath.io.scbLookupRequest.valid - loadPath.scbCache.lookupLineAddr := storeCommitPath.io.scbLookupRequest.lineAddr - loadPath.scbCache.update := storeCommitPath.io.scbDCacheUpdate - loadPath.scbCache.grantWriteValid := storeCommitPath.io.scbRespDecodedUpgrade - loadPath.scbCache.grantWriteLineAddr := - storeCommitPath.io.scbEntriesState(storeCommitPath.io.scbRespDecodedEntryIndex).lineAddr - storeCommitPath.io.dcacheReady := loadPath.scbCache.ready - storeCommitPath.io.dcacheTagHit := loadPath.scbCache.tagHit - storeCommitPath.io.dcacheWriteHit := loadPath.scbCache.writeHit - - val pendingRingReq = Wire(chiselTypeOf(loadPath.recovery.flush)) - pendingRingReq := loadPath.recovery.flush - pendingRingReq.req.valid := loadPath.recovery.valid - recoveryBoundary.io.ringReq := pendingRingReq - recoveryBoundary.io.oldestValid := io.recovery.oldestValid - recoveryBoundary.io.oldestBid := io.recovery.oldestBid - recoveryBoundary.io.oldestRid := io.recovery.oldestRid - recoveryBoundary.io.fullBidLookup := io.recovery.fullBidLookup - recoveryBoundary.io.sourceReady := io.recovery.sourceReady - loadPath.recovery.ready := recoveryBoundary.io.ringReqReady - - io.recovery.source := recoveryBoundary.io.source - io.recovery.fullBidLookupRequest := recoveryBoundary.io.fullBidLookupRequest - io.recovery.sourcePending := loadPath.recovery.pending - io.recovery.sourceEligible := recoveryBoundary.io.eligible - io.recovery.sourceAccepted := recoveryBoundary.io.sourceAccepted - io.recovery.sourceBlockedByNoOldest := recoveryBoundary.io.blockedByNoOldest - io.recovery.sourceBlockedByAge := recoveryBoundary.io.blockedByAge - io.recovery.sourceLookupMatched := recoveryBoundary.io.lookupMatched - io.recovery.sourceBlockedByLookupMiss := recoveryBoundary.io.blockedByLookupMiss - io.recovery.sourceBlockedByStaleLookup := recoveryBoundary.io.blockedByStaleLookup - io.recovery.sourceBlockedByRingProjection := recoveryBoundary.io.blockedByRingProjection - io.recovery.sourceStidInRange := recoveryBoundary.io.stidInRange - - val storeCarriesAddress = io.store.insert.storeType =/= STQStoreType.Data - val storeMdbPermit = !storeCarriesAddress || loadPath.mdbStore.probeReady - storeCommitPath.io.insertValid := io.store.insertValid && storeMdbPermit - io.store.insertReady := storeCommitPath.io.insertReady && storeMdbPermit - - val storeProbe = Wire(chiselTypeOf(loadPath.mdbStore.probe)) - storeProbe := 0.U.asTypeOf(storeProbe) - storeProbe.valid := io.store.insertValid && storeCarriesAddress - storeProbe.addrOnly := io.store.insert.storeType === STQStoreType.Addr - storeProbe.isTile := !io.store.insert.scalarIex - storeProbe.peId := io.store.insert.peId - storeProbe.stid := io.store.insert.stid - storeProbe.tid := io.store.insert.tid - storeProbe.bid := io.store.insert.bid - storeProbe.gid := io.store.insert.gid - storeProbe.rid := io.store.insert.rid - storeProbe.lsId := io.store.insert.lsId - storeProbe.pc := io.store.insert.pc - storeProbe.addr := io.store.insert.addr - storeProbe.size := io.store.insert.size.pad(lsuParams.loadSizeWidth) - loadPath.mdbStore.probe := storeProbe - loadPath.mdbStore.probeCommit := storeCommitPath.io.insertAccepted && storeCarriesAddress - - for (idx <- 0 until lsuParams.stqEntries) { - val row = storeCommitPath.io.stqRows(idx) - val mdbRow = Wire(chiselTypeOf(loadPath.mdbStore.rows(idx))) - mdbRow := 0.U.asTypeOf(mdbRow) - mdbRow.valid := row.valid - mdbRow.storeIndex := idx.U - mdbRow.pc := row.pc - mdbRow.bid := row.bid - mdbRow.lsId := row.lsId - mdbRow.stid := row.stid - mdbRow.addr := row.addr - mdbRow.size := row.size.pad(lsuParams.loadSizeWidth) - mdbRow.addrReady := row.addrReady - mdbRow.dataReady := row.dataReady - mdbRow.isTile := !row.scalarIex - loadPath.mdbStore.rows(idx) := mdbRow - } -} - -object ScalarLSU { - def storePathIO(coreParams: CoreParams, lsuParams: ScalarLsuParams): STQSCBCommitPathIO = - new STQSCBCommitPathIO( - entries = lsuParams.stqEntries, - queueEntries = lsuParams.commitQueueEntries, - issueWidth = lsuParams.commitIssueWidth, - scbEntries = lsuParams.scbEntries, - scbResponseBufferDepth = lsuParams.scbResponseBufferDepth, - addrWidth = lsuParams.addrWidth, - dataWidth = lsuParams.dataWidth, - peIdWidth = lsuParams.peIdWidth, - stidWidth = lsuParams.stidWidth, - tidWidth = lsuParams.tidWidth, - sizeWidth = lsuParams.sizeWidth, - simtLaneWidth = lsuParams.simtLaneWidth, - lineBytes = lsuParams.lineBytes, - mapQDepth = lsuParams.mapQDepth, - robEntries = coreParams.robEntries, - lsidWidth = coreParams.lsidWidth - ) - - def storeCommitPath(coreParams: CoreParams, lsuParams: ScalarLsuParams): STQSCBCommitPath = - new STQSCBCommitPath( - entries = lsuParams.stqEntries, - queueEntries = lsuParams.commitQueueEntries, - issueWidth = lsuParams.commitIssueWidth, - scbEntries = lsuParams.scbEntries, - scbResponseBufferDepth = lsuParams.scbResponseBufferDepth, - addrWidth = lsuParams.addrWidth, - dataWidth = lsuParams.dataWidth, - peIdWidth = lsuParams.peIdWidth, - stidWidth = lsuParams.stidWidth, - tidWidth = lsuParams.tidWidth, - sizeWidth = lsuParams.sizeWidth, - simtLaneWidth = lsuParams.simtLaneWidth, - lineBytes = lsuParams.lineBytes, - mapQDepth = lsuParams.mapQDepth, - robEntries = coreParams.robEntries, - lsidWidth = coreParams.lsidWidth - ) -} diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala index 509ceaf7..bba64769 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala @@ -1,7 +1,7 @@ package linxcore.lsu import chisel3._ -import chisel3.util.{Cat, Fill, Mux1H, RRArbiter, UIntToOH, log2Ceil} +import chisel3.util.{Cat, Decoupled, Fill, Mux1H, PopCount, Queue, RRArbiter, UIntToOH, log2Ceil} import linxcore.common.{CoreParams, ScalarLsuParams} import linxcore.recovery.FlushBus @@ -95,11 +95,40 @@ class ScalarL1DStorePortIO(val p: ScalarLsuParams) extends Bundle { val lookupLineAddr = Input(UInt(p.addrWidth.W)) val grantWriteValid = Input(Bool()) val grantWriteLineAddr = Input(UInt(p.addrWidth.W)) + val grantWriteData = Input(UInt((p.lineBytes * 8).W)) val ready = Output(Bool()) val tagHit = Output(Bool()) val writeHit = Output(Bool()) } +class ScalarLSULoadForwardPortIO( + val coreParams: CoreParams, + val p: ScalarLsuParams, + val stqRobEntries: Int, + val tokenWidth: Int, + val resultDepth: Int) extends Bundle { + private val resultCountWidth = log2Ceil(resultDepth + 1) + private def queryType = new STQLoadForwardQuery( + stqRobEntries, p.addrWidth, p.stidWidth, p.lineBytes, + coreParams.lsidWidth, tokenWidth) + private def responseType = new STQLoadForwardResponse( + stqRobEntries, p.stqEntries, p.addrWidth, p.stidWidth, p.pcWidth, + p.lineBytes, coreParams.lsidWidth, tokenWidth) + + val scb = Input(new LoadSourceLine(p.lineBytes)) + val queries = Vec(p.loadReturnPipeCount, Decoupled(queryType)) + val responses = Flipped(Vec(p.loadReturnPipeCount, Decoupled(responseType))) + val hardBlock = Decoupled(responseType) + val queryAccepted = Output(Bool()) + val resultAccepted = Output(Bool()) + val resultRejectedPermanent = Output(Bool()) + val resultRetryRequired = Output(Bool()) + val resultCount = Output(UInt(resultCountWidth.W)) + val resultPending = Output(Bool()) + val ownedStateEmpty = Output(Bool()) + val protocolError = Output(Bool()) +} + class ScalarLSULoadPathIO(val coreParams: CoreParams, val lsuParams: ScalarLsuParams) extends Bundle { private val liqPtrWidth = log2Ceil(lsuParams.liqEntries) private val liqCountWidth = log2Ceil(lsuParams.liqEntries + 1) @@ -148,6 +177,20 @@ class ScalarLSULoadPathIO(val coreParams: CoreParams, val lsuParams: ScalarLsuPa val attemptRebindBlockedByStaleAttempt = Output(Bool()) val attemptRebindBlockedByNextAttempt = Output(Bool()) + val structuralRetryValid = Input(Bool()) + val structuralRetry = Input(new LoadStructuralBlockRetry( + coreParams.robEntries, lsuParams.stqEntries, lsuParams.pcWidth, + coreParams.lsidWidth)) + val structuralRetryReady = Output(Bool()) + val structuralRetryAccepted = Output(Bool()) + val structuralRetryBlockedByLoadId = Output(Bool()) + val structuralRetryBlockedByAttempt = Output(Bool()) + val structuralRetryBlockedByNextAttempt = Output(Bool()) + val structuralRetryBlockedByPipe = Output(Bool()) + val structuralRetryBlockedByLifecycle = Output(Bool()) + val structuralRetryBlockedByWaitStore = Output(Bool()) + val structuralRetryBlockedByMutation = Output(Bool()) + val launchValid = Input(Bool()) val launchIndex = Input(UInt(liqPtrWidth.W)) val launchReady = Output(Bool()) @@ -184,6 +227,10 @@ class ScalarLSULoadPathIO(val coreParams: CoreParams, val lsuParams: ScalarLsuPa val l1dEviction = Output(new ScalarL1DEviction(lsuParams.addrWidth, lsuParams.lineBytes)) val l1dEvictionReady = Input(Bool()) + val l1dInvalidateAll = Input(Bool()) + val l1dInvalidateLineValid = Input(Bool()) + val l1dInvalidateLineAddress = Input(UInt(lsuParams.addrWidth.W)) + val l1dMaintenanceError = Output(Bool()) val l1dLoadLookupHit = Output(Bool()) val l1dRefillAccepted = Output(Bool()) val l1dRefillDuplicate = Output(Bool()) @@ -350,6 +397,7 @@ class ScalarLSULoadPathIO(val coreParams: CoreParams, val lsuParams: ScalarLsuPa val mdbReplayWakeCollision = Output(Bool()) val mdbTransientEmpty = Output(Bool()) val mdbProtocolError = Output(Bool()) + val transientEmpty = Output(Bool()) val empty = Output(Bool()) } @@ -393,18 +441,41 @@ class ScalarLSULoadPathStoreIO(val coreParams: CoreParams, val p: ScalarLsuParam )) } -class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Module { +class ScalarLSULoadPath( + val coreParams: CoreParams = CoreParams(), + val useExternalStqForwarding: Boolean = false, + val stqForwardRobEntries: Int = 128, + val stqForwardTokenWidth: Int = 64, + val useExternalLaunchPermit: Boolean = false) extends Module { private val p = coreParams.scalarLsu + private val forwardResultDepth = p.loadReturnPipeCount + 2 require(p.resolveQueueEntries >= 4, "resolveQueueEntries must reserve two pipeline arrivals plus one resident row") require(p.liqEntries <= coreParams.robEntries, "liqEntries must fit the ROB identity domain used by replay diagnostics") require(p.lineBytes == 64, "canonical scalar load path currently requires 64-byte cache lines") + if (useExternalStqForwarding) { + require(stqForwardRobEntries > 1 && + (stqForwardRobEntries & (stqForwardRobEntries - 1)) == 0, + "STQ forwarding ROB projection must be a power of two") + require(stqForwardRobEntries <= coreParams.robEntries, + "STQ forwarding identities must widen losslessly into canonical LSU rows") + require(log2Ceil(stqForwardRobEntries) <= LoadAttemptIdentity.IndexWidth, + "STQ forwarding BID projection must fit the producer identity") + require(stqForwardTokenWidth >= LoadAttemptIdentity.GenerationWidth, + "STQ forwarding token must carry the complete attempt generation") + } val io = IO(new ScalarLSULoadPathIO(coreParams, p)) + val launchPermit = if (useExternalLaunchPermit) + Some(IO(Input(Bool()))) else None val scbCache = IO(new ScalarL1DStorePortIO(p)) val mdbStore = IO(new ScalarLSULoadPathStoreIO(coreParams, p)) val recovery = IO(new ScalarLSULoadPathRecoveryIO(coreParams, p)) + val stqForward = if (useExternalStqForwarding) Some(IO( + new ScalarLSULoadForwardPortIO( + coreParams, p, stqForwardRobEntries, stqForwardTokenWidth, + forwardResultDepth))) else None val liq = Module(new LoadInflightQueue( liqEntries = p.liqEntries, @@ -420,7 +491,8 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul stidWidth = p.stidWidth, tidWidth = p.tidWidth, returnPipeCount = p.loadReturnPipeCount, - lsidWidth = coreParams.lsidWidth + lsidWidth = coreParams.lsidWidth, + useExternalForwardResult = useExternalStqForwarding )) val missQueue = Module(new LoadMissQueue( missEntries = p.loadMissQueueEntries, @@ -505,6 +577,16 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul coreParams.robEntries, p, coreParams.lsidWidth)) val flushCycle = io.flush || io.preciseFlush.req.valid + val forwardQueryQueues = if (useExternalStqForwarding) Some( + Seq.fill(p.loadReturnPipeCount) { + withReset(reset.asBool || io.flush) { + Module(new Queue(new STQLoadForwardQuery( + stqForwardRobEntries, p.addrWidth, p.stidWidth, p.lineBytes, + coreParams.lsidWidth, stqForwardTokenWidth), + entries = 1, pipe = true, flow = false)) + } + }) else None + val forwardTransportEmpty = WireDefault(true.B) private val returnLaneCount = p.stidCount * p.loadReturnPipeCount private val returnLaneWidth = math.max(1, log2Ceil(returnLaneCount)) private val reservationWidth = log2Ceil(p.loadReturnQueueEntries + 1) @@ -523,14 +605,35 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul val allocMdbReady = !allocNeedsMdbLookup || mdbPath.io.loadLookupReady liq.io.allocValid := io.allocValid && allocMdbReady liq.io.alloc := io.alloc - liq.io.attemptRebindValid := io.attemptRebindValid liq.io.attemptRebind := io.attemptRebind + val rebindRow = liq.io.rows(io.attemptRebind.loadId.value) + val rebindNeedsMissCancel = rebindRow.valid && + (rebindRow.status === LoadInflightStatus.L1DcMiss || + rebindRow.status === LoadInflightStatus.L2Wait) + missQueue.io.cancelLoadId := io.attemptRebind.loadId + missQueue.io.cancelAttempt := io.attemptRebind.current + missQueue.io.cancelReturnPipeIndex := rebindRow.returnPipeIndex + val rebindOwnersReady = !rebindNeedsMissCancel || missQueue.io.cancelReady + liq.io.attemptRebindValid := io.attemptRebindValid && rebindOwnersReady + missQueue.io.cancelValid := liq.io.attemptRebindAccepted && + rebindNeedsMissCancel + liq.io.structuralRetryValid := io.structuralRetryValid + liq.io.structuralRetry := io.structuralRetry val launchRow = liq.io.rows(io.launchIndex) private val lineOffsetWidth = log2Ceil(p.lineBytes) - val launchLineAddr = Mux( - launchRow.crossLine && launchRow.secondSegmentActive, - Cat(launchRow.addr(p.addrWidth - 1, lineOffsetWidth), 0.U(lineOffsetWidth.W)) + p.lineBytes.U, - Cat(launchRow.addr(p.addrWidth - 1, lineOffsetWidth), 0.U(lineOffsetWidth.W))) + val launchBaseLineAddr = + Cat(launchRow.addr(p.addrWidth - 1, lineOffsetWidth), 0.U(lineOffsetWidth.W)) + val launchFirstSegmentSize = + p.lineBytes.U(p.loadSizeWidth.W) - launchRow.addr(lineOffsetWidth - 1, 0) + val launchSecondSegment = launchRow.crossLine && launchRow.secondSegmentActive + val launchActiveAddr = Mux( + launchSecondSegment, launchBaseLineAddr + p.lineBytes.U, launchRow.addr) + val launchActiveSize = Mux( + launchSecondSegment, + launchRow.size - launchFirstSegmentSize, + Mux(launchRow.crossLine, launchFirstSegmentSize, launchRow.size)) + val launchLineAddr = + Cat(launchActiveAddr(p.addrWidth - 1, lineOffsetWidth), 0.U(lineOffsetWidth.W)) val launchStidInRange = launchRow.stid < p.stidCount.U val launchPipeInRange = launchRow.returnPipeIndex < p.loadReturnPipeCount.U val launchTargetValid = launchStidInRange && launchPipeInRange @@ -548,25 +651,215 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul launchTargetValid && ((launchResidentCount +& launchReservedCount) < p.loadReturnQueueEntries.U || launchDrainCredit) val launchMissCreditSafe = missQueue.io.freeCount > missReservations - liq.io.launchValid := - io.launchValid && resolveCreditSafe && launchReturnCreditSafe && launchMissCreditSafe && - l1d.io.arrayReady && !launchRow.isTile + private val stqForwardBidWidth = log2Ceil(stqForwardRobEntries) + val launchBidProjectionFits = if (useExternalStqForwarding && + stqForwardBidWidth < LoadAttemptIdentity.IndexWidth) { + !launchRow.attempt.producer.nativeBid( + LoadAttemptIdentity.IndexWidth - 1, stqForwardBidWidth).orR + } else { + true.B + } + val launchForwardReady = WireDefault(true.B) + val launchAdmissionValid = + io.launchValid && launchPermit.getOrElse(true.B) && + resolveCreditSafe && launchReturnCreditSafe && + launchMissCreditSafe && l1d.io.arrayReady && !launchRow.isTile + if (useExternalStqForwarding) { + val queryQueues = forwardQueryQueues.get + val selectedReady = Mux1H( + UIntToOH(launchRow.returnPipeIndex, p.loadReturnPipeCount), + queryQueues.map(_.io.enq.ready)) + launchForwardReady := launchTargetValid && launchBidProjectionFits && selectedReady + } + liq.io.launchValid := launchAdmissionValid && launchForwardReady liq.io.launchIndex := io.launchIndex + liq.io.launchIntentValid := io.launchValid + liq.io.launchIntentIndex := io.launchIndex liq.io.pickValid := io.pickValid liq.io.pickIndex := io.pickIndex liq.io.scbReturnValid := io.scbReturnValid liq.io.scbReturnIndex := io.scbReturnIndex liq.io.markResolvedValid := false.B liq.io.markResolvedIndex := 0.U - liq.io.e2Stores := io.e2Stores l1d.io.loadLookupValid := liq.io.launchAccepted l1d.io.loadLookupLineAddr := launchLineAddr - liq.io.e2BaseData := l1d.io.loadLookup.data - liq.io.e2BaseValidMask := Fill(p.lineBytes, l1d.io.loadLookup.readHit) - liq.io.e2LoadDataReturned := liq.io.launchAccepted - liq.io.e2ScbReturned := io.e2ScbReturned - liq.io.e2StqReturned := io.e2StqReturned - liq.io.e2ReturnReady := true.B + if (useExternalStqForwarding) { + val port = stqForward.get + val queryQueues = forwardQueryQueues.get + val sourceMerge = Module(new LoadSourceLineMerge(p.lineBytes)) + val responseArbiter = Module(new RRArbiter( + chiselTypeOf(port.responses.head.bits), p.loadReturnPipeCount)) + val resultPipeline = Module(new STQLoadForwardResultPipeline( + robEntries = stqForwardRobEntries, + stqEntries = p.stqEntries, + addrWidth = p.addrWidth, + stidWidth = p.stidWidth, + pcWidth = p.pcWidth, + lineBytes = p.lineBytes, + lsidWidth = coreParams.lsidWidth, + tokenWidth = stqForwardTokenWidth)) + val resultRetainer = Module(new LoadForwardResultRetainer( + idEntries = coreParams.robEntries, + storeEntries = p.stqEntries, + pcWidth = p.pcWidth, + lineBytes = p.lineBytes, + lsidWidth = coreParams.lsidWidth, + depth = forwardResultDepth)) + + liq.io.e2Stores := 0.U.asTypeOf(liq.io.e2Stores) + liq.io.e2BaseData := 0.U + liq.io.e2BaseValidMask := 0.U + liq.io.e2LoadDataReturned := false.B + liq.io.e2ScbReturned := false.B + liq.io.e2StqReturned := false.B + liq.io.e2ReturnReady := false.B + + sourceMerge.io.l1d.returned := liq.io.launchAccepted + sourceMerge.io.l1d.validMask := + Fill(p.lineBytes, l1d.io.loadLookup.readHit) + sourceMerge.io.l1d.data := l1d.io.loadLookup.data + sourceMerge.io.scb := port.scb + + for (pipe <- 0 until p.loadReturnPipeCount) { + val query = port.queries(pipe) + val queryQueue = queryQueues(pipe) + queryQueue.io.enq.valid := launchAdmissionValid && liq.io.launchReady && + launchForwardReady && launchTargetValid && + (launchRow.returnPipeIndex === pipe.U) + queryQueue.io.enq.bits := 0.U.asTypeOf(queryQueue.io.enq.bits) + queryQueue.io.enq.bits.token := launchRow.attempt.generation + queryQueue.io.enq.bits.loadId := LoadCanonicalRowIdentity.fromRobId(launchRow.loadId) + queryQueue.io.enq.bits.attempt := launchRow.attempt + queryQueue.io.enq.bits.returnPipeIndex := launchRow.returnPipeIndex + queryQueue.io.enq.bits.stid := launchRow.stid + queryQueue.io.enq.bits.loadBid.valid := launchRow.attempt.producer.nativeBidValid + queryQueue.io.enq.bits.loadBid.value := + launchRow.attempt.producer.nativeBid(log2Ceil(stqForwardRobEntries) - 1, 0) + queryQueue.io.enq.bits.loadBid.wrap := launchRow.attempt.producer.brobGeneration(0) + queryQueue.io.enq.bits.loadLsIdFullValid := launchRow.loadLsIdFullValid + queryQueue.io.enq.bits.loadLsIdFull := launchRow.loadLsIdFull + queryQueue.io.enq.bits.address := launchActiveAddr + queryQueue.io.enq.bits.size := launchActiveSize + queryQueue.io.enq.bits.isTile := launchRow.isTile + queryQueue.io.enq.bits.baseLineData := sourceMerge.io.mergedData + queryQueue.io.enq.bits.baseValidMask := sourceMerge.io.mergedValidMask + queryQueue.io.enq.bits.loadDataReturned := sourceMerge.io.loadDataReturned + queryQueue.io.enq.bits.scbReturned := sourceMerge.io.scbReturned + query.valid := queryQueue.io.deq.valid && !flushCycle + query.bits := queryQueue.io.deq.bits + queryQueue.io.deq.ready := query.ready && !flushCycle + responseArbiter.io.in(pipe) <> port.responses(pipe) + } + + resultPipeline.io.flush := io.flush + resultPipeline.io.response.valid := + responseArbiter.io.out.valid && !io.preciseFlush.req.valid + resultPipeline.io.response.bits := responseArbiter.io.out.bits + responseArbiter.io.out.ready := + resultPipeline.io.response.ready && !io.preciseFlush.req.valid + resultPipeline.io.returnReady := true.B + port.hardBlock.valid := resultPipeline.io.hardBlock.valid + port.hardBlock.bits := resultPipeline.io.hardBlock.bits + resultPipeline.io.hardBlock.ready := port.hardBlock.ready + + val resultTerminal = resultRetainer.io.outValid && + (liq.io.forwardResultAccepted || liq.io.forwardResultRejectedPermanent) + val resultReservations = RegInit(0.U(log2Ceil(forwardResultDepth + 1).W)) + val resultCredit = resultReservations < forwardResultDepth.U || resultTerminal + resultPipeline.io.normalReady := resultCredit + + val resultPayload = Wire(chiselTypeOf(resultRetainer.io.in.bits)) + resultPayload := 0.U.asTypeOf(resultPayload) + resultPayload.identity := resultPipeline.io.e4Identity + resultPayload.lineData := resultPipeline.io.e4LineData + resultPayload.validMask := resultPipeline.io.e4ValidMask + resultPayload.loadByteMask := resultPipeline.io.e4LoadByteMask + resultPayload.forwardMask := resultPipeline.io.e4ForwardMask + resultPayload.waitMask := resultPipeline.io.e4WaitMask + resultPayload.dataComplete := resultPipeline.io.e4DataComplete + resultPayload.sourcesReturned := resultPipeline.io.e4SourcesReturned + resultPayload.scbReturned := resultPipeline.io.e4ScbReturned + resultPayload.stqReturned := resultPipeline.io.e4StqReturned + resultPayload.wakeupValid := resultPipeline.io.e4WakeupValid + resultPayload.waitStore.valid := resultPipeline.io.e4WaitStore.valid + resultPayload.waitStore.storeIndex := resultPipeline.io.e4WaitStore.storeIndex + resultPayload.waitStore.storeId.valid := resultPipeline.io.e4WaitStore.storeId.valid + resultPayload.waitStore.storeId.wrap := resultPipeline.io.e4WaitStore.storeId.wrap + resultPayload.waitStore.storeId.value := resultPipeline.io.e4WaitStore.storeId.value + resultPayload.waitStore.storeLsId.valid := resultPipeline.io.e4WaitStore.storeLsId.valid + resultPayload.waitStore.storeLsId.wrap := resultPipeline.io.e4WaitStore.storeLsId.wrap + resultPayload.waitStore.storeLsId.value := resultPipeline.io.e4WaitStore.storeLsId.value + resultPayload.waitStore.storeLsIdFullValid := + resultPipeline.io.e4WaitStore.storeLsIdFullValid + resultPayload.waitStore.storeLsIdFull := + resultPipeline.io.e4WaitStore.storeLsIdFull + resultPayload.waitStore.pc := resultPipeline.io.e4WaitStore.pc + resultPayload.missKind := resultPipeline.io.e4MissKind + + resultRetainer.io.flush := io.flush + resultRetainer.io.in.valid := resultPipeline.io.e4Valid && !io.flush + resultRetainer.io.in.bits := resultPayload + resultRetainer.io.sinkAccepted := liq.io.forwardResultAccepted + resultRetainer.io.sinkRejectedPermanent := + liq.io.forwardResultRejectedPermanent + resultRetainer.io.sinkRetryRequired := liq.io.forwardResultRetryRequired + liq.io.forwardResultValid := resultRetainer.io.outValid + liq.io.forwardResult := resultRetainer.io.out + + when(io.flush) { + resultReservations := 0.U + }.elsewhen(resultPipeline.io.accepted && !resultTerminal) { + resultReservations := resultReservations + 1.U + }.elsewhen(!resultPipeline.io.accepted && resultTerminal) { + resultReservations := resultReservations - 1.U + } + + port.queryAccepted := liq.io.launchAccepted + port.resultAccepted := liq.io.forwardResultAccepted + port.resultRejectedPermanent := liq.io.forwardResultRejectedPermanent + port.resultRetryRequired := liq.io.forwardResultRetryRequired + port.resultCount := resultRetainer.io.count + port.resultPending := resultRetainer.io.pending || + resultPipeline.io.e3Valid || resultPipeline.io.e4Valid + val queryEnqueueFires = queryQueues.map(_.io.enq.fire) + val queryPending = queryQueues.map(_.io.deq.valid).reduce(_ || _) + port.protocolError := resultRetainer.io.protocolError || + (resultPipeline.io.e4Valid && !io.flush && !resultRetainer.io.in.ready) || + (liq.io.launchAccepted =/= queryEnqueueFires.reduce(_ || _)) || + (PopCount(VecInit(queryEnqueueFires)) > 1.U) || + (launchAdmissionValid && !launchBidProjectionFits) + forwardTransportEmpty := !queryPending && !liq.io.launchAccepted && + !responseArbiter.io.out.valid && !resultPipeline.io.accepted && + !resultPipeline.io.e3Valid && !resultPipeline.io.e4Valid && + !resultRetainer.io.pending && (resultReservations === 0.U) && + !port.hardBlock.valid + port.ownedStateEmpty := !queryPending && !resultPipeline.io.e3Valid && + !resultPipeline.io.e4Valid && !resultRetainer.io.pending && + (resultReservations === 0.U) + + assert(!resultPipeline.io.e4Valid || io.flush || resultRetainer.io.in.ready, + "reserved STQ E4 result must enter retained transport") + assert(liq.io.launchAccepted === queryEnqueueFires.reduce(_ || _), + "canonical LIQ launch and selected STQ query enqueue must accept atomically") + when(resultTerminal && !io.flush) { + assert(resultReservations =/= 0.U, + "terminal retained STQ result must consume a prior reservation") + } + when(resultPipeline.io.accepted && !resultTerminal && !io.flush) { + assert(resultReservations < forwardResultDepth.U, + "accepted STQ response must own retained-result capacity") + } + } else { + liq.io.e2Stores := io.e2Stores + liq.io.e2BaseData := l1d.io.loadLookup.data + liq.io.e2BaseValidMask := Fill(p.lineBytes, l1d.io.loadLookup.readHit) + liq.io.e2LoadDataReturned := liq.io.launchAccepted + liq.io.e2ScbReturned := io.e2ScbReturned + liq.io.e2StqReturned := io.e2StqReturned + liq.io.e2ReturnReady := true.B + liq.io.forwardResultValid := false.B + liq.io.forwardResult := 0.U.asTypeOf(liq.io.forwardResult) + } val mdbReplayWake = Wire(chiselTypeOf(io.replayWake)) mdbReplayWake := 0.U.asTypeOf(mdbReplayWake) mdbReplayWake.source := LoadReplayWakeSource.StoreUnit @@ -608,6 +901,9 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul l1d.io.refill.data := refillTransport.io.out.data l1d.io.refill.writable := false.B l1d.io.evictionReady := io.l1dEvictionReady + l1d.io.invalidateAll := io.l1dInvalidateAll + l1d.io.invalidateLineValid := io.l1dInvalidateLineValid + l1d.io.invalidateLineAddr := io.l1dInvalidateLineAddress refillTransport.io.outReady := !flushCycle && (!refillTransport.io.out.isRead || l1d.io.refillReady) val canonicalRefill = Wire(chiselTypeOf(refillTransport.io.out)) @@ -620,6 +916,7 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul l1d.io.storeLookupLineAddr := scbCache.lookupLineAddr l1d.io.grantWriteValid := scbCache.grantWriteValid l1d.io.grantWriteLineAddr := scbCache.grantWriteLineAddr + l1d.io.grantWriteData := scbCache.grantWriteData l1d.io.storeUpdate := scbCache.update scbCache.ready := l1d.io.arrayReady scbCache.tagHit := l1d.io.storeLookup.tagHit @@ -631,6 +928,8 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul io.l1dResidentCount := l1d.io.residentCount io.l1dDirtyCount := l1d.io.dirtyCount io.l1dProtocolError := l1d.io.protocolError + io.l1dMaintenanceError := l1d.io.protocolError && + (io.l1dInvalidateAll || io.l1dInvalidateLineValid) liq.io.clearResolvedValid := transferPending liq.io.clearResolvedIndex := transferIndex @@ -801,20 +1100,43 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul val missReserve = liq.io.launchAccepted val missRelease = liq.io.e4UpdateValid && !flushCycle val missReservationUnderflow = missRelease && (missReservations === 0.U) + val preciseSurvivingForward = VecInit(liq.io.rows.zipWithIndex.map { + case (row, idx) => row.valid && row.forwardPending && !liq.io.flushPruneMask(idx) + }) + val preciseMissReservations = PopCount(preciseSurvivingForward) for (lane <- 0 until returnLaneCount) { val reserve = liq.io.launchAccepted && launchTargetValid && (launchLane === lane.U) val release = releaseReservation && (releaseLane === lane.U) - when(flushCycle) { + val preciseLaneReservations = PopCount(VecInit(liq.io.rows.zipWithIndex.map { + case (row, idx) => + preciseSurvivingForward(idx) && + ((row.stid * p.loadReturnPipeCount.U + row.returnPipeIndex) === lane.U) + })) + when(io.flush) { returnReservations(lane) := 0.U + }.elsewhen(io.preciseFlush.req.valid) { + if (useExternalStqForwarding) { + returnReservations(lane) := preciseLaneReservations + assert(preciseLaneReservations <= p.loadReturnQueueEntries.U, + "precise survivor reservations must fit the physical return lane") + } else { + returnReservations(lane) := 0.U + } }.elsewhen(reserve && !release) { returnReservations(lane) := returnReservations(lane) + 1.U }.elsewhen(release && !reserve) { returnReservations(lane) := returnReservations(lane) - 1.U } } - when(flushCycle) { + when(io.flush) { missReservations := 0.U + }.elsewhen(io.preciseFlush.req.valid) { + if (useExternalStqForwarding) { + missReservations := preciseMissReservations + } else { + missReservations := 0.U + } }.elsewhen(missReserve && !missRelease) { missReservations := missReservations + 1.U }.elsewhen(missRelease && !missReserve) { @@ -844,7 +1166,7 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul io.allocIndex := liq.io.allocIndex io.allocLoadId := liq.io.allocLoadId io.allocAttemptMalformed := liq.io.allocAttemptMalformed - io.attemptRebindReady := liq.io.attemptRebindReady + io.attemptRebindReady := liq.io.attemptRebindReady && rebindOwnersReady io.attemptRebindAccepted := liq.io.attemptRebindAccepted io.attemptRebindBlockedByFlush := liq.io.attemptRebindBlockedByFlush io.attemptRebindBlockedByInvalidLoadId := liq.io.attemptRebindBlockedByInvalidLoadId @@ -852,9 +1174,24 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul io.attemptRebindBlockedByLifecycle := liq.io.attemptRebindBlockedByLifecycle io.attemptRebindBlockedByStaleAttempt := liq.io.attemptRebindBlockedByStaleAttempt io.attemptRebindBlockedByNextAttempt := liq.io.attemptRebindBlockedByNextAttempt + io.structuralRetryReady := liq.io.structuralRetryReady + io.structuralRetryAccepted := liq.io.structuralRetryAccepted + io.structuralRetryBlockedByLoadId := + liq.io.structuralRetryBlockedByLoadId + io.structuralRetryBlockedByAttempt := + liq.io.structuralRetryBlockedByAttempt + io.structuralRetryBlockedByNextAttempt := + liq.io.structuralRetryBlockedByNextAttempt + io.structuralRetryBlockedByPipe := liq.io.structuralRetryBlockedByPipe + io.structuralRetryBlockedByLifecycle := + liq.io.structuralRetryBlockedByLifecycle + io.structuralRetryBlockedByWaitStore := + liq.io.structuralRetryBlockedByWaitStore + io.structuralRetryBlockedByMutation := + liq.io.structuralRetryBlockedByMutation io.launchReady := liq.io.launchReady && resolveCreditSafe && launchReturnCreditSafe && launchMissCreditSafe && - l1d.io.arrayReady && !launchRow.isTile + l1d.io.arrayReady && !launchRow.isTile && launchForwardReady io.launchAccepted := liq.io.launchAccepted io.launchBlockedByResolveCredit := io.launchValid && !resolveCreditSafe io.launchBlockedByReturnCredit := io.launchValid && !launchReturnCreditSafe @@ -1002,8 +1339,10 @@ class ScalarLSULoadPath(val coreParams: CoreParams = CoreParams()) extends Modul io.mdbReplayWakeCollision := mdbPath.io.storeWakeup.valid && io.replayWakeValid io.mdbTransientEmpty := mdbPath.io.transientEmpty io.mdbProtocolError := mdbPath.io.protocolError || io.mdbReplayWakeCollision - io.empty := - liq.io.empty && resolveQueue.io.empty && !transferPending && mdbPath.io.transientEmpty && + io.transientEmpty := + resolveQueue.io.empty && !transferPending && mdbPath.io.transientEmpty && returnQueue.io.empty && returnPipeline.io.empty && (reservedCount === 0.U) && - missQueue.io.empty && (missReservations === 0.U) && refillTransport.io.empty + missQueue.io.empty && (missReservations === 0.U) && refillTransport.io.empty && + forwardTransportEmpty + io.empty := liq.io.empty && io.transientEmpty } diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala index 95f1d752..aa836b7d 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala @@ -89,6 +89,9 @@ class ScalarLSULoadPathReturnProbe extends Module { preciseFlush.baseOnBid := true.B path.io.flush := io.hardFlush path.io.preciseFlush := preciseFlush + path.io.l1dInvalidateAll := false.B + path.io.l1dInvalidateLineValid := false.B + path.io.l1dInvalidateLineAddress := 0.U val alloc = Wire(chiselTypeOf(path.io.alloc)) alloc := 0.U.asTypeOf(alloc) @@ -117,6 +120,8 @@ class ScalarLSULoadPathReturnProbe extends Module { path.io.alloc := alloc path.io.attemptRebindValid := false.B path.io.attemptRebind := 0.U.asTypeOf(path.io.attemptRebind) + path.io.structuralRetryValid := false.B + path.io.structuralRetry := 0.U.asTypeOf(path.io.structuralRetry) path.io.launchValid := io.launchValid path.io.launchIndex := io.launchIndex @@ -138,6 +143,7 @@ class ScalarLSULoadPathReturnProbe extends Module { path.scbCache.lookupLineAddr := 0.U path.scbCache.grantWriteValid := false.B path.scbCache.grantWriteLineAddr := 0.U + path.scbCache.grantWriteData := 0.U path.io.l1dEvictionReady := true.B path.io.replayWakeValid := false.B path.io.replayWake := 0.U.asTypeOf(path.io.replayWake) diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueue.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueue.scala index d24b0b44..30734add 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueue.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueue.scala @@ -30,6 +30,13 @@ class LoadReplayReturnLretEntry( val loadLsIdFull = UInt(lsidWidth.W) val loadId = new LoadCanonicalRowIdentity val attempt = new LoadAttemptIdentity + // Public OOO↔LSU adapters retain the asynchronous transaction identity + // beside the canonical row/attempt so stale returns can be drained only + // against the exact canceled transaction. Native LSU-only users leave the + // validity bit clear. + val transactionValid = Bool() + val transactionValue = UInt(64.W) + val transactionGeneration = UInt(16.W) val pc = UInt(pcWidth.W) val addr = UInt(addrWidth.W) val size = UInt(sizeWidth.W) diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala index 1fd4bb7f..88ae25cd 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala @@ -701,7 +701,8 @@ class ScalarLSUMDBPath(val coreParams: CoreParams = CoreParams()) extends Module !recoveryQ.io.deq.valid && !storeWakeupReg.valid io.protocolError := - (io.storeProbe.valid && !io.storeProbeReady) || + (io.storeProbeCommit && + (!io.storeProbe.valid || !io.storeProbeReady)) || (io.loadLookupValid && !io.loadLookupReady) || (failedWaitReleaseAccepted && !fanout.io.deleteInAccepted) || fanout.io.recordOverflow || diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala index 457a3e37..818d7779 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala @@ -227,8 +227,13 @@ class ScalarLSUMDBPathProbe extends Module { integratedLiq.io.alloc := integratedAlloc integratedLiq.io.attemptRebindValid := false.B integratedLiq.io.attemptRebind := 0.U.asTypeOf(integratedLiq.io.attemptRebind) + integratedLiq.io.structuralRetryValid := false.B + integratedLiq.io.structuralRetry := + 0.U.asTypeOf(integratedLiq.io.structuralRetry) integratedLiq.io.launchValid := false.B integratedLiq.io.launchIndex := 0.U + integratedLiq.io.launchIntentValid := false.B + integratedLiq.io.launchIntentIndex := 0.U integratedLiq.io.pickValid := false.B integratedLiq.io.pickIndex := 0.U integratedLiq.io.scbReturnValid := false.B @@ -242,6 +247,9 @@ class ScalarLSUMDBPathProbe extends Module { integratedLiq.io.e2ScbReturned := false.B integratedLiq.io.e2StqReturned := false.B integratedLiq.io.e2ReturnReady := false.B + integratedLiq.io.forwardResultValid := false.B + integratedLiq.io.forwardResult := + 0.U.asTypeOf(integratedLiq.io.forwardResult) integratedLiq.io.replayWakeValid := false.B integratedLiq.io.replayWake := 0.U.asTypeOf(integratedLiq.io.replayWake) integratedLiq.io.refillValid := false.B diff --git a/chisel/src/main/scala/linxcore/lsu/ScalarLrScReservationOwner.scala b/chisel/src/main/scala/linxcore/lsu/ScalarLrScReservationOwner.scala index a262cacf..c6550713 100644 --- a/chisel/src/main/scala/linxcore/lsu/ScalarLrScReservationOwner.scala +++ b/chisel/src/main/scala/linxcore/lsu/ScalarLrScReservationOwner.scala @@ -154,6 +154,8 @@ class ScalarLrScReservationOwner(val coreParams: CoreParams = CoreParams()) exte val scStidIdx = if (p.stidCount == 1) 0.U(stidIndexWidth.W) else stidIndex(scStid) val storeInvalidateIdx = if (p.stidCount == 1) 0.U(stidIndexWidth.W) else stidIndex(io.committedStoreInvalidateStid) + val flushStidIdx = + if (p.stidCount == 1) 0.U(stidIndexWidth.W) else stidIndex(io.flushStid) val lrStidIdx = if (p.stidCount == 1) 0.U(stidIndexWidth.W) else stidIndex(io.lrStid) val scInvalidatedThisCycle = io.committedStoreInvalidateValid && @@ -163,6 +165,9 @@ class ScalarLrScReservationOwner(val coreParams: CoreParams = CoreParams()) exte io.committedStoreInvalidateLineAddr === scLineAddr val scReservationHit = scResident && scStidOk && reservationValid(scStidIdx) && reservationLine(scStidIdx) === scLineAddr + val flushMatchesReservation = io.flushValid && io.flushIdentityValid && + stidInRange(io.flushStid) && reservationValid(flushStidIdx) && + identityMatches(reservationIdentity(flushStidIdx), io.flushIdentity) val scSuccessNow = scReservationHit && !scInvalidatedThisCycle val scCompleteFire = io.enable && scResident && scSupported && io.scCommitReady && !flushMatchesSc && !io.contextInvalidate io.scCompleteFire := scCompleteFire @@ -184,6 +189,8 @@ class ScalarLrScReservationOwner(val coreParams: CoreParams = CoreParams()) exte for (idx <- 0 until p.stidCount) { reservationValid(idx) := false.B } + }.elsewhen(flushMatchesReservation) { + reservationValid(flushStidIdx) := false.B } when(io.committedStoreInvalidateValid && stidInRange(io.committedStoreInvalidateStid)) { diff --git a/chisel/src/main/scala/linxcore/lsu/Translation.scala b/chisel/src/main/scala/linxcore/lsu/Translation.scala new file mode 100644 index 00000000..dd37519c --- /dev/null +++ b/chisel/src/main/scala/linxcore/lsu/Translation.scala @@ -0,0 +1,233 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.util.{Cat, Decoupled, PopCount, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.{LoadIssueTxn, MemoryAccessKind, MemoryCommand, + MemoryRequestTxn, MemoryResponseTxn, MemorySize, StoreAddressTxn} + +class DSideTranslationRequest(val p: CoreParams) extends Bundle { + val isStore = Bool() + val load = new LoadIssueTxn(p) + val store = new StoreAddressTxn(p) +} + +class DSideTranslationResult(val p: CoreParams) extends Bundle { + val request = new DSideTranslationRequest(p) + val physicalAddress = UInt(p.physicalAddressWidth.W) + val alignmentFault = Bool() + val accessFault = Bool() + val cacheable = Bool() + val device = Bool() +} + +class DSideTranslationIO( + val p: CoreParams, + val entries: Int, + val pageBytes: Int) + extends Bundle { + val lookup = Flipped(Decoupled(new DSideTranslationRequest(p))) + val result = Decoupled(new DSideTranslationResult(p)) + val invalidate = Input(Bool()) + + val memoryRequest = Decoupled(new MemoryRequestTxn(p)) + val memoryResponse = Flipped(Decoupled(new MemoryResponseTxn(p))) + val responseOwned = Output(Bool()) + val responseMatch = Output(Bool()) + val staleResponse = Output(Bool()) + val outstanding = Output(Bool()) + val quiescent = Output(Bool()) +} + +/** The sole retained D-side translation owner. It accepts a complete load or + * STA transaction through Decoupled, retains it across a PTW miss, and + * publishes exactly one retained result. Physical protection and memory + * attributes are classified after either mapping through one canonical + * region source. + */ +class DSideTranslation( + val p: CoreParams, + val entries: Int = 4, + val pageBytes: Int = 4096) + extends Module { + require(entries > 1 && (entries & (entries - 1)) == 0) + require(pageBytes > 1 && (pageBytes & (pageBytes - 1)) == 0) + require(p.physicalAddressWidth > log2Ceil(pageBytes)) + + private val addrWidth = p.physicalAddressWidth + private val pageOffsetWidth = log2Ceil(pageBytes) + private val pageNumberWidth = addrWidth - pageOffsetWidth + private val indexWidth = log2Ceil(entries) + + val io = IO(new DSideTranslationIO(p, entries, pageBytes)) + + val valid = RegInit(VecInit(Seq.fill(entries)(false.B))) + val vpn = Reg(Vec(entries, UInt(pageNumberWidth.W))) + val ppn = Reg(Vec(entries, UInt(pageNumberWidth.W))) + val readable = RegInit(VecInit(Seq.fill(entries)(false.B))) + val writable = RegInit(VecInit(Seq.fill(entries)(false.B))) + val cacheable = RegInit(VecInit(Seq.fill(entries)(false.B))) + val device = RegInit(VecInit(Seq.fill(entries)(false.B))) + + private def requestAddress(request: DSideTranslationRequest): UInt = + Mux(request.isStore, request.store.address, request.load.address) + private def requestSize(request: DSideTranslationRequest): UInt = + Mux(request.isStore, request.store.sizeBytes, request.load.sizeBytes) + + private def physicalAttributes(address: UInt): (Bool, Bool, Bool, Bool) = { + val default = p.lsu.defaultMemoryAttributes + p.lsu.physicalMemoryRegions.foldRight(( + default.readable.B, default.writable.B, + default.cacheable.B, default.device.B)) { (region, fallback) => + val selected = (address & region.mask.U(addrWidth.W)) === + (region.base & region.mask).U(addrWidth.W) + val attributes = region.attributes + ( + Mux(selected, attributes.readable.B, fallback._1), + Mux(selected, attributes.writable.B, fallback._2), + Mux(selected, attributes.cacheable.B, fallback._3), + Mux(selected, attributes.device.B, fallback._4)) + } + } + + val lookupAddress = requestAddress(io.lookup.bits) + val lookupSize = requestSize(io.lookup.bits) + val lookupVpn = lookupAddress(addrWidth - 1, pageOffsetWidth) + val lookupIndex = lookupVpn(indexWidth - 1, 0) + val explicitTranslation = lookupAddress(addrWidth - 1) + val entryHit = valid(lookupIndex) && vpn(lookupIndex) === lookupVpn + val translatedAddress = Cat( + ppn(lookupIndex), lookupAddress(pageOffsetWidth - 1, 0)) + val mappedAddress = Mux(explicitTranslation && entryHit, + translatedAddress, lookupAddress) + val supportedSize = lookupSize === 1.U || lookupSize === 2.U || + lookupSize === 4.U || lookupSize === 8.U + val alignmentMask = Mux(lookupSize === 0.U, 0.U, lookupSize - 1.U) + val alignmentFault = !supportedSize || + (lookupAddress & alignmentMask) =/= 0.U + val physical = physicalAttributes(mappedAddress) + val mappingReadable = Mux(explicitTranslation, entryHit && readable(lookupIndex), true.B) + val mappingWritable = Mux(explicitTranslation, entryHit && writable(lookupIndex), true.B) + val selectedReadable = mappingReadable && physical._1 + val selectedWritable = mappingWritable && physical._2 + val permissionFault = Mux(io.lookup.bits.isStore, + !selectedWritable, !selectedReadable) + val selectedDevice = Mux(explicitTranslation, + entryHit && device(lookupIndex), false.B) || physical._4 + val selectedCacheable = Mux(explicitTranslation, + entryHit && cacheable(lookupIndex), true.B) && physical._3 && !selectedDevice + + val active = RegInit(false.B) + val activeRequest = Reg(new DSideTranslationRequest(p)) + val activeVpn = Reg(UInt(pageNumberWidth.W)) + val requestOutstanding = RegInit(false.B) + val requestIdentity = RegInit(0.U.asTypeOf(io.memoryRequest.bits.identity)) + val resultValid = RegInit(false.B) + val resultBits = Reg(new DSideTranslationResult(p)) + + require(p.memoryTransactionIdWidth > 1 && + p.memoryTransactionGenerationWidth > 1, + "translation namespace needs owner and counter bits") + private val counterBits = p.lsu.dTranslationCounterBits + require(counterBits > 0 && counterBits < p.memoryTransactionIdWidth && + counterBits < p.memoryTransactionGenerationWidth) + val nextValueCounter = RegInit(0.U(counterBits.W)) + val nextGenerationCounter = RegInit(0.U(counterBits.W)) + + io.lookup.ready := !active && !resultValid + when(io.lookup.fire) { + when(explicitTranslation && !entryHit && !alignmentFault) { + active := true.B + activeRequest := io.lookup.bits + activeVpn := lookupVpn + }.otherwise { + resultValid := true.B + resultBits.request := io.lookup.bits + resultBits.physicalAddress := mappedAddress + resultBits.alignmentFault := alignmentFault + resultBits.accessFault := !alignmentFault && permissionFault + resultBits.cacheable := selectedCacheable + resultBits.device := selectedDevice + } + } + + io.result.valid := resultValid + io.result.bits := resultBits + when(io.result.fire) { resultValid := false.B } + + io.memoryRequest.valid := active && !requestOutstanding + io.memoryRequest.bits := 0.U.asTypeOf(io.memoryRequest.bits) + io.memoryRequest.bits.identity.value := Cat(1.U(1.W), + 0.U((p.memoryTransactionIdWidth - counterBits - 1).W), nextValueCounter) + io.memoryRequest.bits.identity.generation := Cat(1.U(1.W), + 0.U((p.memoryTransactionGenerationWidth - counterBits - 1).W), + nextGenerationCounter) + io.memoryRequest.bits.command := MemoryCommand.Read + io.memoryRequest.bits.accessKind := MemoryAccessKind.Data + io.memoryRequest.bits.address := activeVpn << pageOffsetWidth + io.memoryRequest.bits.size := MemorySize.fromBytes((p.dataWidth / 8).U) + io.memoryRequest.bits.instructionSide := false.B + + when(io.memoryRequest.fire) { + requestOutstanding := true.B + requestIdentity := io.memoryRequest.bits.identity + val valueWrap = nextValueCounter.andR + nextValueCounter := nextValueCounter + 1.U + when(valueWrap) { nextGenerationCounter := nextGenerationCounter + 1.U } + } + + val responseMatch = requestOutstanding && + io.memoryResponse.bits.identity.value === requestIdentity.value && + io.memoryResponse.bits.identity.generation === requestIdentity.generation + val responseOwned = + io.memoryResponse.bits.identity.value(p.memoryTransactionIdWidth - 1) && + io.memoryResponse.bits.identity.generation( + p.memoryTransactionGenerationWidth - 1) + io.memoryResponse.ready := true.B + io.responseOwned := responseOwned + io.responseMatch := responseMatch + io.staleResponse := io.memoryResponse.valid && responseOwned && !responseMatch + + when(io.memoryResponse.fire && responseMatch) { + val refillIndex = activeVpn(indexWidth - 1, 0) + val refillAllowed = !io.memoryResponse.bits.denied && + !io.memoryResponse.bits.corrupt && io.memoryResponse.bits.attributesValid + val refillPpn = io.memoryResponse.bits.data(pageNumberWidth - 1, 0) + val refillPhysicalAddress = Cat(refillPpn, + requestAddress(activeRequest)(pageOffsetWidth - 1, 0)) + val refillPhysical = physicalAttributes(refillPhysicalAddress) + val refillReadable = refillAllowed && io.memoryResponse.bits.readable + val refillWritable = refillAllowed && io.memoryResponse.bits.writable + val refillDevice = refillAllowed && io.memoryResponse.bits.device + val refillCacheable = refillAllowed && io.memoryResponse.bits.cacheable && + !io.memoryResponse.bits.device + valid(refillIndex) := true.B + vpn(refillIndex) := activeVpn + ppn(refillIndex) := refillPpn + readable(refillIndex) := refillReadable + writable(refillIndex) := refillWritable + cacheable(refillIndex) := refillCacheable + device(refillIndex) := refillDevice + + val finalDevice = refillDevice || refillPhysical._4 + val finalReadable = refillReadable && refillPhysical._1 + val finalWritable = refillWritable && refillPhysical._2 + resultValid := true.B + resultBits.request := activeRequest + resultBits.physicalAddress := refillPhysicalAddress + resultBits.alignmentFault := false.B + resultBits.accessFault := Mux(activeRequest.isStore, + !finalWritable, !finalReadable) + resultBits.cacheable := refillCacheable && refillPhysical._3 && !finalDevice + resultBits.device := finalDevice + requestOutstanding := false.B + active := false.B + } + + when(io.invalidate) { valid.foreach(_ := false.B) } + + io.outstanding := active || requestOutstanding || resultValid + io.quiescent := !active && !requestOutstanding && !resultValid + + assert(PopCount(valid) <= entries.U) +} diff --git a/chisel/src/main/scala/linxcore/ooo/BROB.scala b/chisel/src/main/scala/linxcore/ooo/BROB.scala new file mode 100644 index 00000000..51ff38d0 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/BROB.scala @@ -0,0 +1,518 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class BROBIO(val p: CoreParams) extends Bundle { + val candidate = Flipped(Valid(new D3RenameGroup(p))) + val prefixOffer = Output(Valid(new D3PrefixLimit(p))) + val prepare = Flipped(Decoupled(new D3RenameGroup(p))) + val robPrepared = Input(new OOORobPrepared(p)) + val prepared = Output(new BROBPrepared(p)) + val publishFire = Input(Bool()) + val release = Flipped(Valid(new BROBReleaseTxn(p))) + val releaseReady = Output(Bool()) + val releaseApply = Input(Bool()) + val releaseAccepted = Valid(new RobIdentity(p)) + val releaseRejected = Valid(new RobIdentity(p)) + val recoveryPrepare = Flipped(Decoupled(new RecoveryPlan(p))) + val recoveryPrepared = Valid(new RecoveryPlan(p)) + val recoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val recoveryAbort = Flipped(Valid(new RecoveryPlan(p))) + val debugUsed = Output(Vec(p.ooo.stidCount, + UInt(PrefixPacketContract.countWidth(p.ooo.brobEntriesPerStid).W))) +} + +class BROB(val p: CoreParams) extends Module { + val io = IO(new BROBIO(p)) + + private val physicalStidWidth = math.max(1, log2Ceil(p.ooo.stidCount)) + private val physicalBidWidth = math.max(1, + log2Ceil(p.ooo.brobEntriesPerStid)) + private def safeStid(stid: UInt): UInt = + if (p.ooo.stidCount == 1) 0.U(physicalStidWidth.W) + else stid(physicalStidWidth - 1, 0) + private def bidInRange(bid: UInt): Bool = + bid < p.ooo.brobEntriesPerStid.U + private def physicalBid(bid: UInt): UInt = + bid(physicalBidWidth - 1, 0) + private def safePhysicalBid(bid: UInt): UInt = + Mux(bidInRange(bid), physicalBid(bid), 0.U(physicalBidWidth.W)) + + val used = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(PrefixPacketContract.countWidth(p.ooo.brobEntriesPerStid).W)))) + io.debugUsed := used + val tail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(p.nativeBidWidth.W)))) + val generation = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.brobGenerationWidth.W)))) + val currentValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + val currentBid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.nativeBidWidth.W)))) + val currentGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.brobGenerationWidth.W)))) + val tableValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(p.ooo.brobEntriesPerStid)(false.B))))) + val tableGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(p.ooo.brobEntriesPerStid)( + 0.U(p.brobGenerationWidth.W)))))) + val tableClosed = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(p.ooo.brobEntriesPerStid)(false.B))))) + val tableFirstRob = Reg(Vec(p.ooo.stidCount, + Vec(p.ooo.brobEntriesPerStid, new RobIdentity(p)))) + val tableLastRob = Reg(Vec(p.ooo.stidCount, + Vec(p.ooo.brobEntriesPerStid, new RobIdentity(p)))) + val head = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(p.nativeBidWidth.W)))) + val headGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.brobGenerationWidth.W)))) + + // Side-effect-free offer computed from the full RENU candidate. ROB + // bindings are intentionally excluded; they are checked only after the + // graph selects one common complete-group prefix. + val candidate = io.candidate.bits + val candidateStidRaw = candidate.entries(0).uop.decoded.rob.stid + val candidateStidInRange = candidateStidRaw < p.ooo.stidCount.U + val candidateStid = safeStid(candidateStidRaw) + val candidateLaneGroupMatch = Wire(Vec(p.ooo.d3PrefixWidth, + Vec(p.ooo.d3PrefixWidth, Bool()))) + for (lane <- 0 until p.ooo.d3PrefixWidth; + group <- 0 until p.ooo.d3PrefixWidth) { + val row = candidate.entries(lane).uop.decoded.rob + val intent = candidate.groups(group) + candidateLaneGroupMatch(lane)(group) := lane.U < candidate.count && + group.U < candidate.groupCount && intent.valid && + intent.peId === row.peId && intent.stid === row.stid && + intent.ridSlot === row.ridSlot && + intent.ridGeneration === row.ridGeneration + } + val candidateScanTail = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(p.nativeBidWidth.W))) + val candidateScanGen = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(p.brobGenerationWidth.W))) + val candidateScanCurrentValid = Wire(Vec(p.ooo.d3PrefixWidth + 1, Bool())) + val candidateScanCurrentBid = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(p.nativeBidWidth.W))) + val candidateScanCurrentGen = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(p.brobGenerationWidth.W))) + val candidateScanCurrentResident = Wire(Vec(p.ooo.d3PrefixWidth + 1, Bool())) + val candidateAllocates = Wire(Vec(p.ooo.d3PrefixWidth, Bool())) + candidateScanTail(0) := tail(candidateStid) + candidateScanGen(0) := generation(candidateStid) + candidateScanCurrentValid(0) := currentValid(candidateStid) + candidateScanCurrentBid(0) := currentBid(candidateStid) + candidateScanCurrentGen(0) := currentGeneration(candidateStid) + candidateScanCurrentResident(0) := currentValid(candidateStid) && + tableValid(candidateStid)(physicalBid(currentBid(candidateStid))) && + tableGeneration(candidateStid)(physicalBid(currentBid(candidateStid))) === + currentGeneration(candidateStid) + for (lane <- 0 until p.ooo.d3PrefixWidth) { + val active = lane.U < candidate.count + val startsBlock = active && candidate.entries(lane).blockStart + val stopsBlock = active && candidate.entries(lane).blockStop + val reopensBlock = active && !startsBlock && + candidateScanCurrentValid(lane) && !candidateScanCurrentResident(lane) + val allocates = startsBlock || reopensBlock + candidateAllocates(lane) := allocates + val nextTailWide = candidateScanTail(lane) +& allocates.asUInt + val wraps = nextTailWide >= p.ooo.brobEntriesPerStid.U + candidateScanTail(lane + 1) := Mux(wraps, 0.U(p.nativeBidWidth.W), + physicalBid(nextTailWide)) + candidateScanGen(lane + 1) := candidateScanGen(lane) + wraps.asUInt + candidateScanCurrentValid(lane + 1) := + Mux(active, !stopsBlock, candidateScanCurrentValid(lane)) + candidateScanCurrentBid(lane + 1) := Mux(allocates, + candidateScanTail(lane), candidateScanCurrentBid(lane)) + candidateScanCurrentGen(lane + 1) := Mux(allocates, + candidateScanGen(lane), candidateScanCurrentGen(lane)) + candidateScanCurrentResident(lane + 1) := Mux(active, + candidateScanCurrentResident(lane) || allocates, + candidateScanCurrentResident(lane)) + } + val candidateGroupExact = Wire(Vec(p.ooo.d3PrefixWidth, Bool())) + val candidateAcceptedGroup = Wire(Vec(p.ooo.d3PrefixWidth, Bool())) + val candidateOfferChain = Wire(Vec(p.ooo.d3PrefixWidth + 1, Bool())) + val candidateAllocThrough = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W))) + candidateOfferChain(0) := true.B + candidateAllocThrough(0) := 0.U + for (group <- 0 until p.ooo.d3PrefixWidth) { + val active = group.U < candidate.groupCount + val groupSeen = (0 until p.ooo.d3PrefixWidth).map { lane => + candidateLaneGroupMatch(lane)(group) + }.reduce(_ || _) + val laneShape = (0 until p.ooo.d3PrefixWidth).map { lane => + val laneActive = lane.U < candidate.count + !candidateLaneGroupMatch(lane)(group) || + (laneActive && candidate.entries(lane).uop.decoded.valid && + PopCount(candidateLaneGroupMatch(lane)) === 1.U) + }.reduce(_ && _) + val groupAllocations = PopCount((0 until p.ooo.d3PrefixWidth).map { lane => + candidateLaneGroupMatch(lane)(group) && candidateAllocates(lane) + }) + candidateAllocThrough(group + 1) := + candidateAllocThrough(group) + groupAllocations + candidateGroupExact(group) := active && candidate.groups(group).valid && + groupSeen && laneShape + candidateAcceptedGroup(group) := candidateOfferChain(group) && + candidateGroupExact(group) && + used(candidateStid) + candidateAllocThrough(group + 1) <= + p.ooo.brobEntriesPerStid.U + candidateOfferChain(group + 1) := candidateAcceptedGroup(group) + } + val candidateOfferedGroups = PopCount(candidateAcceptedGroup) + val candidateOfferedLanes = PopCount((0 until p.ooo.d3PrefixWidth).map { lane => + lane.U < candidate.count && (0 until p.ooo.d3PrefixWidth).map { group => + group.U < candidateOfferedGroups && + candidateLaneGroupMatch(lane)(group) + }.reduce(_ || _) + }) + val candidateShapeExact = candidate.count.orR && + candidate.count <= p.ooo.d3PrefixWidth.U && candidate.groupCount.orR && + candidate.groupCount <= candidate.count && + candidate.groupCount <= p.ooo.d3PrefixWidth.U + io.prefixOffer.valid := io.candidate.valid && candidateStidInRange && + candidateShapeExact && candidateOfferedGroups.orR && + candidateOfferedLanes.orR + io.prefixOffer.bits.count := candidateOfferedLanes + io.prefixOffer.bits.groupCount := candidateOfferedGroups + + val prepareStidRaw = io.prepare.bits.entries(0).uop.decoded.rob.stid + val prepareStidInRange = prepareStidRaw < p.ooo.stidCount.U + val stid = safeStid(prepareStidRaw) + val prepared = Wire(new BROBPrepared(p)) + prepared := 0.U.asTypeOf(prepared) + prepared.count := io.prepare.bits.count + val scanTail = Wire(Vec(p.ooo.d3PrefixWidth + 1, UInt(p.nativeBidWidth.W))) + val scanGen = Wire(Vec(p.ooo.d3PrefixWidth + 1, UInt(p.brobGenerationWidth.W))) + val scanCurrentValid = Wire(Vec(p.ooo.d3PrefixWidth + 1, Bool())) + val scanCurrentBid = Wire(Vec(p.ooo.d3PrefixWidth + 1, UInt(p.nativeBidWidth.W))) + val scanCurrentGen = Wire(Vec(p.ooo.d3PrefixWidth + 1, UInt(p.brobGenerationWidth.W))) + val scanCurrentResident = Wire(Vec(p.ooo.d3PrefixWidth + 1, Bool())) + val allocCount = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W))) + scanTail(0) := tail(stid) + scanGen(0) := generation(stid) + scanCurrentValid(0) := currentValid(stid) + scanCurrentBid(0) := currentBid(stid) + scanCurrentGen(0) := currentGeneration(stid) + scanCurrentResident(0) := currentValid(stid) && + tableValid(stid)(physicalBid(currentBid(stid))) && + tableGeneration(stid)(physicalBid(currentBid(stid))) === + currentGeneration(stid) + allocCount(0) := 0.U + for (lane <- 0 until p.ooo.d3PrefixWidth) { + val active = lane.U < io.prepare.bits.count + val startsBlock = active && io.prepare.bits.entries(lane).blockStart + val stopsBlock = active && io.prepare.bits.entries(lane).blockStop + // A recovered open-current context can outlive retirement of its original + // BROB slot. The first redirected continuation re-materializes that + // context at the current tail so its eventual stop has a live head-owned + // slot to close and release. + val reopensBlock = active && !startsBlock && scanCurrentValid(lane) && + !scanCurrentResident(lane) + val allocatesBlock = startsBlock || reopensBlock + val bid = Mux(allocatesBlock, scanTail(lane), scanCurrentBid(lane)) + val gen = Mux(allocatesBlock, scanGen(lane), scanCurrentGen(lane)) + prepared.entries(lane).valid := active + prepared.entries(lane).stid := stid + prepared.entries(lane).bid := bid + prepared.entries(lane).brobGeneration := gen + prepared.entries(lane).allocated := allocatesBlock + val nextTailWide = scanTail(lane) +& allocatesBlock.asUInt + val wrap = nextTailWide >= p.ooo.brobEntriesPerStid.U + scanTail(lane + 1) := Mux(wrap, 0.U(p.nativeBidWidth.W), + physicalBid(nextTailWide)) + scanGen(lane + 1) := scanGen(lane) + wrap.asUInt + scanCurrentValid(lane + 1) := Mux(active, !stopsBlock, scanCurrentValid(lane)) + scanCurrentBid(lane + 1) := Mux(allocatesBlock, bid, scanCurrentBid(lane)) + scanCurrentGen(lane + 1) := Mux(allocatesBlock, gen, scanCurrentGen(lane)) + scanCurrentResident(lane + 1) := Mux( + active, scanCurrentResident(lane) || allocatesBlock, + scanCurrentResident(lane)) + allocCount(lane + 1) := allocCount(lane) + allocatesBlock.asUInt + } + io.prepared := prepared + val publicationExact = io.robPrepared.count === io.prepare.bits.count && + (0 until p.ooo.d3PrefixWidth).map { lane => + val active = lane.U < io.prepare.bits.count + val raw = io.prepare.bits.entries(lane).uop.decoded.rob + val bound = io.robPrepared.entries(lane).rob + !active || ( + io.robPrepared.entries(lane).valid && + bound.peId === raw.peId && + bound.stid === raw.stid && + bound.ridSlot === raw.ridSlot && + bound.ridGeneration === raw.ridGeneration && + bound.memberIndex === raw.memberIndex && + bound.bid === prepared.entries(lane).bid && + bound.brobGeneration === prepared.entries(lane).brobGeneration) + }.reduce(_ && _) + val recoveryPending = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val recoveryKilledMaskReg = RegInit(VecInit(Seq.fill(p.ooo.brobEntriesPerStid)( + false.B))) + val recoveryKilledCountReg = + RegInit(0.U(PrefixPacketContract.countWidth(p.ooo.brobEntriesPerStid).W)) + val recoveryStraddlingBlockReg = RegInit(false.B) + val recoveryStraddlingBidReg = RegInit(0.U(p.nativeBidWidth.W)) + val recoveryStraddlingGenerationReg = RegInit(0.U(p.brobGenerationWidth.W)) + val recoveryCurrentValidReg = RegInit(false.B) + val recoveryCurrentBidReg = RegInit(0.U(p.nativeBidWidth.W)) + val recoveryCurrentGenerationReg = RegInit(0.U(p.brobGenerationWidth.W)) + val recoveryUsedReg = + RegInit(0.U(PrefixPacketContract.countWidth(p.ooo.brobEntriesPerStid).W)) + val recoveryTailReg = RegInit(0.U(p.nativeBidWidth.W)) + val recoveryGenerationReg = RegInit(0.U(p.brobGenerationWidth.W)) + val recoverySurvivingTailReg = Reg(new RobIdentity(p)) + + io.prepare.ready := !recoveryPending && + prepareStidInRange && + io.prepare.bits.count <= p.ooo.d3PrefixWidth.U && + used(stid) + allocCount(p.ooo.d3PrefixWidth) <= p.ooo.brobEntriesPerStid.U && + publicationExact + + when(io.prepare.valid && io.publishFire && io.prepare.ready) { + tail(stid) := scanTail(p.ooo.d3PrefixWidth) + generation(stid) := scanGen(p.ooo.d3PrefixWidth) + currentValid(stid) := scanCurrentValid(p.ooo.d3PrefixWidth) + currentBid(stid) := scanCurrentBid(p.ooo.d3PrefixWidth) + currentGeneration(stid) := scanCurrentGen(p.ooo.d3PrefixWidth) + used(stid) := used(stid) + allocCount(p.ooo.d3PrefixWidth) + for (lane <- 0 until p.ooo.d3PrefixWidth) { + val startsBlock = io.prepare.bits.entries(lane).blockStart + when(prepared.entries(lane).valid && startsBlock && + scanCurrentValid(lane) && scanCurrentResident(lane)) { + tableClosed(stid)(physicalBid(scanCurrentBid(lane))) := true.B + } + when(prepared.entries(lane).valid && prepared.entries(lane).allocated) { + val boundRob = io.robPrepared.entries(lane).rob + val preparedBid = physicalBid(prepared.entries(lane).bid) + tableValid(stid)(preparedBid) := true.B + tableGeneration(stid)(preparedBid) := + prepared.entries(lane).brobGeneration + tableClosed(stid)(preparedBid) := false.B + tableFirstRob(stid)(preparedBid) := + boundRob + tableLastRob(stid)(preparedBid) := + boundRob + } + val currentBlockInPrefix = scanCurrentValid(lane) && + scanCurrentBid(lane) === prepared.entries(lane).bid + when(prepared.entries(lane).valid && + (prepared.entries(lane).allocated || + tableValid(stid)(physicalBid(prepared.entries(lane).bid)) || + currentBlockInPrefix)) { + val boundRob = io.robPrepared.entries(lane).rob + tableLastRob(stid)(physicalBid(prepared.entries(lane).bid)) := + boundRob + } + when(prepared.entries(lane).valid && io.prepare.bits.entries(lane).blockStop) { + val boundRob = io.robPrepared.entries(lane).rob + tableClosed(stid)(physicalBid(prepared.entries(lane).bid)) := true.B + tableLastRob(stid)(physicalBid(prepared.entries(lane).bid)) := + boundRob + } + } + } + + val rel = io.release.bits.entries(0) + val relStid = safeStid(rel.stid) + val relPrefixShape = (0 until p.widths.retireWidth).map { lane => + val active = lane.U < io.release.bits.count + !active || ( + io.release.bits.entries(lane).stid === rel.stid && + io.release.bits.entries(lane).bid === head(relStid) && + io.release.bits.entries(lane).brobGeneration === headGeneration(relStid)) + }.reduce(_ && _) + val relIncludesLast = (0 until p.widths.retireWidth).map { lane => + val active = lane.U < io.release.bits.count + val id = io.release.bits.entries(lane) + val last = tableLastRob(relStid)(physicalBid(head(relStid))) + active && + id.stid === last.stid && + id.ridSlot === last.ridSlot && + id.ridGeneration === last.ridGeneration && + id.memberIndex === last.memberIndex && + id.bid === last.bid && + id.brobGeneration === last.brobGeneration + }.reduce(_ || _) + val releaseExact = !recoveryPending && + io.release.valid && io.release.bits.count =/= 0.U && + rel.stid < p.ooo.stidCount.U && + rel.bid === head(relStid) && + bidInRange(rel.bid) && + rel.brobGeneration === headGeneration(relStid) && + tableValid(relStid)(safePhysicalBid(rel.bid)) && + tableGeneration(relStid)(safePhysicalBid(rel.bid)) === + rel.brobGeneration && + tableClosed(relStid)(safePhysicalBid(rel.bid)) && + relPrefixShape + io.releaseReady := releaseExact + val relRob = Wire(new RobIdentity(p)) + relRob := rel + io.releaseAccepted.valid := releaseExact && io.releaseApply + io.releaseAccepted.bits := relRob + io.releaseRejected.valid := io.release.valid && io.release.bits.count =/= 0.U && + !releaseExact + io.releaseRejected.bits := relRob + when(io.release.valid && io.release.bits.count =/= 0.U) { + when(releaseExact && io.releaseApply) { + when(relIncludesLast) { + val relBid = physicalBid(rel.bid) + tableValid(relStid)(relBid) := false.B + tableClosed(relStid)(relBid) := false.B + used(relStid) := used(relStid) - 1.U + val nextHead = head(relStid) +& 1.U + val wrap = nextHead >= p.ooo.brobEntriesPerStid.U + head(relStid) := Mux(wrap, 0.U(p.nativeBidWidth.W), + physicalBid(nextHead)) + headGeneration(relStid) := headGeneration(relStid) + wrap.asUInt + } + } + } + + val recIn = io.recoveryPrepare.bits + val recStid = safeStid(recIn.trigger.stid) + val recSuffixLegal = RecoveryPlanContract.legalSuffixWindow(recIn) + val recTargetValid = recIn.trigger.stid < p.ooo.stidCount.U + val recFirstBid = recIn.firstKilled.bid + val recLastBid = recIn.lastKilled.bid + val recFirstBidInRange = bidInRange(recFirstBid) + val recLastBidInRange = bidInRange(recLastBid) + val recFirstPhysicalBid = safePhysicalBid(recFirstBid) + val recLastPhysicalBid = safePhysicalBid(recLastBid) + val recFirstSlotValid = recIn.firstKilledValid && + recFirstBidInRange && tableValid(recStid)(recFirstPhysicalBid) && + tableGeneration(recStid)(recFirstPhysicalBid) === + recIn.firstKilled.brobGeneration + val recLastSlotValid = recIn.firstKilledValid && + recLastBidInRange && tableValid(recStid)(recLastPhysicalBid) && + tableGeneration(recStid)(recLastPhysicalBid) === + recIn.lastKilled.brobGeneration + val recFirstSlotFirstKilled = recFirstSlotValid && + RecoveryPlanContract.suffixMember(recIn, + tableFirstRob(recStid)(recFirstPhysicalBid)) + val recFirstSlotStraddles = recFirstSlotValid && + !RecoveryPlanContract.suffixMember(recIn, + tableFirstRob(recStid)(recFirstPhysicalBid)) && + RecoveryPlanContract.suffixMember(recIn, + tableLastRob(recStid)(recFirstPhysicalBid)) + val recFirstEndpointExact = !recIn.firstKilledValid || ( + (recFirstSlotFirstKilled && + tableFirstRob(recStid)(recFirstPhysicalBid).asUInt === + recIn.firstKilled.asUInt) || + (recFirstSlotStraddles && + RecoveryPlanContract.suffixMember(recIn, recIn.firstKilled))) + val recLastEndpointExact = !recIn.firstKilledValid || ( + recLastSlotValid && + tableLastRob(recStid)(recLastPhysicalBid).asUInt === + recIn.lastKilled.asUInt) + val prepareKilledMask = Wire(Vec(p.ooo.brobEntriesPerStid, Bool())) + val prepareStraddlingMask = Wire(Vec(p.ooo.brobEntriesPerStid, Bool())) + for (bid <- 0 until p.ooo.brobEntriesPerStid) { + val entryExact = tableValid(recStid)(bid) && + tableFirstRob(recStid)(bid).peId === recIn.trigger.peId && + tableFirstRob(recStid)(bid).stid === recIn.trigger.stid && + tableFirstRob(recStid)(bid).bid === bid.U && + tableFirstRob(recStid)(bid).brobGeneration === tableGeneration(recStid)(bid) && + tableLastRob(recStid)(bid).peId === recIn.trigger.peId && + tableLastRob(recStid)(bid).stid === recIn.trigger.stid && + tableLastRob(recStid)(bid).bid === bid.U && + tableLastRob(recStid)(bid).brobGeneration === tableGeneration(recStid)(bid) + val firstKilled = entryExact && + RecoveryPlanContract.suffixMember(recIn, tableFirstRob(recStid)(bid)) + val lastKilled = entryExact && + RecoveryPlanContract.suffixMember(recIn, tableLastRob(recStid)(bid)) + prepareKilledMask(bid) := recIn.firstKilledValid && firstKilled + prepareStraddlingMask(bid) := recIn.firstKilledValid && !firstKilled && lastKilled + } + val prepareStraddlingCount = PopCount(prepareStraddlingMask) + val recLocalProjectionExact = + !recIn.firstKilledValid || prepareKilledMask.asUInt.orR || + prepareStraddlingMask.asUInt.orR + val recBidExact = recSuffixLegal && recTargetValid && + recFirstEndpointExact && recLastEndpointExact && + recLocalProjectionExact && prepareStraddlingCount <= 1.U + io.recoveryPrepare.ready := !recoveryPending && + recIn.phase === RecoveryPhase.Prepare && recBidExact + io.recoveryPrepared.valid := recoveryPending || io.recoveryPrepare.ready + io.recoveryPrepared.bits := Mux(recoveryPending, recoveryPlan, recIn) + when(io.recoveryPrepare.fire) { + val partialCurrent = Wire(Bool()) + val killedCount = Wire(UInt(PrefixPacketContract.countWidth( + p.ooo.brobEntriesPerStid).W)) + killedCount := PopCount(prepareKilledMask) + val straddlingBlock = prepareStraddlingMask.asUInt.orR + val straddlingBid = PriorityEncoder(prepareStraddlingMask) + val straddlingTailWide = straddlingBid +& 1.U + val straddlingTailWrap = straddlingTailWide >= p.ooo.brobEntriesPerStid.U + assert(prepareStraddlingCount <= 1.U) + // Pruning the closing suffix reopens the surviving prefix regardless of + // whether the original block had already published its stop marker. + partialCurrent := straddlingBlock + val currentSurvives = currentValid(recStid) && + tableValid(recStid)(physicalBid(currentBid(recStid))) && + !prepareKilledMask(physicalBid(currentBid(recStid))) + recoveryPending := true.B + recoveryPlan := recIn + recoveryKilledMaskReg := prepareKilledMask + recoveryKilledCountReg := killedCount + recoveryStraddlingBlockReg := straddlingBlock + recoveryStraddlingBidReg := straddlingBid + recoveryStraddlingGenerationReg := tableGeneration(recStid)(straddlingBid) + recoveryCurrentValidReg := Mux(partialCurrent, + true.B, + currentSurvives) + recoveryCurrentBidReg := Mux(partialCurrent, + straddlingBid, currentBid(recStid)) + recoveryCurrentGenerationReg := Mux(partialCurrent, + tableGeneration(recStid)(straddlingBid), currentGeneration(recStid)) + recoveryUsedReg := used(recStid) - killedCount + recoveryTailReg := Mux(straddlingBlock, + Mux(straddlingTailWrap, 0.U(p.nativeBidWidth.W), + straddlingTailWide.pad(p.nativeBidWidth)), + recIn.firstKilled.bid) + recoveryGenerationReg := Mux(straddlingBlock, + tableGeneration(recStid)(straddlingBid) + straddlingTailWrap.asUInt, + recIn.firstKilled.brobGeneration) + recoverySurvivingTailReg := recIn.survivingTail + } + + val recoveryApplyHit = recoveryPending && io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryApply.bits, recoveryPlan) + val recoveryAbortHit = recoveryPending && io.recoveryAbort.valid && + io.recoveryAbort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryAbort.bits, recoveryPlan) + val recoveryApplyStid = safeStid(recoveryPlan.trigger.stid) + when(recoveryApplyHit && !recoveryAbortHit) { + when(recoveryPlan.firstKilledValid) { + for (bid <- 0 until p.ooo.brobEntriesPerStid) { + when(recoveryKilledMaskReg(bid)) { + tableValid(recoveryApplyStid)(bid) := false.B + tableClosed(recoveryApplyStid)(bid) := false.B + } + } + tail(recoveryApplyStid) := recoveryTailReg + generation(recoveryApplyStid) := recoveryGenerationReg + used(recoveryApplyStid) := recoveryUsedReg + currentValid(recoveryApplyStid) := recoveryCurrentValidReg + currentBid(recoveryApplyStid) := recoveryCurrentBidReg + currentGeneration(recoveryApplyStid) := recoveryCurrentGenerationReg + when(recoveryStraddlingBlockReg) { + val straddlingBid = physicalBid(recoveryStraddlingBidReg) + assert(tableGeneration(recoveryApplyStid)(straddlingBid) === + recoveryStraddlingGenerationReg) + tableLastRob(recoveryApplyStid)(straddlingBid) := + recoverySurvivingTailReg + } + } + recoveryPending := false.B + } + when(recoveryAbortHit) { + recoveryPending := false.B + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/CommitControl.scala b/chisel/src/main/scala/linxcore/ooo/CommitControl.scala new file mode 100644 index 00000000..64c3fd68 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/CommitControl.scala @@ -0,0 +1,204 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class CommitControlIO(val p: CoreParams) extends Bundle { + val rob = Flipped(Valid(new OOORobCommitPreview(p))) + val residentHeads = Input(Vec(p.ooo.stidCount, + new OOORobResidentHeadPreview(p))) + val recoveryFence = Input(Vec(p.ooo.stidCount, Bool())) + val interrupts = Input(Vec(p.ooo.stidCount, new InterruptRequest(p))) + val interruptBoundaryValid = Input(Bool()) + val interruptBoundary = Input(new RobIdentity(p)) + val robReleaseReady = Input(Bool()) + val renameReleaseReady = Input(Bool()) + val brobReleaseReady = Input(Bool()) + val pcBufferCommitReady = Input(Bool()) + val debugRequest = Flipped(Decoupled(new DebugRequest(p))) + val debugResponse = Decoupled(new DebugResponse(p)) + val halted = Output(Bool()) + val out = Decoupled(new CommitControlTxn(p)) + val robNoflushReady = Flipped(Decoupled(new RobNoflushReadyTxn(p))) + val robNoflush = Decoupled(new RobNoflushTxn(p)) +} + +class CommitControl(val p: CoreParams) extends Module { + val io = IO(new CommitControlIO(p)) + private def recoveryFenced(stid: UInt): Bool = + if (p.ooo.stidCount == 1) io.recoveryFence(0) else io.recoveryFence(stid) + + val heldValid = RegInit(false.B) + val held = Reg(new CommitControlTxn(p)) + val acceptedValid = RegInit(false.B) + val acceptedTxn = Reg(new CommitControlTxn(p)) + val halted = RegInit(false.B) + val debugPendingValid = RegInit(false.B) + val debugPending = Reg(new DebugRequest(p)) + val debugResponseValid = RegInit(false.B) + val debugResponse = RegInit(0.U.asTypeOf(new DebugResponse(p))) + + io.halted := halted + io.debugRequest.ready := !debugPendingValid && !debugResponseValid + io.debugResponse.valid := debugResponseValid + io.debugResponse.bits := debugResponse + when(io.debugResponse.fire) { + debugResponseValid := false.B + } + when(io.debugRequest.fire) { + when(io.debugRequest.bits.command === DebugCommand.Resume) { + halted := false.B + debugResponseValid := true.B + debugResponse := 0.U.asTypeOf(debugResponse) + debugResponse.transactionId := io.debugRequest.bits.transactionId + debugResponse.accepted := true.B + }.elsewhen(io.debugRequest.bits.command === DebugCommand.Halt && + io.debugRequest.bits.stid < p.ooo.stidCount.U && !halted) { + debugPendingValid := true.B + debugPending := io.debugRequest.bits + }.otherwise { + debugResponseValid := true.B + debugResponse := 0.U.asTypeOf(debugResponse) + debugResponse.transactionId := io.debugRequest.bits.transactionId + debugResponse.error := true.B + } + } + + val next = Wire(new CommitControlTxn(p)) + next := 0.U.asTypeOf(next) + next.commit.count := io.rob.bits.count + next.rename.count := io.rob.bits.count + next.robRelease.count := io.rob.bits.count + next.brobRelease.count := io.rob.bits.count + for (lane <- 0 until p.widths.retireWidth) { + when(lane.U < io.rob.bits.count) { + next.commit.entries(lane) := io.rob.bits.entries(lane).commit + next.rename.lanes(lane) := io.rob.bits.entries(lane).rename + next.robRelease.lanes(lane).valid := io.rob.bits.entries(lane).valid + next.robRelease.lanes(lane).rob := + io.rob.bits.entries(lane).commit.rob + next.brobRelease.entries(lane) := io.rob.bits.entries(lane).commit.rob + } + } + val firstEntryTrap = io.rob.valid && io.rob.bits.count =/= 0.U && + io.rob.bits.entries(0).commit.trap.valid + val headTrap = io.rob.valid && (io.rob.bits.headTrap.valid || firstEntryTrap) + val scopedInterrupts = Wire(Vec(p.ooo.stidCount, new InterruptRequest(p))) + for (stid <- 0 until p.ooo.stidCount) { + scopedInterrupts(stid) := io.interrupts(stid) + scopedInterrupts(stid).valid := io.interrupts(stid).valid && + io.interruptBoundaryValid && + io.interrupts(stid).stid === io.interruptBoundary.stid + } + val anyInterrupt = scopedInterrupts.map(_.valid).reduce(_ || _) + val bestInterrupt = scopedInterrupts.reduce { (a, b) => + Mux(a.valid && (!b.valid || a.priority >= b.priority), a, b) + } + val debugBoundary = debugPendingValid && + debugPending.command === DebugCommand.Halt && io.rob.valid && + io.interruptBoundaryValid && + debugPending.stid === io.interruptBoundary.stid + next.trap := 0.U.asTypeOf(next.trap) + when(headTrap) { + next.trap := Mux(io.rob.bits.headTrap.valid, + io.rob.bits.headTrap, + io.rob.bits.entries(0).commit.trap) + }.elsewhen(debugBoundary) { + next.trap.valid := true.B + next.trap.kind := TrapKind.Debug + next.trap.rob := io.interruptBoundary + }.elsewhen(anyInterrupt && io.interruptBoundaryValid) { + next.trap.valid := true.B + next.trap.kind := TrapKind.Interrupt + next.trap.cause := bestInterrupt.cause + next.trap.rob := io.interruptBoundary + } + + val candidate = Wire(new CommitControlTxn(p)) + candidate := Mux(heldValid, held, next) + val candidateHasTxn = candidate.commit.count =/= 0.U || candidate.trap.valid + val sameAccepted = acceptedValid && candidateHasTxn && + candidate.asUInt === acceptedTxn.asUInt + val robTxnValid = io.rob.valid && !sameAccepted && + (io.rob.bits.count =/= 0.U || io.rob.bits.headTrap.valid || + debugBoundary || (anyInterrupt && io.interruptBoundaryValid)) + val candidateValid = heldValid || robTxnValid + val hasReleaseLanes = candidate.commit.count =/= 0.U + val releaseReady = io.robReleaseReady && io.renameReleaseReady && + io.brobReleaseReady && io.pcBufferCommitReady + io.out.valid := candidateValid && !halted && + (!hasReleaseLanes || releaseReady) + io.out.bits := candidate + val txnAccepted = io.out.fire + when(io.out.valid && !io.out.ready && !heldValid) { + held := next + heldValid := true.B + }.elsewhen(txnAccepted) { + heldValid := false.B + acceptedTxn := candidate + acceptedValid := true.B + when(debugPendingValid && candidate.trap.valid && + candidate.trap.kind === TrapKind.Debug) { + halted := true.B + debugPendingValid := false.B + debugResponseValid := true.B + debugResponse := 0.U.asTypeOf(debugResponse) + debugResponse.transactionId := debugPending.transactionId + debugResponse.accepted := true.B + } + } + when(!txnAccepted && + (!io.rob.valid || (acceptedValid && candidateHasTxn && + candidate.asUInt =/= acceptedTxn.asUInt))) { + acceptedValid := false.B + } + + val noflushAcceptedValid = RegInit(VecInit( + Seq.fill(p.ooo.stidCount)(false.B))) + val noflushAcceptedRob = Reg(Vec(p.ooo.stidCount, new RobIdentity(p))) + for (stid <- 0 until p.ooo.stidCount) { + when(!io.residentHeads(stid).valid || + io.residentHeads(stid).rob.asUInt =/= noflushAcceptedRob(stid).asUInt) { + noflushAcceptedValid(stid) := false.B + } + } + + val readyStidRaw = io.robNoflushReady.bits.rob.stid + val readyStidInRange = readyStidRaw < p.ooo.stidCount.U + val readyStid = Mux(readyStidInRange, readyStidRaw, 0.U) + val readyHead = if (p.ooo.stidCount == 1) io.residentHeads(0) + else io.residentHeads(readyStid) + val readyIdentityExact = readyStidInRange && readyHead.valid && + readyHead.noflushEligible && + readyHead.transactionId === io.robNoflushReady.bits.transactionId && + readyHead.instruction.asUInt === io.robNoflushReady.bits.instruction.asUInt && + readyHead.rob.asUInt === io.robNoflushReady.bits.rob.asUInt + val readyAlreadyAccepted = readyStidInRange && + (if (p.ooo.stidCount == 1) noflushAcceptedValid(0) + else noflushAcceptedValid(readyStid)) && + (if (p.ooo.stidCount == 1) + noflushAcceptedRob(0).asUInt === readyHead.rob.asUInt + else noflushAcceptedRob(readyStid).asUInt === readyHead.rob.asUInt) + val readyFenced = readyStidInRange && recoveryFenced(readyStid) + val noflushCandidate = io.robNoflushReady.valid && readyIdentityExact && + !readyAlreadyAccepted && !readyFenced + + io.robNoflush.valid := noflushCandidate + io.robNoflush.bits := 0.U.asTypeOf(io.robNoflush.bits) + io.robNoflush.bits.transactionId := io.robNoflushReady.bits.transactionId + io.robNoflush.bits.instruction := io.robNoflushReady.bits.instruction + io.robNoflush.bits.rob := io.robNoflushReady.bits.rob + io.robNoflushReady.ready := !readyIdentityExact || readyAlreadyAccepted || + (!readyFenced && io.robNoflush.ready) + when(io.robNoflush.fire) { + if (p.ooo.stidCount == 1) { + noflushAcceptedValid(0) := true.B + noflushAcceptedRob(0) := io.robNoflush.bits.rob + } else { + noflushAcceptedValid(readyStid) := true.B + noflushAcceptedRob(readyStid) := io.robNoflush.bits.rob + } + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/DEC.scala b/chisel/src/main/scala/linxcore/ooo/DEC.scala new file mode 100644 index 00000000..cbfa7fed --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/DEC.scala @@ -0,0 +1,485 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Decoupled, MuxLookup, PopCount, switch, is} +import linxcore.common.{BoundaryKind, DestinationKind, OperandClass, + TemplateRowKind} +import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class DECIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new D1Packet(p))) + val out = Decoupled(new DecodedPacket(p)) +} + +/** Canonical D1 decoder. + * + * This module owns no state. Length-qualified encoded decode reuses the + * generated OOO recipe table through the validated instruction decode leaf; + * CTU template rows bypass encoded decode and are converted directly. + */ +class DEC(val p: CoreParams) extends Module { + val io = IO(new DECIO(p)) + + private val decodeParams = OooParams.fromCoreParams(p) + private val width = p.widths.decodeWidth + require(width == p.widths.ctuOutputWidth) + require(width == decodeParams.instructionDecodeWidth) + require(width <= decodeParams.decodedUopWidth) + + val inputCountValid = io.in.bits.count.orR && io.in.bits.count <= width.U + val active = Wire(Vec(width, Bool())) + val template = Wire(Vec(width, Bool())) + val encoded = Wire(Vec(width, Bool())) + for (lane <- 0 until width) { + active(lane) := lane.U < io.in.bits.count + template(lane) := active(lane) && + io.in.bits.entries(lane).kind === FrontEndOpKind.TemplateUop + encoded(lane) := active(lane) && !template(lane) + } + val encodedMask = encoded.asUInt + val encodedAny = encodedMask.orR + + val decoder = Module(new OooD1Decode(decodeParams, allowSparseInput = true)) + decoder.io.in.valid := io.in.valid && inputCountValid && encodedAny + decoder.io.in.bits := 0.U.asTypeOf(decoder.io.in.bits) + decoder.io.in.bits.validMask := encodedMask + decoder.io.in.bits.peId := io.in.bits.entries(0).parent.identity.peId + decoder.io.in.bits.stid := io.in.bits.entries(0).parent.identity.stid + decoder.io.in.bits.epoch := io.in.bits.entries(0).parent.identity.epoch + for (lane <- 0 until width) { + val source = io.in.bits.entries(lane).parent + val target = decoder.io.in.bits.entries(lane) + target.parent.key.valid := active(lane) + target.parent.key.peId := source.identity.peId + target.parent.key.stid := source.identity.stid + target.parent.key.instructionId := source.identity.instructionId + target.parent.key.epoch := source.identity.epoch + target.parent.pc := source.pc + target.parent.rawInstruction := source.instruction + target.parent.lengthBytes := source.lengthBytes + target.parent.traceOwner := active(lane) + target.parent.preciseExceptionOwner := active(lane) + target.parent.prediction.valid := source.prediction.valid + target.parent.prediction.predictionTag := source.prediction.predictionTag + target.parent.prediction.transactionId := source.prediction.transactionId + target.parent.prediction.fetchPacketUid := source.prediction.fetchPacketUid + target.parent.prediction.fetchSeq := source.prediction.fetchSeq + target.parent.prediction.requestPc := source.prediction.requestPc + target.parent.prediction.taken := source.prediction.taken + target.parent.prediction.branchPc := source.prediction.branchPc + target.parent.prediction.target := source.prediction.target + target.parent.prediction.fallthroughPc := source.prediction.fallthroughPc + target.parent.prediction.kind := BoundaryKind.Fall + switch(source.prediction.kind) { + is(PredictionKind.Conditional) { + target.parent.prediction.kind := BoundaryKind.Cond + } + is(PredictionKind.Call) { + target.parent.prediction.kind := BoundaryKind.Call + } + is(PredictionKind.Return) { + target.parent.prediction.kind := BoundaryKind.Ret + } + is(PredictionKind.Direct) { + target.parent.prediction.kind := BoundaryKind.Direct + } + is(PredictionKind.Indirect) { + target.parent.prediction.kind := BoundaryKind.Ind + } + } + target.parent.prediction.provider := source.prediction.provider + target.parent.prediction.stage := source.prediction.stage + target.parent.prediction.confidence := source.prediction.confidence + target.parent.prediction.checkpointId := source.prediction.checkpointId + target.parent.prediction.epoch := source.prediction.epoch + target.fetchFaultValid := source.fetchFault + target.fetchFaultCause := source.fetchFaultCause + } + + val result = Wire(new DecodedPacket(p)) + result := 0.U.asTypeOf(result) + val encodedCount = PopCount(decoder.io.out.bits.uopMask) + + private def mapSource( + target: DecodedSource, + source: OooDecodedOperand): Unit = { + target.valid := source.valid + target.kind := OperandKind.None + switch(source.operandClass) { + is(OperandClass.P) { target.kind := OperandKind.Gpr } + is(OperandClass.T) { target.kind := OperandKind.T } + is(OperandClass.U) { target.kind := OperandKind.U } + is(OperandClass.CArg) { target.kind := OperandKind.Immediate } + } + target.atag := source.atag + target.relativeIndex := source.relativeIndex + } + + private def mapDestination( + target: DecodedDestination, + source: OooDecodedDestination): Unit = { + target.valid := source.valid + target.kind := OperandKind.None + switch(source.kind) { + is(DestinationKind.Gpr) { target.kind := OperandKind.Gpr } + is(DestinationKind.T) { target.kind := OperandKind.T } + is(DestinationKind.U) { target.kind := OperandKind.U } + } + target.atag := source.atag + target.relativeIndex := source.relativeIndex + } + + private def mapClass(dispatchClass: UInt, target: UopClass.Type): Unit = { + target := UopClass.System + switch(dispatchClass) { + is(OooDispatchClass.Alu.U) { target := UopClass.Alu } + is(OooDispatchClass.Bru.U) { target := UopClass.Bru } + is(OooDispatchClass.Agu.U) { target := UopClass.Agu } + is(OooDispatchClass.Std.U) { target := UopClass.Std } + is(OooDispatchClass.Sys.U) { target := UopClass.System } + is(OooDispatchClass.Cmd.U) { target := UopClass.Cmd } + is(OooDispatchClass.Boundary.U) { target := UopClass.Boundary } + } + } + + private def mapDecoded( + output: DecodedLane, + decodedUop: OooDecodedUop, + input: FrontEndOp): Unit = { + output.uop.valid := true.B + output.uop.instruction := input + output.uop.opcode := decodedUop.opcode + mapClass(decodedUop.recipe.dispatchClass, output.uop.uopClass) + when(decodedUop.recipe.recipeKind === OooOpcodeRecipeKind.Boundary.U) { + output.uop.uopClass := UopClass.Boundary + } + output.uop.classification.valid := decodedUop.recipe.valid + output.uop.classification.disposition := decodedUop.recipe.disposition + output.uop.classification.kind := decodedUop.recipe.recipeKind + output.uop.classification.uopCountMin := decodedUop.recipe.uopCountMin + output.uop.classification.uopCountMax := decodedUop.recipe.uopCountMax + output.uop.classification.complexBreak := decodedUop.recipe.complexBreak + output.uop.classification.splitKind := decodedUop.recipe.lateSplitKind + output.uop.classification.fusionHeadClass := + decodedUop.recipe.fusionHeadClass + output.uop.classification.fusionTailClass := + decodedUop.recipe.fusionTailClass + output.uop.classification.fastResolveClass := + decodedUop.recipe.fastResolveClass + output.uop.classification.implicitSourceMask := + decodedUop.recipe.implicitSourceMask + output.uop.classification.implicitDestination := + decodedUop.recipe.implicitDestination + output.uop.classification.sideEffectOwner := + decodedUop.recipe.sideEffectOwner + output.uop.classification.requiresTargetValidation := + decodedUop.recipe.requiresTargetValidation + output.uop.classification.mayTrap := decodedUop.recipe.mayTrap + output.uop.classification.mayTrapLate := decodedUop.recipe.mayTrapLate + output.uop.classification.mayRedirect := decodedUop.recipe.mayRedirect + output.uop.classification.nonspeculative := + decodedUop.recipe.nonspeculative + output.uop.classification.pcReadRequired := + decodedUop.recipe.pcReadRequired + output.uop.classification.pcReadClass := decodedUop.recipe.pcReadClass + output.uop.classification.dispatchClass := + decodedUop.recipe.dispatchClass + output.uop.classification.dispatchWrites := + decodedUop.recipe.dispatchWrites + for (issueClass <- 0 until p.iex.issueQueueClasses) { + output.uop.classification.dispatchDemand(issueClass) := + decodedUop.recipe.dispatchDemand(issueClass) + output.uop.classification.executionPipeCapability(issueClass) := + decodedUop.recipe.dispatchCapabilities(issueClass) + } + output.uop.classification.memoryRequestCount := + decodedUop.recipe.memoryRequestCount + output.uop.classification.pSourceCount := decodedUop.recipe.pSourceCount + output.uop.classification.pDestinationCount := + decodedUop.recipe.pDestinationCount + output.uop.classification.tAllocationCount := + decodedUop.recipe.tAllocationCount + output.uop.classification.uAllocationCount := + decodedUop.recipe.uAllocationCount + for (source <- 0 until p.maxSourceOperands) { + mapSource(output.uop.sources(source), decodedUop.sources(source)) + } + for (destination <- 0 until p.maxDestinationOperands) { + mapDestination( + output.uop.destinations(destination), + decodedUop.destinations(destination)) + } + output.uop.memory.valid := decodedUop.memory.valid + output.uop.memory.isLoad := decodedUop.memory.isLoad + output.uop.memory.isStore := decodedUop.memory.isStore + output.uop.memory.addressMode := MemoryAddressMode.None + switch(decodedUop.memory.addressMode) { + is(OooMemoryAddressMode.BaseIndex) { + output.uop.memory.addressMode := MemoryAddressMode.BaseIndex + } + is(OooMemoryAddressMode.BaseOffset) { + output.uop.memory.addressMode := MemoryAddressMode.BaseOffset + } + is(OooMemoryAddressMode.PcOffset) { + output.uop.memory.addressMode := MemoryAddressMode.PcOffset + } + } + output.uop.memory.accessBytes := decodedUop.memory.accessBytes + output.uop.memory.signExtend := decodedUop.memory.signExtend + output.uop.memory.offset := decodedUop.memory.offset + output.uop.memory.indexMode := MemoryIndexMode.Identity + switch(decodedUop.memory.indexMode) { + is(OooMemoryIndexMode.SignExtend32) { + output.uop.memory.indexMode := MemoryIndexMode.SignExtend32 + } + is(OooMemoryIndexMode.ZeroExtend32) { + output.uop.memory.indexMode := MemoryIndexMode.ZeroExtend32 + } + is(OooMemoryIndexMode.Negate) { + output.uop.memory.indexMode := MemoryIndexMode.Negate + } + } + output.uop.memory.indexShift := decodedUop.memory.indexShift + output.uop.memory.addressSourceMask := decodedUop.memory.addressSourceMask + output.uop.memory.dataSourceMask := decodedUop.memory.dataSourceMask + output.uop.memory.writebackValid := decodedUop.memory.writebackValid + output.uop.memory.writebackPreIndex := decodedUop.memory.writebackPreIndex + output.uop.memory.requestCount := Mux(decodedUop.memory.valid, + decodedUop.recipe.memoryRequestCount, 0.U) + output.uop.immediateValid := decodedUop.immediateValid + output.uop.immediate := decodedUop.immediate + output.uop.earlyComplete := decodedUop.preciseTrap || + output.uop.uopClass === UopClass.Boundary + output.uop.blockStart := decodedUop.identity.boundary.start + output.uop.blockStop := decodedUop.identity.boundary.stop + output.uop.blockBoundary := decodedUop.identity.boundary.explicit + output.trap.valid := decodedUop.preciseTrap + output.trap.cause := decodedUop.trapCause + } + + private def mapTemplate(output: DecodedLane, input: FrontEndOp): Unit = { + output.uop.valid := true.B + output.uop.instruction := input + val templateSpSub = input.templateOpcode === TemplateRowKind.SP_SUB.asUInt + val templateSpAdd = input.templateOpcode === TemplateRowKind.SP_ADD.asUInt + val templateSpAdjust = templateSpSub || templateSpAdd + val templateStore = input.templateOpcode === TemplateRowKind.STORE.asUInt + val templateLoad = input.templateOpcode === TemplateRowKind.LOAD.asUInt || + input.templateOpcode === TemplateRowKind.VLOAD.asUInt + output.uop.opcode := MuxLookup(input.templateOpcode, + input.templateOpcode)(Seq( + TemplateRowKind.SP_SUB.asUInt -> + FrontendOpcodeDecodeTable.OP_SUBI.U, + TemplateRowKind.SP_ADD.asUInt -> + FrontendOpcodeDecodeTable.OP_ADDI.U, + TemplateRowKind.STORE.asUInt -> + FrontendOpcodeDecodeTable.OP_SDI.U, + TemplateRowKind.LOAD.asUInt -> + FrontendOpcodeDecodeTable.OP_LDI.U, + TemplateRowKind.VLOAD.asUInt -> + FrontendOpcodeDecodeTable.OP_LDI.U)) + output.uop.uopClass := UopClass.System + switch(input.templateOpcode) { + is(TemplateRowKind.SP_SUB.asUInt) { output.uop.uopClass := UopClass.Alu } + is(TemplateRowKind.SP_ADD.asUInt) { output.uop.uopClass := UopClass.Alu } + is(TemplateRowKind.RESTORE_R10.asUInt) { output.uop.uopClass := UopClass.Alu } + is(TemplateRowKind.STORE.asUInt) { output.uop.uopClass := UopClass.Std } + is(TemplateRowKind.LOAD.asUInt) { output.uop.uopClass := UopClass.Agu } + is(TemplateRowKind.VLOAD.asUInt) { output.uop.uopClass := UopClass.Agu } + is(TemplateRowKind.VTGT.asUInt) { output.uop.uopClass := UopClass.Bru } + is(TemplateRowKind.TARGET_PUBLISH.asUInt) { + output.uop.uopClass := UopClass.Bru + } + is(TemplateRowKind.FINAL.asUInt) { + output.uop.uopClass := UopClass.Boundary + } + } + val templateBranch = output.uop.uopClass === UopClass.Bru + val templateBoundary = output.uop.uopClass === UopClass.Boundary + val templateRobOnly = templateBoundary || + input.templateOpcode === TemplateRowKind.VFORM.asUInt + output.uop.classification.valid := true.B + output.uop.classification.disposition := Mux(templateRobOnly, + OooOpcodeDisposition.FastResolve.U, OooOpcodeDisposition.Dispatch.U) + output.uop.classification.kind := Mux(templateStore, + OooOpcodeRecipeKind.ScalarStore.U, + Mux(templateLoad, OooOpcodeRecipeKind.ScalarLoad.U, + Mux(templateRobOnly, OooOpcodeRecipeKind.Boundary.U, + OooOpcodeRecipeKind.CtuTemplate.U))) + output.uop.classification.uopCountMin := 1.U + output.uop.classification.uopCountMax := Mux(templateStore, 2.U, 1.U) + output.uop.classification.splitKind := Mux(templateStore, + OooLateSplitKind.StoreAddressData.U, OooLateSplitKind.None.U) + output.uop.classification.fastResolveClass := Mux(templateRobOnly, + OooFastResolveClass.BoundaryMetadata.U, + OooFastResolveClass.None.U) + output.uop.classification.sideEffectOwner := Mux( + templateStore || templateLoad, OooSideEffectOwner.Lsu.U, + Mux(templateBranch, OooSideEffectOwner.Bctrl.U, + Mux(templateRobOnly, OooSideEffectOwner.Ctu.U, + OooSideEffectOwner.Iex.U))) + output.uop.classification.mayTrap := input.parent.fetchFault || + templateStore || templateLoad + output.uop.classification.mayTrapLate := templateStore || templateLoad + output.uop.classification.mayRedirect := templateBranch + output.uop.classification.nonspeculative := + templateBranch || templateRobOnly + output.uop.classification.pcReadRequired := templateBranch + output.uop.classification.pcReadClass := Mux(templateBranch, + OooDispatchClass.Bru.U, 0.U) + output.uop.classification.dispatchClass := MuxLookup( + output.uop.uopClass.asUInt, OooDispatchClass.None.U)(Seq( + UopClass.Alu.asUInt -> OooDispatchClass.Alu.U, + UopClass.Bru.asUInt -> OooDispatchClass.Bru.U, + UopClass.Agu.asUInt -> OooDispatchClass.Agu.U, + UopClass.Std.asUInt -> OooDispatchClass.Std.U, + UopClass.System.asUInt -> OooDispatchClass.Sys.U, + UopClass.Cmd.asUInt -> OooDispatchClass.Cmd.U, + UopClass.Boundary.asUInt -> OooDispatchClass.None.U)) + output.uop.classification.dispatchWrites := Mux( + templateRobOnly, 0.U, Mux(templateStore, 2.U, 1.U)) + for (issueClass <- 0 until p.iex.issueQueueClasses) { + output.uop.classification.dispatchDemand(issueClass) := 0.U + output.uop.classification.executionPipeCapability(issueClass) := 0.U + } + val aluClass = OooDispatchClass.Alu - 1 + val bruClass = OooDispatchClass.Bru - 1 + val aguClass = OooDispatchClass.Agu - 1 + val stdClass = OooDispatchClass.Std - 1 + when(output.uop.uopClass === UopClass.Alu) { + output.uop.classification.dispatchDemand(aluClass) := 1.U + output.uop.classification.executionPipeCapability(aluClass) := + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U + } + when(templateBranch) { + output.uop.classification.dispatchDemand(bruClass) := 1.U + output.uop.classification.executionPipeCapability(bruClass) := + OooIexDomainCapability.mask(OooIexDomainCapability.Branch).U + } + when(templateLoad) { + output.uop.classification.dispatchDemand(aguClass) := 1.U + output.uop.classification.executionPipeCapability(aguClass) := + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress).U + } + when(templateStore) { + output.uop.classification.dispatchDemand(aguClass) := 1.U + output.uop.classification.dispatchDemand(stdClass) := 1.U + output.uop.classification.executionPipeCapability(aguClass) := + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress).U + output.uop.classification.executionPipeCapability(stdClass) := + OooIexDomainCapability.mask(OooIexDomainCapability.StoreData).U + } + output.uop.classification.memoryRequestCount := + Mux(templateStore || templateLoad, 1.U, 0.U) + when(templateSpAdjust) { + output.uop.sources(0).valid := true.B + output.uop.sources(0).kind := OperandKind.Gpr + output.uop.sources(0).atag := 1.U + output.uop.destinations(0).valid := true.B + output.uop.destinations(0).kind := OperandKind.Gpr + output.uop.destinations(0).atag := 1.U + output.uop.classification.pSourceCount := 1.U + output.uop.classification.pDestinationCount := 1.U + } + when(templateStore) { + output.uop.sources(0).valid := true.B + output.uop.sources(0).kind := OperandKind.Gpr + output.uop.sources(0).atag := input.templateRegister + output.uop.sources(1).valid := true.B + output.uop.sources(1).kind := OperandKind.Gpr + output.uop.sources(1).atag := 1.U + output.uop.classification.pSourceCount := 2.U + } + when(templateLoad) { + output.uop.sources(0).valid := true.B + output.uop.sources(0).kind := OperandKind.Gpr + output.uop.sources(0).atag := 1.U + output.uop.destinations(0).valid := true.B + output.uop.destinations(0).kind := OperandKind.Gpr + output.uop.destinations(0).atag := input.templateRegister + output.uop.classification.pSourceCount := 1.U + output.uop.classification.pDestinationCount := 1.U + } + output.uop.memory.valid := templateStore || templateLoad + output.uop.memory.isStore := templateStore + output.uop.memory.isLoad := templateLoad + output.uop.memory.addressMode := MemoryAddressMode.BaseOffset + output.uop.memory.accessBytes := 8.U + output.uop.memory.offset := input.templateImmediate + output.uop.memory.addressSourceMask := Mux(templateStore, 2.U, 1.U) + output.uop.memory.dataSourceMask := Mux(templateStore, 1.U, 0.U) + output.uop.memory.writebackValid := templateLoad + output.uop.memory.requestCount := Mux(templateStore || templateLoad, 1.U, 0.U) + output.uop.immediateValid := true.B + output.uop.immediate := input.templateImmediate + output.uop.blockStart := input.templateOpcode === TemplateRowKind.VFORM.asUInt + output.uop.blockStop := input.templateOpcode === TemplateRowKind.FINAL.asUInt + output.uop.earlyComplete := + input.parent.fetchFault || + input.templateOpcode === TemplateRowKind.VFORM.asUInt || + input.templateOpcode === TemplateRowKind.FINAL.asUInt + output.uop.blockBoundary := + output.uop.blockStart || output.uop.blockStop + output.trap.valid := input.parent.fetchFault + output.trap.cause := input.parent.fetchFaultCause + } + + val decodedMatch = Wire(Vec(width, Vec(width, Bool()))) + val encodedEmit = Wire(Vec(width, Bool())) + val emit = Wire(Vec(width, Bool())) + for (inputLane <- 0 until width) { + for (decodedSlot <- 0 until width) { + decodedMatch(inputLane)(decodedSlot) := encoded(inputLane) && + decoder.io.out.bits.uopMask(decodedSlot) && + io.in.bits.entries(inputLane).parent.identity.instructionId === + decoder.io.out.bits.uops(decodedSlot).identity.key.primaryParent.instructionId + } + encodedEmit(inputLane) := decodedMatch(inputLane).asUInt.orR + emit(inputLane) := template(inputLane) || encodedEmit(inputLane) + } + val outputCount = PopCount(emit) + result.count := outputCount + for (inputLane <- 0 until width) { + val outputIndex = if (inputLane == 0) 0.U else PopCount(emit.take(inputLane)) + for (outputSlot <- 0 until width) { + when(emit(inputLane) && outputIndex === outputSlot.U) { + when(template(inputLane)) { + mapTemplate(result.entries(outputSlot), io.in.bits.entries(inputLane)) + } + for (decodedSlot <- 0 until width) { + when(decodedMatch(inputLane)(decodedSlot)) { + mapDecoded( + result.entries(outputSlot), + decoder.io.out.bits.uops(decodedSlot), + io.in.bits.entries(inputLane)) + } + } + } + } + } + + val encodedShapeValid = !encodedAny || + (decoder.io.out.valid && !decoder.io.out.bits.ctuParentMask.orR && + !decoder.io.out.bits.complexParentMask.orR && + encodedCount === PopCount(encodedEmit)) + io.out.valid := io.in.valid && inputCountValid && encodedShapeValid && + outputCount.orR + io.out.bits := result + decoder.io.out.ready := io.out.ready + io.in.ready := inputCountValid && encodedShapeValid && io.out.ready + + when(io.in.valid && inputCountValid) { + for (lane <- 0 until width) { + when(active(lane)) { + assert(io.in.bits.entries(lane).parent.identity.peId === + io.in.bits.entries(0).parent.identity.peId) + assert(io.in.bits.entries(lane).parent.identity.stid === + io.in.bits.entries(0).parent.identity.stid) + assert(io.in.bits.entries(lane).parent.identity.epoch === + io.in.bits.entries(0).parent.identity.epoch) + } + } + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/Dispatch.scala b/chisel/src/main/scala/linxcore/ooo/Dispatch.scala new file mode 100644 index 00000000..2ed731e3 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/Dispatch.scala @@ -0,0 +1,47 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.Decoupled +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class DispatchIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new D3RenameGroup(p))) + val robPrepared = Input(new OOORobPrepared(p)) + val brobPrepared = Input(new BROBPrepared(p)) + val iex = new OOODispatchChannels(p) + val recovery = Flipped(new RecoveryTargetIO(p)) + val pending = Output(Bool()) + val publicationTransactionBase = Output(UInt(p.transactionIdWidth.W)) +} + +/** Canonical D3/S1 composition boundary. */ +class Dispatch(val p: CoreParams) extends Module { + val io = IO(new DispatchIO(p)) + val allocator = Module(new OooD3ReservationAllocator(p)) + val classify = Module(new OooDispatch(p)) + + allocator.io.in <> io.in + allocator.io.robPrepared := io.robPrepared + allocator.io.brobPrepared := io.brobPrepared + allocator.io.advance := classify.io.advance + allocator.io.recovery.prepare.valid := io.recovery.prepare.valid + allocator.io.recovery.prepare.bits := io.recovery.prepare.bits + io.recovery.prepare.ready := allocator.io.recovery.prepare.ready + io.recovery.prepared.valid := allocator.io.recovery.prepared.valid + io.recovery.prepared.bits := allocator.io.recovery.prepared.bits + allocator.io.recovery.prepared.ready := io.recovery.prepared.ready + allocator.io.recovery.apply.valid := io.recovery.apply.valid + allocator.io.recovery.apply.bits := io.recovery.apply.bits + allocator.io.recovery.abort.valid := io.recovery.abort.valid + allocator.io.recovery.abort.bits := io.recovery.abort.bits + + classify.io.valid := allocator.io.pendingValid + classify.io.group := allocator.io.pending + classify.io.cursor := allocator.io.cursor + classify.io.transactionBase := allocator.io.transactionBase + classify.io.suppress := io.recovery.apply.valid + io.iex <> classify.io.iex + io.pending := allocator.io.pendingValid + io.publicationTransactionBase := allocator.io.publicationTransactionBase +} diff --git a/chisel/src/main/scala/linxcore/ooo/OOO.scala b/chisel/src/main/scala/linxcore/ooo/OOO.scala new file mode 100644 index 00000000..e97a46f3 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OOO.scala @@ -0,0 +1,267 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{DecoupledIO, PriorityEncoder, Queue} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +/** Canonical D1/D2 stage retained inside the public OOO owner graph. */ +private[ooo] class OOOD1D2Stage(val p: CoreParams) extends Module { + val io = IO(new OOOD1D2IO(p)) + private val width = p.widths.decodeWidth + private val stidWidth = p.ooo.stidWidth + private val ridSlotWidth = p.ooo.ridSlotWidth + private def select[T <: Data](values: Vec[T], index: UInt): T = + if (p.ooo.stidCount == 1) values(0) else values(index) + + val dec = Module(new DEC(p)) + dec.io.in <> io.fromCtu + + val valid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + val rows = Reg(Vec(p.ooo.stidCount, new D2AdmissionGroup(p))) + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val recoveryStid = recoveryPlan.trigger.stid + val prepareStid = io.recovery.prepare.bits.trigger.stid + + private def terminalMatches(candidate: RecoveryPlan): Bool = + candidate.transactionId === recoveryPlan.transactionId && + candidate.cause === recoveryPlan.cause && + candidate.trigger.asUInt === recoveryPlan.trigger.asUInt && + candidate.survivingTailValid === recoveryPlan.survivingTailValid && + candidate.survivingTail.asUInt === recoveryPlan.survivingTail.asUInt && + candidate.redirectPc === recoveryPlan.redirectPc && + candidate.newEpoch === recoveryPlan.newEpoch + + val preparedCompletes = !preparedValid || io.recovery.prepared.fire + val applyHit = recoveryPending && io.recovery.apply.valid && + preparedCompletes && terminalMatches(io.recovery.apply.bits) && + io.recovery.apply.bits.phase === RecoveryPhase.Apply + val abortHit = recoveryPending && io.recovery.abort.valid && + preparedCompletes && terminalMatches(io.recovery.abort.bits) && + io.recovery.abort.bits.phase === RecoveryPhase.Abort + val prepareFire = io.recovery.prepare.fire + + io.recovery.prepare.ready := !recoveryPending && + io.recovery.prepare.bits.trigger.stid < p.ooo.stidCount.U + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan + when(prepareFire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(applyHit || abortHit) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + val fence = Wire(Vec(p.ooo.stidCount, Bool())) + val cancel = Wire(Vec(p.ooo.stidCount, Bool())) + for (stid <- 0 until p.ooo.stidCount) { + fence(stid) := (recoveryPending && recoveryStid === stid.U) || + (prepareFire && prepareStid === stid.U) + cancel(stid) := applyHit && recoveryStid === stid.U + } + + val inputStid = dec.io.out.bits.entries(0).uop.instruction.parent.identity.stid + val inputInRange = inputStid < p.ooo.stidCount.U + val inputOccupied = Mux(inputInRange, select(valid, inputStid), true.B) + val inputFenced = Mux(inputInRange, select(fence, inputStid), true.B) + + val admission = Wire(new D2AdmissionGroup(p)) + admission := 0.U.asTypeOf(admission) + admission.count := dec.io.out.bits.count + val stateGroup = Wire(Vec(width + 1, + UInt(PrefixPacketContract.countWidth(width).W))) + val stateMembers = Wire(Vec(width + 1, + UInt(PrefixPacketContract.countWidth( + p.ooo.maxInstructionsPerRobGroup).W))) + val stateClosed = Wire(Vec(width + 1, Bool())) + val assignedGroup = Wire(Vec(width, + UInt(PrefixPacketContract.countWidth(width).W))) + val assignedMember = Wire(Vec(width, + UInt(p.ooo.robMemberIndexWidth.W))) + stateGroup(0) := 0.U + stateMembers(0) := 0.U + stateClosed(0) := false.B + for (lane <- 0 until width) { + val laneActive = lane.U < dec.io.out.bits.count + val needNewGroup = laneActive && stateMembers(lane).orR && + (stateClosed(lane) || + dec.io.out.bits.entries(lane).uop.blockBoundary || + stateMembers(lane) === p.ooo.maxInstructionsPerRobGroup.U) + assignedGroup(lane) := stateGroup(lane) + needNewGroup.asUInt + assignedMember(lane) := Mux(needNewGroup, 0.U, stateMembers(lane)) + stateGroup(lane + 1) := Mux( + laneActive, assignedGroup(lane), stateGroup(lane)) + stateMembers(lane + 1) := Mux( + laneActive, + Mux(needNewGroup, 1.U, stateMembers(lane) + 1.U), + stateMembers(lane)) + stateClosed(lane + 1) := Mux( + laneActive, + dec.io.out.bits.entries(lane).uop.blockBoundary, + stateClosed(lane)) + } + val groupCount = Mux( + dec.io.out.bits.count.orR, + stateGroup(width) + 1.U, + 0.U) + admission.groupCount := groupCount + for (group <- 0 until width) { + val activeGroup = group.U < groupCount + val slotSum = select(io.ridTailSlot, inputStid) +& group.U + val wraps = slotSum >= p.ooo.robGroupsPerStid.U + admission.groups(group).valid := activeGroup + admission.groups(group).peId := + dec.io.out.bits.entries(0).uop.instruction.parent.identity.peId + admission.groups(group).stid := inputStid + admission.groups(group).ridSlot := Mux(wraps, + (slotSum - p.ooo.robGroupsPerStid.U)(ridSlotWidth - 1, 0), + slotSum(ridSlotWidth - 1, 0)) + admission.groups(group).ridGeneration := + select(io.ridTailGeneration, inputStid) + wraps.asUInt + } + for (lane <- 0 until width) { + val slotSum = select(io.ridTailSlot, inputStid) +& assignedGroup(lane) + val wraps = slotSum >= p.ooo.robGroupsPerStid.U + admission.entries(lane).uop := dec.io.out.bits.entries(lane).uop + admission.entries(lane).trap := dec.io.out.bits.entries(lane).trap + admission.entries(lane).uop.rob.peId := + dec.io.out.bits.entries(lane).uop.instruction.parent.identity.peId + admission.entries(lane).uop.rob.stid := + dec.io.out.bits.entries(lane).uop.instruction.parent.identity.stid + admission.entries(lane).uop.rob.ridSlot := Mux(wraps, + (slotSum - p.ooo.robGroupsPerStid.U)(ridSlotWidth - 1, 0), + slotSum(ridSlotWidth - 1, 0)) + admission.entries(lane).uop.rob.ridGeneration := + select(io.ridTailGeneration, inputStid) + wraps.asUInt + admission.entries(lane).uop.rob.memberIndex := assignedMember(lane) + admission.entries(lane).uop.rob.residentGeneration := 0.U + admission.entries(lane).uop.rob.bid := 0.U + admission.entries(lane).uop.rob.brobGeneration := 0.U + admission.entries(lane).residentBound := false.B + admission.entries(lane).brobBound := false.B + } + + dec.io.out.ready := inputInRange && !inputOccupied && !inputFenced + when(dec.io.out.fire) { + for (stid <- 0 until p.ooo.stidCount) { + when(inputStid === stid.U) { + rows(stid) := admission + valid(stid) := true.B + } + } + } + + val heldGrantValid = RegInit(false.B) + val heldGrantStid = RegInit(0.U(stidWidth.W)) + val eligible = Wire(Vec(p.ooo.stidCount, Bool())) + for (stid <- 0 until p.ooo.stidCount) { + eligible(stid) := valid(stid) && !fence(stid) && !cancel(stid) + } + val selectedNew = if (p.ooo.stidCount == 1) 0.U(stidWidth.W) + else PriorityEncoder(eligible.asUInt) + val heldBlocked = heldGrantValid && + (select(fence, heldGrantStid) || select(cancel, heldGrantStid) || + !select(valid, heldGrantStid)) + val useHeld = heldGrantValid && !heldBlocked + val selected = Mux(useHeld, heldGrantStid, selectedNew) + io.d2.valid := Mux(useHeld, select(valid, selected), eligible.asUInt.orR) + io.d2.bits := select(rows, selected) + + when(io.d2.valid && !io.d2.ready && !useHeld) { + heldGrantValid := true.B + heldGrantStid := selected + } + when(heldBlocked) { + heldGrantValid := false.B + } + when(io.d2.fire) { + for (stid <- 0 until p.ooo.stidCount) { + when(selected === stid.U) { + valid(stid) := false.B + } + } + heldGrantValid := false.B + } + for (stid <- 0 until p.ooo.stidCount) { + when(cancel(stid)) { + valid(stid) := false.B + } + } + + when(dec.io.out.fire) { + assert(dec.io.out.bits.count.orR) + assert(dec.io.out.bits.count <= width.U) + } +} + +/** Public OOO box with one canonical D1-through-S1 owner graph. */ +class OOO(val p: CoreParams) extends Module { + val io = IO(new OOOIO(p)) + + val d1d2 = Module(new OOOD1D2Stage(p)) + val d3s1 = Module(new OOOD3S1Graph(p)) + + d1d2.io.fromCtu <> io.fromCtu + d1d2.io.ridTailSlot := d3s1.io.ridAdmissionTailSlot + d1d2.io.ridTailGeneration := d3s1.io.ridAdmissionTailGeneration + d3s1.io.fromD2 <> d1d2.io.d2 + d1d2.io.recovery <> d3s1.io.recoveryToD1 + for (lane <- io.iex.aluDispatch.indices) { + io.iex.aluDispatch(lane) <> d3s1.io.iex.aluDispatch(lane) + } + for (lane <- io.iex.bruDispatch.indices) { + io.iex.bruDispatch(lane) <> d3s1.io.iex.bruDispatch(lane) + } + for (lane <- io.iex.aguDispatch.indices) { + io.iex.aguDispatch(lane) <> d3s1.io.iex.aguDispatch(lane) + } + for (lane <- io.iex.storeDispatch.indices) { + io.iex.storeDispatch(lane) <> d3s1.io.iex.storeDispatch(lane) + } + for (lane <- io.iex.systemDispatch.indices) { + io.iex.systemDispatch(lane) <> d3s1.io.iex.systemDispatch(lane) + } + for (lane <- io.iex.cmdDispatch.indices) { + io.iex.cmdDispatch(lane) <> d3s1.io.iex.cmdDispatch(lane) + } + io.iex.allocationClear := d3s1.io.iex.allocationClear + io.iex.fastResult <> d3s1.io.iex.fastResult + d3s1.io.iex.pcBufferReadAddress := io.iex.pcBufferReadAddress + io.iex.pcBufferReadPcBase := d3s1.io.iex.pcBufferReadPcBase + d3s1.io.iex.robNoflushReady <> io.iex.robNoflushReady + io.iex.robNoflush <> d3s1.io.iex.robNoflush + for (lane <- io.iex.robResolve.indices) { + d3s1.io.iex.robResolve(lane) <> io.iex.robResolve(lane) + } + d3s1.io.storeResolve <> io.storeResolve + for (lane <- io.iex.storeBinding.indices) { + d3s1.io.iex.storeBinding(lane).valid := io.iex.storeBinding(lane).valid + d3s1.io.iex.storeBinding(lane).bits := io.iex.storeBinding(lane).bits + io.iex.storeBinding(lane).ready := d3s1.io.iex.storeBinding(lane).ready + } + for (lane <- io.iex.systemIssue.indices) { + d3s1.io.iex.systemIssue(lane) <> io.iex.systemIssue(lane) + } + d3s1.io.iex.recoveryEvent <> io.iex.recoveryEvent + d3s1.io.iex.recovery <> io.iex.recovery + io.commit <> d3s1.io.commit + io.storeCommit <> d3s1.io.storeCommit + io.trap <> d3s1.io.trap + d3s1.io.interrupt <> io.interrupt + d3s1.io.debugRequest <> io.debugRequest + io.debugResponse <> d3s1.io.debugResponse + io.recoveryToIfu <> d3s1.io.recoveryToIfu + io.recoveryToCtu <> d3s1.io.recoveryToCtu + io.recoveryToLsu <> d3s1.io.recoveryToLsu + for (lane <- io.systemIssue.indices) { + io.systemIssue(lane) <> d3s1.io.systemIssue(lane) + } + io.trace <> d3s1.io.trace +} diff --git a/chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala b/chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala new file mode 100644 index 00000000..226b5c5b --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala @@ -0,0 +1,465 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Arbiter, Decoupled, Mux1H, PopCount, PriorityEncoder, + Valid} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +private[ooo] object OOOCommitApplyPolicy { + def releaseFire(transactionFire: Bool, commitCount: UInt): Bool = + transactionFire && commitCount =/= 0.U +} + +/** Canonical production graph below the D2 boundary. The public OOO box and + * the multi-STID reference test both use this exact owner composition. + */ +class OOOD3S1GraphIO(val p: CoreParams) extends Bundle { + val fromD2 = Flipped(Decoupled(new D2AdmissionGroup(p))) + val ridTailSlot = Output(Vec(p.ooo.stidCount, + UInt(p.ooo.ridSlotWidth.W))) + val ridTailGeneration = Output(Vec(p.ooo.stidCount, + UInt(p.ridGenerationWidth.W))) + val ridAdmissionTailSlot = Output(Vec(p.ooo.stidCount, + UInt(p.ooo.ridSlotWidth.W))) + val ridAdmissionTailGeneration = Output(Vec(p.ooo.stidCount, + UInt(p.ridGenerationWidth.W))) + val iex = new OOOIEXIO(p) + val storeResolve = Flipped(Decoupled(new RobResolveTxn(p))) + val commit = Decoupled(new CommitTxn(p)) + val storeCommit = Decoupled(new StoreCommitAuthorizationTxn(p)) + val trap = Decoupled(new TrapEvent(p)) + val interrupt = Flipped(Valid(new InterruptRequest(p))) + val debugRequest = Flipped(Decoupled(new DebugRequest(p))) + val debugResponse = Decoupled(new DebugResponse(p)) + val recoveryToD1 = new RecoveryTargetIO(p) + val recoveryToIfu = new RecoveryTargetIO(p) + val recoveryToCtu = new RecoveryTargetIO(p) + val recoveryToLsu = new RecoveryTargetIO(p) + val systemIssue = Vec(p.iex.systemMulticycleQueues, + Decoupled(new SystemIssueTxn(p))) + val trace = Decoupled(new TracePacket(p)) +} + +class OOOD3S1Graph(val p: CoreParams) extends Module { + val io = IO(new OOOD3S1GraphIO(p)) + private def select[T <: Data](values: Vec[T], index: UInt): T = + if (p.ooo.stidCount == 1) values(0) else values(index) + + val renu = Module(new RENU(p)) + val memoryOrder = Module(new OooMemoryOrderAllocator(p)) + val rob = Module(new ROB(p)) + val brob = Module(new BROB(p)) + val pcBuffer = Module(new OooPcBuffer(p)) + val dispatch = Module(new Dispatch(p)) + val fastResult = Module(new OooD3FastResultQueue(p)) + val commitControl = Module(new CommitControl(p)) + private val recoveryTargetCount = 10 + val recovery = Module(new RecoveryControl(p, recoveryTargetCount)) + + val d2Stid = io.fromD2.bits.entries(0).uop.rob.stid + rob.io.storeBinding <> io.iex.storeBinding + val earlyRecoveryValid = recovery.io.robPrepare.valid || + rob.io.recoveryPrepared.valid + val earlyRecoveryStid = Mux(recovery.io.robPrepare.valid, + recovery.io.robPrepare.bits.trigger.stid, + rob.io.recoveryPrepared.bits.trigger.stid) + val d2RecoveryFenced = earlyRecoveryValid && d2Stid === earlyRecoveryStid + memoryOrder.io.prepare.valid := io.fromD2.valid && !d2RecoveryFenced + memoryOrder.io.prepare.bits := io.fromD2.bits + renu.io.fromD2.valid := io.fromD2.valid && !d2RecoveryFenced && + memoryOrder.io.prepareReady + renu.io.fromD2.bits := io.fromD2.bits + io.fromD2.ready := !d2RecoveryFenced && renu.io.fromD2.ready && + memoryOrder.io.prepareReady + memoryOrder.io.reserveFire := io.fromD2.fire + memoryOrder.io.cancel := VecInit(Seq.fill(p.ooo.stidCount)(false.B)) + io.ridTailSlot := rob.io.ridTailSlot + io.ridTailGeneration := rob.io.ridTailGeneration + for (stid <- 0 until p.ooo.stidCount) { + val admissionTail = rob.io.ridTailSlot(stid) +& + renu.io.reservedGroupCount(stid) + val admissionWrap = admissionTail >= p.ooo.robGroupsPerStid.U + io.ridAdmissionTailSlot(stid) := Mux( + admissionWrap, + (admissionTail - p.ooo.robGroupsPerStid.U)(p.ooo.ridSlotWidth - 1, 0), + admissionTail(p.ooo.ridSlotWidth - 1, 0)) + io.ridAdmissionTailGeneration(stid) := + rob.io.ridTailGeneration(stid) + admissionWrap.asUInt + } + + pcBuffer.io.prepare.valid := renu.io.candidate.valid + pcBuffer.io.prepare.bits := renu.io.candidate.bits + rob.io.candidate := renu.io.candidate + brob.io.candidate := renu.io.candidate + val allPrefixOffersValid = rob.io.prefixOffer.valid && + brob.io.prefixOffer.valid && pcBuffer.io.prefixOffer.valid + val robBrobGroups = Mux( + rob.io.prefixOffer.bits.groupCount <= brob.io.prefixOffer.bits.groupCount, + rob.io.prefixOffer.bits.groupCount, + brob.io.prefixOffer.bits.groupCount) + val commonGroupCount = Mux( + robBrobGroups <= pcBuffer.io.prefixOffer.bits.groupCount, + robBrobGroups, + pcBuffer.io.prefixOffer.bits.groupCount) + val candidateLaneGroupMatch = Wire(Vec(p.ooo.d3PrefixWidth, + Vec(p.ooo.d3PrefixWidth, Bool()))) + for (lane <- 0 until p.ooo.d3PrefixWidth; + group <- 0 until p.ooo.d3PrefixWidth) { + val row = renu.io.candidate.bits.entries(lane).uop.decoded.rob + val intent = renu.io.candidate.bits.groups(group) + candidateLaneGroupMatch(lane)(group) := + lane.U < renu.io.candidate.bits.count && + group.U < commonGroupCount && intent.valid && + intent.peId === row.peId && intent.stid === row.stid && + intent.ridSlot === row.ridSlot && + intent.ridGeneration === row.ridGeneration + } + val commonLaneMask = VecInit((0 until p.ooo.d3PrefixWidth).map { lane => + candidateLaneGroupMatch(lane).asUInt.orR + }) + val commonLaneCount = PopCount(commonLaneMask) + val commonLanePrefixExact = (0 until p.ooo.d3PrefixWidth).map { lane => + commonLaneMask(lane) === (lane.U < commonLaneCount) + }.reduce(_ && _) + val commonLimitValid = renu.io.candidate.valid && allPrefixOffersValid && + commonGroupCount.orR && commonLaneCount.orR && commonLanePrefixExact + renu.io.prefixLimit.valid := commonLimitValid + renu.io.prefixLimit.bits.count := commonLaneCount + renu.io.prefixLimit.bits.groupCount := commonGroupCount + pcBuffer.io.selectedLimit.valid := commonLimitValid + pcBuffer.io.selectedLimit.bits := renu.io.prefixLimit.bits + when(commonLimitValid) { + assert(rob.io.prefixOffer.bits.groupCount >= commonGroupCount && + brob.io.prefixOffer.bits.groupCount >= commonGroupCount && + pcBuffer.io.prefixOffer.bits.groupCount >= commonGroupCount, + "all D3 owners must cover the selected complete-group prefix") + assert(rob.io.prefixOffer.bits.count >= commonLaneCount && + brob.io.prefixOffer.bits.count >= commonLaneCount && + pcBuffer.io.prefixOffer.bits.count >= commonLaneCount, + "all D3 owners must cover every lane in the selected prefix") + } + + val d3StidRaw = renu.io.toD3.bits.entries(0).uop.decoded.rob.stid + val d3Stid = Mux(d3StidRaw < p.ooo.stidCount.U, d3StidRaw, 0.U) + val liveMemoryOrder = select(memoryOrder.io.provisional, d3Stid) + val liveMemoryOrderLanes = select(memoryOrder.io.provisionalLanes, d3Stid) + val stateAfterPrefix = Wire(new MemoryOrderState(p)) + stateAfterPrefix := liveMemoryOrder.after + val nextMemoryLane = Mux1H((0 until p.ooo.d3PrefixWidth).map { lane => + (renu.io.toD3.bits.count === lane.U) -> liveMemoryOrderLanes(lane) + }) + when(renu.io.toD3.bits.count < liveMemoryOrder.count) { + stateAfterPrefix.lsid := nextMemoryLane.firstLsid + stateAfterPrefix.lid := nextMemoryLane.firstLid + stateAfterPrefix.sid := nextMemoryLane.firstSid + stateAfterPrefix.yostValid := nextMemoryLane.yostValid + stateAfterPrefix.yostLsid := nextMemoryLane.yostLsid + stateAfterPrefix.yostSid := nextMemoryLane.yostSid + stateAfterPrefix.yoldValid := nextMemoryLane.yoldValid + stateAfterPrefix.yoldLsid := nextMemoryLane.yoldLsid + stateAfterPrefix.yoldLid := nextMemoryLane.yoldLid + } + val d3WithMemory = Wire(new D3RenameGroup(p)) + d3WithMemory := renu.io.toD3.bits + d3WithMemory.memoryOrder := liveMemoryOrder + d3WithMemory.memoryOrder.count := renu.io.toD3.bits.count + d3WithMemory.memoryOrder.after := stateAfterPrefix + for (lane <- 0 until p.ooo.d3PrefixWidth) { + when(lane.U < renu.io.toD3.bits.count) { + d3WithMemory.entries(lane).memoryOrder := liveMemoryOrderLanes(lane) + } + } + val d3WithPc = Wire(new D3RenameGroup(p)) + d3WithPc := d3WithMemory + for (lane <- 0 until p.ooo.d3PrefixWidth) { + when(lane.U < pcBuffer.io.prepared.count) { + d3WithPc.entries(lane).pcBufferIndexOffset := + pcBuffer.io.prepared.lanes(lane) + } + } + memoryOrder.io.publishPrepare.valid := renu.io.toD3.valid + memoryOrder.io.publishPrepare.bits := d3WithPc + rob.io.prepare.valid := renu.io.toD3.valid + rob.io.prepare.bits := d3WithPc + brob.io.prepare.valid := renu.io.toD3.valid + brob.io.prepare.bits := d3WithPc + rob.io.brobPrepared := brob.io.prepared + brob.io.robPrepared := rob.io.prepared + + val fastResultValid = Wire(Vec(p.ooo.d3PrefixWidth, Bool())) + val fastResultPrefix = Wire(Vec(p.ooo.d3PrefixWidth + 1, + UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W))) + val fastResultCandidates = Wire(Vec(p.ooo.d3PrefixWidth, + new FastWritebackTxn(p))) + fastResultPrefix(0) := 0.U + for (lane <- 0 until p.ooo.d3PrefixWidth) { + val row = d3WithPc.entries(lane) + val destinationMask = VecInit(row.uop.destinations.map { destination => + destination.valid && destination.kind === OperandKind.Gpr && + destination.ptagValid + }) + val destinationIndex = PriorityEncoder(destinationMask.asUInt) + val resultClass = row.uop.decoded.classification.fastResolveClass + fastResultValid(lane) := lane.U < d3WithPc.count && + row.uop.decoded.classification.disposition === + OooOpcodeDisposition.FastResolve.U && + (resultClass === OooFastResolveClass.ImmediateProducer.U || + resultClass === OooFastResolveClass.ControlValueProducer.U) + fastResultPrefix(lane + 1) := fastResultPrefix(lane) + + fastResultValid(lane).asUInt + fastResultCandidates(lane) := 0.U.asTypeOf(fastResultCandidates(lane)) + fastResultCandidates(lane).rob := rob.io.prepared.entries(lane).rob + fastResultCandidates(lane).epoch := + row.uop.decoded.instruction.parent.identity.epoch + fastResultCandidates(lane).destinationIndex := destinationIndex + fastResultCandidates(lane).destination := + row.uop.destinations(destinationIndex) + fastResultCandidates(lane).value := Mux( + resultClass === OooFastResolveClass.ControlValueProducer.U, + row.uop.decoded.instruction.parent.pc + + row.uop.decoded.instruction.parent.lengthBytes, + row.uop.decoded.instruction.parent.pc + row.uop.decoded.immediate) + when(renu.io.toD3.valid && fastResultValid(lane)) { + assert(PopCount(destinationMask) === 1.U && + rob.io.prepared.entries(lane).valid, + "canonical fast-result D3 rows require one exact ROB-bound P destination") + } + } + fastResult.io.prepare.valid := renu.io.toD3.valid + fastResult.io.prepare.bits := 0.U.asTypeOf(fastResult.io.prepare.bits) + fastResult.io.prepare.bits.count := fastResultPrefix.last + for (slot <- 0 until p.ooo.d3PrefixWidth) { + for (lane <- 0 until p.ooo.d3PrefixWidth) { + when(fastResultValid(lane) && fastResultPrefix(lane) === slot.U) { + fastResult.io.prepare.bits.entries(slot) := fastResultCandidates(lane) + } + } + } + val residencyPreviewReady = rob.io.prepare.ready && brob.io.prepare.ready && + pcBuffer.io.prepareReady && fastResult.io.prepareReady + val d3RecoveryFenced = earlyRecoveryValid && d3StidRaw === earlyRecoveryStid + dispatch.io.in.valid := renu.io.toD3.valid && residencyPreviewReady && + memoryOrder.io.publishReady && !d3RecoveryFenced + dispatch.io.in.bits := d3WithPc + renu.io.publicationIdentity.valid := + renu.io.toD3.valid && residencyPreviewReady + renu.io.publicationIdentity.bits := rob.io.prepared + pcBuffer.io.publicationIdentity.valid := + renu.io.toD3.valid && residencyPreviewReady + pcBuffer.io.publicationIdentity.bits := rob.io.prepared + dispatch.io.robPrepared := rob.io.prepared + dispatch.io.brobPrepared := brob.io.prepared + val d3Ready = !d3RecoveryFenced && residencyPreviewReady && + dispatch.io.in.ready && memoryOrder.io.publishReady + val d3Fire = renu.io.toD3.valid && d3Ready + renu.io.toD3.ready := d3Ready + rob.io.publishFire := d3Fire + brob.io.publishFire := d3Fire + pcBuffer.io.publishFire := d3Fire + fastResult.io.publishFire := d3Fire + memoryOrder.io.publishFire := d3Fire + rob.io.publicationTransactionBase := dispatch.io.publicationTransactionBase + when(d3Fire) { + assert(renu.io.publicationIdentity.valid, + "canonical RENU publication requires ROB-prepared full identities") + assert(pcBuffer.io.prepared.count === renu.io.toD3.bits.count && + pcBuffer.io.prepared.groupCount === renu.io.toD3.bits.groupCount, + "PC, ROB, BROB, and RENU must publish the exact same D3 prefix") + } + + for (lane <- 0 until p.ooo.d3PrefixWidth; + dest <- 0 until p.maxDestinationOperands) { + val clear = io.iex.allocationClear( + lane * p.maxDestinationOperands + dest) + val destination = d3WithPc.entries(lane).uop.destinations(dest) + clear.valid := d3Fire && lane.U < d3WithPc.count && destination.valid + clear.bits := 0.U.asTypeOf(clear.bits) + clear.bits.rob := rob.io.prepared.entries(lane).rob + clear.bits.epoch := d3WithPc.entries(lane).uop.decoded.instruction.parent + .identity.epoch + clear.bits.destination := destination + } + assert(dispatch.io.in.fire === d3Fire, + "Dispatch reservation must share the unique D3 publication fire") + + io.iex.aluDispatch <> dispatch.io.iex.aluDispatch + io.iex.bruDispatch <> dispatch.io.iex.bruDispatch + io.iex.aguDispatch <> dispatch.io.iex.aguDispatch + io.iex.storeDispatch <> dispatch.io.iex.storeDispatch + io.iex.systemDispatch <> dispatch.io.iex.systemDispatch + io.iex.cmdDispatch <> dispatch.io.iex.cmdDispatch + pcBuffer.io.readAddress := io.iex.pcBufferReadAddress + io.iex.pcBufferReadPcBase := pcBuffer.io.readPcBase + + val completionArb = Module(new Arbiter( + new RobResolveTxn(p), p.widths.issueWidth + 2)) + val fastCompletion = completionArb.io.in(0) + val fastPublish = Module(new OooFastResultAtomicPublish(p)) + fastPublish.io.source <> fastResult.io.out + io.iex.fastResult <> fastPublish.io.iex + fastCompletion <> fastPublish.io.rob + for (lane <- 0 until p.widths.issueWidth) { + completionArb.io.in(lane + 1) <> io.iex.robResolve(lane) + } + completionArb.io.in(p.widths.issueWidth + 1) <> io.storeResolve + rob.io.completion <> completionArb.io.out + + commitControl.io.rob.valid := rob.io.commit.valid + commitControl.io.rob.bits := rob.io.commit.bits + commitControl.io.residentHeads := rob.io.residentHeads + val interrupts = Wire(Vec(p.ooo.stidCount, new InterruptRequest(p))) + for (stid <- 0 until p.ooo.stidCount) { + interrupts(stid) := io.interrupt.bits + interrupts(stid).valid := io.interrupt.valid && + io.interrupt.bits.valid && io.interrupt.bits.stid === stid.U + } + commitControl.io.interrupts := interrupts + commitControl.io.debugRequest <> io.debugRequest + io.debugResponse <> commitControl.io.debugResponse + commitControl.io.interruptBoundaryValid := rob.io.commit.bits.headValid + commitControl.io.interruptBoundary := rob.io.commit.bits.head + for (stid <- 0 until p.ooo.stidCount) { + commitControl.io.recoveryFence(stid) := + (recovery.io.robPrepare.valid && + recovery.io.robPrepare.bits.trigger.stid === stid.U) || + (rob.io.recoveryPrepared.valid && + rob.io.recoveryPrepared.bits.trigger.stid === stid.U) + } + commitControl.io.robNoflushReady <> io.iex.robNoflushReady + io.iex.robNoflush <> commitControl.io.robNoflush + for (lane <- io.systemIssue.indices) { + io.systemIssue(lane) <> io.iex.systemIssue(lane) + } + + val releaseProbe = rob.io.commit.valid && rob.io.commit.bits.count =/= 0.U + pcBuffer.io.commitPreview.valid := releaseProbe + pcBuffer.io.commitPreview.bits := commitControl.io.out.bits.commit + rob.io.release.valid := releaseProbe + rob.io.release.bits := commitControl.io.out.bits.robRelease + renu.io.release.valid := releaseProbe + renu.io.release.bits := commitControl.io.out.bits.rename + brob.io.release.valid := releaseProbe + brob.io.release.bits := commitControl.io.out.bits.brobRelease + commitControl.io.robReleaseReady := rob.io.releaseReady + commitControl.io.renameReleaseReady := renu.io.releaseReady + commitControl.io.brobReleaseReady := brob.io.releaseReady + commitControl.io.pcBufferCommitReady := pcBuffer.io.commitReady + + io.commit.valid := commitControl.io.out.valid && + commitControl.io.out.bits.commit.count =/= 0.U + io.commit.bits := commitControl.io.out.bits.commit + io.trap.valid := commitControl.io.out.valid && + commitControl.io.out.bits.trap.valid + io.trap.bits := commitControl.io.out.bits.trap + private val storeAuthorization = Module( + new OooStoreCommitAuthorizationOwner(p)) + storeAuthorization.io.commit.valid := commitControl.io.out.valid + storeAuthorization.io.commit.bits := commitControl.io.out.bits.commit + io.storeCommit <> storeAuthorization.io.storeCommit + io.commit.valid := commitControl.io.out.valid && + commitControl.io.out.bits.commit.count =/= 0.U && + storeAuthorization.io.canAccept + io.trap.valid := commitControl.io.out.valid && + commitControl.io.out.bits.trap.valid && storeAuthorization.io.canAccept + commitControl.io.out.ready := storeAuthorization.io.canAccept && + (!io.commit.valid || io.commit.ready) && (!io.trap.valid || io.trap.ready) + val commitFire = commitControl.io.out.fire + storeAuthorization.io.applied := commitFire + val releaseFire = OOOCommitApplyPolicy.releaseFire( + commitFire, commitControl.io.out.bits.commit.count) + rob.io.commit.ready := true.B + rob.io.commitApply := commitFire + rob.io.releaseApply := releaseFire + renu.io.releaseApply := releaseFire + brob.io.releaseApply := releaseFire + pcBuffer.io.commitApply := releaseFire + when(releaseFire) { + assert(rob.io.releaseReady && renu.io.releaseReady && brob.io.releaseReady && + pcBuffer.io.commitReady, + "canonical commit must atomically apply every owner release") + assert(commitControl.io.out.bits.rename.count === + commitControl.io.out.bits.commit.count) + assert(commitControl.io.out.bits.robRelease.count === + commitControl.io.out.bits.commit.count) + assert(commitControl.io.out.bits.brobRelease.count === + commitControl.io.out.bits.commit.count) + for (lane <- 0 until p.widths.retireWidth) { + when(lane.U < commitControl.io.out.bits.commit.count) { + val identity = commitControl.io.out.bits.commit.entries(lane).rob + assert(commitControl.io.out.bits.rename.lanes(lane).rob.asUInt === + identity.asUInt, + "canonical rename release must use the retained commit identity") + assert(commitControl.io.out.bits.robRelease.lanes(lane).rob.asUInt === + identity.asUInt, + "canonical ROB release must use the retained commit identity") + assert(commitControl.io.out.bits.brobRelease.entries(lane).asUInt === + identity.asUInt, + "canonical BROB release must use the retained commit identity") + } + } + } + + recovery.io.events(0) <> io.iex.recoveryEvent + recovery.io.events(1).valid := false.B + recovery.io.events(1).bits := 0.U.asTypeOf(recovery.io.events(1).bits) + recovery.io.interrupts := interrupts + recovery.io.interruptBoundaryValid := rob.io.commit.bits.headValid + recovery.io.interruptBoundary := rob.io.commit.bits.head + recovery.io.abort := false.B + rob.io.recoveryCandidate := recovery.io.robCandidate + recovery.io.robCandidateStatus := rob.io.recoveryCandidateStatus + rob.io.recoveryPrepare.valid := recovery.io.robPrepare.valid + rob.io.recoveryPrepare.bits := recovery.io.robPrepare.bits + recovery.io.robPrepare.ready := rob.io.recoveryPrepare.ready + memoryOrder.io.recoveryPrepare.valid := rob.io.recoveryPrepared.valid + memoryOrder.io.recoveryPrepare.bits := rob.io.memoryRecoveryPrepared + recovery.io.robPrepared.valid := rob.io.recoveryPrepared.valid && + memoryOrder.io.recoveryPrepareReady + recovery.io.robPrepared.bits := rob.io.recoveryPrepared.bits + rob.io.recoveryAbort := recovery.io.robAbort + rob.io.recoveryApply.valid := recovery.io.targets(0).apply.valid + rob.io.recoveryApply.bits := recovery.io.targets(0).apply.bits + memoryOrder.io.recoveryFire := recovery.io.targets(0).apply.valid && + RecoveryPlanContract.sameTransactionIgnoringPhase( + recovery.io.targets(0).apply.bits, rob.io.recoveryPrepared.bits) + when(rob.io.recoveryPrepared.valid) { + assert(memoryOrder.io.recoveryPrepareReady, + "ROB recovery memory snapshots must match the live OOO serial tail") + } + + private def connectTarget( + controller: RecoveryTargetIO, + target: RecoveryTargetIO): Unit = { + target.prepare.valid := controller.prepare.valid + target.prepare.bits := controller.prepare.bits + controller.prepare.ready := target.prepare.ready + controller.prepared.valid := target.prepared.valid + controller.prepared.bits := target.prepared.bits + target.prepared.ready := controller.prepared.ready + target.apply.valid := controller.apply.valid + target.apply.bits := controller.apply.bits + target.abort.valid := controller.abort.valid + target.abort.bits := controller.abort.bits + } + + connectTarget(recovery.io.targets(0), io.recoveryToD1) + connectTarget(recovery.io.targets(1), renu.io.recovery) + brob.io.recoveryPrepare.valid := recovery.io.targets(2).prepare.valid + brob.io.recoveryPrepare.bits := recovery.io.targets(2).prepare.bits + recovery.io.targets(2).prepare.ready := brob.io.recoveryPrepare.ready + recovery.io.targets(2).prepared.valid := brob.io.recoveryPrepared.valid + recovery.io.targets(2).prepared.bits := brob.io.recoveryPrepared.bits + brob.io.recoveryApply := recovery.io.targets(2).apply + brob.io.recoveryAbort := recovery.io.targets(2).abort + connectTarget(recovery.io.targets(3), pcBuffer.io.recovery) + connectTarget(recovery.io.targets(4), dispatch.io.recovery) + connectTarget(recovery.io.targets(5), fastResult.io.recovery) + connectTarget(recovery.io.targets(6), io.iex.recovery) + connectTarget(recovery.io.targets(7), io.recoveryToIfu) + connectTarget(recovery.io.targets(8), io.recoveryToCtu) + connectTarget(recovery.io.targets(9), io.recoveryToLsu) + + io.trace.valid := false.B + io.trace.bits := 0.U.asTypeOf(io.trace.bits) +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooBrob.scala b/chisel/src/main/scala/linxcore/ooo/OooBrob.scala deleted file mode 100644 index 817368b5..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooBrob.scala +++ /dev/null @@ -1,631 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, PriorityEncoder, Valid} - -class OooBrobIO(val p: OooParams = OooParams()) extends Bundle { - val prepare = Flipped(Valid(new OooD3GroupedReservation(p))) - val prepared = Output(new OooBrobPreparedBindings(p)) - val prepareReady = Output(Bool()) - val publishFire = Input(Bool()) - val commit = Flipped(Decoupled(new OooRobCommitBatch(p))) - val recoveryPrepare = Flipped(Valid(new OooRobRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooBrobRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - - val prepareRejected = Valid(new OooBrobPrepareReject(p)) - val commitRejected = Valid(new OooBrobCommitReject(p)) - val recoveryRejected = Valid(new OooBrobRecoveryReject(p)) - val usedBlocks = Output(Vec(p.stidCount, UInt(p.brobCountWidth.W))) - val head = Output(Vec(p.stidCount, new BrobPointer(p))) - val tail = Output(Vec(p.stidCount, new BrobPointer(p))) - val currentValid = Output(Vec(p.stidCount, Bool())) - val current = Output(Vec(p.stidCount, new BrobPointer(p))) -} - -/** Per-STID block reorder buffer. - * - * `prepare` is a side-effect-free view of the retained D3 row. The caller may - * use `prepared.pointers` to form S1 bindings only while `prepareReady` is - * true. State changes exactly once on the shared `publishFire`; commit changes - * BROB state only on the same retained ROB commit handshake. - */ -class OooBrob(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooBrobIO(p)) - - val table = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.brobEntriesPerStid)( - 0.U.asTypeOf(new OooBrobEntry(p))))))) - val usedBlocks = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.brobCountWidth.W)))) - val headSlot = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.nativeBidWidth.W)))) - val headGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.brobGenerationWidth.W)))) - val tailSlot = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.nativeBidWidth.W)))) - val tailGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.brobGenerationWidth.W)))) - val currentValid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val currentPointer = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new BrobPointer(p))))) - - val recoveryPlan = io.recoveryPrepare.bits - val recoveryStid = recoveryPlan.request.rename.key.member.group.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryTargetsStid = io.recoveryPrepare.valid && - recoveryPlan.valid && recoveryStidInRange - - val prepareStid = io.prepare.bits.transaction.plan.stid - val prepareStidInRange = prepareStid < p.stidCount.U - val safePrepareStid = Mux(prepareStidInRange, prepareStid, 0.U) - val prepareGroupCount = io.prepare.bits.transaction.plan.groupCount - val prepareGroupCountInRange = prepareGroupCount.orR && - prepareGroupCount <= p.instructionDecodeWidth.U - val expectedPrepareMask = - ((1.U((p.instructionDecodeWidth + 1).W) << prepareGroupCount) - 1.U)( - p.instructionDecodeWidth - 1, 0) - - val scanCurrentValid = Wire(Vec(p.instructionDecodeWidth + 1, Bool())) - val scanCurrent = Wire(Vec(p.instructionDecodeWidth + 1, new BrobPointer(p))) - val scanAllocCount = Wire(Vec(p.instructionDecodeWidth + 1, UInt(p.robGroupCountWidth.W))) - val scanLegal = Wire(Vec(p.instructionDecodeWidth, Bool())) - val groupPointers = Wire(Vec(p.instructionDecodeWidth, new BrobPointer(p))) - val newBlock = Wire(Vec(p.instructionDecodeWidth, Bool())) - val implicitClose = Wire(Vec(p.instructionDecodeWidth, Bool())) - val implicitClosePointers = Wire(Vec(p.instructionDecodeWidth, new BrobPointer(p))) - - scanCurrentValid(0) := currentValid(safePrepareStid) - scanCurrent(0) := currentPointer(safePrepareStid) - scanAllocCount(0) := 0.U - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = io.prepare.bits.transaction.groups(groupIndex) - val active = groupIndex.U < prepareGroupCount - val allocate = active && group.boundaryStart - val tailSum = tailSlot(safePrepareStid) +& scanAllocCount(groupIndex) - val tailWrap = tailSum >= p.brobEntriesPerStid.U - val allocatedPointer = Wire(new BrobPointer(p)) - allocatedPointer.valid := true.B - allocatedPointer.bid.valid := true.B - allocatedPointer.bid.value := tailSum(p.nativeBidWidth - 1, 0) - allocatedPointer.generation := tailGeneration(safePrepareStid) + tailWrap.asUInt - - newBlock(groupIndex) := allocate - implicitClose(groupIndex) := allocate && scanCurrentValid(groupIndex) - implicitClosePointers(groupIndex) := scanCurrent(groupIndex) - groupPointers(groupIndex) := Mux(allocate, allocatedPointer, scanCurrent(groupIndex)) - scanLegal(groupIndex) := Mux( - active, - group.valid && group.key.valid && - group.key.peId === io.prepare.bits.transaction.plan.peId && - group.key.stid === prepareStid && - (allocate || scanCurrentValid(groupIndex)) && groupPointers(groupIndex).valid && - groupPointers(groupIndex).bid.valid, - !group.valid) - scanCurrentValid(groupIndex + 1) := Mux( - active, - !group.boundaryStop, - scanCurrentValid(groupIndex)) - scanCurrent(groupIndex + 1) := Mux( - active, - groupPointers(groupIndex), - scanCurrent(groupIndex)) - scanAllocCount(groupIndex + 1) := - scanAllocCount(groupIndex) + allocate.asUInt - } - - val allocatedBlocks = scanAllocCount(p.instructionDecodeWidth) - val tailAfterSum = tailSlot(safePrepareStid) +& allocatedBlocks - val tailAfterWrap = tailAfterSum >= p.brobEntriesPerStid.U - val freeBlocks = p.brobEntriesPerStid.U(p.brobCountWidth.W) - usedBlocks(safePrepareStid) - val prepareHasCapacity = freeBlocks >= allocatedBlocks - val newTargetsFree = (0 until p.instructionDecodeWidth).map { groupIndex => - !newBlock(groupIndex) || - !table(safePrepareStid)(groupPointers(groupIndex).bid.value).valid - }.reduce(_ && _) - val liveCurrentExact = !currentValid(safePrepareStid) || { - val row = table(safePrepareStid)(currentPointer(safePrepareStid).bid.value) - row.valid && row.pointer.asUInt === currentPointer(safePrepareStid).asUInt && - row.peId === io.prepare.bits.transaction.plan.peId - } - val commitStid = io.commit.bits.release.firstGroup.stid - val exactCommitConflict = Wire(Bool()) - val prepareExact = prepareStidInRange && prepareGroupCountInRange && - io.prepare.bits.transaction.groupMask === expectedPrepareMask && - io.prepare.bits.transaction.plan.peId === io.prepare.bits.transaction.decoded.peId && - io.prepare.bits.transaction.plan.stid === io.prepare.bits.transaction.decoded.stid && - io.prepare.bits.transaction.plan.epoch === io.prepare.bits.transaction.decoded.epoch && - scanLegal.reduce(_ && _) && prepareHasCapacity && newTargetsFree && liveCurrentExact - - io.prepared := 0.U.asTypeOf(io.prepared) - io.prepared.validMask := expectedPrepareMask - io.prepared.pointers := groupPointers - io.prepared.newBlockMask := newBlock.asUInt - io.prepared.implicitCloseMask := implicitClose.asUInt - io.prepared.implicitClosePointers := implicitClosePointers - io.prepared.allocatedBlocks := allocatedBlocks - io.prepared.tailAfter.valid := true.B - io.prepared.tailAfter.bid.valid := true.B - io.prepared.tailAfter.bid.value := tailAfterSum(p.nativeBidWidth - 1, 0) - io.prepared.tailAfter.generation := tailGeneration(safePrepareStid) + tailAfterWrap.asUInt - io.prepared.currentAfterValid := scanCurrentValid(p.instructionDecodeWidth) - io.prepared.currentAfter := scanCurrent(p.instructionDecodeWidth) - val recoveryBlocksPrepare = recoveryTargetsStid && - prepareStid === recoveryStid - io.prepareReady := prepareExact && !exactCommitConflict && - !recoveryBlocksPrepare - io.prepareRejected.valid := io.prepare.valid && !io.prepareReady - io.prepareRejected.bits.stid := prepareStid - io.prepareRejected.bits.transactionId := io.prepare.bits.transaction.plan.transactionId - io.prepareRejected.bits.groupMask := io.prepare.bits.transaction.groupMask - - val commitGroupCount = io.commit.bits.release.groupCount - val commitStidInRange = commitStid < p.stidCount.U - val safeCommitStid = Mux(commitStidInRange, commitStid, 0.U) - val commitCountInRange = commitGroupCount.orR && commitGroupCount <= p.retireGroupWidth.U - val headPointer = Wire(new BrobPointer(p)) - headPointer.valid := usedBlocks(safeCommitStid).orR - headPointer.bid.valid := headPointer.valid - headPointer.bid.value := headSlot(safeCommitStid) - headPointer.generation := headGeneration(safeCommitStid) - - val commitGroupExact = Wire(Vec(p.retireGroupWidth, Bool())) - for (groupIndex <- 0 until p.retireGroupWidth) { - val active = groupIndex.U < commitGroupCount - val group = io.commit.bits.groups(groupIndex) - val row = table(safeCommitStid)(group.brob.bid.value) - val liveExact = group.valid && group.key.valid && group.key.stid === commitStid && - group.brob.valid && group.brob.bid.valid && row.valid && - row.pointer.asUInt === group.brob.asUInt && row.peId === group.key.peId && - row.stid === commitStid - val startsEntryPrefix = if (groupIndex == 0) { - true.B - } else { - group.brob.asUInt =/= io.commit.bits.groups(groupIndex - 1).brob.asUInt - } - val priorGroupSequential = if (groupIndex == 0) { - true.B - } else { - val priorKey = io.commit.bits.groups(groupIndex - 1).key - val nextRidSum = priorKey.ridSlot +& 1.U - val nextRidWrap = nextRidSum >= p.robGroupsPerStid.U - group.key.valid && priorKey.valid && group.key.peId === priorKey.peId && - group.key.stid === priorKey.stid && - group.key.ridSlot === nextRidSum(p.ridSlotWidth - 1, 0) && - group.key.ridGeneration === priorKey.ridGeneration + nextRidWrap.asUInt - } - val entryPrefixExact = !startsEntryPrefix || - (row.nextCommitRobGroup.valid && - row.nextCommitRobGroup.asUInt === group.key.asUInt) - val orderExact = if (groupIndex == 0) { - val headRow = table(safeCommitStid)(headPointer.bid.value) - val nextSum = headPointer.bid.value +& 1.U - val nextWrap = nextSum >= p.brobEntriesPerStid.U - val closesEmptyHead = headRow.valid && headRow.closed && - headRow.liveRobGroups === 0.U && headRow.closeOwnerValid && - headRow.closeOwner.asUInt === group.key.asUInt && group.boundaryStart && - group.brob.bid.value === nextSum(p.nativeBidWidth - 1, 0) && - group.brob.generation === headPointer.generation + nextWrap.asUInt - group.brob.asUInt === headPointer.asUInt || closesEmptyHead - } else { - val prior = io.commit.bits.groups(groupIndex - 1) - val nextSum = prior.brob.bid.value +& 1.U - val nextWrap = nextSum >= p.brobEntriesPerStid.U - val sameBlock = group.brob.asUInt === prior.brob.asUInt && - !group.boundaryStart && !prior.boundaryStop - val nextBlock = group.boundaryStart && group.brob.valid && group.brob.bid.valid && - group.brob.bid.value === nextSum(p.nativeBidWidth - 1, 0) && - group.brob.generation === prior.brob.generation + nextWrap.asUInt - sameBlock || nextBlock - } - commitGroupExact(groupIndex) := Mux( - active, - liveExact && orderExact && priorGroupSequential && entryPrefixExact, - !group.valid) - } - - val retireHitsBySlot = Wire(Vec(p.brobEntriesPerStid, UInt(p.robReleaseCountWidth.W))) - for (slot <- 0 until p.brobEntriesPerStid) { - retireHitsBySlot(slot) := PopCount((0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitGroupCount && - io.commit.bits.groups(groupIndex).brob.bid.value === slot.U && - io.commit.bits.groups(groupIndex).brob.generation === table(safeCommitStid)(slot).pointer.generation - }) - } - val retireCountsLegal = (0 until p.brobEntriesPerStid).map { slot => - retireHitsBySlot(slot) <= table(safeCommitStid)(slot).liveRobGroups - }.reduce(_ && _) - - val freePrefix = Wire(Vec(p.retireGroupWidth + 1, UInt(p.robReleaseCountWidth.W))) - freePrefix(0) := 0.U - for (offset <- 0 until p.retireGroupWidth) { - val pointerSum = headSlot(safeCommitStid) +& offset.U - val pointerWrap = pointerSum >= p.brobEntriesPerStid.U - val slot = pointerSum(p.nativeBidWidth - 1, 0) - val row = table(safeCommitStid)(slot) - val hits = retireHitsBySlot(slot) - val closeOwnerCommits = (0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitGroupCount && row.closeOwnerValid && - io.commit.bits.groups(groupIndex).key.asUInt === row.closeOwner.asUInt - }.reduce(_ || _) - val exactPointer = row.pointer.valid && row.pointer.bid.valid && - row.pointer.bid.value === slot && - row.pointer.generation === headGeneration(safeCommitStid) + pointerWrap.asUInt - val becomesEmpty = row.valid && row.closed && - (row.closeCommitted || closeOwnerCommits) && hits === row.liveRobGroups - val extend = freePrefix(offset) === offset.U && exactPointer && becomesEmpty - freePrefix(offset + 1) := Mux(extend, (offset + 1).U, freePrefix(offset)) - } - val freedBlocks = freePrefix(p.retireGroupWidth) - val releaseHeaderExact = io.commit.bits.release.firstGroup.valid && - io.commit.bits.groups(0).valid && - io.commit.bits.release.firstGroup.asUInt === io.commit.bits.groups(0).key.asUInt - val commitExact = commitStidInRange && commitCountInRange && - usedBlocks(safeCommitStid).orR && commitGroupExact.reduce(_ && _) && - retireCountsLegal && releaseHeaderExact - val recoveryKilledActive = Wire(Vec(p.robGroupsPerStid, Bool())) - val recoveryKilledRowsExact = Wire(Vec(p.robGroupsPerStid, Bool())) - val recoveryAllocatedMask = Wire(Vec(p.robGroupsPerStid, Bool())) - for (killedIndex <- 0 until p.robGroupsPerStid) { - val group = recoveryPlan.killedGroups(killedIndex) - val active = killedIndex.U < recoveryPlan.killedGroupCount - val row = table(safeRecoveryStid)(group.brob.bid.value) - recoveryKilledActive(killedIndex) := active - recoveryAllocatedMask(killedIndex) := active && group.brobAllocated - recoveryKilledRowsExact(killedIndex) := - recoveryPlan.killedGroupMask(killedIndex) === active && (!active || ( - group.valid && group.key.valid && group.key.stid === recoveryStid && - group.brob.valid && group.brob.bid.valid && row.valid && - row.stid === recoveryStid && row.peId === group.key.peId && - row.pointer.asUInt === group.brob.asUInt && - (!group.brobAllocated || - (group.boundaryStart && - row.firstRobGroup.asUInt === group.key.asUInt)) && - (!group.brobImplicitCloseValid || - (group.brobAllocated && - table(safeRecoveryStid)(group.brobImplicitClose.bid.value) - .valid && - table(safeRecoveryStid)(group.brobImplicitClose.bid.value) - .pointer.asUInt === group.brobImplicitClose.asUInt)))) - } - val recoveryFreedBlocks = PopCount(recoveryAllocatedMask) - val recoveryFirstAllocatedIndex = PriorityEncoder( - recoveryAllocatedMask.asUInt) - val recoveryFirstAllocated = recoveryPlan.killedGroups( - recoveryFirstAllocatedIndex).brob - val recoveryAllocationPrefix = Wire(Vec(p.robGroupsPerStid + 1, - UInt(p.brobCountWidth.W))) - recoveryAllocationPrefix(0) := 0.U - val recoveryAllocatedOrderExact = Wire(Vec(p.robGroupsPerStid, Bool())) - for (killedIndex <- 0 until p.robGroupsPerStid) { - val group = recoveryPlan.killedGroups(killedIndex) - val expectedSum = recoveryFirstAllocated.bid.value +& - recoveryAllocationPrefix(killedIndex) - val expectedWrap = expectedSum >= p.brobEntriesPerStid.U - recoveryAllocatedOrderExact(killedIndex) := - !recoveryAllocatedMask(killedIndex) || ( - group.brob.bid.value === - expectedSum(p.nativeBidWidth - 1, 0) && - group.brob.generation === - recoveryFirstAllocated.generation + expectedWrap.asUInt) - recoveryAllocationPrefix(killedIndex + 1) := - recoveryAllocationPrefix(killedIndex) + - recoveryAllocatedMask(killedIndex).asUInt - } - val recoveryLiveTail = Wire(new BrobPointer(p)) - recoveryLiveTail.valid := true.B - recoveryLiveTail.bid.valid := true.B - recoveryLiveTail.bid.value := tailSlot(safeRecoveryStid) - recoveryLiveTail.generation := tailGeneration(safeRecoveryStid) - val recoveryTailEndSum = recoveryFirstAllocated.bid.value +& - recoveryFreedBlocks - val recoveryTailEndWrap = - recoveryTailEndSum >= p.brobEntriesPerStid.U - val recoveryTailSuffixExact = Mux( - recoveryFreedBlocks.orR, - recoveryFirstAllocated.valid && recoveryFirstAllocated.bid.valid && - recoveryAllocatedOrderExact.reduce(_ && _) && - recoveryLiveTail.bid.value === - recoveryTailEndSum(p.nativeBidWidth - 1, 0) && - recoveryLiveTail.generation === - recoveryFirstAllocated.generation + recoveryTailEndWrap.asUInt && - usedBlocks(safeRecoveryStid) >= recoveryFreedBlocks, - true.B) - val recoveryTailAfter = Mux(recoveryFreedBlocks.orR, - recoveryFirstAllocated, recoveryLiveTail) - val recoveryFirstKilled = recoveryPlan.killedGroups(0) - val recoveryCurrentAfterValid = Mux( - recoveryPlan.survivingTailValid, - !recoveryPlan.survivingTail.boundaryStop, - Mux(recoveryFirstKilled.brobAllocated, - recoveryFirstKilled.brobImplicitCloseValid, - true.B)) - val recoveryCurrentAfter = Mux( - recoveryPlan.survivingTailValid, - recoveryPlan.survivingTail.brob, - Mux(recoveryFirstKilled.brobAllocated, - recoveryFirstKilled.brobImplicitClose, - recoveryFirstKilled.brob)) - val recoveryCurrentRow = table(safeRecoveryStid)( - recoveryCurrentAfter.bid.value) - val recoveryCurrentAfterExact = !recoveryCurrentAfterValid || ( - recoveryCurrentAfter.valid && recoveryCurrentAfter.bid.valid && - recoveryCurrentRow.valid && - recoveryCurrentRow.stid === recoveryStid && - recoveryCurrentRow.pointer.asUInt === recoveryCurrentAfter.asUInt) - val recoveryHitsBySlot = Wire(Vec(p.brobEntriesPerStid, - UInt(p.nonFlushPrefixCountWidth.W))) - val recoveryHitCountsLegal = Wire(Vec(p.brobEntriesPerStid, Bool())) - for (slot <- 0 until p.brobEntriesPerStid) { - recoveryHitsBySlot(slot) := PopCount((0 until p.robGroupsPerStid).map { - killedIndex => recoveryKilledActive(killedIndex) && - recoveryPlan.killedGroups(killedIndex).brob.bid.value === slot.U && - recoveryPlan.killedGroups(killedIndex).brob.generation === - table(safeRecoveryStid)(slot).pointer.generation - }) - recoveryHitCountsLegal(slot) := - recoveryHitsBySlot(slot) <= - table(safeRecoveryStid)(slot).liveRobGroups - } - val recoveryShapeExact = recoveryPlan.valid && recoveryStidInRange && - recoveryPlan.oldOccupied.orR && - recoveryPlan.killedGroupCount === - recoveryPlan.oldOccupied - recoveryPlan.newOccupied && - recoveryPlan.survivingTailValid === recoveryPlan.newOccupied.orR && - (!recoveryPlan.survivingTailValid || - (recoveryPlan.survivingTail.valid && - recoveryPlan.survivingTail.key.stid === recoveryStid && - recoveryPlan.survivingTail.brob.valid && - recoveryPlan.survivingTail.brob.bid.valid)) - val recoveryExact = recoveryShapeExact && - recoveryKilledRowsExact.reduce(_ && _) && - recoveryTailSuffixExact && recoveryCurrentAfterExact && - recoveryHitCountsLegal.reduce(_ && _) - val recoveryCommitConflict = io.commit.valid && commitExact && - commitStid === recoveryStid - io.recoveryPrepareReady := io.recoveryPrepare.valid && recoveryExact && - !recoveryCommitConflict - io.recoveryPrepared.valid := io.recoveryPrepareReady - io.recoveryPrepared.stid := recoveryStid - io.recoveryPrepared.freedBlocks := recoveryFreedBlocks - io.recoveryPrepared.tailAfter := recoveryTailAfter - io.recoveryPrepared.currentAfterValid := recoveryCurrentAfterValid - io.recoveryPrepared.currentAfter := recoveryCurrentAfter - io.recoveryRejected.valid := io.recoveryPrepare.valid && !recoveryExact - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.liveTail := recoveryLiveTail - io.recoveryRejected.bits.usedBlocks := usedBlocks(safeRecoveryStid) - io.recoveryRejected.bits.killedRowsExact := - recoveryKilledRowsExact.reduce(_ && _) - io.recoveryRejected.bits.tailSuffixExact := recoveryTailSuffixExact - io.recoveryRejected.bits.currentAfterExact := recoveryCurrentAfterExact - // One exact same-STID commit wins this cycle. Invalid retained commits report - // rejection but cannot starve a prepare; different STIDs remain concurrent. - exactCommitConflict := io.commit.valid && commitExact && prepareStidInRange && - commitStid === prepareStid - io.commit.ready := commitExact && - !(recoveryTargetsStid && commitStid === recoveryStid) - val commitFire = io.commit.valid && io.commit.ready - io.commitRejected.valid := io.commit.valid && !io.commit.ready - io.commitRejected.bits.requested := io.commit.bits - io.commitRejected.bits.head := headPointer - - val publishFire = io.publishFire && io.prepare.valid && io.prepareReady - when(io.publishFire) { - assert(io.prepare.valid && io.prepareReady, - "BROB publish must use the exact accepted prepare view") - } - - for (stid <- 0 until p.stidCount) { - val publishHere = publishFire && prepareStid === stid.U - val commitHere = commitFire && commitStid === stid.U - when(publishHere) { - usedBlocks(stid) := usedBlocks(stid) + allocatedBlocks - tailSlot(stid) := tailAfterSum(p.nativeBidWidth - 1, 0) - tailGeneration(stid) := tailGeneration(stid) + tailAfterWrap.asUInt - currentValid(stid) := io.prepared.currentAfterValid - currentPointer(stid) := io.prepared.currentAfter - } - when(commitHere) { - val headSum = headSlot(stid) +& freedBlocks - val headWrap = headSum >= p.brobEntriesPerStid.U - usedBlocks(stid) := usedBlocks(stid) - freedBlocks - headSlot(stid) := headSum(p.nativeBidWidth - 1, 0) - headGeneration(stid) := headGeneration(stid) + headWrap.asUInt - } - } - - for (stid <- 0 until p.stidCount; slot <- 0 until p.brobEntriesPerStid) { - val publishHere = publishFire && prepareStid === stid.U - val matchingGroups = VecInit((0 until p.instructionDecodeWidth).map { groupIndex => - groupIndex.U < prepareGroupCount && - groupPointers(groupIndex).bid.value === slot.U && - groupPointers(groupIndex).generation === - Mux(newBlock(groupIndex), groupPointers(groupIndex).generation, table(stid)(slot).pointer.generation) - }) - val groupHits = PopCount(matchingGroups) - val newHit = (0 until p.instructionDecodeWidth).map { groupIndex => - matchingGroups(groupIndex) && newBlock(groupIndex) - }.reduce(_ || _) - val closeHit = (0 until p.instructionDecodeWidth).map { groupIndex => - (matchingGroups(groupIndex) && - io.prepare.bits.transaction.groups(groupIndex).boundaryStop) || - (implicitClose(groupIndex) && - implicitClosePointers(groupIndex).bid.value === slot.U && - implicitClosePointers(groupIndex).generation === table(stid)(slot).pointer.generation) - }.reduce(_ || _) - val closeOwner = Wire(new RobGroupKey(p)) - closeOwner := 0.U.asTypeOf(closeOwner) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - when((matchingGroups(groupIndex) && - io.prepare.bits.transaction.groups(groupIndex).boundaryStop) || - (implicitClose(groupIndex) && - implicitClosePointers(groupIndex).bid.value === slot.U && - implicitClosePointers(groupIndex).generation === table(stid)(slot).pointer.generation)) { - closeOwner := io.prepare.bits.transaction.groups(groupIndex).key - } - } - val firstGroupIndex = PriorityEncoder(matchingGroups.asUInt) - val lastGroup = Wire(new RobGroupKey(p)) - lastGroup := 0.U.asTypeOf(lastGroup) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - when(matchingGroups(groupIndex)) { - lastGroup := io.prepare.bits.transaction.groups(groupIndex).key - } - } - - val retireHits = Mux(commitStid === stid.U, retireHitsBySlot(slot), 0.U) - val commitHere = commitFire && commitStid === stid.U - val closeOwnerCommits = (0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitGroupCount && table(stid)(slot).closeOwnerValid && - io.commit.bits.groups(groupIndex).key.asUInt === table(stid)(slot).closeOwner.asUInt - }.reduce(_ || _) - val lastRetiredGroup = Wire(new RobGroupKey(p)) - lastRetiredGroup := 0.U.asTypeOf(lastRetiredGroup) - for (groupIndex <- 0 until p.retireGroupWidth) { - when(groupIndex.U < commitGroupCount && - io.commit.bits.groups(groupIndex).brob.bid.value === slot.U && - io.commit.bits.groups(groupIndex).brob.generation === - table(stid)(slot).pointer.generation) { - lastRetiredGroup := io.commit.bits.groups(groupIndex).key - } - } - val freedHere = (0 until p.retireGroupWidth).map { offset => - val pointerSum = headSlot(stid) +& offset.U - val pointerWrap = pointerSum >= p.brobEntriesPerStid.U - offset.U < freedBlocks && pointerSum(p.nativeBidWidth - 1, 0) === slot.U && - table(stid)(slot).pointer.generation === headGeneration(stid) + pointerWrap.asUInt - }.reduce(_ || _) - - when(publishHere && groupHits.orR) { - when(newHit) { - table(stid)(slot).valid := true.B - table(stid)(slot).pointer := groupPointers(firstGroupIndex) - table(stid)(slot).peId := io.prepare.bits.transaction.plan.peId - table(stid)(slot).stid := stid.U - table(stid)(slot).firstRobGroup := - io.prepare.bits.transaction.groups(firstGroupIndex).key - table(stid)(slot).nextCommitRobGroup := - io.prepare.bits.transaction.groups(firstGroupIndex).key - table(stid)(slot).liveRobGroups := groupHits - }.otherwise { - table(stid)(slot).liveRobGroups := table(stid)(slot).liveRobGroups + groupHits - } - table(stid)(slot).lastRobGroup := lastGroup - table(stid)(slot).closed := Mux(newHit, closeHit, table(stid)(slot).closed || closeHit) - when(closeHit) { - table(stid)(slot).closeOwnerValid := true.B - table(stid)(slot).closeOwner := closeOwner - table(stid)(slot).closeCommitted := false.B - } - }.elsewhen(publishHere && closeHit) { - table(stid)(slot).closed := true.B - table(stid)(slot).closeOwnerValid := true.B - table(stid)(slot).closeOwner := closeOwner - table(stid)(slot).closeCommitted := false.B - } - when(commitHere && retireHits.orR) { - val nextRidSum = lastRetiredGroup.ridSlot +& 1.U - val nextRidWrap = nextRidSum >= p.robGroupsPerStid.U - table(stid)(slot).liveRobGroups := table(stid)(slot).liveRobGroups - retireHits - table(stid)(slot).nextCommitRobGroup.valid := true.B - table(stid)(slot).nextCommitRobGroup.peId := lastRetiredGroup.peId - table(stid)(slot).nextCommitRobGroup.stid := lastRetiredGroup.stid - table(stid)(slot).nextCommitRobGroup.ridSlot := - nextRidSum(p.ridSlotWidth - 1, 0) - table(stid)(slot).nextCommitRobGroup.ridGeneration := - lastRetiredGroup.ridGeneration + nextRidWrap.asUInt - } - when(commitHere && closeOwnerCommits) { - table(stid)(slot).closeCommitted := true.B - } - when(commitHere && freedHere) { - table(stid)(slot) := 0.U.asTypeOf(new OooBrobEntry(p)) - } - } - - val recoveryApply = io.recoveryFire && io.recoveryPrepareReady - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady && - io.recoveryPrepared.valid, - "BROB recovery fire requires the same exact prepared suffix") - } - when(recoveryApply) { - usedBlocks(safeRecoveryStid) := - usedBlocks(safeRecoveryStid) - recoveryFreedBlocks - tailSlot(safeRecoveryStid) := recoveryTailAfter.bid.value - tailGeneration(safeRecoveryStid) := recoveryTailAfter.generation - currentValid(safeRecoveryStid) := recoveryCurrentAfterValid - currentPointer(safeRecoveryStid) := Mux( - recoveryCurrentAfterValid, - recoveryCurrentAfter, - 0.U.asTypeOf(new BrobPointer(p))) - } - for (slot <- 0 until p.brobEntriesPerStid) { - val killedInSlot = VecInit((0 until p.robGroupsPerStid).map { - killedIndex => recoveryKilledActive(killedIndex) && - recoveryPlan.killedGroups(killedIndex).brob.bid.value === slot.U && - recoveryPlan.killedGroups(killedIndex).brob.generation === - table(safeRecoveryStid)(slot).pointer.generation - }) - val firstKilledIndex = PriorityEncoder(killedInSlot.asUInt) - val firstKilledKey = recoveryPlan.killedGroups(firstKilledIndex).key - val priorSlot = Mux(firstKilledKey.ridSlot === 0.U, - (p.robGroupsPerStid - 1).U, - firstKilledKey.ridSlot - 1.U) - val priorGeneration = Mux(firstKilledKey.ridSlot === 0.U, - firstKilledKey.ridGeneration - 1.U, - firstKilledKey.ridGeneration) - val priorKey = Wire(new RobGroupKey(p)) - priorKey.valid := killedInSlot.asUInt.orR - priorKey.peId := firstKilledKey.peId - priorKey.stid := firstKilledKey.stid - priorKey.ridSlot := priorSlot - priorKey.ridGeneration := priorGeneration - val closeOwnerKilled = table(safeRecoveryStid)(slot).closeOwnerValid && - ((0 until p.robGroupsPerStid).map { killedIndex => - recoveryKilledActive(killedIndex) && - recoveryPlan.killedGroups(killedIndex).key.asUInt === - table(safeRecoveryStid)(slot).closeOwner.asUInt - }.reduce(_ || _) || - (recoveryPlan.survivingPivotValid && - recoveryPlan.pivot.boundaryStop && - !recoveryPlan.survivingPivot.boundaryStop && - recoveryPlan.pivot.key.asUInt === - table(safeRecoveryStid)(slot).closeOwner.asUInt)) - val freedHere = (0 until p.robGroupsPerStid).map { killedIndex => - recoveryAllocatedMask(killedIndex) && - recoveryPlan.killedGroups(killedIndex).brob.bid.value === slot.U && - recoveryPlan.killedGroups(killedIndex).brob.generation === - table(safeRecoveryStid)(slot).pointer.generation - }.reduce(_ || _) - when(recoveryApply && recoveryHitsBySlot(slot).orR) { - table(safeRecoveryStid)(slot).liveRobGroups := - table(safeRecoveryStid)(slot).liveRobGroups - - recoveryHitsBySlot(slot) - table(safeRecoveryStid)(slot).lastRobGroup := priorKey - } - when(recoveryApply && closeOwnerKilled && !freedHere) { - table(safeRecoveryStid)(slot).closed := false.B - table(safeRecoveryStid)(slot).closeOwnerValid := false.B - table(safeRecoveryStid)(slot).closeOwner := - 0.U.asTypeOf(new RobGroupKey(p)) - table(safeRecoveryStid)(slot).closeCommitted := false.B - } - when(recoveryApply && freedHere) { - table(safeRecoveryStid)(slot) := - 0.U.asTypeOf(new OooBrobEntry(p)) - } - } - - io.usedBlocks := usedBlocks - for (stid <- 0 until p.stidCount) { - io.head(stid).valid := usedBlocks(stid).orR - io.head(stid).bid.valid := io.head(stid).valid - io.head(stid).bid.value := headSlot(stid) - io.head(stid).generation := headGeneration(stid) - io.tail(stid).valid := true.B - io.tail(stid).bid.valid := true.B - io.tail(stid).bid.value := tailSlot(stid) - io.tail(stid).generation := tailGeneration(stid) - } - io.currentValid := currentValid - io.current := currentPointer -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooBundles.scala b/chisel/src/main/scala/linxcore/ooo/OooBundles.scala index d6a51359..16beac90 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooBundles.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooBundles.scala @@ -193,8 +193,8 @@ class OooD1DecodedPacket(val p: OooParams = OooParams()) extends Bundle { class CanonicalUopKey(val p: OooParams = OooParams()) extends Bundle { val primaryParent = new CanonicalParentKey(p) - val uopOrdinal = UInt(p.robMemberIndexWidth.W) - val uopCount = UInt(p.robMemberCountWidth.W) + val uopOrdinal = UInt(p.recipeUopIndexWidth.W) + val uopCount = UInt(p.recipeUopCountWidth.W) } class BoundarySidecar(val p: OooParams = OooParams()) extends Bundle { @@ -265,6 +265,13 @@ class OooMemoryOrderUopAllocation(val p: OooParams = OooParams()) val firstTypeId = UInt(p.lsidWidth.W) val before = new OooMemoryIdState(p) val after = new OooMemoryIdState(p) + // Preserve the complete public ordering boundary. The type-local counters + // in `before` identify this uop's first load/store, but cannot reproduce + // invalid canonical payloads or the youngest older load identity exactly. + val yostSid = UInt(p.lsidWidth.W) + val yoldValid = Bool() + val yoldLsid = UInt(p.lsidWidth.W) + val yoldLid = UInt(p.lsidWidth.W) } /** All-or-none D3 memory-order lease retained until common S1 publication. */ @@ -880,6 +887,13 @@ object OooIexWakeupKind extends ChiselEnum { val Committed, SpeculativeLoad = Value } +/** Non-reused IEX identity shared by every attempt of one memory operation. */ +class OooIexMemoryTransactionIdentity( + val p: OooParams = OooParams()) extends Bundle { + val value = UInt(p.memoryTransactionIdWidth.W) + val generation = UInt(p.memoryTransactionGenerationWidth.W) +} + /** Exact identity of one speculative load attempt. * * A numerical attempt generation is never authoritative by itself. The @@ -889,9 +903,19 @@ object OooIexWakeupKind extends ChiselEnum { class OooIexLoadGeneration(val p: OooParams = OooParams()) extends Bundle { val valid = Bool() val producer = new RobMemberKey(p) + val transaction = new OooIexMemoryTransactionIdentity(p) val generation = UInt(p.loadGenerationWidth.W) } +/** Retained canonical LSU return before atomic RF/wakeup/ROB publication. */ +class OooIexLoadResult(val p: OooParams = OooParams()) extends Bundle { + val agu = new OooIexAguLoadRequest(p) + val load = new OooIexLoadGeneration(p) + val data = UInt(p.pcWidth.W) + val faultValid = Bool() + val faultCause = UInt(p.trapCauseWidth.W) +} + /** Producer-relative result age carried by the data bypass network. */ object OooIexBypassStage extends ChiselEnum { val W1, W2, W3 = Value @@ -949,9 +973,44 @@ class OooIexSourceState(val p: OooParams = OooParams()) extends Bundle { val ptagGeneration = UInt(p.pTagGenerationWidth.W) val localTag = UInt(p.localTagWidth.W) val localSequence = new OooLocalSeq(p) + /** Producer/allocation epoch for an exact T/U identity. */ + val localEpoch = UInt(p.epochWidth.W) val load = new OooIexLoadGeneration(p) } +/** Read-only PTag Ready Bits entry exported by the physical register file. + * + * The register file remains the unique owner. Dispatch may sample this + * generation-qualified view, but cannot mutate it or infer readiness from a + * numerical tag alone. + */ +class OooIexPTagReadyBitsEntry(val p: OooParams = OooParams()) + extends Bundle { + val valid = Bool() + val ready = Bool() + val stid = UInt(p.stidWidth.W) + val epoch = UInt(p.epochWidth.W) + val generation = UInt(p.pTagGenerationWidth.W) +} + +/** Read-only T/U Ready Bits entry exported by one STID-local register file. */ +class OooIexLocalReadyBitsEntry(val p: OooParams = OooParams()) + extends Bundle { + val allocated = Bool() + val ready = Bool() + val epoch = UInt(p.epochWidth.W) + val sequence = new OooLocalSeq(p) +} + +/** Exact register-file readiness view consumed only while an IQ row binds. */ +class OooIexOperandReadyBits(val p: OooParams = OooParams()) extends Bundle { + val ptag = Vec(p.pPhysRegs, new OooIexPTagReadyBitsEntry(p)) + val ttag = Vec(p.stidCount, + Vec(p.tPhysRegs, new OooIexLocalReadyBitsEntry(p))) + val utag = Vec(p.stidCount, + Vec(p.uPhysRegs, new OooIexLocalReadyBitsEntry(p))) +} + /** Destination identity retained by IEX without copying rename-owner state. */ class OooIexDestinationState(val p: OooParams = OooParams()) extends Bundle { val valid = Bool() @@ -1006,6 +1065,14 @@ class OooIexScheduleRow(val p: OooParams = OooParams()) extends Bundle { val stid = UInt(p.stidWidth.W) val epoch = UInt(p.epochWidth.W) val transactionId = UInt(p.transactionIdWidth.W) + // Allocated once when the logical memory uop first becomes IQ-resident. + // Store address/data children retain the same transaction identity. + val memoryTransactionValid = Bool() + val memoryTransaction = new OooIexMemoryTransactionIdentity(p) + // Loads retain the IEX-owned initial attempt; LSU allocates only replay + // generations after the first LIQ binding. + val initialLoadAttemptValid = Bool() + val initialLoadAttemptGeneration = UInt(p.loadGenerationWidth.W) val dispatchLane = UInt(math.max(1, chisel3.util.log2Ceil(p.dispatchWidth)).W) val uopIndex = UInt(p.decodedUopIndexWidth.W) @@ -1071,6 +1138,10 @@ class OooIexIssueRow(val p: OooParams = OooParams()) extends Bundle { def stid = schedule.stid def epoch = schedule.epoch def transactionId = schedule.transactionId + def memoryTransactionValid = schedule.memoryTransactionValid + def memoryTransaction = schedule.memoryTransaction + def initialLoadAttemptValid = schedule.initialLoadAttemptValid + def initialLoadAttemptGeneration = schedule.initialLoadAttemptGeneration def dispatchLane = schedule.dispatchLane def uopIndex = schedule.uopIndex def childIndex = schedule.childIndex @@ -1392,7 +1463,8 @@ class OooD2GroupedTransaction(val p: OooParams = OooParams()) extends Bundle { val groupMask = UInt(p.instructionDecodeWidth.W) val groups = Vec(p.instructionDecodeWidth, new OooRobGroupPreview(p)) val uopGroupIndex = Vec(p.decodedUopWidth, UInt(p.robGroupIndexWidth.W)) - val uopMemberBase = Vec(p.decodedUopWidth, UInt(p.robMemberIndexWidth.W)) + val uopMemberBase = Vec(p.decodedUopWidth, + UInt(p.robPhysicalMemberIndexWidth.W)) } class OooD3GroupedReservation(val p: OooParams = OooParams()) extends Bundle { diff --git a/chisel/src/main/scala/linxcore/ooo/OooCtuIngressBridge.scala b/chisel/src/main/scala/linxcore/ooo/OooCtuIngressBridge.scala deleted file mode 100644 index 96cd747e..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooCtuIngressBridge.scala +++ /dev/null @@ -1,470 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, PriorityEncoder, Valid} -import linxcore.common.DestinationKind - -object OooCtuLeaseState extends ChiselEnum { - val Idle, WaitPlan, EmitChildren = Value -} - -object OooCtuPlanRejectReason extends ChiselEnum { - val StaleLease, MalformedCount = Value -} - -object OooCtuChildRejectReason extends ChiselEnum { - val StaleLease, WrongOrdinal, MalformedChild = Value -} - -object OooCtuRecoveryRejectReason extends ChiselEnum { - val MalformedRequest = Value -} - -class OooCtuLeaseKey(val p: OooParams = OooParams()) extends Bundle { - val valid = Bool() - val peId = UInt(p.peIdWidth.W) - val stid = UInt(p.stidWidth.W) - val parent = new CanonicalParentKey(p) - val templateGroupId = UInt(p.templateGroupIdWidth.W) - val generation = UInt(p.residentGenerationWidth.W) -} - -class OooCtuParentClaim(val p: OooParams = OooParams()) extends Bundle { - val lease = new OooCtuLeaseKey(p) - val parent = new OooRawInstruction(p) -} - -class OooCtuExpansionPlan(val p: OooParams = OooParams()) extends Bundle { - val lease = new OooCtuLeaseKey(p) - val childCount = UInt(p.recipeUopCountWidth.W) -} - -class OooCtuCanonicalChild(val p: OooParams = OooParams()) extends Bundle { - val lease = new OooCtuLeaseKey(p) - val ordinal = UInt(p.recipeUopCountWidth.W) - val childCount = UInt(p.recipeUopCountWidth.W) - val finalChild = Bool() - val uop = new OooDecodedUop(p) -} - -class OooCtuPlanReject(val p: OooParams = OooParams()) extends Bundle { - val plan = new OooCtuExpansionPlan(p) - val reason = OooCtuPlanRejectReason() -} - -class OooCtuChildReject(val p: OooParams = OooParams()) extends Bundle { - val child = new OooCtuCanonicalChild(p) - val reason = OooCtuChildRejectReason() -} - -class OooCtuRecoveryPrepared(val p: OooParams = OooParams()) extends Bundle { - val request = new OooGlobalRecoveryRequest(p) - val packetPresent = Bool() - val claimPending = Bool() - val expansionActive = Bool() - val lease = new OooCtuLeaseKey(p) -} - -class OooCtuRecoveryReject(val p: OooParams = OooParams()) extends Bundle { - val request = new OooGlobalRecoveryRequest(p) - val reason = OooCtuRecoveryRejectReason() -} - -class OooCtuIngressBridgeIO(val p: OooParams = OooParams()) extends Bundle { - val in = Flipped(Decoupled(new OooD1DecodedPacket(p))) - val out = Decoupled(new OooD1DecodedPacket(p)) - - val parentClaim = Decoupled(new OooCtuParentClaim(p)) - val expansionPlan = Flipped(Decoupled(new OooCtuExpansionPlan(p))) - val child = Flipped(Decoupled(new OooCtuCanonicalChild(p))) - val planRejected = Valid(new OooCtuPlanReject(p)) - val childRejected = Valid(new OooCtuChildReject(p)) - - /** Fence is non-mutating; cancel is the destructive stage event. */ - val fence = Input(Vec(p.stidCount, Bool())) - val cancel = Input(Vec(p.stidCount, Bool())) - - val recoveryPrepare = Flipped(Decoupled(new OooGlobalRecoveryRequest(p))) - val recoveryPrepared = Valid(new OooCtuRecoveryPrepared(p)) - val recoveryRejected = Valid(new OooCtuRecoveryReject(p)) - val recoveryApply = Input(Bool()) - val recoveryAbort = Input(Bool()) - - val occupied = Output(Vec(p.stidCount, Bool())) - val active = Output(Vec(p.stidCount, Bool())) - val blockedByComplex = Output(Vec(p.stidCount, Bool())) -} - -/** Production OOO-side CTU ingress and lease ledger. - * - * D1 packets are retained per STID. Ordinary uops before the next diverted - * parent leave as a dense packet; a CTU parent is claimed exactly once and - * blocks only its STID until the external CTU supplies an exact plan and - * ordered canonical children. Each accepted child re-enters the ordinary D2 - * path as one logical uop, so long expansions naturally span multiple RID - * groups. Only the final child owns the architectural parent trace. - */ -class OooCtuIngressBridge(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooCtuIngressBridgeIO(p)) - - private def instructionOlder(left: UInt, right: UInt): Bool = { - val distance = right - left - distance.orR && !distance(p.instructionIdWidth - 1) - } - - val packetValid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val packets = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooD1DecodedPacket(p))))) - val remainingUops = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.decodedUopWidth.W)))) - val remainingCtu = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.instructionDecodeWidth.W)))) - val remainingComplex = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.instructionDecodeWidth.W)))) - - val leaseState = RegInit(VecInit(Seq.fill(p.stidCount)(OooCtuLeaseState.Idle))) - val lease = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooCtuLeaseKey(p))))) - val leaseParent = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooRawInstruction(p))))) - val leaseChildCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.recipeUopCountWidth.W)))) - val expectedOrdinal = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.recipeUopCountWidth.W)))) - val nextTemplateGroupId = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.templateGroupIdWidth.W)))) - val nextGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.residentGenerationWidth.W)))) - - val recoveryPending = RegInit(false.B) - val recoveryRequest = RegInit(0.U.asTypeOf(new OooGlobalRecoveryRequest(p))) - val recoverySnapshot = RegInit(0.U.asTypeOf(new OooCtuRecoveryPrepared(p))) - val recoveryStid = recoveryRequest.rename.key.member.group.stid - val offeredRecoveryStid = io.recoveryPrepare.bits.rename.key.member.group.stid - val offeredRecoveryWellFormed = - io.recoveryPrepare.bits.rename.key.member.group.valid && - io.recoveryPrepare.bits.rename.key.member.bid.valid && - offeredRecoveryStid < p.stidCount.U - - io.recoveryPrepare.ready := !recoveryPending - io.recoveryPrepared.valid := recoveryPending - io.recoveryPrepared.bits := recoverySnapshot - io.recoveryRejected.valid := io.recoveryPrepare.fire && !offeredRecoveryWellFormed - io.recoveryRejected.bits.request := io.recoveryPrepare.bits - io.recoveryRejected.bits.reason := OooCtuRecoveryRejectReason.MalformedRequest - - when(io.recoveryPrepare.fire && offeredRecoveryWellFormed) { - val stid = offeredRecoveryStid - recoveryPending := true.B - recoveryRequest := io.recoveryPrepare.bits - recoverySnapshot.request := io.recoveryPrepare.bits - recoverySnapshot.packetPresent := packetValid(stid) - recoverySnapshot.claimPending := leaseState(stid) === OooCtuLeaseState.WaitPlan - recoverySnapshot.expansionActive := leaseState(stid) === OooCtuLeaseState.EmitChildren - recoverySnapshot.lease := lease(stid) - } - - val effectiveFence = Wire(Vec(p.stidCount, Bool())) - for (stid <- 0 until p.stidCount) { - effectiveFence(stid) := io.fence(stid) || - (recoveryPending && recoveryStid === stid.U) - } - - val inputStid = io.in.bits.stid - val inputStidInRange = inputStid < p.stidCount.U - val inputBusy = Mux(inputStidInRange, packetValid(inputStid), true.B) - val inputLeaseBusy = Mux( - inputStidInRange, - leaseState(inputStid) =/= OooCtuLeaseState.Idle, - true.B) - val inputFenced = Mux(inputStidInRange, effectiveFence(inputStid), true.B) - val inputCancelled = Mux(inputStidInRange, io.cancel(inputStid), true.B) - io.in.ready := inputStidInRange && !inputBusy && !inputLeaseBusy && - !inputFenced && !inputCancelled - - when(io.in.fire) { - packetValid(inputStid) := true.B - packets(inputStid) := io.in.bits - remainingUops(inputStid) := io.in.bits.uopMask - remainingCtu(inputStid) := io.in.bits.ctuParentMask - remainingComplex(inputStid) := io.in.bits.complexParentMask - } - - val normalMaskByStid = Wire(Vec(p.stidCount, UInt(p.decodedUopWidth.W))) - val nextOwnerIsCtu = Wire(Vec(p.stidCount, Bool())) - val actionCandidate = Wire(Vec(p.stidCount, Bool())) - val complexBlocked = Wire(Vec(p.stidCount, Bool())) - for (stid <- 0 until p.stidCount) { - val packet = packets(stid) - val ctuMask = remainingCtu(stid) - val complexMask = remainingComplex(stid) - val hasCtu = ctuMask.orR - val hasComplex = complexMask.orR - val ctuLane = PriorityEncoder(ctuMask) - val complexLane = PriorityEncoder(complexMask) - val ctuId = packet.ctuParents(ctuLane).parent.key.instructionId - val complexId = packet.complexParents(complexLane).parent.key.instructionId - val boundaryValid = hasCtu || hasComplex - val ctuFirst = hasCtu && (!hasComplex || instructionOlder(ctuId, complexId)) - val boundaryId = Mux(ctuFirst, ctuId, complexId) - val normalBits = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - normalBits(uopIndex) := remainingUops(stid)(uopIndex) && - (!boundaryValid || - instructionOlder( - packet.uops(uopIndex).identity.key.primaryParent.instructionId, - boundaryId)) - } - normalMaskByStid(stid) := normalBits.asUInt - nextOwnerIsCtu(stid) := ctuFirst && !normalBits.asUInt.orR - complexBlocked(stid) := packetValid(stid) && hasComplex && !ctuFirst && - !normalBits.asUInt.orR - actionCandidate(stid) := packetValid(stid) && - leaseState(stid) === OooCtuLeaseState.Idle && !effectiveFence(stid) && - !io.cancel(stid) && (normalBits.asUInt.orR || nextOwnerIsCtu(stid)) - } - - val rrStart = RegInit(0.U(p.stidWidth.W)) - val rotated = Wire(Vec(p.stidCount, Bool())) - for (offset <- 0 until p.stidCount) { - val index = if (p.stidCount == 1) 0.U else (rrStart + offset.U)(p.stidWidth - 1, 0) - rotated(offset) := actionCandidate(index) - } - val actionValid = rotated.asUInt.orR - val actionOffset = if (p.stidCount == 1) 0.U else PriorityEncoder(rotated.asUInt) - val actionStid = - if (p.stidCount == 1) 0.U(p.stidWidth.W) - else (rrStart + actionOffset)(p.stidWidth - 1, 0) - val actionNormalMask = normalMaskByStid(actionStid) - val actionNormal = actionValid && actionNormalMask.orR - val actionClaim = actionValid && !actionNormal && nextOwnerIsCtu(actionStid) - - val claimLane = PriorityEncoder(remainingCtu(actionStid)) - val offeredLease = Wire(new OooCtuLeaseKey(p)) - offeredLease := 0.U.asTypeOf(offeredLease) - offeredLease.valid := true.B - offeredLease.peId := packets(actionStid).peId - offeredLease.stid := actionStid - offeredLease.parent := packets(actionStid).ctuParents(claimLane).parent.key - offeredLease.templateGroupId := nextTemplateGroupId(actionStid) - offeredLease.generation := nextGeneration(actionStid) - - io.parentClaim.valid := actionClaim - io.parentClaim.bits.lease := offeredLease - io.parentClaim.bits.parent := packets(actionStid).ctuParents(claimLane) - - val planStidInRange = io.expansionPlan.bits.lease.stid < p.stidCount.U - val planStid = Mux(planStidInRange, io.expansionPlan.bits.lease.stid, 0.U) - val planLeaseExact = planStidInRange && - leaseState(planStid) === OooCtuLeaseState.WaitPlan && - io.expansionPlan.bits.lease.asUInt === lease(planStid).asUInt - val planCountWellFormed = io.expansionPlan.bits.childCount.orR && - io.expansionPlan.bits.childCount <= p.maxRecipeUops.U - val planBlocked = planLeaseExact && effectiveFence(planStid) - io.expansionPlan.ready := !planBlocked - io.planRejected.valid := io.expansionPlan.fire && - (!planLeaseExact || !planCountWellFormed) - io.planRejected.bits.plan := io.expansionPlan.bits - io.planRejected.bits.reason := Mux( - !planLeaseExact, - OooCtuPlanRejectReason.StaleLease, - OooCtuPlanRejectReason.MalformedCount) - - val childStidInRange = io.child.bits.lease.stid < p.stidCount.U - val childStid = Mux(childStidInRange, io.child.bits.lease.stid, 0.U) - val childLeaseExact = childStidInRange && - leaseState(childStid) === OooCtuLeaseState.EmitChildren && - io.child.bits.lease.asUInt === lease(childStid).asUInt - val childOrdinalExact = childLeaseExact && - io.child.bits.ordinal === expectedOrdinal(childStid) && - io.child.bits.childCount === leaseChildCount(childStid) - val childFinalExpected = childOrdinalExact && - io.child.bits.finalChild === - (expectedOrdinal(childStid) === leaseChildCount(childStid) - 1.U) - val childShapeExact = childFinalExpected && io.child.bits.uop.valid && - io.child.bits.uop.recipe.valid && - io.child.bits.uop.recipe.disposition =/= OooOpcodeDisposition.Ctu.U && - io.child.bits.uop.recipe.disposition =/= OooOpcodeDisposition.Illegal.U && - io.child.bits.uop.plannedChildCount.orR && - io.child.bits.uop.plannedChildCount <= p.maxOrdinaryUopsPerGroup.U - val childBlocked = childShapeExact && effectiveFence(childStid) - val childExact = childShapeExact && !childBlocked - - io.childRejected.valid := io.child.valid && !childShapeExact - io.childRejected.bits.child := io.child.bits - io.childRejected.bits.reason := Mux( - !childLeaseExact, - OooCtuChildRejectReason.StaleLease, - Mux( - !childOrdinalExact, - OooCtuChildRejectReason.WrongOrdinal, - OooCtuChildRejectReason.MalformedChild)) - - private def populateDemand(packet: OooD1DecodedPacket): Unit = { - packet.demand.instructionRows := PopCount(packet.uops.flatMap(_.identity.parents).map { parent => - parent.key.valid && parent.traceOwner - }) - packet.acceptedInstructionMask := - ((1.U((p.instructionDecodeWidth + 1).W) << packet.demand.instructionRows) - 1.U)( - p.instructionDecodeWidth - 1, 0) - packet.demand.decodedUops := PopCount(packet.uopMask) - packet.demand.robGroups := 0.U - packet.demand.brobSlots := PopCount(packet.uops.map { uop => - uop.valid && uop.identity.boundary.start - }) - packet.demand.pcBaseWrites := PopCount(packet.uops.flatMap(_.identity.parents).map { parent => - parent.key.valid && parent.traceOwner && parent.prediction.valid && parent.prediction.taken - }) - packet.demand.pDestinations := PopCount(packet.uops.flatMap(_.destinations).map { destination => - destination.valid && destination.kind === DestinationKind.Gpr - }) - packet.demand.tAllocations := PopCount(packet.uops.flatMap(_.destinations).map { destination => - destination.valid && destination.kind === DestinationKind.T - }) - packet.demand.uAllocations := PopCount(packet.uops.flatMap(_.destinations).map { destination => - destination.valid && destination.kind === DestinationKind.U - }) - packet.demand.mapQRows := packet.demand.pDestinations - for (dispatchClass <- 0 until p.iqClassCount) { - packet.demand.dispatchWritesByClass(dispatchClass) := packet.uops.map { uop => - Mux(uop.valid, uop.recipe.dispatchDemand(dispatchClass), 0.U) - }.reduce(_ +& _) - } - packet.demand.dispatchWritesByBank.foreach(_ := 0.U) - packet.demand.loadIds := packet.uops.map { uop => - val load = uop.recipe.recipeKind === OooOpcodeRecipeKind.ScalarLoad.U || - uop.recipe.recipeKind === OooOpcodeRecipeKind.PairLoad.U - Mux(uop.valid && load, uop.recipe.memoryRequestCount, 0.U) - }.reduce(_ +& _) - packet.demand.storeIds := packet.uops.map { uop => - val store = uop.recipe.recipeKind === OooOpcodeRecipeKind.ScalarStore.U || - uop.recipe.recipeKind === OooOpcodeRecipeKind.PairStore.U - Mux(uop.valid && store, uop.recipe.memoryRequestCount, 0.U) - }.reduce(_ +& _) - } - - val normalPacket = Wire(new OooD1DecodedPacket(p)) - normalPacket := 0.U.asTypeOf(normalPacket) - normalPacket.peId := packets(actionStid).peId - normalPacket.stid := actionStid - normalPacket.epoch := packets(actionStid).epoch - val normalCount = PopCount(actionNormalMask) - normalPacket.uopMask := - ((1.U((p.decodedUopWidth + 1).W) << normalCount) - 1.U)(p.decodedUopWidth - 1, 0) - for (sourceIndex <- 0 until p.decodedUopWidth) { - val outputIndex = if (sourceIndex == 0) 0.U else PopCount(actionNormalMask(sourceIndex - 1, 0)) - for (outputSlot <- 0 until p.decodedUopWidth) { - when(actionNormalMask(sourceIndex) && outputIndex === outputSlot.U) { - normalPacket.uops(outputSlot) := packets(actionStid).uops(sourceIndex) - } - } - } - val normalLeavesUops = (remainingUops(actionStid) & ~actionNormalMask).orR - val normalLeavesSideband = remainingCtu(actionStid).orR || - remainingComplex(actionStid).orR - normalPacket.endOfStream := packets(actionStid).endOfStream && - !normalLeavesUops && !normalLeavesSideband - populateDemand(normalPacket) - - val childPacket = Wire(new OooD1DecodedPacket(p)) - childPacket := 0.U.asTypeOf(childPacket) - childPacket.peId := lease(childStid).peId - childPacket.stid := childStid - childPacket.epoch := lease(childStid).parent.epoch - childPacket.uopMask := 1.U - childPacket.uops(0) := io.child.bits.uop - childPacket.uops(0).identity.key.primaryParent := lease(childStid).parent - childPacket.uops(0).identity.key.uopOrdinal := io.child.bits.ordinal - childPacket.uops(0).identity.key.uopCount := io.child.bits.childCount - childPacket.uops(0).identity.parentCount := 1.U - childPacket.uops(0).identity.parents(0) := leaseParent(childStid).parent - childPacket.uops(0).identity.parents(0).traceOwner := io.child.bits.finalChild - childPacket.uops(0).identity.templateValid := true.B - childPacket.uops(0).identity.templateGroupId := lease(childStid).templateGroupId - childPacket.uops(0).identity.templateGeneration := lease(childStid).generation - childPacket.endOfStream := false.B - populateDemand(childPacket) - - val childUsesOutput = io.child.valid && childExact - io.out.valid := childUsesOutput || (!childUsesOutput && actionNormal) - io.out.bits := Mux(childUsesOutput, childPacket, normalPacket) - io.child.ready := Mux(childBlocked, false.B, Mux(childExact, io.out.ready, true.B)) - - val normalFire = io.out.fire && !childUsesOutput - val childFire = io.child.fire && childExact - when(normalFire) { - remainingUops(actionStid) := remainingUops(actionStid) & ~actionNormalMask - when(!normalLeavesUops && !normalLeavesSideband) { - packetValid(actionStid) := false.B - } - rrStart := actionStid + 1.U - } - - when(io.parentClaim.fire) { - leaseState(actionStid) := OooCtuLeaseState.WaitPlan - lease(actionStid) := offeredLease - leaseParent(actionStid) := io.parentClaim.bits.parent - remainingCtu(actionStid) := remainingCtu(actionStid) & ~(1.U << claimLane) - nextTemplateGroupId(actionStid) := nextTemplateGroupId(actionStid) + 1.U - nextGeneration(actionStid) := nextGeneration(actionStid) + 1.U - rrStart := actionStid + 1.U - } - - when(io.expansionPlan.fire && planLeaseExact && planCountWellFormed) { - leaseState(planStid) := OooCtuLeaseState.EmitChildren - leaseChildCount(planStid) := io.expansionPlan.bits.childCount - expectedOrdinal(planStid) := 0.U - } - - when(childFire) { - when(io.child.bits.finalChild) { - leaseState(childStid) := OooCtuLeaseState.Idle - lease(childStid).valid := false.B - when(!remainingUops(childStid).orR && !remainingCtu(childStid).orR && - !remainingComplex(childStid).orR) { - packetValid(childStid) := false.B - } - }.otherwise { - expectedOrdinal(childStid) := expectedOrdinal(childStid) + 1.U - } - } - - for (stid <- 0 until p.stidCount) { - val recoveryOwnsCancellation = recoveryPending && recoveryStid === stid.U - when(io.cancel(stid) && !recoveryOwnsCancellation) { - packetValid(stid) := false.B - remainingUops(stid) := 0.U - remainingCtu(stid) := 0.U - remainingComplex(stid) := 0.U - leaseState(stid) := OooCtuLeaseState.Idle - lease(stid).valid := false.B - } - } - - when(io.recoveryApply) { - assert(recoveryPending, "CTU recovery apply requires a retained prepare") - val stid = recoveryStid - packetValid(stid) := false.B - remainingUops(stid) := 0.U - remainingCtu(stid) := 0.U - remainingComplex(stid) := 0.U - leaseState(stid) := OooCtuLeaseState.Idle - lease(stid).valid := false.B - recoveryPending := false.B - }.elsewhen(io.recoveryAbort) { - assert(recoveryPending, "CTU recovery abort requires a retained prepare") - recoveryPending := false.B - } - - io.occupied := packetValid - for (stid <- 0 until p.stidCount) { - io.active(stid) := leaseState(stid) =/= OooCtuLeaseState.Idle - io.blockedByComplex(stid) := complexBlocked(stid) - } - - when(io.in.valid) { - assert(inputStidInRange, "CTU ingress packet STID must be in range") - } - when(io.parentClaim.fire) { - assert(io.parentClaim.bits.parent.parent.key === io.parentClaim.bits.lease.parent) - } - when(childFire) { - assert(io.out.bits.ctuParentMask === 0.U) - assert(io.out.bits.complexParentMask === 0.U) - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooD1Decode.scala b/chisel/src/main/scala/linxcore/ooo/OooD1Decode.scala index 67b82675..e99738ff 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooD1Decode.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooD1Decode.scala @@ -35,7 +35,7 @@ private[ooo] class OooD1DecodeLaneIO(val p: OooParams = OooParams()) extends Bun /** Exact decode and operand-normalization leaf for one architectural parent. */ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Module { - private val legacyP = InterfaceParams() + private val legacyP = InterfaceParams(blockEpochWidth = p.epochWidth) require(legacyP.insnWidth == p.instructionWidth) require(legacyP.opcodeWidth == p.opcodeWidth) require(legacyP.archRegWidth == p.archRegWidth) @@ -148,6 +148,9 @@ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Modul recipe.recipeKind === OooOpcodeRecipeKind.ScalarStore.U && recipe.lateSplitKind === OooLateSplitKind.StoreAddressData.U && recipe.sideEffectOwner === OooSideEffectOwner.Lsu.U + val compactStore = opcodeIs( + FrontendOpcodeDecodeTable.OP_C_SDI, + FrontendOpcodeDecodeTable.OP_C_SWI) val loadPcr = opcodeIs( FrontendOpcodeDecodeTable.OP_LB_PCR, FrontendOpcodeDecodeTable.OP_LBU_PCR, @@ -218,6 +221,7 @@ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Modul FrontendOpcodeDecodeTable.OP_HL_SHP, FrontendOpcodeDecodeTable.OP_HL_SHP_U) val wordLoad = opcodeIs( + FrontendOpcodeDecodeTable.OP_C_LWI, FrontendOpcodeDecodeTable.OP_LW, FrontendOpcodeDecodeTable.OP_LWI, FrontendOpcodeDecodeTable.OP_LWI_U, @@ -227,6 +231,7 @@ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Modul FrontendOpcodeDecodeTable.OP_LWUI_U, FrontendOpcodeDecodeTable.OP_LWU_PCR) val wordStore = opcodeIs( + FrontendOpcodeDecodeTable.OP_C_SWI, FrontendOpcodeDecodeTable.OP_SW, FrontendOpcodeDecodeTable.OP_SW_U, FrontendOpcodeDecodeTable.OP_SWI, @@ -249,6 +254,7 @@ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Modul FrontendOpcodeDecodeTable.OP_LWUI_U, FrontendOpcodeDecodeTable.OP_LWU_PCR) val signedNarrowLoad = opcodeIs( + FrontendOpcodeDecodeTable.OP_C_LWI, FrontendOpcodeDecodeTable.OP_LB, FrontendOpcodeDecodeTable.OP_LBI, FrontendOpcodeDecodeTable.OP_LB_PCR, @@ -338,10 +344,11 @@ private[ooo] class OooD1DecodeLane(val p: OooParams = OooParams()) extends Modul Mux(pairStoreRegister, 12.U, Mux(storeRegister, 6.U, Mux(pairStore, 4.U, - Mux(scalarStore, 2.U, - Mux(loadRegister, 3.U, 1.U)))))) + Mux(compactStore, 1.U, + Mux(scalarStore, 2.U, + Mux(loadRegister, 3.U, 1.U))))))) uop.memory.dataSourceMask := Mux(pairStore, 3.U, - Mux(scalarStore, 1.U, 0.U)) + Mux(compactStore, 2.U, Mux(scalarStore, 1.U, 0.U))) uop.memory.writebackValid := storeWriteback uop.memory.writebackPreIndex := storeWritebackPreIndex uop.boundaryTargetValid := recipe.requiresTargetValidation && legacy.io.out.immValid @@ -471,7 +478,9 @@ class OooD1DecodeIO(val p: OooParams = OooParams()) extends Bundle { } /** Parameterized same-cycle D1 decode, operand normalization, fusion, and compaction. */ -class OooD1Decode(val p: OooParams = OooParams()) extends Module { +class OooD1Decode( + val p: OooParams = OooParams(), + val allowSparseInput: Boolean = false) extends Module { val io = IO(new OooD1DecodeIO(p)) val laneResults = Wire(Vec(p.instructionDecodeWidth, new OooD1LaneResult(p))) @@ -616,10 +625,13 @@ class OooD1Decode(val p: OooParams = OooParams()) extends Module { io.in.ready := Mux(io.in.bits.validMask.orR || io.in.bits.endOfStream, io.out.ready, true.B) when(io.in.valid) { - val denseInput = - ((1.U((p.instructionDecodeWidth + 1).W) << PopCount(io.in.bits.validMask)) - 1.U)( - p.instructionDecodeWidth - 1, 0) - assert(io.in.bits.validMask === denseInput, "OOO D1 accepts only a dense instruction prefix") + if (!allowSparseInput) { + val denseInput = + ((1.U((p.instructionDecodeWidth + 1).W) << PopCount(io.in.bits.validMask)) - 1.U)( + p.instructionDecodeWidth - 1, 0) + assert(io.in.bits.validMask === denseInput, + "OOO D1 accepts only a dense instruction prefix") + } for (lane <- 0 until p.instructionDecodeWidth) { when(io.in.bits.validMask(lane)) { assert( diff --git a/chisel/src/main/scala/linxcore/ooo/OooD2GroupPlanner.scala b/chisel/src/main/scala/linxcore/ooo/OooD2GroupPlanner.scala index b023e695..f8b8fe68 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooD2GroupPlanner.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooD2GroupPlanner.scala @@ -37,7 +37,8 @@ class OooD2GroupPlanner(val p: OooParams = OooParams()) extends Module { stateClosed(0) := false.B val assignedGroup = Wire(Vec(p.decodedUopWidth, UInt(p.robGroupIndexWidth.W))) - val assignedMemberBase = Wire(Vec(p.decodedUopWidth, UInt(p.robMemberIndexWidth.W))) + val assignedMemberBase = Wire(Vec(p.decodedUopWidth, + UInt(p.robPhysicalMemberIndexWidth.W))) val releasePcBase = Wire(Vec(p.decodedUopWidth, Bool())) for (uopIndex <- 0 until p.decodedUopWidth) { @@ -61,7 +62,8 @@ class OooD2GroupPlanner(val p: OooParams = OooParams()) extends Module { assignedGroup(uopIndex) := (stateGroup(uopIndex) + newGroup.asUInt)(p.robGroupIndexWidth - 1, 0) assignedMemberBase(uopIndex) := - Mux(newGroup, 0.U, stateMembers(uopIndex))(p.robMemberIndexWidth - 1, 0) + Mux(newGroup, 0.U, stateMembers(uopIndex))( + p.robPhysicalMemberIndexWidth - 1, 0) releasePcBase(uopIndex) := uop.identity.parents.zipWithIndex.map { case (parent, parentIndex) => @@ -119,7 +121,9 @@ class OooD2GroupPlanner(val p: OooParams = OooParams()) extends Module { group.key.valid := group.valid group.key.peId := io.in.bits.peId group.key.stid := stid - group.key.ridSlot := slotSum(p.ridSlotWidth - 1, 0) + group.key.ridSlot := Mux(wraps, + (slotSum - p.robGroupsPerStid.U)(p.ridSlotWidth - 1, 0), + slotSum(p.ridSlotWidth - 1, 0)) group.key.ridGeneration := io.tailGeneration(stid) + wraps.asUInt group.logicalUopMask := VecInit((0 until p.decodedUopWidth).map { uopIndex => io.in.bits.uopMask(uopIndex) && assignedGroup(uopIndex) === groupIndex.U diff --git a/chisel/src/main/scala/linxcore/ooo/OooD3FastResultQueue.scala b/chisel/src/main/scala/linxcore/ooo/OooD3FastResultQueue.scala new file mode 100644 index 00000000..52760a07 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooD3FastResultQueue.scala @@ -0,0 +1,117 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Decoupled, PopCount, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.{FastWritebackTxn, RecoveryPhase, RecoveryPlan, + RecoveryPlanContract, RecoveryTargetIO} + +private[ooo] class OooD3FastResultBatch(val p: CoreParams) extends Bundle { + val count = UInt(log2Ceil(p.ooo.d3PrefixWidth + 1).W) + val entries = Vec(p.ooo.d3PrefixWidth, new FastWritebackTxn(p)) +} + +private[ooo] class OooD3FastResultQueueIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Valid(new OooD3FastResultBatch(p))) + val prepareReady = Output(Bool()) + val publishFire = Input(Bool()) + val out = Decoupled(new FastWritebackTxn(p)) + val recovery = Flipped(new RecoveryTargetIO(p)) +} + +/** Retains canonical D3 fast-result producers until their committed + * writeback/wakeup fork fires. Recovery removes only exact killed ROB + * members; preparation and publication remain split by the common D3 fire. + */ +private[ooo] class OooD3FastResultQueue(val p: CoreParams) extends Module { + val io = IO(new OooD3FastResultQueueIO(p)) + private val depth = p.ooo.d3PrefixWidth * 2 + private val countWidth = log2Ceil(depth + 1) + private val indexWidth = log2Ceil(depth) + + val entries = Reg(Vec(depth, new FastWritebackTxn(p))) + val count = RegInit(0.U(countWidth.W)) + val recoveryPending = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(p)) + + val offeredCountExact = io.prepare.bits.count <= p.ooo.d3PrefixWidth.U + val free = depth.U - count + io.prepareReady := offeredCountExact && + io.prepare.bits.count <= free && !recoveryPending + when(io.publishFire) { + assert(io.prepare.valid && io.prepareReady, + "fast-result publication requires capacity for the exact D3 batch") + } + + io.out.valid := count.orR && !recoveryPending + io.out.bits := entries(0) + val dequeue = io.out.fire + val baseCount = count - dequeue.asUInt + + when(!recoveryPending) { + when(dequeue) { + for (slot <- 0 until depth - 1) { + entries(slot) := entries(slot + 1) + } + } + when(io.publishFire) { + for (lane <- 0 until p.ooo.d3PrefixWidth) { + when(lane.U < io.prepare.bits.count) { + entries((baseCount + lane.U)(indexWidth - 1, 0)) := + io.prepare.bits.entries(lane) + } + } + } + when(dequeue || io.publishFire) { + count := baseCount + Mux(io.publishFire, io.prepare.bits.count, 0.U) + } + } + + io.recovery.prepare.ready := !recoveryPending + io.recovery.prepared.valid := recoveryPending + io.recovery.prepared.bits := retainedRecovery + when(io.recovery.prepare.fire) { + retainedRecovery := io.recovery.prepare.bits + recoveryPending := true.B + } + + val applyHit = recoveryPending && io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val abortHit = recoveryPending && io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + when(io.recovery.apply.valid) { + assert(applyHit, + "fast-result recovery apply must match the retained canonical plan") + } + when(io.recovery.abort.valid) { + assert(abortHit, + "fast-result recovery abort must match the retained canonical plan") + } + + val survivors = Wire(Vec(depth, Bool())) + val survivorPrefix = Wire(Vec(depth + 1, UInt(countWidth.W))) + survivorPrefix(0) := 0.U + for (slot <- 0 until depth) { + survivors(slot) := slot.U < count && + !RecoveryPlanContract.suffixMember(retainedRecovery, entries(slot).rob) + survivorPrefix(slot + 1) := survivorPrefix(slot) + survivors(slot).asUInt + } + when(applyHit) { + val compacted = Wire(Vec(depth, new FastWritebackTxn(p))) + compacted := 0.U.asTypeOf(compacted) + for (slot <- 0 until depth) { + when(survivors(slot)) { + compacted(survivorPrefix(slot)(indexWidth - 1, 0)) := entries(slot) + } + } + entries := compacted + count := PopCount(survivors) + recoveryPending := false.B + }.elsewhen(abortHit) { + recoveryPending := false.B + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala b/chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala index 68b427a2..f393ebc8 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala @@ -1,374 +1,123 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, PopCount, PriorityEncoder, Valid} - -class OooD3ReservationAllocatorIO(val p: OooParams = OooParams()) extends Bundle { - val in = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val release = Flipped(Decoupled(new OooRobGroupRelease(p))) - val cancel = Input(Vec(p.stidCount, Bool())) - val publishEligible = Input(Vec(p.stidCount, Bool())) - val recoveryPrepare = Flipped(Valid(new OooRobRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryFire = Input(Bool()) - val out = Decoupled(new OooD3GroupedReservation(p)) - - val tailSlot = Output(Vec(p.stidCount, UInt(p.ridSlotWidth.W))) - val tailGeneration = Output(Vec(p.stidCount, UInt(p.ridGenerationWidth.W))) - val tailEpoch = Output(Vec(p.stidCount, UInt(p.reservationEpochWidth.W))) - val nextTransactionId = Output(Vec(p.stidCount, UInt(p.transactionIdWidth.W))) - val headSlot = Output(Vec(p.stidCount, UInt(p.ridSlotWidth.W))) - val headGeneration = Output(Vec(p.stidCount, UInt(p.ridGenerationWidth.W))) - val headEpoch = Output(Vec(p.stidCount, UInt(p.reservationEpochWidth.W))) - val usedGroups = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val publishedGroups = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val provisionalMask = Output(UInt(p.stidCount.W)) - val planStale = Output(Bool()) - val staleRejected = Valid(new OooD3StalePlanReject(p)) - val releaseRejected = Valid(new OooD3ReleaseReject(p)) - val recoveryRejected = Valid(new OooD3RecoveryReject(p)) - val capacityBlocked = Output(Bool()) +import chisel3.util.{Decoupled, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class OooD3ReservationAllocatorIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new D3RenameGroup(p))) + val robPrepared = Input(new OOORobPrepared(p)) + val brobPrepared = Input(new BROBPrepared(p)) + val advance = Input(UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W)) + val pendingValid = Output(Bool()) + val pending = Output(new D3RenameGroup(p)) + val cursor = Output(UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W)) + val transactionBase = Output(UInt(p.transactionIdWidth.W)) + val publicationTransactionBase = Output(UInt(p.transactionIdWidth.W)) + val recovery = Flipped(new RecoveryTargetIO(p)) } -/** D3 provisional grouped-ROB allocator. +/** Canonical D3/S1 dispatch-reservation owner. * - * Accepted claims advance private reserved tails but do not create public ROB - * rows. `out.fire` is the later S1 publication boundary. A canceled claim can - * therefore roll back exactly because only one provisional row exists per - * STID. Stale plans are consumed and reported with zero state mutation. + * ROB and BROB remain the only residency owners. This module retains only the + * already-published canonical payload while classed dispatch drains an exact + * continuous suffix. The common caller-controlled publication pulse is the + * sole point at which a new row becomes visible here. */ -class OooD3ReservationAllocator(val p: OooParams = OooParams()) extends Module { +class OooD3ReservationAllocator(val p: CoreParams) extends Module { val io = IO(new OooD3ReservationAllocatorIO(p)) - private val usedWidth = p.countWidth(p.robGroupsPerStid) - - val tailSlot = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridSlotWidth.W)))) - val tailGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridGenerationWidth.W)))) - val tailEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.reservationEpochWidth.W)))) - val nextTransactionId = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.transactionIdWidth.W)))) - val headSlot = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridSlotWidth.W)))) - val headGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridGenerationWidth.W)))) - val headEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.reservationEpochWidth.W)))) - val headPeId = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.peIdWidth.W)))) - val usedGroups = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(usedWidth.W)))) - val publishedGroups = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(usedWidth.W)))) - val valid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val rows = Reg(Vec(p.stidCount, new OooD3GroupedReservation(p))) - - val recoveryPlan = io.recoveryPrepare.bits - val recoveryStid = recoveryPlan.request.rename.key.member.group.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryTargetsStid = io.recoveryPrepare.valid && - recoveryPlan.valid && recoveryStidInRange - val rrStart = RegInit(0.U(p.stidWidth.W)) - val heldGrantValid = RegInit(false.B) - val heldGrantStid = RegInit(0.U(p.stidWidth.W)) - val rotated = Wire(Vec(p.stidCount, Bool())) - for (offset <- 0 until p.stidCount) { - val index = if (p.stidCount == 1) 0.U else (rrStart + offset.U)(p.stidWidth - 1, 0) - rotated(offset) := valid(index) && !io.cancel(index) && - !(recoveryTargetsStid && index === recoveryStid) && - io.publishEligible(index) + private val countWidth = PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth) + val heldValid = RegInit(false.B) + val held = Reg(new D3RenameGroup(p)) + val cursor = RegInit(0.U(countWidth.W)) + val nextTransaction = RegInit(0.U(p.transactionIdWidth.W)) + val heldTransactionBase = RegInit(0.U(p.transactionIdWidth.W)) + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val sameApply = recoveryPending && io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, recoveryPlan) + val sameAbort = recoveryPending && io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, recoveryPlan) + + io.recovery.prepare.ready := !recoveryPending + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan + when(io.recovery.prepare.fire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(sameApply || sameAbort) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B } - val rrValid = rotated.asUInt.orR - val rrOffset = if (p.stidCount == 1) 0.U else PriorityEncoder(rotated.asUInt) - val rrSelected = - if (p.stidCount == 1) 0.U(p.stidWidth.W) - else (rrStart + rrOffset)(p.stidWidth - 1, 0) - val selected = Mux(heldGrantValid, heldGrantStid, rrSelected) - // Eligibility filters only a new grant. Once valid has been exposed and the - // grant is held, ready/valid requires it to remain asserted until fire or an - // explicit matching cancel, even if downstream eligibility later changes. - val selectedLive = if (p.stidCount == 1) { - valid(0) && !io.cancel(0) && - (heldGrantValid || (!recoveryTargetsStid && io.publishEligible(0))) - } else { - valid(selected) && !io.cancel(selected) && - (heldGrantValid || - (!(recoveryTargetsStid && selected === recoveryStid) && - io.publishEligible(selected))) - } - io.out.valid := Mux(heldGrantValid, selectedLive, rrValid) - io.out.bits := (if (p.stidCount == 1) rows(0) else rows(selected)) - val inStid = io.in.bits.plan.stid - val inRange = inStid < p.stidCount.U - val liveSlot = tailSlot(inStid) - val liveGeneration = tailGeneration(inStid) - val liveEpoch = tailEpoch(inStid) - val groupCount = io.in.bits.plan.groupCount - val firstKey = io.in.bits.plan.firstVirtualGroup - val groupCountInRange = groupCount.orR && groupCount <= p.instructionDecodeWidth.U - val expectedGroupMask = - ((1.U((p.instructionDecodeWidth + 1).W) << groupCount) - 1.U)( - p.instructionDecodeWidth - 1, 0) - val planIdentityExact = - io.in.bits.plan.peId === io.in.bits.decoded.peId && - io.in.bits.plan.stid === io.in.bits.decoded.stid && - io.in.bits.plan.epoch === io.in.bits.decoded.epoch - val allGroupKeysExact = (0 until p.instructionDecodeWidth).map { groupIndex => - val expectedSum = liveSlot +& groupIndex.U - val expectedWrap = expectedSum >= p.robGroupsPerStid.U - val group = io.in.bits.groups(groupIndex) - val shouldBeValid = groupIndex.U < groupCount - group.valid === shouldBeValid && (!shouldBeValid || ( - group.key.valid && - group.key.peId === io.in.bits.plan.peId && - group.key.stid === inStid && - group.key.ridSlot === expectedSum(p.ridSlotWidth - 1, 0) && - group.key.ridGeneration === liveGeneration + expectedWrap.asUInt)) + val inputCountExact = io.in.bits.count =/= 0.U && + io.in.bits.count <= p.ooo.d3PrefixWidth.U && + io.robPrepared.count === io.in.bits.count && + io.brobPrepared.count === io.in.bits.count + val preparedExact = (0 until p.ooo.d3PrefixWidth).map { lane => + val active = lane.U < io.in.bits.count + val raw = io.in.bits.entries(lane).uop.decoded.rob + val bound = io.robPrepared.entries(lane).rob + val brob = io.brobPrepared.entries(lane) + !active || (io.robPrepared.entries(lane).valid && brob.valid && + raw.peId === bound.peId && raw.stid === bound.stid && + raw.ridSlot === bound.ridSlot && + raw.ridGeneration === bound.ridGeneration && + raw.memberIndex === bound.memberIndex && + brob.stid === bound.stid && + bound.bid === brob.bid && + bound.brobGeneration === brob.brobGeneration) }.reduce(_ && _) - val stale = inRange && ( - io.in.bits.plan.transactionId =/= nextTransactionId(inStid) || - io.in.bits.plan.virtualTailEpoch =/= liveEpoch || - !firstKey.valid || firstKey.ridSlot =/= liveSlot || - firstKey.ridGeneration =/= liveGeneration || - firstKey.peId =/= io.in.bits.plan.peId || firstKey.stid =/= inStid || - !groupCountInRange || io.in.bits.groupMask =/= expectedGroupMask || - !planIdentityExact || !allGroupKeysExact) - // Combinational preview is deliberately independent of `in.valid`. The - // composition layer uses it to consume stale plans even when another D3 - // resource owner would reject their obsolete demand or operand shape. - io.planStale := stale - val releaseStid = io.release.bits.firstGroup.stid - val releaseInRange = releaseStid < p.stidCount.U - val safeReleaseStid = Mux(releaseInRange, releaseStid, 0.U) - val releaseExact = releaseInRange && - io.release.bits.firstGroup.valid && - io.release.bits.firstGroup.peId === headPeId(safeReleaseStid) && - io.release.bits.firstGroup.ridSlot === headSlot(safeReleaseStid) && - io.release.bits.firstGroup.ridGeneration === headGeneration(safeReleaseStid) && - io.release.bits.headEpoch === headEpoch(safeReleaseStid) && - io.release.bits.groupCount.orR && - io.release.bits.groupCount <= p.retireGroupWidth.U && - publishedGroups(safeReleaseStid) >= io.release.bits.groupCount && - !(recoveryTargetsStid && releaseStid === recoveryStid) - io.release.ready := releaseExact - val releaseFire = io.release.valid && io.release.ready - val releaseHitsInput = releaseFire && releaseStid === inStid - val releasedForInput = Mux(releaseHitsInput, io.release.bits.groupCount, 0.U) - val freeAfterRelease = - p.robGroupsPerStid.U((usedWidth + 1).W) - usedGroups(inStid).pad(usedWidth + 1) + - releasedForInput.pad(usedWidth + 1) - val hasCapacity = freeAfterRelease >= groupCount.pad(usedWidth + 1) - val replacingSelected = io.out.fire && selected === inStid - val occupied = if (p.stidCount == 1) valid(0) else valid(inStid) - val cancelled = (if (p.stidCount == 1) io.cancel(0) else io.cancel(inStid)) && - !(recoveryTargetsStid && inStid === recoveryStid) - val recoveryBlocksInput = recoveryTargetsStid && inStid === recoveryStid - - io.in.ready := inRange && Mux( - stale, - !recoveryBlocksInput, - !recoveryBlocksInput && !cancelled && groupCount.orR && hasCapacity && - (!occupied || replacingSelected)) - val inFire = io.in.valid && io.in.ready - val staleFire = inFire && stale - val reserveFire = inFire && !stale - - io.staleRejected.valid := staleFire - io.staleRejected.bits.stid := inStid - io.staleRejected.bits.transactionId := io.in.bits.plan.transactionId - io.staleRejected.bits.plannedTailEpoch := io.in.bits.plan.virtualTailEpoch - io.staleRejected.bits.liveTailEpoch := liveEpoch - io.releaseRejected.valid := io.release.valid && !io.release.ready - io.releaseRejected.bits.requested := io.release.bits - io.releaseRejected.bits.liveHead.valid := releaseInRange && publishedGroups(safeReleaseStid).orR - io.releaseRejected.bits.liveHead.peId := Mux(releaseInRange, headPeId(safeReleaseStid), 0.U) - io.releaseRejected.bits.liveHead.stid := releaseStid - io.releaseRejected.bits.liveHead.ridSlot := Mux(releaseInRange, headSlot(safeReleaseStid), 0.U) - io.releaseRejected.bits.liveHead.ridGeneration := - Mux(releaseInRange, headGeneration(safeReleaseStid), 0.U) - io.releaseRejected.bits.liveHeadEpoch := Mux(releaseInRange, headEpoch(safeReleaseStid), 0.U) - io.capacityBlocked := io.in.valid && inRange && !stale && !hasCapacity - - val recoveryOldTailSum = recoveryPlan.oldHead.ridSlot +& - recoveryPlan.oldOccupied - val recoveryOldTailWrap = recoveryOldTailSum >= p.robGroupsPerStid.U - val recoveryNewTailSum = recoveryPlan.oldHead.ridSlot +& - recoveryPlan.newOccupied - val recoveryNewTailWrap = recoveryNewTailSum >= p.robGroupsPerStid.U - val recoveryExpectedKilledMask = - ((1.U((p.robGroupsPerStid + 1).W) << - recoveryPlan.killedGroupCount) - 1.U)(p.robGroupsPerStid - 1, 0) - val recoveryProvisional = valid(safeRecoveryStid) - val recoveryProvisionalCount = Mux(recoveryProvisional, - rows(safeRecoveryStid).transaction.plan.groupCount, 0.U) - val recoveryLiveTail = Wire(new RobGroupKey(p)) - recoveryLiveTail.valid := true.B - recoveryLiveTail.peId := headPeId(safeRecoveryStid) - recoveryLiveTail.stid := recoveryStid - recoveryLiveTail.ridSlot := tailSlot(safeRecoveryStid) - recoveryLiveTail.ridGeneration := tailGeneration(safeRecoveryStid) - val recoveryExposedConflict = io.out.valid && selected === recoveryStid - val recoveryHeadExact = recoveryPlan.oldHead.valid && - recoveryPlan.oldHead.peId === headPeId(safeRecoveryStid) && - recoveryPlan.oldHead.stid === recoveryStid && - recoveryPlan.oldHead.ridSlot === headSlot(safeRecoveryStid) && - recoveryPlan.oldHead.ridGeneration === headGeneration(safeRecoveryStid) - val recoveryOldTailExact = recoveryPlan.oldTail.valid && - recoveryPlan.oldTail.peId === recoveryPlan.oldHead.peId && - recoveryPlan.oldTail.stid === recoveryStid && - recoveryPlan.oldTail.ridSlot === - recoveryOldTailSum(p.ridSlotWidth - 1, 0) && - recoveryPlan.oldTail.ridGeneration === - recoveryPlan.oldHead.ridGeneration + recoveryOldTailWrap.asUInt - val recoveryNewTailExact = recoveryPlan.newTail.valid && - recoveryPlan.newTail.peId === recoveryPlan.oldHead.peId && - recoveryPlan.newTail.stid === recoveryStid && - recoveryPlan.newTail.ridSlot === - recoveryNewTailSum(p.ridSlotWidth - 1, 0) && - recoveryPlan.newTail.ridGeneration === - recoveryPlan.oldHead.ridGeneration + recoveryNewTailWrap.asUInt - val recoveryCountExact = recoveryPlan.oldOccupied.orR && - recoveryPlan.oldOccupied === publishedGroups(safeRecoveryStid) && - recoveryPlan.newOccupied <= recoveryPlan.oldOccupied && - recoveryPlan.killedGroupCount === - recoveryPlan.oldOccupied - recoveryPlan.newOccupied && - recoveryPlan.killedGroupMask === recoveryExpectedKilledMask && - recoveryPlan.newOccupied === recoveryPlan.pivotOffset + - recoveryPlan.survivingPivotValid.asUInt - val recoveryProvisionalExact = Mux( - recoveryProvisional, - rows(safeRecoveryStid).transaction.plan.firstVirtualGroup.asUInt === - recoveryPlan.oldTail.asUInt && - rows(safeRecoveryStid).tailAfter.asUInt === recoveryLiveTail.asUInt && - usedGroups(safeRecoveryStid) === - publishedGroups(safeRecoveryStid) + recoveryProvisionalCount, - recoveryLiveTail.asUInt === recoveryPlan.oldTail.asUInt && - usedGroups(safeRecoveryStid) === publishedGroups(safeRecoveryStid)) - val recoveryExact = recoveryPlan.valid && recoveryStidInRange && - recoveryHeadExact && recoveryOldTailExact && recoveryNewTailExact && - recoveryCountExact && recoveryProvisionalExact - io.recoveryPrepareReady := io.recoveryPrepare.valid && recoveryExact && - !recoveryExposedConflict - io.recoveryRejected.valid := io.recoveryPrepare.valid && !recoveryExact - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.liveHead.valid := - publishedGroups(safeRecoveryStid).orR - io.recoveryRejected.bits.liveHead.peId := headPeId(safeRecoveryStid) - io.recoveryRejected.bits.liveHead.stid := recoveryStid - io.recoveryRejected.bits.liveHead.ridSlot := headSlot(safeRecoveryStid) - io.recoveryRejected.bits.liveHead.ridGeneration := - headGeneration(safeRecoveryStid) - io.recoveryRejected.bits.liveTail := recoveryLiveTail - io.recoveryRejected.bits.usedGroups := usedGroups(safeRecoveryStid) - io.recoveryRejected.bits.publishedGroups := - publishedGroups(safeRecoveryStid) - io.recoveryRejected.bits.provisional := recoveryProvisional - io.recoveryRejected.bits.exposedConflict := recoveryExposedConflict - - val tailSum = liveSlot +& groupCount - val tailWrap = tailSum >= p.robGroupsPerStid.U - val reservation = Wire(new OooD3GroupedReservation(p)) - reservation := 0.U.asTypeOf(reservation) - reservation.transaction := io.in.bits - reservation.claimEpoch := liveEpoch - reservation.tailAfter.valid := true.B - reservation.tailAfter.peId := io.in.bits.plan.peId - reservation.tailAfter.stid := inStid - reservation.tailAfter.ridSlot := tailSum(p.ridSlotWidth - 1, 0) - reservation.tailAfter.ridGeneration := liveGeneration + tailWrap.asUInt - - for (stid <- 0 until p.stidCount) { - val cancelClaim = io.cancel(stid) && valid(stid) && - !(recoveryTargetsStid && recoveryStid === stid.U) - val releaseHit = releaseFire && releaseStid === stid.U - val reserveHit = reserveFire && inStid === stid.U - val publishHit = io.out.fire && selected === stid.U - val releaseCount = Mux(releaseHit, io.release.bits.groupCount, 0.U) - val cancelCount = Mux(cancelClaim, rows(stid).transaction.plan.groupCount, 0.U) - val reserveCount = Mux(reserveHit, groupCount, 0.U) - - when(releaseHit || cancelClaim || reserveHit) { - usedGroups(stid) := usedGroups(stid) + reserveCount.pad(usedWidth) - - releaseCount.pad(usedWidth) - cancelCount.pad(usedWidth) - tailEpoch(stid) := tailEpoch(stid) + - releaseHit.asUInt + cancelClaim.asUInt + reserveHit.asUInt - } - when(releaseHit || publishHit) { - publishedGroups(stid) := publishedGroups(stid) + - Mux(publishHit, rows(stid).transaction.plan.groupCount, 0.U).pad(usedWidth) - - Mux(releaseHit, io.release.bits.groupCount, 0.U).pad(usedWidth) - } - when(releaseHit) { - val headSum = headSlot(stid) +& io.release.bits.groupCount - val headWrap = headSum >= p.robGroupsPerStid.U - headSlot(stid) := headSum(p.ridSlotWidth - 1, 0) - headGeneration(stid) := headGeneration(stid) + headWrap.asUInt - headEpoch(stid) := headEpoch(stid) + 1.U - } - when(cancelClaim) { - tailSlot(stid) := rows(stid).transaction.plan.firstVirtualGroup.ridSlot - tailGeneration(stid) := rows(stid).transaction.plan.firstVirtualGroup.ridGeneration + val inputStid = io.in.bits.entries(0).uop.decoded.rob.stid + val recoveryBlocksInput = recoveryPending && + recoveryPlan.trigger.stid === inputStid + val remaining = held.count - cursor + val drainsHeld = heldValid && io.advance.orR && io.advance === remaining + io.in.ready := (!heldValid || drainsHeld) && !recoveryBlocksInput && + inputCountExact && preparedExact + + val published = io.in.fire + when(heldValid && io.advance =/= 0.U) { + assert(io.advance <= remaining) + when(io.advance === remaining) { + heldValid := false.B + cursor := 0.U + }.otherwise { + cursor := cursor + io.advance } - when(reserveHit) { - when(usedGroups(stid) === Mux(releaseHit, io.release.bits.groupCount, 0.U)) { - headPeId(stid) := io.in.bits.plan.peId + } + when(published) { + held := io.in.bits + for (lane <- 0 until p.ooo.d3PrefixWidth) { + when(lane.U < io.in.bits.count) { + held.entries(lane).uop.decoded.rob := io.robPrepared.entries(lane).rob } - tailSlot(stid) := reservation.tailAfter.ridSlot - tailGeneration(stid) := reservation.tailAfter.ridGeneration - nextTransactionId(stid) := nextTransactionId(stid) + 1.U - rows(stid) := reservation - } - - when(io.cancel(stid) && - !(recoveryTargetsStid && recoveryStid === stid.U)) { - valid(stid) := false.B - }.elsewhen(io.out.fire && selected === stid.U) { - valid(stid) := false.B - } - when(reserveHit) { - valid(stid) := true.B } + heldValid := true.B + cursor := 0.U + heldTransactionBase := nextTransaction + nextTransaction := nextTransaction + io.in.bits.count } - - when(io.out.valid && !io.out.ready && !heldGrantValid) { - heldGrantValid := true.B - heldGrantStid := selected - } - when(heldGrantValid && (if (p.stidCount == 1) io.cancel(0) else io.cancel(heldGrantStid))) { - heldGrantValid := false.B - } - when(io.out.fire) { - heldGrantValid := false.B - rrStart := - (if (p.stidCount == 1) 0.U else (selected + 1.U)(p.stidWidth - 1, 0)) + when(sameApply && heldValid && + held.entries(0).uop.decoded.rob.stid === recoveryPlan.trigger.stid) { + heldValid := false.B + cursor := 0.U } - val recoveryApply = io.recoveryFire && io.recoveryPrepareReady - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady, - "D3 recovery fire requires the same exact prepared ROB suffix") - } - when(recoveryApply) { - tailSlot(safeRecoveryStid) := recoveryPlan.newTail.ridSlot - tailGeneration(safeRecoveryStid) := recoveryPlan.newTail.ridGeneration - tailEpoch(safeRecoveryStid) := tailEpoch(safeRecoveryStid) + 1.U - usedGroups(safeRecoveryStid) := recoveryPlan.newOccupied - publishedGroups(safeRecoveryStid) := recoveryPlan.newOccupied - valid(safeRecoveryStid) := false.B - rows(safeRecoveryStid) := - 0.U.asTypeOf(new OooD3GroupedReservation(p)) - } - - io.tailSlot := tailSlot - io.tailGeneration := tailGeneration - io.tailEpoch := tailEpoch - io.nextTransactionId := nextTransactionId - io.headSlot := headSlot - io.headGeneration := headGeneration - io.headEpoch := headEpoch - io.usedGroups := usedGroups - io.publishedGroups := publishedGroups - io.provisionalMask := valid.asUInt - - when(reserveFire) { - assert(io.in.bits.plan.transactionId === nextTransactionId(inStid)) - assert(groupCount <= p.robGroupsPerStid.U) - } - when(heldGrantValid && io.out.valid && !io.out.ready) { - assert(io.out.bits.transaction.plan.stid === heldGrantStid) - } + io.pendingValid := heldValid + io.pending := held + io.cursor := cursor + io.transactionBase := heldTransactionBase + io.publicationTransactionBase := nextTransaction } diff --git a/chisel/src/main/scala/linxcore/ooo/OooDispatch.scala b/chisel/src/main/scala/linxcore/ooo/OooDispatch.scala index e1b30fc0..b321b202 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooDispatch.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooDispatch.scala @@ -1,609 +1,240 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, Mux1H, PopCount, PriorityEncoder, UIntToOH, - Valid} - -object OooDispatchSlotState extends ChiselEnum { - val Free, Provisional, Published = Value +import chisel3.util.{Decoupled, DecoupledIO, PopCount, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +class OOODispatchChannels(val p: CoreParams) extends Bundle { + val aluDispatch = Vec(p.iex.aluPipes, Decoupled(new DispatchTxn(p))) + val bruDispatch = Vec(p.iex.bruPipes, Decoupled(new DispatchTxn(p))) + val aguDispatch = Vec(p.iex.aguPipes, Decoupled(new DispatchTxn(p))) + val storeDispatch = Vec(p.iex.stdPipes, Decoupled(new StoreDispatchTxn(p))) + val systemDispatch = Vec(p.iex.systemMulticycleQueues, + Decoupled(new DispatchTxn(p))) + val cmdDispatch = Vec(p.iex.cmdIssueQueues, Decoupled(new DispatchTxn(p))) } -class OooDispatchIO(val p: OooParams = OooParams()) extends Bundle { - val prepare = Flipped(Valid(new OooD2GroupedTransaction(p))) - val prepareReady = Output(Bool()) - val prepared = Output(new OooDispatchReservationLease(p)) - val reserveFire = Input(Bool()) - val cancel = Input(Vec(p.stidCount, Bool())) - - val publish = Flipped(Valid(new OooDispatchPublish(p))) - val releases = Flipped(Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p)))) - def release = releases(0) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooDispatchRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - - val provisional = Output(Vec(p.stidCount, - new OooDispatchReservationLease(p))) - val freeEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val provisionalEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val publishedEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val publishedByStid = Output(Vec(p.stidCount, - UInt(p.countWidth(p.iqClassCount * p.iqBankCount * - p.iqEntriesPerBank).W))) - - val prepareRejected = Valid(new OooDispatchPrepareReject(p)) - val publishRejected = Valid(new OooDispatchPublishReject(p)) - val releaseRejecteds = Vec(p.iexReleaseWidth, - Valid(new OooDispatchReleaseReject(p))) - def releaseRejected = releaseRejecteds(0) - val recoveryRejected = Valid(new OooDispatchRecoveryReject(p)) +class OooDispatchIO(val p: CoreParams) extends Bundle { + val valid = Input(Bool()) + val group = Input(new D3RenameGroup(p)) + val cursor = Input(UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W)) + val transactionBase = Input(UInt(p.transactionIdWidth.W)) + val suppress = Input(Bool()) + val iex = new OOODispatchChannels(p) + val advance = Output(UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W)) } -/** D3 owner for exact speculative issue-queue reservations. - * - * Generated dispatch demand is compacted in logical-uop/class/child order. - * Every child receives an exact class, sub-bank, write port, slot, and reuse - * generation. The complete bundle reserves or publishes atomically; a later - * IEX owner may release only the identical published token. - */ -class OooDispatch( - val p: OooParams = OooParams(), - val capabilityTopology: OooIexCapabilityTopology = - OooIexCapabilityTopology(Seq.empty)) extends Module { - private val effectiveCapabilityTopology = - if (capabilityTopology.classBankCapabilities.isEmpty) - OooIexCapabilityTopology.permissive(p) - else capabilityTopology - effectiveCapabilityTopology.validate(p) +/** Stateless canonical class/credit mapper for one retained D3 suffix. */ +class OooDispatch(val p: CoreParams) extends Module { val io = IO(new OooDispatchIO(p)) - - private val candidateCount = p.decodedUopWidth * p.iqClassCount * - p.maxDispatchWritesPerInstruction - private val childIndexWidth = math.max(1, - chisel3.util.log2Ceil(p.maxDispatchWritesPerInstruction)) - - private val classValues = VecInit(Seq( - OooUopClass.Alu, - OooUopClass.Bru, - OooUopClass.Agu, - OooUopClass.Std, - OooUopClass.Fsu, - OooUopClass.Sys, - OooUopClass.Cmd, - OooUopClass.Boundary)) - private val classBankCapabilities = VecInit( - effectiveCapabilityTopology.classBankCapabilities.map { banks => - VecInit(banks.map(_.U(OooIexDomainCapability.Count.W))) - }) - - val slotState = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(OooDispatchSlotState.Free))))))) - val slotGeneration = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)( - 0.U(p.reservationEpochWidth.W)))))))) - val slotWritePort = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)( - 0.U(p.iqWritePortWidth.W)))))))) - val slotPeId = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(0.U(p.peIdWidth.W)))))))) - val slotStid = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(0.U(p.stidWidth.W)))))))) - val slotEpoch = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(0.U(p.epochWidth.W)))))))) - val slotTransaction = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)( - 0.U(p.transactionIdWidth.W)))))))) - val slotMemberValid = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(false.B))))))) - val slotMember = Reg(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iqEntriesPerBank, new RobMemberKey(p))))) - val provisional = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooDispatchReservationLease(p))))) - - val recoveryPlan = io.recoveryPrepare.bits - val recoveryStid = recoveryPlan.oldHead.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryFreeze = io.recoveryPrepare.valid && recoveryPlan.valid && - recoveryStidInRange - - val freeMask = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqEntriesPerBank.W)))) - for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount) { - freeMask(uopClass)(bank) := VecInit((0 until p.iqEntriesPerBank).map { - entry => slotState(uopClass)(bank)(entry) === OooDispatchSlotState.Free - }).asUInt - io.freeEntries(uopClass)(bank) := PopCount(VecInit( - (0 until p.iqEntriesPerBank).map { entry => - slotState(uopClass)(bank)(entry) === OooDispatchSlotState.Free - }).asUInt) - io.provisionalEntries(uopClass)(bank) := PopCount(VecInit( - (0 until p.iqEntriesPerBank).map { entry => - slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Provisional - }).asUInt) - io.publishedEntries(uopClass)(bank) := PopCount(VecInit( - (0 until p.iqEntriesPerBank).map { entry => - slotState(uopClass)(bank)(entry) === OooDispatchSlotState.Published - }).asUInt) + private val width = p.ooo.d3PrefixWidth + private def fitIndex(value: UInt, entries: Int): UInt = + if (entries == 1) 0.U else value(log2Ceil(entries) - 1, 0) + private def laneAt(value: UInt): D3RenameLane = + io.group.entries(fitIndex(Mux(value < width.U, value, 0.U), width)) + private def readyAt(values: Vec[DecoupledIO[DispatchTxn]], value: UInt): Bool = + if (values.length == 1) values.head.ready + else values(fitIndex(value, values.length)).ready + private def storeReadyAt(value: UInt): Bool = + if (io.iex.storeDispatch.length == 1) io.iex.storeDispatch.head.ready + else io.iex.storeDispatch(fitIndex(value, io.iex.storeDispatch.length)).ready + private val aluClass = OooDispatchClass.Alu - 1 + private val aguClass = OooDispatchClass.Agu - 1 + private val stdClass = OooDispatchClass.Std - 1 + private def hasCapability( + lane: D3RenameLane, + issueClass: Int, + capability: Int): Bool = + lane.uop.decoded.classification + .executionPipeCapability(issueClass)(capability) + private def routesAlu(lane: D3RenameLane): Bool = + lane.uop.decoded.classification.valid && + lane.uop.decoded.classification.dispatchClass === OooDispatchClass.Alu.U && + hasCapability(lane, aluClass, OooIexDomainCapability.SimpleAlu) + private def routesBru(lane: D3RenameLane): Bool = + lane.uop.decoded.classification.valid && + lane.uop.decoded.classification.dispatchClass === OooDispatchClass.Bru.U && + hasCapability(lane, OooDispatchClass.Bru - 1, + OooIexDomainCapability.Branch) + private def routesAgu(lane: D3RenameLane): Bool = + lane.uop.decoded.classification.valid && + lane.uop.decoded.classification.dispatchClass === OooDispatchClass.Agu.U && + hasCapability(lane, aguClass, OooIexDomainCapability.LoadAddress) + private def routesStore(lane: D3RenameLane): Bool = + lane.uop.decoded.classification.valid && + lane.uop.decoded.classification.dispatchClass === OooDispatchClass.Std.U && + hasCapability(lane, aguClass, OooIexDomainCapability.StoreAddress) && + hasCapability(lane, stdClass, OooIexDomainCapability.StoreData) + private def routesSystem(lane: D3RenameLane): Bool = { + val classification = lane.uop.decoded.classification + val systemClass = classification.dispatchClass === OooDispatchClass.Sys.U && + hasCapability(lane, OooDispatchClass.Sys - 1, + OooIexDomainCapability.System) + val multicycleAlu = + classification.dispatchClass === OooDispatchClass.Alu.U && + (hasCapability(lane, aluClass, + OooIexDomainCapability.MultiCycleAlu) || + hasCapability(lane, aluClass, OooIexDomainCapability.PointerAuth)) + classification.valid && (systemClass || multicycleAlu) } - io.provisional := provisional - for (stid <- 0 until p.stidCount) { - io.publishedByStid(stid) := PopCount(VecInit( - (0 until p.iqClassCount).flatMap { uopClass => - (0 until p.iqBankCount).flatMap { bank => - (0 until p.iqEntriesPerBank).map { entry => - slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Published && - slotStid(uopClass)(bank)(entry) === stid.U - } - } - }).asUInt) + private def routesCmd(lane: D3RenameLane): Bool = + lane.uop.decoded.classification.valid && + lane.uop.decoded.classification.dispatchClass === OooDispatchClass.Cmd.U && + hasCapability(lane, OooDispatchClass.Cmd - 1, + OooIexDomainCapability.EngineCommand) + private def routesFastResult(lane: D3RenameLane): Bool = { + val classification = lane.uop.decoded.classification + classification.valid && + classification.disposition === OooOpcodeDisposition.FastResolve.U && + (classification.fastResolveClass === + OooFastResolveClass.ImmediateProducer.U || + classification.fastResolveClass === + OooFastResolveClass.ControlValueProducer.U) } - val transaction = io.prepare.bits - val plan = transaction.plan - val decoded = transaction.decoded - val prepareStid = plan.stid - val prepareStidInRange = prepareStid < p.stidCount.U - val safePrepareStid = Mux(prepareStidInRange, prepareStid, 0.U) - val uopMaskExact = plan.uopMask === decoded.uopMask && - decoded.uopMask === transaction.plan.uopMask - val identityExact = plan.peId === decoded.peId && - plan.stid === decoded.stid && plan.epoch === decoded.epoch - - val candidateActive = Wire(Vec(candidateCount, Bool())) - val candidateUop = Wire(Vec(candidateCount, - UInt(p.decodedUopIndexWidth.W))) - val candidateClass = Wire(Vec(candidateCount, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val candidateChild = Wire(Vec(candidateCount, UInt(childIndexWidth.W))) - var candidateIndex = 0 - for (uopIndex <- 0 until p.decodedUopWidth; - uopClass <- 0 until p.iqClassCount; - repeat <- 0 until p.maxDispatchWritesPerInstruction) { - val uop = decoded.uops(uopIndex) - candidateActive(candidateIndex) := decoded.uopMask(uopIndex) && uop.valid && - repeat.U < uop.recipe.dispatchDemand(uopClass) - candidateUop(candidateIndex) := uopIndex.U - candidateClass(candidateIndex) := uopClass.U - val olderClassWrites = if (uopClass == 0) 0.U else - uop.recipe.dispatchDemand.take(uopClass).reduce(_ +& _) - candidateChild(candidateIndex) := - (olderClassWrites + repeat.U)(childIndexWidth - 1, 0) - candidateIndex += 1 + io.iex.aluDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } - val requestedWrites = PopCount(candidateActive) - - val uopDispatchShapeExact = (0 until p.decodedUopWidth).map { uopIndex => - val uop = decoded.uops(uopIndex) - val active = decoded.uopMask(uopIndex) - val demandTotal = uop.recipe.dispatchDemand.reduce(_ +& _) - val capabilityShapeExact = (0 until p.iqClassCount).map { classIndex => - val demand = uop.recipe.dispatchDemand(classIndex) - val capability = uop.recipe.dispatchCapabilities(classIndex) - demand.orR === capability.orR && PopCount(capability) <= 1.U - }.reduce(_ && _) - !active || (uop.valid && uop.recipe.valid && capabilityShapeExact && - demandTotal === uop.recipe.dispatchWrites && - uop.recipe.dispatchWrites <= p.maxDispatchWritesPerInstruction.U) - }.reduce(_ && _) - val classDemandExact = (0 until p.iqClassCount).map { uopClass => - val decodedDemand = decoded.uops.zipWithIndex.map { case (uop, index) => - Mux(decoded.uopMask(index) && uop.valid, - uop.recipe.dispatchDemand(uopClass), 0.U) - }.reduce(_ +& _) - decodedDemand === plan.demand.dispatchWritesByClass(uopClass) - }.reduce(_ && _) - val plannedWrites = plan.demand.dispatchWritesByClass.reduce(_ +& _) - val requestShapeExact = uopMaskExact && identityExact && - uopDispatchShapeExact && classDemandExact && - requestedWrites === plannedWrites && requestedWrites <= p.dispatchWidth.U - - val laneActive = Wire(Vec(p.dispatchWidth, Bool())) - val laneUop = Wire(Vec(p.dispatchWidth, - UInt(p.decodedUopIndexWidth.W))) - val laneClass = Wire(Vec(p.dispatchWidth, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val laneChild = Wire(Vec(p.dispatchWidth, UInt(childIndexWidth.W))) - for (lane <- 0 until p.dispatchWidth) { - laneActive(lane) := lane.U < requestedWrites - val candidateSelect = Wire(Vec(candidateCount, Bool())) - for (index <- 0 until candidateCount) { - val olderCount = if (index == 0) 0.U else - PopCount(candidateActive.take(index)) - candidateSelect(index) := candidateActive(index) && - olderCount === lane.U - } - laneUop(lane) := Mux1H(candidateSelect, candidateUop) - laneClass(lane) := Mux1H(candidateSelect, candidateClass) - laneChild(lane) := Mux1H(candidateSelect, candidateChild) + io.iex.bruDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } - - val selectedValid = Wire(Vec(p.dispatchWidth, Bool())) - val selectedBank = Wire(Vec(p.dispatchWidth, UInt(p.iqBankWidth.W))) - val selectedPort = Wire(Vec(p.dispatchWidth, UInt(p.iqWritePortWidth.W))) - val selectedSlot = Wire(Vec(p.dispatchWidth, UInt(p.iqEntryWidth.W))) - val selectedEpoch = Wire(Vec(p.dispatchWidth, - UInt(p.reservationEpochWidth.W))) - val laneRequiredCapability = Wire(Vec(p.dispatchWidth, - UInt(OooIexDomainCapability.Count.W))) - - for (lane <- 0 until p.dispatchWidth) { - laneRequiredCapability(lane) := decoded.uops(laneUop(lane)).recipe - .dispatchCapabilities(laneClass(lane)) + io.iex.aguDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } - - for (lane <- 0 until p.dispatchWidth) { - val olderPrefixReady = if (lane == 0) true.B else - (0 until lane).map { older => - !laneActive(older) || selectedValid(older) - }.reduce(_ && _) - val usedMask = Wire(Vec(p.iqBankCount, UInt(p.iqEntriesPerBank.W))) - val olderWrites = Wire(Vec(p.iqBankCount, - UInt(p.dispatchCountWidth.W))) - for (bank <- 0 until p.iqBankCount) { - val olderHere = if (lane == 0) Seq(false.B) else - (0 until lane).map { older => - selectedValid(older) && laneClass(older) === laneClass(lane) && - selectedBank(older) === bank.U - } - olderWrites(bank) := PopCount(VecInit(olderHere).asUInt) - val masks = if (lane == 0) Seq(0.U(p.iqEntriesPerBank.W)) else - (0 until lane).map { older => - Mux(selectedValid(older) && - laneClass(older) === laneClass(lane) && - selectedBank(older) === bank.U, - UIntToOH(selectedSlot(older), p.iqEntriesPerBank), - 0.U(p.iqEntriesPerBank.W)) - } - usedMask(bank) := masks.reduce(_ | _) - } - - val preferredBank = (plan.transactionId + laneUop(lane) + - laneClass(lane))(p.iqBankWidth - 1, 0) - val candidateBank = Wire(Vec(p.iqBankCount, UInt(p.iqBankWidth.W))) - val candidateAvailable = Wire(Vec(p.iqBankCount, - UInt(p.iqEntriesPerBank.W))) - val candidateValid = Wire(Vec(p.iqBankCount, Bool())) - val candidateSlot = Wire(Vec(p.iqBankCount, UInt(p.iqEntryWidth.W))) - for (offset <- 0 until p.iqBankCount) { - candidateBank(offset) := (preferredBank + offset.U)( - p.iqBankWidth - 1, 0) - candidateAvailable(offset) := - freeMask(laneClass(lane))(candidateBank(offset)) & - ~usedMask(candidateBank(offset)) - val freeSelect = Module(new OooHierarchicalFreeSlotSelect( - p.iqEntriesPerBank, p.iqFreeSelectLeafEntriesEffective)) - freeSelect.io.available := candidateAvailable(offset) - candidateValid(offset) := freeSelect.io.selectedValid && - olderWrites(candidateBank(offset)) < p.iqWritePortsPerBank.U && - OooIexDomainCapability.covers( - classBankCapabilities(laneClass(lane))(candidateBank(offset)), - laneRequiredCapability(lane)) - candidateSlot(offset) := freeSelect.io.selectedIndex - } - val chosenOffset = PriorityEncoder(candidateValid) - val chosenBank = candidateBank(chosenOffset) - val chosenSlot = candidateSlot(chosenOffset) - val canSelect = candidateValid.asUInt.orR - selectedValid(lane) := laneActive(lane) && olderPrefixReady && canSelect - selectedBank(lane) := chosenBank - selectedPort(lane) := olderWrites(chosenBank)(p.iqWritePortWidth - 1, 0) - selectedSlot(lane) := chosenSlot - selectedEpoch(lane) := slotGeneration(laneClass(lane))(chosenBank)( - chosenSlot) + 1.U + io.iex.storeDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } - - val allSelected = (0 until p.dispatchWidth).map { lane => - !laneActive(lane) || selectedValid(lane) - }.reduce(_ && _) - val noLiveLease = !provisional(safePrepareStid).valid - io.prepareReady := prepareStidInRange && requestShapeExact && - !io.cancel(safePrepareStid) && - !(recoveryFreeze && prepareStid === recoveryStid) && - noLiveLease && allSelected - - io.prepared := 0.U.asTypeOf(io.prepared) - io.prepared.valid := io.prepare.valid && io.prepareReady - io.prepared.peId := plan.peId - io.prepared.stid := plan.stid - io.prepared.epoch := plan.epoch - io.prepared.transactionId := plan.transactionId - io.prepared.allocationMask := VecInit((0 until p.dispatchWidth).map { - lane => laneActive(lane) && selectedValid(lane) - }).asUInt - for (lane <- 0 until p.dispatchWidth) { - val allocation = io.prepared.allocations(lane) - allocation.valid := laneActive(lane) && selectedValid(lane) - allocation.uopIndex := laneUop(lane) - allocation.childIndex := laneChild(lane) - allocation.reservation.valid := allocation.valid - allocation.reservation.uopClass := classValues(laneClass(lane)) - allocation.reservation.bank := selectedBank(lane) - allocation.reservation.writePort := selectedPort(lane) - allocation.reservation.speculativeSlot := selectedSlot(lane) - allocation.reservation.reservationEpoch := selectedEpoch(lane) + io.iex.systemDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } - - io.prepareRejected.valid := io.prepare.valid && !io.prepareReady - io.prepareRejected.bits.stid := prepareStid - io.prepareRejected.bits.transactionId := plan.transactionId - io.prepareRejected.bits.requestedWrites := requestedWrites - io.prepareRejected.bits.plannedWrites := plannedWrites - io.prepareRejected.bits.liveLease := provisional(safePrepareStid) - - for (stid <- 0 until p.stidCount) { - when(io.cancel(stid) && provisional(stid).valid) { - for (lane <- 0 until p.dispatchWidth) { - val allocation = provisional(stid).allocations(lane) - when(allocation.valid) { - val reservation = allocation.reservation - slotState(reservation.uopClass.asUInt)(reservation.bank)( - reservation.speculativeSlot) := OooDispatchSlotState.Free - slotMemberValid(reservation.uopClass.asUInt)(reservation.bank)( - reservation.speculativeSlot) := false.B - } - } - provisional(stid) := - 0.U.asTypeOf(new OooDispatchReservationLease(p)) - } + io.iex.cmdDispatch.foreach { out => + out.valid := false.B; out.bits := 0.U.asTypeOf(out.bits) } + val laneActive = Wire(Vec(width, Bool())) + val laneNeedsOutput = Wire(Vec(width, Bool())) + val laneStructurallyComplete = Wire(Vec(width, Bool())) + val laneComplete = Wire(Vec(width, Bool())) + val structuralPrefix = Wire(Vec(width + 1, Bool())) + val prefixComplete = Wire(Vec(width + 1, Bool())) + val nextActiveLane = Module(new OooHierarchicalFreeSlotSelect(width, 1)) + nextActiveLane.io.available := laneActive.asUInt + prefixComplete(0) := io.valid && !io.suppress && + nextActiveLane.io.selectedValid && nextActiveLane.io.selectedIndex === 0.U + structuralPrefix(0) := prefixComplete(0) + + for (offset <- 0 until width) { + val index = io.cursor + offset.U + val inRange = index < io.group.count + val lane = laneAt(index) + laneActive(offset) := inRange + val early = lane.earlyRobComplete || routesFastResult(lane) || + lane.uop.decoded.uopClass === UopClass.Boundary + laneNeedsOutput(offset) := inRange && !early + + val olderAlu = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + routesAlu(laneAt(io.cursor + older.U)) + }) + val olderBru = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + routesBru(laneAt(io.cursor + older.U)) + }) + val olderAgu = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + (routesAgu(laneAt(io.cursor + older.U)) || + routesStore(laneAt(io.cursor + older.U))) + }) + val olderStd = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + routesStore(laneAt(io.cursor + older.U)) + }) + val olderSystem = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + routesSystem(laneAt(io.cursor + older.U)) + }) + val olderCmd = if (offset == 0) 0.U else PopCount((0 until offset).map { older => + laneActive(older) && laneNeedsOutput(older) && + routesCmd(laneAt(io.cursor + older.U)) + }) - when(io.reserveFire) { - assert(io.prepared.valid, - "dispatch reserve must claim one complete prepared transaction") - provisional(safePrepareStid) := io.prepared - for (lane <- 0 until p.dispatchWidth) { - val allocation = io.prepared.allocations(lane) - when(allocation.valid) { - val reservation = allocation.reservation - val uopClass = reservation.uopClass.asUInt - val bank = reservation.bank - val slot = reservation.speculativeSlot - assert(slotState(uopClass)(bank)(slot) === OooDispatchSlotState.Free, - "dispatch reserve must own a free exact IQ slot") - slotState(uopClass)(bank)(slot) := OooDispatchSlotState.Provisional - slotGeneration(uopClass)(bank)(slot) := - reservation.reservationEpoch - slotWritePort(uopClass)(bank)(slot) := reservation.writePort - slotPeId(uopClass)(bank)(slot) := plan.peId - slotStid(uopClass)(bank)(slot) := prepareStid - slotEpoch(uopClass)(bank)(slot) := plan.epoch - slotTransaction(uopClass)(bank)(slot) := plan.transactionId - slotMemberValid(uopClass)(bank)(slot) := false.B - } + val txn = Wire(new DispatchTxn(p)) + txn.transactionId := io.transactionBase + index + txn.uop := lane.uop + txn.memoryOrder := lane.memoryOrder + txn.trap := lane.trap + txn.pcBufferIndexOffset := lane.pcBufferIndexOffset + // Payload and valid are functions only of the retained source group and + // static port geometry. Sink readiness controls `advance`, never the + // presented transaction. This is the Decoupled stability boundary. + val allowed = structuralPrefix(offset) && inRange && !early + val routeAlu = routesAlu(lane) + val routeBru = routesBru(lane) + val routeAgu = routesAgu(lane) + val routeStore = routesStore(lane) + val routeSystem = routesSystem(lane) + val routeCmd = routesCmd(lane) + val aluComplete = olderAlu < p.iex.aluPipes.U && + readyAt(io.iex.aluDispatch, olderAlu) + val bruComplete = olderBru < p.iex.bruPipes.U && + readyAt(io.iex.bruDispatch, olderBru) + val aguComplete = olderAgu < p.iex.aguPipes.U && + readyAt(io.iex.aguDispatch, olderAgu) + val storeComplete = olderAgu < p.iex.aguPipes.U && + olderStd < p.iex.stdPipes.U && storeReadyAt(olderStd) + val sysComplete = olderSystem < p.iex.systemMulticycleQueues.U && + readyAt(io.iex.systemDispatch, olderSystem) + val cmdComplete = olderCmd < p.iex.cmdIssueQueues.U && + readyAt(io.iex.cmdDispatch, olderCmd) + laneStructurallyComplete(offset) := !inRange || early || + (routeAlu && olderAlu < p.iex.aluPipes.U) || + (routeBru && olderBru < p.iex.bruPipes.U) || + (routeAgu && olderAgu < p.iex.aguPipes.U) || + (routeStore && olderAgu < p.iex.aguPipes.U && + olderStd < p.iex.stdPipes.U) || + (routeSystem && olderSystem < p.iex.systemMulticycleQueues.U) || + (routeCmd && olderCmd < p.iex.cmdIssueQueues.U) + laneComplete(offset) := laneStructurallyComplete(offset) && ( + !inRange || early || + (routeAlu && aluComplete) || + (routeBru && bruComplete) || + (routeAgu && aguComplete) || + (routeStore && storeComplete) || + (routeSystem && sysComplete) || + (routeCmd && cmdComplete)) + + for (pipe <- 0 until p.iex.aluPipes) when(allowed && routeAlu && olderAlu === pipe.U) { + io.iex.aluDispatch(pipe).valid := true.B; io.iex.aluDispatch(pipe).bits := txn } - } - - val publishStid = io.publish.bits.stid - val publishStidInRange = publishStid < p.stidCount.U - val safePublishStid = Mux(publishStidInRange, publishStid, 0.U) - val publishLease = provisional(safePublishStid) - val publishExact = publishStidInRange && !io.cancel(safePublishStid) && - !(recoveryFreeze && publishStid === recoveryStid) && - publishLease.valid && - publishLease.peId === io.publish.bits.peId && - publishLease.stid === publishStid && - publishLease.epoch === io.publish.bits.epoch && - publishLease.transactionId === io.publish.bits.transactionId && - io.publish.bits.memberMask === publishLease.allocationMask && - (0 until p.dispatchWidth).map { lane => - val allocation = publishLease.allocations(lane) - val member = io.publish.bits.members(lane) - !allocation.valid || (member.group.valid && member.bid.valid && - member.group.peId === publishLease.peId && - member.group.stid === publishLease.stid && - member.memberIndex < p.maxOrdinaryUopsPerGroup.U) - }.reduce(_ && _) - io.publishRejected.valid := io.publish.valid && !publishExact - io.publishRejected.bits.requested := io.publish.bits - io.publishRejected.bits.live := publishLease - when(io.publish.valid && publishExact) { - for (lane <- 0 until p.dispatchWidth) { - val allocation = publishLease.allocations(lane) - when(allocation.valid) { - val reservation = allocation.reservation - val uopClass = reservation.uopClass.asUInt - val bank = reservation.bank - val slot = reservation.speculativeSlot - assert(slotState(uopClass)(bank)(slot) === - OooDispatchSlotState.Provisional && - slotGeneration(uopClass)(bank)(slot) === - reservation.reservationEpoch && - slotWritePort(uopClass)(bank)(slot) === reservation.writePort && - slotPeId(uopClass)(bank)(slot) === io.publish.bits.peId && - slotStid(uopClass)(bank)(slot) === publishStid && - slotEpoch(uopClass)(bank)(slot) === io.publish.bits.epoch && - slotTransaction(uopClass)(bank)(slot) === - io.publish.bits.transactionId, - "dispatch publish must match every exact provisional IQ slot") - slotState(uopClass)(bank)(slot) := OooDispatchSlotState.Published - slotMemberValid(uopClass)(bank)(slot) := true.B - slotMember(uopClass)(bank)(slot) := io.publish.bits.members(lane) - } + for (pipe <- 0 until p.iex.bruPipes) when(allowed && routeBru && olderBru === pipe.U) { + io.iex.bruDispatch(pipe).valid := true.B; io.iex.bruDispatch(pipe).bits := txn } - provisional(safePublishStid) := - 0.U.asTypeOf(new OooDispatchReservationLease(p)) - } - - val releaseClasses = Wire(Vec(p.iexReleaseWidth, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val releaseClassInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseBankInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseSlotInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val safeReleaseClasses = Wire(Vec(p.iexReleaseWidth, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val safeReleaseBanks = Wire(Vec(p.iexReleaseWidth, - UInt(p.iqBankWidth.W))) - val safeReleaseSlots = Wire(Vec(p.iexReleaseWidth, - UInt(p.iqEntryWidth.W))) - val releaseAddressExact = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseOwnerExact = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseCollision = Wire(Vec(p.iexReleaseWidth, Bool())) - - for (lane <- 0 until p.iexReleaseWidth) { - val release = io.releases(lane).bits - releaseClasses(lane) := release.reservation.uopClass.asUInt - releaseClassInRange(lane) := releaseClasses(lane) < p.iqClassCount.U - releaseBankInRange(lane) := release.reservation.bank < p.iqBankCount.U - releaseSlotInRange(lane) := - release.reservation.speculativeSlot < p.iqEntriesPerBank.U - safeReleaseClasses(lane) := Mux( - releaseClassInRange(lane), releaseClasses(lane), 0.U) - safeReleaseBanks(lane) := Mux( - releaseBankInRange(lane), release.reservation.bank, 0.U) - safeReleaseSlots(lane) := Mux( - releaseSlotInRange(lane), release.reservation.speculativeSlot, 0.U) - releaseAddressExact(lane) := release.reservation.valid && - releaseClassInRange(lane) && releaseBankInRange(lane) && - releaseSlotInRange(lane) - releaseOwnerExact(lane) := releaseAddressExact(lane) && - slotState(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === OooDispatchSlotState.Published && - slotGeneration(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.reservation.reservationEpoch && - slotWritePort(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.reservation.writePort && - slotPeId(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.peId && - slotStid(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.stid && - slotEpoch(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.epoch && - slotTransaction(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) === release.transactionId && - slotMemberValid(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) && - slotMember(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)).asUInt === release.member.asUInt && - !(recoveryFreeze && release.stid === recoveryStid) - releaseCollision(lane) := (0 until p.iexReleaseWidth).filter(_ != lane) - .map { peer => - io.releases(peer).valid && releaseAddressExact(lane) && - releaseAddressExact(peer) && - safeReleaseClasses(lane) === safeReleaseClasses(peer) && - safeReleaseBanks(lane) === safeReleaseBanks(peer) && - safeReleaseSlots(lane) === safeReleaseSlots(peer) - }.foldLeft(false.B)(_ || _) - val releaseExact = releaseOwnerExact(lane) && !releaseCollision(lane) - io.releases(lane).ready := releaseExact - io.releaseRejecteds(lane).valid := - io.releases(lane).valid && !releaseExact - io.releaseRejecteds(lane).bits.requested := release - when(io.releases(lane).fire) { - slotState(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) := OooDispatchSlotState.Free - slotMemberValid(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseSlots(lane)) := false.B + for (pipe <- 0 until p.iex.aguPipes) when(allowed && + routeAgu && olderAgu === pipe.U) { + io.iex.aguDispatch(pipe).valid := true.B; io.iex.aguDispatch(pipe).bits := txn } - } - - val recoveryPublishedExact = (0 until p.iqClassCount).flatMap { uopClass => - (0 until p.iqBankCount).flatMap { bank => - (0 until p.iqEntriesPerBank).map { entry => - val selected = slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Published && - slotStid(uopClass)(bank)(entry) === recoveryStid - !selected || (slotMemberValid(uopClass)(bank)(entry) && - slotMember(uopClass)(bank)(entry).group.valid && - slotMember(uopClass)(bank)(entry).bid.valid && - slotMember(uopClass)(bank)(entry).group.peId === - slotPeId(uopClass)(bank)(entry) && - slotMember(uopClass)(bank)(entry).group.stid === - slotStid(uopClass)(bank)(entry) && - OooRecoveryMembership.memberInOldWindow( - p, recoveryPlan, slotMember(uopClass)(bank)(entry))) - } + for (pipe <- 0 until p.iex.stdPipes) when(allowed && routeStore && + olderAgu < p.iex.aguPipes.U && olderStd === pipe.U) { + io.iex.storeDispatch(pipe).valid := true.B + io.iex.storeDispatch(pipe).bits.sta := txn + io.iex.storeDispatch(pipe).bits.std := txn + io.iex.storeDispatch(pipe).bits.aguPipe := fitIndex(olderAgu, p.iex.aguPipes) + io.iex.storeDispatch(pipe).bits.stdPipe := fitIndex(olderStd, p.iex.stdPipes) } - }.reduce(_ && _) - val recoveryProvisionalKilled = PopCount(VecInit( - (0 until p.iqClassCount).flatMap { uopClass => - (0 until p.iqBankCount).flatMap { bank => - (0 until p.iqEntriesPerBank).map { entry => - slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Provisional && - slotStid(uopClass)(bank)(entry) === recoveryStid - } - } - }).asUInt) - val recoveryPublishedKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, Bool())))) - for (uopClass <- 0 until p.iqClassCount; - bank <- 0 until p.iqBankCount; - entry <- 0 until p.iqEntriesPerBank) { - recoveryPublishedKill(uopClass)(bank)(entry) := - slotState(uopClass)(bank)(entry) === OooDispatchSlotState.Published && - slotStid(uopClass)(bank)(entry) === recoveryStid && - slotMemberValid(uopClass)(bank)(entry) && - OooRecoveryMembership.memberKilled( - p, recoveryPlan, slotMember(uopClass)(bank)(entry)) - } - val recoveryPublishedKilled = PopCount(VecInit( - (0 until p.iqClassCount).flatMap { uopClass => - (0 until p.iqBankCount).flatMap { bank => - (0 until p.iqEntriesPerBank).map { entry => - recoveryPublishedKill(uopClass)(bank)(entry) - } - } - }).asUInt) - val recoveryPrepareExact = recoveryPlan.valid && recoveryStidInRange && - recoveryPublishedExact - io.recoveryPrepareReady := io.recoveryPrepare.valid && recoveryPrepareExact - io.recoveryPrepared := 0.U.asTypeOf(io.recoveryPrepared) - io.recoveryPrepared.valid := io.recoveryPrepareReady - io.recoveryPrepared.stid := recoveryStid - io.recoveryPrepared.provisionalKilled := recoveryProvisionalKilled - io.recoveryPrepared.publishedKilled := recoveryPublishedKilled - io.recoveryRejected.valid := io.recoveryPrepare.valid && - !recoveryPrepareExact - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.stidInRange := recoveryStidInRange - io.recoveryRejected.bits.publishedMembersExact := recoveryPublishedExact - - when(io.recoveryFire) { - assert(io.recoveryPrepareReady, - "dispatch recovery may apply only one exact prepared ROB suffix") - provisional(safeRecoveryStid) := - 0.U.asTypeOf(new OooDispatchReservationLease(p)) - for (uopClass <- 0 until p.iqClassCount; - bank <- 0 until p.iqBankCount; - entry <- 0 until p.iqEntriesPerBank) { - val provisionalTarget = slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Provisional && - slotStid(uopClass)(bank)(entry) === recoveryStid - when(provisionalTarget || recoveryPublishedKill(uopClass)(bank)(entry)) { - slotState(uopClass)(bank)(entry) := OooDispatchSlotState.Free - slotMemberValid(uopClass)(bank)(entry) := false.B - } + for (queue <- 0 until p.iex.systemMulticycleQueues) when(allowed && + routeSystem && olderSystem === queue.U) { + io.iex.systemDispatch(queue).valid := true.B; io.iex.systemDispatch(queue).bits := txn } - } - - for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount) { - assert(io.freeEntries(uopClass)(bank) + - io.provisionalEntries(uopClass)(bank) + - io.publishedEntries(uopClass)(bank) === p.iqEntriesPerBank.U, - "every dispatch IQ slot must have exactly one lifecycle owner") - for (entry <- 0 until p.iqEntriesPerBank) { - assert(slotMemberValid(uopClass)(bank)(entry) === - (slotState(uopClass)(bank)(entry) === - OooDispatchSlotState.Published), - "only a published dispatch slot may retain exact ROB membership") + for (queue <- 0 until p.iex.cmdIssueQueues) when(allowed && + routeCmd && olderCmd === queue.U) { + io.iex.cmdDispatch(queue).valid := true.B; io.iex.cmdDispatch(queue).bits := txn } + prefixComplete(offset + 1) := prefixComplete(offset) && laneComplete(offset) + structuralPrefix(offset + 1) := structuralPrefix(offset) && + laneStructurallyComplete(offset) } + + io.advance := PopCount((0 until width).map { offset => + laneActive(offset) && prefixComplete(offset) && laneComplete(offset) + }) } diff --git a/chisel/src/main/scala/linxcore/ooo/OooFastResultAtomicPublish.scala b/chisel/src/main/scala/linxcore/ooo/OooFastResultAtomicPublish.scala new file mode 100644 index 00000000..853912f0 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooFastResultAtomicPublish.scala @@ -0,0 +1,38 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.Decoupled +import linxcore.params.CoreParams +import linxcore.top.interface.{FastResultTxn, FastWritebackTxn, RobResolveTxn} + +class OooFastResultAtomicPublishIO(val p: CoreParams) extends Bundle { + val source = Flipped(Decoupled(new FastWritebackTxn(p))) + val iex = Decoupled(new FastResultTxn(p)) + val rob = Decoupled(new RobResolveTxn(p)) +} + +/** Stateless atomic fork for one retained fast result. + * + * The upstream OooD3FastResultQueue remains the only owner. Payload is always + * projected from that retained transaction; each branch is offered only when + * its peer can accept, so P-write/wakeup and ROB completion share one fire. + */ +class OooFastResultAtomicPublish(val p: CoreParams) extends Module { + val io = IO(new OooFastResultAtomicPublishIO(p)) + + io.iex.valid := io.source.valid && io.rob.ready + io.iex.bits.writeback := io.source.bits + io.rob.valid := io.source.valid && io.iex.ready + io.rob.bits := 0.U.asTypeOf(io.rob.bits) + io.rob.bits.rob := io.source.bits.rob + io.rob.bits.destinationValid := true.B + io.rob.bits.destinationIndex := io.source.bits.destinationIndex + io.rob.bits.value := io.source.bits.value + io.source.ready := io.iex.ready && io.rob.ready + + when(io.source.valid) { + assert(io.source.fire === io.iex.fire && + io.source.fire === io.rob.fire, + "fast result branches must publish on one common fire") + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryBridge.scala b/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryBridge.scala deleted file mode 100644 index 74f7bb07..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryBridge.scala +++ /dev/null @@ -1,282 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Valid} -import linxcore.common.InterfaceParams -import linxcore.frontend.{ - IfuInnerFlush, - IfuInnerFlushReason, - IfuPruneScope -} - -object OooFrontendRecoveryState extends ChiselEnum { - val Idle, RequestCtu, WaitCtu, RequestO3, WaitApply, WaitTerminal = Value -} - -object OooFrontendRecoveryRejectReason extends ChiselEnum { - val MalformedCommand, CtuRejected, O3Aborted = Value -} - -/** One recovery command joins the exact OOO suffix authority with CTU and the - * IFU restart proposal that describes the same architectural event. - */ -class OooFrontendRecoveryCommand( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Bundle { - val ooo = new OooGlobalRecoveryRequest(oooP) - val redirect = new IfuInnerFlush(ifuP) -} - -class OooFrontendRecoveryCompletion( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Bundle { - val command = new OooFrontendRecoveryCommand(ifuP, oooP) - val acceptedEpoch = UInt(ifuP.blockEpochWidth.W) -} - -class OooFrontendRecoveryReject( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Bundle { - val command = new OooFrontendRecoveryCommand(ifuP, oooP) - val reason = OooFrontendRecoveryRejectReason() -} - -object OooFrontendRecoveryContract { - /** IFU allocates `newEpoch`; every other field must echo the proposal. */ - def sameRedirectProposal(left: IfuInnerFlush, right: IfuInnerFlush): Bool = - left.valid === right.valid && - left.peId === right.peId && - left.threadId === right.threadId && - left.transactionId === right.transactionId && - left.fetchSeq === right.fetchSeq && - left.oldEpoch === right.oldEpoch && - left.restartPc === right.restartPc && - left.checkpointId === right.checkpointId && - left.reason === right.reason && - left.scope === right.scope && - left.terminalSteer === right.terminalSteer && - left.terminalTaken === right.terminalTaken && - left.boundaryPc === right.boundaryPc && - left.boundaryFallthroughPc === right.boundaryFallthroughPc && - left.historyKeyValid === right.historyKeyValid && - left.predictionTag === right.predictionTag && - left.fetchPacketUid === right.fetchPacketUid && - left.ghrAction === right.ghrAction && - left.ghrAppendValid === right.ghrAppendValid && - left.ghrAppendTaken === right.ghrAppendTaken && - left.rasAction === right.rasAction && - left.rasUpdate === right.rasUpdate && - left.rasPushAddress === right.rasPushAddress -} - -class OooFrontendRecoveryBridgeIO( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Bundle { - val in = Flipped(Decoupled(new OooFrontendRecoveryCommand(ifuP, oooP))) - - val o3Request = Decoupled(new OooGlobalRecoveryRequest(oooP)) - val o3Applied = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Completed = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Aborted = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - - val ctuPrepare = Decoupled(new OooGlobalRecoveryRequest(oooP)) - val ctuPrepared = Flipped(Valid(new OooCtuRecoveryPrepared(oooP))) - val ctuRejected = Flipped(Valid(new OooCtuRecoveryReject(oooP))) - val ctuApply = Output(Bool()) - val ctuAbort = Output(Bool()) - - val ifuRedirect = Decoupled(new IfuInnerFlush(ifuP)) - val canonicalFlush = Flipped(Valid(new IfuInnerFlush(ifuP))) - - /** Fence is non-mutating; stageCancel fires only after O3 common apply. */ - val fence = Output(Vec(oooP.stidCount, Bool())) - val stageCancel = Output(Vec(oooP.stidCount, Bool())) - val busy = Output(Bool()) - val complete = Valid(new OooFrontendRecoveryCompletion(ifuP, oooP)) - val rejected = Valid(new OooFrontendRecoveryReject(ifuP, oooP)) -} - -/** R4 join between the OOO physical recovery transaction and canonical IFU - * restart publication. - * - * Capture immediately fences the selected STID without mutating retained - * frontend or D2/S1 state. Only an exact O3 apply emits `stageCancel` and - * releases the retained IFU redirect. Completion waits for both exact O3 - * rebuild completion and the canonical IFU echo, in either order. - */ -class OooFrontendRecoveryBridge( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Module { - require(oooP.stidCount <= (1 << ifuP.threadIdWidth)) - require(oooP.peIdWidth == ifuP.peIdWidth) - require(oooP.stidWidth <= ifuP.threadIdWidth) - require(oooP.epochWidth == ifuP.blockEpochWidth) - - val io = IO(new OooFrontendRecoveryBridgeIO(ifuP, oooP)) - - val state = RegInit(OooFrontendRecoveryState.Idle) - val command = RegInit(0.U.asTypeOf(new OooFrontendRecoveryCommand(ifuP, oooP))) - val redirectSent = RegInit(false.B) - val o3CompletedSeen = RegInit(false.B) - val canonicalSeen = RegInit(false.B) - val canonicalEpoch = RegInit(0.U(ifuP.blockEpochWidth.W)) - - private def commandWellFormed(candidate: OooFrontendRecoveryCommand): Bool = { - val key = candidate.ooo.rename.key - val redirect = candidate.redirect - val stidInRange = key.member.group.stid < oooP.stidCount.U - val expectedScope = Mux( - candidate.ooo.rename.killTrigger, - IfuPruneScope.KillTriggerAndYounger, - IfuPruneScope.PreserveTriggerKillYounger) - val expectedReason = Mux( - key.cause === OooRecoveryCause.Branch, - IfuInnerFlushReason.BruRecovery, - IfuInnerFlushReason.OooRecovery) - - key.member.group.valid && key.member.bid.valid && - stidInRange && candidate.ooo.triggerMemberCount.orR && redirect.valid && - redirect.peId === key.member.group.peId && - redirect.threadId === key.member.group.stid && - redirect.oldEpoch === key.epoch && - redirect.scope === expectedScope && redirect.reason === expectedReason - } - - val idle = state === OooFrontendRecoveryState.Idle - val offeredCommandWellFormed = commandWellFormed(io.in.bits) - val acceptedMalformed = io.in.fire && !offeredCommandWellFormed - val acceptedCommand = io.in.fire && offeredCommandWellFormed - val activeStid = command.ooo.rename.key.member.group.stid - - io.in.ready := idle - io.ctuPrepare.valid := state === OooFrontendRecoveryState.RequestCtu - io.ctuPrepare.bits := command.ooo - io.o3Request.valid := state === OooFrontendRecoveryState.RequestO3 - io.o3Request.bits := command.ooo - - val exactCtuPrepared = state === OooFrontendRecoveryState.WaitCtu && - io.ctuPrepared.valid && - io.ctuPrepared.bits.request.asUInt === command.ooo.asUInt - val exactCtuRejected = - (state === OooFrontendRecoveryState.RequestCtu || - state === OooFrontendRecoveryState.WaitCtu) && - io.ctuRejected.valid && - io.ctuRejected.bits.request.asUInt === command.ooo.asUInt - - val exactO3Applied = state === OooFrontendRecoveryState.WaitApply && - io.o3Applied.valid && io.o3Applied.bits.asUInt === command.ooo.asUInt - val exactO3Completed = state === OooFrontendRecoveryState.WaitTerminal && - io.o3Completed.valid && io.o3Completed.bits.asUInt === command.ooo.asUInt - val exactO3Aborted = state === OooFrontendRecoveryState.WaitApply && - io.o3Aborted.valid && io.o3Aborted.bits.asUInt === command.ooo.asUInt - - io.ifuRedirect.valid := - state === OooFrontendRecoveryState.WaitTerminal && !redirectSent - io.ifuRedirect.bits := command.redirect - val ifuRedirectFire = io.ifuRedirect.fire - val exactCanonicalFlush = state === OooFrontendRecoveryState.WaitTerminal && - (redirectSent || ifuRedirectFire) && io.canonicalFlush.valid && - OooFrontendRecoveryContract.sameRedirectProposal( - io.canonicalFlush.bits, - command.redirect) - - val terminalO3Complete = o3CompletedSeen || exactO3Completed - val terminalCanonical = canonicalSeen || exactCanonicalFlush - val terminalComplete = state === OooFrontendRecoveryState.WaitTerminal && - terminalO3Complete && terminalCanonical - - io.fence.foreach(_ := false.B) - io.stageCancel.foreach(_ := false.B) - io.ctuApply := exactO3Applied - io.ctuAbort := exactO3Aborted - for (stid <- 0 until oooP.stidCount) { - io.fence(stid) := - (state =/= OooFrontendRecoveryState.Idle && activeStid === stid.U) || - (idle && io.in.valid && offeredCommandWellFormed && - io.in.bits.ooo.rename.key.member.group.stid === stid.U) - io.stageCancel(stid) := exactO3Applied && activeStid === stid.U - } - - io.busy := state =/= OooFrontendRecoveryState.Idle - io.complete.valid := terminalComplete - io.complete.bits.command := command - io.complete.bits.acceptedEpoch := Mux( - exactCanonicalFlush, - io.canonicalFlush.bits.newEpoch, - canonicalEpoch) - - io.rejected.valid := acceptedMalformed || exactCtuRejected || exactO3Aborted - io.rejected.bits.command := Mux(acceptedMalformed, io.in.bits, command) - io.rejected.bits.reason := Mux( - acceptedMalformed, - OooFrontendRecoveryRejectReason.MalformedCommand, - Mux( - exactCtuRejected, - OooFrontendRecoveryRejectReason.CtuRejected, - OooFrontendRecoveryRejectReason.O3Aborted)) - - when(acceptedCommand) { - command := io.in.bits - redirectSent := false.B - o3CompletedSeen := false.B - canonicalSeen := false.B - canonicalEpoch := 0.U - state := OooFrontendRecoveryState.RequestCtu - } - - when(io.ctuPrepare.fire) { - state := OooFrontendRecoveryState.WaitCtu - } - when(exactCtuPrepared) { - state := OooFrontendRecoveryState.RequestO3 - }.elsewhen(exactCtuRejected) { - state := OooFrontendRecoveryState.Idle - } - - when(io.o3Request.fire) { - state := OooFrontendRecoveryState.WaitApply - } - - when(exactO3Applied) { - state := OooFrontendRecoveryState.WaitTerminal - }.elsewhen(exactO3Aborted) { - state := OooFrontendRecoveryState.Idle - } - - when(ifuRedirectFire) { - redirectSent := true.B - } - when(exactO3Completed) { - o3CompletedSeen := true.B - } - when(exactCanonicalFlush) { - canonicalSeen := true.B - canonicalEpoch := io.canonicalFlush.bits.newEpoch - } - when(terminalComplete) { - state := OooFrontendRecoveryState.Idle - redirectSent := false.B - o3CompletedSeen := false.B - canonicalSeen := false.B - } - - when(io.o3Applied.valid && state === OooFrontendRecoveryState.WaitApply) { - assert(io.o3Applied.bits.asUInt === command.ooo.asUInt, - "active frontend recovery must observe only its exact O3 apply") - } - when(io.o3Completed.valid && state === OooFrontendRecoveryState.WaitApply) { - assert(false.B, "O3 recovery cannot complete before common apply") - } - when(io.o3Aborted.valid && state === OooFrontendRecoveryState.WaitTerminal) { - assert(false.B, "an applied O3 recovery cannot subsequently abort") - } - when(io.ctuPrepared.valid && state === OooFrontendRecoveryState.WaitCtu) { - assert(io.ctuPrepared.bits.request.asUInt === command.ooo.asUInt, - "CTU prepare acknowledgement must retain the exact recovery request") - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryContract.scala b/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryContract.scala new file mode 100644 index 00000000..ca545c86 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryContract.scala @@ -0,0 +1,34 @@ +package linxcore.ooo + +import chisel3._ +import linxcore.frontend.IfuInnerFlush + +/** Stateless equality helper retained after deletion of the displaced + * frontend recovery wrapper. + */ +object OooFrontendRecoveryContract { + def sameRedirectProposal(left: IfuInnerFlush, right: IfuInnerFlush): Bool = + left.valid === right.valid && + left.peId === right.peId && + left.threadId === right.threadId && + left.transactionId === right.transactionId && + left.fetchSeq === right.fetchSeq && + left.oldEpoch === right.oldEpoch && + left.restartPc === right.restartPc && + left.checkpointId === right.checkpointId && + left.reason === right.reason && + left.scope === right.scope && + left.terminalSteer === right.terminalSteer && + left.terminalTaken === right.terminalTaken && + left.boundaryPc === right.boundaryPc && + left.boundaryFallthroughPc === right.boundaryFallthroughPc && + left.historyKeyValid === right.historyKeyValid && + left.predictionTag === right.predictionTag && + left.fetchPacketUid === right.fetchPacketUid && + left.ghrAction === right.ghrAction && + left.ghrAppendValid === right.ghrAppendValid && + left.ghrAppendTaken === right.ghrAppendTaken && + left.rasAction === right.rasAction && + left.rasUpdate === right.rasUpdate && + left.rasPushAddress === right.rasPushAddress +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala b/chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala index 96779359..d37e2a6d 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala @@ -18,8 +18,8 @@ class OooHierarchicalFreeSlotSelectIO(val entries: Int) extends Bundle { class OooHierarchicalFreeSlotSelect( val entries: Int, val groupEntries: Int) extends Module { - require(entries > 0 && (entries & (entries - 1)) == 0, - "hierarchical selector entries must be a positive power of two") + require(entries > 0, + "hierarchical selector entries must be positive") require(groupEntries > 0 && (groupEntries & (groupEntries - 1)) == 0 && groupEntries <= entries && entries % groupEntries == 0, "hierarchical selector group size must be a power-of-two divisor of entries") diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexAguPipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexAguPipeline.scala index 165ee884..18ca06cd 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexAguPipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexAguPipeline.scala @@ -3,6 +3,9 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Cat, Decoupled, Fill, is, MuxLookup, PopCount, switch, Valid} +import linxcore.common.DestinationKind +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} /** Retained scalar-load address request before LSU acceptance. */ class OooIexAguLoadRequest(val p: OooParams = OooParams()) extends Bundle { @@ -29,11 +32,14 @@ class OooIexAguReject(val p: OooParams = OooParams()) extends Bundle { val incomingKilled = Bool() } -class OooIexAguPipelineIO(val p: OooParams = OooParams()) extends Bundle { +class OooIexAguPipelineIO( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Bundle { val e1 = Flipped(Decoupled(new OooIexExecuteTransaction(p))) val request = Decoupled(new OooIexAguLoadRequest(p)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(coreParams))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -60,10 +66,16 @@ object OooIexAguPipeline { * accepts it. This module does not allocate a load generation, access memory, * publish speculative wakeup, write RF, or complete ROB. */ -class OooIexAguPipeline(val p: OooParams = OooParams()) extends Module { +class OooIexAguPipeline( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Module { + def this(p: OooParams) = + this(p, OooRecoveryMembership.coreParams(p)) import OooIexAguPipeline._ + OooRecoveryMembership.requireCompatible(p, coreParams) - val io = IO(new OooIexAguPipelineIO(p)) + val io = IO(new OooIexAguPipelineIO(p, coreParams)) private def opcode(value: Int): UInt = value.U(p.opcodeWidth.W) @@ -71,8 +83,10 @@ class OooIexAguPipeline(val p: OooParams = OooParams()) extends Module { SupportedOpcodes.map(value => op === opcode(value)).reduce(_ || _) private def killedByRecovery(execute: OooIexExecuteTransaction): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, + io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + OooRecoveryMembership.memberKilled(p, coreParams, + io.recoveryApply.bits, execute.i2.row.member) private def canceledByLoad(execute: OooIexExecuteTransaction): Bool = @@ -147,6 +161,17 @@ class OooIexAguPipeline(val p: OooParams = OooParams()) extends Module { accessBytesExact && addressModeExact && memory.dataSourceMask === 0.U val logicalSourceMask = VecInit(row.sources.map(_.valid)).asUInt val destinationMask = VecInit(row.destinations.map(_.valid)).asUInt + val destination = row.destinations(0) + val gprDestinationExact = destination.kind === DestinationKind.Gpr && + destination.ptag < p.pPhysRegs.U && + row.recipe.pDestinationCount === 1.U && + row.recipe.tAllocationCount === 0.U && + row.recipe.uAllocationCount === 0.U + val tDestinationExact = destination.kind === DestinationKind.T && + destination.localTag < p.tPhysRegs.U && destination.localSequence.valid && + row.recipe.pDestinationCount === 0.U && + row.recipe.tAllocationCount === 1.U && + row.recipe.uAllocationCount === 0.U val pcRequired = memory.addressMode === OooMemoryAddressMode.PcOffset val immediateRequired = memory.addressMode === OooMemoryAddressMode.BaseOffset || pcRequired @@ -157,7 +182,7 @@ class OooIexAguPipeline(val p: OooParams = OooParams()) extends Module { incoming.i2.sourceMask === memory.addressSourceMask && PopCount(incoming.i2.sourceMask) === row.recipe.pSourceCount && PopCount(destinationMask) === 1.U && - row.recipe.pDestinationCount === 1.U && + (gprDestinationExact || tDestinationExact) && row.recipe.pcReadRequired === pcRequired && (!pcRequired || incoming.i2.pcValid) && (!immediateRequired || row.immediateValid) diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexAluPipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexAluPipeline.scala index df244d91..c0f90f64 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexAluPipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexAluPipeline.scala @@ -3,6 +3,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Cat, Decoupled, Fill, PopCount, Valid} import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} class OooIexAluWriteback(val p: OooParams = OooParams()) extends Bundle { val valid = Bool() @@ -28,12 +30,15 @@ class OooIexAluReject(val p: OooParams = OooParams()) extends Bundle { val incomingKilled = Bool() } -class OooIexAluPipelineIO(val p: OooParams = OooParams()) extends Bundle { +class OooIexAluPipelineIO( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Bundle { val e1 = Flipped(Decoupled(new OooIexExecuteTransaction(p))) val w1Bypass = Valid(new OooIexAluTerminalTransaction(p)) val w2 = Decoupled(new OooIexAluTerminalTransaction(p)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(coreParams))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -68,11 +73,40 @@ object OooIexAluPipeline { val MoveImmediateOpcodes: Seq[Int] = Seq( FrontendOpcodeDecodeTable.OP_C_MOVI) + val LoadImmediateOpcodes: Seq[Int] = Seq( + FrontendOpcodeDecodeTable.OP_LUI, + FrontendOpcodeDecodeTable.OP_HL_LUI, + FrontendOpcodeDecodeTable.OP_HL_LIS, + FrontendOpcodeDecodeTable.OP_HL_LIU) + val MoveRegisterOpcodes: Seq[Int] = Seq( FrontendOpcodeDecodeTable.OP_C_MOVR) + val CompactSignExtendOpcodes: Seq[Int] = Seq( + FrontendOpcodeDecodeTable.OP_C_SEXT_B, + FrontendOpcodeDecodeTable.OP_C_SEXT_H, + FrontendOpcodeDecodeTable.OP_C_SEXT_W) + + val RegisterShiftOpcodes: Seq[Int] = Seq( + FrontendOpcodeDecodeTable.OP_SLL, + FrontendOpcodeDecodeTable.OP_SLLW, + FrontendOpcodeDecodeTable.OP_SRA, + FrontendOpcodeDecodeTable.OP_SRAW, + FrontendOpcodeDecodeTable.OP_SRL, + FrontendOpcodeDecodeTable.OP_SRLW) + + val ImmediateShiftOpcodes: Seq[Int] = Seq( + FrontendOpcodeDecodeTable.OP_SLLI, + FrontendOpcodeDecodeTable.OP_SLLIW, + FrontendOpcodeDecodeTable.OP_SRAI, + FrontendOpcodeDecodeTable.OP_SRAIW, + FrontendOpcodeDecodeTable.OP_SRLI, + FrontendOpcodeDecodeTable.OP_SRLIW) + val SupportedOpcodes: Seq[Int] = ImmediateOpcodes ++ - CompactRegisterOpcodes ++ MoveImmediateOpcodes ++ MoveRegisterOpcodes + CompactRegisterOpcodes ++ MoveImmediateOpcodes ++ LoadImmediateOpcodes ++ + MoveRegisterOpcodes ++ CompactSignExtendOpcodes ++ RegisterShiftOpcodes ++ + ImmediateShiftOpcodes } /** One-cycle integer ALU with retained W1 bypass and retained W2 terminal row. @@ -82,10 +116,16 @@ object OooIexAluPipeline { * write, wakeup, ROB completion, redirect, or trace side effect occurs here; * a later atomic terminal sink must accept W2 before publishing those effects. */ -class OooIexAluPipeline(val p: OooParams = OooParams()) extends Module { +class OooIexAluPipeline( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Module { + def this(p: OooParams) = + this(p, OooRecoveryMembership.coreParams(p)) import OooIexAluPipeline._ + OooRecoveryMembership.requireCompatible(p, coreParams) - val io = IO(new OooIexAluPipelineIO(p)) + val io = IO(new OooIexAluPipelineIO(p, coreParams)) private def opcode(value: Int): UInt = value.U(p.opcodeWidth.W) @@ -93,8 +133,10 @@ class OooIexAluPipeline(val p: OooParams = OooParams()) extends Module { values.map(value => op === opcode(value)).reduce(_ || _) private def killedByRecovery(execute: OooIexExecuteTransaction): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, + io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + OooRecoveryMembership.memberKilled(p, coreParams, + io.recoveryApply.bits, execute.i2.row.member) private def canceledByLoad(execute: OooIexExecuteTransaction): Bool = @@ -157,8 +199,49 @@ class OooIexAluPipeline(val p: OooParams = OooParams()) extends Module { result := src0 - src1 }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVI)) { result := imm + }.elsewhen(isOneOf(op, LoadImmediateOpcodes)) { + result := imm }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_MOVR)) { result := src0 + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_B)) { + result := Cat(Fill(p.pcWidth - 8, src0(7)), src0(7, 0)) + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_H)) { + result := Cat(Fill(p.pcWidth - 16, src0(15)), src0(15, 0)) + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_C_SEXT_W)) { + result := Cat(Fill(p.pcWidth - 32, src0(31)), src0(31, 0)) + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLL) || + op === opcode(FrontendOpcodeDecodeTable.OP_SLLI)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SLL), src1(5, 0), imm(5, 0)) + result := src0 << shiftAmount + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRL) || + op === opcode(FrontendOpcodeDecodeTable.OP_SRLI)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SRL), src1(5, 0), imm(5, 0)) + result := src0 >> shiftAmount + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRA) || + op === opcode(FrontendOpcodeDecodeTable.OP_SRAI)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SRA), src1(5, 0), imm(5, 0)) + result := (src0.asSInt >> shiftAmount).asUInt + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SLLW) || + op === opcode(FrontendOpcodeDecodeTable.OP_SLLIW)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SLLW), src1(4, 0), imm(4, 0)) + val shifted = (src0(31, 0) << shiftAmount)(31, 0) + result := Cat(Fill(p.pcWidth - 32, shifted(31)), shifted) + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRLW) || + op === opcode(FrontendOpcodeDecodeTable.OP_SRLIW)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SRLW), src1(4, 0), imm(4, 0)) + val shifted = src0(31, 0) >> shiftAmount + result := Cat(Fill(p.pcWidth - 32, shifted(31)), shifted) + }.elsewhen(op === opcode(FrontendOpcodeDecodeTable.OP_SRAW) || + op === opcode(FrontendOpcodeDecodeTable.OP_SRAIW)) { + val shiftAmount = Mux( + op === opcode(FrontendOpcodeDecodeTable.OP_SRAW), src1(4, 0), imm(4, 0)) + val shifted = (src0(31, 0).asSInt >> shiftAmount).asUInt + result := Cat(Fill(p.pcWidth - 32, shifted(31)), shifted) } terminal.writebacks(0).valid := true.B @@ -180,13 +263,17 @@ class OooIexAluPipeline(val p: OooParams = OooParams()) extends Module { val expectedSourceCount = WireDefault(0.U(p.sourceCountWidth.W)) when(isOneOf(incomingOpcode, ImmediateOpcodes) || - isOneOf(incomingOpcode, MoveRegisterOpcodes)) { + isOneOf(incomingOpcode, ImmediateShiftOpcodes) || + isOneOf(incomingOpcode, + MoveRegisterOpcodes ++ CompactSignExtendOpcodes)) { expectedSourceCount := 1.U - }.elsewhen(isOneOf(incomingOpcode, CompactRegisterOpcodes)) { + }.elsewhen(isOneOf(incomingOpcode, + CompactRegisterOpcodes ++ RegisterShiftOpcodes)) { expectedSourceCount := 2.U } val needsImmediate = isOneOf(incomingOpcode, - ImmediateOpcodes ++ MoveImmediateOpcodes) + ImmediateOpcodes ++ ImmediateShiftOpcodes ++ MoveImmediateOpcodes ++ + LoadImmediateOpcodes) val logicalSourceMask = VecInit( incoming.i2.row.sources.map(_.valid)).asUInt val destinationMask = VecInit( diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexAtomicReadArbiter.scala b/chisel/src/main/scala/linxcore/ooo/OooIexAtomicReadArbiter.scala index f3cdf74d..bab98646 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexAtomicReadArbiter.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexAtomicReadArbiter.scala @@ -3,6 +3,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Cat, Mux1H, PopCount, Valid, log2Ceil} import linxcore.common.OperandClass +import linxcore.params.CoreParams +import linxcore.top.interface.PcBufferReadAddress class OooIexOperandReadPortRequest(val p: OooParams = OooParams()) extends Bundle { @@ -14,15 +16,7 @@ class OooIexOperandReadPortRequest(val p: OooParams = OooParams()) val source = new OooIexSourceState(p) } -class OooIexPcReadPortRequest(val p: OooParams = OooParams()) - extends Bundle { - val domain = UInt(p.iexIssueDomainWidth.W) - val stid = UInt(p.stidWidth.W) - val epoch = UInt(p.epochWidth.W) - val token = new PcBufferToken(p) -} - -class OooIexAtomicReadArbiterIO(val p: OooParams = OooParams()) +class OooIexAtomicReadArbiterIO(val core: CoreParams, val p: OooParams) extends Bundle { val attempts = Input(Vec(p.iexIssueDomainCount, Valid(new OooIexI1ReadAttempt(p)))) @@ -49,7 +43,7 @@ class OooIexAtomicReadArbiterIO(val p: OooParams = OooParams()) val uReadResponses = Input(Vec(p.iexUReadPorts, Valid(UInt(p.pcWidth.W)))) val pcReadRequests = Output(Vec(p.pcReadPorts, - Valid(new OooIexPcReadPortRequest(p)))) + Valid(new PcBufferReadAddress(core)))) val pcReadResponses = Input(Vec(p.pcReadPorts, Valid(UInt(p.pcWidth.W)))) @@ -77,8 +71,14 @@ class OooIexAtomicReadArbiterIO(val p: OooParams = OooParams()) * response retains the grant but exposes an incomplete valid mask, allowing * the existing I1 lane to reject and repick the exact resident row. */ -class OooIexAtomicReadArbiter(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooIexAtomicReadArbiterIO(p)) +class OooIexAtomicReadArbiter( + val core: CoreParams, + val p: OooParams) + extends Module { + def this(core: CoreParams) = + this(core, OooIexPhysicalProfile.fromCoreParams(core).params) + OooRecoveryMembership.requireCompatible(p, core) + val io = IO(new OooIexAtomicReadArbiterIO(core, p)) private val domainCount = p.iexIssueDomainCount private val ageWidth = @@ -231,7 +231,7 @@ class OooIexAtomicReadArbiter(val p: OooParams = OooParams()) extends Module { io.uReadRequests := VecInit(Seq.fill(p.iexUReadPorts)( 0.U.asTypeOf(Valid(new OooIexOperandReadPortRequest(p))))) io.pcReadRequests := VecInit(Seq.fill(p.pcReadPorts)( - 0.U.asTypeOf(Valid(new OooIexPcReadPortRequest(p))))) + 0.U.asTypeOf(Valid(new PcBufferReadAddress(core))))) val flatSources = for { domain <- 0 until domainCount @@ -284,7 +284,7 @@ class OooIexAtomicReadArbiter(val p: OooParams = OooParams()) extends Module { io.tReadRequests(port).bits.domain := domain.U io.tReadRequests(port).bits.sourceIndex := sourceIndex.U io.tReadRequests(port).bits.stid := attempt.stid - io.tReadRequests(port).bits.epoch := attempt.epoch + io.tReadRequests(port).bits.epoch := source.localEpoch io.tReadRequests(port).bits.source := source sourceDataValidBySource(domain)(sourceIndex) := io.tReadResponses(port).valid @@ -297,7 +297,7 @@ class OooIexAtomicReadArbiter(val p: OooParams = OooParams()) extends Module { io.uReadRequests(port).bits.domain := domain.U io.uReadRequests(port).bits.sourceIndex := sourceIndex.U io.uReadRequests(port).bits.stid := attempt.stid - io.uReadRequests(port).bits.epoch := attempt.epoch + io.uReadRequests(port).bits.epoch := source.localEpoch io.uReadRequests(port).bits.source := source sourceDataValidBySource(domain)(sourceIndex) := io.uReadResponses(port).valid @@ -314,11 +314,12 @@ class OooIexAtomicReadArbiter(val p: OooParams = OooParams()) extends Module { for (port <- 0 until p.pcReadPorts) { when(pcActive && pcPort === port.U) { io.pcReadRequests(port).valid := true.B - io.pcReadRequests(port).bits.domain := domain.U + io.pcReadRequests(port).bits.valid := true.B io.pcReadRequests(port).bits.stid := io.attempts(domain).bits.stid - io.pcReadRequests(port).bits.epoch := io.attempts(domain).bits.epoch - io.pcReadRequests(port).bits.token := - io.attempts(domain).bits.pcToken + io.pcReadRequests(port).bits.pcBufferIndex := + io.attempts(domain).bits.pcToken.index + io.pcReadRequests(port).bits.allocationEpoch := + io.attempts(domain).bits.pcToken.allocationEpoch io.pcDataValid(domain) := io.pcReadResponses(port).valid io.pcData(domain) := io.pcReadResponses(port).bits } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexBruPipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexBruPipeline.scala index fc7f6eea..746d8ca9 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexBruPipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexBruPipeline.scala @@ -3,6 +3,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, PopCount, Valid} import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} object OooIexBctrlUpdateKind extends ChiselEnum { val Condition, Target = Value @@ -40,11 +42,14 @@ class OooIexBruReject(val p: OooParams = OooParams()) extends Bundle { val incomingKilled = Bool() } -class OooIexBruPipelineIO(val p: OooParams = OooParams()) extends Bundle { +class OooIexBruPipelineIO( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Bundle { val e1 = Flipped(Decoupled(new OooIexExecuteTransaction(p))) val e2 = Decoupled(new OooIexBruTerminalTransaction(p)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(coreParams))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -76,22 +81,31 @@ object OooIexBruPipeline { FrontendOpcodeDecodeTable.OP_SETC_TGT, FrontendOpcodeDecodeTable.OP_C_SETC_TGT) + val RedirectOpcodes: Seq[Int] = Seq( + FrontendOpcodeDecodeTable.OP_J) + val SupportedOpcodes: Seq[Int] = PcValueOpcodes ++ - CompareImmediateOpcodes ++ CompactConditionOpcodes ++ TargetOpcodes + CompareImmediateOpcodes ++ CompactConditionOpcodes ++ TargetOpcodes ++ + RedirectOpcodes } /** One-cycle BRU value/condition execution with a retained E2 transaction. * - * The module owns no BCTRL state and emits no redirect directly. E2 must be - * accepted by a later atomic sink that applies the BCTRL/RF/ROB effects - * together. Conditional/unconditional redirect opcodes stay fail-closed - * until their missing architectural condition and prediction inputs have - * explicit typed owners. + * The module owns no BCTRL state. E2 must be accepted by a later atomic sink + * that applies BCTRL/RF/ROB effects together. Direct J emits its exact + * PC-relative target; conditional redirects remain fail-closed until their + * architectural condition and prediction inputs have typed owners. */ -class OooIexBruPipeline(val p: OooParams = OooParams()) extends Module { +class OooIexBruPipeline( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Module { + def this(p: OooParams) = + this(p, OooRecoveryMembership.coreParams(p)) import OooIexBruPipeline._ + OooRecoveryMembership.requireCompatible(p, coreParams) - val io = IO(new OooIexBruPipelineIO(p)) + val io = IO(new OooIexBruPipelineIO(p, coreParams)) private def opcode(value: Int): UInt = value.U(p.opcodeWidth.W) @@ -99,8 +113,10 @@ class OooIexBruPipeline(val p: OooParams = OooParams()) extends Module { values.map(value => op === opcode(value)).reduce(_ || _) private def killedByRecovery(execute: OooIexExecuteTransaction): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, + io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + OooRecoveryMembership.memberKilled(p, coreParams, + io.recoveryApply.bits, execute.i2.row.member) private def canceledByLoad(execute: OooIexExecuteTransaction): Bool = @@ -155,16 +171,17 @@ class OooIexBruPipeline(val p: OooParams = OooParams()) extends Module { val compactCondition = isOneOf(op, CompactConditionOpcodes) val targetUpdate = isOneOf(op, TargetOpcodes) - terminal.bctrl.valid := compactCondition || targetUpdate - terminal.bctrl.kind := Mux(targetUpdate, + val redirect = isOneOf(op, RedirectOpcodes) + terminal.bctrl.valid := compactCondition || targetUpdate || redirect + terminal.bctrl.kind := Mux(targetUpdate || redirect, OooIexBctrlUpdateKind.Target, OooIexBctrlUpdateKind.Condition) terminal.bctrl.condition := Mux( op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_EQ), src0 === src1, Mux(op === opcode(FrontendOpcodeDecodeTable.OP_C_SETC_NE), src0 =/= src1, src0 =/= 0.U)) - terminal.bctrl.targetValid := targetUpdate && src0 =/= 0.U - terminal.bctrl.target := src0 + terminal.bctrl.targetValid := redirect || (targetUpdate && src0 =/= 0.U) + terminal.bctrl.target := Mux(redirect, i2.pc + imm, src0) terminal } @@ -194,8 +211,8 @@ class OooIexBruPipeline(val p: OooParams = OooParams()) extends Module { val destinationMask = VecInit( incoming.i2.row.destinations.map(_.valid)).asUInt val needsImmediate = isOneOf(incomingOpcode, - PcValueOpcodes ++ CompareImmediateOpcodes) - val needsPc = isOneOf(incomingOpcode, PcValueOpcodes) + PcValueOpcodes ++ CompareImmediateOpcodes ++ RedirectOpcodes) + val needsPc = isOneOf(incomingOpcode, PcValueOpcodes ++ RedirectOpcodes) val operandShapeExact = incoming.i2.row.valid && incoming.i2.row.member.group.valid && incoming.i2.row.member.bid.valid && incoming.i2.row.reservation.valid && diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexCanonicalLoadOwnership.scala b/chisel/src/main/scala/linxcore/ooo/OooIexCanonicalLoadOwnership.scala new file mode 100644 index 00000000..5a14fb4a --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooIexCanonicalLoadOwnership.scala @@ -0,0 +1,281 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Decoupled, Valid, log2Ceil} + +import linxcore.common.{CoreParams, ScalarLsuParams} +import linxcore.iex._ +import linxcore.lsu.{LoadAttemptRebind, LoadCanonicalRowIdentity, + LoadInflightAlloc, ScalarLSULoadReturnEntry} +import linxcore.params.{CoreParams => MainlineCoreParams} +import linxcore.rob.ROBID +import linxcore.top.interface.{RecoveryPlanContract, RecoveryTargetIO} + +object OooIexCanonicalLoadOwnership { + def defaultCoreParams(p: OooParams): CoreParams = { + require(p.nativeBidWidth <= 16, + "default canonical LSU projection supports native BID up to 16 bits") + val bidProjectionEntries = 1 << (p.nativeBidWidth - 1) + val robEntries = math.max(p.robIdentityGroupsPerStid, bidProjectionEntries) + val defaultLiqEntries = ScalarLsuParams().liqEntries + val scalarLsu = ScalarLsuParams( + stidCount = p.stidCount, + liqEntries = math.min(defaultLiqEntries, robEntries), + loadReturnPipeCount = 2, + peIdWidth = math.max(8, p.peIdWidth), + stidWidth = math.max(8, p.stidWidth), + tidWidth = math.max(8, p.stidWidth), + archRegWidth = math.max(6, p.archRegWidth), + physRegWidth = math.max(7, p.pTagWidth)) + CoreParams( + robEntries = robEntries, + lsidWidth = p.lsidWidth, + scalarLsu = scalarLsu) + } +} + +/** Canonical LSU-facing port of the OOO execution composition. */ +class OooIexCanonicalLoadPortIO( + val p: OooParams, + val coreParams: CoreParams) extends Bundle { + private val lsu = coreParams.scalarLsu + + private def allocType = new LoadInflightAlloc( + lsu.liqEntries, coreParams.robEntries, lsu.addrWidth, lsu.pcWidth, + lsu.loadSizeWidth, lsu.archRegWidth, lsu.physRegWidth, lsu.peIdWidth, + lsu.stidWidth, lsu.tidWidth, lsu.loadReturnPipeCount, + coreParams.lsidWidth) + private def completionType = new ScalarLSULoadReturnEntry( + coreParams.robEntries, lsu.addrWidth, lsu.pcWidth, lsu.dataWidth, + lsu.loadSizeWidth, lsu.loadReturnPipeCount, lsu.archRegWidth, + lsu.physRegWidth, lsu.peIdWidth, lsu.stidWidth, lsu.tidWidth, + coreParams.lsidWidth) + + val liqAlloc = Decoupled(allocType) + val liqAllocLoadId = Input(new ROBID(lsu.liqEntries)) + val rebind = Flipped(Decoupled( + new OooIexLoadTerminalMetadataRebind(p, coreParams))) + val liqRebind = Decoupled(new LoadAttemptRebind(lsu.liqEntries)) + val attemptLaunch = Flipped(Valid(new OooIexLoadAttemptLaunch)) + val attemptLaunchAccepted = Output(Bool()) + val completion = Flipped(Decoupled(completionType)) +} + +class OooIexCanonicalLoadOwnershipIO( + val p: OooParams, + val coreParams: CoreParams, + val laneCount: Int, + val recoveryParams: MainlineCoreParams) extends Bundle { + private val lsu = coreParams.scalarLsu + + private def allocType = new LoadInflightAlloc( + lsu.liqEntries, + coreParams.robEntries, + lsu.addrWidth, + lsu.pcWidth, + lsu.loadSizeWidth, + lsu.archRegWidth, + lsu.physRegWidth, + lsu.peIdWidth, + lsu.stidWidth, + lsu.tidWidth, + lsu.loadReturnPipeCount, + coreParams.lsidWidth) + + private def completionType = new ScalarLSULoadReturnEntry( + coreParams.robEntries, + lsu.addrWidth, + lsu.pcWidth, + lsu.dataWidth, + lsu.loadSizeWidth, + lsu.loadReturnPipeCount, + lsu.archRegWidth, + lsu.physRegWidth, + lsu.peIdWidth, + lsu.stidWidth, + lsu.tidWidth, + coreParams.lsidWidth) + + val agu = Flipped(Vec(laneCount, + Decoupled(new OooIexAguLoadRequest(p)))) + + // The canonical ScalarLSULoadPath remains the sole lifecycle owner. Its + // current allocation lease is returned combinationally beside allocReady. + val liqAlloc = Decoupled(allocType) + val liqAllocLoadId = Input(new ROBID(lsu.liqEntries)) + + // Replay policy requests one exact generation transition. Both the + // canonical LIQ and the OOO metadata sidecar must accept the same fire. + val rebind = Flipped(Decoupled( + new OooIexLoadTerminalMetadataRebind(p, coreParams))) + val liqRebind = Decoupled(new LoadAttemptRebind(lsu.liqEntries)) + val attemptLaunch = Flipped(Valid( + new OooIexLoadAttemptLaunch)) + + val completion = Flipped(Decoupled(completionType)) + val result = Decoupled(new OooIexLoadResult(p)) + val resultLane = Output(UInt(math.max(1, log2Ceil(laneCount)).W)) + val speculativeWakeup = Output(Vec(laneCount, + Valid(new OooIexWakeup(p)))) + val loadCancel = Output(Vec(laneCount, + Valid(new OooIexLoadCancel(p)))) + val loadBypass = Output(Vec(laneCount, + Valid(new OooIexBypassCandidate(p)))) + + val recovery = Flipped(new RecoveryTargetIO(recoveryParams)) + + val allocAccepted = Output(Bool()) + val rebindAccepted = Output(Bool()) + val aguRejected = Output(Vec(laneCount, + Valid(new LoadIexIssueReject(p)))) + val metadataAllocRejected = Output(Valid( + new OooIexLoadTerminalMetadataReject(p, coreParams))) + val metadataRebindRejected = Output(Valid( + new OooIexLoadTerminalMetadataReject(p, coreParams))) + val attemptLaunchAccepted = Output(Bool()) + val attemptLaunchRejected = Output(Valid( + new OooIexLoadTerminalMetadataReject(p, coreParams))) + val completionRejected = Output(Valid( + new OooIexLoadTerminalMetadataReject(p, coreParams))) + val metadataOccupied = Output(UInt(log2Ceil(lsu.liqEntries + 1).W)) + val metadataEmpty = Output(Bool()) +} + +/** Non-resident ownership join between parameterized OOO AGUs and canonical LIQ. + * + * Address, launch, miss, refill, replay, and result residency belong only to + * `ScalarLSULoadPath`. This module atomically joins each canonical LIQ row + * lease to the minimal OOO terminal metadata needed after the LIQ row has + * transferred into LRET/W1/W2. It cannot accept one half of allocation or + * rebind, and terminal backpressure releases neither half early. + */ +class OooIexCanonicalLoadOwnership( + val p: OooParams = OooParams(), + val coreParams: CoreParams = CoreParams( + scalarLsu = linxcore.common.ScalarLsuParams( + stidCount = 4, loadReturnPipeCount = 2)), + val laneCount: Int = 2, + val recoveryParams: MainlineCoreParams) extends Module { + def this(p: OooParams, coreParams: CoreParams) = + this(p, coreParams, coreParams.scalarLsu.loadReturnPipeCount, + OooRecoveryMembership.coreParams(p)) + + def this(p: OooParams, coreParams: CoreParams, laneCount: Int) = + this(p, coreParams, laneCount, OooRecoveryMembership.coreParams(p)) + private val lsu = coreParams.scalarLsu + + require(laneCount > 0, + "the Linx scalar profile needs at least one AGU load lane") + require(lsu.loadReturnPipeCount >= laneCount, + "canonical LSU return-pipe identities must cover every AGU load lane") + LoadCanonicalRowIdentity.requireBridgeFits(lsu.liqEntries) + + val io = IO(new OooIexCanonicalLoadOwnershipIO( + p, coreParams, laneCount, recoveryParams)) + + val issuePipeline = Module(new LoadIexIssuePipeline( + p, coreParams, laneCount, recoveryParams)) + val metadata = Module(new OooIexLoadTerminalMetadata( + p, coreParams, laneCount = laneCount, recoveryParams = recoveryParams)) + + issuePipeline.io.agu <> io.agu + + val issuePrepareReady = issuePipeline.io.recovery.prepare.ready + metadata.io.recoveryPrepare.bits := io.recovery.prepare.bits + val metadataPrepareReady = metadata.io.recoveryPrepareReady + val commonPrepareReady = issuePrepareReady && metadataPrepareReady + val commonPrepareFire = io.recovery.prepare.valid && commonPrepareReady + io.recovery.prepare.ready := commonPrepareReady + issuePipeline.io.recovery.prepare.valid := commonPrepareFire + issuePipeline.io.recovery.prepare.bits := io.recovery.prepare.bits + metadata.io.recoveryPrepare.valid := commonPrepareFire + + val bothPrepared = issuePipeline.io.recovery.prepared.valid && + metadata.io.recoveryPrepared.valid + io.recovery.prepared.valid := bothPrepared + io.recovery.prepared.bits := issuePipeline.io.recovery.prepared.bits + issuePipeline.io.recovery.prepared.ready := io.recovery.prepared.ready && + metadata.io.recoveryPrepared.valid + + issuePipeline.io.recovery.apply := io.recovery.apply + issuePipeline.io.recovery.abort := io.recovery.abort + metadata.io.recoveryApply := io.recovery.apply + metadata.io.recoveryAbort := io.recovery.abort + + io.liqAlloc.bits := issuePipeline.io.alloc.bits + io.liqAlloc.valid := issuePipeline.io.alloc.valid && metadata.io.alloc.ready + issuePipeline.io.alloc.ready := io.liqAlloc.ready && metadata.io.alloc.ready + + metadata.io.alloc.valid := issuePipeline.io.alloc.valid && io.liqAlloc.ready + metadata.io.alloc.bits := 0.U.asTypeOf(metadata.io.alloc.bits) + metadata.io.alloc.bits.loadId := + LoadCanonicalRowIdentity.fromRobId(io.liqAllocLoadId) + metadata.io.alloc.bits.attempt := issuePipeline.io.alloc.bits.attempt + metadata.io.alloc.bits.load := issuePipeline.io.accepted.bits.load + metadata.io.alloc.bits.request := issuePipeline.io.accepted.bits.request + metadata.io.alloc.bits.lane := issuePipeline.io.accepted.bits.lane + + io.allocAccepted := io.liqAlloc.fire && metadata.io.alloc.fire && + issuePipeline.io.accepted.valid + + private def toRobId(target: ROBID, source: LoadCanonicalRowIdentity): Unit = { + target.valid := source.valid + target.value := source.slot(log2Ceil(target.entries) - 1, 0) + target.wrap := source.generation(0) + } + + io.liqRebind.bits := 0.U.asTypeOf(io.liqRebind.bits) + toRobId(io.liqRebind.bits.loadId, io.rebind.bits.loadId) + io.liqRebind.bits.current := io.rebind.bits.currentAttempt + io.liqRebind.bits.next := io.rebind.bits.nextAttempt + io.liqRebind.valid := io.rebind.valid && metadata.io.rebind.ready + + metadata.io.rebind.bits := io.rebind.bits + metadata.io.rebind.valid := io.rebind.valid && io.liqRebind.ready + io.rebind.ready := io.liqRebind.ready && metadata.io.rebind.ready + io.rebindAccepted := io.rebind.fire && io.liqRebind.fire && + metadata.io.rebind.fire + + metadata.io.attemptLaunch := io.attemptLaunch + io.attemptLaunchAccepted := metadata.io.attemptLaunchAccepted + io.attemptLaunchRejected := metadata.io.attemptLaunchRejected + io.speculativeWakeup := metadata.io.speculativeWakeup + io.loadCancel := metadata.io.loadCancel + io.loadBypass := metadata.io.loadBypass + + metadata.io.completion <> io.completion + io.result <> metadata.io.result + io.resultLane := metadata.io.resultLane + + io.aguRejected := issuePipeline.io.rejected + io.metadataAllocRejected := metadata.io.allocRejected + io.metadataRebindRejected := metadata.io.rebindRejected + io.completionRejected := metadata.io.completionRejected + io.metadataOccupied := metadata.io.occupied + io.metadataEmpty := metadata.io.empty + + when(io.liqAlloc.fire || metadata.io.alloc.fire || + issuePipeline.io.accepted.valid) { + assert(io.liqAlloc.fire && metadata.io.alloc.fire && + issuePipeline.io.accepted.valid, + "canonical LIQ and OOO terminal metadata allocation must be atomic") + } + when(io.rebind.fire || io.liqRebind.fire || metadata.io.rebind.fire) { + assert(io.rebind.fire && io.liqRebind.fire && metadata.io.rebind.fire, + "canonical LIQ and OOO metadata rebind must be atomic") + } + when(io.recovery.prepared.fire) { + assert(RecoveryPlanContract.sameTransactionIgnoringPhase( + issuePipeline.io.recovery.prepared.bits, + metadata.io.recoveryPrepared.bits), + "canonical load owners must echo one exact common prepared plan") + } + when(io.recovery.apply.valid) { + assert(metadata.io.recoveryApplyAccepted, + "canonical load apply must match the commonly prepared plan") + } + when(io.recovery.abort.valid) { + assert(metadata.io.recoveryAbortAccepted, + "canonical load abort must match the commonly prepared plan") + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferFabric.scala b/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferFabric.scala index 02c8e6da..e65c587c 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferFabric.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferFabric.scala @@ -2,6 +2,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, RRArbiter, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.RecoveryPlan /** Elaboration-time projection of one picker/execution lane. */ final case class OooIexIssueDomainConfig( @@ -60,7 +62,9 @@ object OooIexIssueDomainConfig { } } -class OooIexE1TransferFabricIO(val p: OooParams = OooParams()) +class OooIexE1TransferFabricIO( + val p: OooParams = OooParams(), + val coreParams: CoreParams) extends Bundle { val i2 = Flipped(Vec(p.iexIssueDomainCount, Decoupled(new OooIexI2Transaction(p)))) @@ -70,7 +74,7 @@ class OooIexE1TransferFabricIO(val p: OooParams = OooParams()) val e1 = Vec(p.iexIssueDomainCount, Decoupled(new OooIexExecuteTransaction(p))) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(coreParams))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -96,13 +100,18 @@ class OooIexE1TransferFabricIO(val p: OooParams = OooParams()) */ class OooIexE1TransferFabric( val p: OooParams, - val domains: Seq[OooIexIssueDomainConfig]) extends Module { + val domains: Seq[OooIexIssueDomainConfig], + val coreParams: CoreParams) + extends Module { + def this(p: OooParams, domains: Seq[OooIexIssueDomainConfig]) = + this(p, domains, OooRecoveryMembership.coreParams(p)) OooIexIssueDomainConfig.validate(p, domains) + OooRecoveryMembership.requireCompatible(p, coreParams) - val io = IO(new OooIexE1TransferFabricIO(p)) + val io = IO(new OooIexE1TransferFabricIO(p, coreParams)) val slots = domains.zipWithIndex.map { case (domain, lane) => Module(new OooIexE1TransferSlot(p, domain.classBankEnables, lane, - domain.capabilities)) + domain.capabilities, coreParams)) } for (((slot, domain), lane) <- slots.zip(domains).zipWithIndex) { @@ -133,7 +142,7 @@ class OooIexE1TransferFabric( io.empty := !io.occupied.asUInt.orR } -/** Production Linx specialization driven by the formal physical profile. */ +/** Linx E1 transfer specialization driven by the physical profile. */ class OooIexLinxE1TransferFabric( val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile()) diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferSlot.scala b/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferSlot.scala index 8a40890d..f2b2c586 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferSlot.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexE1TransferSlot.scala @@ -2,6 +2,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} class OooIexE1TransferReject(val p: OooParams = OooParams()) extends Bundle { val member = new RobMemberKey(p) @@ -10,12 +12,15 @@ class OooIexE1TransferReject(val p: OooParams = OooParams()) extends Bundle { val incomingKilled = Bool() } -class OooIexE1TransferSlotIO(val p: OooParams = OooParams()) extends Bundle { +class OooIexE1TransferSlotIO( + val p: OooParams = OooParams(), + val coreParams: CoreParams) + extends Bundle { val i2 = Flipped(Decoupled(new OooIexI2Transaction(p))) val issueRelease = Decoupled(new OooIexIssueRelease(p)) val e1 = Decoupled(new OooIexExecuteTransaction(p)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(coreParams))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -36,8 +41,21 @@ class OooIexE1TransferSlot( val p: OooParams = OooParams(), val acceptedClassBankEnables: Seq[BigInt] = Seq.empty, val ownerLane: Int = 0, - val acceptedCapabilities: BigInt = OooIexDomainCapability.ValidMask) + val acceptedCapabilities: BigInt = OooIexDomainCapability.ValidMask, + val coreParams: CoreParams) extends Module { + def this(p: OooParams) = + this(p, Seq.empty, 0, OooIexDomainCapability.ValidMask, + OooRecoveryMembership.coreParams(p)) + + def this( + p: OooParams, + acceptedClassBankEnables: Seq[BigInt], + ownerLane: Int, + acceptedCapabilities: BigInt) = + this(p, acceptedClassBankEnables, ownerLane, acceptedCapabilities, + OooRecoveryMembership.coreParams(p)) + OooRecoveryMembership.requireCompatible(p, coreParams) private val defaultClassBankEnables = Seq.tabulate(p.iqClassCount) { classIndex => if (classIndex == OooUopClass.Alu.asUInt.litValue.toInt) @@ -59,15 +77,17 @@ class OooIexE1TransferSlot( (acceptedCapabilities & ~OooIexDomainCapability.ValidMask) == 0, "E1 transfer owner needs a nonempty declared capability mask") - val io = IO(new OooIexE1TransferSlotIO(p)) + val io = IO(new OooIexE1TransferSlotIO(p, coreParams)) val slotValid = RegInit(false.B) val slot = Reg(new OooIexExecuteTransaction(p)) val nextGeneration = RegInit(0.U(p.executeSlotGenerationWidth.W)) private def killedByRecovery(i2: OooIexI2Transaction): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, + io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + OooRecoveryMembership.memberKilled(p, coreParams, + io.recoveryApply.bits, i2.row.member) private def canceledByLoad(i2: OooIexI2Transaction): Bool = diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionCluster.scala b/chisel/src/main/scala/linxcore/ooo/OooIexExecutionCluster.scala index b1314103..35daa87f 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionCluster.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexExecutionCluster.scala @@ -1,7 +1,12 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, DecoupledIO, PopCount, Valid} +import chisel3.util.{Decoupled, DecoupledIO, PopCount, Valid, log2Ceil} +import linxcore.common.{CoreParams => LoadCoreParams} +import linxcore.params.CoreParams +import linxcore.top.interface.{CmdIssueTxn, RecoveryEvent, RecoveryPhase, + RecoveryPlan, RecoveryPlanContract, RecoveryTargetIO, RobNoflushReadyTxn, + RobNoflushTxn, RobResolveTxn, SystemIssueTxn} class OooIexExecutionRouteReject(val p: OooParams = OooParams()) extends Bundle { @@ -22,24 +27,47 @@ class OooIexExecutionRouteReject(val p: OooParams = OooParams()) * and engine-command work leave through explicit retained boundaries. The * upstream E1 slot remains the owner until one of those boundaries fires. */ -class OooIexExecutionClusterIO(val p: OooParams) extends Bundle { +class OooIexExecutionClusterIO( + val core: CoreParams, + val profile: OooIexPhysicalProfile, + val loadParams: LoadCoreParams) extends Bundle { + val p = profile.params private val terminalPorts = p.iexTerminalWidth * p.maxDestinationOperands + private def capabilityCount(capability: Int): Int = + profile.pickerFunctions.count(_.hasCapability(capability)) + private val aluCount = capabilityCount(OooIexDomainCapability.SimpleAlu) + private val bruCount = capabilityCount(OooIexDomainCapability.Branch) + private val loadCount = capabilityCount(OooIexDomainCapability.LoadAddress) + private val storeAddressCount = + capabilityCount(OooIexDomainCapability.StoreAddress) + private val storeDataCount = capabilityCount(OooIexDomainCapability.StoreData) + private val multiCycleCount = + capabilityCount(OooIexDomainCapability.MultiCycleAlu) + private val systemCount = capabilityCount(OooIexDomainCapability.System) + private val pointerAuthCount = + capabilityCount(OooIexDomainCapability.PointerAuth) - val e1 = Flipped(Vec(OooIexLinxPhysicalProfile.ExecutionLaneCount, + val e1 = Flipped(Vec(profile.pickerFunctions.length, Decoupled(new OooIexExecuteTransaction(p)))) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recovery = Flipped(new RecoveryTargetIO(core)) - val storeAddress = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val storeData = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val multiCycleAlu = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val system = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val pointerAuth = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) + val storeAddress = Vec(storeAddressCount, + Decoupled(new OooIexExecuteTransaction(p))) + val storeData = Vec(storeDataCount, + Decoupled(new OooIexExecuteTransaction(p))) + val multiCycleAlu = Vec(multiCycleCount, + Decoupled(new OooIexExecuteTransaction(p))) + val pointerAuth = Vec(pointerAuthCount, + Decoupled(new OooIexExecuteTransaction(p))) val floatingVector = Decoupled(new OooIexExecuteTransaction(p)) - val engineCommand = Decoupled(new OooIexExecuteTransaction(p)) + val robNoflushReady = Decoupled(new RobNoflushReadyTxn(core)) + val robNoflush = Flipped(Decoupled(new RobNoflushTxn(core))) + val systemIssue = Vec(systemCount, Decoupled(new SystemIssueTxn(core))) + val cmdIssue = Decoupled(new CmdIssueTxn(core)) + val systemCmdResolve = Decoupled(new RobResolveTxn(core)) + val systemCmdTrace = Decoupled(new OooIexTerminalTrace(p)) - val memoryRequest = Vec(3, Decoupled(new OooIexLoadMemoryRequest(p))) - val memoryResponse = Flipped(Vec(3, - Decoupled(new OooIexLoadMemoryResponse(p)))) + val load = new OooIexCanonicalLoadPortIO(p, loadParams) val pWrite = Vec(terminalPorts, Decoupled(new OooIexPFileWrite(p))) val tWrite = Vec(terminalPorts, Decoupled(new OooIexLocalFileWrite(p))) @@ -54,42 +82,60 @@ class OooIexExecutionClusterIO(val p: OooParams) extends Bundle { Decoupled(new OooIexTerminalBctrl(p))) val trace = Vec(p.iexTerminalWidth, Decoupled(new OooIexTerminalTrace(p))) - val completion = Vec(p.iexTerminalWidth, - Decoupled(new OooRobMemberCompletion(p))) + val robResolve = Vec(p.iexTerminalWidth, + Decoupled(new RobResolveTxn(core))) + val recoveryEvent = Vec(p.iexTerminalWidth, + Decoupled(new RecoveryEvent(core))) + val architecturalAccepted = Output(Vec(p.iexTerminalWidth, + Valid(new OooIexTerminalRequest(p)))) - val routeRejected = Output(Vec( - OooIexLinxPhysicalProfile.ExecutionLaneCount, + val routeRejected = Output(Vec(profile.pickerFunctions.length, Valid(new OooIexExecutionRouteReject(p)))) - val aluRejected = Output(Vec(6, Valid(new OooIexAluReject(p)))) - val bruRejected = Output(Vec(2, Valid(new OooIexBruReject(p)))) - val aguRejected = Output(Vec(3, Valid(new OooIexAguReject(p)))) - val loadAcceptRejected = Output(Vec(3, - Valid(new OooIexLoadAcceptReject(p)))) - val loadResponseRejected = Output(Vec(3, - Valid(new OooIexLoadResponseReject(p)))) + val aluRejected = Output(Vec(aluCount, Valid(new OooIexAluReject(p)))) + val bruRejected = Output(Vec(bruCount, Valid(new OooIexBruReject(p)))) + val aguRejected = Output(Vec(loadCount, Valid(new OooIexAguReject(p)))) val terminalRejected = Output(Vec(p.iexTerminalWidth, Vec(3, Valid(new OooIexTerminalReject(p))))) val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) - val loadOccupied = Output(Vec(3, - UInt(p.countWidth(p.iexLoadTrackEntries).W))) + val systemCmdTerminalFire = Output(Bool()) + val loadMetadataOccupied = Output(UInt( + log2Ceil(loadParams.scalarLsu.liqEntries + 1).W)) val empty = Output(Bool()) } class OooIexExecutionCluster( - val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile()) + val core: CoreParams, + val loadParamsOverride: Option[LoadCoreParams] = None) extends Module { import OooIexDomainCapability._ + val profile = OooIexPhysicalProfile.fromCoreParams(core) val p = profile.params - private val aluCount = 6 - private val bruCount = 2 - private val loadCount = 3 + val loadParams = loadParamsOverride.getOrElse( + OooIexCanonicalLoadOwnership.defaultCoreParams(p)) + private def pickerIndices(capability: Int): Seq[Int] = + profile.pickerFunctions.zipWithIndex.collect { + case (picker, index) if picker.hasCapability(capability) => index + } + private val aluLanes = pickerIndices(SimpleAlu) + private val bruLanes = pickerIndices(Branch) + private val loadLanes = pickerIndices(LoadAddress) + private val storeAddressLanes = pickerIndices(StoreAddress) + private val storeDataLanes = pickerIndices(StoreData) + private val multiCycleLanes = pickerIndices(MultiCycleAlu) + private val systemLanes = pickerIndices(System) + private val pointerAuthLanes = pickerIndices(PointerAuth) + private val floatingVectorLanes = pickerIndices(FloatingVector) + private val engineCommandLanes = pickerIndices(EngineCommand) + private val aluCount = aluLanes.length + private val bruCount = bruLanes.length + private val loadCount = loadLanes.length private val terminalPorts = p.iexTerminalWidth * p.maxDestinationOperands - require(profile.name == "linx-scalar-control-v2" && - profile.pickerFunctions.length == - OooIexLinxPhysicalProfile.PickerFunctionCount, - "execution cluster requires the formal Linx scalar/control profile") + require(aluCount > 0 && bruCount > 0 && loadCount > 0, + "execution cluster requires ALU, BRU, and load-address mechanisms") + require(floatingVectorLanes.length == 1 && engineCommandLanes.length == 1, + "execution cluster retains one floating/vector and one command boundary") require(p.iexWakeupPorts >= terminalPorts + loadCount, "committed and speculative load wakeups need independent ports") require(p.iexBypassPorts >= aluCount + loadCount, @@ -97,47 +143,138 @@ class OooIexExecutionCluster( require(p.iexLoadCancelPorts >= loadCount, "every scalar load pipe needs an independent cancel port") - val io = IO(new OooIexExecutionClusterIO(p)) + val io = IO(new OooIexExecutionClusterIO(core, profile, loadParams)) - val alus = Seq.fill(aluCount)(Module(new OooIexAluPipeline(p))) - val brus = Seq.fill(bruCount)(Module(new OooIexBruPipeline(p))) - val agus = Seq.fill(loadCount)(Module(new OooIexAguPipeline(p))) - val loads = Seq.fill(loadCount)(Module(new OooIexLoadUnit(p))) + val alus = Seq.fill(aluCount)(Module(new OooIexAluPipeline(p, core))) + val brus = Seq.fill(bruCount)(Module(new OooIexBruPipeline(p, core))) + val agus = Seq.fill(loadCount)(Module(new OooIexAguPipeline(p, core))) + val load = Module(new OooIexCanonicalLoadOwnership( + p, loadParams, laneCount = loadCount, recoveryParams = core)) val terminal = Module(new OooIexTerminalFabric( - p, aluCount, bruCount, loadCount)) + core, aluCount, bruCount, loadCount)) + val systemCmd = Module(new OooIexSystemCmdTerminal(core)) + + val recoveryPending = RegInit(false.B) + val childrenPreparedAccepted = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val prepareReady = !recoveryPending && terminal.io.recovery.prepare.ready && + load.io.recovery.prepare.ready && systemCmd.io.recovery.prepare.ready + io.recovery.prepare.ready := prepareReady + terminal.io.recovery.prepare.valid := io.recovery.prepare.valid && prepareReady + terminal.io.recovery.prepare.bits := io.recovery.prepare.bits + load.io.recovery.prepare.valid := io.recovery.prepare.valid && prepareReady + load.io.recovery.prepare.bits := io.recovery.prepare.bits + systemCmd.io.recovery.prepare.valid := + io.recovery.prepare.valid && prepareReady + systemCmd.io.recovery.prepare.bits := io.recovery.prepare.bits + when(io.recovery.prepare.fire) { + retainedRecovery := io.recovery.prepare.bits + recoveryPending := true.B + childrenPreparedAccepted := false.B + } + + val childrenPrepared = terminal.io.recovery.prepared.valid && + load.io.recovery.prepared.valid && systemCmd.io.recovery.prepared.valid + io.recovery.prepared.valid := recoveryPending && childrenPrepared + io.recovery.prepared.bits := retainedRecovery + io.recovery.prepared.bits.phase := RecoveryPhase.Prepare + terminal.io.recovery.prepared.ready := io.recovery.prepared.ready && + load.io.recovery.prepared.valid && systemCmd.io.recovery.prepared.valid + load.io.recovery.prepared.ready := io.recovery.prepared.ready && + terminal.io.recovery.prepared.valid && systemCmd.io.recovery.prepared.valid + systemCmd.io.recovery.prepared.ready := io.recovery.prepared.ready && + terminal.io.recovery.prepared.valid && load.io.recovery.prepared.valid + + val preparedPlansExact = childrenPrepared && + RecoveryPlanContract.sameTransactionIgnoringPhase( + terminal.io.recovery.prepared.bits, retainedRecovery) && + RecoveryPlanContract.sameTransactionIgnoringPhase( + load.io.recovery.prepared.bits, retainedRecovery) && + RecoveryPlanContract.sameTransactionIgnoringPhase( + systemCmd.io.recovery.prepared.bits, retainedRecovery) + when(io.recovery.prepared.fire) { + assert(preparedPlansExact, + "execution children must prepare one exact recovery transaction") + childrenPreparedAccepted := preparedPlansExact + } + val applyExact = io.recovery.apply.valid && recoveryPending && + childrenPreparedAccepted && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val abortExact = io.recovery.abort.valid && recoveryPending && + childrenPreparedAccepted && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + val recoveryApply = Wire(Valid(new RecoveryPlan(core))) + recoveryApply.valid := applyExact + recoveryApply.bits := retainedRecovery + recoveryApply.bits.phase := RecoveryPhase.Apply + terminal.io.recovery.apply.valid := applyExact + terminal.io.recovery.apply.bits := recoveryApply.bits + load.io.recovery.apply.valid := applyExact + load.io.recovery.apply.bits := recoveryApply.bits + systemCmd.io.recovery.apply.valid := applyExact + systemCmd.io.recovery.apply.bits := recoveryApply.bits + terminal.io.recovery.abort.valid := abortExact + terminal.io.recovery.abort.bits := retainedRecovery + terminal.io.recovery.abort.bits.phase := RecoveryPhase.Abort + load.io.recovery.abort.valid := abortExact + load.io.recovery.abort.bits := retainedRecovery + load.io.recovery.abort.bits.phase := RecoveryPhase.Abort + systemCmd.io.recovery.abort.valid := abortExact + systemCmd.io.recovery.abort.bits := retainedRecovery + systemCmd.io.recovery.abort.bits.phase := RecoveryPhase.Abort + when(applyExact || abortExact) { + recoveryPending := false.B + childrenPreparedAccepted := false.B + } + when(io.recovery.apply.valid) { + assert(applyExact, + "execution recovery apply requires the exact prepared transaction") + } + when(io.recovery.abort.valid) { + assert(abortExact, + "execution recovery abort requires the exact prepared transaction") + } for (index <- 0 until aluCount) { - alus(index).io.recoveryApply := io.recoveryApply + alus(index).io.recoveryApply := recoveryApply alus(index).io.loadCancel := io.loadCancel terminal.io.alu(index) <> alus(index).io.w2 io.aluRejected(index) := alus(index).io.rejected } for (index <- 0 until bruCount) { - brus(index).io.recoveryApply := io.recoveryApply + brus(index).io.recoveryApply := recoveryApply brus(index).io.loadCancel := io.loadCancel terminal.io.bru(index) <> brus(index).io.e2 io.bruRejected(index) := brus(index).io.rejected } for (index <- 0 until loadCount) { - agus(index).io.recoveryApply := io.recoveryApply + agus(index).io.recoveryApply := recoveryApply agus(index).io.loadCancel := io.loadCancel - loads(index).io.recoveryApply := io.recoveryApply - loads(index).io.agu <> agus(index).io.request - terminal.io.load(index) <> loads(index).io.result - - io.memoryRequest(index).valid := loads(index).io.memoryRequest.valid - io.memoryRequest(index).bits := loads(index).io.memoryRequest.bits - loads(index).io.memoryRequest.ready := io.memoryRequest(index).ready - loads(index).io.memoryResponse.valid := io.memoryResponse(index).valid - loads(index).io.memoryResponse.bits := io.memoryResponse(index).bits - io.memoryResponse(index).ready := loads(index).io.memoryResponse.ready + load.io.agu(index) <> agus(index).io.request io.aguRejected(index) := agus(index).io.rejected - io.loadAcceptRejected(index) := loads(index).io.acceptRejected - io.loadResponseRejected(index) := loads(index).io.responseRejected - io.loadOccupied(index) := loads(index).io.occupied } + io.load.liqAlloc <> load.io.liqAlloc + load.io.liqAllocLoadId := io.load.liqAllocLoadId + load.io.rebind <> io.load.rebind + io.load.liqRebind <> load.io.liqRebind + load.io.attemptLaunch := io.load.attemptLaunch + io.load.attemptLaunchAccepted := load.io.attemptLaunchAccepted + load.io.completion <> io.load.completion + for (index <- 0 until loadCount) { + terminal.io.load(index).valid := load.io.result.valid && + load.io.resultLane === index.U + terminal.io.load(index).bits := load.io.result.bits + } + load.io.result.ready := VecInit(terminal.io.load.map(_.ready))( + load.io.resultLane) + io.loadMetadataOccupied := load.io.metadataOccupied + for (port <- 0 until terminalPorts) { io.pWrite(port).valid := terminal.io.pWrite(port).valid io.pWrite(port).bits := terminal.io.pWrite(port).bits @@ -156,12 +293,22 @@ class OooIexExecutionCluster( io.trace(lane).valid := terminal.io.trace(lane).valid io.trace(lane).bits := terminal.io.trace(lane).bits terminal.io.trace(lane).ready := io.trace(lane).ready - io.completion(lane).valid := terminal.io.completion(lane).valid - io.completion(lane).bits := terminal.io.completion(lane).bits - terminal.io.completion(lane).ready := io.completion(lane).ready + io.robResolve(lane) <> terminal.io.robResolve(lane) + io.recoveryEvent(lane) <> terminal.io.recoveryEvent(lane) } io.terminalRejected := terminal.io.rejected io.terminalFireMask := terminal.io.terminalFireMask + io.architecturalAccepted := terminal.io.architecturalAccepted + + io.robNoflushReady <> systemCmd.io.robNoflushReady + systemCmd.io.robNoflush <> io.robNoflush + for (lane <- io.systemIssue.indices) { + io.systemIssue(lane) <> systemCmd.io.systemIssue(lane) + } + io.cmdIssue <> systemCmd.io.cmdIssue + io.systemCmdResolve <> systemCmd.io.robResolve + io.systemCmdTrace <> systemCmd.io.trace + io.systemCmdTerminalFire := systemCmd.io.terminalFire io.wakeup.foreach(_ := 0.U.asTypeOf(io.wakeup.head)) for (port <- 0 until terminalPorts) { @@ -170,7 +317,7 @@ class OooIexExecutionCluster( terminal.io.wakeup(port).ready := true.B } for (index <- 0 until loadCount) { - io.wakeup(terminalPorts + index) := loads(index).io.speculativeWakeup + io.wakeup(terminalPorts + index) := load.io.speculativeWakeup(index) } io.bypass.foreach(_ := 0.U.asTypeOf(io.bypass.head)) @@ -198,12 +345,12 @@ class OooIexExecutionCluster( io.bypass(index).bits.data := writeback.data } for (index <- 0 until loadCount) { - io.bypass(aluCount + index) := loads(index).io.bypass + io.bypass(aluCount + index) := load.io.loadBypass(index) } io.loadCancel.foreach(_ := 0.U.asTypeOf(io.loadCancel.head)) for (index <- 0 until loadCount) { - io.loadCancel(index) := loads(index).io.cancel + io.loadCancel(index) := load.io.loadCancel(index) } private def route( @@ -246,40 +393,37 @@ class OooIexExecutionCluster( "one E1 owner must select at most one typed execution destination") } - val aluLanes = (0 until aluCount).map(index => - profile.pickerIndex(s"alu$index")) - route(aluLanes(0), Seq(SimpleAlu -> alus(0).io.e1, - StoreData -> io.storeData(0))) - route(aluLanes(1), Seq(SimpleAlu -> alus(1).io.e1)) - route(aluLanes(2), Seq(SimpleAlu -> alus(2).io.e1, - MultiCycleAlu -> io.multiCycleAlu(0), System -> io.system(0), - PointerAuth -> io.pointerAuth(0))) - route(aluLanes(3), Seq(SimpleAlu -> alus(3).io.e1, - StoreData -> io.storeData(1))) - route(aluLanes(4), Seq(SimpleAlu -> alus(4).io.e1)) - route(aluLanes(5), Seq(SimpleAlu -> alus(5).io.e1, - MultiCycleAlu -> io.multiCycleAlu(1), System -> io.system(1), - PointerAuth -> io.pointerAuth(1))) - - route(profile.pickerIndex("agu0-lda"), - Seq(LoadAddress -> agus(0).io.e1)) - route(profile.pickerIndex("agu0-sta"), - Seq(StoreAddress -> io.storeAddress(0))) - route(profile.pickerIndex("agu1-lda"), - Seq(LoadAddress -> agus(1).io.e1)) - route(profile.pickerIndex("agu1-sta"), - Seq(StoreAddress -> io.storeAddress(1))) - route(profile.pickerIndex("agu2-lda"), - Seq(LoadAddress -> agus(2).io.e1)) - route(profile.pickerIndex("bru0"), Seq(Branch -> brus(0).io.e1)) - route(profile.pickerIndex("bru1"), Seq(Branch -> brus(1).io.e1)) - route(profile.pickerIndex("fsu0"), Seq( - FloatingVector -> io.floatingVector, - EngineCommand -> io.engineCommand)) + for (domain <- profile.pickerFunctions.indices) { + val destinations = scala.collection.mutable.ArrayBuffer.empty[ + (Int, DecoupledIO[OooIexExecuteTransaction])] + def append(capability: Int, lanes: Seq[Int], + outputs: Seq[DecoupledIO[OooIexExecuteTransaction]]): Unit = { + val ordinal = lanes.indexOf(domain) + if (ordinal >= 0) destinations += capability -> outputs(ordinal) + } + append(SimpleAlu, aluLanes, alus.map(_.io.e1)) + append(StoreData, storeDataLanes, io.storeData.toSeq) + append(LoadAddress, loadLanes, agus.map(_.io.e1)) + append(StoreAddress, storeAddressLanes, io.storeAddress.toSeq) + append(Branch, bruLanes, brus.map(_.io.e1)) + append(MultiCycleAlu, multiCycleLanes, io.multiCycleAlu.toSeq) + append(System, systemLanes, systemCmd.io.system.toSeq) + append(PointerAuth, pointerAuthLanes, io.pointerAuth.toSeq) + if (floatingVectorLanes.contains(domain)) + destinations += FloatingVector -> io.floatingVector + if (engineCommandLanes.contains(domain)) { + val ordinal = engineCommandLanes.indexOf(domain) + destinations += EngineCommand -> systemCmd.io.cmd(ordinal) + } + require(destinations.nonEmpty, + s"IEX picker ${profile.pickerFunctions(domain).name} has no execution destination") + route(domain, destinations.toSeq) + } val internalEmpty = alus.map(_.io.empty).reduce(_ && _) && brus.map(!_.io.occupied).reduce(_ && _) && agus.map(!_.io.occupied).reduce(_ && _) && - loads.map(_.io.occupied === 0.U).reduce(_ && _) - io.empty := internalEmpty && !io.e1.map(_.valid).reduce(_ || _) + load.io.metadataEmpty && systemCmd.io.empty + io.empty := !recoveryPending && internalEmpty && + !io.e1.map(_.valid).reduce(_ || _) } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala index db540df9..2345b9b3 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala @@ -2,38 +2,41 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, Valid} +import linxcore.common.{CoreParams => LoadCoreParams} +import linxcore.params.CoreParams +import linxcore.top.interface.{CmdIssueTxn, PcBufferReadAddress, RecoveryEvent, + RecoveryPhase, RecoveryPlan, RecoveryPlanContract, RecoveryTargetIO, + RobNoflushReadyTxn, RobNoflushTxn, RobResolveTxn, SystemIssueTxn} -/** Production static composition from OOO S1 through typed execution owners. +/** Private stage composition from canonical issue through typed execution owners. * * The wrapper keeps IQ/read/E1 ownership in `OooIexPipeline`, feeds execution * results back into its canonical P/T/U files and wakeup/bypass domains, and * exposes only execution families whose later owners are still external. */ class OooIexExecutionPipelineIO( - val p: OooParams, - val requireStoreReservation: Boolean = false) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) + val core: CoreParams, + val profile: OooIexPhysicalProfile, + val requireStoreReservation: Boolean, + val loadParams: LoadCoreParams) extends Bundle { + val p = profile.params + private def capabilityCount(capability: Int): Int = + profile.pickerFunctions.count(_.hasCapability(capability)) + val dispatch = Flipped(new OOODispatchChannels(core)) val storeReserve = if (requireStoreReservation) Some( - Decoupled(new OooIexIssueRow(p))) else None - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryRejected = Output(Valid(new OooIexRecoveryReject(p))) - val recoveryFire = Input(Bool()) + Vec(core.iex.stdPipes, Decoupled(new OooIexIssueRow(p)))) else None + val recovery = Flipped(new RecoveryTargetIO(core)) val issuePolicy = Input(new OooIexIssuePolicy(p)) val stageCancels = Flipped(Vec(p.iexIssueDomainCount, Vec(2, Decoupled(new OooIexStageCancel(p))))) val pcReadRequests = Output(Vec(p.pcReadPorts, - Valid(new OooIexPcReadPortRequest(p)))) + Valid(new PcBufferReadAddress(core)))) val pcReadResponses = Input(Vec(p.pcReadPorts, Valid(UInt(p.pcWidth.W)))) val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) + val pClear = Flipped(Vec(p.pTagAllocationWidth, + Valid(new OooIexPFileKey(p)))) val fastWriteback = Flipped(Decoupled(new OooFastResolveWriteback(p))) val fastWakeup = Flipped(Decoupled(new OooIexWakeup(p))) val tClear = Flipped(Vec(p.tuAllocationWidth, @@ -41,16 +44,26 @@ class OooIexExecutionPipelineIO( val uClear = Flipped(Vec(p.tuAllocationWidth, Valid(new OooIexLocalFileKey(p)))) - val storeAddress = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val storeData = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val multiCycleAlu = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val system = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val pointerAuth = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) + val storeAddress = Vec(capabilityCount( + OooIexDomainCapability.StoreAddress), + Decoupled(new OooIexExecuteTransaction(p))) + val storeData = Vec(capabilityCount(OooIexDomainCapability.StoreData), + Decoupled(new OooIexExecuteTransaction(p))) + val multiCycleAlu = Vec(capabilityCount( + OooIexDomainCapability.MultiCycleAlu), + Decoupled(new OooIexExecuteTransaction(p))) + val pointerAuth = Vec(capabilityCount( + OooIexDomainCapability.PointerAuth), + Decoupled(new OooIexExecuteTransaction(p))) val floatingVector = Decoupled(new OooIexExecuteTransaction(p)) - val engineCommand = Decoupled(new OooIexExecuteTransaction(p)) - val memoryRequest = Vec(3, Decoupled(new OooIexLoadMemoryRequest(p))) - val memoryResponse = Flipped(Vec(3, - Decoupled(new OooIexLoadMemoryResponse(p)))) + val robNoflushReady = Decoupled(new RobNoflushReadyTxn(core)) + val robNoflush = Flipped(Decoupled(new RobNoflushTxn(core))) + val systemIssue = Vec(capabilityCount(OooIexDomainCapability.System), + Decoupled(new SystemIssueTxn(core))) + val cmdIssue = Decoupled(new CmdIssueTxn(core)) + val systemCmdResolve = Decoupled(new RobResolveTxn(core)) + val systemCmdTrace = Decoupled(new OooIexTerminalTrace(p)) + val load = new OooIexCanonicalLoadPortIO(p, loadParams) val loadCancel = Output(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) @@ -58,16 +71,20 @@ class OooIexExecutionPipelineIO( Decoupled(new OooIexTerminalBctrl(p))) val trace = Vec(p.iexTerminalWidth, Decoupled(new OooIexTerminalTrace(p))) - val completion = Vec(p.iexTerminalWidth, - Decoupled(new OooRobMemberCompletion(p))) + val robResolve = Vec(p.iexTerminalWidth, + Decoupled(new RobResolveTxn(core))) + val recoveryEvent = Vec(p.iexTerminalWidth, + Decoupled(new RecoveryEvent(core))) + val architecturalAccepted = Output(Vec(p.iexTerminalWidth, + Valid(new OooIexTerminalRequest(p)))) val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) + val systemCmdTerminalFire = Output(Bool()) val transferFireMask = Output(UInt(p.iexReleaseWidth.W)) val pWriteFire = Output(Vec(p.iexPWritePorts, Bool())) val tWriteFire = Output(Vec(p.iexTWritePorts, Bool())) val uWriteFire = Output(Vec(p.iexUWritePorts, Bool())) - val routeRejected = Output(Vec( - OooIexLinxPhysicalProfile.ExecutionLaneCount, + val routeRejected = Output(Vec(profile.pickerFunctions.length, Valid(new OooIexExecutionRouteReject(p)))) val terminalRejected = Output(Vec(p.iexTerminalWidth, Vec(3, Valid(new OooIexTerminalReject(p))))) @@ -85,34 +102,99 @@ class OooIexExecutionPipelineIO( } class OooIexExecutionPipeline( - val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile(), - val requireStoreReservation: Boolean = false) + val core: CoreParams, + val requireStoreReservation: Boolean = false, + val loadParamsOverride: Option[LoadCoreParams] = None) extends Module { + val profile = OooIexPhysicalProfile.fromCoreParams(core) val p = profile.params + val loadParams = loadParamsOverride.getOrElse( + OooIexCanonicalLoadOwnership.defaultCoreParams(p)) private val terminalPorts = p.iexTerminalWidth * p.maxDestinationOperands private val fastPWritePort = terminalPorts private val fastWakeupPort = p.iexWakeupPorts - 1 - private val committedAndLoadWakeupPorts = terminalPorts + 3 + private val loadCount = profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.LoadAddress)) + private val committedAndLoadWakeupPorts = terminalPorts + loadCount require(p.iexPWritePorts > terminalPorts, - "production execution needs one dedicated fast-result P write port") + "IEX terminal composition needs one dedicated fast-result P write port") require(p.iexWakeupPorts > committedAndLoadWakeupPorts, - "production execution needs one dedicated fast-result wakeup port") - val io = IO(new OooIexExecutionPipelineIO(p, requireStoreReservation)) + "IEX terminal composition needs one dedicated fast-result wakeup port") + val io = IO(new OooIexExecutionPipelineIO( + core, profile, requireStoreReservation, loadParams)) - val issue = Module(new OooIexPipeline(profile, requireStoreReservation)) - val execute = Module(new OooIexExecutionCluster(profile)) + val issue = Module(new OooIexPipeline(core, requireStoreReservation)) + val execute = Module(new OooIexExecutionCluster(core, Some(loadParams))) - issue.io.s1 <> io.s1 + issue.io.dispatch <> io.dispatch if (requireStoreReservation) { io.storeReserve.get <> issue.io.storeReserve.get } - io.dispatchReleases <> issue.io.dispatchReleases - issue.io.ptagRecycle <> io.ptagRecycle - issue.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := issue.io.recoveryPrepareReady - io.recoveryPrepared := issue.io.recoveryPrepared - io.recoveryRejected := issue.io.recoveryRejected - issue.io.recoveryFire := io.recoveryFire + val recoveryPending = RegInit(false.B) + val childrenPreparedAccepted = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val prepareReady = !recoveryPending && issue.io.recovery.prepare.ready && + execute.io.recovery.prepare.ready + io.recovery.prepare.ready := prepareReady + issue.io.recovery.prepare.valid := io.recovery.prepare.valid && prepareReady + issue.io.recovery.prepare.bits := io.recovery.prepare.bits + execute.io.recovery.prepare.valid := io.recovery.prepare.valid && prepareReady + execute.io.recovery.prepare.bits := io.recovery.prepare.bits + when(io.recovery.prepare.fire) { + retainedRecovery := io.recovery.prepare.bits + recoveryPending := true.B + childrenPreparedAccepted := false.B + } + + val bothPrepared = issue.io.recovery.prepared.valid && + execute.io.recovery.prepared.valid + io.recovery.prepared.valid := recoveryPending && bothPrepared + io.recovery.prepared.bits := retainedRecovery + io.recovery.prepared.bits.phase := RecoveryPhase.Prepare + issue.io.recovery.prepared.ready := io.recovery.prepared.ready && + execute.io.recovery.prepared.valid + execute.io.recovery.prepared.ready := io.recovery.prepared.ready && + issue.io.recovery.prepared.valid + when(io.recovery.prepared.fire) { + assert(RecoveryPlanContract.sameTransactionIgnoringPhase( + issue.io.recovery.prepared.bits, + execute.io.recovery.prepared.bits), + "issue and execution must prepare one exact recovery transaction") + assert(RecoveryPlanContract.sameTransactionIgnoringPhase( + issue.io.recovery.prepared.bits, retainedRecovery), + "issue must echo the retained recovery transaction") + childrenPreparedAccepted := true.B + } + val applyExact = io.recovery.apply.valid && recoveryPending && + childrenPreparedAccepted && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val abortExact = io.recovery.abort.valid && recoveryPending && + childrenPreparedAccepted && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + issue.io.recovery.apply.valid := applyExact + issue.io.recovery.apply.bits := io.recovery.apply.bits + execute.io.recovery.apply.valid := applyExact + execute.io.recovery.apply.bits := io.recovery.apply.bits + issue.io.recovery.abort.valid := abortExact + issue.io.recovery.abort.bits := io.recovery.abort.bits + execute.io.recovery.abort.valid := abortExact + execute.io.recovery.abort.bits := io.recovery.abort.bits + when(applyExact || abortExact) { + recoveryPending := false.B + childrenPreparedAccepted := false.B + } + when(io.recovery.apply.valid) { + assert(applyExact, + "IEX recovery apply requires the exact prepared transaction") + } + when(io.recovery.abort.valid) { + assert(abortExact, + "IEX recovery abort requires the exact prepared transaction") + } issue.io.issuePolicy := io.issuePolicy issue.io.stageCancels <> io.stageCancels io.pcReadRequests := issue.io.pcReadRequests @@ -125,8 +207,6 @@ class OooIexExecutionPipeline( for (domain <- 0 until p.iexIssueDomainCount) { execute.io.e1(domain) <> issue.io.e1(domain) } - execute.io.recoveryApply.valid := io.recoveryFire - execute.io.recoveryApply.bits := io.recoveryPrepare.bits issue.io.wakeup := execute.io.wakeup issue.io.bypass := execute.io.bypass issue.io.loadCancel := execute.io.loadCancel @@ -173,19 +253,22 @@ class OooIexExecutionPipeline( } } - for (index <- 0 until 2) { + for (index <- io.storeAddress.indices) { io.storeAddress(index).valid := execute.io.storeAddress(index).valid io.storeAddress(index).bits := execute.io.storeAddress(index).bits execute.io.storeAddress(index).ready := io.storeAddress(index).ready + } + for (index <- io.storeData.indices) { io.storeData(index).valid := execute.io.storeData(index).valid io.storeData(index).bits := execute.io.storeData(index).bits execute.io.storeData(index).ready := io.storeData(index).ready + } + for (index <- io.multiCycleAlu.indices) { io.multiCycleAlu(index).valid := execute.io.multiCycleAlu(index).valid io.multiCycleAlu(index).bits := execute.io.multiCycleAlu(index).bits execute.io.multiCycleAlu(index).ready := io.multiCycleAlu(index).ready - io.system(index).valid := execute.io.system(index).valid - io.system(index).bits := execute.io.system(index).bits - execute.io.system(index).ready := io.system(index).ready + } + for (index <- io.pointerAuth.indices) { io.pointerAuth(index).valid := execute.io.pointerAuth(index).valid io.pointerAuth(index).bits := execute.io.pointerAuth(index).bits execute.io.pointerAuth(index).ready := io.pointerAuth(index).ready @@ -193,18 +276,35 @@ class OooIexExecutionPipeline( io.floatingVector.valid := execute.io.floatingVector.valid io.floatingVector.bits := execute.io.floatingVector.bits execute.io.floatingVector.ready := io.floatingVector.ready - io.engineCommand.valid := execute.io.engineCommand.valid - io.engineCommand.bits := execute.io.engineCommand.bits - execute.io.engineCommand.ready := io.engineCommand.ready - - for (index <- 0 until 3) { - io.memoryRequest(index).valid := execute.io.memoryRequest(index).valid - io.memoryRequest(index).bits := execute.io.memoryRequest(index).bits - execute.io.memoryRequest(index).ready := io.memoryRequest(index).ready - execute.io.memoryResponse(index).valid := io.memoryResponse(index).valid - execute.io.memoryResponse(index).bits := io.memoryResponse(index).bits - io.memoryResponse(index).ready := execute.io.memoryResponse(index).ready + io.robNoflushReady.valid := execute.io.robNoflushReady.valid + io.robNoflushReady.bits := execute.io.robNoflushReady.bits + execute.io.robNoflushReady.ready := io.robNoflushReady.ready + execute.io.robNoflush.valid := io.robNoflush.valid + execute.io.robNoflush.bits := io.robNoflush.bits + io.robNoflush.ready := execute.io.robNoflush.ready + for (index <- io.systemIssue.indices) { + io.systemIssue(index).valid := execute.io.systemIssue(index).valid + io.systemIssue(index).bits := execute.io.systemIssue(index).bits + execute.io.systemIssue(index).ready := io.systemIssue(index).ready } + io.cmdIssue.valid := execute.io.cmdIssue.valid + io.cmdIssue.bits := execute.io.cmdIssue.bits + execute.io.cmdIssue.ready := io.cmdIssue.ready + io.systemCmdResolve.valid := execute.io.systemCmdResolve.valid + io.systemCmdResolve.bits := execute.io.systemCmdResolve.bits + execute.io.systemCmdResolve.ready := io.systemCmdResolve.ready + io.systemCmdTrace.valid := execute.io.systemCmdTrace.valid + io.systemCmdTrace.bits := execute.io.systemCmdTrace.bits + execute.io.systemCmdTrace.ready := io.systemCmdTrace.ready + + io.load.liqAlloc <> execute.io.load.liqAlloc + execute.io.load.liqAllocLoadId := io.load.liqAllocLoadId + execute.io.load.rebind <> io.load.rebind + io.load.liqRebind <> execute.io.load.liqRebind + execute.io.load.attemptLaunch := io.load.attemptLaunch + io.load.attemptLaunchAccepted := + execute.io.load.attemptLaunchAccepted + execute.io.load.completion <> io.load.completion for (lane <- 0 until p.iexTerminalWidth) { io.bctrl(lane).valid := execute.io.bctrl(lane).valid io.bctrl(lane).bits := execute.io.bctrl(lane).bits @@ -212,12 +312,13 @@ class OooIexExecutionPipeline( io.trace(lane).valid := execute.io.trace(lane).valid io.trace(lane).bits := execute.io.trace(lane).bits execute.io.trace(lane).ready := io.trace(lane).ready - io.completion(lane).valid := execute.io.completion(lane).valid - io.completion(lane).bits := execute.io.completion(lane).bits - execute.io.completion(lane).ready := io.completion(lane).ready + io.robResolve(lane) <> execute.io.robResolve(lane) + io.recoveryEvent(lane) <> execute.io.recoveryEvent(lane) } io.terminalFireMask := execute.io.terminalFireMask + io.architecturalAccepted := execute.io.architecturalAccepted + io.systemCmdTerminalFire := execute.io.systemCmdTerminalFire io.transferFireMask := issue.io.transferFireMask io.pWriteFire := issue.io.pWriteFire io.tWriteFire := issue.io.tWriteFire @@ -229,13 +330,12 @@ class OooIexExecutionPipeline( io.inFlightEntries := issue.io.inFlightEntries io.issueEmpty := issue.io.empty io.executionEmpty := execute.io.empty - io.empty := issue.io.empty && execute.io.empty + dontTouch(io.residentEntries) + dontTouch(io.inFlightEntries) + dontTouch(io.issueEmpty) + dontTouch(io.executionEmpty) + io.empty := !recoveryPending && issue.io.empty && execute.io.empty io.pProtocolError := issue.io.pProtocolError io.localProtocolError := issue.io.localProtocolError - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && issue.io.recoveryPrepareReady && - issue.io.recoveryPrepared.valid, - "execution-pipeline recovery needs one held prepared issue plan") - } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionStorePipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexExecutionStorePipeline.scala deleted file mode 100644 index 89613614..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIexExecutionStorePipeline.scala +++ /dev/null @@ -1,406 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Valid, log2Ceil} - -import linxcore.lsu.{MDBConflictStoreProbe, STQEntryBankRow, - STQLoadForwardQuery, STQLoadForwardResponse, STQMemoryAttribute, - STQMemoryClassifyToken, STQRobCommitToken, STQSCBCommitBackend, - STQSerializedStoreRequest, STQSerializedStoreResponse} - -/** Canonical external boundary for the scalar/control execution cluster with - * its production store queue owner connected. - * - * Store reservation, STA, and STD are private connections. Recovery is - * published ready only when both IQ residency and the complete STQ/store - * projection can participate in the same common fire. - */ -class OooIexExecutionStorePipelineIO( - val p: OooParams, - val stqEntries: Int, - val storeCommitQueueEntries: Int, - val storeCommitIssueWidth: Int, - val scbEntries: Int) extends Bundle { - private val scbResponseTxnIdWidth = math.max(1, log2Ceil(scbEntries)) + 2 - private val storeCommitRequestCount = storeCommitIssueWidth * 2 - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryRejected = Output(Valid(new OooIexRecoveryReject(p))) - val recoveryFire = Input(Bool()) - - val issuePolicy = Input(new OooIexIssuePolicy(p)) - val stageCancels = Flipped(Vec(p.iexIssueDomainCount, - Vec(2, Decoupled(new OooIexStageCancel(p))))) - - val pcReadRequests = Output(Vec(p.pcReadPorts, - Valid(new OooIexPcReadPortRequest(p)))) - val pcReadResponses = Input(Vec(p.pcReadPorts, - Valid(UInt(p.pcWidth.W)))) - val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) - val fastWriteback = Flipped(Decoupled(new OooFastResolveWriteback(p))) - val fastWakeup = Flipped(Decoupled(new OooIexWakeup(p))) - val tClear = Flipped(Vec(p.tuAllocationWidth, - Valid(new OooIexLocalFileKey(p)))) - val uClear = Flipped(Vec(p.tuAllocationWidth, - Valid(new OooIexLocalFileKey(p)))) - - val multiCycleAlu = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val system = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val pointerAuth = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val floatingVector = Decoupled(new OooIexExecuteTransaction(p)) - val engineCommand = Decoupled(new OooIexExecuteTransaction(p)) - val memoryRequest = Vec(3, Decoupled(new OooIexLoadMemoryRequest(p))) - val memoryResponse = Flipped(Vec(3, - Decoupled(new OooIexLoadMemoryResponse(p)))) - val loadCancel = Output(Vec(p.iexLoadCancelPorts, - Valid(new OooIexLoadCancel(p)))) - val stqLoadForwardQuery = Flipped(Vec(3, Decoupled( - new STQLoadForwardQuery( - p.robGroupsPerStid, stidWidth = p.stidWidth, - lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth)))) - val stqLoadForwardResponse = Vec(3, Decoupled( - new STQLoadForwardResponse( - p.robGroupsPerStid, stqEntries, stidWidth = p.stidWidth, - lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth))) - val stqLoadForwardOccupied = Output(UInt(3.W)) - val lateStaProbe = Output(Valid(new MDBConflictStoreProbe( - p.robGroupsPerStid, peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, tidWidth = p.stidWidth, - sizeWidth = 7, lsidWidth = p.lsidWidth))) - - val bctrl = Vec(p.iexTerminalWidth, - Decoupled(new OooIexTerminalBctrl(p))) - val trace = Vec(p.iexTerminalWidth, - Decoupled(new OooIexTerminalTrace(p))) - val completion = Vec(p.iexTerminalWidth, - Decoupled(new OooRobMemberCompletion(p))) - - val robStoreCommit = Flipped(Decoupled(new STQRobCommitToken( - p.robGroupsPerStid, p.lsidWidth, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth))) - val memoryClassify = Flipped(Decoupled(new STQMemoryClassifyToken( - stqEntries, p.robGroupsPerStid, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth, - p.executeSlotGenerationWidth))) - val storeCommitIssueEnable = Input(Bool()) - val storeEvictEnable = Input(Bool()) - val storeDcacheReady = Input(Bool()) - val storeDcacheWriteHit = Input(Bool()) - val storeDcacheTagHit = Input(Bool()) - val storeL2RequestReady = Input(Bool()) - val storeRawRespValid = Input(Bool()) - val storeRawRespTxnId = Input(UInt(scbResponseTxnIdWidth.W)) - val storeRawRespWrite = Input(Bool()) - val storeRawRespUpgrade = Input(Bool()) - val storeRawRespReady = Output(Bool()) - val serializedStoreRequest = Decoupled(new STQSerializedStoreRequest( - stqEntries, p.robGroupsPerStid, lsidWidth = p.lsidWidth, - peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth)) - val serializedStoreResponse = Flipped(Decoupled( - new STQSerializedStoreResponse())) - - val robStoreCommitAccepted = Output(Bool()) - val robStoreCommitMissing = Output(Bool()) - val robStoreCommitMultiple = Output(Bool()) - val robStoreCommitNotReady = Output(Bool()) - val robStoreCommitClassificationMissing = Output(Bool()) - val robStoreCommitClassificationFault = Output(Bool()) - val memoryClassifyAccepted = Output(Bool()) - val memoryClassifyMissing = Output(Bool()) - val memoryClassifyMultiple = Output(Bool()) - val memoryClassifyDuplicate = Output(Bool()) - val memoryClassifyConflict = Output(Bool()) - val memoryClassifyMalformed = Output(Bool()) - val stqMemoryAttributes = Output(Vec(stqEntries, - new STQMemoryAttribute)) - val storeCommitQueueCount = Output(UInt( - log2Ceil(storeCommitQueueEntries + 1).W)) - val storeCommitDrainIssueCount = Output(UInt( - log2Ceil(storeCommitIssueWidth + 1).W)) - val storeScbAcceptedMask = Output(UInt(storeCommitRequestCount.W)) - val storeScbValidMask = Output(UInt(scbEntries.W)) - val storeLogicalCompletionCount = Output(UInt( - log2Ceil(storeCommitIssueWidth + 1).W)) - val serializedStoreBusy = Output(Bool()) - val storeCommitProtocolError = Output(Bool()) - - val stqRows = Output(Vec(stqEntries, new STQEntryBankRow( - p.robGroupsPerStid, - peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, - tidWidth = p.stidWidth, - mapQDepth = p.tuMapQDepthPerStid, - lsidWidth = p.lsidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth))) - val stqOccupiedMask = Output(UInt(stqEntries.W)) - val stqAddressReadyMask = Output(UInt(stqEntries.W)) - val stqDataReadyMask = Output(UInt(stqEntries.W)) - val stqResidentCount = Output(UInt(log2Ceil(stqEntries + 1).W)) - val storePipelinesOccupied = Output(UInt(2.W)) - val storeReserveAccepted = Output(Bool()) - val storeReserveRejected = Output(Bool()) - val storeLeaseLookupRejected = Output(Vec(4, Bool())) - val storeFillConflict = Output(Bool()) - val storeRecoveryFreeMask = Output(UInt(stqEntries.W)) - val storeRecoveryBlockedMask = Output(UInt(stqEntries.W)) - val storeRecoveryPartialCut = Output(Bool()) - - val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) - val transferFireMask = Output(UInt(p.iexReleaseWidth.W)) - val pWriteFire = Output(Vec(p.iexPWritePorts, Bool())) - val tWriteFire = Output(Vec(p.iexTWritePorts, Bool())) - val uWriteFire = Output(Vec(p.iexUWritePorts, Bool())) - val routeRejected = Output(Vec( - OooIexLinxPhysicalProfile.ExecutionLaneCount, - Valid(new OooIexExecutionRouteReject(p)))) - val terminalRejected = Output(Vec(p.iexTerminalWidth, - Vec(3, Valid(new OooIexTerminalReject(p))))) - val boundEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val residentEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val inFlightEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val issueEmpty = Output(Bool()) - val executionEmpty = Output(Bool()) - val storeEmpty = Output(Bool()) - val empty = Output(Bool()) - val pProtocolError = Output(Bool()) - val localProtocolError = Output(Bool()) -} - -class OooIexExecutionStoreRecoveryJoinIO(val p: OooParams) extends Bundle { - val requested = Input(Valid(new OooResidencyRecoveryPlan(p))) - val executionReady = Input(Bool()) - val executionPrepared = Input(new OooIexRecoveryPrepared(p)) - val executionRejected = Input(Valid(new OooIexRecoveryReject(p))) - val storeReady = Input(Bool()) - val storeRejected = Input(Bool()) - val fire = Input(Bool()) - - val prepareReady = Output(Bool()) - val prepared = Output(new OooIexRecoveryPrepared(p)) - val rejected = Output(Valid(new OooIexRecoveryReject(p))) - val commonFire = Output(Bool()) -} - -/** Stateless rendezvous for the issue/execution and STQ/store recovery - * projections. Neither owner sees an apply edge until both have prepared the - * same held request. - */ -class OooIexExecutionStoreRecoveryJoin(val p: OooParams) extends Module { - val io = IO(new OooIexExecutionStoreRecoveryJoinIO(p)) - - io.prepareReady := io.requested.valid && io.executionReady && - io.executionPrepared.valid && io.storeReady - io.prepared := io.executionPrepared - io.prepared.valid := io.prepareReady - io.commonFire := io.fire && io.prepareReady - - io.rejected := io.executionRejected - when(!io.executionRejected.valid && io.requested.valid && io.storeRejected) { - io.rejected.valid := true.B - io.rejected.bits.requested := io.requested.bits - io.rejected.bits.stidInRange := - io.requested.bits.oldHead.stid < p.stidCount.U - io.rejected.bits.residentRowsExact := false.B - io.rejected.bits.s1RowsExact := true.B - } -} - -class OooIexExecutionStorePipeline( - val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile(), - val stqEntries: Int = 16, - val storeCommitQueueEntries: Int = 16, - val storeCommitIssueWidth: Int = 2, - val scbEntries: Int = 16, - val scbResponseBufferDepth: Int = 4, - val storeLineBytes: Int = 64) extends Module { - val p = profile.params - val io = IO(new OooIexExecutionStorePipelineIO( - p, stqEntries, storeCommitQueueEntries, storeCommitIssueWidth, - scbEntries)) - - val execution = Module(new OooIexExecutionPipeline( - profile, requireStoreReservation = true)) - val store = Module(new OooIexStoreStqFabric(p, stqEntries)) - val storeCommit = Module(new STQSCBCommitBackend( - entries = stqEntries, - queueEntries = storeCommitQueueEntries, - issueWidth = storeCommitIssueWidth, - scbEntries = scbEntries, - scbResponseBufferDepth = scbResponseBufferDepth, - lineBytes = storeLineBytes, - mapQDepth = p.tuMapQDepthPerStid, - robEntries = p.robGroupsPerStid, - lsidWidth = p.lsidWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, - tidWidth = p.stidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth)) - - execution.io.s1 <> io.s1 - io.dispatchReleases <> execution.io.dispatchReleases - execution.io.ptagRecycle <> io.ptagRecycle - execution.io.issuePolicy := io.issuePolicy - execution.io.stageCancels <> io.stageCancels - io.pcReadRequests := execution.io.pcReadRequests - execution.io.pcReadResponses := io.pcReadResponses - execution.io.pInit := io.pInit - execution.io.pClear := io.pClear - execution.io.fastWriteback <> io.fastWriteback - execution.io.fastWakeup <> io.fastWakeup - execution.io.tClear := io.tClear - execution.io.uClear := io.uClear - - execution.io.storeReserve.get <> store.io.reserve - store.io.storeAddress <> execution.io.storeAddress - store.io.storeData <> execution.io.storeData - store.io.loadCancel := execution.io.loadCancel - store.io.loadForwardQuery <> io.stqLoadForwardQuery - io.stqLoadForwardResponse <> store.io.loadForwardResponse - io.stqLoadForwardOccupied := store.io.loadForwardOccupied - io.lateStaProbe := store.io.lateStaProbe - - execution.io.recoveryPrepare := io.recoveryPrepare - store.io.recoveryPrepare := io.recoveryPrepare - val recoveryJoin = Module(new OooIexExecutionStoreRecoveryJoin(p)) - recoveryJoin.io.requested := io.recoveryPrepare - recoveryJoin.io.executionReady := execution.io.recoveryPrepareReady - recoveryJoin.io.executionPrepared := execution.io.recoveryPrepared - recoveryJoin.io.executionRejected := execution.io.recoveryRejected - recoveryJoin.io.storeReady := store.io.recoveryPrepareReady - recoveryJoin.io.storeRejected := store.io.recoveryRejected - recoveryJoin.io.fire := io.recoveryFire - io.recoveryPrepareReady := recoveryJoin.io.prepareReady - io.recoveryPrepared := recoveryJoin.io.prepared - io.recoveryRejected := recoveryJoin.io.rejected - execution.io.recoveryFire := recoveryJoin.io.commonFire - store.io.recoveryFire := recoveryJoin.io.commonFire - - for (index <- 0 until 2) { - io.multiCycleAlu(index) <> execution.io.multiCycleAlu(index) - io.system(index) <> execution.io.system(index) - io.pointerAuth(index) <> execution.io.pointerAuth(index) - } - io.floatingVector <> execution.io.floatingVector - io.engineCommand <> execution.io.engineCommand - for (index <- 0 until 3) { - io.memoryRequest(index) <> execution.io.memoryRequest(index) - execution.io.memoryResponse(index) <> io.memoryResponse(index) - } - io.loadCancel := execution.io.loadCancel - for (lane <- 0 until p.iexTerminalWidth) { - io.bctrl(lane) <> execution.io.bctrl(lane) - io.trace(lane) <> execution.io.trace(lane) - io.completion(lane) <> execution.io.completion(lane) - } - - storeCommit.io.rows := store.io.rows - storeCommit.io.recoveryActive := io.recoveryPrepare.valid - storeCommit.io.robStoreCommit <> io.robStoreCommit - storeCommit.io.memoryClassify <> io.memoryClassify - store.io.markCommitValid := storeCommit.io.markCommitValid - store.io.markCommitIndex := storeCommit.io.markCommitIndex - storeCommit.io.markCommitAccepted := store.io.markCommitAccepted - store.io.commitFreeMaskValid := storeCommit.io.commitFreeMaskValid - store.io.commitFreeMask := storeCommit.io.commitFreeMask - storeCommit.io.commitFreeAcceptedMask := store.io.commitFreeAcceptedMask - storeCommit.io.issueEnable := io.storeCommitIssueEnable - storeCommit.io.evictEnable := io.storeEvictEnable - storeCommit.io.dcacheReady := io.storeDcacheReady - storeCommit.io.dcacheWriteHit := io.storeDcacheWriteHit - storeCommit.io.dcacheTagHit := io.storeDcacheTagHit - storeCommit.io.l2RequestReady := io.storeL2RequestReady - storeCommit.io.rawRespValid := io.storeRawRespValid - storeCommit.io.rawRespTxnId := io.storeRawRespTxnId - storeCommit.io.rawRespWrite := io.storeRawRespWrite - storeCommit.io.rawRespUpgrade := io.storeRawRespUpgrade - io.storeRawRespReady := storeCommit.io.rawRespReady - io.serializedStoreRequest <> storeCommit.io.serializedRequest - storeCommit.io.serializedResponse <> io.serializedStoreResponse - - io.robStoreCommitAccepted := storeCommit.io.robStoreCommitAccepted - io.robStoreCommitMissing := storeCommit.io.robStoreCommitMissing - io.robStoreCommitMultiple := storeCommit.io.robStoreCommitMultiple - io.robStoreCommitNotReady := storeCommit.io.robStoreCommitNotReady - io.robStoreCommitClassificationMissing := - storeCommit.io.robStoreCommitClassificationMissing - io.robStoreCommitClassificationFault := - storeCommit.io.robStoreCommitClassificationFault - io.memoryClassifyAccepted := storeCommit.io.memoryClassifyAccepted - io.memoryClassifyMissing := storeCommit.io.memoryClassifyMissing - io.memoryClassifyMultiple := storeCommit.io.memoryClassifyMultiple - io.memoryClassifyDuplicate := storeCommit.io.memoryClassifyDuplicate - io.memoryClassifyConflict := storeCommit.io.memoryClassifyConflict - io.memoryClassifyMalformed := storeCommit.io.memoryClassifyMalformed - io.stqMemoryAttributes := storeCommit.io.memoryAttributes - io.storeCommitQueueCount := storeCommit.io.drainQueueCount - io.storeCommitDrainIssueCount := storeCommit.io.drainIssueCount - io.storeScbAcceptedMask := storeCommit.io.scbAcceptedMask - io.storeScbValidMask := storeCommit.io.scbValidMask - io.storeLogicalCompletionCount := storeCommit.io.logicalCompletionCount - io.serializedStoreBusy := storeCommit.io.serializedBusy - io.storeCommitProtocolError := storeCommit.io.protocolError - - io.stqRows := store.io.rows - io.stqOccupiedMask := store.io.occupiedMask - io.stqAddressReadyMask := store.io.addrReadyMask - io.stqDataReadyMask := store.io.dataReadyMask - io.stqResidentCount := store.io.residentCount - io.storePipelinesOccupied := store.io.storePipelinesOccupied - io.storeReserveAccepted := store.io.reserveAccepted - io.storeReserveRejected := store.io.reserveRejected - io.storeLeaseLookupRejected := store.io.leaseLookupRejected - io.storeFillConflict := store.io.fillConflict - io.storeRecoveryFreeMask := store.io.recoveryFreeMask - io.storeRecoveryBlockedMask := store.io.recoveryBlockedMask - io.storeRecoveryPartialCut := store.io.recoveryPartialStoreCut - - io.terminalFireMask := execution.io.terminalFireMask - io.transferFireMask := execution.io.transferFireMask - io.pWriteFire := execution.io.pWriteFire - io.tWriteFire := execution.io.tWriteFire - io.uWriteFire := execution.io.uWriteFire - io.routeRejected := execution.io.routeRejected - io.terminalRejected := execution.io.terminalRejected - io.boundEntries := execution.io.boundEntries - io.residentEntries := execution.io.residentEntries - io.inFlightEntries := execution.io.inFlightEntries - io.issueEmpty := execution.io.issueEmpty - io.executionEmpty := execution.io.executionEmpty - io.storeEmpty := store.io.empty && storeCommit.io.empty - io.empty := execution.io.empty && store.io.empty && storeCommit.io.empty - io.pProtocolError := execution.io.pProtocolError - io.localProtocolError := execution.io.localProtocolError - - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && recoveryJoin.io.prepareReady, - "execution/store recovery needs one common prepared owner set") - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala b/chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala index 9cb2f414..74ff11d0 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala @@ -1,41 +1,44 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, Mux1H, OHToUInt, PopCount, PriorityEncoder, +import chisel3.util.{Decoupled, MuxLookup, PopCount, PriorityEncoder, PriorityEncoderOH, UIntToOH, Valid, log2Ceil} -import linxcore.common.{DestinationKind, OperandClass} +import linxcore.common.{BoundaryKind, DestinationKind, OperandClass} +import linxcore.params.CoreParams +import linxcore.top.interface.{DispatchTxn, MemoryAddressMode, MemoryIndexMode, + OperandKind, PredictionKind, RecoveryPhase, RecoveryPlan, + RecoveryPlanContract, RecoveryTargetIO, RobIdentity, StoreDispatchTxn, + UopClass} object OooIexIssueSlotState extends ChiselEnum { val Free, BoundS2, ResidentS3 = Value } object OooIexRecoveryScanState extends ChiselEnum { - val Idle, Scan, Prepared, Rejected = Value + val Idle, Scan, Prepared = Value } -class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) - val storeReserve = Decoupled(new OooIexIssueRow(p)) +class OooIexIssueIO( + val core: CoreParams, + val p: OooParams) + extends Bundle { + def this(core: CoreParams) = + this(core, OooIexPhysicalProfile.fromCoreParams(core).params) + val dispatch = Flipped(new OOODispatchChannels(core)) + val storeReserve = Vec(core.iex.stdPipes, + Decoupled(new OooIexIssueRow(p))) + val operandReadyBits = Input(new OooIexOperandReadyBits(p)) val wakeup = Input(Vec(p.iexWakeupPorts, Valid(new OooIexWakeup(p)))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) - + val loadCancelRetries = Input(Vec(p.iexIssueDomainCount, + Vec(OooIexP1I2Lane.LoadCancelStageCount, + Valid(new OooIexReadRepick(p))))) val releases = Flipped(Vec(p.iexReleaseWidth, Decoupled(new OooIexIssueRelease(p)))) def release = releases(0) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - def dispatchRelease = dispatchReleases(0) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - val recoveryApplied = Valid(new OooResidencyRecoveryPlan(p)) - val recoveryBusy = Output(Bool()) - // Every PTag return must invalidate the generation-qualified ready record - // before the freelist can recycle that token. - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) + val recovery = Flipped(new RecoveryTargetIO(core)) + val acceptedRecoveryApply = Valid(new RecoveryPlan(core)) val queries = Input(Vec(p.iexIssueDomainCount, new OooIexSlotQuery(p))) @@ -44,10 +47,6 @@ class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { val queryRows = Output(Vec(p.iexIssueDomainCount, new OooIexIssueRow(p))) val queryPickables = Output(Vec(p.iexIssueDomainCount, Bool())) - - // Each topology-neutral picker sees the same canonical IQ owner through a - // class/bank/capability projection. Capability-disjoint pickers may observe - // the same bank. The picker count changes bandwidth, never physical rows. val pickBankEnables = Input(Vec(p.iexIssueDomainCount, Vec(p.iqClassCount, UInt(p.iqBankCount.W)))) val issuePolicy = Input(new OooIexIssuePolicy(p)) @@ -61,8 +60,6 @@ class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { Valid(new OooIexPickClaimReject(p))) val pickRetryRejectedByDomain = Vec(p.iexIssueDomainCount, Valid(new OooIexPickRetryReject(p))) - val pickRecoveryCanceledByDomain = Vec(p.iexIssueDomainCount, - Valid(new OooIexPickToken(p))) val pickRecoveryBlockedByDomain = Vec(p.iexIssueDomainCount, Valid(new OooIexPickToken(p))) val pickPolicyBlockedByDomain = Vec(p.iexIssueDomainCount, @@ -73,8 +70,6 @@ class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { UInt(p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W))) - // Domain-zero aliases keep focused single-domain modules and regression - // tests source-compatible while the physical IO is explicitly vectorized. def query = queries(0) def queryState = queryStates(0) def queryRow = queryRows(0) @@ -85,14 +80,10 @@ class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { def pickMalformed = pickMalformedByDomain(0) def pickRejected = pickRejectedByDomain(0) def pickRetryRejected = pickRetryRejectedByDomain(0) - def pickRecoveryCanceled = pickRecoveryCanceledByDomain(0) def pickRecoveryBlocked = pickRecoveryBlockedByDomain(0) def pickPolicyBlocked = pickPolicyBlockedByDomain(0) def queryPolicyReason = queryPolicyReasons(0) - val s1Occupied = Output(Vec(p.stidCount, Bool())) - val s2Bind = Valid(new OooIexS2BindAck(p)) - val s3Enable = Valid(new OooIexS3Enable(p)) val boundEntries = Output(Vec(p.iqClassCount, Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) val residentEntries = Output(Vec(p.iqClassCount, @@ -102,54 +93,39 @@ class OooIexIssueIO(val p: OooParams = OooParams()) extends Bundle { val storeFrontierBlocked = Output(Vec(p.stidCount, UInt(p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W))) - - val s1Rejected = Valid(new OooIexS1Reject(p)) val releaseRejecteds = Vec(p.iexReleaseWidth, Valid(new OooIexReleaseReject(p))) def releaseRejected = releaseRejecteds(0) - val recoveryRejected = Valid(new OooIexRecoveryReject(p)) + val recoveryIdle = Output(Bool()) } -/** OOO-S1 to IEX-S3 residency owner. - * - * One retained S1 slot exists per STID. A fair shared S2 writer consumes at - * most one transaction per cycle, writes every exact dispatch child or none, - * and leaves the rows in `BoundS2` for a complete cycle. Only the following - * S3 transition makes a row eligible for a future picker. Source wakeups are - * registered into the row, so a wakeup observed in cycle N cannot affect an - * S3 eligibility decision in that same cycle. +/** Canonical Dispatch-to-IQ owner with retained S2/S3 residency. * - * One topology-neutral oldest-ready domain now claims canonical in-flight - * state before P1. Read denial/rejection returns that exact claim for retry. - * The release seam models only a later exact, non-cancellable I2 terminal - * event and joins physical row removal to the existing dispatch-reservation - * release handshake. + * Classed OOO channels allocate physical IQ rows directly. The compact + * schedule row and payload sidecar remain the unique issue state; the PTag + * Ready Bits view is sampled only on the accepted dispatch edge. Recovery + * scans exact ROB identities without reconstructing global age. */ class OooIexIssue( - val p: OooParams = OooParams(), - val domainCapabilities: Seq[BigInt] = Seq.empty, + val core: CoreParams, val requireStoreReservation: Boolean = false) extends Module { - private val effectiveDomainCapabilities = - if (domainCapabilities.isEmpty) Seq.fill(p.iexIssueDomainCount)( - OooIexDomainCapability.ValidMask) else domainCapabilities - require(effectiveDomainCapabilities.length == p.iexIssueDomainCount, - "IEX issue capability topology must define every physical domain") - require(effectiveDomainCapabilities.forall(mask => mask != 0 && - (mask & ~OooIexDomainCapability.ValidMask) == 0), - "IEX issue domains need nonempty declared capability masks") - val io = IO(new OooIexIssueIO(p)) - private val ttagIndexWidth = log2Ceil(p.tPhysRegs) - private val utagIndexWidth = log2Ceil(p.uPhysRegs) + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p = profile.params + OooRecoveryMembership.requireCompatible(p, core) + val io = IO(new OooIexIssueIO(core, p)) + + private val classWidth = math.max(1, log2Ceil(p.iqClassCount)) + private val physicalRowCount = + p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank + private val normalAdmissionCount = core.iex.aluPipes + core.iex.bruPipes + + core.iex.aguPipes + core.iex.systemMulticycleQueues + + core.iex.cmdIssueQueues + private val admissionCount = normalAdmissionCount + 2 * core.iex.stdPipes + private val admissionIndexWidth = math.max(1, log2Ceil(admissionCount)) val slotState = RegInit(VecInit(Seq.fill(p.iqClassCount)( VecInit(Seq.fill(p.iqBankCount)( VecInit(Seq.fill(p.iqEntriesPerBank)(OooIexIssueSlotState.Free))))))) - // S1 owns a pending physical-write claim before S2 installs the row. Keep - // this separate from slotState so queryState continues to describe physical - // IQ residency, while a second STID still cannot claim the same target. - val s1Claimed = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(false.B))))))) val scheduleRows = RegInit(VecInit(Seq.fill(p.iqClassCount)( VecInit(Seq.fill(p.iqBankCount)( VecInit(Seq.fill(p.iqEntriesPerBank)( @@ -158,997 +134,995 @@ class OooIexIssue( Vec(p.iqClassCount, Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, UInt(OooIexDomainCapability.Count.W)))))) - private val physicalDomainCapabilities = VecInit( - effectiveDomainCapabilities.map(_.U(OooIexDomainCapability.Count.W))) + val reservationEpoch = RegInit(VecInit(Seq.fill(p.iqClassCount)( + VecInit(Seq.fill(p.iqBankCount)( + VecInit(Seq.fill(p.iqEntriesPerBank)( + 0.U(p.reservationEpochWidth.W)))))))) + // These serials advance only on canonical Dispatch-to-IQ admission. They + // deliberately do not rewind on recovery: a canceled memory uop must never + // alias a later retained uop or load attempt. + private val memoryTransactionSerialWidth = + p.memoryTransactionGenerationWidth + p.memoryTransactionIdWidth + private val memoryTransactionSerial = + RegInit(0.U(memoryTransactionSerialWidth.W)) + private val initialLoadAttemptSerial = + RegInit(0.U(p.loadGenerationWidth.W)) val payloadRows = Seq.tabulate(p.iqClassCount, p.iqBankCount) { (_, _) => Mem(p.iqEntriesPerBank, new OooIexPayloadSidecar(p)) } - private val storeIssueClasses = Seq( - OooUopClass.Agu.asUInt.litValue.toInt, - OooUopClass.Std.asUInt.litValue.toInt) - private val storeIssuePhysicalRowCount = - storeIssueClasses.size * p.iqBankCount * p.iqEntriesPerBank - private def storePhysicalRowIndex( - storeClassIndex: Int, - bank: Int, - entry: Int): Int = - (storeClassIndex * p.iqBankCount + bank) * p.iqEntriesPerBank + entry - - val storeIssueFrontier = Module( - new OooIexStoreIssueFrontier(p, storeIssuePhysicalRowCount)) - val storeIssueAllowed = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, Bool())))) - for (uopClass <- 0 until p.iqClassCount; - bank <- 0 until p.iqBankCount; - entry <- 0 until p.iqEntriesPerBank) { - storeIssueAllowed(uopClass)(bank)(entry) := true.B - } - for ((uopClass, storeClassIndex) <- storeIssueClasses.zipWithIndex; - bank <- 0 until p.iqBankCount; - entry <- 0 until p.iqEntriesPerBank) { - val index = storePhysicalRowIndex(storeClassIndex, bank, entry) - val row = scheduleRows(uopClass)(bank)(entry) - val candidate = storeIssueFrontier.io.candidates(index) - candidate.resident := - slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.ResidentS3 && - row.valid - candidate.isStore := row.isStore - candidate.peId := row.peId - candidate.stid := row.stid - candidate.order := row.storeOrder - storeIssueAllowed(uopClass)(bank)(entry) := - storeIssueFrontier.io.allowed(index) - } - io.storeFrontierBlocked := storeIssueFrontier.io.blockedCount - - val s1Valid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val s1Rows = Reg(Vec(p.stidCount, new OooIexS1Transaction(p))) - val s1StoreReserved = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.decodedUopWidth.W)))) - val s2RoundRobin = RegInit(0.U(p.stidWidth.W)) - val storeReserveRoundRobin = RegInit(0.U(p.stidWidth.W)) - - val recoveryScanState = RegInit(OooIexRecoveryScanState.Idle) - val retainedRecoveryPlan = RegInit( - 0.U.asTypeOf(new OooResidencyRecoveryPlan(p))) - val recoveryScanCursor = RegInit(0.U(p.iexRecoveryScanCursorWidth.W)) - val recoveryRowKillMask = RegInit(VecInit(Seq.fill(p.iqClassCount)( - VecInit(Seq.fill(p.iqBankCount)( - VecInit(Seq.fill(p.iqEntriesPerBank)(false.B))))))) - val retainedRecoveryS1KillMask = RegInit(0.U(p.dispatchWidth.W)) - val retainedRecoveryS1RowsExact = RegInit(false.B) - val retainedRecoveryBoundKilled = RegInit(0.U( - p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W)) - val retainedRecoveryResidentKilled = RegInit(0.U( - p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W)) - val retainedRecoveryS3SeenMask = RegInit(0.U(p.dispatchWidth.W)) - val retainedRecoveryS3KillMask = RegInit(0.U(p.dispatchWidth.W)) - val retainedRecoveryPReadyKillMask = RegInit(0.U(p.pPhysRegs.W)) - val retainedRecoveryTReadyKillMask = RegInit(0.U(p.tPhysRegs.W)) - val retainedRecoveryUReadyKillMask = RegInit(0.U(p.uPhysRegs.W)) - - val recoveryPlan = Mux( - recoveryScanState === OooIexRecoveryScanState.Idle, - io.recoveryPrepare.bits, - retainedRecoveryPlan) - val recoveryStid = recoveryPlan.oldHead.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryOfferExact = io.recoveryPrepare.valid && - io.recoveryPrepare.bits.asUInt === recoveryPlan.asUInt - val recoveryFreeze = recoveryPlan.valid && recoveryStidInRange && - (io.recoveryPrepare.valid || - recoveryScanState =/= OooIexRecoveryScanState.Idle) - io.recoveryApplied.valid := io.recoveryFire && io.recoveryPrepareReady - io.recoveryApplied.bits := recoveryPlan - io.recoveryBusy := recoveryScanState =/= OooIexRecoveryScanState.Idle - // A wakeup must remain visible to consumers dispatched after that producer - // completed. These generation-qualified scoreboards complement per-row - // ready bits; without them, a consumer arriving after the one-cycle wakeup - // pulse could remain blocked forever. - val pReadyValid = RegInit(VecInit(Seq.fill(p.pPhysRegs)(false.B))) - val pReadyGeneration = Reg(Vec(p.pPhysRegs, - UInt(p.pTagGenerationWidth.W))) - val pReadyStid = Reg(Vec(p.pPhysRegs, UInt(p.stidWidth.W))) - val pReadyEpoch = Reg(Vec(p.pPhysRegs, UInt(p.epochWidth.W))) - // The global P-ready scoreboard may be recycled and rewritten by a peer - // while a target-STID recovery scan is retained. Snapshot the complete - // owner identity at capture so the scan never follows mutable scoreboard - // state, then revalidate the same identity again at common apply. - val retainedRecoveryPReadyValid = RegInit( - VecInit(Seq.fill(p.pPhysRegs)(false.B))) - val retainedRecoveryPReadyGeneration = RegInit(VecInit( - Seq.fill(p.pPhysRegs)(0.U(p.pTagGenerationWidth.W)))) - val retainedRecoveryPReadyStid = RegInit(VecInit( - Seq.fill(p.pPhysRegs)(0.U(p.stidWidth.W)))) - val retainedRecoveryPReadyEpoch = RegInit(VecInit( - Seq.fill(p.pPhysRegs)(0.U(p.epochWidth.W)))) - val tReadyValid = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.tPhysRegs)(false.B))))) - val tReadySequence = Reg(Vec(p.stidCount, - Vec(p.tPhysRegs, new OooLocalSeq(p)))) - val tReadyEpoch = Reg(Vec(p.stidCount, - Vec(p.tPhysRegs, UInt(p.epochWidth.W)))) - val uReadyValid = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.uPhysRegs)(false.B))))) - val uReadySequence = Reg(Vec(p.stidCount, - Vec(p.uPhysRegs, new OooLocalSeq(p)))) - val uReadyEpoch = Reg(Vec(p.stidCount, - Vec(p.uPhysRegs, UInt(p.epochWidth.W)))) + private def selectEntry[T <: Data](rows: Vec[T], index: UInt): T = + if (p.iqEntriesPerBank == 1) rows(0) else rows(index) - val recycleCountInRange = io.ptagRecycle.bits.count <= p.pTagReturnWidth.U - val recycleTokensExact = (0 until p.pTagReturnWidth).map { index => - val active = index.U < io.ptagRecycle.bits.count - val token = io.ptagRecycle.bits.tokens(index) - token.valid === active && (!active || token.ptag < p.pPhysRegs.U) - }.reduce(_ && _) - io.ptagRecycle.ready := recycleCountInRange && recycleTokensExact - - def sameMember(left: RobMemberKey, right: RobMemberKey): Bool = + private def sameMember(left: RobMemberKey, right: RobMemberKey): Bool = left.asUInt === right.asUInt - def sourceLoadCanceled( - row: OooIexScheduleRow, - source: OooIexSourceState): Bool = - io.loadCancel.map { cancel => - cancel.valid && cancel.bits.load.valid && source.valid && - source.specReady && source.load.valid && - cancel.bits.stid === row.stid && cancel.bits.epoch === row.epoch && - cancel.bits.load.asUInt === source.load.asUInt - }.reduce(_ || _) - - def rowLoadCanceled(row: OooIexScheduleRow): Bool = - row.sources.map(sourceLoadCanceled(row, _)).reduce(_ || _) - - def issuePolicyReasons( - domain: Int, - uopClass: OooUopClass.Type, - row: OooIexScheduleRow): UInt = { - val query = Wire(new OooIexIssueBlockQuery(p)) - query.uopClass := uopClass - query.stid := row.stid - query.isStore := row.isStore - OooIexIssueBlockMatrix.reasons(p, io.issuePolicy, domain, query) + private def privateMember(rob: RobIdentity): RobMemberKey = { + val member = Wire(new RobMemberKey(p)) + member.group.valid := true.B + member.group.peId := rob.peId + member.group.stid := rob.stid + member.group.ridSlot := rob.ridSlot + member.group.ridGeneration := rob.ridGeneration + member.bid.valid := true.B + member.bid.value := rob.bid + member.brobGeneration := rob.brobGeneration + member.memberIndex := rob.memberIndex + member.residentGeneration := rob.residentGeneration + member } - val request = io.s1.bits - val transaction = request.o3.request.reservation.transaction - val plan = transaction.plan - val decoded = transaction.decoded - val requestStid = plan.stid - val requestStidInRange = requestStid < p.stidCount.U - val safeRequestStid = Mux(requestStidInRange, requestStid, 0.U) - - val identityExact = request.pRename.valid && request.tuRename.valid && - request.dispatch.valid && request.pRename.peId === plan.peId && - request.tuRename.peId === plan.peId && request.dispatch.peId === plan.peId && - request.pRename.stid === plan.stid && request.tuRename.stid === plan.stid && - request.dispatch.stid === plan.stid && - request.pRename.epoch === plan.epoch && request.tuRename.epoch === plan.epoch && - request.dispatch.epoch === plan.epoch && - request.pRename.transactionId === plan.transactionId && - request.tuRename.transactionId === plan.transactionId && - request.dispatch.transactionId === plan.transactionId && - decoded.peId === plan.peId && decoded.stid === plan.stid && - decoded.epoch === plan.epoch && - request.pRename.uopMask === decoded.uopMask && - request.tuRename.uopMask === decoded.uopMask - val calculatedLoadIds = Wire(Vec(p.decodedUopWidth, - UInt(p.memoryDemandWidth.W))) - val calculatedStoreIds = Wire(Vec(p.decodedUopWidth, - UInt(p.memoryDemandWidth.W))) - val memoryOrderUopExact = Wire(Vec(p.decodedUopWidth, Bool())) - val memoryOrderDecodeShapeExact = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val active = decoded.uopMask(uopIndex) - val uop = decoded.uops(uopIndex) - val requestCount = uop.recipe.memoryRequestCount - val typedMemory = uop.memory.valid && - (uop.memory.isLoad ^ uop.memory.isStore) - val memoryActive = active && uop.valid && uop.recipe.valid && - typedMemory && requestCount.orR - val loadActive = memoryActive && uop.memory.isLoad - val storeActive = memoryActive && uop.memory.isStore - val allocation = request.memoryOrder.uops(uopIndex) - val expectedBefore = if (uopIndex == 0) request.memoryOrder.before - else request.memoryOrder.uops(uopIndex - 1).after - - calculatedLoadIds(uopIndex) := Mux(loadActive, requestCount, 0.U) - calculatedStoreIds(uopIndex) := Mux(storeActive, requestCount, 0.U) - memoryOrderDecodeShapeExact(uopIndex) := !active || ( - uop.valid && uop.recipe.valid && - (requestCount.orR === typedMemory) && - requestCount <= p.maxMemoryRequestsPerInstruction.U) - memoryOrderUopExact(uopIndex) := - allocation.valid === active && - allocation.memoryValid === memoryActive && - allocation.isLoad === loadActive && - allocation.isStore === storeActive && - allocation.requestCount === Mux(memoryActive, requestCount, 0.U) && - allocation.before.asUInt === expectedBefore.asUInt && - allocation.firstLsid === allocation.before.lsid && - (!memoryActive || allocation.firstTypeId === Mux(loadActive, - allocation.before.loadId, allocation.before.storeId)) && - allocation.after.lsid === allocation.before.lsid + - Mux(memoryActive, requestCount, 0.U) && - allocation.after.loadId === allocation.before.loadId + - Mux(loadActive, requestCount, 0.U) && - allocation.after.storeId === allocation.before.storeId + - Mux(storeActive, requestCount, 0.U) + private def operandClass(kind: OperandKind.Type): OperandClass.Type = + MuxLookup(kind.asUInt, OperandClass.Invalid)(Seq( + OperandKind.Gpr.asUInt -> OperandClass.P, + OperandKind.T.asUInt -> OperandClass.T, + OperandKind.U.asUInt -> OperandClass.U)) + + private def destinationKind(kind: OperandKind.Type): DestinationKind.Type = + MuxLookup(kind.asUInt, DestinationKind.None)(Seq( + OperandKind.Gpr.asUInt -> DestinationKind.Gpr, + OperandKind.T.asUInt -> DestinationKind.T, + OperandKind.U.asUInt -> DestinationKind.U)) + + private def localSequence( + source: linxcore.top.interface.RenamedSource, + isT: Bool): OooLocalSeq = { + val sequence = Wire(new OooLocalSeq(p)) + sequence.valid := source.valid && (source.ttagValid || source.utagValid) + sequence.index := Mux(isT, source.tSeqIndex, source.uSeqIndex) + sequence.generation := Mux( + isT, source.tSeqGeneration, source.uSeqGeneration) + sequence } - val calculatedLoadTotal = calculatedLoadIds.reduce(_ +& _) - val calculatedStoreTotal = calculatedStoreIds.reduce(_ +& _) - val memoryOrderDemandExact = - calculatedLoadTotal === plan.demand.loadIds && - calculatedStoreTotal === plan.demand.storeIds && - plan.demand.loadIds === decoded.demand.loadIds && - plan.demand.storeIds === decoded.demand.storeIds - val memoryOrderRequired = calculatedLoadTotal.orR || - calculatedStoreTotal.orR - val memoryOrderIdentityExact = request.memoryOrder.valid && - request.memoryOrder.peId === plan.peId && - request.memoryOrder.stid === plan.stid && - request.memoryOrder.epoch === plan.epoch && - request.memoryOrder.transactionId === plan.transactionId && - request.memoryOrder.uopMask === decoded.uopMask - val memoryOrderLeaseExact = memoryOrderIdentityExact && - memoryOrderUopExact.asUInt.andR && - request.memoryOrder.after.asUInt === - request.memoryOrder.uops(p.decodedUopWidth - 1).after.asUInt - val memoryOrderExact = memoryOrderDemandExact && - memoryOrderDecodeShapeExact.asUInt.andR && Mux(request.memoryOrder.valid, - memoryOrderLeaseExact, !memoryOrderRequired) - val allocationShapeExact = (0 until p.dispatchWidth).map { lane => - val allocation = request.dispatch.allocations(lane) - request.dispatch.allocationMask(lane) === allocation.valid && - (!allocation.valid || allocation.reservation.valid) - }.reduce(_ && _) - val allocationDense = (1 until p.dispatchWidth).map { lane => - !request.dispatch.allocationMask(lane) || - request.dispatch.allocationMask(lane - 1) - }.foldLeft(true.B)(_ && _) + private def localDestinationSequence( + destination: linxcore.top.interface.RenamedDestination, + isT: Bool): OooLocalSeq = { + val sequence = Wire(new OooLocalSeq(p)) + sequence.valid := destination.valid && + (destination.ttagValid || destination.utagValid) + sequence.index := Mux(isT, + destination.tSeqIndex, destination.uSeqIndex) + sequence.generation := Mux(isT, + destination.tSeqGeneration, destination.uSeqGeneration) + sequence + } - val laneExact = Wire(Vec(p.dispatchWidth, Bool())) - val laneTargetFree = Wire(Vec(p.dispatchWidth, Bool())) - for (lane <- 0 until p.dispatchWidth) { - val allocation = request.dispatch.allocations(lane) - val reservation = allocation.reservation - val uopIndexInRange = allocation.uopIndex < p.decodedUopWidth.U - val safeUopIndex = Mux(uopIndexInRange, allocation.uopIndex, 0.U) - val decodedUop = decoded.uops(safeUopIndex) - val pUop = request.pRename.uops(safeUopIndex) - val tuUop = request.tuRename.uops(safeUopIndex) - val activeUop = decoded.uopMask(safeUopIndex) && - decodedUop.valid && pUop.valid && tuUop.valid - val memberEnd = pUop.member.memberIndex +& - allocation.childIndex - val classIndex = reservation.uopClass.asUInt - val classInRange = classIndex < p.iqClassCount.U - val bankInRange = reservation.bank < p.iqBankCount.U - val entryInRange = reservation.speculativeSlot < p.iqEntriesPerBank.U - val portInRange = reservation.writePort < p.iqWritePortsPerBank.U - val safeClass = Mux(classInRange, classIndex, 0.U) - val safeBank = Mux(bankInRange, reservation.bank, 0.U) - val safeEntry = Mux(entryInRange, reservation.speculativeSlot, 0.U) - val storeSplit = - decodedUop.recipe.lateSplitKind === OooLateSplitKind.StoreAddressData.U || - decodedUop.recipe.lateSplitKind === OooLateSplitKind.PairStoreAddressData.U - val storeChildClassExact = !storeSplit || - (allocation.childIndex === 0.U && - reservation.uopClass === OooUopClass.Agu) || - (allocation.childIndex === 1.U && - reservation.uopClass === OooUopClass.Std) - val memoryStore = decodedUop.memory.valid && - decodedUop.memory.isStore && !decodedUop.memory.isLoad - val storeClassExact = !memoryStore || - reservation.uopClass === OooUopClass.Agu || - reservation.uopClass === OooUopClass.Std - val requiredCapability = decodedUop.recipe - .dispatchCapabilities(safeClass) - val recipeCapabilityShapeExact = (0 until p.iqClassCount).map { - recipeClass => - val demand = decodedUop.recipe.dispatchDemand(recipeClass) - val capability = decodedUop.recipe.dispatchCapabilities(recipeClass) - demand.orR === capability.orR && PopCount(capability) <= 1.U - }.reduce(_ && _) - val capabilityShapeExact = - decodedUop.recipe.dispatchDemand(safeClass).orR && - requiredCapability.orR && PopCount(requiredCapability) === 1.U && - recipeCapabilityShapeExact - laneExact(lane) := !allocation.valid || (uopIndexInRange && activeUop && - classInRange && bankInRange && entryInRange && portInRange && - pUop.decoded.asUInt === decodedUop.asUInt && - sameMember(pUop.member, tuUop.member) && - storeChildClassExact && storeClassExact && capabilityShapeExact && - allocation.childIndex < decodedUop.plannedChildCount && - memberEnd < p.maxOrdinaryUopsPerGroup.U) - laneTargetFree(lane) := !allocation.valid || - (slotState(safeClass)(safeBank)(safeEntry) === - OooIexIssueSlotState.Free && - !s1Claimed(safeClass)(safeBank)(safeEntry)) + private def exactWakeup( + txn: DispatchTxn, + source: linxcore.top.interface.RenamedSource, + sourceClass: OperandClass.Type, + sequence: OooLocalSeq, + committed: Boolean): Bool = io.wakeup.map { wakeup => + val classExact = wakeup.bits.operandClass === sourceClass + val tagExact = Mux(sourceClass === OperandClass.P, + wakeup.bits.ptag === source.ptag && + wakeup.bits.ptagGeneration === source.pGeneration, + wakeup.bits.localTag === Mux(sourceClass === OperandClass.T, + source.ttag, source.utag) && + wakeup.bits.localSequence.asUInt === sequence.asUInt) + wakeup.valid && classExact && tagExact && + wakeup.bits.stid === txn.uop.decoded.rob.stid && + (sourceClass === OperandClass.P || + wakeup.bits.epoch === source.localEpoch) && + wakeup.bits.kind === (if (committed) OooIexWakeupKind.Committed + else OooIexWakeupKind.SpeculativeLoad) + }.reduce(_ || _) + + private def exactReady( + txn: DispatchTxn, + source: linxcore.top.interface.RenamedSource, + sourceClass: OperandClass.Type, + sequence: OooLocalSeq): Bool = { + def physicalIndex(value: UInt, entries: Int): UInt = { + val width = math.max(1, log2Ceil(entries)) + if (entries == 1) 0.U(width.W) else value(width - 1, 0) + } + def safePhysicalIndex(value: UInt, entries: Int, inRange: Bool): UInt = { + val width = math.max(1, log2Ceil(entries)) + Mux(inRange, physicalIndex(value, entries), 0.U(width.W)) + } + val stid = txn.uop.decoded.rob.stid + val stidInRange = stid < p.stidCount.U + val safeStid = safePhysicalIndex(stid, p.stidCount, stidInRange) + val ptagInRange = source.ptag < p.pPhysRegs.U + val safePtag = safePhysicalIndex(source.ptag, p.pPhysRegs, ptagInRange) + val ttagInRange = source.ttag < p.tPhysRegs.U + val safeTtag = safePhysicalIndex(source.ttag, p.tPhysRegs, ttagInRange) + val utagInRange = source.utag < p.uPhysRegs.U + val safeUtag = safePhysicalIndex(source.utag, p.uPhysRegs, utagInRange) + val pEntry = io.operandReadyBits.ptag(safePtag) + val tEntry = if (p.stidCount == 1) + io.operandReadyBits.ttag(0)(safeTtag) + else io.operandReadyBits.ttag(safeStid)(safeTtag) + val uEntry = if (p.stidCount == 1) + io.operandReadyBits.utag(0)(safeUtag) + else io.operandReadyBits.utag(safeStid)(safeUtag) + // A P mapping can remain live across frontend epochs. PTag generation + // is the exact reuse discriminator; T/U retain their block-local epoch. + val pExact = ptagInRange && pEntry.valid && pEntry.ready && + pEntry.stid === stid && + pEntry.generation === source.pGeneration + val tExact = stidInRange && ttagInRange && tEntry.allocated && + tEntry.ready && tEntry.epoch === source.localEpoch && + tEntry.sequence.asUInt === sequence.asUInt + val uExact = stidInRange && utagInRange && uEntry.allocated && + uEntry.ready && uEntry.epoch === source.localEpoch && + uEntry.sequence.asUInt === sequence.asUInt + MuxLookup(sourceClass.asUInt, false.B)(Seq( + OperandClass.P.asUInt -> pExact, + OperandClass.T.asUInt -> tExact, + OperandClass.U.asUInt -> uExact)) || + exactWakeup(txn, source, sourceClass, sequence, committed = true) } - val noDuplicateTargets = (0 until p.dispatchWidth).flatMap { left => - (left + 1 until p.dispatchWidth).map { right => - val a = request.dispatch.allocations(left) - val b = request.dispatch.allocations(right) - !a.valid || !b.valid || a.reservation.uopClass =/= b.reservation.uopClass || - a.reservation.bank =/= b.reservation.bank || - a.reservation.speculativeSlot =/= b.reservation.speculativeSlot + private def residentExactReady( + row: OooIexScheduleRow, + source: OooIexSourceState): Bool = { + def safeIndex(value: UInt, entries: Int, inRange: Bool): UInt = { + val width = math.max(1, log2Ceil(entries)) + val index = if (entries == 1) 0.U(width.W) else value(width - 1, 0) + Mux(inRange, index, 0.U(width.W)) } - }.foldLeft(true.B)(_ && _) + val stidInRange = row.stid < p.stidCount.U + val safeStid = safeIndex(row.stid, p.stidCount, stidInRange) + val ptagInRange = source.ptag < p.pPhysRegs.U + val safePtag = safeIndex(source.ptag, p.pPhysRegs, ptagInRange) + val localTag = source.localTag + val ttagInRange = localTag < p.tPhysRegs.U + val safeTtag = safeIndex(localTag, p.tPhysRegs, ttagInRange) + val utagInRange = localTag < p.uPhysRegs.U + val safeUtag = safeIndex(localTag, p.uPhysRegs, utagInRange) + val pEntry = io.operandReadyBits.ptag(safePtag) + val tEntry = if (p.stidCount == 1) + io.operandReadyBits.ttag(0)(safeTtag) + else io.operandReadyBits.ttag(safeStid)(safeTtag) + val uEntry = if (p.stidCount == 1) + io.operandReadyBits.utag(0)(safeUtag) + else io.operandReadyBits.utag(safeStid)(safeUtag) + val pExact = ptagInRange && pEntry.valid && pEntry.ready && + pEntry.stid === row.stid && + pEntry.generation === source.ptagGeneration + val tExact = stidInRange && ttagInRange && tEntry.allocated && + tEntry.ready && tEntry.epoch === source.localEpoch && + tEntry.sequence.asUInt === source.localSequence.asUInt + val uExact = stidInRange && utagInRange && uEntry.allocated && + uEntry.ready && uEntry.epoch === source.localEpoch && + uEntry.sequence.asUInt === source.localSequence.asUInt + MuxLookup(source.operandClass.asUInt, false.B)(Seq( + OperandClass.P.asUInt -> pExact, + OperandClass.T.asUInt -> tExact, + OperandClass.U.asUInt -> uExact)) + } - val storeReservationShapeExact = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val uop = decoded.uops(uopIndex) - val pUop = request.pRename.uops(uopIndex) - val memoryOrder = request.memoryOrder.uops(uopIndex) - val typedStore = decoded.uopMask(uopIndex) && uop.valid && - uop.memory.valid && uop.memory.isStore && !uop.memory.isLoad && - uop.recipe.memoryRequestCount.orR - val storeRecipeExact = uop.recipe.valid && - uop.recipe.disposition === OooOpcodeDisposition.Dispatch.U && - uop.recipe.sideEffectOwner === OooSideEffectOwner.Lsu.U && - (uop.recipe.recipeKind === OooOpcodeRecipeKind.ScalarStore.U || - uop.recipe.recipeKind === OooOpcodeRecipeKind.PairStore.U) && - (uop.recipe.lateSplitKind === OooLateSplitKind.StoreAddressData.U || - uop.recipe.lateSplitKind === - OooLateSplitKind.PairStoreAddressData.U) - val requestCountLegal = memoryOrder.requestCount === 1.U || - memoryOrder.requestCount === 2.U - val pairShapeExact = - (uop.recipe.recipeKind === OooOpcodeRecipeKind.PairStore.U) === - (memoryOrder.requestCount === 2.U) - val addressChildren = VecInit((0 until p.dispatchWidth).map { lane => - val allocation = request.dispatch.allocations(lane) - allocation.valid && allocation.uopIndex === uopIndex.U && - allocation.childIndex === 0.U && - allocation.reservation.valid && - allocation.reservation.uopClass === OooUopClass.Agu - }) - storeReservationShapeExact(uopIndex) := - !typedStore || (storeRecipeExact && requestCountLegal && - pairShapeExact && memoryOrder.valid && memoryOrder.memoryValid && - memoryOrder.isStore && !memoryOrder.isLoad && - pUop.member.group.valid && pUop.member.bid.valid && - PopCount(addressChildren) === 1.U) + private def sourceSelected( + txn: DispatchTxn, + sourceIndex: Int, + uopClass: OooUopClass.Type, + childIndex: UInt): Bool = { + val source = txn.uop.sources(sourceIndex) + val storeAddress = uopClass === OooUopClass.Agu && childIndex === 0.U + val storeData = uopClass === OooUopClass.Std && childIndex === 1.U + source.valid && Mux(storeAddress, + txn.uop.decoded.memory.addressSourceMask(sourceIndex), + Mux(storeData, + txn.uop.decoded.memory.dataSourceMask(sourceIndex), true.B)) } - val s1ShapeExact = requestStidInRange && identityExact && memoryOrderExact && - allocationShapeExact && allocationDense && laneExact.reduce(_ && _) && - noDuplicateTargets && - (!requireStoreReservation.B || storeReservationShapeExact.asUInt.andR) - val s1TargetsExact = laneTargetFree.reduce(_ && _) - io.s1.ready := !s1Valid(safeRequestStid) && s1ShapeExact && s1TargetsExact && - !(recoveryFreeze && requestStid === recoveryStid) - io.s1Rejected.valid := io.s1.valid && (!s1ShapeExact || !s1TargetsExact) - io.s1Rejected.bits.peId := plan.peId - io.s1Rejected.bits.stid := plan.stid - io.s1Rejected.bits.epoch := plan.epoch - io.s1Rejected.bits.transactionId := plan.transactionId - io.s1Rejected.bits.shapeExact := s1ShapeExact - io.s1Rejected.bits.targetsExact := s1TargetsExact + private def makeRow( + txn: DispatchTxn, + uopClass: OooUopClass.Type, + childIndex: UInt, + bank: UInt, + entry: UInt, + nextEpoch: UInt, + capability: UInt, + memoryTransaction: OooIexMemoryTransactionIdentity, + initialLoadAttemptGeneration: UInt): OooIexIssueRow = { + val row = Wire(new OooIexIssueRow(p)) + row := 0.U.asTypeOf(row) + val decoded = txn.uop.decoded + val instruction = decoded.instruction.parent + val member = privateMember(decoded.rob) + row.valid := true.B + row.peId := decoded.rob.peId + row.stid := decoded.rob.stid + row.epoch := instruction.identity.epoch + row.transactionId := txn.transactionId + row.memoryTransactionValid := decoded.memory.valid + row.memoryTransaction := Mux(decoded.memory.valid, memoryTransaction, + 0.U.asTypeOf(row.memoryTransaction)) + row.initialLoadAttemptValid := decoded.memory.valid && decoded.memory.isLoad + row.initialLoadAttemptGeneration := Mux( + row.initialLoadAttemptValid, initialLoadAttemptGeneration, 0.U) + row.dispatchLane := 0.U + row.uopIndex := decoded.rob.memberIndex + row.childIndex := childIndex + row.member := member + row.reservation.valid := true.B + row.reservation.uopClass := uopClass + row.reservation.bank := bank + row.reservation.writePort := 0.U + row.reservation.speculativeSlot := entry + row.reservation.reservationEpoch := nextEpoch + + row.uopKey.primaryParent.valid := true.B + row.uopKey.primaryParent.peId := instruction.identity.peId + row.uopKey.primaryParent.stid := instruction.identity.stid + row.uopKey.primaryParent.instructionId := instruction.identity.instructionId + row.uopKey.primaryParent.epoch := instruction.identity.epoch + row.uopKey.uopOrdinal := decoded.rob.memberIndex + row.uopKey.uopCount := 1.U + row.parentCount := 1.U + row.parentPcTokens(0).valid := txn.pcBufferIndexOffset.valid + row.parentPcTokens(0).index := txn.pcBufferIndexOffset.pcBufferIndex + row.parentPcTokens(0).byteOffset := txn.pcBufferIndexOffset.pcOffset + row.parentPcTokens(0).allocationEpoch := + txn.pcBufferIndexOffset.allocationEpoch + row.pcParentIndexValid := txn.pcBufferIndexOffset.valid + row.pcParentIndex := 0.U + row.primaryPrediction.valid := instruction.prediction.valid + row.primaryPrediction.predictionTag := instruction.prediction.predictionTag + row.primaryPrediction.transactionId := instruction.prediction.transactionId + row.primaryPrediction.fetchPacketUid := instruction.prediction.fetchPacketUid + row.primaryPrediction.fetchSeq := instruction.prediction.fetchSeq + row.primaryPrediction.requestPc := instruction.prediction.requestPc + row.primaryPrediction.taken := instruction.prediction.taken + row.primaryPrediction.branchPc := instruction.prediction.branchPc + row.primaryPrediction.target := instruction.prediction.target + row.primaryPrediction.fallthroughPc := instruction.prediction.fallthroughPc + row.primaryPrediction.kind := BoundaryKind.Fall + when(instruction.prediction.kind === PredictionKind.Conditional) { + row.primaryPrediction.kind := BoundaryKind.Cond + }.elsewhen(instruction.prediction.kind === PredictionKind.Call) { + row.primaryPrediction.kind := BoundaryKind.Call + }.elsewhen(instruction.prediction.kind === PredictionKind.Return) { + row.primaryPrediction.kind := BoundaryKind.Ret + }.elsewhen(instruction.prediction.kind === PredictionKind.Direct) { + row.primaryPrediction.kind := BoundaryKind.Direct + }.elsewhen(instruction.prediction.kind === PredictionKind.Indirect) { + row.primaryPrediction.kind := BoundaryKind.Ind + } + row.primaryPrediction.provider := instruction.prediction.provider + row.primaryPrediction.stage := instruction.prediction.stage + row.primaryPrediction.confidence := instruction.prediction.confidence + row.primaryPrediction.checkpointId := instruction.prediction.checkpointId + row.primaryPrediction.epoch := instruction.prediction.epoch + + row.boundary.start := decoded.blockStart + row.boundary.stop := decoded.blockStop + row.boundary.explicit := decoded.blockBoundary + row.opcode := decoded.opcode + row.recipe.valid := decoded.classification.valid + row.recipe.opcode := decoded.opcode + row.recipe.disposition := decoded.classification.disposition + row.recipe.recipeKind := decoded.classification.kind + row.recipe.uopCountMin := decoded.classification.uopCountMin + row.recipe.uopCountMax := decoded.classification.uopCountMax + row.recipe.complexBreak := decoded.classification.complexBreak + row.recipe.lateSplitKind := decoded.classification.splitKind + row.recipe.fusionHeadClass := decoded.classification.fusionHeadClass + row.recipe.fusionTailClass := decoded.classification.fusionTailClass + row.recipe.fastResolveClass := decoded.classification.fastResolveClass + row.recipe.implicitSourceMask := + decoded.classification.implicitSourceMask + row.recipe.implicitDestination := + decoded.classification.implicitDestination + row.recipe.sideEffectOwner := decoded.classification.sideEffectOwner + row.recipe.requiresTargetValidation := + decoded.classification.requiresTargetValidation + row.recipe.mayTrap := decoded.classification.mayTrap + row.recipe.mayTrapLate := decoded.classification.mayTrapLate + row.recipe.mayRedirect := decoded.classification.mayRedirect + row.recipe.nonspeculative := decoded.classification.nonspeculative + row.recipe.pcReadRequired := decoded.classification.pcReadRequired + row.recipe.pcReadClass := decoded.classification.pcReadClass + row.recipe.dispatchClass := decoded.classification.dispatchClass + row.recipe.dispatchWrites := decoded.classification.dispatchWrites + for (classIndex <- 0 until p.iqClassCount) { + row.recipe.dispatchDemand(classIndex) := + decoded.classification.dispatchDemand(classIndex) + row.recipe.dispatchCapabilities(classIndex) := + decoded.classification.executionPipeCapability(classIndex) + } + row.recipe.memoryRequestCount := + decoded.classification.memoryRequestCount + row.recipe.pSourceCount := decoded.classification.pSourceCount + row.recipe.pDestinationCount := decoded.classification.pDestinationCount + row.recipe.tAllocationCount := decoded.classification.tAllocationCount + row.recipe.uAllocationCount := decoded.classification.uAllocationCount + row.plannedChildCount := decoded.classification.uopCountMax + row.immediateValid := decoded.immediateValid + row.immediate := decoded.immediate + row.memory.valid := decoded.memory.valid + row.memory.isLoad := decoded.memory.isLoad + row.memory.isStore := decoded.memory.isStore + row.memory.addressMode := MuxLookup(decoded.memory.addressMode.asUInt, + OooMemoryAddressMode.None)(Seq( + MemoryAddressMode.BaseIndex.asUInt -> OooMemoryAddressMode.BaseIndex, + MemoryAddressMode.BaseOffset.asUInt -> OooMemoryAddressMode.BaseOffset, + MemoryAddressMode.PcOffset.asUInt -> OooMemoryAddressMode.PcOffset)) + row.memory.accessBytes := decoded.memory.accessBytes + row.memory.signExtend := decoded.memory.signExtend + row.memory.offset := decoded.memory.offset + row.memory.indexMode := MuxLookup(decoded.memory.indexMode.asUInt, + OooMemoryIndexMode.Identity)(Seq( + MemoryIndexMode.SignExtend32.asUInt -> OooMemoryIndexMode.SignExtend32, + MemoryIndexMode.ZeroExtend32.asUInt -> OooMemoryIndexMode.ZeroExtend32, + MemoryIndexMode.Negate.asUInt -> OooMemoryIndexMode.Negate)) + row.memory.indexShift := decoded.memory.indexShift + row.memory.addressSourceMask := decoded.memory.addressSourceMask + row.memory.dataSourceMask := decoded.memory.dataSourceMask + row.memory.writebackValid := decoded.memory.writebackValid + row.memory.writebackPreIndex := decoded.memory.writebackPreIndex + + row.memoryOrder.valid := decoded.valid + row.memoryOrder.memoryValid := decoded.memory.valid + row.memoryOrder.isLoad := decoded.memory.isLoad + row.memoryOrder.isStore := decoded.memory.isStore + row.memoryOrder.requestCount := txn.memoryOrder.requestCount + row.memoryOrder.firstLsid := txn.memoryOrder.firstLsid + row.memoryOrder.firstTypeId := Mux(decoded.memory.isLoad, + txn.memoryOrder.firstLid, txn.memoryOrder.firstSid) + row.memoryOrder.before.lsid := txn.memoryOrder.firstLsid + row.memoryOrder.before.loadId := txn.memoryOrder.firstLid + row.memoryOrder.before.storeId := txn.memoryOrder.firstSid + row.memoryOrder.before.youngestStoreLsidValid := txn.memoryOrder.yostValid + row.memoryOrder.before.youngestStoreLsid := txn.memoryOrder.yostLsid + row.memoryOrder.yostSid := txn.memoryOrder.yostSid + row.memoryOrder.yoldValid := txn.memoryOrder.yoldValid + row.memoryOrder.yoldLsid := txn.memoryOrder.yoldLsid + row.memoryOrder.yoldLid := txn.memoryOrder.yoldLid + row.memoryOrder.after := row.memoryOrder.before + row.memoryOrder.after.lsid := txn.memoryOrder.firstLsid + + txn.memoryOrder.requestCount + row.memoryOrder.after.loadId := txn.memoryOrder.firstLid + + Mux(decoded.memory.isLoad, txn.memoryOrder.requestCount, 0.U) + row.memoryOrder.after.storeId := txn.memoryOrder.firstSid + + Mux(decoded.memory.isStore, txn.memoryOrder.requestCount, 0.U) + when(decoded.memory.isStore && txn.memoryOrder.requestCount.orR) { + row.memoryOrder.after.youngestStoreLsidValid := true.B + row.memoryOrder.after.youngestStoreLsid := + txn.memoryOrder.firstLsid + txn.memoryOrder.requestCount - 1.U + } + row.isStore := decoded.memory.valid && decoded.memory.isStore + row.storeOrder.valid := row.isStore + row.storeOrder.logicalMember := member + row.storeOrder.firstLsid := txn.memoryOrder.firstLsid + row.storeOrder.firstStoreId := txn.memoryOrder.firstSid + row.storeOrder.requestCount := txn.memoryOrder.requestCount + row.preciseTrap := txn.trap.valid + row.trapCause := txn.trap.cause + row.blockLast := decoded.blockStop - when(io.s1.fire) { - s1Valid(safeRequestStid) := true.B - s1Rows(safeRequestStid) := request - s1StoreReserved(safeRequestStid) := 0.U - for (lane <- 0 until p.dispatchWidth) { - val allocation = request.dispatch.allocations(lane) - val reservation = allocation.reservation - when(allocation.valid) { - s1Claimed(reservation.uopClass.asUInt)(reservation.bank)( - reservation.speculativeSlot) := true.B + for (sourceIndex <- 0 until p.maxSourceOperands) { + val renamed = txn.uop.sources(sourceIndex) + val source = row.sources(sourceIndex) + val cls = operandClass(renamed.kind) + val isT = cls === OperandClass.T + val sequence = localSequence(renamed, isT) + val selected = sourceSelected(txn, sourceIndex, uopClass, childIndex) + val ready = exactReady(txn, renamed, cls, sequence) + val speculative = exactWakeup( + txn, renamed, cls, sequence, committed = false) + source.valid := selected + source.ready := !selected || ready + source.specReady := selected && !ready && speculative + source.operandClass := cls + source.ptag := renamed.ptag + source.ptagGeneration := renamed.pGeneration + source.localTag := Mux(isT, renamed.ttag, renamed.utag) + source.localSequence := sequence + source.localEpoch := renamed.localEpoch + source.load := 0.U.asTypeOf(source.load) + for (port <- 0 until p.iexWakeupPorts) { + when(source.specReady && io.wakeup(port).valid && + io.wakeup(port).bits.kind === OooIexWakeupKind.SpeculativeLoad && + io.wakeup(port).bits.operandClass === cls) { + source.load := io.wakeup(port).bits.load + } } } + for (destinationIndex <- 0 until p.maxDestinationOperands) { + val renamed = txn.uop.destinations(destinationIndex) + val destination = row.destinations(destinationIndex) + val isT = renamed.kind === OperandKind.T + val selected = renamed.valid && + !(decoded.memory.isStore && uopClass === OooUopClass.Std) + destination.valid := selected + destination.kind := destinationKind(renamed.kind) + destination.atag := renamed.atag + destination.relativeIndex := Mux(isT, + renamed.tSeqIndex, renamed.uSeqIndex) + destination.ptag := renamed.ptag + destination.ptagGeneration := renamed.pGeneration + destination.localTag := Mux(isT, renamed.ttag, renamed.utag) + destination.localSequence := localDestinationSequence(renamed, isT) + row.payload.previousPDestinations(destinationIndex).valid := selected && + renamed.kind === OperandKind.Gpr && renamed.previousPtagValid + row.payload.previousPDestinations(destinationIndex).ptag := + renamed.previousPtag + row.payload.previousPDestinations(destinationIndex).ptagGeneration := + renamed.previousPGeneration + } + row } - val storeReserveNeeds = Wire(Vec(p.stidCount, - UInt(p.decodedUopWidth.W))) - for (stid <- 0 until p.stidCount) { - val retained = s1Rows(stid) - val retainedDecoded = retained.o3.request.reservation.transaction.decoded - val needed = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val uop = retainedDecoded.uops(uopIndex) - val addressChildren = VecInit((0 until p.dispatchWidth).map { lane => - val allocation = retained.dispatch.allocations(lane) - allocation.valid && allocation.uopIndex === uopIndex.U && - allocation.childIndex === 0.U && - allocation.reservation.valid && - allocation.reservation.uopClass === OooUopClass.Agu - }) - needed(uopIndex) := s1Valid(stid) && retainedDecoded.uopMask(uopIndex) && - uop.valid && uop.memory.valid && uop.memory.isStore && - !uop.memory.isLoad && PopCount(addressChildren) === 1.U && - !s1StoreReserved(stid)(uopIndex) + val admissionValid = Wire(Vec(admissionCount, Bool())) + val admissionTxn = Wire(Vec(admissionCount, new DispatchTxn(core))) + val admissionClass = Wire(Vec(admissionCount, OooUopClass())) + val admissionChild = Wire(Vec(admissionCount, + UInt(math.max(1, log2Ceil(p.maxDispatchWritesPerInstruction)).W))) + val admissionCapability = Wire(Vec(admissionCount, + UInt(OooIexDomainCapability.Count.W))) + val admissionBankMask = Wire(Vec(admissionCount, UInt(p.iqBankCount.W))) + val admissionChannelExact = Wire(Vec(admissionCount, Bool())) + admissionValid.foreach(_ := false.B) + admissionTxn.foreach(_ := 0.U.asTypeOf(new DispatchTxn(core))) + admissionClass.foreach(_ := OooUopClass.Alu) + admissionChild.foreach(_ := 0.U) + admissionCapability.foreach(_ := 0.U) + admissionBankMask.foreach(_ := 0.U) + admissionChannelExact.foreach(_ := false.B) + + private def laneBankMask(lane: Int, laneCount: Int): BigInt = + (0 until p.iqBankCount).filter(_ % laneCount == lane).foldLeft(BigInt(0))( + (mask, bank) => mask | (BigInt(1) << bank)) + private val allBanks = ((BigInt(1) << p.iqBankCount) - 1) + private def txnIdentityExact(txn: DispatchTxn): Bool = + txn.uop.decoded.valid && + txn.uop.decoded.rob.stid < p.stidCount.U && + txn.uop.decoded.rob.peId === txn.uop.decoded.instruction.parent.identity.peId && + txn.uop.decoded.rob.stid === txn.uop.decoded.instruction.parent.identity.stid && + (!txn.uop.decoded.instruction.parent.prediction.valid || + txn.uop.decoded.instruction.parent.identity.epoch === + txn.uop.decoded.instruction.parent.prediction.epoch) + private def classificationExact( + txn: DispatchTxn, + uopClass: UopClass.Type, + dispatchClass: Int, + issueClass: Int, + capabilityMask: BigInt, + dispatchWrites: Int): Bool = { + val classification = txn.uop.decoded.classification + txnIdentityExact(txn) && txn.uop.decoded.uopClass === uopClass && + classification.valid && + classification.disposition === OooOpcodeDisposition.Dispatch.U && + classification.dispatchClass === dispatchClass.U && + classification.dispatchWrites === dispatchWrites.U && + classification.dispatchDemand(issueClass).orR && + (classification.executionPipeCapability(issueClass) & + capabilityMask.U).orR + } + private def loadMemoryExact(txn: DispatchTxn): Bool = { + val decoded = txn.uop.decoded + decoded.memory.valid && decoded.memory.isLoad && !decoded.memory.isStore && + decoded.memory.requestCount === 1.U && + decoded.classification.memoryRequestCount === 1.U && + txn.memoryOrder.requestCount === 1.U + } + private def storeMemoryExact(txn: DispatchTxn): Bool = { + val decoded = txn.uop.decoded + decoded.memory.valid && !decoded.memory.isLoad && decoded.memory.isStore && + decoded.memory.requestCount === 1.U && + decoded.classification.memoryRequestCount === 1.U && + txn.memoryOrder.requestCount === 1.U + } + private val systemCapabilityMask = OooIexDomainCapability.mask( + OooIexDomainCapability.MultiCycleAlu, + OooIexDomainCapability.System, + OooIexDomainCapability.PointerAuth) + private def systemClassificationExact(txn: DispatchTxn): Bool = { + val decoded = txn.uop.decoded + val classification = decoded.classification + val alu = decoded.uopClass === UopClass.Alu && + classification.dispatchClass === OooDispatchClass.Alu.U && + classification.dispatchDemand(OooDispatchClass.Alu - 1).orR && + (classification.executionPipeCapability(OooDispatchClass.Alu - 1) & + systemCapabilityMask.U).orR + val system = decoded.uopClass === UopClass.System && + classification.dispatchClass === OooDispatchClass.Sys.U && + classification.dispatchDemand(OooDispatchClass.Sys - 1).orR && + (classification.executionPipeCapability(OooDispatchClass.Sys - 1) & + systemCapabilityMask.U).orR + txnIdentityExact(txn) && classification.valid && + classification.disposition === OooOpcodeDisposition.Dispatch.U && + classification.dispatchWrites === 1.U && !decoded.memory.valid && + (alu || system) + } + + var admission = 0 + for (lane <- 0 until core.iex.aluPipes) { + val channel = io.dispatch.aluDispatch(lane) + admissionValid(admission) := channel.valid + admissionTxn(admission) := channel.bits + admissionClass(admission) := OooUopClass.Alu + admissionCapability(admission) := channel.bits.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Alu - 1) + admissionBankMask(admission) := allBanks.U + admissionChannelExact(admission) := classificationExact( + channel.bits, UopClass.Alu, OooDispatchClass.Alu, + OooDispatchClass.Alu - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu), 1) && + !channel.bits.uop.decoded.memory.valid + admission += 1 + } + for (lane <- 0 until core.iex.bruPipes) { + val channel = io.dispatch.bruDispatch(lane) + admissionValid(admission) := channel.valid + admissionTxn(admission) := channel.bits + admissionClass(admission) := OooUopClass.Bru + admissionCapability(admission) := channel.bits.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Bru - 1) + admissionBankMask(admission) := allBanks.U + admissionChannelExact(admission) := classificationExact( + channel.bits, UopClass.Bru, OooDispatchClass.Bru, + OooDispatchClass.Bru - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.Branch), 1) && + !channel.bits.uop.decoded.memory.valid + admission += 1 + } + for (lane <- 0 until core.iex.aguPipes) { + val channel = io.dispatch.aguDispatch(lane) + admissionValid(admission) := channel.valid + admissionTxn(admission) := channel.bits + admissionClass(admission) := OooUopClass.Agu + admissionCapability(admission) := channel.bits.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Agu - 1) + admissionBankMask(admission) := laneBankMask( + lane, core.iex.aguPipes).U + admissionChannelExact(admission) := classificationExact( + channel.bits, UopClass.Agu, OooDispatchClass.Agu, + OooDispatchClass.Agu - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress), 1) && + loadMemoryExact(channel.bits) + admission += 1 + } + val storeAdmissionBase = admission + for (lane <- 0 until core.iex.stdPipes) { + val channel = io.dispatch.storeDispatch(lane) + val address = admission + val data = admission + 1 + admissionValid(address) := channel.valid + admissionTxn(address) := channel.bits.sta + admissionClass(address) := OooUopClass.Agu + admissionChild(address) := 0.U + admissionCapability(address) := channel.bits.sta.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Agu - 1) + admissionBankMask(address) := VecInit((0 until p.iqBankCount).map { bank => + (bank % core.iex.aguPipes).U === channel.bits.aguPipe + }).asUInt + admissionValid(data) := channel.valid + admissionTxn(data) := channel.bits.std + admissionClass(data) := OooUopClass.Std + admissionChild(data) := 1.U + admissionCapability(data) := channel.bits.std.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Std - 1) + admissionBankMask(data) := VecInit((0 until p.iqBankCount).map { bank => + (bank % core.iex.stdPipes).U === channel.bits.stdPipe + }).asUInt + val pairExact = classificationExact(channel.bits.sta, UopClass.Std, + OooDispatchClass.Std, OooDispatchClass.Agu - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress), 2) && + classificationExact(channel.bits.std, UopClass.Std, + OooDispatchClass.Std, OooDispatchClass.Std - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.StoreData), 2) && + channel.bits.sta.uop.decoded.classification.splitKind =/= + OooLateSplitKind.None.U && + storeMemoryExact(channel.bits.sta) && + storeMemoryExact(channel.bits.std) && + channel.bits.sta.uop.decoded.memory.asUInt === + channel.bits.std.uop.decoded.memory.asUInt && + channel.bits.sta.transactionId === channel.bits.std.transactionId && + channel.bits.sta.uop.decoded.rob.asUInt === + channel.bits.std.uop.decoded.rob.asUInt && + channel.bits.sta.memoryOrder.asUInt === + channel.bits.std.memoryOrder.asUInt && + channel.bits.sta.pcBufferIndexOffset.asUInt === + channel.bits.std.pcBufferIndexOffset.asUInt + admissionChannelExact(address) := pairExact + admissionChannelExact(data) := pairExact + admission += 2 + } + for (lane <- 0 until core.iex.systemMulticycleQueues) { + val channel = io.dispatch.systemDispatch(lane) + admissionValid(admission) := channel.valid + admissionTxn(admission) := channel.bits + admissionClass(admission) := OooUopClass.Sys + admissionCapability(admission) := Mux( + channel.bits.uop.decoded.classification.dispatchClass === + OooDispatchClass.Alu.U, + channel.bits.uop.decoded.classification.executionPipeCapability( + OooDispatchClass.Alu - 1), + channel.bits.uop.decoded.classification.executionPipeCapability( + OooDispatchClass.Sys - 1)) + admissionBankMask(admission) := allBanks.U + admissionChannelExact(admission) := systemClassificationExact(channel.bits) + admission += 1 + } + for (lane <- 0 until core.iex.cmdIssueQueues) { + val channel = io.dispatch.cmdDispatch(lane) + admissionValid(admission) := channel.valid + admissionTxn(admission) := channel.bits + admissionClass(admission) := OooUopClass.Cmd + admissionCapability(admission) := channel.bits.uop.decoded.classification + .executionPipeCapability(OooDispatchClass.Cmd - 1) + admissionBankMask(admission) := allBanks.U + admissionChannelExact(admission) := classificationExact( + channel.bits, UopClass.Cmd, OooDispatchClass.Cmd, + OooDispatchClass.Cmd - 1, + OooIexDomainCapability.mask(OooIexDomainCapability.EngineCommand), 1) && + !channel.bits.uop.decoded.memory.valid + admission += 1 + } + require(admission == admissionCount) + + val selectedValid = Wire(Vec(admissionCount, Bool())) + val selectedBank = Wire(Vec(admissionCount, UInt(p.iqBankWidth.W))) + val selectedEntry = Wire(Vec(admissionCount, UInt(p.iqEntryWidth.W))) + for (index <- 0 until admissionCount) { + val candidates = Wire(Vec(p.iqBankCount * p.iqEntriesPerBank, Bool())) + for (bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank) { + val flat = bank * p.iqEntriesPerBank + entry + val claimedByOlder = (0 until index).map { older => + admissionValid(older) && selectedValid(older) && + admissionClass(older) === admissionClass(index) && + selectedBank(older) === bank.U && selectedEntry(older) === entry.U + }.foldLeft(false.B)(_ || _) + candidates(flat) := admissionBankMask(index)(bank) && + slotState(admissionClass(index).asUInt)(bank)(entry) === + OooIexIssueSlotState.Free && !claimedByOlder } - storeReserveNeeds(stid) := needed.asUInt + val selectedOH = PriorityEncoderOH(candidates.asUInt) + val selectedFlat = PriorityEncoder(candidates.asUInt) + selectedValid(index) := candidates.asUInt.orR + selectedBank(index) := selectedFlat / p.iqEntriesPerBank.U + selectedEntry(index) := selectedFlat % p.iqEntriesPerBank.U + assert(PopCount(selectedOH) <= 1.U, + "one dispatch child may select at most one physical IQ row") } - val storeReserveStidCandidates = Wire(Vec(p.stidCount, Bool())) - for (offset <- 0 until p.stidCount) { - val candidate = (storeReserveRoundRobin + offset.U)(p.stidWidth - 1, 0) - storeReserveStidCandidates(offset) := - requireStoreReservation.B && storeReserveNeeds(candidate).orR && - !(recoveryFreeze && candidate === recoveryStid) + val recoveryState = RegInit(OooIexRecoveryScanState.Idle) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val recoveryCursor = RegInit(0.U(p.iexRecoveryScanCursorWidth.W)) + val recoveryKillMask = RegInit(VecInit(Seq.fill(p.iqClassCount)( + VecInit(Seq.fill(p.iqBankCount)( + VecInit(Seq.fill(p.iqEntriesPerBank)(false.B))))))) + val prepareExact = + io.recovery.prepare.bits.phase === RecoveryPhase.Prepare && + io.recovery.prepare.bits.trigger.stid < p.stidCount.U && + RecoveryPlanContract.legalSuffixWindow(io.recovery.prepare.bits) + val preparing = io.recovery.prepare.valid && prepareExact + val recoveryTargetStid = Mux(recoveryState === OooIexRecoveryScanState.Idle, + io.recovery.prepare.bits.trigger.stid, retainedRecovery.trigger.stid) + val recoveryTargetActive = preparing || + recoveryState =/= OooIexRecoveryScanState.Idle + io.recoveryIdle := recoveryState === OooIexRecoveryScanState.Idle && + !io.recovery.prepare.valid + private def targetFenced(stid: UInt): Bool = + recoveryTargetActive && stid === recoveryTargetStid + + val admissionReady = Wire(Vec(admissionCount, Bool())) + for (index <- 0 until admissionCount) { + admissionReady(index) := selectedValid(index) && + admissionChannelExact(index) && + !targetFenced(admissionTxn(index).uop.decoded.rob.stid) } - val storeReserveStidOH = PriorityEncoderOH( - storeReserveStidCandidates.asUInt) - val storeReserveValid = storeReserveStidCandidates.asUInt.orR - val storeReserveStid = Mux(storeReserveValid, - (storeReserveRoundRobin + OHToUInt(storeReserveStidOH))( - p.stidWidth - 1, 0), 0.U) - val storeReserveUop = PriorityEncoder(storeReserveNeeds(storeReserveStid)) - val storeReserveS1 = s1Rows(storeReserveStid) - val storeReservePUop = storeReserveS1.pRename.uops(storeReserveUop) - val storeReserveTU = storeReserveS1.tuRename.uops(storeReserveUop) - val storeReserveAllocationHits = VecInit((0 until p.dispatchWidth).map { - lane => - val allocation = storeReserveS1.dispatch.allocations(lane) - allocation.valid && allocation.uopIndex === storeReserveUop && - allocation.childIndex === 0.U && allocation.reservation.valid && - allocation.reservation.uopClass === OooUopClass.Agu - }) - val storeReserveAllocation = Mux1H(storeReserveAllocationHits, - storeReserveS1.dispatch.allocations) - val storeReserveRow = Wire(new OooIexIssueRow(p)) - storeReserveRow := 0.U.asTypeOf(storeReserveRow) - storeReserveRow.valid := storeReserveValid - storeReserveRow.peId := storeReserveS1.dispatch.peId - storeReserveRow.stid := storeReserveS1.dispatch.stid - storeReserveRow.epoch := storeReserveS1.dispatch.epoch - storeReserveRow.transactionId := storeReserveS1.dispatch.transactionId - storeReserveRow.uopIndex := storeReserveUop - storeReserveRow.childIndex := 0.U - storeReserveRow.member := storeReservePUop.member - storeReserveRow.reservation := storeReserveAllocation.reservation - storeReserveRow.recipe := storeReservePUop.decoded.recipe - storeReserveRow.memory := storeReservePUop.decoded.memory - storeReserveRow.memoryOrder := - storeReserveS1.memoryOrder.uops(storeReserveUop) - storeReserveRow.blockLast := storeReserveTU.blockLast - storeReserveRow.closeBeforeValid := storeReserveTU.closeBeforeValid - storeReserveRow.closeBefore := storeReserveTU.closeBefore - io.storeReserve.valid := storeReserveValid - io.storeReserve.bits := storeReserveRow - if (!requireStoreReservation) { - io.storeReserve.valid := false.B - io.storeReserve.bits := 0.U.asTypeOf(io.storeReserve.bits) - } else { - when(io.storeReserve.fire) { - s1StoreReserved(storeReserveStid) := - s1StoreReserved(storeReserveStid) | UIntToOH( - storeReserveUop, p.decodedUopWidth) - storeReserveRoundRobin := Mux( - storeReserveStid === (p.stidCount - 1).U, - 0.U, storeReserveStid + 1.U) - } + val allPresentedAdmissionsReady = (0 until admissionCount).map { index => + !admissionValid(index) || admissionReady(index) + }.reduce(_ && _) + val commonDispatchReady = allPresentedAdmissionsReady && + io.dispatch.storeDispatch.indices.map { lane => + !requireStoreReservation.B || !io.dispatch.storeDispatch(lane).valid || + io.storeReserve(lane).ready + }.reduce(_ && _) + + var readyIndex = 0 + for (lane <- 0 until core.iex.aluPipes) { + io.dispatch.aluDispatch(lane).ready := commonDispatchReady + readyIndex += 1 + } + for (lane <- 0 until core.iex.bruPipes) { + io.dispatch.bruDispatch(lane).ready := commonDispatchReady + readyIndex += 1 + } + for (lane <- 0 until core.iex.aguPipes) { + io.dispatch.aguDispatch(lane).ready := commonDispatchReady + readyIndex += 1 } + for (lane <- 0 until core.iex.stdPipes) { + io.dispatch.storeDispatch(lane).ready := commonDispatchReady + readyIndex += 2 + } + for (lane <- 0 until core.iex.systemMulticycleQueues) { + io.dispatch.systemDispatch(lane).ready := commonDispatchReady + readyIndex += 1 + } + for (lane <- 0 until core.iex.cmdIssueQueues) { + io.dispatch.cmdDispatch(lane).ready := commonDispatchReady + readyIndex += 1 + } + require(readyIndex == admissionCount) - val s2OffsetCandidates = Wire(Vec(p.stidCount, Bool())) - val s3PendingValid = RegInit(false.B) - val s3Pending = Reg(new OooIexS3Enable(p)) - val s3PendingFrozen = recoveryFreeze && s3PendingValid && - s3Pending.bind.stid === recoveryStid - for (offset <- 0 until p.stidCount) { - val candidate = (s2RoundRobin + offset.U)(p.stidWidth - 1, 0) - val storeReservationsComplete = !requireStoreReservation.B || - !storeReserveNeeds(candidate).orR - s2OffsetCandidates(offset) := s1Valid(candidate) && - storeReservationsComplete && !s3PendingFrozen && - !(recoveryFreeze && candidate === recoveryStid) + val admissionFire = Wire(Vec(admissionCount, Bool())) + var fireIndex = 0 + for (lane <- 0 until core.iex.aluPipes) { + admissionFire(fireIndex) := io.dispatch.aluDispatch(lane).fire + fireIndex += 1 } - val s2OffsetSelect = PriorityEncoderOH(s2OffsetCandidates.asUInt) - val s2Valid = s2OffsetCandidates.asUInt.orR - val s2Stid = Mux(s2Valid, - (s2RoundRobin + OHToUInt(s2OffsetSelect))(p.stidWidth - 1, 0), 0.U) - val s2Request = s1Rows(s2Stid) - val s2Dispatch = s2Request.dispatch - val safeS2OwnerStid = Mux(s2Dispatch.stid < p.stidCount.U, - s2Dispatch.stid, 0.U) - val s2Ack = Wire(new OooIexS2BindAck(p)) - s2Ack.peId := s2Dispatch.peId - s2Ack.stid := s2Dispatch.stid - s2Ack.epoch := s2Dispatch.epoch - s2Ack.transactionId := s2Dispatch.transactionId - s2Ack.allocationMask := s2Dispatch.allocationMask - io.s2Bind.valid := s2Valid - io.s2Bind.bits := s2Ack + for (lane <- 0 until core.iex.bruPipes) { + admissionFire(fireIndex) := io.dispatch.bruDispatch(lane).fire + fireIndex += 1 + } + for (lane <- 0 until core.iex.aguPipes) { + admissionFire(fireIndex) := io.dispatch.aguDispatch(lane).fire + fireIndex += 1 + } + for (lane <- 0 until core.iex.stdPipes) { + admissionFire(fireIndex) := io.dispatch.storeDispatch(lane).fire + admissionFire(fireIndex + 1) := io.dispatch.storeDispatch(lane).fire + fireIndex += 2 + } + for (lane <- 0 until core.iex.systemMulticycleQueues) { + admissionFire(fireIndex) := io.dispatch.systemDispatch(lane).fire + fireIndex += 1 + } + for (lane <- 0 until core.iex.cmdIssueQueues) { + admissionFire(fireIndex) := io.dispatch.cmdDispatch(lane).fire + fireIndex += 1 + } + require(fireIndex == admissionCount) + + // A logical memory transaction is allocated by its only leader. Loads have + // one AGU child; a split store's address child is the leader and its data + // child receives the same candidate below. + val memoryLeaderFire = Wire(Vec(admissionCount, Bool())) + val loadLeaderFire = Wire(Vec(admissionCount, Bool())) + val admissionMemoryTransaction = Wire(Vec(admissionCount, + new OooIexMemoryTransactionIdentity(p))) + val admissionInitialLoadAttempt = Wire(Vec(admissionCount, + UInt(p.loadGenerationWidth.W))) + for (index <- 0 until admissionCount) { + val decoded = admissionTxn(index).uop.decoded + val leader = decoded.memory.valid && + admissionClass(index) === OooUopClass.Agu && + admissionChild(index) === 0.U + memoryLeaderFire(index) := admissionFire(index) && leader + loadLeaderFire(index) := memoryLeaderFire(index) && decoded.memory.isLoad + val precedingMemoryLeaders = if (index == 0) 0.U else + PopCount(memoryLeaderFire.take(index)) + val transactionCandidate = memoryTransactionSerial + + precedingMemoryLeaders + admissionMemoryTransaction(index).value := + transactionCandidate(p.memoryTransactionIdWidth - 1, 0) + admissionMemoryTransaction(index).generation := + transactionCandidate(memoryTransactionSerialWidth - 1, + p.memoryTransactionIdWidth) + val precedingLoadLeaders = if (index == 0) 0.U else + PopCount(loadLeaderFire.take(index)) + admissionInitialLoadAttempt(index) := initialLoadAttemptSerial + + precedingLoadLeaders + 1.U + } + for (lane <- 0 until core.iex.stdPipes) { + val address = storeAdmissionBase + 2 * lane + val data = address + 1 + admissionMemoryTransaction(data) := admissionMemoryTransaction(address) + } - io.s3Enable.valid := s3PendingValid && !s3PendingFrozen - io.s3Enable.bits := s3Pending + when(PopCount(memoryLeaderFire).orR) { + memoryTransactionSerial := memoryTransactionSerial + + PopCount(memoryLeaderFire) + } - for (port <- 0 until p.iexWakeupPorts) { - val wakeup = io.wakeup(port) - val wakeStidInRange = wakeup.bits.stid < p.stidCount.U - val safeWakeStid = Mux(wakeStidInRange, wakeup.bits.stid, 0.U) - val ptagInRange = wakeup.bits.ptag < p.pPhysRegs.U - val safePtag = Mux(ptagInRange, wakeup.bits.ptag, 0.U) - val ttagInRange = wakeup.bits.localTag < p.tPhysRegs.U - val safeTtag = Mux(ttagInRange, wakeup.bits.localTag, 0.U)( - ttagIndexWidth - 1, 0) - val utagInRange = wakeup.bits.localTag < p.uPhysRegs.U - val safeUtag = Mux(utagInRange, wakeup.bits.localTag, 0.U)( - utagIndexWidth - 1, 0) - val wakeupFrozen = recoveryFreeze && wakeup.bits.stid === recoveryStid - when(wakeup.valid && wakeupFrozen) { - assert(false.B, - "global recovery must quiesce target-STID wakeups before IEX prepare") - } - when(wakeup.valid && wakeup.bits.kind === - OooIexWakeupKind.SpeculativeLoad) { - assert(wakeup.bits.load.valid && wakeup.bits.load.producer.group.valid && - wakeup.bits.load.producer.bid.valid && - wakeup.bits.load.producer.group.stid === wakeup.bits.stid, - "speculative IEX wakeup requires an exact same-STID load producer") - } - when(wakeup.valid && !wakeupFrozen && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.P && - ptagInRange) { - pReadyValid(safePtag) := true.B - pReadyGeneration(safePtag) := wakeup.bits.ptagGeneration - pReadyStid(safePtag) := wakeup.bits.stid - pReadyEpoch(safePtag) := wakeup.bits.epoch - } - when(wakeup.valid && !wakeupFrozen && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.T && - wakeStidInRange && ttagInRange && - wakeup.bits.localSequence.valid) { - tReadyValid(safeWakeStid)(safeTtag) := true.B - tReadySequence(safeWakeStid)(safeTtag) := - wakeup.bits.localSequence - tReadyEpoch(safeWakeStid)(safeTtag) := wakeup.bits.epoch - } - when(wakeup.valid && !wakeupFrozen && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.U && - wakeStidInRange && utagInRange && - wakeup.bits.localSequence.valid) { - uReadyValid(safeWakeStid)(safeUtag) := true.B - uReadySequence(safeWakeStid)(safeUtag) := - wakeup.bits.localSequence - uReadyEpoch(safeWakeStid)(safeUtag) := wakeup.bits.epoch - } + when(PopCount(loadLeaderFire).orR) { + initialLoadAttemptSerial := initialLoadAttemptSerial + + PopCount(loadLeaderFire) } - for (port <- 0 until p.iexLoadCancelPorts) { - val cancel = io.loadCancel(port) - when(cancel.valid) { - assert(cancel.bits.load.valid && cancel.bits.load.producer.group.valid && - cancel.bits.load.producer.bid.valid && - cancel.bits.stid < p.stidCount.U && - cancel.bits.load.producer.group.stid === cancel.bits.stid, - "load cancel requires an exact same-STID producer generation") - } + + for (lane <- io.storeReserve.indices) { + val address = storeAdmissionBase + 2 * lane + io.storeReserve(lane).valid := requireStoreReservation.B && + io.dispatch.storeDispatch(lane).valid && allPresentedAdmissionsReady + io.storeReserve(lane).bits := makeRow( + admissionTxn(address), OooUopClass.Agu, 0.U, + selectedBank(address), selectedEntry(address), + reservationEpoch(OooUopClass.Agu.asUInt)(selectedBank(address))( + selectedEntry(address)) + 1.U, + admissionCapability(address), admissionMemoryTransaction(address), + admissionInitialLoadAttempt(address)) } - // Existing S2 rows advance before a new S2 bind writes its targets. The - // later assignment below keeps newly bound rows in S2 for one full cycle. for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank) { when(slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.BoundS2 && - !(recoveryFreeze && - scheduleRows(uopClass)(bank)(entry).stid === recoveryStid)) { + !targetFenced(scheduleRows(uopClass)(bank)(entry).stid)) { slotState(uopClass)(bank)(entry) := OooIexIssueSlotState.ResidentS3 } } - when(s2Valid) { - s1Valid(s2Stid) := false.B - s1StoreReserved(s2Stid) := 0.U - s2RoundRobin := s2Stid + 1.U - s3PendingValid := true.B - s3Pending.bind := s2Ack - - for (lane <- 0 until p.dispatchWidth) { - val allocation = s2Dispatch.allocations(lane) - val reservation = allocation.reservation - val uopIndex = allocation.uopIndex - val uopClass = reservation.uopClass.asUInt - val bank = reservation.bank - val entry = reservation.speculativeSlot - when(allocation.valid) { - assert(slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.Free, - "a retained dispatch lease must bind one free physical IQ row") - assert(s1Claimed(uopClass)(bank)(entry), - "S2 may bind only the exact physical target claimed by retained S1") - val pUop = s2Request.pRename.uops(uopIndex) - val tuUop = s2Request.tuRename.uops(uopIndex) - val row = Wire(new OooIexIssueRow(p)) - row := 0.U.asTypeOf(row) - row.valid := true.B - row.peId := s2Dispatch.peId - row.stid := s2Dispatch.stid - row.epoch := s2Dispatch.epoch - row.transactionId := s2Dispatch.transactionId - row.dispatchLane := lane.U - row.uopIndex := allocation.uopIndex - row.childIndex := allocation.childIndex - row.member := pUop.member - row.member.memberIndex := pUop.member.memberIndex + allocation.childIndex - row.reservation := reservation - row.uopKey := pUop.decoded.identity.key - row.parentCount := pUop.decoded.identity.parentCount - row.parentPcTokens := s2Request.o3.parentPcTokens(uopIndex) - row.pcParentIndexValid := false.B - row.pcParentIndex := 0.U - row.primaryPrediction := 0.U.asTypeOf(row.primaryPrediction) - for (parentIndex <- 0 until p.maxArchitecturalParentRefs) { - val parent = pUop.decoded.identity.parents(parentIndex) - when(parent.key.valid && parent.key.asUInt === - pUop.decoded.identity.key.primaryParent.asUInt) { - row.pcParentIndexValid := true.B - row.pcParentIndex := parentIndex.U - row.primaryPrediction := parent.prediction - } - } - row.boundary := pUop.decoded.identity.boundary - row.templateValid := pUop.decoded.identity.templateValid - row.templateGroupId := pUop.decoded.identity.templateGroupId - row.templateGeneration := pUop.decoded.identity.templateGeneration - row.opcode := pUop.decoded.opcode - row.recipe := pUop.decoded.recipe - row.plannedChildCount := pUop.decoded.plannedChildCount - row.immediateValid := pUop.decoded.immediateValid - row.immediate := pUop.decoded.immediate - row.memory := pUop.decoded.memory - row.memoryOrder := s2Request.memoryOrder.uops(uopIndex) - row.isStore := row.memoryOrder.valid && - row.memoryOrder.memoryValid && row.memoryOrder.isStore && - !row.memoryOrder.isLoad - row.storeOrder.valid := row.isStore - row.storeOrder.logicalMember := pUop.member - row.storeOrder.firstLsid := row.memoryOrder.firstLsid - row.storeOrder.firstStoreId := row.memoryOrder.firstTypeId - row.storeOrder.requestCount := row.memoryOrder.requestCount - row.boundaryTargetValid := pUop.decoded.boundaryTargetValid - row.boundaryTarget := pUop.decoded.boundaryTarget - row.preciseTrap := pUop.decoded.preciseTrap - row.trapCause := pUop.decoded.trapCause - row.blockLast := tuUop.blockLast - row.closeBeforeValid := tuUop.closeBeforeValid - row.closeBefore := tuUop.closeBefore - val storeSplit = - pUop.decoded.recipe.lateSplitKind === OooLateSplitKind.StoreAddressData.U || - pUop.decoded.recipe.lateSplitKind === OooLateSplitKind.PairStoreAddressData.U - val storeAddressChild = storeSplit && allocation.childIndex === 0.U - val storeDataChild = storeSplit && allocation.childIndex === 1.U - for (sourceIndex <- 0 until p.maxSourceOperands) { - val decodedSource = pUop.decoded.sources(sourceIndex) - val pSource = pUop.sources(sourceIndex).pMapping - val localSource = tuUop.sources(sourceIndex) - val source = row.sources(sourceIndex) - val sourceSelected = decodedSource.valid && Mux(storeAddressChild, - pUop.decoded.memory.addressSourceMask(sourceIndex), - Mux(storeDataChild, - pUop.decoded.memory.dataSourceMask(sourceIndex), true.B)) - val isP = decodedSource.operandClass === OperandClass.P - val isT = decodedSource.operandClass === OperandClass.T - val isU = decodedSource.operandClass === OperandClass.U - val ptagInRange = pSource.ptag < p.pPhysRegs.U - val safePtag = Mux(ptagInRange, pSource.ptag, 0.U) - val ttagInRange = localSource.physicalTag < p.tPhysRegs.U - val safeTtag = Mux(ttagInRange, localSource.physicalTag, 0.U)( - ttagIndexWidth - 1, 0) - val utagInRange = localSource.physicalTag < p.uPhysRegs.U - val safeUtag = Mux(utagInRange, localSource.physicalTag, 0.U)( - utagIndexWidth - 1, 0) - val pReadyRecorded = ptagInRange && pReadyValid(safePtag) && - pReadyGeneration(safePtag) === pSource.ptagGeneration && - pReadyStid(safePtag) === s2Dispatch.stid && - pReadyEpoch(safePtag) === s2Dispatch.epoch - val tReadyRecorded = ttagInRange && - tReadyValid(safeS2OwnerStid)(safeTtag) && - tReadySequence(safeS2OwnerStid)(safeTtag).asUInt === - localSource.sequence.asUInt && - tReadyEpoch(safeS2OwnerStid)(safeTtag) === s2Dispatch.epoch - val uReadyRecorded = utagInRange && - uReadyValid(safeS2OwnerStid)(safeUtag) && - uReadySequence(safeS2OwnerStid)(safeUtag).asUInt === - localSource.sequence.asUInt && - uReadyEpoch(safeS2OwnerStid)(safeUtag) === s2Dispatch.epoch - // The registered scoreboards above are pre-edge state. Include an - // exact current-cycle wakeup when constructing the S2 row so a - // consumer bound on the same edge cannot miss the one-cycle pulse. - // The result is still written into registered row state; neither - // query nor future pick logic consumes wakeup combinationally. - val pReadyNow = io.wakeup.map { wakeup => - wakeup.valid && wakeup.bits.stid === s2Dispatch.stid && - wakeup.bits.epoch === s2Dispatch.epoch && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.P && - wakeup.bits.ptag === pSource.ptag && - wakeup.bits.ptagGeneration === pSource.ptagGeneration - }.reduce(_ || _) - val tReadyNow = io.wakeup.map { wakeup => - wakeup.valid && wakeup.bits.stid === s2Dispatch.stid && - wakeup.bits.epoch === s2Dispatch.epoch && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.T && - wakeup.bits.localTag === localSource.physicalTag && - wakeup.bits.localSequence.asUInt === localSource.sequence.asUInt - }.reduce(_ || _) - val uReadyNow = io.wakeup.map { wakeup => - wakeup.valid && wakeup.bits.stid === s2Dispatch.stid && - wakeup.bits.epoch === s2Dispatch.epoch && - wakeup.bits.kind === OooIexWakeupKind.Committed && - wakeup.bits.operandClass === OperandClass.U && - wakeup.bits.localTag === localSource.physicalTag && - wakeup.bits.localSequence.asUInt === localSource.sequence.asUInt - }.reduce(_ || _) - val nonSpecReady = !sourceSelected || - (isP && (pSource.ready || pReadyRecorded || pReadyNow)) || - (isT && (tReadyRecorded || tReadyNow)) || - (isU && (uReadyRecorded || uReadyNow)) - val specWakeMatches = VecInit(io.wakeup.map { wakeup => - val pMatch = isP && wakeup.bits.operandClass === OperandClass.P && - wakeup.bits.ptag === pSource.ptag && - wakeup.bits.ptagGeneration === pSource.ptagGeneration - val tMatch = isT && wakeup.bits.operandClass === OperandClass.T && - wakeup.bits.localTag === localSource.physicalTag && - wakeup.bits.localSequence.asUInt === localSource.sequence.asUInt - val uMatch = isU && wakeup.bits.operandClass === OperandClass.U && - wakeup.bits.localTag === localSource.physicalTag && - wakeup.bits.localSequence.asUInt === localSource.sequence.asUInt - wakeup.valid && wakeup.bits.kind === - OooIexWakeupKind.SpeculativeLoad && wakeup.bits.load.valid && - wakeup.bits.stid === s2Dispatch.stid && - wakeup.bits.epoch === s2Dispatch.epoch && - (pMatch || tMatch || uMatch) - }) - val specLoadNow = Wire(new OooIexLoadGeneration(p)) - specLoadNow := 0.U.asTypeOf(specLoadNow) - for (port <- 0 until p.iexWakeupPorts) { - when(specWakeMatches(port)) { - specLoadNow := io.wakeup(port).bits.load - } - } - val specLoadCanceledNow = io.loadCancel.map { cancel => - cancel.valid && cancel.bits.load.valid && - cancel.bits.stid === s2Dispatch.stid && - cancel.bits.epoch === s2Dispatch.epoch && - cancel.bits.load.asUInt === specLoadNow.asUInt - }.reduce(_ || _) - assert(PopCount(specWakeMatches) <= 1.U, - "one source cannot accept multiple speculative load generations") - source.valid := sourceSelected - source.ready := nonSpecReady - source.specReady := sourceSelected && !nonSpecReady && - specWakeMatches.asUInt.orR && !specLoadCanceledNow - source.operandClass := decodedSource.operandClass - source.ptag := pSource.ptag - source.ptagGeneration := pSource.ptagGeneration - source.localTag := localSource.physicalTag - source.localSequence := localSource.sequence - source.load := Mux(source.specReady, specLoadNow, - 0.U.asTypeOf(specLoadNow)) - when(sourceSelected && !(isP || isT || isU)) { - source.ready := false.B - source.specReady := false.B - source.load := 0.U.asTypeOf(source.load) - } + for (index <- 0 until admissionCount) { + when(admissionFire(index)) { + val cls = admissionClass(index).asUInt + val bank = selectedBank(index) + val entry = selectedEntry(index) + val nextEpoch = reservationEpoch(cls)(bank)(entry) + 1.U + val row = makeRow(admissionTxn(index), admissionClass(index), + admissionChild(index), bank, entry, nextEpoch, + admissionCapability(index), admissionMemoryTransaction(index), + admissionInitialLoadAttempt(index)) + assert(slotState(cls)(bank)(entry) === OooIexIssueSlotState.Free, + "canonical dispatch may bind only a free physical IQ row") + scheduleRows(cls)(bank)(entry) := row.schedule + capabilityRows(cls)(bank)(entry) := admissionCapability(index) + reservationEpoch(cls)(bank)(entry) := nextEpoch + for (targetClass <- 0 until p.iqClassCount; + targetBank <- 0 until p.iqBankCount) { + when(cls === targetClass.U && bank === targetBank.U) { + payloadRows(targetClass)(targetBank).write(entry, row.payload) } - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val decodedDestination = - pUop.decoded.destinations(destinationIndex) - val pDestination = - pUop.destinations(destinationIndex).currentPMapping - val previousPDestination = - pUop.destinations(destinationIndex).previousPMapping - val localDestination = tuUop.destinations(destinationIndex) - val destination = row.destinations(destinationIndex) - val destinationSelected = decodedDestination.valid && - (!storeSplit || storeAddressChild) - destination.valid := destinationSelected - destination.kind := decodedDestination.kind - destination.atag := decodedDestination.atag - destination.relativeIndex := decodedDestination.relativeIndex - destination.ptag := pDestination.ptag - destination.ptagGeneration := pDestination.ptagGeneration - destination.localTag := localDestination.physicalTag - destination.localSequence := localDestination.sequence - row.payload.previousPDestinations(destinationIndex).valid := - destinationSelected && - decodedDestination.kind === DestinationKind.Gpr && - previousPDestination.valid - row.payload.previousPDestinations(destinationIndex).ptag := - previousPDestination.ptag - row.payload.previousPDestinations(destinationIndex).ptagGeneration := - previousPDestination.ptagGeneration - when(destinationSelected && - decodedDestination.kind === DestinationKind.Gpr && - pDestination.valid) { - pReadyValid(pDestination.ptag) := false.B - } - when(destinationSelected && - decodedDestination.kind === DestinationKind.T && - localDestination.valid && - localDestination.physicalTag < p.tPhysRegs.U) { - val destinationTtag = localDestination.physicalTag( - ttagIndexWidth - 1, 0) - tReadyValid(safeS2OwnerStid)(destinationTtag) := false.B - } - when(destinationSelected && - decodedDestination.kind === DestinationKind.U && - localDestination.valid && - localDestination.physicalTag < p.uPhysRegs.U) { - val destinationUtag = localDestination.physicalTag( - utagIndexWidth - 1, 0) - uReadyValid(safeS2OwnerStid)(destinationUtag) := false.B - } - } - scheduleRows(uopClass)(bank)(entry) := row.schedule - capabilityRows(uopClass)(bank)(entry) := - pUop.decoded.recipe.dispatchCapabilities(uopClass) - for (targetClass <- 0 until p.iqClassCount; - targetBank <- 0 until p.iqBankCount) { - when(uopClass === targetClass.U && bank === targetBank.U) { - payloadRows(targetClass)(targetBank).write(entry, row.payload) - } - } - s1Claimed(uopClass)(bank)(entry) := false.B - slotState(uopClass)(bank)(entry) := OooIexIssueSlotState.BoundS2 } + slotState(cls)(bank)(entry) := OooIexIssueSlotState.BoundS2 + } + } + for (left <- 0 until admissionCount; right <- left + 1 until admissionCount) { + when(admissionFire(left) && admissionFire(right)) { + assert(admissionClass(left) =/= admissionClass(right) || + selectedBank(left) =/= selectedBank(right) || + selectedEntry(left) =/= selectedEntry(right), + "simultaneously accepted dispatch children need distinct IQ rows") } - }.elsewhen(!s3PendingFrozen) { - s3PendingValid := false.B } - // Wakeups mutate only registered source-ready state. Query/pick-enable - // below never consumes the combinational wakeup inputs directly. + def sourceLoadCanceled( + row: OooIexScheduleRow, + source: OooIexSourceState): Bool = io.loadCancel.map { cancel => + cancel.valid && cancel.bits.load.valid && source.valid && + source.specReady && source.load.valid && + cancel.bits.stid === row.stid && cancel.bits.epoch === row.epoch && + cancel.bits.load.asUInt === source.load.asUInt + }.reduce(_ || _) + def rowLoadCanceled(row: OooIexScheduleRow): Bool = + row.sources.map(sourceLoadCanceled(row, _)).reduce(_ || _) + for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank; sourceIndex <- 0 until p.maxSourceOperands) { - val source = scheduleRows(uopClass)(bank)(entry).sources(sourceIndex) - val wakeMatch = io.wakeup.map { wake => - val pMatch = source.operandClass === OperandClass.P && - wake.bits.operandClass === OperandClass.P && - source.ptag === wake.bits.ptag && - source.ptagGeneration === wake.bits.ptagGeneration - val tMatch = source.operandClass === OperandClass.T && - wake.bits.operandClass === OperandClass.T && - source.localTag === wake.bits.localTag && - source.localSequence.asUInt === wake.bits.localSequence.asUInt - val uMatch = source.operandClass === OperandClass.U && - wake.bits.operandClass === OperandClass.U && - source.localTag === wake.bits.localTag && - source.localSequence.asUInt === wake.bits.localSequence.asUInt - wake.valid && wake.bits.stid === scheduleRows(uopClass)(bank)(entry).stid && - wake.bits.epoch === scheduleRows(uopClass)(bank)(entry).epoch && - (pMatch || tMatch || uMatch) - } - val committedWakeMatch = VecInit(wakeMatch.zip(io.wakeup).map { - case (matches, wake) => matches && - wake.bits.kind === OooIexWakeupKind.Committed - }) - val speculativeWakeMatch = VecInit(wakeMatch.zip(io.wakeup).map { - case (matches, wake) => matches && - wake.bits.kind === OooIexWakeupKind.SpeculativeLoad && - wake.bits.load.valid + val row = scheduleRows(uopClass)(bank)(entry) + val source = row.sources(sourceIndex) + val committedMatch = io.wakeup.map { wakeup => + val tagExact = Mux(source.operandClass === OperandClass.P, + wakeup.bits.ptag === source.ptag && + wakeup.bits.ptagGeneration === source.ptagGeneration, + wakeup.bits.localTag === source.localTag && + wakeup.bits.localSequence.asUInt === source.localSequence.asUInt) + wakeup.valid && wakeup.bits.kind === OooIexWakeupKind.Committed && + wakeup.bits.stid === row.stid && + (source.operandClass === OperandClass.P || + wakeup.bits.epoch === source.localEpoch) && + wakeup.bits.operandClass === source.operandClass && tagExact + }.reduce(_ || _) + val speculativeMatches = VecInit(io.wakeup.map { wakeup => + val tagExact = Mux(source.operandClass === OperandClass.P, + wakeup.bits.ptag === source.ptag && + wakeup.bits.ptagGeneration === source.ptagGeneration, + wakeup.bits.localTag === source.localTag && + wakeup.bits.localSequence.asUInt === source.localSequence.asUInt) + wakeup.valid && wakeup.bits.kind === OooIexWakeupKind.SpeculativeLoad && + wakeup.bits.load.valid && wakeup.bits.stid === row.stid && + (source.operandClass === OperandClass.P || + wakeup.bits.epoch === source.localEpoch) && + wakeup.bits.operandClass === source.operandClass && tagExact }) - val speculativeLoad = Wire(new OooIexLoadGeneration(p)) - speculativeLoad := 0.U.asTypeOf(speculativeLoad) - for (port <- 0 until p.iexWakeupPorts) { - when(speculativeWakeMatch(port)) { - speculativeLoad := io.wakeup(port).bits.load - } - } - assert(PopCount(speculativeWakeMatch) <= 1.U, - "one resident source cannot accept multiple speculative load generations") - assert(!(committedWakeMatch.asUInt.orR && - sourceLoadCanceled(scheduleRows(uopClass)(bank)(entry), source)), - "one source cannot commit and cancel on the same cycle") - when(slotState(uopClass)(bank)(entry) =/= OooIexIssueSlotState.Free && - !(recoveryFreeze && - scheduleRows(uopClass)(bank)(entry).stid === recoveryStid) && - source.valid && committedWakeMatch.asUInt.orR) { + val fileReady = residentExactReady(row, source) + val canceled = sourceLoadCanceled(row, source) + when(row.valid && source.valid && !targetFenced(row.stid) && + (committedMatch || fileReady)) { source.ready := true.B source.specReady := false.B source.load := 0.U.asTypeOf(source.load) - }.elsewhen(slotState(uopClass)(bank)(entry) =/= - OooIexIssueSlotState.Free && - !(recoveryFreeze && - scheduleRows(uopClass)(bank)(entry).stid === recoveryStid) && - source.valid && !source.ready && speculativeWakeMatch.asUInt.orR) { + }.elsewhen(row.valid && source.valid && canceled) { + source.specReady := false.B + source.load := 0.U.asTypeOf(source.load) + }.elsewhen(row.valid && source.valid && !source.ready && + !targetFenced(row.stid) && speculativeMatches.asUInt.orR) { source.specReady := true.B - source.load := speculativeLoad + for (port <- 0 until p.iexWakeupPorts) { + when(speculativeMatches(port)) { + source.load := io.wakeup(port).bits.load + } + } } + assert(PopCount(speculativeMatches) <= 1.U, + "one IQ source cannot accept multiple speculative load attempts") } - // Load miss/replay follows wakeup assignment so cancel wins a same-cycle - // race. IQ residency is retained, but any P1/I1/I2 claim is returned to S3 - // by clearing inFlight. A later exact wakeup can make the row pickable again. + private val storeClasses = Seq( + OooUopClass.Agu.asUInt.litValue.toInt, + OooUopClass.Std.asUInt.litValue.toInt) + private val storePhysicalRows = + storeClasses.size * p.iqBankCount * p.iqEntriesPerBank + val storeIssueFrontier = Module( + new OooIexStoreIssueFrontier(p, storePhysicalRows)) + val storeIssueAllowed = Wire(Vec(p.iqClassCount, + Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, Bool())))) for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank) { + storeIssueAllowed(uopClass)(bank)(entry) := true.B + } + for ((uopClass, classIndex) <- storeClasses.zipWithIndex; + bank <- 0 until p.iqBankCount; + entry <- 0 until p.iqEntriesPerBank) { + val flat = (classIndex * p.iqBankCount + bank) * + p.iqEntriesPerBank + entry val row = scheduleRows(uopClass)(bank)(entry) - val canceledSources = Wire(Vec(p.maxSourceOperands, Bool())) - for (sourceIndex <- 0 until p.maxSourceOperands) { - val source = row.sources(sourceIndex) - canceledSources(sourceIndex) := sourceLoadCanceled(row, source) - when(slotState(uopClass)(bank)(entry) =/= - OooIexIssueSlotState.Free && canceledSources(sourceIndex)) { - source.specReady := false.B - source.load := 0.U.asTypeOf(source.load) - } - } - when(slotState(uopClass)(bank)(entry) === - OooIexIssueSlotState.ResidentS3 && canceledSources.asUInt.orR) { - row.inFlight := false.B - } + val candidate = storeIssueFrontier.io.candidates(flat) + candidate.resident := + slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.ResidentS3 && + row.valid + candidate.isStore := row.isStore + candidate.peId := row.peId + candidate.stid := row.stid + candidate.order := row.storeOrder + storeIssueAllowed(uopClass)(bank)(entry) := + storeIssueFrontier.io.allowed(flat) } - - val releaseClasses = Wire(Vec(p.iexReleaseWidth, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val releaseClassInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseBankInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseEntryInRange = Wire(Vec(p.iexReleaseWidth, Bool())) - val safeReleaseClasses = Wire(Vec(p.iexReleaseWidth, - UInt(math.max(1, chisel3.util.log2Ceil(p.iqClassCount)).W))) - val safeReleaseBanks = Wire(Vec(p.iexReleaseWidth, - UInt(p.iqBankWidth.W))) - val safeReleaseEntries = Wire(Vec(p.iexReleaseWidth, - UInt(p.iqEntryWidth.W))) - val releaseAddressExact = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseOwnerExact = Wire(Vec(p.iexReleaseWidth, Bool())) - val releaseCollision = Wire(Vec(p.iexReleaseWidth, Bool())) + io.storeFrontierBlocked := storeIssueFrontier.io.blockedCount for (lane <- 0 until p.iexReleaseWidth) { val release = io.releases(lane).bits - releaseClasses(lane) := release.dispatch.reservation.uopClass.asUInt - releaseClassInRange(lane) := releaseClasses(lane) < p.iqClassCount.U - releaseBankInRange(lane) := - release.dispatch.reservation.bank < p.iqBankCount.U - releaseEntryInRange(lane) := - release.dispatch.reservation.speculativeSlot < p.iqEntriesPerBank.U - safeReleaseClasses(lane) := Mux( - releaseClassInRange(lane), releaseClasses(lane), 0.U) - safeReleaseBanks(lane) := Mux(releaseBankInRange(lane), + val cls = release.dispatch.reservation.uopClass.asUInt + val classInRange = cls < p.iqClassCount.U + val bankInRange = release.dispatch.reservation.bank < p.iqBankCount.U + val entryInRange = release.dispatch.reservation.speculativeSlot < + p.iqEntriesPerBank.U + val safeClass = Mux(classInRange, cls, 0.U) + val safeBank = Mux(bankInRange, release.dispatch.reservation.bank, 0.U) - safeReleaseEntries(lane) := Mux(releaseEntryInRange(lane), + val safeEntry = Mux(entryInRange, release.dispatch.reservation.speculativeSlot, 0.U) - releaseAddressExact(lane) := release.dispatch.reservation.valid && - releaseClassInRange(lane) && releaseBankInRange(lane) && - releaseEntryInRange(lane) - val releaseRow = scheduleRows(safeReleaseClasses(lane))( - safeReleaseBanks(lane))(safeReleaseEntries(lane)) - releaseOwnerExact(lane) := releaseAddressExact(lane) && - slotState(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseEntries(lane)) === OooIexIssueSlotState.ResidentS3 && - releaseRow.valid && releaseRow.inFlight && - sameMember(release.member, releaseRow.member) && - release.dispatch.peId === releaseRow.peId && - release.dispatch.stid === releaseRow.stid && - release.dispatch.epoch === releaseRow.epoch && - release.dispatch.transactionId === releaseRow.transactionId && - release.dispatch.reservation.asUInt === releaseRow.reservation.asUInt && - sameMember(release.dispatch.member, release.member) && - !rowLoadCanceled(releaseRow) && - !(recoveryFreeze && release.dispatch.stid === recoveryStid) - releaseCollision(lane) := (0 until p.iexReleaseWidth).filter(_ != lane) - .map { peer => - io.releases(peer).valid && releaseAddressExact(lane) && - releaseAddressExact(peer) && - safeReleaseClasses(lane) === safeReleaseClasses(peer) && - safeReleaseBanks(lane) === safeReleaseBanks(peer) && - safeReleaseEntries(lane) === safeReleaseEntries(peer) - }.foldLeft(false.B)(_ || _) - val releaseExact = releaseOwnerExact(lane) && !releaseCollision(lane) - io.dispatchReleases(lane).valid := - io.releases(lane).valid && releaseExact - io.dispatchReleases(lane).bits := release.dispatch - io.releases(lane).ready := - releaseExact && io.dispatchReleases(lane).ready - io.releaseRejecteds(lane).valid := - io.releases(lane).valid && !releaseExact + val row = selectEntry(scheduleRows(safeClass)(safeBank), safeEntry) + val collision = (0 until lane).map { older => + io.releases(older).valid && + io.releases(older).bits.dispatch.reservation.asUInt === + release.dispatch.reservation.asUInt + }.foldLeft(false.B)(_ || _) + val exact = classInRange && bankInRange && entryInRange && + release.dispatch.reservation.valid && + selectEntry(slotState(safeClass)(safeBank), safeEntry) === + OooIexIssueSlotState.ResidentS3 && row.valid && row.inFlight && + sameMember(release.member, row.member) && + release.dispatch.peId === row.peId && release.dispatch.stid === row.stid && + release.dispatch.epoch === row.epoch && + release.dispatch.transactionId === row.transactionId && + release.dispatch.reservation.asUInt === row.reservation.asUInt && + !collision && !targetFenced(row.stid) + io.releases(lane).ready := exact + io.releaseRejecteds(lane).valid := io.releases(lane).valid && !exact io.releaseRejecteds(lane).bits.member := release.member io.releaseRejecteds(lane).bits.peId := release.dispatch.peId io.releaseRejecteds(lane).bits.stid := release.dispatch.stid @@ -1157,464 +1131,117 @@ class OooIexIssue( release.dispatch.transactionId io.releaseRejecteds(lane).bits.reservation := release.dispatch.reservation - when(io.releases(lane).fire) { - slotState(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseEntries(lane)) := OooIexIssueSlotState.Free - scheduleRows(safeReleaseClasses(lane))(safeReleaseBanks(lane))( - safeReleaseEntries(lane)) := + selectEntry(slotState(safeClass)(safeBank), safeEntry) := + OooIexIssueSlotState.Free + selectEntry(scheduleRows(safeClass)(safeBank), safeEntry) := 0.U.asTypeOf(new OooIexScheduleRow(p)) } } - val recoveryS1 = s1Rows(safeRecoveryStid) - val recoveryS1Live = recoveryStidInRange && s1Valid(safeRecoveryStid) - val recoveryS1Kill = Wire(Vec(p.dispatchWidth, Bool())) - val recoveryS1LaneExact = Wire(Vec(p.dispatchWidth, Bool())) - for (lane <- 0 until p.dispatchWidth) { - val allocation = recoveryS1.dispatch.allocations(lane) - val reservation = allocation.reservation - val uopIndexInRange = allocation.uopIndex < p.decodedUopWidth.U - val safeUopIndex = Mux(uopIndexInRange, allocation.uopIndex, 0.U) - val pUop = recoveryS1.pRename.uops(safeUopIndex) - val decodedUop = recoveryS1.o3.request.reservation.transaction.decoded - .uops(safeUopIndex) - val classIndex = reservation.uopClass.asUInt - val classInRange = classIndex < p.iqClassCount.U - val bankInRange = reservation.bank < p.iqBankCount.U - val entryInRange = reservation.speculativeSlot < p.iqEntriesPerBank.U - val safeClass = Mux(classInRange, classIndex, 0.U) - val safeBank = Mux(bankInRange, reservation.bank, 0.U) - val safeEntry = Mux(entryInRange, reservation.speculativeSlot, 0.U) - val member = Wire(new RobMemberKey(p)) - member := pUop.member - member.memberIndex := pUop.member.memberIndex + allocation.childIndex - recoveryS1LaneExact(lane) := !allocation.valid || ( - recoveryS1.dispatch.allocationMask(lane) && reservation.valid && - uopIndexInRange && pUop.valid && decodedUop.valid && - allocation.childIndex < decodedUop.plannedChildCount && - classInRange && bankInRange && entryInRange && - slotState(safeClass)(safeBank)(safeEntry) === - OooIexIssueSlotState.Free && - s1Claimed(safeClass)(safeBank)(safeEntry) && - member.group.peId === recoveryS1.dispatch.peId && - member.group.stid === recoveryS1.dispatch.stid && - OooRecoveryMembership.memberInOldWindow(p, recoveryPlan, member)) - recoveryS1Kill(lane) := recoveryS1Live && allocation.valid && - OooRecoveryMembership.memberKilled(p, recoveryPlan, member) - } - val recoveryS1StoreKillExact = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val decodedUop = recoveryS1.o3.request.reservation.transaction.decoded - .uops(uopIndex) - val splitStore = recoveryS1Live && decodedUop.valid && - decodedUop.memory.valid && decodedUop.memory.isStore && - !decodedUop.memory.isLoad && - (decodedUop.recipe.lateSplitKind === - OooLateSplitKind.StoreAddressData.U || - decodedUop.recipe.lateSplitKind === - OooLateSplitKind.PairStoreAddressData.U) - val children = VecInit((0 until p.dispatchWidth).map { lane => - val allocation = recoveryS1.dispatch.allocations(lane) - allocation.valid && allocation.uopIndex === uopIndex.U - }) - val killedChildren = VecInit((0 until p.dispatchWidth).map { lane => - children(lane) && recoveryS1Kill(lane) - }) - recoveryS1StoreKillExact(uopIndex) := !splitStore || - !killedChildren.asUInt.orR || - PopCount(killedChildren) === PopCount(children) - } - val recoveryS1IdentityExact = !recoveryS1Live || ( - recoveryS1.dispatch.valid && recoveryS1.pRename.valid && - recoveryS1.dispatch.stid === recoveryStid && - recoveryS1.pRename.stid === recoveryStid && - recoveryS1.dispatch.peId === recoveryPlan.oldHead.peId && - recoveryS1.pRename.peId === recoveryPlan.oldHead.peId && - recoveryS1.dispatch.transactionId === - recoveryS1.pRename.transactionId && - recoveryS1.dispatch.allocationMask === VecInit( - recoveryS1.dispatch.allocations.map(_.valid)).asUInt) - val recoveryS1RowsExact = !recoveryS1Live || - (recoveryS1IdentityExact && recoveryS1LaneExact.reduce(_ && _) && - recoveryS1StoreKillExact.asUInt.andR) - - // Recovery scans one shallow slice from every physical class/bank per - // cycle. This replaces the former one-cycle CAM over every resident row. - // The scan is side-effect free: it retains exact masks and counters, then - // the common O3 apply consumes those masks in one architectural event. - val recoveryScanRowExact = Wire(Vec(p.iqClassCount, + val scanKill = Wire(Vec(p.iqClassCount, Vec(p.iqBankCount, Vec(p.iexRecoveryScanEntriesPerBankPerCycle, Bool())))) - val recoveryScanRowKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, Bool())))) - val recoveryScanBoundKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, Bool())))) - val recoveryScanResidentKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, Bool())))) - val recoveryScanS3Seen = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, - UInt(p.dispatchWidth.W))))) - val recoveryScanS3Kill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, - UInt(p.dispatchWidth.W))))) - val recoveryScanPReadyKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, - UInt(p.pPhysRegs.W))))) - val recoveryScanTReadyKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, - UInt(p.tPhysRegs.W))))) - val recoveryScanUReadyKill = Wire(Vec(p.iqClassCount, - Vec(p.iqBankCount, - Vec(p.iexRecoveryScanEntriesPerBankPerCycle, - UInt(p.uPhysRegs.W))))) - for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; - scanLane <- 0 until p.iexRecoveryScanEntriesPerBankPerCycle) { - val entryWide = recoveryScanCursor * - p.iexRecoveryScanEntriesPerBankPerCycle.U + scanLane.U + lane <- 0 until p.iexRecoveryScanEntriesPerBankPerCycle) { + val entryWide = recoveryCursor * + p.iexRecoveryScanEntriesPerBankPerCycle.U + lane.U val entry = entryWide(p.iqEntryWidth - 1, 0) - val state = slotState(uopClass)(bank)(entry) val row = scheduleRows(uopClass)(bank)(entry) - val occupied = state =/= OooIexIssueSlotState.Free - val selected = occupied && row.stid === recoveryStid - val logicalMember = Wire(new RobMemberKey(p)) - logicalMember := row.member - logicalMember.memberIndex := row.member.memberIndex - row.childIndex - val logicalMemberNoUnderflow = row.member.memberIndex >= row.childIndex - val storeRecoveryExact = !row.isStore || - (logicalMemberNoUnderflow && - OooRecoveryMembership.memberKilled(p, recoveryPlan, row.member) === - OooRecoveryMembership.memberKilled( - p, recoveryPlan, logicalMember)) - val rowExact = !selected || ( - row.valid && row.peId === recoveryPlan.oldHead.peId && - row.member.group.peId === row.peId && - row.member.group.stid === row.stid && - row.reservation.valid && - row.reservation.uopClass.asUInt === uopClass.U && - row.reservation.bank === bank.U && - row.reservation.speculativeSlot === entry && - row.dispatchLane < p.dispatchWidth.U && - storeRecoveryExact && - OooRecoveryMembership.memberInOldWindow( - p, recoveryPlan, row.member)) - val rowKill = selected && rowExact && - OooRecoveryMembership.memberKilled(p, recoveryPlan, row.member) - recoveryScanRowExact(uopClass)(bank)(scanLane) := rowExact - recoveryScanRowKill(uopClass)(bank)(scanLane) := rowKill - recoveryScanBoundKill(uopClass)(bank)(scanLane) := rowKill && - state === OooIexIssueSlotState.BoundS2 - recoveryScanResidentKill(uopClass)(bank)(scanLane) := rowKill && - state === OooIexIssueSlotState.ResidentS3 - - val s3RowExact = s3PendingValid && - s3Pending.bind.stid === recoveryStid && occupied && row.valid && - row.dispatchLane < p.dispatchWidth.U && - row.peId === s3Pending.bind.peId && - row.stid === s3Pending.bind.stid && - row.epoch === s3Pending.bind.epoch && - row.transactionId === s3Pending.bind.transactionId - recoveryScanS3Seen(uopClass)(bank)(scanLane) := Mux(s3RowExact, - UIntToOH(row.dispatchLane, p.dispatchWidth), 0.U(p.dispatchWidth.W)) - recoveryScanS3Kill(uopClass)(bank)(scanLane) := Mux( - s3RowExact && rowKill, - UIntToOH(row.dispatchLane, p.dispatchWidth), 0.U(p.dispatchWidth.W)) - - val pReadyKill = (0 until p.maxDestinationOperands).map { - destinationIndex => - val destination = row.destinations(destinationIndex) - val inRange = destination.ptag < p.pPhysRegs.U - val safeTag = Mux(inRange, destination.ptag, 0.U) - val exact = rowKill && destination.valid && - destination.kind === DestinationKind.Gpr && inRange && - retainedRecoveryPReadyValid(safeTag) && - retainedRecoveryPReadyGeneration(safeTag) === - destination.ptagGeneration && - retainedRecoveryPReadyStid(safeTag) === row.stid && - retainedRecoveryPReadyEpoch(safeTag) === row.epoch - Mux(exact, UIntToOH(destination.ptag, p.pPhysRegs), - 0.U(p.pPhysRegs.W)) - }.reduce(_ | _) - val tReadyKill = (0 until p.maxDestinationOperands).map { - destinationIndex => - val destination = row.destinations(destinationIndex) - val inRange = destination.localTag < p.tPhysRegs.U - val safeTag = Mux(inRange, destination.localTag, 0.U)( - ttagIndexWidth - 1, 0) - val exact = rowKill && destination.valid && - destination.kind === DestinationKind.T && inRange && - tReadyValid(safeRecoveryStid)(safeTag) && - tReadySequence(safeRecoveryStid)(safeTag).asUInt === - destination.localSequence.asUInt && - tReadyEpoch(safeRecoveryStid)(safeTag) === row.epoch - Mux(exact, UIntToOH(destination.localTag, p.tPhysRegs), - 0.U(p.tPhysRegs.W)) - }.reduce(_ | _) - val uReadyKill = (0 until p.maxDestinationOperands).map { - destinationIndex => - val destination = row.destinations(destinationIndex) - val inRange = destination.localTag < p.uPhysRegs.U - val safeTag = Mux(inRange, destination.localTag, 0.U)( - utagIndexWidth - 1, 0) - val exact = rowKill && destination.valid && - destination.kind === DestinationKind.U && inRange && - uReadyValid(safeRecoveryStid)(safeTag) && - uReadySequence(safeRecoveryStid)(safeTag).asUInt === - destination.localSequence.asUInt && - uReadyEpoch(safeRecoveryStid)(safeTag) === row.epoch - Mux(exact, UIntToOH(destination.localTag, p.uPhysRegs), - 0.U(p.uPhysRegs.W)) - }.reduce(_ | _) - recoveryScanPReadyKill(uopClass)(bank)(scanLane) := pReadyKill - recoveryScanTReadyKill(uopClass)(bank)(scanLane) := tReadyKill - recoveryScanUReadyKill(uopClass)(bank)(scanLane) := uReadyKill + scanKill(uopClass)(bank)(lane) := row.valid && + RecoveryPlanContract.suffixMember( + retainedRecovery, + OooRecoveryMembership.robIdentity(p, core, row.member)) } - - val recoveryScanRowsExact = recoveryScanRowExact.asUInt.andR - val recoveryScanBoundKilled = PopCount(recoveryScanBoundKill.asUInt) - val recoveryScanResidentKilled = PopCount(recoveryScanResidentKill.asUInt) - val recoveryScanS3SeenMask = (0 until p.iqClassCount).flatMap { - uopClass => (0 until p.iqBankCount).flatMap { bank => - (0 until p.iexRecoveryScanEntriesPerBankPerCycle).map { scanLane => - recoveryScanS3Seen(uopClass)(bank)(scanLane) - } - } - }.reduce(_ | _) - val recoveryScanS3KillMask = (0 until p.iqClassCount).flatMap { - uopClass => (0 until p.iqBankCount).flatMap { bank => - (0 until p.iexRecoveryScanEntriesPerBankPerCycle).map { scanLane => - recoveryScanS3Kill(uopClass)(bank)(scanLane) - } - } - }.reduce(_ | _) - val recoveryScanPReadyKillMask = (0 until p.iqClassCount).flatMap { - uopClass => (0 until p.iqBankCount).flatMap { bank => - (0 until p.iexRecoveryScanEntriesPerBankPerCycle).map { scanLane => - recoveryScanPReadyKill(uopClass)(bank)(scanLane) - } - } - }.reduce(_ | _) - val recoveryScanTReadyKillMask = (0 until p.iqClassCount).flatMap { - uopClass => (0 until p.iqBankCount).flatMap { bank => - (0 until p.iexRecoveryScanEntriesPerBankPerCycle).map { scanLane => - recoveryScanTReadyKill(uopClass)(bank)(scanLane) - } - } - }.reduce(_ | _) - val recoveryScanUReadyKillMask = (0 until p.iqClassCount).flatMap { - uopClass => (0 until p.iqBankCount).flatMap { bank => - (0 until p.iexRecoveryScanEntriesPerBankPerCycle).map { scanLane => - recoveryScanUReadyKill(uopClass)(bank)(scanLane) - } + val scanLast = recoveryCursor === (p.iexRecoveryScanCycles - 1).U + io.recovery.prepare.ready := + recoveryState === OooIexRecoveryScanState.Idle && prepareExact + io.recovery.prepared.valid := + recoveryState === OooIexRecoveryScanState.Prepared + io.recovery.prepared.bits := retainedRecovery + io.recovery.prepared.bits.phase := RecoveryPhase.Prepare + val applyExact = io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val abortExact = io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + io.acceptedRecoveryApply.valid := + recoveryState === OooIexRecoveryScanState.Prepared && applyExact + io.acceptedRecoveryApply.bits := retainedRecovery + io.acceptedRecoveryApply.bits.phase := RecoveryPhase.Apply + + when(io.recovery.prepare.fire) { + retainedRecovery := io.recovery.prepare.bits + recoveryCursor := 0.U + recoveryKillMask := 0.U.asTypeOf(recoveryKillMask) + recoveryState := OooIexRecoveryScanState.Scan + }.elsewhen(recoveryState === OooIexRecoveryScanState.Scan) { + for (uopClass <- 0 until p.iqClassCount; + bank <- 0 until p.iqBankCount; + lane <- 0 until p.iexRecoveryScanEntriesPerBankPerCycle) { + val entryWide = recoveryCursor * + p.iexRecoveryScanEntriesPerBankPerCycle.U + lane.U + val entry = entryWide(p.iqEntryWidth - 1, 0) + recoveryKillMask(uopClass)(bank)(entry) := + scanKill(uopClass)(bank)(lane) } - }.reduce(_ | _) - val recoveryScanLast = recoveryScanCursor === - (p.iexRecoveryScanCycles - 1).U - val recoveryNextS3SeenMask = retainedRecoveryS3SeenMask | - recoveryScanS3SeenMask - val recoveryS3ExactAfterScan = !s3PendingValid || - s3Pending.bind.stid =/= recoveryStid || - (s3Pending.bind.allocationMask & ~recoveryNextS3SeenMask) === 0.U - val recoveryCaptureExact = recoveryPlan.valid && recoveryStidInRange && - recoveryS1RowsExact - - val recoveryCaptureRejected = - recoveryScanState === OooIexRecoveryScanState.Idle && - io.recoveryPrepare.valid && !recoveryCaptureExact - val recoveryOfferChanged = - recoveryScanState =/= OooIexRecoveryScanState.Idle && - recoveryScanState =/= OooIexRecoveryScanState.Rejected && - io.recoveryPrepare.valid && !recoveryOfferExact - val recoveryScanRejected = - recoveryScanState === OooIexRecoveryScanState.Scan && - io.recoveryPrepare.valid && recoveryOfferExact && - (!recoveryScanRowsExact || - (recoveryScanLast && !recoveryS3ExactAfterScan)) - - io.recoveryPrepareReady := - recoveryScanState === OooIexRecoveryScanState.Prepared && - recoveryOfferExact - io.recoveryPrepared := 0.U.asTypeOf(io.recoveryPrepared) - io.recoveryPrepared.valid := io.recoveryPrepareReady - io.recoveryPrepared.stid := recoveryStid - io.recoveryPrepared.s1Killed := PopCount(retainedRecoveryS1KillMask) - io.recoveryPrepared.boundKilled := retainedRecoveryBoundKilled - io.recoveryPrepared.residentKilled := retainedRecoveryResidentKilled - io.recoveryRejected.valid := recoveryCaptureRejected || - recoveryOfferChanged || recoveryScanRejected || - (recoveryScanState === OooIexRecoveryScanState.Rejected && - io.recoveryPrepare.valid) - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.stidInRange := recoveryStidInRange - io.recoveryRejected.bits.residentRowsExact := false.B - io.recoveryRejected.bits.s1RowsExact := Mux( - recoveryScanState === OooIexRecoveryScanState.Idle, - recoveryS1RowsExact, retainedRecoveryS1RowsExact) - - when(recoveryScanState === OooIexRecoveryScanState.Idle && - io.recoveryPrepare.valid && recoveryCaptureExact) { - retainedRecoveryPlan := io.recoveryPrepare.bits - retainedRecoveryS1KillMask := recoveryS1Kill.asUInt - retainedRecoveryS1RowsExact := recoveryS1RowsExact - retainedRecoveryBoundKilled := 0.U - retainedRecoveryResidentKilled := 0.U - retainedRecoveryS3SeenMask := 0.U - retainedRecoveryS3KillMask := 0.U - retainedRecoveryPReadyKillMask := 0.U - retainedRecoveryTReadyKillMask := 0.U - retainedRecoveryUReadyKillMask := 0.U - retainedRecoveryPReadyValid := pReadyValid - retainedRecoveryPReadyGeneration := pReadyGeneration - retainedRecoveryPReadyStid := pReadyStid - retainedRecoveryPReadyEpoch := pReadyEpoch - recoveryScanCursor := 0.U - recoveryScanState := OooIexRecoveryScanState.Scan - }.elsewhen(recoveryScanState =/= OooIexRecoveryScanState.Idle && - !io.recoveryPrepare.valid) { - // Valid deassertion is the existing owner-abort indication. Scan state is - // disposable metadata and has never mutated physical residency. - recoveryScanState := OooIexRecoveryScanState.Idle - }.elsewhen(recoveryOfferChanged) { - recoveryScanState := OooIexRecoveryScanState.Rejected - }.elsewhen(recoveryScanState === OooIexRecoveryScanState.Scan) { - when(!recoveryScanRowsExact) { - recoveryScanState := OooIexRecoveryScanState.Rejected + when(scanLast) { + recoveryState := OooIexRecoveryScanState.Prepared }.otherwise { - for (uopClass <- 0 until p.iqClassCount; - bank <- 0 until p.iqBankCount; - scanLane <- 0 until p.iexRecoveryScanEntriesPerBankPerCycle) { - val entryWide = recoveryScanCursor * - p.iexRecoveryScanEntriesPerBankPerCycle.U + scanLane.U - val entry = entryWide(p.iqEntryWidth - 1, 0) - recoveryRowKillMask(uopClass)(bank)(entry) := - recoveryScanRowKill(uopClass)(bank)(scanLane) - } - retainedRecoveryBoundKilled := retainedRecoveryBoundKilled + - recoveryScanBoundKilled - retainedRecoveryResidentKilled := retainedRecoveryResidentKilled + - recoveryScanResidentKilled - retainedRecoveryS3SeenMask := recoveryNextS3SeenMask - retainedRecoveryS3KillMask := retainedRecoveryS3KillMask | - recoveryScanS3KillMask - retainedRecoveryPReadyKillMask := retainedRecoveryPReadyKillMask | - recoveryScanPReadyKillMask - retainedRecoveryTReadyKillMask := retainedRecoveryTReadyKillMask | - recoveryScanTReadyKillMask - retainedRecoveryUReadyKillMask := retainedRecoveryUReadyKillMask | - recoveryScanUReadyKillMask - when(recoveryScanLast) { - recoveryScanState := Mux(recoveryS3ExactAfterScan, - OooIexRecoveryScanState.Prepared, - OooIexRecoveryScanState.Rejected) - }.otherwise { - recoveryScanCursor := recoveryScanCursor + 1.U - } + recoveryCursor := recoveryCursor + 1.U } - }.elsewhen(io.recoveryFire) { - recoveryScanState := OooIexRecoveryScanState.Idle - } - - when(io.recoveryFire) { - assert(io.recoveryPrepareReady, - "IEX recovery may apply only one exact prepared ROB suffix") - - val survivingS1Mask = recoveryS1.dispatch.allocationMask & - ~retainedRecoveryS1KillMask - when(recoveryS1Live) { - s1Rows(safeRecoveryStid).dispatch.allocationMask := survivingS1Mask - for (lane <- 0 until p.dispatchWidth) { - val allocation = recoveryS1.dispatch.allocations(lane) - when(retainedRecoveryS1KillMask(lane)) { - s1Claimed(allocation.reservation.uopClass.asUInt)( - allocation.reservation.bank)( - allocation.reservation.speculativeSlot) := false.B - s1Rows(safeRecoveryStid).dispatch.allocations(lane).valid := false.B - s1Rows(safeRecoveryStid).dispatch.allocations(lane) - .reservation.valid := false.B - } - } - when(!survivingS1Mask.orR) { - s1Valid(safeRecoveryStid) := false.B - } - } - + }.elsewhen(recoveryState === OooIexRecoveryScanState.Prepared && + applyExact) { for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank) { - when(recoveryRowKillMask(uopClass)(bank)(entry)) { + when(recoveryKillMask(uopClass)(bank)(entry)) { slotState(uopClass)(bank)(entry) := OooIexIssueSlotState.Free scheduleRows(uopClass)(bank)(entry) := 0.U.asTypeOf(new OooIexScheduleRow(p)) } } - - when(s3PendingValid && s3Pending.bind.stid === recoveryStid) { - val survivingS3Mask = s3Pending.bind.allocationMask & - ~retainedRecoveryS3KillMask - s3Pending.bind.allocationMask := survivingS3Mask - when(!survivingS3Mask.orR) { - s3PendingValid := false.B - } - } - - for (ptag <- 0 until p.pPhysRegs) { - val retainedPReadyIdentityStillExact = pReadyValid(ptag) && - retainedRecoveryPReadyValid(ptag) && - pReadyGeneration(ptag) === - retainedRecoveryPReadyGeneration(ptag) && - pReadyStid(ptag) === retainedRecoveryPReadyStid(ptag) && - pReadyEpoch(ptag) === retainedRecoveryPReadyEpoch(ptag) - when(retainedRecoveryPReadyKillMask(ptag) && - retainedPReadyIdentityStillExact) { - pReadyValid(ptag) := false.B - } - } - for (ttag <- 0 until p.tPhysRegs) { - when(retainedRecoveryTReadyKillMask(ttag)) { - tReadyValid(safeRecoveryStid)(ttag) := false.B - } - } - for (utag <- 0 until p.uPhysRegs) { - when(retainedRecoveryUReadyKillMask(utag)) { - uReadyValid(safeRecoveryStid)(utag) := false.B - } - } + recoveryState := OooIexRecoveryScanState.Idle + }.elsewhen(recoveryState === OooIexRecoveryScanState.Prepared && + abortExact) { + recoveryState := OooIexRecoveryScanState.Idle + } + when(io.recovery.apply.valid) { + assert(recoveryState === OooIexRecoveryScanState.Prepared && applyExact, + "IQ recovery apply requires the exact prepared transaction") + } + when(io.recovery.abort.valid) { + assert(recoveryState === OooIexRecoveryScanState.Prepared && abortExact, + "IQ recovery abort requires the exact prepared transaction") } - // This assignment intentionally follows wakeup and recovery processing: - // token recycle wins a same-cycle race so a stale completion can never make - // the next generation of the physical register appear ready. - when(io.ptagRecycle.fire) { - for (index <- 0 until p.pTagReturnWidth) { - val token = io.ptagRecycle.bits.tokens(index) - when(index.U < io.ptagRecycle.bits.count && token.valid && - pReadyValid(token.ptag) && - pReadyGeneration(token.ptag) === token.generation) { - pReadyValid(token.ptag) := false.B - } - } + private def policyReasons( + domain: Int, + uopClass: OooUopClass.Type, + row: OooIexScheduleRow): UInt = { + val query = Wire(new OooIexIssueBlockQuery(p)) + query.uopClass := uopClass + query.stid := row.stid + query.isStore := row.isStore + OooIexIssueBlockMatrix.reasons(p, io.issuePolicy, domain, query) } + val physicalCapabilities = VecInit(profile.pickerFunctions.map( + _.capabilities.U(OooIexDomainCapability.Count.W))) for (left <- 0 until p.iexIssueDomainCount; right <- left + 1 until p.iexIssueDomainCount) { - val projectionOverlap = VecInit((0 until p.iqClassCount).map { - classIndex => - (io.pickBankEnables(left)(classIndex) & - io.pickBankEnables(right)(classIndex)).orR + val overlap = VecInit((0 until p.iqClassCount).map { classIndex => + (io.pickBankEnables(left)(classIndex) & + io.pickBankEnables(right)(classIndex)).orR }).asUInt.orR - if ((effectiveDomainCapabilities(left) & - effectiveDomainCapabilities(right)) != 0) { - assert(!projectionOverlap, - "IEX pickers may overlap class/bank only with disjoint capabilities") + if ((profile.pickerFunctions(left).capabilities & + profile.pickerFunctions(right).capabilities) != 0) { + assert(!overlap, + "picker projections may overlap only for disjoint capabilities") } } @@ -1623,38 +1250,32 @@ class OooIexIssue( for (domain <- 0 until p.iexIssueDomainCount) { val picker = pickers(domain) picker.io.classBankEnables := io.pickBankEnables(domain) - picker.io.stidBlock := Mux(recoveryFreeze, - UIntToOH(safeRecoveryStid, p.stidCount), 0.U) - picker.io.recoveryApply.valid := io.recoveryFire && recoveryPlan.valid - picker.io.recoveryApply.bits := recoveryPlan + picker.io.stidBlock := Mux(recoveryTargetActive, + UIntToOH(recoveryTargetStid, p.stidCount), 0.U) - val candidatePolicyBlocked = Wire(Vec(p.iqClassCount, + val policyBlocked = Wire(Vec(p.iqClassCount, Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, Bool())))) for (classIndex <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount; entry <- 0 until p.iqEntriesPerBank) { val row = scheduleRows(classIndex)(bank)(entry) - val sourcesReady = row.sources.map(source => + val ready = row.sources.map(source => !source.valid || source.ready || source.specReady).reduce(_ && _) - val loadCanceled = rowLoadCanceled(row) - val policyReasons = issuePolicyReasons( - domain, OooUopClass.all(classIndex), row) - candidatePolicyBlocked(classIndex)(bank)(entry) := + val reasons = policyReasons(domain, OooUopClass.all(classIndex), row) + policyBlocked(classIndex)(bank)(entry) := io.pickBankEnables(domain)(classIndex)(bank) && - slotState(classIndex)(bank)(entry) === - OooIexIssueSlotState.ResidentS3 && row.valid && - policyReasons.orR + slotState(classIndex)(bank)(entry) === + OooIexIssueSlotState.ResidentS3 && row.valid && reasons.orR val candidate = picker.io.candidates(classIndex)(bank)(entry) candidate.eligible := slotState(classIndex)(bank)(entry) === OooIexIssueSlotState.ResidentS3 && row.valid && !row.inFlight && - sourcesReady && !loadCanceled && - storeIssueAllowed(classIndex)(bank)(entry) && - OooIexDomainCapability.covers( - physicalDomainCapabilities(domain), - capabilityRows(classIndex)(bank)(entry)) && - !policyReasons.orR && - !(recoveryFreeze && row.stid === recoveryStid) + ready && !rowLoadCanceled(row) && + storeIssueAllowed(classIndex)(bank)(entry) && + OooIexDomainCapability.covers( + physicalCapabilities(domain), + capabilityRows(classIndex)(bank)(entry)) && + !reasons.orR && !targetFenced(row.stid) candidate.peId := row.peId candidate.stid := row.stid candidate.epoch := row.epoch @@ -1662,71 +1283,55 @@ class OooIexIssue( candidate.member := row.member candidate.reservation := row.reservation } - io.policyBlockedCount(domain) := - PopCount(candidatePolicyBlocked.toSeq.flatMap( - _.toSeq.flatMap(_.toSeq))) - - val pickToken = picker.io.pick.bits - val pickClassIndex = pickToken.query.uopClass.asUInt - val pickClassInRange = pickClassIndex < p.iqClassCount.U - val pickBankInRange = pickToken.query.bank < p.iqBankCount.U - val pickEntryInRange = pickToken.query.entry < p.iqEntriesPerBank.U - val safePickClass = Mux(pickClassInRange, pickClassIndex, 0.U) - val safePickBank = Mux(pickBankInRange, pickToken.query.bank, 0.U) - val safePickEntry = Mux(pickEntryInRange, pickToken.query.entry, 0.U) - val pickRow = scheduleRows(safePickClass)(safePickBank)(safePickEntry) - val pickResidentExact = pickClassInRange && pickBankInRange && - pickEntryInRange && - slotState(safePickClass)(safePickBank)(safePickEntry) === - OooIexIssueSlotState.ResidentS3 && pickRow.valid - val pickIdentityExact = pickToken.candidate.peId === pickRow.peId && - pickToken.candidate.stid === pickRow.stid && - pickToken.candidate.epoch === pickRow.epoch && - pickToken.candidate.transactionId === pickRow.transactionId && - sameMember(pickToken.candidate.member, pickRow.member) && - pickToken.candidate.reservation.asUInt === pickRow.reservation.asUInt && - pickToken.query.uopClass === pickRow.reservation.uopClass && - pickToken.query.bank === pickRow.reservation.bank && - pickToken.query.entry === pickRow.reservation.speculativeSlot - val pickNotInFlight = !pickRow.inFlight - val pickDomainExact = pickClassInRange && pickBankInRange && - io.pickBankEnables(domain)(safePickClass)(safePickBank) && - OooIexDomainCapability.covers( - physicalDomainCapabilities(domain), - capabilityRows(safePickClass)(safePickBank)(safePickEntry)) - val pickBaseClaimExact = pickResidentExact && pickIdentityExact && - pickDomainExact && pickNotInFlight && !rowLoadCanceled(pickRow) && - storeIssueAllowed(safePickClass)(safePickBank)(safePickEntry) && - !(recoveryFreeze && pickToken.candidate.stid === recoveryStid) - val pickPolicyReasons = issuePolicyReasons( - domain, pickToken.query.uopClass, pickRow) - val pickPolicyBlocked = pickBaseClaimExact && pickPolicyReasons.orR - val pickClaimExact = pickBaseClaimExact && !pickPolicyBlocked - - io.picks(domain).valid := picker.io.pick.valid && pickClaimExact - io.picks(domain).bits := pickToken - // A stale retained token is consumed as a typed rejection so corruption - // or an unexpected lifecycle race cannot wedge one physical domain. - picker.io.pick.ready := Mux( - pickClaimExact, io.picks(domain).ready, true.B) + io.policyBlockedCount(domain) := PopCount( + policyBlocked.toSeq.flatMap(_.toSeq.flatMap(_.toSeq))) + + val token = picker.io.pick.bits + val cls = token.query.uopClass.asUInt + val classInRange = cls < p.iqClassCount.U + val bankInRange = token.query.bank < p.iqBankCount.U + val entryInRange = token.query.entry < p.iqEntriesPerBank.U + val safeClass = Mux(classInRange, cls, 0.U) + val safeBank = Mux(bankInRange, token.query.bank, 0.U) + val safeEntry = Mux(entryInRange, token.query.entry, 0.U) + val row = selectEntry(scheduleRows(safeClass)(safeBank), safeEntry) + val residentExact = classInRange && bankInRange && entryInRange && + selectEntry(slotState(safeClass)(safeBank), safeEntry) === + OooIexIssueSlotState.ResidentS3 && row.valid + val identityExact = token.candidate.peId === row.peId && + token.candidate.stid === row.stid && + token.candidate.epoch === row.epoch && + token.candidate.transactionId === row.transactionId && + sameMember(token.candidate.member, row.member) && + token.candidate.reservation.asUInt === row.reservation.asUInt + val domainExact = classInRange && bankInRange && + io.pickBankEnables(domain)(safeClass)(safeBank) && + OooIexDomainCapability.covers(physicalCapabilities(domain), + selectEntry(capabilityRows(safeClass)(safeBank), safeEntry)) + val baseExact = residentExact && identityExact && domainExact && + !row.inFlight && !rowLoadCanceled(row) && + selectEntry(storeIssueAllowed(safeClass)(safeBank), safeEntry) && + !targetFenced(row.stid) + val reasons = policyReasons(domain, token.query.uopClass, row) + val claimExact = baseExact && !reasons.orR + io.picks(domain).valid := picker.io.pick.valid && claimExact + io.picks(domain).bits := token + picker.io.pick.ready := Mux(claimExact, io.picks(domain).ready, true.B) io.pickRejectedByDomain(domain).valid := - picker.io.pick.valid && !pickBaseClaimExact - io.pickRejectedByDomain(domain).bits.token := pickToken - io.pickRejectedByDomain(domain).bits.residentExact := pickResidentExact + picker.io.pick.valid && !baseExact + io.pickRejectedByDomain(domain).bits.token := token + io.pickRejectedByDomain(domain).bits.residentExact := residentExact io.pickRejectedByDomain(domain).bits.identityExact := - pickIdentityExact && pickDomainExact - io.pickRejectedByDomain(domain).bits.notInFlight := pickNotInFlight + identityExact && domainExact + io.pickRejectedByDomain(domain).bits.notInFlight := !row.inFlight io.pickMalformedByDomain(domain) := picker.io.malformed - io.pickRecoveryCanceledByDomain(domain) := picker.io.recoveryCanceled io.pickRecoveryBlockedByDomain(domain) := picker.io.blockedCanceled io.pickPolicyBlockedByDomain(domain).valid := - picker.io.pick.valid && pickPolicyBlocked - io.pickPolicyBlockedByDomain(domain).bits.token := pickToken - io.pickPolicyBlockedByDomain(domain).bits.reasonMask := - pickPolicyReasons - + picker.io.pick.valid && baseExact && reasons.orR + io.pickPolicyBlockedByDomain(domain).bits.token := token + io.pickPolicyBlockedByDomain(domain).bits.reasonMask := reasons when(io.picks(domain).fire) { - scheduleRows(safePickClass)(safePickBank)(safePickEntry).inFlight := + selectEntry(scheduleRows(safeClass)(safeBank), safeEntry).inFlight := true.B } @@ -1734,35 +1339,32 @@ class OooIexIssue( val retryClass = retry.reservation.uopClass.asUInt val retryClassInRange = retryClass < p.iqClassCount.U val retryBankInRange = retry.reservation.bank < p.iqBankCount.U - val retryEntryInRange = - retry.reservation.speculativeSlot < p.iqEntriesPerBank.U + val retryEntryInRange = retry.reservation.speculativeSlot < + p.iqEntriesPerBank.U val safeRetryClass = Mux(retryClassInRange, retryClass, 0.U) - val safeRetryBank = Mux(retryBankInRange, retry.reservation.bank, 0.U) - val safeRetryEntry = Mux( - retryEntryInRange, retry.reservation.speculativeSlot, 0.U) - val retryRow = scheduleRows(safeRetryClass)(safeRetryBank)(safeRetryEntry) + val safeRetryBank = Mux(retryBankInRange, + retry.reservation.bank, 0.U) + val safeRetryEntry = Mux(retryEntryInRange, + retry.reservation.speculativeSlot, 0.U) + val retryRow = selectEntry( + scheduleRows(safeRetryClass)(safeRetryBank), safeRetryEntry) val retryResidentExact = retryClassInRange && retryBankInRange && retryEntryInRange && - slotState(safeRetryClass)(safeRetryBank)(safeRetryEntry) === + selectEntry(slotState(safeRetryClass)(safeRetryBank), safeRetryEntry) === OooIexIssueSlotState.ResidentS3 && retryRow.valid val retryIdentityExact = sameMember(retry.member, retryRow.member) && retry.reservation.asUInt === retryRow.reservation.asUInt val retryDomainExact = retryClassInRange && io.pickBankEnables(domain)(safeRetryClass)(safeRetryBank) && - OooIexDomainCapability.covers( - physicalDomainCapabilities(domain), - capabilityRows(safeRetryClass)(safeRetryBank)(safeRetryEntry)) - val retryClaimsCurrentPick = io.picks(domain).fire && - safeRetryClass === safePickClass && safeRetryBank === safePickBank && - safeRetryEntry === safePickEntry && - sameMember(retry.member, pickToken.candidate.member) && - retry.reservation.asUInt === pickToken.candidate.reservation.asUInt - // A fail-closed P1/join rejection can return the exact claim on the same - // edge that its picker fires. The later retry assignment wins. - val retryWasInFlight = retryRow.inFlight || retryClaimsCurrentPick + OooIexDomainCapability.covers(physicalCapabilities(domain), + selectEntry(capabilityRows(safeRetryClass)(safeRetryBank), + safeRetryEntry)) + val sameCyclePick = io.picks(domain).fire && + safeRetryClass === safeClass && safeRetryBank === safeBank && + safeRetryEntry === safeEntry + val wasInFlight = retryRow.inFlight || sameCyclePick val retryExact = retryResidentExact && retryIdentityExact && - retryDomainExact && retryWasInFlight && - !(recoveryFreeze && retry.member.group.stid === recoveryStid) + retryDomainExact && wasInFlight && !targetFenced(retryRow.stid) io.pickRetryRejectedByDomain(domain).valid := io.pickRetries(domain).valid && !retryExact io.pickRetryRejectedByDomain(domain).bits.retry := retry @@ -1770,10 +1372,54 @@ class OooIexIssue( retryResidentExact io.pickRetryRejectedByDomain(domain).bits.identityExact := retryIdentityExact && retryDomainExact - io.pickRetryRejectedByDomain(domain).bits.wasInFlight := retryWasInFlight + io.pickRetryRejectedByDomain(domain).bits.wasInFlight := wasInFlight when(io.pickRetries(domain).valid && retryExact) { - scheduleRows(safeRetryClass)(safeRetryBank)(safeRetryEntry).inFlight := - false.B + selectEntry(scheduleRows(safeRetryClass)(safeRetryBank), + safeRetryEntry).inFlight := false.B + } + + for (stage <- 0 until OooIexP1I2Lane.LoadCancelStageCount) { + val canceled = io.loadCancelRetries(domain)(stage) + val canceledClass = canceled.bits.reservation.uopClass.asUInt + val canceledClassInRange = canceledClass < p.iqClassCount.U + val canceledBankInRange = + canceled.bits.reservation.bank < p.iqBankCount.U + val canceledEntryInRange = + canceled.bits.reservation.speculativeSlot < p.iqEntriesPerBank.U + val safeCanceledClass = Mux( + canceledClassInRange, canceledClass, 0.U) + val safeCanceledBank = Mux( + canceledBankInRange, canceled.bits.reservation.bank, 0.U) + val safeCanceledEntry = Mux( + canceledEntryInRange, + canceled.bits.reservation.speculativeSlot, 0.U) + val canceledRow = selectEntry( + scheduleRows(safeCanceledClass)(safeCanceledBank), safeCanceledEntry) + val canceledResidentExact = canceledClassInRange && + canceledBankInRange && canceledEntryInRange && + selectEntry(slotState(safeCanceledClass)(safeCanceledBank), + safeCanceledEntry) === + OooIexIssueSlotState.ResidentS3 && canceledRow.valid + val canceledIdentityExact = + sameMember(canceled.bits.member, canceledRow.member) && + canceled.bits.reservation.asUInt === + canceledRow.reservation.asUInt + val canceledDomainExact = canceledClassInRange && + io.pickBankEnables(domain)(safeCanceledClass)(safeCanceledBank) && + OooIexDomainCapability.covers( + physicalCapabilities(domain), + selectEntry(capabilityRows(safeCanceledClass)(safeCanceledBank), + safeCanceledEntry)) + val canceledExact = canceledResidentExact && + canceledIdentityExact && canceledDomainExact && canceledRow.inFlight + when(canceled.valid) { + assert(canceledExact, + "load-canceled private IEX state must return an exact in-flight IQ row") + } + when(canceled.valid && canceledExact) { + selectEntry(scheduleRows(safeCanceledClass)(safeCanceledBank), + safeCanceledEntry).inFlight := false.B + } } val query = io.queries(domain) @@ -1785,40 +1431,52 @@ class OooIexIssue( val safeQueryBank = Mux(queryBankInRange, query.bank, 0.U) val safeQueryEntry = Mux(queryEntryInRange, query.entry, 0.U) io.queryStates(domain) := - slotState(safeQueryClass)(safeQueryBank)(safeQueryEntry) - val queryPayloads = Wire(Vec(p.iqClassCount, + selectEntry(slotState(safeQueryClass)(safeQueryBank), safeQueryEntry) + val queryPayload = Wire(Vec(p.iqClassCount, Vec(p.iqBankCount, new OooIexPayloadSidecar(p)))) - for (uopClass <- 0 until p.iqClassCount; - bank <- 0 until p.iqBankCount) { - queryPayloads(uopClass)(bank) := - payloadRows(uopClass)(bank).read(safeQueryEntry) + for (queryClassIndex <- 0 until p.iqClassCount; + queryBank <- 0 until p.iqBankCount) { + queryPayload(queryClassIndex)(queryBank) := + payloadRows(queryClassIndex)(queryBank).read(safeQueryEntry) } - io.queryRows(domain).schedule := - scheduleRows(safeQueryClass)(safeQueryBank)(safeQueryEntry) + val querySchedule = Wire(new OooIexScheduleRow(p)) + querySchedule := + selectEntry(scheduleRows(safeQueryClass)(safeQueryBank), safeQueryEntry) + // The registered IQ row converges on exact file readiness at the clock + // edge below, but a P1 claim can join this query in the same cycle. Give + // that join the current generation-qualified view so it cannot retain an + // expired speculative-ready snapshot after the bypass window has closed. + for (sourceIndex <- 0 until p.maxSourceOperands) { + val source = querySchedule.sources(sourceIndex) + when(source.valid && residentExactReady(querySchedule, source)) { + source.ready := true.B + source.specReady := false.B + source.load := 0.U.asTypeOf(source.load) + } + } + io.queryRows(domain).schedule := querySchedule io.queryRows(domain).payload := - queryPayloads(safeQueryClass)(safeQueryBank) - val querySourcesReady = io.queryRows(domain).sources.map { source => - !source.valid || source.ready || source.specReady - }.reduce(_ && _) - val queryPolicyReason = issuePolicyReasons( + queryPayload(safeQueryClass)(safeQueryBank) + val queryReady = io.queryRows(domain).sources.map(source => + !source.valid || source.ready || source.specReady).reduce(_ && _) + val queryReasons = policyReasons( domain, query.uopClass, io.queryRows(domain).schedule) - io.queryPolicyReasons(domain) := queryPolicyReason + io.queryPolicyReasons(domain) := queryReasons io.queryPickables(domain) := queryClassInRange && queryBankInRange && queryEntryInRange && io.pickBankEnables(domain)(safeQueryClass)(safeQueryBank) && - OooIexDomainCapability.covers( - physicalDomainCapabilities(domain), - capabilityRows(safeQueryClass)(safeQueryBank)(safeQueryEntry)) && + OooIexDomainCapability.covers(physicalCapabilities(domain), + selectEntry(capabilityRows(safeQueryClass)(safeQueryBank), + safeQueryEntry)) && io.queryStates(domain) === OooIexIssueSlotState.ResidentS3 && io.queryRows(domain).valid && - !io.queryRows(domain).schedule.inFlight && querySourcesReady && + !io.queryRows(domain).schedule.inFlight && queryReady && !rowLoadCanceled(io.queryRows(domain).schedule) && - storeIssueAllowed(safeQueryClass)(safeQueryBank)(safeQueryEntry) && - !queryPolicyReason.orR && - !(recoveryFreeze && io.queryRows(domain).stid === recoveryStid) + selectEntry(storeIssueAllowed(safeQueryClass)(safeQueryBank), + safeQueryEntry) && + !queryReasons.orR && !targetFenced(io.queryRows(domain).stid) } - io.s1Occupied := s1Valid for (uopClass <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount) { io.boundEntries(uopClass)(bank) := PopCount(VecInit( (0 until p.iqEntriesPerBank).map { entry => @@ -1836,28 +1494,10 @@ class OooIexIssue( for (entry <- 0 until p.iqEntriesPerBank) { assert((slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.Free) === !scheduleRows(uopClass)(bank)(entry).valid, - "a physical IEX row must agree with its lifecycle state") - assert(!s1Claimed(uopClass)(bank)(entry) || - slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.Free, - "an S1 claim may reserve only an otherwise free physical IEX row") + "one IQ row lifecycle must agree with its valid bit") assert(!scheduleRows(uopClass)(bank)(entry).inFlight || - (scheduleRows(uopClass)(bank)(entry).valid && - slotState(uopClass)(bank)(entry) === - OooIexIssueSlotState.ResidentS3), - "only one resident S3 row may own speculative issue in-flight state") - assert(!scheduleRows(uopClass)(bank)(entry).storeOrder.valid || - (scheduleRows(uopClass)(bank)(entry).valid && - (scheduleRows(uopClass)(bank)(entry).reservation.uopClass === - OooUopClass.Agu || - scheduleRows(uopClass)(bank)(entry).reservation.uopClass === - OooUopClass.Std) && - scheduleRows(uopClass)(bank)(entry).storeOrder.logicalMember.group.valid && - scheduleRows(uopClass)(bank)(entry).storeOrder.logicalMember.bid.valid), - "a store issue-order key must belong to one exact resident logical store") - assert(!scheduleRows(uopClass)(bank)(entry).valid || - !scheduleRows(uopClass)(bank)(entry).isStore || - scheduleRows(uopClass)(bank)(entry).storeOrder.valid, - "every resident typed store must retain its logical issue-order key") + slotState(uopClass)(bank)(entry) === OooIexIssueSlotState.ResidentS3, + "only a resident S3 row may be in flight") } } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala b/chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala index d7b12226..4d095505 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala @@ -62,6 +62,8 @@ object OooIexIssueBlockMatrix { val stidInRange = query.stid < p.stidCount.U val safeStid = Mux(stidInRange, query.stid, 0.U) + def stidBit(mask: UInt): Bool = + if (p.stidCount == 1) mask(0) else mask(safeStid) val uopClass = query.uopClass val isLoadAddress = uopClass === OooUopClass.Agu && !query.isStore val isStorePath = query.isStore && @@ -70,21 +72,21 @@ object OooIexIssueBlockMatrix { result(OooIexIssueBlockReason.GlobalQuiesce) := policy.globalQuiesce result(OooIexIssueBlockReason.PowerThrottle) := policy.powerThrottle result(OooIexIssueBlockReason.ClassPressure) := stidInRange && - policy.classPressure(uopClass.asUInt)(safeStid) + stidBit(policy.classPressure(uopClass.asUInt)) result(OooIexIssueBlockReason.LoadQueuePressure) := stidInRange && - isLoadAddress && policy.loadQueuePressure(safeStid) + isLoadAddress && stidBit(policy.loadQueuePressure) result(OooIexIssueBlockReason.StoreWindowPressure) := stidInRange && - isStorePath && policy.storeWindowPressure(safeStid) + isStorePath && stidBit(policy.storeWindowPressure) result(OooIexIssueBlockReason.DomainStructural) := stidInRange && - policy.domainStructural(domain)(safeStid) + stidBit(policy.domainStructural(domain)) result(OooIexIssueBlockReason.LatencyReservation) := stidInRange && - policy.latencyReservation(domain)(safeStid) + stidBit(policy.latencyReservation(domain)) result(OooIexIssueBlockReason.ReflowReservation) := stidInRange && - policy.reflowReservation(domain)(safeStid) + stidBit(policy.reflowReservation(domain)) result(OooIexIssueBlockReason.SideDoorConflict) := stidInRange && - policy.sideDoorConflict(domain)(safeStid) + stidBit(policy.sideDoorConflict(domain)) result(OooIexIssueBlockReason.ResultBusReservation) := stidInRange && - policy.resultBusReservation(domain)(safeStid) + stidBit(policy.resultBusReservation(domain)) result.asUInt } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala b/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala index 2289aed5..40e047c3 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala @@ -2,28 +2,25 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPlan, RecoveryTargetIO} class OooIexIssueP1FabricIO( - val p: OooParams = OooParams(), + val core: CoreParams, + val p: OooParams, val requireStoreReservation: Boolean = false) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) + val dispatch = Flipped(new OOODispatchChannels(core)) val storeReserve = if (requireStoreReservation) Some( - Decoupled(new OooIexIssueRow(p))) else None + Vec(core.iex.stdPipes, Decoupled(new OooIexIssueRow(p)))) else None val wakeup = Input(Vec(p.iexWakeupPorts, Valid(new OooIexWakeup(p)))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) + val operandReadyBits = Input(new OooIexOperandReadyBits(p)) val releases = Flipped(Vec(p.iexReleaseWidth, Decoupled(new OooIexIssueRelease(p)))) def release = releases(0) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - def dispatchRelease = dispatchReleases(0) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) + val recovery = Flipped(new RecoveryTargetIO(core)) + val acceptedRecoveryApply = Valid(new RecoveryPlan(core)) val pickBankEnables = Input(Vec(p.iexIssueDomainCount, Vec(p.iqClassCount, UInt(p.iqBankCount.W)))) @@ -71,8 +68,6 @@ class OooIexIssueP1FabricIO( Valid(new OooIexPickClaimReject(p)))) val pickRetryRejected = Output(Vec(p.iexIssueDomainCount, Valid(new OooIexPickRetryReject(p)))) - val pickRecoveryCanceled = Output(Vec(p.iexIssueDomainCount, - Valid(new OooIexPickToken(p)))) val pickRecoveryBlocked = Output(Vec(p.iexIssueDomainCount, Valid(new OooIexPickToken(p)))) val pickPolicyBlocked = Output(Vec(p.iexIssueDomainCount, @@ -82,13 +77,10 @@ class OooIexIssueP1FabricIO( val policyBlockedCount = Output(Vec(p.iexIssueDomainCount, UInt(p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W))) - val s1Rejected = Output(Valid(new OooIexS1Reject(p))) val releaseRejecteds = Output(Vec(p.iexReleaseWidth, Valid(new OooIexReleaseReject(p)))) def releaseRejected = releaseRejecteds(0) - val recoveryRejected = Output(Valid(new OooIexRecoveryReject(p))) - val s1Occupied = Output(Vec(p.stidCount, Bool())) val i1Occupied = Output(Vec(p.iexIssueDomainCount, Bool())) val i2Occupied = Output(Vec(p.iexIssueDomainCount, Bool())) val lanesEmpty = Output(Bool()) @@ -110,33 +102,30 @@ class OooIexIssueP1FabricIO( * picker functions and asserts that topology before parallel claims. */ class OooIexIssueP1Fabric( - val p: OooParams = OooParams(), - val domainCapabilities: Seq[BigInt] = Seq.empty, + val core: CoreParams, val requireStoreReservation: Boolean = false) extends Module { - val io = IO(new OooIexIssueP1FabricIO(p, requireStoreReservation)) + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p = profile.params + val io = IO(new OooIexIssueP1FabricIO( + core, p, requireStoreReservation)) - val issue = Module(new OooIexIssue( - p, domainCapabilities, requireStoreReservation)) + val issue = Module(new OooIexIssue(core, requireStoreReservation)) val bridges = Seq.fill(p.iexIssueDomainCount)( Module(new OooIexPickP1Bridge(p))) val lanes = Seq.fill(p.iexIssueDomainCount)( - Module(new OooIexP1I2Lane(p))) + Module(new OooIexP1I2Lane(core, p))) - issue.io.s1 <> io.s1 + issue.io.dispatch <> io.dispatch if (requireStoreReservation) { io.storeReserve.get <> issue.io.storeReserve } else { - issue.io.storeReserve.ready := true.B + issue.io.storeReserve.foreach(_.ready := true.B) } issue.io.wakeup := io.wakeup issue.io.loadCancel := io.loadCancel + issue.io.operandReadyBits := io.operandReadyBits issue.io.releases <> io.releases - io.dispatchReleases <> issue.io.dispatchReleases - issue.io.ptagRecycle <> io.ptagRecycle - issue.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := issue.io.recoveryPrepareReady - io.recoveryPrepared := issue.io.recoveryPrepared - issue.io.recoveryFire := io.recoveryFire + issue.io.recovery <> io.recovery issue.io.pickBankEnables := io.pickBankEnables issue.io.issuePolicy := io.issuePolicy @@ -162,6 +151,7 @@ class OooIexIssueP1Fabric( io.readAttempts(domain) := lane.io.readAttempt io.readCapabilities(domain) := lane.io.readCapability + lane.io.operandReadyBits := io.operandReadyBits lane.io.readDecisionValid := io.readDecisionValid(domain) lane.io.readGrant := io.readGrant(domain) lane.io.sourceDataValid := io.sourceDataValid(domain) @@ -172,21 +162,20 @@ class OooIexIssueP1Fabric( lane.io.loadCancel := io.loadCancel lane.io.stageCancel <> io.stageCancels(domain) io.i2(domain) <> lane.io.i2 - lane.io.recoveryApply := issue.io.recoveryApplied + lane.io.recoveryApply := issue.io.acceptedRecoveryApply io.joinRejected(domain) := bridge.io.rejected io.p1Rejected(domain) := lane.io.p1Rejected io.readRejected(domain) := lane.io.readRejected io.recoveryCanceled(domain) := lane.io.recoveryCanceled io.loadCanceled(domain) := lane.io.loadCanceled + issue.io.loadCancelRetries(domain) := lane.io.loadCanceled io.stageCanceled(domain) := lane.io.stageCanceled io.stageCancelRejected(domain) := lane.io.stageCancelRejected io.pickMalformed(domain) := issue.io.pickMalformedByDomain(domain) io.pickRejected(domain) := issue.io.pickRejectedByDomain(domain) io.pickRetryRejected(domain) := issue.io.pickRetryRejectedByDomain(domain) - io.pickRecoveryCanceled(domain) := - issue.io.pickRecoveryCanceledByDomain(domain) io.pickRecoveryBlocked(domain) := issue.io.pickRecoveryBlockedByDomain(domain) io.pickPolicyBlocked(domain) := @@ -197,10 +186,8 @@ class OooIexIssueP1Fabric( io.i2Occupied(domain) := lane.io.i2Occupied } - io.s1Rejected := issue.io.s1Rejected io.releaseRejecteds := issue.io.releaseRejecteds - io.recoveryRejected := issue.io.recoveryRejected - io.s1Occupied := issue.io.s1Occupied + io.acceptedRecoveryApply := issue.io.acceptedRecoveryApply io.boundEntries := issue.io.boundEntries io.residentEntries := issue.io.residentEntries io.inFlightEntries := issue.io.inFlightEntries @@ -209,6 +196,6 @@ class OooIexIssueP1Fabric( val noBoundRows = issue.io.boundEntries.flatten.map(_ === 0.U).reduce(_ && _) val noResidentRows = issue.io.residentEntries.flatten.map(_ === 0.U).reduce(_ && _) - io.empty := io.lanesEmpty && !issue.io.s1Occupied.asUInt.orR && - noBoundRows && noResidentRows && !issue.io.recoveryBusy + io.empty := issue.io.recoveryIdle && io.lanesEmpty && + noBoundRows && noResidentRows } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Lane.scala b/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Lane.scala deleted file mode 100644 index 833cfa35..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Lane.scala +++ /dev/null @@ -1,160 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Valid} - -class OooIexIssueP1LaneIO(val p: OooParams = OooParams()) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) - val wakeup = Input(Vec(p.iexWakeupPorts, Valid(new OooIexWakeup(p)))) - val release = Flipped(Decoupled(new OooIexIssueRelease(p))) - val dispatchRelease = Decoupled(new OooDispatchRelease(p)) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - - val pickBankEnables = Input(Vec(p.iqClassCount, - UInt(p.iqBankCount.W))) - val issuePolicy = Input(new OooIexIssuePolicy(p)) - - val readAttempt = Valid(new OooIexI1ReadAttempt(p)) - val readDecisionValid = Input(Bool()) - val readGrant = Input(Bool()) - val sourceDataValid = Input(UInt(p.maxSourceOperands.W)) - val sourceData = Input(Vec(p.maxSourceOperands, UInt(p.pcWidth.W))) - val pcDataValid = Input(Bool()) - val pcData = Input(UInt(p.pcWidth.W)) - val bypass = Input(Vec(p.iexBypassPorts, - Valid(new OooIexBypassCandidate(p)))) - val loadCancel = Input(Vec(p.iexLoadCancelPorts, - Valid(new OooIexLoadCancel(p)))) - val stageCancel = Flipped(Vec(2, - Decoupled(new OooIexStageCancel(p)))) - val i2 = Decoupled(new OooIexI2Transaction(p)) - - val retryFeedback = Valid(new OooIexReadRepick(p)) - val joinRejected = Valid(new OooIexPickJoinReject(p)) - val p1Rejected = Valid(new OooIexP1Reject(p)) - val readRejected = Valid(new OooIexReadReject(p)) - val recoveryCanceled = Output(Vec(2, - Valid(new OooIexReadRepick(p)))) - val loadCanceled = Output(Vec(3, - Valid(new OooIexReadRepick(p)))) - val stageCanceled = Output(Vec(2, - Valid(new OooIexStageCancel(p)))) - val stageCancelRejected = Output(Vec(2, - Valid(new OooIexStageCancelReject(p)))) - - val pickMalformed = Valid(new OooIexPickReject(p)) - val pickRejected = Valid(new OooIexPickClaimReject(p)) - val pickRetryRejected = Valid(new OooIexPickRetryReject(p)) - val pickRecoveryCanceled = Valid(new OooIexPickToken(p)) - val pickRecoveryBlocked = Valid(new OooIexPickToken(p)) - val pickPolicyBlocked = Valid(new OooIexIssuePolicyBlockEvent(p)) - val queryPolicyReason = Output( - UInt(OooIexIssueBlockReason.Count.W)) - val policyBlockedCount = Output( - UInt(p.countWidth(p.iqClassCount * p.iqBankCount * - p.iqEntriesPerBank).W)) - val s1Rejected = Valid(new OooIexS1Reject(p)) - val releaseRejected = Valid(new OooIexReleaseReject(p)) - val recoveryRejected = Valid(new OooIexRecoveryReject(p)) - - val s1Occupied = Output(Vec(p.stidCount, Bool())) - val i1Occupied = Output(Bool()) - val i2Occupied = Output(Bool()) - val pipelineEmpty = Output(Bool()) - val boundEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val residentEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val inFlightEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) -} - -/** Canonical one-domain IQ → P1 → I1 → I2 composition. - * - * This module is the first executable integration seam: the IQ remains the - * only row/payload owner, the bridge performs one exact sidecar join, and the - * lane owns only pipeline residency. Every unsuccessful P1/I1 attempt feeds - * the exact member back to the IQ so it becomes pickable again. - */ -class OooIexIssueP1Lane(val p: OooParams = OooParams()) extends Module { - require(p.iexIssueDomainCount == 1, - "OooIexIssueP1Lane is the one-domain compatibility composition") - val io = IO(new OooIexIssueP1LaneIO(p)) - - val issue = Module(new OooIexIssue(p)) - issue.io.storeReserve.ready := true.B - val bridge = Module(new OooIexPickP1Bridge(p)) - val lane = Module(new OooIexP1I2Lane(p)) - - issue.io.s1 <> io.s1 - issue.io.wakeup := io.wakeup - issue.io.loadCancel := io.loadCancel - issue.io.release <> io.release - io.dispatchRelease <> issue.io.dispatchRelease - issue.io.ptagRecycle <> io.ptagRecycle - issue.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := issue.io.recoveryPrepareReady - io.recoveryPrepared := issue.io.recoveryPrepared - issue.io.recoveryFire := io.recoveryFire - issue.io.pickBankEnable := io.pickBankEnables - issue.io.issuePolicy := io.issuePolicy - - bridge.io.pick <> issue.io.pick - issue.io.query := bridge.io.query - bridge.io.queryState := issue.io.queryState - bridge.io.queryRow := issue.io.queryRow - lane.io.p1 <> bridge.io.p1 - - val retryConflict = bridge.io.repick.valid && lane.io.repick.valid - assert(!retryConflict, - "one IEX lane must never return two distinct exact retries in one cycle") - issue.io.pickRetry.valid := bridge.io.repick.valid || lane.io.repick.valid - issue.io.pickRetry.bits := Mux( - bridge.io.repick.valid, bridge.io.repick.bits, lane.io.repick.bits) - lane.io.repick.ready := true.B - io.retryFeedback := issue.io.pickRetry - - io.readAttempt := lane.io.readAttempt - lane.io.readDecisionValid := io.readDecisionValid - lane.io.readGrant := io.readGrant - lane.io.sourceDataValid := io.sourceDataValid - lane.io.sourceData := io.sourceData - lane.io.pcDataValid := io.pcDataValid - lane.io.pcData := io.pcData - lane.io.bypass := io.bypass - lane.io.loadCancel := io.loadCancel - lane.io.stageCancel <> io.stageCancel - io.i2 <> lane.io.i2 - lane.io.recoveryApply := issue.io.recoveryApplied - - io.joinRejected := bridge.io.rejected - io.p1Rejected := lane.io.p1Rejected - io.readRejected := lane.io.readRejected - io.recoveryCanceled := lane.io.recoveryCanceled - io.loadCanceled := lane.io.loadCanceled - io.stageCanceled := lane.io.stageCanceled - io.stageCancelRejected := lane.io.stageCancelRejected - io.pickMalformed := issue.io.pickMalformed - io.pickRejected := issue.io.pickRejected - io.pickRetryRejected := issue.io.pickRetryRejected - io.pickRecoveryCanceled := issue.io.pickRecoveryCanceled - io.pickRecoveryBlocked := issue.io.pickRecoveryBlocked - io.pickPolicyBlocked := issue.io.pickPolicyBlocked - io.queryPolicyReason := issue.io.queryPolicyReason - io.policyBlockedCount := issue.io.policyBlockedCount(0) - io.s1Rejected := issue.io.s1Rejected - io.releaseRejected := issue.io.releaseRejected - io.recoveryRejected := issue.io.recoveryRejected - io.s1Occupied := issue.io.s1Occupied - io.i1Occupied := lane.io.i1Occupied - io.i2Occupied := lane.io.i2Occupied - io.pipelineEmpty := lane.io.empty - io.boundEntries := issue.io.boundEntries - io.residentEntries := issue.io.residentEntries - io.inFlightEntries := issue.io.inFlightEntries -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala b/chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala index b6dd6854..f296878d 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala @@ -3,6 +3,9 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, Mux1H, PopCount, PriorityEncoderOH, UIntToOH, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.{PcBufferReadAddress, RecoveryPlan, + RecoveryTargetIO} /** One physical resource shared by otherwise independent picker functions. */ final case class OooIexSharedResourceConfig( @@ -14,8 +17,6 @@ object OooIexSharedResourceConfig { def validate( p: OooParams, resources: Seq[OooIexSharedResourceConfig]): Unit = { - require(resources.nonEmpty, - "shared IEX arbitration needs at least one declared resource") require(resources.map(_.name).forall(_.nonEmpty) && resources.map(_.name).distinct.length == resources.length, "shared IEX resources need nonempty unique names") @@ -60,6 +61,8 @@ class OooIexSharedResourceArbiterIO( class OooIexSharedResourceArbiter( val p: OooParams, val resources: Seq[OooIexSharedResourceConfig]) extends Module { + require(resources.nonEmpty, + "shared-resource arbiter hardware needs at least one shared resource") OooIexSharedResourceConfig.validate(p, resources) val io = IO(new OooIexSharedResourceArbiterIO(p, resources.length)) @@ -126,41 +129,34 @@ class OooIexSharedResourceArbiter( } class OooIexIssueReadFabricIO( - val p: OooParams = OooParams(), + val core: CoreParams, + val p: OooParams, val requireStoreReservation: Boolean = false) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) + val dispatch = Flipped(new OOODispatchChannels(core)) val storeReserve = if (requireStoreReservation) Some( - Decoupled(new OooIexIssueRow(p))) else None + Vec(core.iex.stdPipes, Decoupled(new OooIexIssueRow(p)))) else None val wakeup = Input(Vec(p.iexWakeupPorts, Valid(new OooIexWakeup(p)))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) val releases = Flipped(Vec(p.iexReleaseWidth, Decoupled(new OooIexIssueRelease(p)))) def release = releases(0) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - def dispatchRelease = dispatchReleases(0) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - - val pickBankEnables = Input(Vec(p.iexIssueDomainCount, - Vec(p.iqClassCount, UInt(p.iqBankCount.W)))) + val recovery = Flipped(new RecoveryTargetIO(core)) + val acceptedRecoveryApply = Valid(new RecoveryPlan(core)) val issuePolicy = Input(new OooIexIssuePolicy(p)) val stageCancels = Flipped(Vec(p.iexIssueDomainCount, Vec(2, Decoupled(new OooIexStageCancel(p))))) val pcReadRequests = Output(Vec(p.pcReadPorts, - Valid(new OooIexPcReadPortRequest(p)))) + Valid(new PcBufferReadAddress(core)))) val pcReadResponses = Input(Vec(p.pcReadPorts, Valid(UInt(p.pcWidth.W)))) val bypass = Input(Vec(p.iexBypassPorts, Valid(new OooIexBypassCandidate(p)))) val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) + val pClear = Flipped(Vec(p.pTagAllocationWidth, + Valid(new OooIexPFileKey(p)))) val pWrite = Flipped(Vec(p.iexPWritePorts, Valid(new OooIexPFileWrite(p)))) val pWriteReady = Output(Vec(p.iexPWritePorts, Bool())) @@ -212,11 +208,9 @@ class OooIexIssueReadFabricIO( val policyBlockedCount = Output(Vec(p.iexIssueDomainCount, UInt(p.countWidth(p.iqClassCount * p.iqBankCount * p.iqEntriesPerBank).W))) - val s1Rejected = Output(Valid(new OooIexS1Reject(p))) val releaseRejecteds = Output(Vec(p.iexReleaseWidth, Valid(new OooIexReleaseReject(p)))) def releaseRejected = releaseRejecteds(0) - val recoveryRejected = Output(Valid(new OooIexRecoveryReject(p))) val empty = Output(Bool()) val boundEntries = Output(Vec(p.iqClassCount, @@ -246,68 +240,35 @@ class OooIexIssueReadFabricIO( * operand-data injection remains on this composition. */ class OooIexIssueReadFabric( - val p: OooParams = OooParams(), - val domainCapabilities: Seq[BigInt] = Seq.empty, - val sharedResources: Seq[OooIexSharedResourceConfig] = Seq.empty, - val staticDomains: Seq[OooIexIssueDomainConfig] = Seq.empty, + val core: CoreParams, val requireStoreReservation: Boolean = false) extends Module { - if (staticDomains.nonEmpty) { - OooIexIssueDomainConfig.validate(p, staticDomains) - } - private val effectiveDomainCapabilities = - if (staticDomains.nonEmpty) staticDomains.map(_.capabilities) - else domainCapabilities - if (effectiveDomainCapabilities.nonEmpty) { - require(effectiveDomainCapabilities.length == p.iexIssueDomainCount && - effectiveDomainCapabilities.forall(mask => mask != 0 && - (mask & ~OooIexDomainCapability.ValidMask) == 0), - "IEX read fabric needs one valid capability mask per picker") - } - if (staticDomains.nonEmpty && domainCapabilities.nonEmpty) { - require(domainCapabilities == effectiveDomainCapabilities, - "static IEX domain capabilities must match the issue configuration") - } - if (sharedResources.nonEmpty) { - OooIexSharedResourceConfig.validate(p, sharedResources) - val declaredCapabilities = - if (effectiveDomainCapabilities.nonEmpty) effectiveDomainCapabilities - else Seq.fill(p.iexIssueDomainCount)( - OooIexDomainCapability.ValidMask) - sharedResources.foreach { resource => - val resourceMask = OooIexDomainCapability.mask(resource.capability) - require(resource.pickerFunctions.forall(picker => - (declaredCapabilities(picker) & resourceMask) != 0), - s"shared IEX resource ${resource.name} names an incapable picker") - } - } - val io = IO(new OooIexIssueReadFabricIO(p, requireStoreReservation)) + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p = profile.params + val staticDomains = profile.transferConfigs + val sharedResources = OooIexLinxPhysicalProfile.sharedReadResources(profile) + OooIexIssueDomainConfig.validate(p, staticDomains) + OooIexSharedResourceConfig.validate(p, sharedResources) + val io = IO(new OooIexIssueReadFabricIO( + core, p, requireStoreReservation)) - val issue = Module(new OooIexIssueP1Fabric(p, - effectiveDomainCapabilities, requireStoreReservation)) - val arbiter = Module(new OooIexAtomicReadArbiter(p)) + val issue = Module(new OooIexIssueP1Fabric( + core, requireStoreReservation)) + val arbiter = Module(new OooIexAtomicReadArbiter(core, p)) val operands = Module(new OooIexOperandFiles(p)) - issue.io.s1 <> io.s1 + issue.io.dispatch <> io.dispatch if (requireStoreReservation) { io.storeReserve.get <> issue.io.storeReserve.get } issue.io.wakeup := io.wakeup issue.io.loadCancel := io.loadCancel + issue.io.operandReadyBits := operands.io.readyBits issue.io.releases <> io.releases - io.dispatchReleases <> issue.io.dispatchReleases - issue.io.ptagRecycle <> io.ptagRecycle - issue.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := issue.io.recoveryPrepareReady - io.recoveryPrepared := issue.io.recoveryPrepared - issue.io.recoveryFire := io.recoveryFire - if (staticDomains.nonEmpty) { - for (picker <- 0 until p.iexIssueDomainCount) { - issue.io.pickBankEnables(picker) := VecInit( - staticDomains(picker).classBankEnables.map(_.U(p.iqBankCount.W))) - } - } else { - issue.io.pickBankEnables := io.pickBankEnables + issue.io.recovery <> io.recovery + for (picker <- 0 until p.iexIssueDomainCount) { + issue.io.pickBankEnables(picker) := VecInit( + staticDomains(picker).classBankEnables.map(_.U(p.iqBankCount.W))) } issue.io.issuePolicy := io.issuePolicy issue.io.stageCancels <> io.stageCancels @@ -330,10 +291,16 @@ class OooIexIssueReadFabric( io.sharedConflictMask := shared.io.conflicted io.sharedMalformedMask := shared.io.malformed } else { - io.sharedEligibleMask := VecInit( - issue.io.readAttempts.map(_.valid)).asUInt + val requestValid = VecInit(issue.io.readAttempts.map(_.valid)).asUInt + val capabilityExact = VecInit(issue.io.readCapabilities.map(capability => + capability.orR && PopCount(capability) === 1.U)).asUInt + for (picker <- 0 until p.iexIssueDomainCount) { + arbitratedAttempts(picker).valid := + issue.io.readAttempts(picker).valid && capabilityExact(picker) + } + io.sharedEligibleMask := requestValid & capabilityExact io.sharedConflictMask := 0.U - io.sharedMalformedMask := 0.U + io.sharedMalformedMask := requestValid & ~capabilityExact } arbiter.io.attempts := arbitratedAttempts for (domain <- 0 until p.iexIssueDomainCount) { @@ -371,6 +338,7 @@ class OooIexIssueReadFabric( io.uWriteFire := operands.io.uWriteFire io.readAttempts := issue.io.readAttempts + io.acceptedRecoveryApply := issue.io.acceptedRecoveryApply io.readCapabilities := issue.io.readCapabilities io.readSelectedMask := arbiter.io.selectedMask io.readDeniedMask := arbiter.io.deniedMask @@ -385,9 +353,7 @@ class OooIexIssueReadFabric( io.pickPolicyBlocked := issue.io.pickPolicyBlocked io.queryPolicyReasons := issue.io.queryPolicyReasons io.policyBlockedCount := issue.io.policyBlockedCount - io.s1Rejected := issue.io.s1Rejected io.releaseRejecteds := issue.io.releaseRejecteds - io.recoveryRejected := issue.io.recoveryRejected io.empty := issue.io.empty io.boundEntries := issue.io.boundEntries io.residentEntries := issue.io.residentEntries @@ -399,15 +365,3 @@ class OooIexIssueReadFabric( io.pProtocolError := operands.io.pProtocolError io.localProtocolError := operands.io.localProtocolError } - -/** Production Linx specialization with one authoritative physical profile. */ -class OooIexLinxIssueReadFabric( - val profile: OooIexPhysicalProfile = - OooIexLinxPhysicalProfile(), - override val requireStoreReservation: Boolean = false) - extends OooIexIssueReadFabric( - profile.params, - profile.transferConfigs.map(_.capabilities), - OooIexLinxPhysicalProfile.sharedReadResources(profile), - profile.transferConfigs, - requireStoreReservation) diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexLoadTerminalMetadata.scala b/chisel/src/main/scala/linxcore/ooo/OooIexLoadTerminalMetadata.scala deleted file mode 100644 index 210dff6b..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIexLoadTerminalMetadata.scala +++ /dev/null @@ -1,359 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, Valid, log2Ceil} - -import linxcore.common.{CoreParams, DestinationKind} -import linxcore.lsu.{LoadAttemptIdentity, LoadCanonicalRowIdentity, - LoadReplayDestination, LoadTerminalFault, ScalarLSULoadReturnEntry} - -/** Metadata installed atomically beside one canonical LIQ allocation. - * - * Address, miss, replay, data, and request residency remain solely in the - * scalar LSU. This sidecar retains only the typed OOO execution context that - * the architectural terminal sink must revalidate after the LIQ row has - * transferred into LRET/W1/W2. - */ -class OooIexLoadTerminalMetadataAlloc( - val p: OooParams, - val coreParams: CoreParams) extends Bundle { - val loadId = new LoadCanonicalRowIdentity - val attempt = new LoadAttemptIdentity - val load = new OooIexLoadGeneration(p) - val request = new OooIexAguLoadRequest(p) -} - -/** Exact replay-generation update for one still-live terminal sidecar. */ -class OooIexLoadTerminalMetadataRebind( - val p: OooParams, - val coreParams: CoreParams) extends Bundle { - val loadId = new LoadCanonicalRowIdentity - val currentAttempt = new LoadAttemptIdentity - val nextAttempt = new LoadAttemptIdentity - val currentLoad = new OooIexLoadGeneration(p) - val nextLoad = new OooIexLoadGeneration(p) -} - -class OooIexLoadTerminalMetadataReject( - val p: OooParams, - val coreParams: CoreParams) extends Bundle { - val loadId = new LoadCanonicalRowIdentity - val member = new RobMemberKey(p) - val rowIdExact = Bool() - val resident = Bool() - val producerExact = Bool() - val attemptExact = Bool() - val destinationExact = Bool() - val outcomeExact = Bool() -} - -class OooIexLoadTerminalMetadataEntry( - val p: OooParams, - val coreParams: CoreParams) extends Bundle { - val valid = Bool() - val loadId = new LoadCanonicalRowIdentity - val attempt = new LoadAttemptIdentity - val load = new OooIexLoadGeneration(p) - val request = new OooIexAguLoadRequest(p) -} - -class OooIexLoadTerminalMetadataIO( - val p: OooParams, - val coreParams: CoreParams) extends Bundle { - private val lsu = coreParams.scalarLsu - private def completionType = new ScalarLSULoadReturnEntry( - coreParams.robEntries, - lsu.addrWidth, - lsu.pcWidth, - lsu.dataWidth, - lsu.loadSizeWidth, - lsu.loadReturnPipeCount, - lsu.archRegWidth, - lsu.physRegWidth, - lsu.peIdWidth, - lsu.stidWidth, - lsu.tidWidth, - coreParams.lsidWidth) - - val flush = Input(Bool()) - val alloc = Flipped(Decoupled( - new OooIexLoadTerminalMetadataAlloc(p, coreParams))) - val rebind = Flipped(Decoupled( - new OooIexLoadTerminalMetadataRebind(p, coreParams))) - val completion = Flipped(Decoupled(completionType)) - val result = Decoupled(new OooIexLoadResult(p)) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryRejected = Output(Bool()) - val recoveryKilledMask = Output(UInt(lsu.liqEntries.W)) - val recoveryFire = Input(Bool()) - - val allocRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) - val rebindRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) - val completionRejected = Valid(new OooIexLoadTerminalMetadataReject(p, coreParams)) - val occupied = Output(UInt(log2Ceil(lsu.liqEntries + 1).W)) - val empty = Output(Bool()) -} - -/** Exact metadata-only owner joining canonical LSU completion to OOO terminal. - * - * A sidecar row remains occupied after LIQ resolution and is released only - * by the same `result.fire` that releases the LSU W2 transaction. Therefore - * the corresponding LIQ slot cannot be rebound to another producer while a - * delayed terminal transaction still names its old physical row lease. - */ -class OooIexLoadTerminalMetadata( - val p: OooParams = OooParams(), - val coreParams: CoreParams = CoreParams( - scalarLsu = linxcore.common.ScalarLsuParams( - stidCount = 4, loadReturnPipeCount = 3))) extends Module { - private val lsu = coreParams.scalarLsu - private val entriesCount = lsu.liqEntries - - require(lsu.stidCount == p.stidCount, - "OOO and canonical scalar LSU must share the STID population") - require(coreParams.robEntries >= p.robGroupsPerStid, - "canonical LSU ROB projection must cover every OOO RID slot") - require(p.pcWidth <= lsu.pcWidth && p.peIdWidth <= lsu.peIdWidth && - p.stidWidth <= lsu.stidWidth && p.archRegWidth <= lsu.archRegWidth && - p.pTagWidth <= lsu.physRegWidth, - "OOO terminal metadata must fit the canonical scalar LSU payload") - require(p.trapCauseWidth <= LoadTerminalFault.CauseWidth, - "OOO trap cause must fit the canonical load terminal fault payload") - LoadCanonicalRowIdentity.requireBridgeFits(entriesCount) - LoadAttemptIdentity.requireBridgeFits( - p.peIdWidth, - p.stidWidth, - p.nativeBidWidth, - p.ridSlotWidth, - p.brobGenerationWidth, - p.ridGenerationWidth, - p.robMemberIndexWidth, - p.residentGenerationWidth, - p.loadGenerationWidth) - - val io = IO(new OooIexLoadTerminalMetadataIO(p, coreParams)) - - private def zeroEntry: OooIexLoadTerminalMetadataEntry = { - val entry = Wire(new OooIexLoadTerminalMetadataEntry(p, coreParams)) - entry := 0.U.asTypeOf(entry) - entry.loadId := LoadCanonicalRowIdentity.none - entry.attempt := LoadAttemptIdentity.none - entry - } - - private def toAttempt(load: OooIexLoadGeneration): LoadAttemptIdentity = { - val attempt = Wire(new LoadAttemptIdentity) - attempt := 0.U.asTypeOf(attempt) - attempt.valid := load.valid - attempt.producer.valid := load.producer.group.valid - attempt.producer.peId := load.producer.group.peId - attempt.producer.stid := load.producer.group.stid - attempt.producer.nativeBidValid := load.producer.bid.valid - attempt.producer.nativeBid := load.producer.bid.value - attempt.producer.brobGeneration := load.producer.brobGeneration - attempt.producer.ridSlot := load.producer.group.ridSlot - attempt.producer.ridGeneration := load.producer.group.ridGeneration - attempt.producer.memberIndex := load.producer.memberIndex - attempt.producer.residentGeneration := load.producer.residentGeneration - attempt.generation := load.generation - attempt - } - - private def producerExact( - load: OooIexLoadGeneration, - request: OooIexAguLoadRequest): Bool = { - val row = request.execute.i2.row - load.valid && row.valid && row.member.group.valid && row.member.bid.valid && - load.producer.asUInt === row.member.asUInt && - row.member.group.peId === row.peId && - row.member.group.stid === row.stid && row.stid < p.stidCount.U - } - - private def projectedDestinationExact( - destination: LoadReplayDestination, - request: OooIexAguLoadRequest): Bool = { - val previous = request.execute.i2.row.payload.previousPDestinations(0) - destination.valid && destination.kind === DestinationKind.Gpr && - request.destination.valid && request.destination.kind === DestinationKind.Gpr && - destination.archTag === request.destination.atag && - destination.relTag === request.destination.relativeIndex && - destination.physTag === request.destination.ptag && - destination.oldPhysTag === previous.ptag - } - - private def sidecarExact( - entry: OooIexLoadTerminalMetadataEntry, - index: Int): Bool = - !entry.valid || ( - LoadCanonicalRowIdentity.wellFormed(entry.loadId, entriesCount) && - entry.loadId.valid && entry.loadId.slot === index.U && - LoadAttemptIdentity.equal(entry.attempt, toAttempt(entry.load)) && - producerExact(entry.load, entry.request)) - - val entries = RegInit(VecInit(Seq.fill(entriesCount)(zeroEntry))) - val fence = io.flush || io.recoveryPrepare.valid - - val allocIdWellFormed = - LoadCanonicalRowIdentity.wellFormed(io.alloc.bits.loadId, entriesCount) - val allocIdValid = allocIdWellFormed && io.alloc.bits.loadId.valid - val allocIndex = io.alloc.bits.loadId.slot(log2Ceil(entriesCount) - 1, 0) - val allocResident = allocIdValid && entries(allocIndex).valid - val allocProducerExact = producerExact(io.alloc.bits.load, io.alloc.bits.request) - val allocAttemptExact = LoadAttemptIdentity.equal( - io.alloc.bits.attempt, toAttempt(io.alloc.bits.load)) - val allocExact = allocIdValid && allocProducerExact && allocAttemptExact - io.alloc.ready := !fence && allocExact && !allocResident - - val completionId = io.completion.bits.payload.loadId - val completionIdWellFormed = - LoadCanonicalRowIdentity.wellFormed(completionId, entriesCount) - val completionIdValid = completionIdWellFormed && completionId.valid - val completionIndex = completionId.slot(log2Ceil(entriesCount) - 1, 0) - val completionEntry = entries(completionIndex) - val completionResident = completionIdValid && completionEntry.valid && - LoadCanonicalRowIdentity.equal(completionEntry.loadId, completionId) - val completionProducerExact = completionResident && - producerExact(completionEntry.load, completionEntry.request) && - io.completion.bits.peId === completionEntry.request.execute.i2.row.peId && - io.completion.bits.stid === completionEntry.request.execute.i2.row.stid && - io.completion.bits.tid === completionEntry.request.execute.i2.row.stid - val completionAttemptExact = completionResident && - LoadAttemptIdentity.equal(io.completion.bits.payload.attempt, - completionEntry.attempt) - val completionDestinationExact = completionResident && - projectedDestinationExact(io.completion.bits.payload.dst, - completionEntry.request) - val completionOutcomeExact = io.completion.bits.payload.valid && - (!io.completion.bits.payload.faultValid || - io.completion.bits.payload.data === 0.U) - val completionExact = completionIdValid && completionProducerExact && - completionAttemptExact && completionDestinationExact && - completionOutcomeExact - - io.result.valid := io.completion.valid && completionExact && !fence - io.result.bits := 0.U.asTypeOf(io.result.bits) - io.result.bits.agu := completionEntry.request - io.result.bits.load := completionEntry.load - io.result.bits.data := io.completion.bits.payload.data - io.result.bits.faultValid := io.completion.bits.payload.faultValid - io.result.bits.faultCause := io.completion.bits.payload.faultCause - io.completion.ready := io.result.ready && completionExact && !fence - - val rebindId = io.rebind.bits.loadId - val rebindIdWellFormed = - LoadCanonicalRowIdentity.wellFormed(rebindId, entriesCount) - val rebindIdValid = rebindIdWellFormed && rebindId.valid - val rebindIndex = rebindId.slot(log2Ceil(entriesCount) - 1, 0) - val rebindEntry = entries(rebindIndex) - val rebindResident = rebindIdValid && rebindEntry.valid && - LoadCanonicalRowIdentity.equal(rebindEntry.loadId, rebindId) - val rebindCurrentExact = rebindResident && - rebindEntry.load.asUInt === io.rebind.bits.currentLoad.asUInt && - LoadAttemptIdentity.equal(rebindEntry.attempt, - io.rebind.bits.currentAttempt) && - LoadAttemptIdentity.equal(io.rebind.bits.currentAttempt, - toAttempt(io.rebind.bits.currentLoad)) - val rebindNextExact = rebindResident && - io.rebind.bits.nextLoad.valid && - io.rebind.bits.nextLoad.producer.asUInt === rebindEntry.load.producer.asUInt && - io.rebind.bits.nextLoad.generation === rebindEntry.load.generation + 1.U && - LoadAttemptIdentity.equal(io.rebind.bits.nextAttempt, - toAttempt(io.rebind.bits.nextLoad)) - val completionTargetsRebind = io.completion.valid && completionIdValid && - LoadCanonicalRowIdentity.equal(completionId, rebindId) - val rebindExact = rebindCurrentExact && rebindNextExact - io.rebind.ready := !fence && rebindExact && !completionTargetsRebind - - val entryExact = VecInit(entries.zipWithIndex.map { - case (entry, index) => sidecarExact(entry, index) - }) - val recoveryPlanExact = io.recoveryPrepare.bits.valid && - io.recoveryPrepare.bits.oldHead.stid < p.stidCount.U && entryExact.asUInt.andR - val recoveryKill = VecInit(entries.map(entry => - entry.valid && recoveryPlanExact && - OooRecoveryMembership.memberKilled( - p, io.recoveryPrepare.bits, entry.load.producer))) - io.recoveryPrepareReady := io.recoveryPrepare.valid && recoveryPlanExact - io.recoveryRejected := io.recoveryPrepare.valid && !recoveryPlanExact - io.recoveryKilledMask := Mux(io.recoveryPrepareReady, - recoveryKill.asUInt, 0.U) - - private def rejectDefaults( - out: Valid[OooIexLoadTerminalMetadataReject]): Unit = { - out.valid := false.B - out.bits := 0.U.asTypeOf(out.bits) - out.bits.loadId := LoadCanonicalRowIdentity.none - } - rejectDefaults(io.allocRejected) - rejectDefaults(io.rebindRejected) - rejectDefaults(io.completionRejected) - - io.allocRejected.valid := io.alloc.valid && !fence && !io.alloc.ready - io.allocRejected.bits.loadId := io.alloc.bits.loadId - io.allocRejected.bits.member := io.alloc.bits.load.producer - io.allocRejected.bits.rowIdExact := allocIdValid - io.allocRejected.bits.resident := allocResident - io.allocRejected.bits.producerExact := allocProducerExact - io.allocRejected.bits.attemptExact := allocAttemptExact - io.allocRejected.bits.destinationExact := true.B - io.allocRejected.bits.outcomeExact := true.B - - io.rebindRejected.valid := io.rebind.valid && !fence && !io.rebind.ready - io.rebindRejected.bits.loadId := rebindId - io.rebindRejected.bits.member := io.rebind.bits.currentLoad.producer - io.rebindRejected.bits.rowIdExact := rebindIdValid - io.rebindRejected.bits.resident := rebindResident - io.rebindRejected.bits.producerExact := rebindCurrentExact - io.rebindRejected.bits.attemptExact := rebindNextExact - io.rebindRejected.bits.destinationExact := true.B - io.rebindRejected.bits.outcomeExact := !completionTargetsRebind - - io.completionRejected.valid := io.completion.valid && !fence && !completionExact - io.completionRejected.bits.loadId := completionId - io.completionRejected.bits.member := completionEntry.load.producer - io.completionRejected.bits.rowIdExact := completionIdValid - io.completionRejected.bits.resident := completionResident - io.completionRejected.bits.producerExact := completionProducerExact - io.completionRejected.bits.attemptExact := completionAttemptExact - io.completionRejected.bits.destinationExact := completionDestinationExact - io.completionRejected.bits.outcomeExact := completionOutcomeExact - - when(io.flush) { - for (index <- 0 until entriesCount) { - entries(index) := zeroEntry - } - }.elsewhen(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady, - "load terminal metadata recovery must share one accepted common fire") - for (index <- 0 until entriesCount) { - when(recoveryKill(index)) { - entries(index) := zeroEntry - } - } - }.otherwise { - when(io.result.fire) { - entries(completionIndex) := zeroEntry - } - when(io.rebind.fire) { - entries(rebindIndex).attempt := io.rebind.bits.nextAttempt - entries(rebindIndex).load := io.rebind.bits.nextLoad - } - when(io.alloc.fire) { - entries(allocIndex).valid := true.B - entries(allocIndex).loadId := io.alloc.bits.loadId - entries(allocIndex).attempt := io.alloc.bits.attempt - entries(allocIndex).load := io.alloc.bits.load - entries(allocIndex).request := io.alloc.bits.request - } - } - - io.occupied := PopCount(VecInit(entries.map(_.valid))) - io.empty := !VecInit(entries.map(_.valid)).asUInt.orR - - when(io.result.fire) { - assert(io.completion.fire, - "canonical LSU completion and OOO terminal result must share owner release") - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexLoadUnit.scala b/chisel/src/main/scala/linxcore/ooo/OooIexLoadUnit.scala deleted file mode 100644 index 768b10a0..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIexLoadUnit.scala +++ /dev/null @@ -1,291 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Cat, Decoupled, Fill, PopCount, PriorityEncoder, RRArbiter, - Valid} -import linxcore.common.{DestinationKind, OperandClass} - -object OooIexLoadResponseKind extends ChiselEnum { - val Hit, Miss, Fault = Value -} - -object OooIexLoadTrackState extends ChiselEnum { - val Free, RequestPending, AwaitingResponse, ResultPending = Value -} - -class OooIexLoadMemoryRequest(val p: OooParams = OooParams()) extends Bundle { - val stid = UInt(p.stidWidth.W) - val epoch = UInt(p.epochWidth.W) - val load = new OooIexLoadGeneration(p) - val address = UInt(p.pcWidth.W) - val accessBytes = UInt(4.W) -} - -class OooIexLoadMemoryResponse(val p: OooParams = OooParams()) extends Bundle { - val load = new OooIexLoadGeneration(p) - val kind = OooIexLoadResponseKind() - val data = UInt(p.pcWidth.W) - val faultCause = UInt(p.trapCauseWidth.W) -} - -/** Retained load return before atomic RF/wakeup/ROB publication. */ -class OooIexLoadResult(val p: OooParams = OooParams()) extends Bundle { - val agu = new OooIexAguLoadRequest(p) - val load = new OooIexLoadGeneration(p) - val data = UInt(p.pcWidth.W) - val faultValid = Bool() - val faultCause = UInt(p.trapCauseWidth.W) -} - -class OooIexLoadAcceptReject(val p: OooParams = OooParams()) extends Bundle { - val member = new RobMemberKey(p) - val noFreeEntry = Bool() - val duplicateProducer = Bool() - val identityExact = Bool() - val accessExact = Bool() - val destinationExact = Bool() -} - -class OooIexLoadResponseReject(val p: OooParams = OooParams()) extends Bundle { - val response = new OooIexLoadMemoryResponse(p) - val matchCount = UInt(p.countWidth(p.iexLoadTrackEntries).W) -} - -class OooIexLoadTrackEntry(val p: OooParams = OooParams()) extends Bundle { - val state = OooIexLoadTrackState() - val agu = new OooIexAguLoadRequest(p) - val load = new OooIexLoadGeneration(p) - val data = UInt(p.pcWidth.W) - val faultValid = Bool() - val faultCause = UInt(p.trapCauseWidth.W) -} - -class OooIexLoadUnitIO(val p: OooParams = OooParams()) extends Bundle { - val agu = Flipped(Decoupled(new OooIexAguLoadRequest(p))) - val memoryRequest = Decoupled(new OooIexLoadMemoryRequest(p)) - val memoryResponse = Flipped(Decoupled(new OooIexLoadMemoryResponse(p))) - val result = Decoupled(new OooIexLoadResult(p)) - - val speculativeWakeup = Valid(new OooIexWakeup(p)) - val bypass = Valid(new OooIexBypassCandidate(p)) - val cancel = Valid(new OooIexLoadCancel(p)) - - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - - val acceptRejected = Valid(new OooIexLoadAcceptReject(p)) - val responseRejected = Valid(new OooIexLoadResponseReject(p)) - val occupied = Output(UInt(p.countWidth(p.iexLoadTrackEntries).W)) -} - -/** Multi-entry scalar-load tracker with exact generation replay. - * - * AGU acceptance allocates one tracking entry and a producer-qualified load - * generation. Every memory-attempt fire emits one speculative wakeup. A hit - * retains extended data for bypass/result; a miss cancels that generation - * and retries under the same entry with a new generation; a fault cancels - * speculation and retains a precise terminal result. RF write, committed - * wakeup, ROB completion, and trace remain a later atomic sink. - */ -class OooIexLoadUnit(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooIexLoadUnitIO(p)) - - private val entries = RegInit(VecInit(Seq.fill(p.iexLoadTrackEntries)( - 0.U.asTypeOf(new OooIexLoadTrackEntry(p))))) - private val generation = RegInit(VecInit(Seq.fill(p.iexLoadTrackEntries)( - 0.U(p.loadGenerationWidth.W)))) - - private def memberKilled(member: RobMemberKey): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, member) - - private def destinationExact(destination: OooIexDestinationState): Bool = - destination.valid && (destination.kind === DestinationKind.Gpr || - destination.kind === DestinationKind.T || - destination.kind === DestinationKind.U) - - private def operandClass(destination: OooIexDestinationState): OperandClass.Type = - Mux(destination.kind === DestinationKind.Gpr, OperandClass.P, - Mux(destination.kind === DestinationKind.T, OperandClass.T, - Mux(destination.kind === DestinationKind.U, OperandClass.U, - OperandClass.Invalid))) - - private def extendedData(entry: OooIexLoadTrackEntry, raw: UInt): UInt = { - val bytes = entry.agu.accessBytes - val signed = entry.agu.signExtend - Mux(bytes === 1.U, - Mux(signed, Cat(Fill(p.pcWidth - 8, raw(7)), raw(7, 0)), - raw(7, 0).pad(p.pcWidth)), - Mux(bytes === 2.U, - Mux(signed, Cat(Fill(p.pcWidth - 16, raw(15)), raw(15, 0)), - raw(15, 0).pad(p.pcWidth)), - Mux(bytes === 4.U, - Mux(signed, Cat(Fill(p.pcWidth - 32, raw(31)), raw(31, 0)), - raw(31, 0).pad(p.pcWidth)), raw))) - } - - val validEntry = VecInit(entries.map(_.state =/= OooIexLoadTrackState.Free)) - val killedEntry = VecInit(entries.zip(validEntry).map { case (entry, valid) => - valid && memberKilled(entry.agu.execute.i2.row.member) - }) - val freeMask = VecInit(entries.map( - _.state === OooIexLoadTrackState.Free)).asUInt - val freeAvailable = freeMask.orR - val freeIndex = PriorityEncoder(freeMask) - val incomingMember = io.agu.bits.execute.i2.row.member - val duplicateProducer = entries.zip(validEntry).map { case (entry, valid) => - valid && !memberKilled(entry.agu.execute.i2.row.member) && - entry.load.producer.asUInt === incomingMember.asUInt - }.reduce(_ || _) - val incomingRow = io.agu.bits.execute.i2.row - val incomingIdentityExact = incomingRow.valid && - incomingMember.group.valid && incomingMember.bid.valid && - incomingRow.stid < p.stidCount.U && - incomingMember.group.stid === incomingRow.stid && - incomingMember.group.peId === incomingRow.peId - val incomingAccessExact = io.agu.bits.accessBytes === 1.U || - io.agu.bits.accessBytes === 2.U || io.agu.bits.accessBytes === 4.U || - io.agu.bits.accessBytes === 8.U - val incomingDestinationExact = destinationExact(io.agu.bits.destination) - io.agu.ready := freeAvailable && !duplicateProducer && - incomingIdentityExact && incomingAccessExact && incomingDestinationExact && - !memberKilled(incomingMember) - io.acceptRejected.valid := io.agu.valid && !io.agu.ready - io.acceptRejected.bits.member := incomingMember - io.acceptRejected.bits.noFreeEntry := !freeAvailable - io.acceptRejected.bits.duplicateProducer := duplicateProducer - io.acceptRejected.bits.identityExact := incomingIdentityExact - io.acceptRejected.bits.accessExact := incomingAccessExact - io.acceptRejected.bits.destinationExact := incomingDestinationExact - - val requestArbiter = Module(new RRArbiter( - new OooIexLoadMemoryRequest(p), p.iexLoadTrackEntries)) - for (index <- 0 until p.iexLoadTrackEntries) { - val entry = entries(index) - val request = requestArbiter.io.in(index) - request.valid := entry.state === OooIexLoadTrackState.RequestPending && - !killedEntry(index) - request.bits.stid := entry.agu.execute.i2.row.stid - request.bits.epoch := entry.agu.execute.i2.row.epoch - request.bits.load := entry.load - request.bits.address := entry.agu.address - request.bits.accessBytes := entry.agu.accessBytes - } - io.memoryRequest <> requestArbiter.io.out - - val responseMatch = VecInit(entries.zip(validEntry).map { - case (entry, valid) => valid && !memberKilled(entry.load.producer) && - entry.state === OooIexLoadTrackState.AwaitingResponse && - entry.load.asUInt === io.memoryResponse.bits.load.asUInt - }) - val responseMatchCount = PopCount(responseMatch) - val responseExact = responseMatchCount === 1.U - val responseIndex = PriorityEncoder(responseMatch) - io.memoryResponse.ready := true.B - io.responseRejected.valid := io.memoryResponse.fire && !responseExact - io.responseRejected.bits.response := io.memoryResponse.bits - io.responseRejected.bits.matchCount := responseMatchCount - - io.cancel.valid := io.memoryResponse.fire && responseExact && - io.memoryResponse.bits.kind =/= OooIexLoadResponseKind.Hit - io.cancel.bits.stid := entries(responseIndex).agu.execute.i2.row.stid - io.cancel.bits.epoch := entries(responseIndex).agu.execute.i2.row.epoch - io.cancel.bits.load := io.memoryResponse.bits.load - - io.speculativeWakeup := 0.U.asTypeOf(io.speculativeWakeup) - when(io.memoryRequest.fire) { - val entry = entries(requestArbiter.io.chosen) - val destination = entry.agu.destination - io.speculativeWakeup.valid := true.B - io.speculativeWakeup.bits.kind := OooIexWakeupKind.SpeculativeLoad - io.speculativeWakeup.bits.stid := entry.agu.execute.i2.row.stid - io.speculativeWakeup.bits.epoch := entry.agu.execute.i2.row.epoch - io.speculativeWakeup.bits.operandClass := operandClass(destination) - io.speculativeWakeup.bits.ptag := destination.ptag - io.speculativeWakeup.bits.ptagGeneration := destination.ptagGeneration - io.speculativeWakeup.bits.localTag := destination.localTag - io.speculativeWakeup.bits.localSequence := destination.localSequence - io.speculativeWakeup.bits.load := entry.load - } - - val resultArbiter = Module(new RRArbiter( - new OooIexLoadResult(p), p.iexLoadTrackEntries)) - for (index <- 0 until p.iexLoadTrackEntries) { - val entry = entries(index) - val result = resultArbiter.io.in(index) - result.valid := entry.state === OooIexLoadTrackState.ResultPending && - !killedEntry(index) - result.bits.agu := entry.agu - result.bits.load := entry.load - result.bits.data := entry.data - result.bits.faultValid := entry.faultValid - result.bits.faultCause := entry.faultCause - } - io.result <> resultArbiter.io.out - - io.bypass := 0.U.asTypeOf(io.bypass) - when(io.result.valid && !io.result.bits.faultValid) { - val result = io.result.bits - val destination = result.agu.destination - io.bypass.valid := true.B - io.bypass.bits.stid := result.agu.execute.i2.row.stid - io.bypass.bits.epoch := result.agu.execute.i2.row.epoch - io.bypass.bits.producer := result.load.producer - io.bypass.bits.operandClass := operandClass(destination) - io.bypass.bits.ptag := destination.ptag - io.bypass.bits.ptagGeneration := destination.ptagGeneration - io.bypass.bits.localTag := destination.localTag - io.bypass.bits.localSequence := destination.localSequence - io.bypass.bits.load := result.load - io.bypass.bits.stage := OooIexBypassStage.W1 - io.bypass.bits.data := result.data - } - - when(io.agu.fire) { - val nextGeneration = generation(freeIndex) + 1.U - val entry = entries(freeIndex) - entry := 0.U.asTypeOf(entry) - entry.state := OooIexLoadTrackState.RequestPending - entry.agu := io.agu.bits - entry.load.valid := true.B - entry.load.producer := incomingMember - entry.load.generation := nextGeneration - generation(freeIndex) := nextGeneration - } - - when(io.memoryRequest.fire) { - entries(requestArbiter.io.chosen).state := - OooIexLoadTrackState.AwaitingResponse - } - - when(io.memoryResponse.fire && responseExact) { - val entry = entries(responseIndex) - when(io.memoryResponse.bits.kind === OooIexLoadResponseKind.Miss) { - val nextGeneration = generation(responseIndex) + 1.U - entry.state := OooIexLoadTrackState.RequestPending - entry.load.generation := nextGeneration - generation(responseIndex) := nextGeneration - }.otherwise { - entry.state := OooIexLoadTrackState.ResultPending - entry.data := Mux( - io.memoryResponse.bits.kind === OooIexLoadResponseKind.Hit, - extendedData(entry, io.memoryResponse.bits.data), 0.U) - entry.faultValid := - io.memoryResponse.bits.kind === OooIexLoadResponseKind.Fault - entry.faultCause := io.memoryResponse.bits.faultCause - } - } - - when(io.result.fire) { - entries(resultArbiter.io.chosen).state := OooIexLoadTrackState.Free - } - - for (index <- 0 until p.iexLoadTrackEntries) { - when(killedEntry(index)) { - entries(index).state := OooIexLoadTrackState.Free - } - } - - assert(responseMatchCount <= 1.U, - "one memory response must match at most one exact load generation") - io.occupied := PopCount(validEntry) -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexOldestReadyPicker.scala b/chisel/src/main/scala/linxcore/ooo/OooIexOldestReadyPicker.scala index 76042b1c..dba8d67b 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexOldestReadyPicker.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexOldestReadyPicker.scala @@ -12,11 +12,8 @@ class OooIexOldestReadyPickerIO(val p: OooParams = OooParams()) val candidates = Input(Vec(p.iqClassCount, Vec(p.iqBankCount, Vec(p.iqEntriesPerBank, new OooIexPickCandidate(p))))) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val pick = Decoupled(new OooIexPickToken(p)) val malformed = Valid(new OooIexPickReject(p)) - val recoveryCanceled = Valid(new OooIexPickToken(p)) val blockedCanceled = Valid(new OooIexPickToken(p)) val held = Output(Bool()) val roundRobin = Output(UInt(p.stidWidth.W)) @@ -96,19 +93,17 @@ class OooIexOldestReadyPicker(val p: OooParams = OooParams()) } } - val heldKilled = heldValid && io.recoveryApply.valid && - io.recoveryApply.bits.valid && OooRecoveryMembership.memberKilled( - p, io.recoveryApply.bits, heldToken.candidate.member) + private def stidBlocked(stid: UInt): Bool = + if (p.stidCount == 1) io.stidBlock(0) else io.stidBlock(stid) + val safeHeldStid = Mux(heldValid, heldToken.candidate.stid, 0.U) - val heldBlocked = heldValid && io.stidBlock(safeHeldStid) - io.pick.valid := heldValid && !heldKilled && !heldBlocked + val heldBlocked = heldValid && stidBlocked(safeHeldStid) + io.pick.valid := heldValid && !heldBlocked io.pick.bits := heldToken val pickFire = io.pick.valid && io.pick.ready - io.recoveryCanceled.valid := heldKilled - io.recoveryCanceled.bits := heldToken io.blockedCanceled.valid := heldBlocked io.blockedCanceled.bits := heldToken - io.held := heldValid && !heldKilled && !heldBlocked + io.held := heldValid && !heldBlocked io.roundRobin := roundRobin val tokens = Wire(Vec(p.iqClassCount, Vec(p.iqBankCount, @@ -141,17 +136,14 @@ class OooIexOldestReadyPicker(val p: OooParams = OooParams()) candidate.reservation.bank === bank.U && candidate.reservation.writePort < p.iqWritePortsPerBank.U && candidate.reservation.speculativeSlot === entry.U - val killed = io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled( - p, io.recoveryApply.bits, candidate.member) val firedAgain = pickFire && sameExact(token, heldToken) - val stidBlocked = candidate.stid < p.stidCount.U && - io.stidBlock(candidate.stid) + val candidateStidBlocked = candidate.stid < p.stidCount.U && + stidBlocked(candidate.stid) selectable(classIndex)(bank)(entry) := io.classBankEnables(classIndex)(bank) && candidate.eligible && identityExact(classIndex)(bank)(entry) && reservationExact(classIndex)(bank)(entry) && - !stidBlocked && !killed && !firedAgain + !candidateStidBlocked && !firedAgain } val flatMalformed = Wire(Vec(candidateCount, Bool())) @@ -207,8 +199,12 @@ class OooIexOldestReadyPicker(val p: OooParams = OooParams()) heldToken.candidate.stid + 1.U, roundRobin) val rotated = Wire(Vec(p.stidCount, Valid(new OooIexPickToken(p)))) for (offset <- 0 until p.stidCount) { - val stid = (arbitrationBase + offset.U)(p.stidWidth - 1, 0) - rotated(offset) := perStidWinner(stid) + if (p.stidCount == 1) { + rotated(offset) := perStidWinner(0) + } else { + val stid = (arbitrationBase + offset.U)(p.stidWidth - 1, 0) + rotated(offset) := perStidWinner(stid) + } } val rotatedMask = VecInit(rotated.map(_.valid)).asUInt val selectedOH = PriorityEncoderOH(rotatedMask) @@ -218,7 +214,7 @@ class OooIexOldestReadyPicker(val p: OooParams = OooParams()) Mux1H(selectedOH, rotated.map(_.bits)), 0.U.asTypeOf(selectedToken)) - val canCapture = !heldValid || heldKilled || heldBlocked || pickFire + val canCapture = !heldValid || heldBlocked || pickFire when(canCapture) { heldValid := selectedValid when(selectedValid) { diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala b/chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala index d2a4187f..20e30734 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala @@ -3,7 +3,6 @@ package linxcore.ooo import chisel3._ import chisel3.util.{PopCount, Valid, log2Ceil} import linxcore.common.OperandClass -import linxcore.execute.ScalarGPRFile class OooIexPFileKey(val p: OooParams = OooParams()) extends Bundle { val stid = UInt(p.stidWidth.W) @@ -51,7 +50,8 @@ class OooIexOperandFilesIO(val p: OooParams = OooParams()) extends Bundle { Valid(UInt(p.pcWidth.W)))) val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) + val pClear = Flipped(Vec(p.pTagAllocationWidth, + Valid(new OooIexPFileKey(p)))) val pWrite = Flipped(Vec(p.iexPWritePorts, Valid(new OooIexPFileWrite(p)))) val pWriteReady = Output(Vec(p.iexPWritePorts, Bool())) @@ -81,12 +81,13 @@ class OooIexOperandFilesIO(val p: OooParams = OooParams()) extends Bundle { UInt(p.countWidth(p.uPhysRegs).W))) val pProtocolError = Output(Bool()) val localProtocolError = Output(Bool()) + val readyBits = Output(new OooIexOperandReadyBits(p)) } /** Canonical physical operand data owners for the formal OOO path. * - * P data and non-speculative readiness remain owned by the existing - * ScalarGPRFile. T and U are independent STID-local arrays whose allocation + * P data and non-speculative readiness are private to this canonical owner. + * T and U are independent STID-local arrays whose allocation * identity is the complete `{tag, sequence, epoch}` tuple. Allocation clear * installs a new identity as not-ready; only an exact committed write makes * its data readable. Recovery does not roll data back: a later allocation @@ -98,12 +99,13 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { private val tTagIndexWidth = log2Ceil(p.tPhysRegs) private val uTagIndexWidth = log2Ceil(p.uPhysRegs) - val pFile = Module(new ScalarGPRFile( + private val pFile = Module(new OooIexPDataFile( archRegs = p.pArchRegs, physRegs = p.pPhysRegs, dataWidth = p.pcWidth, readPorts = p.iexPReadPorts, - writePorts = p.iexPWritePorts)) + writePorts = p.iexPWritePorts, + clearPorts = p.pTagAllocationWidth)) val pOwnerValid = RegInit(VecInit(Seq.fill(p.pPhysRegs)(false.B))) val pOwnerStid = Reg(Vec(p.pPhysRegs, UInt(p.stidWidth.W))) @@ -120,7 +122,6 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val ownerExact = stidInRange && tagInRange && pOwnerValid(safeTag) && pOwnerStid(safeTag) === request.bits.stid && - pOwnerEpoch(safeTag) === request.bits.epoch && pOwnerGeneration(safeTag) === request.bits.source.ptagGeneration pFile.io.readValid(port) := request.valid && request.bits.source.operandClass === OperandClass.P && @@ -149,8 +150,8 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { pOwnerGeneration(safePInitTag) := io.pInit.bits.key.generation } - val invalidPClear = Wire(Vec(2, Bool())) - for (port <- 0 until 2) { + val invalidPClear = Wire(Vec(p.pTagAllocationWidth, Bool())) + for (port <- 0 until p.pTagAllocationWidth) { val key = io.pClear(port).bits val stidInRange = key.stid < p.stidCount.U val tagInRange = key.ptag < p.pPhysRegs.U @@ -164,12 +165,21 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { pOwnerGeneration(safeTag) := key.generation } } - val duplicatePClear = io.pClear(0).valid && io.pClear(1).valid && - io.pClear(0).bits.ptag === io.pClear(1).bits.ptag + val duplicatePClear = (0 until p.pTagAllocationWidth).flatMap { left => + (left + 1 until p.pTagAllocationWidth).map { right => + io.pClear(left).valid && io.pClear(right).valid && + io.pClear(left).bits.ptag === io.pClear(right).bits.ptag + } + }.foldLeft(false.B)(_ || _) pFile.io.clearValid := io.pClear(0).valid && !invalidPClear(0) pFile.io.clearTag := io.pClear(0).bits.ptag pFile.io.clearSecondValid := io.pClear(1).valid && !invalidPClear(1) pFile.io.clearSecondTag := io.pClear(1).bits.ptag + for (port <- 2 until p.pTagAllocationWidth) { + pFile.io.additionalClearValid(port - 2) := + io.pClear(port).valid && !invalidPClear(port) + pFile.io.additionalClearTag(port - 2) := io.pClear(port).bits.ptag + } val stalePWrite = Wire(Vec(p.iexPWritePorts, Bool())) val pWriteFire = Wire(Vec(p.iexPWritePorts, Bool())) @@ -206,11 +216,19 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { stalePWrite(port) := request.valid && !ownerExact } io.pReadyMask := pFile.io.readyMask - val pInitClearCollision = io.pInit.valid && (0 until 2).map { port => + for (tag <- 0 until p.pPhysRegs) { + io.readyBits.ptag(tag).valid := pOwnerValid(tag) + io.readyBits.ptag(tag).ready := pFile.io.readyMask(tag) + io.readyBits.ptag(tag).stid := pOwnerStid(tag) + io.readyBits.ptag(tag).epoch := pOwnerEpoch(tag) + io.readyBits.ptag(tag).generation := pOwnerGeneration(tag) + } + val pInitClearCollision = io.pInit.valid && + (0 until p.pTagAllocationWidth).map { port => io.pClear(port).valid && io.pInit.bits.key.ptag === io.pClear(port).bits.ptag }.foldLeft(false.B)(_ || _) - val pClearWriteCollision = (0 until 2).flatMap { clear => + val pClearWriteCollision = (0 until p.pTagAllocationWidth).flatMap { clear => (0 until p.iexPWritePorts).map { write => io.pClear(clear).valid && pWriteFire(write) && io.pClear(clear).bits.ptag === io.pWrite(write).bits.key.ptag @@ -250,6 +268,45 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val uData = Reg(Vec(p.stidCount, Vec(p.uPhysRegs, UInt(p.pcWidth.W)))) + // A single-STID profile must retain the full STID range check without + // elaborating a dynamic index into Vec(1). These accessors select the + // resident bank statically for that profile and keep the multi-STID shape + // unchanged. + private def tAllocatedAt(stid: UInt, tag: UInt): Bool = + if (p.stidCount == 1) tAllocated(0)(tag) else tAllocated(stid)(tag) + private def tReadyAt(stid: UInt, tag: UInt): Bool = + if (p.stidCount == 1) tReady(0)(tag) else tReady(stid)(tag) + private def tEpochAt(stid: UInt, tag: UInt): UInt = + if (p.stidCount == 1) tEpoch(0)(tag) else tEpoch(stid)(tag) + private def tSequenceAt(stid: UInt, tag: UInt): OooLocalSeq = + if (p.stidCount == 1) tSequence(0)(tag) else tSequence(stid)(tag) + private def tDataAt(stid: UInt, tag: UInt): UInt = + if (p.stidCount == 1) tData(0)(tag) else tData(stid)(tag) + + private def uAllocatedAt(stid: UInt, tag: UInt): Bool = + if (p.stidCount == 1) uAllocated(0)(tag) else uAllocated(stid)(tag) + private def uReadyAt(stid: UInt, tag: UInt): Bool = + if (p.stidCount == 1) uReady(0)(tag) else uReady(stid)(tag) + private def uEpochAt(stid: UInt, tag: UInt): UInt = + if (p.stidCount == 1) uEpoch(0)(tag) else uEpoch(stid)(tag) + private def uSequenceAt(stid: UInt, tag: UInt): OooLocalSeq = + if (p.stidCount == 1) uSequence(0)(tag) else uSequence(stid)(tag) + private def uDataAt(stid: UInt, tag: UInt): UInt = + if (p.stidCount == 1) uData(0)(tag) else uData(stid)(tag) + + for (stid <- 0 until p.stidCount; tag <- 0 until p.tPhysRegs) { + io.readyBits.ttag(stid)(tag).allocated := tAllocated(stid)(tag) + io.readyBits.ttag(stid)(tag).ready := tReady(stid)(tag) + io.readyBits.ttag(stid)(tag).epoch := tEpoch(stid)(tag) + io.readyBits.ttag(stid)(tag).sequence := tSequence(stid)(tag) + } + for (stid <- 0 until p.stidCount; tag <- 0 until p.uPhysRegs) { + io.readyBits.utag(stid)(tag).allocated := uAllocated(stid)(tag) + io.readyBits.utag(stid)(tag).ready := uReady(stid)(tag) + io.readyBits.utag(stid)(tag).epoch := uEpoch(stid)(tag) + io.readyBits.utag(stid)(tag).sequence := uSequence(stid)(tag) + } + private def sameLocalTarget( left: OooIexLocalFileKey, right: OooIexLocalFileKey): Bool = @@ -261,29 +318,43 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val tKey = io.tClear(port).bits val tStidInRange = tKey.stid < p.stidCount.U val tTagInRange = tKey.tag < p.tPhysRegs.U - val safeTStid = Mux(tStidInRange, tKey.stid, 0.U) val safeTTag = Mux(tTagInRange, tKey.tag, 0.U)(tTagIndexWidth - 1, 0) invalidTClear(port) := io.tClear(port).valid && !(tStidInRange && tTagInRange && tKey.sequence.valid) when(io.tClear(port).valid && !invalidTClear(port)) { - tAllocated(safeTStid)(safeTTag) := true.B - tReady(safeTStid)(safeTTag) := false.B - tEpoch(safeTStid)(safeTTag) := tKey.epoch - tSequence(safeTStid)(safeTTag) := tKey.sequence + if (p.stidCount == 1) { + tAllocated(0)(safeTTag) := true.B + tReady(0)(safeTTag) := false.B + tEpoch(0)(safeTTag) := tKey.epoch + tSequence(0)(safeTTag) := tKey.sequence + } else { + val safeTStid = Mux(tStidInRange, tKey.stid, 0.U) + tAllocated(safeTStid)(safeTTag) := true.B + tReady(safeTStid)(safeTTag) := false.B + tEpoch(safeTStid)(safeTTag) := tKey.epoch + tSequence(safeTStid)(safeTTag) := tKey.sequence + } } val uKey = io.uClear(port).bits val uStidInRange = uKey.stid < p.stidCount.U val uTagInRange = uKey.tag < p.uPhysRegs.U - val safeUStid = Mux(uStidInRange, uKey.stid, 0.U) val safeUTag = Mux(uTagInRange, uKey.tag, 0.U)(uTagIndexWidth - 1, 0) invalidUClear(port) := io.uClear(port).valid && !(uStidInRange && uTagInRange && uKey.sequence.valid) when(io.uClear(port).valid && !invalidUClear(port)) { - uAllocated(safeUStid)(safeUTag) := true.B - uReady(safeUStid)(safeUTag) := false.B - uEpoch(safeUStid)(safeUTag) := uKey.epoch - uSequence(safeUStid)(safeUTag) := uKey.sequence + if (p.stidCount == 1) { + uAllocated(0)(safeUTag) := true.B + uReady(0)(safeUTag) := false.B + uEpoch(0)(safeUTag) := uKey.epoch + uSequence(0)(safeUTag) := uKey.sequence + } else { + val safeUStid = Mux(uStidInRange, uKey.stid, 0.U) + uAllocated(safeUStid)(safeUTag) := true.B + uReady(safeUStid)(safeUTag) := false.B + uEpoch(safeUStid)(safeUTag) := uKey.epoch + uSequence(safeUStid)(safeUTag) := uKey.sequence + } } } @@ -328,17 +399,22 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val safeStid = Mux(stidInRange, key.stid, 0.U) val safeTag = Mux(tagInRange, key.tag, 0.U)(tTagIndexWidth - 1, 0) val ownerExact = stidInRange && tagInRange && key.sequence.valid && - tAllocated(safeStid)(safeTag) && - tEpoch(safeStid)(safeTag) === key.epoch && - tSequence(safeStid)(safeTag).asUInt === key.sequence.asUInt + tAllocatedAt(safeStid, safeTag) && + tEpochAt(safeStid, safeTag) === key.epoch && + tSequenceAt(safeStid, safeTag).asUInt === key.sequence.asUInt io.tWriteReady(port) := ownerExact staleTWrite(port) := request.valid && !ownerExact tWriteFire(port) := request.valid && request.bits.commit && io.tWriteReady(port) && !duplicateTWrite io.tWriteFire(port) := tWriteFire(port) when(tWriteFire(port)) { - tData(safeStid)(safeTag) := request.bits.data - tReady(safeStid)(safeTag) := true.B + if (p.stidCount == 1) { + tData(0)(safeTag) := request.bits.data + tReady(0)(safeTag) := true.B + } else { + tData(safeStid)(safeTag) := request.bits.data + tReady(safeStid)(safeTag) := true.B + } } } for (port <- 0 until p.iexUWritePorts) { @@ -349,17 +425,22 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val safeStid = Mux(stidInRange, key.stid, 0.U) val safeTag = Mux(tagInRange, key.tag, 0.U)(uTagIndexWidth - 1, 0) val ownerExact = stidInRange && tagInRange && key.sequence.valid && - uAllocated(safeStid)(safeTag) && - uEpoch(safeStid)(safeTag) === key.epoch && - uSequence(safeStid)(safeTag).asUInt === key.sequence.asUInt + uAllocatedAt(safeStid, safeTag) && + uEpochAt(safeStid, safeTag) === key.epoch && + uSequenceAt(safeStid, safeTag).asUInt === key.sequence.asUInt io.uWriteReady(port) := ownerExact staleUWrite(port) := request.valid && !ownerExact uWriteFire(port) := request.valid && request.bits.commit && io.uWriteReady(port) && !duplicateUWrite io.uWriteFire(port) := uWriteFire(port) when(uWriteFire(port)) { - uData(safeStid)(safeTag) := request.bits.data - uReady(safeStid)(safeTag) := true.B + if (p.stidCount == 1) { + uData(0)(safeTag) := request.bits.data + uReady(0)(safeTag) := true.B + } else { + uData(safeStid)(safeTag) := request.bits.data + uReady(safeStid)(safeTag) := true.B + } } } @@ -372,12 +453,12 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val safeTag = Mux(tagInRange, key.localTag, 0.U)(tTagIndexWidth - 1, 0) val exact = request.valid && key.operandClass === OperandClass.T && stidInRange && tagInRange && key.localSequence.valid && - tAllocated(safeStid)(safeTag) && tReady(safeStid)(safeTag) && - tEpoch(safeStid)(safeTag) === request.bits.epoch && - tSequence(safeStid)(safeTag).asUInt === key.localSequence.asUInt + tAllocatedAt(safeStid, safeTag) && tReadyAt(safeStid, safeTag) && + tEpochAt(safeStid, safeTag) === request.bits.epoch && + tSequenceAt(safeStid, safeTag).asUInt === key.localSequence.asUInt io.tReadResponses(port).valid := exact io.tReadResponses(port).bits := Mux(exact, - tData(safeStid)(safeTag), 0.U) + tDataAt(safeStid, safeTag), 0.U) } for (port <- 0 until p.iexUReadPorts) { val request = io.uReadRequests(port) @@ -388,12 +469,12 @@ class OooIexOperandFiles(val p: OooParams = OooParams()) extends Module { val safeTag = Mux(tagInRange, key.localTag, 0.U)(uTagIndexWidth - 1, 0) val exact = request.valid && key.operandClass === OperandClass.U && stidInRange && tagInRange && key.localSequence.valid && - uAllocated(safeStid)(safeTag) && uReady(safeStid)(safeTag) && - uEpoch(safeStid)(safeTag) === request.bits.epoch && - uSequence(safeStid)(safeTag).asUInt === key.localSequence.asUInt + uAllocatedAt(safeStid, safeTag) && uReadyAt(safeStid, safeTag) && + uEpochAt(safeStid, safeTag) === request.bits.epoch && + uSequenceAt(safeStid, safeTag).asUInt === key.localSequence.asUInt io.uReadResponses(port).valid := exact io.uReadResponses(port).bits := Mux(exact, - uData(safeStid)(safeTag), 0.U) + uDataAt(safeStid, safeTag), 0.U) } val tClearWriteCollision = (0 until p.tuAllocationWidth).flatMap { clear => diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexP1I2Lane.scala b/chisel/src/main/scala/linxcore/ooo/OooIexP1I2Lane.scala index 7be86894..d7b3eae2 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexP1I2Lane.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexP1I2Lane.scala @@ -1,10 +1,16 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, PopCount, Queue, Valid} +import chisel3.util.{Decoupled, log2Ceil, MuxLookup, PopCount, Queue, Valid} import linxcore.common.OperandClass +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} -class OooIexP1I2LaneIO(val p: OooParams = OooParams()) extends Bundle { +object OooIexP1I2Lane { + val LoadCancelStageCount = 3 +} + +class OooIexP1I2LaneIO(val core: CoreParams, val p: OooParams) extends Bundle { val p1 = Flipped(Decoupled(new OooIexP1Request(p))) /** One whole-uop request. The shared arbiter grants every requested P/T/U @@ -12,6 +18,7 @@ class OooIexP1I2LaneIO(val p: OooParams = OooParams()) extends Bundle { */ val readAttempt = Valid(new OooIexI1ReadAttempt(p)) val readCapability = Output(UInt(OooIexDomainCapability.Count.W)) + val operandReadyBits = Input(new OooIexOperandReadyBits(p)) val readDecisionValid = Input(Bool()) val readGrant = Input(Bool()) val sourceDataValid = Input(UInt(p.maxSourceOperands.W)) @@ -30,7 +37,7 @@ class OooIexP1I2LaneIO(val p: OooParams = OooParams()) extends Bundle { val stageCancel = Flipped(Vec(2, Decoupled(new OooIexStageCancel(p)))) val i2 = Decoupled(new OooIexI2Transaction(p)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + val recoveryApply = Flipped(Valid(new RecoveryPlan(core))) val repick = Decoupled(new OooIexReadRepick(p)) val p1Rejected = Valid(new OooIexP1Reject(p)) @@ -40,7 +47,8 @@ class OooIexP1I2LaneIO(val p: OooParams = OooParams()) extends Bundle { val recoveryCanceled = Output(Vec(2, Valid(new OooIexReadRepick(p)))) // P1, retained I1, and retained I2 cancellation diagnostics. Canonical IQ // inFlight/specReady mutation is driven directly by the same cancel event. - val loadCanceled = Output(Vec(3, Valid(new OooIexReadRepick(p)))) + val loadCanceled = Output(Vec(OooIexP1I2Lane.LoadCancelStageCount, + Valid(new OooIexReadRepick(p)))) val stageCanceled = Output(Vec(2, Valid(new OooIexStageCancel(p)))) val stageCancelRejected = Output(Vec(2, Valid(new OooIexStageCancelReject(p)))) @@ -64,8 +72,14 @@ class OooIexP1I2LaneIO(val p: OooParams = OooParams()) extends Bundle { * This lane owns only pipeline residency. The physical IQ, RFs, PC buffer, * picker, and execution pipe remain separate single owners. */ -class OooIexP1I2Lane(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooIexP1I2LaneIO(p)) +class OooIexP1I2Lane( + val core: CoreParams, + val p: OooParams) + extends Module { + def this(core: CoreParams) = + this(core, OooIexPhysicalProfile.fromCoreParams(core).params) + OooRecoveryMembership.requireCompatible(p, core) + val io = IO(new OooIexP1I2LaneIO(core, p)) val i1Valid = RegInit(false.B) val i1Request = Reg(new OooIexP1Request(p)) @@ -76,8 +90,10 @@ class OooIexP1I2Lane(val p: OooParams = OooParams()) extends Module { io.repick <> retryQueue.io.deq private def killedByRecovery(row: OooIexIssueRow): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && - OooRecoveryMembership.memberKilled(p, io.recoveryApply.bits, row.member) + io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + OooRecoveryMembership.memberKilled( + p, core, io.recoveryApply.bits, row.member) private def repickFrom(row: OooIexIssueRow): OooIexReadRepick = { val result = Wire(new OooIexReadRepick(p)) @@ -209,9 +225,11 @@ class OooIexP1I2Lane(val p: OooParams = OooParams()) extends Module { val speculativeExact = !requiresSpecBypass || (source.load.valid && candidate.bits.load.valid && source.load.asUInt === candidate.bits.load.asUInt) + val epochExact = source.operandClass === OperandClass.P || + candidate.bits.epoch === source.localEpoch candidate.valid && source.valid && candidate.bits.stid === i1Request.row.stid && - candidate.bits.epoch === i1Request.row.epoch && + epochExact && candidate.bits.producer.group.stid === i1Request.row.stid && speculativeExact && (pMatch || tMatch || uMatch) }) @@ -240,14 +258,51 @@ class OooIexP1I2Lane(val p: OooParams = OooParams()) extends Module { } } } + private def i1ExactFileReady(source: OooIexSourceState): Bool = { + def safeIndex(value: UInt, entries: Int, inRange: Bool): UInt = { + val width = math.max(1, log2Ceil(entries)) + val index = if (entries == 1) 0.U(width.W) else value(width - 1, 0) + Mux(inRange, index, 0.U(width.W)) + } + val stidInRange = i1Request.row.stid < p.stidCount.U + val safeStid = safeIndex(i1Request.row.stid, p.stidCount, stidInRange) + val ptagInRange = source.ptag < p.pPhysRegs.U + val safePtag = safeIndex(source.ptag, p.pPhysRegs, ptagInRange) + val ttagInRange = source.localTag < p.tPhysRegs.U + val safeTtag = safeIndex(source.localTag, p.tPhysRegs, ttagInRange) + val utagInRange = source.localTag < p.uPhysRegs.U + val safeUtag = safeIndex(source.localTag, p.uPhysRegs, utagInRange) + val pEntry = io.operandReadyBits.ptag(safePtag) + val tEntry = if (p.stidCount == 1) + io.operandReadyBits.ttag(0)(safeTtag) + else io.operandReadyBits.ttag(safeStid)(safeTtag) + val uEntry = if (p.stidCount == 1) + io.operandReadyBits.utag(0)(safeUtag) + else io.operandReadyBits.utag(safeStid)(safeUtag) + val pExact = ptagInRange && pEntry.valid && pEntry.ready && + pEntry.stid === i1Request.row.stid && + pEntry.generation === source.ptagGeneration + val tExact = stidInRange && ttagInRange && tEntry.allocated && + tEntry.ready && tEntry.epoch === source.localEpoch && + tEntry.sequence.asUInt === source.localSequence.asUInt + val uExact = stidInRange && utagInRange && uEntry.allocated && + uEntry.ready && uEntry.epoch === source.localEpoch && + uEntry.sequence.asUInt === source.localSequence.asUInt + MuxLookup(source.operandClass.asUInt, false.B)(Seq( + OperandClass.P.asUInt -> pExact, + OperandClass.T.asUInt -> tExact, + OperandClass.U.asUInt -> uExact)) + } + val i1FileReady = VecInit(i1Request.row.sources.map(i1ExactFileReady)) val i1SpecSourcesCovered = i1Request.row.sources.zipWithIndex.map { case (source, sourceIndex) => !source.valid || !source.specReady || source.ready || - i1BypassValid(sourceIndex) + i1BypassValid(sourceIndex) || i1FileReady(sourceIndex) }.reduce(_ && _) val i1RfSourceMask = VecInit(i1Request.row.sources.zipWithIndex.map { case (source, sourceIndex) => - val requiresSpecBypass = source.specReady && !source.ready + val requiresSpecBypass = source.specReady && !source.ready && + !i1FileReady(sourceIndex) source.valid && !i1BypassValid(sourceIndex) && !requiresSpecBypass }).asUInt val i1ParentIndexInRange = @@ -382,7 +437,10 @@ class OooIexP1I2Lane(val p: OooParams = OooParams()) extends Module { } i2Transaction.bypassMask := i1BypassValid.asUInt i2Transaction.pcValid := i1Request.pcReadRequired - i2Transaction.pc := Mux(i1Request.pcReadRequired, io.pcData, 0.U) + i2Transaction.pc := Mux( + i1Request.pcReadRequired, + io.pcData + i1PcToken.byteOffset, + 0.U) } when(i1WillClear) { diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexPDataFile.scala b/chisel/src/main/scala/linxcore/ooo/OooIexPDataFile.scala new file mode 100644 index 00000000..1c1e1447 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooIexPDataFile.scala @@ -0,0 +1,159 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.log2Ceil + +private class OooIexPDataWritePort(tagWidth: Int, dataWidth: Int) + extends Bundle { + val requestValid = Input(Bool()) + val commit = Input(Bool()) + val tag = Input(UInt(tagWidth.W)) + val data = Input(UInt(dataWidth.W)) + val ready = Output(Bool()) + val fire = Output(Bool()) + val blockedByHigherSameTag = Output(Bool()) +} + +private class OooIexPDataFileIO( + archRegs: Int, + physRegs: Int, + dataWidth: Int, + readPorts: Int, + writePorts: Int, + clearPorts: Int) + extends Bundle { + private val tagWidth = log2Ceil(physRegs) + + val readValid = Input(Vec(readPorts, Bool())) + val readTag = Input(Vec(readPorts, UInt(tagWidth.W))) + val readData = Output(Vec(readPorts, UInt(dataWidth.W))) + val readReady = Output(Vec(readPorts, Bool())) + + val initValid = Input(Bool()) + val initTag = Input(UInt(tagWidth.W)) + val initData = Input(UInt(dataWidth.W)) + val clearValid = Input(Bool()) + val clearTag = Input(UInt(tagWidth.W)) + val clearSecondValid = Input(Bool()) + val clearSecondTag = Input(UInt(tagWidth.W)) + val additionalClearValid = Input(Vec(clearPorts - 2, Bool())) + val additionalClearTag = Input(Vec(clearPorts - 2, UInt(tagWidth.W))) + + val write = Vec(writePorts, new OooIexPDataWritePort(tagWidth, dataWidth)) + + val readyMask = Output(UInt(physRegs.W)) + val clearWriteCollision = Output(Bool()) + val duplicateWriteCommit = Output(Bool()) + val protocolError = Output(Bool()) +} + +/** P physical-register data and non-speculative readiness owned by IEX. */ +private class OooIexPDataFile( + archRegs: Int, + physRegs: Int, + dataWidth: Int, + readPorts: Int, + writePorts: Int, + clearPorts: Int) + extends Module { + require(archRegs == 24, + "Linx scalar GPR namespace has 24 architectural registers") + require(physRegs > archRegs && (physRegs & (physRegs - 1)) == 0, + "physical GPR capacity must be a power of two above the architectural namespace") + require(dataWidth > 0, "GPR data width must be positive") + require(readPorts > 0, "GPR read-port count must be positive") + require(writePorts > 0, "GPR write-port count must be positive") + require(clearPorts >= 2, "GPR clear-port count must preserve both allocation ports") + + private val tagWidth = log2Ceil(physRegs) + val io = IO(new OooIexPDataFileIO( + archRegs, physRegs, dataWidth, readPorts, writePorts, clearPorts)) + + private val data = RegInit(VecInit(Seq.fill(physRegs)(0.U(dataWidth.W)))) + private val ready = RegInit(VecInit( + (0 until physRegs).map(index => (index < archRegs).B))) + + for (port <- 0 until readPorts) { + io.readData(port) := data(io.readTag(port)) + io.readReady(port) := !io.readValid(port) || ready(io.readTag(port)) + } + + val blockedByHigher = Wire(Vec(writePorts, Bool())) + val writeFire = Wire(Vec(writePorts, Bool())) + for (port <- 0 until writePorts) { + val higherSameTag = + if (port == 0) false.B + else VecInit((0 until port).map { higher => + io.write(higher).requestValid && + io.write(higher).tag === io.write(port).tag + }).asUInt.orR + blockedByHigher(port) := io.write(port).requestValid && higherSameTag + io.write(port).ready := !higherSameTag + writeFire(port) := io.write(port).requestValid && + io.write(port).commit && !higherSameTag + io.write(port).fire := writeFire(port) + io.write(port).blockedByHigherSameTag := blockedByHigher(port) + } + + val anyWriteFire = writeFire.asUInt.orR + val clearValid = Wire(Vec(clearPorts, Bool())) + val clearTag = Wire(Vec(clearPorts, UInt(tagWidth.W))) + clearValid(0) := io.clearValid + clearTag(0) := io.clearTag + clearValid(1) := io.clearSecondValid + clearTag(1) := io.clearSecondTag + for (port <- 2 until clearPorts) { + clearValid(port) := io.additionalClearValid(port - 2) + clearTag(port) := io.additionalClearTag(port - 2) + } + + val clearWriteCollision = (0 until clearPorts).flatMap { clear => + (0 until writePorts).map { write => + clearValid(clear) && writeFire(write) && + io.write(write).tag === clearTag(clear) + } + }.foldLeft(false.B)(_ || _) + val duplicateClear = (0 until clearPorts).flatMap { left => + (left + 1 until clearPorts).map { right => + clearValid(left) && clearValid(right) && + clearTag(left) === clearTag(right) + } + }.foldLeft(false.B)(_ || _) + val duplicateWriteCommit = + if (writePorts == 1) false.B + else VecInit((0 until writePorts).flatMap { left => + (left + 1 until writePorts).map { right => + writeFire(left) && writeFire(right) && + io.write(left).tag === io.write(right).tag + } + }).asUInt.orR + val commitWithoutRequest = VecInit((0 until writePorts).map { port => + io.write(port).commit && !io.write(port).requestValid + }).asUInt.orR + + when(io.initValid) { + data(io.initTag) := io.initData + ready(io.initTag) := true.B + } + for (port <- 0 until clearPorts) { + when(clearValid(port)) { + ready(clearTag(port)) := false.B + } + } + for (port <- 0 until writePorts) { + when(writeFire(port)) { + data(io.write(port).tag) := io.write(port).data + ready(io.write(port).tag) := true.B + } + } + + io.readyMask := ready.asUInt + io.clearWriteCollision := clearWriteCollision + io.duplicateWriteCommit := duplicateWriteCommit + io.protocolError := clearWriteCollision || duplicateClear || + duplicateWriteCommit || commitWithoutRequest || + (io.initValid && anyWriteFire) + + assert(!io.protocolError, + "P-file mutation requires unique committed write ownership") +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexPhysicalProfile.scala b/chisel/src/main/scala/linxcore/ooo/OooIexPhysicalProfile.scala index 4edb24d2..20bb51c7 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexPhysicalProfile.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexPhysicalProfile.scala @@ -1,6 +1,7 @@ package linxcore.ooo import chisel3._ +import linxcore.params.CoreParams /** Stable execution capabilities used to separate IQ residency from the * physical operation that a picker/pipe can accept. @@ -92,6 +93,8 @@ final case class OooIexPickerFunction( classBankEnables: Seq[BigInt], capabilities: BigInt, releasePort: Int) { + def hasCapability(capability: Int): Boolean = + (capabilities & (BigInt(1) << capability)) != 0 def transferConfig: OooIexIssueDomainConfig = OooIexIssueDomainConfig(classBankEnables, releasePort, name, capabilities) } @@ -158,10 +161,13 @@ final case class OooIexPhysicalProfile( for (left <- residencyOwners.indices; right <- left + 1 until residencyOwners.length) { - require(residencyOwners(left).classBankEnables - .zip(residencyOwners(right).classBankEnables) - .forall { case (leftMask, rightMask) => (leftMask & rightMask) == 0 }, - s"IEX residency owners $left and $right overlap one class/bank") + val capabilityOverlap = residencyOwners(left).capabilities & + residencyOwners(right).capabilities + require(capabilityOverlap == 0 || + residencyOwners(left).classBankEnables + .zip(residencyOwners(right).classBankEnables) + .forall { case (leftMask, rightMask) => (leftMask & rightMask) == 0 }, + s"IEX residency owners $left and $right overlap one class/bank/capability") } dispatchableClasses.foreach { classIndex => @@ -289,15 +295,14 @@ object OooIexLinxPhysicalProfile { def sharedReadResources( profile: OooIexPhysicalProfile): Seq[OooIexSharedResourceConfig] = { - val symmetricAluPickers = Seq( - profile.pickerIndex("alu2"), profile.pickerIndex("alu5")) - Seq( - OooIexSharedResourceConfig("divide", MultiCycleAlu, - symmetricAluPickers), - OooIexSharedResourceConfig("pointer-auth", PointerAuth, - symmetricAluPickers), - OooIexSharedResourceConfig("system", System, - symmetricAluPickers)) + Seq("divide" -> MultiCycleAlu, "pointer-auth" -> PointerAuth, + "system" -> System).flatMap { case (name, capability) => + val pickers = profile.pickerFunctions.zipWithIndex.collect { + case (picker, index) if picker.hasCapability(capability) => index + } + Option.when(pickers.length > 1)( + OooIexSharedResourceConfig(name, capability, pickers)) + } } def apply(base: OooParams = OooParams()): OooIexPhysicalProfile = { @@ -428,3 +433,157 @@ object OooIexLinxPhysicalProfile { profile } } + +object OooIexPhysicalProfile { + /** Derive the physical Issue Queue and Execution pipe topology directly + * from the canonical core parameters. This is a value projection only; + * the returned profile owns no hardware state. + */ + import OooIexDomainCapability._ + + /** Exact canonical-IEX projection into the private OOO mechanism record. + * + * `issueWidth` is the canonical S1 admission prefix: today that prefix is + * required to equal both WidthParams.issueWidth and the OOO dispatch + * prefix. It is deliberately not used as the number of physical picker + * functions; LDA and STA share each AGU residency owner but require + * distinct functions, while system/multicycle and CMD have independent + * owners. `scalarIssueEntries` is total scalar IQ capacity and is divided + * evenly across `scalarIssueBanks`. + */ + private def canonicalIexParams(core: CoreParams): OooParams = { + val iex = core.iex + require(iex.issueWidth == core.widths.issueWidth, + "canonical IEX issue width must match WidthParams") + require(iex.issueWidth == core.widths.dispatchWidth && + iex.issueWidth == core.ooo.dispatchWidth, + "canonical IEX admission must equal the OOO dispatch prefix") + require(iex.scalarIssueEntries % iex.scalarIssueBanks == 0, + "canonical scalar issue capacity must divide evenly across IQ banks") + require(iex.issueQueueClasses == OooParams.fromCoreParams(core).iqClassCount, + "canonical Issue Queue class count must match the physical profile") + require(iex.executionPipeKinds == OooIexDomainCapability.Count, + "canonical Execution pipe classification must cover every capability") + + val minimumRetireSourceDepth = { + val rows = core.ooo.robGroupsPerStid * + math.max(core.ooo.decodeWidth, core.ooo.renameWidth) + if (rows <= 1) 1 + else 1 << (32 - Integer.numberOfLeadingZeros(rows - 1)) + } + OooParams.fromCoreParams(core).copy( + iqBankCount = iex.scalarIssueBanks, + iqEntriesPerBank = iex.scalarIssueEntries / iex.scalarIssueBanks, + iexPReadPorts = iex.integerReadPorts, + iexPWritePorts = iex.integerWritePorts, + tuRetireSourceDepthPerStid = minimumRetireSourceDepth) + } + + private def bankMask(bankCount: Int, lane: Int, laneCount: Int): BigInt = + (0 until bankCount).filter(_ % laneCount == lane).foldLeft(BigInt(0))( + (mask, bank) => mask | (BigInt(1) << bank)) + + def fromCoreParams(core: CoreParams): OooIexPhysicalProfile = { + val iex = core.iex + require(iex.aluPipes == 2 && iex.bruPipes == 1 && iex.aguPipes == 2 && + iex.stdPipes == 2 && iex.systemMulticycleQueues == 1 && + iex.cmdIssueQueues == 1, + "IEX currently supports the canonical 2/1/2/2/1/1 Execution pipe topology") + + val base = canonicalIexParams(core) + val pickerCount = iex.aluPipes + iex.bruPipes + + 2 * iex.aguPipes + iex.systemMulticycleQueues + + iex.cmdIssueQueues + 1 // one floating/vector owner + val p = base.copy( + iexIssueDomainCount = pickerCount, + iexReleaseWidth = pickerCount) + val allBanks = (BigInt(1) << p.iqBankCount) - 1 + val aluClass = OooDispatchClass.Alu - 1 + val bruClass = OooDispatchClass.Bru - 1 + val aguClass = OooDispatchClass.Agu - 1 + val stdClass = OooDispatchClass.Std - 1 + val fsuClass = OooDispatchClass.Fsu - 1 + val sysClass = OooDispatchClass.Sys - 1 + val cmdClass = OooDispatchClass.Cmd - 1 + val boundaryClass = OooDispatchClass.Boundary - 1 + def classes(entries: (Int, BigInt)*): Seq[BigInt] = { + val result = Array.fill[BigInt](p.iqClassCount)(BigInt(0)) + entries.foreach { case (classIndex, mask) => + result(classIndex) = mask + } + result.toSeq + } + + val aluOwners = (0 until iex.aluPipes).map { lane => + OooIexResidencyOwner(s"alu$lane", + classes( + aluClass -> bankMask(p.iqBankCount, lane, iex.aluPipes), + stdClass -> bankMask(p.iqBankCount, lane, iex.stdPipes)), + mask(SimpleAlu, StoreData)) + } + val aguOwners = (0 until iex.aguPipes).map { lane => + OooIexResidencyOwner(s"agu$lane", + classes(aguClass -> bankMask(p.iqBankCount, lane, iex.aguPipes)), + mask(LoadAddress, StoreAddress)) + } + val bruOwners = (0 until iex.bruPipes).map { lane => + OooIexResidencyOwner(s"bru$lane", classes(bruClass -> allBanks), + mask(Branch)) + } + val systemOwners = (0 until iex.systemMulticycleQueues).map { lane => + OooIexResidencyOwner(s"sys$lane", + classes(aluClass -> allBanks, sysClass -> allBanks), + mask(MultiCycleAlu, System, PointerAuth)) + } + val fsuOwner = OooIexResidencyOwner("fsu0", classes(fsuClass -> allBanks), + mask(FloatingVector)) + val commandOwners = (0 until iex.cmdIssueQueues).map { lane => + OooIexResidencyOwner(s"cmd$lane", classes(cmdClass -> allBanks), + mask(EngineCommand)) + } + val owners = aluOwners ++ aguOwners ++ bruOwners ++ systemOwners ++ + Seq(fsuOwner) ++ commandOwners + + def picker( + name: String, + owner: OooIexResidencyOwner, + capabilities: BigInt, + releasePort: Int): OooIexPickerFunction = + OooIexPickerFunction(name, owner.name, name, owner.classBankEnables, + capabilities, releasePort) + + val pickerBuffer = scala.collection.mutable.ArrayBuffer.empty[ + OooIexPickerFunction] + def append(name: String, owner: OooIexResidencyOwner, + capabilities: BigInt): Unit = + pickerBuffer += picker(name, owner, capabilities, pickerBuffer.length) + aluOwners.foreach(owner => append(owner.name, owner, + mask(SimpleAlu, StoreData))) + aguOwners.foreach { owner => + append(s"${owner.name}-lda", owner, mask(LoadAddress)) + append(s"${owner.name}-sta", owner, mask(StoreAddress)) + } + bruOwners.foreach(owner => append(owner.name, owner, mask(Branch))) + systemOwners.foreach(owner => append(owner.name, owner, + mask(MultiCycleAlu, System, PointerAuth))) + append(fsuOwner.name, fsuOwner, mask(FloatingVector)) + commandOwners.foreach(owner => append(owner.name, owner, + mask(EngineCommand))) + val pickers = pickerBuffer.toSeq + require(pickers.length == pickerCount, + "canonical IEX topology must derive one exact picker count") + val lanes = pickers.map(entry => + OooIexExecutionLane(entry.executionLane, entry.capabilities)) + val physical = OooIexPhysicalProfile( + name = s"linx-w${core.widths.issueWidth}-issue-execution-v1", + params = p, + residencyOwners = owners, + pickerFunctions = pickers, + executionLanes = lanes, + dispatchableClasses = Set(aluClass, bruClass, aguClass, stdClass, + fsuClass, sysClass, cmdClass), + fastResolvedClasses = Set(boundaryClass)) + + physical + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexPipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexPipeline.scala index 1f95e47f..40655f76 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexPipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexPipeline.scala @@ -2,6 +2,8 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.{PcBufferReadAddress, RecoveryTargetIO} /** Public boundary of the canonical Linx P1/I1/I2/E1 issue pipeline. * @@ -10,36 +12,31 @@ import chisel3.util.{Decoupled, Valid} * IQ release independently from E1 capture. */ class OooIexPipelineIO( + val core: CoreParams, val p: OooParams, val requireStoreReservation: Boolean = false) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) + val dispatch = Flipped(new OOODispatchChannels(core)) val storeReserve = if (requireStoreReservation) Some( - Decoupled(new OooIexIssueRow(p))) else None + Vec(core.iex.stdPipes, Decoupled(new OooIexIssueRow(p)))) else None val wakeup = Input(Vec(p.iexWakeupPorts, Valid(new OooIexWakeup(p)))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - val ptagRecycle = Flipped(Decoupled(new OooPTagReturnBatch(p))) - - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooIexRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) + val recovery = Flipped(new RecoveryTargetIO(core)) val issuePolicy = Input(new OooIexIssuePolicy(p)) val stageCancels = Flipped(Vec(p.iexIssueDomainCount, Vec(2, Decoupled(new OooIexStageCancel(p))))) val pcReadRequests = Output(Vec(p.pcReadPorts, - Valid(new OooIexPcReadPortRequest(p)))) + Valid(new PcBufferReadAddress(core)))) val pcReadResponses = Input(Vec(p.pcReadPorts, Valid(UInt(p.pcWidth.W)))) val bypass = Input(Vec(p.iexBypassPorts, Valid(new OooIexBypassCandidate(p)))) val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) + val pClear = Flipped(Vec(p.pTagAllocationWidth, + Valid(new OooIexPFileKey(p)))) val pWrite = Flipped(Vec(p.iexPWritePorts, Valid(new OooIexPFileWrite(p)))) val pWriteReady = Output(Vec(p.iexPWritePorts, Bool())) @@ -87,10 +84,8 @@ class OooIexPipelineIO( Valid(new OooIexPickJoinReject(p)))) val pickPolicyBlocked = Output(Vec(p.iexIssueDomainCount, Valid(new OooIexIssuePolicyBlockEvent(p)))) - val s1Rejected = Output(Valid(new OooIexS1Reject(p))) val releaseRejecteds = Output(Vec(p.iexReleaseWidth, Valid(new OooIexReleaseReject(p)))) - val recoveryRejected = Output(Valid(new OooIexRecoveryReject(p))) val transferRejected = Output(Vec(p.iexIssueDomainCount, Valid(new OooIexE1TransferReject(p)))) val transferKilled = Output(Vec(p.iexIssueDomainCount, @@ -117,36 +112,31 @@ class OooIexPipelineIO( val localProtocolError = Output(Bool()) } -/** Canonical production composition from retained S1 through typed E1 lanes. +/** Canonical stage composition from retained IQ issue through typed E1 lanes. * * One physical profile constructs both children. The I2 handoff, exact IQ - * release, dispatch-slot return, and E1 capture therefore share one topology + * release and E1 capture therefore share one topology * and one ownership transaction by construction. */ class OooIexPipeline( - val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile(), + val core: CoreParams, val requireStoreReservation: Boolean = false) extends Module { + val profile = OooIexPhysicalProfile.fromCoreParams(core) val p = profile.params - val io = IO(new OooIexPipelineIO(p, requireStoreReservation)) + val io = IO(new OooIexPipelineIO(core, p, requireStoreReservation)) - val issue = Module(new OooIexLinxIssueReadFabric( - profile, requireStoreReservation)) + val issue = Module(new OooIexIssueReadFabric( + core, requireStoreReservation)) val transfer = Module(new OooIexLinxE1TransferFabric(profile)) - issue.io.s1 <> io.s1 + issue.io.dispatch <> io.dispatch if (requireStoreReservation) { io.storeReserve.get <> issue.io.storeReserve.get } issue.io.wakeup := io.wakeup issue.io.loadCancel := io.loadCancel - io.dispatchReleases <> issue.io.dispatchReleases - issue.io.ptagRecycle <> io.ptagRecycle - issue.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := issue.io.recoveryPrepareReady - io.recoveryPrepared := issue.io.recoveryPrepared - issue.io.recoveryFire := io.recoveryFire - issue.io.pickBankEnables := transfer.io.pickBankEnables + issue.io.recovery <> io.recovery issue.io.issuePolicy := io.issuePolicy issue.io.stageCancels <> io.stageCancels io.pcReadRequests := issue.io.pcReadRequests @@ -174,14 +164,7 @@ class OooIexPipeline( } issue.io.releases <> transfer.io.issueReleases transfer.io.loadCancel := io.loadCancel - transfer.io.recoveryApply.valid := io.recoveryFire - transfer.io.recoveryApply.bits := io.recoveryPrepare.bits - - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && issue.io.recoveryPrepareReady && - issue.io.recoveryPrepared.valid, - "IEX pipeline recovery must apply one held, prepared physical plan") - } + transfer.io.recoveryApply := issue.io.acceptedRecoveryApply io.staticBankEnables := transfer.io.pickBankEnables io.releaseDomains := transfer.io.releaseDomains @@ -200,9 +183,7 @@ class OooIexPipeline( io.p1Rejected := issue.io.p1Rejected io.joinRejected := issue.io.joinRejected io.pickPolicyBlocked := issue.io.pickPolicyBlocked - io.s1Rejected := issue.io.s1Rejected io.releaseRejecteds := issue.io.releaseRejecteds - io.recoveryRejected := issue.io.recoveryRejected io.transferRejected := transfer.io.rejected io.transferKilled := transfer.io.killed diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexStoreIssueFrontier.scala b/chisel/src/main/scala/linxcore/ooo/OooIexStoreIssueFrontier.scala index 32fd0f9d..4bf64d51 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexStoreIssueFrontier.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexStoreIssueFrontier.scala @@ -140,14 +140,18 @@ class OooIexStoreIssueFrontier( for (index <- 0 until candidateCount) { val candidate = io.candidates(index) val safeStid = Mux(candidate.stid < p.stidCount.U, candidate.stid, 0.U) - val exactFrontier = selected(safeStid).valid && - sameLogical(candidate.order, selected(safeStid).bits) + val frontier = if (p.stidCount == 1) selected(0) else selected(safeStid) + val malformed = if (p.stidCount == 1) + stidMalformed(0) + else stidMalformed(safeStid) + val exactFrontier = frontier.valid && + sameLogical(candidate.order, frontier.bits) val storeAllowed = activeStore(index) && candidateExact(index) && - !stidMalformed(safeStid) && exactFrontier + !malformed && exactFrontier io.allowed(index) := !activeStore(index) || storeAllowed io.blocked(index) := activeStore(index) && !storeAllowed io.malformed(index) := activeStore(index) && - (!candidateExact(index) || stidMalformed(safeStid)) + (!candidateExact(index) || malformed) } for (stid <- 0 until p.stidCount) { diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexStorePipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooIexStorePipeline.scala index 867b4c3c..6d9cce5a 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexStorePipeline.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexStorePipeline.scala @@ -6,6 +6,8 @@ import chisel3.util.{Cat, Decoupled, Fill, Mux1H, MuxLookup, PriorityEncoderOH, import linxcore.common.DestinationKind import linxcore.lsu.{STQPhysicalLease, STQStoreRequest, STQStoreType} +import linxcore.params.CoreParams +import linxcore.top.interface.RecoveryPlan class OooStqLeaseSet( val p: OooParams = OooParams(), @@ -29,13 +31,14 @@ class OooIexStoreExecute( } class OooIexStorePipelineIO( - val p: OooParams, + val core: CoreParams, val stqEntries: Int) extends Bundle { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params val sta = Flipped(Decoupled(new OooIexStoreExecute(p, stqEntries))) val std = Flipped(Decoupled(new OooIexStoreExecute(p, stqEntries))) val fill = Decoupled(new STQStoreRequest( - p.robGroupsPerStid, + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, @@ -47,8 +50,9 @@ class OooIexStorePipelineIO( memberIndexWidth = p.robMemberIndexWidth, residentGenerationWidth = p.residentGenerationWidth, leaseGenerationWidth = p.executeSlotGenerationWidth, - physicalStqEntries = stqEntries)) - val recoveryApply = Flipped(Valid(new OooResidencyRecoveryPlan(p))) + physicalStqEntries = stqEntries, + transactionIdWidth = p.transactionIdWidth)) + val recoveryApply = Flipped(Valid(new RecoveryPlan(core))) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) val staRejected = Output(Bool()) @@ -60,20 +64,22 @@ class OooIexStorePipelineIO( * each accepted half writes the generation-qualified canonical STQ row. */ class OooIexStorePipeline( - val p: OooParams = OooParams(), + val core: CoreParams, val stqEntries: Int = 16) extends Module { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + OooRecoveryMembership.requireCompatible(p, core) require(p.maxMemoryRequestsPerInstruction == 2, "store pipeline currently supports one or two beats") - val io = IO(new OooIexStorePipelineIO(p, stqEntries)) + val io = IO(new OooIexStorePipelineIO(core, stqEntries)) private val beatWidth = math.max(1, log2Ceil(p.maxMemoryRequestsPerInstruction)) private def killedByRecovery(value: OooIexStoreExecute): Bool = - io.recoveryApply.valid && io.recoveryApply.bits.valid && + io.recoveryApply.valid && OooRecoveryMembership.memberKilled( - p, io.recoveryApply.bits, value.execute.i2.row.member) + p, core, io.recoveryApply.bits, value.execute.i2.row.member) private def canceledByLoad(value: OooIexStoreExecute): Bool = io.loadCancel.map { cancel => @@ -88,15 +94,14 @@ class OooIexStorePipeline( }.reduce(_ || _) private def childMatches( - value: OooIexStoreExecute, - child: Int): Bool = { + value: OooIexStoreExecute): Bool = { val member = value.execute.i2.row.member val logical = value.lease.logicalMember member.group.asUInt === logical.group.asUInt && member.bid.asUInt === logical.bid.asUInt && member.brobGeneration === logical.brobGeneration && member.residentGeneration === logical.residentGeneration && - member.memberIndex === logical.memberIndex + child.U + member.memberIndex === logical.memberIndex } private def commonShape(value: OooIexStoreExecute): Bool = { @@ -125,7 +130,7 @@ class OooIexStorePipeline( private def staShape(value: OooIexStoreExecute): Bool = { val execute = value.execute val row = execute.i2.row - commonShape(value) && childMatches(value, 0) && + commonShape(value) && childMatches(value) && execute.ownerClass === OooUopClass.Agu && row.reservation.uopClass === OooUopClass.Agu && row.childIndex === 0.U && @@ -135,7 +140,7 @@ class OooIexStorePipeline( private def stdShape(value: OooIexStoreExecute): Bool = { val execute = value.execute val row = execute.i2.row - commonShape(value) && childMatches(value, 1) && + commonShape(value) && childMatches(value) && execute.ownerClass === OooUopClass.Std && row.reservation.uopClass === OooUopClass.Std && row.childIndex === 1.U && @@ -213,6 +218,7 @@ class OooIexStorePipeline( val fullLsid = value.lease.firstLsid + beat val fullStoreId = value.lease.firstStoreId + beat req := 0.U.asTypeOf(req) + req.transactionId := row.transactionId req.storeType := Mux(addressHalf, STQStoreType.Addr, STQStoreType.Data) req.peId := logical.group.peId req.stid := logical.group.stid @@ -225,8 +231,8 @@ class OooIexStorePipeline( req.gid.wrap := logical.group.ridGeneration(0) req.rid := req.gid req.lsId.valid := true.B - req.lsId.value := fullLsid(log2Ceil(p.robGroupsPerStid) - 1, 0) - req.lsId.wrap := fullLsid(log2Ceil(p.robGroupsPerStid)) + req.lsId.value := fullLsid(p.ridSlotWidth - 1, 0) + req.lsId.wrap := fullLsid(p.ridSlotWidth) req.lsIdFull := fullLsid req.storeIdFullValid := true.B req.storeIdFull := fullStoreId diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala b/chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala index 8c0c5003..4e9193d5 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala @@ -1,41 +1,49 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, Mux1H, OHToUInt, PopCount, RRArbiter, Valid, - log2Ceil} +import chisel3.util.{Decoupled, Mux1H, OHToUInt, PopCount, PriorityEncoder, + RRArbiter, UIntToOH, Valid, log2Ceil} import linxcore.lsu.{MDBConflictStoreProbe, STQDataBank, STQEntryBank, STQEntryBankRow, STQEntryStatus, STQLoadForwardQuery, STQLoadForwardResponse, STQLoadForwardingPipeline, STQStoreRequest, STQStoreType} +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan, + RecoveryPlanContract, RecoveryTargetIO, RobResolveTxn} class OooIexStoreStqFabricIO( - val p: OooParams, + val core: CoreParams, val stqEntries: Int) extends Bundle { - val reserve = Flipped(Decoupled(new OooIexIssueRow(p))) - val storeAddress = Flipped(Vec(2, + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + val reserve = Flipped(Vec(core.iex.stdPipes, + Decoupled(new OooIexIssueRow(p)))) + val storeAddress = Flipped(Vec(core.lsu.storePipes, Decoupled(new OooIexExecuteTransaction(p)))) - val storeData = Flipped(Vec(2, + val storeData = Flipped(Vec(core.lsu.storePipes, Decoupled(new OooIexExecuteTransaction(p)))) - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryFire = Input(Bool()) + val recovery = Flipped(new RecoveryTargetIO(core)) val recoveryApplied = Output(Bool()) val loadCancel = Input(Vec(p.iexLoadCancelPorts, Valid(new OooIexLoadCancel(p)))) - val loadForwardQuery = Flipped(Vec(3, Decoupled( + val loadForwardQuery = Flipped(Vec(core.lsu.loadPipes, Decoupled( new STQLoadForwardQuery( - p.robGroupsPerStid, stidWidth = p.stidWidth, + p.robIdentityGroupsPerStid, stidWidth = p.stidWidth, lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth)))) - val loadForwardResponse = Vec(3, Decoupled( + val loadForwardResponse = Vec(core.lsu.loadPipes, Decoupled( new STQLoadForwardResponse( - p.robGroupsPerStid, stqEntries, stidWidth = p.stidWidth, + p.robIdentityGroupsPerStid, stqEntries, stidWidth = p.stidWidth, lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth))) - val loadForwardOccupied = Output(UInt(3.W)) + val loadForwardOccupied = Output(UInt(core.lsu.loadPipes.W)) val lateStaProbe = Output(Valid(new MDBConflictStoreProbe( - p.robGroupsPerStid, peIdWidth = p.peIdWidth, + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, sizeWidth = 7, lsidWidth = p.lsidWidth))) + val lateStaCandidate = Output(Valid(new MDBConflictStoreProbe( + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, + stidWidth = p.stidWidth, tidWidth = p.stidWidth, + sizeWidth = 7, lsidWidth = p.lsidWidth))) + val lateStaPermit = Input(Bool()) val markCommitValid = Input(Bool()) val markCommitIndex = Input(UInt(log2Ceil(stqEntries).W)) @@ -50,11 +58,11 @@ class OooIexStoreStqFabricIO( val fillConflict = Output(Bool()) val recoveryFreeMask = Output(UInt(stqEntries.W)) val recoveryBlockedMask = Output(UInt(stqEntries.W)) - val recoveryPartialStoreCut = Output(Bool()) val recoveryRejected = Output(Bool()) + val completion = Decoupled(new RobResolveTxn(core)) val rows = Output(Vec(stqEntries, new STQEntryBankRow( - p.robGroupsPerStid, + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, @@ -65,7 +73,8 @@ class OooIexStoreStqFabricIO( brobGenerationWidth = p.brobGenerationWidth, memberIndexWidth = p.robMemberIndexWidth, residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth))) + leaseGenerationWidth = p.executeSlotGenerationWidth, + transactionIdWidth = p.transactionIdWidth))) val occupiedMask = Output(UInt(stqEntries.W)) val addrReadyMask = Output(UInt(stqEntries.W)) val dataReadyMask = Output(UInt(stqEntries.W)) @@ -82,17 +91,23 @@ class OooIexStoreStqFabricIO( * no pre-STQ address/data join state. */ class OooIexStoreStqFabric( - val p: OooParams = OooParams(), + val core: CoreParams, val stqEntries: Int = 16) extends Module { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + OooRecoveryMembership.requireCompatible(p, core) require(stqEntries > 1 && (stqEntries & (stqEntries - 1)) == 0, "STQ capacity must be a power of two greater than one") require(p.maxMemoryRequestsPerInstruction == 2, "static store fabric currently supports one or two store beats") - val io = IO(new OooIexStoreStqFabricIO(p, stqEntries)) - val reservation = Module(new OooStqReservationProjection(p, stqEntries)) - val recovery = Module(new OooStqRecoveryProjection(p, stqEntries)) - val stores = Seq.fill(2)(Module(new OooIexStorePipeline(p, stqEntries))) + require(core.lsu.storePipes == 2, + "the current store fabric owns exactly two STA and two STD pipes") + val io = IO(new OooIexStoreStqFabricIO(core, stqEntries)) + val reservations = Seq.fill(core.iex.stdPipes)( + Module(new OooStqReservationProjection(p, stqEntries))) + val recovery = Module(new OooStqRecoveryProjection(core, stqEntries)) + val stores = Seq.fill(core.lsu.storePipes)( + Module(new OooIexStorePipeline(core, stqEntries))) val addressFillArbiter = Module(new RRArbiter(chiselTypeOf( stores.head.io.fill.bits), stores.length)) val stq = Module(new STQEntryBank( @@ -101,7 +116,7 @@ class OooIexStoreStqFabric( stidWidth = p.stidWidth, tidWidth = p.stidWidth, mapQDepth = p.tuMapQDepthPerStid, - robEntries = p.robGroupsPerStid, + robEntries = p.robIdentityGroupsPerStid, lsidWidth = p.lsidWidth, nativeBidWidth = p.nativeBidWidth, ridGenerationWidth = p.ridGenerationWidth, @@ -109,14 +124,16 @@ class OooIexStoreStqFabric( memberIndexWidth = p.robMemberIndexWidth, residentGenerationWidth = p.residentGenerationWidth, leaseGenerationWidth = p.executeSlotGenerationWidth, - maxReserveBeats = p.maxMemoryRequestsPerInstruction)) + maxReserveBeats = core.iex.stdPipes * + p.maxMemoryRequestsPerInstruction, + transactionIdWidth = p.transactionIdWidth)) val dataBank = Module(new STQDataBank( entries = stqEntries, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, mapQDepth = p.tuMapQDepthPerStid, - robEntries = p.robGroupsPerStid, + robEntries = p.robIdentityGroupsPerStid, lsidWidth = p.lsidWidth, nativeBidWidth = p.nativeBidWidth, ridGenerationWidth = p.ridGenerationWidth, @@ -126,9 +143,9 @@ class OooIexStoreStqFabric( leaseGenerationWidth = p.executeSlotGenerationWidth, writePorts = stores.length)) val loadForward = Module(new STQLoadForwardingPipeline( - loadPipes = 3, + loadPipes = core.lsu.loadPipes, stqEntries = stqEntries, - robEntries = p.robGroupsPerStid, + robEntries = p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, @@ -142,84 +159,161 @@ class OooIexStoreStqFabric( leaseGenerationWidth = p.executeSlotGenerationWidth, tokenWidth = p.transactionIdWidth)) - val recoveryFence = io.recoveryPrepare.valid + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val retainedFreeMask = Reg(UInt(stqEntries.W)) + val retainedBlockedMask = Reg(UInt(stqEntries.W)) - reservation.io.inputValid := io.reserve.valid && !recoveryFence - reservation.io.input := io.reserve.bits - stq.io.reserveBatchValid := reservation.io.reserveValid - stq.io.reserveBatchMask := reservation.io.reserveMask - stq.io.reserveBatch := reservation.io.reserve - io.reserve.ready := !recoveryFence && reservation.io.reserveValid && - stq.io.reserveBatchReady - io.reserveAccepted := io.reserve.fire - io.reserveRejected := io.reserve.valid && reservation.io.rejected - - recovery.io.recoveryValid := io.recoveryPrepare.valid - recovery.io.recovery := io.recoveryPrepare.bits + val prepareShapeExact = + io.recovery.prepare.bits.phase === RecoveryPhase.Prepare && + io.recovery.prepare.bits.trigger.stid < p.stidCount.U && + RecoveryPlanContract.legalSuffixWindow(io.recovery.prepare.bits) + recovery.io.prepareValid := io.recovery.prepare.valid && prepareShapeExact + recovery.io.prepare := io.recovery.prepare.bits recovery.io.rows := stq.io.rows - val partialPivot = io.recoveryPrepare.bits.survivingPivotValid && - io.recoveryPrepare.bits.survivingPivotPhysicalMemberCount =/= 0.U && - io.recoveryPrepare.bits.survivingPivotPhysicalMemberCount < - io.recoveryPrepare.bits.pivotPhysicalMemberCount - val pivotStoreRows = VecInit(stq.io.rows.map { row => - val owner = row.exactOwner - val pivot = io.recoveryPrepare.bits.pivot - io.recoveryPrepare.valid && row.valid && owner.valid && - owner.nativeBidValid && pivot.group.valid && pivot.bid.valid && - owner.peId === pivot.group.peId && - owner.stid === pivot.group.stid && - owner.nativeBid === pivot.bid.value && - owner.brobGeneration === pivot.brobGeneration && - owner.ridSlot === pivot.group.ridSlot && - owner.ridGeneration === pivot.group.ridGeneration && - owner.memberIndex === pivot.memberIndex && - owner.residentGeneration === pivot.residentGeneration - }) - io.recoveryPartialStoreCut := partialPivot && pivotStoreRows.asUInt.orR - io.recoveryPrepareReady := io.recoveryPrepare.valid && - !recovery.io.rejected && !recovery.io.statusBlockedMask.orR && - !io.recoveryPartialStoreCut - val recoveryAccepted = io.recoveryFire && io.recoveryPrepareReady - io.recoveryApplied := recoveryAccepted - stq.io.exactRecoveryValid := recoveryAccepted - stq.io.exactRecoveryFreeMask := recovery.io.freeMask - io.recoveryFreeMask := Mux(io.recoveryPrepareReady, - recovery.io.freeMask, 0.U) - io.recoveryBlockedMask := recovery.io.statusBlockedMask - io.recoveryRejected := io.recoveryPrepare.valid && - !io.recoveryPrepareReady + val prepareAcceptable = prepareShapeExact && !recovery.io.rejected && + !recovery.io.statusBlockedMask.orR + io.recovery.prepare.ready := !recoveryPending && prepareAcceptable + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := retainedRecovery + + val terminalConflict = io.recovery.apply.valid && io.recovery.abort.valid + val matchingApply = recoveryPending && !terminalConflict && + io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val matchingAbort = recoveryPending && !terminalConflict && + io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + + when(io.recovery.prepare.fire) { + recoveryPending := true.B + preparedValid := true.B + retainedRecovery := io.recovery.prepare.bits + retainedFreeMask := recovery.io.freeMask + retainedBlockedMask := recovery.io.statusBlockedMask + }.elsewhen(matchingApply || matchingAbort) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + private def stidFenced(stid: UInt): Bool = { + val preparing = io.recovery.prepare.valid && prepareShapeExact && + io.recovery.prepare.bits.trigger.stid === stid + val pending = recoveryPending && retainedRecovery.trigger.stid === stid + preparing || pending + } + + val reserveLaneExact = Wire(Vec(io.reserve.length, Bool())) + for (lane <- io.reserve.indices) { + val reserveFence = stidFenced(io.reserve(lane).bits.stid) + reservations(lane).io.inputValid := !reserveFence + reservations(lane).io.input := io.reserve(lane).bits + reserveLaneExact(lane) := !io.reserve(lane).valid || + (!reserveFence && reservations(lane).io.reserveValid) + } + val anyReserve = io.reserve.map(_.valid).reduce(_ || _) + val allReserveExact = reserveLaneExact.asUInt.andR + stq.io.reserveBatchValid := anyReserve && allReserveExact + private val reserveSources = io.reserve.length * + p.maxMemoryRequestsPerInstruction + val reserveSourceValid = Wire(Vec(reserveSources, Bool())) + val reserveSourcePayload = Wire(Vec(reserveSources, + chiselTypeOf(stq.io.reserveBatch.head))) + for (lane <- io.reserve.indices; beat <- 0 until p.maxMemoryRequestsPerInstruction) { + val source = lane * p.maxMemoryRequestsPerInstruction + beat + reserveSourceValid(source) := io.reserve(lane).valid && + reservations(lane).io.reserveMask(beat) + reserveSourcePayload(source) := reservations(lane).io.reserve(beat) + } + val reserveCompactedValid = Wire(Vec(reserveSources, Bool())) + val reserveCompactedPayload = Wire(Vec(reserveSources, + chiselTypeOf(stq.io.reserveBatch.head))) + for (slot <- 0 until reserveSources) { + val selected = VecInit((0 until reserveSources).map { source => + val rank = if (source == 0) 0.U else + PopCount(reserveSourceValid.take(source)) + reserveSourceValid(source) && rank === slot.U + }) + reserveCompactedValid(slot) := selected.asUInt.orR + reserveCompactedPayload(slot) := 0.U.asTypeOf( + reserveCompactedPayload(slot)) + for (source <- 0 until reserveSources) { + when(selected(source)) { + reserveCompactedPayload(slot) := reserveSourcePayload(source) + } + } + } + stq.io.reserveBatchMask := reserveCompactedValid.asUInt + stq.io.reserveBatch := reserveCompactedPayload + io.reserve.foreach(_.ready := allReserveExact && stq.io.reserveBatchReady) + io.reserveAccepted := io.reserve.map(_.fire).reduce(_ || _) + io.reserveRejected := io.reserve.indices.map { lane => + io.reserve(lane).valid && reservations(lane).io.rejected + }.reduce(_ || _) + + io.recoveryApplied := matchingApply + stq.io.exactRecoveryValid := matchingApply + stq.io.exactRecoveryFreeMask := retainedFreeMask + io.recoveryFreeMask := Mux(recoveryPending, retainedFreeMask, + Mux(io.recovery.prepare.valid && prepareAcceptable, + recovery.io.freeMask, 0.U)) + io.recoveryBlockedMask := Mux(recoveryPending, retainedBlockedMask, + recovery.io.statusBlockedMask) + io.recoveryRejected := io.recovery.prepare.valid && + !io.recovery.prepare.ready stq.io.flush := 0.U.asTypeOf(stq.io.flush) stq.io.insertValid := false.B stq.io.insert := 0.U.asTypeOf(stq.io.insert) stq.io.reserveValid := false.B stq.io.reserve := 0.U.asTypeOf(stq.io.reserve) - stq.io.markCommitValid := io.markCommitValid && !recoveryFence + val markCommitRow = stq.io.rows(io.markCommitIndex) + val markCommitFence = markCommitRow.valid && + stidFenced(markCommitRow.stid) + stq.io.markCommitValid := io.markCommitValid && !markCommitFence stq.io.markCommitIndex := io.markCommitIndex io.markCommitAccepted := stq.io.markCommitAccepted stq.io.commitFreeValid := false.B stq.io.commitFreeIndex := 0.U - stq.io.commitFreeMaskValid := io.commitFreeMaskValid && !recoveryFence - stq.io.commitFreeMask := io.commitFreeMask + val recoveryTargetRows = VecInit(stq.io.rows.map { row => + row.valid && stidFenced(row.stid) + }).asUInt + val peerCommitFreeMask = io.commitFreeMask & ~recoveryTargetRows + stq.io.commitFreeMaskValid := io.commitFreeMaskValid && + peerCommitFreeMask.orR + stq.io.commitFreeMask := peerCommitFreeMask io.commitFreeAcceptedMask := stq.io.commitFreeAcceptedMask dataBank.io.residentRows := stq.io.rows - dataBank.io.hold := recoveryFence + dataBank.io.hold := false.B dataBank.io.clearMask := stq.io.exactRecoveryAcceptedMask | stq.io.commitFreeAcceptedMask stq.io.dataCompletions := dataBank.io.completions - loadForward.io.hold := recoveryFence - loadForward.io.flush := recoveryAccepted + loadForward.io.hold := false.B + loadForward.io.flush := false.B loadForward.io.metadataRows := stq.io.rows loadForward.io.dataRows := dataBank.io.rows - loadForward.io.queries <> io.loadForwardQuery - io.loadForwardResponse <> loadForward.io.responses + for (pipe <- 0 until core.lsu.loadPipes) { + val queryFence = stidFenced(io.loadForwardQuery(pipe).bits.stid) + loadForward.io.queries(pipe).valid := + io.loadForwardQuery(pipe).valid && !queryFence + loadForward.io.queries(pipe).bits := io.loadForwardQuery(pipe).bits + io.loadForwardQuery(pipe).ready := + loadForward.io.queries(pipe).ready && !queryFence + io.loadForwardResponse(pipe) <> loadForward.io.responses(pipe) + } io.loadForwardOccupied := loadForward.io.occupied private def exactOwnerMatches( row: STQEntryBankRow, execute: OooIexExecuteTransaction): Bool = { val member = execute.i2.row.member - val logicalIndex = member.memberIndex - execute.i2.row.childIndex row.exactOwner.valid && row.exactOwner.nativeBidValid && row.exactOwner.peId === member.group.peId && row.exactOwner.stid === member.group.stid && @@ -227,7 +321,7 @@ class OooIexStoreStqFabric( row.exactOwner.brobGeneration === member.brobGeneration && row.exactOwner.ridSlot === member.group.ridSlot && row.exactOwner.ridGeneration === member.group.ridGeneration && - row.exactOwner.memberIndex === logicalIndex && + row.exactOwner.memberIndex === member.memberIndex && row.exactOwner.residentGeneration === member.residentGeneration } @@ -237,7 +331,6 @@ class OooIexStoreStqFabric( val row = execute.i2.row val logical = Wire(new RobMemberKey(p)) logical := row.member - logical.memberIndex := row.member.memberIndex - row.childIndex lease := 0.U.asTypeOf(lease) lease.logicalMember := logical lease.requestCount := row.memoryOrder.requestCount @@ -267,6 +360,13 @@ class OooIexStoreStqFabric( lease.leases(beat).generation := Mux1H(matches, stq.io.rows.map(_.leaseGeneration)) } + val childShape = + (execute.ownerClass === OooUopClass.Agu && + row.reservation.uopClass === OooUopClass.Agu && + row.childIndex === 0.U) || + (execute.ownerClass === OooUopClass.Std && + row.reservation.uopClass === OooUopClass.Std && + row.childIndex === 1.U) val requestShape = row.valid && row.member.group.valid && row.member.bid.valid && row.memory.valid && row.memory.isStore && !row.memory.isLoad && row.memoryOrder.valid && @@ -274,7 +374,7 @@ class OooIexStoreStqFabric( !row.memoryOrder.isLoad && ((row.memoryOrder.requestCount === 1.U) || (row.memoryOrder.requestCount === 2.U)) && - row.childIndex <= 1.U && row.member.memberIndex >= row.childIndex + childShape val exact = requestShape && beatExact.asUInt.andR lease.valid := exact (lease, exact) @@ -283,63 +383,183 @@ class OooIexStoreStqFabric( for (index <- 0 until stores.length) { val (staLease, staLeaseExact) = leaseFor(io.storeAddress(index).bits) val (stdLease, stdLeaseExact) = leaseFor(io.storeData(index).bits) + val staRecoveryFence = stidFenced( + io.storeAddress(index).bits.i2.row.stid) + val stdRecoveryFence = stidFenced( + io.storeData(index).bits.i2.row.stid) stores(index).io.sta.valid := - io.storeAddress(index).valid && staLeaseExact && !recoveryFence + io.storeAddress(index).valid && staLeaseExact && !staRecoveryFence stores(index).io.sta.bits.execute := io.storeAddress(index).bits stores(index).io.sta.bits.lease := staLease io.storeAddress(index).ready := - !recoveryFence && staLeaseExact && stores(index).io.sta.ready + !staRecoveryFence && staLeaseExact && stores(index).io.sta.ready stores(index).io.std.valid := io.storeData(index).valid && stdLeaseExact && - !recoveryFence + !stdRecoveryFence stores(index).io.std.bits.execute := io.storeData(index).bits stores(index).io.std.bits.lease := stdLease io.storeData(index).ready := - !recoveryFence && stdLeaseExact && stores(index).io.std.ready + !stdRecoveryFence && stdLeaseExact && stores(index).io.std.ready io.leaseLookupRejected(index) := io.storeAddress(index).valid && !staLeaseExact io.leaseLookupRejected(2 + index) := io.storeData(index).valid && !stdLeaseExact - stores(index).io.recoveryApply.valid := recoveryAccepted - stores(index).io.recoveryApply.bits := io.recoveryPrepare.bits + stores(index).io.recoveryApply.valid := matchingApply + stores(index).io.recoveryApply.bits := io.recovery.apply.bits stores(index).io.loadCancel := io.loadCancel val dataFill = stores(index).io.fill.bits.storeType === STQStoreType.Data + val fillRecoveryFence = stidFenced(stores(index).io.fill.bits.stid) dataBank.io.writes(index).valid := stores(index).io.fill.valid && - dataFill && !recoveryFence + dataFill && !fillRecoveryFence dataBank.io.writes(index).bits := stores(index).io.fill.bits addressFillArbiter.io.in(index).valid := stores(index).io.fill.valid && - !dataFill && !recoveryFence + !dataFill && !fillRecoveryFence addressFillArbiter.io.in(index).bits := stores(index).io.fill.bits - stores(index).io.fill.ready := !recoveryFence && Mux(dataFill, + stores(index).io.fill.ready := !fillRecoveryFence && Mux(dataFill, dataBank.io.writes(index).ready, addressFillArbiter.io.in(index).ready) } - stq.io.fillValid := addressFillArbiter.io.out.valid && !recoveryFence + val addressFillRecoveryFence = stidFenced( + addressFillArbiter.io.out.bits.stid) + stq.io.fillValid := addressFillArbiter.io.out.valid && + !addressFillRecoveryFence && + io.lateStaPermit stq.io.fill := addressFillArbiter.io.out.bits - addressFillArbiter.io.out.ready := stq.io.fillReady && !recoveryFence + addressFillArbiter.io.out.ready := stq.io.fillReady && + !addressFillRecoveryFence && + io.lateStaPermit io.fillConflict := stq.io.fillConflict || dataBank.io.conflict.reduce(_ || _) + private def projectLateStaProbe( + target: MDBConflictStoreProbe, + accepted: STQStoreRequest): Unit = { + target.valid := true.B + target.addrOnly := true.B + target.isTile := !accepted.scalarIex + target.peId := accepted.peId + target.stid := accepted.stid + target.tid := accepted.tid + target.bid := accepted.bid + target.gid := accepted.gid + target.rid := accepted.rid + target.lsId := accepted.lsId + target.lsIdFullValid := true.B + target.lsIdFull := accepted.lsIdFull + target.pc := accepted.pc + target.addr := accepted.addr + target.size := accepted.size + } + + io.lateStaCandidate := 0.U.asTypeOf(io.lateStaCandidate) + io.lateStaCandidate.valid := addressFillArbiter.io.out.valid && + !addressFillRecoveryFence + projectLateStaProbe( + io.lateStaCandidate.bits, addressFillArbiter.io.out.bits) + io.lateStaProbe := 0.U.asTypeOf(io.lateStaProbe) when(stq.io.fillAccepted) { val accepted = addressFillArbiter.io.out.bits io.lateStaProbe.valid := true.B - io.lateStaProbe.bits.valid := true.B - io.lateStaProbe.bits.addrOnly := true.B - io.lateStaProbe.bits.isTile := !accepted.scalarIex - io.lateStaProbe.bits.peId := accepted.peId - io.lateStaProbe.bits.stid := accepted.stid - io.lateStaProbe.bits.tid := accepted.tid - io.lateStaProbe.bits.bid := accepted.bid - io.lateStaProbe.bits.gid := accepted.gid - io.lateStaProbe.bits.rid := accepted.rid - io.lateStaProbe.bits.lsId := accepted.lsId - io.lateStaProbe.bits.lsIdFullValid := true.B - io.lateStaProbe.bits.lsIdFull := accepted.lsIdFull - io.lateStaProbe.bits.pc := accepted.pc - io.lateStaProbe.bits.addr := accepted.addr - io.lateStaProbe.bits.size := accepted.size + projectLateStaProbe(io.lateStaProbe.bits, accepted) } + // A store resolves only after every semantic beat has accepted both its + // STA and STD half. The STQ is the canonical join owner, so the completion + // token is retained here until OOO accepts it and cannot be reconstructed + // from an IEX pipe-local pulse. + val completionPublished = RegInit(0.U(stqEntries.W)) + val completionPending = RegInit(false.B) + val completionPendingBits = Reg(new RobResolveTxn(core)) + val completionPendingMask = Reg(UInt(stqEntries.W)) + + val reservationAllocatedMask = stq.io.reserveBatchLeases.map { lease => + Mux(lease.valid, UIntToOH(lease.index, stqEntries), 0.U(stqEntries.W)) + }.reduce(_ | _) + val completionClearMask = stq.io.exactRecoveryAcceptedMask | + stq.io.commitFreeAcceptedMask | reservationAllocatedMask + val completionPendingInvalidated = completionPending && + (completionPendingMask & completionClearMask).orR + + io.completion.valid := completionPending && !completionPendingInvalidated && + !recoveryPending + io.completion.bits := completionPendingBits + val completionFire = io.completion.fire + val completionSetMask = Mux(completionFire, completionPendingMask, + 0.U(stqEntries.W)) + val completionVisibleMask = (completionPublished | completionSetMask) & + ~completionClearMask + + val completionCandidates = Wire(Vec(stqEntries, Bool())) + val completionCandidateMasks = Wire(Vec(stqEntries, UInt(stqEntries.W))) + for (headIndex <- 0 until stqEntries) { + val head = stq.io.rows(headIndex) + val requestCountLegal = head.logicalRequestCount === 1.U || + head.logicalRequestCount === 2.U + val beatMatches = Wire(Vec(p.maxMemoryRequestsPerInstruction, + UInt(stqEntries.W))) + val beatExact = Wire(Vec(p.maxMemoryRequestsPerInstruction, Bool())) + for (beat <- 0 until p.maxMemoryRequestsPerInstruction) { + val required = beat.U < head.logicalRequestCount + val matches = VecInit(stq.io.rows.zipWithIndex.map { case (row, index) => + row.valid && row.status === STQEntryStatus.Wait && + row.logicalStoreValid && row.exactOwner.valid && + row.exactOwner.nativeBidValid && + row.transactionId === head.transactionId && + row.exactOwner.asUInt === head.exactOwner.asUInt && + row.logicalFirstLsid === head.logicalFirstLsid && + row.logicalFirstStoreId === head.logicalFirstStoreId && + row.logicalRequestCount === head.logicalRequestCount && + row.logicalBeat === beat.U && row.addrReady && row.dataReady && + !completionVisibleMask(index) && !completionClearMask(index) + }) + beatMatches(beat) := matches.asUInt + beatExact(beat) := Mux(required, PopCount(matches) === 1.U, + !matches.asUInt.orR) + } + completionCandidateMasks(headIndex) := beatMatches.reduce(_ | _) + completionCandidates(headIndex) := !recoveryPending && + head.valid && head.status === STQEntryStatus.Wait && + head.logicalStoreValid && head.logicalBeat === 0.U && + head.exactOwner.valid && head.exactOwner.nativeBidValid && + requestCountLegal && beatExact.asUInt.andR + } + + val completionCandidateValid = completionCandidates.asUInt.orR + val completionCandidateIndex = PriorityEncoder(completionCandidates.asUInt) + val completionCandidate = stq.io.rows(completionCandidateIndex) + val completionCandidateMask = Mux1H(completionCandidates, + completionCandidateMasks) + + val completionCanReload = !completionPending || completionFire || + completionPendingInvalidated + when(completionCanReload) { + when(completionCandidateValid) { + completionPending := true.B + completionPendingMask := completionCandidateMask + completionPendingBits := 0.U.asTypeOf(completionPendingBits) + completionPendingBits.transactionId := + completionCandidate.transactionId + completionPendingBits.rob.peId := completionCandidate.exactOwner.peId + completionPendingBits.rob.stid := completionCandidate.exactOwner.stid + completionPendingBits.rob.ridSlot := + completionCandidate.exactOwner.ridSlot + completionPendingBits.rob.ridGeneration := + completionCandidate.exactOwner.ridGeneration + completionPendingBits.rob.memberIndex := + completionCandidate.exactOwner.memberIndex + completionPendingBits.rob.residentGeneration := + completionCandidate.exactOwner.residentGeneration + completionPendingBits.rob.bid := + completionCandidate.exactOwner.nativeBid + completionPendingBits.rob.brobGeneration := + completionCandidate.exactOwner.brobGeneration + }.otherwise { + completionPending := false.B + completionPendingMask := 0.U + } + } + completionPublished := completionVisibleMask + val joinedRows = Wire(chiselTypeOf(io.rows)) for (index <- 0 until stqEntries) { joinedRows(index) := stq.io.rows(index) @@ -355,13 +575,19 @@ class OooIexStoreStqFabric( io.storePipelinesOccupied := VecInit(stores.map(_.io.occupied)).asUInt io.empty := stq.io.empty && dataBank.io.empty && !loadForward.io.occupied.orR && - !io.storePipelinesOccupied.orR + !io.storePipelinesOccupied.orR && !completionPending && !recoveryPending - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady, - "store/STQ recovery needs one exact prepared WAIT-only projection") + when(io.recovery.apply.valid) { + assert(matchingApply, + "store/STQ Apply must match one exact prepared recovery transaction") + } + when(io.recovery.abort.valid) { + assert(matchingAbort, + "store/STQ Abort must match one exact prepared recovery transaction") } - when(io.reserve.fire) { + when(io.reserve.map(_.fire).reduce(_ || _)) { + assert(io.reserve.map(reserve => !reserve.valid || reserve.fire).reduce(_ && _), + "one presented store-reservation prefix must fire atomically") assert(stq.io.reserveBatchAccepted, "store reservation and canonical STQ allocation must fire atomically") } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala b/chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala index 22a20335..b0b879ee 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala @@ -2,6 +2,9 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, RRArbiter, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryTargetIO, RecoveryPlanContract, + RobResolveTxn, RecoveryEvent} /** Physical terminal topology for the formal scalar/control execution profile. * @@ -12,10 +15,11 @@ import chisel3.util.{Decoupled, RRArbiter, Valid} * can be released at most once. */ class OooIexTerminalFabricIO( - val p: OooParams, + val core: CoreParams, val aluSourceCount: Int, val bruSourceCount: Int, val loadSourceCount: Int) extends Bundle { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params private val publicationPorts = p.iexTerminalWidth * p.maxDestinationOperands val alu = Flipped(Vec(aluSourceCount, @@ -37,25 +41,30 @@ class OooIexTerminalFabricIO( Decoupled(new OooIexTerminalBctrl(p))) val trace = Vec(p.iexTerminalWidth, Decoupled(new OooIexTerminalTrace(p))) - val completion = Vec(p.iexTerminalWidth, - Decoupled(new OooRobMemberCompletion(p))) + val robResolve = Vec(p.iexTerminalWidth, + Decoupled(new RobResolveTxn(core))) + val recoveryEvent = Vec(p.iexTerminalWidth, + Decoupled(new RecoveryEvent(core))) + val recovery = Flipped(new RecoveryTargetIO(core)) val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) + val architecturalAccepted = Output(Vec(p.iexTerminalWidth, + Valid(new OooIexTerminalRequest(p)))) val rejected = Output(Vec(p.iexTerminalWidth, Vec(3, Valid(new OooIexTerminalReject(p))))) } class OooIexTerminalFabric( - val p: OooParams = OooParams(), - val aluSourceCount: Int = 6, - val bruSourceCount: Int = 2, - val loadSourceCount: Int = 3) extends Module { + val core: CoreParams, + val aluSourceCount: Int, + val bruSourceCount: Int, + val loadSourceCount: Int) extends Module { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params private val width = p.iexTerminalWidth private val publicationPorts = width * p.maxDestinationOperands - require(aluSourceCount >= width && bruSourceCount >= width && - loadSourceCount >= width, - "every terminal lane needs at least one ALU, BRU, and load source owner") + require(aluSourceCount > 0 && bruSourceCount > 0 && loadSourceCount > 0, + "terminal topology needs at least one ALU, BRU, and load source owner") require(p.iexPWritePorts >= publicationPorts && p.iexTWritePorts >= publicationPorts && p.iexUWritePorts >= publicationPorts, @@ -64,23 +73,26 @@ class OooIexTerminalFabric( "terminal width must fit committed wakeup bandwidth") val io = IO(new OooIexTerminalFabricIO( - p, aluSourceCount, bruSourceCount, loadSourceCount)) + core, aluSourceCount, bruSourceCount, loadSourceCount)) private def ownedSources(sourceCount: Int, lane: Int): Seq[Int] = (0 until sourceCount).filter(_ % width == lane) - val publishers = Seq.fill(width)(Module(new OooIexTerminalPublish(p))) + val publishers = Seq.fill(width)(Module(new OooIexTerminalPublish(core))) val aluArbiters = Seq.tabulate(width) { lane => - Module(new RRArbiter(new OooIexAluTerminalTransaction(p), - ownedSources(aluSourceCount, lane).length)) + val count = ownedSources(aluSourceCount, lane).length + Option.when(count > 0)(Module(new RRArbiter( + new OooIexAluTerminalTransaction(p), count))) } val bruArbiters = Seq.tabulate(width) { lane => - Module(new RRArbiter(new OooIexBruTerminalTransaction(p), - ownedSources(bruSourceCount, lane).length)) + val count = ownedSources(bruSourceCount, lane).length + Option.when(count > 0)(Module(new RRArbiter( + new OooIexBruTerminalTransaction(p), count))) } val loadArbiters = Seq.tabulate(width) { lane => - Module(new RRArbiter(new OooIexLoadResult(p), - ownedSources(loadSourceCount, lane).length)) + val count = ownedSources(loadSourceCount, lane).length + Option.when(count > 0)(Module(new RRArbiter( + new OooIexLoadResult(p), count))) } for (lane <- 0 until width) { @@ -89,24 +101,42 @@ class OooIexTerminalFabric( val loadSources = ownedSources(loadSourceCount, lane) aluSources.zipWithIndex.foreach { case (source, local) => - aluArbiters(lane).io.in(local).valid := io.alu(source).valid - aluArbiters(lane).io.in(local).bits := io.alu(source).bits - io.alu(source).ready := aluArbiters(lane).io.in(local).ready + aluArbiters(lane).get.io.in(local).valid := io.alu(source).valid + aluArbiters(lane).get.io.in(local).bits := io.alu(source).bits + io.alu(source).ready := aluArbiters(lane).get.io.in(local).ready } bruSources.zipWithIndex.foreach { case (source, local) => - bruArbiters(lane).io.in(local).valid := io.bru(source).valid - bruArbiters(lane).io.in(local).bits := io.bru(source).bits - io.bru(source).ready := bruArbiters(lane).io.in(local).ready + bruArbiters(lane).get.io.in(local).valid := io.bru(source).valid + bruArbiters(lane).get.io.in(local).bits := io.bru(source).bits + io.bru(source).ready := bruArbiters(lane).get.io.in(local).ready } loadSources.zipWithIndex.foreach { case (source, local) => - loadArbiters(lane).io.in(local).valid := io.load(source).valid - loadArbiters(lane).io.in(local).bits := io.load(source).bits - io.load(source).ready := loadArbiters(lane).io.in(local).ready + loadArbiters(lane).get.io.in(local).valid := io.load(source).valid + loadArbiters(lane).get.io.in(local).bits := io.load(source).bits + io.load(source).ready := loadArbiters(lane).get.io.in(local).ready } - publishers(lane).io.alu <> aluArbiters(lane).io.out - publishers(lane).io.bru <> bruArbiters(lane).io.out - publishers(lane).io.load <> loadArbiters(lane).io.out + aluArbiters(lane) match { + case Some(arbiter) => publishers(lane).io.alu <> arbiter.io.out + case None => + publishers(lane).io.alu.valid := false.B + publishers(lane).io.alu.bits := + 0.U.asTypeOf(publishers(lane).io.alu.bits) + } + bruArbiters(lane) match { + case Some(arbiter) => publishers(lane).io.bru <> arbiter.io.out + case None => + publishers(lane).io.bru.valid := false.B + publishers(lane).io.bru.bits := + 0.U.asTypeOf(publishers(lane).io.bru.bits) + } + loadArbiters(lane) match { + case Some(arbiter) => publishers(lane).io.load <> arbiter.io.out + case None => + publishers(lane).io.load.valid := false.B + publishers(lane).io.load.bits := + 0.U.asTypeOf(publishers(lane).io.load.bits) + } for (destination <- 0 until p.maxDestinationOperands) { val port = lane * p.maxDestinationOperands + destination @@ -134,11 +164,47 @@ class OooIexTerminalFabric( io.trace(lane).valid := publishers(lane).io.trace.valid io.trace(lane).bits := publishers(lane).io.trace.bits publishers(lane).io.trace.ready := io.trace(lane).ready - io.completion(lane).valid := publishers(lane).io.completion.valid - io.completion(lane).bits := publishers(lane).io.completion.bits - publishers(lane).io.completion.ready := io.completion(lane).ready + io.robResolve(lane).valid := publishers(lane).io.robResolve.valid + io.robResolve(lane).bits := publishers(lane).io.robResolve.bits + publishers(lane).io.robResolve.ready := io.robResolve(lane).ready + io.recoveryEvent(lane).valid := publishers(lane).io.recoveryEvent.valid + io.recoveryEvent(lane).bits := publishers(lane).io.recoveryEvent.bits + publishers(lane).io.recoveryEvent.ready := io.recoveryEvent(lane).ready + io.architecturalAccepted(lane) := + publishers(lane).io.architecturalAccepted io.rejected(lane) := publishers(lane).io.rejected } + val everyPrepareReady = publishers.map(_.io.recovery.prepare.ready) + .reduce(_ && _) + io.recovery.prepare.ready := everyPrepareReady + publishers.foreach { publisher => + publisher.io.recovery.prepare.valid := io.recovery.prepare.valid && + everyPrepareReady + publisher.io.recovery.prepare.bits := io.recovery.prepare.bits + publisher.io.recovery.apply := io.recovery.apply + publisher.io.recovery.abort := io.recovery.abort + } + + val everyPreparedValid = publishers.map(_.io.recovery.prepared.valid) + .reduce(_ && _) + io.recovery.prepared.valid := everyPreparedValid + io.recovery.prepared.bits := publishers.head.io.recovery.prepared.bits + publishers.zipWithIndex.foreach { case (publisher, lane) => + val peersValid = publishers.zipWithIndex.filter(_._2 != lane) + .map(_._1.io.recovery.prepared.valid).foldLeft(true.B)(_ && _) + publisher.io.recovery.prepared.ready := io.recovery.prepared.ready && + peersValid + } + + when(io.recovery.prepared.fire) { + publishers.tail.foreach { publisher => + assert(RecoveryPlanContract.sameTransactionIgnoringPhase( + publisher.io.recovery.prepared.bits, + publishers.head.io.recovery.prepared.bits), + "terminal publishers must echo one exact canonical recovery plan") + } + } + io.terminalFireMask := VecInit(publishers.map(_.io.terminalFire)).asUInt } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIexTerminalPublish.scala b/chisel/src/main/scala/linxcore/ooo/OooIexTerminalPublish.scala index 6453ec2e..1b8380a9 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooIexTerminalPublish.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooIexTerminalPublish.scala @@ -3,9 +3,15 @@ package linxcore.ooo import chisel3._ import chisel3.util.{Decoupled, RRArbiter, Valid} import linxcore.common.{DestinationKind, OperandClass} +import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.CoreParams +import linxcore.top.interface.{CmdIssueTxn, InstructionIdentity, RecoveryCause, + RecoveryEvent, RecoveryPhase, RecoveryPlan, RecoveryPlanContract, + RecoveryTargetIO, RobIdentity, RobNoflushReadyTxn, RobNoflushTxn, + RobResolveTxn, SystemIssueTxn, TrapEvent, TrapKind} object OooIexTerminalSource extends ChiselEnum { - val Alu, Bru, Load = Value + val Alu, Bru, Load, System, Cmd = Value } class OooIexTerminalWriteback(val p: OooParams = OooParams()) extends Bundle { @@ -17,11 +23,13 @@ class OooIexTerminalWriteback(val p: OooParams = OooParams()) extends Bundle { /** One normalized terminal transaction before architectural publication. */ class OooIexTerminalRequest(val p: OooParams = OooParams()) extends Bundle { val source = OooIexTerminalSource() + val transactionId = UInt(p.transactionIdWidth.W) val member = new RobMemberKey(p) val uopKey = new CanonicalUopKey(p) val opcode = UInt(p.opcodeWidth.W) val stid = UInt(p.stidWidth.W) val epoch = UInt(p.epochWidth.W) + val prediction = new OooPredictionRecord(p) val writebacks = Vec(p.maxDestinationOperands, new OooIexTerminalWriteback(p)) val bctrl = new OooIexBctrlUpdate(p) @@ -34,6 +42,8 @@ class OooIexTerminalBctrl(val p: OooParams = OooParams()) extends Bundle { val member = new RobMemberKey(p) val uopKey = new CanonicalUopKey(p) val opcode = UInt(p.opcodeWidth.W) + val transactionId = UInt(p.transactionIdWidth.W) + val prediction = new OooPredictionRecord(p) val update = new OooIexBctrlUpdate(p) } @@ -58,7 +68,8 @@ class OooIexTerminalReject(val p: OooParams = OooParams()) extends Bundle { val duplicateDestination = Bool() } -class OooIexTerminalPublishIO(val p: OooParams = OooParams()) extends Bundle { +class OooIexTerminalPublishIO(val core: CoreParams) extends Bundle { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params val alu = Flipped(Decoupled(new OooIexAluTerminalTransaction(p))) val bru = Flipped(Decoupled(new OooIexBruTerminalTransaction(p))) val load = Flipped(Decoupled(new OooIexLoadResult(p))) @@ -73,27 +84,329 @@ class OooIexTerminalPublishIO(val p: OooParams = OooParams()) extends Bundle { Decoupled(new OooIexWakeup(p))) val bctrl = Decoupled(new OooIexTerminalBctrl(p)) val trace = Decoupled(new OooIexTerminalTrace(p)) - val completion = Decoupled(new OooRobMemberCompletion(p)) + val robResolve = Decoupled(new RobResolveTxn(core)) + val recoveryEvent = Decoupled(new RecoveryEvent(core)) + val recovery = Flipped(new RecoveryTargetIO(core)) val terminalFire = Output(Bool()) + val architecturalAccepted = Valid(new OooIexTerminalRequest(p)) val rejected = Vec(3, Valid(new OooIexTerminalReject(p))) } -/** Fair ALU/BRU/load terminal arbiter with one atomic publication event. +class OooIexSystemCmdCandidate(val p: OooParams) extends Bundle { + val cmd = Bool() + val execute = new OooIexExecuteTransaction(p) +} + +class OooIexSystemCmdTerminalIO( + val core: CoreParams, + val profile: OooIexPhysicalProfile) extends Bundle { + val p: OooParams = profile.params + private def capabilityCount(capability: Int): Int = + profile.pickerFunctions.count(_.hasCapability(capability)) + private val systemCount = capabilityCount(OooIexDomainCapability.System) + private val cmdCount = capabilityCount(OooIexDomainCapability.EngineCommand) + + val system = Flipped(Vec(systemCount, + Decoupled(new OooIexExecuteTransaction(p)))) + val cmd = Flipped(Vec(cmdCount, + Decoupled(new OooIexExecuteTransaction(p)))) + val robNoflushReady = Decoupled(new RobNoflushReadyTxn(core)) + val robNoflush = Flipped(Decoupled(new RobNoflushTxn(core))) + val systemIssue = Vec(systemCount, Decoupled(new SystemIssueTxn(core))) + val cmdIssue = Decoupled(new CmdIssueTxn(core)) + val robResolve = Decoupled(new RobResolveTxn(core)) + val trace = Decoupled(new OooIexTerminalTrace(p)) + val recovery = Flipped(new RecoveryTargetIO(core)) + val terminalFire = Output(Bool()) + val empty = Output(Bool()) +} + +/** Head-authorized no-destination System/CMD terminal rendezvous. + * + * The upstream E1 transfer slot remains the sole resident-uop owner. This + * module only arbitrates the retained candidates, publishes an exact NFRDY + * proof, and releases one candidate when the matching ROB authorization, + * side-effect sink, and no-value ROB resolve all fire together. Unsupported + * or destination-producing rows remain resident and fail closed. + */ +class OooIexSystemCmdTerminal(val core: CoreParams) extends Module { + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p: OooParams = profile.params + private val systemCount = profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.System)) + private val cmdCount = profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.EngineCommand)) + require(systemCount == 1 && cmdCount == 1, + "System/CMD terminal requires one System pipe and one CMD pipe") + + val io = IO(new OooIexSystemCmdTerminalIO(core, profile)) + + private def toRobIdentity(execute: OooIexExecuteTransaction): RobIdentity = + OooRecoveryMembership.robIdentity(p, core, execute.i2.row.member) + + private def toInstructionIdentity( + execute: OooIexExecuteTransaction): InstructionIdentity = { + val result = Wire(new InstructionIdentity(core)) + result := 0.U.asTypeOf(result) + result.peId := execute.i2.row.uopKey.primaryParent.peId + result.stid := execute.i2.row.uopKey.primaryParent.stid + result.instructionId := + execute.i2.row.uopKey.primaryParent.instructionId + result.epoch := execute.i2.row.epoch + result + } + + private def identityExact(execute: OooIexExecuteTransaction): Bool = { + val row = execute.i2.row + row.valid && row.stid < p.stidCount.U && row.member.group.valid && + row.member.bid.valid && row.member.group.peId === row.peId && + row.member.group.stid === row.stid && + row.member.memberIndex < core.ooo.maxInstructionsPerRobGroup.U && + row.uopKey.primaryParent.valid && + row.uopKey.primaryParent.peId === row.peId && + row.uopKey.primaryParent.stid === row.stid + } + + private def noDestinations(execute: OooIexExecuteTransaction): Bool = + !VecInit(execute.i2.row.destinations.map(_.valid)).asUInt.orR + + private def sourceMaskExact(execute: OooIexExecuteTransaction): Bool = + execute.i2.sourceMask === + VecInit(execute.i2.row.sources.map(_.valid)).asUInt + + private def routeExact( + execute: OooIexExecuteTransaction, + ownerClass: OooUopClass.Type, + dispatchClass: Int): Bool = { + val row = execute.i2.row + execute.ownerClass === ownerClass && row.reservation.valid && + row.reservation.uopClass === ownerClass && row.recipe.valid && + row.recipe.opcode === row.opcode && + row.recipe.disposition === OooOpcodeDisposition.Dispatch.U && + row.recipe.dispatchClass === dispatchClass.U && + row.recipe.sideEffectOwner === OooSideEffectOwner.Commit.U && + !row.preciseTrap && noDestinations(execute) && sourceMaskExact(execute) + } + + private def memberKilled( + plan: RecoveryPlan, + execute: OooIexExecuteTransaction): Bool = + RecoveryPlanContract.suffixMember(plan, toRobIdentity(execute)) + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val matchingApply = recoveryPending && io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val matchingAbort = recoveryPending && io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + + io.recovery.prepare.ready := !recoveryPending + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := retainedRecovery + val prepareFire = io.recovery.prepare.fire + when(prepareFire) { + recoveryPending := true.B + preparedValid := true.B + retainedRecovery := io.recovery.prepare.bits + }.elsewhen(matchingApply || matchingAbort) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + private def recoveryBlocked(execute: OooIexExecuteTransaction): Bool = + (prepareFire && memberKilled(io.recovery.prepare.bits, execute)) || + (recoveryPending && memberKilled(retainedRecovery, execute)) + + private def recoveryKilled(execute: OooIexExecuteTransaction): Bool = + matchingApply && memberKilled(io.recovery.apply.bits, execute) + + val systemExact = identityExact(io.system.head.bits) && + routeExact(io.system.head.bits, OooUopClass.Sys, OooDispatchClass.Sys) && + !io.system.head.bits.i2.sourceMask.orR + val cmdExact = identityExact(io.cmd.head.bits) && + routeExact(io.cmd.head.bits, OooUopClass.Cmd, OooDispatchClass.Cmd) + val systemKilled = io.system.head.valid && recoveryKilled(io.system.head.bits) + val cmdKilled = io.cmd.head.valid && recoveryKilled(io.cmd.head.bits) + val systemEligible = io.system.head.valid && systemExact && + !recoveryBlocked(io.system.head.bits) && !systemKilled + val cmdEligible = io.cmd.head.valid && cmdExact && + !recoveryBlocked(io.cmd.head.bits) && !cmdKilled + + val arbiter = Module(new RRArbiter(new OooIexSystemCmdCandidate(p), 2)) + arbiter.io.in(0).valid := systemEligible + arbiter.io.in(0).bits.cmd := false.B + arbiter.io.in(0).bits.execute := io.system.head.bits + arbiter.io.in(1).valid := cmdEligible + arbiter.io.in(1).bits.cmd := true.B + arbiter.io.in(1).bits.execute := io.cmd.head.bits + arbiter.io.out.ready := io.robNoflushReady.ready + + val selected = arbiter.io.out + val selectedRob = toRobIdentity(selected.bits.execute) + val selectedInstruction = toInstructionIdentity(selected.bits.execute) + + io.robNoflushReady.valid := selected.valid + io.robNoflushReady.bits := 0.U.asTypeOf(io.robNoflushReady.bits) + io.robNoflushReady.bits.transactionId := + selected.bits.execute.i2.row.transactionId + io.robNoflushReady.bits.instruction := selectedInstruction + io.robNoflushReady.bits.rob := selectedRob + + val permitExact = io.robNoflush.bits.transactionId === + io.robNoflushReady.bits.transactionId && + io.robNoflush.bits.instruction.asUInt === selectedInstruction.asUInt && + io.robNoflush.bits.rob.asUInt === selectedRob.asUInt + val authorized = selected.valid && io.robNoflush.valid && permitExact + + io.systemIssue.foreach { issue => + issue.valid := false.B + issue.bits := 0.U.asTypeOf(issue.bits) + issue.bits.transactionId := selected.bits.execute.i2.row.transactionId + issue.bits.instruction := selectedInstruction + issue.bits.rob := selectedRob + issue.bits.opcode := selected.bits.execute.i2.row.opcode + issue.bits.immediate := selected.bits.execute.i2.row.immediate + } + io.systemIssue.head.valid := authorized && !selected.bits.cmd && + io.robResolve.ready && io.trace.ready + + io.cmdIssue.valid := authorized && selected.bits.cmd && io.robResolve.ready && + io.trace.ready + io.cmdIssue.bits := 0.U.asTypeOf(io.cmdIssue.bits) + io.cmdIssue.bits.transactionId := selected.bits.execute.i2.row.transactionId + io.cmdIssue.bits.instruction := selectedInstruction + io.cmdIssue.bits.rob := selectedRob + io.cmdIssue.bits.opcode := selected.bits.execute.i2.row.opcode + io.cmdIssue.bits.sourceValid := selected.bits.execute.i2.sourceMask + for (source <- 0 until p.maxSourceOperands) { + io.cmdIssue.bits.sourceValues(source) := + selected.bits.execute.i2.sourceData(source) + } + + val sideEffectReady = Mux(selected.bits.cmd, + io.cmdIssue.ready, io.systemIssue.head.ready) + val sideEffectFire = Mux(selected.bits.cmd, + io.cmdIssue.fire, io.systemIssue.head.fire) + + io.robResolve.valid := authorized && sideEffectReady && io.trace.ready + io.robResolve.bits := 0.U.asTypeOf(io.robResolve.bits) + io.robResolve.bits.transactionId := selected.bits.execute.i2.row.transactionId + io.robResolve.bits.rob := selectedRob + io.robResolve.bits.destinationValid := false.B + io.robResolve.bits.destinationIndex := 0.U + io.robResolve.bits.value := 0.U + io.robResolve.bits.trap := 0.U.asTypeOf(io.robResolve.bits.trap) + + io.trace.valid := authorized && sideEffectReady && io.robResolve.ready + io.trace.bits := 0.U.asTypeOf(io.trace.bits) + io.trace.bits.source := Mux(selected.bits.cmd, + OooIexTerminalSource.Cmd, OooIexTerminalSource.System) + io.trace.bits.member := selected.bits.execute.i2.row.member + io.trace.bits.uopKey := selected.bits.execute.i2.row.uopKey + io.trace.bits.opcode := selected.bits.execute.i2.row.opcode + + io.robNoflush.ready := selected.valid && permitExact && sideEffectReady && + io.robResolve.ready && io.trace.ready + val atomicFire = selected.valid && io.robNoflush.fire && + io.robNoflushReady.fire && sideEffectFire && io.robResolve.fire && + io.trace.fire + io.system.head.ready := systemKilled || (!selected.bits.cmd && atomicFire) + io.cmd.head.ready := cmdKilled || (selected.bits.cmd && atomicFire) + io.terminalFire := atomicFire + io.empty := !recoveryPending && !io.system.head.valid && !io.cmd.head.valid + + when(io.robNoflush.fire || sideEffectFire || io.robResolve.fire || + io.trace.fire) { + assert(atomicFire, + "System/CMD permit, side effect, resolve, trace, proof, and owner release must fire atomically") + } + when(atomicFire) { + assert(!selected.bits.execute.i2.row.destinations.map(_.valid).reduce(_ || _), + "destination-producing System/CMD operations must fail closed") + } +} + +/** Fair ALU/BRU/load terminal arbiter with one atomic architectural event. * * A selected owner is released only when every required physical-file write, - * committed wakeup, ROB completion, trace record, and optional BCTRL update - * fires together. No endpoint can consume a partial transaction while a peer - * endpoint is backpressured. + * committed wakeup, ROB resolve, and optional BCTRL update fires together. + * Trace is a best-effort observation of that event and cannot participate in + * owner release or architectural backpressure. */ -class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooIexTerminalPublishIO(p)) +class OooIexTerminalPublish(val core: CoreParams) extends Module { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + val io = IO(new OooIexTerminalPublishIO(core)) + + private def toRobIdentity(member: RobMemberKey): RobIdentity = { + OooRecoveryMembership.robIdentity(p, core, member) + } + + private def toInstructionIdentity( + request: OooIexTerminalRequest): InstructionIdentity = { + val result = Wire(new InstructionIdentity(core)) + result := 0.U.asTypeOf(result) + result.peId := request.uopKey.primaryParent.peId + result.stid := request.uopKey.primaryParent.stid + result.instructionId := request.uopKey.primaryParent.instructionId + result.epoch := request.epoch + result + } + + private def trapEvent(request: OooIexTerminalRequest): TrapEvent = { + val result = Wire(new TrapEvent(core)) + result := 0.U.asTypeOf(result) + result.valid := request.trapValid + result.kind := Mux(request.trapValid, TrapKind.Exception, TrapKind.None) + result.instruction := toInstructionIdentity(request) + result.rob := toRobIdentity(request.member) + result.cause := request.trapCause + result + } + + val recoveryPending = RegInit(false.B) + val retainedRecovery = Reg(new RecoveryPlan(core)) + val preparedValid = RegInit(false.B) + + io.recovery.prepare.ready := !recoveryPending + val directPrepared = io.recovery.prepare.valid && io.recovery.prepare.ready + io.recovery.prepared.valid := preparedValid || directPrepared + io.recovery.prepared.bits := Mux(preparedValid, retainedRecovery, + io.recovery.prepare.bits) + + val matchingApply = recoveryPending && io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, retainedRecovery) + val matchingAbort = recoveryPending && io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, retainedRecovery) + + when(io.recovery.prepare.fire) { + recoveryPending := true.B + retainedRecovery := io.recovery.prepare.bits + preparedValid := !io.recovery.prepared.ready + }.elsewhen(matchingApply || matchingAbort) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } private def identityExact(execute: OooIexExecuteTransaction): Bool = { val row = execute.i2.row row.valid && row.stid < p.stidCount.U && row.member.group.valid && row.member.bid.valid && row.member.group.peId === row.peId && - row.member.group.stid === row.stid + row.member.group.stid === row.stid && + row.member.memberIndex < core.ooo.maxInstructionsPerRobGroup.U } private def routeExact( @@ -159,11 +472,13 @@ class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { val request = Wire(new OooIexTerminalRequest(p)) request := 0.U.asTypeOf(request) request.source := source + request.transactionId := execute.i2.row.transactionId request.member := execute.i2.row.member request.uopKey := execute.i2.row.uopKey request.opcode := execute.i2.row.opcode request.stid := execute.i2.row.stid request.epoch := execute.i2.row.epoch + request.prediction := execute.i2.row.primaryPrediction request } @@ -274,19 +589,59 @@ class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { (writeReady(index) && io.wakeup(index).ready) } val allDestinationReady = destinationReady.reduce(_ && _) - val bctrlReady = !selected.bits.bctrl.valid || io.bctrl.ready - val allReady = io.completion.ready && io.trace.ready && bctrlReady && - allDestinationReady - selected.ready := allReady - - io.completion.valid := selected.valid && io.trace.ready && bctrlReady && - allDestinationReady - io.completion.bits.key := selected.bits.member - io.completion.bits.faultValid := selected.bits.trapValid - io.completion.bits.faultCause := selected.bits.trapCause - - io.trace.valid := selected.valid && io.completion.ready && bctrlReady && - allDestinationReady + val branchRedirect = selected.bits.bctrl.valid && + selected.bits.opcode === FrontendOpcodeDecodeTable.OP_J.U && + selected.bits.bctrl.kind === OooIexBctrlUpdateKind.Target && + selected.bits.bctrl.targetValid + val bctrlRequired = selected.bits.bctrl.valid && !branchRedirect + val bctrlReady = !bctrlRequired || io.bctrl.ready + val recoveryEventRequired = selected.bits.trapValid || branchRedirect + val recoveryEventReady = !recoveryEventRequired || io.recoveryEvent.ready + val selectedRob = toRobIdentity(selected.bits.member) + val recoveryKillsSelected = matchingApply && selected.valid && + RecoveryPlanContract.suffixMember(io.recovery.apply.bits, selectedRob) + val recoveryBlocksSelected = selected.valid && ( + (recoveryPending && !matchingApply && !matchingAbort && + RecoveryPlanContract.suffixMember(retainedRecovery, selectedRob)) || + (directPrepared && RecoveryPlanContract.suffixMember( + io.recovery.prepare.bits, selectedRob))) + val publicationEnabled = selected.valid && !recoveryKillsSelected && + !recoveryBlocksSelected + val architecturalReady = io.robResolve.ready && bctrlReady && + allDestinationReady && recoveryEventReady + selected.ready := recoveryKillsSelected || + (!recoveryBlocksSelected && architecturalReady) + + io.robResolve.valid := publicationEnabled && bctrlReady && + allDestinationReady && recoveryEventReady + io.robResolve.bits := 0.U.asTypeOf(io.robResolve.bits) + io.robResolve.bits.transactionId := selected.bits.transactionId + io.robResolve.bits.rob := selectedRob + io.robResolve.bits.destinationValid := + selected.bits.writebacks(0).valid && !selected.bits.trapValid + io.robResolve.bits.destinationIndex := 0.U + io.robResolve.bits.value := Mux( + io.robResolve.bits.destinationValid, + selected.bits.writebacks(0).data, + 0.U) + io.robResolve.bits.trap := trapEvent(selected.bits) + + io.recoveryEvent.valid := publicationEnabled && recoveryEventRequired && + io.robResolve.ready && bctrlReady && allDestinationReady + io.recoveryEvent.bits := 0.U.asTypeOf(io.recoveryEvent.bits) + io.recoveryEvent.bits.transactionId := selected.bits.transactionId + io.recoveryEvent.bits.cause := Mux(branchRedirect, + RecoveryCause.Branch, RecoveryCause.Exception) + io.recoveryEvent.bits.trigger := selectedRob + io.recoveryEvent.bits.instruction := toInstructionIdentity(selected.bits) + io.recoveryEvent.bits.redirectPc := Mux(branchRedirect, + selected.bits.bctrl.target, 0.U) + io.recoveryEvent.bits.trap := trapEvent(selected.bits) + + val architecturalFire = selected.fire && !recoveryKillsSelected + io.architecturalAccepted.valid := architecturalFire + io.architecturalAccepted.bits := selected.bits + io.trace.valid := architecturalFire io.trace.bits.source := selected.bits.source io.trace.bits.member := selected.bits.member io.trace.bits.uopKey := selected.bits.uopKey @@ -296,22 +651,24 @@ class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { io.trace.bits.trapValid := selected.bits.trapValid io.trace.bits.trapCause := selected.bits.trapCause - io.bctrl.valid := selected.valid && selected.bits.bctrl.valid && - io.completion.ready && io.trace.ready && allDestinationReady + io.bctrl.valid := publicationEnabled && bctrlRequired && + io.robResolve.ready && recoveryEventReady && allDestinationReady io.bctrl.bits.member := selected.bits.member io.bctrl.bits.uopKey := selected.bits.uopKey io.bctrl.bits.opcode := selected.bits.opcode + io.bctrl.bits.transactionId := selected.bits.transactionId + io.bctrl.bits.prediction := selected.bits.prediction io.bctrl.bits.update := selected.bits.bctrl for (index <- 0 until p.maxDestinationOperands) { val writeback = selected.bits.writebacks(index) val otherDestinationsReady = (0 until p.maxDestinationOperands) .filter(_ != index).map(destinationReady).foldLeft(true.B)(_ && _) - val commonPeerReady = io.completion.ready && io.trace.ready && + val commonPeerReady = io.robResolve.ready && recoveryEventReady && bctrlReady && otherDestinationsReady - val writeValid = selected.valid && writeRequired(index) && + val writeValid = publicationEnabled && writeRequired(index) && commonPeerReady && io.wakeup(index).ready - val wakeValid = selected.valid && writeRequired(index) && + val wakeValid = publicationEnabled && writeRequired(index) && commonPeerReady && writeReady(index) io.pWrite(index).valid := writeValid && @@ -360,11 +717,17 @@ class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { io.wakeup(index).bits.load := selected.bits.load } - io.terminalFire := selected.fire - when(selected.fire) { - assert(io.completion.fire && io.trace.fire, - "terminal completion and trace must share the owner release") - when(selected.bits.bctrl.valid) { + io.terminalFire := architecturalFire + when(architecturalFire) { + assert(io.robResolve.fire, + "terminal ROB resolve must share the architectural owner release") + assert(io.trace.valid, + "terminal trace observation must be generated from architectural fire") + when(recoveryEventRequired) { + assert(io.recoveryEvent.fire, + "required recovery event must share the terminal owner release") + } + when(bctrlRequired) { assert(io.bctrl.fire, "BCTRL mutation must share the terminal owner release") } @@ -376,4 +739,9 @@ class OooIexTerminalPublish(val p: OooParams = OooParams()) extends Module { } } } + when(recoveryKillsSelected) { + assert(selected.fire && !io.robResolve.fire && !io.trace.valid && + !io.recoveryEvent.fire, + "recovery-killed terminal ownership must release without publication") + } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooIfuD1Ingress.scala b/chisel/src/main/scala/linxcore/ooo/OooIfuD1Ingress.scala deleted file mode 100644 index 8fdcf747..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIfuD1Ingress.scala +++ /dev/null @@ -1,97 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Valid, log2Ceil} -import linxcore.common.InterfaceParams -import linxcore.frontend.{D1InstructionGroup, IfuInnerFlush} - -class OooIfuD1IngressIO( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams(), - val depthPerStid: Int = 16) - extends Bundle { - private val countWidth = log2Ceil(depthPerStid + 1) - - val ifuThreadId = Output(UInt(ifuP.threadIdWidth.W)) - val ifuD1 = Flipped(Decoupled(new D1InstructionGroup(ifuP))) - val selectStid = Input(UInt(oooP.stidWidth.W)) - val flush = Input(new IfuInnerFlush(ifuP)) - /** Stops new target-STID movement without clearing retained frontend state. */ - val fence = Input(Vec(oooP.stidCount, Bool())) - val cancel = Input(Vec(oooP.stidCount, Bool())) - - val ctuParentClaim = Decoupled(new OooCtuParentClaim(oooP)) - val ctuExpansionPlan = Flipped(Decoupled(new OooCtuExpansionPlan(oooP))) - val ctuChild = Flipped(Decoupled(new OooCtuCanonicalChild(oooP))) - val ctuPlanRejected = Valid(new OooCtuPlanReject(oooP)) - val ctuChildRejected = Valid(new OooCtuChildReject(oooP)) - val ctuRecoveryPrepare = Flipped(Decoupled( - new OooGlobalRecoveryRequest(oooP))) - val ctuRecoveryPrepared = Valid(new OooCtuRecoveryPrepared(oooP)) - val ctuRecoveryRejected = Valid(new OooCtuRecoveryReject(oooP)) - val ctuRecoveryApply = Input(Bool()) - val ctuRecoveryAbort = Input(Bool()) - - val out = Decoupled(new OooD1DecodedPacket(oooP)) - - val rawCounts = Output(Vec(oooP.stidCount, UInt(countWidth.W))) - val rawEligibleMask = Output(UInt(oooP.stidCount.W)) - val fusionHeld = Output(Vec(oooP.stidCount, Bool())) - val ctuOccupied = Output(Vec(oooP.stidCount, Bool())) - val ctuActive = Output(Vec(oooP.stidCount, Bool())) - val complexBlocked = Output(Vec(oooP.stidCount, Bool())) - val malformedInput = Output(Bool()) -} - -/** Canonical seam from fixed-four-wide IFU D1 to OOO D1. - * - * CTU and complex parents leave this seam as exact diverted-parent sidebands; - * they are never reconstructed from a mask or allowed to mutate ROB/RF/LSU. - */ -class OooIfuD1Ingress( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams(), - val depthPerStid: Int = 16) - extends Module { - val io = IO(new OooIfuD1IngressIO(ifuP, oooP, depthPerStid)) - - val raw = Module(new OooIfuRawIngress(ifuP, oooP, depthPerStid)) - val d1 = Module(new OooD1FusionDecode(oooP)) - val ctu = Module(new OooCtuIngressBridge(oooP)) - - raw.io.ifuD1 <> io.ifuD1 - raw.io.selectStid := io.selectStid - raw.io.fence := io.fence - raw.io.flush := io.flush - d1.io.in <> raw.io.out - - for (stid <- 0 until oooP.stidCount) { - d1.io.cancel(stid) := - io.cancel(stid) || (io.flush.valid && io.flush.threadId === stid.U) - ctu.io.cancel(stid) := d1.io.cancel(stid) - } - ctu.io.fence := io.fence - ctu.io.in <> d1.io.out - io.out <> ctu.io.out - - io.ctuParentClaim <> ctu.io.parentClaim - ctu.io.expansionPlan <> io.ctuExpansionPlan - ctu.io.child <> io.ctuChild - io.ctuPlanRejected := ctu.io.planRejected - io.ctuChildRejected := ctu.io.childRejected - ctu.io.recoveryPrepare <> io.ctuRecoveryPrepare - io.ctuRecoveryPrepared := ctu.io.recoveryPrepared - io.ctuRecoveryRejected := ctu.io.recoveryRejected - ctu.io.recoveryApply := io.ctuRecoveryApply - ctu.io.recoveryAbort := io.ctuRecoveryAbort - - io.ifuThreadId := raw.io.ifuThreadId - io.rawCounts := raw.io.counts - io.rawEligibleMask := raw.io.eligibleMask & - ~ctu.io.occupied.asUInt & ~ctu.io.active.asUInt - io.fusionHeld := d1.io.held - io.ctuOccupied := ctu.io.occupied - io.ctuActive := ctu.io.active - io.complexBlocked := ctu.io.blockedByComplex - io.malformedInput := raw.io.malformedInput -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooIfuRawIngress.scala b/chisel/src/main/scala/linxcore/ooo/OooIfuRawIngress.scala deleted file mode 100644 index 48c64442..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooIfuRawIngress.scala +++ /dev/null @@ -1,305 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, PriorityEncoder, log2Ceil} -import linxcore.common.InterfaceParams -import linxcore.frontend.{ - D1InstructionGroup, - IfuFlushContract, - IfuInnerFlush, - IfuPruneScope, - InstructionBufferEntry -} - -class OooIfuRawIngressIO( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams(), - val depthPerStid: Int = 16) - extends Bundle { - private val countWidth = log2Ceil(depthPerStid + 1) - - /** Thread hint driven back to the fixed-four-wide IFU D1 dequeue. */ - val ifuThreadId = Output(UInt(ifuP.threadIdWidth.W)) - val ifuD1 = Flipped(Decoupled(new D1InstructionGroup(ifuP))) - - /** OOO chooses the STID whose oldest dense prefix is presented. */ - val selectStid = Input(UInt(oooP.stidWidth.W)) - /** Non-mutating recovery admission fence. Retained rows remain intact. */ - val fence = Input(Vec(oooP.stidCount, Bool())) - val out = Decoupled(new OooRawInstructionGroup(oooP)) - val flush = Input(new IfuInnerFlush(ifuP)) - - val counts = Output(Vec(oooP.stidCount, UInt(countWidth.W))) - val eligibleMask = Output(UInt(oooP.stidCount.W)) - val acceptedLaneCount = Output(UInt(log2Ceil(ifuP.decodeWidth + 1).W)) - val emittedLaneCount = Output(UInt(log2Ceil(oooP.instructionDecodeWidth + 1).W)) - val malformedInput = Output(Bool()) -} - -/** Width and identity adapter between the fixed-four-wide IFU and production OOO. - * - * The IFU retains ownership of cacheline fetch and fixed-64-bit expansion. This - * module owns only a per-STID raw-instruction reservoir, exact metadata mapping, - * and independent 2/4/6-wide OOO dequeue. It performs no instruction decode. - */ -class OooIfuRawIngress( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams(), - val depthPerStid: Int = 16) - extends Module { - require(ifuP.fetchWidth == 4 && ifuP.decodeWidth == 4, - "production IFU ingress consumes the fixed-four-wide D1 contract") - require(ifuP.insnWidth == 64 && oooP.instructionWidth == 64) - require(depthPerStid >= math.max(ifuP.decodeWidth, oooP.instructionDecodeWidth)) - require((depthPerStid & (depthPerStid - 1)) == 0, - "depthPerStid must be a power of two") - require(oooP.stidCount <= (1 << ifuP.threadIdWidth)) - require(oooP.peIdWidth == ifuP.peIdWidth) - require(oooP.pcWidth == ifuP.pcWidth) - require(oooP.instructionIdWidth == ifuP.uopUidWidth) - require(oooP.transactionIdWidth == ifuP.uopUidWidth) - require(oooP.predictionTagWidth == ifuP.uopUidWidth) - require(oooP.checkpointWidth == ifuP.checkpointWidth) - require(oooP.epochWidth == ifuP.blockEpochWidth) - - private val ptrWidth = math.max(1, log2Ceil(depthPerStid)) - private val countWidth = log2Ceil(depthPerStid + 1) - - val io = IO(new OooIfuRawIngressIO(ifuP, oooP, depthPerStid)) - - val entries = RegInit(VecInit(Seq.fill(oooP.stidCount)( - VecInit(Seq.fill(depthPerStid)(0.U.asTypeOf(new InstructionBufferEntry(ifuP))))))) - val heads = RegInit(VecInit(Seq.fill(oooP.stidCount)(0.U(ptrWidth.W)))) - val tails = RegInit(VecInit(Seq.fill(oooP.stidCount)(0.U(ptrWidth.W)))) - val counts = RegInit(VecInit(Seq.fill(oooP.stidCount)(0.U(countWidth.W)))) - val pullStid = RegInit(0.U(oooP.stidWidth.W)) - - private def advancePtr(ptr: UInt, amount: UInt): UInt = - (ptr + amount)(ptrWidth - 1, 0) - - private def denseMask(mask: UInt, width: Int): Bool = - (0 to width) - .map(lanes => mask === ((BigInt(1) << lanes) - 1).U(width.W)) - .reduce(_ || _) - - private def mapEntry(target: OooRawInstruction, source: InstructionBufferEntry): Unit = { - target := 0.U.asTypeOf(target) - target.parent.key.valid := true.B - target.parent.key.peId := source.identity.peId - target.parent.key.stid := source.identity.threadId - target.parent.key.instructionId := source.instructionUid - target.parent.key.epoch := source.identity.epoch - target.parent.pc := source.pc - target.parent.rawInstruction := source.insn - target.parent.lengthBytes := source.lenBytes - target.parent.prediction.valid := source.prediction.valid - target.parent.prediction.predictionTag := source.prediction.predictionTag - target.parent.prediction.transactionId := source.transactionId - target.parent.prediction.fetchPacketUid := source.identity.fetchPacketUid - target.parent.prediction.fetchSeq := source.identity.fetchSeq - target.parent.prediction.requestPc := source.prediction.requestPc - target.parent.prediction.taken := source.prediction.taken - target.parent.prediction.branchPc := source.prediction.branchPc - target.parent.prediction.target := source.prediction.target - target.parent.prediction.fallthroughPc := source.prediction.fallthroughPc - target.parent.prediction.kind := source.prediction.kind - target.parent.prediction.provider := source.prediction.provider.asUInt - target.parent.prediction.stage := source.prediction.stage.asUInt - target.parent.prediction.confidence := source.prediction.confidence - target.parent.prediction.checkpointId := source.prediction.checkpointId - target.parent.prediction.epoch := source.prediction.epoch - target.parent.traceOwner := true.B - target.parent.preciseExceptionOwner := true.B - target.fetchFaultValid := false.B - target.fetchFaultCause := 0.U - } - - val pullCandidates = Wire(Vec(oooP.stidCount, Bool())) - val pullCandidateStids = Wire(Vec(oooP.stidCount, UInt(oooP.stidWidth.W))) - for (offset <- 0 until oooP.stidCount) { - val candidate = - if (oooP.stidCount == 1) 0.U(oooP.stidWidth.W) - else (pullStid + offset.U)(oooP.stidWidth - 1, 0) - pullCandidateStids(offset) := candidate - pullCandidates(offset) := !io.fence(candidate) - } - val anyPullCandidate = pullCandidates.asUInt.orR - val pullOffset = PriorityEncoder(pullCandidates.asUInt) - val selectedPullStid = - if (oooP.stidCount == 1) 0.U(oooP.stidWidth.W) - else Mux(anyPullCandidate, pullCandidateStids(pullOffset), pullStid) - - io.ifuThreadId := selectedPullStid.pad(ifuP.threadIdWidth) - when(!io.flush.valid && (!io.ifuD1.valid || io.ifuD1.fire)) { - pullStid := Mux( - selectedPullStid === (oooP.stidCount - 1).U, - 0.U, - selectedPullStid + 1.U) - } - - val inMask = io.ifuD1.bits.validMask - val inLaneCount = PopCount(inMask) - val inHasRows = inLaneCount.orR - val inStid = io.ifuD1.bits.entries(0).identity.threadId - val inStidSupported = inStid < oooP.stidCount.U - val inBank = inStid(oooP.stidWidth - 1, 0) - val inFenced = inStidSupported && io.fence(inBank) - val inPeId = io.ifuD1.bits.entries(0).identity.peId - val inEpoch = io.ifuD1.bits.entries(0).identity.epoch - val inDense = denseMask(inMask, ifuP.decodeWidth) - val inSameContext = (0 until ifuP.decodeWidth).map { lane => - !inMask(lane) || ( - io.ifuD1.bits.entries(lane).identity.threadId === inStid && - io.ifuD1.bits.entries(lane).identity.peId === inPeId && - io.ifuD1.bits.entries(lane).identity.epoch === inEpoch && - io.ifuD1.bits.entries(lane).prediction.epoch === inEpoch) - }.reduce(_ && _) - val malformedInput = !inHasRows || !inDense || !inStidSupported || !inSameContext - - val selectSupported = io.selectStid < oooP.stidCount.U - val selectedBank = io.selectStid - val selectedCount = Mux(selectSupported, counts(selectedBank), 0.U) - val selectedHead = entries(selectedBank)(heads(selectedBank)) - - val outputPrefix = Wire(Vec(oooP.instructionDecodeWidth, Bool())) - for (lane <- 0 until oooP.instructionDecodeWidth) { - val readPtr = advancePtr(heads(selectedBank), lane.U) - val candidate = entries(selectedBank)(readPtr) - val present = lane.U < selectedCount - val sameContext = - candidate.identity.peId === selectedHead.identity.peId && - candidate.identity.threadId === selectedHead.identity.threadId && - candidate.identity.epoch === selectedHead.identity.epoch && - candidate.prediction.epoch === selectedHead.identity.epoch - outputPrefix(lane) := - present && sameContext && (if (lane == 0) true.B else outputPrefix(lane - 1)) - } - val emittedLaneCount = PopCount(outputPrefix) - - // The canonical flush cycle is a global publication barrier. Only the - // addressed bank is mutated; every unaffected bank resumes on the next - // cycle without losing or duplicating its head transaction. - io.out.valid := selectSupported && selectedCount.orR && - !io.fence(selectedBank) && !io.flush.valid - io.out.bits := 0.U.asTypeOf(io.out.bits) - io.out.bits.peId := selectedHead.identity.peId - io.out.bits.stid := selectedHead.identity.threadId - io.out.bits.epoch := selectedHead.identity.epoch - io.out.bits.validMask := outputPrefix.asUInt - io.out.bits.endOfStream := false.B - for (lane <- 0 until oooP.instructionDecodeWidth) { - val readPtr = advancePtr(heads(selectedBank), lane.U) - when(outputPrefix(lane)) { - mapEntry(io.out.bits.entries(lane), entries(selectedBank)(readPtr)) - } - } - - val outFire = io.out.valid && io.out.ready - val sameBankFire = - outFire && inStidSupported && inBank === selectedBank - val reclaimedRows = Mux(sameBankFire, emittedLaneCount, 0.U) - val freeRows = - depthPerStid.U((countWidth + 1).W) - - counts(inBank).pad(countWidth + 1) + - reclaimedRows.pad(countWidth + 1) - val inCanFit = freeRows >= inLaneCount.pad(countWidth + 1) - - io.ifuD1.ready := - !io.flush.valid && !inFenced && !malformedInput && inCanFit - val inFire = io.ifuD1.valid && io.ifuD1.ready - - io.counts := counts - io.eligibleMask := VecInit((0 until oooP.stidCount).map { stid => - counts(stid).orR && !io.fence(stid) - }).asUInt - io.acceptedLaneCount := Mux(inFire, inLaneCount, 0.U) - io.emittedLaneCount := Mux(outFire, emittedLaneCount, 0.U) - io.malformedInput := io.ifuD1.valid && malformedInput - - when(io.ifuD1.valid) { - assert(!malformedInput, - "IFU raw ingress requires a non-empty dense same-PE/STID/epoch prefix") - } - when(io.out.valid) { - assert(outputPrefix(0), "OOO raw ingress may only publish a non-empty prefix") - assert(io.out.bits.stid === io.selectStid) - for (lane <- 0 until oooP.instructionDecodeWidth) { - when(io.out.bits.validMask(lane)) { - assert(io.out.bits.entries(lane).parent.key.valid) - assert(io.out.bits.entries(lane).parent.key.peId === io.out.bits.peId) - assert(io.out.bits.entries(lane).parent.key.stid === io.out.bits.stid) - assert(io.out.bits.entries(lane).parent.key.epoch === io.out.bits.epoch) - assert(io.out.bits.entries(lane).parent.prediction.epoch === io.out.bits.epoch) - } - } - } - - when(io.flush.valid) { - for (stid <- 0 until oooP.stidCount) { - when(io.flush.threadId === stid.U) { - when(io.flush.scope === IfuPruneScope.KillAllThreadState) { - heads(stid) := 0.U - tails(stid) := 0.U - counts(stid) := 0.U - }.otherwise { - val keep = Wire(Vec(depthPerStid, Bool())) - for (offset <- 0 until depthPerStid) { - val readPtr = advancePtr(heads(stid), offset.U) - keep(offset) := - offset.U < counts(stid) && - !IfuFlushContract.killsInstruction(entries(stid)(readPtr), io.flush) - } - val keepPrefix = Wire(Vec(depthPerStid + 1, UInt(countWidth.W))) - keepPrefix(0) := 0.U - for (offset <- 0 until depthPerStid) { - val readPtr = advancePtr(heads(stid), offset.U) - val writePtr = keepPrefix(offset)(ptrWidth - 1, 0) - keepPrefix(offset + 1) := keepPrefix(offset) + keep(offset).asUInt - when(keep(offset)) { - val retained = Wire(new InstructionBufferEntry(ifuP)) - retained := entries(stid)(readPtr) - when(io.flush.terminalSteer) { - retained.identity.epoch := io.flush.newEpoch - retained.prediction.epoch := io.flush.newEpoch - } - entries(stid)(writePtr) := retained - } - } - val keptCount = keepPrefix(depthPerStid) - heads(stid) := 0.U - tails(stid) := keptCount(ptrWidth - 1, 0) - counts(stid) := keptCount - } - } - } - }.otherwise { - when(outFire) { - heads(selectedBank) := advancePtr(heads(selectedBank), emittedLaneCount) - } - when(inFire) { - for (lane <- 0 until ifuP.decodeWidth) { - val priorMask = - if (lane == 0) 0.U(ifuP.decodeWidth.W) - else inMask(lane - 1, 0).pad(ifuP.decodeWidth) - val writeOffset = PopCount(priorMask) - val writePtr = advancePtr(tails(inBank), writeOffset) - when(inMask(lane)) { - entries(inBank)(writePtr) := io.ifuD1.bits.entries(lane) - } - } - tails(inBank) := advancePtr(tails(inBank), inLaneCount) - } - - when(inFire && outFire && inBank === selectedBank) { - counts(inBank) := - counts(inBank) + inLaneCount.pad(countWidth) - emittedLaneCount.pad(countWidth) - }.otherwise { - when(inFire) { - counts(inBank) := counts(inBank) + inLaneCount.pad(countWidth) - } - when(outFire) { - counts(selectedBank) := counts(selectedBank) - emittedLaneCount.pad(countWidth) - } - } - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala b/chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala index 22fe9ae9..dfedf2af 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala @@ -1,300 +1,238 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{PopCount, Valid} +import chisel3.util.{Mux1H, Valid} +import linxcore.params.CoreParams +import linxcore.top.interface._ -class OooMemoryOrderAllocatorIO(val p: OooParams = OooParams()) - extends Bundle { - val prepare = Flipped(Valid(new OooD2GroupedTransaction(p))) +class OooMemoryOrderAllocatorIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Valid(new D2AdmissionGroup(p))) val prepareReady = Output(Bool()) - val prepared = Output(new OooMemoryOrderReservationLease(p)) + val prepared = Output(new MemoryOrderReservation(p)) + val preparedLanes = Output(Vec(p.ooo.d3PrefixWidth, new MemoryOrderMeta(p))) val reserveFire = Input(Bool()) - - /** Exact D3 row selected for the common S1 publication. */ - val publishPrepare = Flipped(Valid(new OooD3GroupedReservation(p))) + val publishPrepare = Flipped(Valid(new D3RenameGroup(p))) val publishReady = Output(Bool()) val publishFire = Input(Bool()) - - val cancel = Input(Vec(p.stidCount, Bool())) - - val recoveryPrepare = Flipped(Valid(new OooRobRecoveryPlan(p))) + val cancel = Input(Vec(p.ooo.stidCount, Bool())) + val recoveryPrepare = Flipped(Valid(new OOORobMemoryRecovery(p))) val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooMemoryOrderRecoveryPrepared(p)) val recoveryFire = Input(Bool()) - - val provisional = Output(Vec(p.stidCount, - new OooMemoryOrderReservationLease(p))) - val next = Output(Vec(p.stidCount, new OooMemoryIdState(p))) - val prepareRejected = Valid(new OooMemoryOrderPrepareReject(p)) - val recoveryRejected = Valid(new OooMemoryOrderRecoveryReject(p)) + val next = Output(Vec(p.ooo.stidCount, new MemoryOrderState(p))) + val provisional = Output(Vec(p.ooo.stidCount, new MemoryOrderReservation(p))) + val provisionalLanes = Output(Vec(p.ooo.stidCount, + Vec(p.ooo.d3PrefixWidth, new MemoryOrderMeta(p)))) } -/** Canonical full-LSID, load-ID, and store-ID owner. - * - * D2 supplies only demand. One exact D3 reserve fire claims all serial ranges - * for the transaction and retains a per-STID provisional lease. Common S1 - * publication consumes that lease. Cancellation rolls back only the private - * provisional suffix. Global recovery restores the serial tails from the - * ROB-owned group snapshots on the same common apply used by ROB, rename, - * dispatch, and IEX. - * - * The serials are never physical LHQ/STQ indexes. Future queue owners bind a - * separate generation-qualified lease while preserving these full identities. - */ -class OooMemoryOrderAllocator(val p: OooParams = OooParams()) extends Module { +/** Sole OOO owner of full LSID/LID/SID program-order tails. */ +class OooMemoryOrderAllocator(val p: CoreParams) extends Module { val io = IO(new OooMemoryOrderAllocatorIO(p)) - - private def sameState(left: OooMemoryIdState, right: OooMemoryIdState): Bool = - left.asUInt === right.asUInt - - val nextState = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooMemoryIdState(p))))) - val provisionalValid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val provisionalRows = Reg(Vec(p.stidCount, - new OooMemoryOrderReservationLease(p))) - - val prepareTransaction = io.prepare.bits - val preparePlan = prepareTransaction.plan - val prepareDecoded = prepareTransaction.decoded - val prepareStid = preparePlan.stid - val prepareStidInRange = prepareStid < p.stidCount.U - val safePrepareStid = Mux(prepareStidInRange, prepareStid, 0.U) - - val allocationState = Wire(Vec(p.decodedUopWidth + 1, - new OooMemoryIdState(p))) - allocationState(0) := nextState(safePrepareStid) - val allocations = Wire(Vec(p.decodedUopWidth, - new OooMemoryOrderUopAllocation(p))) - val calculatedLoadIds = Wire(Vec(p.decodedUopWidth, - UInt(p.memoryDemandWidth.W))) - val calculatedStoreIds = Wire(Vec(p.decodedUopWidth, - UInt(p.memoryDemandWidth.W))) - val uopShapeExact = Wire(Vec(p.decodedUopWidth, Bool())) - - for (uopIndex <- 0 until p.decodedUopWidth) { - val uop = prepareDecoded.uops(uopIndex) - val active = prepareDecoded.uopMask(uopIndex) - val requestCount = uop.recipe.memoryRequestCount + private val width = p.ooo.d3PrefixWidth + private def select[T <: Data](values: Vec[T], index: UInt): T = + if (p.ooo.stidCount == 1) values(0) else values(index) + + private def sameState(a: MemoryOrderState, b: MemoryOrderState): Bool = + a.asUInt === b.asUInt + + val nextState = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U.asTypeOf(new MemoryOrderState(p))))) + val provisionalValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + val provisionalRows = Reg(Vec(p.ooo.stidCount, new MemoryOrderReservation(p))) + val provisionalMetas = Reg(Vec(p.ooo.stidCount, + Vec(width, new MemoryOrderMeta(p)))) + + val prepareStidRaw = io.prepare.bits.entries(0).uop.rob.stid + val prepareStidInRange = prepareStidRaw < p.ooo.stidCount.U + val prepareStid = Mux(prepareStidInRange, prepareStidRaw, 0.U) + val publishStidRaw = io.publishPrepare.bits.entries(0).uop.decoded.rob.stid + val publishStid = Mux(publishStidRaw < p.ooo.stidCount.U, publishStidRaw, 0.U) + val livePublish = select(provisionalRows, publishStid) + val livePublishMetas = select(provisionalMetas, publishStid) + val publishCount = io.publishPrepare.bits.count + val publishReady = Wire(Bool()) + val finalPublish = io.publishFire && publishReady && + publishCount === livePublish.count + val sameStidFinalPublish = finalPublish && + publishStidRaw === prepareStidRaw + val states = Wire(Vec(width + 1, new MemoryOrderState(p))) + val metas = Wire(Vec(width, new MemoryOrderMeta(p))) + val laneExact = Wire(Vec(width, Bool())) + states(0) := Mux(sameStidFinalPublish, livePublish.after, + select(nextState, prepareStid)) + for (lane <- 0 until width) { + val active = lane.U < io.prepare.bits.count + val uop = io.prepare.bits.entries(lane).uop + val requestCount = uop.memory.requestCount val typedMemory = uop.memory.valid && (uop.memory.isLoad ^ uop.memory.isStore) - val memoryActive = active && uop.valid && uop.recipe.valid && - typedMemory && requestCount.orR + val memoryActive = active && typedMemory && requestCount.orR val loadActive = memoryActive && uop.memory.isLoad val storeActive = memoryActive && uop.memory.isStore - val allocation = allocations(uopIndex) - - allocation := 0.U.asTypeOf(allocation) - allocation.valid := active - allocation.memoryValid := memoryActive - allocation.isLoad := loadActive - allocation.isStore := storeActive - allocation.requestCount := Mux(memoryActive, requestCount, 0.U) - allocation.firstLsid := allocationState(uopIndex).lsid - allocation.firstTypeId := Mux(loadActive, - allocationState(uopIndex).loadId, - allocationState(uopIndex).storeId) - allocation.before := allocationState(uopIndex) - allocation.after := allocationState(uopIndex) - allocation.after.lsid := allocationState(uopIndex).lsid + + metas(lane) := 0.U.asTypeOf(metas(lane)) + metas(lane).requestCount := Mux(memoryActive, requestCount, 0.U) + metas(lane).firstLsid := states(lane).lsid + metas(lane).firstLid := states(lane).lid + metas(lane).firstSid := states(lane).sid + metas(lane).yostValid := states(lane).yostValid + metas(lane).yostLsid := states(lane).yostLsid + metas(lane).yostSid := states(lane).yostSid + metas(lane).yoldValid := states(lane).yoldValid + metas(lane).yoldLsid := states(lane).yoldLsid + metas(lane).yoldLid := states(lane).yoldLid + states(lane + 1) := states(lane) + states(lane + 1).lsid := states(lane).lsid + Mux(memoryActive, requestCount, 0.U) - allocation.after.loadId := allocationState(uopIndex).loadId + + states(lane + 1).lid := states(lane).lid + Mux(loadActive, requestCount, 0.U) - allocation.after.storeId := allocationState(uopIndex).storeId + + states(lane + 1).sid := states(lane).sid + Mux(storeActive, requestCount, 0.U) - allocation.after.youngestStoreLsidValid := - allocationState(uopIndex).youngestStoreLsidValid || storeActive - allocation.after.youngestStoreLsid := Mux(storeActive, - allocationState(uopIndex).lsid + requestCount - 1.U, - allocationState(uopIndex).youngestStoreLsid) - allocationState(uopIndex + 1) := allocation.after - - calculatedLoadIds(uopIndex) := Mux(loadActive, requestCount, 0.U) - calculatedStoreIds(uopIndex) := Mux(storeActive, requestCount, 0.U) - uopShapeExact(uopIndex) := !active || ( - uop.valid && uop.recipe.valid && - (requestCount.orR === typedMemory) && - requestCount <= p.maxMemoryRequestsPerInstruction.U) - } - - val calculatedLoadTotal = calculatedLoadIds.reduce(_ +& _) - val calculatedStoreTotal = calculatedStoreIds.reduce(_ +& _) - val identityExact = preparePlan.peId === prepareDecoded.peId && - preparePlan.stid === prepareDecoded.stid && - preparePlan.epoch === prepareDecoded.epoch && - preparePlan.uopMask === prepareDecoded.uopMask - val demandExact = calculatedLoadTotal === preparePlan.demand.loadIds && - calculatedStoreTotal === preparePlan.demand.storeIds && - preparePlan.demand.loadIds === prepareDecoded.demand.loadIds && - preparePlan.demand.storeIds === prepareDecoded.demand.storeIds - val shapeExact = prepareStidInRange && identityExact && demandExact && - uopShapeExact.asUInt.andR - val replacesPublishedLease = io.publishFire && - io.publishPrepare.valid && - io.publishPrepare.bits.transaction.plan.stid === prepareStid - val prepareSlotAvailable = !provisionalValid(safePrepareStid) || - replacesPublishedLease - - val prepared = Wire(new OooMemoryOrderReservationLease(p)) - prepared := 0.U.asTypeOf(prepared) - prepared.valid := io.prepare.valid && shapeExact && - prepareSlotAvailable - prepared.peId := preparePlan.peId - prepared.stid := prepareStid - prepared.epoch := preparePlan.epoch - prepared.transactionId := preparePlan.transactionId - prepared.uopMask := prepareDecoded.uopMask - prepared.before := allocationState(0) - prepared.after := allocationState(p.decodedUopWidth) - prepared.uops := allocations - io.prepared := prepared - io.prepareReady := shapeExact && prepareSlotAvailable - io.prepareRejected.valid := io.prepare.valid && !io.prepareReady - io.prepareRejected.bits.stid := prepareStid - io.prepareRejected.bits.transactionId := preparePlan.transactionId - io.prepareRejected.bits.requestedLoadIds := preparePlan.demand.loadIds - io.prepareRejected.bits.requestedStoreIds := preparePlan.demand.storeIds - io.prepareRejected.bits.calculatedLoadIds := calculatedLoadTotal - io.prepareRejected.bits.calculatedStoreIds := calculatedStoreTotal - io.prepareRejected.bits.occupied := provisionalValid(safePrepareStid) - - val publishReservation = io.publishPrepare.bits - val publishPlan = publishReservation.transaction.plan - val publishStid = publishPlan.stid - val publishStidInRange = publishStid < p.stidCount.U - val safePublishStid = Mux(publishStidInRange, publishStid, 0.U) - val livePublishLease = provisionalRows(safePublishStid) - val publishExact = publishStidInRange && - provisionalValid(safePublishStid) && livePublishLease.valid && - livePublishLease.peId === publishPlan.peId && - livePublishLease.stid === publishPlan.stid && - livePublishLease.epoch === publishPlan.epoch && - livePublishLease.transactionId === publishPlan.transactionId && - livePublishLease.uopMask === publishPlan.uopMask && - sameState(livePublishLease.after, nextState(safePublishStid)) - io.publishReady := io.publishPrepare.valid && publishExact - - val recoveryPlan = io.recoveryPrepare.bits - val recoveryStid = recoveryPlan.request.rename.key.member.group.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryKilledCount = recoveryPlan.killedGroupCount - val safeLastKilledIndex = Mux(recoveryKilledCount.orR, - recoveryKilledCount - 1.U, 0.U)(p.ridSlotWidth - 1, 0) - val lastKilled = recoveryPlan.killedGroups(safeLastKilledIndex) - val oldPublishedTailRow = Mux(recoveryKilledCount.orR, - lastKilled, recoveryPlan.pivot) - val oldPublishedTail = oldPublishedTailRow.memoryAfter - val newTail = Mux(recoveryPlan.newOccupied.orR, - recoveryPlan.survivingTail.memoryAfter, - recoveryPlan.pivot.memoryBefore) - - val killedRowsExact = Wire(Vec(p.robGroupsPerStid, Bool())) - val killedChainExact = Wire(Vec(p.robGroupsPerStid, Bool())) - for (index <- 0 until p.robGroupsPerStid) { - val active = index.U < recoveryKilledCount - val row = recoveryPlan.killedGroups(index) - val previousTail = if (index == 0) { - Mux(recoveryPlan.survivingPivotValid, - recoveryPlan.pivot.memoryAfter, - Mux(recoveryPlan.newOccupied.orR, - recoveryPlan.survivingTail.memoryAfter, - recoveryPlan.pivot.memoryBefore)) - } else { - recoveryPlan.killedGroups(index - 1).memoryAfter + when(loadActive) { + states(lane + 1).yoldValid := true.B + states(lane + 1).yoldLsid := states(lane).lsid + requestCount - 1.U + states(lane + 1).yoldLid := states(lane).lid + requestCount - 1.U } - killedRowsExact(index) := !active || - (row.valid && row.memoryOrderValid) - killedChainExact(index) := !active || - sameState(row.memoryBefore, previousTail) + when(storeActive) { + states(lane + 1).yostValid := true.B + states(lane + 1).yostLsid := states(lane).lsid + requestCount - 1.U + states(lane + 1).yostSid := states(lane).sid + requestCount - 1.U + } + laneExact(lane) := !active || (uop.valid && + (typedMemory === requestCount.orR) && + requestCount <= p.maxMemoryRequestsPerInstruction.U) } - val publishedChainExact = recoveryPlan.valid && - recoveryPlan.oldOccupied.orR && recoveryPlan.pivot.memoryOrderValid && - (!recoveryPlan.newOccupied.orR || - (recoveryPlan.survivingTailValid && - recoveryPlan.survivingTail.memoryOrderValid)) && - oldPublishedTailRow.valid && oldPublishedTailRow.memoryOrderValid && - killedRowsExact.asUInt.andR && killedChainExact.asUInt.andR - - val recoveryHasProvisional = provisionalValid(safeRecoveryStid) - val recoveryProvisional = provisionalRows(safeRecoveryStid) - val provisionalExact = !recoveryHasProvisional || ( - recoveryProvisional.valid && - recoveryProvisional.stid === recoveryStid && - sameState(recoveryProvisional.before, oldPublishedTail) && - sameState(recoveryProvisional.after, nextState(safeRecoveryStid))) - val liveTailExact = Mux(recoveryHasProvisional, - sameState(nextState(safeRecoveryStid), recoveryProvisional.after), - sameState(nextState(safeRecoveryStid), oldPublishedTail)) - val recoveryExact = io.recoveryPrepare.valid && recoveryPlan.valid && - recoveryStidInRange && publishedChainExact && provisionalExact && - liveTailExact - - io.recoveryPrepareReady := recoveryExact - io.recoveryPrepared.valid := recoveryExact - io.recoveryPrepared.stid := recoveryStid - io.recoveryPrepared.oldPublishedTail := oldPublishedTail - io.recoveryPrepared.newTail := newTail - io.recoveryPrepared.provisionalKilled := recoveryHasProvisional - io.recoveryRejected.valid := io.recoveryPrepare.valid && !recoveryExact - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.stidInRange := recoveryStidInRange - io.recoveryRejected.bits.publishedChainExact := publishedChainExact - io.recoveryRejected.bits.liveTailExact := liveTailExact - io.recoveryRejected.bits.provisionalExact := provisionalExact + val countExact = io.prepare.bits.count.orR && + io.prepare.bits.count <= width.U + val commonStidExact = (0 until width).map { lane => + lane.U >= io.prepare.bits.count || + io.prepare.bits.entries(lane).uop.rob.stid === prepareStidRaw + }.reduce(_ && _) + val slotAvailable = !select(provisionalValid, prepareStid) || + sameStidFinalPublish + io.prepareReady := prepareStidInRange && countExact && commonStidExact && + laneExact.asUInt.andR && slotAvailable + io.prepared := 0.U.asTypeOf(io.prepared) + io.prepared.valid := io.prepare.valid && io.prepareReady + io.prepared.stid := prepareStidRaw + io.prepared.count := io.prepare.bits.count + io.prepared.before := states(0) + io.prepared.after := states(width) + io.preparedLanes := metas + + val publishCountExact = publishCount.orR && publishCount <= livePublish.count + val stateAfterPrefix = Wire(new MemoryOrderState(p)) + stateAfterPrefix := livePublish.after + val nextPrefixMeta = Mux1H((0 until width).map { lane => + (publishCount === lane.U) -> livePublishMetas(lane) + }) + when(publishCount < livePublish.count) { + stateAfterPrefix.lsid := nextPrefixMeta.firstLsid + stateAfterPrefix.lid := nextPrefixMeta.firstLid + stateAfterPrefix.sid := nextPrefixMeta.firstSid + stateAfterPrefix.yostValid := nextPrefixMeta.yostValid + stateAfterPrefix.yostLsid := nextPrefixMeta.yostLsid + stateAfterPrefix.yostSid := nextPrefixMeta.yostSid + stateAfterPrefix.yoldValid := nextPrefixMeta.yoldValid + stateAfterPrefix.yoldLsid := nextPrefixMeta.yoldLsid + stateAfterPrefix.yoldLid := nextPrefixMeta.yoldLid + } + val expectedPublication = Wire(new MemoryOrderReservation(p)) + expectedPublication := 0.U.asTypeOf(expectedPublication) + expectedPublication.valid := livePublish.valid + expectedPublication.stid := livePublish.stid + expectedPublication.count := publishCount + expectedPublication.before := livePublish.before + expectedPublication.after := stateAfterPrefix + val publishExact = publishStidRaw < p.ooo.stidCount.U && + select(provisionalValid, publishStid) && livePublish.valid && + livePublish.stid === publishStidRaw && + publishCountExact && + io.publishPrepare.bits.memoryOrder.asUInt === expectedPublication.asUInt && + (0 until width).map { lane => + lane.U >= publishCount || + io.publishPrepare.bits.entries(lane).memoryOrder.asUInt === + livePublishMetas(lane).asUInt + }.reduce(_ && _) && + sameState(livePublish.after, select(nextState, publishStid)) + publishReady := io.publishPrepare.valid && publishExact + io.publishReady := publishReady + + val recoveryStidRaw = io.recoveryPrepare.bits.stid + val recoveryStid = Mux(recoveryStidRaw < p.ooo.stidCount.U, + recoveryStidRaw, 0.U) + val recoveryLiveExact = Mux(select(provisionalValid, recoveryStid), + sameState(select(provisionalRows, recoveryStid).before, + io.recoveryPrepare.bits.oldTail) && + sameState(select(provisionalRows, recoveryStid).after, + select(nextState, recoveryStid)), + sameState(select(nextState, recoveryStid), io.recoveryPrepare.bits.oldTail)) + io.recoveryPrepareReady := io.recoveryPrepare.valid && + io.recoveryPrepare.bits.valid && recoveryStidRaw < p.ooo.stidCount.U && + recoveryLiveExact when(io.reserveFire) { - assert(io.prepare.valid && io.prepareReady && prepared.valid, - "memory-order reserve requires one exact prepared D2 transaction") - provisionalValid(safePrepareStid) := true.B - provisionalRows(safePrepareStid) := prepared - nextState(safePrepareStid) := prepared.after + assert(io.prepare.valid && io.prepareReady) + when(select(provisionalValid, prepareStid)) { + assert(sameStidFinalPublish, + "memory-order replacement requires final publication of the old reservation") + } + select(provisionalValid, prepareStid) := true.B + select(provisionalRows, prepareStid) := io.prepared + select(provisionalMetas, prepareStid) := io.preparedLanes + select(nextState, prepareStid) := io.prepared.after } - when(io.publishFire) { - assert(io.publishPrepare.valid && io.publishReady, - "memory-order publication requires the retained exact D3 lease") - when(!(io.reserveFire && safePrepareStid === safePublishStid)) { - provisionalValid(safePublishStid) := false.B - provisionalRows(safePublishStid) := - 0.U.asTypeOf(new OooMemoryOrderReservationLease(p)) + assert(io.publishReady) + val remaining = livePublish.count - publishCount + when(remaining.orR) { + val suffix = Wire(new MemoryOrderReservation(p)) + suffix := livePublish + suffix.count := remaining + suffix.before := stateAfterPrefix + val suffixMetas = Wire(Vec(width, new MemoryOrderMeta(p))) + suffixMetas := 0.U.asTypeOf(suffixMetas) + for (lane <- 0 until width) { + for (source <- 0 until width) { + when(source.U === lane.U + publishCount && + source.U < livePublish.count) { + suffixMetas(lane) := livePublishMetas(source) + } + } + } + select(provisionalRows, publishStid) := suffix + select(provisionalMetas, publishStid) := suffixMetas + select(provisionalValid, publishStid) := true.B + }.otherwise { + select(provisionalValid, publishStid) := false.B + select(provisionalRows, publishStid) := 0.U.asTypeOf(livePublish) + } + when(io.reserveFire && prepareStid === publishStid) { + assert(finalPublish, + "memory-order reservation capture may replace only a fully published row") + select(provisionalValid, publishStid) := true.B + select(provisionalRows, publishStid) := io.prepared + select(provisionalMetas, publishStid) := io.preparedLanes + select(nextState, publishStid) := io.prepared.after } } - - for (stid <- 0 until p.stidCount) { - val cancelProvisional = io.cancel(stid) && provisionalValid(stid) - when(cancelProvisional) { - assert(!(io.publishFire && safePublishStid === stid.U), - "an exposed common S1 publication cannot be canceled privately") + for (stid <- 0 until p.ooo.stidCount) { + when(io.cancel(stid) && provisionalValid(stid)) { nextState(stid) := provisionalRows(stid).before provisionalValid(stid) := false.B - provisionalRows(stid) := - 0.U.asTypeOf(new OooMemoryOrderReservationLease(p)) + provisionalRows(stid) := 0.U.asTypeOf(provisionalRows(stid)) } } - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady, - "memory-order recovery requires the same exact ROB suffix plan") - nextState(safeRecoveryStid) := newTail - provisionalValid(safeRecoveryStid) := false.B - provisionalRows(safeRecoveryStid) := - 0.U.asTypeOf(new OooMemoryOrderReservationLease(p)) - } - - when(io.reserveFire) { - assert(!io.cancel(safePrepareStid), - "memory-order reserve and cancel cannot target the same STID") - } - when(io.recoveryFire) { - assert(!(io.reserveFire && safePrepareStid === safeRecoveryStid), - "memory-order reserve and recovery cannot target the same STID") - assert(!(io.publishFire && safePublishStid === safeRecoveryStid), - "memory-order publication and recovery cannot target the same STID") - } - - for (stid <- 0 until p.stidCount) { - io.provisional(stid) := Mux(provisionalValid(stid), - provisionalRows(stid), - 0.U.asTypeOf(new OooMemoryOrderReservationLease(p))) + assert(io.recoveryPrepareReady) + select(nextState, recoveryStid) := io.recoveryPrepare.bits.newTail + select(provisionalValid, recoveryStid) := false.B + select(provisionalRows, recoveryStid) := 0.U.asTypeOf( + select(provisionalRows, recoveryStid)) } io.next := nextState + for (stid <- 0 until p.ooo.stidCount) { + io.provisional(stid) := Mux(provisionalValid(stid), provisionalRows(stid), + 0.U.asTypeOf(provisionalRows(stid))) + io.provisionalLanes(stid) := Mux(provisionalValid(stid), + provisionalMetas(stid), + 0.U.asTypeOf(provisionalMetas(stid))) + } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooO3IexStorePipeline.scala b/chisel/src/main/scala/linxcore/ooo/OooO3IexStorePipeline.scala deleted file mode 100644 index 2ff589dc..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooO3IexStorePipeline.scala +++ /dev/null @@ -1,250 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Valid, log2Ceil} -import linxcore.lsu.{MDBConflictStoreProbe, STQLoadForwardQuery, - STQLoadForwardResponse, STQMemoryClassifyToken, STQSerializedStoreRequest, - STQSerializedStoreResponse} - -/** External production boundary around the retained O3, issue/execute, and - * canonical store-retirement owners. Internal ownership handshakes are not - * re-exported and therefore cannot be acknowledged by placeholder logic. - */ -class OooO3IexStorePipelineIO( - val p: OooParams, - val stqEntries: Int, - val storeCommitQueueEntries: Int, - val scbEntries: Int) extends Bundle { - private val scbResponseTxnIdWidth = math.max(1, log2Ceil(scbEntries)) + 2 - - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val cancel = Input(Vec(p.stidCount, Bool())) - val nonFlushEvidence = Flipped(Decoupled(new OooRobNonFlushEvidence(p))) - val interruptPending = Input(Vec(p.stidCount, Bool())) - val commit = Decoupled(new OooRobCommitBatch(p)) - val recoveryRequest = Flipped(Decoupled(new OooGlobalRecoveryRequest(p))) - - val queryStid = Input(UInt(p.stidWidth.W)) - val queryAtag = Input(UInt(p.archRegWidth.W)) - val speculativeMapping = Output(new PMapPayload(p)) - val committedMapping = Output(new PMapPayload(p)) - - val issuePolicy = Input(new OooIexIssuePolicy(p)) - val stageCancels = Flipped(Vec(p.iexIssueDomainCount, - Vec(2, Decoupled(new OooIexStageCancel(p))))) - val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val pClear = Flipped(Vec(2, Valid(new OooIexPFileKey(p)))) - val tClear = Flipped(Vec(p.tuAllocationWidth, - Valid(new OooIexLocalFileKey(p)))) - val uClear = Flipped(Vec(p.tuAllocationWidth, - Valid(new OooIexLocalFileKey(p)))) - - val fastBoundary = Decoupled(new OooFastResolveBoundaryRequest(p)) - val fastTrace = Decoupled(new OooFastResolveTrace(p)) - val multiCycleAlu = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val system = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val pointerAuth = Vec(2, Decoupled(new OooIexExecuteTransaction(p))) - val floatingVector = Decoupled(new OooIexExecuteTransaction(p)) - val engineCommand = Decoupled(new OooIexExecuteTransaction(p)) - val memoryRequest = Vec(3, Decoupled(new OooIexLoadMemoryRequest(p))) - val memoryResponse = Flipped(Vec(3, - Decoupled(new OooIexLoadMemoryResponse(p)))) - val loadCancel = Output(Vec(p.iexLoadCancelPorts, - Valid(new OooIexLoadCancel(p)))) - val stqLoadForwardQuery = Flipped(Vec(3, Decoupled( - new STQLoadForwardQuery( - p.robGroupsPerStid, stidWidth = p.stidWidth, - lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth)))) - val stqLoadForwardResponse = Vec(3, Decoupled( - new STQLoadForwardResponse( - p.robGroupsPerStid, stqEntries, stidWidth = p.stidWidth, - lsidWidth = p.lsidWidth, tokenWidth = p.transactionIdWidth))) - val stqLoadForwardOccupied = Output(UInt(3.W)) - val lateStaProbe = Output(Valid(new MDBConflictStoreProbe( - p.robGroupsPerStid, peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, tidWidth = p.stidWidth, - sizeWidth = 7, lsidWidth = p.lsidWidth))) - val bctrl = Vec(p.iexTerminalWidth, - Decoupled(new OooIexTerminalBctrl(p))) - val trace = Vec(p.iexTerminalWidth, - Decoupled(new OooIexTerminalTrace(p))) - - val memoryClassify = Flipped(Decoupled(new STQMemoryClassifyToken( - stqEntries, p.robGroupsPerStid, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth, - p.executeSlotGenerationWidth))) - val storeCommitIssueEnable = Input(Bool()) - val storeEvictEnable = Input(Bool()) - val storeDcacheReady = Input(Bool()) - val storeDcacheWriteHit = Input(Bool()) - val storeDcacheTagHit = Input(Bool()) - val storeL2RequestReady = Input(Bool()) - val storeRawRespValid = Input(Bool()) - val storeRawRespTxnId = Input(UInt(scbResponseTxnIdWidth.W)) - val storeRawRespWrite = Input(Bool()) - val storeRawRespUpgrade = Input(Bool()) - val storeRawRespReady = Output(Bool()) - val serializedStoreRequest = Decoupled(new STQSerializedStoreRequest( - stqEntries, p.robGroupsPerStid, lsidWidth = p.lsidWidth, - peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth)) - val serializedStoreResponse = Flipped(Decoupled( - new STQSerializedStoreResponse())) - - val publishFire = Output(Bool()) - val fastTerminalFire = Output(Bool()) - val completionBufferUsed = Output(UInt(p.robCompletionBufferCountWidth.W)) - val storeCommitUsed = Output(UInt(p.storeCommitBufferCountWidth.W)) - val recoveryBusy = Output(Bool()) - val recoveryComplete = Output(Bool()) - val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) - val transferFireMask = Output(UInt(p.iexReleaseWidth.W)) - val stqOccupiedMask = Output(UInt(stqEntries.W)) - val storeCommitQueueCount = Output(UInt( - log2Ceil(storeCommitQueueEntries + 1).W)) - val issueEmpty = Output(Bool()) - val executionEmpty = Output(Bool()) - val storeEmpty = Output(Bool()) - val empty = Output(Bool()) - val pProtocolError = Output(Bool()) - val localProtocolError = Output(Bool()) - val storeCommitProtocolError = Output(Bool()) -} - -/** Production retained path from grouped D2 transactions through O3, typed - * issue/execute, exact ROB completion, and canonical STQ/CommitQ/SCB store - * retirement. - * - * The composition closes five formerly external ownership seams: S1 publish, - * IQ release, PTag recycle, all execution completion lanes, and exact ROB - * store-commit tokens. PC lookup and global recovery are also private common - * transactions. Fast results use their dedicated PRF+wakeup ingress while - * boundary and trace publication remain explicit architectural sinks. - */ -class OooO3IexStorePipeline( - val profile: OooIexPhysicalProfile = OooIexLinxPhysicalProfile(), - val stqEntries: Int = 16, - val storeCommitQueueEntries: Int = 16, - val storeCommitIssueWidth: Int = 2, - val scbEntries: Int = 16, - val scbResponseBufferDepth: Int = 4, - val storeLineBytes: Int = 64) extends Module { - val p = profile.params - val io = IO(new OooO3IexStorePipelineIO( - p, stqEntries, storeCommitQueueEntries, scbEntries)) - - val o3 = Module(new OooO3RenameCoordinator( - p, profile.capabilityTopology)) - val iex = Module(new OooIexExecutionStorePipeline( - profile, stqEntries, storeCommitQueueEntries, storeCommitIssueWidth, - scbEntries, scbResponseBufferDepth, storeLineBytes)) - - o3.io.reserve <> io.reserve - o3.io.cancel := io.cancel - o3.io.nonFlushEvidence <> io.nonFlushEvidence - o3.io.interruptPending := io.interruptPending - io.commit <> o3.io.commit - o3.io.recoveryRequest <> io.recoveryRequest - o3.io.queryStid := io.queryStid - o3.io.queryAtag := io.queryAtag - io.speculativeMapping := o3.io.speculativeMapping - io.committedMapping := o3.io.committedMapping - - iex.io.s1 <> o3.io.iexS1 - o3.io.dispatchReleases <> iex.io.dispatchReleases - iex.io.ptagRecycle <> o3.io.ptagRecycle - for (lane <- 0 until p.iexTerminalWidth) { - o3.io.completions(lane) <> iex.io.completion(lane) - } - iex.io.robStoreCommit <> o3.io.storeCommit - - iex.io.recoveryPrepare := o3.io.iexRecoveryPrepare - o3.io.iexRecoveryPrepareReady := iex.io.recoveryPrepareReady - o3.io.iexRecoveryPrepared := iex.io.recoveryPrepared - o3.io.iexRecoveryRejected := iex.io.recoveryRejected - iex.io.recoveryFire := o3.io.iexRecoveryFire - - for (port <- 0 until p.pcReadPorts) { - o3.io.pcReadTokens(port) := iex.io.pcReadRequests(port).bits.token - iex.io.pcReadResponses(port).valid := - iex.io.pcReadRequests(port).valid && o3.io.pcReadValid(port) - iex.io.pcReadResponses(port).bits := o3.io.pcRead(port) - } - - iex.io.fastWriteback <> o3.io.fastWriteback - iex.io.fastWakeup <> o3.io.fastWakeup - io.fastBoundary <> o3.io.fastBoundary - io.fastTrace <> o3.io.fastTrace - - iex.io.issuePolicy := io.issuePolicy - iex.io.stageCancels <> io.stageCancels - iex.io.pInit := io.pInit - iex.io.pClear := io.pClear - iex.io.tClear := io.tClear - iex.io.uClear := io.uClear - for (index <- 0 until 2) { - io.multiCycleAlu(index) <> iex.io.multiCycleAlu(index) - io.system(index) <> iex.io.system(index) - io.pointerAuth(index) <> iex.io.pointerAuth(index) - } - io.floatingVector <> iex.io.floatingVector - io.engineCommand <> iex.io.engineCommand - for (index <- 0 until 3) { - io.memoryRequest(index) <> iex.io.memoryRequest(index) - iex.io.memoryResponse(index) <> io.memoryResponse(index) - } - io.loadCancel := iex.io.loadCancel - iex.io.stqLoadForwardQuery <> io.stqLoadForwardQuery - io.stqLoadForwardResponse <> iex.io.stqLoadForwardResponse - io.stqLoadForwardOccupied := iex.io.stqLoadForwardOccupied - io.lateStaProbe := iex.io.lateStaProbe - for (lane <- 0 until p.iexTerminalWidth) { - io.bctrl(lane) <> iex.io.bctrl(lane) - io.trace(lane) <> iex.io.trace(lane) - } - - iex.io.memoryClassify <> io.memoryClassify - iex.io.storeCommitIssueEnable := io.storeCommitIssueEnable - iex.io.storeEvictEnable := io.storeEvictEnable - iex.io.storeDcacheReady := io.storeDcacheReady - iex.io.storeDcacheWriteHit := io.storeDcacheWriteHit - iex.io.storeDcacheTagHit := io.storeDcacheTagHit - iex.io.storeL2RequestReady := io.storeL2RequestReady - iex.io.storeRawRespValid := io.storeRawRespValid - iex.io.storeRawRespTxnId := io.storeRawRespTxnId - iex.io.storeRawRespWrite := io.storeRawRespWrite - iex.io.storeRawRespUpgrade := io.storeRawRespUpgrade - io.storeRawRespReady := iex.io.storeRawRespReady - io.serializedStoreRequest <> iex.io.serializedStoreRequest - iex.io.serializedStoreResponse <> io.serializedStoreResponse - - io.publishFire := o3.io.publishFire - io.fastTerminalFire := o3.io.fastTerminalFire - io.completionBufferUsed := o3.io.completionBufferUsed - io.storeCommitUsed := o3.io.storeCommitUsed - io.recoveryBusy := o3.io.recoveryBusy - io.recoveryComplete := o3.io.recoveryComplete - io.terminalFireMask := iex.io.terminalFireMask - io.transferFireMask := iex.io.transferFireMask - io.stqOccupiedMask := iex.io.stqOccupiedMask - io.storeCommitQueueCount := iex.io.storeCommitQueueCount - io.issueEmpty := iex.io.issueEmpty - io.executionEmpty := iex.io.executionEmpty - io.storeEmpty := iex.io.storeEmpty - val o3ResidencyEmpty = !VecInit(o3.io.robOccupiedGroups.map(_ =/= 0.U)).asUInt.orR && - !VecInit(o3.io.d3UsedGroups.map(_ =/= 0.U)).asUInt.orR && - !VecInit(o3.io.fastPendingByStid.map(_ =/= 0.U)).asUInt.orR && - o3.io.ptagProvisionalCount === 0.U - io.empty := iex.io.empty && o3ResidencyEmpty && - o3.io.completionBufferUsed === 0.U && o3.io.storeCommitUsed === 0.U && - !o3.io.recoveryBusy - io.pProtocolError := iex.io.pProtocolError - io.localProtocolError := iex.io.localProtocolError - io.storeCommitProtocolError := iex.io.storeCommitProtocolError -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooO3RenameCoordinator.scala b/chisel/src/main/scala/linxcore/ooo/OooO3RenameCoordinator.scala deleted file mode 100644 index 9fdb6236..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooO3RenameCoordinator.scala +++ /dev/null @@ -1,740 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, Valid} -import linxcore.common.{DestinationKind, OperandClass} -import linxcore.lsu.STQRobCommitToken - -object OooGlobalRecoveryState extends ChiselEnum { - val Idle, CaptureOwners, PrepareOwners, Rebuild, AbortOwners = Value -} - -class OooO3RenameCoordinatorIO(val p: OooParams = OooParams()) extends Bundle { - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val cancel = Input(Vec(p.stidCount, Bool())) - - val preparedValid = Output(Bool()) - val prepared = Output(new OooPRenamePreparedTransaction(p)) - val tuPrepared = Output(new OooTURenamePreparedTransaction(p)) - val iexS1 = Decoupled(new OooIexS1Transaction(p)) - val publishFire = Output(Bool()) - - val fastBoundary = Decoupled(new OooFastResolveBoundaryRequest(p)) - val fastWriteback = Decoupled(new OooFastResolveWriteback(p)) - val fastWakeup = Decoupled(new OooIexWakeup(p)) - val fastTrace = Decoupled(new OooFastResolveTrace(p)) - val fastPendingByStid = Output(Vec(p.stidCount, - UInt(p.decodedUopCountWidth.W))) - val fastTerminalFire = Output(Bool()) - val fastS1Rejected = Valid(new OooFastResolveS1Reject(p)) - - val completions = Flipped(Vec(p.iexTerminalWidth, - Decoupled(new OooRobMemberCompletion(p)))) - def completion = completions(0) - val completionBufferUsed = Output(UInt(p.robCompletionBufferCountWidth.W)) - val completionBufferFree = Output(UInt(p.robCompletionBufferCountWidth.W)) - val nonFlushEvidence = Flipped(Decoupled(new OooRobNonFlushEvidence(p))) - val interruptPending = Input(Vec(p.stidCount, Bool())) - val nonFlushWindows = Output(Vec(p.stidCount, new NonFlushWindow(p))) - val commit = Decoupled(new OooRobCommitBatch(p)) - val storeCommit = Decoupled(new STQRobCommitToken( - p.robGroupsPerStid, p.lsidWidth, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth)) - val storeCommitUsed = Output(UInt(p.storeCommitBufferCountWidth.W)) - val storeCommitFree = Output(UInt(p.storeCommitBufferCountWidth.W)) - val storeCommitRejected = Valid(new OooRobCommitBatch(p)) - val dispatchReleases = Flipped(Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p)))) - def dispatchRelease = dispatchReleases(0) - val ptagRecycle = Decoupled(new OooPTagReturnBatch(p)) - - val recoveryRequest = Flipped(Decoupled( - new OooGlobalRecoveryRequest(p))) - val recoveryBusy = Output(Bool()) - val recoveryStid = Output(UInt(p.stidWidth.W)) - val recoveryComplete = Output(Bool()) - val recoveryCompleted = Valid(new OooGlobalRecoveryRequest(p)) - val recoveryApplied = Valid(new OooGlobalRecoveryRequest(p)) - val recoveryAborted = Valid(new OooGlobalRecoveryRequest(p)) - val iexRecoveryPrepare = Valid(new OooResidencyRecoveryPlan(p)) - val iexRecoveryPrepareReady = Input(Bool()) - val iexRecoveryPrepared = Input(new OooIexRecoveryPrepared(p)) - val iexRecoveryRejected = Flipped(Valid(new OooIexRecoveryReject(p))) - val iexRecoveryFire = Output(Bool()) - val recoveryRejected = Valid(new OooRenameRecoveryReject(p)) - val pRecoveryRejected = Valid(new OooPRenameRecoveryReject(p)) - val tuRecoveryRejected = Valid(new OooTURenameRecoveryReject(p)) - val robRecoveryRejected = Valid(new OooRobRecoveryReject(p)) - val d3RecoveryRejected = Valid(new OooD3RecoveryReject(p)) - val brobRecoveryRejected = Valid(new OooBrobRecoveryReject(p)) - val pcRecoveryRejected = Valid(new OooPcRecoveryReject(p)) - val dispatchRecoveryRejected = Valid(new OooDispatchRecoveryReject(p)) - val fastRecoveryRejected = Valid(new OooFastResolveRecoveryReject(p)) - val completionRecoveryRejected = - Valid(new OooRobCompletionBufferRecoveryReject(p)) - val memoryOrderPrepareRejected = Valid(new OooMemoryOrderPrepareReject(p)) - val memoryOrderRecoveryRejected = - Valid(new OooMemoryOrderRecoveryReject(p)) - val memoryOrderNext = Output(Vec(p.stidCount, - new OooMemoryIdState(p))) - val dispatchPrepared = Output(new OooDispatchReservationLease(p)) - val dispatchFreeEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val dispatchProvisionalEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val dispatchPublishedEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val dispatchPrepareRejected = Valid(new OooDispatchPrepareReject(p)) - val dispatchPublishRejected = Valid(new OooDispatchPublishReject(p)) - val dispatchReleaseRejecteds = Vec(p.iexReleaseWidth, - Valid(new OooDispatchReleaseReject(p))) - def dispatchReleaseRejected = dispatchReleaseRejecteds(0) - - val queryStid = Input(UInt(p.stidWidth.W)) - val queryAtag = Input(UInt(p.archRegWidth.W)) - val speculativeMapping = Output(new PMapPayload(p)) - val committedMapping = Output(new PMapPayload(p)) - val mapQUsed = Output(Vec(p.stidCount, UInt(p.pMapQCountWidth.W))) - val tMapQUsed = Output(Vec(p.stidCount, UInt(p.tuMapQCountWidth.W))) - val uMapQUsed = Output(Vec(p.stidCount, UInt(p.tuMapQCountWidth.W))) - val tuRetireSourceUsed = Output(Vec(p.stidCount, - UInt(p.tuRetireSourceCountWidth.W))) - val tRelationUsed = Output(Vec(p.stidCount, - UInt(p.tuRelationCountWidth.W))) - val uRelationUsed = Output(Vec(p.stidCount, - UInt(p.tuRelationCountWidth.W))) - - val pcReadTokens = Input(Vec(p.pcReadPorts, new PcBufferToken(p))) - val pcReadValid = Output(Vec(p.pcReadPorts, Bool())) - val pcRead = Output(Vec(p.pcReadPorts, UInt(p.pcWidth.W))) - - val ptagFreeCount = Output(UInt(p.countWidth(p.pPhysRegs).W)) - val ptagProvisionalCount = Output(UInt(p.countWidth(p.pPhysRegs).W)) - val ptagPublishedCount = Output(UInt(p.countWidth(p.pPhysRegs).W)) - val robOccupiedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3UsedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3PublishedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3TailSlot = Output(Vec(p.stidCount, UInt(p.ridSlotWidth.W))) - val d3TailGeneration = Output(Vec(p.stidCount, - UInt(p.ridGenerationWidth.W))) - val d3TailEpoch = Output(Vec(p.stidCount, - UInt(p.reservationEpochWidth.W))) - val d3NextTransactionId = Output(Vec(p.stidCount, - UInt(p.transactionIdWidth.W))) - val pCommitBusy = Output(Bool()) - val tuCommitBusy = Output(Bool()) - val pCommitRejected = Valid(new OooPRenameCommitReject(p)) - val tuCommitRejected = Valid(new OooTURetireCommitReject(p)) - val tuReserveRejected = Valid(new OooTURenamePrepareReject(p)) - val tuPublicationRejected = Valid(new OooTURenamePublishReject(p)) - val nonFlushEvidenceRejected = Valid(new OooRobNonFlushEvidenceReject(p)) -} - -/** Atomic D3/S1 seam through ROB/BROB/PC, P/T/U rename, and dispatch. - * - * D3 and the PTag staging pool claim on the same reserve handshake. Later, - * ROB/BROB/PC publication, PTag publication, SMAP update, and MapQ insertion - * and exact IQ reservations occur on the same terminal fire. The terminal - * sink is the real retained IEX S1 transaction; no external Boolean permit - * can publish the OOO owners without also transferring that exact payload. - */ -class OooO3RenameCoordinator( - val p: OooParams = OooParams(), - val capabilityTopology: OooIexCapabilityTopology = - OooIexCapabilityTopology(Seq.empty)) extends Module { - private val effectiveCapabilityTopology = - if (capabilityTopology.classBankCapabilities.isEmpty) - OooIexCapabilityTopology.permissive(p) - else capabilityTopology - val io = IO(new OooO3RenameCoordinatorIO(p)) - - val o3 = Module(new OooRobBrobPcCoordinator(p)) - val ptag = Module(new OooPTagStagingPool(p)) - val prename = Module(new OooPRename(p)) - val turename = Module(new OooTURename(p)) - val turetire = Module(new OooTURetire(p)) - val dispatch = Module(new OooDispatch(p, effectiveCapabilityTopology)) - val fast = Module(new OooFastResolve(p)) - val memoryOrder = Module(new OooMemoryOrderAllocator(p)) - val storeCommit = Module(new OooRobStoreCommitOwner(p)) - val completionBuffer = Module(new OooRobCompletionBuffer(p)) - - val preparedStid = o3.io.prepared.request.reservation.transaction.plan.stid - val globalRecoveryState = RegInit(OooGlobalRecoveryState.Idle) - val globalRecoveryRequest = RegInit( - 0.U.asTypeOf(new OooGlobalRecoveryRequest(p))) - val lowerRecoveryAccepted = RegInit(false.B) - val renameRecoveryAccepted = RegInit(false.B) - val globalRecoveryActive = - globalRecoveryState =/= OooGlobalRecoveryState.Idle - val activeRecoveryStid = globalRecoveryRequest.rename.key.member.group.stid - - val recoveryRequestStid = - io.recoveryRequest.bits.rename.key.member.group.stid - val recoveryRequestStidInRange = recoveryRequestStid < p.stidCount.U - val recoveryRequestConflictsPrepared = o3.io.preparedValid && - recoveryRequestStidInRange && preparedStid === recoveryRequestStid - io.recoveryRequest.ready := !globalRecoveryActive && - !recoveryRequestConflictsPrepared - when(io.recoveryRequest.fire) { - globalRecoveryRequest := io.recoveryRequest.bits - lowerRecoveryAccepted := false.B - renameRecoveryAccepted := false.B - globalRecoveryState := OooGlobalRecoveryState.CaptureOwners - } - - val reserveStid = io.reserve.bits.plan.stid - val reserveBlockedByRecovery = io.reserve.valid && ( - (globalRecoveryActive && reserveStid === activeRecoveryStid) || - (io.recoveryRequest.valid && recoveryRequestStidInRange && - reserveStid === recoveryRequestStid)) - val reserveOffer = io.reserve.valid && !reserveBlockedByRecovery - - ptag.io.prepare.valid := reserveOffer - ptag.io.prepare.bits := io.reserve.bits - turename.io.reservePrepare.valid := reserveOffer - turename.io.reservePrepare.bits := io.reserve.bits - dispatch.io.prepare.valid := reserveOffer - dispatch.io.prepare.bits := io.reserve.bits - memoryOrder.io.prepare.valid := reserveOffer - memoryOrder.io.prepare.bits := io.reserve.bits - val renameResourcesReady = ptag.io.prepareReady && turename.io.reserveReady && - dispatch.io.prepareReady && memoryOrder.io.prepareReady - // Stale virtual plans are terminally consumed by D3 even when their obsolete - // P/T/U shape would fail current resource checks. The stale pulse suppresses - // both physical lease fires below, so this bypass cannot mutate rename state. - val reserveCanReachD3 = renameResourcesReady || o3.io.d3PlanStale - o3.io.reserve.valid := reserveOffer && reserveCanReachD3 - o3.io.reserve.bits := io.reserve.bits - io.reserve.ready := o3.io.reserve.ready && reserveCanReachD3 && - !reserveBlockedByRecovery - // D3 intentionally consumes stale virtual plans with zero mutation. Do not - // turn that input handshake into a PTag claim: only a non-stale D3 reserve - // may acquire the matching lease. - ptag.io.reserveFire := io.reserve.fire && !o3.io.d3StaleRejected.valid - turename.io.reserveFire := io.reserve.fire && - !o3.io.d3StaleRejected.valid - dispatch.io.reserveFire := io.reserve.fire && - !o3.io.d3StaleRejected.valid - memoryOrder.io.reserveFire := io.reserve.fire && - !o3.io.d3StaleRejected.valid - - o3.io.cancel := io.cancel - o3.io.nonFlushEvidence <> io.nonFlushEvidence - o3.io.interruptPending := io.interruptPending - io.nonFlushWindows := o3.io.nonFlushWindows - val captureRecoveryOwners = - globalRecoveryState === OooGlobalRecoveryState.CaptureOwners - o3.io.recoveryRequest.valid := captureRecoveryOwners && - !lowerRecoveryAccepted - o3.io.recoveryRequest.bits := globalRecoveryRequest - turetire.io.recoveryRequest.valid := captureRecoveryOwners && - !renameRecoveryAccepted - turetire.io.recoveryRequest.bits := globalRecoveryRequest.rename - val lowerRecoveryFire = o3.io.recoveryRequest.fire - val renameRecoveryFire = turetire.io.recoveryRequest.fire - when(lowerRecoveryFire) { - lowerRecoveryAccepted := true.B - } - when(renameRecoveryFire) { - renameRecoveryAccepted := true.B - } - val recoveryOwnersCaptured = - (lowerRecoveryAccepted || lowerRecoveryFire) && - (renameRecoveryAccepted || renameRecoveryFire) - when(captureRecoveryOwners && recoveryOwnersCaptured) { - globalRecoveryState := OooGlobalRecoveryState.PrepareOwners - } - - val residencyRecoveryPlan = Wire(new OooResidencyRecoveryPlan(p)) - residencyRecoveryPlan := 0.U.asTypeOf(residencyRecoveryPlan) - residencyRecoveryPlan.valid := o3.io.recoveryPrepared.valid - residencyRecoveryPlan.oldHead := o3.io.recoveryPrepared.oldHead - residencyRecoveryPlan.oldOccupied := o3.io.recoveryPrepared.oldOccupied - residencyRecoveryPlan.newOccupied := o3.io.recoveryPrepared.newOccupied - residencyRecoveryPlan.pivotOffset := o3.io.recoveryPrepared.pivotOffset - residencyRecoveryPlan.pivot := - o3.io.recoveryPrepared.request.rename.key.member - residencyRecoveryPlan.pivotPhysicalMemberCount := - o3.io.recoveryPrepared.pivot.physicalMemberCount - residencyRecoveryPlan.survivingPivotValid := - o3.io.recoveryPrepared.survivingPivotValid - residencyRecoveryPlan.survivingPivotPhysicalMemberCount := Mux( - o3.io.recoveryPrepared.survivingPivotValid, - o3.io.recoveryPrepared.survivingPivot.physicalMemberCount, - 0.U) - - val prepareGlobalOwners = - globalRecoveryState === OooGlobalRecoveryState.PrepareOwners && - o3.io.recoveryPreparedValid && turetire.io.recoveryAuthorize.valid - dispatch.io.recoveryPrepare.valid := prepareGlobalOwners - dispatch.io.recoveryPrepare.bits := residencyRecoveryPlan - fast.io.recoveryPrepare.valid := prepareGlobalOwners - fast.io.recoveryPrepare.bits := residencyRecoveryPlan - memoryOrder.io.recoveryPrepare.valid := prepareGlobalOwners - memoryOrder.io.recoveryPrepare.bits := o3.io.recoveryPrepared - completionBuffer.io.recoveryPrepare.valid := prepareGlobalOwners - completionBuffer.io.recoveryPrepare.bits := residencyRecoveryPlan - io.iexRecoveryPrepare.valid := prepareGlobalOwners - io.iexRecoveryPrepare.bits := residencyRecoveryPlan - - val iexRecoveryPreparedExact = io.iexRecoveryPrepareReady && - io.iexRecoveryPrepared.valid && - io.iexRecoveryPrepared.stid === activeRecoveryStid - val renameRecoveryAuthority = turetire.io.recoveryAuthorize.bits - val renameRecoveryAuthorityExact = - renameRecoveryAuthority.key.member.group.valid && - renameRecoveryAuthority.key.member.bid.valid && - renameRecoveryAuthority.key.member.group.stid < p.stidCount.U && - renameRecoveryAuthority.key.member.group.stid === activeRecoveryStid - val renameRecoveryPrepared = prename.io.recoveryAuthorize.ready && - turename.io.recoveryAuthorize.ready - val allGlobalOwnersPrepared = prepareGlobalOwners && - dispatch.io.recoveryPrepareReady && fast.io.recoveryPrepareReady && - memoryOrder.io.recoveryPrepareReady && - completionBuffer.io.recoveryPrepareReady && - iexRecoveryPreparedExact && renameRecoveryAuthorityExact && - renameRecoveryPrepared - val globalRecoveryApply = allGlobalOwnersPrepared - o3.io.recoveryApply := globalRecoveryApply - dispatch.io.recoveryFire := globalRecoveryApply - fast.io.recoveryFire := globalRecoveryApply - memoryOrder.io.recoveryFire := globalRecoveryApply - completionBuffer.io.recoveryFire := globalRecoveryApply - io.iexRecoveryFire := globalRecoveryApply - io.recoveryApplied.valid := globalRecoveryApply - io.recoveryApplied.bits := globalRecoveryRequest - when(globalRecoveryApply) { - assert(o3.io.recoveryApplied.valid && dispatch.io.recoveryPrepared.valid && - fast.io.recoveryPrepared.valid && - memoryOrder.io.recoveryPrepared.valid && - completionBuffer.io.recoveryPrepared.valid && - io.iexRecoveryPrepared.valid, - "all lower and upper physical owners must share one recovery apply") - assert(turetire.io.recoveryAuthorize.fire && - prename.io.recoveryAuthorize.fire && turename.io.recoveryAuthorize.fire, - "global recovery apply must authorize P/T/U rebuild atomically") - } - when(turetire.io.recoveryAuthorize.valid) { - assert(renameRecoveryAuthorityExact, - "rename suffix authority must retain the exact active recovery key") - } - - val lowerRecoveryRejected = o3.io.robRecoveryRejected.valid || - o3.io.d3RecoveryRejected.valid || o3.io.brobRecoveryRejected.valid || - o3.io.pcRecoveryRejected.valid - val upperRecoveryRejected = turetire.io.recoveryRejected.valid || - dispatch.io.recoveryRejected.valid || fast.io.recoveryRejected.valid || - memoryOrder.io.recoveryRejected.valid || - completionBuffer.io.recoveryRejected.valid || - io.iexRecoveryRejected.valid - val anyGlobalRecoveryRejected = globalRecoveryActive && - (lowerRecoveryRejected || upperRecoveryRejected) - val abortGlobalOwners = - globalRecoveryState === OooGlobalRecoveryState.AbortOwners - o3.io.recoveryAbort := abortGlobalOwners && o3.io.recoveryBusy - turetire.io.recoveryAbort := abortGlobalOwners && turetire.io.recoveryBusy - - ptag.io.cancel := io.cancel - turename.io.cancel := io.cancel - dispatch.io.cancel := io.cancel - memoryOrder.io.cancel := io.cancel - for (stid <- 0 until p.stidCount) { - o3.io.publishEligible(stid) := !prename.io.commitBusy || - prename.io.commitStid =/= stid.U - when(turetire.io.commitBusy && turetire.io.commitStid === stid.U) { - o3.io.publishEligible(stid) := false.B - } - when(globalRecoveryActive && activeRecoveryStid === stid.U) { - o3.io.publishEligible(stid) := false.B - } - } - - val preparedStidInRange = preparedStid < p.stidCount.U - val safePreparedStid = Mux(preparedStidInRange, preparedStid, 0.U) - prename.io.prepare.valid := o3.io.preparedValid - prename.io.prepare.bits := o3.io.prepared - prename.io.ptagLease := ptag.io.provisional(safePreparedStid) - prename.io.dispatchLease := dispatch.io.provisional(safePreparedStid) - io.dispatchPrepared := dispatch.io.provisional(safePreparedStid) - o3.io.memoryOrder := memoryOrder.io.provisional(safePreparedStid) - memoryOrder.io.publishPrepare.valid := o3.io.preparedValid - memoryOrder.io.publishPrepare.bits := - o3.io.prepared.request.reservation - - val tuPublication = Wire(new OooTUPublicationRequest(p)) - tuPublication := 0.U.asTypeOf(tuPublication) - val preparedTransaction = o3.io.prepared.request.reservation.transaction - val preparedPlan = preparedTransaction.plan - val preparedDecoded = preparedTransaction.decoded - tuPublication.peId := preparedPlan.peId - tuPublication.stid := preparedPlan.stid - tuPublication.epoch := preparedPlan.epoch - tuPublication.transactionId := preparedPlan.transactionId - tuPublication.uopMask := preparedDecoded.uopMask - for (uopIndex <- 0 until p.decodedUopWidth) { - val decodedUop = preparedDecoded.uops(uopIndex) - val publicationUop = tuPublication.uops(uopIndex) - val activeUop = preparedDecoded.uopMask(uopIndex) && decodedUop.valid - val groupIndex = preparedTransaction.uopGroupIndex(uopIndex) - val groupIndexInRange = groupIndex < p.instructionDecodeWidth.U && - groupIndex < preparedPlan.groupCount - val safeGroupIndex = Mux(groupIndexInRange, groupIndex, 0.U) - val group = preparedTransaction.groups(safeGroupIndex) - val binding = o3.io.prepared.request.bindings(safeGroupIndex) - - publicationUop.valid := activeUop - publicationUop.member := 0.U.asTypeOf(publicationUop.member) - publicationUop.member.group := group.key - publicationUop.member.bid := binding.brob.bid - publicationUop.member.brobGeneration := binding.brob.generation - publicationUop.member.memberIndex := - preparedTransaction.uopMemberBase(uopIndex) - publicationUop.member.residentGeneration := binding.residentGeneration - val memberEnd = preparedTransaction.uopMemberBase(uopIndex) +& - decodedUop.plannedChildCount - publicationUop.blockLast := activeUop && group.boundaryStop && - memberEnd === group.physicalMemberCount - publicationUop.closeBeforeValid := activeUop && - uopIndex.U === group.firstLogicalUop && - o3.io.prepared.brobImplicitCloseMask(safeGroupIndex) - publicationUop.closeBefore := - o3.io.prepared.brobImplicitClosePointers(safeGroupIndex) - for (sourceIndex <- 0 until p.maxSourceOperands) { - val decodedSource = decodedUop.sources(sourceIndex) - val source = publicationUop.sources(sourceIndex) - val sourceIsT = decodedSource.operandClass === OperandClass.T - val sourceIsU = decodedSource.operandClass === OperandClass.U - source.valid := activeUop && decodedSource.valid && - (sourceIsT || sourceIsU) - source.kind := Mux(sourceIsT, DestinationKind.T, DestinationKind.U) - source.relativeIndex := decodedSource.relativeIndex - } - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val decodedDestination = decodedUop.destinations(destinationIndex) - val destination = publicationUop.destinations(destinationIndex) - val destinationIsLocal = decodedDestination.kind === DestinationKind.T || - decodedDestination.kind === DestinationKind.U - destination.valid := activeUop && decodedDestination.valid && - destinationIsLocal - destination.kind := decodedDestination.kind - destination.relativeIndex := decodedDestination.relativeIndex - } - } - turename.io.publicationPrepare.valid := o3.io.preparedValid - turename.io.publicationPrepare.bits := tuPublication - - val tuRetirePublication = Wire(new OooTURetirePublication(p)) - tuRetirePublication := 0.U.asTypeOf(tuRetirePublication) - tuRetirePublication.peId := preparedPlan.peId - tuRetirePublication.stid := preparedPlan.stid - tuRetirePublication.epoch := preparedPlan.epoch - tuRetirePublication.transactionId := preparedPlan.transactionId - tuRetirePublication.uopMask := preparedDecoded.uopMask - for (uopIndex <- 0 until p.decodedUopWidth) { - val renamed = turename.io.prepared.uops(uopIndex) - val source = tuRetirePublication.sources(uopIndex) - source.valid := renamed.valid - source.transactionId := preparedPlan.transactionId - source.epoch := preparedPlan.epoch - source.uopIndex := uopIndex.U - source.member := renamed.member - source.blockLast := renamed.blockLast - source.closeBeforeValid := renamed.closeBeforeValid - source.closeBefore := renamed.closeBefore - source.tSeqBefore := renamed.tSeqBefore - source.uSeqBefore := renamed.uSeqBefore - source.pDestinationCount := PopCount((0 until p.maxDestinationOperands) - .map { destinationIndex => - prename.io.prepared.mapQRows( - uopIndex * p.maxDestinationOperands + destinationIndex).valid - }) - source.destinations := renamed.destinations - } - turetire.io.publicationPrepare.valid := o3.io.preparedValid && - turename.io.publicationReady - turetire.io.publicationPrepare.bits := tuRetirePublication - turename.io.retireCommand <> turetire.io.retireCommand - turename.io.blockCommit <> turetire.io.blockCommit - - // The retire-source owner is the sole suffix authority. Authorization and - // every youngest-to-oldest source item fire only when both state owners can - // accept in the same cycle; neither owner may observe a partial recovery. - val recoveryAuthorizeBothReady = prename.io.recoveryAuthorize.ready && - turename.io.recoveryAuthorize.ready - turetire.io.recoveryAuthorize.ready := recoveryAuthorizeBothReady && - globalRecoveryApply - prename.io.recoveryAuthorize.valid := - turetire.io.recoveryAuthorize.valid && turename.io.recoveryAuthorize.ready && - globalRecoveryApply - prename.io.recoveryAuthorize.bits := turetire.io.recoveryAuthorize.bits - turename.io.recoveryAuthorize.valid := - turetire.io.recoveryAuthorize.valid && prename.io.recoveryAuthorize.ready && - globalRecoveryApply - turename.io.recoveryAuthorize.bits := turetire.io.recoveryAuthorize.bits - - val recoverySourceBothReady = prename.io.recoverySource.ready && - turename.io.recoverySource.ready - turetire.io.recoverySource.ready := recoverySourceBothReady - prename.io.recoverySource.valid := - turetire.io.recoverySource.valid && turename.io.recoverySource.ready - prename.io.recoverySource.bits := turetire.io.recoverySource.bits - turename.io.recoverySource.valid := - turetire.io.recoverySource.valid && prename.io.recoverySource.ready - turename.io.recoverySource.bits := turetire.io.recoverySource.bits - - prename.io.recoverySourcesDone := turetire.io.recoverySourcesDone - turename.io.recoverySourcesDone := turetire.io.recoverySourcesDone - val commonRecoveryComplete = turetire.io.recoverySourcesDone && - prename.io.recoveryComplete && turename.io.recoveryComplete - val globalRecoveryAbortComplete = abortGlobalOwners && - !o3.io.recoveryBusy && !turetire.io.recoveryBusy - turetire.io.recoveryFinish := commonRecoveryComplete - prename.io.recoveryFinish := commonRecoveryComplete - turename.io.recoveryFinish := commonRecoveryComplete - - when(globalRecoveryApply) { - globalRecoveryState := OooGlobalRecoveryState.Rebuild - }.elsewhen(anyGlobalRecoveryRejected) { - globalRecoveryState := OooGlobalRecoveryState.AbortOwners - }.elsewhen(globalRecoveryAbortComplete) { - globalRecoveryState := OooGlobalRecoveryState.Idle - lowerRecoveryAccepted := false.B - renameRecoveryAccepted := false.B - }.elsewhen(globalRecoveryState === OooGlobalRecoveryState.Rebuild && - commonRecoveryComplete) { - globalRecoveryState := OooGlobalRecoveryState.Idle - lowerRecoveryAccepted := false.B - renameRecoveryAccepted := false.B - } - - when(turetire.io.recoveryAuthorize.fire) { - assert(prename.io.recoveryAuthorize.fire && - turename.io.recoveryAuthorize.fire, - "rename recovery authorization must start P and T/U atomically") - } - when(globalRecoveryState === OooGlobalRecoveryState.Rebuild) { - assert(!prename.io.recoveryRejected.valid && - !turename.io.recoveryRejected.valid, - "prevalidated P/T/U recovery authority cannot reject after apply") - } - when(turetire.io.recoverySource.fire) { - assert(prename.io.recoverySource.fire && turename.io.recoverySource.fire, - "rename recovery source must mutate P and T/U atomically") - } - - io.preparedValid := o3.io.preparedValid && prename.io.prepareReady && - turename.io.publicationReady && turetire.io.publicationReady && - memoryOrder.io.publishReady - io.prepared := prename.io.prepared - io.tuPrepared := turename.io.prepared - // The real IEX residency owner and typed fast-resolve owner observe the - // identical retained common-S1 transaction. Neither can consume alone. - io.iexS1.valid := io.preparedValid && fast.io.s1.ready - io.iexS1.bits.o3 := o3.io.prepared - io.iexS1.bits.pRename := prename.io.prepared - io.iexS1.bits.tuRename := turename.io.prepared - io.iexS1.bits.dispatch := dispatch.io.provisional(safePreparedStid) - io.iexS1.bits.memoryOrder := - memoryOrder.io.provisional(safePreparedStid) - fast.io.s1.valid := io.preparedValid && io.iexS1.ready - fast.io.s1.bits := io.iexS1.bits - o3.io.publishPermit := io.iexS1.ready && fast.io.s1.ready && - prename.io.prepareReady && - turename.io.publicationReady && turetire.io.publicationReady && - memoryOrder.io.publishReady - prename.io.publishFire := o3.io.publishFire - turename.io.publishFire := o3.io.publishFire - turetire.io.publishFire := o3.io.publishFire - io.publishFire := o3.io.publishFire - memoryOrder.io.publishFire := o3.io.publishFire - when(io.iexS1.valid || fast.io.s1.valid || o3.io.publishFire) { - assert(io.iexS1.fire === o3.io.publishFire, - "OOO publication and the exact IEX S1 transfer must share one fire") - assert(fast.io.s1.fire === o3.io.publishFire, - "OOO publication and typed fast-resolve observation must share one fire") - } - - val exposedPrepareValid = RegInit(false.B) - val exposedPrepareStid = RegInit(0.U(p.stidWidth.W)) - val exposedPrepareCanceled = exposedPrepareValid && - io.cancel(exposedPrepareStid) - when(io.publishFire || exposedPrepareCanceled) { - exposedPrepareValid := false.B - }.elsewhen(io.preparedValid) { - exposedPrepareValid := true.B - exposedPrepareStid := preparedStid - } - - ptag.io.publish.valid := o3.io.publishFire - ptag.io.publish.bits.stid := preparedStid - ptag.io.publish.bits.transactionId := - o3.io.prepared.request.reservation.transaction.plan.transactionId - when(o3.io.publishFire) { - assert(io.preparedValid, - "O3 P rename publication requires one exact prepared transaction") - assert(!ptag.io.publishRejected.valid, - "O3 P rename publication must publish the retained exact PTag lease") - } - dispatch.io.publish.valid := o3.io.publishFire - dispatch.io.publish.bits.peId := - o3.io.prepared.request.reservation.transaction.plan.peId - dispatch.io.publish.bits.stid := preparedStid - dispatch.io.publish.bits.epoch := - o3.io.prepared.request.reservation.transaction.plan.epoch - dispatch.io.publish.bits.transactionId := - o3.io.prepared.request.reservation.transaction.plan.transactionId - dispatch.io.publish.bits.memberMask := - dispatch.io.provisional(safePreparedStid).allocationMask - for (lane <- 0 until p.dispatchWidth) { - val allocation = dispatch.io.provisional(safePreparedStid).allocations(lane) - val pUop = prename.io.prepared.uops(allocation.uopIndex) - dispatch.io.publish.bits.members(lane) := pUop.member - dispatch.io.publish.bits.members(lane).memberIndex := - pUop.member.memberIndex + allocation.childIndex - } - when(o3.io.publishFire) { - assert(!dispatch.io.publishRejected.valid, - "O3 publication must publish the retained exact dispatch lease") - } - - for (lane <- 0 until p.iexTerminalWidth) { - completionBuffer.io.enqueues(lane) <> io.completions(lane) - } - completionBuffer.io.enqueues(p.iexTerminalWidth) <> fast.io.completion - o3.io.completion <> completionBuffer.io.dequeue - io.completionBufferUsed := completionBuffer.io.used - io.completionBufferFree := completionBuffer.io.free - - io.fastBoundary <> fast.io.boundary - io.fastWriteback <> fast.io.writeback - io.fastWakeup <> fast.io.wakeup - io.fastTrace <> fast.io.trace - io.fastPendingByStid := fast.io.pendingByStid - io.fastTerminalFire := fast.io.terminalFire - io.fastS1Rejected := fast.io.s1Rejected - - val commitStid = o3.io.commit.bits.release.firstGroup.stid - val commitStidInRange = commitStid < p.stidCount.U - // A fully prepared row that was exposed in a prior cycle cannot be withdrawn. - // Let that exact row publish first. The O3 coordinator also prevents a raw - // same-STID ROB commit from exposing a new D3 grant in the first place. - // Merely provisional, unprepared rows do not block older commit. - val commitConflictsExposedPrepare = exposedPrepareValid && - commitStidInRange && exposedPrepareStid === commitStid - val commitProbeValid = o3.io.commit.valid && - !commitConflictsExposedPrepare - prename.io.commitPrepare.bits := o3.io.commit.bits - turetire.io.commitPrepare.bits := o3.io.commit.bits - storeCommit.io.commitPrepare.bits := o3.io.commit.bits - val commitOwnersStarted = RegInit(false.B) - val commitOwnersStart = commitProbeValid && !commitOwnersStarted && - prename.io.commitStartReady && turetire.io.commitStartReady && - storeCommit.io.commitStartReady - val ownerCommitPrepareValid = commitOwnersStarted || commitOwnersStart - prename.io.commitPrepare.valid := ownerCommitPrepareValid - turetire.io.commitPrepare.valid := ownerCommitPrepareValid - storeCommit.io.commitPrepare.valid := ownerCommitPrepareValid - when(commitOwnersStart) { - commitOwnersStarted := true.B - } - // A returned token is made free only on the same handshake which tells the - // external IEX scoreboard to invalidate that exact generation. - ptag.io.release.valid := prename.io.ptagReturn.valid && - io.ptagRecycle.ready - ptag.io.release.bits := prename.io.ptagReturn.bits - io.ptagRecycle.valid := prename.io.ptagReturn.valid && - ptag.io.release.ready - io.ptagRecycle.bits := prename.io.ptagReturn.bits - prename.io.ptagReturn.ready := ptag.io.release.ready && - io.ptagRecycle.ready - io.commit.valid := o3.io.commit.valid && commitOwnersStarted && - prename.io.commitReady && turetire.io.commitReady && - storeCommit.io.commitStartReady - io.commit.bits := o3.io.commit.bits - o3.io.commit.ready := io.commit.ready && commitOwnersStarted && - prename.io.commitReady && turetire.io.commitReady && - storeCommit.io.commitStartReady - val sharedCommitFire = io.commit.valid && io.commit.ready - prename.io.commitFire := sharedCommitFire - turetire.io.commitFire := sharedCommitFire - storeCommit.io.commitFire := sharedCommitFire - when(sharedCommitFire) { - commitOwnersStarted := false.B - } - - dispatch.io.releases <> io.dispatchReleases - - io.storeCommit <> storeCommit.io.storeCommit - io.storeCommitUsed := storeCommit.io.used - io.storeCommitFree := storeCommit.io.free - io.storeCommitRejected := storeCommit.io.commitRejected - - prename.io.queryStid := io.queryStid - prename.io.queryAtag := io.queryAtag - io.speculativeMapping := prename.io.speculativeMapping - io.committedMapping := prename.io.committedMapping - io.mapQUsed := prename.io.mapQUsed - io.tMapQUsed := turename.io.tMapQUsed - io.uMapQUsed := turename.io.uMapQUsed - io.tuRetireSourceUsed := turetire.io.sourceQueueUsed - io.tRelationUsed := turetire.io.tRelationUsed - io.uRelationUsed := turetire.io.uRelationUsed - - o3.io.pcReadTokens := io.pcReadTokens - io.pcReadValid := o3.io.pcReadValid - io.pcRead := o3.io.pcRead - - io.ptagFreeCount := ptag.io.freeCount - io.ptagProvisionalCount := ptag.io.provisionalCount - io.ptagPublishedCount := ptag.io.publishedCount - io.robOccupiedGroups := o3.io.robOccupiedGroups - io.d3UsedGroups := o3.io.d3UsedGroups - io.d3PublishedGroups := o3.io.d3PublishedGroups - io.d3TailSlot := o3.io.d3TailSlot - io.d3TailGeneration := o3.io.d3TailGeneration - io.d3TailEpoch := o3.io.d3TailEpoch - io.d3NextTransactionId := o3.io.d3NextTransactionId - io.pCommitBusy := prename.io.commitBusy - io.tuCommitBusy := turetire.io.commitBusy - io.pCommitRejected := prename.io.commitRejected - io.tuCommitRejected := turetire.io.commitRejected - io.tuReserveRejected := turename.io.reserveRejected - io.tuPublicationRejected := turename.io.publicationRejected - io.nonFlushEvidenceRejected := o3.io.nonFlushEvidenceRejected - io.dispatchFreeEntries := dispatch.io.freeEntries - io.dispatchProvisionalEntries := dispatch.io.provisionalEntries - io.dispatchPublishedEntries := dispatch.io.publishedEntries - io.dispatchPrepareRejected := dispatch.io.prepareRejected - io.dispatchPublishRejected := dispatch.io.publishRejected - io.dispatchReleaseRejecteds := dispatch.io.releaseRejecteds - io.recoveryBusy := globalRecoveryActive || turetire.io.recoveryBusy || - prename.io.recoveryBusy || turename.io.recoveryBusy || o3.io.recoveryBusy - io.recoveryStid := Mux(globalRecoveryActive, activeRecoveryStid, - Mux(turetire.io.recoveryBusy, turetire.io.recoveryStid, - Mux(prename.io.recoveryBusy, prename.io.recoveryStid, - turename.io.recoveryStid))) - io.recoveryComplete := commonRecoveryComplete - io.recoveryCompleted.valid := - globalRecoveryState === OooGlobalRecoveryState.Rebuild && commonRecoveryComplete - io.recoveryCompleted.bits := globalRecoveryRequest - io.recoveryAborted.valid := globalRecoveryAbortComplete - io.recoveryAborted.bits := globalRecoveryRequest - io.recoveryRejected := turetire.io.recoveryRejected - io.pRecoveryRejected := prename.io.recoveryRejected - io.tuRecoveryRejected := turename.io.recoveryRejected - io.robRecoveryRejected := o3.io.robRecoveryRejected - io.d3RecoveryRejected := o3.io.d3RecoveryRejected - io.brobRecoveryRejected := o3.io.brobRecoveryRejected - io.pcRecoveryRejected := o3.io.pcRecoveryRejected - io.dispatchRecoveryRejected := dispatch.io.recoveryRejected - io.fastRecoveryRejected := fast.io.recoveryRejected - io.completionRecoveryRejected := completionBuffer.io.recoveryRejected - io.memoryOrderPrepareRejected := memoryOrder.io.prepareRejected - io.memoryOrderRecoveryRejected := memoryOrder.io.recoveryRejected - io.memoryOrderNext := memoryOrder.io.next -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooOpcodeRecipeTable.scala b/chisel/src/main/scala/linxcore/ooo/OooOpcodeRecipeTable.scala index ef604204..7bcd3fcc 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooOpcodeRecipeTable.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooOpcodeRecipeTable.scala @@ -147,7 +147,7 @@ private object OooOpcodeRecipeRules1 { OooOpcodeRecipeRule(symbol = "OP_BSTART_STD_COND", opcode = 19, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("3001000e", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_STD_DIRECT", opcode = 20, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("2001000e", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_STD_FALL", opcode = 72, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("1001000e", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_HL_BSTART_SYS", opcode = 96, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("1081000e", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_HL_BSTART_SYS", opcode = 96, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("1081000e", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_HL_SSRGET", opcode = 559, lenBytes = 6, mask = BigInt("ffff000ff07f000f", 16), value = BigInt("3b000e", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_HL_SSRSET", opcode = 560, lenBytes = 6, mask = BigInt("ffff00007fff000f", 16), value = BigInt("103b000e", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_START_CALL_48", opcode = 653, lenBytes = 6, mask = BigInt("fffff83f0000007f", 16), value = BigInt("501600000011", 16), disposition = 1, recipeKind = 4, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 3, implicitSourceMask = 0, implicitDestination = 1, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = false, mayTrapLate = false, mayRedirect = true, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0) @@ -190,11 +190,11 @@ private object OooOpcodeRecipeRules2 { OooOpcodeRecipeRule(symbol = "OP_V_SLL", opcode = 534, lenBytes = 8, mask = BigInt("fe00707ffe00707f", 16), value = BigInt("70050000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_SRA", opcode = 536, lenBytes = 8, mask = BigInt("fe00707ffe00707f", 16), value = BigInt("60050000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_SRL", opcode = 538, lenBytes = 8, mask = BigInt("fe00707ffe00707f", 16), value = BigInt("50050000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG_DN2NZ", opcode = 43, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("1800a4a3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG_DN2ZN", opcode = 44, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("18022423", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG_ND2ZN", opcode = 45, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("180221a3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG_NORM", opcode = 46, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("fa023", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG_NZ2DN", opcode = 47, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("20fae23", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG_DN2NZ", opcode = 43, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("1800a4a3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG_DN2ZN", opcode = 44, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("18022423", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG_ND2ZN", opcode = 45, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("180221a3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG_NORM", opcode = 46, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("fa023", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG_NZ2DN", opcode = 47, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("20fae23", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BC_IALL", opcode = 588, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("10402b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_FP_ICALL", opcode = 8, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("6101", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_FP_IND", opcode = 9, lenBytes = 4, mask = BigInt("ffffffff", 16), value = BigInt("5101", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), @@ -321,11 +321,11 @@ private object OooOpcodeRecipeRules5 { OooOpcodeRecipeRule(symbol = "OP_V_REV", opcode = 529, lenBytes = 8, mask = BigInt("707ffff0707f", 16), value = BigInt("70670000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_SUBI", opcode = 541, lenBytes = 8, mask = BigInt("707ffff0707f", 16), value = BigInt("10150000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_XORI", opcode = 545, lenBytes = 8, mask = BigInt("707ffff0707f", 16), value = BigInt("40150000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_HINT_TRACE", opcode = 57, lenBytes = 4, mask = BigInt("ffff7fff", 16), value = BigInt("1033", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_MPAR", opcode = 13, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("1181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_MSEQ", opcode = 14, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("9181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_VPAR", opcode = 24, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("21181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_VSEQ", opcode = 25, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("29181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_HINT_TRACE", opcode = 57, lenBytes = 4, mask = BigInt("ffff7fff", 16), value = BigInt("1033", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_MPAR", opcode = 13, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("1181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_MSEQ", opcode = 14, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("9181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_VPAR", opcode = 24, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("21181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_VSEQ", opcode = 25, lenBytes = 4, mask = BigInt("fbffffff", 16), value = BigInt("29181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_HL_ADDI", opcode = 87, lenBytes = 6, mask = BigInt("ffff0000707f000f", 16), value = BigInt("15000e", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_HL_ADDIW", opcode = 88, lenBytes = 6, mask = BigInt("ffff0000707f000f", 16), value = BigInt("35000e", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_HL_ANDI", opcode = 89, lenBytes = 6, mask = BigInt("ffff0000707f000f", 16), value = BigInt("2015000e", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -374,30 +374,30 @@ private object OooOpcodeRecipeRules6 { OooOpcodeRecipeRule(symbol = "OP_ACRE", opcode = 547, lenBytes = 4, mask = BigInt("ff0fffff", 16), value = BigInt("100302b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_EBREAK", opcode = 548, lenBytes = 4, mask = BigInt("f0ffffff", 16), value = BigInt("10102b", 16), disposition = 1, recipeKind = 7, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 4, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_ASSERT", opcode = 587, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("102b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_ARG", opcode = 42, lenBytes = 4, mask = BigInt("fffff07f", 16), value = BigInt("3043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_ARG", opcode = 42, lenBytes = 4, mask = BigInt("fffff07f", 16), value = BigInt("3043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BC_IVA", opcode = 589, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("402b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 6, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 1, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 8, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSE", opcode = 590, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("2b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("411181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("811181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("611181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("511181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("711181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1031181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1231181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1131181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1431181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1631181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1531181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("11181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("31181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("231181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("131181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("431181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("631181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("531181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("211181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("311181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("111181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("411181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("811181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("611181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("511181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("711181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1031181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1231181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1131181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1431181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1631181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("1531181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("11181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("31181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("231181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("131181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("431181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("631181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("531181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("211181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("311181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TMA", opcode = 23, lenBytes = 4, mask = BigInt("7ffffff", 16), value = BigInt("111181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BWE", opcode = 592, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("10002b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BWI", opcode = 593, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("20002b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BWT", opcode = 594, lenBytes = 4, mask = BigInt("fff07fff", 16), value = BigInt("30002b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), @@ -443,16 +443,16 @@ private object OooOpcodeRecipeRules7 { OooOpcodeRecipeRule(symbol = "OP_V_SW", opcode = 542, lenBytes = 8, mask = BigInt("6007fff0600207f", 16), value = BigInt("20490000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_SW_BRG", opcode = 543, lenBytes = 8, mask = BigInt("6007fff0600207f", 16), value = BigInt("20490000207f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_XOR", opcode = 544, lenBytes = 8, mask = BigInt("707ffe00707f", 16), value = BigInt("40050000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_CATR", opcode = 48, lenBytes = 4, mask = BigInt("3ffffff", 16), value = BigInt("23", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("c03fffff", 16), value = BigInt("6013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_CATR", opcode = 48, lenBytes = 4, mask = BigInt("3ffffff", 16), value = BigInt("23", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("c03fffff", 16), value = BigInt("6013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_FENCE_D", opcode = 609, lenBytes = 4, mask = BigInt("f00fffff", 16), value = BigInt("202b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_FMADD", opcode = 488, lenBytes = 8, mask = BigInt("600707f0600707f", 16), value = BigInt("404b0000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_FMSUB", opcode = 491, lenBytes = 8, mask = BigInt("600707f0600707f", 16), value = BigInt("504b0000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_FNMADD", opcode = 495, lenBytes = 8, mask = BigInt("600707f0600707f", 16), value = BigInt("604b0000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_FNMSUB", opcode = 496, lenBytes = 8, mask = BigInt("600707f0600707f", 16), value = BigInt("704b0000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_MADD", opcode = 512, lenBytes = 8, mask = BigInt("600707f0600707f", 16), value = BigInt("60470000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("60fffff", 16), value = BigInt("31181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_FIXP", opcode = 3, lenBytes = 4, mask = BigInt("60fffff", 16), value = BigInt("39181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_CUBE", opcode = 1, lenBytes = 4, mask = BigInt("60fffff", 16), value = BigInt("31181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_FIXP", opcode = 3, lenBytes = 4, mask = BigInt("60fffff", 16), value = BigInt("39181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_DMA", opcode = 86, lenBytes = 4, mask = BigInt("fe007fff", 16), value = BigInt("700b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_L_BSTART_FP", opcode = 635, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("10810000000f", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_L_BSTART_FP", opcode = 635, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("20810000000f", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), @@ -462,7 +462,7 @@ private object OooOpcodeRecipeRules7 { OooOpcodeRecipeRule(symbol = "OP_L_BSTART_STD", opcode = 636, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("20010000000f", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_L_BSTART_STD", opcode = 636, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("30010000000f", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_L_BSTART_STD", opcode = 636, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("40010000000f", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_L_BSTART_SYS", opcode = 637, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("10110000000f", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_L_BSTART_SYS", opcode = 637, lenBytes = 8, mask = BigInt("7fff0000007f", 16), value = BigInt("10110000000f", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_CSEL", opcode = 472, lenBytes = 8, mask = BigInt("707f0600707f", 16), value = BigInt("770000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_V_PSEL", opcode = 518, lenBytes = 8, mask = BigInt("707f0600707f", 16), value = BigInt("10770000007f", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_FABS", opcode = 549, lenBytes = 4, mask = BigInt("f9f0707f", 16), value = BigInt("7b", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 5, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 1, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 128, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -498,8 +498,8 @@ private object OooOpcodeRecipeRules8 { OooOpcodeRecipeRule(symbol = "OP_SW_UMAX", opcode = 421, lenBytes = 4, mask = BigInt("f4007fff", 16), value = BigInt("6000300b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SW_UMIN", opcode = 422, lenBytes = 4, mask = BigInt("f4007fff", 16), value = BigInt("7000300b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SW_XOR", opcode = 423, lenBytes = 4, mask = BigInt("f4007fff", 16), value = BigInt("3000300b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("803f707f", 16), value = BigInt("5013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_TEPL", opcode = 22, lenBytes = 4, mask = BigInt("6007fff", 16), value = BigInt("2001181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("803f707f", 16), value = BigInt("5013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_TEPL", opcode = 22, lenBytes = 4, mask = BigInt("6007fff", 16), value = BigInt("2001181", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_DIV", opcode = 82, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("57", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(2, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_DIVU", opcode = 83, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("1057", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(2, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_DIVUW", opcode = 84, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("3057", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(2, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -534,9 +534,9 @@ private object OooOpcodeRecipeRules9 { OooOpcodeRecipeRule(symbol = "OP_SRL", opcode = 289, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("5005", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SRLIW", opcode = 291, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("5035", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SRLW", opcode = 292, lenBytes = 4, mask = BigInt("fe00707f", 16), value = BigInt("5025", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_HINT", opcode = 56, lenBytes = 4, mask = BigInt("87fff", 16), value = BigInt("33", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_BSTART_MPAR", opcode = 29, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("8c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_BSTART_MSEQ", opcode = 30, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("48c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_HINT", opcode = 56, lenBytes = 4, mask = BigInt("87fff", 16), value = BigInt("33", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_BSTART_MPAR", opcode = 29, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("8c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_BSTART_MSEQ", opcode = 30, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("48c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_CALL", opcode = 31, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("2000", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_COND", opcode = 32, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("1800", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_DIRECT", opcode = 33, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("1000", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), @@ -544,9 +544,9 @@ private object OooOpcodeRecipeRules9 { OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_ICALL", opcode = 35, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("3000", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_IND", opcode = 36, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("2800", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_STD_RET", opcode = 37, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("3800", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_BSTART_SYS", opcode = 38, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("840", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_BSTART_VPAR", opcode = 39, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("88c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_BSTART_VSEQ", opcode = 40, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("c8c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_BSTART_SYS", opcode = 38, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("840", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_BSTART_VPAR", opcode = 39, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("88c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_BSTART_VSEQ", opcode = 40, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("c8c0", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTOP", opcode = 41, lenBytes = 2, mask = BigInt("ffff", 16), value = BigInt("0", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 2, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SLLI", opcode = 282, lenBytes = 4, mask = BigInt("fc00707f", 16), value = BigInt("7015", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SRAI", opcode = 286, lenBytes = 4, mask = BigInt("fc00707f", 16), value = BigInt("6015", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -559,7 +559,7 @@ private object OooOpcodeRecipeRules9 { OooOpcodeRecipeRule(symbol = "OP_BSTART_FP_COND", opcode = 5, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("3101", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_FP_DIRECT", opcode = 6, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("2101", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_FP_FALL", opcode = 7, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("1101", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BSTART_SYS", opcode = 21, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("1081", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BSTART_SYS", opcode = 21, lenBytes = 4, mask = BigInt("7fff", 16), value = BigInt("1081", 16), disposition = 0, recipeKind = 11, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_CMP_AND", opcode = 304, lenBytes = 4, mask = BigInt("f800707f", 16), value = BigInt("2045", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_CMP_EQ", opcode = 306, lenBytes = 4, mask = BigInt("f800707f", 16), value = BigInt("45", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_CMP_GE", opcode = 308, lenBytes = 4, mask = BigInt("f800707f", 16), value = BigInt("5045", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -640,7 +640,7 @@ private object OooOpcodeRecipeRules11 { OooOpcodeRecipeRule(symbol = "OP_SWAPH", opcode = 410, lenBytes = 4, mask = BigInt("f000707f", 16), value = BigInt("1000600b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SWAPW", opcode = 411, lenBytes = 4, mask = BigInt("f000707f", 16), value = BigInt("2000600b", 16), disposition = 3, recipeKind = 8, uopCountMin = 0, uopCountMax = 0, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_FP", opcode = 28, lenBytes = 2, mask = BigInt("c7ff", 16), value = BigInt("80", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BIOR", opcode = 424, lenBytes = 4, mask = BigInt("600707f", 16), value = BigInt("13", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BIOR", opcode = 424, lenBytes = 4, mask = BigInt("600707f", 16), value = BigInt("13", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_MADD", opcode = 638, lenBytes = 4, mask = BigInt("600707f", 16), value = BigInt("6047", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_MADDW", opcode = 639, lenBytes = 4, mask = BigInt("600707f", 16), value = BigInt("7047", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_SETRET", opcode = 343, lenBytes = 4, mask = BigInt("fff", 16), value = BigInt("507", 16), disposition = 1, recipeKind = 5, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 2, implicitSourceMask = 0, implicitDestination = 1, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = true, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -666,17 +666,17 @@ private object OooOpcodeRecipeRules11 { OooOpcodeRecipeRule(symbol = "OP_ANDI", opcode = 66, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2015", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_ANDIW", opcode = 67, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2035", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_ANDW", opcode = 68, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2025", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_DATR", opcode = 49, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1023", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB0", opcode = 50, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("43", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB1", opcode = 51, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB2", opcode = 52, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_EQ", opcode = 53, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("27", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_GE", opcode = 54, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("3027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_GEU", opcode = 55, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("5027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("4013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_LT", opcode = 58, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_LTU", opcode = 59, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("4027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_B_NE", opcode = 60, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_DATR", opcode = 49, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1023", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB0", opcode = 50, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("43", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB1", opcode = 51, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_DIM_LB2", opcode = 52, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2043", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_EQ", opcode = 53, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("27", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_GE", opcode = 54, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("3027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_GEU", opcode = 55, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("5027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_IOT", opcode = 426, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("4013", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_LT", opcode = 58, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_LTU", opcode = 59, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("4027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_B_NE", opcode = 60, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1027", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_B_NZ", opcode = 302, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("2037", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = true, nonspeculative = false, pcReadRequired = true, pcReadClass = 2, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_B_Z", opcode = 303, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("1037", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = true, nonspeculative = false, pcReadRequired = true, pcReadClass = 2, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BCNT", opcode = 69, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("6067", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -782,7 +782,7 @@ private object OooOpcodeRecipeRules13 { OooOpcodeRecipeRule(symbol = "OP_XORW", opcode = 300, lenBytes = 4, mask = BigInt("707f", 16), value = BigInt("4025", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_B_DIM", opcode = 567, lenBytes = 2, mask = BigInt("c03f", 16), value = BigInt("c03c", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_ADDTPC", opcode = 301, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("7", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = true, pcReadClass = 2, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_BTEXT", opcode = 425, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_BTEXT", opcode = 425, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("3", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 5, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 7, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 1, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 256, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_SPLIT_COND", opcode = 16, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("21", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_BSTART_SPLIT_DIRECT", opcode = 17, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("11", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_LUI", opcode = 268, lenBytes = 4, mask = BigInt("7f", 16), value = BigInt("17", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), @@ -795,16 +795,16 @@ private object OooOpcodeRecipeRules14 { OooOpcodeRecipeRule(symbol = "OP_C_ADDI", opcode = 565, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("c", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_AND", opcode = 566, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("28", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_B_DIMI", opcode = 568, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3c", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_LDI", opcode = 570, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("1a", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_LWI", opcode = 571, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("a", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_LDI", opcode = 570, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("1a", 16), disposition = 0, recipeKind = 1, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 3, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 1, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 32, 0, 0, 0, 0, 0), memoryRequestCount = 1, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 1, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_LWI", opcode = 571, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("a", 16), disposition = 0, recipeKind = 1, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 3, dispatchWrites = 1, dispatchDemand = Seq(0, 0, 1, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 32, 0, 0, 0, 0, 0), memoryRequestCount = 1, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 1, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_MOVI", opcode = 572, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("16", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_MOVR", opcode = 573, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("6", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 1, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_OR", opcode = 574, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("38", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_SDI", opcode = 575, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3a", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_SDI", opcode = 575, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("3a", 16), disposition = 0, recipeKind = 2, uopCountMin = 2, uopCountMax = 2, complexBreak = false, lateSplitKind = 1, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 4, dispatchWrites = 2, dispatchDemand = Seq(0, 0, 1, 1, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 64, 4, 0, 0, 0, 0), memoryRequestCount = 1, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_SETC_EQ", opcode = 322, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("26", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_SETC_NE", opcode = 323, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("36", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 2, dispatchWrites = 1, dispatchDemand = Seq(0, 1, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 16, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_SUB", opcode = 582, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("18", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), - OooOpcodeRecipeRule(symbol = "OP_C_SWI", opcode = 583, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("2a", 16), disposition = 0, recipeKind = 0, uopCountMin = 1, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 1, requiresTargetValidation = false, mayTrap = false, mayTrapLate = false, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 1, dispatchWrites = 1, dispatchDemand = Seq(1, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(1, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 1, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), + OooOpcodeRecipeRule(symbol = "OP_C_SWI", opcode = 583, lenBytes = 2, mask = BigInt("3f", 16), value = BigInt("2a", 16), disposition = 0, recipeKind = 2, uopCountMin = 2, uopCountMax = 2, complexBreak = false, lateSplitKind = 1, fusionHeadClass = 0, fusionTailClass = 0, fastResolveClass = 0, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 2, requiresTargetValidation = false, mayTrap = true, mayTrapLate = true, mayRedirect = false, nonspeculative = false, pcReadRequired = false, pcReadClass = 0, dispatchClass = 4, dispatchWrites = 2, dispatchDemand = Seq(0, 0, 1, 1, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 64, 4, 0, 0, 0, 0), memoryRequestCount = 1, pSourceCount = 2, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_COND", opcode = 26, lenBytes = 2, mask = BigInt("f", 16), value = BigInt("4", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0), OooOpcodeRecipeRule(symbol = "OP_C_BSTART_DIRECT", opcode = 27, lenBytes = 2, mask = BigInt("f", 16), value = BigInt("2", 16), disposition = 1, recipeKind = 3, uopCountMin = 0, uopCountMax = 1, complexBreak = false, lateSplitKind = 0, fusionHeadClass = 1, fusionTailClass = 0, fastResolveClass = 1, implicitSourceMask = 0, implicitDestination = 0, sideEffectOwner = 3, requiresTargetValidation = true, mayTrap = true, mayTrapLate = false, mayRedirect = true, nonspeculative = true, pcReadRequired = false, pcReadClass = 0, dispatchClass = 0, dispatchWrites = 0, dispatchDemand = Seq(0, 0, 0, 0, 0, 0, 0, 0), dispatchCapabilities = Seq(0, 0, 0, 0, 0, 0, 0, 0), memoryRequestCount = 0, pSourceCount = 0, pDestinationCount = 0, tAllocationCount = 0, uAllocationCount = 0) ) diff --git a/chisel/src/main/scala/linxcore/ooo/OooPRename.scala b/chisel/src/main/scala/linxcore/ooo/OooPRename.scala deleted file mode 100644 index d2677fe9..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooPRename.scala +++ /dev/null @@ -1,960 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Mux1H, PopCount, PriorityEncoder, Valid, is, - switch} -import linxcore.common.{DestinationKind, OperandClass} - -import scala.collection.mutable.ArrayBuffer - -object OooPCommitState extends ChiselEnum { - val Idle, ReadMapQ, ReturnTags, AwaitDeallocation = Value -} - -object OooPRecoveryState extends ChiselEnum { - val Idle, WaitSources, ReadRow, ReturnTag, CopyCmap, ReplaySurvivors, - Complete = Value -} - -class OooPRenameIO(val p: OooParams = OooParams()) extends Bundle { - val prepare = Flipped(Valid(new OooO3PreparedPublication(p))) - val ptagLease = Input(new OooPTagReservation(p)) - val dispatchLease = Input(new OooDispatchReservationLease(p)) - val prepareReady = Output(Bool()) - val prepared = Output(new OooPRenamePreparedTransaction(p)) - val publishFire = Input(Bool()) - - val commitPrepare = Flipped(Valid(new OooRobCommitBatch(p))) - val commitStartReady = Output(Bool()) - val commitReady = Output(Bool()) - val commitPrepared = Output(new OooPRenameCommitPrepared(p)) - val commitFire = Input(Bool()) - val commitBusy = Output(Bool()) - val commitStid = Output(UInt(p.stidWidth.W)) - val ptagReturn = Decoupled(new OooPTagReturnBatch(p)) - - val queryStid = Input(UInt(p.stidWidth.W)) - val queryAtag = Input(UInt(p.archRegWidth.W)) - val speculativeMapping = Output(new PMapPayload(p)) - val committedMapping = Output(new PMapPayload(p)) - val mapQUsed = Output(Vec(p.stidCount, UInt(p.pMapQCountWidth.W))) - val prepareRejected = Valid(new OooPRenamePrepareReject(p)) - val commitRejected = Valid(new OooPRenameCommitReject(p)) - - val recoveryAuthorize = Flipped(Decoupled( - new OooRenameRecoveryRequest(p))) - val recoverySource = Flipped(Decoupled(new OooRenameRecoverySource(p))) - val recoverySourcesDone = Input(Bool()) - val recoveryComplete = Output(Bool()) - val recoveryFinish = Input(Bool()) - val recoveryBusy = Output(Bool()) - val recoveryStid = Output(UInt(p.stidWidth.W)) - val recoveryRejected = Valid(new OooPRenameRecoveryReject(p)) -} - -/** P-register rename prepare and publication owner. - * - * The shared PTag pool owns physical allocation. This module consumes its - * retained exact lease, resolves all P sources against the per-STID SMAP, - * forwards older destinations across the complete transaction, and prepares - * exact MapQ rows. SMAP and MapQ publish only on the O3 common publish fire. - * A retained commit walk later advances CMAP and returns old PTags at the - * independently parameterized return width before physical deallocation. - */ -class OooPRename(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooPRenameIO(p)) - - private val destinationIndexWidth = math.max(1, - chisel3.util.log2Ceil(p.maxDestinationOperands)) - private val archIndexWidth = math.max(1, chisel3.util.log2Ceil(p.pArchRegs)) - private val mapQReadWidth = math.min( - p.pTagReturnWidth, p.pMapQSubbankCount) - - private def subMapQPtr(ptr: UInt, amount: UInt): UInt = { - val difference = ptr - amount - difference(p.pMapQIndexWidth - 1, 0) - } - - private def identityMapping(stid: Int, atag: Int): PMapPayload = { - val mapping = Wire(new PMapPayload(p)) - mapping := 0.U.asTypeOf(mapping) - mapping.valid := true.B - mapping.ptag := (stid * p.pArchRegs + atag).U - mapping.ready := true.B - mapping.stid := stid.U - mapping - } - - val smap = RegInit(VecInit((0 until p.stidCount).map { stid => - VecInit((0 until p.pArchRegs).map(atag => identityMapping(stid, atag))) - })) - val cmap = RegInit(VecInit((0 until p.stidCount).map { stid => - VecInit((0 until p.pArchRegs).map(atag => identityMapping(stid, atag))) - })) - val mapQ = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.pMapQSubbankCount)( - VecInit(Seq.fill(p.pMapQRowsPerSubbank)( - 0.U.asTypeOf(new OooPMapQEntry(p))))))))) - private def mapQRow(stid: UInt, index: UInt): OooPMapQEntry = { - if (p.pMapQSubbankCount == 1) { - mapQ(stid)(0)(index) - } else { - val subbank = index(p.pMapQSubbankIndexBits - 1, 0) - if (p.pMapQRowsPerSubbank == 1) { - mapQ(stid)(subbank)(0) - } else { - val row = index(p.pMapQIndexWidth - 1, p.pMapQSubbankIndexBits) - mapQ(stid)(subbank)(row) - } - } - } - val mapQTail = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.pMapQIndexWidth.W)))) - val mapQHead = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.pMapQIndexWidth.W)))) - val mapQCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.pMapQCountWidth.W)))) - val commitState = RegInit(OooPCommitState.Idle) - val commitBatch = RegInit(0.U.asTypeOf(new OooRobCommitBatch(p))) - val commitRowsRemaining = RegInit(0.U(p.commitMapQRowCountWidth.W)) - val commitRowsTotal = RegInit(0.U(p.commitMapQRowCountWidth.W)) - val commitReadHead = RegInit(0.U(p.pMapQIndexWidth.W)) - val commitReadRowCount = RegInit(0.U(p.pTagReturnCountWidth.W)) - val commitReadRows = RegInit(VecInit(Seq.fill(p.pTagReturnWidth)( - 0.U.asTypeOf(new OooPMapQEntry(p))))) - val commitActiveStid = commitBatch.release.firstGroup.stid - io.commitBusy := commitState =/= OooPCommitState.Idle - io.commitStid := Mux(io.commitBusy, commitActiveStid, 0.U) - val recoveryState = RegInit(OooPRecoveryState.Idle) - val recoveryRequest = RegInit( - 0.U.asTypeOf(new OooRenameRecoveryRequest(p))) - val recoveryCurrentSource = RegInit( - 0.U.asTypeOf(new OooTURetireSource(p))) - val recoveryRowsRemaining = RegInit( - 0.U(p.destinationCountWidth.W)) - val recoveryReadIndex = RegInit(0.U(p.pMapQIndexWidth.W)) - val recoveryReadRow = RegInit(0.U.asTypeOf(new OooPMapQEntry(p))) - val recoveryReplayOffset = RegInit(0.U(p.pMapQCountWidth.W)) - val recoveryReplayRemaining = RegInit(0.U(p.pMapQCountWidth.W)) - val recoveryRejectValid = RegInit(false.B) - val recoveryRejectRequest = RegInit( - 0.U.asTypeOf(new OooRenameRecoveryRequest(p))) - val recoveryRejectTail = RegInit(0.U(p.pMapQIndexWidth.W)) - val recoveryRejectCount = RegInit(0.U(p.pMapQCountWidth.W)) - val recoveryActiveStid = recoveryRequest.key.member.group.stid - io.recoveryBusy := recoveryState =/= OooPRecoveryState.Idle - io.recoveryStid := Mux(io.recoveryBusy, recoveryActiveStid, 0.U) - - val reservation = io.prepare.bits.request.reservation - val transaction = reservation.transaction - val decoded = transaction.decoded - val plan = transaction.plan - val stidInRange = plan.stid < p.stidCount.U - val safeStid = Mux(stidInRange, plan.stid, 0.U) - - val destinationActive = Wire(Vec(p.pTagAllocationWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth; - destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - val uop = decoded.uops(uopIndex) - val destination = uop.destinations(destinationIndex) - destinationActive(flatIndex) := decoded.uopMask(uopIndex) && uop.valid && - destination.valid && destination.kind === DestinationKind.Gpr - } - val destinationCount = PopCount(destinationActive) - - val identityExact = plan.peId === decoded.peId && - plan.stid === decoded.stid && plan.epoch === decoded.epoch && - plan.uopMask === decoded.uopMask && - plan.demand.pDestinations === destinationCount && - plan.demand.mapQRows === destinationCount - val leaseIdentityExact = io.ptagLease.valid && - io.ptagLease.peId === plan.peId && io.ptagLease.stid === plan.stid && - io.ptagLease.epoch === plan.epoch && - io.ptagLease.transactionId === plan.transactionId && - io.ptagLease.allocationMask === destinationActive.asUInt - - val leaseRowsExact = (0 until p.pTagAllocationWidth).map { flatIndex => - val uopIndex = flatIndex / p.maxDestinationOperands - val destinationIndex = flatIndex % p.maxDestinationOperands - val destination = decoded.uops(uopIndex).destinations(destinationIndex) - val allocation = io.ptagLease.allocations(flatIndex) - val tagInRange = allocation.token.ptag < p.pPhysRegs.U - val bankExact = if (p.pTagBanks == 1) { - allocation.token.bank === 0.U - } else { - allocation.token.bank === - allocation.token.ptag(p.pTagBankWidth - 1, 0) - } - Mux(destinationActive(flatIndex), - allocation.valid && allocation.uopIndex === uopIndex.U && - allocation.destinationIndex === destinationIndex.U && - destination.atag < p.pArchRegs.U && - allocation.atag === destination.atag && allocation.token.valid && - tagInRange && bankExact, - !allocation.valid) - }.reduce(_ && _) - val leaseTagsUnique = (0 until p.pTagAllocationWidth).map { index => - val allocation = io.ptagLease.allocations(index) - (0 until index).map { older => - !allocation.valid || !io.ptagLease.allocations(older).valid || - allocation.token.ptag =/= io.ptagLease.allocations(older).token.ptag - }.reduceOption(_ && _).getOrElse(true.B) - }.reduce(_ && _) - - val dispatchDemandPresent = (0 until p.decodedUopWidth).map { uopIndex => - decoded.uopMask(uopIndex) && decoded.uops(uopIndex).valid && - decoded.uops(uopIndex).recipe.dispatchWrites.orR - }.reduce(_ || _) - val dispatchLeasePresent = !dispatchDemandPresent || io.dispatchLease.valid - val dispatchLeaseIdentityExact = !io.dispatchLease.valid || ( - io.dispatchLease.peId === plan.peId && - io.dispatchLease.stid === plan.stid && - io.dispatchLease.epoch === plan.epoch && - io.dispatchLease.transactionId === plan.transactionId) - val dispatchLeaseRowsExact = (0 until p.dispatchWidth).map { lane => - val allocation = io.dispatchLease.allocations(lane) - val active = io.dispatchLease.allocationMask(lane) - val uopIndexInRange = allocation.uopIndex < p.decodedUopWidth.U - val safeUopIndex = Mux(uopIndexInRange, allocation.uopIndex, 0.U) - !io.dispatchLease.valid || (allocation.valid === active && (!active || ( - uopIndexInRange && decoded.uopMask(safeUopIndex) && - decoded.uops(safeUopIndex).valid && allocation.reservation.valid && - allocation.reservation.uopClass.asUInt < p.iqClassCount.U && - allocation.reservation.bank < p.iqBankCount.U && - allocation.reservation.writePort < p.iqWritePortsPerBank.U && - allocation.reservation.speculativeSlot < p.iqEntriesPerBank.U))) - }.reduce(_ && _) - val dispatchedUopsBound = (0 until p.decodedUopWidth).map { uopIndex => - val uop = decoded.uops(uopIndex) - val active = decoded.uopMask(uopIndex) && uop.valid && - uop.recipe.dispatchWrites.orR - val allocationCount = PopCount(io.dispatchLease.allocations.map { - allocation => allocation.valid && allocation.uopIndex === uopIndex.U - }) - !active || (io.dispatchLease.valid && - allocationCount === uop.recipe.dispatchWrites) - }.reduce(_ && _) - - val groupShapeExact = (0 until p.instructionDecodeWidth).map { groupIndex => - val group = transaction.groups(groupIndex) - val membership = VecInit((0 until p.decodedUopWidth).map { uopIndex => - decoded.uopMask(uopIndex) && decoded.uops(uopIndex).valid && - transaction.uopGroupIndex(uopIndex) === groupIndex.U - }) - val memberCount = (0 until p.decodedUopWidth).map { uopIndex => - Mux(membership(uopIndex), decoded.uops(uopIndex).plannedChildCount, 0.U) - }.reduce(_ +& _) - val pRows = (0 until p.decodedUopWidth).flatMap { uopIndex => - (0 until p.maxDestinationOperands).map { destinationIndex => - val destination = decoded.uops(uopIndex).destinations(destinationIndex) - Mux(membership(uopIndex) && destination.valid && - destination.kind === DestinationKind.Gpr, 1.U, 0.U) - } - }.reduce(_ +& _) - group.logicalUopMask === membership.asUInt && - group.physicalMemberCount === memberCount && group.pMapQRows === pRows - }.reduce(_ && _) - - val memberBindingsExact = (0 until p.decodedUopWidth).map { uopIndex => - val active = decoded.uopMask(uopIndex) && decoded.uops(uopIndex).valid - val groupIndex = transaction.uopGroupIndex(uopIndex) - val groupIndexInRange = groupIndex < p.instructionDecodeWidth.U && - groupIndex < plan.groupCount - val safeGroupIndex = Mux(groupIndexInRange, groupIndex, 0.U) - val group = transaction.groups(safeGroupIndex) - val binding = io.prepare.bits.request.bindings(safeGroupIndex) - val childCount = decoded.uops(uopIndex).plannedChildCount - val memberEnd = transaction.uopMemberBase(uopIndex) +& childCount - val expectedMemberBase = (0 until uopIndex).map { olderIndex => - val olderActive = decoded.uopMask(olderIndex) && - decoded.uops(olderIndex).valid && - transaction.uopGroupIndex(olderIndex) === groupIndex - Mux(olderActive, decoded.uops(olderIndex).plannedChildCount, 0.U) - }.reduceOption(_ +& _).getOrElse(0.U) - !active || (groupIndexInRange && group.valid && group.key.valid && - group.key.peId === plan.peId && group.key.stid === plan.stid && - group.logicalUopMask(uopIndex) && binding.valid && - childCount.orR && childCount <= p.maxOrdinaryUopsPerGroup.U && - transaction.uopMemberBase(uopIndex) === expectedMemberBase && - memberEnd <= group.physicalMemberCount && - group.physicalMemberCount <= p.maxOrdinaryUopsPerGroup.U && - binding.brob.valid && binding.brob.bid.valid && binding.pcBase.valid) - }.reduce(_ && _) - val freeRows = p.pMapQDepthPerStid.U - mapQCount(safeStid) - val mapQAvailable = destinationCount <= freeRows - val prepareExact = stidInRange && identityExact && leaseIdentityExact && - leaseRowsExact && leaseTagsUnique && dispatchLeasePresent && - dispatchLeaseIdentityExact && dispatchLeaseRowsExact && - dispatchedUopsBound && groupShapeExact && memberBindingsExact - - val commitBlocksPrepare = io.commitBusy && plan.stid === commitActiveStid - val recoveryBlocksPrepare = io.recoveryBusy && - plan.stid === recoveryActiveStid - io.prepareReady := prepareExact && mapQAvailable && !commitBlocksPrepare && - !recoveryBlocksPrepare - io.prepared := 0.U.asTypeOf(io.prepared) - io.prepared.valid := io.prepare.valid && io.prepareReady - io.prepared.peId := plan.peId - io.prepared.stid := plan.stid - io.prepared.epoch := plan.epoch - io.prepared.transactionId := plan.transactionId - io.prepared.uopMask := decoded.uopMask - io.prepared.mapQRowMask := destinationActive.asUInt - - val historyValid = ArrayBuffer.empty[Bool] - val historyAtag = ArrayBuffer.empty[UInt] - val historyMapping = ArrayBuffer.empty[PMapPayload] - - for (uopIndex <- 0 until p.decodedUopWidth) { - val decodedUop = decoded.uops(uopIndex) - val renamedUop = io.prepared.uops(uopIndex) - val activeUop = decoded.uopMask(uopIndex) && decodedUop.valid - val groupIndex = transaction.uopGroupIndex(uopIndex) - val groupIndexInRange = groupIndex < p.instructionDecodeWidth.U && - groupIndex < plan.groupCount - val safeGroupIndex = Mux(groupIndexInRange, groupIndex, 0.U) - val group = transaction.groups(safeGroupIndex) - val binding = io.prepare.bits.request.bindings(safeGroupIndex) - - renamedUop.valid := activeUop - renamedUop.decoded := decodedUop - renamedUop.member := 0.U.asTypeOf(renamedUop.member) - renamedUop.member.group := group.key - renamedUop.member.bid := binding.brob.bid - renamedUop.member.brobGeneration := binding.brob.generation - renamedUop.member.memberIndex := transaction.uopMemberBase(uopIndex) - renamedUop.member.residentGeneration := binding.residentGeneration - - for (sourceIndex <- 0 until p.maxSourceOperands) { - val source = decodedUop.sources(sourceIndex) - val renamedSource = renamedUop.sources(sourceIndex) - val atagInRange = source.atag < p.pArchRegs.U - val safeAtag = Mux(atagInRange, source.atag, 0.U)(archIndexWidth - 1, 0) - var resolved = smap(safeStid)(safeAtag) - for (historyIndex <- historyValid.indices) { - resolved = Mux(historyValid(historyIndex) && - historyAtag(historyIndex) === source.atag, - historyMapping(historyIndex), resolved) - } - renamedSource.decoded := source - renamedSource.pMapping := 0.U.asTypeOf(renamedSource.pMapping) - when(activeUop && source.valid && source.operandClass === OperandClass.P && - atagInRange) { - renamedSource.pMapping := resolved - } - } - - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - val destination = decodedUop.destinations(destinationIndex) - val renamedDestination = renamedUop.destinations(destinationIndex) - val allocation = io.ptagLease.allocations(flatIndex) - val atagInRange = destination.atag < p.pArchRegs.U - val safeAtag = Mux(atagInRange, destination.atag, 0.U)(archIndexWidth - 1, 0) - var previous = smap(safeStid)(safeAtag) - for (historyIndex <- historyValid.indices) { - previous = Mux(historyValid(historyIndex) && - historyAtag(historyIndex) === destination.atag, - historyMapping(historyIndex), previous) - } - - val current = Wire(new PMapPayload(p)) - current := 0.U.asTypeOf(current) - current.valid := destinationActive(flatIndex) - current.ptag := allocation.token.ptag - current.ptagGeneration := allocation.token.generation - current.producerToken := plan.transactionId - val producerMatches = VecInit(io.dispatchLease.allocations.map { - dispatchAllocation => dispatchAllocation.valid && - dispatchAllocation.uopIndex === uopIndex.U && - dispatchAllocation.childIndex === 0.U - }) - val producerReservation = Mux1H(producerMatches, - io.dispatchLease.allocations.map(_.reservation)) - current.producerBindingValid := destinationActive(flatIndex) && - io.dispatchLease.valid && producerMatches.asUInt.orR - current.producerIqClass := producerReservation.uopClass - current.producerIqBank := producerReservation.bank - current.producerIqEntry := producerReservation.speculativeSlot - current.producerIqEpoch := producerReservation.reservationEpoch - current.ready := false.B - current.stid := plan.stid - current.epoch := plan.epoch - - renamedDestination.decoded := destination - renamedDestination.previousPMapping := - Mux(destinationActive(flatIndex), previous, - 0.U.asTypeOf(previous)) - renamedDestination.currentPMapping := current - - val row = io.prepared.mapQRows(flatIndex) - val olderRows = if (flatIndex == 0) 0.U else - PopCount(destinationActive.take(flatIndex)) - row.valid := destinationActive(flatIndex) - row.mapQIndex := mapQTail(safeStid) + olderRows - row.transactionId := plan.transactionId - row.uopIndex := uopIndex.U - row.destinationIndex := destinationIndex.U(destinationIndexWidth.W) - row.member := renamedUop.member - row.atag := destination.atag - row.previous := renamedDestination.previousPMapping - row.current := current - - historyValid += destinationActive(flatIndex) - historyAtag += destination.atag - historyMapping += current - } - } - - io.prepareRejected.valid := io.prepare.valid && !io.prepareReady - io.prepareRejected.bits.stid := plan.stid - io.prepareRejected.bits.transactionId := plan.transactionId - io.prepareRejected.bits.requestedRows := destinationCount - io.prepareRejected.bits.freeRows := freeRows - io.prepareRejected.bits.lease := io.ptagLease - - val publishExact = io.publishFire && io.prepare.valid && - io.prepareReady && io.prepared.valid - when(io.publishFire) { - assert(io.prepare.valid && io.prepareReady && io.prepared.valid, - "P rename publishFire requires one exact prepared transaction") - } - when(publishExact) { - for (flatIndex <- 0 until p.pTagAllocationWidth) { - val row = io.prepared.mapQRows(flatIndex) - when(row.valid) { - mapQRow(safeStid, row.mapQIndex) := row - smap(safeStid)(row.atag(archIndexWidth - 1, 0)) := row.current - } - } - mapQTail(safeStid) := mapQTail(safeStid) + destinationCount - mapQCount(safeStid) := mapQCount(safeStid) + destinationCount - } - - val incomingBatch = io.commitPrepare.bits - val incomingGroupCount = incomingBatch.release.groupCount - val incomingStid = incomingBatch.release.firstGroup.stid - val incomingStidInRange = incomingStid < p.stidCount.U - val safeIncomingStid = Mux(incomingStidInRange, incomingStid, 0.U) - val incomingGroupCountInRange = incomingGroupCount.orR && - incomingGroupCount <= p.retireGroupWidth.U - val incomingGroupsExact = (0 until p.retireGroupWidth).map { groupIndex => - val active = groupIndex.U < incomingGroupCount - val record = incomingBatch.groups(groupIndex) - val slotSum = incomingBatch.release.firstGroup.ridSlot +& groupIndex.U - val wraps = slotSum >= p.robGroupsPerStid.U - val completedMask = - ((1.U((p.maxOrdinaryUopsPerGroup + 1).W) << record.physicalMemberCount) - 1.U)( - p.maxOrdinaryUopsPerGroup - 1, 0) - record.valid === active && (!active || (record.key.valid && - record.key.peId === incomingBatch.release.firstGroup.peId && - record.key.stid === incomingStid && - record.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && - record.key.ridGeneration === - incomingBatch.release.firstGroup.ridGeneration + wraps.asUInt && - record.brob.valid && record.brob.bid.valid && record.pcBase.valid && - record.physicalMemberCount.orR && - record.completedMembers === completedMask && - record.pMapQRows <= p.maxCommitMapQRows.U)) - }.reduce(_ && _) - val incomingExpectedRows = (0 until p.retireGroupWidth).map { groupIndex => - Mux(groupIndex.U < incomingGroupCount, - incomingBatch.groups(groupIndex).pMapQRows, 0.U) - }.reduce(_ +& _) - val incomingRowsInRange = incomingExpectedRows <= p.maxCommitMapQRows.U && - incomingExpectedRows <= mapQCount(safeIncomingStid) - - val incomingRows = Wire(Vec(p.maxCommitMapQRows, new OooPMapQEntry(p))) - val incomingRowActive = Wire(Vec(p.maxCommitMapQRows, Bool())) - val incomingRowMatches = Wire(Vec(p.maxCommitMapQRows, - Vec(p.retireGroupWidth, Bool()))) - for (rowIndex <- 0 until p.maxCommitMapQRows) { - val queueIndex = mapQHead(safeIncomingStid) + rowIndex.U - incomingRows(rowIndex) := - mapQRow(safeIncomingStid, queueIndex(p.pMapQIndexWidth - 1, 0)) - incomingRowActive(rowIndex) := rowIndex.U < incomingExpectedRows - for (groupIndex <- 0 until p.retireGroupWidth) { - val group = incomingBatch.groups(groupIndex) - val row = incomingRows(rowIndex) - val uopIndexInRange = row.uopIndex < p.decodedUopWidth.U - val safeUopIndex = Mux(uopIndexInRange, row.uopIndex, 0.U) - incomingRowMatches(rowIndex)(groupIndex) := - groupIndex.U < incomingGroupCount && group.valid && row.valid && - row.member.group.asUInt === group.key.asUInt && - row.member.bid.asUInt === group.brob.bid.asUInt && - row.member.brobGeneration === group.brob.generation && - row.member.residentGeneration === group.residentGeneration && - row.transactionId === group.transactionId && - row.member.memberIndex < group.physicalMemberCount && - uopIndexInRange && group.logicalUopMask(safeUopIndex) && - row.destinationIndex < p.maxDestinationOperands.U - } - } - val incomingGroupRowsExact = (0 until p.retireGroupWidth).map { groupIndex => - val active = groupIndex.U < incomingGroupCount - val count = PopCount((0 until p.maxCommitMapQRows).map { rowIndex => - incomingRowActive(rowIndex) && incomingRowMatches(rowIndex)(groupIndex) - }) - !active || count === incomingBatch.groups(groupIndex).pMapQRows - }.reduce(_ && _) - val incomingRowsExact = (0 until p.maxCommitMapQRows).map { rowIndex => - val row = incomingRows(rowIndex) - val queueIndex = mapQHead(safeIncomingStid) + rowIndex.U - val atagInRange = row.atag < p.pArchRegs.U - val safeAtag = Mux(atagInRange, row.atag, 0.U)(archIndexWidth - 1, 0) - var expectedPrevious = cmap(safeIncomingStid)(safeAtag) - for (olderIndex <- 0 until rowIndex) { - val older = incomingRows(olderIndex) - expectedPrevious = Mux(incomingRowActive(olderIndex) && - older.atag === row.atag, older.current, expectedPrevious) - } - val matchesOne = PopCount(incomingRowMatches(rowIndex)) === 1.U - !incomingRowActive(rowIndex) || (row.valid && - row.mapQIndex === queueIndex(p.pMapQIndexWidth - 1, 0) && - atagInRange && matchesOne && - row.previous.valid && row.current.valid && - row.previous.ptag === expectedPrevious.ptag && - row.previous.ptagGeneration === expectedPrevious.ptagGeneration && - row.previous.stid === expectedPrevious.stid && - row.previous.epoch === expectedPrevious.epoch && - row.current.stid === incomingStid && - row.current.producerToken === row.transactionId && - row.previous.ptag =/= row.current.ptag && - row.current.ptag < p.pPhysRegs.U) - }.reduce(_ && _) - val incomingReturnsUnique = (0 until p.maxCommitMapQRows).map { rowIndex => - val row = incomingRows(rowIndex) - val returnsTag = incomingRowActive(rowIndex) - (0 until rowIndex).map { olderIndex => - val older = incomingRows(olderIndex) - val olderReturns = incomingRowActive(olderIndex) - !returnsTag || !olderReturns || row.previous.ptag =/= older.previous.ptag - }.reduceOption(_ && _).getOrElse(true.B) - }.reduce(_ && _) - val incomingGroupOrderExact = (1 until p.maxCommitMapQRows).map { rowIndex => - !incomingRowActive(rowIndex) || !incomingRowActive(rowIndex - 1) || - PriorityEncoder(incomingRowMatches(rowIndex - 1).asUInt) <= - PriorityEncoder(incomingRowMatches(rowIndex).asUInt) - }.reduceOption(_ && _).getOrElse(true.B) - val lateQueueIndex = mapQHead(safeIncomingStid) + incomingExpectedRows - val lateRow = mapQRow(safeIncomingStid, - lateQueueIndex(p.pMapQIndexWidth - 1, 0)) - val lateRowMatches = (0 until p.retireGroupWidth).map { groupIndex => - val group = incomingBatch.groups(groupIndex) - groupIndex.U < incomingGroupCount && group.valid && lateRow.valid && - lateRow.member.group.asUInt === group.key.asUInt && - lateRow.member.bid.asUInt === group.brob.bid.asUInt && - lateRow.member.brobGeneration === group.brob.generation && - lateRow.member.residentGeneration === group.residentGeneration && - lateRow.transactionId === group.transactionId - }.reduce(_ || _) - val noLateBatchRow = mapQCount(safeIncomingStid) === incomingExpectedRows || - !lateRowMatches - val incomingCommitExact = incomingStidInRange && - incomingGroupCountInRange && incomingBatch.release.firstGroup.valid && - incomingGroupsExact && incomingRowsInRange && incomingGroupRowsExact && - incomingRowsExact && incomingReturnsUnique && incomingGroupOrderExact && - noLateBatchRow - - val commitBatchRetained = io.commitPrepare.valid && - io.commitPrepare.bits.asUInt === commitBatch.asUInt - io.commitStartReady := commitState === OooPCommitState.Idle && - recoveryState === OooPRecoveryState.Idle && - incomingCommitExact - val commitStart = commitState === OooPCommitState.Idle && - recoveryState === OooPRecoveryState.Idle && - io.commitPrepare.valid && incomingCommitExact - when(commitStart) { - commitBatch := incomingBatch - commitRowsRemaining := incomingExpectedRows - commitRowsTotal := incomingExpectedRows - commitState := Mux(incomingExpectedRows.orR, - OooPCommitState.ReadMapQ, OooPCommitState.AwaitDeallocation) - } - when(io.commitBusy) { - assert(commitBatchRetained, - "ROB must retain the exact P commit batch through MapQ drain") - } - - // Read at most one logical row from each physical subbank, then retain the - // complete slice before any pointer or CMAP update. This is the registered - // boundary that breaks the MapQ entry-read-to-head-update loop. - val chunkRowCount = Mux(commitRowsRemaining > mapQReadWidth.U, - mapQReadWidth.U, commitRowsRemaining) - val chunkRows = Wire(Vec(p.pTagReturnWidth, new OooPMapQEntry(p))) - val chunkActive = Wire(Vec(p.pTagReturnWidth, Bool())) - val chunkMatches = Wire(Vec(p.pTagReturnWidth, - Vec(p.retireGroupWidth, Bool()))) - for (lane <- 0 until p.pTagReturnWidth) { - if (lane < mapQReadWidth) { - val queueIndex = mapQHead(commitActiveStid) + lane.U - chunkRows(lane) := - mapQRow(commitActiveStid, queueIndex(p.pMapQIndexWidth - 1, 0)) - chunkActive(lane) := lane.U < chunkRowCount - for (groupIndex <- 0 until p.retireGroupWidth) { - val group = commitBatch.groups(groupIndex) - val row = chunkRows(lane) - val uopIndexInRange = row.uopIndex < p.decodedUopWidth.U - val safeUopIndex = Mux(uopIndexInRange, row.uopIndex, 0.U) - chunkMatches(lane)(groupIndex) := - groupIndex.U < commitBatch.release.groupCount && group.valid && row.valid && - row.member.group.asUInt === group.key.asUInt && - row.member.bid.asUInt === group.brob.bid.asUInt && - row.member.brobGeneration === group.brob.generation && - row.member.residentGeneration === group.residentGeneration && - row.transactionId === group.transactionId && - row.member.memberIndex < group.physicalMemberCount && - uopIndexInRange && group.logicalUopMask(safeUopIndex) && - row.destinationIndex < p.maxDestinationOperands.U - } - } else { - chunkRows(lane) := 0.U.asTypeOf(chunkRows(lane)) - chunkActive(lane) := false.B - chunkMatches(lane) := VecInit(Seq.fill(p.retireGroupWidth)(false.B)) - } - } - val chunkExact = (0 until p.pTagReturnWidth).map { lane => - val row = chunkRows(lane) - val queueIndex = mapQHead(commitActiveStid) + lane.U - val atagInRange = row.atag < p.pArchRegs.U - val safeAtag = Mux(atagInRange, row.atag, 0.U)(archIndexWidth - 1, 0) - var expectedPrevious = cmap(commitActiveStid)(safeAtag) - for (older <- 0 until lane) { - expectedPrevious = Mux(chunkActive(older) && - chunkRows(older).atag === row.atag, - chunkRows(older).current, expectedPrevious) - } - !chunkActive(lane) || (row.valid && - row.mapQIndex === queueIndex(p.pMapQIndexWidth - 1, 0) && - atagInRange && - PopCount(chunkMatches(lane)) === 1.U && row.previous.valid && - row.current.valid && row.previous.ptag === expectedPrevious.ptag && - row.previous.ptagGeneration === expectedPrevious.ptagGeneration && - row.previous.stid === expectedPrevious.stid && - row.previous.epoch === expectedPrevious.epoch && - row.previous.ptag =/= row.current.ptag) - }.reduce(_ && _) - val chunkReturnCount = PopCount(chunkActive) - val commitReadCapture = commitState === OooPCommitState.ReadMapQ && - commitBatchRetained && chunkExact && chunkReturnCount.orR - when(commitState === OooPCommitState.ReadMapQ) { - assert(commitRowsRemaining.orR && chunkExact && chunkReturnCount.orR, - "P commit MapQ read stage must identify an exact non-empty slice") - } - when(commitReadCapture) { - commitReadHead := mapQHead(commitActiveStid) - commitReadRowCount := chunkReturnCount - commitReadRows := chunkRows - commitState := OooPCommitState.ReturnTags - } - - val commitRegisteredRowsExact = - commitReadRowCount.orR && - commitReadRowCount <= mapQReadWidth.U && - commitRowsRemaining >= commitReadRowCount && - (0 until p.pTagReturnWidth).map { lane => - val active = lane.U < commitReadRowCount - val queueIndex = commitReadHead + lane.U - val row = commitReadRows(lane) - !active || (row.valid && - row.mapQIndex === queueIndex(p.pMapQIndexWidth - 1, 0)) - }.reduce(_ && _) - val commitLiveRowsStable = mapQHead(commitActiveStid) === commitReadHead && - (0 until mapQReadWidth).map { lane => - val active = lane.U < commitReadRowCount - val queueIndex = commitReadHead + lane.U - !active || (mapQRow(commitActiveStid, - queueIndex(p.pMapQIndexWidth - 1, 0)).asUInt === - commitReadRows(lane).asUInt) - }.reduce(_ && _) - when(commitState === OooPCommitState.ReturnTags) { - assert(commitBatchRetained && commitRegisteredRowsExact && - commitLiveRowsStable, - "P commit retained MapQ slice must remain exact until PTag return") - } - - io.ptagReturn.valid := commitState === OooPCommitState.ReturnTags && - commitRegisteredRowsExact - io.ptagReturn.bits := 0.U.asTypeOf(io.ptagReturn.bits) - io.ptagReturn.bits.count := commitReadRowCount - for (returnIndex <- 0 until p.pTagReturnWidth) { - val selected = commitReadRows(returnIndex) - val token = io.ptagReturn.bits.tokens(returnIndex) - token.valid := returnIndex.U < commitReadRowCount - token.ptag := selected.previous.ptag - token.generation := selected.previous.ptagGeneration - token.bank := (if (p.pTagBanks == 1) 0.U else - selected.previous.ptag(p.pTagBankWidth - 1, 0)) - } - val chunkAdvance = commitState === OooPCommitState.ReturnTags && - io.ptagReturn.fire - when(chunkAdvance) { - for (lane <- 0 until p.pTagReturnWidth) { - when(lane.U < commitReadRowCount) { - val row = commitReadRows(lane) - val committedMapping = Wire(new PMapPayload(p)) - committedMapping := row.current - committedMapping.ready := true.B - committedMapping.producerBindingValid := false.B - committedMapping.producerIqClass := OooUopClass.Alu - committedMapping.producerIqBank := 0.U - committedMapping.producerIqEntry := 0.U - committedMapping.producerIqEpoch := 0.U - cmap(commitActiveStid)(row.atag(archIndexWidth - 1, 0)) := - committedMapping - val queueIndex = commitReadHead + lane.U - mapQRow(commitActiveStid, - queueIndex(p.pMapQIndexWidth - 1, 0)).valid := false.B - } - } - mapQHead(commitActiveStid) := commitReadHead + commitReadRowCount - mapQCount(commitActiveStid) := - mapQCount(commitActiveStid) - commitReadRowCount - commitRowsRemaining := commitRowsRemaining - commitReadRowCount - commitReadRowCount := 0.U - when(commitRowsRemaining === commitReadRowCount) { - commitState := OooPCommitState.AwaitDeallocation - }.otherwise { - commitState := OooPCommitState.ReadMapQ - } - } - - io.commitReady := commitState === OooPCommitState.AwaitDeallocation && - commitBatchRetained - io.commitPrepared := 0.U.asTypeOf(io.commitPrepared) - io.commitPrepared.valid := io.commitReady - io.commitPrepared.stid := commitActiveStid - io.commitPrepared.mapQRowCount := commitRowsTotal - io.commitRejected.valid := commitState === OooPCommitState.Idle && - io.commitPrepare.valid && !incomingCommitExact - io.commitRejected.bits.requested := io.commitPrepare.bits - io.commitRejected.bits.mapQHead := mapQHead(safeIncomingStid) - io.commitRejected.bits.mapQCount := mapQCount(safeIncomingStid) - - val commitExactFire = io.commitFire && io.commitReady - when(io.commitFire) { - assert(io.commitReady, - "P rename deallocation fire requires completed retained MapQ commit") - } - when(commitExactFire) { - commitState := OooPCommitState.Idle - commitRowsRemaining := 0.U - commitRowsTotal := 0.U - } - when(publishExact && io.commitBusy) { - assert(safeStid =/= commitActiveStid, - "same-STID P rename publication must wait for commit deallocation") - } - - when(publishExact && io.recoveryBusy) { - assert(safeStid =/= recoveryActiveStid, - "same-STID P rename publication must wait for recovery rebuild") - } - - recoveryRejectValid := false.B - val incomingRecovery = io.recoveryAuthorize.bits - val incomingRecoveryStid = incomingRecovery.key.member.group.stid - val incomingRecoveryStidInRange = incomingRecoveryStid < p.stidCount.U - val safeIncomingRecoveryStid = Mux(incomingRecoveryStidInRange, - incomingRecoveryStid, 0.U) - val incomingRecoveryShapeExact = incomingRecoveryStidInRange && - incomingRecovery.key.member.group.valid && - incomingRecovery.key.member.bid.valid - val recoveryConflictsPrepare = io.prepare.valid && io.prepareReady && - plan.stid === incomingRecoveryStid - io.recoveryAuthorize.ready := recoveryState === OooPRecoveryState.Idle && - commitState === OooPCommitState.Idle && !io.commitPrepare.valid && - !recoveryConflictsPrepare - val recoveryAuthorizeFire = io.recoveryAuthorize.fire - when(recoveryAuthorizeFire) { - when(incomingRecoveryShapeExact) { - recoveryRequest := incomingRecovery - recoveryRowsRemaining := 0.U - recoveryReplayOffset := 0.U - recoveryReplayRemaining := 0.U - recoveryState := OooPRecoveryState.WaitSources - }.otherwise { - recoveryRejectValid := true.B - recoveryRejectRequest := incomingRecovery - recoveryRejectTail := mapQTail(safeIncomingRecoveryStid) - recoveryRejectCount := mapQCount(safeIncomingRecoveryStid) - } - } - - val killed = io.recoverySource.bits.source - val killedCountInRange = killed.pDestinationCount <= - p.maxDestinationOperands.U && - killed.pDestinationCount <= mapQCount(recoveryActiveStid) - val killedRowsExact = (0 until p.maxDestinationOperands).map { offset => - val active = offset.U < killed.pDestinationCount - val rowIndex = subMapQPtr(mapQTail(recoveryActiveStid), offset.U + 1.U) - val row = mapQRow(recoveryActiveStid, rowIndex) - val atagInRange = row.atag < p.pArchRegs.U - !active || (row.valid && row.mapQIndex === rowIndex && atagInRange && - row.transactionId === killed.transactionId && - row.uopIndex === killed.uopIndex && - row.destinationIndex < p.maxDestinationOperands.U && - row.member.asUInt === killed.member.asUInt && row.current.valid && - row.current.ptag < p.pPhysRegs.U && - row.current.stid === recoveryActiveStid && - row.current.epoch === killed.epoch && - row.current.producerToken === killed.transactionId) - }.reduce(_ && _) - val nextOlderIndex = subMapQPtr(mapQTail(recoveryActiveStid), - killed.pDestinationCount + 1.U) - val nextOlderRow = mapQRow(recoveryActiveStid, nextOlderIndex) - val nextOlderMatchesKilled = mapQCount(recoveryActiveStid) > - killed.pDestinationCount && nextOlderRow.valid && - nextOlderRow.transactionId === killed.transactionId && - nextOlderRow.uopIndex === killed.uopIndex && - nextOlderRow.member.asUInt === killed.member.asUInt - val killedSourceExact = io.recoverySource.bits.request.asUInt === - recoveryRequest.asUInt && killed.valid && - killed.member.group.stid === recoveryActiveStid && - killedCountInRange && killedRowsExact && !nextOlderMatchesKilled - io.recoverySource.ready := - recoveryState === OooPRecoveryState.WaitSources && killedSourceExact - val recoverySourceFire = io.recoverySource.fire - when(recoveryState === OooPRecoveryState.WaitSources && - io.recoverySource.valid) { - assert(killedSourceExact, - "P recovery source must own the exact MapQ tail rows") - } - - val recoveryDrainIndex = subMapQPtr(mapQTail(recoveryActiveStid), 1.U) - val recoveryDrainRow = mapQRow(recoveryActiveStid, recoveryDrainIndex) - val recoveryDrainExact = recoveryDrainRow.valid && - recoveryDrainRow.mapQIndex === recoveryDrainIndex && - recoveryDrainRow.transactionId === recoveryCurrentSource.transactionId && - recoveryDrainRow.uopIndex === recoveryCurrentSource.uopIndex && - recoveryDrainRow.member.asUInt === recoveryCurrentSource.member.asUInt && - recoveryDrainRow.current.valid && - recoveryDrainRow.current.ptag < p.pPhysRegs.U && - recoveryDrainRow.current.stid === recoveryActiveStid && - recoveryDrainRow.current.epoch === recoveryCurrentSource.epoch - val recoveryReadCapture = recoveryState === OooPRecoveryState.ReadRow && - recoveryRowsRemaining.orR && recoveryDrainExact - when(recoveryState === OooPRecoveryState.ReadRow) { - assert(recoveryRowsRemaining.orR && recoveryDrainExact, - "P recovery MapQ read stage must identify the exact killed tail row") - } - when(recoveryReadCapture) { - recoveryReadIndex := recoveryDrainIndex - recoveryReadRow := recoveryDrainRow - recoveryState := OooPRecoveryState.ReturnTag - } - val recoveryRegisteredRowExact = recoveryRowsRemaining.orR && - recoveryReadRow.valid && - recoveryReadRow.mapQIndex === recoveryReadIndex && - recoveryReadRow.transactionId === recoveryCurrentSource.transactionId && - recoveryReadRow.uopIndex === recoveryCurrentSource.uopIndex && - recoveryReadRow.member.asUInt === recoveryCurrentSource.member.asUInt && - recoveryReadRow.current.valid && - recoveryReadRow.current.ptag < p.pPhysRegs.U && - recoveryReadRow.current.stid === recoveryActiveStid && - recoveryReadRow.current.epoch === recoveryCurrentSource.epoch - val recoveryLiveRowStable = - subMapQPtr(mapQTail(recoveryActiveStid), 1.U) === recoveryReadIndex && - mapQRow(recoveryActiveStid, recoveryReadIndex).asUInt === - recoveryReadRow.asUInt - when(recoveryState === OooPRecoveryState.ReturnTag) { - assert(recoveryRegisteredRowExact && recoveryLiveRowStable, - "P recovery retained MapQ row must remain exact until PTag return") - io.ptagReturn.valid := recoveryRegisteredRowExact - io.ptagReturn.bits := 0.U.asTypeOf(io.ptagReturn.bits) - io.ptagReturn.bits.count := 1.U - io.ptagReturn.bits.tokens(0).valid := true.B - io.ptagReturn.bits.tokens(0).ptag := recoveryReadRow.current.ptag - io.ptagReturn.bits.tokens(0).generation := - recoveryReadRow.current.ptagGeneration - io.ptagReturn.bits.tokens(0).bank := (if (p.pTagBanks == 1) 0.U else - recoveryReadRow.current.ptag(p.pTagBankWidth - 1, 0)) - } - val recoveryDrainFire = recoveryState === OooPRecoveryState.ReturnTag && - io.ptagReturn.fire - - val replayIndexSum = mapQHead(recoveryActiveStid) +& recoveryReplayOffset - val replayIndex = replayIndexSum(p.pMapQIndexWidth - 1, 0) - val replayRow = mapQRow(recoveryActiveStid, replayIndex) - val replayRowExact = replayRow.valid && replayRow.mapQIndex === replayIndex && - replayRow.atag < p.pArchRegs.U && replayRow.current.valid && - replayRow.current.stid === recoveryActiveStid && - replayRow.current.ptag < p.pPhysRegs.U - - switch(recoveryState) { - is(OooPRecoveryState.WaitSources) { - when(recoverySourceFire) { - recoveryCurrentSource := killed - recoveryRowsRemaining := killed.pDestinationCount - when(killed.pDestinationCount.orR) { - recoveryState := OooPRecoveryState.ReadRow - } - }.elsewhen(io.recoverySourcesDone) { - recoveryState := OooPRecoveryState.CopyCmap - } - } - is(OooPRecoveryState.ReturnTag) { - when(recoveryDrainFire) { - mapQRow(recoveryActiveStid, recoveryReadIndex) := - 0.U.asTypeOf(new OooPMapQEntry(p)) - mapQTail(recoveryActiveStid) := recoveryReadIndex - mapQCount(recoveryActiveStid) := - mapQCount(recoveryActiveStid) - 1.U - recoveryRowsRemaining := recoveryRowsRemaining - 1.U - when(recoveryRowsRemaining === 1.U) { - recoveryState := OooPRecoveryState.WaitSources - }.otherwise { - recoveryState := OooPRecoveryState.ReadRow - } - } - } - is(OooPRecoveryState.CopyCmap) { - for (atag <- 0 until p.pArchRegs) { - smap(recoveryActiveStid)(atag) := cmap(recoveryActiveStid)(atag) - } - recoveryReplayOffset := 0.U - recoveryReplayRemaining := mapQCount(recoveryActiveStid) - recoveryState := Mux(mapQCount(recoveryActiveStid).orR, - OooPRecoveryState.ReplaySurvivors, OooPRecoveryState.Complete) - } - is(OooPRecoveryState.ReplaySurvivors) { - assert(recoveryReplayRemaining.orR && replayRowExact, - "P recovery replay must walk the exact surviving MapQ prefix") - smap(recoveryActiveStid)(replayRow.atag(archIndexWidth - 1, 0)) := - replayRow.current - recoveryReplayOffset := recoveryReplayOffset + 1.U - recoveryReplayRemaining := recoveryReplayRemaining - 1.U - when(recoveryReplayRemaining === 1.U) { - recoveryState := OooPRecoveryState.Complete - } - } - is(OooPRecoveryState.Complete) { - when(io.recoveryFinish) { - recoveryState := OooPRecoveryState.Idle - } - } - } - - io.recoveryComplete := recoveryState === OooPRecoveryState.Complete - io.recoveryRejected.valid := recoveryRejectValid - io.recoveryRejected.bits.requested := recoveryRejectRequest - io.recoveryRejected.bits.mapQTail := recoveryRejectTail - io.recoveryRejected.bits.mapQCount := recoveryRejectCount - when(io.recoveryFinish) { - assert(io.recoveryComplete, - "P recovery may finish only after CMAP copy and survivor replay") - } - - val queryStidInRange = io.queryStid < p.stidCount.U - val queryAtagInRange = io.queryAtag < p.pArchRegs.U - val safeQueryStid = Mux(queryStidInRange, io.queryStid, 0.U) - val safeQueryAtag = Mux(queryAtagInRange, io.queryAtag, 0.U)(archIndexWidth - 1, 0) - io.speculativeMapping := Mux(queryStidInRange && queryAtagInRange, - smap(safeQueryStid)(safeQueryAtag), - 0.U.asTypeOf(new PMapPayload(p))) - io.committedMapping := Mux(queryStidInRange && queryAtagInRange, - cmap(safeQueryStid)(safeQueryAtag), - 0.U.asTypeOf(new PMapPayload(p))) - io.mapQUsed := mapQCount -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooParams.scala b/chisel/src/main/scala/linxcore/ooo/OooParams.scala index 632dbe12..51db578a 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooParams.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooParams.scala @@ -10,6 +10,7 @@ import chisel3.util.log2Ceil */ final case class OooParams( stidCount: Int = 4, + stidIdentityEntries: Int = 4, instructionDecodeWidth: Int = 4, decodedUopWidth: Int = 8, renameWidth: Int = 8, @@ -18,16 +19,21 @@ final case class OooParams( robCompletionBufferEntries: Int = 8, storeCommitBufferEntries: Int = 64, maxInstPerRobGroup: Int = 4, + robIdentityMembersPerGroup: Int = 4, maxOrdinaryUopsPerGroup: Int = 12, maxRecipeUops: Int = 32, + uopIdentityEntriesPerInstruction: Int = 32, robGroupsPerStid: Int = 64, + robIdentityGroupsPerStid: Int = 64, robBankCount: Int = 8, robSubbankCount: Int = 2, robRecoveryScanGroupsPerCycle: Int = 8, robNonFlushScanGroupsPerCycle: Int = 8, brobEntriesPerStid: Int = 256, + brobIdentityEntriesPerStid: Int = 256, pArchRegs: Int = 24, pPhysRegs: Int = 128, + pTagIdentityEntries: Int = 128, pTagBanks: Int = 2, pTagStagingDepthPerBank: Int = 8, pTagReturnWidth: Int = 8, @@ -35,7 +41,9 @@ final case class OooParams( pMapQDepthPerStid: Int = 256, pMapQSubbankCount: Int = 2, tPhysRegs: Int = 32, + tTagIdentityEntries: Int = 32, uPhysRegs: Int = 32, + uTagIdentityEntries: Int = 32, tuMapQDepthPerStid: Int = 32, tuRetireSourceDepthPerStid: Int = 512, tuRelationDepthPerStid: Int = 8, @@ -66,7 +74,6 @@ final case class OooParams( iexBypassPorts: Int = 12, iexLoadCancelPorts: Int = 4, iexTerminalWidth: Int = 2, - iexLoadTrackEntries: Int = 16, maxArchitecturalParentRefs: Int = 3, maxSourceOperands: Int = 4, maxDestinationOperands: Int = 2, @@ -82,6 +89,8 @@ final case class OooParams( localTagWidth: Int = 8, lsidWidth: Int = 32, transactionIdWidth: Int = 64, + memoryTransactionIdWidth: Int = 64, + memoryTransactionGenerationWidth: Int = 16, instructionIdWidth: Int = 64, templateGroupIdWidth: Int = 64, predictionTagWidth: Int = 64, @@ -100,8 +109,10 @@ final case class OooParams( (stidCount * pArchRegs until pPhysRegs).count(_ % pTagBanks == bank) require(isPowerOfTwo(stidCount), "stidCount must be a positive power of two") - require(Set(2, 4, 6).contains(instructionDecodeWidth), - "instructionDecodeWidth must be one of 2, 4, or 6") + require(isPowerOfTwo(stidIdentityEntries) && stidIdentityEntries >= stidCount, + "STID identity entries must be a power of two covering physical STIDs") + require(Set(2, 4, 6, 8).contains(instructionDecodeWidth), + "instructionDecodeWidth must be one of 2, 4, 6, or 8") require(decodedUopWidth >= instructionDecodeWidth, "decodedUopWidth must contain the instruction decode prefix") require(renameWidth > 0 && dispatchWidth > 0 && retireGroupWidth > 0, @@ -111,12 +122,22 @@ final case class OooParams( "store commit buffer must be a power of two covering one worst-case ROB commit batch") require(maxInstPerRobGroup > 0, "ROB group instruction cap must be positive") + require(isPowerOfTwo(robIdentityMembersPerGroup) && + robIdentityMembersPerGroup >= maxInstPerRobGroup, + "ROB identity members must be a power of two covering physical group instruction capacity") require(maxOrdinaryUopsPerGroup >= maxInstPerRobGroup, "ROB group member cap must cover its architectural parents") require(maxRecipeUops >= maxOrdinaryUopsPerGroup, "recipe count must cover ordinary and multi-group CTU expansion") + require(isPowerOfTwo(uopIdentityEntriesPerInstruction) && + uopIdentityEntriesPerInstruction >= maxRecipeUops && + uopIdentityEntriesPerInstruction >= robIdentityMembersPerGroup, + "uop identity entries must be a power of two covering recipe uops and ROB identity members") require(isPowerOfTwo(robGroupsPerStid), "ROB groups per STID must be a power of two") + require(isPowerOfTwo(robIdentityGroupsPerStid) && + robIdentityGroupsPerStid >= robGroupsPerStid, + "ROB identity groups must be a power of two covering physical ROB groups") require(isPowerOfTwo(robBankCount), "ROB bank count must be a positive power of two") require(isPowerOfTwo(robSubbankCount), @@ -132,9 +153,14 @@ final case class OooParams( "ROB banks must cover one publication and retirement prefix without a bank collision") require(isPowerOfTwo(brobEntriesPerStid), "BROB entries per STID must be a power of two") + require(isPowerOfTwo(brobIdentityEntriesPerStid) && + brobIdentityEntriesPerStid >= brobEntriesPerStid, + "BROB identity entries must be a power of two covering physical entries") require(pArchRegs == 24, "Linx scalar P namespace contains 24 registers") require(isPowerOfTwo(pPhysRegs) && pPhysRegs > stidCount * pArchRegs, "PTag namespace must cover committed mappings for every STID plus speculation") + require(isPowerOfTwo(pTagIdentityEntries) && pTagIdentityEntries >= pPhysRegs, + "PTag identity entries must cover the physical namespace") require(pTagMinimumSpeculativePerStid > 0, "every STID must receive a nonzero speculative PTag guarantee") require(pPhysRegs >= stidCount * (pArchRegs + pTagMinimumSpeculativePerStid), @@ -162,6 +188,10 @@ final case class OooParams( require(isPowerOfTwo(tPhysRegs) && isPowerOfTwo(uPhysRegs) && tPhysRegs >= 2 && uPhysRegs >= 2, "T and U physical namespaces must be powers of two with at least two entries") + require(isPowerOfTwo(tTagIdentityEntries) && + isPowerOfTwo(uTagIdentityEntries) && + tTagIdentityEntries >= tPhysRegs && uTagIdentityEntries >= uPhysRegs, + "T and U tag identity entries must cover their physical namespaces") require(isPowerOfTwo(tuMapQDepthPerStid), "T/U MapQ depth per STID must be a power of two") require(tuMapQDepthPerStid >= decodedUopWidth * maxDestinationOperands, @@ -175,8 +205,9 @@ final case class OooParams( require(tuRelationReleaseThreshold >= 0 && tuRelationReleaseThreshold < tuRelationDepthPerStid, "T/U relation pressure threshold must fit the relation CMAP") - require(localTagWidth >= log2Ceil(math.max(tPhysRegs, uPhysRegs)), - "localTagWidth must address both T and U physical namespaces") + require(localTagWidth >= log2Ceil(math.max( + tTagIdentityEntries, uTagIdentityEntries)), + "localTagWidth must preserve both T and U tag identity namespaces") require(localSeqGenerationWidth > 0, "local sequence generation width must be positive") require(isPowerOfTwo(pcBufferEntries), "PC buffer entries must be a power of two") @@ -236,10 +267,11 @@ final case class OooParams( require(isPowerOfTwo(robCompletionBufferEntries) && robCompletionBufferEntries >= robCompletionInputWidth, "ROB completion buffer must be a power of two covering every same-cycle producer") - require(isPowerOfTwo(iexLoadTrackEntries), - "load tracking entries must be a positive power of two") require(loadGenerationWidth > 0, "speculative load attempts need a positive generation width") + require(memoryTransactionIdWidth > 0 && + memoryTransactionGenerationWidth > 0, + "memory transactions need positive value and generation widths") require(executeSlotGenerationWidth > 0, "retained execute slots need a positive generation width") require(maxArchitecturalParentRefs >= 3, @@ -259,11 +291,11 @@ final case class OooParams( def countWidth(maximum: Int): Int = math.max(1, log2Ceil(maximum + 1)) def robCompletionInputWidth: Int = iexTerminalWidth + 1 def robCompletionBufferCountWidth: Int = countWidth(robCompletionBufferEntries) - def maxCommitStoreTokens: Int = retireGroupWidth * decodedUopWidth * + def maxCommitStoreTokens: Int = retireGroupWidth * maxMemoryRequestsPerInstruction def storeCommitBufferCountWidth: Int = countWidth(storeCommitBufferEntries) - def stidWidth: Int = math.max(1, log2Ceil(stidCount)) - def ridSlotWidth: Int = log2Ceil(robGroupsPerStid) + def stidWidth: Int = math.max(1, log2Ceil(stidIdentityEntries)) + def ridSlotWidth: Int = log2Ceil(robIdentityGroupsPerStid) def robBankCountEffective: Int = math.min(robBankCount, robGroupsPerStid) def robSubbankCountEffective: Int = math.min( robSubbankCount, @@ -285,10 +317,12 @@ final case class OooParams( math.min(robNonFlushScanGroupsPerCycle, robBankCountEffective) def robNonFlushScanCycles: Int = robGroupsPerStid / robNonFlushScanGroupsPerCycleEffective - def nativeBidWidth: Int = log2Ceil(brobEntriesPerStid) + def nativeBidWidth: Int = log2Ceil(brobIdentityEntriesPerStid) def brobCountWidth: Int = countWidth(brobEntriesPerStid) def brobLiveGroupCountWidth: Int = countWidth(robGroupsPerStid) - def pTagWidth: Int = log2Ceil(pPhysRegs) + def pTagWidth: Int = log2Ceil(pTagIdentityEntries) + def tTagWidth: Int = log2Ceil(tTagIdentityEntries) + def uTagWidth: Int = log2Ceil(uTagIdentityEntries) def pTagBankWidth: Int = math.max(1, log2Ceil(pTagBanks)) def pTagAllocationWidth: Int = decodedUopWidth * maxDestinationOperands def pTagReturnCountWidth: Int = countWidth(pTagReturnWidth) @@ -346,13 +380,16 @@ final case class OooParams( def robReleaseCountWidth: Int = countWidth(retireGroupWidth) def robGroupIndexWidth: Int = math.max(1, log2Ceil(instructionDecodeWidth)) def robGroupParentDemandWidth: Int = - countWidth(maxInstPerRobGroup + maxArchitecturalParentRefs) - private def maxLogicalUopsPerParent: Int = - math.max(maxOrdinaryUopsPerGroup, maxRecipeUops) - def robMemberIndexWidth: Int = math.max(1, log2Ceil(maxLogicalUopsPerParent)) - def robMemberCountWidth: Int = countWidth(maxLogicalUopsPerParent) + countWidth(robIdentityMembersPerGroup + maxArchitecturalParentRefs) + def robMemberIndexWidth: Int = math.max(1, + log2Ceil(robIdentityMembersPerGroup)) + def robPhysicalMemberIndexWidth: Int = math.max(1, + log2Ceil(maxOrdinaryUopsPerGroup)) + def robMemberCountWidth: Int = countWidth(maxOrdinaryUopsPerGroup) def decodedUopIndexWidth: Int = math.max(1, log2Ceil(decodedUopWidth)) - def recipeUopCountWidth: Int = countWidth(maxRecipeUops) + def recipeUopIndexWidth: Int = math.max(1, + log2Ceil(uopIdentityEntriesPerInstruction)) + def recipeUopCountWidth: Int = countWidth(uopIdentityEntriesPerInstruction) def architecturalParentCountWidth: Int = countWidth(maxArchitecturalParentRefs) def sourceCountWidth: Int = countWidth(maxSourceOperands) def destinationCountWidth: Int = countWidth(maxDestinationOperands) @@ -362,4 +399,122 @@ final case class OooParams( countWidth(decodedUopWidth * maxDispatchWritesPerInstruction) def memoryDemandWidth: Int = countWidth(decodedUopWidth * maxMemoryRequestsPerInstruction) + + /** Temporary value-only bridge into the centralized OOO parameter record. */ + def toMainline: linxcore.params.OOOParams = + linxcore.params.OOOParams( + stidCount = stidCount, + stidIdentityEntries = stidIdentityEntries, + decodeWidth = instructionDecodeWidth, + renameWidth = renameWidth, + dispatchWidth = dispatchWidth, + d3PrefixWidth = math.min(renameWidth, dispatchWidth), + retireWidth = retireGroupWidth, + robGroupsPerStid = robGroupsPerStid, + robIdentityGroupsPerStid = robIdentityGroupsPerStid, + maxInstructionsPerRobGroup = maxInstPerRobGroup, + robIdentityMembersPerGroup = robIdentityMembersPerGroup, + maxUopsPerInstruction = maxRecipeUops, + uopIdentityEntriesPerInstruction = uopIdentityEntriesPerInstruction, + robBankCount = robBankCount, + brobEntriesPerStid = brobEntriesPerStid, + brobIdentityEntriesPerStid = brobIdentityEntriesPerStid, + pcBufferEntries = pcBufferEntries, + pcBankCount = pcBankCount, + pcRecoveryScanGroupsPerCycle = pcRecoveryScanGroupsPerCycle, + pcOffsetWidth = pcOffsetWidth, + pcWritePorts = pcWritePorts, + pcReadPorts = pcReadPorts, + pcReadReplicaCount = pcReadReplicaCount, + pcAllocationEpochWidth = reservationEpochWidth, + gprArchRegs = pArchRegs, + gprPhysRegs = pPhysRegs, + gprTagIdentityEntries = pTagIdentityEntries, + gprTagGenerationWidth = pTagGenerationWidth, + gprMapQDepthPerStid = pMapQDepthPerStid, + tPhysRegs = tPhysRegs, + tTagIdentityEntries = tTagIdentityEntries, + uPhysRegs = uPhysRegs, + uTagIdentityEntries = uTagIdentityEntries, + localSeqGenerationWidth = localSeqGenerationWidth, + tuMapQDepthPerStid = tuMapQDepthPerStid) +} + +object OooParams { + /** Temporary constructor bridge for OOO modules awaiting migration. */ + def fromMainline(p: linxcore.params.OOOParams): OooParams = { + val decodedWidth = math.max(p.decodeWidth, p.renameWidth) + OooParams( + stidCount = p.stidCount, + stidIdentityEntries = p.stidIdentityEntries, + instructionDecodeWidth = p.decodeWidth, + decodedUopWidth = decodedWidth, + renameWidth = p.renameWidth, + dispatchWidth = p.dispatchWidth, + retireGroupWidth = p.retireWidth, + storeCommitBufferEntries = p.storeCommitBufferEntries, + maxInstPerRobGroup = p.maxInstructionsPerRobGroup, + robIdentityMembersPerGroup = p.robIdentityMembersPerGroup, + maxRecipeUops = p.maxUopsPerInstruction, + uopIdentityEntriesPerInstruction = p.uopIdentityEntriesPerInstruction, + robGroupsPerStid = p.robGroupsPerStid, + robIdentityGroupsPerStid = p.robIdentityGroupsPerStid, + robBankCount = p.robBankCount, + robRecoveryScanGroupsPerCycle = p.robBankCount, + robNonFlushScanGroupsPerCycle = p.robBankCount, + brobEntriesPerStid = p.brobEntriesPerStid, + brobIdentityEntriesPerStid = p.brobIdentityEntriesPerStid, + pcBufferEntries = p.pcBufferEntries, + pcBankCount = p.pcBankCount, + pcRecoveryScanGroupsPerCycle = p.pcRecoveryScanGroupsPerCycle, + pcOffsetWidth = p.pcOffsetWidth, + pcWritePorts = p.pcWritePorts, + pcReadPorts = p.pcReadPorts, + pcReadReplicaCount = p.pcReadReplicaCount, + reservationEpochWidth = p.pcAllocationEpochWidth, + pArchRegs = p.gprArchRegs, + pPhysRegs = p.gprPhysRegs, + pTagIdentityEntries = p.gprTagIdentityEntries, + pTagGenerationWidth = p.gprTagGenerationWidth, + pMapQDepthPerStid = p.gprMapQDepthPerStid, + tPhysRegs = p.tPhysRegs, + tTagIdentityEntries = p.tTagIdentityEntries, + uPhysRegs = p.uPhysRegs, + uTagIdentityEntries = p.uTagIdentityEntries, + localSeqGenerationWidth = p.localSeqGenerationWidth, + tuMapQDepthPerStid = p.tuMapQDepthPerStid) + } + + /** Width-exact bridge for public modules that still reuse validated OOO + * mechanisms. Identity and generation widths come from CoreParams rather + * than the historical eight-bit defaults. + */ + def fromCoreParams(p: linxcore.params.CoreParams): OooParams = + fromMainline(p.ooo).copy( + peIdWidth = p.peIdWidth, + pcWidth = p.pcWidth, + instructionWidth = p.instructionWidth, + opcodeWidth = p.opcodeWidth, + archRegWidth = p.archRegWidth, + trapCauseWidth = p.trapCauseWidth, + lsidWidth = p.lsidWidth, + transactionIdWidth = p.transactionIdWidth, + memoryTransactionIdWidth = p.memoryTransactionIdWidth, + memoryTransactionGenerationWidth = + p.memoryTransactionGenerationWidth, + instructionIdWidth = p.instructionIdWidth, + predictionTagWidth = p.transactionIdWidth, + epochWidth = p.epochWidth, + ridGenerationWidth = p.ridGenerationWidth, + brobGenerationWidth = p.brobGenerationWidth, + residentGenerationWidth = p.residentGenerationWidth, + pcBufferEntries = p.ooo.pcBufferEntries, + pcBankCount = p.ooo.pcBankCount, + pcRecoveryScanGroupsPerCycle = + p.ooo.pcRecoveryScanGroupsPerCycle, + pcOffsetWidth = p.ooo.pcOffsetWidth, + pcWritePorts = p.ooo.pcWritePorts, + pcReadPorts = p.ooo.pcReadPorts, + pcReadReplicaCount = p.ooo.pcReadReplicaCount, + reservationEpochWidth = p.ooo.pcAllocationEpochWidth) } diff --git a/chisel/src/main/scala/linxcore/ooo/OooPcBuffer.scala b/chisel/src/main/scala/linxcore/ooo/OooPcBuffer.scala index 623c17a3..c72f4021 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooPcBuffer.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooPcBuffer.scala @@ -1,985 +1,1020 @@ package linxcore.ooo import chisel3._ -import chisel3.util.{Decoupled, PopCount, PriorityEncoder, Valid} +import chisel3.util.{Cat, PopCount, PriorityEncoder, Valid, log2Ceil} +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ + +private[ooo] class PcBufferRow(val p: CoreParams) extends Bundle { + private val liveWidth = PrefixPacketContract.countWidth( + p.ooo.robGroupsPerStid) + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val pcBufferIndex = UInt(InterfaceWidth.index(p.ooo.pcBufferEntries).W) + val allocationEpoch = UInt(p.ooo.pcAllocationEpochWidth.W) + val pcBase = UInt(p.pcWidth.W) + val firstRob = new RobIdentity(p) + val lastRob = new RobIdentity(p) + val nextCommitValid = Bool() + val nextCommitPeId = UInt(p.peIdWidth.W) + val nextCommitStid = UInt(p.ooo.stidWidth.W) + val nextCommitRidSlot = UInt(p.ooo.ridSlotWidth.W) + val nextCommitRidGeneration = UInt(p.ridGenerationWidth.W) + val liveRobGroups = UInt(liveWidth.W) + val closed = Bool() + val closeOwnerValid = Bool() + val closeOwner = new RobIdentity(p) + val closeCommitted = Bool() +} + +private[ooo] class PcBufferReadRow(val p: CoreParams) extends Bundle { + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val pcBufferIndex = UInt(InterfaceWidth.index(p.ooo.pcBufferEntries).W) + val allocationEpoch = UInt(p.ooo.pcAllocationEpochWidth.W) + val pcBase = UInt(p.pcWidth.W) +} -object OooPcRecoveryScanState extends ChiselEnum { +private[ooo] object PcBufferRecoveryState extends ChiselEnum { val Idle, Scan, Prepared, Rejected = Value } -class OooPcBufferIO(val p: OooParams = OooParams()) extends Bundle { - val prepare = Flipped(Valid(new OooD3GroupedReservation(p))) - val prepared = Output(new OooPcPreparedBindings(p)) +class OooPcBufferIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Valid(new D3RenameGroup(p))) + val prefixOffer = Output(Valid(new D3PrefixLimit(p))) + val selectedLimit = Input(Valid(new D3PrefixLimit(p))) + val prepared = Output(new PcBufferD3Prepared(p)) val prepareReady = Output(Bool()) + val publicationIdentity = Input(Valid(new OOORobPrepared(p))) val publishFire = Input(Bool()) - val commit = Flipped(Decoupled(new OooRobCommitBatch(p))) - val recoveryPrepare = Flipped(Valid(new OooRobRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooPcRecoveryPrepared(p)) - val recoveryFire = Input(Bool()) - val readTokens = Input(Vec(p.pcReadPorts, new PcBufferToken(p))) - val readValid = Output(Vec(p.pcReadPorts, Bool())) - val readPc = Output(Vec(p.pcReadPorts, UInt(p.pcWidth.W))) - - val prepareRejected = Valid(new OooPcPrepareReject(p)) - val commitRejected = Valid(new OooPcCommitReject(p)) - val recoveryRejected = Valid(new OooPcRecoveryReject(p)) - val usedBases = Output(Vec(p.stidCount, UInt(p.pcPartitionCountWidth.W))) - val head = Output(Vec(p.stidCount, new PcBufferToken(p))) - val currentValid = Output(Vec(p.stidCount, Bool())) - val current = Output(Vec(p.stidCount, new PcBufferToken(p))) + + val commitPreview = Flipped(Valid(new CommitTxn(p))) + val commitReady = Output(Bool()) + val commitApply = Input(Bool()) + + val recovery = Flipped(new RecoveryTargetIO(p)) + + val readAddress = Input(Vec(p.ooo.pcReadPorts, + new PcBufferReadAddress(p))) + val readPcBase = Output(Vec(p.ooo.pcReadPorts, Valid(UInt(p.pcWidth.W)))) } -/** Fixed-partition, bank-addressed PC-base buffer. +/** Fixed-partition, bank-addressed PC-base owner. * - * The default 64 rows are four independent 16-row rings. D3 observes a pure - * prepare result; bases become visible only on the shared S1 publication. - * Commit consumes exact ROB-group/token prefixes and frees only an ordered - * partition-head prefix whose close owners have committed. Low local-index - * bits select one physical address bank and higher bits select its row. A - * canonical metadata table owns allocation/commit/recovery while minimal - * base-payload replicas provide fixed readyless consumer read ports. The - * token's global index and allocation epoch remain the public identity. + * D3 preparation is side-effect free. One common S1 publication installs at + * most three bases, while six readyless reads are served by three exact + * replicas. Commit and recovery mutate only on their common apply events. */ -class OooPcBuffer(val p: OooParams = OooParams()) extends Module { +class OooPcBuffer(val p: CoreParams = ParamProfiles.Default) extends Module { val io = IO(new OooPcBufferIO(p)) - private val maxOffset = ((BigInt(1) << p.pcOffsetWidth) - 1).U(p.pcWidth.W) - private def partitionBase(stid: UInt): UInt = - stid * p.pcEntriesPerStid.U - private def localIndex(token: PcBufferToken): UInt = - token.index(p.pcPartitionIndexWidth - 1, 0) - - val table = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.pcBankCount)( - VecInit(Seq.fill(p.pcRowsPerBank)( - 0.U.asTypeOf(new OooPcBaseEntry(p))))))))) - val readReplicas = RegInit(VecInit(Seq.fill(p.pcReadReplicaCount)( - VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.pcBankCount)( - VecInit(Seq.fill(p.pcRowsPerBank)( - 0.U.asTypeOf(new OooPcReadEntry(p))))))))))) + private val d3Width = p.ooo.d3PrefixWidth + private val retireWidth = p.widths.retireWidth + private val entriesPerStid = p.ooo.pcBufferEntries / p.ooo.stidCount + private val localWidth = InterfaceWidth.index(entriesPerStid) + private val indexWidth = InterfaceWidth.index(p.ooo.pcBufferEntries) + private val usedWidth = PrefixPacketContract.countWidth(entriesPerStid) + private val liveWidth = PrefixPacketContract.countWidth( + p.ooo.robGroupsPerStid) + private val bankSelectionBits = + if (p.ooo.pcBankCount == 1) 0 else log2Ceil(p.ooo.pcBankCount) + private val rowsPerBank = entriesPerStid / p.ooo.pcBankCount + private val bankIndexWidth = InterfaceWidth.index(p.ooo.pcBankCount) + private val bankRowWidth = InterfaceWidth.index(rowsPerBank) + private val scanWidth = p.ooo.pcRecoveryScanGroupsPerCycle + private val scanCursorWidth = PrefixPacketContract.countWidth(entriesPerStid) + private val maxOffset = + ((BigInt(1) << p.ooo.pcOffsetWidth) - 1).U(p.pcWidth.W) + + private def partitionBase(stid: UInt): UInt = stid * entriesPerStid.U + private def inPartition(index: UInt, stid: UInt): Bool = + if (p.ooo.stidCount == 1) true.B + else index >= partitionBase(stid) && + index < partitionBase(stid) + entriesPerStid.U + private def localFromIndex(index: UInt): UInt = index(localWidth - 1, 0) + private def sizedLocal(local: UInt): UInt = local.pad(localWidth) + private def bank(local: UInt): UInt = + if (p.ooo.pcBankCount == 1) 0.U(bankIndexWidth.W) + else sizedLocal(local)(bankSelectionBits - 1, 0) + private def bankRow(local: UInt): UInt = + if (rowsPerBank == 1) 0.U(bankRowWidth.W) + else sizedLocal(local)(localWidth - 1, bankSelectionBits) + private def groupMatches(a: VirtualRobGroupIntent, b: RobIdentity): Bool = + a.valid && a.peId === b.peId && a.stid === b.stid && + a.ridSlot === b.ridSlot && a.ridGeneration === b.ridGeneration + private def nextGroup(previous: RobIdentity, current: RobIdentity): Bool = { + val slotSum = previous.ridSlot +& 1.U + val wraps = slotSum >= p.ooo.robGroupsPerStid.U + current.peId === previous.peId && current.stid === previous.stid && + current.ridSlot === Mux(wraps, 0.U(p.ooo.ridSlotWidth.W), + slotSum(p.ooo.ridSlotWidth - 1, 0)) && + current.ridGeneration === previous.ridGeneration + wraps.asUInt + } + private def groupOrdinal(id: RobIdentity): UInt = + Cat(id.ridGeneration, id.ridSlot) + private def select[T <: Data](values: Vec[T], index: UInt): T = + if (p.ooo.stidCount == 1) values(0) else values(index) + + private val table = RegInit(VecInit(Seq.fill(p.ooo.stidCount) { + VecInit(Seq.fill(p.ooo.pcBankCount) { + VecInit(Seq.fill(rowsPerBank)(0.U.asTypeOf(new PcBufferRow(p)))) + }) + })) + private val readReplicas = RegInit(VecInit(Seq.fill( + p.ooo.pcReadReplicaCount) { + VecInit(Seq.fill(p.ooo.stidCount) { + VecInit(Seq.fill(p.ooo.pcBankCount) { + VecInit(Seq.fill(rowsPerBank)( + 0.U.asTypeOf(new PcBufferReadRow(p)))) + }) + }) + })) dontTouch(readReplicas) - private def sizedLocal(local: UInt): UInt = - local.pad(p.pcPartitionIndexWidth) - private def pcBankIndex(local: UInt): UInt = - if (p.pcBankCount == 1) 0.U(p.pcBankIndexWidth.W) - else sizedLocal(local)(p.pcBankSelectionBits - 1, 0) - private def pcBankRowIndex(local: UInt): UInt = - if (p.pcRowsPerBank == 1) 0.U(p.pcBankRowIndexWidth.W) - else sizedLocal(local)(p.pcPartitionIndexWidth - 1, - p.pcBankSelectionBits) - private def rowAt(stid: UInt, local: UInt): OooPcBaseEntry = - table(stid)(pcBankIndex(local))(pcBankRowIndex(local)) + + private def rowAt(stid: UInt, local: UInt): PcBufferRow = + select(table, stid)(bank(local))(bankRow(local)) private def readRowAt( replica: Int, stid: UInt, - local: UInt): OooPcReadEntry = - readReplicas(replica)(stid)(pcBankIndex(local))(pcBankRowIndex(local)) - val usedBases = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.pcPartitionCountWidth.W)))) - val headLocal = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.pcPartitionIndexWidth.W)))) - val headEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.reservationEpochWidth.W)))) - val tailLocal = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.pcPartitionIndexWidth.W)))) - val tailEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.reservationEpochWidth.W)))) - val currentValid = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val currentToken = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new PcBufferToken(p))))) - val currentBase = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.pcWidth.W)))) - - val recoveryScanState = RegInit(OooPcRecoveryScanState.Idle) - val retainedRecoveryPlan = RegInit( - 0.U.asTypeOf(new OooRobRecoveryPlan(p))) - val retainedRecoveryPrepared = RegInit( - 0.U.asTypeOf(new OooPcRecoveryPrepared(p))) - val retainedRecoveryReject = RegInit( - 0.U.asTypeOf(new OooPcRecoveryReject(p))) - val recoveryScanCursor = RegInit(0.U(p.pcRecoveryScanCursorWidth.W)) - val recoveryHitCounts = RegInit(VecInit(Seq.fill(p.pcEntriesPerStid)( - 0.U(p.nonFlushPrefixCountWidth.W)))) - val recoveryPriorKeys = RegInit(VecInit(Seq.fill(p.pcEntriesPerStid)( - 0.U.asTypeOf(new RobGroupKey(p))))) - val recoveryCloseOwnerKilledMask = RegInit(0.U(p.pcEntriesPerStid.W)) - val recoveryFreedRowMask = RegInit(0.U(p.pcEntriesPerStid.W)) - val recoveryFreedBasesReg = RegInit(0.U(p.nonFlushPrefixCountWidth.W)) - val recoveryFirstAllocatedValid = RegInit(false.B) - val recoveryFirstAllocated = RegInit( - 0.U.asTypeOf(new PcBufferToken(p))) - val recoveryKilledRowsExactReg = RegInit(true.B) - val recoveryAllocatedOrderExactReg = RegInit(true.B) - val recoverySnapshotUsedBases = RegInit(0.U(p.pcPartitionCountWidth.W)) - val recoverySnapshotTail = RegInit( - 0.U.asTypeOf(new PcBufferToken(p))) - - val recoveryPlan = Mux( - recoveryScanState === OooPcRecoveryScanState.Idle, - io.recoveryPrepare.bits, - retainedRecoveryPlan) - val recoveryStid = recoveryPlan.request.rename.key.member.group.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryOfferExact = io.recoveryPrepare.valid && - io.recoveryPrepare.bits.asUInt === recoveryPlan.asUInt - val recoveryTargetsStid = - (io.recoveryPrepare.valid || - recoveryScanState =/= OooPcRecoveryScanState.Idle) && - recoveryPlan.valid && recoveryStidInRange - val recoveryCommitConflict = WireDefault(false.B) - - val prepareStid = io.prepare.bits.transaction.plan.stid - val prepareStidInRange = prepareStid < p.stidCount.U - val safePrepareStid = Mux(prepareStidInRange, prepareStid, 0.U) - val groupCount = io.prepare.bits.transaction.plan.groupCount - val groupCountInRange = groupCount.orR && groupCount <= p.instructionDecodeWidth.U - val expectedGroupMask = - ((1.U((p.instructionDecodeWidth + 1).W) << groupCount) - 1.U)( - p.instructionDecodeWidth - 1, 0) - - val groupHasPc = Wire(Vec(p.instructionDecodeWidth, Bool())) - val groupMinPc = Wire(Vec(p.instructionDecodeWidth, UInt(p.pcWidth.W))) - val groupMaxPc = Wire(Vec(p.instructionDecodeWidth, UInt(p.pcWidth.W))) - val groupParentsExact = Wire(Vec(p.instructionDecodeWidth, Bool())) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val seen = Wire(Vec(p.decodedUopWidth * p.maxArchitecturalParentRefs + 1, Bool())) - val minima = Wire(Vec(p.decodedUopWidth * p.maxArchitecturalParentRefs + 1, - UInt(p.pcWidth.W))) - val maxima = Wire(Vec(p.decodedUopWidth * p.maxArchitecturalParentRefs + 1, - UInt(p.pcWidth.W))) + local: UInt): PcBufferReadRow = + select(readReplicas(replica), stid)(bank(local))(bankRow(local)) + + private val usedBases = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(usedWidth.W)))) + private val headLocal = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(localWidth.W)))) + private val headEpoch = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.pcAllocationEpochWidth.W)))) + private val tailLocal = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(localWidth.W)))) + private val tailEpoch = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.pcAllocationEpochWidth.W)))) + private val currentValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + private val currentIndex = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(indexWidth.W)))) + private val currentEpoch = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.pcAllocationEpochWidth.W)))) + private val currentBase = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.pcWidth.W)))) + + // D3 exact ROB-group discovery. + private val prepareCount = io.prepare.bits.count + private val prepareCountExact = prepareCount =/= 0.U && + prepareCount <= d3Width.U + private val firstRob = io.prepare.bits.entries(0).uop.decoded.rob + private val prepareStidInRange = firstRob.stid < p.ooo.stidCount.U + private val prepareStid = Mux(prepareStidInRange, firstRob.stid, 0.U) + private val groupCount = io.prepare.bits.groupCount + private val groupCountExact = groupCount =/= 0.U && + groupCount <= prepareCount && groupCount <= d3Width.U + + private val laneGroupMatch = Wire(Vec(d3Width, Vec(d3Width, Bool()))) + for (lane <- 0 until d3Width; group <- 0 until d3Width) { + val active = lane.U < prepareCount + laneGroupMatch(lane)(group) := active && group.U < groupCount && + groupMatches(io.prepare.bits.groups(group), + io.prepare.bits.entries(lane).uop.decoded.rob) + } + + private val groupSeen = Wire(Vec(d3Width, Bool())) + private val groupMinPc = Wire(Vec(d3Width, UInt(p.pcWidth.W))) + private val groupMaxPc = Wire(Vec(d3Width, UInt(p.pcWidth.W))) + private val groupFirstRob = Wire(Vec(d3Width, new RobIdentity(p))) + private val groupLastRob = Wire(Vec(d3Width, new RobIdentity(p))) + private val groupTrap = Wire(Vec(d3Width, Bool())) + private val groupBlockStop = Wire(Vec(d3Width, Bool())) + for (group <- 0 until d3Width) { + val seen = Wire(Vec(d3Width + 1, Bool())) + val minima = Wire(Vec(d3Width + 1, UInt(p.pcWidth.W))) + val maxima = Wire(Vec(d3Width + 1, UInt(p.pcWidth.W))) + val first = Wire(Vec(d3Width + 1, new RobIdentity(p))) + val last = Wire(Vec(d3Width + 1, new RobIdentity(p))) + val traps = Wire(Vec(d3Width + 1, Bool())) + val stops = Wire(Vec(d3Width + 1, Bool())) seen(0) := false.B minima(0) := 0.U maxima(0) := 0.U - for (uopIndex <- 0 until p.decodedUopWidth; - parentIndex <- 0 until p.maxArchitecturalParentRefs) { - val flatIndex = uopIndex * p.maxArchitecturalParentRefs + parentIndex - val uop = io.prepare.bits.transaction.decoded.uops(uopIndex) - val parent = uop.identity.parents(parentIndex) - val hit = io.prepare.bits.transaction.groups(groupIndex).logicalUopMask(uopIndex) && - parentIndex.U < uop.identity.parentCount && parent.key.valid - seen(flatIndex + 1) := seen(flatIndex) || hit - minima(flatIndex + 1) := Mux( - !seen(flatIndex), - Mux(hit, parent.pc, minima(flatIndex)), - Mux(hit && parent.pc < minima(flatIndex), parent.pc, minima(flatIndex))) - maxima(flatIndex + 1) := Mux( - hit && (!seen(flatIndex) || parent.pc > maxima(flatIndex)), - parent.pc, - maxima(flatIndex)) + first(0) := 0.U.asTypeOf(first(0)) + last(0) := 0.U.asTypeOf(last(0)) + traps(0) := false.B + stops(0) := false.B + for (lane <- 0 until d3Width) { + val hit = laneGroupMatch(lane)(group) + val entry = io.prepare.bits.entries(lane) + val pc = entry.uop.decoded.instruction.parent.pc + seen(lane + 1) := seen(lane) || hit + minima(lane + 1) := Mux(hit && (!seen(lane) || pc < minima(lane)), + pc, minima(lane)) + maxima(lane + 1) := Mux(hit && (!seen(lane) || pc > maxima(lane)), + pc, maxima(lane)) + first(lane + 1) := Mux(hit && !seen(lane), + entry.uop.decoded.rob, first(lane)) + last(lane + 1) := Mux(hit, entry.uop.decoded.rob, last(lane)) + traps(lane + 1) := traps(lane) || (hit && entry.trap.valid) + stops(lane + 1) := stops(lane) || (hit && + (entry.blockStop || entry.uop.decoded.blockStop)) } - groupHasPc(groupIndex) := seen.last - groupMinPc(groupIndex) := minima.last - groupMaxPc(groupIndex) := maxima.last - groupParentsExact(groupIndex) := (0 until p.decodedUopWidth).flatMap { uopIndex => - (0 until p.maxArchitecturalParentRefs).map { parentIndex => - val uop = io.prepare.bits.transaction.decoded.uops(uopIndex) - val parent = uop.identity.parents(parentIndex) - val hit = io.prepare.bits.transaction.groups(groupIndex).logicalUopMask(uopIndex) && - parentIndex.U < uop.identity.parentCount - !hit || (parent.key.valid && - parent.key.peId === io.prepare.bits.transaction.plan.peId && - parent.key.stid === prepareStid && - parent.key.epoch === io.prepare.bits.transaction.plan.epoch) - } - }.reduce(_ && _) + groupSeen(group) := seen.last + groupMinPc(group) := minima.last + groupMaxPc(group) := maxima.last + groupFirstRob(group) := first.last + groupLastRob(group) := last.last + groupTrap(group) := traps.last + groupBlockStop(group) := stops.last } - val scanValid = Wire(Vec(p.instructionDecodeWidth + 1, Bool())) - val scanToken = Wire(Vec(p.instructionDecodeWidth + 1, new PcBufferToken(p))) - val scanBase = Wire(Vec(p.instructionDecodeWidth + 1, UInt(p.pcWidth.W))) - val scanAllocCount = Wire(Vec(p.instructionDecodeWidth + 1, UInt(p.robGroupCountWidth.W))) - val scanLegal = Wire(Vec(p.instructionDecodeWidth, Bool())) - val groupTokens = Wire(Vec(p.instructionDecodeWidth, new PcBufferToken(p))) - val groupBases = Wire(Vec(p.instructionDecodeWidth, UInt(p.pcWidth.W))) - val newBase = Wire(Vec(p.instructionDecodeWidth, Bool())) - val implicitClose = Wire(Vec(p.instructionDecodeWidth, Bool())) - val implicitCloseTokens = Wire(Vec(p.instructionDecodeWidth, new PcBufferToken(p))) - - scanValid(0) := currentValid(safePrepareStid) - scanToken(0) := currentToken(safePrepareStid) - scanBase(0) := currentBase(safePrepareStid) + private val laneShapeExact = (0 until d3Width).map { lane => + val active = lane.U < prepareCount + val entry = io.prepare.bits.entries(lane) + Mux(active, + entry.uop.decoded.valid && + PopCount(laneGroupMatch(lane)) === 1.U && + entry.uop.decoded.rob.stid === firstRob.stid && + entry.uop.decoded.rob.peId === firstRob.peId && + entry.uop.decoded.instruction.parent.identity.stid === firstRob.stid && + entry.uop.decoded.instruction.parent.identity.peId === firstRob.peId, + !entry.uop.decoded.valid) + }.reduce(_ && _) + private val groupShapeExact = (0 until d3Width).map { group => + val active = group.U < groupCount + Mux(active, + io.prepare.bits.groups(group).valid && groupSeen(group), + !io.prepare.bits.groups(group).valid && !groupSeen(group)) + }.reduce(_ && _) + + // Base selection proceeds in exact group order and never mutates state. + private val scanValid = Wire(Vec(d3Width + 1, Bool())) + private val scanIndex = Wire(Vec(d3Width + 1, UInt(indexWidth.W))) + private val scanEpoch = Wire(Vec(d3Width + 1, + UInt(p.ooo.pcAllocationEpochWidth.W))) + private val scanBase = Wire(Vec(d3Width + 1, UInt(p.pcWidth.W))) + private val scanAllocCount = Wire(Vec(d3Width + 1, UInt(usedWidth.W))) + private val groupIndex = Wire(Vec(d3Width, UInt(indexWidth.W))) + private val groupEpoch = Wire(Vec(d3Width, + UInt(p.ooo.pcAllocationEpochWidth.W))) + private val groupBase = Wire(Vec(d3Width, UInt(p.pcWidth.W))) + private val groupNewBase = Wire(Vec(d3Width, Bool())) + private val groupImplicitClose = Wire(Vec(d3Width, Bool())) + private val groupImplicitCloseIndex = Wire(Vec(d3Width, UInt(indexWidth.W))) + private val groupImplicitCloseEpoch = Wire(Vec(d3Width, + UInt(p.ooo.pcAllocationEpochWidth.W))) + + scanValid(0) := select(currentValid, prepareStid) + scanIndex(0) := select(currentIndex, prepareStid) + scanEpoch(0) := select(currentEpoch, prepareStid) + scanBase(0) := select(currentBase, prepareStid) scanAllocCount(0) := 0.U - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = io.prepare.bits.transaction.groups(groupIndex) - val active = groupIndex.U < groupCount - val currentFits = groupHasPc(groupIndex) && - groupMinPc(groupIndex) >= scanBase(groupIndex) && - groupMaxPc(groupIndex) - scanBase(groupIndex) <= maxOffset - val allocate = active && - (!scanValid(groupIndex) || !currentFits || group.preciseTrap) - val tailSum = tailLocal(safePrepareStid) +& scanAllocCount(groupIndex) - val tailWrap = tailSum >= p.pcEntriesPerStid.U - val allocatedToken = Wire(new PcBufferToken(p)) - allocatedToken.valid := true.B - allocatedToken.index := - partitionBase(safePrepareStid) + tailSum(p.pcPartitionIndexWidth - 1, 0) - allocatedToken.byteOffset := 0.U - allocatedToken.allocationEpoch := tailEpoch(safePrepareStid) + tailWrap.asUInt - - newBase(groupIndex) := allocate - implicitClose(groupIndex) := allocate && scanValid(groupIndex) - implicitCloseTokens(groupIndex) := scanToken(groupIndex) - groupTokens(groupIndex) := Mux(allocate, allocatedToken, scanToken(groupIndex)) - groupBases(groupIndex) := Mux(allocate, groupMinPc(groupIndex), scanBase(groupIndex)) - val spanFits = groupHasPc(groupIndex) && - groupMaxPc(groupIndex) - groupMinPc(groupIndex) <= maxOffset - scanLegal(groupIndex) := Mux( - active, - group.valid && group.key.valid && - group.key.peId === io.prepare.bits.transaction.plan.peId && - group.key.stid === prepareStid && spanFits && - groupParentsExact(groupIndex) && - groupTokens(groupIndex).valid, - !group.valid) - val closes = group.releasePcBase || group.preciseTrap - scanValid(groupIndex + 1) := Mux(active, !closes, scanValid(groupIndex)) - scanToken(groupIndex + 1) := Mux(active, groupTokens(groupIndex), scanToken(groupIndex)) - scanBase(groupIndex + 1) := Mux(active, groupBases(groupIndex), scanBase(groupIndex)) - scanAllocCount(groupIndex + 1) := scanAllocCount(groupIndex) + allocate.asUInt + for (group <- 0 until d3Width) { + val active = group.U < groupCount + val fits = groupSeen(group) && groupMinPc(group) >= scanBase(group) && + groupMaxPc(group) - scanBase(group) <= maxOffset + val allocate = active && (!scanValid(group) || !fits || groupTrap(group)) + val tailSum = select(tailLocal, prepareStid) +& scanAllocCount(group) + val wraps = tailSum >= entriesPerStid.U + val allocatedIndex = partitionBase(prepareStid) + + tailSum(localWidth - 1, 0) + groupNewBase(group) := allocate + groupImplicitClose(group) := allocate && scanValid(group) + groupImplicitCloseIndex(group) := scanIndex(group) + groupImplicitCloseEpoch(group) := scanEpoch(group) + groupIndex(group) := Mux(allocate, allocatedIndex, scanIndex(group)) + groupEpoch(group) := Mux(allocate, + select(tailEpoch, prepareStid) + wraps.asUInt, scanEpoch(group)) + groupBase(group) := Mux(allocate, groupMinPc(group), scanBase(group)) + val closes = active && (groupBlockStop(group) || groupTrap(group)) + scanValid(group + 1) := Mux(active, !closes, scanValid(group)) + scanIndex(group + 1) := Mux(active, groupIndex(group), scanIndex(group)) + scanEpoch(group + 1) := Mux(active, groupEpoch(group), scanEpoch(group)) + scanBase(group + 1) := Mux(active, groupBase(group), scanBase(group)) + scanAllocCount(group + 1) := scanAllocCount(group) + allocate.asUInt } - val allocatedBases = scanAllocCount.last - val freeBases = p.pcEntriesPerStid.U(p.pcPartitionCountWidth.W) - - usedBases(safePrepareStid) - val hasCapacity = freeBases >= allocatedBases - val writePortsFit = allocatedBases <= p.pcWritePorts.U - val newTargetsFree = (0 until p.instructionDecodeWidth).map { groupIndex => - !newBase(groupIndex) || - !rowAt(safePrepareStid, localIndex(groupTokens(groupIndex))).valid - }.reduce(_ && _) - val liveCurrentExact = !currentValid(safePrepareStid) || { - val row = rowAt(safePrepareStid, localIndex(currentToken(safePrepareStid))) - row.valid && row.token.index === currentToken(safePrepareStid).index && - row.token.allocationEpoch === currentToken(safePrepareStid).allocationEpoch && - row.stid === prepareStid && row.base === currentBase(safePrepareStid) + private val freeBases = entriesPerStid.U(usedWidth.W) - + select(usedBases, prepareStid) + private val groupResourceExact = Wire(Vec(d3Width, Bool())) + private val acceptedGroupChain = Wire(Vec(d3Width + 1, Bool())) + private val acceptedGroups = Wire(Vec(d3Width, Bool())) + acceptedGroupChain(0) := true.B + for (group <- 0 until d3Width) { + val active = group.U < groupCount + val allocatedThroughGroup = scanAllocCount(group + 1) + val offsetExact = groupSeen(group) && + groupMaxPc(group) >= groupBase(group) && + groupMaxPc(group) - groupBase(group) <= maxOffset + val local = localFromIndex(groupIndex(group)) + val rowAvailable = !groupNewBase(group) || + !rowAt(prepareStid, local).valid + groupResourceExact(group) := active && offsetExact && rowAvailable && + allocatedThroughGroup <= p.ooo.pcWritePorts.U && + allocatedThroughGroup <= freeBases + acceptedGroups(group) := acceptedGroupChain(group) && + groupResourceExact(group) + acceptedGroupChain(group + 1) := acceptedGroups(group) + } + private val localOfferedGroupCount = PopCount(acceptedGroups) + private val localOfferedLanes = Wire(Vec(d3Width, Bool())) + for (lane <- 0 until d3Width) { + localOfferedLanes(lane) := lane.U < prepareCount && + (0 until d3Width).map { group => + group.U < localOfferedGroupCount && laneGroupMatch(lane)(group) + }.reduce(_ || _) + } + private val localOfferedCount = PopCount(localOfferedLanes) + private val acceptedGroupCount = io.selectedLimit.bits.groupCount + private val acceptedCount = io.selectedLimit.bits.count + private val acceptedLanes = Wire(Vec(d3Width, Bool())) + for (lane <- 0 until d3Width) { + acceptedLanes(lane) := lane.U < prepareCount && + (0 until d3Width).map { group => + group.U < acceptedGroupCount && laneGroupMatch(lane)(group) + }.reduce(_ || _) + } + private val boundGroupFirstRob = Wire(Vec(d3Width, new RobIdentity(p))) + private val boundGroupLastRob = Wire(Vec(d3Width, new RobIdentity(p))) + for (group <- 0 until d3Width) { + val boundFirst = Wire(Vec(d3Width + 1, new RobIdentity(p))) + val boundLast = Wire(Vec(d3Width + 1, new RobIdentity(p))) + val boundSeen = Wire(Vec(d3Width + 1, Bool())) + boundFirst(0) := 0.U.asTypeOf(boundFirst(0)) + boundLast(0) := 0.U.asTypeOf(boundLast(0)) + boundSeen(0) := false.B + for (lane <- 0 until d3Width) { + val hit = laneGroupMatch(lane)(group) && lane.U < acceptedCount + val identity = io.publicationIdentity.bits.entries(lane).rob + boundFirst(lane + 1) := Mux(hit && !boundSeen(lane), + identity, boundFirst(lane)) + boundLast(lane + 1) := Mux(hit, identity, boundLast(lane)) + boundSeen(lane + 1) := boundSeen(lane) || hit + } + boundGroupFirstRob(group) := boundFirst.last + boundGroupLastRob(group) := boundLast.last + } + private val acceptedLanePrefixExact = (0 until d3Width).map { lane => + acceptedLanes(lane) === (lane.U < acceptedCount) + }.reduce(_ && _) && acceptedGroupCount.orR && acceptedCount.orR && + acceptedGroupCount <= localOfferedGroupCount && + acceptedCount <= localOfferedCount + private val allocatedBases = scanAllocCount(acceptedGroupCount) + private val acceptedScanValid = scanValid(acceptedGroupCount) + private val acceptedScanIndex = scanIndex(acceptedGroupCount) + private val acceptedScanEpoch = scanEpoch(acceptedGroupCount) + private val acceptedScanBase = scanBase(acceptedGroupCount) + private val currentRowExact = !select(currentValid, prepareStid) || { + val current = select(currentIndex, prepareStid) + val row = rowAt(prepareStid, localFromIndex(current)) + row.valid && row.stid === prepareStid && + row.pcBufferIndex === current && + row.allocationEpoch === select(currentEpoch, prepareStid) && + row.pcBase === select(currentBase, prepareStid) } - val uopMappingExact = (0 until p.decodedUopWidth).map { uopIndex => - val active = io.prepare.bits.transaction.decoded.uopMask(uopIndex) - val uop = io.prepare.bits.transaction.decoded.uops(uopIndex) - val requestedGroup = io.prepare.bits.transaction.uopGroupIndex(uopIndex) - val groupInRange = requestedGroup < groupCount && - requestedGroup < p.instructionDecodeWidth.U - val safeGroup = Mux(groupInRange, requestedGroup, 0.U) - val targetGroup = io.prepare.bits.transaction.groups(safeGroup) - val maskInverseExact = (0 until p.instructionDecodeWidth).map { groupIndex => - io.prepare.bits.transaction.groups(groupIndex).logicalUopMask(uopIndex) === - (active && requestedGroup === groupIndex.U) - }.reduce(_ && _) - val parentsFit = (0 until p.maxArchitecturalParentRefs).map { parentIndex => - val parent = uop.identity.parents(parentIndex) - val parentActive = active && parentIndex.U < uop.identity.parentCount - !parentActive || (parent.key.valid && parent.pc >= groupBases(safeGroup) && - parent.pc - groupBases(safeGroup) <= maxOffset) - }.reduce(_ && _) - uop.valid === active && (!active || - (groupInRange && targetGroup.valid && targetGroup.logicalUopMask(uopIndex) && - maskInverseExact && parentsFit)) - }.reduce(_ && _) - - val commitStid = io.commit.bits.release.firstGroup.stid - val exactCommitConflict = Wire(Bool()) - val prepareExact = prepareStidInRange && groupCountInRange && - io.prepare.bits.transaction.groupMask === expectedGroupMask && - io.prepare.bits.transaction.plan.peId === io.prepare.bits.transaction.decoded.peId && - io.prepare.bits.transaction.plan.stid === io.prepare.bits.transaction.decoded.stid && - scanLegal.reduce(_ && _) && uopMappingExact && hasCapacity && writePortsFit && - newTargetsFree && liveCurrentExact + // Recovery state is declared before admission so its target can fence only + // the selected STID while peer partitions continue. + private val recoveryState = RegInit(PcBufferRecoveryState.Idle) + private val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + private val recoveryTargetStid = recoveryPlan.trigger.stid + private val offeredRecoveryStid = io.recovery.prepare.bits.trigger.stid + private val recoveryOfferTargetsPrepare = io.recovery.prepare.valid && + offeredRecoveryStid < p.ooo.stidCount.U && + prepareStidInRange && offeredRecoveryStid === prepareStid + private val retainedRecoveryTargetsPrepare = + recoveryState =/= PcBufferRecoveryState.Idle && + prepareStidInRange && recoveryTargetStid === prepareStid + private val prepareRecoveryFence = recoveryOfferTargetsPrepare || + retainedRecoveryTargetsPrepare + + private val commitCount = io.commitPreview.bits.count + private val commitCountExact = commitCount =/= 0.U && + commitCount <= retireWidth.U + private val commitFirstRob = io.commitPreview.bits.entries(0).rob + private val commitStidInRange = commitFirstRob.stid < p.ooo.stidCount.U + private val commitStid = Mux(commitStidInRange, commitFirstRob.stid, 0.U) + private val sameStidCommitPreview = io.commitPreview.valid && + commitStidInRange && prepareStidInRange && commitStid === prepareStid + private val sameStidCommitApply = sameStidCommitPreview && io.commitApply + + io.prefixOffer.valid := io.prepare.valid && prepareCountExact && + prepareStidInRange && groupCountExact && laneShapeExact && + groupShapeExact && localOfferedGroupCount.orR && + localOfferedCount.orR && currentRowExact && !prepareRecoveryFence && + !sameStidCommitApply + io.prefixOffer.bits.count := localOfferedCount + io.prefixOffer.bits.groupCount := localOfferedGroupCount + io.prepareReady := io.prepare.valid && prepareCountExact && + prepareStidInRange && groupCountExact && laneShapeExact && + groupShapeExact && io.selectedLimit.valid && acceptedLanePrefixExact && + currentRowExact && !prepareRecoveryFence && !sameStidCommitApply io.prepared := 0.U.asTypeOf(io.prepared) - io.prepared.validMask := expectedGroupMask - io.prepared.groupTokens := groupTokens - io.prepared.newBaseMask := newBase.asUInt - io.prepared.newBases := groupBases - io.prepared.implicitCloseMask := implicitClose.asUInt - io.prepared.implicitCloseTokens := implicitCloseTokens - io.prepared.allocatedBases := allocatedBases - io.prepared.currentAfterValid := scanValid.last - io.prepared.currentAfter := scanToken.last - for (uopIndex <- 0 until p.decodedUopWidth; - parentIndex <- 0 until p.maxArchitecturalParentRefs) { - val requestedGroup = io.prepare.bits.transaction.uopGroupIndex(uopIndex) - val groupInRange = requestedGroup < groupCount && - requestedGroup < p.instructionDecodeWidth.U - val groupIndex = Mux(groupInRange, requestedGroup, 0.U) - val parent = io.prepare.bits.transaction.decoded.uops(uopIndex).identity.parents(parentIndex) - val token = io.prepared.parentTokens(uopIndex)(parentIndex) - val parentValid = io.prepare.bits.transaction.decoded.uopMask(uopIndex) && - parentIndex.U < io.prepare.bits.transaction.decoded.uops(uopIndex).identity.parentCount && - parent.key.valid - token.valid := parentValid && groupInRange - token.index := groupTokens(groupIndex).index - token.byteOffset := Mux(parentValid && groupInRange, - parent.pc - groupBases(groupIndex), 0.U) - token.allocationEpoch := groupTokens(groupIndex).allocationEpoch + io.prepared.count := acceptedCount + io.prepared.groupCount := acceptedGroupCount + for (lane <- 0 until d3Width) { + val matches = laneGroupMatch(lane) + val selected = PriorityEncoder(matches.asUInt) + val active = lane.U < acceptedCount && matches.asUInt.orR + val pc = io.prepare.bits.entries(lane).uop.decoded.instruction.parent.pc + io.prepared.lanes(lane).valid := active + io.prepared.lanes(lane).pcBufferIndex := groupIndex(selected) + io.prepared.lanes(lane).pcOffset := + (pc - groupBase(selected))(p.ooo.pcOffsetWidth - 1, 0) + io.prepared.lanes(lane).allocationEpoch := groupEpoch(selected) } - val recoveryBlocksPrepare = recoveryTargetsStid && - prepareStid === recoveryStid - io.prepareReady := prepareExact && !exactCommitConflict && - !recoveryBlocksPrepare - io.prepareRejected.valid := io.prepare.valid && !io.prepareReady - io.prepareRejected.bits.stid := prepareStid - io.prepareRejected.bits.transactionId := io.prepare.bits.transaction.plan.transactionId - io.prepareRejected.bits.groupMask := io.prepare.bits.transaction.groupMask - - val commitCount = io.commit.bits.release.groupCount - val commitStidInRange = commitStid < p.stidCount.U - val safeCommitStid = Mux(commitStidInRange, commitStid, 0.U) - val commitCountInRange = commitCount.orR && commitCount <= p.retireGroupWidth.U - val headToken = Wire(new PcBufferToken(p)) - headToken.valid := usedBases(safeCommitStid).orR - headToken.index := partitionBase(safeCommitStid) + headLocal(safeCommitStid) - headToken.byteOffset := 0.U - headToken.allocationEpoch := headEpoch(safeCommitStid) - - val commitGroupExact = Wire(Vec(p.retireGroupWidth, Bool())) - for (groupIndex <- 0 until p.retireGroupWidth) { - val active = groupIndex.U < commitCount - val group = io.commit.bits.groups(groupIndex) - val row = rowAt(safeCommitStid, localIndex(group.pcBase)) - val liveExact = group.valid && group.key.valid && group.key.stid === commitStid && - group.pcBase.valid && row.valid && row.stid === commitStid && - row.token.asUInt === group.pcBase.asUInt - val startsEntry = if (groupIndex == 0) true.B else - group.pcBase.index =/= io.commit.bits.groups(groupIndex - 1).pcBase.index || - group.pcBase.allocationEpoch =/= - io.commit.bits.groups(groupIndex - 1).pcBase.allocationEpoch - val entryPrefixExact = !startsEntry || - (row.nextCommitRobGroup.valid && row.nextCommitRobGroup.asUInt === group.key.asUInt) - val ridSequential = if (groupIndex == 0) true.B else { - val prior = io.commit.bits.groups(groupIndex - 1).key - val sum = prior.ridSlot +& 1.U - val wrap = sum >= p.robGroupsPerStid.U - group.key.peId === prior.peId && group.key.stid === prior.stid && - group.key.ridSlot === sum(p.ridSlotWidth - 1, 0) && - group.key.ridGeneration === prior.ridGeneration + wrap.asUInt + + private val publishFire = io.publishFire && io.prepare.valid && + io.prepareReady + when(io.publishFire) { + assert(io.prepare.valid && io.prepareReady, + "PC-buffer publication requires the exact accepted D3 view") + assert(io.publicationIdentity.valid && + io.publicationIdentity.bits.count === acceptedCount, + "PC-buffer publication requires ROB-bound identities for the exact accepted prefix") + for (lane <- 0 until d3Width) { + when(lane.U < acceptedCount) { + val preparedRob = io.prepare.bits.entries(lane).uop.decoded.rob + val bound = io.publicationIdentity.bits.entries(lane) + assert(bound.valid && bound.rob.peId === preparedRob.peId && + bound.rob.stid === preparedRob.stid && + bound.rob.ridSlot === preparedRob.ridSlot && + bound.rob.ridGeneration === preparedRob.ridGeneration && + bound.rob.memberIndex === preparedRob.memberIndex, + "PC-buffer ROB-bound publication identities must preserve accepted lane order") + } } - val orderExact = if (groupIndex == 0) { - val headRow = rowAt(safeCommitStid, headLocal(safeCommitStid)) - val nextSum = headLocal(safeCommitStid) +& 1.U - val nextWrap = nextSum >= p.pcEntriesPerStid.U - val closesEmptyHead = headRow.valid && headRow.closed && - headRow.liveRobGroups === 0.U && headRow.closeOwnerValid && - headRow.closeOwner.asUInt === group.key.asUInt && - group.pcBase.index === partitionBase(safeCommitStid) + - nextSum(p.pcPartitionIndexWidth - 1, 0) && - group.pcBase.allocationEpoch === headEpoch(safeCommitStid) + nextWrap.asUInt - (group.pcBase.index === headToken.index && - group.pcBase.allocationEpoch === headToken.allocationEpoch) || closesEmptyHead - } else { - val prior = io.commit.bits.groups(groupIndex - 1).pcBase - val priorGroup = io.commit.bits.groups(groupIndex - 1) - val sameBase = group.pcBase.asUInt === prior.asUInt && - !priorGroup.releasePcBase && !priorGroup.preciseTrap - val priorLocal = localIndex(prior) - val nextSum = priorLocal +& 1.U - val nextWrap = nextSum >= p.pcEntriesPerStid.U - val nextBase = group.pcBase.index === partitionBase(safeCommitStid) + - nextSum(p.pcPartitionIndexWidth - 1, 0) && - group.pcBase.allocationEpoch === prior.allocationEpoch + nextWrap.asUInt - sameBase || nextBase + } + + // Exact ordered commit preview. Only group-last rows advance the base owner. + private val commitLaneExact = Wire(Vec(retireWidth, Bool())) + for (lane <- 0 until retireWidth) { + val active = lane.U < commitCount + val entry = io.commitPreview.bits.entries(lane) + val reference = entry.pcBufferIndexOffset + val local = localFromIndex(reference.pcBufferIndex) + val row = rowAt(commitStid, local) + val partitionExact = inPartition(reference.pcBufferIndex, commitStid) + val rowExact = reference.valid && partitionExact && row.valid && + row.stid === commitStid && + row.pcBufferIndex === reference.pcBufferIndex && + row.allocationEpoch === reference.allocationEpoch + val priorHits = Wire(Vec(lane + 1, Bool())) + val priorRob = Wire(new RobIdentity(p)) + priorRob := 0.U.asTypeOf(priorRob) + for (prior <- 0 until lane) { + val previous = io.commitPreview.bits.entries(prior) + priorHits(prior) := prior.U < commitCount && previous.robGroupLast && + previous.pcBufferIndexOffset.valid && + previous.pcBufferIndexOffset.pcBufferIndex === + reference.pcBufferIndex && + previous.pcBufferIndexOffset.allocationEpoch === + reference.allocationEpoch + when(priorHits(prior)) { priorRob := previous.rob } } - commitGroupExact(groupIndex) := Mux( - active, - liveExact && entryPrefixExact && ridSequential && orderExact, - !group.valid) + priorHits(lane) := false.B + val hasPrior = priorHits.asUInt.orR + val firstGroupExact = row.nextCommitValid && + entry.rob.peId === row.nextCommitPeId && + entry.rob.stid === row.nextCommitStid && + entry.rob.ridSlot === row.nextCommitRidSlot && + entry.rob.ridGeneration === row.nextCommitRidGeneration + val ordered = !entry.robGroupLast || + Mux(hasPrior, nextGroup(priorRob, entry.rob), firstGroupExact) + commitLaneExact(lane) := Mux(active, + entry.rob.stid === commitFirstRob.stid && rowExact && ordered, + true.B) } - val hitsByLocal = Wire(Vec(p.pcEntriesPerStid, UInt(p.robReleaseCountWidth.W))) - for (local <- 0 until p.pcEntriesPerStid) { - val row = rowAt(safeCommitStid, local.U) - hitsByLocal(local) := PopCount((0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitCount && localIndex(io.commit.bits.groups(groupIndex).pcBase) === local.U && - io.commit.bits.groups(groupIndex).pcBase.allocationEpoch === - row.token.allocationEpoch + private val commitHitsByLocal = Wire(Vec(entriesPerStid, UInt( + PrefixPacketContract.countWidth(retireWidth).W))) + private val commitCloseByLocal = Wire(Vec(entriesPerStid, Bool())) + private val commitLastRobByLocal = Wire(Vec(entriesPerStid, + new RobIdentity(p))) + for (local <- 0 until entriesPerStid) { + val row = rowAt(commitStid, local.U) + val groupHits = VecInit((0 until retireWidth).map { lane => + val entry = io.commitPreview.bits.entries(lane) + lane.U < commitCount && entry.robGroupLast && + entry.pcBufferIndexOffset.valid && + localFromIndex(entry.pcBufferIndexOffset.pcBufferIndex) === local.U && + entry.pcBufferIndexOffset.allocationEpoch === row.allocationEpoch }) + commitHitsByLocal(local) := PopCount(groupHits) + commitCloseByLocal(local) := row.closeOwnerValid && + (0 until retireWidth).map { lane => + lane.U < commitCount && + io.commitPreview.bits.entries(lane).rob.asUInt === + row.closeOwner.asUInt + }.reduce(_ || _) + val last = Wire(new RobIdentity(p)) + last := 0.U.asTypeOf(last) + for (lane <- 0 until retireWidth) { + when(groupHits(lane)) { last := io.commitPreview.bits.entries(lane).rob } + } + commitLastRobByLocal(local) := last } - val countsLegal = (0 until p.pcEntriesPerStid).map { local => - hitsByLocal(local) <= rowAt(safeCommitStid, local.U).liveRobGroups + private val commitCountsExact = (0 until entriesPerStid).map { local => + commitHitsByLocal(local) <= rowAt(commitStid, local.U).liveRobGroups }.reduce(_ && _) - val freePrefix = Wire(Vec(p.retireGroupWidth + 1, UInt(p.robReleaseCountWidth.W))) - freePrefix(0) := 0.U - for (offset <- 0 until p.retireGroupWidth) { - val sum = headLocal(safeCommitStid) +& offset.U - val wrap = sum >= p.pcEntriesPerStid.U - val local = sum(p.pcPartitionIndexWidth - 1, 0) - val row = rowAt(safeCommitStid, local) - val closeOwnerCommits = (0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitCount && row.closeOwnerValid && - io.commit.bits.groups(groupIndex).key.asUInt === row.closeOwner.asUInt - }.reduce(_ || _) - val exact = row.valid && row.token.index === - partitionBase(safeCommitStid) + local && - row.token.allocationEpoch === headEpoch(safeCommitStid) + wrap.asUInt - val empty = row.closed && (row.closeCommitted || closeOwnerCommits) && - hitsByLocal(local) === row.liveRobGroups - val extend = freePrefix(offset) === offset.U && exact && empty - freePrefix(offset + 1) := Mux(extend, (offset + 1).U, freePrefix(offset)) + private val recoveryOfferTargetsCommit = io.recovery.prepare.valid && + offeredRecoveryStid < p.ooo.stidCount.U && commitStidInRange && + offeredRecoveryStid === commitStid + private val retainedRecoveryTargetsCommit = + recoveryState =/= PcBufferRecoveryState.Idle && commitStidInRange && + recoveryTargetStid === commitStid + private val commitRecoveryFence = recoveryOfferTargetsCommit || + retainedRecoveryTargetsCommit + + private val commitShapeExact = commitCountExact && commitStidInRange && + commitLaneExact.asUInt.andR && commitCountsExact + io.commitReady := io.commitPreview.valid && commitShapeExact && + !commitRecoveryFence + + when(io.commitApply && publishFire) { + assert(!prepareStidInRange || !commitStidInRange || + prepareStid =/= commitStid, + "PC-buffer cannot publish and commit the same STID on one edge") } - val freedBases = freePrefix.last - val releaseHeaderExact = io.commit.bits.release.firstGroup.valid && - io.commit.bits.groups(0).valid && - io.commit.bits.release.firstGroup.asUInt === io.commit.bits.groups(0).key.asUInt - val commitExact = commitStidInRange && commitCountInRange && - usedBases(safeCommitStid).orR && commitGroupExact.reduce(_ && _) && - countsLegal && releaseHeaderExact - recoveryCommitConflict := io.commit.valid && commitExact && - commitStid === recoveryStid - - // Recovery preparation walks a fixed number of ROB-group records per cycle. - // Every result below is private until all slices validate; common recoveryFire - // remains the sole event that mutates PC rows or partition pointers. - val recoveryExpectedKilledMask = - ((1.U((p.robGroupsPerStid + 1).W) << recoveryPlan.killedGroupCount) - 1.U)( - p.robGroupsPerStid - 1, 0) - val recoveryCaptureShapeExact = recoveryPlan.valid && - recoveryStidInRange && recoveryPlan.oldOccupied.orR && - recoveryPlan.oldOccupied <= p.robGroupsPerStid.U && - recoveryPlan.newOccupied <= recoveryPlan.oldOccupied && - recoveryPlan.killedGroupCount <= p.robGroupsPerStid.U && - recoveryPlan.killedGroupCount === - recoveryPlan.oldOccupied - recoveryPlan.newOccupied && - recoveryPlan.killedGroupMask === recoveryExpectedKilledMask && - recoveryPlan.survivingTailValid === recoveryPlan.newOccupied.orR && - (!recoveryPlan.survivingTailValid || - (recoveryPlan.survivingTail.valid && - recoveryPlan.survivingTail.key.valid && - recoveryPlan.survivingTail.key.stid === recoveryStid && - recoveryPlan.survivingTail.pcBase.valid)) - val recoveryCaptureMalformed = io.recoveryPrepare.valid && - recoveryScanState === OooPcRecoveryScanState.Idle && - !recoveryCaptureShapeExact - val recoveryOfferChanged = - recoveryScanState =/= OooPcRecoveryScanState.Idle && - recoveryScanState =/= OooPcRecoveryScanState.Rejected && - io.recoveryPrepare.valid && !recoveryOfferExact - - val recoveryScanGroups = Wire(Vec(p.pcRecoveryScanGroupsPerCycle, - new OooRobPhysicalGroupRecord(p))) - val recoveryScanActive = Wire(Vec(p.pcRecoveryScanGroupsPerCycle, Bool())) - val recoveryScanAllocated = Wire(Vec(p.pcRecoveryScanGroupsPerCycle, Bool())) - val recoveryScanRowsExact = Wire(Vec(p.pcRecoveryScanGroupsPerCycle, Bool())) - for (scanLane <- 0 until p.pcRecoveryScanGroupsPerCycle) { - val offsetWide = recoveryScanCursor * - p.pcRecoveryScanGroupsPerCycle.U + scanLane.U - val offset = Wire(UInt(p.nonFlushPrefixCountWidth.W)) - offset := offsetWide - val group = recoveryPlan.killedGroups(offset(p.ridSlotWidth - 1, 0)) - val active = offset < recoveryPlan.killedGroupCount - val row = rowAt(safeRecoveryStid, localIndex(group.pcBase)) - val implicitRow = rowAt(safeRecoveryStid, - localIndex(group.pcImplicitClose)) - recoveryScanGroups(scanLane) := group - recoveryScanActive(scanLane) := active - recoveryScanAllocated(scanLane) := active && group.pcBaseAllocated - recoveryScanRowsExact(scanLane) := - recoveryPlan.killedGroupMask(offset(p.ridSlotWidth - 1, 0)) === active && - (!active || (group.valid && group.key.valid && - group.key.stid === recoveryStid && group.pcBase.valid && - row.valid && row.stid === recoveryStid && - row.token.asUInt === group.pcBase.asUInt && - (!group.pcBaseAllocated || - row.firstRobGroup.asUInt === group.key.asUInt) && - (!group.pcImplicitCloseValid || - (group.pcBaseAllocated && implicitRow.valid && - implicitRow.stid === recoveryStid && - implicitRow.token.asUInt === group.pcImplicitClose.asUInt)))) - } - val recoverySliceAllocatedCount = PopCount(recoveryScanAllocated) - val recoverySliceHasAllocated = recoveryScanAllocated.asUInt.orR - val recoverySliceFirstAllocatedIndex = - if (p.pcRecoveryScanGroupsPerCycle == 1) 0.U - else PriorityEncoder(recoveryScanAllocated.asUInt) - val recoveryFirstAllocatedCandidate = Mux( - recoveryFirstAllocatedValid, - recoveryFirstAllocated, - recoveryScanGroups(recoverySliceFirstAllocatedIndex).pcBase) - val recoveryFirstAllocatedValidNext = recoveryFirstAllocatedValid || - recoverySliceHasAllocated - val recoveryFreedBasesNext = recoveryFreedBasesReg + - recoverySliceAllocatedCount - val recoverySliceAllocatedOrderExact = Wire(Vec( - p.pcRecoveryScanGroupsPerCycle, Bool())) - for (scanLane <- 0 until p.pcRecoveryScanGroupsPerCycle) { - val priorInSlice = if (scanLane == 0) 0.U else - PopCount(recoveryScanAllocated.take(scanLane)) - val allocationOrdinal = recoveryFreedBasesReg + priorInSlice - val expectedSum = localIndex(recoveryFirstAllocatedCandidate) +& - allocationOrdinal - val expectedWrap = expectedSum >= p.pcEntriesPerStid.U - val group = recoveryScanGroups(scanLane) - recoverySliceAllocatedOrderExact(scanLane) := - !recoveryScanAllocated(scanLane) || - (localIndex(group.pcBase) === - expectedSum(p.pcPartitionIndexWidth - 1, 0) && - group.pcBase.index === partitionBase(safeRecoveryStid) + - expectedSum(p.pcPartitionIndexWidth - 1, 0) && - group.pcBase.allocationEpoch === - recoveryFirstAllocatedCandidate.allocationEpoch + - expectedWrap.asUInt) + + private val freeChain = Wire(Vec(retireWidth + 1, Bool())) + private val freedLocal = Wire(Vec(retireWidth, UInt(localWidth.W))) + freeChain(0) := true.B + for (offset <- 0 until retireWidth) { + val sum = select(headLocal, commitStid) +& offset.U + val wraps = sum >= entriesPerStid.U + val local = sum(localWidth - 1, 0) + val row = rowAt(commitStid, local) + val liveAfter = row.liveRobGroups - commitHitsByLocal(local) + val closeAfter = row.closeCommitted || commitCloseByLocal(local) + val headExact = row.valid && + row.pcBufferIndex === partitionBase(commitStid) + local && + row.allocationEpoch === select(headEpoch, commitStid) + wraps.asUInt + freedLocal(offset) := local + freeChain(offset + 1) := freeChain(offset) && + offset.U < select(usedBases, commitStid) && + headExact && liveAfter === 0.U && row.closed && closeAfter } - val recoveryAllocatedOrderExactNext = - recoveryAllocatedOrderExactReg && - recoverySliceAllocatedOrderExact.asUInt.andR - val recoveryKilledRowsExactNext = recoveryKilledRowsExactReg && - recoveryScanRowsExact.asUInt.andR - - val recoveryHitCountsNext = Wire(Vec(p.pcEntriesPerStid, - UInt(p.nonFlushPrefixCountWidth.W))) - val recoveryPriorKeysNext = Wire(Vec(p.pcEntriesPerStid, - new RobGroupKey(p))) - val recoverySliceCloseOwnerKilled = Wire(Vec(p.pcEntriesPerStid, Bool())) - val recoverySliceFreedRows = Wire(Vec(p.pcEntriesPerStid, Bool())) - val recoveryPivotReopens = Wire(Vec(p.pcEntriesPerStid, Bool())) - val recoveryHitCountsLegal = Wire(Vec(p.pcEntriesPerStid, Bool())) - for (local <- 0 until p.pcEntriesPerStid) { - val row = rowAt(safeRecoveryStid, local.U) - val laneHits = VecInit((0 until p.pcRecoveryScanGroupsPerCycle).map { - scanLane => recoveryScanActive(scanLane) && - localIndex(recoveryScanGroups(scanLane).pcBase) === local.U && - recoveryScanGroups(scanLane).pcBase.allocationEpoch === - row.token.allocationEpoch - }) - val sliceHits = PopCount(laneHits) - recoveryHitCountsNext(local) := recoveryHitCounts(local) + sliceHits - val firstLane = if (p.pcRecoveryScanGroupsPerCycle == 1) 0.U - else PriorityEncoder(laneHits.asUInt) - val firstKilledKey = recoveryScanGroups(firstLane).key - val priorKey = Wire(new RobGroupKey(p)) - priorKey.valid := laneHits.asUInt.orR - priorKey.peId := firstKilledKey.peId - priorKey.stid := firstKilledKey.stid - priorKey.ridSlot := Mux(firstKilledKey.ridSlot === 0.U, - (p.robGroupsPerStid - 1).U, - firstKilledKey.ridSlot - 1.U) - priorKey.ridGeneration := Mux(firstKilledKey.ridSlot === 0.U, - firstKilledKey.ridGeneration - 1.U, - firstKilledKey.ridGeneration) - recoveryPriorKeysNext(local) := Mux( - recoveryHitCounts(local).orR, - recoveryPriorKeys(local), - priorKey) - recoverySliceCloseOwnerKilled(local) := row.closeOwnerValid && - (0 until p.pcRecoveryScanGroupsPerCycle).map { scanLane => - recoveryScanActive(scanLane) && - recoveryScanGroups(scanLane).key.asUInt === row.closeOwner.asUInt - }.reduce(_ || _) - recoverySliceFreedRows(local) := - (0 until p.pcRecoveryScanGroupsPerCycle).map { scanLane => - recoveryScanAllocated(scanLane) && - localIndex(recoveryScanGroups(scanLane).pcBase) === local.U && - recoveryScanGroups(scanLane).pcBase.allocationEpoch === - row.token.allocationEpoch - }.reduce(_ || _) - recoveryPivotReopens(local) := row.closeOwnerValid && - recoveryPlan.survivingPivotValid && - (recoveryPlan.pivot.releasePcBase || - recoveryPlan.pivot.preciseTrap) && - !(recoveryPlan.survivingPivot.releasePcBase || - recoveryPlan.survivingPivot.preciseTrap) && - recoveryPlan.pivot.key.asUInt === row.closeOwner.asUInt - recoveryHitCountsLegal(local) := - recoveryHitCountsNext(local) <= row.liveRobGroups + private val freedBases = PopCount(freeChain.tail) + + when(io.commitApply) { + assert(io.commitPreview.valid && io.commitReady, + "PC-buffer commit apply requires the exact common preview") } - val recoveryCloseOwnerKilledMaskNext = - recoveryCloseOwnerKilledMask | - recoverySliceCloseOwnerKilled.asUInt | recoveryPivotReopens.asUInt - val recoveryFreedRowMaskNext = recoveryFreedRowMask | - recoverySliceFreedRows.asUInt - val recoveryScanLast = recoveryScanCursor === - (p.pcRecoveryScanCycles - 1).U - - val recoveryTailEndSum = localIndex(recoveryFirstAllocatedCandidate) +& - recoveryFreedBasesNext - val recoveryTailEndWrap = recoveryTailEndSum >= p.pcEntriesPerStid.U - val recoveryTailSuffixExact = Mux( - recoveryFreedBasesNext.orR, - recoveryFirstAllocatedValidNext && recoveryAllocatedOrderExactNext && - recoverySnapshotTail.index === partitionBase(safeRecoveryStid) + - recoveryTailEndSum(p.pcPartitionIndexWidth - 1, 0) && - recoverySnapshotTail.allocationEpoch === - recoveryFirstAllocatedCandidate.allocationEpoch + - recoveryTailEndWrap.asUInt && - recoverySnapshotUsedBases >= recoveryFreedBasesNext, - true.B) - val recoveryTailAfter = Mux( - recoveryFreedBasesNext.orR, - recoveryFirstAllocatedCandidate, - recoverySnapshotTail) - val recoveryFirstKilled = recoveryPlan.killedGroups(0) - val recoveryCurrentAfterValid = Mux( - recoveryPlan.survivingTailValid, - !(recoveryPlan.survivingTail.releasePcBase || - recoveryPlan.survivingTail.preciseTrap), - Mux(recoveryFirstKilled.pcBaseAllocated, - recoveryFirstKilled.pcImplicitCloseValid, - true.B)) - val recoveryCurrentAfter = Mux( - recoveryPlan.survivingTailValid, - recoveryPlan.survivingTail.pcBase, - Mux(recoveryFirstKilled.pcBaseAllocated, - recoveryFirstKilled.pcImplicitClose, - recoveryFirstKilled.pcBase)) - val recoveryCurrentRow = rowAt(safeRecoveryStid, - localIndex(recoveryCurrentAfter)) - val recoveryCurrentAfterExact = !recoveryCurrentAfterValid || - (recoveryCurrentAfter.valid && recoveryCurrentRow.valid && - recoveryCurrentRow.stid === recoveryStid && - recoveryCurrentRow.token.asUInt === recoveryCurrentAfter.asUInt) - val recoveryCurrentBaseAfter = Mux( - recoveryCurrentAfterValid, - recoveryCurrentRow.base, - 0.U) - val recoveryScanExact = recoveryKilledRowsExactNext && - recoveryAllocatedOrderExactNext && recoveryTailSuffixExact && - recoveryCurrentAfterExact && recoveryHitCountsLegal.asUInt.andR - val recoveryScanRejected = - recoveryScanState === OooPcRecoveryScanState.Scan && - recoveryScanLast && !recoveryScanExact - - io.recoveryPrepareReady := - recoveryScanState === OooPcRecoveryScanState.Prepared && - recoveryOfferExact && retainedRecoveryPrepared.valid && - !recoveryCommitConflict - io.recoveryPrepared := retainedRecoveryPrepared - io.recoveryPrepared.valid := io.recoveryPrepareReady - io.recoveryRejected.valid := recoveryCaptureMalformed || - recoveryOfferChanged || recoveryScanRejected || - (recoveryScanState === OooPcRecoveryScanState.Rejected && - io.recoveryPrepare.valid) - io.recoveryRejected.bits := retainedRecoveryReject - when(recoveryCaptureMalformed) { - io.recoveryRejected.bits.requested := io.recoveryPrepare.bits - io.recoveryRejected.bits.liveTail.valid := true.B - io.recoveryRejected.bits.liveTail.index := - partitionBase(safeRecoveryStid) + tailLocal(safeRecoveryStid) - io.recoveryRejected.bits.liveTail.byteOffset := 0.U - io.recoveryRejected.bits.liveTail.allocationEpoch := - tailEpoch(safeRecoveryStid) - io.recoveryRejected.bits.usedBases := usedBases(safeRecoveryStid) - io.recoveryRejected.bits.killedRowsExact := false.B - io.recoveryRejected.bits.tailSuffixExact := false.B - io.recoveryRejected.bits.currentAfterExact := false.B - }.elsewhen(recoveryOfferChanged) { - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.liveTail := recoverySnapshotTail - io.recoveryRejected.bits.usedBases := recoverySnapshotUsedBases - io.recoveryRejected.bits.killedRowsExact := false.B - io.recoveryRejected.bits.tailSuffixExact := false.B - io.recoveryRejected.bits.currentAfterExact := false.B - }.elsewhen(recoveryScanRejected) { - io.recoveryRejected.bits.requested := recoveryPlan - io.recoveryRejected.bits.liveTail := recoverySnapshotTail - io.recoveryRejected.bits.usedBases := recoverySnapshotUsedBases - io.recoveryRejected.bits.killedRowsExact := recoveryKilledRowsExactNext - io.recoveryRejected.bits.tailSuffixExact := recoveryTailSuffixExact - io.recoveryRejected.bits.currentAfterExact := recoveryCurrentAfterExact + + // Recovery scans the target partition in allocation order. It retains row + // repair masks and echoes the canonical plan without projecting identity. + private val recoveryCursor = RegInit(0.U(scanCursorWidth.W)) + private val recoverySnapshotUsed = RegInit(0.U(usedWidth.W)) + private val recoverySnapshotHeadLocal = RegInit(0.U(localWidth.W)) + private val recoverySnapshotHeadEpoch = RegInit( + 0.U(p.ooo.pcAllocationEpochWidth.W)) + private val recoverySnapshotTailLocal = RegInit(0.U(localWidth.W)) + private val recoverySnapshotTailEpoch = RegInit( + 0.U(p.ooo.pcAllocationEpochWidth.W)) + private val recoveryFreeMask = RegInit(0.U(entriesPerStid.W)) + private val recoveryRepairMask = RegInit(0.U(entriesPerStid.W)) + private val recoveryReopenMask = RegInit(0.U(entriesPerStid.W)) + private val recoveryRepairLive = RegInit(VecInit(Seq.fill(entriesPerStid)( + 0.U(liveWidth.W)))) + private val recoveryExact = RegInit(true.B) + private val recoverySeenSuffix = RegInit(false.B) + private val recoveryFirstEndpoint = RegInit(false.B) + private val recoveryLastEndpoint = RegInit(false.B) + private val recoveryKilledGroups = RegInit(0.U(liveWidth.W)) + private val recoveryFreedBases = RegInit(0.U(usedWidth.W)) + private val recoveryFirstFreedValid = RegInit(false.B) + private val recoveryFirstFreedIndex = RegInit(0.U(indexWidth.W)) + private val recoveryFirstFreedEpoch = RegInit( + 0.U(p.ooo.pcAllocationEpochWidth.W)) + private val recoveryLastSurvivorValid = RegInit(false.B) + private val recoveryLastSurvivorIndex = RegInit(0.U(indexWidth.W)) + private val recoveryLastSurvivorEpoch = RegInit( + 0.U(p.ooo.pcAllocationEpochWidth.W)) + private val recoveryLastSurvivorBase = RegInit(0.U(p.pcWidth.W)) + private val recoveryLastSurvivorOpen = RegInit(false.B) + + private val recoveryOfferLegal = + io.recovery.prepare.bits.phase === RecoveryPhase.Prepare && + io.recovery.prepare.bits.trigger.stid < p.ooo.stidCount.U && + RecoveryPlanContract.legalSuffixWindow(io.recovery.prepare.bits) + io.recovery.prepare.ready := recoveryState === PcBufferRecoveryState.Idle && + recoveryOfferLegal + io.recovery.prepared.valid := recoveryState === PcBufferRecoveryState.Prepared + io.recovery.prepared.bits := recoveryPlan + + private val scanExactChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanSeenChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanFirstEndpointChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanLastEndpointChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanKilledGroupsChain = Wire(Vec(scanWidth + 1, UInt(liveWidth.W))) + private val scanFreedBasesChain = Wire(Vec(scanWidth + 1, UInt(usedWidth.W))) + private val scanFirstFreedValidChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanFirstFreedIndexChain = Wire(Vec(scanWidth + 1, + UInt(indexWidth.W))) + private val scanFirstFreedEpochChain = Wire(Vec(scanWidth + 1, + UInt(p.ooo.pcAllocationEpochWidth.W))) + private val scanLastSurvivorValidChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanLastSurvivorIndexChain = Wire(Vec(scanWidth + 1, + UInt(indexWidth.W))) + private val scanLastSurvivorEpochChain = Wire(Vec(scanWidth + 1, + UInt(p.ooo.pcAllocationEpochWidth.W))) + private val scanLastSurvivorBaseChain = Wire(Vec(scanWidth + 1, + UInt(p.pcWidth.W))) + private val scanLastSurvivorOpenChain = Wire(Vec(scanWidth + 1, Bool())) + private val scanFree = Wire(Vec(scanWidth, Bool())) + private val scanRepair = Wire(Vec(scanWidth, Bool())) + private val scanReopen = Wire(Vec(scanWidth, Bool())) + private val scanLocal = Wire(Vec(scanWidth, UInt(localWidth.W))) + private val scanRepairLive = Wire(Vec(scanWidth, UInt(liveWidth.W))) + + scanExactChain(0) := recoveryExact + scanSeenChain(0) := recoverySeenSuffix + scanFirstEndpointChain(0) := recoveryFirstEndpoint + scanLastEndpointChain(0) := recoveryLastEndpoint + scanKilledGroupsChain(0) := recoveryKilledGroups + scanFreedBasesChain(0) := recoveryFreedBases + scanFirstFreedValidChain(0) := recoveryFirstFreedValid + scanFirstFreedIndexChain(0) := recoveryFirstFreedIndex + scanFirstFreedEpochChain(0) := recoveryFirstFreedEpoch + scanLastSurvivorValidChain(0) := recoveryLastSurvivorValid + scanLastSurvivorIndexChain(0) := recoveryLastSurvivorIndex + scanLastSurvivorEpochChain(0) := recoveryLastSurvivorEpoch + scanLastSurvivorBaseChain(0) := recoveryLastSurvivorBase + scanLastSurvivorOpenChain(0) := recoveryLastSurvivorOpen + + for (lane <- 0 until scanWidth) { + val position = recoveryCursor +& lane.U + val active = position < recoverySnapshotUsed + val localSum = recoverySnapshotHeadLocal +& position + val wraps = localSum >= entriesPerStid.U + val local = localSum(localWidth - 1, 0) + val row = rowAt(recoveryTargetStid, local) + val liveFirst = Wire(new RobIdentity(p)) + liveFirst := row.firstRob + liveFirst.peId := row.nextCommitPeId + liveFirst.stid := row.nextCommitStid + liveFirst.ridSlot := row.nextCommitRidSlot + liveFirst.ridGeneration := row.nextCommitRidGeneration + liveFirst.memberIndex := 0.U + val rowExact = !active || (row.valid && + row.stid === recoveryTargetStid && + row.pcBufferIndex === partitionBase(recoveryTargetStid) + local && + row.allocationEpoch === recoverySnapshotHeadEpoch + wraps.asUInt && + row.nextCommitValid && row.liveRobGroups =/= 0.U && + liveFirst.peId === recoveryPlan.trigger.peId && + liveFirst.stid === recoveryPlan.trigger.stid && + row.lastRob.peId === recoveryPlan.trigger.peId && + row.lastRob.stid === recoveryPlan.trigger.stid) + val firstKilled = active && recoveryPlan.firstKilledValid && + RecoveryPlanContract.suffixMember(recoveryPlan, liveFirst) + val lastKilled = active && recoveryPlan.firstKilledValid && + RecoveryPlanContract.suffixMember(recoveryPlan, row.lastRob) + val straddles = !firstKilled && lastKilled + val liveFirstOrdinal = groupOrdinal(liveFirst) + val killedOrdinal = groupOrdinal(recoveryPlan.firstKilled) + val groupsBeforeKilled = killedOrdinal - liveFirstOrdinal + val keepsPartialGroup = recoveryPlan.firstKilled.memberIndex =/= 0.U + val survivorsWide = groupsBeforeKilled + keepsPartialGroup.asUInt + val survivors = Mux(straddles, + survivorsWide(liveWidth - 1, 0), row.liveRobGroups) + val survivorsExact = !straddles || + (survivors =/= 0.U && survivors <= row.liveRobGroups) + val free = firstKilled + val repair = straddles + val closeKilled = active && row.closeOwnerValid && + RecoveryPlanContract.suffixMember(recoveryPlan, row.closeOwner) + val suffixOrderExact = !active || !scanSeenChain(lane) || firstKilled + val firstEndpoint = recoveryPlan.firstKilledValid && ( + (firstKilled && liveFirst.asUInt === recoveryPlan.firstKilled.asUInt) || + (straddles && + groupOrdinal(recoveryPlan.firstKilled) >= liveFirstOrdinal && + groupOrdinal(recoveryPlan.firstKilled) <= groupOrdinal(row.lastRob))) + val lastEndpoint = lastKilled && + row.lastRob.asUInt === recoveryPlan.lastKilled.asUInt + val removedGroups = Mux(free, row.liveRobGroups, + Mux(repair, + row.liveRobGroups - survivors + keepsPartialGroup.asUInt, 0.U)) + val retained = active && !free + val openAfter = !row.closed || closeKilled + + scanLocal(lane) := local + scanFree(lane) := free + scanRepair(lane) := repair + scanReopen(lane) := retained && closeKilled + scanRepairLive(lane) := survivors + scanExactChain(lane + 1) := scanExactChain(lane) && rowExact && + survivorsExact && suffixOrderExact + scanSeenChain(lane + 1) := scanSeenChain(lane) || lastKilled + scanFirstEndpointChain(lane + 1) := scanFirstEndpointChain(lane) || + firstEndpoint + scanLastEndpointChain(lane + 1) := scanLastEndpointChain(lane) || + lastEndpoint + scanKilledGroupsChain(lane + 1) := scanKilledGroupsChain(lane) + + removedGroups + scanFreedBasesChain(lane + 1) := scanFreedBasesChain(lane) + free.asUInt + scanFirstFreedValidChain(lane + 1) := + scanFirstFreedValidChain(lane) || free + scanFirstFreedIndexChain(lane + 1) := Mux( + free && !scanFirstFreedValidChain(lane), row.pcBufferIndex, + scanFirstFreedIndexChain(lane)) + scanFirstFreedEpochChain(lane + 1) := Mux( + free && !scanFirstFreedValidChain(lane), row.allocationEpoch, + scanFirstFreedEpochChain(lane)) + scanLastSurvivorValidChain(lane + 1) := + scanLastSurvivorValidChain(lane) || retained + scanLastSurvivorIndexChain(lane + 1) := Mux(retained, + row.pcBufferIndex, scanLastSurvivorIndexChain(lane)) + scanLastSurvivorEpochChain(lane + 1) := Mux(retained, + row.allocationEpoch, scanLastSurvivorEpochChain(lane)) + scanLastSurvivorBaseChain(lane + 1) := Mux(retained, + row.pcBase, scanLastSurvivorBaseChain(lane)) + scanLastSurvivorOpenChain(lane + 1) := Mux(retained, + openAfter, scanLastSurvivorOpenChain(lane)) } - when(recoveryScanState === OooPcRecoveryScanState.Idle && - io.recoveryPrepare.valid && recoveryCaptureShapeExact && - !recoveryCommitConflict) { - retainedRecoveryPlan := io.recoveryPrepare.bits - retainedRecoveryPrepared := - 0.U.asTypeOf(retainedRecoveryPrepared) - retainedRecoveryReject := 0.U.asTypeOf(retainedRecoveryReject) - recoveryScanCursor := 0.U - recoveryHitCounts.foreach(_ := 0.U) - recoveryPriorKeys.foreach(_ := 0.U.asTypeOf(new RobGroupKey(p))) - recoveryCloseOwnerKilledMask := 0.U - recoveryFreedRowMask := 0.U - recoveryFreedBasesReg := 0.U - recoveryFirstAllocatedValid := false.B - recoveryFirstAllocated := 0.U.asTypeOf(recoveryFirstAllocated) - recoveryKilledRowsExactReg := true.B - recoveryAllocatedOrderExactReg := true.B - recoverySnapshotUsedBases := usedBases(safeRecoveryStid) - recoverySnapshotTail.valid := true.B - recoverySnapshotTail.index := partitionBase(safeRecoveryStid) + - tailLocal(safeRecoveryStid) - recoverySnapshotTail.byteOffset := 0.U - recoverySnapshotTail.allocationEpoch := tailEpoch(safeRecoveryStid) - recoveryScanState := OooPcRecoveryScanState.Scan - }.elsewhen(recoveryScanState =/= OooPcRecoveryScanState.Idle && - !io.recoveryPrepare.valid) { - recoveryScanState := OooPcRecoveryScanState.Idle - }.elsewhen(recoveryOfferChanged) { - retainedRecoveryReject.requested := recoveryPlan - retainedRecoveryReject.liveTail := recoverySnapshotTail - retainedRecoveryReject.usedBases := recoverySnapshotUsedBases - retainedRecoveryReject.killedRowsExact := false.B - retainedRecoveryReject.tailSuffixExact := false.B - retainedRecoveryReject.currentAfterExact := false.B - recoveryScanState := OooPcRecoveryScanState.Rejected - }.elsewhen(recoveryScanState === OooPcRecoveryScanState.Scan) { - recoveryHitCounts := recoveryHitCountsNext - recoveryPriorKeys := recoveryPriorKeysNext - recoveryCloseOwnerKilledMask := recoveryCloseOwnerKilledMaskNext - recoveryFreedRowMask := recoveryFreedRowMaskNext - recoveryFreedBasesReg := recoveryFreedBasesNext - recoveryFirstAllocatedValid := recoveryFirstAllocatedValidNext - when(!recoveryFirstAllocatedValid && recoverySliceHasAllocated) { - recoveryFirstAllocated := recoveryFirstAllocatedCandidate - } - recoveryKilledRowsExactReg := recoveryKilledRowsExactNext - recoveryAllocatedOrderExactReg := recoveryAllocatedOrderExactNext - when(recoveryScanLast) { - when(recoveryScanExact) { - retainedRecoveryPrepared.valid := true.B - retainedRecoveryPrepared.stid := recoveryStid - retainedRecoveryPrepared.freedBases := recoveryFreedBasesNext.pad( - math.max(p.nonFlushPrefixCountWidth, p.pcPartitionCountWidth))( - p.pcPartitionCountWidth - 1, 0) - retainedRecoveryPrepared.tailAfter := recoveryTailAfter - retainedRecoveryPrepared.currentAfterValid := - recoveryCurrentAfterValid - retainedRecoveryPrepared.currentAfter := recoveryCurrentAfter - retainedRecoveryPrepared.currentBaseAfter := - recoveryCurrentBaseAfter - recoveryScanState := OooPcRecoveryScanState.Prepared - }.otherwise { - retainedRecoveryReject.requested := recoveryPlan - retainedRecoveryReject.liveTail := recoverySnapshotTail - retainedRecoveryReject.usedBases := recoverySnapshotUsedBases - retainedRecoveryReject.killedRowsExact := - recoveryKilledRowsExactNext - retainedRecoveryReject.tailSuffixExact := recoveryTailSuffixExact - retainedRecoveryReject.currentAfterExact := - recoveryCurrentAfterExact - recoveryScanState := OooPcRecoveryScanState.Rejected + private val recoveryScanDone = recoveryCursor + scanWidth.U >= + recoverySnapshotUsed + private val recoveryFinalExact = scanExactChain.last && + scanFirstEndpointChain.last === recoveryPlan.firstKilledValid && + scanLastEndpointChain.last === recoveryPlan.firstKilledValid && + scanKilledGroupsChain.last === recoveryPlan.killedGroupCount + private val scanFreeMask = (0 until scanWidth).map { lane => + Mux(scanFree(lane), (1.U(entriesPerStid.W) << scanLocal(lane)), 0.U) + }.reduce(_ | _) + private val scanRepairMask = (0 until scanWidth).map { lane => + Mux(scanRepair(lane), (1.U(entriesPerStid.W) << scanLocal(lane)), 0.U) + }.reduce(_ | _) + private val scanReopenMask = (0 until scanWidth).map { lane => + Mux(scanReopen(lane), (1.U(entriesPerStid.W) << scanLocal(lane)), 0.U) + }.reduce(_ | _) + + when(io.recovery.prepare.fire) { + val stid = io.recovery.prepare.bits.trigger.stid + recoveryPlan := io.recovery.prepare.bits + recoveryCursor := 0.U + recoverySnapshotUsed := select(usedBases, stid) + recoverySnapshotHeadLocal := select(headLocal, stid) + recoverySnapshotHeadEpoch := select(headEpoch, stid) + recoverySnapshotTailLocal := select(tailLocal, stid) + recoverySnapshotTailEpoch := select(tailEpoch, stid) + recoveryFreeMask := 0.U + recoveryRepairMask := 0.U + recoveryReopenMask := 0.U + recoveryRepairLive.foreach(_ := 0.U) + recoveryExact := true.B + recoverySeenSuffix := false.B + recoveryFirstEndpoint := false.B + recoveryLastEndpoint := false.B + recoveryKilledGroups := 0.U + recoveryFreedBases := 0.U + recoveryFirstFreedValid := false.B + recoveryFirstFreedIndex := 0.U + recoveryFirstFreedEpoch := 0.U + recoveryLastSurvivorValid := false.B + recoveryLastSurvivorIndex := 0.U + recoveryLastSurvivorEpoch := 0.U + recoveryLastSurvivorBase := 0.U + recoveryLastSurvivorOpen := false.B + recoveryState := PcBufferRecoveryState.Scan + }.elsewhen(recoveryState === PcBufferRecoveryState.Scan) { + recoveryExact := scanExactChain.last + recoverySeenSuffix := scanSeenChain.last + recoveryFirstEndpoint := scanFirstEndpointChain.last + recoveryLastEndpoint := scanLastEndpointChain.last + recoveryKilledGroups := scanKilledGroupsChain.last + recoveryFreedBases := scanFreedBasesChain.last + recoveryFirstFreedValid := scanFirstFreedValidChain.last + recoveryFirstFreedIndex := scanFirstFreedIndexChain.last + recoveryFirstFreedEpoch := scanFirstFreedEpochChain.last + recoveryLastSurvivorValid := scanLastSurvivorValidChain.last + recoveryLastSurvivorIndex := scanLastSurvivorIndexChain.last + recoveryLastSurvivorEpoch := scanLastSurvivorEpochChain.last + recoveryLastSurvivorBase := scanLastSurvivorBaseChain.last + recoveryLastSurvivorOpen := scanLastSurvivorOpenChain.last + recoveryFreeMask := recoveryFreeMask | scanFreeMask + recoveryRepairMask := recoveryRepairMask | scanRepairMask + recoveryReopenMask := recoveryReopenMask | scanReopenMask + for (lane <- 0 until scanWidth) { + when(scanRepair(lane)) { + recoveryRepairLive(scanLocal(lane)) := scanRepairLive(lane) } + } + when(recoveryScanDone) { + recoveryState := Mux(recoveryFinalExact, + PcBufferRecoveryState.Prepared, PcBufferRecoveryState.Rejected) }.otherwise { - recoveryScanCursor := recoveryScanCursor + 1.U + recoveryCursor := recoveryCursor + scanWidth.U } - }.elsewhen(recoveryScanState === OooPcRecoveryScanState.Prepared && - io.recoveryFire) { - recoveryScanState := OooPcRecoveryScanState.Idle } - io.commit.ready := commitExact && - !(recoveryTargetsStid && commitStid === recoveryStid) - val commitFire = io.commit.valid && io.commit.ready - exactCommitConflict := io.commit.valid && commitExact && prepareStidInRange && - commitStid === prepareStid - io.commitRejected.valid := io.commit.valid && !io.commit.ready - io.commitRejected.bits.requested := io.commit.bits - io.commitRejected.bits.head := headToken - - val publishFire = io.publishFire && io.prepare.valid && io.prepareReady - when(io.publishFire) { - assert(io.prepare.valid && io.prepareReady, - "PC-buffer publish must use the exact accepted prepare view") + + private val recoveryApply = recoveryState === PcBufferRecoveryState.Prepared && + io.recovery.apply.valid && + io.recovery.apply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.apply.bits, recoveryPlan) + private val recoveryAbort = + (recoveryState === PcBufferRecoveryState.Prepared || + recoveryState === PcBufferRecoveryState.Rejected) && + io.recovery.abort.valid && + io.recovery.abort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recovery.abort.bits, recoveryPlan) + when(io.recovery.apply.valid) { + assert(recoveryApply, + "PC-buffer recovery apply must match the retained canonical plan") + } + when(io.recovery.abort.valid) { + assert(recoveryAbort, + "PC-buffer recovery abort must match the retained canonical plan") + } + when(recoveryApply || recoveryAbort) { + recoveryState := PcBufferRecoveryState.Idle } - for (stid <- 0 until p.stidCount) { + // Common pointer mutations. Same-STID publication and commit are mutually + // excluded; recovery fences only its target partition. + for (stid <- 0 until p.ooo.stidCount) { val publishHere = publishFire && prepareStid === stid.U - val commitHere = commitFire && commitStid === stid.U + val commitHere = io.commitApply && io.commitReady && commitStid === stid.U + val recoveryHere = recoveryApply && recoveryTargetStid === stid.U when(publishHere) { val sum = tailLocal(stid) +& allocatedBases - val wrap = sum >= p.pcEntriesPerStid.U + val wraps = sum >= entriesPerStid.U usedBases(stid) := usedBases(stid) + allocatedBases - tailLocal(stid) := sum(p.pcPartitionIndexWidth - 1, 0) - tailEpoch(stid) := tailEpoch(stid) + wrap.asUInt - currentValid(stid) := io.prepared.currentAfterValid - currentToken(stid) := io.prepared.currentAfter - currentBase(stid) := scanBase.last + tailLocal(stid) := sum(localWidth - 1, 0) + tailEpoch(stid) := tailEpoch(stid) + wraps.asUInt + currentValid(stid) := acceptedScanValid + currentIndex(stid) := acceptedScanIndex + currentEpoch(stid) := acceptedScanEpoch + currentBase(stid) := acceptedScanBase } when(commitHere) { val sum = headLocal(stid) +& freedBases - val wrap = sum >= p.pcEntriesPerStid.U + val wraps = sum >= entriesPerStid.U usedBases(stid) := usedBases(stid) - freedBases - headLocal(stid) := sum(p.pcPartitionIndexWidth - 1, 0) - headEpoch(stid) := headEpoch(stid) + wrap.asUInt + headLocal(stid) := sum(localWidth - 1, 0) + headEpoch(stid) := headEpoch(stid) + wraps.asUInt + } + when(recoveryHere) { + usedBases(stid) := usedBases(stid) - recoveryFreedBases + when(recoveryFirstFreedValid) { + tailLocal(stid) := localFromIndex(recoveryFirstFreedIndex) + tailEpoch(stid) := recoveryFirstFreedEpoch + }.otherwise { + tailLocal(stid) := recoverySnapshotTailLocal + tailEpoch(stid) := recoverySnapshotTailEpoch + } + currentValid(stid) := recoveryLastSurvivorValid && + recoveryLastSurvivorOpen + currentIndex(stid) := recoveryLastSurvivorIndex + currentEpoch(stid) := recoveryLastSurvivorEpoch + currentBase(stid) := recoveryLastSurvivorBase } } - for (stid <- 0 until p.stidCount; local <- 0 until p.pcEntriesPerStid) { + // Banked metadata and the three exact read replicas share every mutation. + for (stid <- 0 until p.ooo.stidCount; local <- 0 until entriesPerStid) { val row = rowAt(stid.U, local.U) val publishHere = publishFire && prepareStid === stid.U - val matching = VecInit((0 until p.instructionDecodeWidth).map { groupIndex => - groupIndex.U < groupCount && localIndex(groupTokens(groupIndex)) === local.U && - (newBase(groupIndex) || groupTokens(groupIndex).allocationEpoch === - row.token.allocationEpoch) + val matchingGroups = VecInit((0 until d3Width).map { group => + group.U < acceptedGroupCount && + localFromIndex(groupIndex(group)) === local.U && + groupEpoch(group) === Mux(groupNewBase(group), + groupEpoch(group), row.allocationEpoch) }) - val groupHits = PopCount(matching) - val newHit = (0 until p.instructionDecodeWidth).map { groupIndex => - matching(groupIndex) && newBase(groupIndex) + val groupHits = PopCount(matchingGroups) + val newHit = (0 until d3Width).map { group => + matchingGroups(group) && groupNewBase(group) + }.reduce(_ || _) + val firstGroup = PriorityEncoder(matchingGroups.asUInt) + val lastGroup = Wire(UInt(InterfaceWidth.index(d3Width).W)) + lastGroup := firstGroup + for (group <- 0 until d3Width) { + when(matchingGroups(group)) { lastGroup := group.U } + } + val explicitClose = (0 until d3Width).map { group => + matchingGroups(group) && + (groupBlockStop(group) || groupTrap(group)) }.reduce(_ || _) - val closeHit = (0 until p.instructionDecodeWidth).map { groupIndex => - (matching(groupIndex) && - (io.prepare.bits.transaction.groups(groupIndex).releasePcBase || - io.prepare.bits.transaction.groups(groupIndex).preciseTrap)) || - (implicitClose(groupIndex) && - localIndex(implicitCloseTokens(groupIndex)) === local.U && - implicitCloseTokens(groupIndex).allocationEpoch === - row.token.allocationEpoch) + val implicitClose = (0 until d3Width).map { group => + group.U < acceptedGroupCount && groupImplicitClose(group) && + localFromIndex(groupImplicitCloseIndex(group)) === local.U && + groupImplicitCloseEpoch(group) === row.allocationEpoch }.reduce(_ || _) - val closeOwner = Wire(new RobGroupKey(p)) - val lastGroup = Wire(new RobGroupKey(p)) + val closeOwner = Wire(new RobIdentity(p)) closeOwner := 0.U.asTypeOf(closeOwner) - lastGroup := 0.U.asTypeOf(lastGroup) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - when(matching(groupIndex)) { - lastGroup := io.prepare.bits.transaction.groups(groupIndex).key + for (group <- 0 until d3Width) { + when(matchingGroups(group) && + (groupBlockStop(group) || groupTrap(group))) { + closeOwner := boundGroupLastRob(group) } - when((matching(groupIndex) && - (io.prepare.bits.transaction.groups(groupIndex).releasePcBase || - io.prepare.bits.transaction.groups(groupIndex).preciseTrap)) || - (implicitClose(groupIndex) && - localIndex(implicitCloseTokens(groupIndex)) === local.U && - implicitCloseTokens(groupIndex).allocationEpoch === - row.token.allocationEpoch)) { - closeOwner := io.prepare.bits.transaction.groups(groupIndex).key + when(group.U < acceptedGroupCount && groupImplicitClose(group) && + localFromIndex(groupImplicitCloseIndex(group)) === local.U && + groupImplicitCloseEpoch(group) === row.allocationEpoch) { + closeOwner := boundGroupFirstRob(group) } } - val firstIndex = PriorityEncoder(matching.asUInt) - val retireHits = Mux(commitStid === stid.U, hitsByLocal(local), 0.U) - val commitHere = commitFire && commitStid === stid.U - val closeOwnerCommits = (0 until p.retireGroupWidth).map { groupIndex => - groupIndex.U < commitCount && row.closeOwnerValid && - io.commit.bits.groups(groupIndex).key.asUInt === row.closeOwner.asUInt - }.reduce(_ || _) - val lastRetired = Wire(new RobGroupKey(p)) - lastRetired := 0.U.asTypeOf(lastRetired) - for (groupIndex <- 0 until p.retireGroupWidth) { - when(groupIndex.U < commitCount && - localIndex(io.commit.bits.groups(groupIndex).pcBase) === local.U && - io.commit.bits.groups(groupIndex).pcBase.allocationEpoch === - row.token.allocationEpoch) { - lastRetired := io.commit.bits.groups(groupIndex).key - } - } - val freedHere = (0 until p.retireGroupWidth).map { offset => - val sum = headLocal(stid) +& offset.U - val wrap = sum >= p.pcEntriesPerStid.U - offset.U < freedBases && sum(p.pcPartitionIndexWidth - 1, 0) === local.U && - row.token.allocationEpoch === headEpoch(stid) + wrap.asUInt + + val commitHere = io.commitApply && io.commitReady && commitStid === stid.U + val commitHits = commitHitsByLocal(local) + val commitClose = commitCloseByLocal(local) + val freedHere = (0 until retireWidth).map { offset => + freeChain(offset + 1) && freedLocal(offset) === local.U }.reduce(_ || _) + val recoveryHere = recoveryApply && recoveryTargetStid === stid.U when(publishHere && groupHits.orR) { when(newHit) { row.valid := true.B row.stid := stid.U - row.token := groupTokens(firstIndex) - row.base := groupBases(firstIndex) - row.firstRobGroup := - io.prepare.bits.transaction.groups(firstIndex).key - row.nextCommitRobGroup := - io.prepare.bits.transaction.groups(firstIndex).key + row.pcBufferIndex := groupIndex(firstGroup) + row.allocationEpoch := groupEpoch(firstGroup) + row.pcBase := groupBase(firstGroup) + row.firstRob := boundGroupFirstRob(firstGroup) + row.nextCommitValid := true.B + row.nextCommitPeId := boundGroupFirstRob(firstGroup).peId + row.nextCommitStid := boundGroupFirstRob(firstGroup).stid + row.nextCommitRidSlot := boundGroupFirstRob(firstGroup).ridSlot + row.nextCommitRidGeneration := boundGroupFirstRob(firstGroup).ridGeneration row.liveRobGroups := groupHits - for (replica <- 0 until p.pcReadReplicaCount) { + row.closed := explicitClose + row.closeOwnerValid := explicitClose + row.closeCommitted := false.B + for (replica <- 0 until p.ooo.pcReadReplicaCount) { val readRow = readRowAt(replica, stid.U, local.U) readRow.valid := true.B readRow.stid := stid.U - readRow.index := groupTokens(firstIndex).index - readRow.allocationEpoch := - groupTokens(firstIndex).allocationEpoch - readRow.base := groupBases(firstIndex) + readRow.pcBufferIndex := groupIndex(firstGroup) + readRow.allocationEpoch := groupEpoch(firstGroup) + readRow.pcBase := groupBase(firstGroup) } }.otherwise { row.liveRobGroups := row.liveRobGroups + groupHits } - row.lastRobGroup := lastGroup - row.closed := Mux(newHit, closeHit, row.closed || closeHit) - when(closeHit) { + row.lastRob := boundGroupLastRob(lastGroup) + when(explicitClose) { + row.closed := true.B row.closeOwnerValid := true.B row.closeOwner := closeOwner row.closeCommitted := false.B } - }.elsewhen(publishHere && closeHit) { + } + when(publishHere && implicitClose) { row.closed := true.B row.closeOwnerValid := true.B row.closeOwner := closeOwner row.closeCommitted := false.B } - when(commitHere && retireHits.orR) { - val sum = lastRetired.ridSlot +& 1.U - val wrap = sum >= p.robGroupsPerStid.U - row.liveRobGroups := row.liveRobGroups - retireHits - row.nextCommitRobGroup.valid := true.B - row.nextCommitRobGroup.peId := lastRetired.peId - row.nextCommitRobGroup.stid := lastRetired.stid - row.nextCommitRobGroup.ridSlot := sum(p.ridSlotWidth - 1, 0) - row.nextCommitRobGroup.ridGeneration := - lastRetired.ridGeneration + wrap.asUInt - } - when(commitHere && closeOwnerCommits) { - row.closeCommitted := true.B + when(commitHere && commitHits.orR) { + row.liveRobGroups := row.liveRobGroups - commitHits + val last = commitLastRobByLocal(local) + val sum = last.ridSlot +& 1.U + val wraps = sum >= p.ooo.robGroupsPerStid.U + row.nextCommitPeId := last.peId + row.nextCommitStid := last.stid + row.nextCommitRidSlot := Mux(wraps, 0.U(p.ooo.ridSlotWidth.W), + sum(p.ooo.ridSlotWidth - 1, 0)) + row.nextCommitRidGeneration := last.ridGeneration + wraps.asUInt } + when(commitHere && commitClose) { row.closeCommitted := true.B } when(commitHere && freedHere) { - row := 0.U.asTypeOf(new OooPcBaseEntry(p)) - for (replica <- 0 until p.pcReadReplicaCount) { - readRowAt(replica, stid.U, local.U) := - 0.U.asTypeOf(new OooPcReadEntry(p)) + row.valid := false.B + row.closed := false.B + row.closeOwnerValid := false.B + row.closeCommitted := false.B + for (replica <- 0 until p.ooo.pcReadReplicaCount) { + readRowAt(replica, stid.U, local.U).valid := false.B } } - } - - val recoveryApply = io.recoveryFire && io.recoveryPrepareReady - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady && - io.recoveryPrepared.valid, - "PC recovery fire requires the same exact prepared suffix") - } - when(recoveryApply) { - usedBases(safeRecoveryStid) := - usedBases(safeRecoveryStid) - retainedRecoveryPrepared.freedBases - tailLocal(safeRecoveryStid) := - localIndex(retainedRecoveryPrepared.tailAfter) - tailEpoch(safeRecoveryStid) := - retainedRecoveryPrepared.tailAfter.allocationEpoch - currentValid(safeRecoveryStid) := - retainedRecoveryPrepared.currentAfterValid - currentToken(safeRecoveryStid) := Mux( - retainedRecoveryPrepared.currentAfterValid, - retainedRecoveryPrepared.currentAfter, - 0.U.asTypeOf(new PcBufferToken(p))) - currentBase(safeRecoveryStid) := - retainedRecoveryPrepared.currentBaseAfter - } - for (local <- 0 until p.pcEntriesPerStid) { - val row = rowAt(safeRecoveryStid, local.U) - val closeOwnerKilled = recoveryCloseOwnerKilledMask(local) - val freedHere = recoveryFreedRowMask(local) - when(recoveryApply && recoveryHitCounts(local).orR) { - row.liveRobGroups := row.liveRobGroups - recoveryHitCounts(local) - row.lastRobGroup := recoveryPriorKeys(local) + when(recoveryHere && recoveryRepairMask(local)) { + row.liveRobGroups := recoveryRepairLive(local) + row.lastRob := recoveryPlan.survivingTail } - when(recoveryApply && closeOwnerKilled && !freedHere) { + when(recoveryHere && recoveryReopenMask(local)) { row.closed := false.B row.closeOwnerValid := false.B - row.closeOwner := - 0.U.asTypeOf(new RobGroupKey(p)) row.closeCommitted := false.B } - when(recoveryApply && freedHere) { - row := 0.U.asTypeOf(new OooPcBaseEntry(p)) - for (replica <- 0 until p.pcReadReplicaCount) { - readRowAt(replica, safeRecoveryStid, local.U) := - 0.U.asTypeOf(new OooPcReadEntry(p)) + when(recoveryHere && recoveryFreeMask(local)) { + row.valid := false.B + row.closed := false.B + row.closeOwnerValid := false.B + row.closeCommitted := false.B + for (replica <- 0 until p.ooo.pcReadReplicaCount) { + readRowAt(replica, stid.U, local.U).valid := false.B } } } - io.usedBases := usedBases - for (stid <- 0 until p.stidCount) { - io.head(stid).valid := usedBases(stid).orR - io.head(stid).index := stid.U * p.pcEntriesPerStid.U + headLocal(stid) - io.head(stid).byteOffset := 0.U - io.head(stid).allocationEpoch := headEpoch(stid) - } - io.currentValid := currentValid - io.current := currentToken - - for (port <- 0 until p.pcReadPorts) { - val token = io.readTokens(port) - val readStidRaw = token.index / p.pcEntriesPerStid.U - val readStidInRange = readStidRaw < p.stidCount.U - val readStid = readStidRaw(p.stidWidth - 1, 0) - val safeReadStid = Mux(readStidInRange, readStid, 0.U) - val replica = port % p.pcReadReplicaCount - val row = readRowAt(replica, safeReadStid, localIndex(token)) - io.readValid(port) := token.valid && readStidInRange && row.valid && - row.stid === readStid && row.index === token.index && - row.allocationEpoch === token.allocationEpoch - io.readPc(port) := Mux( - io.readValid(port), - row.base + token.byteOffset.pad(p.pcWidth), - 0.U) + private val readsPerReplica = p.ooo.pcReadPorts / + p.ooo.pcReadReplicaCount + for (port <- 0 until p.ooo.pcReadPorts) { + val address = io.readAddress(port) + val stidInRange = address.stid < p.ooo.stidCount.U + val safeStid = Mux(stidInRange, address.stid, 0.U) + val local = localFromIndex(address.pcBufferIndex) + val row = readRowAt(port / readsPerReplica, safeStid, local) + val partitionExact = inPartition(address.pcBufferIndex, safeStid) + io.readPcBase(port).valid := address.valid && stidInRange && + partitionExact && row.valid && row.stid === address.stid && + row.pcBufferIndex === address.pcBufferIndex && + row.allocationEpoch === address.allocationEpoch + io.readPcBase(port).bits := row.pcBase } } diff --git a/chisel/src/main/scala/linxcore/ooo/OooRecoveryMembership.scala b/chisel/src/main/scala/linxcore/ooo/OooRecoveryMembership.scala index 98f11e1e..0aa26c41 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooRecoveryMembership.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooRecoveryMembership.scala @@ -1,16 +1,19 @@ package linxcore.ooo import chisel3._ +import linxcore.params.{CoreParams, CTUParams, DTUParams, IEXParams, IFUParams, + WidthParams} +import linxcore.top.interface.{RecoveryPlan, RecoveryPlanContract, + InterfaceWidth, RobIdentity} -/** Shared exact membership predicates for O7 recovery consumers. - * - * The grouped ROB has already resolved one request against its live ordered - * window. Downstream owners therefore consume the retained wrap-qualified - * window instead of comparing native BID/RID magnitudes or building a CAM - * over every killed ROB record for every physical queue row. +/** Exact value mapping used while the retained IEX mechanisms still carry + * their private row payload. Recovery age is never recomputed here: the OOO + * owner publishes the killed suffix in one canonical [[RecoveryPlan]], and + * every retention owner asks the canonical contract whether its exact ROB + * identity belongs to that suffix. */ object OooRecoveryMembership { - private def memberOffset( + private def oldMemberOffset( p: OooParams, plan: OooResidencyRecoveryPlan, member: RobMemberKey): (UInt, Bool) = { @@ -23,25 +26,24 @@ object OooRecoveryMembership { (offset, wrapsFromHead) } - private def memberMatchesPivot( + private def oldMemberMatchesPivot( plan: OooResidencyRecoveryPlan, - member: RobMemberKey): Bool = { + member: RobMemberKey): Bool = plan.pivot.group.valid && member.group.asUInt === plan.pivot.group.asUInt && member.bid.asUInt === plan.pivot.bid.asUInt && member.brobGeneration === plan.pivot.brobGeneration && member.residentGeneration === plan.pivot.residentGeneration - } - /** True only when `member` belongs to the exact old ROB window authorized - * by `plan`. The wrap-qualified ROB key is the group identity; native BID - * magnitude is deliberately not used as an age comparator. + /** Temporary predicate retained only for owners outside the current IEX + * cutover. It consumes their existing plan directly and never converts a + * canonical plan back into the displaced representation. */ def memberInOldWindow( p: OooParams, plan: OooResidencyRecoveryPlan, member: RobMemberKey): Bool = { - val (offset, wrapsFromHead) = memberOffset(p, plan, member) + val (offset, wrapsFromHead) = oldMemberOffset(p, plan, member) val expectedGeneration = plan.oldHead.ridGeneration + wrapsFromHead.asUInt plan.valid && plan.oldHead.valid && member.group.valid && member.bid.valid && @@ -52,24 +54,112 @@ object OooRecoveryMembership { member.memberIndex < p.maxOrdinaryUopsPerGroup.U } - /** True only when `member` belongs to the exact old ROB window authorized - * by `plan` and lies in its killed physical-member suffix. + /** Temporary overload for non-IEX owners awaiting their own atomic + * recovery cutover. Canonical IEX retention owners must use the overload + * taking `CoreParams` and `RecoveryPlan` below. */ def memberKilled( p: OooParams, plan: OooResidencyRecoveryPlan, member: RobMemberKey): Bool = { - val (offset, _) = memberOffset(p, plan, member) + val (offset, _) = oldMemberOffset(p, plan, member) val exactWindowMember = memberInOldWindow(p, plan, member) - - val completeKilledGroup = exactWindowMember && - offset >= plan.newOccupied + val completeKilledGroup = exactWindowMember && offset >= plan.newOccupied val partialPivotKilled = exactWindowMember && plan.survivingPivotValid && offset === plan.pivotOffset && - memberMatchesPivot(plan, member) && + oldMemberMatchesPivot(plan, member) && member.memberIndex >= plan.survivingPivotPhysicalMemberCount && member.memberIndex < plan.pivotPhysicalMemberCount - completeKilledGroup || partialPivotKilled } + + /** Canonical parameter view for private mechanisms whose callers have not + * yet been lifted to `CoreParams`. All identity-bearing widths and ROB + * geometry are copied exactly from the mechanism parameter record. + */ + def coreParams(p: OooParams): CoreParams = { + val widths = WidthParams( + fetchWidth = p.instructionDecodeWidth, + ctuOutputWidth = p.instructionDecodeWidth, + decodeWidth = p.instructionDecodeWidth, + renameWidth = p.renameWidth, + dispatchWidth = p.dispatchWidth, + issueWidth = p.dispatchWidth, + retireWidth = p.retireGroupWidth) + CoreParams( + widths = widths, + ifu = IFUParams(fetchWidth = widths.fetchWidth, + ctuTransferWidth = widths.ctuOutputWidth), + ctu = CTUParams(inputWidth = widths.ctuOutputWidth, + outputWidth = widths.ctuOutputWidth), + ooo = p.toMainline, + iex = IEXParams(issueWidth = widths.issueWidth), + dtu = DTUParams(traceWidth = math.max( + widths.retireWidth, widths.fetchWidth)), + pcWidth = p.pcWidth, + instructionWidth = p.instructionWidth, + opcodeWidth = p.opcodeWidth, + archRegWidth = p.archRegWidth, + lsidWidth = p.lsidWidth, + maxMemoryRequestsPerInstruction = p.maxMemoryRequestsPerInstruction, + peIdWidth = p.peIdWidth, + instructionIdWidth = p.instructionIdWidth, + transactionIdWidth = p.transactionIdWidth, + memoryTransactionIdWidth = p.memoryTransactionIdWidth, + memoryTransactionGenerationWidth = + p.memoryTransactionGenerationWidth, + epochWidth = p.epochWidth, + brobGenerationWidth = p.brobGenerationWidth, + ridGenerationWidth = p.ridGenerationWidth, + residentGenerationWidth = p.residentGenerationWidth, + memoryAttemptGenerationWidth = p.loadGenerationWidth, + trapCauseWidth = p.trapCauseWidth, + maxSourceOperands = p.maxSourceOperands, + maxDestinationOperands = p.maxDestinationOperands) + } + + def requireCompatible(p: OooParams, core: CoreParams): Unit = { + require(p.peIdWidth == core.peIdWidth && + p.stidWidth == core.ooo.stidWidth && + p.ridSlotWidth == core.ooo.ridSlotWidth && + p.ridGenerationWidth == core.ridGenerationWidth && + p.nativeBidWidth == core.nativeBidWidth && + p.brobGenerationWidth == core.brobGenerationWidth && + p.residentGenerationWidth == core.residentGenerationWidth && + p.memoryTransactionIdWidth == core.memoryTransactionIdWidth && + p.memoryTransactionGenerationWidth == + core.memoryTransactionGenerationWidth && + p.robMemberIndexWidth == core.ooo.robMemberIndexWidth, + "private IEX ROB identity fields must cover canonical CoreParams") + require(p.robGroupsPerStid == core.ooo.robGroupsPerStid && + p.stidCount == core.ooo.stidCount, + "private IEX ROB geometry must equal canonical CoreParams") + } + + def robIdentity( + p: OooParams, + core: CoreParams, + member: RobMemberKey): RobIdentity = { + requireCompatible(p, core) + val identity = Wire(new RobIdentity(core)) + identity.peId := member.group.peId + identity.stid := member.group.stid + identity.ridSlot := member.group.ridSlot + identity.ridGeneration := member.group.ridGeneration + identity.memberIndex := member.memberIndex + identity.residentGeneration := member.residentGeneration + identity.bid := member.bid.value + identity.brobGeneration := member.brobGeneration + + identity + } + + def memberKilled( + p: OooParams, + core: CoreParams, + plan: RecoveryPlan, + member: RobMemberKey): Bool = + member.group.valid && member.bid.valid && + member.memberIndex < core.ooo.maxInstructionsPerRobGroup.U && + RecoveryPlanContract.suffixMember(plan, robIdentity(p, core, member)) } diff --git a/chisel/src/main/scala/linxcore/ooo/OooRobBrobPcCoordinator.scala b/chisel/src/main/scala/linxcore/ooo/OooRobBrobPcCoordinator.scala deleted file mode 100644 index ce79bdbb..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooRobBrobPcCoordinator.scala +++ /dev/null @@ -1,369 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, Enum, Valid, is, switch} - -class OooRobBrobPcCoordinatorIO(val p: OooParams = OooParams()) extends Bundle { - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val cancel = Input(Vec(p.stidCount, Bool())) - val publishEligible = Input(Vec(p.stidCount, Bool())) - val memoryOrder = Input(new OooMemoryOrderReservationLease(p)) - - // Later RENU/dispatch owners inspect this immutable D3 view and assert the - // permit only when their own reservations can join the same publication. - val preparedValid = Output(Bool()) - val prepared = Output(new OooO3PreparedPublication(p)) - val publishPermit = Input(Bool()) - val publishFire = Output(Bool()) - - val completion = Flipped(Decoupled(new OooRobMemberCompletion(p))) - val nonFlushEvidence = Flipped(Decoupled(new OooRobNonFlushEvidence(p))) - val interruptPending = Input(Vec(p.stidCount, Bool())) - val nonFlushWindows = Output(Vec(p.stidCount, new NonFlushWindow(p))) - val commit = Decoupled(new OooRobCommitBatch(p)) - - // Retained physical-owner recovery subtransaction. A future global R0-R4 - // coordinator joins this prepared view with rename, dispatch, IEX, fast, - // frontend-stage, and CTU owners before asserting `recoveryApply`. - val recoveryRequest = Flipped(Decoupled(new OooGlobalRecoveryRequest(p))) - val recoveryBusy = Output(Bool()) - val recoveryPreparedValid = Output(Bool()) - val recoveryPrepared = Output(new OooRobRecoveryPlan(p)) - val recoveryApply = Input(Bool()) - val recoveryAbort = Input(Bool()) - val recoveryApplied = Valid(new OooGlobalRecoveryRequest(p)) - - val pcReadTokens = Input(Vec(p.pcReadPorts, new PcBufferToken(p))) - val pcReadValid = Output(Vec(p.pcReadPorts, Bool())) - val pcRead = Output(Vec(p.pcReadPorts, UInt(p.pcWidth.W))) - - val d3StaleRejected = Valid(new OooD3StalePlanReject(p)) - val d3PlanStale = Output(Bool()) - val d3ReleaseRejected = Valid(new OooD3ReleaseReject(p)) - val robPublicationRejected = Valid(new OooS1PublicationReject(p)) - val completionRejected = Valid(new OooRobMemberCompletionReject(p)) - val nonFlushEvidenceRejected = Valid(new OooRobNonFlushEvidenceReject(p)) - val brobPrepareRejected = Valid(new OooBrobPrepareReject(p)) - val brobCommitRejected = Valid(new OooBrobCommitReject(p)) - val pcPrepareRejected = Valid(new OooPcPrepareReject(p)) - val pcCommitRejected = Valid(new OooPcCommitReject(p)) - val robRecoveryRejected = Valid(new OooRobRecoveryReject(p)) - val d3RecoveryRejected = Valid(new OooD3RecoveryReject(p)) - val brobRecoveryRejected = Valid(new OooBrobRecoveryReject(p)) - val pcRecoveryRejected = Valid(new OooPcRecoveryReject(p)) - - val d3UsedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3PublishedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3TailSlot = Output(Vec(p.stidCount, UInt(p.ridSlotWidth.W))) - val d3TailGeneration = Output(Vec(p.stidCount, - UInt(p.ridGenerationWidth.W))) - val d3TailEpoch = Output(Vec(p.stidCount, - UInt(p.reservationEpochWidth.W))) - val d3NextTransactionId = Output(Vec(p.stidCount, - UInt(p.transactionIdWidth.W))) - val robOccupiedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val brobUsedBlocks = Output(Vec(p.stidCount, UInt(p.brobCountWidth.W))) - val pcUsedBases = Output(Vec(p.stidCount, UInt(p.pcPartitionCountWidth.W))) -} - -/** Atomic O3 coordinator for D3 allocation, grouped ROB, native BROB, and PC. - * - * BROB and PC perform side-effect-free preparation against the retained D3 - * reservation. The grouped ROB validates the fully bound publication. None - * of the four owners mutate until `publishPermit` joins all ready views into - * one `publishFire`. Commit follows the same rule: the retained ROB batch is - * externally visible only when D3 release, BROB retirement, and PC retirement - * all accept the exact batch, so every owner fires in the same cycle. - */ -class OooRobBrobPcCoordinator(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooRobBrobPcCoordinatorIO(p)) - - val d3 = Module(new OooD3ReservationAllocator(p)) - val rob = Module(new OooS1GroupedRob(p)) - val brob = Module(new OooBrob(p)) - val pc = Module(new OooPcBuffer(p)) - - val recoveryIdle :: recoveryPreparing :: recoveryPrepared :: Nil = Enum(3) - val recoveryState = RegInit(recoveryIdle) - val recoveryRequestReg = RegInit( - 0.U.asTypeOf(new OooGlobalRecoveryRequest(p))) - val recoveryPlanReg = RegInit(0.U.asTypeOf(new OooRobRecoveryPlan(p))) - - d3.io.in <> io.reserve - d3.io.cancel := io.cancel - val rawCommitStid = rob.io.commit.bits.release.firstGroup.stid - val rawCommitStidInRange = rawCommitStid < p.stidCount.U - for (stid <- 0 until p.stidCount) { - // An older raw ROB head gets same-STID priority before D3 exposes a new - // grant. Different STIDs remain independently eligible. - d3.io.publishEligible(stid) := io.publishEligible(stid) && - !(rob.io.commit.valid && rawCommitStidInRange && rawCommitStid === stid.U) - } - - brob.io.prepare.valid := d3.io.out.valid - brob.io.prepare.bits := d3.io.out.bits - pc.io.prepare.valid := d3.io.out.valid - pc.io.prepare.bits := d3.io.out.bits - - val residentGeneration = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.robGroupsPerStid)(0.U(p.residentGenerationWidth.W)))))) - val publishRequest = Wire(new OooS1GroupedPublicationRequest(p)) - publishRequest := 0.U.asTypeOf(publishRequest) - publishRequest.reservation := d3.io.out.bits - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = d3.io.out.bits.transaction.groups(groupIndex) - val binding = publishRequest.bindings(groupIndex) - val stid = d3.io.out.bits.transaction.plan.stid - binding.valid := group.valid - binding.brob := brob.io.prepared.pointers(groupIndex) - binding.brobAllocated := brob.io.prepared.newBlockMask(groupIndex) - binding.brobImplicitCloseValid := - brob.io.prepared.implicitCloseMask(groupIndex) - binding.brobImplicitClose := - brob.io.prepared.implicitClosePointers(groupIndex) - binding.pcBase := pc.io.prepared.groupTokens(groupIndex) - binding.pcBaseAllocated := pc.io.prepared.newBaseMask(groupIndex) - binding.pcImplicitCloseValid := - pc.io.prepared.implicitCloseMask(groupIndex) - binding.pcImplicitClose := - pc.io.prepared.implicitCloseTokens(groupIndex) - binding.residentGeneration := - residentGeneration(stid)(group.key.ridSlot) + 1.U - binding.initiallyCompletedMembers := 0.U - binding.memoryOrderValid := io.memoryOrder.valid - binding.memoryBefore := io.memoryOrder.before - binding.memoryAfter := io.memoryOrder.before - for (uopIndex <- 0 until p.decodedUopWidth) { - val logical = group.logicalUopMask(uopIndex) - binding.logicalMemoryAfter(uopIndex) := Mux(logical, - io.memoryOrder.uops(uopIndex).after, - 0.U.asTypeOf(new OooMemoryIdState(p))) - when(logical && uopIndex.U === group.firstLogicalUop) { - binding.memoryBefore := io.memoryOrder.uops(uopIndex).before - } - when(logical) { - binding.memoryAfter := io.memoryOrder.uops(uopIndex).after - } - } - } - - val memoryOrderIdentityExact = io.memoryOrder.valid && - io.memoryOrder.peId === d3.io.out.bits.transaction.plan.peId && - io.memoryOrder.stid === d3.io.out.bits.transaction.plan.stid && - io.memoryOrder.epoch === d3.io.out.bits.transaction.plan.epoch && - io.memoryOrder.transactionId === - d3.io.out.bits.transaction.plan.transactionId && - io.memoryOrder.uopMask === d3.io.out.bits.transaction.plan.uopMask - val memoryOrderUopShapeExact = (0 until p.decodedUopWidth).map { uopIndex => - val active = d3.io.out.bits.transaction.plan.uopMask(uopIndex) - val allocation = io.memoryOrder.uops(uopIndex) - val expectedBefore = if (uopIndex == 0) io.memoryOrder.before - else io.memoryOrder.uops(uopIndex - 1).after - allocation.valid === active && - allocation.before.asUInt === expectedBefore.asUInt - }.reduce(_ && _) - val memoryOrderRequired = - d3.io.out.bits.transaction.plan.demand.loadIds.orR || - d3.io.out.bits.transaction.plan.demand.storeIds.orR - val memoryOrderExact = memoryOrderIdentityExact && - memoryOrderUopShapeExact && - io.memoryOrder.after.asUInt === - io.memoryOrder.uops(p.decodedUopWidth - 1).after.asUInt - // Direct owner-level tests which predate the memory-order owner may omit a - // lease for a transaction with no memory demand. Canonical composition - // always supplies the valid full-tail lease, including non-memory groups. - val memoryOrderAccepted = memoryOrderExact || - (!memoryOrderRequired && !io.memoryOrder.valid) - - rob.io.publish.bits := publishRequest - val ownerPrepareReady = brob.io.prepareReady && pc.io.prepareReady && - rob.io.publish.ready && memoryOrderAccepted - io.preparedValid := d3.io.out.valid && ownerPrepareReady - io.prepared.request := publishRequest - io.prepared.parentPcTokens := pc.io.prepared.parentTokens - io.prepared.brobImplicitCloseMask := brob.io.prepared.implicitCloseMask - io.prepared.brobImplicitClosePointers := - brob.io.prepared.implicitClosePointers - - rob.io.publish.valid := d3.io.out.valid && brob.io.prepareReady && - pc.io.prepareReady && io.publishPermit - d3.io.out.ready := ownerPrepareReady && io.publishPermit - val sharedPublishFire = d3.io.out.valid && d3.io.out.ready - brob.io.publishFire := sharedPublishFire - pc.io.publishFire := sharedPublishFire - io.publishFire := sharedPublishFire - - when(sharedPublishFire) { - assert(rob.io.publish.fire, - "grouped ROB must publish on the shared ROB/BROB/PC fire") - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = d3.io.out.bits.transaction.groups(groupIndex) - when(group.valid) { - residentGeneration(group.key.stid)(group.key.ridSlot) := - publishRequest.bindings(groupIndex).residentGeneration - } - } - } - - rob.io.completion <> io.completion - rob.io.nonFlushEvidence <> io.nonFlushEvidence - rob.io.interruptPending := io.interruptPending - io.nonFlushWindows := rob.io.nonFlushWindows - val incomingRecoveryStid = - io.recoveryRequest.bits.rename.key.member.group.stid - val incomingRecoveryStidInRange = incomingRecoveryStid < p.stidCount.U - val incomingRecoveryHitsExposedD3 = incomingRecoveryStidInRange && - d3.io.out.valid && - d3.io.out.bits.transaction.plan.stid === incomingRecoveryStid - val incomingRecoveryHitsRetainedCommit = incomingRecoveryStidInRange && - rob.io.commit.valid && rawCommitStidInRange && - rawCommitStid === incomingRecoveryStid - - // A Decoupled producer cannot retract an exposed D3 publication, and an - // already-retained architectural commit cannot be silently canceled. Both - // obligations drain before R0 capture. Hidden provisional reservations are - // legal and are canceled by the later common recovery fire. - io.recoveryRequest.ready := recoveryState === recoveryIdle && - !incomingRecoveryHitsExposedD3 && - !incomingRecoveryHitsRetainedCommit - - val recoveryActive = recoveryState =/= recoveryIdle - rob.io.recoveryPrepare.valid := recoveryActive - rob.io.recoveryPrepare.bits := recoveryRequestReg - - val liveRecoveryPlan = rob.io.recoveryPrepared - val selectedRecoveryPlan = Wire(new OooRobRecoveryPlan(p)) - selectedRecoveryPlan := Mux( - recoveryState === recoveryPrepared, - recoveryPlanReg, - liveRecoveryPlan) - val downstreamRecoveryOffer = recoveryActive && Mux( - recoveryState === recoveryPrepared, - true.B, - rob.io.recoveryPrepareReady) - - d3.io.recoveryPrepare.valid := downstreamRecoveryOffer - d3.io.recoveryPrepare.bits := selectedRecoveryPlan - brob.io.recoveryPrepare.valid := downstreamRecoveryOffer - brob.io.recoveryPrepare.bits := selectedRecoveryPlan - pc.io.recoveryPrepare.valid := downstreamRecoveryOffer - pc.io.recoveryPrepare.bits := selectedRecoveryPlan - - val allRecoveryOwnersReady = rob.io.recoveryPrepareReady && - d3.io.recoveryPrepareReady && brob.io.recoveryPrepareReady && - pc.io.recoveryPrepareReady - val recoveryPlanStable = liveRecoveryPlan.asUInt === recoveryPlanReg.asUInt - io.recoveryPreparedValid := recoveryState === recoveryPrepared && - allRecoveryOwnersReady && recoveryPlanStable - io.recoveryPrepared := recoveryPlanReg - io.recoveryBusy := recoveryActive - - val recoveryApplyFire = io.recoveryApply && io.recoveryPreparedValid - rob.io.recoveryFire := recoveryApplyFire - d3.io.recoveryFire := recoveryApplyFire - brob.io.recoveryFire := recoveryApplyFire - pc.io.recoveryFire := recoveryApplyFire - io.recoveryApplied.valid := recoveryApplyFire - io.recoveryApplied.bits := recoveryRequestReg - - val anyRecoveryOwnerRejected = rob.io.recoveryRejected.valid || - d3.io.recoveryRejected.valid || brob.io.recoveryRejected.valid || - pc.io.recoveryRejected.valid - - switch(recoveryState) { - is(recoveryIdle) { - when(io.recoveryRequest.fire) { - recoveryRequestReg := io.recoveryRequest.bits - recoveryState := recoveryPreparing - } - } - is(recoveryPreparing) { - when(io.recoveryAbort || anyRecoveryOwnerRejected) { - recoveryState := recoveryIdle - }.elsewhen(allRecoveryOwnersReady) { - recoveryPlanReg := liveRecoveryPlan - recoveryState := recoveryPrepared - } - } - is(recoveryPrepared) { - when(io.recoveryAbort || anyRecoveryOwnerRejected) { - recoveryState := recoveryIdle - }.elsewhen(recoveryApplyFire) { - recoveryState := recoveryIdle - } - } - } - - when(io.recoveryApply) { - assert(io.recoveryPreparedValid, - "physical recovery apply requires one retained all-owner plan") - } - when(io.recoveryAbort) { - assert(recoveryActive && !recoveryApplyFire, - "physical recovery abort requires one unapplied retained transaction") - } - when(recoveryState === recoveryPrepared) { - assert(recoveryPlanStable, - "ROB recovery plan must remain stable through external apply backpressure") - } - when(recoveryApplyFire) { - assert(rob.io.recoveryPrepareReady && d3.io.recoveryPrepareReady && - brob.io.recoveryPrepareReady && pc.io.recoveryPrepareReady, - "ROB, D3, BROB, and PC must apply recovery atomically") - } - - // The ROB is the retained commit source. All other owners see the same valid - // batch while computing readiness; external visibility is gated until every - // exact owner can fire, preventing partial architectural retirement. - // Owner readiness is a side-effect-free exactness check. Their valids are - // asserted only for the terminal external handshake, so no owner can retire - // early while the consumer is applying backpressure. - d3.io.release.bits := rob.io.commit.bits.release - brob.io.commit.bits := rob.io.commit.bits - pc.io.commit.bits := rob.io.commit.bits - val allCommitReady = d3.io.release.ready && brob.io.commit.ready && pc.io.commit.ready - io.commit.valid := rob.io.commit.valid && allCommitReady - io.commit.bits := rob.io.commit.bits - rob.io.commit.ready := io.commit.ready && allCommitReady - val sharedCommitFire = io.commit.valid && io.commit.ready - d3.io.release.valid := sharedCommitFire - brob.io.commit.valid := sharedCommitFire - pc.io.commit.valid := sharedCommitFire - - when(rob.io.commit.fire) { - assert(d3.io.release.fire && brob.io.commit.fire && pc.io.commit.fire, - "ROB, D3 release, BROB, and PC must commit atomically") - } - - pc.io.readTokens := io.pcReadTokens - io.pcReadValid := pc.io.readValid - io.pcRead := pc.io.readPc - - io.d3StaleRejected := d3.io.staleRejected - io.d3PlanStale := d3.io.planStale - io.d3ReleaseRejected := d3.io.releaseRejected - io.robPublicationRejected := rob.io.publicationRejected - io.completionRejected := rob.io.completionRejected - io.nonFlushEvidenceRejected := rob.io.nonFlushEvidenceRejected - io.brobPrepareRejected := brob.io.prepareRejected - io.brobCommitRejected := brob.io.commitRejected - io.pcPrepareRejected := pc.io.prepareRejected - io.pcCommitRejected := pc.io.commitRejected - io.robRecoveryRejected := rob.io.recoveryRejected - io.d3RecoveryRejected := d3.io.recoveryRejected - io.brobRecoveryRejected := brob.io.recoveryRejected - io.pcRecoveryRejected := pc.io.recoveryRejected - - io.d3UsedGroups := d3.io.usedGroups - io.d3PublishedGroups := d3.io.publishedGroups - io.d3TailSlot := d3.io.tailSlot - io.d3TailGeneration := d3.io.tailGeneration - io.d3TailEpoch := d3.io.tailEpoch - io.d3NextTransactionId := d3.io.nextTransactionId - io.robOccupiedGroups := rob.io.occupiedGroups - io.brobUsedBlocks := brob.io.usedBlocks - io.pcUsedBases := pc.io.usedBases -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooRobStoreCommitOwner.scala b/chisel/src/main/scala/linxcore/ooo/OooRobStoreCommitOwner.scala deleted file mode 100644 index b6eb27af..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooRobStoreCommitOwner.scala +++ /dev/null @@ -1,230 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Decoupled, PopCount, Valid, log2Ceil} - -import linxcore.lsu.STQRobCommitToken - -class OooRobStoreCommitOwnerIO(val p: OooParams = OooParams()) - extends Bundle { - val commitPrepare = Flipped(Valid(new OooRobCommitBatch(p))) - val commitStartReady = Output(Bool()) - val commitFire = Input(Bool()) - - val storeCommit = Decoupled(new STQRobCommitToken( - p.robGroupsPerStid, p.lsidWidth, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth)) - val used = Output(UInt(p.storeCommitBufferCountWidth.W)) - val free = Output(UInt(p.storeCommitBufferCountWidth.W)) - val preparedTokenCount = Output(UInt( - p.countWidth(p.maxCommitStoreTokens).W)) - val commitRejected = Valid(new OooRobCommitBatch(p)) -} - -/** ROB-owned committed-store token buffer. - * - * The grouped ROB retains memory-order tails rather than physical STQ - * pointers. This owner reconstructs every logical store range, expands it - * into one/two exact beats, and atomically captures the complete batch only - * on the common architectural commit fire. Tokens drain later through a - * decoupled LSU ingress, so LSU backpressure cannot split ROB/BROB/rename - * retirement and no store becomes non-flush before that retirement. - */ -class OooRobStoreCommitOwner(val p: OooParams = OooParams()) extends Module { - require(p.maxMemoryRequestsPerInstruction == 2, - "canonical scalar store commit expansion currently supports one/two beats") - - val io = IO(new OooRobStoreCommitOwnerIO(p)) - - private val capacity = p.storeCommitBufferEntries - private val ptrWidth = log2Ceil(capacity) - private val tokenCountWidth = p.countWidth(p.maxCommitStoreTokens) - - private def tokenType: STQRobCommitToken = new STQRobCommitToken( - p.robGroupsPerStid, p.lsidWidth, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth) - - private def zeroToken: STQRobCommitToken = { - val token = Wire(tokenType) - token := 0.U.asTypeOf(token) - token - } - - private def addPtr(pointer: UInt, amount: UInt): UInt = - (pointer + amount)(ptrWidth - 1, 0) - - val rows = Reg(Vec(capacity, tokenType)) - val head = RegInit(0.U(ptrWidth.W)) - val tail = RegInit(0.U(ptrWidth.W)) - val count = RegInit(0.U(p.storeCommitBufferCountWidth.W)) - - io.storeCommit.valid := count.orR - io.storeCommit.bits := rows(head) - val dequeue = io.storeCommit.fire - - val batch = io.commitPrepare.bits - val groupCount = batch.release.groupCount - val commitStid = batch.release.firstGroup.stid - val commitStidInRange = commitStid < p.stidCount.U - val groupCountInRange = groupCount.orR && - groupCount <= p.retireGroupWidth.U - - val groupExact = Wire(Vec(p.retireGroupWidth, Bool())) - val groupMemoryExact = Wire(Vec(p.retireGroupWidth, Bool())) - val state = Wire(Vec(p.retireGroupWidth, - Vec(p.decodedUopWidth + 1, new OooMemoryIdState(p)))) - val logicalStore = Wire(Vec(p.retireGroupWidth, - Vec(p.decodedUopWidth, Bool()))) - val logicalRequestCount = Wire(Vec(p.retireGroupWidth, - Vec(p.decodedUopWidth, UInt(p.memoryDemandWidth.W)))) - - for (groupIndex <- 0 until p.retireGroupWidth) { - val active = groupIndex.U < groupCount - val group = batch.groups(groupIndex) - val slotSum = batch.release.firstGroup.ridSlot +& groupIndex.U - val wraps = slotSum >= p.robGroupsPerStid.U - val completedMask = - ((1.U((p.maxOrdinaryUopsPerGroup + 1).W) << - group.physicalMemberCount) - 1.U)( - p.maxOrdinaryUopsPerGroup - 1, 0) - val groupIdentityExact = group.valid === active && (!active || ( - group.key.valid && - group.key.peId === batch.release.firstGroup.peId && - group.key.stid === commitStid && - group.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && - group.key.ridGeneration === - batch.release.firstGroup.ridGeneration + wraps.asUInt && - group.brob.valid && group.brob.bid.valid && - group.physicalMemberCount.orR && - group.completedMembers === completedMask)) - - state(groupIndex)(0) := group.memoryBefore - val logicalExact = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val logical = active && group.logicalUopMask(uopIndex) - val before = state(groupIndex)(uopIndex) - val recordedAfter = group.logicalMemoryAfter(uopIndex) - state(groupIndex)(uopIndex + 1) := - Mux(logical, recordedAfter, before) - - val lsidDelta = recordedAfter.lsid - before.lsid - val loadDelta = recordedAfter.loadId - before.loadId - val storeDelta = recordedAfter.storeId - before.storeId - val typedDeltaExact = lsidDelta === loadDelta + storeDelta && - !(loadDelta.orR && storeDelta.orR) && - loadDelta <= p.maxMemoryRequestsPerInstruction.U && - storeDelta <= p.maxMemoryRequestsPerInstruction.U - val memberEnd = group.logicalMemberBase(uopIndex) +& - group.logicalMemberCount(uopIndex) - val memberExact = group.logicalMemberCount(uopIndex).orR && - memberEnd <= group.physicalMemberCount - val inactiveMetadataZero = - group.logicalMemberBase(uopIndex) === 0.U && - group.logicalMemberCount(uopIndex) === 0.U && - recordedAfter.asUInt === 0.U - - logicalExact(uopIndex) := Mux(logical, - memberExact && typedDeltaExact, - inactiveMetadataZero) - logicalStore(groupIndex)(uopIndex) := logical && - group.memoryOrderValid && storeDelta.orR && typedDeltaExact - logicalRequestCount(groupIndex)(uopIndex) := storeDelta - } - - val canonicalMemoryExact = group.memoryOrderValid && - state(groupIndex)(p.decodedUopWidth).asUInt === - group.memoryAfter.asUInt && logicalExact.asUInt.andR - val legacyNoMemory = !group.memoryOrderValid && - group.memoryBefore.asUInt === 0.U && group.memoryAfter.asUInt === 0.U && - group.logicalMemoryAfter.asUInt === 0.U - val priorGroupChainExact = if (groupIndex == 0) true.B else - !active || group.memoryBefore.asUInt === - batch.groups(groupIndex - 1).memoryAfter.asUInt - groupMemoryExact(groupIndex) := (!active || - canonicalMemoryExact || legacyNoMemory) && priorGroupChainExact - groupExact(groupIndex) := groupIdentityExact && - groupMemoryExact(groupIndex) - } - - val rawValid = Wire(Vec(p.maxCommitStoreTokens, Bool())) - val rawToken = Wire(Vec(p.maxCommitStoreTokens, tokenType)) - for (groupIndex <- 0 until p.retireGroupWidth) { - for (uopIndex <- 0 until p.decodedUopWidth) { - for (beat <- 0 until p.maxMemoryRequestsPerInstruction) { - val rawIndex = - (groupIndex * p.decodedUopWidth + uopIndex) * - p.maxMemoryRequestsPerInstruction + beat - val group = batch.groups(groupIndex) - val token = rawToken(rawIndex) - token := zeroToken - token.logicalFirstLsid := state(groupIndex)(uopIndex).lsid - token.logicalFirstStoreId := state(groupIndex)(uopIndex).storeId - token.logicalRequestCount := - logicalRequestCount(groupIndex)(uopIndex) - token.logicalBeat := beat.U - token.exactOwner.valid := group.key.valid - token.exactOwner.peId := group.key.peId - token.exactOwner.stid := group.key.stid - token.exactOwner.nativeBidValid := group.brob.bid.valid - token.exactOwner.nativeBid := group.brob.bid.value - token.exactOwner.brobGeneration := group.brob.generation - token.exactOwner.ridSlot := group.key.ridSlot - token.exactOwner.ridGeneration := group.key.ridGeneration - token.exactOwner.memberIndex := group.logicalMemberBase(uopIndex) - token.exactOwner.residentGeneration := group.residentGeneration - rawValid(rawIndex) := logicalStore(groupIndex)(uopIndex) && - beat.U < logicalRequestCount(groupIndex)(uopIndex) - } - } - } - - val preparedTokenCount = PopCount(rawValid) - val freeWithDequeue = capacity.U - count + dequeue.asUInt - val incomingExact = commitStidInRange && groupCountInRange && - batch.release.firstGroup.valid && groupExact.asUInt.andR - val hasCredit = preparedTokenCount <= freeWithDequeue - io.commitStartReady := incomingExact && hasCredit - io.preparedTokenCount := preparedTokenCount - io.commitRejected.valid := io.commitPrepare.valid && - (!incomingExact || !hasCredit) - io.commitRejected.bits := batch - - val enqueue = io.commitFire - when(enqueue) { - assert(io.commitPrepare.valid && io.commitStartReady, - "store commit capture requires one exact credit-qualified ROB batch") - for (rawIndex <- 0 until p.maxCommitStoreTokens) { - val rank = if (rawIndex == 0) 0.U - else PopCount(rawValid.take(rawIndex)) - when(rawValid(rawIndex)) { - rows(addPtr(tail, rank)) := rawToken(rawIndex) - } - } - tail := addPtr(tail, preparedTokenCount) - } - - when(dequeue) { - head := addPtr(head, 1.U) - } - when(enqueue && !dequeue) { - count := count + preparedTokenCount - }.elsewhen(!enqueue && dequeue) { - count := count - 1.U - }.elsewhen(enqueue && dequeue) { - count := count + preparedTokenCount - 1.U - } - - io.used := count - io.free := capacity.U - count - - when(count.orR) { - assert(io.storeCommit.bits.exactOwner.valid && - io.storeCommit.bits.exactOwner.nativeBidValid && - io.storeCommit.bits.logicalRequestCount.orR && - io.storeCommit.bits.logicalBeat < - io.storeCommit.bits.logicalRequestCount, - "resident store commit tokens must retain exact logical ownership") - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooS1GroupedRob.scala b/chisel/src/main/scala/linxcore/ooo/OooS1GroupedRob.scala deleted file mode 100644 index d05bdc6d..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooS1GroupedRob.scala +++ /dev/null @@ -1,1103 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Cat, Decoupled, PopCount, PriorityEncoder, UIntToOH, Valid} - -object OooRobRecoveryScanState extends ChiselEnum { - val Idle, FindPivot, BuildPlan, Prepared, Rejected = Value -} - -class OooS1GroupedRobIO(val p: OooParams = OooParams()) extends Bundle { - val publish = Flipped(Decoupled(new OooS1GroupedPublicationRequest(p))) - val completion = Flipped(Decoupled(new OooRobMemberCompletion(p))) - val nonFlushEvidence = Flipped(Decoupled(new OooRobNonFlushEvidence(p))) - val interruptPending = Input(Vec(p.stidCount, Bool())) - val recoveryPrepare = Flipped(Valid(new OooGlobalRecoveryRequest(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryPrepared = Output(new OooRobRecoveryPlan(p)) - val recoveryFire = Input(Bool()) - val commit = Decoupled(new OooRobCommitBatch(p)) - - val publicationRejected = Valid(new OooS1PublicationReject(p)) - val completionRejected = Valid(new OooRobMemberCompletionReject(p)) - val nonFlushEvidenceRejected = Valid(new OooRobNonFlushEvidenceReject(p)) - val recoveryRejected = Valid(new OooRobRecoveryReject(p)) - val nonFlushWindows = Output(Vec(p.stidCount, new NonFlushWindow(p))) - val occupiedGroups = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val headSlot = Output(Vec(p.stidCount, UInt(p.ridSlotWidth.W))) - val headGeneration = Output(Vec(p.stidCount, UInt(p.ridGenerationWidth.W))) - val headEpoch = Output(Vec(p.stidCount, UInt(p.reservationEpochWidth.W))) -} - -/** S1 physical grouped ROB owner. - * - * Publication is atomic across every group in a D3 reservation. Completion - * consumes an exact member key and rejects stale/duplicate reports with zero - * mutation. Commit is a retained, older-first batch; its release token is the - * sole authority for advancing the matching D3 allocator head. - */ -class OooS1GroupedRob(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooS1GroupedRobIO(p)) - private val occupiedWidth = p.countWidth(p.robGroupsPerStid) - - val rows = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.robBankCountEffective)( - VecInit(Seq.fill(p.robSubbankCountEffective)( - VecInit(Seq.fill(p.robRowsPerSubbank)( - 0.U.asTypeOf(new OooRobPhysicalGroupRecord(p))))))))))) - private def robBankIndex(slot: UInt): UInt = - if (p.robBankCountEffective == 1) 0.U(p.robBankIndexWidth.W) - else slot(p.robBankSelectionBits - 1, 0) - private def robSubbankIndex(slot: UInt): UInt = - if (p.robSubbankCountEffective == 1) 0.U(p.robSubbankIndexWidth.W) - else (slot >> p.robBankSelectionBits)(p.robSubbankSelectionBits - 1, 0) - private def robSubbankRowIndex(slot: UInt): UInt = - if (p.robRowsPerSubbank == 1) 0.U(p.robSubbankRowIndexWidth.W) - else (slot >> (p.robBankSelectionBits + p.robSubbankSelectionBits))( - p.robSubbankRowIndexWidth - 1, 0) - private def rowAt(stid: UInt, slot: UInt): OooRobPhysicalGroupRecord = - rows(stid)(robBankIndex(slot))(robSubbankIndex(slot))( - robSubbankRowIndex(slot)) - val occupied = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(occupiedWidth.W)))) - val headSlot = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridSlotWidth.W)))) - val headGeneration = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.ridGenerationWidth.W)))) - val headEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.reservationEpochWidth.W)))) - val headPeId = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.peIdWidth.W)))) - val nonFlushAuthorized = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.nonFlushPrefixCountWidth.W)))) - val nonFlushEpoch = RegInit(VecInit(Seq.fill(p.stidCount)(0.U(p.epochWidth.W)))) - val nonFlushScanDirty = RegInit(VecInit(Seq.fill(p.stidCount)(false.B))) - val nonFlushScanActive = RegInit(false.B) - val nonFlushScanStid = RegInit(0.U(p.stidWidth.W)) - val nonFlushScanRrStart = RegInit(0.U(p.stidWidth.W)) - val nonFlushScanCursor = RegInit(0.U(p.nonFlushPrefixCountWidth.W)) - val nonFlushScanCandidate = RegInit(0.U(p.nonFlushPrefixCountWidth.W)) - val nonFlushScanSnapshotOccupied = RegInit( - 0.U(p.nonFlushPrefixCountWidth.W)) - val nonFlushScanSnapshotHeadSlot = RegInit(0.U(p.ridSlotWidth.W)) - val nonFlushScanSnapshotHeadGeneration = RegInit( - 0.U(p.ridGenerationWidth.W)) - val nonFlushScanSnapshotHeadEpoch = RegInit( - 0.U(p.reservationEpochWidth.W)) - val nonFlushScanSnapshotHeadPeId = RegInit(0.U(p.peIdWidth.W)) - val nonFlushScanSnapshotAuthorized = RegInit( - 0.U(p.nonFlushPrefixCountWidth.W)) - val nonFlushScanSnapshotEpoch = RegInit(0.U(p.epochWidth.W)) - - val recoveryScanState = RegInit(OooRobRecoveryScanState.Idle) - val retainedRecoveryRequest = RegInit( - 0.U.asTypeOf(new OooGlobalRecoveryRequest(p))) - val retainedRecoveryPlan = RegInit( - 0.U.asTypeOf(new OooRobRecoveryPlan(p))) - val recoveryScanCursor = RegInit(0.U(p.robRecoveryScanCursorWidth.W)) - val recoveryExactMatchCountReg = RegInit( - 0.U(p.countWidth(p.robGroupsPerStid).W)) - val recoveryWindowExactReg = RegInit(true.B) - val recoveryPivotReg = RegInit( - 0.U.asTypeOf(new OooRobPhysicalGroupRecord(p))) - val recoveryPivotOffsetReg = RegInit( - 0.U(p.nonFlushPrefixCountWidth.W)) - val recoverySnapshotOccupied = RegInit( - 0.U(p.nonFlushPrefixCountWidth.W)) - val recoverySnapshotHeadSlot = RegInit(0.U(p.ridSlotWidth.W)) - val recoverySnapshotHeadGeneration = RegInit( - 0.U(p.ridGenerationWidth.W)) - val recoverySnapshotHeadPeId = RegInit(0.U(p.peIdWidth.W)) - - val recoveryRequest = Mux( - recoveryScanState === OooRobRecoveryScanState.Idle, - io.recoveryPrepare.bits, - retainedRecoveryRequest) - val recoveryMember = recoveryRequest.rename.key.member - val recoveryStid = recoveryMember.group.stid - val recoveryStidInRange = recoveryStid < p.stidCount.U - val safeRecoveryStid = Mux(recoveryStidInRange, recoveryStid, 0.U) - val recoveryOfferExact = io.recoveryPrepare.valid && - io.recoveryPrepare.bits.asUInt === recoveryRequest.asUInt - val recoveryTargetsStid = - (io.recoveryPrepare.valid || - recoveryScanState =/= OooRobRecoveryScanState.Idle) && - recoveryStidInRange && recoveryMember.group.valid && recoveryMember.bid.valid - val recoveryCommitConflict = WireDefault(false.B) - - val publishStid = io.publish.bits.reservation.transaction.plan.stid - val publishStidInRange = publishStid < p.stidCount.U - val safePublishStid = Mux(publishStidInRange, publishStid, 0.U) - val publishGroupCount = io.publish.bits.reservation.transaction.plan.groupCount - val publishGroupCountInRange = publishGroupCount.orR && - publishGroupCount <= p.instructionDecodeWidth.U - val liveTailSum = headSlot(safePublishStid).pad(occupiedWidth + 1) +& - occupied(safePublishStid).pad(occupiedWidth + 1) - val liveTailWrap = liveTailSum >= p.robGroupsPerStid.U - val liveTailSlot = liveTailSum(p.ridSlotWidth - 1, 0) - val liveTailGeneration = headGeneration(safePublishStid) + liveTailWrap.asUInt - val tailAfterSum = liveTailSlot +& publishGroupCount - val tailAfterWrap = tailAfterSum >= p.robGroupsPerStid.U - val hasPublicationCapacity = - occupied(safePublishStid).pad(occupiedWidth + 1) + - publishGroupCount.pad(occupiedWidth + 1) <= p.robGroupsPerStid.U - val expectedGroupMask = - ((1.U((p.instructionDecodeWidth + 1).W) << publishGroupCount) - 1.U)( - p.instructionDecodeWidth - 1, 0) - val publicationIdentityExact = - io.publish.bits.reservation.transaction.plan.peId === - io.publish.bits.reservation.transaction.decoded.peId && - publishStid === io.publish.bits.reservation.transaction.decoded.stid && - io.publish.bits.reservation.transaction.plan.epoch === - io.publish.bits.reservation.transaction.decoded.epoch - - val groupRequiredProofs = Wire(Vec(p.instructionDecodeWidth, - UInt(OooNonFlushProof.Count.W))) - val groupNonFlushNever = Wire(Vec(p.instructionDecodeWidth, Bool())) - val groupLogicalRequiredProofs = Wire(Vec(p.instructionDecodeWidth, - Vec(p.decodedUopWidth, UInt(OooNonFlushProof.Count.W)))) - val groupLogicalNonFlushNever = Wire(Vec(p.instructionDecodeWidth, - UInt(p.decodedUopWidth.W))) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = io.publish.bits.reservation.transaction.groups(groupIndex) - val decoded = io.publish.bits.reservation.transaction.decoded - val logicalNever = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val member = group.logicalUopMask(uopIndex) - val uop = decoded.uops(uopIndex) - val exceptionRequired = member && uop.valid && - (uop.recipe.mayTrap || uop.recipe.mayTrapLate) - val memoryRequired = member && uop.valid && - (uop.recipe.memoryRequestCount.orR || - uop.recipe.mayTrapLate || uop.recipe.sideEffectOwner === OooSideEffectOwner.Lsu.U) - val controlRequired = member && uop.valid && - (uop.identity.boundary.start || uop.identity.boundary.stop || - uop.recipe.mayRedirect || - uop.recipe.requiresTargetValidation || - uop.recipe.sideEffectOwner === OooSideEffectOwner.Bctrl.U) - val serializationRequired = member && uop.valid && - (uop.recipe.nonspeculative || - uop.recipe.dispatchClass === OooDispatchClass.Sys.U || - uop.recipe.dispatchClass === OooDispatchClass.Cmd.U || - uop.recipe.sideEffectOwner === OooSideEffectOwner.Commit.U || - uop.recipe.sideEffectOwner === OooSideEffectOwner.Ctu.U) - groupLogicalRequiredProofs(groupIndex)(uopIndex) := Cat( - serializationRequired, controlRequired, memoryRequired, - exceptionRequired) - logicalNever(uopIndex) := member && - (!decoded.uopMask(uopIndex) || !uop.valid || !uop.recipe.valid || - uop.recipe.disposition === OooOpcodeDisposition.Illegal.U || - uop.recipe.sideEffectOwner === OooSideEffectOwner.Illegal.U) - } - groupRequiredProofs(groupIndex) := - groupLogicalRequiredProofs(groupIndex).reduce(_ | _) - groupLogicalNonFlushNever(groupIndex) := logicalNever.asUInt - groupNonFlushNever(groupIndex) := group.preciseTrap || - !group.logicalUopMask.orR || logicalNever.asUInt.orR - } - - val targetExact = Wire(Vec(p.instructionDecodeWidth, Bool())) - val targetFree = Wire(Vec(p.instructionDecodeWidth, Bool())) - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = io.publish.bits.reservation.transaction.groups(groupIndex) - val binding = io.publish.bits.bindings(groupIndex) - val decoded = io.publish.bits.reservation.transaction.decoded - val active = groupIndex.U < publishGroupCount - val targetRow = rowAt(safePublishStid, group.key.ridSlot) - val expectedSlotSum = - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridSlot +& groupIndex.U - val expectedWrap = expectedSlotSum >= p.robGroupsPerStid.U - val memberMask = - ((1.U((p.maxOrdinaryUopsPerGroup + 1).W) << group.physicalMemberCount) - 1.U)( - p.maxOrdinaryUopsPerGroup - 1, 0) - val templateContinuationMask = VecInit((0 until p.decodedUopWidth).map { uopIndex => - val uop = decoded.uops(uopIndex) - group.logicalUopMask(uopIndex) && uop.valid && - uop.identity.templateValid && uop.identity.key.uopCount > 1.U && - (uop.identity.key.uopOrdinal +& 1.U) < uop.identity.key.uopCount - }).asUInt - val internalTemplateContinuation = group.logicalUopMask.orR && - (group.logicalUopMask & ~templateContinuationMask) === 0.U - targetExact(groupIndex) := - group.valid === active && binding.valid === active && (!active || ( - group.key.valid && - group.key.peId === io.publish.bits.reservation.transaction.plan.peId && - group.key.stid === publishStid && - group.key.ridSlot === expectedSlotSum(p.ridSlotWidth - 1, 0) && - group.key.ridGeneration === - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridGeneration + - expectedWrap.asUInt && - binding.brob.valid && binding.brob.bid.valid && - group.physicalMemberCount.orR && - group.physicalMemberCount <= p.maxOrdinaryUopsPerGroup.U && - (group.architecturalParentCount.orR || internalTemplateContinuation) && - group.architecturalParentCount <= p.maxInstPerRobGroup.U && - (binding.initiallyCompletedMembers & ~memberMask) === 0.U)) - targetFree(groupIndex) := !active || !targetRow.valid - } - val publicationExact = publishStidInRange && publishGroupCountInRange && - hasPublicationCapacity && - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.valid && - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.peId === - io.publish.bits.reservation.transaction.plan.peId && - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.stid === publishStid && - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridSlot === liveTailSlot && - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridGeneration === - liveTailGeneration && - (!occupied(safePublishStid).orR || - io.publish.bits.reservation.transaction.plan.peId === headPeId(safePublishStid)) && - io.publish.bits.reservation.tailAfter.valid && - io.publish.bits.reservation.tailAfter.peId === - io.publish.bits.reservation.transaction.plan.peId && - io.publish.bits.reservation.tailAfter.stid === publishStid && - io.publish.bits.reservation.tailAfter.ridSlot === - tailAfterSum(p.ridSlotWidth - 1, 0) && - io.publish.bits.reservation.tailAfter.ridGeneration === - liveTailGeneration + tailAfterWrap.asUInt && - io.publish.bits.reservation.transaction.groupMask === expectedGroupMask && - publicationIdentityExact && targetExact.reduce(_ && _) - val allTargetsFree = targetFree.reduce(_ && _) - val recoveryBlocksPublish = recoveryTargetsStid && - publishStid === recoveryStid - io.publish.ready := publicationExact && allTargetsFree && - !recoveryBlocksPublish - val publishFire = io.publish.valid && io.publish.ready - - io.publicationRejected.valid := io.publish.valid && !io.publish.ready - io.publicationRejected.bits.stid := publishStid - io.publicationRejected.bits.transactionId := - io.publish.bits.reservation.transaction.plan.transactionId - io.publicationRejected.bits.groupMask := - io.publish.bits.reservation.transaction.groupMask - - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val group = io.publish.bits.reservation.transaction.groups(groupIndex) - val binding = io.publish.bits.bindings(groupIndex) - when(publishFire && group.valid) { - val row = rowAt(publishStid, group.key.ridSlot) - row.valid := true.B - row.key := group.key - row.transactionId := io.publish.bits.reservation.transaction.plan.transactionId - row.publicationEpoch := - io.publish.bits.reservation.transaction.plan.epoch - row.claimEpoch := io.publish.bits.reservation.claimEpoch - row.brob := binding.brob - row.brobAllocated := binding.brobAllocated - row.brobImplicitCloseValid := binding.brobImplicitCloseValid - row.brobImplicitClose := binding.brobImplicitClose - row.pcBase := binding.pcBase - row.pcBaseAllocated := binding.pcBaseAllocated - row.pcImplicitCloseValid := binding.pcImplicitCloseValid - row.pcImplicitClose := binding.pcImplicitClose - row.residentGeneration := binding.residentGeneration - row.logicalUopMask := group.logicalUopMask - row.physicalMemberCount := group.physicalMemberCount - row.pMapQRows := group.pMapQRows - row.completedMembers := binding.initiallyCompletedMembers - row.faultedMembers := 0.U - row.memberFaultCauses.foreach(_ := 0.U) - row.architecturalParentCount := group.architecturalParentCount - row.boundaryStart := group.boundaryStart - row.boundaryStop := group.boundaryStop - row.releasePcBase := group.releasePcBase - row.preciseTrap := group.preciseTrap - row.nonFlushRequiredProofs := groupRequiredProofs(groupIndex) - row.nonFlushObservedProofs := 0.U - row.nonFlushNever := groupNonFlushNever(groupIndex) - row.logicalBoundaryStart := VecInit((0 until p.decodedUopWidth).map { - uopIndex => group.logicalUopMask(uopIndex) && - io.publish.bits.reservation.transaction.decoded.uops(uopIndex) - .identity.boundary.start - }).asUInt - row.logicalBoundaryStop := VecInit((0 until p.decodedUopWidth).map { - uopIndex => group.logicalUopMask(uopIndex) && - io.publish.bits.reservation.transaction.decoded.uops(uopIndex) - .identity.boundary.stop - }).asUInt - row.logicalReleasePcBase := VecInit((0 until p.decodedUopWidth).map { - uopIndex => - val uop = io.publish.bits.reservation.transaction.decoded.uops(uopIndex) - group.logicalUopMask(uopIndex) && - uop.identity.parents.zipWithIndex.map { case (parent, parentIndex) => - parentIndex.U < uop.identity.parentCount && parent.key.valid && - parent.traceOwner && parent.prediction.valid && - parent.prediction.taken - }.reduce(_ || _) - }).asUInt - row.logicalPreciseTrap := VecInit((0 until p.decodedUopWidth).map { - uopIndex => group.logicalUopMask(uopIndex) && - io.publish.bits.reservation.transaction.decoded.uops(uopIndex) - .preciseTrap - }).asUInt - row.logicalNonFlushNever := groupLogicalNonFlushNever(groupIndex) - row.memoryOrderValid := binding.memoryOrderValid - row.memoryBefore := binding.memoryBefore - row.memoryAfter := binding.memoryAfter - row.logicalMemoryAfter := binding.logicalMemoryAfter - for (uopIndex <- 0 until p.decodedUopWidth) { - val decoded = io.publish.bits.reservation.transaction.decoded - val uop = decoded.uops(uopIndex) - val logicalMember = group.logicalUopMask(uopIndex) - val parentCount = PopCount(uop.identity.parents.zipWithIndex.map { - case (parent, parentIndex) => - parentIndex.U < uop.identity.parentCount && parent.key.valid && - parent.traceOwner - }) - val pMapQRows = PopCount(uop.destinations.map { destination => - destination.valid && - destination.kind === linxcore.common.DestinationKind.Gpr - }) - row.logicalMemberBase(uopIndex) := Mux(logicalMember, - io.publish.bits.reservation.transaction.uopMemberBase(uopIndex), 0.U) - row.logicalMemberCount(uopIndex) := Mux(logicalMember, - uop.plannedChildCount, 0.U) - row.logicalPMapQRows(uopIndex) := Mux(logicalMember, pMapQRows, 0.U) - row.logicalArchitecturalParentCount(uopIndex) := - Mux(logicalMember, parentCount, 0.U) - row.logicalNonFlushRequiredProofs(uopIndex) := - groupLogicalRequiredProofs(groupIndex)(uopIndex) - } - } - } - - // Recovery is a retained two-pass walk over the physical bank slices. The - // first pass validates the complete old window and finds one exact pivot; - // the second pass writes the ordered killed-row records into private plan - // state. No ROB row or pointer mutates before the common recovery fire. - val recoveryScanOffsets = Wire(Vec( - p.robRecoveryScanGroupsPerCycleEffective, - UInt(p.nonFlushPrefixCountWidth.W))) - val recoveryScanRows = Wire(Vec( - p.robRecoveryScanGroupsPerCycleEffective, - new OooRobPhysicalGroupRecord(p))) - val recoveryScanWindowExact = Wire(Vec( - p.robRecoveryScanGroupsPerCycleEffective, Bool())) - val recoveryScanMatches = Wire(Vec( - p.robRecoveryScanGroupsPerCycleEffective, Bool())) - for (scanLane <- 0 until p.robRecoveryScanGroupsPerCycleEffective) { - val offsetWide = recoveryScanCursor * - p.robRecoveryScanGroupsPerCycleEffective.U + scanLane.U - val offset = Wire(UInt(p.nonFlushPrefixCountWidth.W)) - offset := offsetWide - val slotSum = recoverySnapshotHeadSlot +& offset - val wraps = slotSum >= p.robGroupsPerStid.U - val row = rowAt(safeRecoveryStid, - slotSum(p.ridSlotWidth - 1, 0)) - val active = offset < recoverySnapshotOccupied - val windowExact = !active || ( - row.valid && row.key.valid && - row.key.peId === recoverySnapshotHeadPeId && - row.key.stid === recoveryStid && - row.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && - row.key.ridGeneration === - recoverySnapshotHeadGeneration + wraps.asUInt) - recoveryScanOffsets(scanLane) := offset - recoveryScanRows(scanLane) := row - recoveryScanWindowExact(scanLane) := windowExact - recoveryScanMatches(scanLane) := active && windowExact && - row.key.asUInt === recoveryMember.group.asUInt && row.brob.valid && - row.brob.bid.asUInt === recoveryMember.bid.asUInt && - row.brob.generation === recoveryMember.brobGeneration && - row.residentGeneration === recoveryMember.residentGeneration && - row.transactionId === recoveryRequest.rename.key.transactionId && - row.publicationEpoch === recoveryRequest.rename.key.epoch - } - val recoverySliceWindowExact = recoveryScanWindowExact.asUInt.andR - val recoverySliceMatchCount = PopCount(recoveryScanMatches) - val recoveryNextExactMatchCount = recoveryExactMatchCountReg + - recoverySliceMatchCount - val recoveryNextWindowExact = recoveryWindowExactReg && - recoverySliceWindowExact - val recoverySliceHasMatch = recoveryScanMatches.asUInt.orR - val recoverySlicePivotIndex = - if (p.robRecoveryScanGroupsPerCycleEffective == 1) 0.U - else PriorityEncoder(recoveryScanMatches.asUInt) - val recoveryCandidatePivot = Mux( - recoverySliceHasMatch, - recoveryScanRows(recoverySlicePivotIndex), - recoveryPivotReg) - val recoveryCandidatePivotOffset = Mux( - recoverySliceHasMatch, - recoveryScanOffsets(recoverySlicePivotIndex), - recoveryPivotOffsetReg) - val recoveryScanLast = recoveryScanCursor === - (p.robRecoveryScanCycles - 1).U - - val recoveryPivot = recoveryCandidatePivot - val recoveryPivotOffset = recoveryCandidatePivotOffset - val recoveryTriggerEnd = recoveryMember.memberIndex +& - recoveryRequest.triggerMemberCount - val recoveryTriggerShape = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - recoveryTriggerShape(uopIndex) := recoveryPivot.logicalUopMask(uopIndex) && - recoveryPivot.logicalMemberCount(uopIndex).orR && - recoveryPivot.logicalMemberBase(uopIndex) === recoveryMember.memberIndex && - recoveryPivot.logicalMemberCount(uopIndex) === - recoveryRequest.triggerMemberCount - } - val recoveryTriggerShapeCount = PopCount(recoveryTriggerShape) - val recoveryTriggerShapeExact = recoveryTriggerShapeCount === 1.U && - recoveryRequest.triggerMemberCount.orR && - recoveryTriggerEnd <= recoveryPivot.physicalMemberCount - val recoverySurvivingMemberCountWide = recoveryMember.memberIndex +& - Mux(recoveryRequest.rename.killTrigger, 0.U, - recoveryRequest.triggerMemberCount) - val recoverySurvivingMemberCount = - recoverySurvivingMemberCountWide(p.robMemberCountWidth - 1, 0) - val recoverySurvivingPivotValid = recoverySurvivingMemberCount.orR - val recoverySurvivingLogical = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val logicalEnd = recoveryPivot.logicalMemberBase(uopIndex) +& - recoveryPivot.logicalMemberCount(uopIndex) - recoverySurvivingLogical(uopIndex) := - recoveryPivot.logicalUopMask(uopIndex) && - recoveryPivot.logicalMemberCount(uopIndex).orR && - logicalEnd <= recoverySurvivingMemberCountWide - } - val recoverySurvivingPivot = Wire(new OooRobPhysicalGroupRecord(p)) - recoverySurvivingPivot := recoveryPivot - recoverySurvivingPivot.valid := recoverySurvivingPivotValid - recoverySurvivingPivot.logicalUopMask := recoverySurvivingLogical.asUInt - recoverySurvivingPivot.physicalMemberCount := recoverySurvivingMemberCount - val recoverySurvivingMemberMask = - ((1.U((p.maxOrdinaryUopsPerGroup + 1).W) << - recoverySurvivingMemberCount) - 1.U)( - p.maxOrdinaryUopsPerGroup - 1, 0) - recoverySurvivingPivot.completedMembers := - recoveryPivot.completedMembers & recoverySurvivingMemberMask - recoverySurvivingPivot.faultedMembers := - recoveryPivot.faultedMembers & recoverySurvivingMemberMask - for (memberIndex <- 0 until p.maxOrdinaryUopsPerGroup) { - recoverySurvivingPivot.memberFaultCauses(memberIndex) := Mux( - recoverySurvivingMemberMask(memberIndex), - recoveryPivot.memberFaultCauses(memberIndex), 0.U) - } - recoverySurvivingPivot.pMapQRows := (0 until p.decodedUopWidth).map { - uopIndex => Mux(recoverySurvivingLogical(uopIndex), - recoveryPivot.logicalPMapQRows(uopIndex), 0.U) - }.reduce(_ +& _) - recoverySurvivingPivot.architecturalParentCount := - (0 until p.decodedUopWidth).map { uopIndex => - Mux(recoverySurvivingLogical(uopIndex), - recoveryPivot.logicalArchitecturalParentCount(uopIndex), 0.U) - }.reduce(_ +& _) - recoverySurvivingPivot.boundaryStart := - (recoveryPivot.logicalBoundaryStart & - recoverySurvivingLogical.asUInt).orR - recoverySurvivingPivot.boundaryStop := - (recoveryPivot.logicalBoundaryStop & - recoverySurvivingLogical.asUInt).orR - recoverySurvivingPivot.releasePcBase := - (recoveryPivot.logicalReleasePcBase & - recoverySurvivingLogical.asUInt).orR - recoverySurvivingPivot.preciseTrap := - (recoveryPivot.logicalPreciseTrap & - recoverySurvivingLogical.asUInt).orR || - (recoveryPivot.faultedMembers & recoverySurvivingMemberMask).orR - recoverySurvivingPivot.nonFlushRequiredProofs := - (0 until p.decodedUopWidth).map { uopIndex => - Mux(recoverySurvivingLogical(uopIndex), - recoveryPivot.logicalNonFlushRequiredProofs(uopIndex), 0.U) - }.reduce(_ | _) - recoverySurvivingPivot.nonFlushObservedProofs := 0.U - recoverySurvivingPivot.nonFlushNever := - (recoveryPivot.logicalNonFlushNever & - recoverySurvivingLogical.asUInt).orR - recoverySurvivingPivot.logicalBoundaryStart := - recoveryPivot.logicalBoundaryStart & recoverySurvivingLogical.asUInt - recoverySurvivingPivot.logicalBoundaryStop := - recoveryPivot.logicalBoundaryStop & recoverySurvivingLogical.asUInt - recoverySurvivingPivot.logicalReleasePcBase := - recoveryPivot.logicalReleasePcBase & recoverySurvivingLogical.asUInt - recoverySurvivingPivot.logicalPreciseTrap := - recoveryPivot.logicalPreciseTrap & recoverySurvivingLogical.asUInt - recoverySurvivingPivot.logicalNonFlushNever := - recoveryPivot.logicalNonFlushNever & recoverySurvivingLogical.asUInt - val recoverySurvivingMemoryAfter = Wire(new OooMemoryIdState(p)) - recoverySurvivingMemoryAfter := recoveryPivot.memoryBefore - for (uopIndex <- 0 until p.decodedUopWidth) { - when(recoverySurvivingLogical(uopIndex)) { - recoverySurvivingMemoryAfter := - recoveryPivot.logicalMemoryAfter(uopIndex) - } - } - recoverySurvivingPivot.memoryAfter := recoverySurvivingMemoryAfter - for (uopIndex <- 0 until p.decodedUopWidth) { - when(!recoverySurvivingLogical(uopIndex)) { - recoverySurvivingPivot.logicalMemberBase(uopIndex) := 0.U - recoverySurvivingPivot.logicalMemberCount(uopIndex) := 0.U - recoverySurvivingPivot.logicalPMapQRows(uopIndex) := 0.U - recoverySurvivingPivot.logicalArchitecturalParentCount(uopIndex) := 0.U - recoverySurvivingPivot.logicalNonFlushRequiredProofs(uopIndex) := 0.U - recoverySurvivingPivot.logicalMemoryAfter(uopIndex) := - 0.U.asTypeOf(new OooMemoryIdState(p)) - } - } - val recoveryNewOccupied = recoveryPivotOffset + - recoverySurvivingPivotValid.asUInt - val recoveryKilledGroupCount = recoverySnapshotOccupied - - recoveryNewOccupied - val recoveryFirstKilledSlotSum = recoverySnapshotHeadSlot +& - recoveryNewOccupied - val recoveryFirstKilledWrap = - recoveryFirstKilledSlotSum >= p.robGroupsPerStid.U - val recoveryOldTailSlotSum = recoverySnapshotHeadSlot +& - recoverySnapshotOccupied - val recoveryOldTailWrap = recoveryOldTailSlotSum >= p.robGroupsPerStid.U - - val recoveryPlanBase = Wire(new OooRobRecoveryPlan(p)) - recoveryPlanBase := 0.U.asTypeOf(recoveryPlanBase) - recoveryPlanBase.valid := false.B - recoveryPlanBase.request := recoveryRequest - recoveryPlanBase.oldHead.valid := recoverySnapshotOccupied.orR - recoveryPlanBase.oldHead.peId := recoverySnapshotHeadPeId - recoveryPlanBase.oldHead.stid := recoveryStid - recoveryPlanBase.oldHead.ridSlot := recoverySnapshotHeadSlot - recoveryPlanBase.oldHead.ridGeneration := recoverySnapshotHeadGeneration - recoveryPlanBase.oldOccupied := recoverySnapshotOccupied - recoveryPlanBase.pivot := recoveryPivot - recoveryPlanBase.pivotOffset := recoveryPivotOffset - recoveryPlanBase.survivingPivotValid := recoverySurvivingPivotValid - recoveryPlanBase.survivingPivot := recoverySurvivingPivot - recoveryPlanBase.newOccupied := recoveryNewOccupied - recoveryPlanBase.survivingTailValid := recoveryNewOccupied.orR - recoveryPlanBase.survivingTail := Mux( - recoverySurvivingPivotValid, - recoverySurvivingPivot, - 0.U.asTypeOf(new OooRobPhysicalGroupRecord(p))) - recoveryPlanBase.firstKilledGroup.valid := recoveryKilledGroupCount.orR - recoveryPlanBase.firstKilledGroup.peId := recoverySnapshotHeadPeId - recoveryPlanBase.firstKilledGroup.stid := recoveryStid - recoveryPlanBase.firstKilledGroup.ridSlot := - recoveryFirstKilledSlotSum(p.ridSlotWidth - 1, 0) - recoveryPlanBase.firstKilledGroup.ridGeneration := - recoverySnapshotHeadGeneration + recoveryFirstKilledWrap.asUInt - recoveryPlanBase.killedGroupCount := recoveryKilledGroupCount - recoveryPlanBase.killedGroupMask := - ((1.U((p.robGroupsPerStid + 1).W) << recoveryKilledGroupCount) - 1.U)( - p.robGroupsPerStid - 1, 0) - recoveryPlanBase.oldTail.valid := true.B - recoveryPlanBase.oldTail.peId := recoverySnapshotHeadPeId - recoveryPlanBase.oldTail.stid := recoveryStid - recoveryPlanBase.oldTail.ridSlot := - recoveryOldTailSlotSum(p.ridSlotWidth - 1, 0) - recoveryPlanBase.oldTail.ridGeneration := - recoverySnapshotHeadGeneration + recoveryOldTailWrap.asUInt - recoveryPlanBase.newTail.valid := true.B - recoveryPlanBase.newTail.peId := recoverySnapshotHeadPeId - recoveryPlanBase.newTail.stid := recoveryStid - recoveryPlanBase.newTail.ridSlot := - recoveryFirstKilledSlotSum(p.ridSlotWidth - 1, 0) - recoveryPlanBase.newTail.ridGeneration := - recoverySnapshotHeadGeneration + recoveryFirstKilledWrap.asUInt - - val recoveryCaptureWellFormed = io.recoveryPrepare.valid && - recoveryStidInRange && recoveryMember.group.valid && - recoveryMember.bid.valid - val recoveryCaptureMalformed = io.recoveryPrepare.valid && - !recoveryCaptureWellFormed - val recoveryOfferChanged = - recoveryScanState =/= OooRobRecoveryScanState.Idle && - recoveryScanState =/= OooRobRecoveryScanState.Rejected && - io.recoveryPrepare.valid && !recoveryOfferExact - val recoveryFindRejected = - recoveryScanState === OooRobRecoveryScanState.FindPivot && - recoveryScanLast && (!recoveryNextWindowExact || - recoveryNextExactMatchCount =/= 1.U || - !recoveryTriggerShapeExact) - val recoveryBuildRejected = - recoveryScanState === OooRobRecoveryScanState.BuildPlan && - recoveryScanLast && !recoveryNextWindowExact - - io.recoveryPrepared := retainedRecoveryPlan - io.recoveryPrepareReady := - recoveryScanState === OooRobRecoveryScanState.Prepared && - recoveryOfferExact && retainedRecoveryPlan.valid && - !recoveryCommitConflict - io.recoveryPrepared.valid := io.recoveryPrepareReady - io.recoveryRejected.valid := recoveryCaptureMalformed || - recoveryOfferChanged || recoveryFindRejected || recoveryBuildRejected || - (recoveryScanState === OooRobRecoveryScanState.Rejected && - io.recoveryPrepare.valid) - io.recoveryRejected.bits.requested := recoveryRequest - io.recoveryRejected.bits.occupied := recoverySnapshotOccupied - io.recoveryRejected.bits.exactMatchCount := Mux( - recoveryScanState === OooRobRecoveryScanState.FindPivot, - recoveryNextExactMatchCount, - recoveryExactMatchCountReg) - io.recoveryRejected.bits.triggerShapeMatch := recoveryTriggerShapeExact - - when(recoveryScanState === OooRobRecoveryScanState.Idle && - recoveryCaptureWellFormed && !recoveryCommitConflict) { - retainedRecoveryRequest := io.recoveryPrepare.bits - retainedRecoveryPlan := 0.U.asTypeOf(retainedRecoveryPlan) - recoverySnapshotOccupied := occupied(safeRecoveryStid) - recoverySnapshotHeadSlot := headSlot(safeRecoveryStid) - recoverySnapshotHeadGeneration := headGeneration(safeRecoveryStid) - recoverySnapshotHeadPeId := headPeId(safeRecoveryStid) - recoveryExactMatchCountReg := 0.U - recoveryWindowExactReg := true.B - recoveryPivotReg := 0.U.asTypeOf(recoveryPivotReg) - recoveryPivotOffsetReg := 0.U - recoveryScanCursor := 0.U - recoveryScanState := OooRobRecoveryScanState.FindPivot - }.elsewhen(recoveryScanState =/= OooRobRecoveryScanState.Idle && - !io.recoveryPrepare.valid) { - // Prepare-valid withdrawal is the owner-abort signal. Both passes have - // touched private metadata only, so cancellation needs no physical undo. - recoveryScanState := OooRobRecoveryScanState.Idle - }.elsewhen(recoveryOfferChanged) { - recoveryScanState := OooRobRecoveryScanState.Rejected - }.elsewhen(recoveryScanState === OooRobRecoveryScanState.FindPivot) { - recoveryExactMatchCountReg := recoveryNextExactMatchCount - recoveryWindowExactReg := recoveryNextWindowExact - when(recoverySliceHasMatch) { - recoveryPivotReg := recoveryCandidatePivot - recoveryPivotOffsetReg := recoveryCandidatePivotOffset - } - when(recoveryScanLast) { - when(recoveryNextWindowExact && - recoveryNextExactMatchCount === 1.U && - recoveryTriggerShapeExact) { - retainedRecoveryPlan := recoveryPlanBase - recoveryWindowExactReg := true.B - recoveryScanCursor := 0.U - recoveryScanState := OooRobRecoveryScanState.BuildPlan - }.otherwise { - recoveryScanState := OooRobRecoveryScanState.Rejected - } - }.otherwise { - recoveryScanCursor := recoveryScanCursor + 1.U - } - }.elsewhen(recoveryScanState === OooRobRecoveryScanState.BuildPlan) { - recoveryWindowExactReg := recoveryNextWindowExact - for (scanLane <- 0 until p.robRecoveryScanGroupsPerCycleEffective) { - val offset = recoveryScanOffsets(scanLane) - val killed = offset >= retainedRecoveryPlan.newOccupied && - offset < recoverySnapshotOccupied - val killedIndex = offset - retainedRecoveryPlan.newOccupied - when(killed && recoveryScanWindowExact(scanLane)) { - retainedRecoveryPlan.killedGroups( - killedIndex(p.ridSlotWidth - 1, 0)) := - recoveryScanRows(scanLane) - } - val survivingTail = retainedRecoveryPlan.survivingTailValid && - !retainedRecoveryPlan.survivingPivotValid && - offset === retainedRecoveryPlan.newOccupied - 1.U - when(survivingTail && recoveryScanWindowExact(scanLane)) { - retainedRecoveryPlan.survivingTail := recoveryScanRows(scanLane) - } - } - when(recoveryScanLast) { - when(recoveryNextWindowExact) { - retainedRecoveryPlan.valid := true.B - recoveryScanState := OooRobRecoveryScanState.Prepared - }.otherwise { - recoveryScanState := OooRobRecoveryScanState.Rejected - } - }.otherwise { - recoveryScanCursor := recoveryScanCursor + 1.U - } - }.elsewhen(recoveryScanState === OooRobRecoveryScanState.Prepared && - io.recoveryFire) { - recoveryScanState := OooRobRecoveryScanState.Idle - } - - val completionStid = io.completion.bits.key.group.stid - val completionStidInRange = completionStid < p.stidCount.U - val safeCompletionStid = Mux(completionStidInRange, completionStid, 0.U) - val completionSlot = io.completion.bits.key.group.ridSlot - val liveCompletionRow = rowAt(safeCompletionStid, completionSlot) - val completionMemberInRange = - io.completion.bits.key.memberIndex < liveCompletionRow.physicalMemberCount && - io.completion.bits.key.memberIndex < p.maxOrdinaryUopsPerGroup.U - val completionBit = UIntToOH( - io.completion.bits.key.memberIndex, - p.maxOrdinaryUopsPerGroup) - val completionExact = completionStidInRange && liveCompletionRow.valid && - liveCompletionRow.brob.valid && liveCompletionRow.brob.bid.valid && - io.completion.bits.key.group.asUInt === liveCompletionRow.key.asUInt && - io.completion.bits.key.bid.asUInt === liveCompletionRow.brob.bid.asUInt && - io.completion.bits.key.brobGeneration === liveCompletionRow.brob.generation && - io.completion.bits.key.residentGeneration === liveCompletionRow.residentGeneration && - completionMemberInRange && - !(liveCompletionRow.completedMembers & completionBit).orR - - val recoveryBlocksCompletion = recoveryTargetsStid && - completionStid === recoveryStid - io.completion.ready := !recoveryBlocksCompletion - val completionFire = io.completion.valid && io.completion.ready - when(completionFire && completionExact) { - rowAt(completionStid, completionSlot).completedMembers := - liveCompletionRow.completedMembers | completionBit - when(io.completion.bits.faultValid) { - rowAt(completionStid, completionSlot).faultedMembers := - liveCompletionRow.faultedMembers | completionBit - for (memberIndex <- 0 until p.maxOrdinaryUopsPerGroup) { - when(io.completion.bits.key.memberIndex === memberIndex.U) { - rowAt(completionStid, completionSlot).memberFaultCauses(memberIndex) := - io.completion.bits.faultCause - } - } - rowAt(completionStid, completionSlot).preciseTrap := true.B - } - } - io.completionRejected.valid := completionFire && !completionExact - io.completionRejected.bits.requested := io.completion.bits.key - io.completionRejected.bits.occupied := completionStidInRange && liveCompletionRow.valid - io.completionRejected.bits.live := liveCompletionRow - - val evidenceStid = io.nonFlushEvidence.bits.key.group.stid - val evidenceStidInRange = evidenceStid < p.stidCount.U - val safeEvidenceStid = Mux(evidenceStidInRange, evidenceStid, 0.U) - val evidenceSlot = io.nonFlushEvidence.bits.key.group.ridSlot - val liveEvidenceRow = rowAt(safeEvidenceStid, evidenceSlot) - val evidenceMemberInRange = - io.nonFlushEvidence.bits.key.memberIndex < liveEvidenceRow.physicalMemberCount && - io.nonFlushEvidence.bits.key.memberIndex < p.maxOrdinaryUopsPerGroup.U - val newEvidenceProofs = io.nonFlushEvidence.bits.proofs & - liveEvidenceRow.nonFlushRequiredProofs & - ~liveEvidenceRow.nonFlushObservedProofs - val evidenceExact = evidenceStidInRange && liveEvidenceRow.valid && - !liveEvidenceRow.nonFlushNever && liveEvidenceRow.brob.valid && - liveEvidenceRow.brob.bid.valid && - io.nonFlushEvidence.bits.key.group.asUInt === liveEvidenceRow.key.asUInt && - io.nonFlushEvidence.bits.key.bid.asUInt === liveEvidenceRow.brob.bid.asUInt && - io.nonFlushEvidence.bits.key.brobGeneration === liveEvidenceRow.brob.generation && - io.nonFlushEvidence.bits.key.residentGeneration === - liveEvidenceRow.residentGeneration && evidenceMemberInRange && - newEvidenceProofs.orR - - val recoveryBlocksEvidence = recoveryTargetsStid && - evidenceStid === recoveryStid - io.nonFlushEvidence.ready := !recoveryBlocksEvidence - val evidenceFire = io.nonFlushEvidence.valid && io.nonFlushEvidence.ready - when(evidenceFire && evidenceExact) { - rowAt(evidenceStid, evidenceSlot).nonFlushObservedProofs := - liveEvidenceRow.nonFlushObservedProofs | newEvidenceProofs - } - io.nonFlushEvidenceRejected.valid := evidenceFire && !evidenceExact - io.nonFlushEvidenceRejected.bits.requested := io.nonFlushEvidence.bits - io.nonFlushEvidenceRejected.bits.occupied := - evidenceStidInRange && liveEvidenceRow.valid - io.nonFlushEvidenceRejected.bits.live := liveEvidenceRow - - def groupComplete(row: OooRobPhysicalGroupRecord): Bool = { - val expected = - ((1.U((p.maxOrdinaryUopsPerGroup + 1).W) << row.physicalMemberCount) - 1.U)( - p.maxOrdinaryUopsPerGroup - 1, 0) - row.valid && row.physicalMemberCount.orR && - (row.completedMembers & expected) === expected - } - - def groupNonFlushSafe(row: OooRobPhysicalGroupRecord): Bool = - row.valid && !row.nonFlushNever && - (row.nonFlushObservedProofs & row.nonFlushRequiredProofs) === - row.nonFlushRequiredProofs - - val rotatedNonFlushDirty = Wire(Vec(p.stidCount, Bool())) - for (offset <- 0 until p.stidCount) { - val index = if (p.stidCount == 1) 0.U else - (nonFlushScanRrStart + offset.U)(p.stidWidth - 1, 0) - val recoveryFence = recoveryTargetsStid && recoveryStid === index - rotatedNonFlushDirty(offset) := nonFlushScanDirty(index) && - !io.interruptPending(index) && !recoveryFence - } - val anyNonFlushDirty = rotatedNonFlushDirty.asUInt.orR - val selectedNonFlushOffset = if (p.stidCount == 1) 0.U else - PriorityEncoder(rotatedNonFlushDirty.asUInt) - val selectedNonFlushStid = if (p.stidCount == 1) 0.U(p.stidWidth.W) else - (nonFlushScanRrStart + selectedNonFlushOffset)(p.stidWidth - 1, 0) - - val nonFlushScanPrefix = Wire(Vec( - p.robNonFlushScanGroupsPerCycleEffective + 1, - UInt(p.nonFlushPrefixCountWidth.W))) - nonFlushScanPrefix(0) := nonFlushScanCandidate - for (scanLane <- 0 until p.robNonFlushScanGroupsPerCycleEffective) { - val offsetWide = nonFlushScanCursor +& scanLane.U - val offset = Wire(UInt(p.nonFlushPrefixCountWidth.W)) - offset := offsetWide - val slotSum = nonFlushScanSnapshotHeadSlot +& offset - val wraps = slotSum >= p.robGroupsPerStid.U - val row = rowAt(nonFlushScanStid, - slotSum(p.ridSlotWidth - 1, 0)) - val exactRow = row.valid && row.key.valid && - row.key.peId === nonFlushScanSnapshotHeadPeId && - row.key.stid === nonFlushScanStid && - row.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && - row.key.ridGeneration === - nonFlushScanSnapshotHeadGeneration + wraps.asUInt - val canExtend = nonFlushScanPrefix(scanLane) === offset && - offset < nonFlushScanSnapshotOccupied && exactRow && - groupNonFlushSafe(row) - nonFlushScanPrefix(scanLane + 1) := Mux( - canExtend, offset + 1.U, nonFlushScanPrefix(scanLane)) - } - val nonFlushScanNextCandidate = - nonFlushScanPrefix(p.robNonFlushScanGroupsPerCycleEffective) - val nonFlushScanSliceEndWide = nonFlushScanCursor +& - p.robNonFlushScanGroupsPerCycleEffective.U - val nonFlushScanSliceEnd = Wire(UInt(p.nonFlushPrefixCountWidth.W)) - nonFlushScanSliceEnd := Mux( - nonFlushScanSliceEndWide >= nonFlushScanSnapshotOccupied, - nonFlushScanSnapshotOccupied, - nonFlushScanSliceEndWide) - val nonFlushScanDone = - nonFlushScanNextCandidate =/= nonFlushScanSliceEnd || - nonFlushScanSliceEnd === nonFlushScanSnapshotOccupied - val nonFlushScanSnapshotExact = - occupied(nonFlushScanStid) === nonFlushScanSnapshotOccupied && - headSlot(nonFlushScanStid) === nonFlushScanSnapshotHeadSlot && - headGeneration(nonFlushScanStid) === - nonFlushScanSnapshotHeadGeneration && - headEpoch(nonFlushScanStid) === nonFlushScanSnapshotHeadEpoch && - headPeId(nonFlushScanStid) === nonFlushScanSnapshotHeadPeId && - nonFlushAuthorized(nonFlushScanStid) === - nonFlushScanSnapshotAuthorized && - nonFlushEpoch(nonFlushScanStid) === nonFlushScanSnapshotEpoch - - val commitCountByStid = Wire(Vec(p.stidCount, UInt(p.robReleaseCountWidth.W))) - for (stid <- 0 until p.stidCount) { - val prefix = Wire(Vec(p.retireGroupWidth + 1, UInt(p.robReleaseCountWidth.W))) - prefix(0) := 0.U - for (offset <- 0 until p.retireGroupWidth) { - val slotSum = headSlot(stid) +& offset.U - val wraps = slotSum >= p.robGroupsPerStid.U - val row = rowAt(stid.U, slotSum(p.ridSlotWidth - 1, 0)) - val expectedGeneration = headGeneration(stid) + wraps.asUInt - val exactHead = row.key.valid && row.key.peId === headPeId(stid) && - row.key.stid === stid.U && - row.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && - row.key.ridGeneration === expectedGeneration - val canExtend = prefix(offset) === offset.U && - offset.U < occupied(stid) && exactHead && groupComplete(row) - prefix(offset + 1) := Mux(canExtend, (offset + 1).U, prefix(offset)) - } - commitCountByStid(stid) := Mux( - recoveryTargetsStid && recoveryStid === stid.U, - 0.U, - prefix(p.retireGroupWidth)) - } - - val commitReadPending = RegInit(false.B) - val commitReadRelease = RegInit( - 0.U.asTypeOf(new OooRobGroupRelease(p))) - val commitPending = RegInit(false.B) - val commitRow = Reg(new OooRobCommitBatch(p)) - val rrStart = RegInit(0.U(p.stidWidth.W)) - val rotatedEligible = Wire(Vec(p.stidCount, Bool())) - for (offset <- 0 until p.stidCount) { - val index = if (p.stidCount == 1) 0.U else (rrStart + offset.U)(p.stidWidth - 1, 0) - rotatedEligible(offset) := commitCountByStid(index).orR - } - val anyEligible = rotatedEligible.asUInt.orR - val selectedOffset = if (p.stidCount == 1) 0.U else PriorityEncoder(rotatedEligible.asUInt) - val selectedStid = - if (p.stidCount == 1) 0.U(p.stidWidth.W) - else (rrStart + selectedOffset)(p.stidWidth - 1, 0) - - when(!commitReadPending && !commitPending && anyEligible) { - val selectedCount = commitCountByStid(selectedStid) - commitReadPending := true.B - commitReadRelease := 0.U.asTypeOf(commitReadRelease) - commitReadRelease.firstGroup.valid := true.B - commitReadRelease.firstGroup.peId := headPeId(selectedStid) - commitReadRelease.firstGroup.stid := selectedStid - commitReadRelease.firstGroup.ridSlot := headSlot(selectedStid) - commitReadRelease.firstGroup.ridGeneration := - headGeneration(selectedStid) - commitReadRelease.headEpoch := headEpoch(selectedStid) - commitReadRelease.groupCount := selectedCount - } - - val commitReadStid = commitReadRelease.firstGroup.stid - val commitReadHeadExact = commitReadRelease.firstGroup.valid && - commitReadStid < p.stidCount.U && - commitReadRelease.firstGroup.peId === headPeId(commitReadStid) && - commitReadRelease.firstGroup.ridSlot === headSlot(commitReadStid) && - commitReadRelease.firstGroup.ridGeneration === - headGeneration(commitReadStid) && - commitReadRelease.headEpoch === headEpoch(commitReadStid) && - commitReadRelease.groupCount.orR && - commitReadRelease.groupCount <= occupied(commitReadStid) - - when(commitReadPending) { - assert(commitReadHeadExact, - "grouped-ROB commit payload read requires the retained exact head token") - commitReadPending := false.B - commitPending := true.B - commitRow := 0.U.asTypeOf(commitRow) - commitRow.release := commitReadRelease - for (offset <- 0 until p.retireGroupWidth) { - val slotSum = commitReadRelease.firstGroup.ridSlot +& offset.U - when(offset.U < commitReadRelease.groupCount) { - commitRow.groups(offset) := - rowAt(commitReadStid, slotSum(p.ridSlotWidth - 1, 0)) - } - } - } - - io.commit.valid := commitPending - io.commit.bits := commitRow - val commitFire = io.commit.valid && io.commit.ready - recoveryCommitConflict := - (commitReadPending && commitReadStid === recoveryStid) || - (commitPending && commitRow.release.firstGroup.stid === recoveryStid) - when(commitFire) { - val stid = commitRow.release.firstGroup.stid - val count = commitRow.release.groupCount - for (offset <- 0 until p.retireGroupWidth) { - val slotSum = commitRow.release.firstGroup.ridSlot +& offset.U - when(offset.U < count) { - rowAt(stid, slotSum(p.ridSlotWidth - 1, 0)) := - 0.U.asTypeOf(new OooRobPhysicalGroupRecord(p)) - } - } - val headSum = headSlot(stid) +& count - val wraps = headSum >= p.robGroupsPerStid.U - occupied(stid) := occupied(stid) - count - headSlot(stid) := headSum(p.ridSlotWidth - 1, 0) - headGeneration(stid) := headGeneration(stid) + wraps.asUInt - headEpoch(stid) := headEpoch(stid) + 1.U - commitPending := false.B - rrStart := - (if (p.stidCount == 1) 0.U else (stid + 1.U)(p.stidWidth - 1, 0)) - } - - for (stid <- 0 until p.stidCount) { - val commitHere = commitFire && - commitRow.release.firstGroup.stid === stid.U - val committedCount = commitRow.release.groupCount - val authorizedAfterCommit = Mux( - committedCount >= nonFlushAuthorized(stid), - 0.U, - nonFlushAuthorized(stid) - committedCount) - when(commitHere) { - nonFlushAuthorized(stid) := authorizedAfterCommit - nonFlushEpoch(stid) := nonFlushEpoch(stid) + 1.U - } - } - - for (stid <- 0 until p.stidCount) { - val publishedHere = publishFire && publishStid === stid.U - when(publishedHere) { - when(occupied(stid) === 0.U) { - headSlot(stid) := io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridSlot - headGeneration(stid) := - io.publish.bits.reservation.transaction.plan.firstVirtualGroup.ridGeneration - headPeId(stid) := io.publish.bits.reservation.transaction.plan.peId - } - occupied(stid) := occupied(stid) + publishGroupCount - } - when(publishedHere && commitFire && commitRow.release.firstGroup.stid === stid.U) { - occupied(stid) := occupied(stid) + publishGroupCount - commitRow.release.groupCount - when(occupied(stid) === commitRow.release.groupCount) { - headPeId(stid) := io.publish.bits.reservation.transaction.plan.peId - } - } - } - - val recoveryApply = io.recoveryFire && io.recoveryPrepareReady - val nonFlushOwnerEvent = Wire(Vec(p.stidCount, Bool())) - for (stid <- 0 until p.stidCount) { - nonFlushOwnerEvent(stid) := - (publishFire && publishStid === stid.U) || - (evidenceFire && evidenceExact && evidenceStid === stid.U) || - (commitFire && commitRow.release.firstGroup.stid === stid.U) || - (recoveryApply && safeRecoveryStid === stid.U) - } - val nonFlushScanRecoveryFence = recoveryTargetsStid && - recoveryStid === nonFlushScanStid - val nonFlushScanMustRestart = nonFlushScanActive && ( - nonFlushOwnerEvent(nonFlushScanStid) || - io.interruptPending(nonFlushScanStid) || - nonFlushScanRecoveryFence || !nonFlushScanSnapshotExact) - - when(!nonFlushScanActive && anyNonFlushDirty) { - nonFlushScanActive := true.B - nonFlushScanStid := selectedNonFlushStid - nonFlushScanCursor := 0.U - nonFlushScanCandidate := 0.U - nonFlushScanSnapshotOccupied := occupied(selectedNonFlushStid) - nonFlushScanSnapshotHeadSlot := headSlot(selectedNonFlushStid) - nonFlushScanSnapshotHeadGeneration := headGeneration(selectedNonFlushStid) - nonFlushScanSnapshotHeadEpoch := headEpoch(selectedNonFlushStid) - nonFlushScanSnapshotHeadPeId := headPeId(selectedNonFlushStid) - nonFlushScanSnapshotAuthorized := nonFlushAuthorized(selectedNonFlushStid) - nonFlushScanSnapshotEpoch := nonFlushEpoch(selectedNonFlushStid) - }.elsewhen(nonFlushScanMustRestart) { - nonFlushScanActive := false.B - nonFlushScanRrStart := - (if (p.stidCount == 1) 0.U else - (nonFlushScanStid + 1.U)(p.stidWidth - 1, 0)) - }.elsewhen(nonFlushScanActive && nonFlushScanDone) { - nonFlushScanActive := false.B - nonFlushScanDirty(nonFlushScanStid) := false.B - nonFlushScanRrStart := - (if (p.stidCount == 1) 0.U else - (nonFlushScanStid + 1.U)(p.stidWidth - 1, 0)) - when(nonFlushScanNextCandidate =/= - nonFlushAuthorized(nonFlushScanStid)) { - nonFlushAuthorized(nonFlushScanStid) := nonFlushScanNextCandidate - nonFlushEpoch(nonFlushScanStid) := - nonFlushEpoch(nonFlushScanStid) + 1.U - } - }.elsewhen(nonFlushScanActive) { - nonFlushScanCursor := nonFlushScanSliceEnd - nonFlushScanCandidate := nonFlushScanNextCandidate - } - - for (stid <- 0 until p.stidCount) { - when(nonFlushOwnerEvent(stid)) { - nonFlushScanDirty(stid) := true.B - } - } - - when(io.recoveryFire) { - assert(io.recoveryPrepare.valid && io.recoveryPrepareReady && - io.recoveryPrepared.valid, - "ROB recovery fire requires the same exact prepared suffix plan") - } - when(recoveryApply) { - for (offset <- 0 until p.robGroupsPerStid) { - val slotSum = retainedRecoveryPlan.oldHead.ridSlot +& offset.U - when(offset.U >= retainedRecoveryPlan.newOccupied && - offset.U < retainedRecoveryPlan.oldOccupied) { - rowAt(safeRecoveryStid, slotSum(p.ridSlotWidth - 1, 0)) := - 0.U.asTypeOf(new OooRobPhysicalGroupRecord(p)) - } - } - when(retainedRecoveryPlan.survivingPivotValid && - retainedRecoveryPlan.survivingPivot.physicalMemberCount < - retainedRecoveryPlan.pivot.physicalMemberCount) { - rowAt(safeRecoveryStid, retainedRecoveryPlan.pivot.key.ridSlot) := - retainedRecoveryPlan.survivingPivot - } - occupied(safeRecoveryStid) := retainedRecoveryPlan.newOccupied - nonFlushAuthorized(safeRecoveryStid) := 0.U - nonFlushEpoch(safeRecoveryStid) := - nonFlushEpoch(safeRecoveryStid) + 1.U - } - - io.occupiedGroups := occupied - io.headSlot := headSlot - io.headGeneration := headGeneration - io.headEpoch := headEpoch - for (stid <- 0 until p.stidCount) { - val window = io.nonFlushWindows(stid) - window.valid := occupied(stid).orR - window.stid := stid.U - window.head.valid := occupied(stid).orR - window.head.peId := headPeId(stid) - window.head.stid := stid.U - window.head.ridSlot := headSlot(stid) - window.head.ridGeneration := headGeneration(stid) - window.prefixCount := nonFlushAuthorized(stid) - window.epoch := nonFlushEpoch(stid) - assert(nonFlushAuthorized(stid) <= occupied(stid), - "non-flush prefix cannot extend beyond the live ROB window") - } - - when(publishFire) { - assert(publishGroupCount <= p.robGroupsPerStid.U) - } - when(commitPending && !io.commit.ready) { - assert(io.commit.bits.asUInt === commitRow.asUInt, - "retained grouped-ROB commit must remain stable under backpressure") - } -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooStoreCommitAuthorizationOwner.scala b/chisel/src/main/scala/linxcore/ooo/OooStoreCommitAuthorizationOwner.scala new file mode 100644 index 00000000..3383b186 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/OooStoreCommitAuthorizationOwner.scala @@ -0,0 +1,78 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Decoupled, PopCount, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface.{CommitTxn, StoreCommitAuthorizationTxn} + +class OooStoreCommitAuthorizationOwnerIO(val p: CoreParams) extends Bundle { + val commit = Flipped(Valid(new CommitTxn(p))) + val canAccept = Output(Bool()) + val applied = Input(Bool()) + val storeCommit = Decoupled(new StoreCommitAuthorizationTxn(p)) + val drained = Output(Bool()) +} + +/** Atomically captures every store beat on the architectural commit fire, then + * serializes the accepted tokens to LSU. Before `applied`, this owner has no + * externally visible store side effect. Once captured, recovery cannot cancel + * or regenerate a committed token. + */ +class OooStoreCommitAuthorizationOwner(val p: CoreParams) extends Module { + val io = IO(new OooStoreCommitAuthorizationOwnerIO(p)) + private val entries = p.ooo.storeCommitBufferEntries + private val candidateSlots = p.widths.retireWidth * + p.maxMemoryRequestsPerInstruction + private val indexWidth = log2Ceil(entries) + private val countWidth = log2Ceil(entries + 1) + + val payloads = Wire(Vec(candidateSlots, + new StoreCommitAuthorizationTxn(p))) + val candidates = Wire(Vec(candidateSlots, Bool())) + for (slot <- 0 until candidateSlots) { + val lane = slot / p.maxMemoryRequestsPerInstruction + val beat = slot % p.maxMemoryRequestsPerInstruction + val entry = io.commit.bits.entries(lane) + candidates(slot) := io.commit.valid && lane.U < io.commit.bits.count && + entry.memoryValid && entry.memoryStore && + beat.U < entry.memoryOrder.requestCount + payloads(slot) := 0.U.asTypeOf(payloads(slot)) + payloads(slot).rob := entry.rob + payloads(slot).transaction := entry.memory.transaction + payloads(slot).logicalFirstLsid := entry.memoryOrder.firstLsid + payloads(slot).logicalFirstStoreId := entry.memoryOrder.firstSid + payloads(slot).requestCount := entry.memoryOrder.requestCount + payloads(slot).beat := beat.U + } + + val buffer = Reg(Vec(entries, new StoreCommitAuthorizationTxn(p))) + val head = RegInit(0.U(indexWidth.W)) + val tail = RegInit(0.U(indexWidth.W)) + val count = RegInit(0.U(countWidth.W)) + val candidateCount = PopCount(candidates) + + io.canAccept := count +& candidateCount <= entries.U + io.storeCommit.valid := count =/= 0.U + io.storeCommit.bits := buffer(head) + io.drained := count === 0.U + + when(io.applied) { + assert(io.commit.valid, + "store-token capture requires the matching retained commit transaction") + assert(io.canAccept, + "architectural commit requires capacity for its complete store-token batch") + for (slot <- 0 until candidateSlots) { + when(candidates(slot)) { + val rank = if (slot == 0) 0.U else PopCount(candidates.take(slot)) + buffer((tail + rank)(indexWidth - 1, 0)) := payloads(slot) + } + } + tail := (tail + candidateCount)(indexWidth - 1, 0) + } + when(io.storeCommit.fire) { + head := head + 1.U + } + + count := count + Mux(io.applied, candidateCount, 0.U) - + io.storeCommit.fire.asUInt +} diff --git a/chisel/src/main/scala/linxcore/ooo/OooStqRecoveryProjection.scala b/chisel/src/main/scala/linxcore/ooo/OooStqRecoveryProjection.scala index 207b3664..1e404d46 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooStqRecoveryProjection.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooStqRecoveryProjection.scala @@ -3,15 +3,19 @@ package linxcore.ooo import chisel3._ import linxcore.lsu.{STQEntryBankRow, STQEntryStatus} +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan, + RecoveryPlanContract} class OooStqRecoveryProjectionIO( - val p: OooParams, + val core: CoreParams, val stqEntries: Int) extends Bundle { - val recoveryValid = Input(Bool()) - val recovery = Input(new OooResidencyRecoveryPlan(p)) + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + val prepareValid = Input(Bool()) + val prepare = Input(new RecoveryPlan(core)) val rows = Input(Vec(stqEntries, new STQEntryBankRow( - p.robGroupsPerStid, + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, @@ -29,14 +33,19 @@ class OooStqRecoveryProjectionIO( val rejected = Output(Bool()) } -/** Projects the ROB-authorized residency suffix onto canonical STQ rows. - * Compatibility rows without an exact owner remain on the legacy flush path. - */ +/** Projects one canonical ROB-authorized suffix onto canonical STQ rows. */ class OooStqRecoveryProjection( - val p: OooParams = OooParams(), + val core: CoreParams, val stqEntries: Int = 16) extends Module { - val io = IO(new OooStqRecoveryProjectionIO(p, stqEntries)) + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + OooRecoveryMembership.requireCompatible(p, core) + val io = IO(new OooStqRecoveryProjectionIO(core, stqEntries)) + + val planLegal = io.prepareValid && + io.prepare.phase === RecoveryPhase.Prepare && + io.prepare.trigger.stid < p.stidCount.U && + RecoveryPlanContract.legalSuffixWindow(io.prepare) val killed = Wire(Vec(stqEntries, Bool())) val malformed = Wire(Vec(stqEntries, Bool())) @@ -60,17 +69,17 @@ class OooStqRecoveryProjection( val ownerConsistent = owner.valid && owner.nativeBidValid && owner.peId === row.peId && owner.stid === row.stid && row.storeIdFullValid - val targetScope = io.recoveryValid && io.recovery.valid && row.valid && - owner.valid && row.stid === io.recovery.oldHead.stid && - row.peId === io.recovery.oldHead.peId + val targetScope = planLegal && row.valid && + row.stid === io.prepare.trigger.stid && + row.peId === io.prepare.trigger.peId malformed(index) := targetScope && !ownerConsistent killed(index) := targetScope && ownerConsistent && - OooRecoveryMembership.memberKilled(p, io.recovery, member) + OooRecoveryMembership.memberKilled(p, core, io.prepare, member) blocked(index) := killed(index) && (row.status =/= STQEntryStatus.Wait) } - val rejected = malformed.asUInt.orR + val rejected = (io.prepareValid && !planLegal) || malformed.asUInt.orR io.freeMask := Mux(rejected, 0.U, VecInit((0 until stqEntries).map(index => killed(index) && !blocked(index))).asUInt) diff --git a/chisel/src/main/scala/linxcore/ooo/OooStqReservationProjection.scala b/chisel/src/main/scala/linxcore/ooo/OooStqReservationProjection.scala index 8d8408a7..ead7366b 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooStqReservationProjection.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooStqReservationProjection.scala @@ -16,7 +16,7 @@ class OooStqReservationProjectionIO( val reserveMask = Output(UInt(p.maxMemoryRequestsPerInstruction.W)) val reserve = Output(Vec(p.maxMemoryRequestsPerInstruction, new STQStoreRequest( - p.robGroupsPerStid, + p.robIdentityGroupsPerStid, peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, tidWidth = p.stidWidth, @@ -28,13 +28,14 @@ class OooStqReservationProjectionIO( memberIndexWidth = p.robMemberIndexWidth, residentGenerationWidth = p.residentGenerationWidth, leaseGenerationWidth = p.executeSlotGenerationWidth, - physicalStqEntries = stqEntries))) + physicalStqEntries = stqEntries, + transactionIdWidth = p.transactionIdWidth))) val rejected = Output(Bool()) } /** Converts the address child of one published store into an atomic STQ - * reservation batch. Physical AGU/STD children have consecutive ROB member - * indices; the STQ owner is the common logical first member. + * reservation batch. Physical AGU/STD children share one ROB identity and + * use `childIndex` only to identify their execution half. */ class OooStqReservationProjection( val p: OooParams = OooParams(), @@ -63,7 +64,7 @@ class OooStqReservationProjection( private def projectBid(target: linxcore.rob.ROBID): Unit = { val valueWidth = log2Ceil(target.entries) target.valid := io.input.member.bid.valid - target.value := io.input.member.bid.value(valueWidth - 1, 0) + target.value := io.input.member.bid.value.pad(valueWidth)(valueWidth - 1, 0) target.wrap := io.input.member.brobGeneration(0) } @@ -80,8 +81,6 @@ class OooStqReservationProjection( val pairShapeExact = (io.input.recipe.recipeKind === OooOpcodeRecipeKind.PairStore.U) === (io.input.memoryOrder.requestCount === 2.U) - val logicalMemberNoUnderflow = - io.input.member.memberIndex >= io.input.childIndex val exactShape = io.input.schedule.valid && io.input.member.group.valid && @@ -91,7 +90,7 @@ class OooStqReservationProjection( io.input.memoryOrder.isStore && !io.input.memoryOrder.isLoad && requestCountLegal && pairShapeExact && storeRecipe && (io.input.reservation.uopClass === OooUopClass.Agu) && - (io.input.childIndex === 0.U) && logicalMemberNoUnderflow + (io.input.childIndex === 0.U) io.reserveValid := io.inputValid && exactShape io.reserveMask := Mux(io.reserveValid, @@ -103,6 +102,7 @@ class OooStqReservationProjection( val fullLsid = io.input.memoryOrder.firstLsid + beat.U val fullStoreId = io.input.memoryOrder.firstTypeId + beat.U req := 0.U.asTypeOf(req) + req.transactionId := io.input.transactionId req.storeType := STQStoreType.All req.peId := io.input.peId req.stid := io.input.stid @@ -127,8 +127,7 @@ class OooStqReservationProjection( req.exactOwner.brobGeneration := io.input.member.brobGeneration req.exactOwner.ridSlot := io.input.member.group.ridSlot req.exactOwner.ridGeneration := io.input.member.group.ridGeneration - req.exactOwner.memberIndex := - io.input.member.memberIndex - io.input.childIndex + req.exactOwner.memberIndex := io.input.member.memberIndex req.exactOwner.residentGeneration := io.input.member.residentGeneration req.tSeq.valid := false.B diff --git a/chisel/src/main/scala/linxcore/ooo/OooTURename.scala b/chisel/src/main/scala/linxcore/ooo/OooTURename.scala deleted file mode 100644 index 541dc4eb..00000000 --- a/chisel/src/main/scala/linxcore/ooo/OooTURename.scala +++ /dev/null @@ -1,873 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.util.{Cat, Decoupled, PopCount, Valid, is, switch} -import linxcore.common.{DestinationKind, OperandClass} - -object OooTURecoveryState extends ChiselEnum { - val Idle, WaitSources, Complete = Value -} - -class OooTURenameIO(val p: OooParams = OooParams()) extends Bundle { - val reservePrepare = Flipped(Valid(new OooD2GroupedTransaction(p))) - val reserveReady = Output(Bool()) - val reservation = Output(new OooTUReservation(p)) - val reserveFire = Input(Bool()) - val cancel = Input(Vec(p.stidCount, Bool())) - - val publicationPrepare = Flipped(Valid(new OooTUPublicationRequest(p))) - val publicationReady = Output(Bool()) - val prepared = Output(new OooTURenamePreparedTransaction(p)) - val publishFire = Input(Bool()) - - val retireCommand = Flipped(Decoupled(new OooTURetireCommand(p))) - val blockCommit = Flipped(Decoupled(new OooTULocalBlockCommit(p))) - - val recoveryAuthorize = Flipped(Decoupled( - new OooRenameRecoveryRequest(p))) - val recoverySource = Flipped(Decoupled(new OooRenameRecoverySource(p))) - val recoverySourcesDone = Input(Bool()) - val recoveryComplete = Output(Bool()) - val recoveryFinish = Input(Bool()) - val recoveryBusy = Output(Bool()) - val recoveryStid = Output(UInt(p.stidWidth.W)) - val recoveryRejected = Valid(new OooTURenameRecoveryReject(p)) - - val provisional = Output(Vec(p.stidCount, new OooTUReservation(p))) - val tMapQUsed = Output(Vec(p.stidCount, UInt(p.tuMapQCountWidth.W))) - val uMapQUsed = Output(Vec(p.stidCount, UInt(p.tuMapQCountWidth.W))) - val tPhysicalUsed = Output(Vec(p.stidCount, - UInt(p.countWidth(p.tPhysRegs).W))) - val uPhysicalUsed = Output(Vec(p.stidCount, - UInt(p.countWidth(p.uPhysRegs).W))) - val reserveRejected = Valid(new OooTURenamePrepareReject(p)) - val publicationRejected = Valid(new OooTURenamePublishReject(p)) -} - -/** Per-STID T/U sequential rename owner. - * - * T and U deliberately share no P SMAP, CMAP, free list, or PTag staging - * state. A relative source names `tail - (relativeIndex + 1)` in its own - * namespace. Each destination claims the current local sequence and the next - * circular physical tag. The complete bundle is previewed oldest-to-youngest - * at D3 reserve, retained as one provisional lease, and becomes visible only - * on the common S1 publication fire. - * - * A sibling relation owner drives exact mark/deallocation and post-clean - * block commands. This module remains the sole MapQ/physical-tag owner and - * never guesses that P commit or ROB slot reuse releases local state. - */ -class OooTURename(val p: OooParams = OooParams()) extends Module { - val io = IO(new OooTURenameIO(p)) - - private val seqPackedWidth = p.localSeqGenerationWidth + p.tuMapQIndexWidth - private val destinationIndexWidth = math.max(1, - chisel3.util.log2Ceil(p.maxDestinationOperands)) - private val sourceSlotCount = p.decodedUopWidth * p.maxSourceOperands - - private def zeroRow: OooTUMapQEntry = - 0.U.asTypeOf(new OooTUMapQEntry(p)) - - private def packSeq(seq: OooLocalSeq): UInt = - Cat(seq.generation, seq.index) - - private def driveSeq(seq: OooLocalSeq, packed: UInt, valid: Bool): Unit = { - seq.valid := valid - seq.index := packed(p.tuMapQIndexWidth - 1, 0) - seq.generation := packed(seqPackedWidth - 1, p.tuMapQIndexWidth) - } - - private def kindIsT(kind: DestinationKind.Type): Bool = - kind === DestinationKind.T - - private def kindIsU(kind: DestinationKind.Type): Bool = - kind === DestinationKind.U - - private def incrementPhysical(ptr: UInt, increment: UInt, entries: Int): UInt = { - val indexWidth = chisel3.util.log2Ceil(entries) - val next = ptr + increment - if (indexWidth == p.localTagWidth) { - next(p.localTagWidth - 1, 0) - } else { - Cat(0.U((p.localTagWidth - indexWidth).W), next(indexWidth - 1, 0)) - } - } - - private def decrementPhysical(ptr: UInt, decrement: UInt, entries: Int): UInt = { - val indexWidth = chisel3.util.log2Ceil(entries) - val previous = ptr - decrement - if (indexWidth == p.localTagWidth) { - previous(p.localTagWidth - 1, 0) - } else { - Cat(0.U((p.localTagWidth - indexWidth).W), - previous(indexWidth - 1, 0)) - } - } - - val tMapQ = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.tuMapQDepthPerStid)(zeroRow))))) - val uMapQ = RegInit(VecInit(Seq.fill(p.stidCount)( - VecInit(Seq.fill(p.tuMapQDepthPerStid)(zeroRow))))) - val tTail = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(seqPackedWidth.W)))) - val uTail = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(seqPackedWidth.W)))) - val tHead = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(seqPackedWidth.W)))) - val uHead = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(seqPackedWidth.W)))) - val tNextPhysical = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.localTagWidth.W)))) - val uNextPhysical = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.localTagWidth.W)))) - val tCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.tuMapQCountWidth.W)))) - val uCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.tuMapQCountWidth.W)))) - val tPhysicalCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.countWidth(p.tPhysRegs).W)))) - val uPhysicalCount = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U(p.countWidth(p.uPhysRegs).W)))) - val provisional = RegInit(VecInit(Seq.fill(p.stidCount)( - 0.U.asTypeOf(new OooTUReservation(p))))) - val recoveryState = RegInit(OooTURecoveryState.Idle) - val recoveryRequest = RegInit( - 0.U.asTypeOf(new OooRenameRecoveryRequest(p))) - val recoveryRejectValid = RegInit(false.B) - val recoveryRejectRequest = RegInit( - 0.U.asTypeOf(new OooRenameRecoveryRequest(p))) - val recoveryRejectTTail = RegInit(0.U(seqPackedWidth.W)) - val recoveryRejectUTail = RegInit(0.U(seqPackedWidth.W)) - val recoveryRejectTCount = RegInit(0.U(p.tuMapQCountWidth.W)) - val recoveryRejectUCount = RegInit(0.U(p.tuMapQCountWidth.W)) - val recoveryActiveStid = recoveryRequest.key.member.group.stid - io.recoveryBusy := recoveryState =/= OooTURecoveryState.Idle - io.recoveryStid := Mux(io.recoveryBusy, recoveryActiveStid, 0.U) - - val reservePlan = io.reservePrepare.bits.plan - val reserveDecoded = io.reservePrepare.bits.decoded - val reserveStid = reservePlan.stid - val reserveStidInRange = reserveStid < p.stidCount.U - val safeReserveStid = Mux(reserveStidInRange, reserveStid, 0.U) - - val destinationActive = Wire(Vec(p.tuAllocationWidth, Bool())) - val destinationIsT = Wire(Vec(p.tuAllocationWidth, Bool())) - val destinationIsU = Wire(Vec(p.tuAllocationWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth; - destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - val uop = reserveDecoded.uops(uopIndex) - val destination = uop.destinations(destinationIndex) - val active = reserveDecoded.uopMask(uopIndex) && uop.valid && - destination.valid && (kindIsT(destination.kind) || - kindIsU(destination.kind)) - destinationActive(flatIndex) := active - destinationIsT(flatIndex) := active && kindIsT(destination.kind) - destinationIsU(flatIndex) := active && kindIsU(destination.kind) - } - val requestedT = PopCount(destinationIsT) - val requestedU = PopCount(destinationIsU) - val publicationStidPreview = io.publicationPrepare.bits.stid - val publicationStidPreviewInRange = - publicationStidPreview < p.stidCount.U - val replacesPublishingLease = io.publishFire && - io.publicationPrepare.valid && publicationStidPreviewInRange && - publicationStidPreview === reserveStid - val publishingLease = provisional(safeReserveStid) - val publishingT = Mux(replacesPublishingLease, - publishingLease.tAllocationCount, 0.U) - val publishingU = Mux(replacesPublishingLease, - publishingLease.uAllocationCount, 0.U) - val freeTEntries = p.tuMapQDepthPerStid.U - - (tCount(safeReserveStid) +& publishingT) - val freeUEntries = p.tuMapQDepthPerStid.U - - (uCount(safeReserveStid) +& publishingU) - val freeTPhysical = p.tPhysRegs.U - - (tPhysicalCount(safeReserveStid) +& publishingT) - val freeUPhysical = p.uPhysRegs.U - - (uPhysicalCount(safeReserveStid) +& publishingU) - - io.reservation := 0.U.asTypeOf(io.reservation) - io.reservation.valid := io.reservePrepare.valid - io.reservation.peId := reservePlan.peId - io.reservation.stid := reserveStid - io.reservation.epoch := reservePlan.epoch - io.reservation.transactionId := reservePlan.transactionId - io.reservation.uopMask := reserveDecoded.uopMask - io.reservation.tAllocationCount := requestedT - io.reservation.uAllocationCount := requestedU - io.reservation.allocationMask := destinationActive.asUInt - - val sourceUnderflow = Wire(Vec(sourceSlotCount, Bool())) - val allocationValid = Wire(Vec(p.tuAllocationWidth, Bool())) - val allocationKind = Wire(Vec(p.tuAllocationWidth, DestinationKind())) - val allocationSeqPacked = Wire(Vec(p.tuAllocationWidth, - UInt(seqPackedWidth.W))) - val allocationPhysical = Wire(Vec(p.tuAllocationWidth, - UInt(p.localTagWidth.W))) - allocationValid := VecInit(Seq.fill(p.tuAllocationWidth)(false.B)) - allocationKind := VecInit(Seq.fill(p.tuAllocationWidth)(DestinationKind.None)) - allocationSeqPacked := VecInit(Seq.fill(p.tuAllocationWidth)(0.U)) - allocationPhysical := VecInit(Seq.fill(p.tuAllocationWidth)(0.U)) - - var virtualTSeq = (tTail(safeReserveStid) + publishingT)( - seqPackedWidth - 1, 0) - var virtualUSeq = (uTail(safeReserveStid) + publishingU)( - seqPackedWidth - 1, 0) - var virtualTPhysical = incrementPhysical(tNextPhysical(safeReserveStid), - publishingT, p.tPhysRegs) - var virtualUPhysical = incrementPhysical(uNextPhysical(safeReserveStid), - publishingU, p.uPhysRegs) - var olderTAllocations = 0.U(p.destinationDemandWidth.W) - var olderUAllocations = 0.U(p.destinationDemandWidth.W) - - for (uopIndex <- 0 until p.decodedUopWidth) { - val uop = reserveDecoded.uops(uopIndex) - val activeUop = reserveDecoded.uopMask(uopIndex) && uop.valid - val groupIndex = io.reservePrepare.bits.uopGroupIndex(uopIndex) - val groupIndexInRange = groupIndex < p.instructionDecodeWidth.U && - groupIndex < reservePlan.groupCount - val safeGroupIndex = Mux(groupIndexInRange, groupIndex, 0.U) - val group = io.reservePrepare.bits.groups(safeGroupIndex) - val member = io.reservation.members(uopIndex) - val memberEnd = io.reservePrepare.bits.uopMemberBase(uopIndex) +& - uop.plannedChildCount - member.valid := activeUop - member.group := group.key - member.memberIndex := io.reservePrepare.bits.uopMemberBase(uopIndex) - member.blockLast := activeUop && groupIndexInRange && - group.boundaryStop && memberEnd === group.physicalMemberCount - driveSeq(io.reservation.tSeqBefore(uopIndex), virtualTSeq, activeUop) - driveSeq(io.reservation.uSeqBefore(uopIndex), virtualUSeq, activeUop) - - for (sourceIndex <- 0 until p.maxSourceOperands) { - val flatSource = uopIndex * p.maxSourceOperands + sourceIndex - val source = uop.sources(sourceIndex) - val isT = activeUop && source.valid && - source.operandClass === OperandClass.T - val isU = activeUop && source.valid && - source.operandClass === OperandClass.U - val isLocal = isT || isU - val offset = source.relativeIndex +& 1.U - val offsetInRange = offset <= p.tuMapQDepthPerStid.U - val availableT = tCount(safeReserveStid) +& publishingT +& - olderTAllocations - val availableU = uCount(safeReserveStid) +& publishingU +& - olderUAllocations - val hasDepth = Mux(isT, offset <= availableT, - Mux(isU, offset <= availableU, false.B)) - val basePacked = Mux(isT, virtualTSeq, virtualUSeq) - val resolvedPacked = basePacked - offset - val resolvedIndex = resolvedPacked(p.tuMapQIndexWidth - 1, 0) - val baseRow = Mux(isT, - tMapQ(safeReserveStid)(resolvedIndex), - uMapQ(safeReserveStid)(resolvedIndex)) - var resolvedValid = baseRow.valid && - packSeq(baseRow.mapping.sequence) === resolvedPacked - var resolvedPhysical = baseRow.mapping.physicalTag - for (publishingFlat <- 0 until p.tuAllocationWidth) { - val publishingAllocation = publishingLease.allocations(publishingFlat) - val kindMatches = Mux(isT, - kindIsT(publishingAllocation.kind), - kindIsU(publishingAllocation.kind)) - val hit = replacesPublishingLease && publishingAllocation.valid && - kindMatches && - packSeq(publishingAllocation.mapping.sequence) === resolvedPacked - resolvedValid = Mux(hit, true.B, resolvedValid) - resolvedPhysical = Mux(hit, - publishingAllocation.mapping.physicalTag, resolvedPhysical) - } - for (olderFlat <- 0 until uopIndex * p.maxDestinationOperands) { - val kindMatches = Mux(isT, - kindIsT(allocationKind(olderFlat)), - kindIsU(allocationKind(olderFlat))) - val hit = allocationValid(olderFlat) && kindMatches && - allocationSeqPacked(olderFlat) === resolvedPacked - resolvedValid = Mux(hit, true.B, resolvedValid) - resolvedPhysical = Mux(hit, - allocationPhysical(olderFlat), resolvedPhysical) - } - - val mapping = io.reservation.sourceMappings(uopIndex)(sourceIndex) - mapping := 0.U.asTypeOf(mapping) - mapping.valid := isLocal && offsetInRange && hasDepth && resolvedValid - mapping.kind := Mux(isT, DestinationKind.T, DestinationKind.U) - mapping.relativeIndex := source.relativeIndex - driveSeq(mapping.sequence, resolvedPacked, isLocal) - mapping.physicalTag := resolvedPhysical - mapping.stid := reserveStid - mapping.epoch := reservePlan.epoch - sourceUnderflow(flatSource) := isLocal && - (!offsetInRange || !hasDepth || !resolvedValid) - } - - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - val destination = uop.destinations(destinationIndex) - val allocation = io.reservation.allocations(flatIndex) - val isT = destinationIsT(flatIndex) - val isU = destinationIsU(flatIndex) - val selectedSeq = Mux(isT, virtualTSeq, virtualUSeq) - val selectedPhysical = Mux(isT, - virtualTPhysical, virtualUPhysical) - - allocation := 0.U.asTypeOf(allocation) - allocation.valid := destinationActive(flatIndex) - allocation.kind := destination.kind - allocation.uopIndex := uopIndex.U - allocation.destinationIndex := destinationIndex.U(destinationIndexWidth.W) - allocation.relativeIndex := destination.relativeIndex - allocation.mapping.valid := destinationActive(flatIndex) - allocation.mapping.kind := destination.kind - allocation.mapping.relativeIndex := destination.relativeIndex - driveSeq(allocation.mapping.sequence, selectedSeq, - destinationActive(flatIndex)) - allocation.mapping.physicalTag := selectedPhysical - allocation.mapping.stid := reserveStid - allocation.mapping.epoch := reservePlan.epoch - - allocationValid(flatIndex) := destinationActive(flatIndex) - allocationKind(flatIndex) := destination.kind - allocationSeqPacked(flatIndex) := selectedSeq - allocationPhysical(flatIndex) := selectedPhysical - - val nextTSeq = virtualTSeq + isT.asUInt - val nextUSeq = virtualUSeq + isU.asUInt - virtualTSeq = nextTSeq(seqPackedWidth - 1, 0) - virtualUSeq = nextUSeq(seqPackedWidth - 1, 0) - virtualTPhysical = incrementPhysical( - virtualTPhysical, isT.asUInt, p.tPhysRegs) - virtualUPhysical = incrementPhysical( - virtualUPhysical, isU.asUInt, p.uPhysRegs) - olderTAllocations = olderTAllocations + isT.asUInt - olderUAllocations = olderUAllocations + isU.asUInt - } - } - - val identityExact = reservePlan.peId === reserveDecoded.peId && - reservePlan.stid === reserveDecoded.stid && - reservePlan.epoch === reserveDecoded.epoch && - reservePlan.uopMask === reserveDecoded.uopMask - val memberShapeExact = (0 until p.decodedUopWidth).map { uopIndex => - val uop = reserveDecoded.uops(uopIndex) - val activeUop = reserveDecoded.uopMask(uopIndex) && uop.valid - val groupIndex = io.reservePrepare.bits.uopGroupIndex(uopIndex) - val groupIndexInRange = groupIndex < p.instructionDecodeWidth.U && - groupIndex < reservePlan.groupCount - val safeGroupIndex = Mux(groupIndexInRange, groupIndex, 0.U) - val group = io.reservePrepare.bits.groups(safeGroupIndex) - val memberEnd = io.reservePrepare.bits.uopMemberBase(uopIndex) +& - uop.plannedChildCount - !activeUop || (groupIndexInRange && group.valid && group.key.valid && - group.key.peId === reservePlan.peId && - group.key.stid === reservePlan.stid && - group.logicalUopMask(uopIndex) && uop.plannedChildCount.orR && - memberEnd <= group.physicalMemberCount) - }.reduce(_ && _) - val demandExact = reservePlan.demand.tAllocations === requestedT && - reservePlan.demand.uAllocations === requestedU - val capacityAvailable = requestedT <= freeTEntries && - requestedU <= freeUEntries && requestedT <= freeTPhysical && - requestedU <= freeUPhysical - val provisionalAvailable = !provisional(safeReserveStid).valid || - io.cancel(safeReserveStid) || replacesPublishingLease - val sourceExact = !sourceUnderflow.asUInt.orR - val reserveExact = reserveStidInRange && identityExact && demandExact && - memberShapeExact - val reserveBlockedByRecovery = io.recoveryBusy && - reserveStid === recoveryActiveStid - - io.reserveReady := reserveExact && capacityAvailable && - provisionalAvailable && sourceExact && !reserveBlockedByRecovery - io.reservation.valid := io.reservePrepare.valid && io.reserveReady - io.reserveRejected.valid := io.reservePrepare.valid && !io.reserveReady - io.reserveRejected.bits.stid := reserveStid - io.reserveRejected.bits.transactionId := reservePlan.transactionId - io.reserveRejected.bits.requestedT := requestedT - io.reserveRejected.bits.requestedU := requestedU - io.reserveRejected.bits.freeTEntries := freeTEntries - io.reserveRejected.bits.freeUEntries := freeUEntries - io.reserveRejected.bits.freeTPhysical := freeTPhysical - io.reserveRejected.bits.freeUPhysical := freeUPhysical - io.reserveRejected.bits.sourceUnderflowMask := sourceUnderflow.asUInt - - val reserveFire = io.reserveFire && io.reservePrepare.valid && io.reserveReady - when(io.reserveFire) { - assert(io.reservePrepare.valid && io.reserveReady, - "T/U reserveFire requires one exact sequential allocation preview") - } - for (stid <- 0 until p.stidCount) { - when(io.cancel(stid)) { - provisional(stid) := 0.U.asTypeOf(provisional(stid)) - } - when(reserveFire && reserveStid === stid.U) { - provisional(stid) := io.reservation - } - } - - val publication = io.publicationPrepare.bits - val publicationStid = publication.stid - val publicationStidInRange = publicationStid < p.stidCount.U - val safePublicationStid = Mux(publicationStidInRange, publicationStid, 0.U) - val live = provisional(safePublicationStid) - val publicationDestinationActive = Wire(Vec(p.tuAllocationWidth, Bool())) - val publicationAllocationExact = Wire(Vec(p.tuAllocationWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth; - destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - val uop = publication.uops(uopIndex) - val destination = uop.destinations(destinationIndex) - publicationDestinationActive(flatIndex) := - publication.uopMask(uopIndex) && uop.valid && - destination.valid && (kindIsT(destination.kind) || - kindIsU(destination.kind)) - val allocation = live.allocations(flatIndex) - val physicalInRange = Mux(kindIsT(destination.kind), - allocation.mapping.physicalTag < p.tPhysRegs.U, - allocation.mapping.physicalTag < p.uPhysRegs.U) - publicationAllocationExact(flatIndex) := - Mux(publicationDestinationActive(flatIndex), - allocation.valid && allocation.mapping.valid && - allocation.kind === destination.kind && - allocation.mapping.kind === destination.kind && - allocation.uopIndex === uopIndex.U && - allocation.destinationIndex === destinationIndex.U && - allocation.relativeIndex === destination.relativeIndex && - allocation.mapping.relativeIndex === destination.relativeIndex && - allocation.mapping.sequence.valid && physicalInRange && - allocation.mapping.stid === publicationStid && - allocation.mapping.epoch === publication.epoch, - !allocation.valid && !allocation.mapping.valid) - } - val publicationSourceExact = (0 until p.decodedUopWidth).flatMap { uopIndex => - (0 until p.maxSourceOperands).map { sourceIndex => - val uop = publication.uops(uopIndex) - val source = uop.sources(sourceIndex) - val activeUop = publication.uopMask(uopIndex) && uop.valid - val local = activeUop && source.valid && - (kindIsT(source.kind) || kindIsU(source.kind)) - val mapping = live.sourceMappings(uopIndex)(sourceIndex) - Mux(local, - mapping.valid && mapping.kind === source.kind && - mapping.relativeIndex === source.relativeIndex && - mapping.sequence.valid && mapping.stid === publicationStid && - mapping.epoch === publication.epoch, - !mapping.valid) - } - }.reduce(_ && _) - val publicationIdentityExact = publicationStidInRange && live.valid && - !io.cancel(safePublicationStid) && live.peId === publication.peId && - live.stid === publicationStid && live.epoch === publication.epoch && - live.transactionId === publication.transactionId && - live.uopMask === publication.uopMask && - live.allocationMask === publicationDestinationActive.asUInt && - publicationAllocationExact.asUInt.andR && publicationSourceExact - - io.prepared := 0.U.asTypeOf(io.prepared) - io.prepared.valid := io.publicationPrepare.valid && publicationIdentityExact - io.prepared.peId := publication.peId - io.prepared.stid := publicationStid - io.prepared.epoch := publication.epoch - io.prepared.transactionId := publication.transactionId - io.prepared.uopMask := publication.uopMask - io.prepared.allocationMask := live.allocationMask - - val memberBindingsExact = Wire(Vec(p.decodedUopWidth, Bool())) - for (uopIndex <- 0 until p.decodedUopWidth) { - val publicationUop = publication.uops(uopIndex) - val renamedUop = io.prepared.uops(uopIndex) - val activeUop = publication.uopMask(uopIndex) && publicationUop.valid - val member = publicationUop.member - val reservedMember = live.members(uopIndex) - - memberBindingsExact(uopIndex) := !activeUop || - (reservedMember.valid && member.group.asUInt === - reservedMember.group.asUInt && - member.memberIndex === reservedMember.memberIndex && - publicationUop.blockLast === reservedMember.blockLast && - member.group.valid && member.group.peId === publication.peId && - member.group.stid === publication.stid && member.bid.valid && - (!publicationUop.closeBeforeValid || - (publicationUop.closeBefore.valid && - publicationUop.closeBefore.bid.valid && - !(publicationUop.closeBefore.bid.value === member.bid.value && - publicationUop.closeBefore.generation === - member.brobGeneration)))) - - renamedUop.valid := activeUop - renamedUop.member := member - renamedUop.blockLast := publicationUop.blockLast - renamedUop.closeBeforeValid := publicationUop.closeBeforeValid - renamedUop.closeBefore := publicationUop.closeBefore - renamedUop.tSeqBefore := live.tSeqBefore(uopIndex) - renamedUop.uSeqBefore := live.uSeqBefore(uopIndex) - renamedUop.sources := live.sourceMappings(uopIndex) - - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val flatIndex = uopIndex * p.maxDestinationOperands + destinationIndex - renamedUop.destinations(destinationIndex) := - live.allocations(flatIndex).mapping - val row = io.prepared.rows(flatIndex) - row.valid := live.allocations(flatIndex).valid - row.retired := false.B - row.transactionId := publication.transactionId - row.uopIndex := uopIndex.U - row.destinationIndex := destinationIndex.U(destinationIndexWidth.W) - row.member := renamedUop.member - row.mapping := live.allocations(flatIndex).mapping - } - } - - val publicationExact = publicationIdentityExact && - memberBindingsExact.asUInt.andR - val publicationBlockedByRecovery = io.recoveryBusy && - publicationStid === recoveryActiveStid - io.publicationReady := publicationExact && !publicationBlockedByRecovery - io.prepared.valid := io.publicationPrepare.valid && publicationExact - io.publicationRejected.valid := io.publicationPrepare.valid && - !io.publicationReady - io.publicationRejected.bits.requestedStid := publicationStid - io.publicationRejected.bits.requestedTransactionId := - publication.transactionId - io.publicationRejected.bits.live := live - - val publishExact = io.publishFire && io.publicationPrepare.valid && - io.publicationReady && io.prepared.valid - when(io.publishFire) { - assert(io.publicationPrepare.valid && io.publicationReady && - io.prepared.valid, - "T/U publishFire requires the retained exact provisional lease") - } - when(publishExact) { - for (flatIndex <- 0 until p.tuAllocationWidth) { - val row = io.prepared.rows(flatIndex) - when(row.valid && kindIsT(row.mapping.kind)) { - tMapQ(safePublicationStid)(row.mapping.sequence.index) := row - } - when(row.valid && kindIsU(row.mapping.kind)) { - uMapQ(safePublicationStid)(row.mapping.sequence.index) := row - } - } - val nextTPacked = tTail(safePublicationStid) + - live.tAllocationCount - val nextUPacked = uTail(safePublicationStid) + - live.uAllocationCount - tTail(safePublicationStid) := nextTPacked(seqPackedWidth - 1, 0) - uTail(safePublicationStid) := nextUPacked(seqPackedWidth - 1, 0) - tNextPhysical(safePublicationStid) := incrementPhysical( - tNextPhysical(safePublicationStid), live.tAllocationCount, p.tPhysRegs) - uNextPhysical(safePublicationStid) := incrementPhysical( - uNextPhysical(safePublicationStid), live.uAllocationCount, p.uPhysRegs) - tCount(safePublicationStid) := - tCount(safePublicationStid) + live.tAllocationCount - uCount(safePublicationStid) := - uCount(safePublicationStid) + live.uAllocationCount - tPhysicalCount(safePublicationStid) := - tPhysicalCount(safePublicationStid) + live.tAllocationCount - uPhysicalCount(safePublicationStid) := - uPhysicalCount(safePublicationStid) + live.uAllocationCount - when(!(reserveFire && reserveStid === safePublicationStid)) { - provisional(safePublicationStid) := 0.U.asTypeOf(live) - } - } - - val retire = io.retireCommand.bits - val retireStid = retire.member.group.stid - val retireStidInRange = retireStid < p.stidCount.U - val safeRetireStid = Mux(retireStidInRange, retireStid, 0.U) - val retireIsT = retire.kind === DestinationKind.T - val retireIsU = retire.kind === DestinationKind.U - val retireRow = Mux(retireIsT, - tMapQ(safeRetireStid)(retire.sequence.index), - uMapQ(safeRetireStid)(retire.sequence.index)) - val retireSequenceExact = retire.sequence.valid && - retireRow.mapping.sequence.valid && - packSeq(retireRow.mapping.sequence) === packSeq(retire.sequence) - val retireMemberExact = retireRow.member.asUInt === retire.member.asUInt - val retireHeadExact = Mux(retireIsT, - packSeq(retire.sequence) === tHead(safeRetireStid), - packSeq(retire.sequence) === uHead(safeRetireStid)) - val retireExact = retire.valid && retireStidInRange && - (retireIsT || retireIsU) && retireRow.valid && retireSequenceExact && - retireMemberExact && Mux(retire.dealloc, - retireRow.retired && retireHeadExact, !retireRow.retired) - val retireBlockedByRecovery = io.recoveryBusy && - retireStid === recoveryActiveStid - io.retireCommand.ready := retireExact && !retireBlockedByRecovery - val retireFire = io.retireCommand.fire - - when(retireFire && !retire.dealloc) { - when(retireIsT) { - tMapQ(safeRetireStid)(retire.sequence.index).retired := true.B - }.otherwise { - uMapQ(safeRetireStid)(retire.sequence.index).retired := true.B - } - } - when(retireFire && retire.dealloc) { - when(retireIsT) { - tMapQ(safeRetireStid)(retire.sequence.index) := zeroRow - tHead(safeRetireStid) := tHead(safeRetireStid) + 1.U - tCount(safeRetireStid) := tCount(safeRetireStid) - 1.U - tPhysicalCount(safeRetireStid) := - tPhysicalCount(safeRetireStid) - 1.U - }.otherwise { - uMapQ(safeRetireStid)(retire.sequence.index) := zeroRow - uHead(safeRetireStid) := uHead(safeRetireStid) + 1.U - uCount(safeRetireStid) := uCount(safeRetireStid) - 1.U - uPhysicalCount(safeRetireStid) := - uPhysicalCount(safeRetireStid) - 1.U - } - } - - val blockCommit = io.blockCommit.bits - val blockCommitStidInRange = blockCommit.stid < p.stidCount.U - val safeBlockCommitStid = Mux(blockCommitStidInRange, - blockCommit.stid, 0.U) - val blockCommitExact = blockCommit.valid && blockCommitStidInRange && - blockCommit.block.valid && blockCommit.block.bid.valid - val blockCommitBlockedByRecovery = io.recoveryBusy && - blockCommit.stid === recoveryActiveStid - io.blockCommit.ready := blockCommitExact && !blockCommitBlockedByRecovery - - def blockReleaseMask( - mapQ: Vec[OooTUMapQEntry], - head: UInt, - block: BrobPointer): UInt = { - val release = Wire(Vec(p.tuMapQDepthPerStid, Bool())) - release := VecInit(Seq.fill(p.tuMapQDepthPerStid)(false.B)) - var prefix = true.B - for (offset <- 0 until p.tuMapQDepthPerStid) { - val sequence = (head + offset.U)(seqPackedWidth - 1, 0) - val index = sequence(p.tuMapQIndexWidth - 1, 0) - val row = mapQ(index) - val exact = row.valid && row.retired && row.member.bid.valid && - row.mapping.sequence.valid && - packSeq(row.mapping.sequence) === sequence && - row.member.bid.value === block.bid.value && - row.member.brobGeneration === block.generation - release(index) := prefix && exact - prefix = prefix && exact - } - release.asUInt - } - - val tBlockReleaseMask = blockReleaseMask( - tMapQ(safeBlockCommitStid), tHead(safeBlockCommitStid), - blockCommit.block) - val uBlockReleaseMask = blockReleaseMask( - uMapQ(safeBlockCommitStid), uHead(safeBlockCommitStid), - blockCommit.block) - val tBlockReleaseCount = PopCount(tBlockReleaseMask) - val uBlockReleaseCount = PopCount(uBlockReleaseMask) - val blockCommitFire = io.blockCommit.fire - when(blockCommitFire) { - for (index <- 0 until p.tuMapQDepthPerStid) { - when(tBlockReleaseMask(index)) { - tMapQ(safeBlockCommitStid)(index) := zeroRow - } - when(uBlockReleaseMask(index)) { - uMapQ(safeBlockCommitStid)(index) := zeroRow - } - } - tHead(safeBlockCommitStid) := - tHead(safeBlockCommitStid) + tBlockReleaseCount - uHead(safeBlockCommitStid) := - uHead(safeBlockCommitStid) + uBlockReleaseCount - tCount(safeBlockCommitStid) := - tCount(safeBlockCommitStid) - tBlockReleaseCount - uCount(safeBlockCommitStid) := - uCount(safeBlockCommitStid) - uBlockReleaseCount - tPhysicalCount(safeBlockCommitStid) := - tPhysicalCount(safeBlockCommitStid) - tBlockReleaseCount - uPhysicalCount(safeBlockCommitStid) := - uPhysicalCount(safeBlockCommitStid) - uBlockReleaseCount - } - - recoveryRejectValid := false.B - val incomingRecovery = io.recoveryAuthorize.bits - val incomingRecoveryStid = incomingRecovery.key.member.group.stid - val incomingRecoveryStidInRange = incomingRecoveryStid < p.stidCount.U - val safeIncomingRecoveryStid = Mux(incomingRecoveryStidInRange, - incomingRecoveryStid, 0.U) - val incomingRecoveryShapeExact = incomingRecoveryStidInRange && - incomingRecovery.key.member.group.valid && - incomingRecovery.key.member.bid.valid - val recoveryConflictsReserve = reserveFire && - reserveStid === incomingRecoveryStid - val recoveryConflictsPublication = publishExact && - publicationStid === incomingRecoveryStid - val recoveryConflictsRetire = retireFire && - retireStid === incomingRecoveryStid - val recoveryConflictsBlockCommit = blockCommitFire && - blockCommit.stid === incomingRecoveryStid - io.recoveryAuthorize.ready := recoveryState === OooTURecoveryState.Idle && - !recoveryConflictsReserve && !recoveryConflictsPublication && - !recoveryConflictsRetire && !recoveryConflictsBlockCommit - val recoveryAuthorizeFire = io.recoveryAuthorize.fire - - val killed = io.recoverySource.bits.source - val killedStid = killed.member.group.stid - val killedDestinationIsT = Wire(Vec(p.maxDestinationOperands, Bool())) - val killedDestinationIsU = Wire(Vec(p.maxDestinationOperands, Bool())) - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val destination = killed.destinations(destinationIndex) - killedDestinationIsT(destinationIndex) := destination.valid && - kindIsT(destination.kind) - killedDestinationIsU(destinationIndex) := destination.valid && - kindIsU(destination.kind) - } - val killedTCount = PopCount(killedDestinationIsT) - val killedUCount = PopCount(killedDestinationIsU) - val killedCountsInRange = killedTCount <= tCount(recoveryActiveStid) && - killedUCount <= uCount(recoveryActiveStid) && - killedTCount <= tPhysicalCount(recoveryActiveStid) && - killedUCount <= uPhysicalCount(recoveryActiveStid) - val killedTBefore = packSeq(killed.tSeqBefore) - val killedUBefore = packSeq(killed.uSeqBefore) - val killedTAfter = (killedTBefore + killedTCount)(seqPackedWidth - 1, 0) - val killedUAfter = (killedUBefore + killedUCount)(seqPackedWidth - 1, 0) - val killedTailExact = killed.tSeqBefore.valid && killed.uSeqBefore.valid && - killedTAfter === tTail(recoveryActiveStid) && - killedUAfter === uTail(recoveryActiveStid) - val killedTPhysicalBefore = decrementPhysical( - tNextPhysical(recoveryActiveStid), killedTCount, p.tPhysRegs) - val killedUPhysicalBefore = decrementPhysical( - uNextPhysical(recoveryActiveStid), killedUCount, p.uPhysRegs) - - val killedRowsExact = (0 until p.maxDestinationOperands).map { - destinationIndex => - val destination = killed.destinations(destinationIndex) - val isT = killedDestinationIsT(destinationIndex) - val isU = killedDestinationIsU(destinationIndex) - val validKind = isT || isU - val olderT = if (destinationIndex == 0) 0.U else - PopCount(killedDestinationIsT.take(destinationIndex)) - val olderU = if (destinationIndex == 0) 0.U else - PopCount(killedDestinationIsU.take(destinationIndex)) - val expectedSequence = Mux(isT, - killedTBefore + olderT, killedUBefore + olderU)(seqPackedWidth - 1, 0) - val expectedPhysical = Mux(isT, - incrementPhysical(killedTPhysicalBefore, olderT, p.tPhysRegs), - incrementPhysical(killedUPhysicalBefore, olderU, p.uPhysRegs)) - val row = Mux(isT, - tMapQ(recoveryActiveStid)(destination.sequence.index), - uMapQ(recoveryActiveStid)(destination.sequence.index)) - !destination.valid || (validKind && destination.sequence.valid && - destination.stid === recoveryActiveStid && - destination.epoch === killed.epoch && - packSeq(destination.sequence) === expectedSequence && - destination.physicalTag === expectedPhysical && row.valid && - !row.retired && row.transactionId === killed.transactionId && - row.uopIndex === killed.uopIndex && - row.destinationIndex === destinationIndex.U && - row.member.asUInt === killed.member.asUInt && - row.mapping.asUInt === destination.asUInt) - }.reduce(_ && _) - val killedSourceExact = io.recoverySource.bits.request.asUInt === - recoveryRequest.asUInt && killed.valid && - killedStid === recoveryActiveStid && killed.member.group.valid && - killed.member.bid.valid && killedCountsInRange && killedTailExact && - killedRowsExact - io.recoverySource.ready := - recoveryState === OooTURecoveryState.WaitSources && killedSourceExact - val recoverySourceFire = io.recoverySource.fire - - when(recoveryAuthorizeFire) { - when(incomingRecoveryShapeExact) { - recoveryRequest := incomingRecovery - provisional(safeIncomingRecoveryStid) := - 0.U.asTypeOf(new OooTUReservation(p)) - recoveryState := OooTURecoveryState.WaitSources - }.otherwise { - recoveryRejectValid := true.B - recoveryRejectRequest := incomingRecovery - recoveryRejectTTail := tTail(safeIncomingRecoveryStid) - recoveryRejectUTail := uTail(safeIncomingRecoveryStid) - recoveryRejectTCount := tCount(safeIncomingRecoveryStid) - recoveryRejectUCount := uCount(safeIncomingRecoveryStid) - } - } - - when(recoveryState === OooTURecoveryState.WaitSources && - io.recoverySource.valid) { - assert(killedSourceExact, - "T/U recovery source must own the exact local MapQ suffix") - } - - switch(recoveryState) { - is(OooTURecoveryState.WaitSources) { - when(recoverySourceFire) { - for (destinationIndex <- 0 until p.maxDestinationOperands) { - val destination = killed.destinations(destinationIndex) - when(killedDestinationIsT(destinationIndex)) { - tMapQ(recoveryActiveStid)(destination.sequence.index) := zeroRow - } - when(killedDestinationIsU(destinationIndex)) { - uMapQ(recoveryActiveStid)(destination.sequence.index) := zeroRow - } - } - tTail(recoveryActiveStid) := killedTBefore - uTail(recoveryActiveStid) := killedUBefore - when(killedTCount.orR) { - tNextPhysical(recoveryActiveStid) := killedTPhysicalBefore - } - when(killedUCount.orR) { - uNextPhysical(recoveryActiveStid) := killedUPhysicalBefore - } - tCount(recoveryActiveStid) := - tCount(recoveryActiveStid) - killedTCount - uCount(recoveryActiveStid) := - uCount(recoveryActiveStid) - killedUCount - tPhysicalCount(recoveryActiveStid) := - tPhysicalCount(recoveryActiveStid) - killedTCount - uPhysicalCount(recoveryActiveStid) := - uPhysicalCount(recoveryActiveStid) - killedUCount - }.elsewhen(io.recoverySourcesDone && !io.recoverySource.valid) { - recoveryState := OooTURecoveryState.Complete - } - } - is(OooTURecoveryState.Complete) { - when(io.recoveryFinish) { - recoveryState := OooTURecoveryState.Idle - } - } - } - - io.recoveryComplete := recoveryState === OooTURecoveryState.Complete - io.recoveryRejected.valid := recoveryRejectValid - io.recoveryRejected.bits.requested := recoveryRejectRequest - driveSeq(io.recoveryRejected.bits.tTail, recoveryRejectTTail, true.B) - driveSeq(io.recoveryRejected.bits.uTail, recoveryRejectUTail, true.B) - io.recoveryRejected.bits.tMapQCount := recoveryRejectTCount - io.recoveryRejected.bits.uMapQCount := recoveryRejectUCount - when(io.recoveryFinish) { - assert(io.recoveryComplete, - "T/U recovery may finish only after the exact suffix rolls back") - } - - when(retireFire && blockCommitFire) { - assert(false.B, - "T/U retire mark/deallocation and block commit are serialized") - } - when(publishExact && (retireFire || blockCommitFire)) { - assert(safePublicationStid =/= Mux(retireFire, - safeRetireStid, safeBlockCommitStid), - "same-STID T/U publication must wait for retirement maintenance") - } - when(io.recoveryBusy) { - assert(!(reserveFire && reserveStid === recoveryActiveStid), - "same-STID T/U reserve must wait for recovery") - assert(!(publishExact && publicationStid === recoveryActiveStid), - "same-STID T/U publication must wait for recovery") - assert(!(retireFire && retireStid === recoveryActiveStid), - "same-STID T/U retirement must wait for recovery") - assert(!(blockCommitFire && blockCommit.stid === recoveryActiveStid), - "same-STID T/U block commit must wait for recovery") - } - - io.provisional := provisional - io.tMapQUsed := tCount - io.uMapQUsed := uCount - io.tPhysicalUsed := tPhysicalCount - io.uPhysicalUsed := uPhysicalCount -} diff --git a/chisel/src/main/scala/linxcore/ooo/OooTURetire.scala b/chisel/src/main/scala/linxcore/ooo/OooTURetire.scala index 1125e8c7..ed48c289 100644 --- a/chisel/src/main/scala/linxcore/ooo/OooTURetire.scala +++ b/chisel/src/main/scala/linxcore/ooo/OooTURetire.scala @@ -68,8 +68,8 @@ class OooTURetireIO(val p: OooParams = OooParams()) extends Bundle { * release -> exact-block relation cleanup -> local block commit. * * This module owns only retire-source and relation-CMAP state. The T/U MapQ - * and physical tags remain owned by [[OooTURename]], which accepts - * the generated exact mark/deallocation and post-clean block commands. + * and physical tags remain owned by [[TURename]], which accepts the generated + * exact mark/deallocation and post-clean block commands. */ class OooTURetire(val p: OooParams = OooParams()) extends Module { val io = IO(new OooTURetireIO(p)) @@ -387,7 +387,9 @@ class OooTURetire(val p: OooParams = OooParams()) extends Module { record.valid === active && (!active || (record.key.valid && record.key.peId === incomingBatch.release.firstGroup.peId && record.key.stid === incomingStid && - record.key.ridSlot === slotSum(p.ridSlotWidth - 1, 0) && + record.key.ridSlot === Mux(wraps, + (slotSum - p.robGroupsPerStid.U)(p.ridSlotWidth - 1, 0), + slotSum(p.ridSlotWidth - 1, 0)) && record.key.ridGeneration === incomingBatch.release.firstGroup.ridGeneration + wraps.asUInt && record.brob.valid && record.brob.bid.valid && diff --git a/chisel/src/main/scala/linxcore/ooo/PRename.scala b/chisel/src/main/scala/linxcore/ooo/PRename.scala new file mode 100644 index 00000000..9c009316 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/PRename.scala @@ -0,0 +1,550 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Cat, PopCount, PriorityEncoder, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +private[ooo] object PRename { + def tagWidth(p: CoreParams): Int = p.ooo.gprTagWidth + def committedTag(p: CoreParams, stid: Int, atag: Int): Int = + stid * p.ooo.gprArchRegs + atag + def isCommittedResetTag(p: CoreParams, tag: UInt): Bool = + tag < (p.ooo.stidCount * p.ooo.gprArchRegs).U +} + +private[ooo] class PRenameIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Valid(new D2AdmissionGroup(p))) + val prepareReady = Output(Bool()) + val prepared = Output(new D3RenameGroup(p)) + val reserve = Flipped(Valid(new D3RenameGroup(p))) + val publish = Flipped(Valid(new D3RenameGroup(p))) + val cancel = Flipped(Valid(UInt(p.ooo.stidWidth.W))) + val release = Flipped(Valid(new RenameCommitReleaseTxn(p))) + val releaseExact = Output(Bool()) + val releaseApply = Input(Bool()) + val recoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val debugPMap = Output(Vec(p.ooo.stidCount, + Vec(p.ooo.gprArchRegs, UInt(PRename.tagWidth(p).W)))) +} + +/** Independent P-register rename owner. + * + * Owns P SMAP/CMAP, physical free state, per-tag generation, and P MapQ. It + * prepares a combinational overlay for RENU and mutates state only when RENU + * sends the common D3 publish pulse. + */ +private[ooo] class PRename(val p: CoreParams) extends Module { + val io = IO(new PRenameIO(p)) + + private val width = p.widths.decodeWidth + private val pTagWidth = PRename.tagWidth(p) + private val physicalPTagWidth = math.max(1, log2Ceil(p.ooo.gprPhysRegs)) + private val archIndexWidth = math.max(1, log2Ceil(p.ooo.gprArchRegs)) + private val physicalStidWidth = math.max(1, log2Ceil(p.ooo.stidCount)) + private val mapQIndexWidth = math.max(1, log2Ceil(p.ooo.gprMapQDepthPerStid)) + private val mapQCountWidth = math.max(1, log2Ceil(p.ooo.gprMapQDepthPerStid + 1)) + private val pDestSlots = width * p.maxDestinationOperands + private val committedPTagLimit = p.ooo.stidCount * p.ooo.gprArchRegs + + private def trunc(value: UInt, width: Int): UInt = + if (value.getWidth == width) value + else if (value.getWidth > width) value(width - 1, 0) + else Cat(0.U((width - value.getWidth).W), value) + + private def safeAtag(value: UInt): UInt = trunc(value, archIndexWidth) + private def ptagInRange(value: UInt): Bool = value < p.ooo.gprPhysRegs.U + private def physicalPtag(value: UInt): UInt = + value(physicalPTagWidth - 1, 0) + private def generationFor(value: UInt): UInt = + Mux(ptagInRange(value), generations(physicalPtag(value)), + 0.U(p.ooo.gprTagGenerationWidth.W)) + private def safeStid(value: UInt): UInt = + if (p.ooo.stidCount == 1) 0.U(physicalStidWidth.W) + else trunc(value, physicalStidWidth) + + private def sameRob(a: RobIdentity, b: RobIdentity): Bool = + a.asUInt === b.asUInt + + private def robOlderOrSame(a: RobIdentity, b: RobIdentity): Bool = { + val groupOrderWidth = a.ridGeneration.getWidth + a.ridSlot.getWidth + val aGroup = Cat(a.ridGeneration, a.ridSlot) + val bGroup = Cat(b.ridGeneration, b.ridSlot) + val delta = trunc(bGroup - aGroup, groupOrderWidth) + val sameGroup = delta === 0.U + val rowToSurvivorWithinLiveWindow = + delta < (BigInt(1) << (groupOrderWidth - 1)).U(groupOrderWidth.W) + a.stid === b.stid && a.peId === b.peId && rowToSurvivorWithinLiveWindow && + (!sameGroup || a.memberIndex <= b.memberIndex) + } + + val smap = RegInit(VecInit((0 until p.ooo.stidCount).map { stid => + VecInit((0 until p.ooo.gprArchRegs).map { atag => + PRename.committedTag(p, stid, atag).U(pTagWidth.W) + }) + })) + val cmap = RegInit(VecInit((0 until p.ooo.stidCount).map { stid => + VecInit((0 until p.ooo.gprArchRegs).map { atag => + PRename.committedTag(p, stid, atag).U(pTagWidth.W) + }) + })) + val free = RegInit(VecInit((0 until p.ooo.gprPhysRegs).map { tag => + (tag >= committedPTagLimit).B + })) + val generations = RegInit(VecInit(Seq.fill(p.ooo.gprPhysRegs)( + 0.U(p.ooo.gprTagGenerationWidth.W)))) + val mapQ = Reg(Vec(p.ooo.stidCount, Vec(p.ooo.gprMapQDepthPerStid, + new RenameCommitReleaseEntry(p)))) + val head = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(mapQIndexWidth.W)))) + val tail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(mapQIndexWidth.W)))) + val tailGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.gprTagGenerationWidth.W)))) + val headGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.gprTagGenerationWidth.W)))) + val count = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(mapQCountWidth.W)))) + val reserved = RegInit(VecInit(Seq.fill(p.ooo.gprPhysRegs)(false.B))) + val reservedValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + val reservedLease = Reg(Vec(p.ooo.stidCount, new D3RenameGroup(p))) + + io.debugPMap := smap + + val in = io.prepare.bits + val stidRaw = in.entries(0).uop.instruction.parent.identity.stid + val stidInRange = stidRaw < p.ooo.stidCount.U + val stid = safeStid(stidRaw) + val prospectivePublish = io.publish.bits + val prospectivePublishStid = safeStid( + prospectivePublish.entries(0).uop.decoded.instruction.parent.identity.stid) + val prospectivePublishSameStid = io.publish.valid && + prospectivePublish.entries(0).uop.decoded.instruction.parent.identity.stid < + p.ooo.stidCount.U && prospectivePublishStid === stid + val prospectivePublishFinal = prospectivePublishSameStid && + reservedValid(stid) && + prospectivePublish.count === reservedLease(stid).count && + prospectivePublish.groupCount === reservedLease(stid).groupCount + val prospectivePublishedP = Wire(Vec(pDestSlots, Bool())) + for (lane <- 0 until width; dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val hist = prospectivePublish.entries(lane).history(dest) + prospectivePublishedP(flat) := prospectivePublishSameStid && + lane.U < prospectivePublish.count && hist.valid && + hist.kind === OperandKind.Gpr + } + val prospectivePublishedPCount = PopCount(prospectivePublishedP) + val prospectiveSmap = Wire(Vec(p.ooo.gprArchRegs, UInt(pTagWidth.W))) + prospectiveSmap := smap(stid) + for (lane <- 0 until width; dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val hist = prospectivePublish.entries(lane).history(dest) + when(prospectivePublishedP(flat) && hist.atag < p.ooo.gprArchRegs.U) { + prospectiveSmap(safeAtag(hist.atag)) := hist.ptag + } + } + val prospectiveTailSum = tail(stid) +& prospectivePublishedPCount + val prospectiveTail = trunc(prospectiveTailSum, mapQIndexWidth) + val prospectiveTailGeneration = tailGeneration(stid) + + (prospectiveTailSum >= p.ooo.gprMapQDepthPerStid.U).asUInt + val prospectiveCount = count(stid) +& prospectivePublishedPCount + val active = Wire(Vec(width, Bool())) + for (lane <- 0 until width) { + active(lane) := lane.U < in.count && in.entries(lane).uop.valid + } + + val destActive = Wire(Vec(pDestSlots, Bool())) + val destAtag = Wire(Vec(pDestSlots, UInt(archIndexWidth.W))) + for (lane <- 0 until width; dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val d = in.entries(lane).uop.destinations(dest) + destActive(flat) := active(lane) && d.valid && + d.kind === OperandKind.Gpr && d.atag < p.ooo.gprArchRegs.U + destAtag(flat) := safeAtag(d.atag) + } + val destCount = PopCount(destActive) + val freeForPrepare = Wire(Vec(p.ooo.gprPhysRegs, Bool())) + for (tag <- 0 until p.ooo.gprPhysRegs) { + freeForPrepare(tag) := free(tag) && !reserved(tag) + } + io.prepareReady := stidInRange && + (!reservedValid(stid) || prospectivePublishFinal) && + destCount <= PopCount(freeForPrepare) && + prospectiveCount +& destCount <= p.ooo.gprMapQDepthPerStid.U + + val allocatedTag = Wire(Vec(pDestSlots, UInt(pTagWidth.W))) + val allocatedGen = Wire(Vec(pDestSlots, + UInt(p.ooo.gprTagGenerationWidth.W))) + allocatedTag := VecInit(Seq.fill(pDestSlots)(0.U(pTagWidth.W))) + allocatedGen := VecInit(Seq.fill(pDestSlots)( + 0.U(p.ooo.gprTagGenerationWidth.W))) + val chosen = Wire(Vec(pDestSlots + 1, Vec(p.ooo.gprPhysRegs, Bool()))) + chosen(0) := VecInit(Seq.fill(p.ooo.gprPhysRegs)(false.B)) + for (flat <- 0 until pDestSlots) { + val available = Wire(Vec(p.ooo.gprPhysRegs, Bool())) + for (tag <- 0 until p.ooo.gprPhysRegs) { + available(tag) := freeForPrepare(tag) && !chosen(flat)(tag) + } + val tag = PriorityEncoder(available.asUInt) + allocatedTag(flat) := trunc(tag, pTagWidth) + allocatedGen(flat) := generations(tag) + for (tagIndex <- 0 until p.ooo.gprPhysRegs) { + chosen(flat + 1)(tagIndex) := + chosen(flat)(tagIndex) || (destActive(flat) && tag === tagIndex.U) + } + } + + io.prepared := 0.U.asTypeOf(io.prepared) + io.prepared.count := in.count + io.prepared.groupCount := in.groupCount + for (group <- 0 until width) { + io.prepared.groups(group) := in.groups(group) + } + for (lane <- 0 until width) { + io.prepared.entries(lane).trap := in.entries(lane).trap + io.prepared.entries(lane).residentBound := in.entries(lane).residentBound + io.prepared.entries(lane).brobBound := in.entries(lane).brobBound + io.prepared.entries(lane).earlyRobComplete := + in.entries(lane).uop.earlyComplete + io.prepared.entries(lane).uop.decoded := in.entries(lane).uop + for (source <- 0 until p.maxSourceOperands) { + val src = in.entries(lane).uop.sources(source) + val out = io.prepared.entries(lane).uop.sources(source) + out.valid := src.valid + out.kind := src.kind + out.atag := src.atag + out.ready := true.B + when(src.valid && src.kind === OperandKind.Gpr && + src.atag < p.ooo.gprArchRegs.U) { + val atag = safeAtag(src.atag) + val tag = Wire(UInt(pTagWidth.W)) + val gen = Wire(UInt(p.ooo.gprTagGenerationWidth.W)) + val forwarded = Wire(Bool()) + tag := prospectiveSmap(atag) + gen := generationFor(tag) + forwarded := false.B + for (flat <- 0 until lane * p.maxDestinationOperands) { + val olderDest = in.entries(flat / p.maxDestinationOperands) + .uop.destinations(flat % p.maxDestinationOperands) + when(destActive(flat) && olderDest.atag === src.atag) { + tag := allocatedTag(flat) + gen := allocatedGen(flat) + forwarded := true.B + } + } + out.ptag := tag + out.pGeneration := gen + out.ptagValid := true.B + out.ready := !forwarded && ptagInRange(tag) + } + } + for (dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val din = in.entries(lane).uop.destinations(dest) + val dout = io.prepared.entries(lane).uop.destinations(dest) + val hist = io.prepared.entries(lane).history(dest) + dout.valid := din.valid + dout.kind := din.kind + dout.atag := din.atag + hist.valid := destActive(flat) + hist.kind := din.kind + hist.atag := din.atag + when(destActive(flat)) { + val previous = Wire(UInt(pTagWidth.W)) + previous := prospectiveSmap(destAtag(flat)) + for (older <- 0 until flat) { + val olderDest = in.entries(older / p.maxDestinationOperands) + .uop.destinations(older % p.maxDestinationOperands) + when(destActive(older) && olderDest.atag === din.atag) { + previous := allocatedTag(older) + } + } + dout.ptag := allocatedTag(flat) + dout.previousPtag := previous + dout.pGeneration := allocatedGen(flat) + dout.previousPGeneration := generationFor(previous) + dout.previousPtagValid := true.B + dout.ptagValid := true.B + hist.ptag := allocatedTag(flat) + hist.previousPtag := previous + hist.pGeneration := allocatedGen(flat) + hist.previousPGeneration := generationFor(previous) + val ordinal = PopCount(destActive.take(flat)) + val indexSum = prospectiveTail +& ordinal + hist.pMapQIndex := trunc(indexSum, mapQIndexWidth) + hist.pMapQGeneration := prospectiveTailGeneration + + (indexSum >= p.ooo.gprMapQDepthPerStid.U).asUInt + } + } + } + + when(io.reserve.valid) { + val lease = io.reserve.bits + val leaseStid = safeStid( + lease.entries(0).uop.decoded.instruction.parent.identity.stid) + reservedLease(leaseStid) := lease + reservedValid(leaseStid) := true.B + for (lane <- 0 until width) { + when(lane.U < lease.count && lease.entries(lane).uop.decoded.valid) { + for (dest <- 0 until p.maxDestinationOperands) { + val hist = lease.entries(lane).history(dest) + when(hist.valid && hist.kind === OperandKind.Gpr && + hist.ptag < p.ooo.gprPhysRegs.U) { + reserved(physicalPtag(hist.ptag)) := true.B + } + } + } + } + } + + when(io.cancel.valid) { + val cancelStid = safeStid(io.cancel.bits) + val lease = reservedLease(cancelStid) + when(reservedValid(cancelStid)) { + for (lane <- 0 until width) { + when(lane.U < lease.count && lease.entries(lane).uop.decoded.valid) { + for (dest <- 0 until p.maxDestinationOperands) { + val hist = lease.entries(lane).history(dest) + when(hist.valid && hist.kind === OperandKind.Gpr && + hist.ptag < p.ooo.gprPhysRegs.U) { + reserved(physicalPtag(hist.ptag)) := false.B + } + } + } + } + } + reservedValid(cancelStid) := false.B + } + + when(io.publish.valid) { + val pub = io.publish.bits + val pubStid = safeStid(pub.entries(0).uop.decoded.instruction.parent.identity.stid) + val lease = reservedLease(pubStid) + val prefixExact = reservedValid(pubStid) && pub.count.orR && + pub.count <= lease.count && pub.groupCount.orR && + pub.groupCount <= lease.groupCount + assert(prefixExact, + "P publication must consume an exact retained reservation prefix") + for (lane <- 0 until width) { + when(lane.U < pub.count) { + assert(pub.entries(lane).history.asUInt === + lease.entries(lane).history.asUInt, + "P publication history must match the retained prefix lease") + } + } + val published = Wire(Vec(pDestSlots, Bool())) + for (flat <- 0 until pDestSlots) { published(flat) := false.B } + for (lane <- 0 until width) { + when(lane.U < pub.count && pub.entries(lane).uop.decoded.valid) { + for (dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val hist = pub.entries(lane).history(dest) + when(hist.valid && hist.kind === OperandKind.Gpr && + hist.atag < p.ooo.gprArchRegs.U && + hist.ptag < p.ooo.gprPhysRegs.U) { + val row = Wire(new RenameCommitReleaseEntry(p)) + row := 0.U.asTypeOf(row) + row.valid := true.B + row.rob := pub.entries(lane).uop.decoded.rob + row.epoch := pub.entries(lane).uop.decoded.instruction.parent + .identity.epoch + row.blockLast := pub.entries(lane).uop.decoded.blockBoundary + row.history(dest) := hist + val idx = trunc(tail(pubStid) + PopCount(published.take(flat)), + mapQIndexWidth) + mapQ(pubStid)(idx) := row + smap(pubStid)(safeAtag(hist.atag)) := hist.ptag + free(physicalPtag(hist.ptag)) := false.B + reserved(physicalPtag(hist.ptag)) := false.B + published(flat) := true.B + } + } + } + } + val n = PopCount(published) + val tailSum = tail(pubStid) +& n + tail(pubStid) := trunc(tailSum, mapQIndexWidth) + when(tailSum >= p.ooo.gprMapQDepthPerStid.U) { + tailGeneration(pubStid) := tailGeneration(pubStid) + 1.U + } + count(pubStid) := count(pubStid) + n + val suffix = Wire(new D3RenameGroup(p)) + suffix := 0.U.asTypeOf(suffix) + suffix.count := lease.count - pub.count + suffix.groupCount := lease.groupCount - pub.groupCount + for (group <- 0 until width) { + for (source <- 0 until width) { + when(source.U === group.U + pub.groupCount && + source.U < lease.groupCount) { + suffix.groups(group) := lease.groups(source) + } + } + } + for (lane <- 0 until width) { + for (source <- 0 until width) { + when(source.U === lane.U + pub.count && source.U < lease.count) { + suffix.entries(lane) := lease.entries(source) + } + } + } + reservedLease(pubStid) := suffix + reservedValid(pubStid) := suffix.count.orR + + val reserveStid = safeStid( + io.reserve.bits.entries(0).uop.decoded.instruction.parent.identity.stid) + val sameStidReplacement = io.reserve.valid && reserveStid === pubStid + when(sameStidReplacement) { + assert(!suffix.count.orR && !suffix.groupCount.orR, + "P reservation replacement requires final publication of the old lease") + for (oldLane <- 0 until width; oldDest <- 0 until p.maxDestinationOperands) { + val oldHist = pub.entries(oldLane).history(oldDest) + val oldLive = oldLane.U < pub.count && oldHist.valid && + oldHist.kind === OperandKind.Gpr + for (newLane <- 0 until width; newDest <- 0 until p.maxDestinationOperands) { + val newHist = io.reserve.bits.entries(newLane).history(newDest) + val newLive = newLane.U < io.reserve.bits.count && newHist.valid && + newHist.kind === OperandKind.Gpr + when(oldLive && newLive) { + assert(oldHist.ptag =/= newHist.ptag, + "replacement P reservations must not reuse a published physical tag") + } + } + } + reservedLease(pubStid) := io.reserve.bits + reservedValid(pubStid) := true.B + } + } + + val releaseSlotCount = p.widths.retireWidth * p.maxDestinationOperands + val releaseWanted = Wire(Vec(releaseSlotCount, Bool())) + val releaseExact = Wire(Vec(releaseSlotCount, Bool())) + val releaseAccept = Wire(Vec(releaseSlotCount, Bool())) + releaseWanted := VecInit(Seq.fill(releaseSlotCount)(false.B)) + releaseExact := VecInit(Seq.fill(releaseSlotCount)(false.B)) + releaseAccept := VecInit(Seq.fill(releaseSlotCount)(false.B)) + for (flat <- 0 until releaseSlotCount) { + val lane = flat / p.maxDestinationOperands + val dest = flat % p.maxDestinationOperands + val rel = io.release.bits.lanes(lane) + val hist = rel.history(dest) + val st = safeStid(rel.rob.stid) + releaseWanted(flat) := io.release.valid && rel.valid && + lane.U < io.release.bits.count && + hist.valid && hist.kind === OperandKind.Gpr + val priorRows = PopCount((0 until flat).map { prior => + val priorLane = prior / p.maxDestinationOperands + releaseWanted(prior) && + io.release.bits.lanes(priorLane).rob.stid === rel.rob.stid + }) + val rowIndex = trunc(head(st) + priorRows, mapQIndexWidth) + val row = mapQ(st)(rowIndex) + val available = count(st) > priorRows + releaseExact(flat) := releaseWanted(flat) && + rel.rob.stid < p.ooo.stidCount.U && available && row.valid && + rel.rob.asUInt === row.rob.asUInt && + hist.asUInt === row.history(dest).asUInt && + hist.pMapQIndex === rowIndex && + ptagInRange(hist.ptag) && ptagInRange(hist.previousPtag) && + hist.pGeneration === generationFor(hist.ptag) && + hist.previousPGeneration === generationFor(hist.previousPtag) + } + val releaseAllExact = !releaseWanted.asUInt.orR || + (releaseWanted.asUInt === releaseExact.asUInt) + io.releaseExact := !io.release.valid || releaseAllExact + for (flat <- 0 until releaseSlotCount) { + releaseAccept(flat) := releaseWanted(flat) && releaseAllExact + } + when(io.release.valid && io.releaseApply && releaseAllExact) { + for (flat <- 0 until releaseSlotCount) { + val lane = flat / p.maxDestinationOperands + val dest = flat % p.maxDestinationOperands + val rel = io.release.bits.lanes(lane) + val hist = rel.history(dest) + val st = safeStid(rel.rob.stid) + when(releaseAccept(flat)) { + cmap(st)(safeAtag(hist.atag)) := hist.ptag + when(!PRename.isCommittedResetTag(p, hist.previousPtag)) { + val previousIndex = physicalPtag(hist.previousPtag) + free(previousIndex) := true.B + generations(previousIndex) := generations(previousIndex) + 1.U + } + } + } + for (stid <- 0 until p.ooo.stidCount) { + val acceptedForStid = PopCount((0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseAccept(flat) && + io.release.bits.lanes(lane).rob.stid === stid.U + }) + when(acceptedForStid.orR) { + val headSum = head(stid) +& acceptedForStid + head(stid) := trunc(headSum, mapQIndexWidth) + when(headSum >= p.ooo.gprMapQDepthPerStid.U) { + headGeneration(stid) := headGeneration(stid) + 1.U + } + count(stid) := count(stid) - acceptedForStid + } + } + } + + when(io.recoveryApply.valid && io.recoveryApply.bits.phase === RecoveryPhase.Apply) { + val target = safeStid(io.recoveryApply.bits.trigger.stid) + val survivorMatches = Wire(Vec(p.ooo.gprMapQDepthPerStid, Bool())) + for (offset <- 0 until p.ooo.gprMapQDepthPerStid) { + val idx = trunc(head(target) + offset.U, mapQIndexWidth) + survivorMatches(offset) := offset.U < count(target) && + io.recoveryApply.bits.survivingTailValid && + mapQ(target)(idx).valid && + robOlderOrSame(mapQ(target)(idx).rob, + io.recoveryApply.bits.survivingTail) + } + val survivorCount = Wire(UInt(mapQCountWidth.W)) + survivorCount := Mux(io.recoveryApply.bits.survivingTailValid, + trunc(PopCount(survivorMatches), mapQCountWidth), + 0.U(mapQCountWidth.W)) + for (offset <- 1 until p.ooo.gprMapQDepthPerStid) { + when(survivorMatches(offset)) { + assert(survivorMatches(offset - 1), + "P recovery survivors must form an ordered prefix") + } + } + + for (atag <- 0 until p.ooo.gprArchRegs) { + smap(target)(atag) := cmap(target)(atag) + } + for (offset <- 0 until p.ooo.gprMapQDepthPerStid) { + val rowIndex = trunc(head(target) + offset.U, mapQIndexWidth) + val row = mapQ(target)(rowIndex) + val live = offset.U < count(target) + val survives = live && offset.U < survivorCount + val killed = live && !survives + when(survives) { + for (dest <- 0 until p.maxDestinationOperands) { + val hist = row.history(dest) + when(hist.valid && hist.kind === OperandKind.Gpr && + hist.atag < p.ooo.gprArchRegs.U && ptagInRange(hist.ptag)) { + smap(target)(safeAtag(hist.atag)) := hist.ptag + } + } + } + when(killed) { + row.valid := false.B + for (dest <- 0 until p.maxDestinationOperands) { + val hist = row.history(dest) + when(hist.valid && hist.kind === OperandKind.Gpr && + hist.ptag < p.ooo.gprPhysRegs.U && + !PRename.isCommittedResetTag(p, hist.ptag)) { + val tagIndex = physicalPtag(hist.ptag) + free(tagIndex) := true.B + generations(tagIndex) := generations(tagIndex) + 1.U + } + } + } + } + val recoveredTail = head(target) +& survivorCount + tail(target) := trunc(recoveredTail, mapQIndexWidth) + tailGeneration(target) := headGeneration(target) + + (recoveredTail >= p.ooo.gprMapQDepthPerStid.U).asUInt + count(target) := survivorCount + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/RENU.scala b/chisel/src/main/scala/linxcore/ooo/RENU.scala new file mode 100644 index 00000000..6a4cbb5f --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/RENU.scala @@ -0,0 +1,406 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{PopCount, PriorityEncoder, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +/** Rename coordinator for D2-to-D3. + * + * The coordinator owns only the retained provisional D3 row and recovery + * handshake. P and T/U state live exclusively in their sibling owner modules. + * Both owners prepare from the same D2 prefix, then both publish from the + * exact retained D3 row on the common toD3 fire. + */ +class RENU(val p: CoreParams) extends Module { + require(p.ooo.d3PrefixWidth == p.widths.decodeWidth) + require(p.ooo.renameWidth >= p.widths.decodeWidth) + + val io = IO(new RENUD2D3IO(p)) + + private val width = p.widths.decodeWidth + private val stidIndexWidth = p.ooo.stidWidth + + private def safeStid(value: UInt): UInt = + if (p.ooo.stidCount == 1) 0.U else value(p.ooo.stidWidth - 1, 0) + + val pRename = Module(new PRename(p)) + val tuRename = Module(new TURename(p)) + + pRename.io.prepare.valid := io.fromD2.valid + pRename.io.prepare.bits := io.fromD2.bits + tuRename.io.prepare.valid := io.fromD2.valid + tuRename.io.prepare.bits := io.fromD2.bits + pRename.io.release.valid := io.release.valid + pRename.io.release.bits := io.release.bits + tuRename.io.release.valid := io.release.valid + tuRename.io.release.bits := io.release.bits + + io.debugPMap := pRename.io.debugPMap + io.debugTCount := tuRename.io.debugTCount + io.debugUCount := tuRename.io.debugUCount + + val pendingValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(false.B))) + val pending = Reg(Vec(p.ooo.stidCount, new D3RenameGroup(p))) + for (stid <- 0 until p.ooo.stidCount) { + io.reservedGroupCount(stid) := Mux( + pendingValid(stid), pending(stid).groupCount, 0.U) + } + val heldGrantValid = RegInit(false.B) + val heldGrantStid = RegInit(0.U(stidIndexWidth.W)) + + val recoveryPending = RegInit(false.B) + val preparedValid = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + + private def samePlan(candidate: RecoveryPlan): Bool = + RecoveryPlanContract.sameTransactionIgnoringPhase(candidate, recoveryPlan) + + val applyHit = recoveryPending && io.recovery.apply.valid && + samePlan(io.recovery.apply.bits) && + io.recovery.apply.bits.phase === RecoveryPhase.Apply + val abortHit = recoveryPending && io.recovery.abort.valid && + samePlan(io.recovery.abort.bits) && + io.recovery.abort.bits.phase === RecoveryPhase.Abort + val rawAnyPending = pendingValid.asUInt.orR + val rawNextPendingStid = PriorityEncoder(pendingValid.asUInt) + val rawPresentedStid = if (p.ooo.stidCount == 1) { + 0.U(stidIndexWidth.W) + } else { + Mux(heldGrantValid, heldGrantStid, rawNextPendingStid) + } + val prepareTargetStid = safeStid(io.recovery.prepare.bits.trigger.stid) + val prepareConflictsWithIrrevocable = rawAnyPending && + rawPresentedStid === prepareTargetStid && + heldGrantValid + + io.recovery.prepare.ready := !recoveryPending && + io.recovery.prepare.bits.phase === RecoveryPhase.Prepare && + io.recovery.prepare.bits.trigger.stid < p.ooo.stidCount.U && + (!io.recovery.prepare.bits.survivingTailValid || + io.recovery.prepare.bits.survivingTail.stid === + io.recovery.prepare.bits.trigger.stid) && + !prepareConflictsWithIrrevocable + val recoveryMutationFence = recoveryPending || io.recovery.prepare.fire || + applyHit || abortHit + val releasePrefixShape = (0 until p.widths.retireWidth).map { lane => + io.release.bits.lanes(lane).valid === (lane.U < io.release.bits.count) + } + val releaseShapeExact = io.release.bits.count <= p.widths.retireWidth.U && + releasePrefixShape.reduce(_ && _) + val releaseReady = io.release.valid && releaseShapeExact && + !recoveryMutationFence && pRename.io.releaseExact && + tuRename.io.releaseExact + io.releaseReady := releaseReady + val releaseApply = releaseReady && io.releaseApply + pRename.io.releaseApply := releaseApply + tuRename.io.releaseApply := releaseApply + io.recovery.prepared.valid := preparedValid + io.recovery.prepared.bits := recoveryPlan + when(io.recovery.prepare.fire) { + recoveryPending := true.B + preparedValid := true.B + recoveryPlan := io.recovery.prepare.bits + }.elsewhen(applyHit || abortHit) { + recoveryPending := false.B + preparedValid := false.B + }.elsewhen(io.recovery.prepared.fire) { + preparedValid := false.B + } + + pRename.io.recoveryApply.valid := applyHit + pRename.io.recoveryApply.bits := io.recovery.apply.bits + tuRename.io.recoveryApply.valid := applyHit + tuRename.io.recoveryApply.bits := io.recovery.apply.bits + + val prepared = Wire(new D3RenameGroup(p)) + prepared := 0.U.asTypeOf(prepared) + prepared.count := io.fromD2.bits.count + prepared.groupCount := io.fromD2.bits.groupCount + for (group <- 0 until width) { + prepared.groups(group) := io.fromD2.bits.groups(group) + } + for (lane <- 0 until width) { + prepared.entries(lane).uop.decoded := io.fromD2.bits.entries(lane).uop + prepared.entries(lane).trap := io.fromD2.bits.entries(lane).trap + prepared.entries(lane).residentBound := + io.fromD2.bits.entries(lane).residentBound + prepared.entries(lane).brobBound := io.fromD2.bits.entries(lane).brobBound + prepared.entries(lane).blockStart := + io.fromD2.bits.entries(lane).uop.blockStart + prepared.entries(lane).blockStop := + io.fromD2.bits.entries(lane).uop.blockStop + val fastResultProducer = + io.fromD2.bits.entries(lane).uop.classification.disposition === + OooOpcodeDisposition.FastResolve.U && + (io.fromD2.bits.entries(lane).uop.classification.fastResolveClass === + OooFastResolveClass.ImmediateProducer.U || + io.fromD2.bits.entries(lane).uop.classification.fastResolveClass === + OooFastResolveClass.ControlValueProducer.U) + prepared.entries(lane).earlyRobComplete := + io.fromD2.bits.entries(lane).uop.earlyComplete && + !fastResultProducer + prepared.entries(lane).tSeqBefore := + tuRename.io.prepared.entries(lane).tSeqBefore + prepared.entries(lane).uSeqBefore := + tuRename.io.prepared.entries(lane).uSeqBefore + for (source <- 0 until p.maxSourceOperands) { + val base = prepared.entries(lane).uop.sources(source) + val pSrc = pRename.io.prepared.entries(lane).uop.sources(source) + val tuSrc = tuRename.io.prepared.entries(lane).uop.sources(source) + base.valid := io.fromD2.bits.entries(lane).uop.sources(source).valid + base.kind := io.fromD2.bits.entries(lane).uop.sources(source).kind + base.atag := io.fromD2.bits.entries(lane).uop.sources(source).atag + when(pSrc.ptagValid) { + base.ptag := pSrc.ptag + base.pGeneration := pSrc.pGeneration + base.ptagValid := true.B + base.ready := pSrc.ready + }.elsewhen(tuSrc.ttagValid) { + base.ttag := tuSrc.ttag + base.tGeneration := tuSrc.tGeneration + base.tSeqIndex := tuSrc.tSeqIndex + base.tSeqGeneration := tuSrc.tSeqGeneration + base.localEpoch := tuSrc.localEpoch + base.ttagValid := true.B + base.ready := tuSrc.ready + }.elsewhen(tuSrc.utagValid) { + base.utag := tuSrc.utag + base.uGeneration := tuSrc.uGeneration + base.uSeqIndex := tuSrc.uSeqIndex + base.uSeqGeneration := tuSrc.uSeqGeneration + base.localEpoch := tuSrc.localEpoch + base.utagValid := true.B + base.ready := tuSrc.ready + }.otherwise { + base.ready := true.B + } + } + for (dest <- 0 until p.maxDestinationOperands) { + val base = prepared.entries(lane).uop.destinations(dest) + val pDest = pRename.io.prepared.entries(lane).uop.destinations(dest) + val tuDest = tuRename.io.prepared.entries(lane).uop.destinations(dest) + val pHist = pRename.io.prepared.entries(lane).history(dest) + val tuHist = tuRename.io.prepared.entries(lane).history(dest) + base.valid := io.fromD2.bits.entries(lane).uop.destinations(dest).valid + base.kind := io.fromD2.bits.entries(lane).uop.destinations(dest).kind + base.atag := io.fromD2.bits.entries(lane).uop.destinations(dest).atag + when(pDest.ptagValid) { + base.ptag := pDest.ptag + base.previousPtag := pDest.previousPtag + base.pGeneration := pDest.pGeneration + base.previousPGeneration := pDest.previousPGeneration + base.previousPtagValid := pDest.previousPtagValid + base.ptagValid := true.B + prepared.entries(lane).history(dest) := pHist + }.elsewhen(tuDest.ttagValid) { + base.ttag := tuDest.ttag + base.tGeneration := tuDest.tGeneration + base.tSeqIndex := tuDest.tSeqIndex + base.tSeqGeneration := tuDest.tSeqGeneration + base.ttagValid := true.B + prepared.entries(lane).history(dest) := tuHist + }.elsewhen(tuDest.utagValid) { + base.utag := tuDest.utag + base.uGeneration := tuDest.uGeneration + base.uSeqIndex := tuDest.uSeqIndex + base.uSeqGeneration := tuDest.uSeqGeneration + base.utagValid := true.B + prepared.entries(lane).history(dest) := tuHist + } + } + } + + val prepareFenceValid = io.recovery.prepare.fire + val targetFenceValid = recoveryPending || prepareFenceValid + val targetFenceStid = Mux(recoveryPending, + safeStid(recoveryPlan.trigger.stid), + safeStid(io.recovery.prepare.bits.trigger.stid)) + val eligiblePending = Wire(Vec(p.ooo.stidCount, Bool())) + for (stid <- 0 until p.ooo.stidCount) { + eligiblePending(stid) := pendingValid(stid) && + !(targetFenceValid && targetFenceStid === stid.U) + } + val anyEligiblePending = eligiblePending.asUInt.orR + val nextPendingStid = PriorityEncoder(eligiblePending.asUInt) + val heldGrantEligible = if (p.ooo.stidCount == 1) { + heldGrantValid && eligiblePending(0) + } else { + heldGrantValid && eligiblePending(heldGrantStid) + } + val selectedPendingStid = if (p.ooo.stidCount == 1) { + 0.U(stidIndexWidth.W) + } else { + Mux(heldGrantEligible, heldGrantStid, nextPendingStid) + } + val selectedPending = if (p.ooo.stidCount == 1) { + pending(0) + } else { + pending(selectedPendingStid) + } + + val incomingStid = safeStid( + io.fromD2.bits.entries(0).uop.instruction.parent.identity.stid) + val incomingPending = if (p.ooo.stidCount == 1) { + pendingValid(0) + } else { + pendingValid(incomingStid) + } + val incomingFenced = targetFenceValid && incomingStid === targetFenceStid + val recoveryTargetStid = safeStid(recoveryPlan.trigger.stid) + val d2LaneShape = (0 until width).map { lane => + val active = lane.U < io.fromD2.bits.count + val laneUop = io.fromD2.bits.entries(lane).uop + laneUop.valid === active && + (!active || (laneUop.instruction.parent.identity.stid === + io.fromD2.bits.entries(0).uop.instruction.parent.identity.stid && + laneUop.rob.stid === + io.fromD2.bits.entries(0).uop.instruction.parent.identity.stid)) + } + val d2ShapeExact = io.fromD2.bits.count.orR && + io.fromD2.bits.count <= width.U && + io.fromD2.bits.groupCount.orR && + io.fromD2.bits.groupCount <= io.fromD2.bits.count && + d2LaneShape.reduce(_ && _) + io.candidate.valid := anyEligiblePending + io.candidate.bits := selectedPending + + val acceptedCount = io.prefixLimit.bits.count + val acceptedGroupCount = io.prefixLimit.bits.groupCount + val acceptedLaneGroupMatch = Wire(Vec(width, Vec(width, Bool()))) + for (lane <- 0 until width; group <- 0 until width) { + val row = selectedPending.entries(lane).uop.decoded.rob + val intent = selectedPending.groups(group) + acceptedLaneGroupMatch(lane)(group) := + lane.U < selectedPending.count && group.U < acceptedGroupCount && + intent.valid && intent.peId === row.peId && intent.stid === row.stid && + intent.ridSlot === row.ridSlot && + intent.ridGeneration === row.ridGeneration + } + val acceptedPrefixShape = (0 until width).map { lane => + val accepted = lane.U < acceptedCount + val matches = PopCount(acceptedLaneGroupMatch(lane)) + Mux(accepted, matches === 1.U, matches === 0.U) + }.reduce(_ && _) && (0 until width).map { group => + val accepted = group.U < acceptedGroupCount + val seen = (0 until width).map(lane => + acceptedLaneGroupMatch(lane)(group)).reduce(_ || _) + Mux(accepted, seen, !seen) + }.reduce(_ && _) + val prefixLimitExact = io.prefixLimit.valid && acceptedCount.orR && + acceptedCount <= selectedPending.count && acceptedGroupCount.orR && + acceptedGroupCount <= selectedPending.groupCount && + acceptedGroupCount <= acceptedCount && acceptedPrefixShape + + val selectedPrefix = Wire(new D3RenameGroup(p)) + selectedPrefix := 0.U.asTypeOf(selectedPrefix) + selectedPrefix.count := acceptedCount + selectedPrefix.groupCount := acceptedGroupCount + for (group <- 0 until width) { + when(group.U < acceptedGroupCount) { + selectedPrefix.groups(group) := selectedPending.groups(group) + } + } + for (lane <- 0 until width) { + when(lane.U < acceptedCount) { + selectedPrefix.entries(lane) := selectedPending.entries(lane) + } + } + io.toD3.valid := anyEligiblePending && prefixLimitExact + io.toD3.bits := selectedPrefix + val drainsSelectedRow = io.toD3.fire && + acceptedCount === selectedPending.count && + acceptedGroupCount === selectedPending.groupCount + val replacesSelectedStid = incomingPending && drainsSelectedRow && + selectedPendingStid === incomingStid + io.fromD2.ready := !incomingFenced && + (!incomingPending || replacesSelectedStid) && d2ShapeExact && + pRename.io.prepareReady && tuRename.io.prepareReady + + when(heldGrantValid && !heldGrantEligible) { + heldGrantValid := false.B + }.elsewhen(io.toD3.fire) { + heldGrantValid := false.B + }.elsewhen(!heldGrantValid && io.toD3.valid && !io.toD3.ready) { + heldGrantValid := true.B + heldGrantStid := nextPendingStid + } + + val compactedSuffix = Wire(new D3RenameGroup(p)) + compactedSuffix := 0.U.asTypeOf(compactedSuffix) + compactedSuffix.count := selectedPending.count - acceptedCount + compactedSuffix.groupCount := + selectedPending.groupCount - acceptedGroupCount + for (group <- 0 until width) { + for (source <- 0 until width) { + when(source.U === group.U + acceptedGroupCount && + source.U < selectedPending.groupCount) { + compactedSuffix.groups(group) := selectedPending.groups(source) + } + } + } + for (lane <- 0 until width) { + for (source <- 0 until width) { + when(source.U === lane.U + acceptedCount && + source.U < selectedPending.count) { + compactedSuffix.entries(lane) := selectedPending.entries(source) + } + } + } + when(io.toD3.fire) { + if (p.ooo.stidCount == 1) { + pending(0) := compactedSuffix + pendingValid(0) := compactedSuffix.count.orR + } else { + pending(selectedPendingStid) := compactedSuffix + pendingValid(selectedPendingStid) := compactedSuffix.count.orR + } + } + when(io.fromD2.fire) { + if (p.ooo.stidCount == 1) { + pending(0) := prepared + pendingValid(0) := true.B + } else { + pending(incomingStid) := prepared + pendingValid(incomingStid) := true.B + } + } + when(applyHit) { + if (p.ooo.stidCount == 1) { + pendingValid(0) := false.B + } else { + pendingValid(recoveryTargetStid) := false.B + } + } + + val publication = Wire(new D3RenameGroup(p)) + publication := selectedPrefix + when(io.toD3.valid && io.publicationIdentity.valid) { + assert(io.publicationIdentity.bits.count === acceptedCount, + "RENU publication identities must cover the exact retained D3 prefix") + for (lane <- 0 until width) { + when(lane.U < acceptedCount) { + assert(io.publicationIdentity.bits.entries(lane).valid) + publication.entries(lane).uop.decoded.rob := + io.publicationIdentity.bits.entries(lane).rob + } + } + } + pRename.io.publish.valid := io.toD3.fire + pRename.io.publish.bits := publication + pRename.io.reserve.valid := io.fromD2.fire + pRename.io.reserve.bits := prepared + pRename.io.cancel.valid := applyHit + pRename.io.cancel.bits := recoveryTargetStid + tuRename.io.publish.valid := io.toD3.fire + tuRename.io.publish.bits := publication + + when(io.fromD2.fire) { + when(incomingPending) { + assert(replacesSelectedStid, + "same-STID D2 replacement requires the final common D3 publication") + } + assert(io.fromD2.bits.count.orR) + assert(io.fromD2.bits.count <= width.U) + } +} diff --git a/chisel/src/main/scala/linxcore/ooo/ROB.scala b/chisel/src/main/scala/linxcore/ooo/ROB.scala new file mode 100644 index 00000000..78e730f1 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/ROB.scala @@ -0,0 +1,989 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams +import linxcore.top.interface._ + +object ROBState extends ChiselEnum { + val Free, Live, Completed, Retired = Value +} + +class ROBIO(val p: CoreParams) extends Bundle { + val candidate = Flipped(Valid(new D3RenameGroup(p))) + val prefixOffer = Output(Valid(new D3PrefixLimit(p))) + val prepare = Flipped(Decoupled(new D3RenameGroup(p))) + val brobPrepared = Input(new BROBPrepared(p)) + val prepared = Output(new OOORobPrepared(p)) + val publicationTransactionBase = Input(UInt(p.transactionIdWidth.W)) + val publishFire = Input(Bool()) + val completion = Flipped(Decoupled(new RobResolveTxn(p))) + val storeBinding = Flipped(Vec(p.iex.stdPipes, + Decoupled(new StoreTransactionBindingTxn(p)))) + val completionAccepted = Valid(new RobIdentity(p)) + val completionRejected = Valid(new RobIdentity(p)) + val commit = Decoupled(new OOORobCommitPreview(p)) + val residentHeads = Output(Vec(p.ooo.stidCount, + new OOORobResidentHeadPreview(p))) + val headStatus = Output(Vec(p.ooo.stidCount, new OOORobHeadStatus(p))) + val commitApply = Input(Bool()) + val release = Flipped(Valid(new OOORobReleaseTxn(p))) + val releaseReady = Output(Bool()) + val releaseApply = Input(Bool()) + val recoveryPrepare = Flipped(Decoupled(new RecoveryPlan(p))) + val recoveryPrepared = Valid(new RecoveryPlan(p)) + val memoryRecoveryPrepared = Output(new OOORobMemoryRecovery(p)) + val recoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val recoveryAbort = Flipped(Valid(new RecoveryPlan(p))) + val recoveryCandidate = Input(Vec(2, Valid(new RecoveryCandidateLookup(p)))) + val recoveryCandidateStatus = Output(Vec(2, Valid(new RecoveryCandidateStatus(p)))) + val ridTailSlot = Output(Vec(p.ooo.stidCount, + UInt(p.ooo.ridSlotWidth.W))) + val ridTailGeneration = Output(Vec(p.ooo.stidCount, + UInt(p.ridGenerationWidth.W))) + val ridHeadSlot = Output(Vec(p.ooo.stidCount, + UInt(p.ooo.ridSlotWidth.W))) +} + +class ROB(val p: CoreParams) extends Module { + require(p.ooo.robBankCount > 0) + require(p.ooo.robBankCount <= p.ooo.robGroupsPerStid) + require(p.ooo.robGroupsPerStid % p.ooo.robBankCount == 0) + RecoveryAge.requireUnambiguousWindow(p) + + val io = IO(new ROBIO(p)) + + private val stidWidth = p.ooo.stidWidth + private val slotWidth = p.ooo.ridSlotWidth + private val memberWidth = p.ooo.robMemberIndexWidth + private val retireWidth = p.widths.retireWidth + private val d3Width = p.ooo.d3PrefixWidth + private val robRowsPerBank = p.ooo.robGroupsPerStid / p.ooo.robBankCount + + private def fitIndex(value: UInt, size: Int): UInt = { + val width = log2Ceil(size) + if (size == 1) 0.U(0.W) else Cat(0.U(width.W), value)(width - 1, 0) + } + + private def stidIndex(stid: UInt): UInt = + fitIndex(stid, p.ooo.stidCount) + + private def robBank(slot: UInt): UInt = + fitIndex(slot % p.ooo.robBankCount.U, p.ooo.robBankCount) + + private def robRow(slot: UInt): UInt = + fitIndex(slot / p.ooo.robBankCount.U, robRowsPerBank) + + private def memberIndex(member: UInt): UInt = + fitIndex(member, p.ooo.maxInstructionsPerRobGroup) + + private def safeStid(stid: UInt): UInt = + if (p.ooo.stidCount == 1) 0.U(stidWidth.W) else stid + + private def slotPlus(slot: UInt, add: UInt): (UInt, Bool) = { + val sum = slot +& add + val wrap = sum >= p.ooo.robGroupsPerStid.U + (Mux(wrap, (sum - p.ooo.robGroupsPerStid.U)(slotWidth - 1, 0), + sum(slotWidth - 1, 0)), wrap) + } + + val state = RegInit(VecInit(Seq.fill(p.ooo.stidCount) { + VecInit(Seq.fill(p.ooo.robBankCount) { + VecInit(Seq.fill(robRowsPerBank) { + VecInit(Seq.fill(p.ooo.maxInstructionsPerRobGroup) { ROBState.Free }) + }) + }) + })) + val memberLive = RegInit(VecInit(Seq.fill(p.ooo.stidCount) { + VecInit(Seq.fill(p.ooo.robBankCount) { + VecInit(Seq.fill(robRowsPerBank) { + VecInit(Seq.fill(p.ooo.maxInstructionsPerRobGroup) { false.B }) + }) + }) + })) + val identities = Reg(Vec(p.ooo.stidCount, + Vec(p.ooo.robBankCount, + Vec(robRowsPerBank, + Vec(p.ooo.maxInstructionsPerRobGroup, new RobIdentity(p)))))) + val commits = Reg(Vec(p.ooo.stidCount, + Vec(p.ooo.robBankCount, + Vec(robRowsPerBank, + Vec(p.ooo.maxInstructionsPerRobGroup, new CommitEntry(p)))))) + val renames = Reg(Vec(p.ooo.stidCount, + Vec(p.ooo.robBankCount, + Vec(robRowsPerBank, + Vec(p.ooo.maxInstructionsPerRobGroup, new RenameCommitReleaseEntry(p)))))) + + val headSlot = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(slotWidth.W)))) + val headGeneration = + RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(p.ridGenerationWidth.W)))) + val tailSlot = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(slotWidth.W)))) + val tailGeneration = + RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(p.ridGenerationWidth.W)))) + val retireSlot = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(slotWidth.W)))) + val retireGeneration = + RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(p.ridGenerationWidth.W)))) + val groupCount = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(PrefixPacketContract.countWidth(p.ooo.robGroupsPerStid).W)))) + val residentGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount) { + VecInit(Seq.fill(p.ooo.robBankCount) { + VecInit(Seq.fill(robRowsPerBank) { + VecInit(Seq.fill(p.ooo.maxInstructionsPerRobGroup) { + 0.U(p.residentGenerationWidth.W) + }) + }) + }) + })) + + private def stateAt(stid: UInt, slot: UInt, member: UInt) = + state(stidIndex(stid))(robBank(slot))(robRow(slot))(memberIndex(member)) + private def memberLiveAt(stid: UInt, slot: UInt, member: UInt) = + memberLive(stidIndex(stid))(robBank(slot))(robRow(slot))(memberIndex(member)) + private def identityAt(stid: UInt, slot: UInt, member: UInt) = + identities(stidIndex(stid))(robBank(slot))(robRow(slot))(memberIndex(member)) + private def commitAt(stid: UInt, slot: UInt, member: UInt) = + commits(stidIndex(stid))(robBank(slot))(robRow(slot))(memberIndex(member)) + private def renameAt(stid: UInt, slot: UInt, member: UInt) = + renames(stidIndex(stid))(robBank(slot))(robRow(slot))(memberIndex(member)) + private def residentGenerationAt(stid: UInt, slot: UInt, member: UInt) = + residentGeneration(stidIndex(stid))(robBank(slot))(robRow(slot))( + memberIndex(member)) + private val orderCapacity = p.ooo.robCapacityPerStid + private val orderPtrWidth = InterfaceWidth.index(orderCapacity) + val orderIds = Reg(Vec(p.ooo.stidCount, + Vec(orderCapacity, new RobIdentity(p)))) + val orderCommits = Reg(Vec(p.ooo.stidCount, + Vec(orderCapacity, new CommitEntry(p)))) + val orderRenames = Reg(Vec(p.ooo.stidCount, + Vec(orderCapacity, new RenameCommitReleaseEntry(p)))) + val orderMemoryBefore = Reg(Vec(p.ooo.stidCount, + Vec(orderCapacity, new MemoryOrderState(p)))) + val orderMemoryAfter = Reg(Vec(p.ooo.stidCount, + Vec(orderCapacity, new MemoryOrderState(p)))) + val orderNoflushEligible = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(false.B))))) + val orderValid = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(false.B))))) + val orderCompleted = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(false.B))))) + val orderRetired = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(false.B))))) + val orderAge = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(0.U(p.transactionIdWidth.W)))))) + val orderTransactionId = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + VecInit(Seq.fill(orderCapacity)(0.U(p.transactionIdWidth.W)))))) + val nextAllocationAge = RegInit(0.U(p.transactionIdWidth.W)) + val orderHead = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(orderPtrWidth.W)))) + val orderCommitHead = + RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(orderPtrWidth.W)))) + val orderTail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(orderPtrWidth.W)))) + val orderCount = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(PrefixPacketContract.countWidth(orderCapacity).W)))) + val orderCommitCount = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(PrefixPacketContract.countWidth(orderCapacity).W)))) + + private def orderPlus(ptr: UInt, add: UInt): UInt = { + val sum = ptr +& add + Mux(sum >= orderCapacity.U, sum - orderCapacity.U, sum)(orderPtrWidth - 1, 0) + } + + io.ridTailSlot := tailSlot + io.ridTailGeneration := tailGeneration + io.ridHeadSlot := headSlot + + for (stid <- 0 until p.ooo.stidCount) { + val idx = orderCommitHead(stid) + io.headStatus(stid) := 0.U.asTypeOf(io.headStatus(stid)) + io.headStatus(stid).valid := orderCommitCount(stid) =/= 0.U && + orderValid(stid)(idx) + io.headStatus(stid).completed := orderCompleted(stid)(idx) + io.headStatus(stid).retired := orderRetired(stid)(idx) + io.headStatus(stid).transactionId := orderTransactionId(stid)(idx) + io.headStatus(stid).instruction := orderCommits(stid)(idx).instruction + io.headStatus(stid).rob := orderIds(stid)(idx) + io.headStatus(stid).pc := orderCommits(stid)(idx).pc + io.headStatus(stid).instructionBits := + orderCommits(stid)(idx).instructionBits + io.headStatus(stid).opcode := orderCommits(stid)(idx).opcode + } + dontTouch(io.headStatus) + + // Side-effect-free capacity offer for the oldest complete candidate groups. + // BROB bindings are deliberately absent here; final binding remains on the + // selected `prepare` transaction below. + val candidate = io.candidate.bits + val candidateStidRaw = candidate.entries(0).uop.decoded.rob.stid + val candidateStidInRange = candidateStidRaw < p.ooo.stidCount.U + val candidateStid = safeStid(candidateStidRaw) + val candidateLaneGroupMatch = Wire(Vec(d3Width, Vec(d3Width, Bool()))) + for (lane <- 0 until d3Width; group <- 0 until d3Width) { + val row = candidate.entries(lane).uop.decoded.rob + val intent = candidate.groups(group) + candidateLaneGroupMatch(lane)(group) := lane.U < candidate.count && + group.U < candidate.groupCount && intent.valid && + intent.peId === row.peId && intent.stid === row.stid && + intent.ridSlot === row.ridSlot && + intent.ridGeneration === row.ridGeneration + } + val candidateLaneExact = Wire(Vec(d3Width, Bool())) + for (lane <- 0 until d3Width) { + val active = lane.U < candidate.count + val row = candidate.entries(lane).uop.decoded + val selectedGroup = PriorityEncoder(candidateLaneGroupMatch(lane).asUInt) + val (expectedSlot, expectedWrap) = slotPlus( + tailSlot(candidateStid), selectedGroup) + val priorMembers = PopCount((0 until lane).map { prior => + candidateLaneGroupMatch(prior)(selectedGroup) + }) + candidateLaneExact(lane) := Mux(active, + row.valid && PopCount(candidateLaneGroupMatch(lane)) === 1.U && + row.rob.stid === candidateStidRaw && + row.rob.ridSlot === expectedSlot && + row.rob.ridGeneration === + tailGeneration(candidateStid) + expectedWrap.asUInt && + row.rob.memberIndex === priorMembers && + row.rob.memberIndex < p.ooo.maxInstructionsPerRobGroup.U && + !memberLiveAt(candidateStid, expectedSlot, row.rob.memberIndex), + !row.valid && !candidateLaneGroupMatch(lane).asUInt.orR) + } + val candidateGroupExact = Wire(Vec(d3Width, Bool())) + val candidateOfferChain = Wire(Vec(d3Width + 1, Bool())) + val candidateAcceptedGroup = Wire(Vec(d3Width, Bool())) + candidateOfferChain(0) := true.B + val candidateFreeGroups = p.ooo.robGroupsPerStid.U - + groupCount(candidateStid) + for (group <- 0 until d3Width) { + val active = group.U < candidate.groupCount + val groupSeen = (0 until d3Width).map { lane => + candidateLaneGroupMatch(lane)(group) + }.reduce(_ || _) + val groupLanesExact = (0 until d3Width).map { lane => + !candidateLaneGroupMatch(lane)(group) || candidateLaneExact(lane) + }.reduce(_ && _) + candidateGroupExact(group) := active && candidate.groups(group).valid && + groupSeen && groupLanesExact + candidateAcceptedGroup(group) := candidateOfferChain(group) && + candidateGroupExact(group) && group.U < candidateFreeGroups + candidateOfferChain(group + 1) := candidateAcceptedGroup(group) + } + val candidateOfferedGroups = PopCount(candidateAcceptedGroup) + val candidateOfferedLanes = PopCount((0 until d3Width).map { lane => + lane.U < candidate.count && (0 until d3Width).map { group => + group.U < candidateOfferedGroups && + candidateLaneGroupMatch(lane)(group) + }.reduce(_ || _) + }) + val candidateShapeExact = candidate.count.orR && + candidate.count <= d3Width.U && candidate.groupCount.orR && + candidate.groupCount <= candidate.count && + candidate.groupCount <= d3Width.U + io.prefixOffer.valid := io.candidate.valid && candidateStidInRange && + candidateShapeExact && candidateOfferedGroups.orR && + candidateOfferedLanes.orR + io.prefixOffer.bits.count := candidateOfferedLanes + io.prefixOffer.bits.groupCount := candidateOfferedGroups + + val prepareStid = safeStid(io.prepare.bits.entries(0).uop.decoded.rob.stid) + val prepareCountLegal = + io.prepare.bits.count > 0.U && io.prepare.bits.count <= d3Width.U + val prepareGroupCountLegal = + io.prepare.bits.groupCount > 0.U && + io.prepare.bits.groupCount <= io.prepare.bits.count + val prepareCapacity = + groupCount(prepareStid) + io.prepare.bits.groupCount <= + p.ooo.robGroupsPerStid.U + val prepareShape = (0 until d3Width).map { lane => + val active = lane.U < io.prepare.bits.count + val row = io.prepare.bits.entries(lane) + row.uop.decoded.valid === active && + (!active || row.uop.decoded.rob.stid === prepareStid) + }.reduce(_ && _) + val prepareGroupStarts = Wire(Vec(d3Width, Bool())) + val prepareGroupOrdinal = Wire(Vec(d3Width, + UInt(PrefixPacketContract.countWidth(d3Width).W))) + for (lane <- 0 until d3Width) { + val active = lane.U < io.prepare.bits.count + val row = io.prepare.bits.entries(lane) + prepareGroupStarts(lane) := active && row.uop.decoded.rob.memberIndex === 0.U + prepareGroupOrdinal(lane) := PopCount(prepareGroupStarts.take(lane + 1)) - 1.U + } + val prepareExactRows = (0 until d3Width).map { lane => + val active = lane.U < io.prepare.bits.count + val row = io.prepare.bits.entries(lane) + val ordinal = prepareGroupOrdinal(lane) + val (expectedSlot, expectedWrap) = slotPlus(tailSlot(prepareStid), ordinal) + val expectedGen = tailGeneration(prepareStid) + expectedWrap.asUInt + val expectedResidentGeneration = residentGenerationAt( + prepareStid, expectedSlot, row.uop.decoded.rob.memberIndex) + val firstLane = lane == 0 + val prev = if (firstLane) row else io.prepare.bits.entries(lane - 1) + val continuousMember = if (firstLane) { + row.uop.decoded.rob.memberIndex === 0.U + } else { + Mux(row.uop.decoded.rob.memberIndex === 0.U, + row.uop.decoded.rob.ridSlot =/= prev.uop.decoded.rob.ridSlot, + row.uop.decoded.rob.ridSlot === prev.uop.decoded.rob.ridSlot && + row.uop.decoded.rob.memberIndex === + prev.uop.decoded.rob.memberIndex + 1.U) + } + !active || ( + row.uop.decoded.rob.ridSlot === expectedSlot && + row.uop.decoded.rob.ridGeneration === expectedGen && + row.uop.decoded.rob.memberIndex < p.ooo.maxInstructionsPerRobGroup.U && + (!row.residentBound || + row.uop.decoded.rob.residentGeneration === expectedResidentGeneration) && + continuousMember && + !memberLiveAt(prepareStid, expectedSlot, row.uop.decoded.rob.memberIndex)) + }.reduce(_ && _) + val brobExact = (0 until d3Width).map { lane => + val active = lane.U < io.prepare.bits.count + val row = io.prepare.bits.entries(lane) + val binding = io.brobPrepared.entries(lane) + val rawBindingExact = !row.brobBound || ( + row.uop.decoded.rob.bid === binding.bid && + row.uop.decoded.rob.brobGeneration === binding.brobGeneration) + val previousBindingExact = if (lane == 0) { + true.B + } else { + val previousActive = (lane - 1).U < io.prepare.bits.count + val previous = io.brobPrepared.entries(lane - 1) + !previousActive || row.blockStart || ( + binding.bid === previous.bid && + binding.brobGeneration === previous.brobGeneration) + } + Mux(active, + io.brobPrepared.count === io.prepare.bits.count && + binding.valid && + binding.stid === prepareStid && + (!row.blockStart || binding.allocated) && + rawBindingExact && previousBindingExact, + !binding.valid) + }.reduce(_ && _) + val memoryReservationExact = io.prepare.bits.memoryOrder.valid && + io.prepare.bits.memoryOrder.stid === prepareStid && + io.prepare.bits.memoryOrder.count === io.prepare.bits.count + val prepareReady = prepareCountLegal && prepareGroupCountLegal && + prepareCapacity && prepareShape && prepareExactRows && + PopCount(prepareGroupStarts) === io.prepare.bits.groupCount && + brobExact && memoryReservationExact + io.prepare.ready := prepareReady + + val prepared = Wire(new OOORobPrepared(p)) + prepared := 0.U.asTypeOf(prepared) + prepared.count := io.prepare.bits.count + for (lane <- 0 until d3Width) { + val active = lane.U < io.prepare.bits.count + val in = io.prepare.bits.entries(lane) + val rid = in.uop.decoded.rob.ridSlot + val member = in.uop.decoded.rob.memberIndex + prepared.entries(lane).valid := active + prepared.entries(lane).rob := in.uop.decoded.rob + when(active) { + prepared.entries(lane).rob.bid := io.brobPrepared.entries(lane).bid + prepared.entries(lane).rob.brobGeneration := + io.brobPrepared.entries(lane).brobGeneration + } + prepared.entries(lane).rob.residentGeneration := + residentGenerationAt(prepareStid, rid, member) + prepared.entries(lane).commit.instruction := + in.uop.decoded.instruction.parent.identity + prepared.entries(lane).commit.rob := prepared.entries(lane).rob + prepared.entries(lane).commit.pc := in.uop.decoded.instruction.parent.pc + prepared.entries(lane).commit.pcBufferIndexOffset := + in.pcBufferIndexOffset + val nextSharesGroup = if (lane == d3Width - 1) false.B else { + val next = io.prepare.bits.entries(lane + 1).uop.decoded.rob + lane.U + 1.U < io.prepare.bits.count && + next.peId === in.uop.decoded.rob.peId && + next.stid === in.uop.decoded.rob.stid && + next.ridSlot === in.uop.decoded.rob.ridSlot && + next.ridGeneration === in.uop.decoded.rob.ridGeneration + } + prepared.entries(lane).commit.robGroupLast := active && !nextSharesGroup + prepared.entries(lane).commit.instructionBits := + in.uop.decoded.instruction.parent.instruction + prepared.entries(lane).commit.instructionLengthBytes := + in.uop.decoded.instruction.parent.lengthBytes + prepared.entries(lane).commit.opcode := in.uop.decoded.opcode + prepared.entries(lane).commit.memoryValid := + in.uop.decoded.memory.valid + prepared.entries(lane).commit.memoryStore := + in.uop.decoded.memory.isStore + prepared.entries(lane).commit.memory.rob := prepared.entries(lane).rob + prepared.entries(lane).commit.memory.lsid := in.memoryOrder.firstLsid + prepared.entries(lane).commit.memoryOrder := in.memoryOrder + prepared.entries(lane).commit.destination := in.uop.destinations(0) + prepared.entries(lane).commit.trap.valid := in.trap.valid + prepared.entries(lane).commit.trap.kind := TrapKind.Exception + prepared.entries(lane).commit.trap.cause := in.trap.cause + prepared.entries(lane).commit.trap.rob := prepared.entries(lane).rob + prepared.entries(lane).commit.trap.instruction := + in.uop.decoded.instruction.parent.identity + prepared.entries(lane).rename.valid := active + prepared.entries(lane).rename.rob := prepared.entries(lane).rob + prepared.entries(lane).rename.epoch := + in.uop.decoded.instruction.parent.identity.epoch + prepared.entries(lane).rename.blockLast := in.uop.decoded.blockBoundary + prepared.entries(lane).rename.history := in.history + } + io.prepared := prepared + + val prepareMemoryState = Wire(Vec(d3Width + 1, new MemoryOrderState(p))) + prepareMemoryState(0) := io.prepare.bits.memoryOrder.before + for (lane <- 0 until d3Width) { + val meta = io.prepare.bits.entries(lane).memoryOrder + val decoded = io.prepare.bits.entries(lane).uop.decoded + val active = lane.U < io.prepare.bits.count && meta.requestCount.orR + prepareMemoryState(lane + 1) := prepareMemoryState(lane) + prepareMemoryState(lane + 1).lsid := prepareMemoryState(lane).lsid + + Mux(active, meta.requestCount, 0.U) + prepareMemoryState(lane + 1).lid := prepareMemoryState(lane).lid + + Mux(active && decoded.memory.isLoad, meta.requestCount, 0.U) + prepareMemoryState(lane + 1).sid := prepareMemoryState(lane).sid + + Mux(active && decoded.memory.isStore, meta.requestCount, 0.U) + when(active && decoded.memory.isLoad) { + prepareMemoryState(lane + 1).yoldValid := true.B + prepareMemoryState(lane + 1).yoldLsid := + meta.firstLsid + meta.requestCount - 1.U + prepareMemoryState(lane + 1).yoldLid := + meta.firstLid + meta.requestCount - 1.U + } + when(active && decoded.memory.isStore) { + prepareMemoryState(lane + 1).yostValid := true.B + prepareMemoryState(lane + 1).yostLsid := + meta.firstLsid + meta.requestCount - 1.U + prepareMemoryState(lane + 1).yostSid := + meta.firstSid + meta.requestCount - 1.U + } + } + + val preparedStoreBindingMatches = io.storeBinding.map { binding => + VecInit((0 until d3Width).map { lane => + val entry = prepared.entries(lane) + lane.U < io.prepare.bits.count && entry.valid && + entry.rob.asUInt === binding.bits.rob.asUInt && + entry.commit.memoryStore && + entry.commit.memoryOrder.asUInt === binding.bits.memoryOrder.asUInt + }) + } + + when(io.prepare.valid && io.publishFire && prepareReady) { + for (lane <- 0 until d3Width) { + when(lane.U < io.prepare.bits.count) { + val id = prepared.entries(lane).rob + val stid = safeStid(id.stid) + val slot = id.ridSlot + val member = id.memberIndex + identityAt(stid, slot, member) := id + commitAt(stid, slot, member) := prepared.entries(lane).commit + renameAt(stid, slot, member) := prepared.entries(lane).rename + memberLiveAt(stid, slot, member) := true.B + stateAt(stid, slot, member) := Mux( + io.prepare.bits.entries(lane).earlyRobComplete, + ROBState.Completed, + ROBState.Live) + val orderIndex = orderPlus(orderTail(stid), lane.U) + orderIds(stid)(orderIndex) := id + orderCommits(stid)(orderIndex) := prepared.entries(lane).commit + orderRenames(stid)(orderIndex) := prepared.entries(lane).rename + orderMemoryBefore(stid)(orderIndex) := prepareMemoryState(lane) + orderMemoryAfter(stid)(orderIndex) := prepareMemoryState(lane + 1) + orderNoflushEligible(stid)(orderIndex) := + (io.prepare.bits.entries(lane).uop.decoded.uopClass === UopClass.System || + io.prepare.bits.entries(lane).uop.decoded.uopClass === UopClass.Cmd) && + !io.prepare.bits.entries(lane).uop.destinations.map(_.valid).reduce(_ || _) + orderValid(stid)(orderIndex) := true.B + orderCompleted(stid)(orderIndex) := + io.prepare.bits.entries(lane).earlyRobComplete + orderRetired(stid)(orderIndex) := false.B + orderAge(stid)(orderIndex) := nextAllocationAge + lane.U + orderTransactionId(stid)(orderIndex) := + io.publicationTransactionBase + lane.U + val initialBinding = VecInit(io.storeBinding.indices.map { port => + io.storeBinding(port).valid && + preparedStoreBindingMatches(port)(lane) + }) + when(prepared.entries(lane).commit.memoryStore) { + when(PopCount(initialBinding) === 1.U) { + val transaction = Mux1H(initialBinding, + io.storeBinding.map(_.bits.transaction)) + commitAt(stid, slot, member).memory.transaction := transaction + orderCommits(stid)(orderIndex).memory.transaction := transaction + } + }.otherwise { + assert(!initialBinding.asUInt.orR, + "an initial store binding must not target a non-store D3 row") + } + } + } + val (nextTail, wrap) = slotPlus(tailSlot(prepareStid), + io.prepare.bits.groupCount) + tailSlot(prepareStid) := nextTail + tailGeneration(prepareStid) := tailGeneration(prepareStid) + wrap.asUInt + groupCount(prepareStid) := groupCount(prepareStid) + + io.prepare.bits.groupCount + orderTail(prepareStid) := + orderPlus(orderTail(prepareStid), io.prepare.bits.count) + orderCount(prepareStid) := orderCount(prepareStid) + io.prepare.bits.count + orderCommitCount(prepareStid) := + orderCommitCount(prepareStid) + io.prepare.bits.count + nextAllocationAge := nextAllocationAge + io.prepare.bits.count + } + + val storeBindingMatches = io.storeBinding.map { binding => + val stid = safeStid(binding.bits.rob.stid) + VecInit((0 until orderCapacity).map { idx => + orderValid(stid)(idx) && + orderIds(stid)(idx).asUInt === binding.bits.rob.asUInt && + orderCommits(stid)(idx).memoryStore && + orderCommits(stid)(idx).memoryOrder.asUInt === + binding.bits.memoryOrder.asUInt + }) + } + for (lane <- io.storeBinding.indices) { + val binding = io.storeBinding(lane) + val matches = storeBindingMatches(lane) + val residentHit = binding.bits.rob.stid < p.ooo.stidCount.U && + matches.asUInt.orR + val preparedMatches = preparedStoreBindingMatches(lane) + val preparedHit = io.prepare.valid && prepareReady && + binding.bits.rob.stid < p.ooo.stidCount.U && + preparedMatches.asUInt.orR + val index = PriorityEncoder(matches) + binding.ready := (residentHit && PopCount(matches) === 1.U) || + (preparedHit && PopCount(preparedMatches) === 1.U) + when(binding.valid) { + assert(PopCount(matches) + PopCount(preparedMatches) <= 1.U, + "one IEX store transaction may match at most one exact ROB resident or prepared row") + } + when(binding.fire && residentHit) { + val stid = safeStid(binding.bits.rob.stid) + val id = binding.bits.rob + commitAt(stid, id.ridSlot, id.memberIndex).memory.transaction := + binding.bits.transaction + orderCommits(stid)(index).memory.transaction := binding.bits.transaction + } + } + for (left <- io.storeBinding.indices; right <- left + 1 until io.storeBinding.length) { + when(io.storeBinding(left).valid && io.storeBinding(right).valid) { + assert((storeBindingMatches(left).asUInt & + storeBindingMatches(right).asUInt) === 0.U, + "simultaneous IEX store bindings must target distinct ROB residents") + assert((preparedStoreBindingMatches(left).asUInt & + preparedStoreBindingMatches(right).asUInt) === 0.U, + "simultaneous IEX store bindings must target distinct prepared ROB rows") + } + } + + val comp = io.completion.bits.rob + val compStid = safeStid(comp.stid) + val compMatches = Wire(Vec(orderCapacity, Bool())) + for (idx <- 0 until orderCapacity) { + compMatches(idx) := comp.stid < p.ooo.stidCount.U && + orderValid(compStid)(idx) && + orderIds(compStid)(idx).asUInt === comp.asUInt && + !orderCompleted(compStid)(idx) + } + val compHit = compMatches.asUInt.orR + val compIndex = PriorityEncoder(compMatches.asUInt) + io.completion.ready := true.B + val completionAcceptedReg = RegInit(false.B) + val completionRejectedReg = RegInit(false.B) + val completionReportedRob = Reg(new RobIdentity(p)) + io.completionAccepted.valid := completionAcceptedReg + io.completionAccepted.bits := completionReportedRob + io.completionRejected.valid := completionRejectedReg + io.completionRejected.bits := completionReportedRob + completionAcceptedReg := false.B + completionRejectedReg := false.B + when(io.completion.fire) { + completionReportedRob := comp + completionAcceptedReg := compHit + completionRejectedReg := !compHit + when(compHit) { + orderCompleted(compStid)(compIndex) := true.B + stateAt(compStid, comp.ridSlot, comp.memberIndex) := ROBState.Completed + commitAt(compStid, comp.ridSlot, comp.memberIndex).resultValid := + io.completion.bits.destinationValid + commitAt(compStid, comp.ridSlot, comp.memberIndex).result := + io.completion.bits.value + commitAt(compStid, comp.ridSlot, comp.memberIndex).trap := + io.completion.bits.trap + } + } + + val preview = Wire(new OOORobCommitPreview(p)) + preview := 0.U.asTypeOf(preview) + val stidPrefixCounts = Wire(Vec(p.ooo.stidCount, + UInt(PrefixPacketContract.countWidth(retireWidth).W))) + val stidHeadValid = Wire(Vec(p.ooo.stidCount, Bool())) + val stidHeadTrap = Wire(Vec(p.ooo.stidCount, Bool())) + for (stid <- 0 until p.ooo.stidCount) { + val headIdx = orderCommitHead(stid) + val headRob = orderIds(stid)(headIdx) + stidHeadValid(stid) := orderCommitCount(stid) =/= 0.U && + orderValid(stid)(headIdx) && orderCompleted(stid)(headIdx) && + !orderRetired(stid)(headIdx) + stidHeadTrap(stid) := stidHeadValid(stid) && + orderCommits(stid)(headIdx).trap.valid + val counts = Wire(Vec(retireWidth + 1, + UInt(PrefixPacketContract.countWidth(retireWidth).W))) + counts(0) := 0.U + for (lane <- 0 until retireWidth) { + val idx = orderPlus(orderCommitHead(stid), lane.U) + val rowRob = orderIds(stid)(idx) + val sameBrobBlock = rowRob.bid === headRob.bid && + rowRob.brobGeneration === headRob.brobGeneration + val completed = lane.U < orderCommitCount(stid) && + orderValid(stid)(idx) && orderCompleted(stid)(idx) && + !orderRetired(stid)(idx) && + !orderCommits(stid)(idx).trap.valid && sameBrobBlock + counts(lane + 1) := Mux(counts(lane) === lane.U && completed, + (lane + 1).U, + counts(lane)) + } + stidPrefixCounts(stid) := counts(retireWidth) + } + val eligibleStids = VecInit((0 until p.ooo.stidCount).map { stid => + stidPrefixCounts(stid) =/= 0.U || stidHeadTrap(stid) + }) + val selectedStid = PriorityEncoder(eligibleStids.asUInt) + for (lane <- 0 until retireWidth) { + val idx = orderPlus(orderCommitHead(selectedStid), lane.U) + preview.entries(lane).valid := lane.U < stidPrefixCounts(selectedStid) + preview.entries(lane).commit := orderCommits(selectedStid)(idx) + preview.entries(lane).rename := orderRenames(selectedStid)(idx) + } + preview.count := stidPrefixCounts(selectedStid) + preview.headValid := stidHeadValid(selectedStid) + preview.head := orderIds(selectedStid)(orderCommitHead(selectedStid)) + preview.headTrap := orderCommits(selectedStid)(orderCommitHead(selectedStid)).trap + preview.headTrap.valid := stidHeadTrap(selectedStid) + for (stid <- 0 until p.ooo.stidCount) { + val completedPrefix = Wire(Vec(orderCapacity + 1, Bool())) + val noflushCandidates = Wire(Vec(orderCapacity, Bool())) + completedPrefix(0) := true.B + for (offset <- 0 until orderCapacity) { + val scanIdx = orderPlus(orderHead(stid), offset.U) + val active = offset.U < orderCount(stid) && orderValid(stid)(scanIdx) + val completed = orderCompleted(stid)(scanIdx) || + orderRetired(stid)(scanIdx) + noflushCandidates(offset) := completedPrefix(offset) && active && + !completed && + memberLiveAt(stid.U, orderIds(stid)(scanIdx).ridSlot, + orderIds(stid)(scanIdx).memberIndex) && + !orderCommits(stid)(scanIdx).trap.valid && + orderNoflushEligible(stid)(scanIdx) + completedPrefix(offset + 1) := completedPrefix(offset) && active && + completed && !orderCommits(stid)(scanIdx).trap.valid + } + val eligible = noflushCandidates.asUInt.orR + val eligibleOffset = PriorityEncoder(noflushCandidates) + val idx = orderPlus(orderHead(stid), eligibleOffset) + io.residentHeads(stid) := 0.U.asTypeOf(io.residentHeads(stid)) + io.residentHeads(stid).valid := eligible + io.residentHeads(stid).transactionId := orderTransactionId(stid)(idx) + io.residentHeads(stid).instruction := orderCommits(stid)(idx).instruction + io.residentHeads(stid).rob := orderIds(stid)(idx) + io.residentHeads(stid).noflushEligible := eligible + } + val previewValid = preview.count =/= 0.U + val previewTxnValid = previewValid || preview.headTrap.valid + val retainedValid = RegInit(false.B) + val retained = Reg(new OOORobCommitPreview(p)) + val useRetained = retainedValid + io.commit.valid := useRetained || previewTxnValid + io.commit.bits := Mux(useRetained, retained, preview) + val commitApplyFire = io.commit.valid && io.commitApply + when(io.commit.valid && !io.commit.ready && !retainedValid) { + retained := preview + retainedValid := true.B + }.elsewhen(commitApplyFire && retainedValid) { + retainedValid := false.B + } + when(commitApplyFire) { + val applyCount = Mux(io.release.valid, io.release.bits.count, + io.commit.bits.count) + for (lane <- 0 until retireWidth) { + when(lane.U < applyCount) { + val id = Mux(io.release.valid, io.release.bits.lanes(lane).rob, + io.commit.bits.entries(lane).commit.rob) + val stid = safeStid(id.stid) + stateAt(stid, id.ridSlot, id.memberIndex) := ROBState.Retired + for (idx <- 0 until orderCapacity) { + when(orderValid(stid)(idx) && orderIds(stid)(idx).asUInt === id.asUInt) { + orderRetired(stid)(idx) := true.B + } + } + } + } + val firstId = Mux(io.release.valid, io.release.bits.lanes(0).rob, + io.commit.bits.entries(0).commit.rob) + val stid = safeStid(firstId.stid) + val (nextRetire, wrap) = slotPlus(retireSlot(stid), + applyCount) + retireSlot(stid) := nextRetire + retireGeneration(stid) := retireGeneration(stid) + wrap.asUInt + orderCommitHead(stid) := orderPlus(orderCommitHead(stid), + applyCount) + orderCommitCount(stid) := orderCommitCount(stid) - applyCount + when(io.release.valid) { + assert(io.releaseApply && io.releaseReady, + "ROB commit must apply the authoritative retained release transaction") + assert(io.release.bits.count <= io.commit.bits.count, + "ROB authoritative apply count cannot exceed the live preview") + for (lane <- 0 until retireWidth) { + when(lane.U < io.release.bits.count) { + assert(io.release.bits.lanes(lane).valid) + assert(io.release.bits.lanes(lane).rob.asUInt === + io.commit.bits.entries(lane).commit.rob.asUInt, + "ROB authoritative apply identity must match the live preview prefix") + } + } + } + } + + val releasePrefixShape = (0 until retireWidth).map { lane => + io.release.bits.lanes(lane).valid === (lane.U < io.release.bits.count) + }.reduce(_ && _) + val releaseFirst = io.release.bits.lanes(0).rob + val releaseStid = safeStid(releaseFirst.stid) + val releaseLaneExact = Wire(Vec(retireWidth, Bool())) + val releaseGroupFinished = Wire(Vec(retireWidth, Bool())) + for (lane <- 0 until retireWidth) { + val active = lane.U < io.release.bits.count + val id = io.release.bits.lanes(lane).rob + val expectedIdx = orderPlus(orderHead(releaseStid), lane.U) + releaseLaneExact(lane) := !active || ( + io.release.bits.lanes(lane).valid && + id.stid === releaseFirst.stid && + orderValid(releaseStid)(expectedIdx) && + orderCompleted(releaseStid)(expectedIdx) && + orderIds(releaseStid)(expectedIdx).asUInt === id.asUInt && + memberLiveAt(releaseStid, id.ridSlot, id.memberIndex) && + identityAt(releaseStid, id.ridSlot, id.memberIndex).asUInt === id.asUInt) + val youngerLiveSameGroup = (0 until p.ooo.maxInstructionsPerRobGroup).map { member => + member.U > id.memberIndex && + memberLiveAt(releaseStid, id.ridSlot, member.U) + }.reduce(_ || _) + releaseGroupFinished(lane) := active && releaseLaneExact(lane) && + !youngerLiveSameGroup + } + io.releaseReady := io.release.valid && io.release.bits.count =/= 0.U && + io.release.bits.count <= retireWidth.U && + releaseFirst.stid < p.ooo.stidCount.U && + releasePrefixShape && releaseLaneExact.asUInt.andR + val releaseFire = io.releaseReady && io.releaseApply + when(io.release.valid) { + assert(io.release.bits.count <= retireWidth.U) + } + when(releaseFire) { + for (lane <- 0 until retireWidth) { + when(lane.U < io.release.bits.count) { + val id = io.release.bits.lanes(lane).rob + memberLiveAt(releaseStid, id.ridSlot, id.memberIndex) := false.B + stateAt(releaseStid, id.ridSlot, id.memberIndex) := ROBState.Free + for (idx <- 0 until orderCapacity) { + when(orderValid(releaseStid)(idx) && orderIds(releaseStid)(idx).asUInt === id.asUInt) { + orderValid(releaseStid)(idx) := false.B + } + } + residentGenerationAt(releaseStid, id.ridSlot, id.memberIndex) := + residentGenerationAt(releaseStid, id.ridSlot, id.memberIndex) + 1.U + } + } + val releasedGroups = PopCount(releaseGroupFinished) + val (nextHead, wrap) = slotPlus(headSlot(releaseStid), releasedGroups) + headSlot(releaseStid) := nextHead + headGeneration(releaseStid) := headGeneration(releaseStid) + wrap.asUInt + groupCount(releaseStid) := groupCount(releaseStid) - releasedGroups + orderHead(releaseStid) := orderPlus(orderHead(releaseStid), io.release.bits.count) + orderCount(releaseStid) := orderCount(releaseStid) - io.release.bits.count + } + + val recoveryPending = RegInit(false.B) + val recoveryPlan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + for (source <- 0 until 2) { + val lookup = io.recoveryCandidate(source).bits.event + val lookupStid = safeStid(lookup.trigger.stid) + val matches = Wire(Vec(orderCapacity, Bool())) + for (idx <- 0 until orderCapacity) { + matches(idx) := io.recoveryCandidate(source).valid && + lookup.trigger.stid < p.ooo.stidCount.U && + orderValid(lookupStid)(idx) && + orderIds(lookupStid)(idx).asUInt === lookup.trigger.asUInt && + memberLiveAt(lookupStid, lookup.trigger.ridSlot, + lookup.trigger.memberIndex) && + !orderRetired(lookupStid)(idx) + } + val hit = matches.asUInt.orR + val idx = PriorityEncoder(matches.asUInt) + io.recoveryCandidateStatus(source).valid := io.recoveryCandidate(source).valid + io.recoveryCandidateStatus(source).bits := 0.U.asTypeOf( + io.recoveryCandidateStatus(source).bits) + io.recoveryCandidateStatus(source).bits.transactionId := lookup.transactionId + io.recoveryCandidateStatus(source).bits.trigger := lookup.trigger + io.recoveryCandidateStatus(source).bits.eligible := hit + io.recoveryCandidateStatus(source).bits.rejected := + io.recoveryCandidate(source).valid && !hit + io.recoveryCandidateStatus(source).bits.ageToken := orderAge(lookupStid)(idx) + io.recoveryCandidateStatus(source).bits.headTrap := hit && + idx === orderCommitHead(lookupStid) && + orderCompleted(lookupStid)(idx) && + !orderRetired(lookupStid)(idx) && + orderCommits(lookupStid)(idx).trap.valid + } + val recIn = io.recoveryPrepare.bits + val recStid = safeStid(recIn.trigger.stid) + val recMatches = Wire(Vec(orderCapacity, Bool())) + val recOffsets = Wire(Vec(orderCapacity, + UInt(PrefixPacketContract.countWidth(orderCapacity).W))) + for (off <- 0 until orderCapacity) { + val idx = orderPlus(orderHead(recStid), off.U) + recOffsets(off) := off.U + recMatches(off) := off.U < orderCount(recStid) && + orderValid(recStid)(idx) && + orderIds(recStid)(idx).asUInt === recIn.trigger.asUInt + } + val recHit = recIn.trigger.stid < p.ooo.stidCount.U && recMatches.asUInt.orR + private val recoveryCountWidth = + PrefixPacketContract.countWidth(orderCapacity) + val recOffset = Wire(UInt(recoveryCountWidth.W)) + recOffset := PriorityEncoder(recMatches.asUInt) + io.recoveryPrepare.ready := !recoveryPending && recHit && + recIn.phase === RecoveryPhase.Prepare + val preparedPlan = Wire(new RecoveryPlan(p)) + preparedPlan := recIn + val branchSkipsTrigger = recIn.cause === RecoveryCause.Branch + val firstOffset = Mux(branchSkipsTrigger, + recOffset + 1.U(recoveryCountWidth.W), recOffset) + val lastOffset = orderCount(recStid) - 1.U + val firstIdx = orderPlus(orderHead(recStid), firstOffset) + val lastIdx = orderPlus(orderHead(recStid), lastOffset) + preparedPlan.firstKilledValid := recHit && firstOffset < orderCount(recStid) + preparedPlan.firstKilled := orderIds(recStid)(firstIdx) + preparedPlan.lastKilled := orderIds(recStid)(lastIdx) + val killedMembers = orderCount(recStid) - firstOffset + val killedGroupStarts = Wire(Vec(orderCapacity, Bool())) + for (off <- 0 until orderCapacity) { + val active = recHit && off.U >= firstOffset && off.U < orderCount(recStid) + val idx = orderPlus(orderHead(recStid), off.U) + val prevOff = Mux(off.U === 0.U, 0.U, off.U - 1.U) + val prevIdx = orderPlus(orderHead(recStid), prevOff) + val startsSuffix = off.U === firstOffset + val startsNewGroup = + orderIds(recStid)(idx).ridGeneration =/= + orderIds(recStid)(prevIdx).ridGeneration || + orderIds(recStid)(idx).ridSlot =/= + orderIds(recStid)(prevIdx).ridSlot + killedGroupStarts(off) := active && (startsSuffix || startsNewGroup) + } + preparedPlan.killedGroupCount := PopCount(killedGroupStarts) + preparedPlan.killedMemberCount := killedMembers + preparedPlan.survivingTailValid := recHit && firstOffset =/= 0.U + val survivingTailOffset = Mux(firstOffset === 0.U, 0.U, firstOffset - 1.U) + val survivingTailIdx = orderPlus(orderHead(recStid), survivingTailOffset) + preparedPlan.survivingTail := orderIds(recStid)(survivingTailIdx) + + val preparedMemoryRecovery = Wire(new OOORobMemoryRecovery(p)) + preparedMemoryRecovery := 0.U.asTypeOf(preparedMemoryRecovery) + preparedMemoryRecovery.valid := recHit + preparedMemoryRecovery.transactionId := recIn.transactionId + preparedMemoryRecovery.stid := recIn.trigger.stid + preparedMemoryRecovery.oldTail := orderMemoryAfter(recStid)(lastIdx) + preparedMemoryRecovery.newTail := Mux(firstOffset === 0.U, + orderMemoryBefore(recStid)(firstIdx), + orderMemoryAfter(recStid)(survivingTailIdx)) + val recoveryMemoryPlan = Reg(new OOORobMemoryRecovery(p)) + io.memoryRecoveryPrepared := Mux(recoveryPending, + recoveryMemoryPlan, preparedMemoryRecovery) + + io.recoveryPrepared.valid := recoveryPending || io.recoveryPrepare.fire + io.recoveryPrepared.bits := Mux(recoveryPending, recoveryPlan, preparedPlan) + when(io.recoveryPrepare.fire) { + recoveryPending := true.B + recoveryPlan := preparedPlan + recoveryMemoryPlan := preparedMemoryRecovery + } + val recoveryApplyHit = recoveryPending && io.recoveryApply.valid && + io.recoveryApply.bits.phase === RecoveryPhase.Apply && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryApply.bits, recoveryPlan) + val recoveryAbortHit = recoveryPending && io.recoveryAbort.valid && + io.recoveryAbort.bits.phase === RecoveryPhase.Abort && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.recoveryAbort.bits, recoveryPlan) + + when(recoveryApplyHit && !recoveryAbortHit) { + val stid = safeStid(recoveryPlan.trigger.stid) + retainedValid := false.B + for (slot <- 0 until p.ooo.robGroupsPerStid) { + for (member <- 0 until p.ooo.maxInstructionsPerRobGroup) { + val id = identityAt(stid, slot.U, member.U) + when(RecoveryPlanContract.suffixMember(recoveryPlan, id) && + memberLiveAt(stid, slot.U, member.U)) { + memberLiveAt(stid, slot.U, member.U) := false.B + stateAt(stid, slot.U, member.U) := ROBState.Free + residentGenerationAt(stid, slot.U, member.U) := + residentGenerationAt(stid, slot.U, member.U) + 1.U + } + } + } + when(recoveryPlan.firstKilledValid) { + for (off <- 0 until orderCapacity) { + val idx = orderPlus(orderHead(stid), off.U) + when(off.U < orderCount(stid) && orderValid(stid)(idx) && + RecoveryPlanContract.suffixMember(recoveryPlan, orderIds(stid)(idx))) { + orderValid(stid)(idx) := false.B + orderCompleted(stid)(idx) := false.B + orderRetired(stid)(idx) := false.B + } + } + val (afterPartialSlot, afterPartialWrap) = + slotPlus(recoveryPlan.firstKilled.ridSlot, 1.U) + val killsWholeFirstGroup = recoveryPlan.firstKilled.memberIndex === 0.U + val prunedWholeGroups = Mux(killsWholeFirstGroup, + recoveryPlan.killedGroupCount, + Mux(recoveryPlan.killedGroupCount === 0.U, + 0.U, + recoveryPlan.killedGroupCount - 1.U)) + tailSlot(stid) := Mux(killsWholeFirstGroup, + recoveryPlan.firstKilled.ridSlot, + afterPartialSlot) + tailGeneration(stid) := recoveryPlan.firstKilled.ridGeneration + + Mux(killsWholeFirstGroup, 0.U, afterPartialWrap.asUInt) + groupCount(stid) := groupCount(stid) - prunedWholeGroups + orderTail(stid) := orderPlus(orderTail(stid), 0.U - recoveryPlan.killedMemberCount) + orderCount(stid) := orderCount(stid) - recoveryPlan.killedMemberCount + val killedCommitEntries = Wire(Vec(orderCapacity, Bool())) + for (off <- 0 until orderCapacity) { + val idx = orderPlus(orderCommitHead(stid), off.U) + killedCommitEntries(off) := off.U < orderCommitCount(stid) && + orderValid(stid)(idx) && + RecoveryPlanContract.suffixMember(recoveryPlan, orderIds(stid)(idx)) + } + val killedCommitCount = PopCount(killedCommitEntries) + val commitHeadKilled = orderCommitCount(stid) =/= 0.U && + RecoveryPlanContract.suffixMember( + recoveryPlan, orderIds(stid)(orderCommitHead(stid))) + when(commitHeadKilled) { + orderCommitHead(stid) := orderPlus(orderTail(stid), + 0.U - recoveryPlan.killedMemberCount) + } + orderCommitCount(stid) := orderCommitCount(stid) - killedCommitCount + } + recoveryPending := false.B + } + when(recoveryAbortHit) { + recoveryPending := false.B + } + + when(io.prepare.valid) { + assert(io.prepare.bits.count <= d3Width.U) + assert(io.prepare.bits.groupCount <= io.prepare.bits.count) + } + when(io.commitApply) { + assert(io.commit.valid) + } + assert(!(completionAcceptedReg && completionRejectedReg)) +} diff --git a/chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala b/chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala new file mode 100644 index 00000000..a1e711b1 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala @@ -0,0 +1,388 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams +import linxcore.top.interface._ + +object RecoveryControlState extends ChiselEnum { + val Idle, ResolveCandidates, RequestRob, WaitRob, WaitRobAbort, + PrepareTargets, Apply = Value +} + +class RecoveryControlIO(val p: CoreParams, val targetCount: Int) extends Bundle { + val events = Flipped(Vec(2, Decoupled(new RecoveryEvent(p)))) + val interrupts = Input(Vec(p.ooo.stidCount, new InterruptRequest(p))) + val interruptBoundaryValid = Input(Bool()) + val interruptBoundary = Input(new RobIdentity(p)) + val abort = Input(Bool()) + val robCandidate = Output(Vec(2, Valid(new RecoveryCandidateLookup(p)))) + val robCandidateStatus = Input(Vec(2, Valid(new RecoveryCandidateStatus(p)))) + val robPrepare = Decoupled(new RecoveryPlan(p)) + val robPrepared = Flipped(Decoupled(new RecoveryPlan(p))) + val robAbort = Valid(new RecoveryPlan(p)) + val targets = Vec(targetCount, new RecoveryTargetIO(p)) +} + +class RecoveryControl(val p: CoreParams, val targetCount: Int) extends Module { + require(targetCount > 0) + RecoveryAge.requireUnambiguousWindow(p) + val io = IO(new RecoveryControlIO(p, targetCount)) + + private def preciseTrap(event: RecoveryEvent): Bool = + event.cause === RecoveryCause.Exception && event.trap.valid + + val state = RegInit(RecoveryControlState.Idle) + val pendingValid = RegInit(VecInit(Seq.fill(2)(false.B))) + val pending = Reg(Vec(2, new RecoveryEvent(p))) + val resolvingValid = RegInit(VecInit(Seq.fill(2)(false.B))) + val resolving = Reg(Vec(2, new RecoveryEvent(p))) + val resolvedValid = RegInit(VecInit(Seq.fill(2)(false.B))) + val resolvedStatus = Reg(Vec(2, new RecoveryCandidateStatus(p))) + val resolvingInterruptValid = RegInit(false.B) + val resolvingInterrupt = Reg(new RecoveryEvent(p)) + val activeEvent = RegInit(0.U.asTypeOf(new RecoveryEvent(p))) + val robRequest = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val plan = RegInit(0.U.asTypeOf(new RecoveryPlan(p))) + val sentMask = RegInit(0.U(targetCount.W)) + val ackMask = RegInit(0.U(targetCount.W)) + val applyPulse = RegInit(false.B) + val abortPulse = RegInit(false.B) + val robAbortPulse = RegInit(false.B) + + val interruptEvent = Wire(new RecoveryEvent(p)) + interruptEvent := 0.U.asTypeOf(interruptEvent) + val scopedInterrupts = Wire(Vec(p.ooo.stidCount, new InterruptRequest(p))) + for (stid <- 0 until p.ooo.stidCount) { + scopedInterrupts(stid) := io.interrupts(stid) + scopedInterrupts(stid).valid := io.interrupts(stid).valid && + io.interruptBoundaryValid && + io.interrupts(stid).stid === io.interruptBoundary.stid + } + val anyInterrupt = scopedInterrupts.map(_.valid).reduce(_ || _) + val bestInterrupt = scopedInterrupts.reduce { (a, b) => + Mux(a.valid && (!b.valid || a.priority >= b.priority), a, b) + } + interruptEvent.transactionId := bestInterrupt.cause + interruptEvent.cause := RecoveryCause.Interrupt + interruptEvent.trigger := io.interruptBoundary + interruptEvent.trap.valid := anyInterrupt && io.interruptBoundaryValid + interruptEvent.trap.kind := TrapKind.Interrupt + interruptEvent.trap.cause := bestInterrupt.cause + interruptEvent.trap.rob := io.interruptBoundary + + for (idx <- 0 until 2) { + io.events(idx).ready := !pendingValid(idx) && + state === RecoveryControlState.Idle + when(io.events(idx).fire) { + pendingValid(idx) := true.B + pending(idx) := io.events(idx).bits + } + } + + val candidateValid = Wire(Vec(3, Bool())) + val candidate = Wire(Vec(3, new RecoveryEvent(p))) + candidateValid(0) := pendingValid(0) || io.events(0).valid + candidate(0) := Mux(pendingValid(0), pending(0), io.events(0).bits) + candidateValid(1) := pendingValid(1) || io.events(1).valid + candidate(1) := Mux(pendingValid(1), pending(1), io.events(1).bits) + candidateValid(2) := anyInterrupt && io.interruptBoundaryValid + candidate(2) := interruptEvent + + val lookupValid = Wire(Vec(2, Bool())) + val lookupEvent = Wire(Vec(2, new RecoveryEvent(p))) + for (idx <- 0 until 2) { + lookupValid(idx) := Mux(state === RecoveryControlState.ResolveCandidates, + resolvingValid(idx), + candidateValid(idx)) + lookupEvent(idx) := Mux(state === RecoveryControlState.ResolveCandidates, + resolving(idx), + candidate(idx)) + io.robCandidate(idx).valid := lookupValid(idx) + io.robCandidate(idx).bits.event := lookupEvent(idx) + } + + val statusMatchesLookup = Wire(Vec(2, Bool())) + for (idx <- 0 until 2) { + statusMatchesLookup(idx) := io.robCandidateStatus(idx).valid && + io.robCandidateStatus(idx).bits.transactionId === + lookupEvent(idx).transactionId && + io.robCandidateStatus(idx).bits.trigger.asUInt === + lookupEvent(idx).trigger.asUInt + } + val effectiveResolvedValid = Wire(Vec(2, Bool())) + val effectiveStatus = Wire(Vec(2, new RecoveryCandidateStatus(p))) + val resolvedEligible = Wire(Vec(2, Bool())) + for (idx <- 0 until 2) { + val sameCycleStatus = state === RecoveryControlState.ResolveCandidates && + resolvingValid(idx) && statusMatchesLookup(idx) + effectiveResolvedValid(idx) := resolvedValid(idx) || sameCycleStatus + effectiveStatus(idx) := Mux(resolvedValid(idx), + resolvedStatus(idx), + io.robCandidateStatus(idx).bits) + resolvedEligible(idx) := resolvingValid(idx) && + effectiveResolvedValid(idx) && effectiveStatus(idx).eligible + } + val source1Older = RecoveryAge.older( + effectiveStatus(1).ageToken, + effectiveStatus(0).ageToken) + val idleStatusEligible = Wire(Vec(2, Bool())) + for (idx <- 0 until 2) { + idleStatusEligible(idx) := candidateValid(idx) && statusMatchesLookup(idx) && + io.robCandidateStatus(idx).bits.eligible + } + val idleSource1Older = RecoveryAge.older( + io.robCandidateStatus(1).bits.ageToken, + io.robCandidateStatus(0).bits.ageToken) + val idleSelectedEvent = Wire(new RecoveryEvent(p)) + val idleSelectedSource = Wire(UInt(2.W)) + idleSelectedSource := 0.U + idleSelectedEvent := candidate(0) + when(idleStatusEligible(1) && (!idleStatusEligible(0) || idleSource1Older)) { + idleSelectedSource := 1.U + idleSelectedEvent := candidate(1) + } + when(candidateValid(2) && + (!idleStatusEligible(0) || !preciseTrap(candidate(0)) || + !io.robCandidateStatus(0).bits.headTrap) && + (!idleStatusEligible(1) || !preciseTrap(candidate(1)) || + !io.robCandidateStatus(1).bits.headTrap)) { + idleSelectedSource := 2.U + idleSelectedEvent := candidate(2) + } + when(idleStatusEligible(0) && preciseTrap(candidate(0)) && + io.robCandidateStatus(0).bits.headTrap) { + idleSelectedSource := 0.U + idleSelectedEvent := candidate(0) + }.elsewhen(idleStatusEligible(1) && preciseTrap(candidate(1)) && + io.robCandidateStatus(1).bits.headTrap) { + idleSelectedSource := 1.U + idleSelectedEvent := candidate(1) + } + val idleAllResolved = (0 until 2).map { idx => + !candidateValid(idx) || statusMatchesLookup(idx) + }.reduce(_ && _) + val idleSelectedValid = idleStatusEligible.asUInt.orR || candidateValid(2) + val selectedEvent = Wire(new RecoveryEvent(p)) + val selectedSource = Wire(UInt(2.W)) + selectedSource := 0.U + selectedEvent := resolving(0) + when(resolvedEligible(1) && (!resolvedEligible(0) || source1Older)) { + selectedSource := 1.U + selectedEvent := resolving(1) + } + when(resolvingInterruptValid && + (!resolvedEligible(0) || !preciseTrap(resolving(0)) || + !effectiveStatus(0).headTrap) && + (!resolvedEligible(1) || !preciseTrap(resolving(1)) || + !effectiveStatus(1).headTrap)) { + selectedSource := 2.U + selectedEvent := resolvingInterrupt + } + when(resolvedEligible(0) && preciseTrap(resolving(0)) && + effectiveStatus(0).headTrap) { + selectedSource := 0.U + selectedEvent := resolving(0) + }.elsewhen(resolvedEligible(1) && preciseTrap(resolving(1)) && + effectiveStatus(1).headTrap) { + selectedSource := 1.U + selectedEvent := resolving(1) + } + val producerActive = resolvingValid.asUInt.orR + val allResolved = (0 until 2).map { idx => + !resolvingValid(idx) || effectiveResolvedValid(idx) + }.reduce(_ && _) + val selectedValid = resolvedEligible.asUInt.orR || resolvingInterruptValid + + val seedPlan = Wire(new RecoveryPlan(p)) + seedPlan := 0.U.asTypeOf(seedPlan) + seedPlan.transactionId := activeEvent.transactionId + seedPlan.phase := RecoveryPhase.Prepare + seedPlan.cause := activeEvent.cause + seedPlan.trigger := activeEvent.trigger + seedPlan.redirectPc := activeEvent.redirectPc + seedPlan.newEpoch := activeEvent.instruction.epoch + 1.U + + io.robPrepare.valid := state === RecoveryControlState.RequestRob && !io.abort + io.robPrepare.bits := seedPlan + val requestMatchesSeed = + RecoveryPlanContract.sameRobRequest(io.robPrepared.bits, seedPlan) + val requestMatchesRetained = + RecoveryPlanContract.sameRobRequest(io.robPrepared.bits, robRequest) + val robPrepareFire = io.robPrepare.fire + val requestRobPreparedWindow = state === RecoveryControlState.RequestRob + val waitRobPreparedWindow = state === RecoveryControlState.WaitRob || + state === RecoveryControlState.WaitRobAbort + val noRequestRobPreparedDrain = state === RecoveryControlState.Idle || + state === RecoveryControlState.ResolveCandidates || + state === RecoveryControlState.PrepareTargets || + state === RecoveryControlState.Apply + val robPreparedCanFire = requestRobPreparedWindow || + waitRobPreparedWindow || noRequestRobPreparedDrain + val robPreparedFire = io.robPrepared.valid && robPreparedCanFire + val robPreparedAccepted = robPreparedFire && ( + (requestRobPreparedWindow && robPrepareFire && requestMatchesSeed) || + (waitRobPreparedWindow && requestMatchesRetained)) + io.robPrepared.ready := robPreparedCanFire + io.robAbort.valid := robAbortPulse + io.robAbort.bits := plan + io.robAbort.bits.phase := RecoveryPhase.Abort + + when(state === RecoveryControlState.Idle && + (candidateValid(0) || candidateValid(1) || candidateValid(2))) { + when((!(candidateValid(0) || candidateValid(1)) || + (idleAllResolved && idleSelectedValid))) { + activeEvent := Mux(candidateValid(0) || candidateValid(1), + idleSelectedEvent, + candidate(2)) + state := RecoveryControlState.RequestRob + when(idleSelectedSource === 0.U && (candidateValid(0) || candidateValid(1))) { + pendingValid(0) := false.B + }.elsewhen(idleSelectedSource === 1.U && + (candidateValid(0) || candidateValid(1))) { + pendingValid(1) := false.B + } + for (idx <- 0 until 2) { + when(candidateValid(idx) && statusMatchesLookup(idx) && + io.robCandidateStatus(idx).bits.rejected) { + pendingValid(idx) := false.B + } + resolvingValid(idx) := false.B + resolvedValid(idx) := false.B + } + resolvingInterruptValid := false.B + }.otherwise { + for (idx <- 0 until 2) { + resolvingValid(idx) := candidateValid(idx) + resolving(idx) := candidate(idx) + resolvedValid(idx) := candidateValid(idx) && statusMatchesLookup(idx) + resolvedStatus(idx) := io.robCandidateStatus(idx).bits + } + resolvingInterruptValid := candidateValid(2) + resolvingInterrupt := candidate(2) + state := RecoveryControlState.ResolveCandidates + } + } + + when(state === RecoveryControlState.ResolveCandidates) { + for (idx <- 0 until 2) { + when(resolvingValid(idx) && !resolvedValid(idx) && + statusMatchesLookup(idx)) { + resolvedValid(idx) := true.B + resolvedStatus(idx) := io.robCandidateStatus(idx).bits + } + } + when(allResolved) { + when(selectedValid) { + activeEvent := selectedEvent + state := RecoveryControlState.RequestRob + when(selectedSource === 0.U) { + pendingValid(0) := false.B + }.elsewhen(selectedSource === 1.U) { + pendingValid(1) := false.B + } + }.otherwise { + state := RecoveryControlState.Idle + } + for (idx <- 0 until 2) { + when(resolvingValid(idx) && effectiveStatus(idx).rejected) { + pendingValid(idx) := false.B + } + resolvingValid(idx) := false.B + resolvedValid(idx) := false.B + } + resolvingInterruptValid := false.B + } + } + + when(robPrepareFire) { + robRequest := seedPlan + } + + when(state === RecoveryControlState.RequestRob && io.abort) { + state := RecoveryControlState.Idle + }.elsewhen(state === RecoveryControlState.RequestRob && + robPrepareFire && !robPreparedAccepted) { + state := RecoveryControlState.WaitRob + } + + when(state === RecoveryControlState.WaitRob && io.abort && + !robPreparedAccepted) { + state := RecoveryControlState.WaitRobAbort + } + + when(robPreparedAccepted) { + plan := io.robPrepared.bits + plan.phase := RecoveryPhase.Prepare + sentMask := 0.U + ackMask := 0.U + when(state === RecoveryControlState.WaitRobAbort || + (state === RecoveryControlState.WaitRob && io.abort)) { + robAbortPulse := true.B + state := RecoveryControlState.Idle + }.otherwise { + state := RecoveryControlState.PrepareTargets + } + } + + val sentHits = Wire(Vec(targetCount, Bool())) + val ackHits = Wire(Vec(targetCount, Bool())) + for (target <- 0 until targetCount) { + val sent = sentMask(target) + io.targets(target).prepare.valid := + state === RecoveryControlState.PrepareTargets && !sent + io.targets(target).prepare.bits := plan + sentHits(target) := io.targets(target).prepare.fire + io.targets(target).prepared.ready := true.B + ackHits(target) := state === RecoveryControlState.PrepareTargets && + io.targets(target).prepared.fire && + io.targets(target).prepared.bits.phase === RecoveryPhase.Prepare && + (sent || sentHits(target)) && + RecoveryPlanContract.sameTransactionIgnoringPhase( + io.targets(target).prepared.bits, plan) + io.targets(target).apply.valid := applyPulse + io.targets(target).apply.bits := plan + io.targets(target).apply.bits.phase := RecoveryPhase.Apply + io.targets(target).abort.valid := abortPulse + io.targets(target).abort.bits := plan + io.targets(target).abort.bits.phase := RecoveryPhase.Abort + } + + val nextSent = sentMask | sentHits.asUInt + val nextAck = ackMask | ackHits.asUInt + when(state === RecoveryControlState.PrepareTargets) { + sentMask := nextSent + ackMask := nextAck + } + when(state === RecoveryControlState.PrepareTargets && io.abort) { + abortPulse := true.B + robAbortPulse := true.B + state := RecoveryControlState.Idle + }.elsewhen(state === RecoveryControlState.PrepareTargets && + nextSent.andR && nextAck.andR) { + applyPulse := true.B + state := RecoveryControlState.Apply + }.elsewhen(state === RecoveryControlState.Apply) { + applyPulse := false.B + state := RecoveryControlState.Idle + }.otherwise { + applyPulse := false.B + } + + when(state === RecoveryControlState.ResolveCandidates && io.abort) { + for (idx <- 0 until 2) { + resolvingValid(idx) := false.B + resolvedValid(idx) := false.B + } + resolvingInterruptValid := false.B + state := RecoveryControlState.Idle + } + + when(abortPulse) { + abortPulse := false.B + } + when(robAbortPulse) { + robAbortPulse := false.B + } + assert(!(applyPulse && abortPulse)) +} diff --git a/chisel/src/main/scala/linxcore/ooo/TURename.scala b/chisel/src/main/scala/linxcore/ooo/TURename.scala new file mode 100644 index 00000000..8a6bc5c6 --- /dev/null +++ b/chisel/src/main/scala/linxcore/ooo/TURename.scala @@ -0,0 +1,655 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.util.{Cat, PopCount, Valid, log2Ceil} +import linxcore.params.CoreParams +import linxcore.top.interface._ + +private[ooo] object TURename { + def tTagWidth(p: CoreParams): Int = p.ooo.tTagWidth + def uTagWidth(p: CoreParams): Int = p.ooo.uTagWidth +} + +private[ooo] class TURenameIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Valid(new D2AdmissionGroup(p))) + val prepareReady = Output(Bool()) + val prepared = Output(new D3RenameGroup(p)) + val publish = Flipped(Valid(new D3RenameGroup(p))) + val release = Flipped(Valid(new RenameCommitReleaseTxn(p))) + val releaseExact = Output(Bool()) + val releaseApply = Input(Bool()) + val recoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val debugTCount = Output(Vec(p.ooo.stidCount, + UInt((log2Ceil(p.ooo.tuMapQDepthPerStid + 1)).W))) + val debugUCount = Output(Vec(p.ooo.stidCount, + UInt((log2Ceil(p.ooo.tuMapQDepthPerStid + 1)).W))) +} + +/** Independent relative T/U rename owner. + * + * T and U keep separate ordered MapQ rows, physical cursors, committed-head + * cursors, and counts. Relative lookup walks the full retained sequence: + * same-prefix rows override older MapQ rows, while stale release and recovery + * both require exact ordered row identity. + */ +private[ooo] class TURename(val p: CoreParams) extends Module { + val io = IO(new TURenameIO(p)) + + private val width = p.widths.decodeWidth + private val tTagWidth = TURename.tTagWidth(p) + private val uTagWidth = TURename.uTagWidth(p) + private val stidWidth = p.ooo.stidWidth + private val tuIndexWidth = math.max(1, log2Ceil(p.ooo.tuMapQDepthPerStid)) + private val tuCountWidth = math.max(1, log2Ceil(p.ooo.tuMapQDepthPerStid + 1)) + private val destSlots = width * p.maxDestinationOperands + + private def trunc(value: UInt, width: Int): UInt = + if (value.getWidth == width) value + else if (value.getWidth > width) value(width - 1, 0) + else Cat(0.U((width - value.getWidth).W), value) + + private def safeStid(value: UInt): UInt = + if (p.ooo.stidCount == 1) 0.U(stidWidth.W) else trunc(value, stidWidth) + + private def addWrap( + ptr: UInt, + gen: UInt, + amount: UInt, + entries: Int, + ptrWidth: Int): (UInt, UInt) = { + val physicalWidth = math.max(1, log2Ceil(entries)) + val sum = trunc(ptr, physicalWidth) +& amount + val crossesEnd = sum >= entries.U + val wrapped = Mux(crossesEnd, sum - entries.U, sum) + (trunc(wrapped, ptrWidth), gen + crossesEnd.asUInt) + } + + private def sameRob(a: RobIdentity, b: RobIdentity): Bool = + a.asUInt === b.asUInt + + private def robBeforeOrAt(a: RobIdentity, b: RobIdentity): Bool = { + val slotWidth = p.ooo.ridSlotWidth + val orderWidth = p.ridGenerationWidth + slotWidth + val aOrder = Cat(a.ridGeneration, a.ridSlot) + val bOrder = Cat(b.ridGeneration, b.ridSlot) + val delta = bOrder -% aOrder + val sameGroup = a.ridGeneration === b.ridGeneration && + a.ridSlot === b.ridSlot + a.peId === b.peId && a.stid === b.stid && + (sameGroup && a.memberIndex <= b.memberIndex || + (!sameGroup && delta < (BigInt(1) << (orderWidth - 1)).U)) + } + + val tMapQ = Reg(Vec(p.ooo.stidCount, Vec(p.ooo.tuMapQDepthPerStid, + new RenameCommitReleaseEntry(p)))) + val uMapQ = Reg(Vec(p.ooo.stidCount, Vec(p.ooo.tuMapQDepthPerStid, + new RenameCommitReleaseEntry(p)))) + + val tHeadQ = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(tuIndexWidth.W)))) + val uHeadQ = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(tuIndexWidth.W)))) + val tTailQ = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(tuIndexWidth.W)))) + val uTailQ = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(tuIndexWidth.W)))) + val tHeadGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val uHeadGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + + val tTail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(tTagWidth.W)))) + val uTail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)(0.U(uTagWidth.W)))) + val tTailQGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val uTailQGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val tTagGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val uTagGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val tCommittedTail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(tTagWidth.W)))) + val uCommittedTail = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(uTagWidth.W)))) + val tCommittedGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val uCommittedGeneration = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(p.ooo.localSeqGenerationWidth.W)))) + val tCount = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(tuCountWidth.W)))) + val uCount = RegInit(VecInit(Seq.fill(p.ooo.stidCount)( + 0.U(tuCountWidth.W)))) + + io.debugTCount := tCount + io.debugUCount := uCount + + val in = io.prepare.bits + val stidRaw = in.entries(0).uop.instruction.parent.identity.stid + val stid = safeStid(stidRaw) + val stidInRange = stidRaw < p.ooo.stidCount.U + val prospectivePublish = io.publish.bits + val prospectivePublishStidRaw = + prospectivePublish.entries(0).uop.decoded.instruction.parent.identity.stid + val prospectivePublishStid = safeStid(prospectivePublishStidRaw) + val prospectivePublishSameStid = io.publish.valid && + prospectivePublishStidRaw < p.ooo.stidCount.U && + prospectivePublishStid === stid + val prospectivePublishedT = Wire(Vec(destSlots, Bool())) + val prospectivePublishedU = Wire(Vec(destSlots, Bool())) + for (lane <- 0 until width; dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val hist = prospectivePublish.entries(lane).history(dest) + prospectivePublishedT(flat) := prospectivePublishSameStid && + lane.U < prospectivePublish.count && hist.valid && + hist.kind === OperandKind.T + prospectivePublishedU(flat) := prospectivePublishSameStid && + lane.U < prospectivePublish.count && hist.valid && + hist.kind === OperandKind.U + } + val prospectivePublishedTCount = PopCount(prospectivePublishedT) + val prospectivePublishedUCount = PopCount(prospectivePublishedU) + val prospectiveTSeq = addWrap(tTailQ(stid), tTailQGeneration(stid), + prospectivePublishedTCount, p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val prospectiveUSeq = addWrap(uTailQ(stid), uTailQGeneration(stid), + prospectivePublishedUCount, p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val prospectiveTTag = addWrap(tTail(stid), tTagGeneration(stid), + prospectivePublishedTCount, p.ooo.tPhysRegs, tTagWidth) + val prospectiveUTag = addWrap(uTail(stid), uTagGeneration(stid), + prospectivePublishedUCount, p.ooo.uPhysRegs, uTagWidth) + val prospectiveTCount = tCount(stid) +& prospectivePublishedTCount + val prospectiveUCount = uCount(stid) +& prospectivePublishedUCount + val active = Wire(Vec(width, Bool())) + for (lane <- 0 until width) { + active(lane) := lane.U < in.count && in.entries(lane).uop.valid + } + + val tDestActive = Wire(Vec(destSlots, Bool())) + val uDestActive = Wire(Vec(destSlots, Bool())) + for (lane <- 0 until width; dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val d = in.entries(lane).uop.destinations(dest) + tDestActive(flat) := active(lane) && d.valid && d.kind === OperandKind.T + uDestActive(flat) := active(lane) && d.valid && d.kind === OperandKind.U + } + + val underflow = Wire(Vec(width * p.maxSourceOperands, Bool())) + for (lane <- 0 until width; source <- 0 until p.maxSourceOperands) { + val flat = lane * p.maxSourceOperands + source + val src = in.entries(lane).uop.sources(source) + val olderT = PopCount(tDestActive.take(lane * p.maxDestinationOperands)) + val olderU = PopCount(uDestActive.take(lane * p.maxDestinationOperands)) + val offset = src.relativeIndex +& 1.U + underflow(flat) := active(lane) && src.valid && ( + (src.kind === OperandKind.T && offset > (prospectiveTCount +& olderT)) || + (src.kind === OperandKind.U && offset > (prospectiveUCount +& olderU))) + } + val tDemand = PopCount(tDestActive) + val uDemand = PopCount(uDestActive) + io.prepareReady := stidInRange && !underflow.asUInt.orR && + prospectiveTCount +& tDemand <= p.ooo.tuMapQDepthPerStid.U && + prospectiveUCount +& uDemand <= p.ooo.tuMapQDepthPerStid.U && + prospectiveTCount +& tDemand <= p.ooo.tPhysRegs.U && + prospectiveUCount +& uDemand <= p.ooo.uPhysRegs.U + + io.prepared := 0.U.asTypeOf(io.prepared) + io.prepared.count := in.count + io.prepared.groupCount := in.groupCount + for (group <- 0 until width) { + io.prepared.groups(group) := in.groups(group) + } + for (lane <- 0 until width) { + io.prepared.entries(lane).trap := in.entries(lane).trap + io.prepared.entries(lane).residentBound := in.entries(lane).residentBound + io.prepared.entries(lane).brobBound := in.entries(lane).brobBound + io.prepared.entries(lane).blockStart := in.entries(lane).uop.blockStart + io.prepared.entries(lane).blockStop := in.entries(lane).uop.blockStop + io.prepared.entries(lane).earlyRobComplete := + in.entries(lane).uop.earlyComplete + io.prepared.entries(lane).uop.decoded := in.entries(lane).uop + val olderLaneT = PopCount(tDestActive.take(lane * p.maxDestinationOperands)) + val olderLaneU = PopCount(uDestActive.take(lane * p.maxDestinationOperands)) + val laneTSeq = addWrap(prospectiveTSeq._1, prospectiveTSeq._2, olderLaneT, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val laneUSeq = addWrap(prospectiveUSeq._1, prospectiveUSeq._2, olderLaneU, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + io.prepared.entries(lane).tSeqBefore.valid := active(lane) + io.prepared.entries(lane).tSeqBefore.tag := laneTSeq._1 + io.prepared.entries(lane).tSeqBefore.generation := laneTSeq._2 + io.prepared.entries(lane).uSeqBefore.valid := active(lane) + io.prepared.entries(lane).uSeqBefore.tag := laneUSeq._1 + io.prepared.entries(lane).uSeqBefore.generation := laneUSeq._2 + for (source <- 0 until p.maxSourceOperands) { + val src = in.entries(lane).uop.sources(source) + val out = io.prepared.entries(lane).uop.sources(source) + out.valid := src.valid + out.kind := src.kind + out.atag := src.atag + out.ready := true.B + when(src.valid && src.kind === OperandKind.T) { + val olderT = PopCount(tDestActive.take(lane * p.maxDestinationOperands)) + val offset = src.relativeIndex +& 1.U + val retainedNeed = offset - olderT + val retainedIndex = trunc(prospectiveTSeq._1 - retainedNeed, tuIndexWidth) + out.ttag := tMapQ(stid)(retainedIndex).history(0).ttag + out.tGeneration := tMapQ(stid)(retainedIndex).history(0).tGeneration + out.tSeqIndex := tMapQ(stid)(retainedIndex).history(0).tMapQIndex + out.tSeqGeneration := + tMapQ(stid)(retainedIndex).history(0).tMapQGeneration + out.localEpoch := tMapQ(stid)(retainedIndex).epoch + for (flat <- 0 until destSlots) { + val ordinal = PopCount(prospectivePublishedT.take(flat)) + val history = prospectivePublish.entries( + flat / p.maxDestinationOperands).history( + flat % p.maxDestinationOperands) + when(prospectivePublishedT(flat) && + retainedNeed <= prospectivePublishedTCount && + ordinal === prospectivePublishedTCount - retainedNeed) { + out.ttag := history.ttag + out.tGeneration := history.tGeneration + out.tSeqIndex := history.tMapQIndex + out.tSeqGeneration := history.tMapQGeneration + out.localEpoch := prospectivePublish.entries( + flat / p.maxDestinationOperands).uop.decoded.instruction + .parent.identity.epoch + } + } + out.ttagValid := true.B + out.ready := offset > olderT + for (flat <- 0 until lane * p.maxDestinationOperands) { + val ordinal = PopCount(tDestActive.take(flat)) + val wanted = olderT - offset + when(tDestActive(flat) && offset <= olderT && ordinal === wanted) { + val physical = addWrap(prospectiveTTag._1, prospectiveTTag._2, ordinal, + p.ooo.tPhysRegs, tTagWidth) + val seq = addWrap(prospectiveTSeq._1, prospectiveTSeq._2, ordinal, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + out.ttag := physical._1 + out.tGeneration := physical._2 + out.tSeqIndex := seq._1 + out.tSeqGeneration := seq._2 + out.localEpoch := in.entries( + flat / p.maxDestinationOperands).uop.instruction.parent + .identity.epoch + } + } + }.elsewhen(src.valid && src.kind === OperandKind.U) { + val olderU = PopCount(uDestActive.take(lane * p.maxDestinationOperands)) + val offset = src.relativeIndex +& 1.U + val retainedNeed = offset - olderU + val retainedIndex = trunc(prospectiveUSeq._1 - retainedNeed, tuIndexWidth) + out.utag := uMapQ(stid)(retainedIndex).history(0).utag + out.uGeneration := uMapQ(stid)(retainedIndex).history(0).uGeneration + out.uSeqIndex := uMapQ(stid)(retainedIndex).history(0).uMapQIndex + out.uSeqGeneration := + uMapQ(stid)(retainedIndex).history(0).uMapQGeneration + out.localEpoch := uMapQ(stid)(retainedIndex).epoch + for (flat <- 0 until destSlots) { + val ordinal = PopCount(prospectivePublishedU.take(flat)) + val history = prospectivePublish.entries( + flat / p.maxDestinationOperands).history( + flat % p.maxDestinationOperands) + when(prospectivePublishedU(flat) && + retainedNeed <= prospectivePublishedUCount && + ordinal === prospectivePublishedUCount - retainedNeed) { + out.utag := history.utag + out.uGeneration := history.uGeneration + out.uSeqIndex := history.uMapQIndex + out.uSeqGeneration := history.uMapQGeneration + out.localEpoch := prospectivePublish.entries( + flat / p.maxDestinationOperands).uop.decoded.instruction + .parent.identity.epoch + } + } + out.utagValid := true.B + out.ready := offset > olderU + for (flat <- 0 until lane * p.maxDestinationOperands) { + val ordinal = PopCount(uDestActive.take(flat)) + val wanted = olderU - offset + when(uDestActive(flat) && offset <= olderU && ordinal === wanted) { + val physical = addWrap(prospectiveUTag._1, prospectiveUTag._2, ordinal, + p.ooo.uPhysRegs, uTagWidth) + val seq = addWrap(prospectiveUSeq._1, prospectiveUSeq._2, ordinal, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + out.utag := physical._1 + out.uGeneration := physical._2 + out.uSeqIndex := seq._1 + out.uSeqGeneration := seq._2 + out.localEpoch := in.entries( + flat / p.maxDestinationOperands).uop.instruction.parent + .identity.epoch + } + } + } + } + for (dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val din = in.entries(lane).uop.destinations(dest) + val dout = io.prepared.entries(lane).uop.destinations(dest) + val hist = io.prepared.entries(lane).history(dest) + dout.valid := din.valid + dout.kind := din.kind + dout.atag := din.atag + hist.valid := tDestActive(flat) || uDestActive(flat) + hist.kind := din.kind + hist.atag := din.atag + when(tDestActive(flat)) { + val ordinal = PopCount(tDestActive.take(flat)) + val physical = addWrap(prospectiveTTag._1, prospectiveTTag._2, ordinal, + p.ooo.tPhysRegs, tTagWidth) + val seq = addWrap(prospectiveTSeq._1, prospectiveTSeq._2, ordinal, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + dout.ttag := physical._1 + dout.tGeneration := physical._2 + dout.tSeqIndex := seq._1 + dout.tSeqGeneration := seq._2 + dout.ttagValid := true.B + hist.ttag := dout.ttag + hist.tGeneration := dout.tGeneration + hist.tMapQIndex := seq._1 + hist.tMapQGeneration := seq._2 + }.elsewhen(uDestActive(flat)) { + val ordinal = PopCount(uDestActive.take(flat)) + val physical = addWrap(prospectiveUTag._1, prospectiveUTag._2, ordinal, + p.ooo.uPhysRegs, uTagWidth) + val seq = addWrap(prospectiveUSeq._1, prospectiveUSeq._2, ordinal, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + dout.utag := physical._1 + dout.uGeneration := physical._2 + dout.uSeqIndex := seq._1 + dout.uSeqGeneration := seq._2 + dout.utagValid := true.B + hist.utag := dout.utag + hist.uGeneration := dout.uGeneration + hist.uMapQIndex := seq._1 + hist.uMapQGeneration := seq._2 + } + } + } + + when(io.prepare.valid && io.prepareReady && prospectivePublishSameStid) { + for (oldLane <- 0 until width; oldDest <- 0 until p.maxDestinationOperands) { + val oldHist = prospectivePublish.entries(oldLane).history(oldDest) + val oldLive = oldLane.U < prospectivePublish.count && oldHist.valid + for (newLane <- 0 until width; newDest <- 0 until p.maxDestinationOperands) { + val newHist = io.prepared.entries(newLane).history(newDest) + val newLive = newLane.U < io.prepared.count && newHist.valid + when(oldLive && newLive && oldHist.kind === OperandKind.T && + newHist.kind === OperandKind.T) { + assert(oldHist.ttag =/= newHist.ttag, + "replacement T reservations must not reuse a live physical tag") + } + when(oldLive && newLive && oldHist.kind === OperandKind.U && + newHist.kind === OperandKind.U) { + assert(oldHist.utag =/= newHist.utag, + "replacement U reservations must not reuse a live physical tag") + } + } + } + } + + when(io.publish.valid) { + val pub = io.publish.bits + val st = safeStid(pub.entries(0).uop.decoded.instruction.parent.identity.stid) + val publishedT = Wire(Vec(destSlots, Bool())) + val publishedU = Wire(Vec(destSlots, Bool())) + for (flat <- 0 until destSlots) { + publishedT(flat) := false.B + publishedU(flat) := false.B + } + for (lane <- 0 until width) { + when(lane.U < pub.count && pub.entries(lane).uop.decoded.valid) { + for (dest <- 0 until p.maxDestinationOperands) { + val flat = lane * p.maxDestinationOperands + dest + val hist = pub.entries(lane).history(dest) + when(hist.valid && hist.kind === OperandKind.T) { + val idx = trunc(tTailQ(st) + PopCount(publishedT.take(flat)), + tuIndexWidth) + val row = Wire(new RenameCommitReleaseEntry(p)) + row := 0.U.asTypeOf(row) + row.valid := true.B + row.rob := pub.entries(lane).uop.decoded.rob + row.epoch := pub.entries(lane).uop.decoded.instruction.parent + .identity.epoch + row.blockLast := pub.entries(lane).uop.decoded.blockBoundary + row.history(0) := hist + tMapQ(st)(idx) := row + publishedT(flat) := true.B + }.elsewhen(hist.valid && hist.kind === OperandKind.U) { + val idx = trunc(uTailQ(st) + PopCount(publishedU.take(flat)), + tuIndexWidth) + val row = Wire(new RenameCommitReleaseEntry(p)) + row := 0.U.asTypeOf(row) + row.valid := true.B + row.rob := pub.entries(lane).uop.decoded.rob + row.epoch := pub.entries(lane).uop.decoded.instruction.parent + .identity.epoch + row.blockLast := pub.entries(lane).uop.decoded.blockBoundary + row.history(0) := hist + uMapQ(st)(idx) := row + publishedU(flat) := true.B + } + } + } + } + val tN = PopCount(publishedT) + val uN = PopCount(publishedU) + val nextTSeq = addWrap(tTailQ(st), tTailQGeneration(st), tN, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val nextUSeq = addWrap(uTailQ(st), uTailQGeneration(st), uN, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val nextTTag = addWrap(tTail(st), tTagGeneration(st), tN, + p.ooo.tPhysRegs, tTagWidth) + val nextUTag = addWrap(uTail(st), uTagGeneration(st), uN, + p.ooo.uPhysRegs, uTagWidth) + tTailQ(st) := nextTSeq._1 + tTailQGeneration(st) := nextTSeq._2 + uTailQ(st) := nextUSeq._1 + uTailQGeneration(st) := nextUSeq._2 + tTail(st) := nextTTag._1 + tTagGeneration(st) := nextTTag._2 + uTail(st) := nextUTag._1 + uTagGeneration(st) := nextUTag._2 + tCount(st) := tCount(st) + tN + uCount(st) := uCount(st) + uN + } + + val releaseSlotCount = p.widths.retireWidth * p.maxDestinationOperands + val releaseTAccept = Wire(Vec(releaseSlotCount, Bool())) + val releaseUAccept = Wire(Vec(releaseSlotCount, Bool())) + val releaseTAttempt = Wire(Vec(releaseSlotCount, Bool())) + val releaseUAttempt = Wire(Vec(releaseSlotCount, Bool())) + releaseTAccept := VecInit(Seq.fill(releaseSlotCount)(false.B)) + releaseUAccept := VecInit(Seq.fill(releaseSlotCount)(false.B)) + releaseTAttempt := VecInit(Seq.fill(releaseSlotCount)(false.B)) + releaseUAttempt := VecInit(Seq.fill(releaseSlotCount)(false.B)) + val releaseTAllExact = Wire(Vec(p.ooo.stidCount, Bool())) + val releaseUAllExact = Wire(Vec(p.ooo.stidCount, Bool())) + for (st <- 0 until p.ooo.stidCount) { + val attemptedT = (0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseTAttempt(flat) && io.release.bits.lanes(lane).rob.stid === st.U + } + val attemptedU = (0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseUAttempt(flat) && io.release.bits.lanes(lane).rob.stid === st.U + } + val exactT = (0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseTAccept(flat) && io.release.bits.lanes(lane).rob.stid === st.U + } + val exactU = (0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseUAccept(flat) && io.release.bits.lanes(lane).rob.stid === st.U + } + releaseTAllExact(st) := !VecInit(attemptedT).asUInt.orR || + PopCount(attemptedT) === PopCount(exactT) + releaseUAllExact(st) := !VecInit(attemptedU).asUInt.orR || + PopCount(attemptedU) === PopCount(exactU) + } + val releaseAllExact = releaseTAllExact.asUInt.andR && + releaseUAllExact.asUInt.andR + io.releaseExact := !io.release.valid || releaseAllExact + when(io.release.valid) { + for (flat <- 0 until releaseSlotCount) { + val lane = flat / p.maxDestinationOperands + val dest = flat % p.maxDestinationOperands + val rel = io.release.bits.lanes(lane) + val hist = rel.history(dest) + val st = safeStid(rel.rob.stid) + val priorT = PopCount((0 until flat).map { prior => + val priorLane = prior / p.maxDestinationOperands + val priorRel = io.release.bits.lanes(priorLane) + releaseTAccept(prior) && priorRel.rob.stid === rel.rob.stid + }) + val priorU = PopCount((0 until flat).map { prior => + val priorLane = prior / p.maxDestinationOperands + val priorRel = io.release.bits.lanes(priorLane) + releaseUAccept(prior) && priorRel.rob.stid === rel.rob.stid + }) + val tIdx = trunc(tHeadQ(st) + priorT, tuIndexWidth) + val uIdx = trunc(uHeadQ(st) + priorU, tuIndexWidth) + val tRow = tMapQ(st)(tIdx) + val uRow = uMapQ(st)(uIdx) + val laneLive = rel.valid && lane.U < io.release.bits.count + val tExact = laneLive && hist.valid && hist.kind === OperandKind.T && + rel.rob.stid < p.ooo.stidCount.U && priorT < tCount(st) && + tRow.valid && sameRob(rel.rob, tRow.rob) && + hist.asUInt === tRow.history(0).asUInt + val uExact = laneLive && hist.valid && hist.kind === OperandKind.U && + rel.rob.stid < p.ooo.stidCount.U && priorU < uCount(st) && + uRow.valid && sameRob(rel.rob, uRow.rob) && + hist.asUInt === uRow.history(0).asUInt + releaseTAttempt(flat) := laneLive && hist.valid && + hist.kind === OperandKind.T + releaseUAttempt(flat) := laneLive && hist.valid && + hist.kind === OperandKind.U + releaseTAccept(flat) := tExact + releaseUAccept(flat) := uExact + when(tExact && releaseTAllExact(st) && releaseAllExact && + io.releaseApply) { + val nextCommitted = addWrap(tRow.history(0).ttag, + tRow.history(0).tGeneration, 1.U, p.ooo.tPhysRegs, tTagWidth) + tCommittedTail(st) := nextCommitted._1 + tCommittedGeneration(st) := nextCommitted._2 + tRow.valid := false.B + } + when(uExact && releaseUAllExact(st) && releaseAllExact && + io.releaseApply) { + val nextCommitted = addWrap(uRow.history(0).utag, + uRow.history(0).uGeneration, 1.U, p.ooo.uPhysRegs, uTagWidth) + uCommittedTail(st) := nextCommitted._1 + uCommittedGeneration(st) := nextCommitted._2 + uRow.valid := false.B + } + } + for (st <- 0 until p.ooo.stidCount) { + val acceptedT = PopCount((0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseTAccept(flat) && io.release.bits.lanes(lane).rob.stid === st.U + }) + val acceptedU = PopCount((0 until releaseSlotCount).map { flat => + val lane = flat / p.maxDestinationOperands + releaseUAccept(flat) && io.release.bits.lanes(lane).rob.stid === st.U + }) + val nextTHead = addWrap(tHeadQ(st), tHeadGeneration(st), acceptedT, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val nextUHead = addWrap(uHeadQ(st), uHeadGeneration(st), acceptedU, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + when(acceptedT.orR && releaseTAllExact(st) && releaseAllExact && + io.releaseApply) { + tHeadQ(st) := nextTHead._1 + tHeadGeneration(st) := nextTHead._2 + tCount(st) := tCount(st) - acceptedT + } + when(acceptedU.orR && releaseUAllExact(st) && releaseAllExact && + io.releaseApply) { + uHeadQ(st) := nextUHead._1 + uHeadGeneration(st) := nextUHead._2 + uCount(st) := uCount(st) - acceptedU + } + } + } + + when(io.recoveryApply.valid && io.recoveryApply.bits.phase === RecoveryPhase.Apply) { + val st = safeStid(io.recoveryApply.bits.trigger.stid) + val tBeforeSurvivor = Wire(Vec(p.ooo.tuMapQDepthPerStid, Bool())) + val uBeforeSurvivor = Wire(Vec(p.ooo.tuMapQDepthPerStid, Bool())) + for (offset <- 0 until p.ooo.tuMapQDepthPerStid) { + val tIdx = trunc(tHeadQ(st) + offset.U, tuIndexWidth) + val uIdx = trunc(uHeadQ(st) + offset.U, tuIndexWidth) + tBeforeSurvivor(offset) := offset.U < tCount(st) && + io.recoveryApply.bits.survivingTailValid && + tMapQ(st)(tIdx).valid && + robBeforeOrAt(tMapQ(st)(tIdx).rob, + io.recoveryApply.bits.survivingTail) + uBeforeSurvivor(offset) := offset.U < uCount(st) && + io.recoveryApply.bits.survivingTailValid && + uMapQ(st)(uIdx).valid && + robBeforeOrAt(uMapQ(st)(uIdx).rob, + io.recoveryApply.bits.survivingTail) + } + val tSurvivors = Mux(io.recoveryApply.bits.survivingTailValid, + trunc(PopCount(tBeforeSurvivor), tuCountWidth), 0.U) + val uSurvivors = Mux(io.recoveryApply.bits.survivingTailValid, + trunc(PopCount(uBeforeSurvivor), tuCountWidth), 0.U) + for (offset <- 1 until p.ooo.tuMapQDepthPerStid) { + when(tBeforeSurvivor(offset)) { + assert(tBeforeSurvivor(offset - 1), + "T recovery survivors must form an ordered prefix") + } + when(uBeforeSurvivor(offset)) { + assert(uBeforeSurvivor(offset - 1), + "U recovery survivors must form an ordered prefix") + } + } + + for (offset <- 0 until p.ooo.tuMapQDepthPerStid) { + val tIdx = trunc(tHeadQ(st) + offset.U, tuIndexWidth) + val uIdx = trunc(uHeadQ(st) + offset.U, tuIndexWidth) + when(offset.U < tCount(st) && offset.U >= tSurvivors) { + tMapQ(st)(tIdx).valid := false.B + } + when(offset.U < uCount(st) && offset.U >= uSurvivors) { + uMapQ(st)(uIdx).valid := false.B + } + } + + val nextTTag = Wire(UInt(tTagWidth.W)) + val nextUTag = Wire(UInt(uTagWidth.W)) + val nextTTagGeneration = Wire(UInt(p.ooo.localSeqGenerationWidth.W)) + val nextUTagGeneration = Wire(UInt(p.ooo.localSeqGenerationWidth.W)) + nextTTag := tCommittedTail(st) + nextUTag := uCommittedTail(st) + nextTTagGeneration := tCommittedGeneration(st) + nextUTagGeneration := uCommittedGeneration(st) + for (offset <- 0 until p.ooo.tuMapQDepthPerStid) { + val tIdx = trunc(tHeadQ(st) + offset.U, tuIndexWidth) + val uIdx = trunc(uHeadQ(st) + offset.U, tuIndexWidth) + when(tSurvivors.orR && offset.U === tSurvivors - 1.U) { + val next = addWrap(tMapQ(st)(tIdx).history(0).ttag, + tMapQ(st)(tIdx).history(0).tGeneration, 1.U, + p.ooo.tPhysRegs, tTagWidth) + nextTTag := next._1 + nextTTagGeneration := next._2 + } + when(uSurvivors.orR && offset.U === uSurvivors - 1.U) { + val next = addWrap(uMapQ(st)(uIdx).history(0).utag, + uMapQ(st)(uIdx).history(0).uGeneration, 1.U, + p.ooo.uPhysRegs, uTagWidth) + nextUTag := next._1 + nextUTagGeneration := next._2 + } + } + val nextTSeq = addWrap(tHeadQ(st), tHeadGeneration(st), tSurvivors, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + val nextUSeq = addWrap(uHeadQ(st), uHeadGeneration(st), uSurvivors, + p.ooo.tuMapQDepthPerStid, tuIndexWidth) + tTailQ(st) := nextTSeq._1 + uTailQ(st) := nextUSeq._1 + tTail(st) := nextTTag + tTagGeneration(st) := nextTTagGeneration + tTailQGeneration(st) := nextTSeq._2 + uTail(st) := nextUTag + uTagGeneration(st) := nextUTagGeneration + uTailQGeneration(st) := nextUSeq._2 + tCount(st) := tSurvivors + uCount(st) := uSurvivors + } +} diff --git a/chisel/src/main/scala/linxcore/params/CTUParams.scala b/chisel/src/main/scala/linxcore/params/CTUParams.scala new file mode 100644 index 00000000..20c02771 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/CTUParams.scala @@ -0,0 +1,8 @@ +package linxcore.params + +final case class CTUParams( + inputWidth: Int = 4, + outputWidth: Int = 4, + instructionBits: Int = 64, + instructionBufferEntries: Int = 32, + maxTemplateUops: Int = 32) diff --git a/chisel/src/main/scala/linxcore/params/CoreParams.scala b/chisel/src/main/scala/linxcore/params/CoreParams.scala new file mode 100644 index 00000000..9bf6795b --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/CoreParams.scala @@ -0,0 +1,38 @@ +package linxcore.params + +import chisel3.util.log2Ceil + +final case class CoreParams( + widths: WidthParams = WidthParams(), + ifu: IFUParams = IFUParams(), + ctu: CTUParams = CTUParams(), + ooo: OOOParams = OOOParams(), + iex: IEXParams = IEXParams(), + lsu: LSUParams = LSUParams(), + dtu: DTUParams = DTUParams(), + pcWidth: Int = 64, + instructionWidth: Int = 64, + opcodeWidth: Int = 12, + archRegWidth: Int = 6, + lsidWidth: Int = 32, + maxMemoryRequestsPerInstruction: Int = 2, + peIdWidth: Int = 8, + instructionIdWidth: Int = 64, + transactionIdWidth: Int = 64, + epochWidth: Int = 16, + brobGenerationWidth: Int = 16, + ridGenerationWidth: Int = 16, + residentGenerationWidth: Int = 16, + memoryTransactionIdWidth: Int = 64, + memoryTransactionGenerationWidth: Int = 16, + memoryAttemptGenerationWidth: Int = 16, + trapCauseWidth: Int = 32, + physicalAddressWidth: Int = 64, + dataWidth: Int = 64, + maxSourceOperands: Int = 4, + maxDestinationOperands: Int = 2) { + ParamChecks.validate(this) + + /** Native BID is the per-STID BROB slot; generation remains a separate field. */ + def nativeBidWidth: Int = ooo.nativeBidWidth +} diff --git a/chisel/src/main/scala/linxcore/params/DTUParams.scala b/chisel/src/main/scala/linxcore/params/DTUParams.scala new file mode 100644 index 00000000..76b0bd10 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/DTUParams.scala @@ -0,0 +1,6 @@ +package linxcore.params + +final case class DTUParams( + traceWidth: Int = 4, + performanceCounterCount: Int = 32, + traceBufferEntries: Int = 256) diff --git a/chisel/src/main/scala/linxcore/params/IEXParams.scala b/chisel/src/main/scala/linxcore/params/IEXParams.scala new file mode 100644 index 00000000..07c3fec8 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/IEXParams.scala @@ -0,0 +1,16 @@ +package linxcore.params + +final case class IEXParams( + issueWidth: Int = 4, + aluPipes: Int = 2, + bruPipes: Int = 1, + aguPipes: Int = 2, + stdPipes: Int = 2, + systemMulticycleQueues: Int = 1, + cmdIssueQueues: Int = 1, + issueQueueClasses: Int = 8, + executionPipeKinds: Int = 10, + scalarIssueEntries: Int = 64, + scalarIssueBanks: Int = 2, + integerReadPorts: Int = 6, + integerWritePorts: Int = 5) diff --git a/chisel/src/main/scala/linxcore/params/IFUParams.scala b/chisel/src/main/scala/linxcore/params/IFUParams.scala new file mode 100644 index 00000000..5b5f0c44 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/IFUParams.scala @@ -0,0 +1,18 @@ +package linxcore.params + +final case class IFUParams( + fetchWidth: Int = 4, + ctuTransferWidth: Int = 4, + instructionBits: Int = 64, + fetchBufferEntries: Int = 32, + predictionCheckpointEntries: Int = 32, + iSideStages: Int = 5, + bSideStages: Int = 5, + lineBytes: Int = 64, + pageBytes: Int = 4096, + itlbEntries: Int = 16, + l1iSets: Int = 64, + missEntries: Int = 8, + joinEntries: Int = 8, + maxGroupsPerTransaction: Int = 8, + resetVector: BigInt = 0) diff --git a/chisel/src/main/scala/linxcore/params/LSUParams.scala b/chisel/src/main/scala/linxcore/params/LSUParams.scala new file mode 100644 index 00000000..a2705085 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/LSUParams.scala @@ -0,0 +1,45 @@ +package linxcore.params + +final case class MemoryAccessAttributes( + readable: Boolean = true, + writable: Boolean = true, + cacheable: Boolean = true, + device: Boolean = false) + +/** Canonical physical protection and memory-attribute region. Earlier + * entries have priority, and the same classifier is applied after both + * identity and translated mappings. + */ +final case class PhysicalMemoryRegion( + base: BigInt, + mask: BigInt, + attributes: MemoryAccessAttributes) + +final case class LSUParams( + loadPipes: Int = 2, + storePipes: Int = 2, + loadQueueEntries: Int = 16, + storeQueueEntries: Int = 16, + loadReturnQueueEntries: Int = 2, + storeCommitQueueEntries: Int = 16, + scbEntries: Int = 16, + loadMissQueueEntries: Int = 8, + loadRefillQueueEntries: Int = 4, + resolveQueueEntries: Int = 8, + mdbSsitEntries: Int = 16, + mdbCommandQueueEntries: Int = 16, + mdbOutputQueueEntries: Int = 16, + mdbWaitPlanQueueEntries: Int = 8, + mdbRecoveryQueueEntries: Int = 8, + mdbFailedWaitTimeoutCycles: Int = 300, + l1dSets: Int = 64, + l1dWays: Int = 4, + scbResponseBufferDepth: Int = 4, + dTranslationEntries: Int = 4, + dTranslationPageBytes: Int = 4096, + dTranslationCounterBits: Int = 7, + lowerMemoryTransactionsPerLane: Int = 16, + defaultMemoryAttributes: MemoryAccessAttributes = + MemoryAccessAttributes(), + physicalMemoryRegions: Seq[PhysicalMemoryRegion] = Seq.empty, + lineBytes: Int = 64) diff --git a/chisel/src/main/scala/linxcore/params/NaturalPlatformParams.scala b/chisel/src/main/scala/linxcore/params/NaturalPlatformParams.scala new file mode 100644 index 00000000..2bd35a7e --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/NaturalPlatformParams.scala @@ -0,0 +1,25 @@ +package linxcore.params + +/** Memory attributes owned by the natural simulation platform, not the core. */ +object NaturalPlatformParams { + private val pageMask = BigInt("fffffffffffff000", 16) + private val normalMemoryAttributes = MemoryAccessAttributes( + readable = true, writable = true, cacheable = false, device = false) + private val deviceAttributes = MemoryAccessAttributes( + readable = true, writable = true, cacheable = false, device = true) + + val physicalMemoryRegions: Seq[PhysicalMemoryRegion] = Seq( + PhysicalMemoryRegion( + base = BigInt("10000000", 16), + mask = pageMask, + attributes = deviceAttributes), + PhysicalMemoryRegion( + base = BigInt("10009000", 16), + mask = pageMask, + attributes = deviceAttributes)) + + def apply(base: CoreParams): CoreParams = + base.copy(lsu = base.lsu.copy( + defaultMemoryAttributes = normalMemoryAttributes, + physicalMemoryRegions = physicalMemoryRegions)) +} diff --git a/chisel/src/main/scala/linxcore/params/OOOParams.scala b/chisel/src/main/scala/linxcore/params/OOOParams.scala new file mode 100644 index 00000000..d88678b5 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/OOOParams.scala @@ -0,0 +1,57 @@ +package linxcore.params + +import chisel3.util.log2Ceil + +final case class OOOParams( + stidCount: Int = 1, + stidIdentityEntries: Int = 2, + decodeWidth: Int = 4, + renameWidth: Int = 4, + dispatchWidth: Int = 4, + d3PrefixWidth: Int = 4, + retireWidth: Int = 4, + storeCommitBufferEntries: Int = 64, + robGroupsPerStid: Int = 64, + robIdentityGroupsPerStid: Int = 64, + maxInstructionsPerRobGroup: Int = 4, + robIdentityMembersPerGroup: Int = 4, + maxUopsPerInstruction: Int = 32, + uopIdentityEntriesPerInstruction: Int = 32, + robBankCount: Int = 8, + brobEntriesPerStid: Int = 256, + brobIdentityEntriesPerStid: Int = 256, + pcBufferEntries: Int = 64, + pcBankCount: Int = 4, + pcRecoveryScanGroupsPerCycle: Int = 4, + pcOffsetWidth: Int = 7, + pcWritePorts: Int = 3, + pcReadPorts: Int = 6, + pcReadReplicaCount: Int = 3, + pcAllocationEpochWidth: Int = 16, + gprArchRegs: Int = 24, + gprPhysRegs: Int = 128, + gprTagIdentityEntries: Int = 128, + gprTagGenerationWidth: Int = 16, + gprMapQDepthPerStid: Int = 256, + tPhysRegs: Int = 32, + tTagIdentityEntries: Int = 32, + uPhysRegs: Int = 32, + uTagIdentityEntries: Int = 32, + localSeqGenerationWidth: Int = 16, + tuMapQDepthPerStid: Int = 32) { + def robCapacityPerStid: Int = + robGroupsPerStid * maxInstructionsPerRobGroup + def stidWidth: Int = math.max(1, log2Ceil(stidIdentityEntries)) + def ridSlotWidth: Int = math.max(1, log2Ceil(robIdentityGroupsPerStid)) + def robMemberIndexWidth: Int = math.max(1, + log2Ceil(robIdentityMembersPerGroup)) + def recipeUopIndexWidth: Int = math.max(1, + log2Ceil(uopIdentityEntriesPerInstruction)) + def recipeUopCountWidth: Int = math.max(1, + log2Ceil(uopIdentityEntriesPerInstruction + 1)) + def nativeBidWidth: Int = math.max(1, + log2Ceil(brobIdentityEntriesPerStid)) + def gprTagWidth: Int = math.max(1, log2Ceil(gprTagIdentityEntries)) + def tTagWidth: Int = math.max(1, log2Ceil(tTagIdentityEntries)) + def uTagWidth: Int = math.max(1, log2Ceil(uTagIdentityEntries)) +} diff --git a/chisel/src/main/scala/linxcore/params/ParamChecks.scala b/chisel/src/main/scala/linxcore/params/ParamChecks.scala new file mode 100644 index 00000000..69be7053 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/ParamChecks.scala @@ -0,0 +1,338 @@ +package linxcore.params + +object ParamChecks { + private val supportedPrincipalWidths = Set(2, 4, 6, 8) + + private def isPowerOfTwo(value: Int): Boolean = + value > 0 && (value & (value - 1)) == 0 + + private def requirePrincipalWidth(name: String, value: Int): Unit = + require( + supportedPrincipalWidths.contains(value), + s"$name must be one of 2, 4, 6, or 8") + + def validate(p: CoreParams): Unit = { + requirePrincipalWidth("fetchWidth", p.widths.fetchWidth) + requirePrincipalWidth("ctuOutputWidth", p.widths.ctuOutputWidth) + requirePrincipalWidth("decodeWidth", p.widths.decodeWidth) + requirePrincipalWidth("renameWidth", p.widths.renameWidth) + requirePrincipalWidth("dispatchWidth", p.widths.dispatchWidth) + requirePrincipalWidth("issueWidth", p.widths.issueWidth) + require(p.widths.retireWidth > 0, "retire width must be positive") + + require( + p.widths.fetchWidth >= p.widths.ctuOutputWidth, + "IFU fetch width must cover CTU output") + require( + p.widths.ctuOutputWidth <= p.widths.decodeWidth, + "OOO decode width must cover CTU output") + require( + p.widths.renameWidth >= p.widths.decodeWidth, + "rename width must cover the decode prefix") + require( + p.widths.dispatchWidth >= p.ooo.d3PrefixWidth, + "dispatch width must cover the D3 prefix") + + require( + p.ifu.fetchWidth == p.widths.fetchWidth, + "IFU fetch width must match WidthParams") + require( + p.ifu.ctuTransferWidth == p.widths.ctuOutputWidth, + "IFU CTU-transfer width must match WidthParams") + require( + p.ctu.inputWidth == p.ifu.ctuTransferWidth, + "CTU input width must match the IFU transfer width") + require( + p.ctu.outputWidth == p.widths.ctuOutputWidth, + "CTU output width must match WidthParams") + require( + p.ooo.decodeWidth == p.widths.decodeWidth, + "OOO decode width must match WidthParams") + require( + p.ooo.renameWidth == p.widths.renameWidth, + "OOO rename width must match WidthParams") + require( + p.ooo.dispatchWidth == p.widths.dispatchWidth, + "OOO dispatch width must match WidthParams") + require( + p.ooo.retireWidth == p.widths.retireWidth, + "OOO retire width must match WidthParams") + require( + p.ooo.d3PrefixWidth <= p.ooo.renameWidth, + "D3 prefix width must fit the rename width") + require( + p.iex.issueWidth == p.widths.issueWidth, + "IEX issue width must match WidthParams") + require(p.iex.issueQueueClasses > 0, + "IEX must configure at least one Issue Queue class") + require(p.iex.executionPipeKinds > 0, + "IEX must configure at least one Execution pipe kind") + + require(p.ifu.instructionBits == 64, "IFU instruction container must be 64 bits") + require(p.ctu.instructionBits == 64, "CTU instruction container must be 64 bits") + require(p.instructionWidth == 64, "core instruction container must be 64 bits") + require(p.pcWidth == 64, "LinxCore PC width must be 64 bits") + require(p.opcodeWidth == 12, "canonical opcode identity must preserve 12 bits") + require(p.archRegWidth >= 6, "architectural register width must cover reg6") + require(p.lsidWidth >= 32, "LSID width must preserve at least 32 bits") + require( + p.maxMemoryRequestsPerInstruction >= 2, + "memory request count must cover scalar pair operations") + require(p.peIdWidth > 0, "PE identity width must be positive") + require(p.instructionIdWidth > 0, "instruction identity width must be positive") + require(p.transactionIdWidth > 0, "transaction identity width must be positive") + require(p.epochWidth > 0, "instruction epoch width must be positive") + require(p.brobGenerationWidth > 0, "BROB generation width must be positive") + require(p.ridGenerationWidth > 0, "ROB generation width must be positive") + require( + p.residentGenerationWidth > 0, + "resident generation width must be positive") + require( + p.memoryTransactionIdWidth > 0 && + p.memoryTransactionGenerationWidth > 0 && + p.memoryAttemptGenerationWidth > 0, + "memory identities must carry transaction, generation, and attempt domains") + require(p.trapCauseWidth > 0, "trap cause width must be positive") + require( + p.physicalAddressWidth == 64 && p.dataWidth == 64, + "mainline scalar memory boundary is 64-bit") + require( + p.lsu.dTranslationEntries > 1 && + isPowerOfTwo(p.lsu.dTranslationEntries), + "D-side translation entries must be a power of two greater than one") + require( + p.lsu.dTranslationPageBytes > p.lsu.lineBytes && + isPowerOfTwo(p.lsu.dTranslationPageBytes), + "D-side translation page size must be a power of two above line size") + require( + p.lsu.dTranslationCounterBits > 0 && + p.lsu.dTranslationCounterBits < p.memoryTransactionIdWidth && + p.lsu.dTranslationCounterBits < p.memoryTransactionGenerationWidth, + "D-side translation counter bits must fit below each public owner bit") + require( + p.lsu.lowerMemoryTransactionsPerLane >= p.lsu.loadMissQueueEntries, + "lower-memory ledger per lane must cover the load miss queue") + require( + p.lsu.lowerMemoryTransactionsPerLane >= p.lsu.storeCommitQueueEntries, + "lower-memory ledger per lane must cover the store commit queue") + require( + p.lsu.lowerMemoryTransactionsPerLane >= p.lsu.scbEntries, + "lower-memory ledger per lane must cover the SCB") + require(p.lsu.scbResponseBufferDepth > 0, + "SCB response buffer depth must be positive") + require(p.maxSourceOperands > 0, "source operand count must be positive") + require(p.maxDestinationOperands > 0, "destination operand count must be positive") + require(isPowerOfTwo(p.ooo.storeCommitBufferEntries) && + p.ooo.storeCommitBufferEntries >= + p.ooo.retireWidth * p.maxMemoryRequestsPerInstruction, + "OOO store-commit buffer must hold one worst-case commit batch") + + require( + p.ifu.fetchBufferEntries >= p.ifu.fetchWidth, + "IFU fetch buffer must hold one full fetch packet") + require( + p.ifu.predictionCheckpointEntries > 0, + "IFU prediction checkpoint count must be positive") + require( + p.ifu.iSideStages == 5 && p.ifu.bSideStages == 5, + "IFU I-SIDE and B-SIDE each have five architectural stages") + require( + isPowerOfTwo(p.ifu.lineBytes) && p.ifu.lineBytes >= p.dataWidth / 8, + "IFU cache line size must be a power of two covering one memory beat") + require( + isPowerOfTwo(p.ifu.pageBytes) && p.ifu.pageBytes > p.ifu.lineBytes, + "IFU page size must be a power of two larger than one cache line") + require( + isPowerOfTwo(p.ifu.itlbEntries), + "IFU ITLB entry count must be a positive power of two") + require( + isPowerOfTwo(p.ifu.l1iSets), + "IFU L1I set count must be a positive power of two") + require( + isPowerOfTwo(p.ifu.missEntries) && + isPowerOfTwo(p.ifu.joinEntries) && + p.ifu.missEntries >= p.ifu.joinEntries, + "IFU miss capacity must cover the power-of-two prediction join capacity") + require( + isPowerOfTwo(p.ifu.maxGroupsPerTransaction), + "IFU transaction group capacity must be a positive power of two") + require( + p.ifu.resetVector >= 0 && p.ifu.resetVector < (BigInt(1) << p.pcWidth), + "IFU reset vector must fit the PC width") + require( + p.ctu.instructionBufferEntries >= p.ctu.outputWidth, + "CTU instruction buffer must hold one output packet") + require(p.ctu.maxTemplateUops > 0, "CTU template expansion limit must be positive") + + require( + isPowerOfTwo(p.ooo.stidCount), + "OOO STID count must be a positive power of two") + require( + isPowerOfTwo(p.ooo.stidIdentityEntries) && + p.ooo.stidIdentityEntries >= p.ooo.stidCount, + "STID identity entries must be a power of two covering physical STIDs") + require( + isPowerOfTwo(p.ooo.robGroupsPerStid), + "ROB groups per STID must be a positive power of two") + require( + isPowerOfTwo(p.ooo.robIdentityGroupsPerStid) && + p.ooo.robIdentityGroupsPerStid >= p.ooo.robGroupsPerStid, + "ROB identity groups must be a power of two covering physical ROB groups") + require( + p.ooo.maxInstructionsPerRobGroup > 0, + "ROB group instruction capacity must be positive") + require( + isPowerOfTwo(p.ooo.robIdentityMembersPerGroup) && + p.ooo.robIdentityMembersPerGroup >= + p.ooo.maxInstructionsPerRobGroup, + "ROB identity members must be a power of two covering physical group instruction capacity") + require( + p.ooo.maxUopsPerInstruction > 0, + "decoded instruction uop capacity must be positive") + require( + isPowerOfTwo(p.ooo.uopIdentityEntriesPerInstruction) && + p.ooo.uopIdentityEntriesPerInstruction >= + p.ooo.maxUopsPerInstruction && + p.ooo.uopIdentityEntriesPerInstruction >= + p.ooo.robIdentityMembersPerGroup, + "uop identity entries must be a power of two covering physical uops and ROB identity members") + require( + p.ooo.robCapacityPerStid >= p.ooo.d3PrefixWidth, + "ROB capacity must hold one D3 prefix") + require( + isPowerOfTwo(p.ooo.robBankCount) && + p.ooo.robBankCount <= p.ooo.robGroupsPerStid, + "ROB bank count must be a power of two within the group count") + require( + p.ooo.dispatchWidth <= p.ooo.robBankCount, + "ROB banks must cover one dispatch prefix") + require( + isPowerOfTwo(p.ooo.brobEntriesPerStid) && + p.ooo.brobEntriesPerStid >= 2, + "BROB entries per STID must be a power of two and at least 2") + require( + isPowerOfTwo(p.ooo.brobIdentityEntriesPerStid) && + p.ooo.brobIdentityEntriesPerStid >= p.ooo.brobEntriesPerStid, + "BROB identity entries must be a power of two covering physical entries") + require( + isPowerOfTwo(p.ooo.pcBufferEntries) && + p.ooo.pcBufferEntries % p.ooo.stidCount == 0, + "PC buffer entries must be a power of two evenly partitioned by STID") + val pcEntriesPerStid = p.ooo.pcBufferEntries / p.ooo.stidCount + require( + isPowerOfTwo(p.ooo.pcBankCount) && + p.ooo.pcBankCount >= p.ooo.retireWidth && + p.ooo.pcBankCount <= pcEntriesPerStid && + pcEntriesPerStid % p.ooo.pcBankCount == 0, + "PC buffer banks must cover retire width and divide each STID partition") + require( + p.ooo.pcWritePorts == 3 && p.ooo.pcWritePorts <= p.ooo.pcBankCount, + "PC buffer exposes exactly three D3 PC-base write ports") + require( + p.ooo.pcReadPorts == 6 && p.ooo.pcReadReplicaCount == 3 && + p.ooo.pcReadPorts % p.ooo.pcReadReplicaCount == 0, + "PC buffer exposes six reads through three exact PC-base replicas") + require( + p.ooo.pcRecoveryScanGroupsPerCycle > 0 && + p.ooo.pcOffsetWidth > 0 && + p.ooo.pcAllocationEpochWidth > 0, + "PC buffer recovery, PC offset, and allocation epoch widths must be positive") + require(p.ooo.gprArchRegs == 24, "Linx scalar GPR namespace contains 24 registers") + require( + isPowerOfTwo(p.ooo.gprPhysRegs) && + p.ooo.gprPhysRegs > p.ooo.stidCount * p.ooo.gprArchRegs, + "physical GPR capacity must cover committed and speculative mappings") + require( + isPowerOfTwo(p.ooo.gprTagIdentityEntries) && + p.ooo.gprTagIdentityEntries >= p.ooo.gprPhysRegs, + "GPR tag identity entries must cover the physical GPR capacity") + val renameDestinationDemand = + p.ooo.renameWidth * p.maxDestinationOperands + require( + p.ooo.gprPhysRegs - p.ooo.stidCount * p.ooo.gprArchRegs >= + renameDestinationDemand, + "speculative GPR capacity must cover one maximum rename prefix") + require( + p.ooo.gprTagGenerationWidth > 0, + "GPR physical tag generation width must be positive") + require( + isPowerOfTwo(p.ooo.gprMapQDepthPerStid) && + p.ooo.gprMapQDepthPerStid >= + p.ooo.renameWidth * p.maxDestinationOperands, + "GPR MapQ depth must be a power of two covering one rename prefix") + require( + isPowerOfTwo(p.ooo.tPhysRegs) && isPowerOfTwo(p.ooo.uPhysRegs), + "T and U physical namespaces must be powers of two") + require( + isPowerOfTwo(p.ooo.tTagIdentityEntries) && + isPowerOfTwo(p.ooo.uTagIdentityEntries) && + p.ooo.tTagIdentityEntries >= p.ooo.tPhysRegs && + p.ooo.uTagIdentityEntries >= p.ooo.uPhysRegs, + "T and U tag identity entries must cover their physical namespaces") + require( + p.ooo.tPhysRegs >= renameDestinationDemand && + p.ooo.uPhysRegs >= renameDestinationDemand, + "T and U physical namespaces must independently cover one maximum rename prefix") + require( + p.ooo.localSeqGenerationWidth > 0, + "T/U local sequence generation width must be positive") + require( + isPowerOfTwo(p.ooo.tuMapQDepthPerStid) && + p.ooo.tuMapQDepthPerStid >= renameDestinationDemand, + "T/U MapQ depth must be a power of two covering one maximum rename prefix") + + require(p.iex.aluPipes > 0, "ALU pipe count must be positive") + require(p.iex.bruPipes > 0, "BRU pipe count must be positive") + require(p.iex.aguPipes > 0, "AGU pipe count must be positive") + require(p.iex.stdPipes > 0, "STD pipe count must be positive") + require( + p.iex.systemMulticycleQueues > 0, + "system/multicycle queue count must be positive") + require(p.iex.cmdIssueQueues > 0, "CMD issue queue count must be positive") + require( + isPowerOfTwo(p.iex.scalarIssueEntries), + "scalar issue capacity must be a positive power of two") + require( + isPowerOfTwo(p.iex.scalarIssueBanks) && + p.iex.scalarIssueBanks <= p.iex.scalarIssueEntries, + "scalar issue banks must be a power of two within issue capacity") + require(p.iex.integerReadPorts > 0, "integer read-port count must be positive") + require(p.iex.integerWritePorts > 0, "integer write-port count must be positive") + + require(p.lsu.loadPipes > 0, "load pipe count must be positive") + require(p.lsu.storePipes > 0, "store pipe count must be positive") + require( + p.iex.stdPipes == p.lsu.storePipes, + "STD pipe count must match the LSU store pipe count") + require( + p.lsu.loadQueueEntries >= p.lsu.loadPipes, + "load queue must cover all load pipes") + require( + p.lsu.storeQueueEntries >= + p.iex.stdPipes * p.maxMemoryRequestsPerInstruction, + "store queue must cover one atomic STD reservation batch") + require( + p.lsu.loadReturnQueueEntries >= p.lsu.loadPipes, + "load-return queue must cover all load pipes") + require( + p.lsu.storeCommitQueueEntries >= p.lsu.storePipes, + "store-commit queue must cover all store pipes") + require( + p.lsu.scbEntries >= p.lsu.storePipes * 2, + "SCB must cover one worst-case split-store batch") + require( + isPowerOfTwo(p.lsu.lineBytes), + "cache line size must be a positive power of two") + + require(p.dtu.traceWidth > 0, "DTU trace width must be positive") + require( + p.dtu.traceWidth >= p.widths.fetchWidth, + "DTU trace width must cover the IFU transfer") + require( + p.dtu.performanceCounterCount > 0, + "DTU performance-counter count must be positive") + require( + isPowerOfTwo(p.dtu.traceBufferEntries), + "DTU trace buffer must be a positive power of two") + } +} diff --git a/chisel/src/main/scala/linxcore/params/ParamProfiles.scala b/chisel/src/main/scala/linxcore/params/ParamProfiles.scala new file mode 100644 index 00000000..938dae98 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/ParamProfiles.scala @@ -0,0 +1,36 @@ +package linxcore.params + +object ParamProfiles { + private def uniform(width: Int): CoreParams = { + val widths = WidthParams.uniform(width) + CoreParams( + widths = widths, + ifu = IFUParams(fetchWidth = width, ctuTransferWidth = width), + ctu = CTUParams(inputWidth = width, outputWidth = width), + ooo = OOOParams( + decodeWidth = width, + renameWidth = width, + dispatchWidth = width, + d3PrefixWidth = width, + retireWidth = width, + pcBankCount = if (width <= 4) 4 else 8), + iex = IEXParams(issueWidth = width), + dtu = DTUParams(traceWidth = width)) + } + + val W2: CoreParams = uniform(2) + val W4: CoreParams = uniform(4) + val W6: CoreParams = uniform(6) + val W8: CoreParams = uniform(8) + val Default: CoreParams = W4 + + def forWidth(width: Int): CoreParams = width match { + case 2 => W2 + case 4 => W4 + case 6 => W6 + case 8 => W8 + case _ => + throw new IllegalArgumentException( + s"unsupported width $width; supported widths are 2, 4, 6, and 8") + } +} diff --git a/chisel/src/main/scala/linxcore/params/SimulationParamProfiles.scala b/chisel/src/main/scala/linxcore/params/SimulationParamProfiles.scala new file mode 100644 index 00000000..122ddc43 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/SimulationParamProfiles.scala @@ -0,0 +1,104 @@ +package linxcore.params + +/** Capacity-bounded profiles for directed simulation only. + * + * Principal pipeline widths and fixed identity domains are inherited from + * the corresponding main profile. Only local storage capacities are bounded. + */ +object SimulationParamProfiles { + private def nextPowerOfTwo(value: Int): Int = + if (value <= 1) 1 + else 1 << (32 - Integer.numberOfLeadingZeros(value - 1)) + + private def bounded(width: Int): CoreParams = { + val main = ParamProfiles.forWidth(width) + val prefixCapacity = nextPowerOfTwo(width) + // Keep one physical row per IQ bank at W2. The two-bank topology is + // retained for the canonical picker fanout, but a second row per bank is + // not required by any identity or width contract and doubles the largest + // generated issue graph during bounded natural runs. + val issueCapacity = prefixCapacity + // Rename must admit the block-closing suffix even while an older open + // block retains its speculative mappings. A width-only MapQ (four rows at + // W2) can fill before that suffix reaches D3 and deadlock against BROB + // closure. Sixteen rows is the bounded forward-progress floor; it remains + // one quarter of the main profile. + val destinationCapacity = math.max(16, nextPowerOfTwo( + width * main.maxDestinationOperands)) + val pcCapacity = math.max(4, prefixCapacity) + // An open block can retain one complete 32-uop template window before its + // closing boundary becomes visible. Sixteen four-member groups preserve + // that forward-progress margin while remaining below the 64-group main + // profile. BROB capacity counts blocks rather than ROB groups and remains + // independently bounded. + val robGroupCapacity = math.max(16, prefixCapacity) + val brobCapacity = math.max(8, prefixCapacity) + val gprPhysicalCapacity = nextPowerOfTwo( + main.ooo.stidCount * main.ooo.gprArchRegs + destinationCapacity) + + main.copy( + ifu = main.ifu.copy( + fetchBufferEntries = math.max(4, prefixCapacity), + predictionCheckpointEntries = prefixCapacity, + itlbEntries = 4, + l1iSets = 4, + missEntries = 4, + joinEntries = 4), + ctu = main.ctu.copy( + instructionBufferEntries = prefixCapacity), + ooo = main.ooo.copy( + storeCommitBufferEntries = nextPowerOfTwo( + main.ooo.retireWidth * main.maxMemoryRequestsPerInstruction), + robGroupsPerStid = robGroupCapacity, + maxInstructionsPerRobGroup = main.ooo.maxInstructionsPerRobGroup, + maxUopsPerInstruction = 12, + robBankCount = prefixCapacity, + brobEntriesPerStid = brobCapacity, + pcBufferEntries = pcCapacity, + pcBankCount = pcCapacity, + pcRecoveryScanGroupsPerCycle = math.min(4, robGroupCapacity), + gprPhysRegs = gprPhysicalCapacity, + gprMapQDepthPerStid = destinationCapacity, + tPhysRegs = destinationCapacity, + uPhysRegs = destinationCapacity, + tuMapQDepthPerStid = destinationCapacity), + iex = main.iex.copy(scalarIssueEntries = issueCapacity), + lsu = main.lsu.copy( + loadQueueEntries = 2, + storeQueueEntries = nextPowerOfTwo( + main.iex.stdPipes * main.maxMemoryRequestsPerInstruction), + loadReturnQueueEntries = 2, + storeCommitQueueEntries = 2, + scbEntries = 4, + loadMissQueueEntries = 2, + loadRefillQueueEntries = 2, + resolveQueueEntries = 4, + mdbSsitEntries = 4, + mdbCommandQueueEntries = 4, + mdbOutputQueueEntries = 4, + mdbWaitPlanQueueEntries = 4, + mdbRecoveryQueueEntries = 4, + l1dSets = 2, + l1dWays = 2, + scbResponseBufferDepth = 2, + dTranslationEntries = 2, + dTranslationCounterBits = 2, + lowerMemoryTransactionsPerLane = 4), + dtu = main.dtu.copy(traceBufferEntries = 4)) + } + + val W2: CoreParams = bounded(2) + val W4: CoreParams = bounded(4) + val W6: CoreParams = bounded(6) + val W8: CoreParams = bounded(8) + + def forWidth(width: Int): CoreParams = width match { + case 2 => W2 + case 4 => W4 + case 6 => W6 + case 8 => W8 + case _ => + throw new IllegalArgumentException( + s"unsupported simulation width $width; supported widths are 2, 4, 6, and 8") + } +} diff --git a/chisel/src/main/scala/linxcore/params/WidthParams.scala b/chisel/src/main/scala/linxcore/params/WidthParams.scala new file mode 100644 index 00000000..9db117a9 --- /dev/null +++ b/chisel/src/main/scala/linxcore/params/WidthParams.scala @@ -0,0 +1,22 @@ +package linxcore.params + +final case class WidthParams( + fetchWidth: Int = 4, + ctuOutputWidth: Int = 4, + decodeWidth: Int = 4, + renameWidth: Int = 4, + dispatchWidth: Int = 4, + issueWidth: Int = 4, + retireWidth: Int = 4) + +object WidthParams { + def uniform(width: Int): WidthParams = + WidthParams( + fetchWidth = width, + ctuOutputWidth = width, + decodeWidth = width, + renameWidth = width, + dispatchWidth = width, + issueWidth = width, + retireWidth = width) +} diff --git a/chisel/src/main/scala/linxcore/recovery/ScalarRedirectRecoverySourceProbe.scala b/chisel/src/main/scala/linxcore/recovery/ScalarRedirectRecoverySourceProbe.scala deleted file mode 100644 index c405b49f..00000000 --- a/chisel/src/main/scala/linxcore/recovery/ScalarRedirectRecoverySourceProbe.scala +++ /dev/null @@ -1,96 +0,0 @@ -package linxcore.recovery - -import chisel3._ - -import linxcore.rob.ROBID - -class ScalarRedirectRecoverySourceProbeIO extends Bundle { - val eventValid = Input(Bool()) - val blockBidValid = Input(Bool()) - val blockBid = Input(UInt(16.W)) - val bid = Input(new ROBID(8)) - val rid = Input(new ROBID(8)) - val lsId = Input(new ROBID(8)) - val lsIdFull = Input(UInt(40.W)) - val resolveLsIdValid = Input(Bool()) - val orderValid = Input(Bool()) - val order = Input(UInt(12.W)) - val sourceReady = Input(Bool()) - val sourceResolved = Input(Bool()) - val payloadIntentConsumed = Input(Bool()) - val cancel = Input(Bool()) - - val eventReady = Output(Bool()) - val eventAccepted = Output(Bool()) - val sourceValid = Output(Bool()) - val sourceAccepted = Output(Bool()) - val sourceBlockBid = Output(UInt(16.W)) - val sourceRid = Output(new ROBID(8)) - val sourceLsIdFullValid = Output(Bool()) - val sourceLsIdFull = Output(UInt(40.W)) - val pending = Output(Bool()) - val published = Output(Bool()) - val blockedByMissingIdentity = Output(Bool()) - val cleanupOrderValid = Output(Bool()) - val cleanupOrder = Output(UInt(12.W)) - val cleanupResolveLsIdValid = Output(Bool()) - val cleanupLsId = Output(new ROBID(8)) - val cleanupLsIdFull = Output(UInt(40.W)) -} - -/** Generated-RTL proof surface for retained scalar redirect recovery. */ -class ScalarRedirectRecoverySourceProbe extends Module { - val io = IO(new ScalarRedirectRecoverySourceProbeIO) - val source = Module(new ScalarRedirectRecoverySource( - entries = 8, - bidWidth = 16, - peIdWidth = 1, - stidWidth = 1, - tidWidth = 1, - orderWidth = 12, - lsidWidth = 40 - )) - - source.io.event.valid := io.eventValid - source.io.event.blockBidValid := io.blockBidValid - source.io.event.blockBid := io.blockBid - source.io.event.bid := io.bid - source.io.event.rid := io.rid - source.io.event.lsId := io.lsId - source.io.event.lsIdFull := io.lsIdFull - source.io.event.resolveLsIdValid := io.resolveLsIdValid - source.io.event.stid := 0.U - source.io.event.peId := 0.U - source.io.event.tid := 0.U - source.io.event.orderValid := io.orderValid - source.io.event.order := io.order - source.io.sourceReady := io.sourceReady - source.io.sourceResolved := io.sourceResolved - source.io.payloadIntentConsumed := io.payloadIntentConsumed - source.io.cancel := io.cancel - - io.eventReady := source.io.eventReady - io.eventAccepted := source.io.eventAccepted - io.sourceValid := source.io.source.valid - io.sourceAccepted := source.io.sourceAccepted - io.sourceBlockBid := source.io.source.blockBid - io.sourceRid := source.io.source.rid - io.sourceLsIdFullValid := source.io.source.lsIdFullValid - io.sourceLsIdFull := source.io.source.lsIdFull - io.pending := source.io.pending - io.published := source.io.published - io.blockedByMissingIdentity := source.io.blockedByMissingIdentity - io.cleanupOrderValid := source.io.cleanupOrderValid - io.cleanupOrder := source.io.cleanupOrder - io.cleanupResolveLsIdValid := source.io.cleanupResolveLsIdValid - io.cleanupLsId := source.io.cleanupLsId - io.cleanupLsIdFull := source.io.cleanupLsIdFull -} - -object EmitScalarRedirectRecoverySourceProbe extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new ScalarRedirectRecoverySourceProbe, - args = Array("--target-dir", "../generated/chisel-verilog/scalar-redirect-recovery-source-probe"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/EmitTOP.scala b/chisel/src/main/scala/linxcore/top/EmitTOP.scala new file mode 100644 index 00000000..b5ba4636 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/EmitTOP.scala @@ -0,0 +1,35 @@ +package linxcore.top + +import java.nio.charset.StandardCharsets +import java.nio.file.{Files, Paths} +import linxcore.params.{NaturalPlatformParams, ParamProfiles, + SimulationParamProfiles} + +object EmitTOP extends App { + private val width = sys.env.get("LINX_TOP_WIDTH").map(_.toInt).getOrElse(4) + private val resetVector = sys.env.get("LINX_TOP_RESET_PC") + .map(value => BigInt(value.stripPrefix("0x"), 16)) + private val base = if (sys.env.get("LINX_TOP_SIMULATION_PROFILE").contains("1")) + NaturalPlatformParams(SimulationParamProfiles.forWidth(width)) + else ParamProfiles.forWidth(width) + private val p = base.copy(ifu = base.ifu.copy( + resetVector = resetVector.getOrElse(base.ifu.resetVector))) + + sys.env.get("LINX_TOP_PROFILE_METADATA").foreach { output => + val metadata = Seq( + s"stidCount=${p.ooo.stidCount}", + s"gprArchRegs=${p.ooo.gprArchRegs}", + "spAtag=1", + s"traceWidth=${p.dtu.traceWidth}", + s"retireWidth=${p.ooo.retireWidth}", + s"systemIssueLanes=${p.iex.systemMulticycleQueues}", + s"loadLanes=${p.lsu.loadPipes}", + s"storeLanes=${p.lsu.storePipes}").mkString("\n") + "\n" + Files.write(Paths.get(output), metadata.getBytes(StandardCharsets.UTF_8)) + } + + circt.stage.ChiselStage.emitSystemVerilogFile( + new TOP(p), + args, + firtoolOpts = Array("--disable-all-randomization", "--strip-debug-info")) +} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreBenchmarkAutonomousTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreBenchmarkAutonomousTop.scala deleted file mode 100644 index 34c15e4e..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreBenchmarkAutonomousTop.scala +++ /dev/null @@ -1,833 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.{Cat, Decoupled, Mux1H, PopCount, PriorityEncoder, UIntToOH, log2Ceil} - -import linxcore.commit.{CommitTraceParams, CommitTracePort} -import linxcore.common.{CoreParams, InterfaceParams} -import linxcore.frontend.ISideItlbRefill -import linxcore.system.{ReducedServiceRequestPayload, ReducedServiceRequestResponse} - -object LinxCoreBenchmarkAutonomousTop { - val BenchmarkRobEntries = 32 - val UartDataAddr: BigInt = BigInt("10000000", 16) - val TestFinisherAddr: BigInt = BigInt("10009000", 16) - val FinisherPass: BigInt = BigInt("5555", 16) - - val StatusIdle = 0 - val StatusFetch = 1 - val StatusUnsupported = 2 - val StatusFinisherPass = 3 - val StatusFinisherFail = 4 - - def interfaceParamsFor(coreParams: CoreParams): InterfaceParams = - LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor( - coreParams, - physRegWidth = log2Ceil(coreParams.scalarBackend.gprPhysRegs) - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) -} - -class LinxCoreBenchmarkAutonomousTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val mapQDepth: Int = LinxCoreBenchmarkAutonomousTop.BenchmarkRobEntries) - extends Bundle { - private val tuCountWidth = log2Ceil(mapQDepth + 1) - - val startValid = Input(Bool()) - val resetPc = Input(UInt(p.pcWidth.W)) - val resetSp = Input(UInt(p.immWidth.W)) - val restartValid = Input(Bool()) - val restartPc = Input(UInt(p.pcWidth.W)) - val restartSp = Input(UInt(p.immWidth.W)) - val flushValid = Input(Bool()) - val peId = Input(UInt(p.peIdWidth.W)) - val threadId = Input(UInt(p.threadIdWidth.W)) - - val fetchReqReady = Input(Bool()) - val fetchRespValid = Input(Bool()) - val fetchRespWindow = Input(UInt(p.windowWidth.W)) - - val fetchReqValid = Output(Bool()) - val fetchReqPc = Output(UInt(p.pcWidth.W)) - val fetchReqFire = Output(Bool()) - val fetchRespReady = Output(Bool()) - val fetchRespFire = Output(Bool()) - val fetchCurrentPc = Output(UInt(p.pcWidth.W)) - val sourceOutFire = Output(Bool()) - val sourceRestartValid = Output(Bool()) - val sourceRestartPc = Output(UInt(p.pcWidth.W)) - val debugSourceBlocked = Output(Bool()) - val debugSourceActive = Output(Bool()) - val debugSourceWaitingResponse = Output(Bool()) - val debugSourcePacketValid = Output(Bool()) - val debugBlockMarkerStopRedirectValid = Output(Bool()) - val debugBlockMarkerStopRedirectPc = Output(UInt(p.pcWidth.W)) - val debugMarkerRedirectFire = Output(Bool()) - val debugMarkerRedirectPending = Output(Bool()) - val debugMarkerRedirectPc = Output(UInt(p.pcWidth.W)) - val debugBodyCutAdvanceBytes = Output(UInt(4.W)) - val debugF4TotalLenBytes = Output(UInt(4.W)) - val debugReadinessBits = Output(UInt(8.W)) - val debugFretConditionBits = Output(UInt(8.W)) - val debugContinuationBits = Output(UInt(8.W)) - val debugLocalPendingCounts = Output(UInt(6.W)) - val debugLocalReadyMasks = Output(UInt(8.W)) - val debugLocalHeadPc = Output(UInt(p.pcWidth.W)) - val debugLocalExecuteCompleteValid = Output(Bool()) - val debugLocalCompletePc = Output(UInt(p.pcWidth.W)) - val debugLocalCompleteWbReg = Output(UInt(traceParams.regWidth.W)) - val debugDecodeBlockBits = Output(UInt(4.W)) - val debugDecodeReadyBits = Output(UInt(5.W)) - val debugTuRenameSourceUnderflowMask = Output(UInt(3.W)) - val debugTuRenameBlockedByTAlloc = Output(Bool()) - val debugTuRenameBlockedByUAlloc = Output(Bool()) - val debugTuRenameTUsedEntries = Output(UInt(tuCountWidth.W)) - val debugTuRenameUUsedEntries = Output(UInt(tuCountWidth.W)) - val debugTuRetireCommandValid = Output(Bool()) - val debugTuRetireCommandFire = Output(Bool()) - val debugTuRetireLocalBlockCommitPending = Output(Bool()) - val debugTuRetireLocalBlockCommitValid = Output(Bool()) - val debugTuRetireLocalBlockCommitReady = Output(Bool()) - val debugTuRetireLocalBlockCommitFire = Output(Bool()) - val debugTuRetireAccepted = Output(Bool()) - val debugTuRetireMiss = Output(Bool()) - val debugTuRetireReleaseMismatch = Output(Bool()) - val debugTuRetireUnsupported = Output(Bool()) - val debugGprReservationCount = Output(UInt(8.W)) - val debugGprReservationNeed = Output(UInt(8.W)) - val debugGprFreeCount = Output(UInt(8.W)) - val debugGprMapQValidCount = Output(UInt(8.W)) - val debugGprMapQFreeCount = Output(UInt(8.W)) - val debugGprFreeListMismatchCount = Output(UInt(8.W)) - val debugGprCommitAccepted = Output(Bool()) - val debugGprCommitBlockBid = Output(UInt(p.blockBidWidth.W)) - val debugGprCommittedMapQCount = Output(UInt(8.W)) - val debugGprReleasedPhysCount = Output(UInt(8.W)) - val debugRobRenameUpdateAttemptValid = Output(Bool()) - val debugRobRenameUpdateReady = Output(Bool()) - val debugRobRenameUpdateFire = Output(Bool()) - val debugRobRenameUpdateIgnored = Output(Bool()) - val debugCommitHeadValid = Output(Bool()) - val debugCommitHeadStatus = Output(UInt(3.W)) - val debugCommitHeadRobValue = Output(UInt(p.robIndexWidth.W)) - val debugRobOccupiedMask = Output(UInt(p.robEntries.W)) - val debugRobCompletedMask = Output(UInt(p.robEntries.W)) - val debugRobDeallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val debugRobDeallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val debugRobDeallocBlockLastValid = Output(Bool()) - val debugRobDeallocBlockLastBlockBid = Output(UInt(p.blockBidWidth.W)) - val debugBlockScalarDoneFire = Output(Bool()) - val debugBlockScalarDoneBid = Output(UInt(p.blockBidWidth.W)) - val debugBlockRetireFire = Output(Bool()) - val debugBlockRetireBid = Output(UInt(p.blockBidWidth.W)) - val debugDecRenHeadRidValid = Output(Bool()) - val debugDecRenHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val debugRenamedOutValid = Output(Bool()) - val debugRenamedAccepted = Output(Bool()) - val debugIssueEnqueueFire = Output(Bool()) - val debugIssueInputValid = Output(Bool()) - val debugIssueInputPc = Output(UInt(p.pcWidth.W)) - val debugIssueInputOpcode = Output(UInt(p.opcodeWidth.W)) - val debugIssueInputBidValid = Output(Bool()) - val debugIssueInputBidWrap = Output(Bool()) - val debugIssueInputBidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueInputRidValid = Output(Bool()) - val debugIssueInputRidWrap = Output(Bool()) - val debugIssueInputRidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueInputStid = Output(UInt(p.threadIdWidth.W)) - val debugIssuePickFire = Output(Bool()) - val debugIssueFire = Output(Bool()) - val debugIssueOutputValid = Output(Bool()) - val debugIssueOutputPc = Output(UInt(p.pcWidth.W)) - val debugIssueOutputOpcode = Output(UInt(p.opcodeWidth.W)) - val debugIssueOutputBidValid = Output(Bool()) - val debugIssueOutputBidWrap = Output(Bool()) - val debugIssueOutputBidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueOutputRidValid = Output(Bool()) - val debugIssueOutputRidWrap = Output(Bool()) - val debugIssueOutputRidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueOutputStid = Output(UInt(p.threadIdWidth.W)) - val debugIssueHeadValid = Output(Bool()) - val debugIssueHeadIssued = Output(Bool()) - val debugIssueHeadPc = Output(UInt(p.pcWidth.W)) - val debugIssueHeadStid = Output(UInt(p.threadIdWidth.W)) - val debugIssueHeadBidValid = Output(Bool()) - val debugIssueHeadBidWrap = Output(Bool()) - val debugIssueHeadBidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueHeadRidValid = Output(Bool()) - val debugIssueHeadRidWrap = Output(Bool()) - val debugIssueHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val debugIssueHeadSrcValidMask = Output(UInt(3.W)) - val debugIssueHeadSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val debugIssueSourceReadyMask = Output(UInt(3.W)) - val debugIssueAllSourcesReady = Output(Bool()) - val debugIssueSelectedValid = Output(Bool()) - val debugIssueSelectedIndex = Output(UInt(2.W)) - val debugIssueSelectedReadReady = Output(Bool()) - val debugIssueStageBits = Output(UInt(2.W)) - val debugIssueBlockedBits = Output(UInt(4.W)) - val debugIssueScalarSpOrderBlocked = Output(Bool()) - val debugIssueBankScalarSpOrderBlockedMask = Output(UInt(2.W)) - val debugScalarSpStid0IssueHeadValid = Output(Bool()) - val debugScalarSpStid0IssueHeadBidValid = Output(Bool()) - val debugScalarSpStid0IssueHeadBidWrap = Output(Bool()) - val debugScalarSpStid0IssueHeadBidValue = Output(UInt(p.robIndexWidth.W)) - val debugScalarSpStid0IssueHeadRidValid = Output(Bool()) - val debugScalarSpStid0IssueHeadRidWrap = Output(Bool()) - val debugScalarSpStid0IssueHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val debugRfReadyMask = Output(UInt(64.W)) - val debugPWakeupValid = Output(Bool()) - val debugPWakeupTag = Output(UInt(p.physRegWidth.W)) - val debugExecuteAccepted = Output(Bool()) - val debugExecuteAcceptedIdentityValid = Output(Bool()) - val debugExecuteAcceptedPc = Output(UInt(p.pcWidth.W)) - val debugExecuteAcceptedOpcode = Output(UInt(p.opcodeWidth.W)) - val debugExecuteAcceptedBidValid = Output(Bool()) - val debugExecuteAcceptedBidWrap = Output(Bool()) - val debugExecuteAcceptedBidValue = Output(UInt(p.robIndexWidth.W)) - val debugExecuteAcceptedRidValid = Output(Bool()) - val debugExecuteAcceptedRidWrap = Output(Bool()) - val debugExecuteAcceptedRidValue = Output(UInt(p.robIndexWidth.W)) - val debugExecuteAcceptedStid = Output(UInt(p.threadIdWidth.W)) - val debugExecuteBusy = Output(Bool()) - val debugExecuteUnsupported = Output(Bool()) - val debugExecuteUnsupportedOpcode = Output(UInt(p.opcodeWidth.W)) - val debugExecuteCompleteRobValue = Output(UInt(p.robIndexWidth.W)) - val debugExecuteCompleteSrcPhysValidMask = Output(UInt(3.W)) - val debugExecuteCompleteSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val debugRobCompleteArbiterBits = Output(UInt(3.W)) - val debugRobCompleteResultBits = Output(UInt(2.W)) - val scalarLrReservationValidStid0 = Output(Bool()) - val scalarLrReservationLineStid0 = Output(UInt(p.immWidth.W)) - val scalarLrReservationCount = Output(UInt(8.W)) - val scalarLrReservationProtocolError = Output(Bool()) - val scalarLrReservationBlockedByFlush = Output(Bool()) - val scalarLrReservationCommittedStoreInvalidate = Output(Bool()) - val storeStaQueueValid = Output(Bool()) - val storeStdQueueValid = Output(Bool()) - val storeStaDequeueFire = Output(Bool()) - val storeStdDequeueFire = Output(Bool()) - val storeStaQueueCount = Output(UInt(8.W)) - val storeStdQueueCount = Output(UInt(8.W)) - val storeStaInsertReady = Output(Bool()) - val storeStdInsertReady = Output(Bool()) - val storeSelectedSta = Output(Bool()) - val storeSelectedStd = Output(Bool()) - val storeBlockedByStaExec = Output(Bool()) - val storeBlockedByStdExec = Output(Bool()) - val storeStqInsertValid = Output(Bool()) - val storeStqInsertAccepted = Output(Bool()) - val storeStqInsertConflict = Output(Bool()) - val storeStqInsertIndex = Output(UInt(p.robIndexWidth.W)) - val storeStqOccupiedMask = Output(UInt(p.robEntries.W)) - val storeStqWaitMask = Output(UInt(p.robEntries.W)) - val storeStqCommitMask = Output(UInt(p.robEntries.W)) - val storeStqAddrReadyMask = Output(UInt(p.robEntries.W)) - val storeStqDataReadyMask = Output(UInt(p.robEntries.W)) - val storeStqResidentCount = Output(UInt(8.W)) - val storeStqOutstandingWaitCount = Output(UInt(8.W)) - val storeStqEmpty = Output(Bool()) - val storeStqFull = Output(Bool()) - val storeStqStall = Output(Bool()) - - val loadLookupData = Input(UInt(p.immWidth.W)) - val loadPairFirstLookupData = Input(UInt(p.immWidth.W)) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(p.immWidth.W)) - val loadPairFirstLookupValid = Output(Bool()) - val loadPairFirstLookupAddr = Output(UInt(p.immWidth.W)) - val loadLookupPc = Output(UInt(p.pcWidth.W)) - val loadLookupExecuteGranted = Output(Bool()) - val loadLookupReplayGranted = Output(Bool()) - val loadLookupDstValid = Output(Bool()) - val loadLookupDstKind = Output(UInt(2.W)) - val loadLookupDstArchTag = Output(UInt(p.archRegWidth.W)) - val loadLookupDstRelTag = Output(UInt(p.archRegWidth.W)) - val loadLookupDstPhysTag = Output(UInt(p.physRegWidth.W)) - val loadLookupDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedServiceRequest = Decoupled(new ReducedServiceRequestPayload(p)) - val reducedServiceResponse = Flipped(Decoupled(new ReducedServiceRequestResponse(p))) - - val commit = Output(new CommitTracePort(traceParams)) - - val storeObserveValid = Output(Bool()) - val storeObserveAddr = Output(UInt(p.immWidth.W)) - val storeObserveData = Output(UInt(p.immWidth.W)) - val storeObserveSize = Output(UInt(p.memSizeWidth.W)) - val storeObserveMask = Output(UInt(8.W)) - val storeObservePairValid = Output(Bool()) - val storeObservePairAddr = Output(UInt(p.immWidth.W)) - val storeObservePairData = Output(UInt(p.immWidth.W)) - val storeObservePairSize = Output(UInt(p.memSizeWidth.W)) - val storeObservePairMask = Output(UInt(8.W)) - val storeObservePc = Output(UInt(p.pcWidth.W)) - val storeObserveSeq = Output(UInt(traceParams.seqWidth.W)) - val storeObserveCycle = Output(UInt(traceParams.cycleWidth.W)) - val storeObserveSlot = Output(UInt(traceParams.slotWidth.W)) - val storeObserveBid = Output(UInt(32.W)) - val storeObserveGid = Output(UInt(32.W)) - val storeObserveRid = Output(UInt(32.W)) - val storeObserveRobValid = Output(Bool()) - val storeObserveRobWrap = Output(Bool()) - val storeObserveRobValue = Output(UInt(p.robIndexWidth.W)) - val storeObserveBlockBidValid = Output(Bool()) - val storeObserveBlockBid = Output(UInt(p.blockBidWidth.W)) - - val uartWriteValid = Output(Bool()) - val uartWriteByte = Output(UInt(8.W)) - val finisherWriteValid = Output(Bool()) - val finisherCode = Output(UInt(16.W)) - val finisherPayload = Output(UInt(32.W)) - val finisherPass = Output(Bool()) - - val bootSp = Output(UInt(p.immWidth.W)) - val active = Output(Bool()) - val halted = Output(Bool()) - val trapValid = Output(Bool()) - val unsupportedInstruction = Output(Bool()) - val unsupportedPc = Output(UInt(p.pcWidth.W)) - val status = Output(UInt(4.W)) -} - -private class BenchmarkStoreSideEffectPayload( - val p: InterfaceParams, - val traceParams: CommitTraceParams) - extends Bundle { - val addr = UInt(p.immWidth.W) - val data = UInt(p.immWidth.W) - val size = UInt(p.memSizeWidth.W) - val mask = UInt(8.W) - val pairValid = Bool() - val pairAddr = UInt(p.immWidth.W) - val pairData = UInt(p.immWidth.W) - val pairSize = UInt(p.memSizeWidth.W) - val pairMask = UInt(8.W) - val pc = UInt(p.pcWidth.W) - val seq = UInt(traceParams.seqWidth.W) - val cycle = UInt(traceParams.cycleWidth.W) - val slot = UInt(traceParams.slotWidth.W) - val bid = UInt(32.W) - val gid = UInt(32.W) - val rid = UInt(32.W) - val robValid = Bool() - val robWrap = Bool() - val robValue = UInt(p.robIndexWidth.W) - val blockBidValid = Bool() - val blockBid = UInt(p.blockBidWidth.W) - val uartWrite = Bool() - val uartByte = UInt(8.W) - val finisherWrite = Bool() - val finisherCode = UInt(16.W) - val finisherPayload = UInt(32.W) - val finisherPass = Bool() -} - -class LinxCoreBenchmarkAutonomousTop( - coreParams: CoreParams = - CoreParams(robEntries = LinxCoreBenchmarkAutonomousTop.BenchmarkRobEntries, commitWidth = 2)) - extends Module { - require(coreParams.commitWidth <= 2, - "autonomous benchmark top observes at most two committed rows per cycle") - - private val p = LinxCoreBenchmarkAutonomousTop.interfaceParamsFor(coreParams) - private val traceParams = LinxCoreBenchmarkAutonomousTop.traceParamsFor(p) - val io = IO(new LinxCoreBenchmarkAutonomousTopIO(p, traceParams, coreParams.scalarLsu.mapQDepth)) - - private val live = Module(new LinxCoreFrontendFetchRfAluTraceTop( - coreParams = coreParams, - archRegs = coreParams.scalarBackend.gprArchRegs, - physRegs = coreParams.scalarBackend.gprPhysRegs, - mapQDepth = coreParams.scalarLsu.mapQDepth, - gprMapQDepth = coreParams.scalarBackend.gprMapQDepth, - scalarStidCount = coreParams.scalarLsu.stidCount, - useReducedStoreDispatchStq = true, - useReducedStoreStaAddressExecBridge = true, - useProductionD1Ingress = true - )) - - private val productionIfu = Module(new LinxCoreComposition( - p = p, - threadCount = 1, - lineBytes = 64, - pageBytes = 4096, - itlbEntries = 16, - l1iSets = 64, - missEntries = 8, - joinEntries = 8, - maxGroupsPerTransaction = 8, - instructionBufferDepth = 16, - lineBridgeEntries = 8, - feedbackEntries = 2 - )) - private val lineFill = Module(new IfuWindowLineFillAdapter(p, lineBytes = 64)) - - private val bootSpReg = RegInit(0.U(p.immWidth.W)) - private val haltedReg = RegInit(false.B) - private val trapReg = RegInit(false.B) - private val unsupportedReg = RegInit(false.B) - private val unsupportedPcReg = RegInit(0.U(p.pcWidth.W)) - private val finisherSeenReg = RegInit(false.B) - private val finisherPassReg = RegInit(false.B) - private val finisherCodeReg = RegInit(0.U(16.W)) - private val finisherPayloadReg = RegInit(0.U(32.W)) - private val statusReg = RegInit(LinxCoreBenchmarkAutonomousTop.StatusIdle.U(4.W)) - - private val startOrRestart = io.startValid || io.restartValid - private val selectedSp = Mux(io.restartValid, io.restartSp, io.resetSp) - private val sourceBlocked = haltedReg || trapReg || finisherSeenReg - private val hardFlush = io.flushValid || sourceBlocked - - productionIfu.io.start.valid := io.startValid || io.restartValid || live.io.sourceRestartValid - productionIfu.io.start.bits.peId := io.peId - productionIfu.io.start.bits.threadId := io.threadId - productionIfu.io.start.bits.pc := Mux( - live.io.sourceRestartValid, - live.io.sourceRestartPc, - Mux(io.restartValid, io.restartPc, io.resetPc)) - - private val ptwRefillValid = RegNext(productionIfu.io.ptwRequest.fire, false.B) - private val ptwRefill = RegInit(0.U.asTypeOf(new ISideItlbRefill(p, pageBytes = 4096))) - productionIfu.io.ptwRequest.ready := true.B - when(productionIfu.io.ptwRequest.fire) { - ptwRefill.vpn := productionIfu.io.ptwRequest.bits.vpn - ptwRefill.ppn := productionIfu.io.ptwRequest.bits.vpn - ptwRefill.executable := true.B - } - productionIfu.io.ptwRefill.valid := ptwRefillValid - productionIfu.io.ptwRefill.bits := ptwRefill - productionIfu.io.fetchFault.ready := true.B - productionIfu.io.invalidateItlb := false.B - productionIfu.io.invalidateL1I := false.B - productionIfu.io.d1ThreadId := io.threadId - productionIfu.io.backendValidation <> live.io.backendValidation - productionIfu.io.recoveryRedirect.valid := false.B - productionIfu.io.recoveryRedirect.bits := - 0.U.asTypeOf(productionIfu.io.recoveryRedirect.bits) - - lineFill.io.lineRequest <> productionIfu.io.memoryRequest - productionIfu.io.memoryResponse <> lineFill.io.lineResponse - lineFill.io.fetchReqReady := io.fetchReqReady && !sourceBlocked - lineFill.io.fetchRespValid := io.fetchRespValid && !sourceBlocked - lineFill.io.fetchRespWindow := io.fetchRespWindow - - live.io.productionD1 <> productionIfu.io.decoded - live.io.productionIfuFlush := productionIfu.io.canonicalFlush.bits - - live.io.startValid := io.startValid - live.io.startPc := io.resetPc - live.io.restartValid := io.restartValid - live.io.restartPc := io.restartPc - live.io.bfuBodyValid := false.B - live.io.bfuHeaderPc := 0.U - live.io.bfuHSizeBytes := 0.U - live.io.bfuBSizeBytes := 0.U - live.io.frontendFlushValid := hardFlush - live.io.peId := io.peId - live.io.threadId := io.threadId - live.io.fetchReqReady := false.B - live.io.fetchRespValid := false.B - live.io.fetchRespWindow := 0.U - live.io.rfInitValid := startOrRestart - live.io.rfInitArchTag := 1.U - live.io.rfInitData := selectedSp - live.io.deallocReady := !sourceBlocked - live.io.loadLookupData := io.loadLookupData - live.io.loadPairFirstLookupData := io.loadPairFirstLookupData - live.io.reducedServiceRequest <> io.reducedServiceRequest - live.io.reducedServiceResponse <> io.reducedServiceResponse - - private val acceptedRows = VecInit(live.io.commit.rows.map { row => - row.valid && !startOrRestart && !io.flushValid && !sourceBlocked - }) - private val firstAcceptedIndex = PriorityEncoder(acceptedRows.asUInt) - private val firstAcceptedRow = Mux1H(UIntToOH(firstAcceptedIndex, traceParams.commitWidth), live.io.commit.rows) - private val unsupported = !startOrRestart && !io.flushValid && !sourceBlocked && live.io.commitContractError - private val sideEffectPayloads = Wire(Vec(traceParams.commitWidth, new BenchmarkStoreSideEffectPayload(p, traceParams))) - private val sideEffectValid = Wire(Vec(traceParams.commitWidth, Bool())) - private val fatalCommit = Wire(Vec(traceParams.commitWidth, Bool())) - private val zeroSideEffect = 0.U.asTypeOf(new BenchmarkStoreSideEffectPayload(p, traceParams)) - - for (slot <- 0 until traceParams.commitWidth) { - val row = live.io.commit.rows(slot) - val storeSize = row.mem.size(p.memSizeWidth - 1, 0) - val lowAddr = row.mem.addr(2, 0) - val storeSizeFitsLane = storeSize =/= 0.U && storeSize <= 8.U - val storeEndOffset = lowAddr +& storeSize - val storeFitsObservationLane = storeSizeFitsLane && storeEndOffset <= 8.U - val pairStoreInsn = - ((row.insn & "h707f003f".U(traceParams.insnWidth.W)) === "h2059001e".U) || - ((row.insn & "h707f003f".U(traceParams.insnWidth.W)) === "h6059001e".U) || - ((row.insn & "h707f003f".U(traceParams.insnWidth.W)) === "h3059001e".U) || - ((row.insn & "h707f003f".U(traceParams.insnWidth.W)) === "h7059001e".U) - val pairStoreAddr = row.mem.addr + storeSize - val pairStoreLowAddr = pairStoreAddr(2, 0) - val pairStoreEndOffset = pairStoreLowAddr +& storeSize - val pairStoreFitsObservationLane = storeSizeFitsLane && pairStoreEndOffset <= 8.U - val priorFatal = - if (slot == 0) false.B else fatalCommit.asUInt(slot - 1, 0).orR - val invalidStoreSideEffect = - acceptedRows(slot) && !live.io.commitContractError && !row.trap.valid && row.mem.valid && row.mem.isStore && - (!storeFitsObservationLane || (pairStoreInsn && !pairStoreFitsObservationLane)) - fatalCommit(slot) := acceptedRows(slot) && (row.trap.valid || live.io.commitContractError || invalidStoreSideEffect) - sideEffectValid(slot) := - acceptedRows(slot) && !priorFatal && !live.io.commitContractError && !row.trap.valid && - row.mem.valid && row.mem.isStore && storeFitsObservationLane - - val baseMaskWide = (1.U(9.W) << storeSize) - 1.U - val shiftedMask = (baseMaskWide(7, 0) << lowAddr)(7, 0) - val shiftedStoreData = - (row.mem.wdata << Cat(lowAddr, 0.U(3.W)))(p.immWidth - 1, 0) - val pairShiftedMask = (baseMaskWide(7, 0) << pairStoreLowAddr)(7, 0) - val pairShiftedStoreData = - (row.src1.data << Cat(pairStoreLowAddr, 0.U(3.W)))(p.immWidth - 1, 0) - - val payload = Wire(new BenchmarkStoreSideEffectPayload(p, traceParams)) - payload := zeroSideEffect - payload.addr := row.mem.addr - payload.data := shiftedStoreData - payload.size := storeSize - payload.mask := Mux(storeFitsObservationLane, shiftedMask, 0.U) - payload.pairValid := pairStoreInsn && pairStoreFitsObservationLane - payload.pairAddr := pairStoreAddr - payload.pairData := pairShiftedStoreData - payload.pairSize := storeSize - payload.pairMask := Mux(pairStoreFitsObservationLane, pairShiftedMask, 0.U) - payload.pc := row.pc - payload.seq := row.seq - payload.cycle := row.cycle - payload.slot := row.slot - payload.bid := row.identity.bid - payload.gid := row.identity.gid - payload.rid := row.identity.rid - payload.robValid := row.rob.valid - payload.robWrap := row.rob.wrap - payload.robValue := row.rob.value - payload.blockBidValid := row.blockBidValid - payload.blockBid := row.blockBid - payload.uartWrite := row.mem.addr === LinxCoreBenchmarkAutonomousTop.UartDataAddr.U(p.immWidth.W) - payload.uartByte := row.mem.wdata(7, 0) - payload.finisherWrite := row.mem.addr === LinxCoreBenchmarkAutonomousTop.TestFinisherAddr.U(p.immWidth.W) - payload.finisherCode := row.mem.wdata(15, 0) - payload.finisherPayload := row.mem.wdata(31, 0) - payload.finisherPass := row.mem.wdata(15, 0) === LinxCoreBenchmarkAutonomousTop.FinisherPass.U(16.W) - sideEffectPayloads(slot) := payload - } - - private val trapCommit = (fatalCommit.asUInt & VecInit(live.io.commit.rows.map(_.trap.valid)).asUInt).orR - private val invalidStoreSideEffect = (0 until traceParams.commitWidth).map { slot => - fatalCommit(slot) && !live.io.commit.rows(slot).trap.valid && !live.io.commitContractError - }.reduce(_ || _) - - private val currentSideEffectValid = sideEffectValid.asUInt.orR - assert(PopCount(sideEffectValid) <= 1.U, - "autonomous benchmark top observed multiple committed stores in one cycle") - private val currentSideEffectIndex = PriorityEncoder(sideEffectValid.asUInt) - private val currentSideEffectPayload = - Mux1H(UIntToOH(currentSideEffectIndex, traceParams.commitWidth), sideEffectPayloads) - private val selectedSideEffectValid = currentSideEffectValid - private val selectedSideEffect = currentSideEffectPayload - - when(startOrRestart) { - bootSpReg := selectedSp - haltedReg := false.B - trapReg := false.B - unsupportedReg := false.B - unsupportedPcReg := 0.U - finisherSeenReg := false.B - finisherPassReg := false.B - finisherCodeReg := 0.U - finisherPayloadReg := 0.U - statusReg := LinxCoreBenchmarkAutonomousTop.StatusFetch.U - }.elsewhen(io.flushValid) { - haltedReg := true.B - trapReg := false.B - unsupportedReg := false.B - statusReg := LinxCoreBenchmarkAutonomousTop.StatusIdle.U - }.elsewhen(selectedSideEffectValid && selectedSideEffect.finisherWrite) { - finisherSeenReg := true.B - finisherPassReg := selectedSideEffect.finisherPass - finisherCodeReg := selectedSideEffect.finisherCode - finisherPayloadReg := selectedSideEffect.finisherPayload - haltedReg := true.B - trapReg := !selectedSideEffect.finisherPass - statusReg := Mux( - selectedSideEffect.finisherPass, - LinxCoreBenchmarkAutonomousTop.StatusFinisherPass.U, - LinxCoreBenchmarkAutonomousTop.StatusFinisherFail.U - ) - }.elsewhen(trapCommit || unsupported || invalidStoreSideEffect) { - haltedReg := true.B - trapReg := true.B - unsupportedReg := unsupported || invalidStoreSideEffect - unsupportedPcReg := firstAcceptedRow.pc - statusReg := LinxCoreBenchmarkAutonomousTop.StatusUnsupported.U - } - - io.fetchReqValid := lineFill.io.fetchReqValid && !sourceBlocked - io.fetchReqPc := lineFill.io.fetchReqPc - io.fetchReqFire := lineFill.io.fetchReqFire && !sourceBlocked - io.fetchRespReady := lineFill.io.fetchRespReady && !sourceBlocked - io.fetchRespFire := lineFill.io.fetchRespFire && !sourceBlocked - io.fetchCurrentPc := productionIfu.io.currentPc(0) - io.sourceOutFire := live.io.sourceOutFire - io.sourceRestartValid := live.io.sourceRestartValid - io.sourceRestartPc := live.io.sourceRestartPc - io.debugSourceBlocked := sourceBlocked - io.debugSourceActive := productionIfu.io.active(0) - io.debugSourceWaitingResponse := lineFill.io.active - io.debugSourcePacketValid := productionIfu.io.decoded.valid - io.debugBlockMarkerStopRedirectValid := live.io.debugBlockMarkerStopRedirectValid - io.debugBlockMarkerStopRedirectPc := live.io.debugBlockMarkerStopRedirectPc - io.debugMarkerRedirectFire := live.io.debugMarkerRedirectFire - io.debugMarkerRedirectPending := live.io.debugMarkerRedirectPending - io.debugMarkerRedirectPc := live.io.debugMarkerRedirectPc - io.debugBodyCutAdvanceBytes := productionIfu.io.lineOutstandingCount - io.debugF4TotalLenBytes := productionIfu.io.joinCount - io.debugReadinessBits := Cat( - productionIfu.io.f3WaitingForNextLine, - productionIfu.io.crossLinePending, - productionIfu.io.ptwPending, - productionIfu.io.bSideStageValid) - io.debugFretConditionBits := live.io.debugFretConditionBits - io.debugContinuationBits := live.io.debugContinuationBits - io.debugLocalPendingCounts := Cat(live.io.localUPendingCount, live.io.localTPendingCount) - io.debugLocalReadyMasks := Cat(live.io.localUReadyMask, live.io.localTReadyMask) - io.debugLocalHeadPc := live.io.decRenHeadPc - io.debugLocalExecuteCompleteValid := live.io.executeCompleteValid - io.debugLocalCompletePc := live.io.executeCompletePc - io.debugLocalCompleteWbReg := live.io.executeCompleteWbReg - io.debugDecodeBlockBits := Cat( - live.io.decodeBlockedByTURename, - live.io.decodeBlockedByOutput, - live.io.decodeBlockedByRob, - live.io.decodeBlockedByRename) - io.debugDecodeReadyBits := Cat( - live.io.decodeSelectedNeedsGprReservation, - live.io.decodeSelectedClosesActiveRedirect, - live.io.decodeGprReservationReady, - live.io.decodeAllocReady, - live.io.decodeQueuePushReady) - io.debugTuRenameSourceUnderflowMask := live.io.tuRenameSourceUnderflowMask - io.debugTuRenameBlockedByTAlloc := live.io.tuRenameBlockedByTAlloc - io.debugTuRenameBlockedByUAlloc := live.io.tuRenameBlockedByUAlloc - io.debugTuRenameTUsedEntries := live.io.tuRenameTUsedEntries - io.debugTuRenameUUsedEntries := live.io.tuRenameUUsedEntries - io.debugTuRetireCommandValid := live.io.tuRetireCommandValid - io.debugTuRetireCommandFire := live.io.tuRetireCommandFire - io.debugTuRetireLocalBlockCommitPending := live.io.tuRetireLocalBlockCommitPending - io.debugTuRetireLocalBlockCommitValid := live.io.tuRetireLocalBlockCommitValid - io.debugTuRetireLocalBlockCommitReady := live.io.tuRetireLocalBlockCommitReady - io.debugTuRetireLocalBlockCommitFire := live.io.tuRetireLocalBlockCommitFire - io.debugTuRetireAccepted := live.io.tuRetireAccepted - io.debugTuRetireMiss := live.io.tuRetireMiss - io.debugTuRetireReleaseMismatch := live.io.tuRetireReleaseMismatch - io.debugTuRetireUnsupported := live.io.tuRetireUnsupported - io.debugGprReservationCount := live.io.gprReservationCount - io.debugGprReservationNeed := live.io.gprReservationNeed - io.debugGprFreeCount := live.io.gprFreeCount - io.debugGprMapQValidCount := live.io.gprMapQValidCount - io.debugGprMapQFreeCount := live.io.gprMapQFreeCount - io.debugGprFreeListMismatchCount := live.io.gprFreeListMismatchCount - io.debugGprCommitAccepted := live.io.gprCommitAccepted - io.debugGprCommitBlockBid := live.io.gprCommitBlockBid - io.debugGprCommittedMapQCount := live.io.gprCommittedMapQCount - io.debugGprReleasedPhysCount := live.io.gprReleasedPhysCount - io.debugRobRenameUpdateAttemptValid := live.io.robRenameUpdateAttemptValid - io.debugRobRenameUpdateReady := live.io.robRenameUpdateReady - io.debugRobRenameUpdateFire := live.io.robRenameUpdateFire - io.debugRobRenameUpdateIgnored := live.io.robRenameUpdateIgnored - io.debugCommitHeadValid := live.io.commitHeadValid - io.debugCommitHeadStatus := live.io.commitHeadStatus.asUInt - io.debugCommitHeadRobValue := live.io.commitHeadRobValue - io.debugRobOccupiedMask := live.io.occupiedMask - io.debugRobCompletedMask := live.io.completedMask - io.debugRobDeallocValidMask := live.io.deallocValidMask - io.debugRobDeallocCount := live.io.deallocCount - io.debugRobDeallocBlockLastValid := live.io.robDeallocBlockLastValid - io.debugRobDeallocBlockLastBlockBid := live.io.robDeallocBlockLastBlockBid - io.debugBlockScalarDoneFire := live.io.blockScalarDoneFire - io.debugBlockScalarDoneBid := live.io.blockScalarDoneBid - io.debugBlockRetireFire := live.io.blockRetireFire - io.debugBlockRetireBid := live.io.blockRetireBid - io.debugDecRenHeadRidValid := live.io.decRenHeadRidValid - io.debugDecRenHeadRidValue := live.io.decRenHeadRidValue - io.debugRenamedOutValid := live.io.renamedOutValid - io.debugRenamedAccepted := live.io.renamedAccepted - io.debugIssueEnqueueFire := live.io.issueQueueEnqueueFire - io.debugIssueInputValid := live.io.issueQueueInputValid - io.debugIssueInputPc := live.io.issueQueueInputPc - io.debugIssueInputOpcode := live.io.issueQueueInputOpcode - io.debugIssueInputBidValid := live.io.issueQueueInputBidValid - io.debugIssueInputBidWrap := live.io.issueQueueInputBidWrap - io.debugIssueInputBidValue := live.io.issueQueueInputBidValue - io.debugIssueInputRidValid := live.io.issueQueueInputRidValid - io.debugIssueInputRidWrap := live.io.issueQueueInputRidWrap - io.debugIssueInputRidValue := live.io.issueQueueInputRidValue - io.debugIssueInputStid := live.io.issueQueueInputStid - io.debugIssuePickFire := live.io.issueQueuePickFire - io.debugIssueFire := live.io.issueQueueIssueFire - io.debugIssueOutputValid := live.io.issueQueueOutputValid - io.debugIssueOutputPc := live.io.issueQueueOutputPc - io.debugIssueOutputOpcode := live.io.issueQueueOutputOpcode - io.debugIssueOutputBidValid := live.io.issueQueueOutputBidValid - io.debugIssueOutputBidWrap := live.io.issueQueueOutputBidWrap - io.debugIssueOutputBidValue := live.io.issueQueueOutputBidValue - io.debugIssueOutputRidValid := live.io.issueQueueOutputRidValid - io.debugIssueOutputRidWrap := live.io.issueQueueOutputRidWrap - io.debugIssueOutputRidValue := live.io.issueQueueOutputRidValue - io.debugIssueOutputStid := live.io.issueQueueOutputStid - io.debugIssueHeadValid := live.io.issueQueueHeadValid - io.debugIssueHeadIssued := live.io.issueQueueHeadIssued - io.debugIssueHeadPc := live.io.issueQueueHeadPc - io.debugIssueHeadStid := live.io.issueQueueHeadStid - io.debugIssueHeadBidValid := live.io.issueQueueHeadBidValid - io.debugIssueHeadBidWrap := live.io.issueQueueHeadBidWrap - io.debugIssueHeadBidValue := live.io.issueQueueHeadBidValue - io.debugIssueHeadRidValid := live.io.issueQueueHeadRidValid - io.debugIssueHeadRidWrap := live.io.issueQueueHeadRidWrap - io.debugIssueHeadRidValue := live.io.issueQueueHeadRidValue - io.debugIssueHeadSrcValidMask := live.io.issueQueueHeadSrcValidMask - io.debugIssueHeadSrcPhysTag := live.io.issueQueueHeadSrcPhysTag - io.debugIssueSourceReadyMask := live.io.issueQueueSourceReadyMask - io.debugIssueAllSourcesReady := live.io.issueQueueAllSourcesReady - io.debugIssueSelectedValid := live.io.issueQueueSelectedValid - io.debugIssueSelectedIndex := live.io.issueQueueSelectedIndex - io.debugIssueSelectedReadReady := live.io.issueQueueSelectedReadReady - io.debugIssueStageBits := Cat(live.io.issueQueueI2Valid, live.io.issueQueueI1Valid) - io.debugIssueBlockedBits := Cat( - live.io.issueQueueBlockedByIssued, - live.io.issueQueueBlockedByOutput, - live.io.issueQueueBlockedByRead, - live.io.issueQueueBlockedBySource) - io.debugIssueScalarSpOrderBlocked := live.io.issueQueueScalarSpOrderBlocked - io.debugIssueBankScalarSpOrderBlockedMask := live.io.issueQueueBankScalarSpOrderBlockedMask - io.debugScalarSpStid0IssueHeadValid := live.io.scalarSpStid0IssueHeadValid - io.debugScalarSpStid0IssueHeadBidValid := live.io.scalarSpStid0IssueHeadBidValid - io.debugScalarSpStid0IssueHeadBidWrap := live.io.scalarSpStid0IssueHeadBidWrap - io.debugScalarSpStid0IssueHeadBidValue := live.io.scalarSpStid0IssueHeadBidValue - io.debugScalarSpStid0IssueHeadRidValid := live.io.scalarSpStid0IssueHeadRidValid - io.debugScalarSpStid0IssueHeadRidWrap := live.io.scalarSpStid0IssueHeadRidWrap - io.debugScalarSpStid0IssueHeadRidValue := live.io.scalarSpStid0IssueHeadRidValue - io.debugRfReadyMask := live.io.rfReadyMask - io.debugPWakeupValid := live.io.rfWriteValid - io.debugPWakeupTag := live.io.rfWriteTag - io.debugExecuteAccepted := live.io.executeAccepted - io.debugExecuteAcceptedIdentityValid := live.io.executeAcceptedIdentityValid - io.debugExecuteAcceptedPc := live.io.executeAcceptedPc - io.debugExecuteAcceptedOpcode := live.io.executeAcceptedOpcode - io.debugExecuteAcceptedBidValid := live.io.executeAcceptedBidValid - io.debugExecuteAcceptedBidWrap := live.io.executeAcceptedBidWrap - io.debugExecuteAcceptedBidValue := live.io.executeAcceptedBidValue - io.debugExecuteAcceptedRidValid := live.io.executeAcceptedRidValid - io.debugExecuteAcceptedRidWrap := live.io.executeAcceptedRidWrap - io.debugExecuteAcceptedRidValue := live.io.executeAcceptedRidValue - io.debugExecuteAcceptedStid := live.io.executeAcceptedStid - io.debugExecuteBusy := live.io.executeBusy - io.debugExecuteUnsupported := live.io.executeUnsupported - io.debugExecuteUnsupportedOpcode := live.io.executeUnsupportedOpcode - io.debugExecuteCompleteRobValue := live.io.executeCompleteRobValue - io.debugExecuteCompleteSrcPhysValidMask := live.io.executeCompleteSrcPhysValidMask - io.debugExecuteCompleteSrcPhysTag := live.io.executeCompleteSrcPhysTag - io.debugRobCompleteArbiterBits := Cat( - live.io.robCompleteArbiterReplayBlockedByExecute, - live.io.robCompleteArbiterSelectedReplay, - live.io.robCompleteArbiterSelectedExecute) - io.debugRobCompleteResultBits := Cat(live.io.completeIgnored, live.io.completeAccepted) - io.scalarLrReservationValidStid0 := live.io.scalarLrReservationValidStid0 - io.scalarLrReservationLineStid0 := live.io.scalarLrReservationLineStid0 - io.scalarLrReservationCount := live.io.scalarLrReservationCount - io.scalarLrReservationProtocolError := live.io.scalarLrReservationProtocolError - io.scalarLrReservationBlockedByFlush := live.io.scalarLrReservationBlockedByFlush - io.scalarLrReservationCommittedStoreInvalidate := live.io.scalarLrReservationCommittedStoreInvalidate - io.storeStaQueueValid := live.io.storeStaQueueValid - io.storeStdQueueValid := live.io.storeStdQueueValid - io.storeStaDequeueFire := live.io.storeStaDequeueFire - io.storeStdDequeueFire := live.io.storeStdDequeueFire - io.storeStaQueueCount := live.io.storeStaQueueCount - io.storeStdQueueCount := live.io.storeStdQueueCount - io.storeStaInsertReady := live.io.storeStaInsertReady - io.storeStdInsertReady := live.io.storeStdInsertReady - io.storeSelectedSta := live.io.storeSelectedSta - io.storeSelectedStd := live.io.storeSelectedStd - io.storeBlockedByStaExec := live.io.storeBlockedByStaExec - io.storeBlockedByStdExec := live.io.storeBlockedByStdExec - io.storeStqInsertValid := live.io.storeStqInsertValid - io.storeStqInsertAccepted := live.io.storeStqInsertAccepted - io.storeStqInsertConflict := live.io.storeStqInsertConflict - io.storeStqInsertIndex := live.io.storeStqInsertIndex - io.storeStqOccupiedMask := live.io.storeStqOccupiedMask - io.storeStqWaitMask := live.io.storeStqWaitMask - io.storeStqCommitMask := live.io.storeStqCommitMask - io.storeStqAddrReadyMask := live.io.storeStqAddrReadyMask - io.storeStqDataReadyMask := live.io.storeStqDataReadyMask - io.storeStqResidentCount := live.io.storeStqResidentCount - io.storeStqOutstandingWaitCount := live.io.storeStqOutstandingWaitCount - io.storeStqEmpty := live.io.storeStqEmpty - io.storeStqFull := live.io.storeStqFull - io.storeStqStall := live.io.storeStqStall - - io.loadLookupValid := live.io.loadLookupValid && !sourceBlocked - io.loadLookupAddr := live.io.loadLookupAddr - io.loadPairFirstLookupValid := live.io.loadPairFirstLookupValid && !sourceBlocked - io.loadPairFirstLookupAddr := live.io.loadPairFirstLookupAddr - io.loadLookupPc := live.io.loadLookupPc - io.loadLookupExecuteGranted := live.io.loadLookupExecuteGranted - io.loadLookupReplayGranted := live.io.loadLookupReplayGranted - io.loadLookupDstValid := live.io.loadLookupDstValid - io.loadLookupDstKind := live.io.loadLookupDstKind - io.loadLookupDstArchTag := live.io.loadLookupDstArchTag - io.loadLookupDstRelTag := live.io.loadLookupDstRelTag - io.loadLookupDstPhysTag := live.io.loadLookupDstPhysTag - io.loadLookupDstOldPhysTag := live.io.loadLookupDstOldPhysTag - - io.commit := live.io.commit - - io.storeObserveValid := selectedSideEffectValid - io.storeObserveAddr := selectedSideEffect.addr - io.storeObserveData := selectedSideEffect.data - io.storeObserveSize := selectedSideEffect.size - io.storeObserveMask := selectedSideEffect.mask - io.storeObservePairValid := selectedSideEffectValid && selectedSideEffect.pairValid - io.storeObservePairAddr := selectedSideEffect.pairAddr - io.storeObservePairData := selectedSideEffect.pairData - io.storeObservePairSize := selectedSideEffect.pairSize - io.storeObservePairMask := selectedSideEffect.pairMask - io.storeObservePc := selectedSideEffect.pc - io.storeObserveSeq := selectedSideEffect.seq - io.storeObserveCycle := selectedSideEffect.cycle - io.storeObserveSlot := selectedSideEffect.slot - io.storeObserveBid := selectedSideEffect.bid - io.storeObserveGid := selectedSideEffect.gid - io.storeObserveRid := selectedSideEffect.rid - io.storeObserveRobValid := selectedSideEffect.robValid - io.storeObserveRobWrap := selectedSideEffect.robWrap - io.storeObserveRobValue := selectedSideEffect.robValue - io.storeObserveBlockBidValid := selectedSideEffect.blockBidValid - io.storeObserveBlockBid := selectedSideEffect.blockBid - - io.uartWriteValid := selectedSideEffectValid && selectedSideEffect.uartWrite - io.uartWriteByte := selectedSideEffect.uartByte - io.finisherWriteValid := selectedSideEffectValid && selectedSideEffect.finisherWrite - io.finisherCode := Mux(finisherSeenReg, finisherCodeReg, selectedSideEffect.finisherCode) - io.finisherPayload := Mux(finisherSeenReg, finisherPayloadReg, selectedSideEffect.finisherPayload) - io.finisherPass := finisherSeenReg && finisherPassReg - - io.bootSp := bootSpReg - io.active := live.io.sourceActive && !sourceBlocked - io.halted := haltedReg || trapReg || finisherSeenReg - io.trapValid := trapReg - io.unsupportedInstruction := unsupportedReg - io.unsupportedPc := unsupportedPcReg - io.status := statusReg -} - -object EmitLinxCoreBenchmarkAutonomousTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreBenchmarkAutonomousTop(), - args = Array("--target-dir", "generated/chisel") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendAluTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendAluTraceTop.scala deleted file mode 100644 index 06086e85..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendAluTraceTop.scala +++ /dev/null @@ -1,244 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.{Queue, log2Ceil} - -import linxcore.backend.DecodeRenameROBPath -import linxcore.commit.{CommitTraceParams, CommitTracePort} -import linxcore.common.{CoreParams, FrontendDecodePacket, InterfaceParams, RenamedUop} -import linxcore.execute.ReducedScalarAluExecute -import linxcore.frontend.F4DecodeWindow -import linxcore.lsu.StoreDispatchExecResult -import linxcore.rob.{ROBEntryStatus, ROBID} - -class FrontendAluExecuteIngress(val p: InterfaceParams) extends Bundle { - val uop = new RenamedUop(p) - val srcData = Vec(3, UInt(p.immWidth.W)) - val stackPointerData = UInt(p.immWidth.W) -} - -class LinxCoreFrontendAluTraceTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val decRenQueueDepth: Int = 4) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - private val sizeWidth = log2Ceil(p.robEntries + 1) - private val decRenCountWidth = log2Ceil(decRenQueueDepth + 1) - - val in = Input(new FrontendDecodePacket(p)) - val operandData = Input(Vec(3, UInt(p.immWidth.W))) - val frontendFlushValid = Input(Bool()) - val deallocReady = Input(Bool()) - - val f4ValidMask = Output(UInt(p.decodeWidth.W)) - val f4SlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val decodeReady = Output(Bool()) - val selectedValid = Output(Bool()) - val selectedRobValue = Output(UInt(ptrWidth.W)) - val selectedBlockBid = Output(UInt(p.blockBidWidth.W)) - val decRenPushFire = Output(Bool()) - val decRenPopFire = Output(Bool()) - val decRenCount = Output(UInt(decRenCountWidth.W)) - val renamedOutValid = Output(Bool()) - val renamedAccepted = Output(Bool()) - val executeAccepted = Output(Bool()) - val executeBusy = Output(Bool()) - val executeCompleteValid = Output(Bool()) - val executeCompleteRobValue = Output(UInt(ptrWidth.W)) - val executeUnsupported = Output(Bool()) - val executeUnsupportedOpcode = Output(UInt(p.opcodeWidth.W)) - val robAllocFire = Output(Bool()) - val robRenameUpdateFire = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeIgnored = Output(Bool()) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val deallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val deallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val outstandingCount = Output(UInt(sizeWidth.W)) - val commitHeadValid = Output(Bool()) - val commitHeadStatus = Output(ROBEntryStatus()) - val commitHeadRobValue = Output(UInt(ptrWidth.W)) - val occupiedMask = Output(UInt(p.robEntries.W)) - val completedMask = Output(UInt(p.robEntries.W)) - val retiredMask = Output(UInt(p.robEntries.W)) - val idle = Output(Bool()) -} - -class LinxCoreFrontendAluTraceTop( - val coreParams: CoreParams = CoreParams(), - val decRenQueueDepth: Int = 4, - val storeDispatchQueueDepth: Int = 4, - val mapQDepth: Int = 32) - extends Module { - private val p = LinxCoreFrontendAluTraceTop.interfaceParamsFor(coreParams) - private val traceParams = LinxCoreFrontendAluTraceTop.traceParamsFor(p) - val io = IO(new LinxCoreFrontendAluTraceTopIO(p, traceParams, decRenQueueDepth)) - - val f4 = Module(new F4DecodeWindow(p)) - f4.io.in := io.in - f4.io.flushValid := io.frontendFlushValid - - val path = Module(new DecodeRenameROBPath( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - mapQDepth = mapQDepth - )) - DecodeRenameROBPath.tieOffPredecoded(path) - - val execute = Module(new ReducedScalarAluExecute(p, traceParams)) - execute.io.completeReady := true.B - val executeIngress = withReset(reset.asBool || io.frontendFlushValid) { - Module(new Queue(new FrontendAluExecuteIngress(p), entries = 1, pipe = false, flow = true)) - } - - path.io.d1 := f4.io.d1 - path.io.slots := f4.io.slots - path.io.validMask := f4.io.validMask - path.io.samePacketNextSlotValid := false.B - path.io.samePacketNextSlot := 0.U.asTypeOf(path.io.samePacketNextSlot) - path.io.flushValid := io.frontendFlushValid - DecodeRenameROBPath.tieOffExplicitStoreCount(path) - DecodeRenameROBPath.tieOffStoreScResult(path) - path.io.storeAddressInsertPermit := true.B - path.io.renamedOutReady := executeIngress.io.enq.ready - path.io.storeStaExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeStdExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeMarkCommitValid := false.B - path.io.storeMarkCommitIndex := 0.U - path.io.storeCommitFreeValid := false.B - path.io.storeCommitFreeIndex := 0.U - path.io.storeCommitFreeMaskValid := false.B - path.io.storeCommitFreeMask := 0.U - path.io.deallocHoldMask := 0.U - path.io.checkpointValid := false.B - path.io.checkpointBid := ROBID.disabled(p.robEntries) - path.io.checkpointStid := 0.U - path.io.commitValid := false.B - path.io.commitBid := ROBID.disabled(p.robEntries) - path.io.commitBlockBid := 0.U - path.io.commitStid := 0.U - DecodeRenameROBPath.tieOffRecovery(path) - path.io.scalarCleanupOrderValid := false.B - path.io.scalarCleanupOrder := 0.U - path.io.completeValid := execute.io.completeValid - path.io.completeRobValue := execute.io.completeRobValue - path.io.completeRowValid := execute.io.completeValid - path.io.completeRow := execute.io.completeRow - path.io.blockBranchTakenValid := false.B - path.io.blockBranchTaken := false.B - path.io.scalarRedirectValid := false.B - path.io.scalarRedirectStid := 0.U - path.io.deallocReady := io.deallocReady - path.io.robStatusLookupValid := false.B - path.io.robStatusLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupValid := false.B - path.io.robCommitTraceLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupSourceTraceEnable := false.B - - executeIngress.io.enq.valid := path.io.renamedOutValid - executeIngress.io.enq.bits.uop := path.io.renamedOut - executeIngress.io.enq.bits.srcData := io.operandData - executeIngress.io.enq.bits.stackPointerData := io.operandData(1) - executeIngress.io.deq.ready := execute.io.inReady - - execute.io.inValid := executeIngress.io.deq.valid - execute.io.in := executeIngress.io.deq.bits.uop - execute.io.srcData := executeIngress.io.deq.bits.srcData - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := executeIngress.io.deq.bits.stackPointerData - execute.io.flushValid := io.frontendFlushValid - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.f4ValidMask := f4.io.validMask - io.f4SlotCount := f4.io.slotCount - io.decodeReady := path.io.decodeReady - io.selectedValid := path.io.selectedValid - io.selectedRobValue := path.io.selectedRobValue - io.selectedBlockBid := path.io.selectedBlockBid - io.decRenPushFire := path.io.decRenPushFire - io.decRenPopFire := path.io.decRenPopFire - io.decRenCount := path.io.decRenCount - io.renamedOutValid := path.io.renamedOutValid - io.renamedAccepted := path.io.accepted - io.executeAccepted := execute.io.accepted - io.executeBusy := execute.io.busy - io.executeCompleteValid := execute.io.completeValid - io.executeCompleteRobValue := execute.io.completeRobValue - io.executeUnsupported := execute.io.unsupported - io.executeUnsupportedOpcode := execute.io.unsupportedOpcode - io.robAllocFire := path.io.robAllocFire - io.robRenameUpdateFire := path.io.robRenameUpdateFire - io.completeAccepted := path.io.completeAccepted - io.completeIgnored := path.io.completeIgnored - - io.commit := path.io.commit - io.commitValidMask := path.io.commitValidMask - io.commitCount := path.io.commitCount - io.commitMonitorValidMask := path.io.commitMonitorValidMask - io.commitMonitorValidCount := path.io.commitMonitorValidCount - io.commitSkippedSlot := path.io.commitSkippedSlot - io.commitDuplicateIdentity := path.io.commitDuplicateIdentity - io.commitSlotMismatch := path.io.commitSlotMismatch - io.commitInvalidSideEffect := path.io.commitInvalidSideEffect - io.commitContractError := path.io.commitContractError - - io.deallocValidMask := path.io.deallocValidMask - io.deallocCount := path.io.deallocCount - io.empty := path.io.empty - io.full := path.io.full - io.size := path.io.size - io.outstandingCount := path.io.outstandingCount - io.commitHeadValid := path.io.commitHeadValid - io.commitHeadStatus := path.io.commitHeadStatus - io.commitHeadRobValue := path.io.commitHeadRobValue - io.occupiedMask := path.io.occupiedMask - io.completedMask := path.io.completedMask - io.retiredMask := path.io.retiredMask - io.idle := path.io.empty && !executeIngress.io.deq.valid && !execute.io.busy -} - -object LinxCoreFrontendAluTraceTop { - def interfaceParamsFor(coreParams: CoreParams): InterfaceParams = - InterfaceParams( - robEntries = coreParams.robEntries, - commitWidth = coreParams.commitWidth - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth - ) -} - -object EmitLinxCoreFrontendAluTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendAluTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-alu-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluMarkerRowsTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluMarkerRowsTraceTop.scala deleted file mode 100644 index 276c5c63..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluMarkerRowsTraceTop.scala +++ /dev/null @@ -1,38 +0,0 @@ -package linxcore.top - -import linxcore.common.CoreParams - -class LinxCoreFrontendFetchRfAluMarkerRowsTraceTop( - coreParams: CoreParams = CoreParams(), - decRenQueueDepth: Int = 4, - issueQueueDepth: Int = 4, - denseSlotQueueDepth: Int = 8, - storeDispatchQueueDepth: Int = 4, - mapQDepth: Int = 32, - gprMapQDepth: Int = 32, - archRegs: Int = 24, - physRegs: Int = 64) - extends LinxCoreFrontendFetchRfAluTraceTop( - coreParams = coreParams, - decRenQueueDepth = decRenQueueDepth, - issueQueueDepth = issueQueueDepth, - denseSlotQueueDepth = denseSlotQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - archRegs = archRegs, - physRegs = physRegs, - skipBlockMarkers = false, - useMarkerDecodeContext = true) - -object EmitLinxCoreFrontendFetchRfAluMarkerRowsTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchRfAluMarkerRowsTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 32, - gprMapQDepth = 256, - physRegs = 128), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-rf-alu-marker-rows-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop.scala deleted file mode 100644 index 20064651..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop.scala +++ /dev/null @@ -1,54 +0,0 @@ -package linxcore.top - -import linxcore.common.CoreParams - -/** - * Harness top that routes every ordinary scalar E1 load through LIQ admission. - * - * The inherited replay-LIQ path remains enabled for any later store-wakeup - * work, while `useReducedLiveLoadLiq` removes direct execute completion for - * first-pass loads. - */ -class LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop( - coreParams: CoreParams = CoreParams(), - decRenQueueDepth: Int = 4, - issueQueueDepth: Int = 4, - denseSlotQueueDepth: Int = 8, - storeDispatchQueueDepth: Int = 4, - storeExecBufferEntries: Int = 4, - mapQDepth: Int = 32, - gprMapQDepth: Int = 32, - archRegs: Int = 24, - physRegs: Int = 64, - useReducedStoreStaAddressExecBridge: Boolean = false) - extends LinxCoreFrontendFetchRfAluTraceTop( - coreParams = coreParams, - decRenQueueDepth = decRenQueueDepth, - issueQueueDepth = issueQueueDepth, - denseSlotQueueDepth = denseSlotQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - storeExecBufferEntries = storeExecBufferEntries, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - archRegs = archRegs, - physRegs = physRegs, - useReducedStoreDispatchStq = true, - useReducedStoreStaAddressExecBridge = useReducedStoreStaAddressExecBridge, - useReducedLoadReplayLiqAlloc = true, - useReducedLiveLoadLiq = true) - -object EmitLinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop extends App { - private val useEarlyStaAddressExec = - sys.env.get("LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS").exists(value => value.nonEmpty && value != "0") - - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 32, - gprMapQDepth = 256, - physRegs = 128, - useReducedStoreStaAddressExecBridge = useEarlyStaAddressExec), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-live-load-liq-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop.scala deleted file mode 100644 index 7d9ef564..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop.scala +++ /dev/null @@ -1,111 +0,0 @@ -package linxcore.top - -import linxcore.common.CoreParams - -class LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop( - coreParams: CoreParams = CoreParams(), - decRenQueueDepth: Int = 4, - issueQueueDepth: Int = 4, - denseSlotQueueDepth: Int = 8, - storeDispatchQueueDepth: Int = 4, - storeExecBufferEntries: Int = 4, - mapQDepth: Int = 32, - gprMapQDepth: Int = 32, - archRegs: Int = 24, - physRegs: Int = 64, - useReducedStoreStaAddressExecBridge: Boolean = false, - reducedStoreStdExecDelayCycles: Int = 0, - reducedReplayLiqW2CompletionDelayCycles: Int = 0, - reducedReplayLiqW2PostLretEnqueueHoldCycles: Int = 0, - reducedReplayLiqRetainedOwnerNoPhysicalProbe: Boolean = false, - reducedReplayLiqRetainedOwnerFallbackEmitProbe: Boolean = false, - reducedReplayLiqRetainedOwnerFallbackLiveProbe: Boolean = false, - reducedReplayLiqRetainedOwnerPhysicalSuppressProbe: Boolean = false, - reducedReplayLiqRetainedOwnerPhysicalSuppressPromote: Boolean = false, - reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask: Boolean = false) - extends LinxCoreFrontendFetchRfAluTraceTop( - coreParams = coreParams, - decRenQueueDepth = decRenQueueDepth, - issueQueueDepth = issueQueueDepth, - denseSlotQueueDepth = denseSlotQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - storeExecBufferEntries = storeExecBufferEntries, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - archRegs = archRegs, - physRegs = physRegs, - useReducedStoreDispatchStq = true, - useReducedStoreStaAddressExecBridge = useReducedStoreStaAddressExecBridge, - useReducedLoadReplayLiqAlloc = true, - reducedStoreStdExecDelayCycles = reducedStoreStdExecDelayCycles, - reducedReplayLiqW2CompletionDelayCycles = reducedReplayLiqW2CompletionDelayCycles, - reducedReplayLiqW2PostLretEnqueueHoldCycles = reducedReplayLiqW2PostLretEnqueueHoldCycles, - reducedReplayLiqRetainedOwnerNoPhysicalProbe = reducedReplayLiqRetainedOwnerNoPhysicalProbe, - reducedReplayLiqRetainedOwnerFallbackEmitProbe = reducedReplayLiqRetainedOwnerFallbackEmitProbe, - reducedReplayLiqRetainedOwnerFallbackLiveProbe = reducedReplayLiqRetainedOwnerFallbackLiveProbe, - reducedReplayLiqRetainedOwnerPhysicalSuppressProbe = reducedReplayLiqRetainedOwnerPhysicalSuppressProbe, - reducedReplayLiqRetainedOwnerPhysicalSuppressPromote = - reducedReplayLiqRetainedOwnerPhysicalSuppressPromote, - reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask = - reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask) - -object EmitLinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop extends App { - private def envInt(name: String): Int = - sys.env.get(name).filter(_.nonEmpty).map { value => - value.toIntOption.getOrElse { - throw new IllegalArgumentException(s"$name must be a nonnegative integer, got '$value'") - } - }.getOrElse(0) - - private val stdDelayCycles = envInt("LINXCORE_REPLAY_LIQ_STD_DELAY_CYCLES") - require(stdDelayCycles >= 0, "LINXCORE_REPLAY_LIQ_STD_DELAY_CYCLES must be nonnegative") - private val w2CompletionDelayCycles = envInt("LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES") - require( - w2CompletionDelayCycles >= 0, - "LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES must be nonnegative") - private val w2PostLretEnqueueHoldCycles = - envInt("LINXCORE_REPLAY_LIQ_W2_POST_LRET_ENQUEUE_HOLD_CYCLES") - require( - w2PostLretEnqueueHoldCycles >= 0, - "LINXCORE_REPLAY_LIQ_W2_POST_LRET_ENQUEUE_HOLD_CYCLES must be nonnegative") - private val useEarlyStaAddressExec = - sys.env.get("LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS").exists(value => value.nonEmpty && value != "0") - private val retainedOwnerNoPhysicalProbe = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_NO_PHYSICAL_PROBE").exists(value => - value.nonEmpty && value != "0") - private val retainedOwnerFallbackEmitProbe = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_FALLBACK_EMIT_PROBE").exists(value => - value.nonEmpty && value != "0") - private val retainedOwnerFallbackLiveProbe = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_FALLBACK_LIVE_PROBE").exists(value => - value.nonEmpty && value != "0") - private val retainedOwnerPhysicalSuppressProbe = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_PHYSICAL_SUPPRESS_PROBE").exists(value => - value.nonEmpty && value != "0") - private val retainedOwnerPhysicalSuppressPromote = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_PHYSICAL_SUPPRESS_PROMOTE").exists(value => - value.nonEmpty && value != "0") - private val retainedOwnerPhysicalSuppressLiveMask = - sys.env.get("LINXCORE_REPLAY_LIQ_RETAINED_OWNER_PHYSICAL_SUPPRESS_LIVE_MASK").exists(value => - value.nonEmpty && value != "0") - - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 32, - gprMapQDepth = 256, - physRegs = 128, - useReducedStoreStaAddressExecBridge = useEarlyStaAddressExec, - reducedStoreStdExecDelayCycles = stdDelayCycles, - reducedReplayLiqW2CompletionDelayCycles = w2CompletionDelayCycles, - reducedReplayLiqW2PostLretEnqueueHoldCycles = w2PostLretEnqueueHoldCycles, - reducedReplayLiqRetainedOwnerNoPhysicalProbe = retainedOwnerNoPhysicalProbe, - reducedReplayLiqRetainedOwnerFallbackEmitProbe = retainedOwnerFallbackEmitProbe, - reducedReplayLiqRetainedOwnerFallbackLiveProbe = retainedOwnerFallbackLiveProbe, - reducedReplayLiqRetainedOwnerPhysicalSuppressProbe = retainedOwnerPhysicalSuppressProbe, - reducedReplayLiqRetainedOwnerPhysicalSuppressPromote = retainedOwnerPhysicalSuppressPromote, - reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask = retainedOwnerPhysicalSuppressLiveMask), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-replay-liq-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreTraceTop.scala deleted file mode 100644 index 118c38fa..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluReducedStoreTraceTop.scala +++ /dev/null @@ -1,39 +0,0 @@ -package linxcore.top - -import linxcore.common.CoreParams - -class LinxCoreFrontendFetchRfAluReducedStoreTraceTop( - coreParams: CoreParams = CoreParams(), - decRenQueueDepth: Int = 4, - issueQueueDepth: Int = 4, - denseSlotQueueDepth: Int = 8, - storeDispatchQueueDepth: Int = 4, - storeExecBufferEntries: Int = 4, - mapQDepth: Int = 32, - gprMapQDepth: Int = 32, - archRegs: Int = 24, - physRegs: Int = 64) - extends LinxCoreFrontendFetchRfAluTraceTop( - coreParams = coreParams, - decRenQueueDepth = decRenQueueDepth, - issueQueueDepth = issueQueueDepth, - denseSlotQueueDepth = denseSlotQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - storeExecBufferEntries = storeExecBufferEntries, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - archRegs = archRegs, - physRegs = physRegs, - useReducedStoreDispatchStq = true) - -object EmitLinxCoreFrontendFetchRfAluReducedStoreTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchRfAluReducedStoreTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 32, - gprMapQDepth = 256, - physRegs = 128), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala deleted file mode 100644 index ca2dce7d..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala +++ /dev/null @@ -1,12903 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.{Cat, Decoupled, Fill, Mux1H, PriorityEncoder, Queue, UIntToOH, Valid, ValidIO, log2Ceil} - -import linxcore.backend.{DecodeRenameROBPath, ExecuteCompletionRetainer, ReducedRobCompletionArbiter} -import linxcore.commit.{CommitTraceParams, CommitTracePort, CommitTraceRow} -import linxcore.common.{BoundaryKind, CoreParams, DestinationKind, InterfaceParams, OperandClass, RenamedUop, ScalarLsuParams, ScalarSpAccess, ScalarSpTransaction} -import linxcore.execute.{ReducedScalarAluExecute, ReducedScalarWritebackArbiter, ReducedTemplateContextStack, ReducedTemplateSnapshotTable, ScalarGPRFile, ScalarIssueExternalControlFence, ScalarIssueFabric, ScalarSpOrderOwner} -import linxcore.frontend.{BackendBranchValidation, BackendBranchValidationContract, BranchValidationPoint, D1DecodedInstructionGroup, D1DecodedLaneQueue, F4DecodeWindow, F4DenseSlotQueue, F4Slot, FrontendFetchPacketSource, FrontendOpcodeDecodeTable, IfuInnerFlush, IfuInnerFlushReason, IfuPruneScope, BfuBodyCutArm, BfuBodyCutPredictor, BfuGeometryPredictionLatch, BfuLocalBodyWindow, BfuPendingRuntimeBodyEndCandidate, BfuRuntimeBodyEndOracle, BfuResolvedBodyEndOwner, BfuResolvedBodyEndPending, BfuResolvedBodyEndSource, BfuStaticGeometryProducer, SetcBranchValidationOwnership, SetcValidationKind} -import linxcore.lsu.{LoadInflightStatus, LoadLookupArbiter, LoadReplayBaseDataAlign, LoadReplayDestination, LoadReplayLaunchReadiness, LoadReplayReturnConsumerReady, LoadReplayReturnDataExtract, LoadReplayReturnFinalMetadataCandidate, LoadReplayReturnIexDataCandidate, LoadReplayReturnIexDrainPermit, LoadReplayReturnIexPipeInsertCandidate, LoadReplayReturnIexPipeOccupancy, LoadReplayReturnIexPipeOccupancyLiveControl, LoadReplayReturnLaneCompletionCandidate, LoadReplayReturnLretEntry, LoadReplayReturnLretPayload, LoadReplayReturnPipeBudget, LoadReplayReturnPipePermit, LoadReplayReturnPipeResidencyAdvanceCandidate, LoadReplayReturnPipeResidencyAdvanceLiveControl, LoadReplayReturnPipeResidencyCandidate, LoadReplayReturnPipeResidencyLiveControl, LoadReplayReturnPipeResidencySlot, LoadReplayReturnPipeSelect, LoadReplayReturnPipeW1AdvanceCandidate, LoadReplayReturnPipeW1Slot, LoadReplayReturnPipeW2AdvanceControl, LoadReplayReturnPipeW2AtomicPrereqSnapshot, LoadReplayReturnPipeW2AtomicRequestGate, LoadReplayReturnPipeW2ClearCommitGuard, LoadReplayReturnPipeW2ClearIntent, LoadReplayReturnPipeW2CommitRowCandidate, LoadReplayReturnPipeW2CommitRowTraceSource, LoadReplayReturnPipeW2CompletionCandidate, LoadReplayReturnPipeW2PostLretEnqueueHold, LoadReplayReturnPipeW2PromotionControl, LoadReplayReturnPipeW2RefillReady, LoadReplayReturnPipeW2ReplayRowClearRequest, LoadReplayReturnPipeW2ReplayRowLifecycleCommitPermit, LoadReplayReturnPipeW2ReplayRowLifecycleReady, LoadReplayReturnPipeW2ReplayRowLifecycleRequestControl, LoadReplayReturnPipeW2ResolveArbiterInput, LoadReplayReturnPipeW2ResolveFirePayload, LoadReplayReturnPipeW2ResolveRequest, LoadReplayReturnPipeW2ResolveSinkReady, LoadReplayReturnPipeW2RetireRecord, LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe, LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe, LoadReplayReturnPipeW2RobCompleteSource, LoadReplayReturnPipeW2RowFillEnableControl, LoadReplayReturnPipeW2SideEffectCompletionPermit, LoadReplayReturnPipeW2SideEffectFireComplete, LoadReplayReturnPipeW2SideEffectFireVector, LoadReplayReturnPipeW2SideEffectIssuePermit, LoadReplayReturnPipeW2SideEffectLiveControl, LoadReplayReturnPipeW2SideEffectPayloadPlan, LoadReplayReturnPipeW2SideEffectReady, LoadReplayReturnPipeW2SideEffectRequest, LoadReplayReturnPipeW2Slot, LoadReplayReturnPipeW2SlotReplacePlan, LoadReplayReturnPipeW2WakeupArbiterInput, LoadReplayReturnPipeW2WakeupFirePayload, LoadReplayReturnPipeW2WakeupRequest, LoadReplayReturnPipeW2WakeupSinkReady, LoadReplayReturnPipeW2WritebackArbiterInput, LoadReplayReturnPipeW2WritebackFirePayload, LoadReplayReturnPipeW2WritebackRequest, LoadReplayReturnPipeW2WritebackSinkReady, LoadReplayReturnPublishControl, LoadReplayReturnPublishReady, LoadReplayReturnPublishRequest, LoadReplayReturnReadiness, LoadReplayReturnReducedScalarShapeControl, LoadReplayReturnRobResolveDataCandidate, LoadReplayReturnSideEffectLiveControl, LoadReplayReturnSideEffectReady, LoadReplayReturnTimingStatsCandidate, LoadReplayReturnTloadCompletionCandidate, LoadReplayReturnWakeupCandidate, LoadReplayReturnWakeupSinkReady, LoadReplayReturnWritebackCandidate, LoadReplayReturnWritebackSinkReady, LoadReplaySourceReturnReadiness, LoadReplaySourceReturnScbLiveControl, LoadReplaySourceReturnStoreSnapshotPath, LoadResolveQueue, MDBConflictDetect, MDBConflictLoadEntry, MDBConflictStoreProbe, MDBQueueBus, MDBQueueFanout, MDBStoreWakeupEntry, ReducedLiveLoadLiqCapture, ReducedLoadReplayCompletionDrain, ReducedLoadReplayLiqAllocPath, ReducedLoadReplayRelaunchQueue, ReducedLoadWaitReplaySlot, ReducedStoreCommitFreeOwner, ReducedStoreExecResultBridge, ReducedStoreMemoryOverlay, ReducedStoreResidentForward, ReducedStoreStaAddressExecBridge, ResidentStoreForwardStoreSnapshot, ResidentStoreReplayWakeup, SCBRowBank, ScalarLrScReservationOwner, STQCommitDrain, STQCommitDrainRequest, STQStoreType, StoreDispatchExecResult} -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordCommitRowCandidate -import linxcore.lsu.ScalarLSULoadReturnQueueBank -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordRowFillEnableControl -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordBundleTransferPlan -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordDuplicateVector -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordModelOrderProof -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard -import linxcore.lsu.LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard -import linxcore.lsu.{LoadInflightRowMutationRequestBridge, LoadReplayResolvedRowHitRecord, LoadReplayRowMutationSourceMux} -import linxcore.lsu.MDBStoreProbeReplay -import linxcore.lsu.LoadReplayWakeSource -import linxcore.lsu.{ScalarLSUMDBPath, ScalarLSURecoveryBoundary} -import linxcore.recovery.{FlushBus, FullBidRecoveryBridge, ScalarRedirectRecoverySource} -import linxcore.rob.{ROBEntryStatus, ROBID, ROBRowCommitTraceLookupResult} -import linxcore.system.{ReducedServiceRequestOwner, ReducedServiceRequestPath, ReducedServiceRequestPayload, ReducedServiceRequestResponse} - -class MdbLookupWaitPlanBridgeDiagnostics extends Bundle { - val active = Bool() - val valid = Bool() - val sourceStoreIndexFits = Bool() - val blockedByDisabled = Bool() - val blockedByFlush = Bool() - val blockedByNoRequest = Bool() - val invalidStoreIndexOutOfRange = Bool() - val invalidConflictingStatusWrite = Bool() - val invalidWaitStoreWithoutWaitStatus = Bool() - val invalidReturnWithoutSplitSources = Bool() -} - -class LinxCoreFrontendFetchRfAluTraceTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val decRenQueueDepth: Int = 4, - val issueQueueDepth: Int = 4, - val denseSlotQueueDepth: Int = 8, - val storeDispatchQueueDepth: Int = 4, - val storeExecBufferEntries: Int = 4, - val scalarLsuParams: Option[ScalarLsuParams] = None, - val storeMemoryLineEntries: Int = 64, - val loadReturnQueueEntries: Int = 2, - val loadReturnPipeCount: Int = 1, - val scalarStidCount: Int = 1, - val mapQDepth: Int = 32, - val gprMapQDepth: Int = 32, - val physRegs: Int = 64, - val issueBankCount: Int = 2) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - private val sizeWidth = log2Ceil(p.robEntries + 1) - private val decRenCountWidth = log2Ceil(decRenQueueDepth + 1) - private val issueCountWidth = log2Ceil(issueQueueDepth + 1) - private val issueBankCountWidth = log2Ceil(issueQueueDepth / issueBankCount + 1) - private val denseSlotQueueCountWidth = log2Ceil(denseSlotQueueDepth + 1) - private val denseSlotQueueSlotWidth = math.max(1, log2Ceil(p.decodeWidth)) - private val storeDispatchCountWidth = log2Ceil(storeDispatchQueueDepth + 1) - private val storeExecBufferCountWidth = log2Ceil(storeExecBufferEntries + 1) - private val physicalStoreStqEntries = scalarLsuParams.map(_.stqEntries).getOrElse(p.robEntries) - private val physicalStoreCommitQueueEntries = - scalarLsuParams.map(_.commitQueueEntries).getOrElse(physicalStoreStqEntries) - private val physicalStoreCommitIssueWidth = - scalarLsuParams.map(_.commitIssueWidth).getOrElse(if (physicalStoreStqEntries >= 4) 2 else 1) - private val physicalStoreScbEntries = scalarLsuParams.map(_.scbEntries).getOrElse(physicalStoreStqEntries) - private val storeStqPtrWidth = log2Ceil(physicalStoreStqEntries) - private val storeStqCountWidth = log2Ceil(physicalStoreStqEntries + 1) - private val storeCommitQueueCountWidth = log2Ceil(physicalStoreCommitQueueEntries + 1) - private val storeScbEntryCountWidth = log2Ceil(physicalStoreScbEntries + 1) - private val storeScbRequestCount = physicalStoreCommitIssueWidth * 2 - private val storeMemoryCommitBypassRequestCount = traceParams.commitWidth * 2 - private val storeMemoryRequestCount = storeScbRequestCount + storeMemoryCommitBypassRequestCount - private val storeScbRequestCountWidth = log2Ceil(storeScbRequestCount + 1) - private val storeMemoryLineCountWidth = log2Ceil(storeMemoryLineEntries + 1) - private val loadReplayRelaunchQueueCountWidth = log2Ceil(2 + 1) - private val loadReplayLretSinkCountWidth = - log2Ceil(loadReturnQueueEntries * loadReturnPipeCount * scalarStidCount + 1) - private val sourceReturnStoreSnapshotQueueDepth = 2 - private val sourceReturnStoreSnapshotQueueCountWidth = log2Ceil(sourceReturnStoreSnapshotQueueDepth + 1) - private val mdbConflictOrdinalWidth = log2Ceil(p.robEntries * 2) - private val gprFreeWidth = log2Ceil(physRegs + 1) - private val gprMapQFreeWidth = log2Ceil(gprMapQDepth + 1) - private val tuCountWidth = log2Ceil(mapQDepth + 1) - - val startValid = Input(Bool()) - val startPc = Input(UInt(p.pcWidth.W)) - val restartValid = Input(Bool()) - val restartPc = Input(UInt(p.pcWidth.W)) - val bfuBodyValid = Input(Bool()) - val bfuHeaderPc = Input(UInt(p.pcWidth.W)) - val bfuHSizeBytes = Input(UInt(p.pcWidth.W)) - val bfuBSizeBytes = Input(UInt(p.pcWidth.W)) - val frontendFlushValid = Input(Bool()) - val peId = Input(UInt(p.peIdWidth.W)) - val threadId = Input(UInt(p.threadIdWidth.W)) - - val fetchReqReady = Input(Bool()) - val fetchRespValid = Input(Bool()) - val fetchRespWindow = Input(UInt(p.windowWidth.W)) - - val productionD1 = Flipped(Decoupled(new D1DecodedInstructionGroup(p))) - val productionIfuFlush = Input(new IfuInnerFlush(p)) - val backendValidation = Decoupled(new BackendBranchValidation(p)) - - val rfInitValid = Input(Bool()) - val rfInitArchTag = Input(UInt(p.archRegWidth.W)) - val rfInitData = Input(UInt(p.immWidth.W)) - val deallocReady = Input(Bool()) - val loadLookupData = Input(UInt(p.immWidth.W)) - val loadPairFirstLookupData = Input(UInt(p.immWidth.W)) - - val fetchReqValid = Output(Bool()) - val fetchReqPc = Output(UInt(p.pcWidth.W)) - val fetchRespReady = Output(Bool()) - val sourceActive = Output(Bool()) - val sourceWaitingResponse = Output(Bool()) - val sourcePacketValid = Output(Bool()) - val sourceReqFire = Output(Bool()) - val sourceRespFire = Output(Bool()) - val sourceOutFire = Output(Bool()) - val sourceAdvanceZero = Output(Bool()) - val sourceAdvanceBytes = Output(UInt(4.W)) - val sourceRestartValid = Output(Bool()) - val sourceRestartPc = Output(UInt(p.pcWidth.W)) - val sourceCurrentPc = Output(UInt(p.pcWidth.W)) - val sourceIssuedPc = Output(UInt(p.pcWidth.W)) - val sourceNextPktUid = Output(UInt(p.uopUidWidth.W)) - val debugBlockMarkerStopRedirectValid = Output(Bool()) - val debugBlockMarkerStopRedirectPc = Output(UInt(p.pcWidth.W)) - val debugMarkerRedirectFire = Output(Bool()) - val debugMarkerRedirectPending = Output(Bool()) - val debugMarkerRedirectPc = Output(UInt(p.pcWidth.W)) - val debugBodyCutAdvanceBytes = Output(UInt(4.W)) - val debugF4TotalLenBytes = Output(UInt(4.W)) - val debugReadinessBits = Output(UInt(8.W)) - val debugFretConditionBits = Output(UInt(8.W)) - val debugContinuationBits = Output(UInt(8.W)) - val reducedBodyCutActive = Output(Bool()) - val reducedBodyCutFire = Output(Bool()) - val reducedBodyCutAdvanceBytes = Output(UInt(4.W)) - val bfuStaticGeometryValid = Output(Bool()) - val bfuStaticHeaderActive = Output(Bool()) - val bfuStaticLearnedFire = Output(Bool()) - val bfuStaticResolvedLearnedFire = Output(Bool()) - val bfuResolvedBodyEndAccepted = Output(Bool()) - val bfuResolvedBodyEndHeaderMismatch = Output(Bool()) - val bfuResolvedBodyEndInactiveDrop = Output(Bool()) - val bfuResolvedBodyEndFlushDrop = Output(Bool()) - val bfuResolvedBodyEndUnderflow = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimeSelected = Output(Bool()) - val bfuResolvedBodyEndSourceReplaySelected = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimeReplayComparable = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimeReplayMatch = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimeReplayMismatch = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimeFeedbackFire = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePending = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePendingConsumeFire = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePendingDropMismatch = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePendingCandidateComparable = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePendingCandidateMatch = Output(Bool()) - val bfuResolvedBodyEndSourceRuntimePendingCandidateMismatch = Output(Bool()) - val bfuPendingRuntimeCandidateValid = Output(Bool()) - val bfuPendingRuntimeCandidatePendingWithoutActiveHeader = Output(Bool()) - val bfuPendingRuntimeCandidateActiveHeaderMismatch = Output(Bool()) - val bfuPendingRuntimeCandidateReplayComparable = Output(Bool()) - val bfuPendingRuntimeCandidateReplayMatch = Output(Bool()) - val bfuPendingRuntimeCandidateReplayMismatch = Output(Bool()) - val bfuRuntimeBodyEndOraclePending = Output(Bool()) - val bfuRuntimeBodyEndOracleCaptureFire = Output(Bool()) - val bfuRuntimeBodyEndOracleReplayComparable = Output(Bool()) - val bfuRuntimeBodyEndOracleReplayMatch = Output(Bool()) - val bfuRuntimeBodyEndOracleReplayMismatch = Output(Bool()) - val bfuRuntimeBodyEndOracleOverwritePending = Output(Bool()) - val bfuStaticExternalComparable = Output(Bool()) - val bfuStaticExternalMatch = Output(Bool()) - val bfuStaticExternalMismatch = Output(Bool()) - val bfuStaticExternalHeaderMismatch = Output(Bool()) - val bfuStaticExternalHSizeMismatch = Output(Bool()) - val bfuStaticExternalBSizeMismatch = Output(Bool()) - val bfuBodyCutArmComparable = Output(Bool()) - val bfuBodyCutArmAccepted = Output(Bool()) - val bfuBodyCutArmMismatch = Output(Bool()) - val bfuBodyCutArmHeaderMismatch = Output(Bool()) - val bfuBodyCutArmHSizeMismatch = Output(Bool()) - val bfuBodyCutArmBSizeMismatch = Output(Bool()) - val bfuLocalBodyWindowActive = Output(Bool()) - val bfuLocalBodyWindowArmFire = Output(Bool()) - val bfuLocalBodyWindowReleaseFire = Output(Bool()) - val bfuLocalBodyWindowArmSlot = Output(UInt(log2Ceil(p.decodeWidth).W)) - - val f4ValidMask = Output(UInt(p.decodeWidth.W)) - val f4SlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val denseSlotQueueInFire = Output(Bool()) - val denseSlotQueueOutFire = Output(Bool()) - val denseSlotQueueInSlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val denseSlotQueueCount = Output(UInt(denseSlotQueueCountWidth.W)) - val denseSlotQueueHeadSlot = Output(UInt(denseSlotQueueSlotWidth.W)) - val denseSlotQueueFull = Output(Bool()) - val denseSlotQueueEmpty = Output(Bool()) - val admittedMarkerDrainBarrier = Output(Bool()) - val decodeReady = Output(Bool()) - val decodeQueuePushReady = Output(Bool()) - val decodeAllocReady = Output(Bool()) - val decodeGprReservationReady = Output(Bool()) - val decodeSelectedClosesActiveRedirect = Output(Bool()) - val decodeSelectedNeedsGprReservation = Output(Bool()) - val gprReservationCount = Output(UInt(log2Ceil(decRenQueueDepth * 2 + 1).W)) - val gprReservationNeed = Output(UInt(log2Ceil(decRenQueueDepth * 2 + 1).W)) - val selectedValid = Output(Bool()) - val selectedRobValue = Output(UInt(ptrWidth.W)) - val selectedBlockBid = Output(UInt(p.blockBidWidth.W)) - val blockMarkerSkipFire = Output(Bool()) - val blockMarkerSkipValid = Output(Bool()) - val blockMarkerMixedPacket = Output(Bool()) - val blockMarkerBoundary = Output(Bool()) - val blockMarkerStop = Output(Bool()) - val blockMarkerPc = Output(UInt(p.pcWidth.W)) - val blockMarkerInsn = Output(UInt(p.insnWidth.W)) - val blockMarkerLen = Output(UInt(4.W)) - val blockMarkerTarget = Output(UInt(p.pcWidth.W)) - val blockMarkerAllocReady = Output(Bool()) - val blockMarkerLifecycleConflict = Output(Bool()) - val blockMarkerAllocFire = Output(Bool()) - val blockMarkerAllocBid = Output(UInt(p.blockBidWidth.W)) - val blockMarkerActiveValid = Output(Bool()) - val blockMarkerActiveBid = Output(UInt(p.blockBidWidth.W)) - val blockMarkerActiveTarget = Output(UInt(p.pcWidth.W)) - val blockMarkerStopRedirectValid = Output(Bool()) - val blockMarkerStopRedirectPc = Output(UInt(p.pcWidth.W)) - val robMarkerRetireSourceLifecycleReady = Output(Bool()) - val robMarkerRetireSourceLifecycleFire = Output(Bool()) - val robMarkerRetireSourceLifecycleBoundaryFire = Output(Bool()) - val robMarkerRetireSourceLifecycleStopFire = Output(Bool()) - val robMarkerRetireSourceValid = Output(Bool()) - val robMarkerRetireSourceBoundary = Output(Bool()) - val robMarkerRetireSourceStop = Output(Bool()) - val robMarkerRetireSourceLast = Output(Bool()) - val robMarkerRetireSourceBidValid = Output(Bool()) - val robMarkerRetireSourceBidWrap = Output(Bool()) - val robMarkerRetireSourceBidValue = Output(UInt(p.robIndexWidth.W)) - val robMarkerRetireSourceRidValid = Output(Bool()) - val robMarkerRetireSourceRidWrap = Output(Bool()) - val robMarkerRetireSourceRidValue = Output(UInt(p.robIndexWidth.W)) - val robMarkerRetireSourceStid = Output(UInt(p.threadIdWidth.W)) - val robMarkerRetireSourceBlockBidValid = Output(Bool()) - val robMarkerRetireSourceBlockBid = Output(UInt(p.blockBidWidth.W)) - val robMarkerRetireSourceBoundaryTarget = Output(UInt(p.pcWidth.W)) - val decRenPushFire = Output(Bool()) - val decRenPopFire = Output(Bool()) - val decRenCount = Output(UInt(decRenCountWidth.W)) - val decRenValid = Output(Bool()) - val decRenHeadPc = Output(UInt(p.pcWidth.W)) - val decRenHeadRidValid = Output(Bool()) - val decRenHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val renamedOutValid = Output(Bool()) - val renamedAccepted = Output(Bool()) - val executeAccepted = Output(Bool()) - val executeBusy = Output(Bool()) - val executeCompleteValid = Output(Bool()) - val executeCompleteRobValue = Output(UInt(ptrWidth.W)) - val executeLoadWaitHold = Output(Bool()) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(p.immWidth.W)) - val loadPairFirstLookupValid = Output(Bool()) - val loadPairFirstLookupAddr = Output(UInt(p.immWidth.W)) - val loadLookupPc = Output(UInt(p.pcWidth.W)) - val loadLookupDstValid = Output(Bool()) - val loadLookupDstKind = Output(UInt(2.W)) - val loadLookupDstArchTag = Output(UInt(p.archRegWidth.W)) - val loadLookupDstRelTag = Output(UInt(p.archRegWidth.W)) - val loadLookupDstPhysTag = Output(UInt(p.physRegWidth.W)) - val loadLookupDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val loadLookupExecuteGranted = Output(Bool()) - val loadLookupReplayGranted = Output(Bool()) - val reducedStoreDispatchEnabled = Output(Bool()) - val reducedStoreExecCompleteStoreValid = Output(Bool()) - val reducedStoreExecCaptureFire = Output(Bool()) - val reducedStoreExecCaptureBlocked = Output(Bool()) - val reducedStoreExecCaptureDuplicate = Output(Bool()) - val reducedStoreExecStaMatch = Output(Bool()) - val reducedStoreExecStdMatch = Output(Bool()) - val reducedStoreExecValidMask = Output(UInt(storeExecBufferEntries.W)) - val reducedStoreExecBufferCount = Output(UInt(storeExecBufferCountWidth.W)) - val reducedStoreStaExecValid = Output(Bool()) - val reducedStoreStdExecValid = Output(Bool()) - val reducedStoreCommitStoreSeen = Output(Bool()) - val reducedStoreCommitStoreMatched = Output(Bool()) - val reducedStoreCommitStoreUnmatched = Output(Bool()) - val reducedStoreCommitReleasedByEarlySafe = Output(Bool()) - val reducedStoreCommitMatchMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitEarlySafeMatchMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitPendingIdentityMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitPendingEarlySafeMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitResidentEarlySafeMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitPendingMarkMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitPendingFreeMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitPendingMarkCount = Output(UInt(storeStqCountWidth.W)) - val reducedStoreCommitPendingFreeCount = Output(UInt(storeStqCountWidth.W)) - val reducedStoreCommitMarkValid = Output(Bool()) - val reducedStoreCommitMarkIndex = Output(UInt(storeStqPtrWidth.W)) - val reducedStoreCommitMarkAccepted = Output(Bool()) - val reducedStoreCommitMarkIgnored = Output(Bool()) - val reducedStoreCommitMarkBlocked = Output(Bool()) - val reducedStoreCommitFreeValid = Output(Bool()) - val reducedStoreCommitFreeIndex = Output(UInt(storeStqPtrWidth.W)) - val reducedStoreCommitFreeAccepted = Output(Bool()) - val reducedStoreCommitFreeIgnored = Output(Bool()) - val reducedStoreCommitFreeAcceptedMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitFreeIgnoredMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreCommitFreeCount = Output(UInt(storeStqCountWidth.W)) - val reducedStoreCommitFreeBlocked = Output(Bool()) - val reducedStoreDrainEnqueueAccepted = Output(Bool()) - val reducedStoreDrainEnqueueDuplicate = Output(Bool()) - val reducedStoreDrainIssueValidMask = Output(UInt(physicalStoreCommitIssueWidth.W)) - val reducedStoreDrainIssueCount = Output(UInt(log2Ceil(physicalStoreCommitIssueWidth + 1).W)) - val reducedStoreDrainEarlyFreeMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreDrainQueueCount = Output(UInt(storeCommitQueueCountWidth.W)) - val reducedStoreDrainEmpty = Output(Bool()) - val reducedStoreDrainOrderError = Output(Bool()) - val reducedStoreScbReadyForDrain = Output(Bool()) - val reducedStoreScbAcceptedMask = Output(UInt(storeScbRequestCount.W)) - val reducedStoreScbStalledMask = Output(UInt(storeScbRequestCount.W)) - val reducedStoreScbCommitFreeMaskValid = Output(Bool()) - val reducedStoreScbCommitFreeMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreScbCommitFreeCount = Output(UInt(storeScbRequestCountWidth.W)) - val reducedStoreScbValidMask = Output(UInt(physicalStoreScbEntries.W)) - val reducedStoreScbEntryCount = Output(UInt(storeScbEntryCountWidth.W)) - val reducedStoreMemoryValidMask = Output(UInt(storeMemoryLineEntries.W)) - val reducedStoreMemoryLineCount = Output(UInt(storeMemoryLineCountWidth.W)) - val reducedStoreMemoryLoadForwardMask = Output(UInt(8.W)) - val reducedStoreMemoryStoreDroppedMask = Output(UInt(storeMemoryRequestCount.W)) - val reducedStoreCommitBypassValidMask = Output(UInt(traceParams.commitWidth.W)) - val reducedStoreCommitBypassBid = Output(Vec(traceParams.commitWidth, new ROBID(p.robEntries))) - val reducedStoreCommitBypassLsId = Output(Vec(traceParams.commitWidth, UInt(p.lsidWidth.W))) - val reducedStoreResidentForwardMask = Output(UInt(8.W)) - val reducedStoreResidentWaitMask = Output(UInt(8.W)) - val reducedStoreResidentEligibleMask = Output(UInt(physicalStoreStqEntries.W)) - val reducedStoreResidentReadyForward = Output(Bool()) - val reducedStoreResidentWaitBlocked = Output(Bool()) - val reducedStoreResidentWaitStoreValid = Output(Bool()) - val reducedStoreResidentWaitStoreIndex = Output(UInt(storeStqPtrWidth.W)) - val reducedStoreResidentWaitStoreBidValid = Output(Bool()) - val reducedStoreResidentWaitStoreBidWrap = Output(Bool()) - val reducedStoreResidentWaitStoreBidValue = Output(UInt(ptrWidth.W)) - val reducedStoreResidentWaitStoreLsIdValid = Output(Bool()) - val reducedStoreResidentWaitStoreLsIdWrap = Output(Bool()) - val reducedStoreResidentWaitStoreLsIdValue = Output(UInt(ptrWidth.W)) - val reducedStoreResidentWaitStorePc = Output(UInt(p.pcWidth.W)) - val reducedStoreResidentLoadCrossesLine = Output(Bool()) - val reducedStoreResidentReplayWakeValid = Output(Bool()) - val reducedStoreResidentReplayWakeSelected = Output(Bool()) - val reducedStoreResidentReplayWakeIdentityMatch = Output(Bool()) - val reducedStoreResidentReplayWakeReady = Output(Bool()) - val reducedStoreResidentReplayWakeCrossesLine = Output(Bool()) - val reducedStoreResidentReplayWakeLineAddr = Output(UInt(p.immWidth.W)) - val reducedStoreResidentReplayWakeByteMask = Output(UInt(64.W)) - val reducedLoadWaitReplayActive = Output(Bool()) - val reducedLoadWaitReplayCaptureAccepted = Output(Bool()) - val reducedLoadWaitReplayClearValid = Output(Bool()) - val reducedLoadWaitReplayStoredWaitValid = Output(Bool()) - val reducedLoadWaitReplayStoredWaitPc = Output(UInt(p.pcWidth.W)) - val reducedLoadWaitReplayRelaunchValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchPc = Output(UInt(p.pcWidth.W)) - val reducedLoadWaitReplayRelaunchAddr = Output(UInt(p.immWidth.W)) - val reducedLoadWaitReplayRelaunchSize = Output(UInt(7.W)) - val reducedLoadWaitReplayRelaunchDstValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchDstKind = Output(UInt(2.W)) - val reducedLoadWaitReplayRelaunchDstArchTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadWaitReplayRelaunchDstRelTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadWaitReplayRelaunchDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadWaitReplayRelaunchDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadWaitReplayRelaunchBidValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchBidWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadWaitReplayRelaunchGidValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchGidWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadWaitReplayRelaunchRidValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchRidWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadWaitReplayRelaunchLsIdValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchLsIdWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadWaitReplayRelaunchYoungestStoreIdValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchYoungestStoreIdWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchYoungestStoreIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadWaitReplayRelaunchYoungestStoreLsIdValid = Output(Bool()) - val reducedLoadWaitReplayRelaunchYoungestStoreLsIdWrap = Output(Bool()) - val reducedLoadWaitReplayRelaunchYoungestStoreLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueEnqueueReady = Output(Bool()) - val reducedLoadReplayQueueEnqueueAccepted = Output(Bool()) - val reducedLoadReplayQueueEnqueueDropped = Output(Bool()) - val reducedLoadReplayQueueOutValid = Output(Bool()) - val reducedLoadReplayQueueOutFire = Output(Bool()) - val reducedLoadReplayQueuePending = Output(Bool()) - val reducedLoadReplayQueueFull = Output(Bool()) - val reducedLoadReplayQueueCount = Output(UInt(loadReplayRelaunchQueueCountWidth.W)) - val reducedLoadReplayQueueOutPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayQueueOutAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayQueueOutSize = Output(UInt(7.W)) - val reducedLoadReplayQueueOutReturnSignExtend = Output(Bool()) - val reducedLoadReplayQueueOutDstValid = Output(Bool()) - val reducedLoadReplayQueueOutDstKind = Output(UInt(2.W)) - val reducedLoadReplayQueueOutDstArchTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayQueueOutDstRelTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayQueueOutDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayQueueOutDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayQueueOutBidValid = Output(Bool()) - val reducedLoadReplayQueueOutBidWrap = Output(Bool()) - val reducedLoadReplayQueueOutBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueOutGidValid = Output(Bool()) - val reducedLoadReplayQueueOutGidWrap = Output(Bool()) - val reducedLoadReplayQueueOutGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueOutRidValid = Output(Bool()) - val reducedLoadReplayQueueOutRidWrap = Output(Bool()) - val reducedLoadReplayQueueOutRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueOutLsIdValid = Output(Bool()) - val reducedLoadReplayQueueOutLsIdWrap = Output(Bool()) - val reducedLoadReplayQueueOutLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueOutYoungestStoreIdValid = Output(Bool()) - val reducedLoadReplayQueueOutYoungestStoreIdWrap = Output(Bool()) - val reducedLoadReplayQueueOutYoungestStoreIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayQueueOutYoungestStoreLsIdValid = Output(Bool()) - val reducedLoadReplayQueueOutYoungestStoreLsIdWrap = Output(Bool()) - val reducedLoadReplayQueueOutYoungestStoreLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayDrainConsumeReady = Output(Bool()) - val reducedLoadReplayDrainMatchValid = Output(Bool()) - val reducedLoadReplayDrainMismatch = Output(Bool()) - val reducedLoadReplayDrainPcMismatch = Output(Bool()) - val reducedLoadReplayDrainAddrMismatch = Output(Bool()) - val reducedLoadReplayDrainSizeMismatch = Output(Bool()) - val reducedLoadReplayDrainBidMismatch = Output(Bool()) - val reducedLoadReplayDrainGidMismatch = Output(Bool()) - val reducedLoadReplayDrainRidMismatch = Output(Bool()) - val reducedLoadReplayDrainLsIdMismatch = Output(Bool()) - val reducedLoadReplayLiqAllocEnabled = Output(Bool()) - val reducedLoadReplayLiqAllocConsumeReady = Output(Bool()) - val reducedLoadReplayLiqAllocCandidateUsable = Output(Bool()) - val reducedLoadReplayLiqAllocBlockedByAlloc = Output(Bool()) - val reducedLoadReplayLiqAllocValid = Output(Bool()) - val reducedLoadReplayLiqAllocReady = Output(Bool()) - val reducedLoadReplayLiqAllocAccepted = Output(Bool()) - val reducedLoadReplayLiqAllocIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqAllocLoadIdValid = Output(Bool()) - val reducedLoadReplayLiqAllocLoadIdWrap = Output(Bool()) - val reducedLoadReplayLiqAllocLoadIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqOccupiedMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqWaitMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqWaitStoreMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeValid = Output(Bool()) - val reducedLoadReplayLiqReplayWakeFlush = Output(Bool()) - val reducedLoadReplayLiqReplayWakeWaitStoreCandidateMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeBidMatchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeLsIdMatchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakePcMatchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeFullMatchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeStoreUnit = Output(Bool()) - val reducedLoadReplayLiqReplayWakeStoreUnitFullMatchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReplayWakeWaitStoreClearMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchWaitMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchWaitStoreBlockedMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchTileBlockedMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchUnblockedWaitMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchRequestCompleteMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchDataHitMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchCandidateMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqLaunchValid = Output(Bool()) - val reducedLoadReplayLiqLaunchIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchDriveValid = Output(Bool()) - val reducedLoadReplayLiqLaunchReady = Output(Bool()) - val reducedLoadReplayLiqLaunchAccepted = Output(Bool()) - val reducedLoadReplayLiqLaunchCandidateCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayLiqReturnCompleteRepickMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteSourceReturnedMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteDataCompleteMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteRequestCompleteMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteCandidateMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqReturnCompleteValid = Output(Bool()) - val reducedLoadReplayLiqReturnCompleteIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqReturnCompleteCandidateCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayLiqLaunchSelectedLoadIdValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedLoadIdWrap = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedLoadIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchSelectedBidValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedBidWrap = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchSelectedGidValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedGidWrap = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchSelectedRidValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedRidWrap = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchSelectedLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedLoadLsIdWrap = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLaunchSelectedPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLaunchSelectedAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLaunchSelectedSize = Output(UInt(7.W)) - val reducedLoadReplayLiqLaunchSelectedReturnSignExtend = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedDstValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedDstKind = Output(UInt(2.W)) - val reducedLoadReplayLiqLaunchSelectedDstArchTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLaunchSelectedDstRelTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLaunchSelectedDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLaunchSelectedDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLaunchSelectedRequestByteMask = Output(UInt(64.W)) - val reducedLoadReplayLiqLaunchSelectedSpecWakeup = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedStackValid = Output(Bool()) - val reducedLoadReplayLiqBaseLookupValid = Output(Bool()) - val reducedLoadReplayLiqBaseLookupCrossesLine = Output(Bool()) - val reducedLoadReplayLiqBaseLookupPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqBaseLookupAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqBaseLookupSize = Output(UInt(7.W)) - val reducedLoadReplayLiqBaseLookupRequestByteMask = Output(UInt(64.W)) - val reducedLoadReplayLiqBaseLineValidMask = Output(UInt(64.W)) - val reducedLoadReplayLiqBaseDataReturned = Output(Bool()) - val reducedLoadReplayLiqBaseLookupGranted = Output(Bool()) - val reducedLoadReplayLiqBaseLookupBlockedByExecute = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBaseDataReady = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessSourcesReturned = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessReady = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessEnable = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByBaseData = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByScb = Output(Bool()) - val reducedLoadReplayLiqLaunchReadinessBlockedByReturn = Output(Bool()) - val reducedLoadReplayLiqSourceReturnCandidateValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveRequestActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLegacyReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByLegacySnapshot = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedBySnapshot = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestEnable = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponsePortBlocked = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByPolicyDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByNoLaunch = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRowMutationDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRequestQueue = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByAcceptedToken = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByNoRequest = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRowMutationDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRawSink = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByQueueFull = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByRawResponse = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestEnable = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestQueueCanAccept = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveSinkReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestControlBlockedByToken = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCanAccept = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenResidentValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureAccepted = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenBlockedByOutstanding = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoIssue = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoSelected = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByStaleRow = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadConsumed = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePending = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueFull = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueEmpty = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueCount = - Output(UInt(sourceReturnStoreSnapshotQueueCountWidth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByFull = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneMask = - Output(UInt(sourceReturnStoreSnapshotQueueDepth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneCount = - Output(UInt(sourceReturnStoreSnapshotQueueCountWidth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByPreciseFlush = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkAccepted = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkResponseValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByNoRequest = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByRawSink = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByResponse = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEnqueueAccepted = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadConsumed = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePending = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueFull = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEmpty = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueCount = - Output(UInt(sourceReturnStoreSnapshotQueueCountWidth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByFull = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneMask = - Output(UInt(sourceReturnStoreSnapshotQueueDepth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneCount = - Output(UInt(sourceReturnStoreSnapshotQueueCountWidth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByPreciseFlush = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainDequeueReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainOrderedConsumed = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainStaleDropped = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoHead = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoAction = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLookupQueryValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLookupWaitStoreValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLookupRawDataValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLookupResponseDataValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotLookupStoreBypassComplete = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceRequestValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceQueryActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceResponseAccepted = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotRequired = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceWaitStoreReplay = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoQuery = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoResponse = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByWaitStore = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidResponseWithoutQuery = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidDataWithWaitStore = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueRequestActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByNoLaunch = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyTargetMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyWaitStore = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataMerge = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataNoMerge = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyMergedRequestComplete = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoOrderedResponse = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNotRepick = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByWaitStore = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoData = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidOrderedWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataWithWaitStore = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataValidWithoutRawData = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidSuppressedDataWithoutWait = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanRewait = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataMerge = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataNoMerge = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanSetWaitStatus = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanKeepRepickStatus = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanClearReturnState = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanLineWrite = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanWaitStoreWrite = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextDataComplete = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextScbReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStqReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStoreSourceReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanBlockedByNoApply = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidApplyWithoutStqReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqReturnedWithoutApply = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqApplyWithoutScb = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateTargetMask = - Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationTargetReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetMask = - Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetIndex = - Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByNoTarget = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationInvalidMultiTarget = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch = Output(Bool()) - val reducedLoadReplayLiqSourceReturnStoreSourceReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbSourceReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnSourceReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqSourceReturnBlockedByBaseData = Output(Bool()) - val reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot = Output(Bool()) - val reducedLoadReplayLiqSourceReturnBlockedByScb = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveRequestActive = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLivePending = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveReturned = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveBlockedByNoPending = Output(Bool()) - val reducedLoadReplayLiqSourceReturnScbLiveBlockedByScbReturn = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedSourceTraceValid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedSource0Valid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedSource0Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLaunchSelectedSource0Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqLaunchSelectedSource1Valid = Output(Bool()) - val reducedLoadReplayLiqLaunchSelectedSource1Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLaunchSelectedSource1Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqReturnConsumerCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerLretSinkReady = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerWakeupSinkReady = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerWakeupRequired = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerReady = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerBlockedBySources = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerBlockedByLretSink = Output(Bool()) - val reducedLoadReplayLiqReturnConsumerBlockedByWakeupSink = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkArmed = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkReady = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkBlockedByNoWriteback = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqReturnWritebackSinkBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkArmed = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkReady = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkBlockedByNoWakeup = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqReturnWakeupSinkBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnSideEffectLiveCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnSideEffectLiveRequiredMask = Output(UInt(3.W)) - val reducedLoadReplayLiqReturnSideEffectLiveEnableMask = Output(UInt(3.W)) - val reducedLoadReplayLiqReturnSideEffectLiveBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnSideEffectLiveBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqReturnSideEffectLiveBlockedByNoPayload = Output(Bool()) - val reducedLoadReplayLiqReturnSideEffectLiveBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetEnable = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetConsumerReady = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetAvailable = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetBlockedBySources = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetBlockedByBudgetDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBudgetBlockedByConsumer = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitPipeBudgetAvailable = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitMask = Output(UInt(1.W)) - val reducedLoadReplayLiqReturnPipePermitValid = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitBlockedBySources = Output(Bool()) - val reducedLoadReplayLiqReturnPipePermitBlockedByPipeBudget = Output(Bool()) - val reducedLoadReplayLiqReturnPipeAvailableMask = Output(UInt(1.W)) - val reducedLoadReplayLiqReturnPipeCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnPipeAvailable = Output(Bool()) - val reducedLoadReplayLiqReturnPipeSelectedPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqReturnPipeBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBlockedBySources = Output(Bool()) - val reducedLoadReplayLiqReturnPipeBlockedByNoPipe = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessReady = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessSelectedPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqReturnReadinessBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessBlockedBySources = Output(Bool()) - val reducedLoadReplayLiqReturnReadinessBlockedByReturnPipe = Output(Bool()) - val reducedLoadReplayLiqReturnDataCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnDataRequestByteMask = Output(UInt(64.W)) - val reducedLoadReplayLiqReturnDataBytesComplete = Output(Bool()) - val reducedLoadReplayLiqReturnDataCrossLine = Output(Bool()) - val reducedLoadReplayLiqReturnDataSizeSupported = Output(Bool()) - val reducedLoadReplayLiqReturnDataRawData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqReturnData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqReturnDataValid = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByZeroSize = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByUnsupportedSize = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByCrossLine = Output(Bool()) - val reducedLoadReplayLiqReturnDataBlockedByIncompleteBytes = Output(Bool()) - val reducedLoadReplayLiqReturnPublishCandidateValid = Output(Bool()) - val reducedLoadReplayLiqReturnPublishDataReady = Output(Bool()) - val reducedLoadReplayLiqReturnPublishReady = Output(Bool()) - val reducedLoadReplayLiqReturnPublishBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqReturnPublishBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqReturnPublishBlockedByData = Output(Bool()) - val reducedLoadReplayLiqReturnPublishBlockedByConsumer = Output(Bool()) - val reducedLoadReplayLiqLretPayloadCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPayloadGidValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadGidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPayloadGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPayloadRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPayloadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPayloadLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadLoadLsIdWrap = Output(Bool()) - val reducedLoadReplayLiqLretPayloadLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPayloadPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLretPayloadAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPayloadSize = Output(UInt(7.W)) - val reducedLoadReplayLiqLretPayloadDstValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadDstKind = Output(UInt(2.W)) - val reducedLoadReplayLiqLretPayloadDstArchTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLretPayloadDstRelTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLretPayloadDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPayloadDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPayloadSourceTraceValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadSource0Valid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadSource0Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLretPayloadSource0Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqLretPayloadSource1Valid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadSource1Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLretPayloadSource1Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqLretPayloadData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPayloadPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPayloadSpecWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPayloadStackValid = Output(Bool()) - val reducedLoadReplayLiqLretPayloadWakeupRequired = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPayloadBlockedByData = Output(Bool()) - val reducedLoadReplayLiqLretSinkEnqueueReady = Output(Bool()) - val reducedLoadReplayLiqLretSinkEnqueueAccepted = Output(Bool()) - val reducedLoadReplayLiqLretSinkEnqueueDropped = Output(Bool()) - val reducedLoadReplayLiqLretSinkDrainValid = Output(Bool()) - val reducedLoadReplayLiqLretSinkDrainFire = Output(Bool()) - val reducedLoadReplayLiqLretSinkPending = Output(Bool()) - val reducedLoadReplayLiqLretSinkFull = Output(Bool()) - val reducedLoadReplayLiqLretSinkEmpty = Output(Bool()) - val reducedLoadReplayLiqLretSinkCount = Output(UInt(loadReplayLretSinkCountWidth.W)) - val reducedLoadReplayLiqLretSinkDrainStid = Output(UInt(p.threadIdWidth.W)) - val reducedLoadReplayLiqLretSinkPrecisePruneCount = Output(UInt(loadReplayLretSinkCountWidth.W)) - val reducedLoadReplayLiqLretSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretSinkBlockedByNoPayload = Output(Bool()) - val reducedLoadReplayLiqLretSinkBlockedByFull = Output(Bool()) - val reducedLoadReplayLiqLretSinkBlockedByDrain = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCaptureCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPayloadValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCaptureValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCaptureReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCaptureAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCaptureDropped = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRecordValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRecordReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRecordFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPending = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCapturedWithLretEnqueue = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRecordFromLretEnqueue = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByInvalidPayload = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByFull = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitEnable = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitPipeOccupiedMask = Output(UInt(1.W)) - val reducedLoadReplayLiqLretDrainPermitPipeFreeMask = Output(UInt(1.W)) - val reducedLoadReplayLiqLretDrainPermitAnyPipeFree = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitSelectedPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretDrainPermitReady = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitBlockedByNoEntry = Output(Bool()) - val reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull = Output(Bool()) - val reducedLoadReplayLiqLretIexDataEnable = Output(Bool()) - val reducedLoadReplayLiqLretIexDataRobRowValid = Output(Bool()) - val reducedLoadReplayLiqLretIexDataRobRowNeedFlush = Output(Bool()) - val reducedLoadReplayLiqLretIexDataRobRowBlockedByInvalidRid = Output(Bool()) - val reducedLoadReplayLiqLretIexDataRobRowBlockedByFree = Output(Bool()) - val reducedLoadReplayLiqLretIexDataRobRowBlockedByStaleRid = Output(Bool()) - val reducedLoadReplayLiqLretIexDataCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretIexDataWouldDrain = Output(Bool()) - val reducedLoadReplayLiqLretIexDataSetMemDataValid = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByNoEntry = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByInvalidEntry = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByDrain = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByRobMissing = Output(Bool()) - val reducedLoadReplayLiqLretIexDataBlockedByNeedFlush = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveValid = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveReadyForPipeInsert = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveMarkAllDestinationsDataValid = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveMarkDestinationDataValid = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveRetLaneIncrement = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretRobResolveDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretRobResolveBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveBlockedByNoSetMemData = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveBlockedByUnsupportedMultiLane = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveBlockedByInvalidRid = Output(Bool()) - val reducedLoadReplayLiqLretRobResolveBlockedByNoDestination = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionCompleteValid = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionReadyForPipeInsert = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionRetLaneAfterResolve = Output(UInt(9.W)) - val reducedLoadReplayLiqLretLaneCompletionRequiresAllLanes = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByNoResolve = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByZeroReturnedLanes = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByInvalidRealReqCnt = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByScalarLoadPairIncomplete = Output(Bool()) - val reducedLoadReplayLiqLretLaneCompletionBlockedByVectorMemIncomplete = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionTloadCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionSubInstCntAfter = Output(UInt(8.W)) - val reducedLoadReplayLiqLretTloadCompletionTileScbSendValid = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionTileScbIsLast = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionCompleteValid = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionReadyForPipeInsert = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionBlockedByNoLaneCompletion = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionBlockedByInvalidSubInstCnt = Output(Bool()) - val reducedLoadReplayLiqLretTloadCompletionBlockedByTloadPending = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataIsLoadReturnMarked = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveCalled = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveSideEffectValid = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataPipeCycleSidebandValid = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataReadyForPipeInsert = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretFinalMetadataBlockedByNoTloadCompletion = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsSidebandValid = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsIqNameSidebandValid = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsLdRntCycleValid = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsUpdateValid = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsLdRntCycle = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretTimingStatsLatencyIncrement = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretTimingStatsLatencyUnderflow = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsReadyForPipeInsert = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretTimingStatsBlockedByNoFinalMetadata = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertValid = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertIsLoadReturn = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretIexPipeInsertLoadToUsePipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretIexPipeInsertWakeupRequired = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertBlockedByNoSetMemData = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertBlockedByNoPipe = Output(Bool()) - val reducedLoadReplayLiqLretIexPipeInsertBlockedByInvalidRid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyArmed = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyWriteValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyLiveEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeResidencyBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyBlockedByNoInsertCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyBlockedByNoInsertValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyBlockedByPipeOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotEntryValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByNoWrite = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencySlotBlockedByOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceClearSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvancePipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByNoSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByAdvanceDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotEntryValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW1SlotPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByNoWrite = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1SlotBlockedByOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceClearSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvancePipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW1AdvanceBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceBlockedByNoSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceBlockedByAdvanceDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW1AdvanceBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotEntryValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW2SlotPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotSourceTraceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotSource0Valid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotSource0Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotSource0Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotSource1Valid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotSource1Reg = Output(UInt(traceParams.regWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotSource1Data = Output(UInt(traceParams.dataWidth.W)) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByNoWrite = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotBlockedByOccupied = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionTargetValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionCompleteValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionClearSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW2CompletionResolveRequired = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionResolveValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionWritebackRequired = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionWritebackValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionWritebackTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2CompletionWritebackData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2CompletionWakeupRequired = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionWakeupValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionWakeupTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2CompletionReducedGprWakeupValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionBlockedByNoSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CompletionBlockedBySideEffects = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectResolveReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectWritebackReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectWakeupReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectBlockedByResolve = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectBlockedByWriteback = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectBlockedByWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlRequiredMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlLiveEnableMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlAllRequiredLiveEnabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByNoRequiredSink = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestRequestActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestSideEffectLiveRequested = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestPromotionRequested = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoEvidence = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByModeDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByPolicy = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoSideEffectSink = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoClearCommit = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRowFillCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRequiredSideEffect = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitRequiredMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitMissingReadyMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitPermitted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitMatchesReadyJoin = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkArmed = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByNoResolve = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkArmed = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByNoWriteback = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkArmed = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByNoWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedBySink = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestResolve = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestWriteback = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestBlockedByNoComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidCompleteWithoutCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidCompleteWithoutResolve = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidResolveWithoutComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidWritebackWithoutComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidWakeupWithoutComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestTargetValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestIsComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestGidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestGidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestSize = Output(UInt(p.memSizeWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByNoRequest = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByNoSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidBid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidGid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidRid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidIdentity = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestTargetValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestIdentityValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestDestinationValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestGprDestination = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestGidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestGidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestDstArchTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestDstRelTag = Output(UInt(p.archRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestDstOldPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoRequest = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidTarget = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidBid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidGid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidRid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidIdentity = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoDestination = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNonGprDestination = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupRequestCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupRequestValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupRequestReducedGprWakeupValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupRequestNonGprWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupRequestBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanRequiredMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanRequestMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanPayloadValidMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanIssueValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitSinkReadyMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitMissingReadyMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAcceptedMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAllSinksReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorFireValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorFireMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorResolveFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorWritebackFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorWakeupFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorRequestMatchesAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorPayloadMatchesAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireVectorBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPayloadValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadFireValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidFireWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidPayloadWithoutFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputResolveValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RobCompleteSourceSinkReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RobCompleteSourceCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteRobValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2RobCompleteSourceBlockedByExecute = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateRowFillValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateCompleteRowValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoMetadata = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoSourceTrace = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByInvalidSize = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNonGprDestination = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByRowFillDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateRowFillValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateCompleteRowValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoRecord = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoMetadata = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoSourceTrace = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByInvalidSize = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNonGprDestination = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByRowFillDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureIntent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCapturePayloadRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidMatchesCapture = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2MetadataReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromW2 = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromDrain = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoPayloadRid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Rid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByRidMismatch = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Metadata = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataClearAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataProviderValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceInstructionReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceSourceReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoMetadata = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoSourceTrace = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupRowValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupInstructionValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByNeedFlush = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByMissingInstruction = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceBeforeCompletion = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlPrerequisitesReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlRowFillEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoSideEffectCommit = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoClearCommit = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByLiveClearDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoReplayRowLifecycle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleSlotIdentityValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleResolvedRowMatch = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleMatchCount = Output(UInt(sizeWidth.W)) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByNoResolvedRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByMultipleResolvedRows = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByLifecycleClearDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleSlotIdentityValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleResolvedRowMatch = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRowClearReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByNoResolvedRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByMultipleResolvedRows = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByLifecycleClearDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeLivePromotionCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoAtomicRequest = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillCandidateAligned = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillEnableAligned = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableRequestEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableCandidateAligned = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoRowFillCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureIntent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureFromLifecycle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureBlockedByNoLifecycle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceClearAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValidWithoutRecord = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceRecordValidWithoutProvider = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCapturePhysicalClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackDuplicatePhysicalClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackClearValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCapturePhysicalComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackDuplicatePhysicalComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCompleteValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCapturePhysicalWriteback = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackDuplicatePhysicalWriteback = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackWritebackValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCapturePhysicalWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackDuplicatePhysicalWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackWakeupValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyAllCandidatesReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByPhysicalDuplicate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyNoPhysicalProbeActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackEmitProbeActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackLiveProbeActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyRetainedSoleOwnerEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByGlobalFallbackDisabled = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicySideEffectEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackLiveCompleteSelected = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackLiveWritebackSelected = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackLiveWakeupSelected = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackLiveClearSelected = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRecordCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnSideEffectsReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRetireClearEvidenceReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnThenRetireReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderFallbackOwnerEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingReturnSideEffect = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingRetireClearEvidence = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByOwnerDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionRecordCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionPreArmModelOrderReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionAnyPhysicalDuplicate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByNoRecord = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingFallbackCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingLifecycleEvidence = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByPhysicalDuplicate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByProbeActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorReturnSideEffectBundle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorModelOrderBundle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorPartial = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorSingle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorMulti = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorCount = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorNextRequiresBundleTransfer = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoRecord = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByPreArmNotReady = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoDuplicate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanPreArmReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanModelOrderBundle = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultTransferCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanRequiresPhysicalBundleSuppression = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultPromotionAlreadyReady = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoRecord = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPreArmNotReady = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoDuplicateVector = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPartialDuplicate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByProbeActive = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanTransferCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressionRequired = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanPhysicalBundleComplete = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAtomicSuppressCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRobComplete = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRfWriteback = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressWakeup = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressLifecycleClear = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressMask = - Output(UInt(4.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAllOrNoneSuppress = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoTransferCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoSuppressionRequirement = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByIncompletePhysicalBundle = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeEnabledCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelected = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelectedMask = - Output(UInt(4.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeAllOrNoneInputMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByProbeDisabled = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByNoAtomicCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByPartialMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectPlanPromotedCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelected = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedMask = - Output(UInt(4.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectAllOrNoneInputMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromProbe = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromPromotion = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPromoteDisabled = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByNoPlanCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPartialPlanMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectInvalidProbePromotionMaskMismatch = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryCapture = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredValid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredMask = - Output(UInt(4.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredFullMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByNoSelection = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByPartialMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryClearedByFlush = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCaptureIdentity = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCapturedIdentityValid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRegisteredCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRetainedRecordAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifecycleRowAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifetimeAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityEligibleRegisteredMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNoCapturedIdentity = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingRecord = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByRidMismatch = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLoadLsIdMismatch = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingLifecycleEvidence = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLifecycleRowMismatch = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNotFullMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCaptureOwnership = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCapturedOwnershipValid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredRidValid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLoadLsIdValid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLifecycleRowReady = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredBundleReady = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipEligibleRegisteredMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNoCapturedOwnership = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingRid = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLoadLsId = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLifecycleRow = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNotFullMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskEnabledCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRobComplete = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRfWriteback = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressWakeup = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressLifecycleClear = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressMask = - Output(UInt(4.W)) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskAllOrNone = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByLiveMaskDisabled = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByNoEligibleOwnership = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofCandidate = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFullMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFireCompleteAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofClearIntentAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLiveClearAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofRowFillAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLifecycleClearSuppressed = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofAllClearAligned = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByPartialMask = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoFireComplete = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoClearIntent = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoLiveClear = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoRowFill = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByLifecycleClearStillEnabled = - Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlActive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlRequestCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlLifecycleClearRequestEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByRequestInactive = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoRowFillCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitRowFillPermit = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitLifecycleClearCommitEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoSelection = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoRowFillEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitInvalidRowFillWithoutSelection = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleCandidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleClearEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleSelected = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleAccepted = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByExistingClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleRequestDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByNoLifecycleRow = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleCommitDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardCommitClearReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardLiveClearReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardResolveMatchesSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesResolve = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByNoRobComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByResolveSlotMismatch = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobSlotMismatch = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobResolveMismatch = Output(Bool()) - val robCompleteArbiterSelectedExecute = Output(Bool()) - val robCompleteArbiterSelectedReplay = Output(Bool()) - val robCompleteArbiterSelectedService = Output(Bool()) - val robCompleteArbiterReplayBlockedByExecute = Output(Bool()) - val scalarLrReservationSetCandidate = Output(Bool()) - val scalarLrReservationSetAccepted = Output(Bool()) - val scalarLrReservationSetStid = Output(UInt(p.threadIdWidth.W)) - val scalarLrReservationSetLineAddr = Output(UInt(p.immWidth.W)) - val scalarLrReservationSetRidValid = Output(Bool()) - val scalarLrReservationSetRidWrap = Output(Bool()) - val scalarLrReservationSetRidValue = Output(UInt(ptrWidth.W)) - val scalarLrReservationValidStid0 = Output(Bool()) - val scalarLrReservationLineStid0 = Output(UInt(p.immWidth.W)) - val scalarLrReservationCount = Output(UInt(log2Ceil(scalarStidCount + 1).W)) - val scalarLrReservationProtocolError = Output(Bool()) - val scalarLrReservationBlockedByFlush = Output(Bool()) - val scalarLrReservationCommittedStoreInvalidate = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPayloadValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadFireValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidFireWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidPayloadWithoutFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WritebackArbiterInputBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPayloadValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadFireValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPipeIndex = Output(UInt(1.W)) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstKind = Output(DestinationKind()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadReducedGprWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadNonGprWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidFireWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidPayloadWithoutFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputWakeupValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputTargetIsAgu = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputTargetIsLda = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidWrap = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputDstKind = Output(DestinationKind()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputDstPhysTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputReducedGprWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputNonGprWakeup = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadFireMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteMissingPayloadFireMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteUnexpectedPayloadFireMask = Output(UInt(3.W)) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadMatchesFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFutureClearEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidFireWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidPayloadWithoutFire = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentCandidateValid = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentPreClearEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentPermitEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentPostFireEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentLiveClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedPermit = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedFireComplete = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2ClearIntentInvalidEvidenceWithoutSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlLivePromotion = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlLiveClearEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlAdvanceLivePromotion = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByPromotionDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByClearIntent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2PromotionControlInvalidClearIntentWithoutSlot = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadyEmpty = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadySameCycleEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadySameCycleReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadyFutureAdvance = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadyMatchesCurrent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadyBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2RefillReadyInvalidLiveClearWithoutIntent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanEmptyWriteEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleEligible = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleReady = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanFutureWriteAccept = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanMatchesCurrent = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlockedByCurrentStorage = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2SlotReplacePlanInvalidFutureReadyWithoutLiveClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlAdvanceEnable = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlReplaceOnClear = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlUsesFutureAdvance = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlBlocked = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlBlockedByLivePromotionDisabled = Output(Bool()) - val reducedLoadReplayLiqLretPipeW2AdvanceControlInvalidFutureWriteWithoutAdvance = Output(Bool()) - val reducedLoadReplayLiqWritebackCandidateValid = Output(Bool()) - val reducedLoadReplayLiqWritebackValid = Output(Bool()) - val reducedLoadReplayLiqWritebackTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqWritebackData = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqWritebackIgnoredNoDestination = Output(Bool()) - val reducedLoadReplayLiqWritebackIgnoredNonGprDestination = Output(Bool()) - val reducedLoadReplayLiqWritebackBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqWritebackArbiterReplayEnabled = Output(Bool()) - val reducedLoadReplayLiqWritebackArbiterSelectedExecute = Output(Bool()) - val reducedLoadReplayLiqWritebackArbiterSelectedReplay = Output(Bool()) - val reducedLoadReplayLiqWritebackArbiterReplayBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqWritebackArbiterReplayBlockedByExecute = Output(Bool()) - val reducedLoadReplayLiqSideEffectCandidateValid = Output(Bool()) - val reducedLoadReplayLiqSideEffectLretReady = Output(Bool()) - val reducedLoadReplayLiqSideEffectWritebackReady = Output(Bool()) - val reducedLoadReplayLiqSideEffectWakeupReady = Output(Bool()) - val reducedLoadReplayLiqSideEffectReady = Output(Bool()) - val reducedLoadReplayLiqSideEffectBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqSideEffectBlockedByNoPayload = Output(Bool()) - val reducedLoadReplayLiqSideEffectBlockedByLret = Output(Bool()) - val reducedLoadReplayLiqSideEffectBlockedByWriteback = Output(Bool()) - val reducedLoadReplayLiqSideEffectBlockedByWakeup = Output(Bool()) - val reducedLoadReplayLiqPublishControlCandidateValid = Output(Bool()) - val reducedLoadReplayLiqPublishControlLiveEnable = Output(Bool()) - val reducedLoadReplayLiqPublishControlArmed = Output(Bool()) - val reducedLoadReplayLiqPublishControlFire = Output(Bool()) - val reducedLoadReplayLiqPublishControlBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqPublishControlBlockedByNoPayload = Output(Bool()) - val reducedLoadReplayLiqPublishControlBlockedByPublish = Output(Bool()) - val reducedLoadReplayLiqPublishControlBlockedBySideEffects = Output(Bool()) - val reducedLoadReplayLiqPublishControlBlockedByLiveDisabled = Output(Bool()) - val reducedLoadReplayLiqPublishRequestValid = Output(Bool()) - val reducedLoadReplayLiqPublishRequestLret = Output(Bool()) - val reducedLoadReplayLiqPublishRequestWriteback = Output(Bool()) - val reducedLoadReplayLiqPublishRequestWakeup = Output(Bool()) - val reducedLoadReplayLiqPublishRequestMask = Output(UInt(3.W)) - val reducedLoadReplayLiqPublishRequestBlockedByNoFire = Output(Bool()) - val reducedLoadReplayLiqPublishRequestInvalidFireWithoutPayload = Output(Bool()) - val reducedLoadReplayLiqWakeupCandidateValid = Output(Bool()) - val reducedLoadReplayLiqWakeupRequired = Output(Bool()) - val reducedLoadReplayLiqWakeupValid = Output(Bool()) - val reducedLoadReplayLiqWakeupKind = Output(UInt(2.W)) - val reducedLoadReplayLiqWakeupTag = Output(UInt(p.physRegWidth.W)) - val reducedLoadReplayLiqWakeupReducedGprValid = Output(Bool()) - val reducedLoadReplayLiqWakeupNonGpr = Output(Bool()) - val reducedLoadReplayLiqWakeupSuppressedNotRequired = Output(Bool()) - val reducedLoadReplayLiqWakeupIgnoredNoDestination = Output(Bool()) - val reducedLoadReplayLiqWakeupBlockedByDisabled = Output(Bool()) - val reducedLoadReplayLiqRepickMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqMissMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqResolvedMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayLiqE4UpdateValid = Output(Bool()) - val reducedLoadReplayLiqE4UpdateIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqE4MissKind = Output(UInt(3.W)) - val reducedLoadReplayLiqE4WakeupValid = Output(Bool()) - val reducedLoadReplayLiqLhqRecordValid = Output(Bool()) - val reducedLoadReplayLiqRowMutationBridgeValid = Output(Bool()) - val reducedLoadReplayLiqRowMutationSelectedSourceReturn = Output(Bool()) - val reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan = Output(Bool()) - val reducedLoadReplayLiqRowMutationSourceConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationSourceStoreIndexFits = Output(Bool()) - val reducedLoadReplayLiqRowMutationInvalidStoreIndexOutOfRange = Output(Bool()) - val reducedLoadReplayLiqRowMutationInvalidConflictingStatusWrite = Output(Bool()) - val reducedLoadReplayLiqRowMutationInvalidWaitStoreWithoutWaitStatus = Output(Bool()) - val reducedLoadReplayLiqRowMutationInvalidReturnWithoutSplitSources = Output(Bool()) - val reducedLoadReplayLiqRowMutationWriteEnable = Output(Bool()) - val reducedLoadReplayLiqRowMutationApplyValid = Output(Bool()) - val reducedLoadReplayLiqRowMutationTargetEvidenceValid = Output(Bool()) - val reducedLoadReplayLiqRowMutationWriteConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationBlockedByBridge = Output(Bool()) - val reducedLoadReplayLiqRowMutationBlockedByControl = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByInvalidRow = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByNotRepick = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByScbNotReturned = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByE4UpdateConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByClearResolvedConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByReplayWakeConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByRefillConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByLaunchConflict = Output(Bool()) - val reducedLoadReplayLiqRowMutationControlBlockedByAllocationConflict = Output(Bool()) - val reducedLoadReplayLiqResidentCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayLiqEmpty = Output(Bool()) - val reducedLoadReplayLiqFull = Output(Bool()) - val reducedLoadReplayLiqHeadValid = Output(Bool()) - val reducedLoadReplayLiqHeadIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadStatus = Output(UInt(3.W)) - val reducedLoadReplayLiqHeadLoadIdValid = Output(Bool()) - val reducedLoadReplayLiqHeadLoadIdWrap = Output(Bool()) - val reducedLoadReplayLiqHeadLoadIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadBidValid = Output(Bool()) - val reducedLoadReplayLiqHeadBidWrap = Output(Bool()) - val reducedLoadReplayLiqHeadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadGidValid = Output(Bool()) - val reducedLoadReplayLiqHeadGidWrap = Output(Bool()) - val reducedLoadReplayLiqHeadGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadRidValid = Output(Bool()) - val reducedLoadReplayLiqHeadRidWrap = Output(Bool()) - val reducedLoadReplayLiqHeadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadLoadLsIdValid = Output(Bool()) - val reducedLoadReplayLiqHeadLoadLsIdWrap = Output(Bool()) - val reducedLoadReplayLiqHeadLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayLiqHeadPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayLiqHeadAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayLiqHeadSize = Output(UInt(7.W)) - val reducedLoadReplayLiqHeadWaitStore = Output(Bool()) - val reducedLoadReplayLiqHeadStoreBypass = Output(Bool()) - val reducedLoadReplayLiqHeadDataComplete = Output(Bool()) - val reducedLoadReplayLiqHeadSourcesReturned = Output(Bool()) - val reducedLoadReplayLiqHeadScbReturned = Output(Bool()) - val reducedLoadReplayLiqHeadStqReturned = Output(Bool()) - val reducedLoadReplayResolveQueuePushReady = Output(Bool()) - val reducedLoadReplayResolveQueuePushAccepted = Output(Bool()) - val reducedLoadReplayResolveQueueClearPending = Output(Bool()) - val reducedLoadReplayResolveQueueClearAccepted = Output(Bool()) - val reducedLoadReplayResolveQueueClearIndex = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueRetireValid = Output(Bool()) - val reducedLoadReplayResolveQueueRetireIsLoadStore = Output(Bool()) - val reducedLoadReplayResolveQueueRetireIsLoad = Output(Bool()) - val reducedLoadReplayResolveQueueRetireIsStore = Output(Bool()) - val reducedLoadReplayResolveQueueRetireBidValid = Output(Bool()) - val reducedLoadReplayResolveQueueRetireBidWrap = Output(Bool()) - val reducedLoadReplayResolveQueueRetireBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueRetireRidValid = Output(Bool()) - val reducedLoadReplayResolveQueueRetireRidWrap = Output(Bool()) - val reducedLoadReplayResolveQueueRetireRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueRetireLsIdValid = Output(Bool()) - val reducedLoadReplayResolveQueueRetireLsIdWrap = Output(Bool()) - val reducedLoadReplayResolveQueueRetireLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueuePreciseFlushValid = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushBidValid = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushBidWrap = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueuePreciseFlushRidValid = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushRidWrap = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueuePreciseFlushLsIdValid = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushLsIdWrap = Output(Bool()) - val reducedLoadReplayResolveQueuePreciseFlushLsIdValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueFlushPruneMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayResolveQueueFlushPruneCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayResolveQueueRetireMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayResolveQueueRetireCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayResolveQueueValidMask = Output(UInt(p.robEntries.W)) - val reducedLoadReplayResolveQueueCount = Output(UInt(storeStqCountWidth.W)) - val reducedLoadReplayResolveQueueEmpty = Output(Bool()) - val reducedLoadReplayResolveQueueFull = Output(Bool()) - val reducedLoadReplayResolveQueueHeadValid = Output(Bool()) - val reducedLoadReplayResolveQueueHeadPeId = Output(UInt(p.peIdWidth.W)) - val reducedLoadReplayResolveQueueHeadStid = Output(UInt(p.threadIdWidth.W)) - val reducedLoadReplayResolveQueueHeadTid = Output(UInt(p.threadIdWidth.W)) - val reducedLoadReplayResolveQueueHeadPc = Output(UInt(p.pcWidth.W)) - val reducedLoadReplayResolveQueueHeadAddr = Output(UInt(p.immWidth.W)) - val reducedLoadReplayResolveQueueHeadSize = Output(UInt(7.W)) - val reducedLoadReplayResolveQueueHeadBidValid = Output(Bool()) - val reducedLoadReplayResolveQueueHeadBidWrap = Output(Bool()) - val reducedLoadReplayResolveQueueHeadBidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueHeadGidValid = Output(Bool()) - val reducedLoadReplayResolveQueueHeadGidWrap = Output(Bool()) - val reducedLoadReplayResolveQueueHeadGidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueHeadRidValid = Output(Bool()) - val reducedLoadReplayResolveQueueHeadRidWrap = Output(Bool()) - val reducedLoadReplayResolveQueueHeadRidValue = Output(UInt(ptrWidth.W)) - val reducedLoadReplayResolveQueueHeadLsIdValid = Output(Bool()) - val reducedLoadReplayResolveQueueHeadLsIdWrap = Output(Bool()) - val reducedLoadReplayResolveQueueHeadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedMdbConflictStoreValid = Output(Bool()) - val reducedMdbConflictActiveCandidateMask = Output(UInt(p.robEntries.W)) - val reducedMdbConflictResolveCandidateMask = Output(UInt(p.robEntries.W)) - val reducedMdbConflictWaitStoreMask = Output(UInt(p.robEntries.W)) - val reducedMdbConflictWaitStoreCount = Output(UInt(storeStqCountWidth.W)) - val reducedMdbConflictValid = Output(Bool()) - val reducedMdbConflictFromResolveQueue = Output(Bool()) - val reducedMdbConflictActiveIndex = Output(UInt(ptrWidth.W)) - val reducedMdbConflictResolveIndex = Output(UInt(ptrWidth.W)) - val reducedMdbConflictOrdinal = Output(UInt(mdbConflictOrdinalWidth.W)) - val reducedMdbConflictInnerFlush = Output(Bool()) - val reducedMdbConflictNukeFlush = Output(Bool()) - val reducedMdbConflictLoadBidValid = Output(Bool()) - val reducedMdbConflictLoadBidWrap = Output(Bool()) - val reducedMdbConflictLoadBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbConflictLoadLsIdValid = Output(Bool()) - val reducedMdbConflictLoadLsIdWrap = Output(Bool()) - val reducedMdbConflictLoadLsIdValue = Output(UInt(ptrWidth.W)) - val reducedMdbConflictStoreBidValid = Output(Bool()) - val reducedMdbConflictStoreBidWrap = Output(Bool()) - val reducedMdbConflictStoreBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbConflictStoreLsIdValid = Output(Bool()) - val reducedMdbConflictStoreLsIdWrap = Output(Bool()) - val reducedMdbConflictStoreLsIdValue = Output(UInt(ptrWidth.W)) - val reducedMdbFanoutLookupValid = Output(Bool()) - val reducedMdbFanoutLookupReady = Output(Bool()) - val reducedMdbFanoutLookupAccepted = Output(Bool()) - val reducedMdbFanoutLookupProcessed = Output(Bool()) - val reducedMdbFanoutLookupTableHit = Output(Bool()) - val reducedMdbFanoutLookupFirstAfterNuke = Output(Bool()) - val reducedMdbFanoutLookupConfBlocked = Output(Bool()) - val reducedMdbFanoutLookupWeightBlocked = Output(Bool()) - val reducedMdbFanoutDeleteValid = Output(Bool()) - val reducedMdbFanoutDeleteReady = Output(Bool()) - val reducedMdbFanoutDeleteAccepted = Output(Bool()) - val reducedMdbFanoutDeleteProcessed = Output(Bool()) - val reducedMdbFanoutPhaseStalledByFanout = Output(Bool()) - val reducedMdbFanoutLuOutValid = Output(Bool()) - val reducedMdbFanoutLuOutHit = Output(Bool()) - val reducedMdbFanoutLuOutStoreBidValid = Output(Bool()) - val reducedMdbFanoutLuOutStoreBidWrap = Output(Bool()) - val reducedMdbFanoutLuOutStoreBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbFanoutSuOutValid = Output(Bool()) - val reducedMdbFanoutSuOutHit = Output(Bool()) - val reducedMdbFanoutSuOutStoreBidValid = Output(Bool()) - val reducedMdbFanoutSuOutStoreBidWrap = Output(Bool()) - val reducedMdbFanoutSuOutStoreBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbFanoutRecordValid = Output(Bool()) - val reducedMdbFanoutRecordReady = Output(Bool()) - val reducedMdbFanoutRecordAccepted = Output(Bool()) - val reducedMdbFanoutRecordProcessed = Output(Bool()) - val reducedMdbFanoutBmdbReportValid = Output(Bool()) - val reducedMdbFanoutBmdbLoadBidValid = Output(Bool()) - val reducedMdbFanoutBmdbLoadBidWrap = Output(Bool()) - val reducedMdbFanoutBmdbLoadBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbFanoutBmdbStoreBidValid = Output(Bool()) - val reducedMdbFanoutBmdbStoreBidWrap = Output(Bool()) - val reducedMdbFanoutBmdbStoreBidValue = Output(UInt(ptrWidth.W)) - val reducedMdbFanoutBmdbStoreStid = Output(UInt(p.threadIdWidth.W)) - val reducedMdbFanoutDeleteMatched = Output(Bool()) - val reducedMdbFanoutDeleteReleased = Output(Bool()) - val reducedMdbFanoutDeleteDroppedBelowStall = Output(Bool()) - val reducedMdbFanoutRecordOverflow = Output(Bool()) - val reducedMdbFanoutRecordOrderIllegal = Output(Bool()) - val reducedMdbFanoutSsitValidMask = Output(UInt(p.robEntries.W)) - val reducedMdbFanoutSuMatchedStore = Output(Bool()) - val reducedMdbFanoutSuStorePending = Output(Bool()) - val reducedMdbFanoutSuWakeupValid = Output(Bool()) - val reducedMdbFanoutSuWakeupIndex = Output(UInt(storeStqPtrWidth.W)) - val reducedMdbLookupWaitPlanLookupHit = Output(Bool()) - val reducedMdbLookupWaitPlanCandidateMask = Output(UInt(p.robEntries.W)) - val reducedMdbLookupWaitPlanTargetIndex = Output(UInt(ptrWidth.W)) - val reducedMdbLookupWaitPlanWaitIntentValid = Output(Bool()) - val reducedMdbLookupWaitPlanRequestValid = Output(Bool()) - val reducedMdbLookupWaitPlanBlockedByNoTarget = Output(Bool()) - val reducedMdbLookupWaitPlanBlockedByMissingStoreIndex = Output(Bool()) - val reducedMdbLookupWaitPlanBlockedByMissingStoreLsId = Output(Bool()) - val reducedMdbLookupWaitPlanBridge = Output(new MdbLookupWaitPlanBridgeDiagnostics) - val reducedLoadWaitReplaySlotPc = Output(UInt(p.pcWidth.W)) - val reducedLoadWaitReplaySlotAddr = Output(UInt(p.immWidth.W)) - val reducedLoadWaitReplayRelaunchReturnSignExtend = Output(Bool()) - val storeDispatchReady = Output(Bool()) - val storeDispatchFire = Output(Bool()) - val storeDispatchSplit = Output(Bool()) - val storeStaQueueValid = Output(Bool()) - val storeStdQueueValid = Output(Bool()) - val storeStaEnqueueFire = Output(Bool()) - val storeStdEnqueueFire = Output(Bool()) - val storeStaDequeueFire = Output(Bool()) - val storeStdDequeueFire = Output(Bool()) - val storeDispatchInputProtocolError = Output(Bool()) - val storeStaQueueCount = Output(UInt(storeDispatchCountWidth.W)) - val storeStdQueueCount = Output(UInt(storeDispatchCountWidth.W)) - val storeStaInsertReady = Output(Bool()) - val storeStdInsertReady = Output(Bool()) - val storeSelectedSta = Output(Bool()) - val storeSelectedStd = Output(Bool()) - val storeBlockedByStaExec = Output(Bool()) - val storeBlockedByStdExec = Output(Bool()) - val storeStqInsertValid = Output(Bool()) - val storeStqInsertAccepted = Output(Bool()) - val storeStqInsertAllocated = Output(Bool()) - val storeStqInsertMerged = Output(Bool()) - val storeStqInsertConflict = Output(Bool()) - val storeStqInsertIndex = Output(UInt(storeStqPtrWidth.W)) - val storeStqOccupiedMask = Output(UInt(physicalStoreStqEntries.W)) - val storeStqWaitMask = Output(UInt(physicalStoreStqEntries.W)) - val storeStqCommitMask = Output(UInt(physicalStoreStqEntries.W)) - val storeStqAddrReadyMask = Output(UInt(physicalStoreStqEntries.W)) - val storeStqDataReadyMask = Output(UInt(physicalStoreStqEntries.W)) - val storeStqResidentCount = Output(UInt(storeStqCountWidth.W)) - val storeStqOutstandingWaitCount = Output(UInt(storeStqCountWidth.W)) - val storeStqEmpty = Output(Bool()) - val storeStqFull = Output(Bool()) - val storeStqStall = Output(Bool()) - val executeUnsupported = Output(Bool()) - val executeUnsupportedOpcode = Output(UInt(p.opcodeWidth.W)) - val robAllocFire = Output(Bool()) - val robRenameUpdateAttemptValid = Output(Bool()) - val robRenameUpdateReady = Output(Bool()) - val robRenameUpdateFire = Output(Bool()) - val robRenameUpdateIgnored = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeIgnored = Output(Bool()) - - val rfReadReadyMask = Output(UInt(3.W)) - val rfAllReadReady = Output(Bool()) - val rfReadyMask = Output(UInt(physRegs.W)) - val rfWriteValid = Output(Bool()) - val rfWriteTag = Output(UInt(p.physRegWidth.W)) - val rfWriteData = Output(UInt(p.immWidth.W)) - val reducedServiceRequest = Decoupled(new ReducedServiceRequestPayload(p)) - val reducedServiceResponse = Flipped(Decoupled(new ReducedServiceRequestResponse(p))) - val reducedServiceRenameFence = Output(Bool()) - val reducedServiceControlFence = Output(Bool()) - val reducedServiceGatherBusy = Output(Bool()) - val reducedServiceOwnerBusy = Output(Bool()) - val reducedServiceSnapshotLookupMatch = Output(Bool()) - val reducedServiceTrappedInvalidRequestType = Output(Bool()) - val reducedServiceTrappedIllegalSequence = Output(Bool()) - val executeCompleteSrcPhysValidMask = Output(UInt(3.W)) - val executeCompleteSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val executeCompletePc = Output(UInt(p.pcWidth.W)) - val executeCompleteInsn = Output(UInt(p.insnWidth.W)) - val executeCompleteWbReg = Output(UInt(traceParams.regWidth.W)) - val rfStateError = Output(Bool()) - val issueQueueEnqueueFire = Output(Bool()) - val issueQueueInputValid = Output(Bool()) - val issueQueueInputPc = Output(UInt(p.pcWidth.W)) - val issueQueueInputOpcode = Output(UInt(p.opcodeWidth.W)) - val issueQueueInputBidValid = Output(Bool()) - val issueQueueInputBidWrap = Output(Bool()) - val issueQueueInputBidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueInputRidValid = Output(Bool()) - val issueQueueInputRidWrap = Output(Bool()) - val issueQueueInputRidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueInputStid = Output(UInt(p.threadIdWidth.W)) - val issueQueuePickFire = Output(Bool()) - val issueQueueIssueFire = Output(Bool()) - val issueQueueOutputValid = Output(Bool()) - val issueQueueOutputPc = Output(UInt(p.pcWidth.W)) - val issueQueueOutputOpcode = Output(UInt(p.opcodeWidth.W)) - val issueQueueOutputBidValid = Output(Bool()) - val issueQueueOutputBidWrap = Output(Bool()) - val issueQueueOutputBidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueOutputRidValid = Output(Bool()) - val issueQueueOutputRidWrap = Output(Bool()) - val issueQueueOutputRidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueOutputStid = Output(UInt(p.threadIdWidth.W)) - val executeAcceptedIdentityValid = Output(Bool()) - val executeAcceptedPc = Output(UInt(p.pcWidth.W)) - val executeAcceptedOpcode = Output(UInt(p.opcodeWidth.W)) - val executeAcceptedBidValid = Output(Bool()) - val executeAcceptedBidWrap = Output(Bool()) - val executeAcceptedBidValue = Output(UInt(p.robIndexWidth.W)) - val executeAcceptedRidValid = Output(Bool()) - val executeAcceptedRidWrap = Output(Bool()) - val executeAcceptedRidValue = Output(UInt(p.robIndexWidth.W)) - val executeAcceptedStid = Output(UInt(p.threadIdWidth.W)) - val issueQueueCancelFire = Output(Bool()) - val issueQueueReleaseFire = Output(Bool()) - val issueQueueCount = Output(UInt(issueCountWidth.W)) - val issueQueueIssuedCount = Output(UInt(issueCountWidth.W)) - val issueQueueNotIssuedCount = Output(UInt(issueCountWidth.W)) - val issueQueueHeadValid = Output(Bool()) - val issueQueueHeadIssued = Output(Bool()) - val issueQueueHeadPc = Output(UInt(p.pcWidth.W)) - val issueQueueHeadOpcode = Output(UInt(p.opcodeWidth.W)) - val issueQueueHeadStid = Output(UInt(p.threadIdWidth.W)) - val issueQueueHeadBidValid = Output(Bool()) - val issueQueueHeadBidWrap = Output(Bool()) - val issueQueueHeadBidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueHeadRidValid = Output(Bool()) - val issueQueueHeadRidWrap = Output(Bool()) - val issueQueueHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val issueQueueHeadSrcValidMask = Output(UInt(3.W)) - val issueQueueHeadSrcClass = Output(Vec(3, OperandClass())) - val issueQueueHeadSrcPhysTag = Output(Vec(3, UInt(p.physRegWidth.W))) - val issueQueueHeadSrcRelTag = Output(Vec(3, UInt(p.archRegWidth.W))) - val issueQueueSourceReadyMask = Output(UInt(3.W)) - val issueQueueAllSourcesReady = Output(Bool()) - val issueQueueSelectedValid = Output(Bool()) - val issueQueueSelectedIndex = Output(UInt(log2Ceil(issueQueueDepth).W)) - val issueQueueSelectedReadReady = Output(Bool()) - val issueQueueI1Valid = Output(Bool()) - val issueQueueI2Valid = Output(Bool()) - val issueQueueStageBusy = Output(Bool()) - val issueQueueBlockedBySource = Output(Bool()) - val issueQueueBlockedByRead = Output(Bool()) - val issueQueueBlockedByOutput = Output(Bool()) - val issueQueueBlockedByIssued = Output(Bool()) - val issueQueueBankOccupancy = Output(Vec(issueBankCount, UInt(issueBankCountWidth.W))) - val issueQueueBankPickMask = Output(UInt(issueBankCount.W)) - val issueQueueBankReadAttemptMask = Output(UInt(issueBankCount.W)) - val issueQueueBankReadGrantMask = Output(UInt(issueBankCount.W)) - val issueQueueBankIssueValidMask = Output(UInt(issueBankCount.W)) - val issueQueueBankIssueGrantMask = Output(UInt(issueBankCount.W)) - val issueQueueSimultaneousPick = Output(Bool()) - val issueQueueReadContention = Output(Bool()) - val issueQueueReadArbitrationLoss = Output(Bool()) - val issueQueueIssueContention = Output(Bool()) - val issueQueueControlFenceActive = Output(Bool()) - val issueQueueControlFenceBlocked = Output(Bool()) - val issueQueueBankControlBlockedMask = Output(UInt(issueBankCount.W)) - val issueQueueStoreOrderBlocked = Output(Bool()) - val issueQueueBankStoreOrderBlockedMask = Output(UInt(issueBankCount.W)) - val issueQueueScalarSpOrderBlocked = Output(Bool()) - val issueQueueBankScalarSpOrderBlockedMask = Output(UInt(issueBankCount.W)) - val issueQueueProtocolError = Output(Bool()) - val scalarSpStid0IssueHeadValid = Output(Bool()) - val scalarSpStid0IssueHeadBidValid = Output(Bool()) - val scalarSpStid0IssueHeadBidWrap = Output(Bool()) - val scalarSpStid0IssueHeadBidValue = Output(UInt(p.robIndexWidth.W)) - val scalarSpStid0IssueHeadRidValid = Output(Bool()) - val scalarSpStid0IssueHeadRidWrap = Output(Bool()) - val scalarSpStid0IssueHeadRidValue = Output(UInt(p.robIndexWidth.W)) - val localTReadyMask = Output(UInt(4.W)) - val localUReadyMask = Output(UInt(4.W)) - val localTPendingCount = Output(UInt(issueCountWidth.W)) - val localUPendingCount = Output(UInt(issueCountWidth.W)) - val localIncomingUsesLocal = Output(Bool()) - val localIncomingBlocked = Output(Bool()) - val decodeBlockedByRename = Output(Bool()) - val decodeBlockedByRob = Output(Bool()) - val decodeBlockedByOutput = Output(Bool()) - val decodeBlockedByTURename = Output(Bool()) - val gprFreeCount = Output(UInt(gprFreeWidth.W)) - val gprMapQValidCount = Output(UInt(gprMapQFreeWidth.W)) - val gprMapQFreeCount = Output(UInt(gprMapQFreeWidth.W)) - val gprSmapLiveCount = Output(UInt(gprFreeWidth.W)) - val gprCmapLiveCount = Output(UInt(gprFreeWidth.W)) - val gprMapQLiveCount = Output(UInt(gprFreeWidth.W)) - val gprLivePhysCount = Output(UInt(gprFreeWidth.W)) - val gprFreeFromLiveCount = Output(UInt(gprFreeWidth.W)) - val gprFreeListMismatchCount = Output(UInt(gprFreeWidth.W)) - val gprNextMapQValidCount = Output(UInt(gprMapQFreeWidth.W)) - val gprNextMapQLiveCount = Output(UInt(gprFreeWidth.W)) - val gprNextLivePhysCount = Output(UInt(gprFreeWidth.W)) - val gprNextFreeFromLiveCount = Output(UInt(gprFreeWidth.W)) - val gprCommitAccepted = Output(Bool()) - val gprCommitBlockBid = Output(UInt(p.blockBidWidth.W)) - val gprCommittedMapQCount = Output(UInt(gprMapQFreeWidth.W)) - val gprReleasedPhysCount = Output(UInt(gprFreeWidth.W)) - val tuRenameSourceUnderflowMask = Output(UInt(3.W)) - val tuRenameActiveBankValid = Output(Bool()) - val tuRenameBlockedByTAlloc = Output(Bool()) - val tuRenameBlockedByUAlloc = Output(Bool()) - val tuRenameTUsedEntries = Output(UInt(tuCountWidth.W)) - val tuRenameUUsedEntries = Output(UInt(tuCountWidth.W)) - val tuRetireCommandValid = Output(Bool()) - val tuRetireCommandFire = Output(Bool()) - val tuRetireLocalBlockCommitPending = Output(Bool()) - val tuRetireLocalBlockCommitValid = Output(Bool()) - val tuRetireLocalBlockCommitReady = Output(Bool()) - val tuRetireLocalBlockCommitFire = Output(Bool()) - val tuRetireAccepted = Output(Bool()) - val tuRetireMiss = Output(Bool()) - val tuRetireReleaseMismatch = Output(Bool()) - val tuRetireUnsupported = Output(Bool()) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val deallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val deallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val robDeallocBlockLastValid = Output(Bool()) - val robDeallocBlockLastBlockBid = Output(UInt(p.blockBidWidth.W)) - val blockScalarDoneFire = Output(Bool()) - val blockScalarDoneBid = Output(UInt(p.blockBidWidth.W)) - val blockRetireFire = Output(Bool()) - val blockRetireBid = Output(UInt(p.blockBidWidth.W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val outstandingCount = Output(UInt(sizeWidth.W)) - val commitHeadValid = Output(Bool()) - val commitHeadStatus = Output(ROBEntryStatus()) - val commitHeadRobValue = Output(UInt(ptrWidth.W)) - val occupiedMask = Output(UInt(p.robEntries.W)) - val completedMask = Output(UInt(p.robEntries.W)) - val retiredMask = Output(UInt(p.robEntries.W)) - val blockAllocatedMask = Output(UInt(p.robEntries.W)) - val blockCompleteMask = Output(UInt(p.robEntries.W)) - val blockPendingMask = Output(UInt(p.robEntries.W)) - val idle = Output(Bool()) -} - -class FullBidBlockConditionOwnerIO(blockBidWidth: Int) extends Bundle { - val captureValid = Input(Bool()) - val captureTaken = Input(Bool()) - val captureBlockBidValid = Input(Bool()) - val captureBlockBid = Input(UInt(blockBidWidth.W)) - - val activeBlockValid = Input(Bool()) - val activeBlockBid = Input(UInt(blockBidWidth.W)) - val activeConditionValid = Output(Bool()) - val activeConditionTaken = Output(Bool()) - - val fretValid = Input(Bool()) - val fretBlockBidValid = Input(Bool()) - val fretBlockBid = Input(UInt(blockBidWidth.W)) - val fretConsume = Input(Bool()) - val fretConditionValid = Output(Bool()) - val fretConditionTaken = Output(Bool()) -} - -/** Exact-full-BID SETC condition owner shared by marker and conditional FRET. */ -class FullBidBlockConditionOwner(blockBidWidth: Int) extends Module { - val io = IO(new FullBidBlockConditionOwnerIO(blockBidWidth)) - - val retainedValid = RegInit(false.B) - val retainedTaken = RegInit(false.B) - val retainedBlockBidValid = RegInit(false.B) - val retainedBlockBid = RegInit(0.U(blockBidWidth.W)) - - val captureMatchesActive = - io.captureValid && io.captureBlockBidValid && io.activeBlockValid && - io.captureBlockBid === io.activeBlockBid - val retainedMatchesActive = - retainedValid && retainedBlockBidValid && io.activeBlockValid && - retainedBlockBid === io.activeBlockBid - io.activeConditionValid := captureMatchesActive || retainedMatchesActive - io.activeConditionTaken := Mux(captureMatchesActive, io.captureTaken, retainedTaken) - - val captureMatchesFret = - io.captureValid && io.captureBlockBidValid && io.fretValid && io.fretBlockBidValid && - io.captureBlockBid === io.fretBlockBid - val retainedMatchesFret = - retainedValid && retainedBlockBidValid && io.fretValid && io.fretBlockBidValid && - retainedBlockBid === io.fretBlockBid - io.fretConditionValid := captureMatchesFret || retainedMatchesFret - io.fretConditionTaken := Mux(captureMatchesFret, io.captureTaken, retainedTaken) - - when(io.captureValid) { - retainedValid := io.captureBlockBidValid - retainedTaken := io.captureTaken - retainedBlockBidValid := io.captureBlockBidValid - retainedBlockBid := io.captureBlockBid - }.elsewhen(io.fretConsume && retainedMatchesFret) { - retainedValid := false.B - retainedTaken := false.B - retainedBlockBidValid := false.B - retainedBlockBid := 0.U - } -} - -private object FullBidBlockConditionWiring { - def connect( - clear: Bool, - captureValid: Bool, - captureTaken: Bool, - captureBlockBidValid: Bool, - captureBlockBid: UInt, - activeBlockValid: Bool, - activeBlockBid: UInt, - fretValid: Bool, - fretBlockBidValid: Bool, - fretBlockBid: UInt, - fretConsume: Bool, - blockBidWidth: Int): FullBidBlockConditionOwnerIO = { - val owner = withReset(clear) { - Module(new FullBidBlockConditionOwner(blockBidWidth)) - } - owner.io.captureValid := captureValid - owner.io.captureTaken := captureTaken - owner.io.captureBlockBidValid := captureBlockBidValid - owner.io.captureBlockBid := captureBlockBid - owner.io.activeBlockValid := activeBlockValid - owner.io.activeBlockBid := activeBlockBid - owner.io.fretValid := fretValid - owner.io.fretBlockBidValid := fretBlockBidValid - owner.io.fretBlockBid := fretBlockBid - owner.io.fretConsume := fretConsume - owner.io - } -} - -class LinxCoreFrontendFetchRfAluTraceTop( - val coreParams: CoreParams = CoreParams(), - val decRenQueueDepth: Int = 4, - val issueQueueDepth: Int = 4, - val denseSlotQueueDepth: Int = 8, - val storeDispatchQueueDepth: Int = 4, - val storeExecBufferEntries: Int = 4, - val mapQDepth: Int = 32, - val gprMapQDepth: Int = 32, - val scalarStidCount: Int = 1, - val archRegs: Int = 24, - val physRegs: Int = 64, - val skipBlockMarkers: Boolean = true, - val useMarkerDecodeContext: Boolean = false, - val useReducedStoreDispatchStq: Boolean = false, - val useReducedStoreStaAddressExecBridge: Boolean = false, - val useReducedLoadReplayLiqAlloc: Boolean = false, - val useReducedLiveLoadLiq: Boolean = false, - val reducedStoreStdExecDelayCycles: Int = 0, - val reducedReplayLiqW2CompletionDelayCycles: Int = 0, - val reducedReplayLiqW2PostLretEnqueueHoldCycles: Int = 0, - val reducedReplayLiqRetainedOwnerNoPhysicalProbe: Boolean = false, - val reducedReplayLiqRetainedOwnerFallbackEmitProbe: Boolean = false, - val reducedReplayLiqRetainedOwnerFallbackLiveProbe: Boolean = false, - val reducedReplayLiqRetainedOwnerPhysicalSuppressProbe: Boolean = false, - val reducedReplayLiqRetainedOwnerPhysicalSuppressPromote: Boolean = false, - val reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask: Boolean = false, - val useProductionD1Ingress: Boolean = false) - extends Module { - require(physRegs > 0 && (physRegs & (physRegs - 1)) == 0, "physical register count must be a power of two") - require(scalarStidCount > 0, "reduced top must expose at least one scalar STID") - require( - BigInt(scalarStidCount) <= (BigInt(1) << coreParams.scalarLsu.stidWidth), - "scalar STID count must fit scalar LSU STID width") - require(reducedStoreStdExecDelayCycles >= 0, "reduced store STD execution delay cycles must be nonnegative") - require( - reducedReplayLiqW2CompletionDelayCycles >= 0, - "reduced replay-LIQ W2 completion delay cycles must be nonnegative") - require( - reducedReplayLiqW2PostLretEnqueueHoldCycles >= 0, - "reduced replay-LIQ W2 post-LRET-enqueue hold cycles must be nonnegative") - private val reducedStoreMemoryLineEntries = 64 - private val reducedLoadReplayRelaunchQueueDepth = 2 - private val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor( - coreParams, - physRegWidth = log2Ceil(physRegs) - ) - require(physRegs == (1 << p.physRegWidth), - "physical GPR capacity must match the complete physical-tag namespace") - private val traceParams = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = IO(new LinxCoreFrontendFetchRfAluTraceTopIO( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - issueQueueDepth = issueQueueDepth, - denseSlotQueueDepth = denseSlotQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - storeExecBufferEntries = storeExecBufferEntries, - scalarLsuParams = Some(coreParams.scalarLsu), - storeMemoryLineEntries = reducedStoreMemoryLineEntries, - loadReturnQueueEntries = coreParams.scalarLsu.loadReturnQueueEntries, - loadReturnPipeCount = coreParams.scalarLsu.loadReturnPipeCount, - scalarStidCount = scalarStidCount, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - physRegs = physRegs, - issueBankCount = coreParams.scalarBackend.scalarIssueBanks - )) - - val source = Module(new FrontendFetchPacketSource(p)) - val f4 = Module(new F4DecodeWindow(p)) - val denseSlots = Module(new F4DenseSlotQueue(p, depth = denseSlotQueueDepth)) - val productionD1 = Module(new D1DecodedLaneQueue(p, depth = denseSlotQueueDepth)) - val path = Module(new DecodeRenameROBPath( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - storeStqEntries = coreParams.scalarLsu.stqEntries, - physRegs = physRegs, - mapQDepth = mapQDepth, - gprMapQDepth = gprMapQDepth, - scalarStidCount = scalarStidCount, - useMarkerDecodeContext = useMarkerDecodeContext, - skipBlockMarkers = skipBlockMarkers, - reducedStoreDispatchBypass = !useReducedStoreDispatchStq - )) - if (!useProductionD1Ingress) { - DecodeRenameROBPath.tieOffPredecoded(path) - } - val robCompleteArbiter = Module(new ReducedRobCompletionArbiter( - ptrWidth = log2Ceil(p.robEntries), - traceParams = traceParams - )) - val executeCompletionRetainer = Module(new ExecuteCompletionRetainer( - ptrWidth = log2Ceil(p.robEntries), - traceParams = traceParams, - robEntries = p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth - )) - val servicePath = Module(new ReducedServiceRequestPath(p, traceParams)) - val rf = Module(new ScalarGPRFile( - archRegs = archRegs, - physRegs = physRegs, - dataWidth = p.immWidth, - readPorts = coreParams.scalarBackend.gprReadPorts + 5, - writePorts = 2 - )) - val rfWritebackArbiter = Module(new ReducedScalarWritebackArbiter( - dataWidth = p.immWidth, - physRegWidth = p.physRegWidth - )) - val issue = Module(new ScalarIssueFabric( - p, - depth = issueQueueDepth, - bankCount = coreParams.scalarBackend.scalarIssueBanks, - stidCount = scalarStidCount - )) - val scalarSpOrder = Module(new ScalarSpOrderOwner( - p = p, - traceParams = traceParams, - depth = p.robEntries, - stidCount = scalarStidCount - )) - private val scalarSpStidIndexWidth = math.max(1, log2Ceil(scalarStidCount)) - private def scalarSpStidIndex(stid: UInt): UInt = - if (scalarStidCount == 1) 0.U(scalarSpStidIndexWidth.W) else stid(scalarSpStidIndexWidth - 1, 0) - val markerIssueControlFence = Module(new ScalarIssueExternalControlFence(p)) - val execute = Module(new ReducedScalarAluExecute(p, traceParams)) - val templateContext = Module(new ReducedTemplateContextStack( - archRegs = archRegs, - physRegWidth = p.physRegWidth, - dataWidth = p.immWidth, - frameDepth = p.robEntries - )) - val templateSnapshotTable = Module(new ReducedTemplateSnapshotTable( - entries = p.robEntries, - archRegs = archRegs, - physRegWidth = p.physRegWidth - )) - val storeExecBridge = Module(new ReducedStoreExecResultBridge( - p = p, - traceParams = traceParams, - bufferEntries = storeExecBufferEntries, - mapQDepth = mapQDepth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - stdDelayCycles = reducedStoreStdExecDelayCycles - )) - val storeStaAddressExecBridge = Module(new ReducedStoreStaAddressExecBridge( - p = p, - mapQDepth = mapQDepth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth - )) - val storeCommitOwner = Module(new ReducedStoreCommitFreeOwner( - entries = coreParams.scalarLsu.stqEntries, - robEntries = p.robEntries, - traceParams = traceParams, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - lsidWidth = p.lsidWidth - )) - private val reducedStoreCommitIssueWidth = coreParams.scalarLsu.commitIssueWidth - private val reducedStoreScbRequestCount = reducedStoreCommitIssueWidth * 2 - private val reducedStoreCommitBypassRequestCount = traceParams.commitWidth * 2 - private val reducedStoreMemoryRequestCount = reducedStoreScbRequestCount + reducedStoreCommitBypassRequestCount - val reducedStoreCommitDrain = Module(new STQCommitDrain( - entries = coreParams.scalarLsu.stqEntries, - queueEntries = coreParams.scalarLsu.commitQueueEntries, - issueWidth = reducedStoreCommitIssueWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - robEntries = p.robEntries, - lsidWidth = p.lsidWidth - )) - val reducedStoreScb = Module(new SCBRowBank( - stqEntries = coreParams.scalarLsu.stqEntries, - scbEntries = coreParams.scalarLsu.scbEntries, - requestCount = reducedStoreScbRequestCount, - responseBufferDepth = coreParams.scalarLsu.scbResponseBufferDepth, - robEntries = p.robEntries, - lsidWidth = p.lsidWidth - )) - val reducedStoreMemoryOverlay = Module(new ReducedStoreMemoryOverlay( - stqEntries = coreParams.scalarLsu.stqEntries, - requestCount = reducedStoreMemoryRequestCount, - lineEntries = reducedStoreMemoryLineEntries, - robEntries = p.robEntries, - lsidWidth = p.lsidWidth - )) - val reducedStoreResidentForward = Module(new ReducedStoreResidentForward( - entries = coreParams.scalarLsu.stqEntries, - robEntries = p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - lsidWidth = p.lsidWidth - )) - val reducedReplayLiqStoreSnapshot = Module(new ResidentStoreForwardStoreSnapshot( - entries = coreParams.scalarLsu.stqEntries, - robEntries = p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - lsidWidth = p.lsidWidth - )) - val reducedReplayLiqBaseDataAlign = Module(new LoadReplayBaseDataAlign( - addrWidth = p.immWidth, - dataWidth = p.immWidth - )) - val loadLookupArbiter = Module(new LoadLookupArbiter( - addrWidth = p.immWidth, - pcWidth = p.pcWidth - )) - val reducedReplayLiqSourceReturnStoreSnapshotPath = - Module(new LoadReplaySourceReturnStoreSnapshotPath( - liqEntries = p.robEntries, - idEntries = p.robEntries, - entryIdWidth = p.robIndexWidth, - stqEntries = coreParams.scalarLsu.stqEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - lsidWidth = p.lsidWidth - )) - val reducedReplayLiqSourceReturnScbLiveControl = Module(new LoadReplaySourceReturnScbLiveControl) - val reducedReplayLiqSourceReturnReadiness = Module(new LoadReplaySourceReturnReadiness) - val reducedReplayLiqReturnConsumerReady = Module(new LoadReplayReturnConsumerReady) - val reducedReplayLiqReturnPipeBudget = Module(new LoadReplayReturnPipeBudget) - val reducedReplayLiqReturnPipePermit = Module(new LoadReplayReturnPipePermit(returnPipeCount = 1)) - val reducedReplayLiqReturnPipeSelect = Module(new LoadReplayReturnPipeSelect(returnPipeCount = 1)) - val reducedReplayLiqReturnReadiness = Module(new LoadReplayReturnReadiness(returnPipeCount = 1)) - val reducedReplayLiqReturnDataExtract = Module(new LoadReplayReturnDataExtract( - addrWidth = p.immWidth, - dataWidth = p.immWidth - )) - val reducedReplayLiqReturnPublishReady = Module(new LoadReplayReturnPublishReady) - require(coreParams.scalarLsu.loadReturnPipeCount == 1, - "the reduced W1/W2 integration currently exposes one shared scalar load-return pipe") - val reducedReplayLiqReturnLretPayload = Module(new LoadReplayReturnLretPayload( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = coreParams.scalarLsu.loadReturnPipeCount, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth - )) - val reducedReplayLiqReturnLretSink = Module(new ScalarLSULoadReturnQueueBank( - idEntries = p.robEntries, - stidCount = scalarStidCount, - returnPipeCount = coreParams.scalarLsu.loadReturnPipeCount, - queueDepth = coreParams.scalarLsu.loadReturnQueueEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth - )) - val reducedReplayLiqReturnIexPipeOccupancyLiveControl = - Module(new LoadReplayReturnIexPipeOccupancyLiveControl(returnPipeCount = 1)) - val reducedReplayLiqReturnIexPipeOccupancy = - Module(new LoadReplayReturnIexPipeOccupancy(returnPipeCount = 1)) - val reducedReplayLiqReturnIexDrainPermit = Module(new LoadReplayReturnIexDrainPermit(returnPipeCount = 1)) - val reducedReplayLiqReturnIexDataCandidate = Module(new LoadReplayReturnIexDataCandidate( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnRobResolveDataCandidate = Module(new LoadReplayReturnRobResolveDataCandidate( - idEntries = p.robEntries, - dataWidth = p.immWidth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnReducedScalarShapeControl = - Module(new LoadReplayReturnReducedScalarShapeControl(countWidth = 8)) - val reducedReplayLiqReturnLaneCompletionCandidate = Module(new LoadReplayReturnLaneCompletionCandidate( - countWidth = 8 - )) - val reducedReplayLiqReturnTloadCompletionCandidate = Module(new LoadReplayReturnTloadCompletionCandidate( - countWidth = 8 - )) - val reducedReplayLiqReturnFinalMetadataCandidate = Module(new LoadReplayReturnFinalMetadataCandidate) - val reducedReplayLiqReturnTimingStatsCandidate = Module(new LoadReplayReturnTimingStatsCandidate( - cycleWidth = p.immWidth - )) - val reducedReplayLiqReturnIexPipeInsertCandidate = Module(new LoadReplayReturnIexPipeInsertCandidate( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnPipeResidencyCandidate = Module(new LoadReplayReturnPipeResidencyCandidate( - returnPipeCount = 1 - )) - val reducedReplayLiqReturnPipeResidencyLiveControl = - Module(new LoadReplayReturnPipeResidencyLiveControl) - val reducedReplayLiqReturnPipeResidencySlot = Module(new LoadReplayReturnPipeResidencySlot( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnPipeResidencyAdvanceLiveControl = - Module(new LoadReplayReturnPipeResidencyAdvanceLiveControl(returnPipeCount = 1)) - val reducedReplayLiqReturnPipeResidencyAdvanceCandidate = - Module(new LoadReplayReturnPipeResidencyAdvanceCandidate(returnPipeCount = 1)) - val reducedReplayLiqReturnPipeW1Slot = Module(new LoadReplayReturnPipeW1Slot( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnPipeW1AdvanceCandidate = - Module(new LoadReplayReturnPipeW1AdvanceCandidate(returnPipeCount = 1)) - private val reducedReplayLiqReturnPipeW2Modules = - LinxCoreFrontendFetchRfAluTraceTopW2Modules.create( - p = p, - traceParams = traceParams, - storeEntries = coreParams.scalarLsu.stqEntries, - postLretEnqueueHoldCycles = reducedReplayLiqW2PostLretEnqueueHoldCycles - ) - val reducedReplayLiqReturnWritebackCandidate = Module(new LoadReplayReturnWritebackCandidate( - dataWidth = p.immWidth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnWritebackSinkReadyControl = Module(new LoadReplayReturnWritebackSinkReady) - val reducedReplayLiqReturnWakeupCandidate = Module(new LoadReplayReturnWakeupCandidate( - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) - val reducedReplayLiqReturnWakeupSinkReadyControl = Module(new LoadReplayReturnWakeupSinkReady) - val reducedReplayLiqReturnSideEffectLiveControl = Module(new LoadReplayReturnSideEffectLiveControl) - val reducedReplayLiqReturnSideEffectReady = Module(new LoadReplayReturnSideEffectReady) - val reducedReplayLiqReturnPublishControl = Module(new LoadReplayReturnPublishControl) - val reducedReplayLiqReturnPublishRequest = Module(new LoadReplayReturnPublishRequest) - val reducedReplayLiqLaunchReadiness = Module(new LoadReplayLaunchReadiness) - val reducedStoreResidentReplayWakeup = Module(new ResidentStoreReplayWakeup( - entries = coreParams.scalarLsu.stqEntries, - robEntries = p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - mapQDepth = mapQDepth, - lsidWidth = p.lsidWidth - )) - val reducedLoadWaitReplaySlot = Module(new ReducedLoadWaitReplaySlot( - idEntries = p.robEntries, - storeEntries = coreParams.scalarLsu.stqEntries, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - val reducedLoadReplayRelaunchQueue = Module(new ReducedLoadReplayRelaunchQueue( - idEntries = p.robEntries, - depth = reducedLoadReplayRelaunchQueueDepth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - val reducedLoadReplayLiqAllocPath = Module(new ReducedLoadReplayLiqAllocPath( - liqEntries = p.robEntries, - idEntries = p.robEntries, - storeEntries = coreParams.scalarLsu.stqEntries, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - val reducedLiveLoadLiqCapture = Module(new ReducedLiveLoadLiqCapture( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - // LIQ models 64-byte lines and therefore owns a seven-bit byte-size field; - // the scalar execute lookup's narrower encoded size is zero-extended here. - sizeWidth = 7, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - val scalarLrScReservationOwner = Module(new ScalarLrScReservationOwner( - coreParams.copy(scalarLsu = coreParams.scalarLsu.copy(stidCount = scalarStidCount)) - )) - val reducedLoadReplayResolveQueue = Module(new LoadResolveQueue( - queueEntries = p.robEntries, - liqEntries = p.robEntries, - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth - )) - val reducedMdbCoreParams = coreParams.copy(scalarLsu = coreParams.scalarLsu.copy( - stqEntries = coreParams.scalarLsu.stqEntries, - liqEntries = p.robEntries, - resolveQueueEntries = p.robEntries, - mdbSsitEntries = p.robEntries, - mdbCommandQueueEntries = 4, - mdbOutputQueueEntries = 4, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - loadSizeWidth = 7, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - stidCount = scalarStidCount - )) - val reducedMdbPath = Module(new ScalarLSUMDBPath(reducedMdbCoreParams)) - val reducedLoadReplayCompletionDrain = Module(new ReducedLoadReplayCompletionDrain( - idEntries = p.robEntries, - lsidWidth = p.lsidWidth - )) - - val localQueueDepth = 4 - val localTData = RegInit(VecInit(Seq.fill(localQueueDepth)(0.U(p.immWidth.W)))) - val localUData = RegInit(VecInit(Seq.fill(localQueueDepth)(0.U(p.immWidth.W)))) - val localTReady = RegInit(VecInit(Seq.fill(localQueueDepth)(false.B))) - val localUReady = RegInit(VecInit(Seq.fill(localQueueDepth)(false.B))) - val localPendingCountWidth = log2Ceil(issueQueueDepth + 2) - val localTPendingCount = RegInit(0.U(localPendingCountWidth.W)) - val localUPendingCount = RegInit(0.U(localPendingCountWidth.W)) - - private def pushLocal( - data: Vec[UInt], - ready: Vec[Bool], - value: UInt): Unit = { - for (idx <- (1 until localQueueDepth).reverse) { - data(idx) := data(idx - 1) - ready(idx) := ready(idx - 1) - } - data(0) := value - ready(0) := true.B - } - - // W2 may complete an older direct row while a younger live-LIQ load returns - // in the same cycle. Keep their local T/U results in age order instead of - // silently dropping one through the single-value helper. - private def pushLocalPair( - data: Vec[UInt], - ready: Vec[Bool], - olderValid: Bool, - olderValue: UInt, - youngerValid: Bool, - youngerValue: UInt): Unit = { - when(olderValid && youngerValid) { - for (idx <- (2 until localQueueDepth).reverse) { - data(idx) := data(idx - 2) - ready(idx) := ready(idx - 2) - } - data(1) := olderValue - ready(1) := true.B - data(0) := youngerValue - ready(0) := true.B - }.elsewhen(olderValid) { - pushLocal(data, ready, olderValue) - }.elsewhen(youngerValid) { - pushLocal(data, ready, youngerValue) - } - } - - val markerRedirectPending = RegInit(false.B) - val markerRedirectPcReg = RegInit(0.U(p.pcWidth.W)) - val fretSpRestorePending = RegInit(false.B) - val fretSpRestoreStidReg = RegInit(0.U(p.threadIdWidth.W)) - val fretSpRestoreDataReg = RegInit(0.U(p.immWidth.W)) - val bodyCutRestartPending = RegInit(false.B) - val bodyCutRestartPcReg = RegInit(0.U(p.pcWidth.W)) - val reducedLoadReplayResolveClearPending = RegInit(false.B) - val reducedLoadReplayResolveClearIndex = RegInit(0.U(log2Ceil(p.robEntries).W)) - // Production IFU steering is owned by B-F4 and exact backend validation. - // A marker-only redirect belongs only to the packet-source verification - // configuration; replaying it in production after B-F4 moved F0 can - // re-execute an older target block. - val markerOnlyRedirectFire = - !useProductionD1Ingress.B && - path.io.blockMarkerStopRedirectValid && - !execute.io.redirectValid - val markerRedirectFire = markerOnlyRedirectFire || execute.io.redirectValid - val admittedMarkerDrainBarrier = RegInit(false.B) - val selectedSlotOH = UIntToOH(path.io.selectedSlot, p.decodeWidth) - val selectedMarkerMask = path.io.blockBoundaryMask | path.io.blockStopMask - val frontendIngressFire = - if (useProductionD1Ingress) productionD1.io.out.fire else denseSlots.io.outFire - val admittedMarkerDrainFire = - (!skipBlockMarkers).B && frontendIngressFire && path.io.selectedValid && (selectedMarkerMask & selectedSlotOH).orR - val skippedMarkerLifecycleFire = - skipBlockMarkers.B && frontendIngressFire && path.io.blockMarkerSkipValid - val backendPipeFlush = Wire(Bool()) - val (productionBruRecoveryUop, productionDispatchValidationReady) = - LinxCoreFrontendFetchRfAluTraceTopBranchValidationWiring.connect( - io, - path, - execute, - productionD1, - reset.asBool, - backendPipeFlush, - useProductionD1Ingress, - p) - val scalarRedirectRecovery = Module(new ScalarRedirectRecoverySource( - entries = p.robEntries, - bidWidth = p.blockBidWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - orderWidth = p.uopUidWidth, - lsidWidth = p.lsidWidth - )) - LinxCoreFrontendFetchRfAluTraceTopMarkerRedirectRecoveryWiring.connect( - io, - path, - execute, - scalarRedirectRecovery, - productionBruRecoveryUop, - markerOnlyRedirectFire, - lsidToReducedStoreId(execute.io.completeLsId), - p) - val productionIfuPipeFlush = - LinxCoreFrontendFetchRfAluTraceTopPipeFlushWiring.productionIfuCanonical( - io.productionIfuFlush, - useProductionD1Ingress) - val frontendPipeFlush = - LinxCoreFrontendFetchRfAluTraceTopPipeFlushWiring.frontend( - io.frontendFlushValid, - markerRedirectPending, - productionIfuPipeFlush) - // Once the exact recovery block is closed and all of its resident rows have - // completed, cut younger backend ingress immediately. Waiting for the - // validation to traverse the IFU feedback bridge leaves a multi-cycle hole - // in which a previously non-resident wrong-path row can allocate after the - // ROB suffix query. Keep the fence asserted until the exact IFU recovery - // acknowledgement retires the query: a pulse only clears the rows already - // present and still permits a stale D1 response to refill the backend on the - // following cycle. Delaying assertion until recoveryReady preserves a - // non-terminal SETC's same-block tail through completion. - val recoveryIngressFenceFlush = - LinxCoreFrontendFetchRfAluTraceTopPipeFlushWiring.recoveryIngressFence( - path.io.recoveryBlockQueryValid, - path.io.recoveryBlockReady, - reset.asBool, - useProductionD1Ingress) - // Every marker redirect invalidates decoded/queued old-path work, even when - // the ROB is already empty and no architectural recovery intent is needed. - // Keep ROB/GPR recovery qualified separately; this pulse only clears the - // backend pipeline queues that sit in front of ROB allocation. - backendPipeFlush := - LinxCoreFrontendFetchRfAluTraceTopPipeFlushWiring.backend( - io.frontendFlushValid, - markerRedirectPending, - path.io.recoveryIntentConsumed, - productionIfuPipeFlush) || recoveryIngressFenceFlush - val externalBfuGeometryValid = io.bfuBodyValid - val staticBfuGeometry = Module(new BfuStaticGeometryProducer(p)) - val localBfuCutFeedbackPending = Module(new BfuResolvedBodyEndPending(p)) - val pendingRuntimeBodyEndCandidate = Module(new BfuPendingRuntimeBodyEndCandidate(p)) - val runtimeBodyEndOracle = Module(new BfuRuntimeBodyEndOracle(p)) - val resolvedBfuBodyEndSource = Module(new BfuResolvedBodyEndSource(p)) - val resolvedBfuBodyEnd = Module(new BfuResolvedBodyEndOwner(p)) - resolvedBfuBodyEndSource.io.runtimeValid := pendingRuntimeBodyEndCandidate.io.candidateValid - resolvedBfuBodyEndSource.io.runtimeHeaderPc := pendingRuntimeBodyEndCandidate.io.candidateHeaderPc - resolvedBfuBodyEndSource.io.runtimeHSizeBytes := pendingRuntimeBodyEndCandidate.io.candidateHSizeBytes - resolvedBfuBodyEndSource.io.runtimeBodyEndPc := pendingRuntimeBodyEndCandidate.io.candidateBodyEndPc - resolvedBfuBodyEndSource.io.replayValid := externalBfuGeometryValid - resolvedBfuBodyEndSource.io.replayHeaderPc := io.bfuHeaderPc - resolvedBfuBodyEndSource.io.replayHSizeBytes := io.bfuHSizeBytes - resolvedBfuBodyEndSource.io.replayBSizeBytes := io.bfuBSizeBytes - localBfuCutFeedbackPending.io.flushValid := frontendPipeFlush || io.startValid || io.restartValid || markerRedirectFire - localBfuCutFeedbackPending.io.captureValid := false.B - localBfuCutFeedbackPending.io.captureHeaderPc := 0.U - localBfuCutFeedbackPending.io.captureHSizeBytes := 0.U - localBfuCutFeedbackPending.io.captureBodyEndPc := 0.U - localBfuCutFeedbackPending.io.candidateValid := externalBfuGeometryValid - localBfuCutFeedbackPending.io.candidateHeaderPc := io.bfuHeaderPc - localBfuCutFeedbackPending.io.candidateHSizeBytes := io.bfuHSizeBytes - localBfuCutFeedbackPending.io.candidateBSizeBytes := io.bfuBSizeBytes - localBfuCutFeedbackPending.io.consumeValid := resolvedBfuBodyEndSource.io.selectedRuntime - pendingRuntimeBodyEndCandidate.io.pendingValid := localBfuCutFeedbackPending.io.pending - pendingRuntimeBodyEndCandidate.io.pendingHeaderPc := localBfuCutFeedbackPending.io.pendingHeaderPc - pendingRuntimeBodyEndCandidate.io.pendingHSizeBytes := localBfuCutFeedbackPending.io.pendingHSizeBytes - pendingRuntimeBodyEndCandidate.io.pendingBodyEndPc := localBfuCutFeedbackPending.io.pendingBodyEndPc - pendingRuntimeBodyEndCandidate.io.headerActive := staticBfuGeometry.io.headerActive - pendingRuntimeBodyEndCandidate.io.activeHeaderPc := staticBfuGeometry.io.headerPc - pendingRuntimeBodyEndCandidate.io.replayValid := externalBfuGeometryValid - pendingRuntimeBodyEndCandidate.io.replayHeaderPc := io.bfuHeaderPc - pendingRuntimeBodyEndCandidate.io.replayHSizeBytes := io.bfuHSizeBytes - pendingRuntimeBodyEndCandidate.io.replayBSizeBytes := io.bfuBSizeBytes - runtimeBodyEndOracle.io.flushValid := frontendPipeFlush || io.startValid || io.restartValid || markerRedirectFire - runtimeBodyEndOracle.io.promoteValid := - resolvedBfuBodyEndSource.io.selectedRuntime && pendingRuntimeBodyEndCandidate.io.candidateValid - runtimeBodyEndOracle.io.promoteHeaderPc := pendingRuntimeBodyEndCandidate.io.candidateHeaderPc - runtimeBodyEndOracle.io.promoteHSizeBytes := pendingRuntimeBodyEndCandidate.io.candidateHSizeBytes - runtimeBodyEndOracle.io.promoteBodyEndPc := pendingRuntimeBodyEndCandidate.io.candidateBodyEndPc - runtimeBodyEndOracle.io.replayValid := externalBfuGeometryValid - runtimeBodyEndOracle.io.replayHeaderPc := io.bfuHeaderPc - runtimeBodyEndOracle.io.replayHSizeBytes := io.bfuHSizeBytes - runtimeBodyEndOracle.io.replayBSizeBytes := io.bfuBSizeBytes - resolvedBfuBodyEnd.io.flushValid := frontendPipeFlush || io.startValid || io.restartValid - resolvedBfuBodyEnd.io.headerActive := staticBfuGeometry.io.headerActive - resolvedBfuBodyEnd.io.activeHeaderPc := staticBfuGeometry.io.headerPc - resolvedBfuBodyEnd.io.resolvedValid := resolvedBfuBodyEndSource.io.resolvedValid - resolvedBfuBodyEnd.io.resolvedHeaderPc := resolvedBfuBodyEndSource.io.resolvedHeaderPc - resolvedBfuBodyEnd.io.resolvedHSizeBytes := resolvedBfuBodyEndSource.io.resolvedHSizeBytes - resolvedBfuBodyEnd.io.resolvedBodyEndPc := resolvedBfuBodyEndSource.io.resolvedBodyEndPc - staticBfuGeometry.io.flushValid := frontendPipeFlush || io.startValid || io.restartValid - staticBfuGeometry.io.f4UpdateFire := source.io.outFire - staticBfuGeometry.io.f4Valid := f4.io.d1.valid - staticBfuGeometry.io.f4Slots := f4.io.slots - staticBfuGeometry.io.f4ValidMask := f4.io.validMask - staticBfuGeometry.io.resolvedBodyEndValid := resolvedBfuBodyEnd.io.geometryValid - staticBfuGeometry.io.resolvedHeaderPc := resolvedBfuBodyEnd.io.geometryHeaderPc - staticBfuGeometry.io.resolvedHSizeBytes := resolvedBfuBodyEnd.io.hsizeBytes - staticBfuGeometry.io.resolvedBodyEndPc := resolvedBfuBodyEnd.io.bodyEndPc - val staticExternalComparable = staticBfuGeometry.io.geometryValid && externalBfuGeometryValid - val staticExternalHeaderMatch = staticBfuGeometry.io.headerPc === io.bfuHeaderPc - val staticExternalHSizeMatch = staticBfuGeometry.io.hsizeBytes === io.bfuHSizeBytes - val staticExternalBSizeMatch = staticBfuGeometry.io.bsizeBytes === io.bfuBSizeBytes - val staticExternalMatch = - staticExternalComparable && staticExternalHeaderMatch && staticExternalHSizeMatch && staticExternalBSizeMatch - val staticExternalHeaderMismatch = staticExternalComparable && !staticExternalHeaderMatch - val staticExternalHSizeMismatch = staticExternalComparable && !staticExternalHSizeMatch - val staticExternalBSizeMismatch = staticExternalComparable && !staticExternalBSizeMatch - - val staticBfuPrediction = Module(new BfuGeometryPredictionLatch(p)) - staticBfuPrediction.io.flushValid := io.frontendFlushValid || io.startValid || io.restartValid - staticBfuPrediction.io.learnValid := resolvedBfuBodyEnd.io.geometryValid - staticBfuPrediction.io.learnHeaderPc := resolvedBfuBodyEnd.io.geometryHeaderPc - staticBfuPrediction.io.learnHSizeBytes := resolvedBfuBodyEnd.io.hsizeBytes - staticBfuPrediction.io.learnBSizeBytes := resolvedBfuBodyEnd.io.bsizeBytes - - val bodyCutArm = Module(new BfuBodyCutArm(p)) - bodyCutArm.io.predictionValid := staticBfuPrediction.io.geometryValid - bodyCutArm.io.predictionHeaderPc := staticBfuPrediction.io.headerPc - bodyCutArm.io.predictionHSizeBytes := staticBfuPrediction.io.hsizeBytes - bodyCutArm.io.predictionBSizeBytes := staticBfuPrediction.io.bsizeBytes - bodyCutArm.io.armValid := externalBfuGeometryValid - bodyCutArm.io.armHeaderPc := io.bfuHeaderPc - bodyCutArm.io.armHSizeBytes := io.bfuHSizeBytes - bodyCutArm.io.armBSizeBytes := io.bfuBSizeBytes - - val localBfuBodyWindow = Module(new BfuLocalBodyWindow(p)) - localBfuBodyWindow.io.flushValid := frontendPipeFlush || io.startValid || io.restartValid || markerRedirectFire - localBfuBodyWindow.io.f4ScanValid := f4.io.d1.valid - localBfuBodyWindow.io.predictionValid := staticBfuPrediction.io.geometryValid - localBfuBodyWindow.io.predictionHeaderPc := staticBfuPrediction.io.headerPc - localBfuBodyWindow.io.predictionHSizeBytes := staticBfuPrediction.io.hsizeBytes - localBfuBodyWindow.io.predictionBSizeBytes := staticBfuPrediction.io.bsizeBytes - localBfuBodyWindow.io.f4Valid := f4.io.d1.valid - localBfuBodyWindow.io.f4Slots := f4.io.slots - localBfuBodyWindow.io.f4ValidMask := f4.io.validMask - - val bodyCutGeometryValid = localBfuBodyWindow.io.geometryValid || resolvedBfuBodyEnd.io.geometryValid - val bodyCutHeaderPc = Mux(localBfuBodyWindow.io.geometryValid, localBfuBodyWindow.io.headerPc, resolvedBfuBodyEnd.io.geometryHeaderPc) - val bodyCutHSizeBytes = Mux(localBfuBodyWindow.io.geometryValid, localBfuBodyWindow.io.hsizeBytes, resolvedBfuBodyEnd.io.hsizeBytes) - val bodyCutBSizeBytes = Mux(localBfuBodyWindow.io.geometryValid, localBfuBodyWindow.io.bsizeBytes, resolvedBfuBodyEnd.io.bsizeBytes) - - val bodyCut = Module(new BfuBodyCutPredictor(p)) - bodyCut.io.geometryValid := bodyCutGeometryValid - bodyCut.io.headerPc := bodyCutHeaderPc - bodyCut.io.hsizeBytes := bodyCutHSizeBytes - bodyCut.io.bsizeBytes := bodyCutBSizeBytes - bodyCut.io.f4Valid := f4.io.d1.valid - bodyCut.io.f4Pc := f4.io.d1.pc - bodyCut.io.f4Slots := f4.io.slots - bodyCut.io.f4ValidMask := f4.io.validMask - bodyCut.io.f4TotalLenBytes := f4.io.totalLenBytes - - val reducedBodyCutActive = bodyCut.io.cutActive - val frontendValidMask = bodyCut.io.validMask - val frontendSlotCount = bodyCut.io.slotCount - val effectiveSourceAdvanceBytes = bodyCut.io.advanceBytes - val frontendSlots = Wire(Vec(p.decodeWidth, new F4Slot(p))) - frontendSlots := f4.io.slots - for (slot <- 0 until p.decodeWidth) { - val slotEndPc = (f4.io.slots(slot).pc + f4.io.slots(slot).lenBytes.pad(p.pcWidth))(p.pcWidth - 1, 0) - val reducedBodyCutLast = - reducedBodyCutActive && f4.io.slots(slot).valid && frontendValidMask(slot) && slotEndPc === bodyCut.io.cutPc - frontendSlots(slot).isLastInBlock := f4.io.slots(slot).isLastInBlock || reducedBodyCutLast - } - val bodyCutRestartFire = source.io.outFire && reducedBodyCutActive - val localBfuCutFeedbackFire = bodyCutRestartFire && localBfuBodyWindow.io.geometryValid - localBfuBodyWindow.io.cutFire := bodyCutRestartFire - - localBfuCutFeedbackPending.io.captureValid := localBfuCutFeedbackFire - localBfuCutFeedbackPending.io.captureHeaderPc := localBfuBodyWindow.io.headerPc - localBfuCutFeedbackPending.io.captureHSizeBytes := localBfuBodyWindow.io.hsizeBytes - localBfuCutFeedbackPending.io.captureBodyEndPc := bodyCut.io.cutPc - - when(io.frontendFlushValid || io.restartValid || io.startValid) { - markerRedirectPending := false.B - markerRedirectPcReg := 0.U - fretSpRestorePending := false.B - fretSpRestoreStidReg := 0.U - fretSpRestoreDataReg := 0.U - }.elsewhen(markerRedirectFire) { - markerRedirectPending := true.B - markerRedirectPcReg := Mux(path.io.blockMarkerStopRedirectValid, path.io.blockMarkerStopRedirectPc, execute.io.redirectPc) - fretSpRestorePending := execute.io.redirectValid && execute.io.fretStkSpRestoreValid - fretSpRestoreStidReg := execute.io.releaseStid - fretSpRestoreDataReg := execute.io.fretStkSpRestoreData - }.elsewhen(markerRedirectPending) { - markerRedirectPending := false.B - fretSpRestorePending := false.B - } - assert( - !scalarRedirectRecovery.io.event.valid || scalarRedirectRecovery.io.cancel || - scalarRedirectRecovery.io.eventReady, - "scalar redirect recovery cannot overwrite an unconsumed event" - ) - assert( - !scalarRedirectRecovery.io.blockedByMissingIdentity, - "scalar redirect recovery requires exact full block BID identity" - ) - when(io.frontendFlushValid || io.restartValid || io.startValid || markerRedirectFire) { - admittedMarkerDrainBarrier := false.B - }.elsewhen(admittedMarkerDrainFire) { - admittedMarkerDrainBarrier := true.B - }.elsewhen(path.io.robMarkerRetireSourceLifecycleFire) { - admittedMarkerDrainBarrier := false.B - } - when(io.frontendFlushValid || io.restartValid || io.startValid || markerRedirectFire || markerRedirectPending) { - bodyCutRestartPending := false.B - bodyCutRestartPcReg := 0.U - }.elsewhen(bodyCutRestartFire) { - bodyCutRestartPending := true.B - bodyCutRestartPcReg := bodyCut.io.restartPc - }.elsewhen(bodyCutRestartPending) { - bodyCutRestartPending := false.B - bodyCutRestartPcReg := 0.U - } - - source.io.startValid := io.startValid && (!useProductionD1Ingress).B - source.io.startPc := io.startPc - source.io.restartValid := - (io.restartValid || markerRedirectPending || bodyCutRestartPending) && (!useProductionD1Ingress).B - source.io.restartPc := Mux(markerRedirectPending, markerRedirectPcReg, Mux(bodyCutRestartPending, bodyCutRestartPcReg, io.restartPc)) - source.io.flushValid := io.frontendFlushValid - source.io.peId := io.peId - source.io.threadId := io.threadId - source.io.reqReady := io.fetchReqReady && (!useProductionD1Ingress).B - source.io.respValid := io.fetchRespValid && (!useProductionD1Ingress).B - source.io.respWindow := io.fetchRespWindow - source.io.outReady := denseSlots.io.inReady && (!useProductionD1Ingress).B - source.io.advanceBytes := effectiveSourceAdvanceBytes - - f4.io.in := source.io.out - f4.io.flushValid := frontendPipeFlush - - denseSlots.io.inD1 := f4.io.d1 - denseSlots.io.inD1.valid := f4.io.d1.valid && (!useProductionD1Ingress).B - denseSlots.io.inSlots := frontendSlots - denseSlots.io.inValidMask := Mux(useProductionD1Ingress.B, 0.U, frontendValidMask) - denseSlots.io.outReady := - path.io.decodeReady && !admittedMarkerDrainBarrier && (!useProductionD1Ingress).B - denseSlots.io.flushValid := frontendPipeFlush - - LinxCoreFrontendFetchRfAluTraceTopProductionD1Wiring.connect( - io, - path, - denseSlots, - productionD1, - admittedMarkerDrainBarrier, - productionDispatchValidationReady, - useProductionD1Ingress, - p) - path.io.flushValid := backendPipeFlush - LinxCoreFrontendFetchRfAluTraceTopScalarSpOrderWiring.connect( - io, - path, - scalarSpOrder, - backendPipeFlush, - markerRedirectPending && fretSpRestorePending, - fretSpRestoreStidReg, - fretSpRestoreDataReg) - DecodeRenameROBPath.tieOffExplicitStoreCount(path) - val localIncomingUsesLocal = - path.io.decRenValid && path.io.decRenHeadUsesLocal - val localIncomingBlocked = - localIncomingUsesLocal && ((localTPendingCount =/= 0.U) || (localUPendingCount =/= 0.U)) - val serviceOpcode = FrontendOpcodeDecodeTable.OP_ACRC.U(p.opcodeWidth.W) - val incomingServiceRow = path.io.decRenValid && path.io.decRenHeadOpcode === serviceOpcode - val serviceQueueAccepts = !incomingServiceRow || servicePath.io.enqueueReady - path.io.renamedOutReady := - issue.io.inReady && !localIncomingBlocked && !servicePath.io.renameFence && serviceQueueAccepts - val reducedStoreFlush = backendPipeFlush || io.startValid || io.restartValid || (!useReducedStoreDispatchStq).B - val reducedStoreScbReadyForDrain = LinxCoreFrontendFetchRfAluTraceTopStoreCommitIngressWiring.connect( - io, - path, - execute, - storeExecBridge, - storeStaAddressExecBridge, - storeCommitOwner, - reducedStoreCommitDrain, - reducedStoreScb, - reducedStoreFlush, - useReducedStoreDispatchStq.B, - useReducedStoreStaAddressExecBridge.B, - scalarStidCount, - coreParams - ) - LinxCoreFrontendFetchRfAluTraceTopStaScalarSpWiring.connect( - path, - execute, - storeStaAddressExecBridge, - storeExecBridge, - scalarSpOrder, - useReducedStoreDispatchStq.B, - p, - scalarStidCount) - - reducedStoreScb.io.reqs := reducedStoreCommitDrain.io.memReqs - reducedStoreScb.io.evictEnable := useReducedStoreDispatchStq.B - reducedStoreScb.io.dcacheReady := true.B - reducedStoreScb.io.dcacheWriteHit := true.B - reducedStoreScb.io.dcacheTagHit := true.B - reducedStoreScb.io.l2RequestReady := true.B - reducedStoreScb.io.rawRespValid := false.B - reducedStoreScb.io.rawRespTxnId := 0.U - reducedStoreScb.io.rawRespWrite := false.B - reducedStoreScb.io.rawRespUpgrade := false.B - - private def zeroReducedStoreMemoryReq: STQCommitDrainRequest = { - val req = Wire(new STQCommitDrainRequest( - coreParams.scalarLsu.stqEntries, - p.immWidth, - p.immWidth, - 4, - p.robEntries, - p.lsidWidth)) - req := 0.U.asTypeOf(req) - req - } - - private def lsidToReducedStoreId(lsid: UInt): ROBID = { - val out = Wire(new ROBID(p.robEntries)) - val idWidth = log2Ceil(p.robEntries) - val wrapBit = if (p.lsidWidth > idWidth) lsid(idWidth) else false.B - out.valid := true.B - out.wrap := wrapBit - out.value := lsid(idWidth - 1, 0) - out - } - - val reducedStoreMemoryReqs = Wire(Vec( - reducedStoreMemoryRequestCount, - new STQCommitDrainRequest( - coreParams.scalarLsu.stqEntries, - p.immWidth, - p.immWidth, - 4, - p.robEntries, - p.lsidWidth))) - val reducedStoreMemoryAcceptedVec = Wire(Vec(reducedStoreMemoryRequestCount, Bool())) - for (idx <- 0 until reducedStoreMemoryRequestCount) { - reducedStoreMemoryReqs(idx) := zeroReducedStoreMemoryReq - reducedStoreMemoryAcceptedVec(idx) := false.B - } - - for (idx <- 0 until reducedStoreScbRequestCount) { - reducedStoreMemoryReqs(idx) := reducedStoreCommitDrain.io.memReqs(idx) - reducedStoreMemoryAcceptedVec(idx) := - useReducedStoreDispatchStq.B && reducedStoreScb.io.acceptedMask(idx) - } - - val reducedStoreCommitBypassValidVec = Wire(Vec(traceParams.commitWidth, Bool())) - val reducedStoreCommitBypassBidVec = Wire(Vec(traceParams.commitWidth, new ROBID(p.robEntries))) - val reducedStoreCommitBypassLsIdVec = Wire(Vec(traceParams.commitWidth, UInt(p.lsidWidth.W))) - - for (slot <- 0 until traceParams.commitWidth) { - val commitStoreRow = path.io.commit.rows(slot) - val commitStoreValid = - useReducedStoreDispatchStq.B && commitStoreRow.valid && commitStoreRow.mem.valid && commitStoreRow.mem.isStore - val commitStoreOffset = Wire(UInt(7.W)) - val commitStoreSizeWide = Wire(UInt(7.W)) - commitStoreOffset := commitStoreRow.mem.addr(5, 0) - commitStoreSizeWide := commitStoreRow.mem.size - val commitStoreCrosses = STQCommitDrain.crossesScalarCacheline(commitStoreRow.mem.addr, commitStoreRow.mem.size) - val commitStoreFirstSize = Mux(commitStoreCrosses, 64.U(7.W) - commitStoreOffset, commitStoreSizeWide) - val commitStoreSecondSize = commitStoreSizeWide - commitStoreFirstSize - val commitStoreSecondAddr = (Cat(commitStoreRow.mem.addr(p.immWidth - 1, 6), 0.U(6.W)) + 64.U)(p.immWidth - 1, 0) - val commitStoreAllDataBits = Fill(p.immWidth, 1.B).asUInt - val commitStoreFirstData = commitStoreRow.mem.wdata & (commitStoreAllDataBits >> (commitStoreSecondSize << 3)) - val commitStoreSecondData = commitStoreRow.mem.wdata >> (commitStoreFirstSize << 3) - - val firstReq = Wire(new STQCommitDrainRequest( - coreParams.scalarLsu.stqEntries, - p.immWidth, - p.immWidth, - 4, - p.robEntries, - p.lsidWidth)) - firstReq := zeroReducedStoreMemoryReq - firstReq.valid := commitStoreValid - firstReq.bid := path.io.commitMemoryOrder(slot).bid - firstReq.lsId := path.io.commitMemoryOrder(slot).lsId - firstReq.split := commitStoreCrosses - firstReq.segment := 0.U - firstReq.last := !commitStoreCrosses - firstReq.addr := commitStoreRow.mem.addr - firstReq.data := commitStoreFirstData - firstReq.size := commitStoreFirstSize(3, 0) - - val secondReq = Wire(new STQCommitDrainRequest( - coreParams.scalarLsu.stqEntries, - p.immWidth, - p.immWidth, - 4, - p.robEntries, - p.lsidWidth)) - secondReq := zeroReducedStoreMemoryReq - secondReq.valid := commitStoreValid && commitStoreCrosses - secondReq.bid := path.io.commitMemoryOrder(slot).bid - secondReq.lsId := path.io.commitMemoryOrder(slot).lsId - secondReq.split := commitStoreCrosses - secondReq.segment := 1.U - secondReq.last := true.B - secondReq.addr := commitStoreSecondAddr - secondReq.data := commitStoreSecondData - secondReq.size := commitStoreSecondSize(3, 0) - - val base = reducedStoreScbRequestCount + slot * 2 - reducedStoreMemoryReqs(base) := firstReq - reducedStoreMemoryAcceptedVec(base) := commitStoreValid - reducedStoreMemoryReqs(base + 1) := secondReq - reducedStoreMemoryAcceptedVec(base + 1) := commitStoreValid && commitStoreCrosses - reducedStoreCommitBypassValidVec(slot) := firstReq.valid - reducedStoreCommitBypassBidVec(slot) := firstReq.bid - reducedStoreCommitBypassLsIdVec(slot) := firstReq.lsId - } - - io.reducedStoreCommitBypassValidMask := reducedStoreCommitBypassValidVec.asUInt - io.reducedStoreCommitBypassBid := reducedStoreCommitBypassBidVec - io.reducedStoreCommitBypassLsId := reducedStoreCommitBypassLsIdVec - - val reducedLiveLoadLiqEnabled = - useReducedStoreDispatchStq.B && useReducedLiveLoadLiq.B - val reducedLoadLookupLsId = lsidToReducedStoreId(execute.io.loadLookupLsId) - // The physical-memory overlay and resident-store forwarding lookup must - // follow the arbiter, not just E1. A first-pass live load leaves E1 as soon - // as LIQ accepts it; its later E2 base lookup otherwise saw raw harness - // memory and missed committed-store visibility. - LinxCoreFrontendFetchRfAluTraceTopStoreLookupWiring.connect( - overlay = reducedStoreMemoryOverlay, - residentForward = reducedStoreResidentForward, - lookupArbiter = loadLookupArbiter, - liq = reducedLoadReplayLiqAllocPath, - execute = execute, - executeLoadLsId = reducedLoadLookupLsId, - path = path, - storeReqs = reducedStoreMemoryReqs, - storeAcceptedMask = reducedStoreMemoryAcceptedVec.asUInt, - baseLoadData = io.loadLookupData, - flush = io.startValid || io.restartValid || (!useReducedStoreDispatchStq).B, - enable = useReducedStoreDispatchStq.B) - - val executeLoadLookupDst = Wire(new LoadReplayDestination(p.archRegWidth, p.physRegWidth)) - executeLoadLookupDst.valid := execute.io.loadLookupDst.valid - executeLoadLookupDst.kind := execute.io.loadLookupDst.kind - executeLoadLookupDst.archTag := execute.io.loadLookupDst.archTag - executeLoadLookupDst.relTag := execute.io.loadLookupDst.relTag - executeLoadLookupDst.physTag := execute.io.loadLookupDst.physTag - executeLoadLookupDst.oldPhysTag := execute.io.loadLookupDst.oldPhysTag - - LinxCoreFrontendFetchRfAluTraceTopLiveLoadLiqCaptureWiring.connect( - capture = reducedLiveLoadLiqCapture, - execute = execute, - loadDst = executeLoadLookupDst, - loadLsId = reducedLoadLookupLsId, - loadLsIdFull = execute.io.loadLookupLsId, - enable = reducedLiveLoadLiqEnabled, - flush = reducedStoreFlush) - - reducedLoadWaitReplaySlot.io.flush := reducedStoreFlush - reducedLoadWaitReplaySlot.io.captureValid := - useReducedStoreDispatchStq.B && !useReducedLiveLoadLiq.B && execute.io.loadLookupValid && - reducedStoreResidentForward.io.waitBlocked - reducedLoadWaitReplaySlot.io.capturePc := execute.io.loadLookupPc - reducedLoadWaitReplaySlot.io.captureAddr := execute.io.loadLookupAddr - reducedLoadWaitReplaySlot.io.captureSize := execute.io.loadLookupSize - reducedLoadWaitReplaySlot.io.captureReturnSignExtend := execute.io.loadLookupReturnSignExtend - reducedLoadWaitReplaySlot.io.captureDst := executeLoadLookupDst - reducedLoadWaitReplaySlot.io.captureSourceTraceValid := execute.io.loadLookupSourceTraceValid - reducedLoadWaitReplaySlot.io.captureSource0 := execute.io.loadLookupSource0 - reducedLoadWaitReplaySlot.io.captureSource1 := execute.io.loadLookupSource1 - reducedLoadWaitReplaySlot.io.captureBid := execute.io.loadLookupBid - reducedLoadWaitReplaySlot.io.captureGid := execute.io.loadLookupGid - reducedLoadWaitReplaySlot.io.captureRid := execute.io.loadLookupRid - reducedLoadWaitReplaySlot.io.captureLsId := reducedLoadLookupLsId - reducedLoadWaitReplaySlot.io.captureLsIdFullValid := execute.io.loadLookupValid - reducedLoadWaitReplaySlot.io.captureLsIdFull := execute.io.loadLookupLsId - reducedLoadWaitReplaySlot.io.captureYoungestStoreId := execute.io.loadLookupBid - reducedLoadWaitReplaySlot.io.captureYoungestStoreLsId := reducedLoadLookupLsId - reducedLoadWaitReplaySlot.io.captureYoungestStoreLsIdFullValid := execute.io.loadLookupValid - reducedLoadWaitReplaySlot.io.captureYoungestStoreLsIdFull := execute.io.loadLookupLsId - reducedLoadWaitReplaySlot.io.captureWaitStore := reducedStoreResidentForward.io.waitStore - reducedLoadWaitReplaySlot.io.replayWakeValid := reducedStoreResidentReplayWakeup.io.wakeValid - reducedLoadWaitReplaySlot.io.replayWake := reducedStoreResidentReplayWakeup.io.wake - reducedStoreResidentReplayWakeup.io.enable := useReducedStoreDispatchStq.B - reducedStoreResidentReplayWakeup.io.waitStore := reducedLoadWaitReplaySlot.io.storedWaitStore - reducedStoreResidentReplayWakeup.io.rows := path.io.storeStqRows - reducedLoadReplayRelaunchQueue.io.flush := reducedStoreFlush - reducedLoadReplayRelaunchQueue.io.enqueueValid := - useReducedStoreDispatchStq.B && reducedLoadWaitReplaySlot.io.relaunch.valid - reducedLoadReplayRelaunchQueue.io.enqueue := reducedLoadWaitReplaySlot.io.relaunch - // This legacy-named enable gates the shared LIQ/return machinery for both - // wait-store replays and first-pass ordinary scalar load admission. - val reducedLoadReplayLiqAllocEnabled = - useReducedStoreDispatchStq.B && (useReducedLoadReplayLiqAlloc.B || useReducedLiveLoadLiq.B) - // Legacy replay candidates arrive after a source-return snapshot has already - // owned their row transition. First-pass live loads instead enter LIQ in - // Wait, launch through E2/E3/E4, and only then become return candidates. - // Keeping the source-return mutation path out of live admission prevents it - // from turning a newly allocated row into Repick before LIQ launch accepts. - val reducedReplayLiqLegacySourceReturnEnabled = - reducedLoadReplayLiqAllocEnabled && !reducedLiveLoadLiqEnabled - val reducedReplayLiqCandidateValid = - useReducedStoreDispatchStq.B && useReducedLoadReplayLiqAlloc.B && - reducedLoadReplayRelaunchQueue.io.outValid - val reducedLiqCandidateFromLive = reducedLiveLoadLiqCapture.io.candidateValid - reducedLoadReplayLiqAllocPath.io.flush := reducedStoreFlush - reducedLoadReplayLiqAllocPath.io.candidateValid := - reducedLiqCandidateFromLive || reducedReplayLiqCandidateValid - reducedLoadReplayLiqAllocPath.io.candidate := Mux( - reducedLiqCandidateFromLive, - reducedLiveLoadLiqCapture.io.candidate, - reducedLoadReplayRelaunchQueue.io.out) - reducedLiveLoadLiqCapture.io.allocReady := reducedLoadReplayLiqAllocPath.io.candidateConsumeReady - - val reducedStoreResidentReplayWakeHoldValid = RegInit(false.B) - val reducedStoreResidentReplayWakeHoldAge = RegInit(0.U(4.W)) - val reducedStoreResidentReplayWakeHold = - RegInit(0.U.asTypeOf(chiselTypeOf(reducedStoreResidentReplayWakeup.io.wake))) - val reducedStoreResidentReplayWakeHoldActive = - reducedStoreResidentReplayWakeHoldValid && (reducedStoreResidentReplayWakeHoldAge =/= 0.U) - val reducedStoreResidentReplayWakeForLiqValid = - reducedStoreResidentReplayWakeup.io.wakeValid || reducedStoreResidentReplayWakeHoldActive - val reducedStoreResidentReplayWakeForLiq = - Mux(reducedStoreResidentReplayWakeup.io.wakeValid, reducedStoreResidentReplayWakeup.io.wake, reducedStoreResidentReplayWakeHold) - val reducedMdbReplayWakeValid = WireDefault(false.B) - val reducedMdbReplayWake = Wire(chiselTypeOf(reducedStoreResidentReplayWakeForLiq)) - reducedMdbReplayWake := 0.U.asTypeOf(reducedMdbReplayWake) - val reducedMdbReplayWakeSelected = reducedMdbReplayWakeValid - val reducedStoreResidentReplayWakeSelected = - !reducedMdbReplayWakeSelected && reducedStoreResidentReplayWakeForLiqValid - reducedLoadReplayLiqAllocPath.io.replayWakeValid := - reducedLoadReplayLiqAllocEnabled && - (reducedMdbReplayWakeSelected || reducedStoreResidentReplayWakeSelected) - reducedLoadReplayLiqAllocPath.io.replayWake := - Mux(reducedMdbReplayWakeSelected, reducedMdbReplayWake, reducedStoreResidentReplayWakeForLiq) - val reducedLoadReplayLiqReplayWakeValid = - reducedLoadReplayLiqAllocEnabled && - (reducedMdbReplayWakeSelected || reducedStoreResidentReplayWakeSelected) - val reducedStoreResidentReplayWakeLiqConsumed = - reducedStoreResidentReplayWakeSelected && - (reducedLoadReplayLiqAllocPath.io.replayWakeWaitStoreClearMask.orR || - reducedLoadReplayLiqAllocPath.io.replayWakeMergeMask.orR) - when(reducedStoreFlush || !reducedLoadReplayLiqAllocEnabled) { - reducedStoreResidentReplayWakeHoldValid := false.B - reducedStoreResidentReplayWakeHoldAge := 0.U - }.elsewhen(reducedStoreResidentReplayWakeup.io.wakeValid && !reducedStoreResidentReplayWakeLiqConsumed) { - reducedStoreResidentReplayWakeHoldValid := true.B - reducedStoreResidentReplayWakeHoldAge := "hf".U - reducedStoreResidentReplayWakeHold := reducedStoreResidentReplayWakeup.io.wake - }.elsewhen(reducedStoreResidentReplayWakeLiqConsumed || reducedStoreResidentReplayWakeHoldAge === 0.U) { - reducedStoreResidentReplayWakeHoldValid := false.B - }.elsewhen(reducedStoreResidentReplayWakeHoldValid) { - reducedStoreResidentReplayWakeHoldAge := reducedStoreResidentReplayWakeHoldAge - 1.U - } - reducedReplayLiqStoreSnapshot.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqStoreSnapshot.io.rows := path.io.storeStqRows - reducedReplayLiqSourceReturnStoreSnapshotPath.io.stqRows := path.io.storeStqRows - reducedReplayLiqBaseDataAlign.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqBaseDataAlign.io.loadValid := reducedLoadReplayLiqAllocPath.io.launchValid - reducedReplayLiqBaseDataAlign.io.loadAddr := reducedLoadReplayLiqAllocPath.io.launchSelectedAddr - reducedReplayLiqBaseDataAlign.io.loadSize := reducedLoadReplayLiqAllocPath.io.launchSelectedSize - reducedReplayLiqBaseDataAlign.io.loadData := reducedStoreResidentForward.io.loadData - // First-pass ordinary loads transfer lookup ownership to LIQ. FRET.STK's - // synthetic RA return is explicitly not LIQ eligible, so it must retain the - // direct execute lookup; otherwise the final condition-false return samples - // the idle arbiter's zero data and redirects to address zero. - loadLookupArbiter.io.executeValid := - execute.io.loadLookupValid && (!reducedLiveLoadLiqEnabled || !execute.io.loadLiqEligible) - loadLookupArbiter.io.executeAddr := execute.io.loadLookupAddr - loadLookupArbiter.io.executePc := execute.io.loadLookupPc - loadLookupArbiter.io.replayValid := reducedReplayLiqBaseDataAlign.io.requestValid - loadLookupArbiter.io.replayAddr := reducedLoadReplayLiqAllocPath.io.launchSelectedAddr - loadLookupArbiter.io.replayPc := reducedLoadReplayLiqAllocPath.io.launchSelectedPc - val reducedReplayLiqBaseDataReady = - loadLookupArbiter.io.replayGranted && reducedReplayLiqBaseDataAlign.io.dataReturned - val reducedReplayLiqSelectedRowForStoreSnapshot = - reducedLoadReplayLiqAllocPath.io.rows(reducedLoadReplayLiqAllocPath.io.launchIndex) - val reducedReplayLiqStoreSnapshotLineData = - Mux(reducedReplayLiqBaseDataReady, reducedReplayLiqBaseDataAlign.io.lineData, reducedReplayLiqSelectedRowForStoreSnapshot.lineData) - val reducedReplayLiqStoreSnapshotValidMask = - Mux(reducedReplayLiqBaseDataReady, reducedReplayLiqBaseDataAlign.io.lineValidMask, reducedReplayLiqSelectedRowForStoreSnapshot.validMask) - val reducedReplayLiqRowValidMask = - VecInit((0 until p.robEntries).map(idx => reducedLoadReplayLiqAllocPath.io.rows(idx).valid)).asUInt - val reducedReplayLiqPtrWidth = log2Ceil(p.robEntries) - val reducedReplayLiqHeadValid = reducedReplayLiqRowValidMask.orR - val reducedReplayLiqHeadIndex = - Mux(reducedReplayLiqHeadValid, PriorityEncoder(reducedReplayLiqRowValidMask), 0.U(reducedReplayLiqPtrWidth.W)) - val reducedReplayLiqHeadRow = reducedLoadReplayLiqAllocPath.io.rows(reducedReplayLiqHeadIndex) - val reducedReplayLiqRowScbReturnedMask = - VecInit((0 until p.robEntries).map(idx => - reducedLoadReplayLiqAllocPath.io.rows(idx).valid && reducedLoadReplayLiqAllocPath.io.rows(idx).scbReturned - )).asUInt - val reducedReplayLiqStoreSnapshotHardFlush = - io.frontendFlushValid || io.startValid || io.restartValid || (!useReducedStoreDispatchStq).B || - (path.io.recoveryIntentConsumed && !scalarRedirectRecovery.io.cleanupResolveLsIdValid) - val reducedReplayLiqStoreSnapshotPreciseFlush = - Wire(new FlushBus( - p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth)) - reducedReplayLiqStoreSnapshotPreciseFlush := 0.U.asTypeOf(reducedReplayLiqStoreSnapshotPreciseFlush) - val reducedReplayLiqStoreSnapshotReady = - LinxCoreFrontendFetchRfAluTraceTopR395StoreSnapshotPathWiring.connectInputs( - path = reducedReplayLiqSourceReturnStoreSnapshotPath, - enable = reducedReplayLiqLegacySourceReturnEnabled, - flush = reducedReplayLiqStoreSnapshotHardFlush, - preciseFlush = reducedReplayLiqStoreSnapshotPreciseFlush, - liveArmPolicyEnable = true.B, - liveArmRawSinkAvailable = true.B, - rowMutationLiveEnable = reducedReplayLiqLegacySourceReturnEnabled, - launchValid = reducedLoadReplayLiqAllocPath.io.launchValid, - selectedLaunchIndex = reducedLoadReplayLiqAllocPath.io.launchIndex, - selectedRepickMask = reducedLoadReplayLiqAllocPath.io.repickMask, - selectedRowValidMask = reducedReplayLiqRowValidMask, - selectedRowScbReturnedMask = reducedReplayLiqRowScbReturnedMask, - selectedPickAccepted = reducedLoadReplayLiqAllocPath.io.pickAccepted, - selectedLoadId = reducedLoadReplayLiqAllocPath.io.launchSelectedLoadId, - selectedBid = reducedLoadReplayLiqAllocPath.io.launchSelectedBid, - selectedGid = reducedLoadReplayLiqAllocPath.io.launchSelectedGid, - selectedRid = reducedLoadReplayLiqAllocPath.io.launchSelectedRid, - selectedLoadLsId = reducedLoadReplayLiqAllocPath.io.launchSelectedLoadLsId, - selectedLoadLsIdFullValid = reducedReplayLiqSelectedRowForStoreSnapshot.loadLsIdFullValid, - selectedLoadLsIdFull = reducedReplayLiqSelectedRowForStoreSnapshot.loadLsIdFull, - selectedPeId = io.peId, - selectedStid = io.threadId, - selectedTid = io.threadId, - selectedPc = reducedLoadReplayLiqAllocPath.io.launchSelectedPc, - selectedAddr = reducedLoadReplayLiqAllocPath.io.launchSelectedAddr, - selectedSize = reducedLoadReplayLiqAllocPath.io.launchSelectedSize, - selectedRequestByteMask = reducedLoadReplayLiqAllocPath.io.launchSelectedRequestByteMask, - selectedLineData = reducedReplayLiqStoreSnapshotLineData, - selectedValidMask = reducedReplayLiqStoreSnapshotValidMask, - legacySnapshotReady = reducedReplayLiqLegacySourceReturnEnabled - ) - LinxCoreFrontendFetchRfAluTraceTopR417RowMutationWiring.connect( - source = reducedReplayLiqSourceReturnStoreSnapshotPath, - liqPath = reducedLoadReplayLiqAllocPath, - sourceReadiness = reducedReplayLiqSourceReturnReadiness, - scbLive = reducedReplayLiqSourceReturnScbLiveControl, - enable = reducedReplayLiqLegacySourceReturnEnabled, - flush = reducedStoreFlush, - launchValid = reducedLoadReplayLiqAllocPath.io.launchValid, - baseDataReady = reducedReplayLiqBaseDataReady, - storeSnapshotReady = reducedReplayLiqStoreSnapshotReady) - val reducedReplayLiqReturnLretSinkReady = reducedReplayLiqReturnLretSink.io.preEnqueueReady - val reducedReplayLiqReturnWakeupSinkReady = reducedReplayLiqReturnWakeupSinkReadyControl.io.wakeupSinkReady - val reducedReplayLiqE2BaseData = - Mux(loadLookupArbiter.io.replayGranted, reducedReplayLiqBaseDataAlign.io.lineData, 0.U) - val reducedReplayLiqE2BaseValidMask = - Mux(loadLookupArbiter.io.replayGranted, reducedReplayLiqBaseDataAlign.io.lineValidMask, 0.U) - val (reducedReplayLiqReturnCompleteValid, reducedReplayLiqLaunchReturnPathValid) = - LinxCoreFrontendFetchRfAluTraceTopR489CompleteRepickReturnWiring.connect( - allocPath = reducedLoadReplayLiqAllocPath, - sourceReadiness = reducedReplayLiqSourceReturnReadiness, - consumerReady = reducedReplayLiqReturnConsumerReady, - pipeBudget = reducedReplayLiqReturnPipeBudget, - pipePermit = reducedReplayLiqReturnPipePermit, - pipeSelect = reducedReplayLiqReturnPipeSelect, - returnReadiness = reducedReplayLiqReturnReadiness, - dataExtract = reducedReplayLiqReturnDataExtract, - publishReady = reducedReplayLiqReturnPublishReady, - lretPayload = reducedReplayLiqReturnLretPayload, - enable = reducedLoadReplayLiqAllocEnabled, - allowLaunchDirectReturn = !reducedLiveLoadLiqEnabled, - e2BaseData = reducedReplayLiqE2BaseData, - e2BaseValidMask = reducedReplayLiqE2BaseValidMask, - lretSinkReady = reducedReplayLiqReturnLretSinkReady, - wakeupSinkReady = reducedReplayLiqReturnWakeupSinkReady) - io.reducedLoadReplayLiqLaunchSelectedSourceTraceValid := - reducedLoadReplayLiqAllocPath.io.launchSelectedSourceTraceValid - io.reducedLoadReplayLiqLaunchSelectedSource0Valid := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource0.valid - io.reducedLoadReplayLiqLaunchSelectedSource0Reg := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource0.reg - io.reducedLoadReplayLiqLaunchSelectedSource0Data := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource0.data - io.reducedLoadReplayLiqLaunchSelectedSource1Valid := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource1.valid - io.reducedLoadReplayLiqLaunchSelectedSource1Reg := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource1.reg - io.reducedLoadReplayLiqLaunchSelectedSource1Data := - reducedLoadReplayLiqAllocPath.io.launchSelectedSource1.data - reducedReplayLiqReturnWritebackCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnWritebackCandidate.io.payloadValid := reducedReplayLiqReturnLretPayload.io.payloadValid - reducedReplayLiqReturnWritebackCandidate.io.payloadDst := reducedReplayLiqReturnLretPayload.io.payloadDst - reducedReplayLiqReturnWritebackCandidate.io.payloadData := reducedReplayLiqReturnLretPayload.io.payloadData - reducedReplayLiqReturnWakeupCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnWakeupCandidate.io.payloadValid := reducedReplayLiqReturnLretPayload.io.payloadValid - reducedReplayLiqReturnWakeupCandidate.io.payloadWakeupRequired := reducedReplayLiqReturnLretPayload.io.wakeupRequired - reducedReplayLiqReturnWakeupCandidate.io.payloadDst := reducedReplayLiqReturnLretPayload.io.payloadDst - LinxCoreFrontendFetchRfAluTraceTopR381SideEffectLiveControlWiring.connect( - io = io, - live = reducedReplayLiqReturnSideEffectLiveControl, - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - liveRequested = reducedReplayLiqReturnLretPayload.io.payloadValid, - payloadValid = reducedReplayLiqReturnLretPayload.io.payloadValid, - writebackRequired = reducedReplayLiqReturnWritebackCandidate.io.writeValid, - wakeupRequired = reducedReplayLiqReturnWakeupCandidate.io.wakeupRequired) - LinxCoreFrontendFetchRfAluTraceTopR379WakeupSinkReadyWiring.connect( - io = io, - sink = reducedReplayLiqReturnWakeupSinkReadyControl, - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - liveEnable = reducedReplayLiqReturnSideEffectLiveControl.io.wakeupLiveEnable, - wakeupRequired = reducedReplayLiqReturnWakeupCandidate.io.wakeupRequired) - reducedReplayLiqLaunchReadiness.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqLaunchReadiness.io.launchValid := Mux( - reducedLiveLoadLiqEnabled, - reducedLoadReplayLiqAllocPath.io.launchValid, - reducedReplayLiqLaunchReturnPathValid) - reducedReplayLiqLaunchReadiness.io.baseLookupGranted := loadLookupArbiter.io.replayGranted - reducedReplayLiqLaunchReadiness.io.baseDataReturned := reducedReplayLiqBaseDataAlign.io.dataReturned - reducedReplayLiqLaunchReadiness.io.scbReturned := Mux( - reducedLiveLoadLiqEnabled, - true.B, - reducedReplayLiqSourceReturnReadiness.io.sourceReturned) - // Live ordinary loads reserve their return path after E4. Requiring an LRET - // pipe before E2 launch would make launch wait on the result it must create. - reducedReplayLiqLaunchReadiness.io.returnReady := Mux( - reducedLiveLoadLiqEnabled, - true.B, - reducedReplayLiqReturnReadiness.io.returnReady) - reducedLoadReplayLiqAllocPath.io.launchEnable := reducedReplayLiqLaunchReadiness.io.launchEnable - val reducedReplayLiqMarkResolvedIndex = - Mux(reducedReplayLiqReturnCompleteValid, - reducedLoadReplayLiqAllocPath.io.returnCompleteIndex, - reducedLoadReplayLiqAllocPath.io.launchIndex) - reducedLoadReplayLiqAllocPath.io.markResolvedValid := - reducedReplayLiqReturnPublishRequest.io.lretRequest - reducedLoadReplayLiqAllocPath.io.markResolvedIndex := reducedReplayLiqMarkResolvedIndex - reducedLoadReplayLiqAllocPath.io.e2Stores := reducedReplayLiqStoreSnapshot.io.stores - reducedLoadReplayLiqAllocPath.io.e2BaseData := reducedReplayLiqE2BaseData - reducedLoadReplayLiqAllocPath.io.e2BaseValidMask := reducedReplayLiqE2BaseValidMask - reducedLoadReplayLiqAllocPath.io.e2LoadDataReturned := reducedReplayLiqBaseDataReady - reducedLoadReplayLiqAllocPath.io.e2ScbReturned := Mux( - reducedLiveLoadLiqEnabled, - true.B, - reducedReplayLiqSourceReturnReadiness.io.scbSourceReturned) - reducedLoadReplayLiqAllocPath.io.e2StqReturned := Mux( - reducedLiveLoadLiqEnabled, - true.B, - reducedReplayLiqSourceReturnReadiness.io.storeSourceReturned) - // E2/E3/E4 must be able to produce the live row's first return candidate. - // The LRET pipe is reserved by the post-E4 return owner, so feeding its - // current readiness back into E2 would turn every otherwise-complete live - // load into ReturnPortBlocked and requeue it forever. - reducedLoadReplayLiqAllocPath.io.e2ReturnReady := Mux( - reducedLiveLoadLiqEnabled, - true.B, - reducedReplayLiqReturnReadiness.io.returnReady) - LinxCoreFrontendFetchRfAluTraceTopR453ReplayLiqRefillTieOff.connect(reducedLoadReplayLiqAllocPath) - val reducedLoadReplayResolvePreciseFlush = - Wire(new FlushBus( - p.robEntries, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth)) - reducedLoadReplayResolvePreciseFlush := 0.U.asTypeOf(reducedLoadReplayResolvePreciseFlush) - reducedLoadReplayLiqAllocPath.io.preciseFlush := reducedLoadReplayResolvePreciseFlush - val reducedLoadReplayResolveHardFlush = - io.frontendFlushValid || io.startValid || io.restartValid || (!useReducedStoreDispatchStq).B || - (path.io.recoveryIntentConsumed && !scalarRedirectRecovery.io.cleanupResolveLsIdValid) - reducedLoadReplayResolveQueue.io.flush := reducedLoadReplayResolveHardFlush - reducedLoadReplayResolveQueue.io.preciseFlush := reducedLoadReplayResolvePreciseFlush - val reducedReplayResolvedRowHitRecord = Module(new LoadReplayResolvedRowHitRecord( - liqEntries = p.robEntries, - idEntries = p.robEntries, - storeEntries = coreParams.scalarLsu.stqEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - lineBytes = 64, - sizeWidth = 7, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - val reducedReplayRowMutationResolvedForResolveQ = - reducedLoadReplayLiqAllocEnabled && - reducedLoadReplayLiqAllocPath.io.rowMutationApplyValid && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationRequestValid && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationKeepRepickStatus && - !reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationSetWaitStatus && - !reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationClearReturnState && - !reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextWaitStore && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextDataComplete && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextScbReturned && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextStqReturned && - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextStoreSourceReturned - val reducedReplayResolvedRowHitIndex = - Mux( - reducedReplayRowMutationResolvedForResolveQ, - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationRequestTargetIndex, - reducedReplayLiqMarkResolvedIndex) - reducedReplayResolvedRowHitRecord.io.enable := - reducedLoadReplayLiqAllocEnabled && - (reducedLoadReplayLiqAllocPath.io.markResolvedAccepted || reducedReplayRowMutationResolvedForResolveQ) - reducedReplayResolvedRowHitRecord.io.row := - reducedLoadReplayLiqAllocPath.io.rows(reducedReplayResolvedRowHitIndex) - reducedReplayResolvedRowHitRecord.io.useResolvedImage := reducedReplayRowMutationResolvedForResolveQ - reducedReplayResolvedRowHitRecord.io.resolvedLineData := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextLineData - reducedReplayResolvedRowHitRecord.io.resolvedValidMask := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextValidMask - reducedReplayResolvedRowHitRecord.io.resolvedDataComplete := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextDataComplete - reducedReplayResolvedRowHitRecord.io.resolvedSourcesReturned := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextStoreSourceReturned - reducedReplayResolvedRowHitRecord.io.resolvedScbReturned := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextScbReturned - reducedReplayResolvedRowHitRecord.io.resolvedStqReturned := - reducedReplayLiqSourceReturnStoreSnapshotPath.io.rowMutationNextStqReturned - // A first-pass live row remains resident through W2, where the normal - // resolve/writeback/wakeup owner consumes its LRET. The older replay path - // still mirrors its LHQ record into ResolveQ and uses that queue's clear - // ownership; doing so for a live row would clear the resolved LIQ entry - // before W2 can establish the matching lifecycle proof. - val reducedLoadReplayResolvePushFromLhq = - !reducedLiveLoadLiqEnabled && reducedLoadReplayLiqAllocPath.io.lhqRecordValid - val reducedLoadReplayResolvePushFromReplay = - reducedReplayResolvedRowHitRecord.io.recordValid && !reducedLoadReplayResolvePushFromLhq - val reducedLoadReplayResolvePushRecord = - Mux( - reducedLoadReplayResolvePushFromLhq, - reducedLoadReplayLiqAllocPath.io.lhqRecord, - reducedReplayResolvedRowHitRecord.io.record) - reducedLoadReplayResolveQueue.io.pushValid := - reducedLoadReplayLiqAllocEnabled && - (reducedLoadReplayResolvePushFromLhq || reducedLoadReplayResolvePushFromReplay) - reducedLoadReplayResolveQueue.io.pushPeId := io.peId - reducedLoadReplayResolveQueue.io.pushStid := io.threadId - reducedLoadReplayResolveQueue.io.pushTid := io.threadId - reducedLoadReplayResolveQueue.io.pushRecord := reducedLoadReplayResolvePushRecord - val reducedLoadReplayResolveRetireSource = Wire(chiselTypeOf(path.io.commitMemoryOrder(0))) - reducedLoadReplayResolveRetireSource := 0.U.asTypeOf(reducedLoadReplayResolveRetireSource) - for (slot <- 0 until traceParams.commitWidth) { - when(path.io.commitMemoryOrder(slot).valid) { - reducedLoadReplayResolveRetireSource := path.io.commitMemoryOrder(slot) - } - } - val reducedLoadReplayResolveRetireLsId = lsidToReducedStoreId(reducedLoadReplayResolveRetireSource.lsId) - val reducedLoadReplayResolveClearRetireRow = - reducedLoadReplayLiqAllocPath.io.rows(reducedLoadReplayResolveClearIndex) - val reducedLoadReplayResolveClearRetireValid = - reducedLoadReplayLiqAllocEnabled && - reducedLoadReplayResolveClearPending && - reducedLoadReplayLiqAllocPath.io.clearResolvedAccepted && - reducedLoadReplayResolveClearRetireRow.valid - val reducedLoadReplayResolveLifecycleRetireRow = - reducedLoadReplayLiqAllocPath.io.rows(reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady.io.rowClearIndex) - val reducedLoadReplayResolveLifecycleRetireValid = - reducedLoadReplayLiqAllocEnabled && - reducedReplayLiqReturnPipeW2Modules.replayRowClearRequest.io.lifecycleClearAccepted && - reducedLoadReplayResolveLifecycleRetireRow.valid - reducedLoadReplayResolveQueue.io.retireValid := - (reducedLoadReplayLiqAllocEnabled && reducedLoadReplayResolveRetireSource.valid) || - reducedLoadReplayResolveClearRetireValid || - reducedLoadReplayResolveLifecycleRetireValid - reducedLoadReplayResolveQueue.io.retireBid := - Mux( - reducedLoadReplayResolveClearRetireValid, - reducedLoadReplayResolveClearRetireRow.bid, - Mux( - reducedLoadReplayResolveLifecycleRetireValid, - reducedLoadReplayResolveLifecycleRetireRow.bid, - reducedLoadReplayResolveRetireSource.bid)) - reducedLoadReplayResolveQueue.io.retireLsId := - Mux( - reducedLoadReplayResolveClearRetireValid, - reducedLoadReplayResolveClearRetireRow.loadLsId, - Mux( - reducedLoadReplayResolveLifecycleRetireValid, - reducedLoadReplayResolveLifecycleRetireRow.loadLsId, - reducedLoadReplayResolveRetireLsId)) - reducedLoadReplayResolveQueue.io.retireLsIdFullValid := - Mux( - reducedLoadReplayResolveClearRetireValid, - reducedLoadReplayResolveClearRetireRow.loadLsIdFullValid, - Mux( - reducedLoadReplayResolveLifecycleRetireValid, - reducedLoadReplayResolveLifecycleRetireRow.loadLsIdFullValid, - reducedLoadReplayResolveRetireSource.valid && reducedLoadReplayResolveRetireSource.isLoadStore)) - reducedLoadReplayResolveQueue.io.retireLsIdFull := - Mux( - reducedLoadReplayResolveClearRetireValid, - reducedLoadReplayResolveClearRetireRow.loadLsIdFull, - Mux( - reducedLoadReplayResolveLifecycleRetireValid, - reducedLoadReplayResolveLifecycleRetireRow.loadLsIdFull, - reducedLoadReplayResolveRetireSource.lsId)) - val reducedMdbFanoutStoreRows = Wire(Vec( - coreParams.scalarLsu.stqEntries, - new MDBStoreWakeupEntry( - p.robEntries, - coreParams.scalarLsu.stqEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - stidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth - ) - )) - for (idx <- 0 until coreParams.scalarLsu.stqEntries) { - val stqRow = path.io.storeStqRows(idx) - val wakeRow = Wire(chiselTypeOf(reducedMdbFanoutStoreRows(idx))) - wakeRow := 0.U.asTypeOf(wakeRow) - wakeRow.bid := ROBID.disabled(p.robEntries) - wakeRow.lsId := ROBID.disabled(p.robEntries) - wakeRow.valid := reducedLoadReplayLiqAllocEnabled && stqRow.valid - wakeRow.storeIndex := idx.U - wakeRow.pc := stqRow.pc - wakeRow.bid := stqRow.bid - wakeRow.lsId := stqRow.lsId - wakeRow.stid := stqRow.stid - wakeRow.addr := stqRow.addr - wakeRow.size := stqRow.size.pad(7) - wakeRow.addrReady := stqRow.addrReady - wakeRow.dataReady := stqRow.dataReady - wakeRow.isTile := !stqRow.scalarIex - reducedMdbFanoutStoreRows(idx) := wakeRow - } - - reducedMdbPath.io.flush := reducedStoreFlush || !reducedLoadReplayLiqAllocEnabled - reducedMdbPath.io.storeRows := reducedMdbFanoutStoreRows - reducedMdbPath.io.loadRows := reducedLoadReplayLiqAllocPath.io.rows - reducedMdbPath.io.resolvedRows := reducedLoadReplayResolveQueue.io.conflictRows - val reducedMdbConflictStoreProbe = - LinxCoreFrontendFetchRfAluTraceTopR660MdbStoreAdmissionWiring.connect( - p, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush, - path, - reducedLoadReplayLiqAllocPath, - reducedLoadReplayResolveQueue, - reducedMdbPath - ) - reducedMdbReplayWakeValid := reducedMdbPath.io.storeWakeup.valid - reducedMdbReplayWake.source := LoadReplayWakeSource.StoreUnit - reducedMdbReplayWake.storeId := reducedMdbPath.io.storeWakeup.bid - reducedMdbReplayWake.storeLsId := reducedMdbPath.io.storeWakeup.lsId - reducedMdbReplayWake.storeLsIdFullValid := reducedMdbPath.io.storeWakeup.lsIdFullValid - reducedMdbReplayWake.storeLsIdFull := reducedMdbPath.io.storeWakeup.lsIdFull - reducedMdbReplayWake.pc := reducedMdbPath.io.storeWakeup.pc - reducedMdbReplayWake.lineAddr := Cat( - reducedMdbPath.io.storeWakeup.addr(p.immWidth - 1, log2Ceil(64)), - 0.U(log2Ceil(64).W) - ) - reducedMdbReplayWake.validMask := 0.U - reducedMdbReplayWake.data := 0.U - - val reducedMdbAllocPayload = reducedLoadReplayLiqAllocPath.io.allocPayload - val reducedMdbFanoutLookupValid = - reducedLoadReplayLiqAllocEnabled && - reducedLoadReplayLiqAllocPath.io.allocAccepted && - !reducedMdbAllocPayload.isTile - reducedMdbPath.io.loadLookupValid := reducedMdbFanoutLookupValid - reducedMdbPath.io.loadLookup := reducedMdbAllocPayload - reducedLoadReplayLiqAllocPath.io.allocExternalReady := - !reducedLoadReplayLiqAllocEnabled || - reducedMdbPath.io.loadLookupReady - assert( - !reducedLoadReplayLiqAllocEnabled || - (reducedLoadReplayLiqAllocPath.io.allocAccepted === reducedMdbPath.io.lookupAccepted), - "replay LIQ allocation and canonical MDB lookup must be accepted atomically" - ) - - val (reducedMdbMutationAccepted, reducedMdbLookupWaitPlanBridge) = - LinxCoreFrontendFetchRfAluTraceTopR659CanonicalMdbMutationWiring.connect( - p = p, - io = io, - source = reducedReplayLiqSourceReturnStoreSnapshotPath, - mdb = reducedMdbPath, - liqPath = reducedLoadReplayLiqAllocPath, - storeEntries = coreParams.scalarLsu.stqEntries - ) - reducedMdbPath.io.mutationAccepted := reducedMdbMutationAccepted - - val reducedMdbRecoveryBoundary = Module(new ScalarLSURecoveryBoundary( - entries = p.robEntries, - stidCount = scalarStidCount, - bidWidth = traceParams.blockBidWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - lsidWidth = p.lsidWidth - )) - val reducedMdbRecoveryRingReq = Wire(chiselTypeOf(reducedMdbPath.io.recoveryFlush)) - reducedMdbRecoveryRingReq := reducedMdbPath.io.recoveryFlush - reducedMdbRecoveryRingReq.req.valid := reducedMdbPath.io.recoveryValid - reducedMdbRecoveryBoundary.io.ringReq := reducedMdbRecoveryRingReq - reducedMdbRecoveryBoundary.io.oldestValid := path.io.recoveryOldestValid - reducedMdbRecoveryBoundary.io.oldestBid := path.io.recoveryOldestBid - reducedMdbRecoveryBoundary.io.oldestRid := path.io.recoveryOldestRid - reducedMdbRecoveryBoundary.io.fullBidLookup := path.io.lsuFullBidLookup - reducedMdbRecoveryBoundary.io.sourceReady := path.io.lsuRecoverySourceReady - reducedMdbPath.io.recoveryReady := reducedMdbRecoveryBoundary.io.ringReqReady - path.io.lsuRecoverySource := reducedMdbRecoveryBoundary.io.source - path.io.lsuFullBidLookupRequest := reducedMdbRecoveryBoundary.io.fullBidLookupRequest - - val reducedMdbFanoutRecordValid = reducedMdbPath.io.recordValid - when(reducedStoreFlush || !reducedLoadReplayLiqAllocEnabled) { - reducedLoadReplayResolveClearPending := false.B - }.otherwise { - when(reducedReplayLiqReturnPipeW2Modules.replayRowClearRequest.io.existingClearAccepted) { - reducedLoadReplayResolveClearPending := false.B - } - when(reducedLoadReplayResolveQueue.io.pushAccepted && reducedLoadReplayResolvePushFromLhq) { - reducedLoadReplayResolveClearPending := true.B - reducedLoadReplayResolveClearIndex := reducedLoadReplayResolvePushRecord.loadId.value - } - } - val reducedCompleteLoadLsId = lsidToReducedStoreId(execute.io.completeLsId) - reducedLoadReplayCompletionDrain.io.candidateValid := - reducedLoadReplayRelaunchQueue.io.outValid && !reducedLoadReplayLiqAllocEnabled - reducedLoadReplayCompletionDrain.io.candidate := reducedLoadReplayRelaunchQueue.io.out - reducedLoadReplayCompletionDrain.io.completeValid := - useReducedStoreDispatchStq.B && !reducedLoadReplayLiqAllocEnabled && execute.io.completeFire - reducedLoadReplayCompletionDrain.io.completeMemLoad := - execute.io.completeRow.mem.valid && !execute.io.completeRow.mem.isStore - reducedLoadReplayCompletionDrain.io.completePc := execute.io.completeRow.pc - reducedLoadReplayCompletionDrain.io.completeAddr := execute.io.completeRow.mem.addr - reducedLoadReplayCompletionDrain.io.completeSize := execute.io.completeRow.mem.size - reducedLoadReplayCompletionDrain.io.completeBid := execute.io.releaseBid - reducedLoadReplayCompletionDrain.io.completeGid := execute.io.releaseGid - reducedLoadReplayCompletionDrain.io.completeRid := execute.io.releaseRid - reducedLoadReplayCompletionDrain.io.completeLsId := reducedCompleteLoadLsId - reducedLoadReplayRelaunchQueue.io.outReady := Mux( - reducedLoadReplayLiqAllocEnabled, - reducedLoadReplayLiqAllocPath.io.candidateConsumeReady && !reducedLiqCandidateFromLive, - reducedLoadReplayCompletionDrain.io.consumeReady - ) - - path.io.storeMarkCommitValid := storeCommitOwner.io.markCommitValid - path.io.storeMarkCommitIndex := storeCommitOwner.io.markCommitIndex - path.io.storeCommitFreeValid := false.B - path.io.storeCommitFreeIndex := 0.U - path.io.storeCommitFreeMaskValid := useReducedStoreDispatchStq.B && reducedStoreScb.io.commitFreeMaskValid - path.io.storeCommitFreeMask := Mux(useReducedStoreDispatchStq.B, reducedStoreScb.io.commitFreeMask, 0.U) - path.io.checkpointValid := false.B - path.io.checkpointBid := ROBID.disabled(p.robEntries) - path.io.checkpointStid := 0.U - path.io.commitValid := false.B - path.io.commitBid := ROBID.disabled(p.robEntries) - path.io.commitBlockBid := 0.U - path.io.commitStid := 0.U - path.io.recoveryNonLsuSources := 0.U.asTypeOf(path.io.recoveryNonLsuSources) - path.io.recoveryNonLsuSources(0) := scalarRedirectRecovery.io.source - DecodeRenameROBPath.tieOffDirectRecovery(path) - path.io.recoveryIntentReady := true.B - - val acceptedRecoveryFlush = Wire(chiselTypeOf(path.io.recoveryIntent.flush)) - acceptedRecoveryFlush := path.io.recoveryIntent.flush - acceptedRecoveryFlush.req.valid := path.io.recoveryIntentConsumed - // Replay STQ request/response queues are MemReq-shaped; prune by load LSID, not ROB RID. - reducedReplayLiqStoreSnapshotPreciseFlush := acceptedRecoveryFlush - reducedReplayLiqStoreSnapshotPreciseFlush.req.valid := - reducedLoadReplayLiqAllocEnabled && path.io.recoveryIntentConsumed && - scalarRedirectRecovery.io.cleanupResolveLsIdValid - reducedReplayLiqStoreSnapshotPreciseFlush.req.lsId := scalarRedirectRecovery.io.cleanupLsId - reducedLoadReplayResolvePreciseFlush := acceptedRecoveryFlush - reducedLoadReplayResolvePreciseFlush.req.valid := - reducedLoadReplayLiqAllocEnabled && path.io.recoveryIntentConsumed && - scalarRedirectRecovery.io.cleanupResolveLsIdValid - // ResolveQ is MemReq-shaped; scalar precise pruning compares BID plus LSID, not ROB RID. - reducedLoadReplayResolvePreciseFlush.req.lsId := scalarRedirectRecovery.io.cleanupLsId - path.io.scalarCleanupOrderValid := scalarRedirectRecovery.io.cleanupOrderValid - path.io.scalarCleanupOrder := scalarRedirectRecovery.io.cleanupOrder - - val scalarScIssueFire = WireDefault(false.B) - val scalarScIssueAddr = WireDefault(0.U(p.immWidth.W)) - val scalarScIssueData = WireDefault(0.U(p.immWidth.W)) - val scalarScIssueUop = WireDefault(0.U.asTypeOf(issue.io.issueUop)) - val scalarScHandshake = Module(new ScalarScTopHandshake( - p = p, - traceParams = traceParams, - scbRequestCount = reducedStoreScbRequestCount, - stqEntries = coreParams.scalarLsu.stqEntries)) - scalarScHandshake.io.flush := reducedStoreFlush - scalarScHandshake.io.issueFire := scalarScIssueFire - scalarScHandshake.io.issueUop := scalarScIssueUop - scalarScHandshake.io.issueAddr := scalarScIssueAddr - scalarScHandshake.io.issueData := scalarScIssueData - scalarScHandshake.io.ownerScReqReady := scalarLrScReservationOwner.io.scReqReady - scalarScHandshake.io.ownerScReqAccepted := scalarLrScReservationOwner.io.scReqAccepted - scalarScHandshake.io.ownerScSuccess := scalarLrScReservationOwner.io.scSuccess - scalarScHandshake.io.ownerScStatus := scalarLrScReservationOwner.io.scStatus - scalarScHandshake.io.ownerScStoreData := scalarLrScReservationOwner.io.scStoreData - scalarScHandshake.io.ownerScCompleteFire := scalarLrScReservationOwner.io.scCompleteFire - scalarScHandshake.io.storeScSelectedSuccess := path.io.storeScSelectedSuccess - scalarScHandshake.io.storeScSelectedMissDiscard := path.io.storeScSelectedMissDiscard - scalarScHandshake.io.storeStqInsertAccepted := path.io.storeStqInsertAccepted - scalarScHandshake.io.scbAcceptedMask := reducedStoreScb.io.acceptedMask - scalarScHandshake.io.scbAcceptedReqs := reducedStoreScb.io.acceptedReqs - scalarScHandshake.io.serviceCompleteValid := servicePath.io.completeValid - - LinxCoreFrontendFetchRfAluTraceTopRobCompleteArbiterWiring.connect( - io, - path, - robCompleteArbiter, - executeCompletionRetainer, - execute, - servicePath, - scalarScHandshake.io.completeValid, - scalarScHandshake.io.completeRow, - scalarScHandshake.io.completeRobValue, - reducedReplayLiqReturnPipeW2Modules.robCompleteSource, - reducedReplayLiqReturnPipeW2Modules.retireRecordRobCompleteFallbackGuard, - reducedReplayLiqRetainedOwnerFallbackLiveProbe.B, - reducedReplayLiqReturnPipeW2Modules.retireRecordPhysicalBundleSuppressLiveMask.io.suppressRobComplete - ) - LinxCoreFrontendFetchRfAluTraceTopScalarLrReservationWiring.connect( - io = io, - owner = scalarLrScReservationOwner, - arbiter = robCompleteArbiter, - execute = execute, - robCompleteAccepted = path.io.completeAccepted, - acceptedRecoveryFlush = acceptedRecoveryFlush, - reducedStoreMemoryReqs = reducedStoreMemoryReqs, - reducedStoreMemoryAcceptedVec = reducedStoreMemoryAcceptedVec, - reducedStoreMemoryRequestCount = reducedStoreMemoryRequestCount, - scalarScIssueFire = scalarScIssueFire, - scalarScIssueStid = scalarScHandshake.io.ownerScReqStid, - scalarScIssueLineAddr = scalarScHandshake.io.ownerScReqLineAddr, - scalarScIssueData = scalarScHandshake.io.ownerScReqData, - scalarScIssueBid = scalarScHandshake.io.ownerScReqBid, - scalarScIssueGid = scalarScHandshake.io.ownerScReqGid, - scalarScIssueRid = scalarScHandshake.io.ownerScReqRid, - scalarScIssueLsId = scalarScHandshake.io.ownerScReqLsId, - scalarScCommitReady = scalarScHandshake.io.ownerScCommitReady, - coreParams = coreParams, - p = p) - path.io.storeScResultValid := scalarScHandshake.io.storeScResultValid - path.io.storeScResultSuccess := scalarScHandshake.io.storeScResultSuccess - path.io.storeScResultIdentity := scalarScHandshake.io.storeScResultIdentity - path.io.storeScStoreData := scalarScHandshake.io.storeScStoreData - path.io.scalarRedirectValid := execute.io.redirectValid - path.io.scalarRedirectStid := execute.io.releaseStid - path.io.deallocReady := io.deallocReady - - issue.io.inValid := path.io.renamedOutValid && path.io.renamedOutReady - issue.io.in := path.io.renamedOut - val serviceEnqueueFire = issue.io.inputAcceptFire && issue.io.inputAcceptUop.opcode === serviceOpcode - val serviceStopInfo = LinxCoreFrontendFetchRfAluTraceTopServiceStopMetadataWiring.connect( - io, - path, - issue, - servicePath, - serviceOpcode, - serviceEnqueueFire, - admittedMarkerDrainFire || skippedMarkerLifecycleFire, - backendPipeFlush) - val serviceIssueCandidate = serviceStopInfo.issueCandidate - val serviceStopAdjacent = serviceStopInfo.stopAdjacent - val serviceNextStopInsn = serviceStopInfo.nextStopInsn - val serviceNextStopLen = serviceStopInfo.nextStopLen - val serviceReplayCompleteValid = - Mux( - reducedReplayLiqRetainedOwnerFallbackLiveProbe.B, - reducedReplayLiqReturnPipeW2Modules.retireRecordRobCompleteFallbackGuard.io.fallbackCompleteValid, - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.completeValid && - !reducedReplayLiqReturnPipeW2Modules.retireRecordPhysicalBundleSuppressLiveMask.io.suppressRobComplete) - val serviceHigherPriorityRobCompleteIdle = - !execute.io.completeValid && !serviceReplayCompleteValid - val serviceHigherPriorityWritebackIdle = - !rfWritebackArbiter.io.selectedExecute && !rfWritebackArbiter.io.selectedReplay - LinxCoreFrontendFetchRfAluTraceTopServicePathWiring.connect( - io, - path, - issue, - execute, - servicePath, - serviceEnqueueFire, - serviceIssueCandidate, - serviceStopAdjacent, - serviceNextStopInsn, - serviceNextStopLen, - backendPipeFlush, - serviceHigherPriorityRobCompleteIdle, - serviceHigherPriorityWritebackIdle - ) - val scalarScIssueGate = LinxCoreFrontendFetchRfAluTraceTopScalarScIssueWiring.connect( - issue, - path, - storeStaAddressExecBridge, - scalarLrScReservationOwner, - scalarScIssueFire, - scalarScIssueAddr, - scalarScIssueData, - scalarScIssueUop, - p) - - issue.io.flushValid := backendPipeFlush - issue.io.scalarSpHeadValidByStid := scalarSpOrder.io.issueHeadValidByStid - issue.io.scalarSpHeadBidByStid := scalarSpOrder.io.issueHeadBidByStid - issue.io.scalarSpHeadRidByStid := scalarSpOrder.io.issueHeadRidByStid - issue.io.scalarSpSnapshotByStid := scalarSpOrder.io.issueSnapshotByStid - LinxCoreFrontendFetchRfAluTraceTopIssueReleaseWiring.connect( - issue, - execute, - servicePath, - scalarScHandshake.io.releaseValid, - scalarScHandshake.io.releaseBid, - scalarScHandshake.io.releaseRid, - scalarScHandshake.io.releaseStid, - markerIssueControlFence, - io.frontendFlushValid || io.restartValid || io.startValid || backendPipeFlush) - issue.io.readyMask := rf.io.readyMask - issue.io.pWakeupValid := rf.io.write(0).fire - issue.io.pWakeupTag := rf.io.write(0).tag - issue.io.localTReadyMask := localTReady.asUInt - issue.io.localUReadyMask := localUReady.asUInt - - val rfInitTagInRange = io.rfInitArchTag < archRegs.U - rf.io.initValid := io.rfInitValid && rfInitTagInRange - rf.io.initTag := io.rfInitArchTag - rf.io.initData := io.rfInitData - LinxCoreFrontendFetchRfAluTraceTopRfReadWiring.connect( - rf, - issue, - path, - storeStaAddressExecBridge, - scalarSpOrder, - localTData, - localUData, - localTReady, - localUReady, - coreParams.scalarBackend.gprReadPorts, - useReducedStoreStaAddressExecBridge.B && useReducedStoreDispatchStq.B, - scalarStidCount) - LinxCoreFrontendFetchRfAluTraceTopServiceRfReadWiring.connect( - rf, - servicePath, - serviceRfReadPort = coreParams.scalarBackend.gprReadPorts + 4 - ) - rf.io.clearValid := issue.io.inputAcceptDstValid - rf.io.clearTag := issue.io.inputAcceptDstTag - LinxCoreFrontendFetchRfAluTraceTopWritebackPrimaryWiring.connect( - rfWritebackArbiter, - execute, - servicePath, - scalarScHandshake.io.writebackValid, - scalarScHandshake.io.writebackTag, - scalarScHandshake.io.writebackData, - templateContext, - p.physRegWidth, - p.immWidth - ) - val reducedReplayLiqRetainedOwnerFallbackLiveProbeActive = - reducedReplayLiqRetainedOwnerFallbackLiveProbe.B && - reducedReplayLiqReturnPipeW2Modules.retireRecordFallbackOwnerPolicy.io.sideEffectOwnerEnable - val reducedReplayLiqRetainedOwnerFallbackRfWritebackValid = - reducedReplayLiqRetainedOwnerFallbackLiveProbeActive && - reducedReplayLiqReturnPipeW2Modules.retireRecordRfWritebackFallbackGuard.io.fallbackWritebackValid - LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackRfWritebackMuxWiring.connect( - rfWritebackArbiter, - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl, - reducedReplayLiqReturnPipeW2Modules.writebackArbiterInput, - reducedReplayLiqReturnPipeW2Modules.retireRecordRfWritebackFallbackGuard, - reducedReplayLiqRetainedOwnerFallbackLiveProbe.B, - reducedReplayLiqRetainedOwnerFallbackRfWritebackValid, - reducedReplayLiqReturnPipeW2Modules.retireRecordPhysicalBundleSuppressLiveMask.io.suppressRfWriteback - ) - val reducedReplayLiqRfWritebackSinkReady = - reducedReplayLiqReturnWritebackSinkReadyControl.io.writebackSinkReady - LinxCoreFrontendFetchRfAluTraceTopR380WritebackSinkReadyWiring.connect( - io = io, - sink = reducedReplayLiqReturnWritebackSinkReadyControl, - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - liveEnable = reducedReplayLiqReturnSideEffectLiveControl.io.writebackLiveEnable, - writebackRequired = reducedReplayLiqReturnWritebackCandidate.io.writeValid, - sinkReady = !rfWritebackArbiter.io.selectedExecute) - LinxCoreFrontendFetchRfAluTraceTopR381ReturnPublishWiring.connect( - sideEffectReady = reducedReplayLiqReturnSideEffectReady, - publishControl = reducedReplayLiqReturnPublishControl, - publishRequest = reducedReplayLiqReturnPublishRequest, - lretPayload = reducedReplayLiqReturnLretPayload, - publishReady = reducedReplayLiqReturnPublishReady, - writebackCandidate = reducedReplayLiqReturnWritebackCandidate, - wakeupCandidate = reducedReplayLiqReturnWakeupCandidate, - enable = reducedLoadReplayLiqAllocEnabled, - lretSinkReady = reducedReplayLiqReturnLretSinkReady, - writebackSinkReady = reducedReplayLiqRfWritebackSinkReady, - wakeupSinkReady = reducedReplayLiqReturnWakeupSinkReady, - publishLiveEnable = reducedReplayLiqReturnSideEffectLiveControl.io.publishLiveEnable) - val reducedReplayLiqReturnLretSinkEntry = Wire(new LoadReplayReturnLretEntry( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - lsidWidth = p.lsidWidth - )) - LinxCoreFrontendFetchRfAluTraceTopR388IexPipeOccupancyLiveWiring.connect( - live = reducedReplayLiqReturnIexPipeOccupancyLiveControl, - occupancy = reducedReplayLiqReturnIexPipeOccupancy, - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - requestEnable = reducedReplayLiqReturnLretSink.io.drainValid, - sourceValid = reducedReplayLiqReturnLretSink.io.drainValid, - // IEX drain is allowed only when the residency stage can retain the - // payload. Reporting an always-empty mask lets LRET consume a second - // return while the single residency slot is occupied, which drops that - // load before W1/W2 can complete it. - sourceMask = reducedReplayLiqReturnPipeResidencySlot.io.occupied.asUInt - ) - val reducedReplayLiqReturnIexPipeOccupiedMask = - reducedReplayLiqReturnIexPipeOccupancy.io.pipeOccupiedMask - LinxCoreFrontendFetchRfAluTraceTopR547LretSetMemDataWiring.connect( - path = path, - liqPath = reducedLoadReplayLiqAllocPath, - payload = reducedReplayLiqReturnLretPayload, - sinkEntry = reducedReplayLiqReturnLretSinkEntry, - sink = reducedReplayLiqReturnLretSink, - drainPermit = reducedReplayLiqReturnIexDrainPermit, - iexData = reducedReplayLiqReturnIexDataCandidate, - pipeOccupiedMask = reducedReplayLiqReturnIexPipeOccupiedMask, - enqueueValid = reducedReplayLiqReturnPublishRequest.io.lretRequest, - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - hardFlush = io.frontendFlushValid || io.startValid || io.restartValid, - preciseFlush = acceptedRecoveryFlush, - entries = p.robEntries) - reducedReplayLiqReturnRobResolveDataCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnRobResolveDataCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnRobResolveDataCandidate.io.setMemDataValid := - reducedReplayLiqReturnIexDataCandidate.io.setMemDataValid - reducedReplayLiqReturnRobResolveDataCandidate.io.memRid := - reducedReplayLiqReturnIexDataCandidate.io.memRid - reducedReplayLiqReturnRobResolveDataCandidate.io.memDst := - reducedReplayLiqReturnIexDataCandidate.io.memDst - reducedReplayLiqReturnRobResolveDataCandidate.io.memData := - reducedReplayLiqReturnIexDataCandidate.io.memData - reducedReplayLiqReturnLaneCompletionCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnLaneCompletionCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnLaneCompletionCandidate.io.resolveValid := - reducedReplayLiqReturnRobResolveDataCandidate.io.readyForPipeInsert - reducedReplayLiqReturnTloadCompletionCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnTloadCompletionCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnTloadCompletionCandidate.io.laneCompletionValid := - reducedReplayLiqReturnLaneCompletionCandidate.io.readyForPipeInsert - LinxCoreFrontendFetchRfAluTraceTopR386ReducedScalarShapeWiring.connect( - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - shape = reducedReplayLiqReturnReducedScalarShapeControl, - robResolve = reducedReplayLiqReturnRobResolveDataCandidate, - lane = reducedReplayLiqReturnLaneCompletionCandidate, - tload = reducedReplayLiqReturnTloadCompletionCandidate, - residency = reducedReplayLiqReturnPipeResidencyCandidate) - reducedReplayLiqReturnFinalMetadataCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnFinalMetadataCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnFinalMetadataCandidate.io.tloadCompletionValid := - reducedReplayLiqReturnTloadCompletionCandidate.io.readyForPipeInsert - reducedReplayLiqReturnTimingStatsCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnTimingStatsCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnTimingStatsCandidate.io.finalMetadataValid := - reducedReplayLiqReturnFinalMetadataCandidate.io.readyForPipeInsert - reducedReplayLiqReturnTimingStatsCandidate.io.currentCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memLsuRecvCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memLdqPickCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memLdqIssueCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memL1MissCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memL2MissCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memMemRntCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memL2RntCycle := 0.U - reducedReplayLiqReturnTimingStatsCandidate.io.memL1RntCycle := 0.U - reducedReplayLiqReturnIexPipeInsertCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnIexPipeInsertCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnIexPipeInsertCandidate.io.setMemDataValid := - reducedReplayLiqReturnTimingStatsCandidate.io.readyForPipeInsert - reducedReplayLiqReturnIexPipeInsertCandidate.io.pipeInsertReady := - reducedReplayLiqReturnIexDrainPermit.io.drainReady - reducedReplayLiqReturnIexPipeInsertCandidate.io.pipeInsertIndex := - reducedReplayLiqReturnIexDrainPermit.io.selectedPipeIndex - reducedReplayLiqReturnIexPipeInsertCandidate.io.memBid := - reducedReplayLiqReturnIexDataCandidate.io.memBid - reducedReplayLiqReturnIexPipeInsertCandidate.io.memGid := - reducedReplayLiqReturnIexDataCandidate.io.memGid - reducedReplayLiqReturnIexPipeInsertCandidate.io.memRid := - reducedReplayLiqReturnIexDataCandidate.io.memRid - reducedReplayLiqReturnIexPipeInsertCandidate.io.memLoadLsId := - reducedReplayLiqReturnIexDataCandidate.io.memLoadLsId - reducedReplayLiqReturnIexPipeInsertCandidate.io.memPc := - reducedReplayLiqReturnIexDataCandidate.io.memPc - reducedReplayLiqReturnIexPipeInsertCandidate.io.memAddr := - reducedReplayLiqReturnIexDataCandidate.io.memAddr - reducedReplayLiqReturnIexPipeInsertCandidate.io.memSize := - reducedReplayLiqReturnIexDataCandidate.io.memSize - reducedReplayLiqReturnIexPipeInsertCandidate.io.memDst := - reducedReplayLiqReturnIexDataCandidate.io.memDst - reducedReplayLiqReturnIexPipeInsertCandidate.io.memData := - reducedReplayLiqReturnIexDataCandidate.io.memData - reducedReplayLiqReturnIexPipeInsertCandidate.io.memLoadToUsePipeIndex := - reducedReplayLiqReturnIexDataCandidate.io.memPipeIndex - reducedReplayLiqReturnIexPipeInsertCandidate.io.memSpecWakeup := - reducedReplayLiqReturnIexDataCandidate.io.memSpecWakeup - reducedReplayLiqReturnIexPipeInsertCandidate.io.memStackValid := - reducedReplayLiqReturnIexDataCandidate.io.memStackValid - reducedReplayLiqReturnPipeResidencyCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeResidencyCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeResidencyCandidate.io.insertCandidateValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.candidateValid - reducedReplayLiqReturnPipeResidencyCandidate.io.insertValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertValid - reducedReplayLiqReturnPipeResidencyLiveControl.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeResidencyLiveControl.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeResidencyLiveControl.io.requestEnable := - reducedReplayLiqReturnIexPipeInsertCandidate.io.candidateValid - reducedReplayLiqReturnPipeResidencyLiveControl.io.insertCandidateValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.candidateValid - reducedReplayLiqReturnPipeResidencyLiveControl.io.insertValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertValid - reducedReplayLiqReturnPipeResidencyLiveControl.io.selectedPipeOccupied := - !reducedReplayLiqReturnIexDrainPermit.io.anyPipeFree - reducedReplayLiqReturnPipeResidencyCandidate.io.liveEnable := - reducedReplayLiqReturnPipeResidencyLiveControl.io.liveEnable - reducedReplayLiqReturnPipeResidencyCandidate.io.selectedPipeIndex := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertPipeIndex - reducedReplayLiqReturnPipeResidencyCandidate.io.selectedPipeOccupied := - !reducedReplayLiqReturnIexDrainPermit.io.anyPipeFree - reducedReplayLiqReturnPipeResidencySlot.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeResidencySlot.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeResidencySlot.io.clear := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.clearSlot - reducedReplayLiqReturnPipeResidencySlot.io.writeValid := - reducedReplayLiqReturnPipeResidencyCandidate.io.residencyWriteValid - reducedReplayLiqReturnPipeResidencySlot.io.writeTargetIsAgu := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetIsAgu - reducedReplayLiqReturnPipeResidencySlot.io.writeTargetIsLda := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetIsLda - reducedReplayLiqReturnPipeResidencySlot.io.writePipeIndex := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetPipeIndex - reducedReplayLiqReturnPipeResidencySlot.io.writeLoadToUsePipeIndex := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertLoadToUsePipeIndex - reducedReplayLiqReturnPipeResidencySlot.io.writeBid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertBid - reducedReplayLiqReturnPipeResidencySlot.io.writeGid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertGid - reducedReplayLiqReturnPipeResidencySlot.io.writeRid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertRid - reducedReplayLiqReturnPipeResidencySlot.io.writeLoadLsId := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertLoadLsId - reducedReplayLiqReturnPipeResidencySlot.io.writePc := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertPc - reducedReplayLiqReturnPipeResidencySlot.io.writeAddr := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertAddr - reducedReplayLiqReturnPipeResidencySlot.io.writeSize := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertSize - reducedReplayLiqReturnPipeResidencySlot.io.writeDst := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertDst - reducedReplayLiqReturnPipeResidencySlot.io.writeData := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertData - reducedReplayLiqReturnPipeResidencySlot.io.writeWakeupRequired := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertWakeupRequired - LinxCoreFrontendFetchRfAluTraceTopR385ResidencyAdvanceLiveWiring.connect( - enable = reducedLoadReplayLiqAllocEnabled, - flush = reducedStoreFlush, - live = reducedReplayLiqReturnPipeResidencyAdvanceLiveControl, - slot = reducedReplayLiqReturnPipeResidencySlot, - w1Slot = reducedReplayLiqReturnPipeW1Slot, - advance = reducedReplayLiqReturnPipeResidencyAdvanceCandidate) - reducedReplayLiqReturnPipeW1Slot.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeW1Slot.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeW1Slot.io.clear := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.clearSlot - reducedReplayLiqReturnPipeW1Slot.io.writeValid := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.advanceValid - reducedReplayLiqReturnPipeW1Slot.io.writeTargetIsAgu := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetIsAgu - reducedReplayLiqReturnPipeW1Slot.io.writeTargetIsLda := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetIsLda - reducedReplayLiqReturnPipeW1Slot.io.writePipeIndex := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetPipeIndex - reducedReplayLiqReturnPipeW1Slot.io.writeLoadToUsePipeIndex := - reducedReplayLiqReturnPipeResidencySlot.io.entryLoadToUsePipeIndex - reducedReplayLiqReturnPipeW1Slot.io.writeBid := - reducedReplayLiqReturnPipeResidencySlot.io.entryBid - reducedReplayLiqReturnPipeW1Slot.io.writeGid := - reducedReplayLiqReturnPipeResidencySlot.io.entryGid - reducedReplayLiqReturnPipeW1Slot.io.writeRid := - reducedReplayLiqReturnPipeResidencySlot.io.entryRid - reducedReplayLiqReturnPipeW1Slot.io.writeLoadLsId := - reducedReplayLiqReturnPipeResidencySlot.io.entryLoadLsId - reducedReplayLiqReturnPipeW1Slot.io.writePc := - reducedReplayLiqReturnPipeResidencySlot.io.entryPc - reducedReplayLiqReturnPipeW1Slot.io.writeAddr := - reducedReplayLiqReturnPipeResidencySlot.io.entryAddr - reducedReplayLiqReturnPipeW1Slot.io.writeSize := - reducedReplayLiqReturnPipeResidencySlot.io.entrySize - reducedReplayLiqReturnPipeW1Slot.io.writeDst := - reducedReplayLiqReturnPipeResidencySlot.io.entryDst - reducedReplayLiqReturnPipeW1Slot.io.writeData := - reducedReplayLiqReturnPipeResidencySlot.io.entryData - reducedReplayLiqReturnPipeW1Slot.io.writeWakeupRequired := - reducedReplayLiqReturnPipeResidencySlot.io.entryWakeupRequired - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.advanceEnable := - reducedReplayLiqReturnPipeW2Modules.advanceControl.io.advanceEnable - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.slotOccupied := - reducedReplayLiqReturnPipeW1Slot.io.occupied - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.slotTargetIsAgu := - reducedReplayLiqReturnPipeW1Slot.io.entryTargetIsAgu - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.slotTargetIsLda := - reducedReplayLiqReturnPipeW1Slot.io.entryTargetIsLda - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.slotPipeIndex := - reducedReplayLiqReturnPipeW1Slot.io.entryPipeIndex - reducedReplayLiqReturnPipeW2Modules.slot.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeW2Modules.slot.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeW2Modules.slot.io.clear := - (reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.clearSlot && - !reducedReplayLiqReturnPipeW2Modules.postLretEnqueueHold.io.suppressCurrentClear) || - reducedReplayLiqReturnPipeW2Modules.postLretEnqueueHold.io.releaseClear - reducedReplayLiqReturnPipeW2Modules.slot.io.replaceOnClear := - reducedReplayLiqReturnPipeW2Modules.advanceControl.io.replaceOnClear - reducedReplayLiqReturnPipeW2Modules.slot.io.writeValid := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.advanceValid - reducedReplayLiqReturnPipeW2Modules.slot.io.writeTargetIsAgu := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetIsAgu - reducedReplayLiqReturnPipeW2Modules.slot.io.writeTargetIsLda := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetIsLda - reducedReplayLiqReturnPipeW2Modules.slot.io.writePipeIndex := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetPipeIndex - reducedReplayLiqReturnPipeW2Modules.slot.io.writeLoadToUsePipeIndex := - reducedReplayLiqReturnPipeW1Slot.io.entryLoadToUsePipeIndex - reducedReplayLiqReturnPipeW2Modules.slot.io.writeBid := - reducedReplayLiqReturnPipeW1Slot.io.entryBid - reducedReplayLiqReturnPipeW2Modules.slot.io.writeGid := - reducedReplayLiqReturnPipeW1Slot.io.entryGid - reducedReplayLiqReturnPipeW2Modules.slot.io.writeRid := - reducedReplayLiqReturnPipeW1Slot.io.entryRid - reducedReplayLiqReturnPipeW2Modules.slot.io.writeLoadLsId := - reducedReplayLiqReturnPipeW1Slot.io.entryLoadLsId - reducedReplayLiqReturnPipeW2Modules.slot.io.writePc := - reducedReplayLiqReturnPipeW1Slot.io.entryPc - reducedReplayLiqReturnPipeW2Modules.slot.io.writeAddr := - reducedReplayLiqReturnPipeW1Slot.io.entryAddr - reducedReplayLiqReturnPipeW2Modules.slot.io.writeSize := - reducedReplayLiqReturnPipeW1Slot.io.entrySize - reducedReplayLiqReturnPipeW2Modules.slot.io.writeDst := - reducedReplayLiqReturnPipeW1Slot.io.entryDst - reducedReplayLiqReturnPipeW2Modules.slot.io.writeData := - reducedReplayLiqReturnPipeW1Slot.io.entryData - reducedReplayLiqReturnPipeW2Modules.slot.io.writeWakeupRequired := - reducedReplayLiqReturnPipeW1Slot.io.entryWakeupRequired - val reducedReplayLiqLretDrainCommitTraceLookupValid = - reducedLoadReplayLiqAllocEnabled && !reducedStoreFlush && - reducedReplayLiqReturnLretSink.io.drainFire && - reducedReplayLiqReturnLretSink.io.drain.rid.valid - val reducedReplayLiqW2CommitTraceLookupValid = - reducedLoadReplayLiqAllocEnabled && !reducedStoreFlush && - reducedReplayLiqReturnPipeW2Modules.slot.io.occupied && - !reducedReplayLiqLretDrainCommitTraceLookupValid - path.io.robCommitTraceLookupValid := - reducedReplayLiqLretDrainCommitTraceLookupValid || - reducedReplayLiqW2CommitTraceLookupValid - path.io.robCommitTraceLookupRid := - Mux( - reducedReplayLiqLretDrainCommitTraceLookupValid, - reducedReplayLiqReturnLretSink.io.drain.rid, - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid) - path.io.robCommitTraceLookupSourceTraceEnable := false.B - val reducedReplayLiqLretDrainInstructionProviderValidReg = RegInit(false.B) - val reducedReplayLiqLretDrainInstructionProviderRidReg = - RegInit(ROBID.disabled(p.robEntries)) - val reducedReplayLiqLretDrainInstructionProviderRawReg = - RegInit(0.U(traceParams.insnWidth.W)) - val reducedReplayLiqLretDrainInstructionProviderLenReg = - RegInit(0.U(traceParams.lenWidth.W)) - val reducedReplayLiqLretDrainInstructionProviderCapture = - reducedReplayLiqLretDrainCommitTraceLookupValid && - path.io.robCommitTraceLookup.instructionProviderValid && - (path.io.robCommitTraceLookup.instructionLen =/= 0.U) - val reducedReplayLiqW2InstructionProviderClear = - reducedReplayLiqReturnPipeW2Modules.slot.io.clear && - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid.valid && - reducedReplayLiqLretDrainInstructionProviderRidReg.valid && - ROBID.equal( - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid, - reducedReplayLiqLretDrainInstructionProviderRidReg) - when(reducedStoreFlush || !reducedLoadReplayLiqAllocEnabled) { - reducedReplayLiqLretDrainInstructionProviderValidReg := false.B - reducedReplayLiqLretDrainInstructionProviderRidReg := ROBID.disabled(p.robEntries) - reducedReplayLiqLretDrainInstructionProviderRawReg := 0.U - reducedReplayLiqLretDrainInstructionProviderLenReg := 0.U - }.elsewhen(reducedReplayLiqLretDrainInstructionProviderCapture) { - reducedReplayLiqLretDrainInstructionProviderValidReg := true.B - reducedReplayLiqLretDrainInstructionProviderRidReg := - reducedReplayLiqReturnLretSink.io.drain.rid - reducedReplayLiqLretDrainInstructionProviderRawReg := - path.io.robCommitTraceLookup.instructionRaw - reducedReplayLiqLretDrainInstructionProviderLenReg := - path.io.robCommitTraceLookup.instructionLen - }.elsewhen(reducedReplayLiqW2InstructionProviderClear) { - reducedReplayLiqLretDrainInstructionProviderValidReg := false.B - reducedReplayLiqLretDrainInstructionProviderRidReg := ROBID.disabled(p.robEntries) - reducedReplayLiqLretDrainInstructionProviderRawReg := 0.U - reducedReplayLiqLretDrainInstructionProviderLenReg := 0.U - } - val reducedReplayLiqW2LatchedInstructionProviderValid = - reducedReplayLiqLretDrainInstructionProviderValidReg && - reducedReplayLiqReturnPipeW2Modules.slot.io.occupied && - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid.valid && - ROBID.equal( - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid, - reducedReplayLiqLretDrainInstructionProviderRidReg) - val reducedReplayLiqW2InstructionProviderValid = - reducedReplayLiqW2LatchedInstructionProviderValid || - (reducedReplayLiqW2CommitTraceLookupValid && - path.io.robCommitTraceLookup.instructionProviderValid) - val reducedReplayLiqW2InstructionProviderRaw = - Mux( - reducedReplayLiqW2LatchedInstructionProviderValid, - reducedReplayLiqLretDrainInstructionProviderRawReg, - path.io.robCommitTraceLookup.instructionRaw) - val reducedReplayLiqW2InstructionProviderLen = - Mux( - reducedReplayLiqW2LatchedInstructionProviderValid, - reducedReplayLiqLretDrainInstructionProviderLenReg, - path.io.robCommitTraceLookup.instructionLen) - val reducedReplayLiqW2CompletionDelayReady = - if (reducedReplayLiqW2CompletionDelayCycles > 0) { - val delayWidth = math.max(1, log2Ceil(reducedReplayLiqW2CompletionDelayCycles + 1)) - val delayActive = RegInit(false.B) - val delayCount = RegInit(0.U(delayWidth.W)) - val delayCandidate = - reducedLoadReplayLiqAllocEnabled && !reducedStoreFlush && - reducedReplayLiqReturnPipeW2Modules.slot.io.occupied - val delayReady = delayCandidate && delayActive && delayCount === 0.U - - when(!delayCandidate) { - delayActive := false.B - delayCount := 0.U - }.elsewhen(!delayActive) { - delayActive := true.B - delayCount := (reducedReplayLiqW2CompletionDelayCycles - 1).U - }.elsewhen(delayCount =/= 0.U) { - delayCount := delayCount - 1.U - } - - delayReady - } else { - true.B - } - LinxCoreFrontendFetchRfAluTraceTopR376SourceTraceWiring.connect( - io, - reducedLoadReplayLiqAllocPath, - reducedReplayLiqReturnLretPayload, - reducedReplayLiqReturnLretSinkEntry, - reducedReplayLiqReturnIexDataCandidate, - reducedReplayLiqReturnIexPipeInsertCandidate, - reducedReplayLiqReturnPipeResidencySlot, - reducedReplayLiqReturnPipeW1Slot, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnCompleteValid) - val reducedReplayLiqW2SideEffectLiveRequested = Mux( - reducedLiveLoadLiqEnabled, - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.resolveRequired, - reducedReplayLiqReturnPipeW2Modules.atomicLiveRequestControl.io.sideEffectLiveRequested) - LinxCoreFrontendFetchRfAluTraceTopW2RequestPayloadWiring.connect( - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest, - reducedReplayLiqReturnPipeW2Modules.resolveRequest, - reducedReplayLiqReturnPipeW2Modules.writebackRequest, - reducedReplayLiqReturnPipeW2Modules.wakeupRequest, - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan, - reducedReplayLiqReturnPipeW2Modules.sideEffectReady, - reducedReplayLiqW2CompletionDelayReady && - reducedReplayLiqReturnPipeW2Modules.postLretEnqueueHold.io.completionReady, - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl, - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady, - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady, - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady, - reducedReplayLiqW2SideEffectLiveRequested, - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.sinkReady, - !rfWritebackArbiter.io.selectedExecute, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2CompletionPermitWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.sideEffectCompletionPermit, - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2Modules.sideEffectReady, - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady, - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady, - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2IssuePermitWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.sideEffectIssuePermit, - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan, - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady, - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady, - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2FireVectorWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireVector, - reducedReplayLiqReturnPipeW2Modules.sideEffectIssuePermit, - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ResolveFirePayloadWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.resolveFirePayload, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireVector, - reducedReplayLiqReturnPipeW2Modules.resolveRequest, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ResolveArbiterInputWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.resolveArbiterInput, - reducedReplayLiqReturnPipeW2Modules.resolveFirePayload, - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.resolveLiveEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2CommitRowTraceSourceWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.commitRowTraceSource, - path.io.robCommitTraceLookup, - reducedReplayLiqW2InstructionProviderValid, - reducedReplayLiqW2InstructionProviderRaw, - reducedReplayLiqW2InstructionProviderLen, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - val reducedReplayLiqW2CommitRowFillEnable = Mux( - reducedLiveLoadLiqEnabled, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete.io.fireComplete, - reducedReplayLiqReturnPipeW2Modules.rowFillEnableControl.io.rowFillEnable) - LinxCoreFrontendFetchRfAluTraceTopW2CommitRowCandidateWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate, - reducedReplayLiqReturnPipeW2Modules.commitRowTraceSource, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqW2CommitRowFillEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleReadyWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedLoadReplayLiqAllocPath, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleRequestControlWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleRequestControl, - reducedReplayLiqReturnPipeW2Modules.atomicLiveRequestControl, - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleCommitPermitWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleCommitPermit, - reducedReplayLiqReturnPipeW2Modules.replayRowClearRequest, - reducedReplayLiqReturnPipeW2Modules.rowFillEnableControl, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - val reducedReplayLiqReturnCompleteTargetsHead = - reducedReplayLiqReturnCompleteValid && - (reducedLoadReplayLiqAllocPath.io.returnCompleteIndex === reducedReplayLiqHeadIndex) - val reducedReplayLiqHeadCompleteRepickClear = - reducedReplayLiqHeadValid && - (reducedReplayLiqHeadRow.status === LoadInflightStatus.Repick) && - reducedReplayLiqHeadRow.dataComplete && - reducedReplayLiqHeadRow.sourcesReturned && - reducedReplayLiqHeadRow.scbReturned && - reducedReplayLiqHeadRow.stqReturned && - !reducedReplayLiqHeadRow.waitStore && - !reducedReplayLiqReturnCompleteTargetsHead - // A first-pass live load bypasses the legacy ResolveQ owner. Retire the - // exact Resolved LIQ row only when the matching W2 transaction has issued - // all of its architectural side effects. This is deliberately an - // existing-clear request: the legacy lifecycle gate remains unchanged for - // replay-owned rows, while the live path makes completion and retirement - // one atomic W2 event. - val reducedReplayLiqLiveW2ClearValid = - reducedLiveLoadLiqEnabled && - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete.io.fireComplete && - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady.io.rowClearReady - val reducedReplayLiqExistingClearValid = - Mux( - reducedLiveLoadLiqEnabled, - reducedReplayLiqLiveW2ClearValid, - reducedLoadReplayResolveClearPending || reducedReplayLiqHeadCompleteRepickClear - ) - val reducedReplayLiqExistingClearIndex = - Mux( - reducedLiveLoadLiqEnabled, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady.io.rowClearIndex, - Mux(reducedLoadReplayResolveClearPending, reducedLoadReplayResolveClearIndex, reducedReplayLiqHeadIndex) - ) - LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowClearRequestWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.replayRowClearRequest, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleRequestControl, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleCommitPermit, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleClearFallbackGuard, - reducedLoadReplayLiqAllocPath, - reducedReplayLiqExistingClearValid, - reducedReplayLiqExistingClearIndex, - reducedReplayLiqRetainedOwnerFallbackLiveProbeActive, - reducedReplayLiqReturnPipeW2Modules.retireRecordPhysicalBundleSuppressLiveMask.io.suppressLifecycleClear, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.enable := reducedLoadReplayLiqAllocEnabled - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.flush := reducedStoreFlush - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.resolveValid := - reducedReplayLiqReturnPipeW2Modules.resolveArbiterInput.io.resolveValid - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.resolveRid := - reducedReplayLiqReturnPipeW2Modules.resolveArbiterInput.io.resolveRid - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.executeCompleteValid := - execute.io.completeValid - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.completeRowInputValid := - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate.io.completeRowValid - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.completeRowInput := - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate.io.completeRow - io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceSinkReady := - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.sinkReady - io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCandidateValid := - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteValid := - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.completeValid - io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteRobValue := - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.completeRobValue - io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceBlockedByExecute := - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.blockedByExecute - LinxCoreFrontendFetchRfAluTraceTopW2WritebackFirePayloadWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.writebackFirePayload, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireVector, - reducedReplayLiqReturnPipeW2Modules.writebackRequest, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2WritebackArbiterInputWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.writebackArbiterInput, - reducedReplayLiqReturnPipeW2Modules.writebackFirePayload, - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.writebackLiveEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2WakeupFirePayloadWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.wakeupFirePayload, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireVector, - reducedReplayLiqReturnPipeW2Modules.wakeupRequest, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2WakeupArbiterInputWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.wakeupArbiterInput, - reducedReplayLiqReturnPipeW2Modules.wakeupFirePayload, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.retireRecordWakeupFallbackGuard, - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.wakeupLiveEnable, - reducedReplayLiqRetainedOwnerFallbackLiveProbeActive, - reducedReplayLiqReturnPipeW2Modules.retireRecordPhysicalBundleSuppressLiveMask.io.suppressWakeup, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2FireCompleteWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireVector, - reducedReplayLiqReturnPipeW2Modules.resolveFirePayload, - reducedReplayLiqReturnPipeW2Modules.writebackFirePayload, - reducedReplayLiqReturnPipeW2Modules.wakeupFirePayload, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ClearIntentWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2Modules.sideEffectCompletionPermit, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete, - reducedReplayLiqReturnPipeW2Modules.promotionControl.io.liveClearEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2PostLretEnqueueHoldWiring.connect( - reducedReplayLiqReturnPipeW2Modules.postLretEnqueueHold, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnLretSink, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnLretSink, - reducedReplayLiqReturnLretSinkEntry, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordInstructionMetadataLatchWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordInstructionMetadata, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnLretSink, - reducedReplayLiqReturnLretSinkEntry, - reducedReplayLiqW2InstructionProviderValid, - reducedReplayLiqW2InstructionProviderRaw, - reducedReplayLiqW2InstructionProviderLen, - reducedReplayLiqLretDrainInstructionProviderCapture, - path.io.robCommitTraceLookup.instructionRaw, - path.io.robCommitTraceLookup.instructionLen, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleEvidenceWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleEvidence, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordCommitRowCandidateWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordCommitRowCandidate, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.retireRecordInstructionMetadata.io.providerValid, - reducedReplayLiqReturnPipeW2Modules.retireRecordInstructionMetadata.io.providerRaw, - reducedReplayLiqReturnPipeW2Modules.retireRecordInstructionMetadata.io.providerLen, - reducedReplayLiqReturnPipeW2Modules.retireRecordRowFillEnableControl.io.rowFillEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRowFillEnableControlWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordRowFillEnableControl, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleEvidence.io.providerRowClearReady, - reducedReplayLiqReturnPipeW2Modules.retireRecordCommitRowCandidate, - true.B, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackOwnerWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules, - robCompleteArbiter, - rfWritebackArbiter, - reducedReplayLiqRetainedOwnerFallbackEmitProbe.B, - reducedReplayLiqRetainedOwnerNoPhysicalProbe.B, - reducedReplayLiqRetainedOwnerFallbackLiveProbe.B, - reducedReplayLiqRetainedOwnerFallbackLiveProbeActive, - reducedReplayLiqRetainedOwnerPhysicalSuppressProbe.B, - reducedReplayLiqRetainedOwnerPhysicalSuppressPromote.B, - reducedReplayLiqRetainedOwnerPhysicalSuppressLiveMask.B, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleRequestProbeWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleRequestProbe, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleEvidence.io.providerRowClearReady, - reducedReplayLiqReturnPipeW2Modules.retireRecordRowFillEnableControl.io.requestEvidenceValid, - reducedReplayLiqReturnPipeW2Modules.retireRecordCommitRowCandidate.io.rowFillCandidateValid, - reducedReplayLiqReturnPipeW2Modules.retireRecordRowFillEnableControl.io.rowFillEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordAtomicRequestProbeWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.retireRecordAtomicRequestProbe, - reducedReplayLiqReturnPipeW2Modules.retireRecord, - reducedReplayLiqReturnPipeW2Modules.retireRecordLifecycleEvidence.io.providerRowClearReady, - reducedReplayLiqReturnPipeW2Modules.retireRecordCommitRowCandidate.io.rowFillCandidateValid, - reducedReplayLiqReturnPipeW2Modules.retireRecordRowFillEnableControl.io.rowFillEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2ClearCommitGuardWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.clearCommitGuard, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnPipeW2Modules.resolveFirePayload, - reducedReplayLiqReturnPipeW2Modules.robCompleteSource, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - val reducedReplayLiqReturnPipeW2SideEffectSinksPrereqReady = - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.resolveRequired && - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.resolveArmed && - (!reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.writebackRequired || - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.writebackArmed) && - (!reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.wakeupRequired || - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.wakeupArmed) - val reducedReplayLiqReturnPipeW2ClearCommitPrereqReady = - reducedReplayLiqReturnPipeW2SideEffectSinksPrereqReady && - reducedReplayLiqReturnPipeW2Modules.slot.io.entryRid.valid && - reducedReplayLiqReturnPipeW2Modules.robCompleteSource.io.sinkReady - LinxCoreFrontendFetchRfAluTraceTopW2AtomicLiveRequestWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.atomicLiveRequestControl, - reducedReplayLiqReturnPipeW2Modules.atomicPrereqSnapshot, - reducedReplayLiqReturnPipeW2Modules.completionCandidate, - reducedReplayLiqReturnPipeW2SideEffectSinksPrereqReady, - reducedReplayLiqReturnPipeW2ClearCommitPrereqReady, - reducedReplayLiqReturnPipeW1AdvanceCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedReplayLiqReturnPipeW2Modules.slot, - true.B, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RowFillEnableControlWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.rowFillEnableControl, - reducedReplayLiqReturnPipeW2Modules.replayRowLifecycleReady, - reducedReplayLiqReturnPipeW2Modules.atomicLiveRequestControl, - reducedReplayLiqReturnPipeW2Modules.commitRowCandidate, - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete, - reducedReplayLiqReturnPipeW2Modules.clearCommitGuard, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2PromotionControlWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.promotionControl, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW1AdvanceCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnPipeW2Modules.atomicLiveRequestControl.io.promotionRequested, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RefillReadyWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.refillReady, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW1AdvanceCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2SlotReplacePlanWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.slotReplacePlan, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW1AdvanceCandidate, - reducedReplayLiqReturnPipeW2Modules.clearIntent, - reducedReplayLiqReturnPipeW2Modules.refillReady, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - LinxCoreFrontendFetchRfAluTraceTopW2AdvanceControlWiring.connect( - io, - reducedReplayLiqReturnPipeW2Modules.advanceControl, - reducedReplayLiqReturnPipeW2Modules.slot, - reducedReplayLiqReturnPipeW1AdvanceCandidate, - reducedReplayLiqReturnPipeW2Modules.refillReady, - reducedReplayLiqReturnPipeW2Modules.slotReplacePlan, - reducedReplayLiqReturnPipeW2Modules.promotionControl.io.advanceLivePromotionEnable, - reducedLoadReplayLiqAllocEnabled, - reducedStoreFlush - ) - rf.io.write(0).requestValid := rfWritebackArbiter.io.writeValid - rf.io.write(0).commit := rfWritebackArbiter.io.writeValid - rf.io.write(0).tag := rfWritebackArbiter.io.writeTag - rf.io.write(0).data := rfWritebackArbiter.io.writeData - val localReset = backendPipeFlush || io.startValid || io.restartValid - val issueIsFretStk = - issue.io.issueValid && - issue.io.issueUop.opcode === FrontendOpcodeDecodeTable.OP_FRET_STK.U(p.opcodeWidth.W) - val issueFretStkFallbackValid = - issueIsFretStk && issue.io.issueUop.fretStkFallbackTargetValid - val conditionalFretIssueFire = issue.io.issueFire && issueFretStkFallbackValid - val blockCondition = FullBidBlockConditionWiring.connect( - reset.asBool || io.startValid || io.restartValid, - execute.io.branchConditionValid, - execute.io.branchConditionTaken, - execute.io.branchConditionUop.blockBidValid, - execute.io.branchConditionUop.blockBid, - path.io.blockMarkerActiveValid, - path.io.blockMarkerActiveBid, - issueIsFretStk, - issue.io.issueUop.blockBidValid, - issue.io.issueUop.blockBid, - conditionalFretIssueFire, - p.blockBidWidth) - path.io.blockBranchTakenValid := blockCondition.activeConditionValid - path.io.blockBranchTaken := blockCondition.activeConditionTaken - val liveFretConditionValid = blockCondition.fretConditionValid - val liveFretConditionTaken = blockCondition.fretConditionTaken - val localDstAllocT = - issue.io.inputAcceptFire && issue.io.inputAcceptUop.dst(0).valid && (issue.io.inputAcceptUop.dst(0).kind === DestinationKind.T) - val localDstAllocU = - issue.io.inputAcceptFire && issue.io.inputAcceptUop.dst(0).valid && (issue.io.inputAcceptUop.dst(0).kind === DestinationKind.U) - val localCompleteT = - execute.io.completeFire && execute.io.completeRow.wb.valid && (execute.io.completeRow.wb.reg === 31.U) - val localCompleteU = - execute.io.completeFire && execute.io.completeRow.wb.valid && (execute.io.completeRow.wb.reg === 30.U) - val reducedReplayLiqLiveLocalComplete = - reducedLiveLoadLiqEnabled && - reducedReplayLiqReturnPipeW2Modules.sideEffectFireComplete.io.fireComplete && - reducedReplayLiqReturnPipeW2Modules.slot.io.entryDst.valid - val reducedReplayLiqLiveLocalCompleteT = - reducedReplayLiqLiveLocalComplete && - (reducedReplayLiqReturnPipeW2Modules.slot.io.entryDst.kind === DestinationKind.T) - val reducedReplayLiqLiveLocalCompleteU = - reducedReplayLiqLiveLocalComplete && - (reducedReplayLiqReturnPipeW2Modules.slot.io.entryDst.kind === DestinationKind.U) - val localTCompleteCount = localCompleteT.asUInt + reducedReplayLiqLiveLocalCompleteT.asUInt - val localUCompleteCount = localCompleteU.asUInt + reducedReplayLiqLiveLocalCompleteU.asUInt - - val localTPendingAfterComplete = - Mux(localTPendingCount >= localTCompleteCount, localTPendingCount - localTCompleteCount, 0.U) - val localUPendingAfterComplete = - Mux(localUPendingCount >= localUCompleteCount, localUPendingCount - localUCompleteCount, 0.U) - - when(localReset) { - for (idx <- 0 until localQueueDepth) { - localTData(idx) := 0.U - localUData(idx) := 0.U - localTReady(idx) := false.B - localUReady(idx) := false.B - } - localTPendingCount := 0.U - localUPendingCount := 0.U - }.otherwise { - localTPendingCount := localTPendingAfterComplete + localDstAllocT.asUInt - localUPendingCount := localUPendingAfterComplete + localDstAllocU.asUInt - - pushLocalPair( - localTData, - localTReady, - localCompleteT, - execute.io.completeRow.wb.data, - reducedReplayLiqLiveLocalCompleteT, - reducedReplayLiqReturnPipeW2Modules.slot.io.entryData) - pushLocalPair( - localUData, - localUReady, - localCompleteU, - execute.io.completeRow.wb.data, - reducedReplayLiqLiveLocalCompleteU, - reducedReplayLiqReturnPipeW2Modules.slot.io.entryData) - } - - // Conditional FRET.STK may be renamed before the older SETC reaches W2. - // Preserve normal ROB/rename allocation order, but hold the issue handshake - // until the block-condition latch is valid so execute cannot consume an - // invalid condition snapshot and return instead of taking the loop edge. - val conditionalFretStkWaiting = - issueFretStkFallbackValid && !liveFretConditionValid - val templateContextBlocksIssue = LinxCoreFrontendFetchRfAluTraceTopTemplateContextWiring.connect( - top = io, - path = path, - issue = issue, - execute = execute, - rf = rf, - context = templateContext, - snapshots = templateSnapshotTable, - localReset = localReset, - conditionalFretWaiting = conditionalFretStkWaiting, - liveConditionValid = liveFretConditionValid, - liveConditionTaken = liveFretConditionTaken, - templateRfReadPort = coreParams.scalarBackend.gprReadPorts + 3, - p = p) - val redirectCleanupCutsIssue = LinxCoreFrontendFetchRfAluTraceTopRedirectIssueCutWiring.cutsIssue( - io, - issue, - scalarRedirectRecovery, - backendPipeFlush, - p) - val executeInputUop = Wire(chiselTypeOf(issue.io.issueUop)) - executeInputUop := issue.io.issueUop - when(issueIsFretStk) { - // Every FRET snapshots a complete control context at the issue boundary, - // including the explicit absence of a condition or fallback target. E1 - // runs one cycle later, when decode may already have installed another - // marker; leaving contextValid low would let that younger marker redirect - // an older return. A FRET that owns a fallback still waits above until - // its causal SETC condition is live. - executeInputUop.fretStkContextValid := true.B - executeInputUop.fretStkConditionValid := liveFretConditionValid - executeInputUop.fretStkConditionTaken := liveFretConditionTaken - } - issue.io.issueReady := - Mux( - serviceIssueCandidate, - servicePath.io.issueReady, - Mux( - scalarScIssueGate.candidate, - scalarScIssueGate.ready, - execute.io.inReady && !conditionalFretStkWaiting && !templateContextBlocksIssue && !redirectCleanupCutsIssue)) - execute.io.inValid := - issue.io.issueValid && !serviceIssueCandidate && !scalarScIssueGate.candidate && - !conditionalFretStkWaiting && !templateContextBlocksIssue && !redirectCleanupCutsIssue - execute.io.in := executeInputUop - execute.io.srcData := issue.io.issueSrcData - execute.io.loadLookupData := reducedStoreResidentForward.io.loadData - LinxCoreFrontendFetchRfAluTraceTopPairLoadWiring.connect(io, rf, issue, path, execute) - execute.io.loadLookupWaitBlocked := reducedStoreResidentForward.io.waitBlocked - execute.io.loadLiqEnable := reducedLiveLoadLiqEnabled - execute.io.loadLiqAccepted := reducedLiveLoadLiqCapture.io.captureAccepted - execute.io.stackPointerData := issue.io.scalarSpIssueSnapshot - execute.io.flushValid := backendPipeFlush - // The fallback target is owned by the renamed FRET. Consulting the live - // marker here can attach a younger or unrelated CALL/DIRECT target after - // issue and turn an unconditional return into a conditional redirect. - execute.io.fretStkFallbackTargetValid := issueFretStkFallbackValid - execute.io.fretStkFallbackTarget := issue.io.issueUop.fretStkFallbackTarget - execute.io.fretStkConditionValid := liveFretConditionValid - execute.io.fretStkConditionTaken := liveFretConditionTaken - - io.fetchReqValid := source.io.reqValid && (!useProductionD1Ingress).B - io.fetchReqPc := Mux(useProductionD1Ingress.B, 0.U, source.io.reqPc) - io.fetchRespReady := source.io.respReady && (!useProductionD1Ingress).B - io.sourceActive := Mux(useProductionD1Ingress.B, productionD1.io.count =/= 0.U, source.io.active) - io.sourceWaitingResponse := source.io.waitingResponse && (!useProductionD1Ingress).B - io.sourcePacketValid := Mux(useProductionD1Ingress.B, productionD1.io.out.valid, source.io.packetValid) - io.sourceReqFire := source.io.reqFire && (!useProductionD1Ingress).B - io.sourceRespFire := source.io.respFire && (!useProductionD1Ingress).B - io.sourceOutFire := Mux(useProductionD1Ingress.B, productionD1.io.in.fire, source.io.outFire) - io.sourceAdvanceZero := source.io.advanceZero && (!useProductionD1Ingress).B - io.sourceAdvanceBytes := Mux(useProductionD1Ingress.B, 0.U, effectiveSourceAdvanceBytes) - io.sourceRestartValid := io.restartValid || markerRedirectPending || bodyCutRestartPending - io.sourceRestartPc := Mux(markerRedirectPending, markerRedirectPcReg, Mux(bodyCutRestartPending, bodyCutRestartPcReg, io.restartPc)) - io.sourceCurrentPc := Mux(useProductionD1Ingress.B, 0.U, source.io.currentPc) - io.sourceIssuedPc := Mux(useProductionD1Ingress.B, 0.U, source.io.issuedPc) - io.sourceNextPktUid := Mux(useProductionD1Ingress.B, 0.U, source.io.nextPktUid) - io.debugBlockMarkerStopRedirectValid := path.io.blockMarkerStopRedirectValid - io.debugBlockMarkerStopRedirectPc := path.io.blockMarkerStopRedirectPc - io.debugMarkerRedirectFire := markerRedirectFire - io.debugMarkerRedirectPending := markerRedirectPending - io.debugMarkerRedirectPc := markerRedirectPcReg - io.debugBodyCutAdvanceBytes := Mux(useProductionD1Ingress.B, 0.U, effectiveSourceAdvanceBytes) - io.debugF4TotalLenBytes := Mux(useProductionD1Ingress.B, 0.U, f4.io.totalLenBytes) - io.debugReadinessBits := Cat( - path.io.robMarkerRetireSourceLifecycleFire, - localIncomingBlocked, - issue.io.inReady, - issue.io.inReady && !localIncomingBlocked, - path.io.decodeReady, - path.io.decodeReady && !admittedMarkerDrainBarrier, - denseSlots.io.inReady, - denseSlots.io.inReady) - io.debugFretConditionBits := Cat( - issueFretStkFallbackValid, - issue.io.issueUop.fretStkContextValid, - conditionalFretStkWaiting, - execute.io.branchConditionValid, - execute.io.branchConditionTaken, - blockCondition.activeConditionValid, - blockCondition.activeConditionTaken, - liveFretConditionValid) - io.debugContinuationBits := Cat( - path.io.scalarContinuationOwnershipCutFire, - path.io.scalarContinuationGprCutFire, - path.io.scalarContinuationTCutFire, - path.io.scalarContinuationUCutFire, - path.io.blockMarkerAllocFire, - path.io.blockScalarDoneFire, - path.io.blockRetireFire, - path.io.robDeallocBlockLastValid) - - io.reducedBodyCutActive := reducedBodyCutActive - io.reducedBodyCutFire := bodyCutRestartFire - io.reducedBodyCutAdvanceBytes := Mux(reducedBodyCutActive, effectiveSourceAdvanceBytes, 0.U) - io.bfuStaticGeometryValid := staticBfuGeometry.io.geometryValid - io.bfuStaticHeaderActive := staticBfuGeometry.io.headerActive - io.bfuStaticLearnedFire := staticBfuGeometry.io.learnedFire - io.bfuStaticResolvedLearnedFire := staticBfuGeometry.io.resolvedLearnedFire - io.bfuResolvedBodyEndAccepted := resolvedBfuBodyEnd.io.accepted - io.bfuResolvedBodyEndHeaderMismatch := resolvedBfuBodyEnd.io.headerMismatch - io.bfuResolvedBodyEndInactiveDrop := resolvedBfuBodyEnd.io.inactiveDrop - io.bfuResolvedBodyEndFlushDrop := resolvedBfuBodyEnd.io.flushDrop - io.bfuResolvedBodyEndUnderflow := resolvedBfuBodyEnd.io.bodyEndUnderflow - io.bfuResolvedBodyEndSourceRuntimeSelected := resolvedBfuBodyEndSource.io.selectedRuntime - io.bfuResolvedBodyEndSourceReplaySelected := resolvedBfuBodyEndSource.io.selectedReplay - io.bfuResolvedBodyEndSourceRuntimeReplayComparable := resolvedBfuBodyEndSource.io.runtimeReplayComparable - io.bfuResolvedBodyEndSourceRuntimeReplayMatch := resolvedBfuBodyEndSource.io.runtimeReplayMatch - io.bfuResolvedBodyEndSourceRuntimeReplayMismatch := - resolvedBfuBodyEndSource.io.runtimeReplayHeaderMismatch || - resolvedBfuBodyEndSource.io.runtimeReplayHSizeMismatch || - resolvedBfuBodyEndSource.io.runtimeReplayBodyEndMismatch - io.bfuResolvedBodyEndSourceRuntimeFeedbackFire := localBfuCutFeedbackPending.io.captureFire - io.bfuResolvedBodyEndSourceRuntimePending := localBfuCutFeedbackPending.io.pending - io.bfuResolvedBodyEndSourceRuntimePendingConsumeFire := localBfuCutFeedbackPending.io.consumeFire - io.bfuResolvedBodyEndSourceRuntimePendingDropMismatch := localBfuCutFeedbackPending.io.dropMismatch - io.bfuResolvedBodyEndSourceRuntimePendingCandidateComparable := - localBfuCutFeedbackPending.io.candidateComparable - io.bfuResolvedBodyEndSourceRuntimePendingCandidateMatch := - localBfuCutFeedbackPending.io.candidateMatch - io.bfuResolvedBodyEndSourceRuntimePendingCandidateMismatch := - localBfuCutFeedbackPending.io.candidateMismatch - io.bfuPendingRuntimeCandidateValid := pendingRuntimeBodyEndCandidate.io.candidateValid - io.bfuPendingRuntimeCandidatePendingWithoutActiveHeader := - pendingRuntimeBodyEndCandidate.io.pendingWithoutActiveHeader - io.bfuPendingRuntimeCandidateActiveHeaderMismatch := - pendingRuntimeBodyEndCandidate.io.activeHeaderMismatch - io.bfuPendingRuntimeCandidateReplayComparable := - pendingRuntimeBodyEndCandidate.io.replayComparable - io.bfuPendingRuntimeCandidateReplayMatch := - pendingRuntimeBodyEndCandidate.io.replayMatch - io.bfuPendingRuntimeCandidateReplayMismatch := - pendingRuntimeBodyEndCandidate.io.replayHeaderMismatch || - pendingRuntimeBodyEndCandidate.io.replayHSizeMismatch || - pendingRuntimeBodyEndCandidate.io.replayBodyEndMismatch - io.bfuRuntimeBodyEndOraclePending := runtimeBodyEndOracle.io.pending - io.bfuRuntimeBodyEndOracleCaptureFire := runtimeBodyEndOracle.io.captureFire - io.bfuRuntimeBodyEndOracleReplayComparable := - runtimeBodyEndOracle.io.replayComparable - io.bfuRuntimeBodyEndOracleReplayMatch := - runtimeBodyEndOracle.io.replayMatch - io.bfuRuntimeBodyEndOracleReplayMismatch := - runtimeBodyEndOracle.io.replayHeaderMismatch || - runtimeBodyEndOracle.io.replayHSizeMismatch || - runtimeBodyEndOracle.io.replayBodyEndMismatch - io.bfuRuntimeBodyEndOracleOverwritePending := - runtimeBodyEndOracle.io.overwritePending - io.bfuStaticExternalComparable := staticExternalComparable - io.bfuStaticExternalMatch := staticExternalMatch - io.bfuStaticExternalMismatch := - staticExternalHeaderMismatch || staticExternalHSizeMismatch || staticExternalBSizeMismatch - io.bfuStaticExternalHeaderMismatch := staticExternalHeaderMismatch - io.bfuStaticExternalHSizeMismatch := staticExternalHSizeMismatch - io.bfuStaticExternalBSizeMismatch := staticExternalBSizeMismatch - io.bfuBodyCutArmComparable := bodyCutArm.io.comparable - io.bfuBodyCutArmAccepted := bodyCutArm.io.accepted - io.bfuBodyCutArmMismatch := - bodyCutArm.io.headerMismatch || bodyCutArm.io.hsizeMismatch || bodyCutArm.io.bsizeMismatch - io.bfuBodyCutArmHeaderMismatch := bodyCutArm.io.headerMismatch - io.bfuBodyCutArmHSizeMismatch := bodyCutArm.io.hsizeMismatch - io.bfuBodyCutArmBSizeMismatch := bodyCutArm.io.bsizeMismatch - io.bfuLocalBodyWindowActive := localBfuBodyWindow.io.active - io.bfuLocalBodyWindowArmFire := localBfuBodyWindow.io.armFire - io.bfuLocalBodyWindowReleaseFire := localBfuBodyWindow.io.releaseFire - io.bfuLocalBodyWindowArmSlot := localBfuBodyWindow.io.armSlot - io.f4ValidMask := Mux(useProductionD1Ingress.B, productionD1.io.out.bits.validMask, frontendValidMask) - io.f4SlotCount := Mux(useProductionD1Ingress.B, productionD1.io.inLaneCount, frontendSlotCount) - io.denseSlotQueueInFire := Mux(useProductionD1Ingress.B, productionD1.io.in.fire, denseSlots.io.inFire) - io.denseSlotQueueOutFire := frontendIngressFire - io.denseSlotQueueInSlotCount := - Mux(useProductionD1Ingress.B, productionD1.io.inLaneCount, denseSlots.io.inSlotCount) - io.denseSlotQueueCount := Mux(useProductionD1Ingress.B, productionD1.io.count, denseSlots.io.count) - io.denseSlotQueueHeadSlot := - Mux(useProductionD1Ingress.B, productionD1.io.headLane, denseSlots.io.headSlotIndex) - io.denseSlotQueueFull := - Mux(useProductionD1Ingress.B, productionD1.io.count === denseSlotQueueDepth.U, denseSlots.io.full) - io.denseSlotQueueEmpty := - Mux(useProductionD1Ingress.B, productionD1.io.count === 0.U, denseSlots.io.empty) - io.admittedMarkerDrainBarrier := admittedMarkerDrainBarrier - io.decodeReady := path.io.decodeReady - io.decodeQueuePushReady := path.io.decodeQueuePushReady - io.decodeAllocReady := path.io.decodeAllocReady - io.decodeGprReservationReady := path.io.decodeGprReservationReady - io.decodeSelectedClosesActiveRedirect := path.io.decodeSelectedClosesActiveRedirect - io.decodeSelectedNeedsGprReservation := path.io.decodeSelectedNeedsGprReservation - io.gprReservationCount := path.io.gprReservationCount - io.gprReservationNeed := path.io.gprReservationNeed - io.selectedValid := path.io.selectedValid - io.selectedRobValue := path.io.selectedRobValue - io.selectedBlockBid := path.io.selectedBlockBid - io.blockMarkerSkipFire := skippedMarkerLifecycleFire - io.blockMarkerSkipValid := path.io.blockMarkerSkipValid - io.blockMarkerMixedPacket := path.io.blockMarkerMixedPacket - io.blockMarkerBoundary := path.io.blockMarkerBoundary - io.blockMarkerStop := path.io.blockMarkerStop - io.blockMarkerPc := path.io.blockMarkerPc - io.blockMarkerInsn := path.io.blockMarkerInsn - io.blockMarkerLen := path.io.blockMarkerLen - io.blockMarkerTarget := path.io.blockMarkerTarget - io.blockMarkerAllocReady := path.io.blockMarkerAllocReady - io.blockMarkerLifecycleConflict := path.io.blockMarkerLifecycleConflict - io.blockMarkerAllocFire := path.io.blockMarkerAllocFire - io.blockMarkerAllocBid := path.io.blockMarkerAllocBid - io.blockMarkerActiveValid := path.io.blockMarkerActiveValid - io.blockMarkerActiveBid := path.io.blockMarkerActiveBid - io.blockMarkerActiveTarget := path.io.blockMarkerActiveTarget - io.blockMarkerStopRedirectValid := path.io.blockMarkerStopRedirectValid - io.blockMarkerStopRedirectPc := path.io.blockMarkerStopRedirectPc - io.robMarkerRetireSourceLifecycleReady := path.io.robMarkerRetireSourceLifecycleReady - io.robMarkerRetireSourceLifecycleFire := path.io.robMarkerRetireSourceLifecycleFire - io.robMarkerRetireSourceLifecycleBoundaryFire := path.io.robMarkerRetireSourceLifecycleBoundaryFire - io.robMarkerRetireSourceLifecycleStopFire := path.io.robMarkerRetireSourceLifecycleStopFire - io.robMarkerRetireSourceValid := path.io.robMarkerRetireSource.valid - io.robMarkerRetireSourceBoundary := path.io.robMarkerRetireSource.isBoundary - io.robMarkerRetireSourceStop := path.io.robMarkerRetireSource.isStop - io.robMarkerRetireSourceLast := path.io.robMarkerRetireSource.isLast - io.robMarkerRetireSourceBidValid := path.io.robMarkerRetireSource.bid.valid - io.robMarkerRetireSourceBidWrap := path.io.robMarkerRetireSource.bid.wrap - io.robMarkerRetireSourceBidValue := path.io.robMarkerRetireSource.bid.value - io.robMarkerRetireSourceRidValid := path.io.robMarkerRetireSource.rid.valid - io.robMarkerRetireSourceRidWrap := path.io.robMarkerRetireSource.rid.wrap - io.robMarkerRetireSourceRidValue := path.io.robMarkerRetireSource.rid.value - io.robMarkerRetireSourceStid := path.io.robMarkerRetireSource.stid - io.robMarkerRetireSourceBlockBidValid := path.io.robMarkerRetireSource.blockBidValid - io.robMarkerRetireSourceBlockBid := path.io.robMarkerRetireSource.blockBid - io.robMarkerRetireSourceBoundaryTarget := path.io.robMarkerRetireSource.boundaryTarget - io.decRenPushFire := path.io.decRenPushFire - io.decRenPopFire := path.io.decRenPopFire - io.decRenCount := path.io.decRenCount - io.decRenValid := path.io.decRenValid - io.decRenHeadPc := path.io.decRenHeadPc - io.decRenHeadRidValid := path.io.decRenHeadRidValid - io.decRenHeadRidValue := path.io.decRenHeadRidValue - io.renamedOutValid := path.io.renamedOutValid - io.renamedAccepted := path.io.accepted - io.executeAccepted := execute.io.accepted - io.executeBusy := execute.io.busy - io.executeCompleteValid := execute.io.completeValid - io.executeCompleteRobValue := execute.io.completeRobValue - io.executeLoadWaitHold := execute.io.loadWaitHold - io.loadLookupValid := loadLookupArbiter.io.lookupValid - io.loadLookupAddr := loadLookupArbiter.io.lookupAddr - io.loadLookupPc := loadLookupArbiter.io.lookupPc - io.loadLookupDstValid := executeLoadLookupDst.valid - io.loadLookupDstKind := executeLoadLookupDst.kind.asUInt - io.loadLookupDstArchTag := executeLoadLookupDst.archTag - io.loadLookupDstRelTag := executeLoadLookupDst.relTag - io.loadLookupDstPhysTag := executeLoadLookupDst.physTag - io.loadLookupDstOldPhysTag := executeLoadLookupDst.oldPhysTag - io.loadLookupExecuteGranted := loadLookupArbiter.io.executeGranted - io.loadLookupReplayGranted := loadLookupArbiter.io.replayGranted - io.reducedStoreDispatchEnabled := useReducedStoreDispatchStq.B - io.reducedStoreExecCompleteStoreValid := storeExecBridge.io.completeStoreValid - io.reducedStoreExecCaptureFire := storeExecBridge.io.captureFire - io.reducedStoreExecCaptureBlocked := storeExecBridge.io.captureBlocked - io.reducedStoreExecCaptureDuplicate := storeExecBridge.io.captureDuplicate - io.reducedStoreExecStaMatch := storeExecBridge.io.staMatch - io.reducedStoreExecStdMatch := storeExecBridge.io.stdMatch - io.reducedStoreExecValidMask := storeExecBridge.io.validMask - io.reducedStoreExecBufferCount := storeExecBridge.io.bufferCount - io.reducedStoreStaExecValid := storeExecBridge.io.staExec.valid - io.reducedStoreStdExecValid := storeExecBridge.io.stdExec.valid - io.reducedStoreCommitStoreSeen := storeCommitOwner.io.commitStoreSeen - io.reducedStoreCommitStoreMatched := storeCommitOwner.io.commitStoreMatched - io.reducedStoreCommitStoreUnmatched := storeCommitOwner.io.commitStoreUnmatched - io.reducedStoreCommitReleasedByEarlySafe := storeCommitOwner.io.commitStoreReleasedByEarlySafe - io.reducedStoreCommitMatchMask := storeCommitOwner.io.matchMask - io.reducedStoreCommitEarlySafeMatchMask := storeCommitOwner.io.earlySafeMatchMask - io.reducedStoreCommitPendingIdentityMask := storeCommitOwner.io.pendingCommitIdentityMask - io.reducedStoreCommitPendingEarlySafeMask := storeCommitOwner.io.pendingCommitEarlySafeMask - io.reducedStoreCommitResidentEarlySafeMask := storeCommitOwner.io.residentEarlySafeMask - io.reducedStoreCommitPendingMarkMask := storeCommitOwner.io.pendingMarkMask - io.reducedStoreCommitPendingFreeMask := storeCommitOwner.io.pendingFreeMask - io.reducedStoreCommitPendingMarkCount := storeCommitOwner.io.pendingMarkCount - io.reducedStoreCommitPendingFreeCount := storeCommitOwner.io.pendingFreeCount - io.reducedStoreCommitMarkValid := storeCommitOwner.io.markCommitValid - io.reducedStoreCommitMarkIndex := storeCommitOwner.io.markCommitIndex - io.reducedStoreCommitMarkAccepted := path.io.storeMarkCommitAccepted - io.reducedStoreCommitMarkIgnored := path.io.storeMarkCommitIgnored - io.reducedStoreCommitMarkBlocked := storeCommitOwner.io.markBlocked - io.reducedStoreCommitFreeValid := path.io.storeCommitFreeMaskValid - io.reducedStoreCommitFreeIndex := 0.U - io.reducedStoreCommitFreeAccepted := path.io.storeCommitFreeAcceptedMask.orR - io.reducedStoreCommitFreeIgnored := path.io.storeCommitFreeIgnoredMask.orR - io.reducedStoreCommitFreeAcceptedMask := path.io.storeCommitFreeAcceptedMask - io.reducedStoreCommitFreeIgnoredMask := path.io.storeCommitFreeIgnoredMask - io.reducedStoreCommitFreeCount := path.io.storeCommitFreeCount - io.reducedStoreCommitFreeBlocked := storeCommitOwner.io.freeBlocked - io.reducedStoreDrainEnqueueAccepted := reducedStoreCommitDrain.io.enqueueAccepted - io.reducedStoreDrainEnqueueDuplicate := reducedStoreCommitDrain.io.enqueueDuplicate - io.reducedStoreDrainIssueValidMask := reducedStoreCommitDrain.io.issueValidMask - io.reducedStoreDrainIssueCount := reducedStoreCommitDrain.io.issueCount - io.reducedStoreDrainEarlyFreeMask := reducedStoreCommitDrain.io.commitFreeMask - io.reducedStoreDrainQueueCount := reducedStoreCommitDrain.io.queueCount - io.reducedStoreDrainEmpty := reducedStoreCommitDrain.io.empty - io.reducedStoreDrainOrderError := reducedStoreCommitDrain.io.orderError - io.reducedStoreScbReadyForDrain := reducedStoreScbReadyForDrain - io.reducedStoreScbAcceptedMask := reducedStoreScb.io.acceptedMask - io.reducedStoreScbStalledMask := reducedStoreScb.io.stalledMask - io.reducedStoreScbCommitFreeMaskValid := reducedStoreScb.io.commitFreeMaskValid - io.reducedStoreScbCommitFreeMask := reducedStoreScb.io.commitFreeMask - io.reducedStoreScbCommitFreeCount := reducedStoreScb.io.commitFreeCount - io.reducedStoreScbValidMask := reducedStoreScb.io.validMask - io.reducedStoreScbEntryCount := reducedStoreScb.io.entryCount - io.reducedStoreMemoryValidMask := reducedStoreMemoryOverlay.io.validMask - io.reducedStoreMemoryLineCount := reducedStoreMemoryOverlay.io.lineCount - io.reducedStoreMemoryLoadForwardMask := reducedStoreMemoryOverlay.io.loadForwardMask - io.reducedStoreMemoryStoreDroppedMask := reducedStoreMemoryOverlay.io.storeDroppedMask - io.reducedStoreResidentForwardMask := reducedStoreResidentForward.io.loadForwardMask - io.reducedStoreResidentWaitMask := reducedStoreResidentForward.io.waitMask - io.reducedStoreResidentEligibleMask := reducedStoreResidentForward.io.eligibleStoreMask - io.reducedStoreResidentReadyForward := reducedStoreResidentForward.io.readyForward - io.reducedStoreResidentWaitBlocked := reducedStoreResidentForward.io.waitBlocked - io.reducedStoreResidentWaitStoreValid := reducedStoreResidentForward.io.waitStore.valid - io.reducedStoreResidentWaitStoreIndex := reducedStoreResidentForward.io.waitStore.storeIndex - io.reducedStoreResidentWaitStoreBidValid := reducedStoreResidentForward.io.waitStore.storeId.valid - io.reducedStoreResidentWaitStoreBidWrap := reducedStoreResidentForward.io.waitStore.storeId.wrap - io.reducedStoreResidentWaitStoreBidValue := reducedStoreResidentForward.io.waitStore.storeId.value - io.reducedStoreResidentWaitStoreLsIdValid := reducedStoreResidentForward.io.waitStore.storeLsId.valid - io.reducedStoreResidentWaitStoreLsIdWrap := reducedStoreResidentForward.io.waitStore.storeLsId.wrap - io.reducedStoreResidentWaitStoreLsIdValue := reducedStoreResidentForward.io.waitStore.storeLsId.value - io.reducedStoreResidentWaitStorePc := reducedStoreResidentForward.io.waitStore.pc - io.reducedStoreResidentLoadCrossesLine := reducedStoreResidentForward.io.loadCrossesLine - io.reducedStoreResidentReplayWakeValid := reducedStoreResidentReplayWakeup.io.wakeValid - io.reducedStoreResidentReplayWakeSelected := reducedStoreResidentReplayWakeup.io.selectedRowValid - io.reducedStoreResidentReplayWakeIdentityMatch := reducedStoreResidentReplayWakeup.io.identityMatch - io.reducedStoreResidentReplayWakeReady := reducedStoreResidentReplayWakeup.io.selectedRowReady - io.reducedStoreResidentReplayWakeCrossesLine := reducedStoreResidentReplayWakeup.io.selectedRowCrossesLine - io.reducedStoreResidentReplayWakeLineAddr := reducedStoreResidentReplayWakeup.io.wake.lineAddr - io.reducedStoreResidentReplayWakeByteMask := reducedStoreResidentReplayWakeup.io.wakeByteMask - io.reducedLoadWaitReplayActive := reducedLoadWaitReplaySlot.io.active - io.reducedLoadWaitReplayCaptureAccepted := reducedLoadWaitReplaySlot.io.captureAccepted - io.reducedLoadWaitReplayClearValid := reducedLoadWaitReplaySlot.io.waitStoreClear - io.reducedLoadWaitReplayStoredWaitValid := reducedLoadWaitReplaySlot.io.storedWaitStore.valid - io.reducedLoadWaitReplayStoredWaitPc := reducedLoadWaitReplaySlot.io.storedWaitStore.pc - io.reducedLoadWaitReplayRelaunchValid := reducedLoadWaitReplaySlot.io.relaunch.valid - io.reducedLoadWaitReplayRelaunchPc := reducedLoadWaitReplaySlot.io.relaunch.pc - io.reducedLoadWaitReplayRelaunchAddr := reducedLoadWaitReplaySlot.io.relaunch.addr - io.reducedLoadWaitReplayRelaunchSize := reducedLoadWaitReplaySlot.io.relaunch.size - io.reducedLoadWaitReplayRelaunchReturnSignExtend := reducedLoadWaitReplaySlot.io.relaunch.returnSignExtend - io.reducedLoadWaitReplayRelaunchDstValid := reducedLoadWaitReplaySlot.io.relaunch.dst.valid - io.reducedLoadWaitReplayRelaunchDstKind := reducedLoadWaitReplaySlot.io.relaunch.dst.kind.asUInt - io.reducedLoadWaitReplayRelaunchDstArchTag := reducedLoadWaitReplaySlot.io.relaunch.dst.archTag - io.reducedLoadWaitReplayRelaunchDstRelTag := reducedLoadWaitReplaySlot.io.relaunch.dst.relTag - io.reducedLoadWaitReplayRelaunchDstPhysTag := reducedLoadWaitReplaySlot.io.relaunch.dst.physTag - io.reducedLoadWaitReplayRelaunchDstOldPhysTag := reducedLoadWaitReplaySlot.io.relaunch.dst.oldPhysTag - io.reducedLoadWaitReplayRelaunchBidValid := reducedLoadWaitReplaySlot.io.relaunch.bid.valid - io.reducedLoadWaitReplayRelaunchBidWrap := reducedLoadWaitReplaySlot.io.relaunch.bid.wrap - io.reducedLoadWaitReplayRelaunchBidValue := reducedLoadWaitReplaySlot.io.relaunch.bid.value - io.reducedLoadWaitReplayRelaunchGidValid := reducedLoadWaitReplaySlot.io.relaunch.gid.valid - io.reducedLoadWaitReplayRelaunchGidWrap := reducedLoadWaitReplaySlot.io.relaunch.gid.wrap - io.reducedLoadWaitReplayRelaunchGidValue := reducedLoadWaitReplaySlot.io.relaunch.gid.value - io.reducedLoadWaitReplayRelaunchRidValid := reducedLoadWaitReplaySlot.io.relaunch.rid.valid - io.reducedLoadWaitReplayRelaunchRidWrap := reducedLoadWaitReplaySlot.io.relaunch.rid.wrap - io.reducedLoadWaitReplayRelaunchRidValue := reducedLoadWaitReplaySlot.io.relaunch.rid.value - io.reducedLoadWaitReplayRelaunchLsIdValid := reducedLoadWaitReplaySlot.io.relaunch.loadLsId.valid - io.reducedLoadWaitReplayRelaunchLsIdWrap := reducedLoadWaitReplaySlot.io.relaunch.loadLsId.wrap - io.reducedLoadWaitReplayRelaunchLsIdValue := reducedLoadWaitReplaySlot.io.relaunch.loadLsId.value - io.reducedLoadWaitReplayRelaunchYoungestStoreIdValid := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreId.valid - io.reducedLoadWaitReplayRelaunchYoungestStoreIdWrap := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreId.wrap - io.reducedLoadWaitReplayRelaunchYoungestStoreIdValue := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreId.value - io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdValid := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreLsId.valid - io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdWrap := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreLsId.wrap - io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdValue := reducedLoadWaitReplaySlot.io.relaunch.youngestStoreLsId.value - io.reducedLoadReplayQueueEnqueueReady := reducedLoadReplayRelaunchQueue.io.enqueueReady - io.reducedLoadReplayQueueEnqueueAccepted := reducedLoadReplayRelaunchQueue.io.enqueueAccepted - io.reducedLoadReplayQueueEnqueueDropped := reducedLoadReplayRelaunchQueue.io.enqueueDropped - io.reducedLoadReplayQueueOutValid := reducedLoadReplayRelaunchQueue.io.outValid - io.reducedLoadReplayQueueOutFire := reducedLoadReplayRelaunchQueue.io.outFire - io.reducedLoadReplayQueuePending := reducedLoadReplayRelaunchQueue.io.pending - io.reducedLoadReplayQueueFull := reducedLoadReplayRelaunchQueue.io.full - io.reducedLoadReplayQueueCount := reducedLoadReplayRelaunchQueue.io.count - io.reducedLoadReplayQueueOutPc := reducedLoadReplayRelaunchQueue.io.out.pc - io.reducedLoadReplayQueueOutAddr := reducedLoadReplayRelaunchQueue.io.out.addr - io.reducedLoadReplayQueueOutSize := reducedLoadReplayRelaunchQueue.io.out.size - io.reducedLoadReplayQueueOutReturnSignExtend := reducedLoadReplayRelaunchQueue.io.out.returnSignExtend - io.reducedLoadReplayQueueOutDstValid := reducedLoadReplayRelaunchQueue.io.out.dst.valid - io.reducedLoadReplayQueueOutDstKind := reducedLoadReplayRelaunchQueue.io.out.dst.kind.asUInt - io.reducedLoadReplayQueueOutDstArchTag := reducedLoadReplayRelaunchQueue.io.out.dst.archTag - io.reducedLoadReplayQueueOutDstRelTag := reducedLoadReplayRelaunchQueue.io.out.dst.relTag - io.reducedLoadReplayQueueOutDstPhysTag := reducedLoadReplayRelaunchQueue.io.out.dst.physTag - io.reducedLoadReplayQueueOutDstOldPhysTag := reducedLoadReplayRelaunchQueue.io.out.dst.oldPhysTag - io.reducedLoadReplayQueueOutBidValid := reducedLoadReplayRelaunchQueue.io.out.bid.valid - io.reducedLoadReplayQueueOutBidWrap := reducedLoadReplayRelaunchQueue.io.out.bid.wrap - io.reducedLoadReplayQueueOutBidValue := reducedLoadReplayRelaunchQueue.io.out.bid.value - io.reducedLoadReplayQueueOutGidValid := reducedLoadReplayRelaunchQueue.io.out.gid.valid - io.reducedLoadReplayQueueOutGidWrap := reducedLoadReplayRelaunchQueue.io.out.gid.wrap - io.reducedLoadReplayQueueOutGidValue := reducedLoadReplayRelaunchQueue.io.out.gid.value - io.reducedLoadReplayQueueOutRidValid := reducedLoadReplayRelaunchQueue.io.out.rid.valid - io.reducedLoadReplayQueueOutRidWrap := reducedLoadReplayRelaunchQueue.io.out.rid.wrap - io.reducedLoadReplayQueueOutRidValue := reducedLoadReplayRelaunchQueue.io.out.rid.value - io.reducedLoadReplayQueueOutLsIdValid := reducedLoadReplayRelaunchQueue.io.out.loadLsId.valid - io.reducedLoadReplayQueueOutLsIdWrap := reducedLoadReplayRelaunchQueue.io.out.loadLsId.wrap - io.reducedLoadReplayQueueOutLsIdValue := reducedLoadReplayRelaunchQueue.io.out.loadLsId.value - io.reducedLoadReplayQueueOutYoungestStoreIdValid := reducedLoadReplayRelaunchQueue.io.out.youngestStoreId.valid - io.reducedLoadReplayQueueOutYoungestStoreIdWrap := reducedLoadReplayRelaunchQueue.io.out.youngestStoreId.wrap - io.reducedLoadReplayQueueOutYoungestStoreIdValue := reducedLoadReplayRelaunchQueue.io.out.youngestStoreId.value - io.reducedLoadReplayQueueOutYoungestStoreLsIdValid := reducedLoadReplayRelaunchQueue.io.out.youngestStoreLsId.valid - io.reducedLoadReplayQueueOutYoungestStoreLsIdWrap := reducedLoadReplayRelaunchQueue.io.out.youngestStoreLsId.wrap - io.reducedLoadReplayQueueOutYoungestStoreLsIdValue := reducedLoadReplayRelaunchQueue.io.out.youngestStoreLsId.value - io.reducedLoadReplayDrainConsumeReady := reducedLoadReplayCompletionDrain.io.consumeReady - io.reducedLoadReplayDrainMatchValid := reducedLoadReplayCompletionDrain.io.matchValid - io.reducedLoadReplayDrainMismatch := reducedLoadReplayCompletionDrain.io.mismatch - io.reducedLoadReplayDrainPcMismatch := reducedLoadReplayCompletionDrain.io.pcMismatch - io.reducedLoadReplayDrainAddrMismatch := reducedLoadReplayCompletionDrain.io.addrMismatch - io.reducedLoadReplayDrainSizeMismatch := reducedLoadReplayCompletionDrain.io.sizeMismatch - io.reducedLoadReplayDrainBidMismatch := reducedLoadReplayCompletionDrain.io.bidMismatch - io.reducedLoadReplayDrainGidMismatch := reducedLoadReplayCompletionDrain.io.gidMismatch - io.reducedLoadReplayDrainRidMismatch := reducedLoadReplayCompletionDrain.io.ridMismatch - io.reducedLoadReplayDrainLsIdMismatch := reducedLoadReplayCompletionDrain.io.lsIdMismatch - io.reducedLoadReplayLiqAllocEnabled := reducedLoadReplayLiqAllocEnabled - io.reducedLoadReplayLiqAllocConsumeReady := reducedLoadReplayLiqAllocPath.io.candidateConsumeReady - io.reducedLoadReplayLiqAllocCandidateUsable := reducedLoadReplayLiqAllocPath.io.candidateUsable - io.reducedLoadReplayLiqAllocBlockedByAlloc := reducedLoadReplayLiqAllocPath.io.candidateBlockedByAlloc - io.reducedLoadReplayLiqAllocValid := reducedLoadReplayLiqAllocPath.io.allocValid - io.reducedLoadReplayLiqAllocReady := reducedLoadReplayLiqAllocPath.io.allocReady - io.reducedLoadReplayLiqAllocAccepted := reducedLoadReplayLiqAllocPath.io.allocAccepted - io.reducedLoadReplayLiqAllocIndex := reducedLoadReplayLiqAllocPath.io.allocIndex - io.reducedLoadReplayLiqAllocLoadIdValid := reducedLoadReplayLiqAllocPath.io.allocLoadId.valid - io.reducedLoadReplayLiqAllocLoadIdWrap := reducedLoadReplayLiqAllocPath.io.allocLoadId.wrap - io.reducedLoadReplayLiqAllocLoadIdValue := reducedLoadReplayLiqAllocPath.io.allocLoadId.value - io.reducedLoadReplayLiqOccupiedMask := reducedLoadReplayLiqAllocPath.io.occupiedMask - io.reducedLoadReplayLiqWaitMask := reducedLoadReplayLiqAllocPath.io.waitMask - io.reducedLoadReplayLiqWaitStoreMask := reducedLoadReplayLiqAllocPath.io.waitStoreMask - LinxCoreFrontendFetchRfAluTraceTopReplayWakeVisibilityWiring.connect( - io, - reducedLoadReplayLiqAllocPath, - reducedLoadReplayLiqReplayWakeValid, - reducedStoreFlush - ) - io.reducedLoadReplayLiqLaunchWaitMask := reducedLoadReplayLiqAllocPath.io.launchWaitMask - io.reducedLoadReplayLiqLaunchWaitStoreBlockedMask := reducedLoadReplayLiqAllocPath.io.launchWaitStoreBlockedMask - io.reducedLoadReplayLiqLaunchTileBlockedMask := reducedLoadReplayLiqAllocPath.io.launchTileBlockedMask - io.reducedLoadReplayLiqLaunchUnblockedWaitMask := reducedLoadReplayLiqAllocPath.io.launchUnblockedWaitMask - io.reducedLoadReplayLiqLaunchRequestCompleteMask := reducedLoadReplayLiqAllocPath.io.launchRequestCompleteMask - io.reducedLoadReplayLiqLaunchDataHitMask := reducedLoadReplayLiqAllocPath.io.launchDataHitMask - io.reducedLoadReplayLiqLaunchCandidateMask := reducedLoadReplayLiqAllocPath.io.launchCandidateMask - io.reducedLoadReplayLiqLaunchMask := reducedLoadReplayLiqAllocPath.io.launchMask - io.reducedLoadReplayLiqLaunchValid := reducedLoadReplayLiqAllocPath.io.launchValid - io.reducedLoadReplayLiqLaunchIndex := reducedLoadReplayLiqAllocPath.io.launchIndex - io.reducedLoadReplayLiqLaunchDriveValid := reducedLoadReplayLiqAllocPath.io.launchDriveValid - io.reducedLoadReplayLiqLaunchReady := reducedLoadReplayLiqAllocPath.io.launchReady - io.reducedLoadReplayLiqLaunchAccepted := reducedLoadReplayLiqAllocPath.io.launchAccepted - io.reducedLoadReplayLiqLaunchCandidateCount := reducedLoadReplayLiqAllocPath.io.launchCandidateCount - io.reducedLoadReplayLiqReturnCompleteRepickMask := reducedLoadReplayLiqAllocPath.io.returnCompleteRepickMask - io.reducedLoadReplayLiqReturnCompleteSourceReturnedMask := reducedLoadReplayLiqAllocPath.io.returnCompleteSourceReturnedMask - io.reducedLoadReplayLiqReturnCompleteDataCompleteMask := reducedLoadReplayLiqAllocPath.io.returnCompleteDataCompleteMask - io.reducedLoadReplayLiqReturnCompleteRequestCompleteMask := reducedLoadReplayLiqAllocPath.io.returnCompleteRequestCompleteMask - io.reducedLoadReplayLiqReturnCompleteCandidateMask := reducedLoadReplayLiqAllocPath.io.returnCompleteCandidateMask - io.reducedLoadReplayLiqReturnCompleteMask := reducedLoadReplayLiqAllocPath.io.returnCompleteMask - io.reducedLoadReplayLiqReturnCompleteValid := reducedLoadReplayLiqAllocPath.io.returnCompleteValid - io.reducedLoadReplayLiqReturnCompleteIndex := reducedLoadReplayLiqAllocPath.io.returnCompleteIndex - io.reducedLoadReplayLiqReturnCompleteCandidateCount := reducedLoadReplayLiqAllocPath.io.returnCompleteCandidateCount - io.reducedLoadReplayLiqLaunchSelectedLoadIdValid := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadId.valid - io.reducedLoadReplayLiqLaunchSelectedLoadIdWrap := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadId.wrap - io.reducedLoadReplayLiqLaunchSelectedLoadIdValue := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadId.value - io.reducedLoadReplayLiqLaunchSelectedBidValid := reducedLoadReplayLiqAllocPath.io.launchSelectedBid.valid - io.reducedLoadReplayLiqLaunchSelectedBidWrap := reducedLoadReplayLiqAllocPath.io.launchSelectedBid.wrap - io.reducedLoadReplayLiqLaunchSelectedBidValue := reducedLoadReplayLiqAllocPath.io.launchSelectedBid.value - io.reducedLoadReplayLiqLaunchSelectedGidValid := reducedLoadReplayLiqAllocPath.io.launchSelectedGid.valid - io.reducedLoadReplayLiqLaunchSelectedGidWrap := reducedLoadReplayLiqAllocPath.io.launchSelectedGid.wrap - io.reducedLoadReplayLiqLaunchSelectedGidValue := reducedLoadReplayLiqAllocPath.io.launchSelectedGid.value - io.reducedLoadReplayLiqLaunchSelectedRidValid := reducedLoadReplayLiqAllocPath.io.launchSelectedRid.valid - io.reducedLoadReplayLiqLaunchSelectedRidWrap := reducedLoadReplayLiqAllocPath.io.launchSelectedRid.wrap - io.reducedLoadReplayLiqLaunchSelectedRidValue := reducedLoadReplayLiqAllocPath.io.launchSelectedRid.value - io.reducedLoadReplayLiqLaunchSelectedLoadLsIdValid := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadLsId.valid - io.reducedLoadReplayLiqLaunchSelectedLoadLsIdWrap := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadLsId.wrap - io.reducedLoadReplayLiqLaunchSelectedLoadLsIdValue := reducedLoadReplayLiqAllocPath.io.launchSelectedLoadLsId.value - io.reducedLoadReplayLiqLaunchSelectedPc := reducedLoadReplayLiqAllocPath.io.launchSelectedPc - io.reducedLoadReplayLiqLaunchSelectedAddr := reducedLoadReplayLiqAllocPath.io.launchSelectedAddr - io.reducedLoadReplayLiqLaunchSelectedSize := reducedLoadReplayLiqAllocPath.io.launchSelectedSize - io.reducedLoadReplayLiqLaunchSelectedReturnSignExtend := reducedLoadReplayLiqAllocPath.io.launchSelectedReturnSignExtend - io.reducedLoadReplayLiqLaunchSelectedDstValid := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.valid - io.reducedLoadReplayLiqLaunchSelectedDstKind := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.kind.asUInt - io.reducedLoadReplayLiqLaunchSelectedDstArchTag := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.archTag - io.reducedLoadReplayLiqLaunchSelectedDstRelTag := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.relTag - io.reducedLoadReplayLiqLaunchSelectedDstPhysTag := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.physTag - io.reducedLoadReplayLiqLaunchSelectedDstOldPhysTag := reducedLoadReplayLiqAllocPath.io.launchSelectedDst.oldPhysTag - io.reducedLoadReplayLiqLaunchSelectedRequestByteMask := reducedLoadReplayLiqAllocPath.io.launchSelectedRequestByteMask - io.reducedLoadReplayLiqLaunchSelectedSpecWakeup := reducedLoadReplayLiqAllocPath.io.launchSelectedSpecWakeup - io.reducedLoadReplayLiqLaunchSelectedStackValid := reducedLoadReplayLiqAllocPath.io.launchSelectedStackValid - io.reducedLoadReplayLiqBaseLookupValid := reducedReplayLiqBaseDataAlign.io.requestValid - io.reducedLoadReplayLiqBaseLookupCrossesLine := reducedReplayLiqBaseDataAlign.io.requestCrossesLine - io.reducedLoadReplayLiqBaseLookupPc := reducedLoadReplayLiqAllocPath.io.launchSelectedPc - io.reducedLoadReplayLiqBaseLookupAddr := reducedLoadReplayLiqAllocPath.io.launchSelectedAddr - io.reducedLoadReplayLiqBaseLookupSize := reducedLoadReplayLiqAllocPath.io.launchSelectedSize - io.reducedLoadReplayLiqBaseLookupRequestByteMask := reducedReplayLiqBaseDataAlign.io.requestByteMask - io.reducedLoadReplayLiqBaseLineValidMask := reducedReplayLiqBaseDataAlign.io.lineValidMask - io.reducedLoadReplayLiqBaseDataReturned := reducedReplayLiqBaseDataReady - io.reducedLoadReplayLiqBaseLookupGranted := loadLookupArbiter.io.replayGranted - io.reducedLoadReplayLiqBaseLookupBlockedByExecute := loadLookupArbiter.io.replayBlockedByExecute - io.reducedLoadReplayLiqLaunchReadinessCandidateValid := reducedReplayLiqLaunchReadiness.io.candidateValid - io.reducedLoadReplayLiqLaunchReadinessBaseDataReady := reducedReplayLiqLaunchReadiness.io.baseDataReady - io.reducedLoadReplayLiqLaunchReadinessSourcesReturned := reducedReplayLiqLaunchReadiness.io.sourcesReturned - io.reducedLoadReplayLiqLaunchReadinessReady := reducedReplayLiqLaunchReadiness.io.launchReady - io.reducedLoadReplayLiqLaunchReadinessEnable := reducedReplayLiqLaunchReadiness.io.launchEnable - io.reducedLoadReplayLiqLaunchReadinessBlockedByDisabled := - reducedReplayLiqLaunchReadiness.io.blockedByDisabled - io.reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate := - reducedReplayLiqLaunchReadiness.io.blockedByNoCandidate - io.reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup := - reducedReplayLiqLaunchReadiness.io.blockedByBaseLookup - io.reducedLoadReplayLiqLaunchReadinessBlockedByBaseData := - reducedReplayLiqLaunchReadiness.io.blockedByBaseData - io.reducedLoadReplayLiqLaunchReadinessBlockedByScb := - reducedReplayLiqLaunchReadiness.io.blockedByScb - io.reducedLoadReplayLiqLaunchReadinessBlockedByReturn := - reducedReplayLiqLaunchReadiness.io.blockedByReturn - io.reducedLoadReplayLiqSourceReturnCandidateValid := - reducedReplayLiqSourceReturnReadiness.io.candidateValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotReady := reducedReplayLiqStoreSnapshotReady - LinxCoreFrontendFetchRfAluTraceTopR395StoreSnapshotPathWiring.connectOutputs( - io = io, - path = reducedReplayLiqSourceReturnStoreSnapshotPath - ) - io.reducedLoadReplayLiqSourceReturnStoreSourceReturned := - reducedReplayLiqSourceReturnReadiness.io.storeSourceReturned - io.reducedLoadReplayLiqSourceReturnScbSourceReturned := - reducedReplayLiqSourceReturnReadiness.io.scbSourceReturned - io.reducedLoadReplayLiqSourceReturnSourceReturned := - reducedReplayLiqSourceReturnReadiness.io.sourceReturned - io.reducedLoadReplayLiqSourceReturnBlockedByDisabled := - reducedReplayLiqSourceReturnReadiness.io.blockedByDisabled - io.reducedLoadReplayLiqSourceReturnBlockedByNoCandidate := - reducedReplayLiqSourceReturnReadiness.io.blockedByNoCandidate - io.reducedLoadReplayLiqSourceReturnBlockedByBaseData := - reducedReplayLiqSourceReturnReadiness.io.blockedByBaseData - io.reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot := - reducedReplayLiqSourceReturnReadiness.io.blockedByStoreSnapshot - io.reducedLoadReplayLiqSourceReturnBlockedByScb := - reducedReplayLiqSourceReturnReadiness.io.blockedByScb - io.reducedLoadReplayLiqSourceReturnScbLiveActive := - reducedReplayLiqSourceReturnScbLiveControl.io.active - io.reducedLoadReplayLiqSourceReturnScbLiveRequestActive := - reducedReplayLiqSourceReturnScbLiveControl.io.requestActive - io.reducedLoadReplayLiqSourceReturnScbLiveEvidenceValid := - reducedReplayLiqSourceReturnScbLiveControl.io.scbEvidenceValid - io.reducedLoadReplayLiqSourceReturnScbLivePending := - reducedReplayLiqSourceReturnScbLiveControl.io.externalScbPending - io.reducedLoadReplayLiqSourceReturnScbLiveReturned := - reducedReplayLiqSourceReturnScbLiveControl.io.externalScbReturned - io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByRequestDisabled := - reducedReplayLiqSourceReturnScbLiveControl.io.blockedByRequestDisabled - io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByNoPending := - reducedReplayLiqSourceReturnScbLiveControl.io.blockedByNoPending - io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByScbReturn := - reducedReplayLiqSourceReturnScbLiveControl.io.blockedByScbReturn - io.reducedLoadReplayLiqReturnConsumerCandidateValid := - reducedReplayLiqReturnConsumerReady.io.candidateValid - io.reducedLoadReplayLiqReturnConsumerLretSinkReady := - reducedReplayLiqReturnLretSinkReady - io.reducedLoadReplayLiqReturnConsumerWakeupSinkReady := - reducedReplayLiqReturnWakeupSinkReady - io.reducedLoadReplayLiqReturnConsumerWakeupRequired := - reducedReplayLiqReturnConsumerReady.io.wakeupRequired - io.reducedLoadReplayLiqReturnConsumerReady := - reducedReplayLiqReturnConsumerReady.io.consumerReady - io.reducedLoadReplayLiqReturnConsumerBlockedByDisabled := - reducedReplayLiqReturnConsumerReady.io.blockedByDisabled - io.reducedLoadReplayLiqReturnConsumerBlockedByNoCandidate := - reducedReplayLiqReturnConsumerReady.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnConsumerBlockedBySources := - reducedReplayLiqReturnConsumerReady.io.blockedBySources - io.reducedLoadReplayLiqReturnConsumerBlockedByLretSink := - reducedReplayLiqReturnConsumerReady.io.blockedByLretSink - io.reducedLoadReplayLiqReturnConsumerBlockedByWakeupSink := - reducedReplayLiqReturnConsumerReady.io.blockedByWakeupSink - io.reducedLoadReplayLiqReturnPipeBudgetCandidateValid := - reducedReplayLiqReturnPipeBudget.io.candidateValid - io.reducedLoadReplayLiqReturnPipeBudgetEnable := - reducedLoadReplayLiqAllocEnabled - io.reducedLoadReplayLiqReturnPipeBudgetConsumerReady := - reducedReplayLiqReturnConsumerReady.io.consumerReady - io.reducedLoadReplayLiqReturnPipeBudgetAvailable := - reducedReplayLiqReturnPipeBudget.io.pipeBudgetAvailable - io.reducedLoadReplayLiqReturnPipeBudgetBlockedByDisabled := - reducedReplayLiqReturnPipeBudget.io.blockedByDisabled - io.reducedLoadReplayLiqReturnPipeBudgetBlockedByNoCandidate := - reducedReplayLiqReturnPipeBudget.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnPipeBudgetBlockedBySources := - reducedReplayLiqReturnPipeBudget.io.blockedBySources - io.reducedLoadReplayLiqReturnPipeBudgetBlockedByBudgetDisabled := - reducedReplayLiqReturnPipeBudget.io.blockedByBudgetDisabled - io.reducedLoadReplayLiqReturnPipeBudgetBlockedByConsumer := - reducedReplayLiqReturnPipeBudget.io.blockedByConsumer - io.reducedLoadReplayLiqReturnPipePermitCandidateValid := - reducedReplayLiqReturnPipePermit.io.candidateValid - io.reducedLoadReplayLiqReturnPipePermitPipeBudgetAvailable := - reducedReplayLiqReturnPipeBudget.io.pipeBudgetAvailable - io.reducedLoadReplayLiqReturnPipePermitMask := - reducedReplayLiqReturnPipePermit.io.pipeAvailableMask - io.reducedLoadReplayLiqReturnPipePermitValid := - reducedReplayLiqReturnPipePermit.io.permitValid - io.reducedLoadReplayLiqReturnPipePermitBlockedByDisabled := - reducedReplayLiqReturnPipePermit.io.blockedByDisabled - io.reducedLoadReplayLiqReturnPipePermitBlockedByNoCandidate := - reducedReplayLiqReturnPipePermit.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnPipePermitBlockedBySources := - reducedReplayLiqReturnPipePermit.io.blockedBySources - io.reducedLoadReplayLiqReturnPipePermitBlockedByPipeBudget := - reducedReplayLiqReturnPipePermit.io.blockedByPipeBudget - io.reducedLoadReplayLiqReturnPipeAvailableMask := - reducedReplayLiqReturnPipePermit.io.pipeAvailableMask - io.reducedLoadReplayLiqReturnPipeCandidateValid := - reducedReplayLiqReturnPipeSelect.io.candidateValid - io.reducedLoadReplayLiqReturnPipeAvailable := - reducedReplayLiqReturnPipeSelect.io.pipeAvailable - io.reducedLoadReplayLiqReturnPipeSelectedPipeIndex := - reducedReplayLiqReturnPipeSelect.io.selectedPipeIndex - io.reducedLoadReplayLiqReturnPipeBlockedByDisabled := - reducedReplayLiqReturnPipeSelect.io.blockedByDisabled - io.reducedLoadReplayLiqReturnPipeBlockedByNoCandidate := - reducedReplayLiqReturnPipeSelect.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnPipeBlockedBySources := - reducedReplayLiqReturnPipeSelect.io.blockedBySources - io.reducedLoadReplayLiqReturnPipeBlockedByNoPipe := - reducedReplayLiqReturnPipeSelect.io.blockedByNoPipe - io.reducedLoadReplayLiqReturnReadinessCandidateValid := - reducedReplayLiqReturnReadiness.io.candidateValid - io.reducedLoadReplayLiqReturnReadinessReady := - reducedReplayLiqReturnReadiness.io.returnReady - io.reducedLoadReplayLiqReturnReadinessSelectedPipeIndex := - reducedReplayLiqReturnReadiness.io.selectedPipeIndex - io.reducedLoadReplayLiqReturnReadinessBlockedByDisabled := - reducedReplayLiqReturnReadiness.io.blockedByDisabled - io.reducedLoadReplayLiqReturnReadinessBlockedByNoCandidate := - reducedReplayLiqReturnReadiness.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnReadinessBlockedBySources := - reducedReplayLiqReturnReadiness.io.blockedBySources - io.reducedLoadReplayLiqReturnReadinessBlockedByReturnPipe := - reducedReplayLiqReturnReadiness.io.blockedByReturnPipe - io.reducedLoadReplayLiqReturnDataCandidateValid := reducedReplayLiqReturnDataExtract.io.candidateValid - io.reducedLoadReplayLiqReturnDataRequestByteMask := reducedReplayLiqReturnDataExtract.io.requestByteMask - io.reducedLoadReplayLiqReturnDataBytesComplete := reducedReplayLiqReturnDataExtract.io.bytesComplete - io.reducedLoadReplayLiqReturnDataCrossLine := reducedReplayLiqReturnDataExtract.io.crossLine - io.reducedLoadReplayLiqReturnDataSizeSupported := reducedReplayLiqReturnDataExtract.io.sizeSupported - io.reducedLoadReplayLiqReturnDataRawData := reducedReplayLiqReturnDataExtract.io.rawData - io.reducedLoadReplayLiqReturnData := reducedReplayLiqReturnDataExtract.io.data - io.reducedLoadReplayLiqReturnDataValid := reducedReplayLiqReturnDataExtract.io.dataValid - io.reducedLoadReplayLiqReturnDataBlockedByDisabled := - reducedReplayLiqReturnDataExtract.io.blockedByDisabled - io.reducedLoadReplayLiqReturnDataBlockedByNoCandidate := - reducedReplayLiqReturnDataExtract.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnDataBlockedByZeroSize := - reducedReplayLiqReturnDataExtract.io.blockedByZeroSize - io.reducedLoadReplayLiqReturnDataBlockedByUnsupportedSize := - reducedReplayLiqReturnDataExtract.io.blockedByUnsupportedSize - io.reducedLoadReplayLiqReturnDataBlockedByCrossLine := - reducedReplayLiqReturnDataExtract.io.blockedByCrossLine - io.reducedLoadReplayLiqReturnDataBlockedByIncompleteBytes := - reducedReplayLiqReturnDataExtract.io.blockedByIncompleteBytes - io.reducedLoadReplayLiqReturnPublishCandidateValid := - reducedReplayLiqReturnPublishReady.io.candidateValid - io.reducedLoadReplayLiqReturnPublishDataReady := - reducedReplayLiqReturnPublishReady.io.dataReady - io.reducedLoadReplayLiqReturnPublishReady := - reducedReplayLiqReturnPublishReady.io.publishReady - io.reducedLoadReplayLiqReturnPublishBlockedByDisabled := - reducedReplayLiqReturnPublishReady.io.blockedByDisabled - io.reducedLoadReplayLiqReturnPublishBlockedByNoCandidate := - reducedReplayLiqReturnPublishReady.io.blockedByNoCandidate - io.reducedLoadReplayLiqReturnPublishBlockedByData := - reducedReplayLiqReturnPublishReady.io.blockedByData - io.reducedLoadReplayLiqReturnPublishBlockedByConsumer := - reducedReplayLiqReturnPublishReady.io.blockedByConsumer - io.reducedLoadReplayLiqLretPayloadCandidateValid := - reducedReplayLiqReturnLretPayload.io.candidateValid - io.reducedLoadReplayLiqLretPayloadValid := - reducedReplayLiqReturnLretPayload.io.payloadValid - io.reducedLoadReplayLiqLretPayloadBidValid := - reducedReplayLiqReturnLretPayload.io.payloadBid.valid - io.reducedLoadReplayLiqLretPayloadBidWrap := - reducedReplayLiqReturnLretPayload.io.payloadBid.wrap - io.reducedLoadReplayLiqLretPayloadBidValue := - reducedReplayLiqReturnLretPayload.io.payloadBid.value - io.reducedLoadReplayLiqLretPayloadGidValid := - reducedReplayLiqReturnLretPayload.io.payloadGid.valid - io.reducedLoadReplayLiqLretPayloadGidWrap := - reducedReplayLiqReturnLretPayload.io.payloadGid.wrap - io.reducedLoadReplayLiqLretPayloadGidValue := - reducedReplayLiqReturnLretPayload.io.payloadGid.value - io.reducedLoadReplayLiqLretPayloadRidValid := - reducedReplayLiqReturnLretPayload.io.payloadRid.valid - io.reducedLoadReplayLiqLretPayloadRidWrap := - reducedReplayLiqReturnLretPayload.io.payloadRid.wrap - io.reducedLoadReplayLiqLretPayloadRidValue := - reducedReplayLiqReturnLretPayload.io.payloadRid.value - io.reducedLoadReplayLiqLretPayloadLoadLsIdValid := - reducedReplayLiqReturnLretPayload.io.payloadLoadLsId.valid - io.reducedLoadReplayLiqLretPayloadLoadLsIdWrap := - reducedReplayLiqReturnLretPayload.io.payloadLoadLsId.wrap - io.reducedLoadReplayLiqLretPayloadLoadLsIdValue := - reducedReplayLiqReturnLretPayload.io.payloadLoadLsId.value - io.reducedLoadReplayLiqLretPayloadPc := - reducedReplayLiqReturnLretPayload.io.payloadPc - io.reducedLoadReplayLiqLretPayloadAddr := - reducedReplayLiqReturnLretPayload.io.payloadAddr - io.reducedLoadReplayLiqLretPayloadSize := - reducedReplayLiqReturnLretPayload.io.payloadSize - io.reducedLoadReplayLiqLretPayloadDstValid := - reducedReplayLiqReturnLretPayload.io.payloadDst.valid - io.reducedLoadReplayLiqLretPayloadDstKind := - reducedReplayLiqReturnLretPayload.io.payloadDst.kind.asUInt - io.reducedLoadReplayLiqLretPayloadDstArchTag := - reducedReplayLiqReturnLretPayload.io.payloadDst.archTag - io.reducedLoadReplayLiqLretPayloadDstRelTag := - reducedReplayLiqReturnLretPayload.io.payloadDst.relTag - io.reducedLoadReplayLiqLretPayloadDstPhysTag := - reducedReplayLiqReturnLretPayload.io.payloadDst.physTag - io.reducedLoadReplayLiqLretPayloadDstOldPhysTag := - reducedReplayLiqReturnLretPayload.io.payloadDst.oldPhysTag - io.reducedLoadReplayLiqLretPayloadData := - reducedReplayLiqReturnLretPayload.io.payloadData - io.reducedLoadReplayLiqLretPayloadPipeIndex := - reducedReplayLiqReturnLretPayload.io.payloadPipeIndex - io.reducedLoadReplayLiqLretPayloadSpecWakeup := - reducedReplayLiqReturnLretPayload.io.payloadSpecWakeup - io.reducedLoadReplayLiqLretPayloadStackValid := - reducedReplayLiqReturnLretPayload.io.payloadStackValid - io.reducedLoadReplayLiqLretPayloadWakeupRequired := - reducedReplayLiqReturnLretPayload.io.wakeupRequired - io.reducedLoadReplayLiqLretPayloadBlockedByDisabled := - reducedReplayLiqReturnLretPayload.io.blockedByDisabled - io.reducedLoadReplayLiqLretPayloadBlockedByNoCandidate := - reducedReplayLiqReturnLretPayload.io.blockedByNoCandidate - io.reducedLoadReplayLiqLretPayloadBlockedByData := - reducedReplayLiqReturnLretPayload.io.blockedByData - io.reducedLoadReplayLiqLretSinkEnqueueReady := - reducedReplayLiqReturnLretSink.io.enqueueReady - io.reducedLoadReplayLiqLretSinkEnqueueAccepted := - reducedReplayLiqReturnLretSink.io.enqueueAccepted - io.reducedLoadReplayLiqLretSinkEnqueueDropped := - reducedReplayLiqReturnLretSink.io.enqueueDropped - io.reducedLoadReplayLiqLretSinkDrainValid := - reducedReplayLiqReturnLretSink.io.drainValid - io.reducedLoadReplayLiqLretSinkDrainFire := - reducedReplayLiqReturnLretSink.io.drainFire - io.reducedLoadReplayLiqLretSinkPending := - reducedReplayLiqReturnLretSink.io.pending - io.reducedLoadReplayLiqLretSinkFull := - reducedReplayLiqReturnLretSink.io.full - io.reducedLoadReplayLiqLretSinkEmpty := - reducedReplayLiqReturnLretSink.io.empty - io.reducedLoadReplayLiqLretSinkCount := - reducedReplayLiqReturnLretSink.io.totalCount - io.reducedLoadReplayLiqLretSinkDrainStid := - reducedReplayLiqReturnLretSink.io.drainStid - io.reducedLoadReplayLiqLretSinkPrecisePruneCount := - reducedReplayLiqReturnLretSink.io.precisePruneCount - io.reducedLoadReplayLiqLretSinkBlockedByFlush := - reducedReplayLiqReturnLretSink.io.blockedByFlush - io.reducedLoadReplayLiqLretSinkBlockedByNoPayload := - reducedReplayLiqReturnLretSink.io.blockedByNoPayload - io.reducedLoadReplayLiqLretSinkBlockedByFull := - reducedReplayLiqReturnLretSink.io.blockedByFull - io.reducedLoadReplayLiqLretSinkBlockedByDrain := - reducedReplayLiqReturnLretSink.io.blockedByDrain - io.reducedLoadReplayLiqLretDrainPermitEnable := - reducedReplayLiqReturnIexDrainPermit.io.enable - io.reducedLoadReplayLiqLretDrainPermitPipeOccupiedMask := - reducedReplayLiqReturnIexPipeOccupiedMask - io.reducedLoadReplayLiqLretDrainPermitPipeFreeMask := - reducedReplayLiqReturnIexDrainPermit.io.pipeFreeMask - io.reducedLoadReplayLiqLretDrainPermitAnyPipeFree := - reducedReplayLiqReturnIexDrainPermit.io.anyPipeFree - io.reducedLoadReplayLiqLretDrainPermitSelectedPipeIndex := - reducedReplayLiqReturnIexDrainPermit.io.selectedPipeIndex - io.reducedLoadReplayLiqLretDrainPermitReady := - reducedReplayLiqReturnIexDrainPermit.io.drainReady - io.reducedLoadReplayLiqLretDrainPermitBlockedByDisabled := - reducedReplayLiqReturnIexDrainPermit.io.blockedByDisabled - io.reducedLoadReplayLiqLretDrainPermitBlockedByFlush := - reducedReplayLiqReturnIexDrainPermit.io.blockedByFlush - io.reducedLoadReplayLiqLretDrainPermitBlockedByNoEntry := - reducedReplayLiqReturnIexDrainPermit.io.blockedByNoEntry - io.reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull := - reducedReplayLiqReturnIexDrainPermit.io.blockedByPipeFull - io.reducedLoadReplayLiqLretIexDataEnable := - reducedReplayLiqReturnIexDataCandidate.io.enable - io.reducedLoadReplayLiqLretIexDataRobRowValid := - path.io.robStatusLookup.rowValid - io.reducedLoadReplayLiqLretIexDataRobRowNeedFlush := - path.io.robStatusLookup.needFlush - io.reducedLoadReplayLiqLretIexDataRobRowBlockedByInvalidRid := - path.io.robStatusLookup.blockedByInvalidRid - io.reducedLoadReplayLiqLretIexDataRobRowBlockedByFree := - path.io.robStatusLookup.blockedByFree - io.reducedLoadReplayLiqLretIexDataRobRowBlockedByStaleRid := - path.io.robStatusLookup.blockedByStaleRid - io.reducedLoadReplayLiqLretIexDataCandidateValid := - reducedReplayLiqReturnIexDataCandidate.io.candidateValid - io.reducedLoadReplayLiqLretIexDataWouldDrain := - reducedReplayLiqReturnIexDataCandidate.io.wouldDrain - io.reducedLoadReplayLiqLretIexDataSetMemDataValid := - reducedReplayLiqReturnIexDataCandidate.io.setMemDataValid - io.reducedLoadReplayLiqLretIexDataBlockedByDisabled := - reducedReplayLiqReturnIexDataCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretIexDataBlockedByFlush := - reducedReplayLiqReturnIexDataCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretIexDataBlockedByNoEntry := - reducedReplayLiqReturnIexDataCandidate.io.blockedByNoEntry - io.reducedLoadReplayLiqLretIexDataBlockedByInvalidEntry := - reducedReplayLiqReturnIexDataCandidate.io.blockedByInvalidEntry - io.reducedLoadReplayLiqLretIexDataBlockedByDrain := - reducedReplayLiqReturnIexDataCandidate.io.blockedByDrain - io.reducedLoadReplayLiqLretIexDataBlockedByRobMissing := - reducedReplayLiqReturnIexDataCandidate.io.blockedByRobMissing - io.reducedLoadReplayLiqLretIexDataBlockedByNeedFlush := - reducedReplayLiqReturnIexDataCandidate.io.blockedByNeedFlush - io.reducedLoadReplayLiqLretRobResolveCandidateValid := - reducedReplayLiqReturnRobResolveDataCandidate.io.candidateValid - io.reducedLoadReplayLiqLretRobResolveValid := - reducedReplayLiqReturnRobResolveDataCandidate.io.resolveValid - io.reducedLoadReplayLiqLretRobResolveReadyForPipeInsert := - reducedReplayLiqReturnRobResolveDataCandidate.io.readyForPipeInsert - io.reducedLoadReplayLiqLretRobResolveMarkAllDestinationsDataValid := - reducedReplayLiqReturnRobResolveDataCandidate.io.markAllDestinationsDataValid - io.reducedLoadReplayLiqLretRobResolveMarkDestinationDataValid := - reducedReplayLiqReturnRobResolveDataCandidate.io.markDestinationDataValid - io.reducedLoadReplayLiqLretRobResolveRetLaneIncrement := - reducedReplayLiqReturnRobResolveDataCandidate.io.retLaneIncrement - io.reducedLoadReplayLiqLretRobResolveData := - reducedReplayLiqReturnRobResolveDataCandidate.io.resolveData - io.reducedLoadReplayLiqLretRobResolveDstPhysTag := - reducedReplayLiqReturnRobResolveDataCandidate.io.resolveDst.physTag - io.reducedLoadReplayLiqLretRobResolveBlockedByDisabled := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretRobResolveBlockedByFlush := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretRobResolveBlockedByNoSetMemData := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByNoSetMemData - io.reducedLoadReplayLiqLretRobResolveBlockedByUnsupportedMultiLane := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByUnsupportedMultiLane - io.reducedLoadReplayLiqLretRobResolveBlockedByInvalidRid := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByInvalidRid - io.reducedLoadReplayLiqLretRobResolveBlockedByNoDestination := - reducedReplayLiqReturnRobResolveDataCandidate.io.blockedByNoDestination - io.reducedLoadReplayLiqLretLaneCompletionCandidateValid := - reducedReplayLiqReturnLaneCompletionCandidate.io.candidateValid - io.reducedLoadReplayLiqLretLaneCompletionCompleteValid := - reducedReplayLiqReturnLaneCompletionCandidate.io.completeValid - io.reducedLoadReplayLiqLretLaneCompletionReadyForPipeInsert := - reducedReplayLiqReturnLaneCompletionCandidate.io.readyForPipeInsert - io.reducedLoadReplayLiqLretLaneCompletionRetLaneAfterResolve := - reducedReplayLiqReturnLaneCompletionCandidate.io.retLaneAfterResolve - io.reducedLoadReplayLiqLretLaneCompletionRequiresAllLanes := - reducedReplayLiqReturnLaneCompletionCandidate.io.requiresAllLanes - io.reducedLoadReplayLiqLretLaneCompletionBlockedByDisabled := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretLaneCompletionBlockedByFlush := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretLaneCompletionBlockedByNoResolve := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByNoResolve - io.reducedLoadReplayLiqLretLaneCompletionBlockedByZeroReturnedLanes := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByZeroReturnedLanes - io.reducedLoadReplayLiqLretLaneCompletionBlockedByInvalidRealReqCnt := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByInvalidRealReqCnt - io.reducedLoadReplayLiqLretLaneCompletionBlockedByScalarLoadPairIncomplete := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByScalarLoadPairIncomplete - io.reducedLoadReplayLiqLretLaneCompletionBlockedByVectorMemIncomplete := - reducedReplayLiqReturnLaneCompletionCandidate.io.blockedByVectorMemIncomplete - io.reducedLoadReplayLiqLretTloadCompletionCandidateValid := - reducedReplayLiqReturnTloadCompletionCandidate.io.candidateValid - io.reducedLoadReplayLiqLretTloadCompletionTloadCandidateValid := - reducedReplayLiqReturnTloadCompletionCandidate.io.tloadCandidateValid - io.reducedLoadReplayLiqLretTloadCompletionSubInstCntAfter := - reducedReplayLiqReturnTloadCompletionCandidate.io.subInstCntAfter - io.reducedLoadReplayLiqLretTloadCompletionTileScbSendValid := - reducedReplayLiqReturnTloadCompletionCandidate.io.tileScbSendValid - io.reducedLoadReplayLiqLretTloadCompletionTileScbIsLast := - reducedReplayLiqReturnTloadCompletionCandidate.io.tileScbIsLast - io.reducedLoadReplayLiqLretTloadCompletionCompleteValid := - reducedReplayLiqReturnTloadCompletionCandidate.io.completeValid - io.reducedLoadReplayLiqLretTloadCompletionReadyForPipeInsert := - reducedReplayLiqReturnTloadCompletionCandidate.io.readyForPipeInsert - io.reducedLoadReplayLiqLretTloadCompletionBlockedByDisabled := - reducedReplayLiqReturnTloadCompletionCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretTloadCompletionBlockedByFlush := - reducedReplayLiqReturnTloadCompletionCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretTloadCompletionBlockedByNoLaneCompletion := - reducedReplayLiqReturnTloadCompletionCandidate.io.blockedByNoLaneCompletion - io.reducedLoadReplayLiqLretTloadCompletionBlockedByInvalidSubInstCnt := - reducedReplayLiqReturnTloadCompletionCandidate.io.blockedByInvalidSubInstCnt - io.reducedLoadReplayLiqLretTloadCompletionBlockedByTloadPending := - reducedReplayLiqReturnTloadCompletionCandidate.io.blockedByTloadPending - io.reducedLoadReplayLiqLretFinalMetadataCandidateValid := - reducedReplayLiqReturnFinalMetadataCandidate.io.candidateValid - io.reducedLoadReplayLiqLretFinalMetadataIsLoadReturnMarked := - reducedReplayLiqReturnFinalMetadataCandidate.io.isLoadReturnMarked - io.reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveCalled := - reducedReplayLiqReturnFinalMetadataCandidate.io.loadBranchResolveCalled - io.reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveSideEffectValid := - reducedReplayLiqReturnFinalMetadataCandidate.io.loadBranchResolveSideEffectValid - io.reducedLoadReplayLiqLretFinalMetadataPipeCycleSidebandValid := - reducedReplayLiqReturnFinalMetadataCandidate.io.pipeCycleSidebandValid - io.reducedLoadReplayLiqLretFinalMetadataReadyForPipeInsert := - reducedReplayLiqReturnFinalMetadataCandidate.io.readyForPipeInsert - io.reducedLoadReplayLiqLretFinalMetadataBlockedByDisabled := - reducedReplayLiqReturnFinalMetadataCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretFinalMetadataBlockedByFlush := - reducedReplayLiqReturnFinalMetadataCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretFinalMetadataBlockedByNoTloadCompletion := - reducedReplayLiqReturnFinalMetadataCandidate.io.blockedByNoTloadCompletion - io.reducedLoadReplayLiqLretTimingStatsCandidateValid := - reducedReplayLiqReturnTimingStatsCandidate.io.candidateValid - io.reducedLoadReplayLiqLretTimingStatsSidebandValid := - reducedReplayLiqReturnTimingStatsCandidate.io.timingSidebandValid - io.reducedLoadReplayLiqLretTimingStatsIqNameSidebandValid := - reducedReplayLiqReturnTimingStatsCandidate.io.iqNameSidebandValid - io.reducedLoadReplayLiqLretTimingStatsLdRntCycleValid := - reducedReplayLiqReturnTimingStatsCandidate.io.ldRntCycleValid - io.reducedLoadReplayLiqLretTimingStatsUpdateValid := - reducedReplayLiqReturnTimingStatsCandidate.io.statsUpdateValid - io.reducedLoadReplayLiqLretTimingStatsLdRntCycle := - reducedReplayLiqReturnTimingStatsCandidate.io.ldRntCycle - io.reducedLoadReplayLiqLretTimingStatsLatencyIncrement := - reducedReplayLiqReturnTimingStatsCandidate.io.statsLatencyIncrement - io.reducedLoadReplayLiqLretTimingStatsLatencyUnderflow := - reducedReplayLiqReturnTimingStatsCandidate.io.latencyUnderflow - io.reducedLoadReplayLiqLretTimingStatsReadyForPipeInsert := - reducedReplayLiqReturnTimingStatsCandidate.io.readyForPipeInsert - io.reducedLoadReplayLiqLretTimingStatsBlockedByDisabled := - reducedReplayLiqReturnTimingStatsCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretTimingStatsBlockedByFlush := - reducedReplayLiqReturnTimingStatsCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretTimingStatsBlockedByNoFinalMetadata := - reducedReplayLiqReturnTimingStatsCandidate.io.blockedByNoFinalMetadata - io.reducedLoadReplayLiqLretIexPipeInsertCandidateValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.candidateValid - io.reducedLoadReplayLiqLretIexPipeInsertValid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertValid - io.reducedLoadReplayLiqLretIexPipeInsertIsLoadReturn := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertIsLoadReturn - io.reducedLoadReplayLiqLretIexPipeInsertPipeIndex := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertPipeIndex - io.reducedLoadReplayLiqLretIexPipeInsertLoadToUsePipeIndex := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertLoadToUsePipeIndex - io.reducedLoadReplayLiqLretIexPipeInsertWakeupRequired := - reducedReplayLiqReturnIexPipeInsertCandidate.io.insertWakeupRequired - io.reducedLoadReplayLiqLretIexPipeInsertBlockedByDisabled := - reducedReplayLiqReturnIexPipeInsertCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretIexPipeInsertBlockedByFlush := - reducedReplayLiqReturnIexPipeInsertCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretIexPipeInsertBlockedByNoSetMemData := - reducedReplayLiqReturnIexPipeInsertCandidate.io.blockedByNoSetMemData - io.reducedLoadReplayLiqLretIexPipeInsertBlockedByNoPipe := - reducedReplayLiqReturnIexPipeInsertCandidate.io.blockedByNoPipe - io.reducedLoadReplayLiqLretIexPipeInsertBlockedByInvalidRid := - reducedReplayLiqReturnIexPipeInsertCandidate.io.blockedByInvalidRid - io.reducedLoadReplayLiqLretPipeResidencyCandidateValid := - reducedReplayLiqReturnPipeResidencyCandidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeResidencyArmed := - reducedReplayLiqReturnPipeResidencyCandidate.io.residencyArmed - io.reducedLoadReplayLiqLretPipeResidencyWriteValid := - reducedReplayLiqReturnPipeResidencyCandidate.io.residencyWriteValid - io.reducedLoadReplayLiqLretPipeResidencyLiveEnable := - reducedReplayLiqReturnPipeResidencyCandidate.io.liveEnabled - io.reducedLoadReplayLiqLretPipeResidencyTargetIsAgu := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeResidencyTargetIsLda := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetIsLda - io.reducedLoadReplayLiqLretPipeResidencyPipeIndex := - reducedReplayLiqReturnPipeResidencyCandidate.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeResidencyBlockedByDisabled := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeResidencyBlockedByFlush := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeResidencyBlockedByNoInsertCandidate := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByNoInsertCandidate - io.reducedLoadReplayLiqLretPipeResidencyBlockedByNoInsertValid := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByNoInsertValid - io.reducedLoadReplayLiqLretPipeResidencyBlockedByLiveDisabled := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeResidencyBlockedByPipeOccupied := - reducedReplayLiqReturnPipeResidencyCandidate.io.blockedByPipeOccupied - io.reducedLoadReplayLiqLretPipeResidencySlotAccepted := - reducedReplayLiqReturnPipeResidencySlot.io.accepted - io.reducedLoadReplayLiqLretPipeResidencySlotOccupied := - reducedReplayLiqReturnPipeResidencySlot.io.occupied - io.reducedLoadReplayLiqLretPipeResidencySlotEntryValid := - reducedReplayLiqReturnPipeResidencySlot.io.entryValid - io.reducedLoadReplayLiqLretPipeResidencySlotTargetIsAgu := - reducedReplayLiqReturnPipeResidencySlot.io.entryTargetIsAgu - io.reducedLoadReplayLiqLretPipeResidencySlotTargetIsLda := - reducedReplayLiqReturnPipeResidencySlot.io.entryTargetIsLda - io.reducedLoadReplayLiqLretPipeResidencySlotPipeIndex := - reducedReplayLiqReturnPipeResidencySlot.io.entryPipeIndex - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByDisabled := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByFlush := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByClear := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByClear - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByNoWrite := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByNoWrite - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByInvalidTarget := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeResidencySlotBlockedByOccupied := - reducedReplayLiqReturnPipeResidencySlot.io.blockedByOccupied - io.reducedLoadReplayLiqLretPipeResidencyAdvanceCandidateValid := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeResidencyAdvanceValid := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.advanceValid - io.reducedLoadReplayLiqLretPipeResidencyAdvanceClearSlot := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.clearSlot - io.reducedLoadReplayLiqLretPipeResidencyAdvanceTargetIsAgu := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeResidencyAdvanceTargetIsLda := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetIsLda - io.reducedLoadReplayLiqLretPipeResidencyAdvancePipeIndex := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByDisabled := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByFlush := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByNoSlot := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.blockedByNoSlot - io.reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByAdvanceDisabled := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.blockedByAdvanceDisabled - io.reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByInvalidTarget := - reducedReplayLiqReturnPipeResidencyAdvanceCandidate.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW1SlotAccepted := - reducedReplayLiqReturnPipeW1Slot.io.accepted - io.reducedLoadReplayLiqLretPipeW1SlotOccupied := - reducedReplayLiqReturnPipeW1Slot.io.occupied - io.reducedLoadReplayLiqLretPipeW1SlotEntryValid := - reducedReplayLiqReturnPipeW1Slot.io.entryValid - io.reducedLoadReplayLiqLretPipeW1SlotTargetIsAgu := - reducedReplayLiqReturnPipeW1Slot.io.entryTargetIsAgu - io.reducedLoadReplayLiqLretPipeW1SlotTargetIsLda := - reducedReplayLiqReturnPipeW1Slot.io.entryTargetIsLda - io.reducedLoadReplayLiqLretPipeW1SlotPipeIndex := - reducedReplayLiqReturnPipeW1Slot.io.entryPipeIndex - io.reducedLoadReplayLiqLretPipeW1SlotPc := - reducedReplayLiqReturnPipeW1Slot.io.entryPc - io.reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValid := - reducedReplayLiqReturnPipeW1Slot.io.entryLoadLsId.valid - io.reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValue := - reducedReplayLiqReturnPipeW1Slot.io.entryLoadLsId.value - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByDisabled := - reducedReplayLiqReturnPipeW1Slot.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByFlush := - reducedReplayLiqReturnPipeW1Slot.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByClear := - reducedReplayLiqReturnPipeW1Slot.io.blockedByClear - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByNoWrite := - reducedReplayLiqReturnPipeW1Slot.io.blockedByNoWrite - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW1Slot.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW1SlotBlockedByOccupied := - reducedReplayLiqReturnPipeW1Slot.io.blockedByOccupied - io.reducedLoadReplayLiqLretPipeW1AdvanceCandidateValid := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeW1AdvanceValid := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.advanceValid - io.reducedLoadReplayLiqLretPipeW1AdvanceClearSlot := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.clearSlot - io.reducedLoadReplayLiqLretPipeW1AdvanceTargetIsAgu := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW1AdvanceTargetIsLda := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW1AdvancePipeIndex := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeW1AdvanceBlockedByDisabled := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW1AdvanceBlockedByFlush := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW1AdvanceBlockedByNoSlot := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.blockedByNoSlot - io.reducedLoadReplayLiqLretPipeW1AdvanceBlockedByAdvanceDisabled := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.blockedByAdvanceDisabled - io.reducedLoadReplayLiqLretPipeW1AdvanceBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW1AdvanceCandidate.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW2SlotAccepted := - reducedReplayLiqReturnPipeW2Modules.slot.io.accepted - io.reducedLoadReplayLiqLretPipeW2SlotOccupied := - reducedReplayLiqReturnPipeW2Modules.slot.io.occupied - io.reducedLoadReplayLiqLretPipeW2SlotEntryValid := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryValid - io.reducedLoadReplayLiqLretPipeW2SlotTargetIsAgu := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryTargetIsAgu - io.reducedLoadReplayLiqLretPipeW2SlotTargetIsLda := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryTargetIsLda - io.reducedLoadReplayLiqLretPipeW2SlotPipeIndex := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryPipeIndex - io.reducedLoadReplayLiqLretPipeW2SlotPc := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryPc - io.reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValid := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryLoadLsId.valid - io.reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValue := - reducedReplayLiqReturnPipeW2Modules.slot.io.entryLoadLsId.value - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByFlush := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByClear := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByClear - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByNoWrite := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByNoWrite - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW2SlotBlockedByOccupied := - reducedReplayLiqReturnPipeW2Modules.slot.io.blockedByOccupied - io.reducedLoadReplayLiqLretPipeW2CompletionCandidateValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2CompletionTargetValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.targetValid - io.reducedLoadReplayLiqLretPipeW2CompletionCompleteValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.completeValid - io.reducedLoadReplayLiqLretPipeW2CompletionClearSlot := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.clearSlot - io.reducedLoadReplayLiqLretPipeW2CompletionTargetIsAgu := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2CompletionTargetIsLda := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2CompletionPipeIndex := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeW2CompletionResolveRequired := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.resolveRequired - io.reducedLoadReplayLiqLretPipeW2CompletionResolveValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.resolveValid - io.reducedLoadReplayLiqLretPipeW2CompletionWritebackRequired := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.writebackRequired - io.reducedLoadReplayLiqLretPipeW2CompletionWritebackValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.writebackValid - io.reducedLoadReplayLiqLretPipeW2CompletionWritebackTag := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.writebackTag - io.reducedLoadReplayLiqLretPipeW2CompletionWritebackData := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.writebackData - io.reducedLoadReplayLiqLretPipeW2CompletionWakeupRequired := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.wakeupRequired - io.reducedLoadReplayLiqLretPipeW2CompletionWakeupValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.wakeupValid - io.reducedLoadReplayLiqLretPipeW2CompletionWakeupTag := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.wakeupTag - io.reducedLoadReplayLiqLretPipeW2CompletionReducedGprWakeupValid := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.reducedGprWakeupValid - io.reducedLoadReplayLiqLretPipeW2CompletionBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2CompletionBlockedByFlush := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW2CompletionBlockedByNoSlot := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.blockedByNoSlot - io.reducedLoadReplayLiqLretPipeW2CompletionBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW2CompletionBlockedBySideEffects := - reducedReplayLiqReturnPipeW2Modules.completionCandidate.io.blockedBySideEffects - io.reducedLoadReplayLiqLretPipeW2SideEffectCandidateValid := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.readyCandidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectResolveReady := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.resolveReady - io.reducedLoadReplayLiqLretPipeW2SideEffectWritebackReady := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.writebackReady - io.reducedLoadReplayLiqLretPipeW2SideEffectWakeupReady := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.wakeupReady - io.reducedLoadReplayLiqLretPipeW2SideEffectReady := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.sideEffectsReady - io.reducedLoadReplayLiqLretPipeW2SideEffectBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2SideEffectBlockedByNoCandidate := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.blockedByNoCandidate - io.reducedLoadReplayLiqLretPipeW2SideEffectBlockedByResolve := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.blockedByResolve - io.reducedLoadReplayLiqLretPipeW2SideEffectBlockedByWriteback := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.blockedByWriteback - io.reducedLoadReplayLiqLretPipeW2SideEffectBlockedByWakeup := - reducedReplayLiqReturnPipeW2Modules.sideEffectReady.io.blockedByWakeup - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlCandidateValid := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlRequiredMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.requiredMask - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlLiveEnableMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.liveEnableMask - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlAllRequiredLiveEnabled := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.allRequiredLiveEnabled - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlocked := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByDisabled || - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByFlush || - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByNoCandidate || - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByNoRequiredSink || - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByNoCandidate := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByNoCandidate - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByNoRequiredSink := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByNoRequiredSink - io.reducedLoadReplayLiqLretPipeW2SideEffectLiveControlBlockedByLiveDisabled := - reducedReplayLiqReturnPipeW2Modules.sideEffectLiveControl.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2ResolveSinkCandidateValid := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ResolveSinkArmed := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.resolveArmed - io.reducedLoadReplayLiqLretPipeW2ResolveSinkReady := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.resolveSinkReady - io.reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByFlush := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByNoResolve := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.blockedByNoResolve - io.reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedBySink := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.blockedBySink - io.reducedLoadReplayLiqLretPipeW2ResolveSinkBlockedByLiveDisabled := - reducedReplayLiqReturnPipeW2Modules.resolveSinkReady.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2WritebackSinkCandidateValid := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WritebackSinkArmed := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.writebackArmed - io.reducedLoadReplayLiqLretPipeW2WritebackSinkReady := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.writebackSinkReady - io.reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByFlush := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByNoWriteback := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.blockedByNoWriteback - io.reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedBySink := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.blockedBySink - io.reducedLoadReplayLiqLretPipeW2WritebackSinkBlockedByLiveDisabled := - reducedReplayLiqReturnPipeW2Modules.writebackSinkReady.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2WakeupSinkCandidateValid := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WakeupSinkArmed := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.wakeupArmed - io.reducedLoadReplayLiqLretPipeW2WakeupSinkReady := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.wakeupSinkReady - io.reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByDisabled := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.blockedByDisabled - io.reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByFlush := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.blockedByFlush - io.reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByNoWakeup := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.blockedByNoWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedBySink := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.blockedBySink - io.reducedLoadReplayLiqLretPipeW2WakeupSinkBlockedByLiveDisabled := - reducedReplayLiqReturnPipeW2Modules.wakeupSinkReady.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestValid := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.requestValid - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestResolve := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.resolveRequest - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestWriteback := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.writebackRequest - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestWakeup := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.wakeupRequest - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.requestMask - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestBlockedByNoComplete := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.blockedByNoComplete - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidCompleteWithoutCandidate := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.invalidCompleteWithoutCandidate - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidCompleteWithoutResolve := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.invalidCompleteWithoutResolve - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidResolveWithoutComplete := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.invalidResolveWithoutComplete - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidWritebackWithoutComplete := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.invalidWritebackWithoutComplete - io.reducedLoadReplayLiqLretPipeW2SideEffectRequestInvalidWakeupWithoutComplete := - reducedReplayLiqReturnPipeW2Modules.sideEffectRequest.io.invalidWakeupWithoutComplete - io.reducedLoadReplayLiqLretPipeW2ResolveRequestCandidateValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestTargetValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.targetValid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveValid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestIsComplete := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.isComplete - io.reducedLoadReplayLiqLretPipeW2ResolveRequestTargetIsAgu := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2ResolveRequestTargetIsLda := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBidValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveBid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBidWrap := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveBid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBidValue := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveBid.value - io.reducedLoadReplayLiqLretPipeW2ResolveRequestGidValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveGid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestGidWrap := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveGid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveRequestGidValue := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveGid.value - io.reducedLoadReplayLiqLretPipeW2ResolveRequestRidValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveRid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestRidWrap := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveRid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveRequestRidValue := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveRid.value - io.reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdValid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveLoadLsId.valid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdWrap := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveLoadLsId.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveRequestLoadLsIdValue := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveLoadLsId.value - io.reducedLoadReplayLiqLretPipeW2ResolveRequestPc := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolvePc - io.reducedLoadReplayLiqLretPipeW2ResolveRequestAddr := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveAddr - io.reducedLoadReplayLiqLretPipeW2ResolveRequestSize := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveSize - io.reducedLoadReplayLiqLretPipeW2ResolveRequestDstPhysTag := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveDst.physTag - io.reducedLoadReplayLiqLretPipeW2ResolveRequestData := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.resolveData - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByNoRequest := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByNoRequest - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByNoSlot := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByNoSlot - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidBid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByInvalidBid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidGid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByInvalidGid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidRid := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByInvalidRid - io.reducedLoadReplayLiqLretPipeW2ResolveRequestBlockedByInvalidIdentity := - reducedReplayLiqReturnPipeW2Modules.resolveRequest.io.blockedByInvalidIdentity - io.reducedLoadReplayLiqLretPipeW2WritebackRequestCandidateValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestTargetValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.targetValid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestIdentityValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.identityValid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestDestinationValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.destinationValid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestGprDestination := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.gprDestination - io.reducedLoadReplayLiqLretPipeW2WritebackRequestValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackValid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestTargetIsAgu := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2WritebackRequestTargetIsLda := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBidValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackBid.valid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBidWrap := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackBid.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBidValue := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackBid.value - io.reducedLoadReplayLiqLretPipeW2WritebackRequestGidValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackGid.valid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestGidWrap := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackGid.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackRequestGidValue := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackGid.value - io.reducedLoadReplayLiqLretPipeW2WritebackRequestRidValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackRid.valid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestRidWrap := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackRid.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackRequestRidValue := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackRid.value - io.reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdValid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackLoadLsId.valid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdWrap := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackLoadLsId.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackRequestLoadLsIdValue := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackLoadLsId.value - io.reducedLoadReplayLiqLretPipeW2WritebackRequestPc := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackPc - io.reducedLoadReplayLiqLretPipeW2WritebackRequestDstArchTag := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackArchTag - io.reducedLoadReplayLiqLretPipeW2WritebackRequestDstRelTag := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackRelTag - io.reducedLoadReplayLiqLretPipeW2WritebackRequestDstPhysTag := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackPhysTag - io.reducedLoadReplayLiqLretPipeW2WritebackRequestDstOldPhysTag := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackOldPhysTag - io.reducedLoadReplayLiqLretPipeW2WritebackRequestData := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.writebackData - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoRequest := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByNoRequest - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoSlot := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByNoSlot - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidTarget := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByInvalidTarget - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidBid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByInvalidBid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidGid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByInvalidGid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidRid := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByInvalidRid - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByInvalidIdentity := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByInvalidIdentity - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNoDestination := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByNoDestination - io.reducedLoadReplayLiqLretPipeW2WritebackRequestBlockedByNonGprDestination := - reducedReplayLiqReturnPipeW2Modules.writebackRequest.io.blockedByNonGprDestination - io.reducedLoadReplayLiqLretPipeW2WakeupRequestCandidateValid := - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WakeupRequestValid := - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.wakeupValid - io.reducedLoadReplayLiqLretPipeW2WakeupRequestReducedGprWakeupValid := - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.reducedGprWakeupValid - io.reducedLoadReplayLiqLretPipeW2WakeupRequestNonGprWakeup := - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.nonGprWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupRequestBlocked := - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByNoRequest || - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByNoSlot || - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByInvalidTarget || - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByInvalidIdentity || - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByWakeupNotRequired || - reducedReplayLiqReturnPipeW2Modules.wakeupRequest.io.blockedByNoDestination - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanCandidateValid := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanRequiredMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.requiredMask - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanRequestMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.requestMask - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanPayloadValidMask := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.payloadValidMask - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanIssueValid := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.issueValid - io.reducedLoadReplayLiqLretPipeW2SideEffectPayloadPlanBlocked := - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByDisabled || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByFlush || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByNoCandidate || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByNoRequest || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByRequestMismatch || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByMissingResolvePayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByMissingWritebackPayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByMissingWakeupPayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByUnexpectedResolvePayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByUnexpectedWritebackPayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.blockedByUnexpectedWakeupPayload || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.invalidRequestWithoutCandidate || - reducedReplayLiqReturnPipeW2Modules.sideEffectPayloadPlan.io.invalidPayloadWithoutRequest - io.reducedLoadReplayLiqWritebackCandidateValid := - reducedReplayLiqReturnWritebackCandidate.io.candidateValid - io.reducedLoadReplayLiqWritebackValid := - reducedReplayLiqReturnWritebackCandidate.io.writeValid - io.reducedLoadReplayLiqWritebackTag := - reducedReplayLiqReturnWritebackCandidate.io.writeTag - io.reducedLoadReplayLiqWritebackData := - reducedReplayLiqReturnWritebackCandidate.io.writeData - io.reducedLoadReplayLiqWritebackIgnoredNoDestination := - reducedReplayLiqReturnWritebackCandidate.io.ignoredNoDestination - io.reducedLoadReplayLiqWritebackIgnoredNonGprDestination := - reducedReplayLiqReturnWritebackCandidate.io.ignoredNonGprDestination - io.reducedLoadReplayLiqWritebackBlockedByDisabled := - reducedReplayLiqReturnWritebackCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqWritebackArbiterReplayEnabled := - rfWritebackArbiter.io.replayEnable - io.reducedLoadReplayLiqWritebackArbiterSelectedExecute := - rfWritebackArbiter.io.selectedExecute - io.reducedLoadReplayLiqWritebackArbiterSelectedReplay := - rfWritebackArbiter.io.selectedReplay - io.reducedLoadReplayLiqWritebackArbiterReplayBlockedByDisabled := - rfWritebackArbiter.io.replayBlockedByDisabled - io.reducedLoadReplayLiqWritebackArbiterReplayBlockedByExecute := - rfWritebackArbiter.io.replayBlockedByExecute - io.reducedLoadReplayLiqSideEffectCandidateValid := - reducedReplayLiqReturnSideEffectReady.io.candidateValid - io.reducedLoadReplayLiqSideEffectLretReady := - reducedReplayLiqReturnSideEffectReady.io.lretReady - io.reducedLoadReplayLiqSideEffectWritebackReady := - reducedReplayLiqReturnSideEffectReady.io.writebackReady - io.reducedLoadReplayLiqSideEffectWakeupReady := - reducedReplayLiqReturnSideEffectReady.io.wakeupReady - io.reducedLoadReplayLiqSideEffectReady := - reducedReplayLiqReturnSideEffectReady.io.sideEffectsReady - io.reducedLoadReplayLiqSideEffectBlockedByDisabled := - reducedReplayLiqReturnSideEffectReady.io.blockedByDisabled - io.reducedLoadReplayLiqSideEffectBlockedByNoPayload := - reducedReplayLiqReturnSideEffectReady.io.blockedByNoPayload - io.reducedLoadReplayLiqSideEffectBlockedByLret := - reducedReplayLiqReturnSideEffectReady.io.blockedByLret - io.reducedLoadReplayLiqSideEffectBlockedByWriteback := - reducedReplayLiqReturnSideEffectReady.io.blockedByWriteback - io.reducedLoadReplayLiqSideEffectBlockedByWakeup := - reducedReplayLiqReturnSideEffectReady.io.blockedByWakeup - io.reducedLoadReplayLiqPublishControlCandidateValid := - reducedReplayLiqReturnPublishControl.io.candidateValid - io.reducedLoadReplayLiqPublishControlLiveEnable := - reducedReplayLiqReturnPublishControl.io.liveEnable - io.reducedLoadReplayLiqPublishControlArmed := - reducedReplayLiqReturnPublishControl.io.publishArmed - io.reducedLoadReplayLiqPublishControlFire := - reducedReplayLiqReturnPublishControl.io.publishFire - io.reducedLoadReplayLiqPublishControlBlockedByDisabled := - reducedReplayLiqReturnPublishControl.io.blockedByDisabled - io.reducedLoadReplayLiqPublishControlBlockedByNoPayload := - reducedReplayLiqReturnPublishControl.io.blockedByNoPayload - io.reducedLoadReplayLiqPublishControlBlockedByPublish := - reducedReplayLiqReturnPublishControl.io.blockedByPublish - io.reducedLoadReplayLiqPublishControlBlockedBySideEffects := - reducedReplayLiqReturnPublishControl.io.blockedBySideEffects - io.reducedLoadReplayLiqPublishControlBlockedByLiveDisabled := - reducedReplayLiqReturnPublishControl.io.blockedByLiveDisabled - io.reducedLoadReplayLiqPublishRequestValid := - reducedReplayLiqReturnPublishRequest.io.requestValid - io.reducedLoadReplayLiqPublishRequestLret := - reducedReplayLiqReturnPublishRequest.io.lretRequest - io.reducedLoadReplayLiqPublishRequestWriteback := - reducedReplayLiqReturnPublishRequest.io.writebackRequest - io.reducedLoadReplayLiqPublishRequestWakeup := - reducedReplayLiqReturnPublishRequest.io.wakeupRequest - io.reducedLoadReplayLiqPublishRequestMask := - reducedReplayLiqReturnPublishRequest.io.requestMask - io.reducedLoadReplayLiqPublishRequestBlockedByNoFire := - reducedReplayLiqReturnPublishRequest.io.blockedByNoFire - io.reducedLoadReplayLiqPublishRequestInvalidFireWithoutPayload := - reducedReplayLiqReturnPublishRequest.io.invalidFireWithoutPayload - io.reducedLoadReplayLiqWakeupCandidateValid := - reducedReplayLiqReturnWakeupCandidate.io.candidateValid - io.reducedLoadReplayLiqWakeupRequired := - reducedReplayLiqReturnWakeupCandidate.io.wakeupRequired - io.reducedLoadReplayLiqWakeupValid := - reducedReplayLiqReturnWakeupCandidate.io.wakeupValid - io.reducedLoadReplayLiqWakeupKind := - reducedReplayLiqReturnWakeupCandidate.io.wakeupKind.asUInt - io.reducedLoadReplayLiqWakeupTag := - reducedReplayLiqReturnWakeupCandidate.io.wakeupTag - io.reducedLoadReplayLiqWakeupReducedGprValid := - reducedReplayLiqReturnWakeupCandidate.io.reducedGprWakeupValid - io.reducedLoadReplayLiqWakeupNonGpr := - reducedReplayLiqReturnWakeupCandidate.io.nonGprWakeup - io.reducedLoadReplayLiqWakeupSuppressedNotRequired := - reducedReplayLiqReturnWakeupCandidate.io.suppressedWakeupNotRequired - io.reducedLoadReplayLiqWakeupIgnoredNoDestination := - reducedReplayLiqReturnWakeupCandidate.io.ignoredNoDestination - io.reducedLoadReplayLiqWakeupBlockedByDisabled := - reducedReplayLiqReturnWakeupCandidate.io.blockedByDisabled - io.reducedLoadReplayLiqRepickMask := reducedLoadReplayLiqAllocPath.io.repickMask - io.reducedLoadReplayLiqMissMask := reducedLoadReplayLiqAllocPath.io.missMask - io.reducedLoadReplayLiqResolvedMask := reducedLoadReplayLiqAllocPath.io.resolvedMask - io.reducedLoadReplayLiqE4UpdateValid := reducedLoadReplayLiqAllocPath.io.e4UpdateValid - io.reducedLoadReplayLiqE4UpdateIndex := reducedLoadReplayLiqAllocPath.io.e4UpdateIndex - io.reducedLoadReplayLiqE4MissKind := reducedLoadReplayLiqAllocPath.io.e4MissKind.asUInt - io.reducedLoadReplayLiqE4WakeupValid := reducedLoadReplayLiqAllocPath.io.e4WakeupValid - io.reducedLoadReplayLiqLhqRecordValid := reducedLoadReplayLiqAllocPath.io.lhqRecordValid - LinxCoreFrontendFetchRfAluTraceTopR428RowMutationVisibilityWiring.connect( - io = io, - liqPath = reducedLoadReplayLiqAllocPath - ) - io.reducedLoadReplayLiqResidentCount := reducedLoadReplayLiqAllocPath.io.residentCount - io.reducedLoadReplayLiqEmpty := reducedLoadReplayLiqAllocPath.io.empty - io.reducedLoadReplayLiqFull := reducedLoadReplayLiqAllocPath.io.full - io.reducedLoadReplayLiqHeadValid := reducedReplayLiqHeadValid - io.reducedLoadReplayLiqHeadIndex := reducedReplayLiqHeadIndex - io.reducedLoadReplayLiqHeadStatus := reducedReplayLiqHeadRow.status.asUInt - io.reducedLoadReplayLiqHeadLoadIdValid := reducedReplayLiqHeadRow.loadId.valid - io.reducedLoadReplayLiqHeadLoadIdWrap := reducedReplayLiqHeadRow.loadId.wrap - io.reducedLoadReplayLiqHeadLoadIdValue := reducedReplayLiqHeadRow.loadId.value - io.reducedLoadReplayLiqHeadBidValid := reducedReplayLiqHeadRow.bid.valid - io.reducedLoadReplayLiqHeadBidWrap := reducedReplayLiqHeadRow.bid.wrap - io.reducedLoadReplayLiqHeadBidValue := reducedReplayLiqHeadRow.bid.value - io.reducedLoadReplayLiqHeadGidValid := reducedReplayLiqHeadRow.gid.valid - io.reducedLoadReplayLiqHeadGidWrap := reducedReplayLiqHeadRow.gid.wrap - io.reducedLoadReplayLiqHeadGidValue := reducedReplayLiqHeadRow.gid.value - io.reducedLoadReplayLiqHeadRidValid := reducedReplayLiqHeadRow.rid.valid - io.reducedLoadReplayLiqHeadRidWrap := reducedReplayLiqHeadRow.rid.wrap - io.reducedLoadReplayLiqHeadRidValue := reducedReplayLiqHeadRow.rid.value - io.reducedLoadReplayLiqHeadLoadLsIdValid := reducedReplayLiqHeadRow.loadLsId.valid - io.reducedLoadReplayLiqHeadLoadLsIdWrap := reducedReplayLiqHeadRow.loadLsId.wrap - io.reducedLoadReplayLiqHeadLoadLsIdValue := reducedReplayLiqHeadRow.loadLsId.value - io.reducedLoadReplayLiqHeadPc := reducedReplayLiqHeadRow.pc - io.reducedLoadReplayLiqHeadAddr := reducedReplayLiqHeadRow.addr - io.reducedLoadReplayLiqHeadSize := reducedReplayLiqHeadRow.size - io.reducedLoadReplayLiqHeadWaitStore := reducedReplayLiqHeadRow.waitStore - io.reducedLoadReplayLiqHeadStoreBypass := reducedReplayLiqHeadRow.storeBypass - io.reducedLoadReplayLiqHeadDataComplete := reducedReplayLiqHeadRow.dataComplete - io.reducedLoadReplayLiqHeadSourcesReturned := reducedReplayLiqHeadRow.sourcesReturned - io.reducedLoadReplayLiqHeadScbReturned := reducedReplayLiqHeadRow.scbReturned - io.reducedLoadReplayLiqHeadStqReturned := reducedReplayLiqHeadRow.stqReturned - io.reducedLoadReplayResolveQueuePushReady := reducedLoadReplayResolveQueue.io.pushReady - io.reducedLoadReplayResolveQueuePushAccepted := reducedLoadReplayResolveQueue.io.pushAccepted - io.reducedLoadReplayResolveQueueClearPending := reducedLoadReplayResolveClearPending - io.reducedLoadReplayResolveQueueClearAccepted := reducedLoadReplayLiqAllocPath.io.clearResolvedAccepted - io.reducedLoadReplayResolveQueueClearIndex := reducedLoadReplayResolveClearIndex - io.reducedLoadReplayResolveQueueRetireValid := reducedLoadReplayResolveQueue.io.retireValid - io.reducedLoadReplayResolveQueueRetireIsLoadStore := reducedLoadReplayResolveRetireSource.isLoadStore - io.reducedLoadReplayResolveQueueRetireIsLoad := reducedLoadReplayResolveRetireSource.isLoad - io.reducedLoadReplayResolveQueueRetireIsStore := reducedLoadReplayResolveRetireSource.isStore - io.reducedLoadReplayResolveQueueRetireBidValid := reducedLoadReplayResolveRetireSource.bid.valid - io.reducedLoadReplayResolveQueueRetireBidWrap := reducedLoadReplayResolveRetireSource.bid.wrap - io.reducedLoadReplayResolveQueueRetireBidValue := reducedLoadReplayResolveRetireSource.bid.value - io.reducedLoadReplayResolveQueueRetireRidValid := reducedLoadReplayResolveRetireSource.rid.valid - io.reducedLoadReplayResolveQueueRetireRidWrap := reducedLoadReplayResolveRetireSource.rid.wrap - io.reducedLoadReplayResolveQueueRetireRidValue := reducedLoadReplayResolveRetireSource.rid.value - io.reducedLoadReplayResolveQueueRetireLsIdValid := reducedLoadReplayResolveRetireLsId.valid - io.reducedLoadReplayResolveQueueRetireLsIdWrap := reducedLoadReplayResolveRetireLsId.wrap - io.reducedLoadReplayResolveQueueRetireLsIdValue := reducedLoadReplayResolveRetireLsId.value - io.reducedLoadReplayResolveQueuePreciseFlushValid := reducedLoadReplayResolvePreciseFlush.req.valid - io.reducedLoadReplayResolveQueuePreciseFlushBidValid := reducedLoadReplayResolvePreciseFlush.req.bid.valid - io.reducedLoadReplayResolveQueuePreciseFlushBidWrap := reducedLoadReplayResolvePreciseFlush.req.bid.wrap - io.reducedLoadReplayResolveQueuePreciseFlushBidValue := reducedLoadReplayResolvePreciseFlush.req.bid.value - io.reducedLoadReplayResolveQueuePreciseFlushRidValid := reducedLoadReplayResolvePreciseFlush.req.rid.valid - io.reducedLoadReplayResolveQueuePreciseFlushRidWrap := reducedLoadReplayResolvePreciseFlush.req.rid.wrap - io.reducedLoadReplayResolveQueuePreciseFlushRidValue := reducedLoadReplayResolvePreciseFlush.req.rid.value - io.reducedLoadReplayResolveQueuePreciseFlushLsIdValid := reducedLoadReplayResolvePreciseFlush.req.lsId.valid - io.reducedLoadReplayResolveQueuePreciseFlushLsIdWrap := reducedLoadReplayResolvePreciseFlush.req.lsId.wrap - io.reducedLoadReplayResolveQueuePreciseFlushLsIdValue := reducedLoadReplayResolvePreciseFlush.req.lsId.value - io.reducedLoadReplayResolveQueueFlushPruneMask := reducedLoadReplayResolveQueue.io.flushPruneMask - io.reducedLoadReplayResolveQueueFlushPruneCount := reducedLoadReplayResolveQueue.io.flushPruneCount - io.reducedLoadReplayResolveQueueRetireMask := reducedLoadReplayResolveQueue.io.retireMask - io.reducedLoadReplayResolveQueueRetireCount := reducedLoadReplayResolveQueue.io.retireCount - io.reducedLoadReplayResolveQueueValidMask := reducedLoadReplayResolveQueue.io.validMask - io.reducedLoadReplayResolveQueueCount := reducedLoadReplayResolveQueue.io.count - io.reducedLoadReplayResolveQueueEmpty := reducedLoadReplayResolveQueue.io.empty - io.reducedLoadReplayResolveQueueFull := reducedLoadReplayResolveQueue.io.full - val reducedLoadReplayResolveQueueHead = reducedLoadReplayResolveQueue.io.conflictRows(0) - io.reducedLoadReplayResolveQueueHeadValid := reducedLoadReplayResolveQueueHead.valid - io.reducedLoadReplayResolveQueueHeadPeId := reducedLoadReplayResolveQueueHead.peId - io.reducedLoadReplayResolveQueueHeadStid := reducedLoadReplayResolveQueueHead.stid - io.reducedLoadReplayResolveQueueHeadTid := reducedLoadReplayResolveQueueHead.tid - io.reducedLoadReplayResolveQueueHeadPc := reducedLoadReplayResolveQueueHead.pc - io.reducedLoadReplayResolveQueueHeadAddr := reducedLoadReplayResolveQueueHead.addr - io.reducedLoadReplayResolveQueueHeadSize := reducedLoadReplayResolveQueueHead.size - io.reducedLoadReplayResolveQueueHeadBidValid := reducedLoadReplayResolveQueueHead.bid.valid - io.reducedLoadReplayResolveQueueHeadBidWrap := reducedLoadReplayResolveQueueHead.bid.wrap - io.reducedLoadReplayResolveQueueHeadBidValue := reducedLoadReplayResolveQueueHead.bid.value - io.reducedLoadReplayResolveQueueHeadGidValid := reducedLoadReplayResolveQueueHead.gid.valid - io.reducedLoadReplayResolveQueueHeadGidWrap := reducedLoadReplayResolveQueueHead.gid.wrap - io.reducedLoadReplayResolveQueueHeadGidValue := reducedLoadReplayResolveQueueHead.gid.value - io.reducedLoadReplayResolveQueueHeadRidValid := reducedLoadReplayResolveQueueHead.rid.valid - io.reducedLoadReplayResolveQueueHeadRidWrap := reducedLoadReplayResolveQueueHead.rid.wrap - io.reducedLoadReplayResolveQueueHeadRidValue := reducedLoadReplayResolveQueueHead.rid.value - io.reducedLoadReplayResolveQueueHeadLsIdValid := reducedLoadReplayResolveQueueHead.lsId.valid - io.reducedLoadReplayResolveQueueHeadLsIdWrap := reducedLoadReplayResolveQueueHead.lsId.wrap - io.reducedLoadReplayResolveQueueHeadLsIdValue := reducedLoadReplayResolveQueueHead.lsId.value - io.reducedMdbConflictStoreValid := reducedMdbConflictStoreProbe.valid - io.reducedMdbConflictActiveCandidateMask := reducedMdbPath.io.conflictActiveMask - io.reducedMdbConflictResolveCandidateMask := reducedMdbPath.io.conflictResolveMask - io.reducedMdbConflictWaitStoreMask := reducedMdbPath.io.conflictWaitStoreMask - io.reducedMdbConflictWaitStoreCount := reducedMdbPath.io.conflictWaitStoreCount - io.reducedMdbConflictValid := reducedMdbPath.io.conflictValid - io.reducedMdbConflictFromResolveQueue := reducedMdbPath.io.conflictFromResolveQueue - io.reducedMdbConflictActiveIndex := reducedMdbPath.io.conflictActiveIndex - io.reducedMdbConflictResolveIndex := reducedMdbPath.io.conflictResolveIndex - io.reducedMdbConflictOrdinal := reducedMdbPath.io.conflictOrdinal - io.reducedMdbConflictInnerFlush := reducedMdbPath.io.conflictInnerFlush - io.reducedMdbConflictNukeFlush := reducedMdbPath.io.conflictNukeFlush - io.reducedMdbConflictLoadBidValid := reducedMdbPath.io.conflictRecord.load.bid.valid - io.reducedMdbConflictLoadBidWrap := reducedMdbPath.io.conflictRecord.load.bid.wrap - io.reducedMdbConflictLoadBidValue := reducedMdbPath.io.conflictRecord.load.bid.value - io.reducedMdbConflictLoadLsIdValid := reducedMdbPath.io.conflictRecord.load.lsId.valid - io.reducedMdbConflictLoadLsIdWrap := reducedMdbPath.io.conflictRecord.load.lsId.wrap - io.reducedMdbConflictLoadLsIdValue := reducedMdbPath.io.conflictRecord.load.lsId.value - io.reducedMdbConflictStoreBidValid := reducedMdbPath.io.conflictRecord.store.bid.valid - io.reducedMdbConflictStoreBidWrap := reducedMdbPath.io.conflictRecord.store.bid.wrap - io.reducedMdbConflictStoreBidValue := reducedMdbPath.io.conflictRecord.store.bid.value - io.reducedMdbConflictStoreLsIdValid := reducedMdbPath.io.conflictRecord.store.lsId.valid - io.reducedMdbConflictStoreLsIdWrap := reducedMdbPath.io.conflictRecord.store.lsId.wrap - io.reducedMdbConflictStoreLsIdValue := reducedMdbPath.io.conflictRecord.store.lsId.value - LinxCoreFrontendFetchRfAluTraceTopR659MdbVisibilityWiring.connect( - io, - reducedMdbPath, - reducedMdbFanoutLookupValid - ) - LinxCoreFrontendFetchRfAluTraceTopR465MdbLookupWaitPlanVisibilityWiring.connect(io, reducedMdbPath) - LinxCoreFrontendFetchRfAluTraceTopR466MdbLookupWaitPlanBridgeVisibilityWiring.connect( - io, - reducedMdbLookupWaitPlanBridge - ) - io.reducedLoadWaitReplaySlotPc := reducedLoadWaitReplaySlot.io.slotPc - io.reducedLoadWaitReplaySlotAddr := reducedLoadWaitReplaySlot.io.slotAddr - io.storeDispatchReady := path.io.storeDispatchReady - io.storeDispatchFire := path.io.storeDispatchFire - io.storeDispatchSplit := path.io.storeDispatchSplit - io.storeStaQueueValid := path.io.storeStaQueueValid - io.storeStdQueueValid := path.io.storeStdQueueValid - io.storeStaEnqueueFire := path.io.storeStaEnqueueFire - io.storeStdEnqueueFire := path.io.storeStdEnqueueFire - io.storeStaDequeueFire := path.io.storeStaDequeueFire - io.storeStdDequeueFire := path.io.storeStdDequeueFire - io.storeDispatchInputProtocolError := path.io.storeDispatchInputProtocolError - io.storeStaQueueCount := path.io.storeStaQueueCount - io.storeStdQueueCount := path.io.storeStdQueueCount - io.storeStaInsertReady := path.io.storeStaInsertReady - io.storeStdInsertReady := path.io.storeStdInsertReady - io.storeSelectedSta := path.io.storeSelectedSta - io.storeSelectedStd := path.io.storeSelectedStd - io.storeBlockedByStaExec := path.io.storeBlockedByStaExec - io.storeBlockedByStdExec := path.io.storeBlockedByStdExec - io.storeStqInsertValid := path.io.storeStqInsertValid - io.storeStqInsertAccepted := path.io.storeStqInsertAccepted - io.storeStqInsertAllocated := path.io.storeStqInsertAllocated - io.storeStqInsertMerged := path.io.storeStqInsertMerged - io.storeStqInsertConflict := path.io.storeStqInsertConflict - io.storeStqInsertIndex := path.io.storeStqInsertIndex - io.storeStqOccupiedMask := path.io.storeStqOccupiedMask - io.storeStqWaitMask := path.io.storeStqWaitMask - io.storeStqCommitMask := path.io.storeStqCommitMask - io.storeStqAddrReadyMask := path.io.storeStqAddrReadyMask - io.storeStqDataReadyMask := path.io.storeStqDataReadyMask - io.storeStqResidentCount := path.io.storeStqResidentCount - io.storeStqOutstandingWaitCount := path.io.storeStqOutstandingWaitCount - io.storeStqEmpty := path.io.storeStqEmpty - io.storeStqFull := path.io.storeStqFull - io.storeStqStall := path.io.storeStqStall - io.executeUnsupported := execute.io.unsupported - io.executeUnsupportedOpcode := execute.io.unsupportedOpcode - io.robAllocFire := path.io.robAllocFire - io.robRenameUpdateAttemptValid := path.io.robRenameUpdateAttemptValid - io.robRenameUpdateReady := path.io.robRenameUpdateReady - io.robRenameUpdateFire := path.io.robRenameUpdateFire - io.robRenameUpdateIgnored := path.io.robRenameUpdateIgnored - io.completeAccepted := path.io.completeAccepted - io.completeIgnored := path.io.completeIgnored - - io.rfReadReadyMask := VecInit(rf.io.readReady.take(3)).asUInt - io.rfAllReadReady := rf.io.readReady.take(3).reduce(_ && _) - io.rfReadyMask := rf.io.readyMask - io.rfWriteValid := rf.io.write(0).fire - io.rfWriteTag := rfWritebackArbiter.io.writeTag - io.rfWriteData := rfWritebackArbiter.io.writeData - LinxCoreFrontendFetchRfAluTraceTopServiceDiagnosticsWiring.connect(io, servicePath) - io.executeCompleteSrcPhysValidMask := execute.io.completeSrcPhysValid.asUInt - io.executeCompleteSrcPhysTag := execute.io.completeSrcPhysTag - io.executeCompletePc := execute.io.completeRow.pc - io.executeCompleteInsn := execute.io.completeRow.insn - io.executeCompleteWbReg := execute.io.completeRow.wb.reg - io.rfStateError := - (io.rfInitValid && !rfInitTagInRange) || - rf.io.protocolError || - issue.io.protocolError || - scalarSpOrder.io.protocolError || - executeCompletionRetainer.io.protocolError - LinxCoreFrontendFetchRfAluTraceTopIssueDiagnosticsWiring.connect( - io, - issue, - scalarSpOrder, - execute.io.accepted) - io.localTReadyMask := localTReady.asUInt - io.localUReadyMask := localUReady.asUInt - io.localTPendingCount := localTPendingCount - io.localUPendingCount := localUPendingCount - io.localIncomingUsesLocal := localIncomingUsesLocal - io.localIncomingBlocked := localIncomingBlocked - io.decodeBlockedByRename := path.io.blockedByRename - io.decodeBlockedByRob := path.io.blockedByRob - io.decodeBlockedByOutput := path.io.blockedByOutput - io.decodeBlockedByTURename := path.io.blockedByTURename - io.gprFreeCount := path.io.gprFreeCount - io.gprMapQValidCount := path.io.gprMapQValidCount - io.gprMapQFreeCount := path.io.gprMapQFreeCount - io.gprSmapLiveCount := path.io.gprSmapLiveCount - io.gprCmapLiveCount := path.io.gprCmapLiveCount - io.gprMapQLiveCount := path.io.gprMapQLiveCount - io.gprLivePhysCount := path.io.gprLivePhysCount - io.gprFreeFromLiveCount := path.io.gprFreeFromLiveCount - io.gprFreeListMismatchCount := path.io.gprFreeListMismatchCount - io.gprNextMapQValidCount := path.io.gprNextMapQValidCount - io.gprNextMapQLiveCount := path.io.gprNextMapQLiveCount - io.gprNextLivePhysCount := path.io.gprNextLivePhysCount - io.gprNextFreeFromLiveCount := path.io.gprNextFreeFromLiveCount - io.gprCommitAccepted := path.io.gprCommitAccepted - io.gprCommitBlockBid := path.io.gprCommitBlockBid - io.gprCommittedMapQCount := path.io.gprCommittedMapQCount - io.gprReleasedPhysCount := path.io.gprReleasedPhysCount - io.tuRenameSourceUnderflowMask := path.io.tuRenameSourceUnderflowMask - io.tuRenameActiveBankValid := path.io.tuRenameActiveBankValid - io.tuRenameBlockedByTAlloc := path.io.tuRenameBlockedByTAlloc - io.tuRenameBlockedByUAlloc := path.io.tuRenameBlockedByUAlloc - io.tuRenameTUsedEntries := path.io.tuRenameTUsedEntries - io.tuRenameUUsedEntries := path.io.tuRenameUUsedEntries - io.tuRetireCommandValid := path.io.tuRetireCommandValid - io.tuRetireCommandFire := path.io.tuRetireCommandFire - io.tuRetireLocalBlockCommitPending := path.io.tuRetireLocalBlockCommitPending - io.tuRetireLocalBlockCommitValid := path.io.tuRetireLocalBlockCommitValid - io.tuRetireLocalBlockCommitReady := path.io.tuRetireLocalBlockCommitReady - io.tuRetireLocalBlockCommitFire := path.io.tuRetireLocalBlockCommitFire - io.tuRetireAccepted := path.io.tuRetireAccepted - io.tuRetireMiss := path.io.tuRetireMiss - io.tuRetireReleaseMismatch := path.io.tuRetireReleaseMismatch - io.tuRetireUnsupported := path.io.tuRetireUnsupported - - io.commit := path.io.commit - io.commitValidMask := path.io.commitValidMask - io.commitCount := path.io.commitCount - io.commitMonitorValidMask := path.io.commitMonitorValidMask - io.commitMonitorValidCount := path.io.commitMonitorValidCount - io.commitSkippedSlot := path.io.commitSkippedSlot - io.commitDuplicateIdentity := path.io.commitDuplicateIdentity - io.commitSlotMismatch := path.io.commitSlotMismatch - io.commitInvalidSideEffect := path.io.commitInvalidSideEffect - io.commitContractError := path.io.commitContractError - - io.deallocValidMask := path.io.deallocValidMask - io.deallocCount := path.io.deallocCount - io.robDeallocBlockLastValid := path.io.robDeallocBlockLastValid - io.robDeallocBlockLastBlockBid := path.io.robDeallocBlockLastBlockBid - io.blockScalarDoneFire := path.io.blockScalarDoneFire - io.blockScalarDoneBid := path.io.blockScalarDoneBid - io.blockRetireFire := path.io.blockRetireFire - io.blockRetireBid := path.io.blockRetireBid - io.empty := path.io.empty - io.full := path.io.full - io.size := path.io.size - io.outstandingCount := path.io.outstandingCount - io.commitHeadValid := path.io.commitHeadValid - io.commitHeadStatus := path.io.commitHeadStatus - io.commitHeadRobValue := path.io.commitHeadRobValue - io.occupiedMask := path.io.occupiedMask - io.completedMask := path.io.completedMask - io.retiredMask := path.io.retiredMask - io.blockAllocatedMask := path.io.blockAllocatedMask - io.blockCompleteMask := path.io.blockCompleteMask - io.blockPendingMask := path.io.blockPendingMask - io.idle := path.io.empty && issue.io.empty && !execute.io.busy && - !source.io.waitingResponse && !source.io.packetValid && storeCommitOwner.io.idle && - ((!useReducedStoreDispatchStq).B || reducedStoreCommitDrain.io.empty) && - (!reducedLoadReplayLiqAllocEnabled || - (reducedLoadReplayLiqAllocPath.io.empty && reducedLoadReplayResolveQueue.io.empty)) - } - -private object LinxCoreFrontendFetchRfAluTraceTopR379WakeupSinkReadyWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - sink: LoadReplayReturnWakeupSinkReady, - enable: Bool, - flush: Bool, - liveEnable: Bool, - wakeupRequired: Bool): Unit = { - sink.io.enable := enable - sink.io.flush := flush - sink.io.liveEnable := liveEnable - sink.io.wakeupRequired := wakeupRequired - sink.io.sinkReady := true.B - - io.reducedLoadReplayLiqReturnWakeupSinkCandidateValid := sink.io.candidateValid - io.reducedLoadReplayLiqReturnWakeupSinkArmed := sink.io.wakeupArmed - io.reducedLoadReplayLiqReturnWakeupSinkReady := sink.io.wakeupSinkReady - io.reducedLoadReplayLiqReturnWakeupSinkBlockedByDisabled := sink.io.blockedByDisabled - io.reducedLoadReplayLiqReturnWakeupSinkBlockedByFlush := sink.io.blockedByFlush - io.reducedLoadReplayLiqReturnWakeupSinkBlockedByNoWakeup := sink.io.blockedByNoWakeup - io.reducedLoadReplayLiqReturnWakeupSinkBlockedBySink := sink.io.blockedBySink - io.reducedLoadReplayLiqReturnWakeupSinkBlockedByLiveDisabled := sink.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopReplayWakeVisibilityWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - liqAllocPath: ReducedLoadReplayLiqAllocPath, - replayWakeValid: Bool, - replayWakeFlush: Bool): Unit = { - io.reducedLoadReplayLiqReplayWakeValid := replayWakeValid - io.reducedLoadReplayLiqReplayWakeFlush := replayWakeFlush - io.reducedLoadReplayLiqReplayWakeWaitStoreCandidateMask := - liqAllocPath.io.replayWakeWaitStoreCandidateMask - io.reducedLoadReplayLiqReplayWakeBidMatchMask := - liqAllocPath.io.replayWakeBidMatchMask - io.reducedLoadReplayLiqReplayWakeLsIdMatchMask := - liqAllocPath.io.replayWakeLsIdMatchMask - io.reducedLoadReplayLiqReplayWakePcMatchMask := - liqAllocPath.io.replayWakePcMatchMask - io.reducedLoadReplayLiqReplayWakeFullMatchMask := - liqAllocPath.io.replayWakeFullMatchMask - io.reducedLoadReplayLiqReplayWakeStoreUnit := - liqAllocPath.io.replayWakeStoreUnit - io.reducedLoadReplayLiqReplayWakeStoreUnitFullMatchMask := - liqAllocPath.io.replayWakeStoreUnitFullMatchMask - io.reducedLoadReplayLiqReplayWakeWaitStoreClearMask := - liqAllocPath.io.replayWakeWaitStoreClearMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR380WritebackSinkReadyWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - sink: LoadReplayReturnWritebackSinkReady, - enable: Bool, - flush: Bool, - liveEnable: Bool, - writebackRequired: Bool, - sinkReady: Bool): Unit = { - sink.io.enable := enable - sink.io.flush := flush - sink.io.liveEnable := liveEnable - sink.io.writebackRequired := writebackRequired - sink.io.sinkReady := sinkReady - - io.reducedLoadReplayLiqReturnWritebackSinkCandidateValid := sink.io.candidateValid - io.reducedLoadReplayLiqReturnWritebackSinkArmed := sink.io.writebackArmed - io.reducedLoadReplayLiqReturnWritebackSinkReady := sink.io.writebackSinkReady - io.reducedLoadReplayLiqReturnWritebackSinkBlockedByDisabled := sink.io.blockedByDisabled - io.reducedLoadReplayLiqReturnWritebackSinkBlockedByFlush := sink.io.blockedByFlush - io.reducedLoadReplayLiqReturnWritebackSinkBlockedByNoWriteback := sink.io.blockedByNoWriteback - io.reducedLoadReplayLiqReturnWritebackSinkBlockedBySink := sink.io.blockedBySink - io.reducedLoadReplayLiqReturnWritebackSinkBlockedByLiveDisabled := sink.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR385ResidencyAdvanceLiveWiring { - def connect( - enable: Bool, - flush: Bool, - live: LoadReplayReturnPipeResidencyAdvanceLiveControl, - slot: LoadReplayReturnPipeResidencySlot, - w1Slot: LoadReplayReturnPipeW1Slot, - advance: LoadReplayReturnPipeResidencyAdvanceCandidate): Unit = { - live.io.enable := enable - live.io.flush := flush - live.io.requestEnable := slot.io.occupied && !w1Slot.io.occupied - live.io.slotOccupied := slot.io.occupied - live.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - live.io.slotTargetIsLda := slot.io.entryTargetIsLda - live.io.slotPipeIndex := slot.io.entryPipeIndex - - advance.io.enable := enable - advance.io.flush := flush - advance.io.advanceEnable := live.io.advanceEnable - advance.io.slotOccupied := slot.io.occupied - advance.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - advance.io.slotTargetIsLda := slot.io.entryTargetIsLda - advance.io.slotPipeIndex := slot.io.entryPipeIndex - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR386ReducedScalarShapeWiring { - def connect( - enable: Bool, - flush: Bool, - shape: LoadReplayReturnReducedScalarShapeControl, - robResolve: LoadReplayReturnRobResolveDataCandidate, - lane: LoadReplayReturnLaneCompletionCandidate, - tload: LoadReplayReturnTloadCompletionCandidate, - residency: LoadReplayReturnPipeResidencyCandidate): Unit = { - shape.io.enable := enable - shape.io.flush := flush - - robResolve.io.reducedSingleLane := shape.io.reducedSingleLane - - lane.io.scalarLoadPair := shape.io.scalarLoadPair - lane.io.vectorOrMemMultiLane := shape.io.vectorOrMemMultiLane - lane.io.retLaneBefore := shape.io.retLaneBefore - lane.io.returnedLaneCount := Mux(robResolve.io.retLaneIncrement, shape.io.returnedLaneCount, 0.U) - lane.io.realReqCnt := shape.io.realReqCnt - - tload.io.isMemIex := shape.io.isMemIex - tload.io.isTload := shape.io.isTload - tload.io.subInstCntBefore := shape.io.subInstCntBefore - - residency.io.isVectorMachine := shape.io.isVectorMachine - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR388IexPipeOccupancyLiveWiring { - def connect( - live: LoadReplayReturnIexPipeOccupancyLiveControl, - occupancy: LoadReplayReturnIexPipeOccupancy, - enable: Bool, - flush: Bool, - requestEnable: Bool, - sourceValid: Bool, - sourceMask: UInt): Unit = { - live.io.enable := enable - live.io.flush := flush - live.io.requestEnable := requestEnable - live.io.sourceValid := sourceValid - live.io.livePipeOccupiedMaskIn := sourceMask - - occupancy.io.enable := enable - occupancy.io.flush := flush - occupancy.io.liveRequested := live.io.liveRequested - occupancy.io.livePipeOccupiedMask := live.io.livePipeOccupiedMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR547LretSetMemDataWiring { - def connect( - path: DecodeRenameROBPath, - liqPath: ReducedLoadReplayLiqAllocPath, - payload: LoadReplayReturnLretPayload, - sinkEntry: LoadReplayReturnLretEntry, - sink: ScalarLSULoadReturnQueueBank, - drainPermit: LoadReplayReturnIexDrainPermit, - iexData: LoadReplayReturnIexDataCandidate, - pipeOccupiedMask: UInt, - enqueueValid: Bool, - enable: Bool, - flush: Bool, - hardFlush: Bool, - preciseFlush: FlushBus, - entries: Int): Unit = { - sinkEntry.valid := payload.io.payloadValid - sinkEntry.bid := payload.io.payloadBid - sinkEntry.gid := payload.io.payloadGid - sinkEntry.rid := payload.io.payloadRid - sinkEntry.loadLsId := payload.io.payloadLoadLsId - sinkEntry.loadLsIdFullValid := payload.io.payloadLoadLsIdFullValid - sinkEntry.loadLsIdFull := payload.io.payloadLoadLsIdFull - sinkEntry.pc := payload.io.payloadPc - sinkEntry.addr := payload.io.payloadAddr - sinkEntry.size := payload.io.payloadSize - sinkEntry.dst := payload.io.payloadDst - sinkEntry.data := payload.io.payloadData - sinkEntry.pipeIndex := payload.io.payloadPipeIndex - sinkEntry.specWakeup := payload.io.payloadSpecWakeup - sinkEntry.stackValid := payload.io.payloadStackValid - - sink.io.enable := enable - sink.io.flush := hardFlush - sink.io.preciseFlush := preciseFlush - sink.io.enqueueValid := enqueueValid - sink.io.enqueue := sinkEntry - sink.io.enqueuePeId := payload.io.payloadPeId - sink.io.enqueueStid := payload.io.payloadStid - sink.io.enqueueTid := payload.io.payloadTid - sink.io.enqueuePipeIndex := payload.io.payloadPipeIndex - assert( - !enable || flush || !enqueueValid || sink.io.enqueueAccepted, - "published scalar load return must enter its selected LRET queue atomically") - - val drainHoldMask = - Mux( - sink.io.drainValid && sink.io.drain.valid && sink.io.drain.rid.valid, - UIntToOH(sink.io.drain.rid.value, entries), - 0.U(entries.W)) - val enqueueHoldMask = - Mux( - sink.io.enqueueAccepted && sinkEntry.rid.valid, - UIntToOH(sinkEntry.rid.value, entries), - 0.U(entries.W)) - val payloadCandidateHoldMask = - Mux( - payload.io.candidateValid && payload.io.selectedRid.valid, - UIntToOH(payload.io.selectedRid.value, entries), - 0.U(entries.W)) - val liqAllocHoldMask = - Mux( - liqPath.io.allocAccepted && liqPath.io.candidate.rid.valid, - UIntToOH(liqPath.io.candidate.rid.value, entries), - 0.U(entries.W)) - val drainClearMask = - Mux( - sink.io.drainFire && sink.io.drain.rid.valid, - UIntToOH(sink.io.drain.rid.value, entries), - 0.U(entries.W)) - val outstandingHoldMask = RegInit(0.U(entries.W)) - when(flush || !enable) { - outstandingHoldMask := 0.U - }.otherwise { - outstandingHoldMask := (outstandingHoldMask | liqAllocHoldMask) & ~drainClearMask - } - - path.io.deallocHoldMask := - Mux( - enable && !flush, - outstandingHoldMask | liqAllocHoldMask | drainHoldMask | enqueueHoldMask | payloadCandidateHoldMask, - 0.U(entries.W)) - - drainPermit.io.enable := enable - drainPermit.io.flush := flush - drainPermit.io.sinkValid := sink.io.drainValid - drainPermit.io.pipeOccupiedMask := pipeOccupiedMask - sink.io.drainReady := drainPermit.io.drainReady - - path.io.robStatusLookupValid := enable && !flush && sink.io.drainValid && sink.io.drain.valid - path.io.robStatusLookupRid := sink.io.drain.rid - - iexData.io.enable := enable - iexData.io.flush := flush - iexData.io.sinkValid := sink.io.drainValid - iexData.io.drainReady := drainPermit.io.drainReady - iexData.io.entry := sink.io.drain - iexData.io.robRowValid := path.io.robStatusLookup.rowValid - iexData.io.robRowNeedFlush := path.io.robStatusLookup.needFlush - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR395StoreSnapshotPathWiring { - def connectInputs( - path: LoadReplaySourceReturnStoreSnapshotPath, - enable: Bool, - flush: Bool, - preciseFlush: FlushBus, - liveArmPolicyEnable: Bool, - liveArmRawSinkAvailable: Bool, - rowMutationLiveEnable: Bool, - launchValid: Bool, - selectedLaunchIndex: UInt, - selectedRepickMask: UInt, - selectedRowValidMask: UInt, - selectedRowScbReturnedMask: UInt, - selectedPickAccepted: Bool, - selectedLoadId: ROBID, - selectedBid: ROBID, - selectedGid: ROBID, - selectedRid: ROBID, - selectedLoadLsId: ROBID, - selectedLoadLsIdFullValid: Bool, - selectedLoadLsIdFull: UInt, - selectedPeId: UInt, - selectedStid: UInt, - selectedTid: UInt, - selectedPc: UInt, - selectedAddr: UInt, - selectedSize: UInt, - selectedRequestByteMask: UInt, - selectedLineData: UInt, - selectedValidMask: UInt, - legacySnapshotReady: Bool): Bool = { - path.io.enable := enable - path.io.flush := flush - path.io.preciseFlush := preciseFlush - path.io.requestEnable := false.B - path.io.rowMutationLiveEnable := rowMutationLiveEnable - path.io.rawResponseLiveEnable := false.B - path.io.liveArmPolicyEnable := liveArmPolicyEnable - path.io.liveArmRawSinkAvailable := liveArmRawSinkAvailable - path.io.launchValid := launchValid - path.io.sinkReady := false.B - path.io.selectedIdentityEnable := true.B - path.io.selectedLaunchIndex := selectedLaunchIndex - path.io.selectedRepickMask := selectedRepickMask - path.io.selectedRowValidMask := selectedRowValidMask - path.io.selectedRowScbReturnedMask := selectedRowScbReturnedMask - path.io.selectedValid := false.B - path.io.selectedRepick := false.B - path.io.selectedPickAccepted := selectedPickAccepted - path.io.responseValidIn := false.B - path.io.selectedClusterId := 0.U - path.io.selectedEntryId := 0.U - path.io.selectedLoadId := selectedLoadId - path.io.selectedBid := selectedBid - path.io.selectedGid := selectedGid - path.io.selectedRid := selectedRid - path.io.selectedLoadLsId := selectedLoadLsId - path.io.selectedLoadLsIdFullValid := selectedLoadLsIdFullValid - path.io.selectedLoadLsIdFull := selectedLoadLsIdFull - path.io.selectedPeId := selectedPeId - path.io.selectedStid := selectedStid - path.io.selectedTid := selectedTid - path.io.selectedPc := selectedPc - path.io.selectedAddr := selectedAddr - path.io.selectedSize := selectedSize - path.io.selectedRequestByteMask := selectedRequestByteMask - path.io.selectedLineData := selectedLineData - path.io.selectedValidMask := selectedValidMask - path.io.responseClusterId := 0.U - path.io.responseEntryId := 0.U - path.io.responseHeadStale := false.B - path.io.scbReturned := false.B - path.io.responseRequestBid := 0.U.asTypeOf(path.io.responseRequestBid) - path.io.responseRequestGid := 0.U.asTypeOf(path.io.responseRequestGid) - path.io.responseRequestRid := 0.U.asTypeOf(path.io.responseRequestRid) - path.io.responseRequestLoadLsId := 0.U.asTypeOf(path.io.responseRequestLoadLsId) - path.io.responseRequestLoadLsIdFullValid := false.B - path.io.responseRequestLoadLsIdFull := 0.U - path.io.responseRequestPeId := 0.U - path.io.responseRequestStid := 0.U - path.io.responseRequestTid := 0.U - path.io.waitStoreIn := false.B - path.io.dataValidIn := false.B - path.io.rawDataValidIn := false.B - path.io.dataSuppressedByWaitIn := false.B - path.io.responseWaitStoreIndex := 0.U - path.io.responseWaitStoreBid := 0.U.asTypeOf(path.io.responseWaitStoreBid) - path.io.responseWaitStoreRid := 0.U.asTypeOf(path.io.responseWaitStoreRid) - path.io.responseWaitStoreLsId := 0.U.asTypeOf(path.io.responseWaitStoreLsId) - path.io.responseWaitStoreLsIdFullValid := false.B - path.io.responseWaitStoreLsIdFull := 0.U - path.io.responseWaitStorePc := 0.U - path.io.responseDataMask := 0.U - path.io.responseData := 0.U - path.io.legacySnapshotReady := legacySnapshotReady - - path.io.storeSnapshotReady - } - - def connectOutputs( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: LoadReplaySourceReturnStoreSnapshotPath): Unit = { - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveActive := - path.io.controlActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveRequestActive := - path.io.controlRequestActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveEvidenceValid := - path.io.controlSnapshotEvidenceValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLegacyReady := - path.io.controlLegacyReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveReady := - path.io.controlLiveReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByRequestDisabled := - path.io.controlBlockedByRequestDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByLegacySnapshot := - path.io.controlBlockedByLegacySnapshot - io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedBySnapshot := - path.io.controlBlockedBySnapshot - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyActive := - path.io.liveArmPolicyActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestCandidate := - path.io.liveArmPolicyRequestCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestEnable := - path.io.liveArmPolicyRequestEnable - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkCandidate := - path.io.liveArmPolicySinkCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkReady := - path.io.liveArmPolicySinkReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponsePortBlocked := - path.io.liveArmPolicyResponsePortBlocked - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByDisabled := - path.io.liveArmPolicyBlockedByDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByFlush := - path.io.liveArmPolicyBlockedByFlush - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByPolicyDisabled := - path.io.liveArmPolicyBlockedByPolicyDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByNoLaunch := - path.io.liveArmPolicyRequestBlockedByNoLaunch - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRowMutationDisabled := - path.io.liveArmPolicyRequestBlockedByRowMutationDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRequestQueue := - path.io.liveArmPolicyRequestBlockedByRequestQueue - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByAcceptedToken := - path.io.liveArmPolicyRequestBlockedByAcceptedToken - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByNoRequest := - path.io.liveArmPolicySinkBlockedByNoRequest - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRowMutationDisabled := - path.io.liveArmPolicySinkBlockedByRowMutationDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRawSink := - path.io.liveArmPolicySinkBlockedByRawSink - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByQueueFull := - path.io.liveArmPolicyResponseBlockedByQueueFull - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByRawResponse := - path.io.liveArmPolicyResponseBlockedByRawResponse - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestEnable := - path.io.effectiveRequestEnable - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestQueueCanAccept := - path.io.effectiveRequestQueueCanAccept - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveSinkReady := - path.io.effectiveSinkReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestControlBlockedByToken := - path.io.requestControlBlockedByToken - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCanAccept := - path.io.acceptedTokenCanAccept - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenValid := - path.io.acceptedTokenValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenResidentValid := - path.io.acceptedTokenResidentValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureCandidate := - path.io.acceptedTokenCaptureCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureAccepted := - path.io.acceptedTokenCaptureAccepted - io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenBlockedByOutstanding := - path.io.acceptedTokenBlockedByOutstanding - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadValid := - path.io.requestPayloadValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoIssue := - path.io.requestPayloadBlockedByNoIssue - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoSelected := - path.io.requestPayloadBlockedByNoSelected - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByStaleRow := - path.io.requestPayloadBlockedByStaleRow - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadValid := - path.io.requestQueueHeadValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadConsumed := - path.io.requestQueueHeadConsumed - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePending := - path.io.requestQueuePending - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueFull := - path.io.requestQueueFull - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueEmpty := - path.io.requestQueueEmpty - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueCount := - path.io.requestQueueCount - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByFull := - path.io.requestQueueBlockedByFull - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneMask := - path.io.requestQueuePrecisePruneMask - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneCount := - path.io.requestQueuePrecisePruneCount - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByPreciseFlush := - path.io.requestQueueBlockedByPreciseFlush - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkCandidate := - path.io.requestSinkCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkReady := - path.io.requestSinkReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkAccepted := - path.io.requestSinkAccepted - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkResponseValid := - path.io.requestSinkResponseValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByNoRequest := - path.io.requestSinkBlockedByNoRequest - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByRawSink := - path.io.requestSinkBlockedByRawSink - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByResponse := - path.io.requestSinkBlockedByResponse - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEnqueueAccepted := - path.io.responseQueueEnqueueAccepted - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadValid := - path.io.responseQueueHeadValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadConsumed := - path.io.responseQueueHeadConsumed - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePending := - path.io.responseQueuePending - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueFull := - path.io.responseQueueFull - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEmpty := - path.io.responseQueueEmpty - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueCount := - path.io.responseQueueCount - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByFull := - path.io.responseQueueBlockedByFull - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneMask := - path.io.responseQueuePrecisePruneMask - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneCount := - path.io.responseQueuePrecisePruneCount - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByPreciseFlush := - path.io.responseQueueBlockedByPreciseFlush - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainDequeueReady := - path.io.responseDrainDequeueReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainOrderedConsumed := - path.io.responseDrainOrderedConsumed - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainStaleDropped := - path.io.responseDrainStaleDropped - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoHead := - path.io.responseDrainBlockedByNoHead - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoAction := - path.io.responseDrainBlockedByNoAction - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupQueryValid := - path.io.lookupQueryValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupWaitStoreValid := - path.io.lookupWaitStoreValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupRawDataValid := - path.io.lookupRawDataValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupResponseDataValid := - path.io.lookupResponseDataValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupStoreBypassComplete := - path.io.lookupStoreBypassComplete - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceActive := - path.io.evidenceActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceRequestValid := - path.io.evidenceRequestValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceQueryActive := - path.io.evidenceQueryActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceResponseAccepted := - path.io.evidenceResponseAccepted - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotRequired := - path.io.evidenceSnapshotRequired - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotValid := - path.io.evidenceSnapshotValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceWaitStoreReplay := - path.io.evidenceWaitStoreReplay - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoQuery := - path.io.evidenceBlockedByNoQuery - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoResponse := - path.io.evidenceBlockedByNoResponse - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByWaitStore := - path.io.evidenceBlockedByWaitStore - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidResponseWithoutQuery := - path.io.evidenceInvalidResponseWithoutQuery - io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidDataWithWaitStore := - path.io.evidenceInvalidDataWithWaitStore - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueActive := - path.io.queryIssueActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueRequestActive := - path.io.queryIssueRequestActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueCandidate := - path.io.queryIssueCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueValid := - path.io.queryIssueValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued := - path.io.queryIssueIssued - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByRequestDisabled := - path.io.queryIssueBlockedByRequestDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByNoLaunch := - path.io.queryIssueBlockedByNoLaunch - io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedBySink := - path.io.queryIssueBlockedBySink - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyActive := - path.io.responseApplyActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyCandidate := - path.io.responseApplyCandidate - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid := - path.io.responseApplyValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyTargetMask := - path.io.responseApplyTargetMask - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyWaitStore := - path.io.responseApplyWaitStore - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataMerge := - path.io.responseApplyDataMerge - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataNoMerge := - path.io.responseApplyDataNoMerge - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyMergedRequestComplete := - path.io.responseApplyMergedRequestComplete - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoOrderedResponse := - path.io.responseApplyBlockedByNoOrderedResponse - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNotRepick := - path.io.responseApplyBlockedByNotRepick - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByWaitStore := - path.io.responseApplyBlockedByWaitStore - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoData := - path.io.responseApplyBlockedByNoData - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidOrderedWithoutPayload := - path.io.responseApplyInvalidOrderedWithoutPayload - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataWithWaitStore := - path.io.responseApplyInvalidDataWithWaitStore - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataValidWithoutRawData := - path.io.responseApplyInvalidDataValidWithoutRawData - io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidSuppressedDataWithoutWait := - path.io.responseApplyInvalidSuppressedDataWithoutWait - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanActive := - path.io.rowStatePlanActive - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanValid := - path.io.rowStatePlanValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanRewait := - path.io.rowStatePlanRewait - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataMerge := - path.io.rowStatePlanDataMerge - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataNoMerge := - path.io.rowStatePlanDataNoMerge - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanSetWaitStatus := - path.io.rowStatePlanSetWaitStatus - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanKeepRepickStatus := - path.io.rowStatePlanKeepRepickStatus - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanClearReturnState := - path.io.rowStatePlanClearReturnState - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanLineWrite := - path.io.rowStatePlanLineWrite - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanWaitStoreWrite := - path.io.rowStatePlanWaitStoreWrite - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextDataComplete := - path.io.rowStatePlanNextDataComplete - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextScbReturned := - path.io.rowStatePlanNextScbReturned - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStqReturned := - path.io.rowStatePlanNextStqReturned - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStoreSourceReturned := - path.io.rowStatePlanNextStoreSourceReturned - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanBlockedByNoApply := - path.io.rowStatePlanBlockedByNoApply - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidApplyWithoutStqReturned := - path.io.rowStatePlanInvalidApplyWithoutStqReturned - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqReturnedWithoutApply := - path.io.rowStatePlanInvalidStqReturnedWithoutApply - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqApplyWithoutScb := - path.io.rowStatePlanInvalidStqApplyWithoutScb - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid := - path.io.rowMutationCandidateValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateTargetMask := - path.io.rowMutationCandidateTargetMask - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationTargetReady := - path.io.rowMutationTargetReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid := - path.io.rowMutationRequestValid - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetMask := - path.io.rowMutationRequestTargetMask - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetIndex := - path.io.rowMutationRequestTargetIndex - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByNoTarget := - path.io.rowMutationBlockedByNoTarget - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByLiveDisabled := - path.io.rowMutationBlockedByLiveDisabled - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationInvalidMultiTarget := - path.io.rowMutationInvalidMultiTarget - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady := - path.io.rowMutationHeadProofReady - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit := - path.io.rowMutationLivePermit - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof := - path.io.rowMutationBlockedByHeadProof - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow := - path.io.rowMutationBlockedByHeadInvalidRow - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned := - path.io.rowMutationBlockedByHeadScbNotReturned - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick := - path.io.rowMutationBlockedByHeadNotRepick - io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch := - path.io.rowMutationBlockedByHeadTargetMismatch - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR417RowMutationWiring { - def connect( - source: LoadReplaySourceReturnStoreSnapshotPath, - liqPath: ReducedLoadReplayLiqAllocPath, - sourceReadiness: LoadReplaySourceReturnReadiness, - scbLive: LoadReplaySourceReturnScbLiveControl, - enable: Bool, - flush: Bool, - launchValid: Bool, - baseDataReady: Bool, - storeSnapshotReady: Bool): Unit = { - liqPath.io.pickValid := source.io.queryIssueIssued - liqPath.io.pickIndex := liqPath.io.launchIndex - val scbReturnEntryIndex = source.io.acceptedTokenEntryId(liqPath.io.scbReturnIndex.getWidth - 1, 0) - liqPath.io.scbReturnValid := - enable && !flush && source.io.acceptedTokenResidentValid && (source.io.acceptedTokenClusterId === 0.U) - liqPath.io.scbReturnIndex := scbReturnEntryIndex - - sourceReadiness.io.enable := enable - sourceReadiness.io.launchValid := launchValid - sourceReadiness.io.baseDataReady := baseDataReady - sourceReadiness.io.storeSnapshotReady := storeSnapshotReady - scbLive.io.enable := enable - scbLive.io.flush := flush - scbLive.io.requestEnable := false.B - scbLive.io.scbPendingEvidence := false.B - scbLive.io.scbReturnedEvidence := false.B - sourceReadiness.io.externalScbPending := scbLive.io.externalScbPending - sourceReadiness.io.externalScbReturned := scbLive.io.externalScbReturned - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopPairLoadWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - rf: ScalarGPRFile, - issue: ScalarIssueFabric, - path: DecodeRenameROBPath, - execute: ReducedScalarAluExecute): Unit = { - execute.io.loadPairFirstLookupData := io.loadPairFirstLookupData - - rf.io.clearSecondValid := - issue.io.inputAcceptFire && - issue.io.inputAcceptUop.pairFirstDst.valid && - (issue.io.inputAcceptUop.pairFirstDst.kind === DestinationKind.Gpr) - rf.io.clearSecondTag := issue.io.inputAcceptUop.pairFirstDst.physTag - - rf.io.write(1).requestValid := execute.io.completePairFirstDstPhysValid - rf.io.write(1).commit := execute.io.completePairFirstDstPhysValid - rf.io.write(1).tag := execute.io.completePairFirstDstPhysTag - rf.io.write(1).data := execute.io.completePairFirstDstData - - io.loadPairFirstLookupValid := execute.io.loadPairFirstLookupValid - io.loadPairFirstLookupAddr := execute.io.loadPairFirstLookupAddr - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR660MdbStoreAdmissionWiring { - def connect( - p: InterfaceParams, - enabled: Bool, - flush: Bool, - path: DecodeRenameROBPath, - liqPath: ReducedLoadReplayLiqAllocPath, - resolveQueue: LoadResolveQueue, - mdb: ScalarLSUMDBPath): MDBConflictStoreProbe = { - val live = Wire(new MDBConflictStoreProbe( - p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth - )) - live := 0.U.asTypeOf(live) - live.bid := ROBID.disabled(p.robEntries) - live.gid := ROBID.disabled(p.robEntries) - live.rid := ROBID.disabled(p.robEntries) - live.lsId := ROBID.disabled(p.robEntries) - val intent = path.io.storeStqInsertIntent - val carriesAddress = intent.storeType =/= STQStoreType.Data - live.valid := enabled && path.io.storeStqInsertIntentValid && carriesAddress - live.addrOnly := intent.storeType === STQStoreType.Addr - live.isTile := !intent.scalarIex - live.peId := intent.peId - live.stid := intent.stid - live.tid := intent.tid - live.bid := intent.bid - live.gid := intent.gid - live.rid := intent.rid - live.lsId := intent.lsId - live.pc := intent.pc - live.addr := intent.addr - live.size := intent.size.pad(7) - - val replay = Module(new MDBStoreProbeReplay( - p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth - )) - replay.io.flush := flush || !enabled - replay.io.live := live - val acceptedCarriesAddress = - path.io.storeStqInsertAccepted && - (path.io.storeStqInsert.storeType =/= STQStoreType.Data) - replay.io.liveCommit := acceptedCarriesAddress - replay.io.retainForReplay := VecInit( - liqPath.io.rows.map(row => row.valid && (row.status =/= LoadInflightStatus.Resolved)) - ).asUInt.orR - replay.io.replayEnable := resolveQueue.io.count =/= 0.U - - mdb.io.storeProbe := replay.io.out - mdb.io.storeProbeCommit := - (replay.io.liveSelected && acceptedCarriesAddress) || - replay.io.replaySelected - val consume = mdb.io.storeProbeCommit && mdb.io.storeProbeReady - replay.io.replayConsume := consume - path.io.storeAddressInsertPermit := - !enabled || (replay.io.liveReady && mdb.io.storeProbeReady) - - assert( - !enabled || !acceptedCarriesAddress || - (replay.io.liveSelected && consume), - "accepted address-bearing store must enter canonical MDB atomically" - ) - replay.io.out - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR659CanonicalMdbMutationWiring { - def connect( - p: InterfaceParams, - io: LinxCoreFrontendFetchRfAluTraceTopIO, - source: LoadReplaySourceReturnStoreSnapshotPath, - mdb: ScalarLSUMDBPath, - liqPath: ReducedLoadReplayLiqAllocPath, - storeEntries: Int): (Bool, LoadInflightRowMutationRequestBridge) = { - val mux = Module(new LoadReplayRowMutationSourceMux( - liqEntries = p.robEntries, - idEntries = p.robEntries, - sourceStoreEntries = storeEntries, - pcWidth = p.pcWidth, - lineBytes = 64, - lsidWidth = p.lsidWidth - )) - - mux.io.sourceReturn.valid := source.io.rowMutationRequestValid - mux.io.sourceReturn.targetMask := source.io.rowMutationRequestTargetMask - mux.io.sourceReturn.targetIndex := source.io.rowMutationRequestTargetIndex - mux.io.sourceReturn.setWaitStatus := source.io.rowMutationSetWaitStatus - mux.io.sourceReturn.keepRepickStatus := source.io.rowMutationKeepRepickStatus - mux.io.sourceReturn.clearReturnState := source.io.rowMutationClearReturnState - mux.io.sourceReturn.lineWrite := source.io.rowMutationLineWrite - mux.io.sourceReturn.waitStoreWrite := source.io.rowMutationWaitStoreWrite - mux.io.sourceReturn.nextWaitStore := source.io.rowMutationNextWaitStore - mux.io.sourceReturn.nextWaitStoreInfo := source.io.rowMutationNextWaitStoreInfo - mux.io.sourceReturn.nextLineData := source.io.rowMutationNextLineData - mux.io.sourceReturn.nextValidMask := source.io.rowMutationNextValidMask - mux.io.sourceReturn.nextDataComplete := source.io.rowMutationNextDataComplete - mux.io.sourceReturn.nextScbReturned := source.io.rowMutationNextScbReturned - mux.io.sourceReturn.nextStqReturned := source.io.rowMutationNextStqReturned - mux.io.sourceReturn.nextStoreSourceReturned := source.io.rowMutationNextStoreSourceReturned - - mux.io.mdbWaitPlan.valid := mdb.io.mutationValid - mux.io.mdbWaitPlan.targetMask := mdb.io.mutationTargetMask - mux.io.mdbWaitPlan.targetIndex := mdb.io.mutationTargetIndex - mux.io.mdbWaitPlan.setWaitStatus := mdb.io.mutationSetWaitStatus - mux.io.mdbWaitPlan.keepRepickStatus := false.B - mux.io.mdbWaitPlan.clearReturnState := mdb.io.mutationClearReturnState - mux.io.mdbWaitPlan.lineWrite := mdb.io.mutationLineWrite - mux.io.mdbWaitPlan.waitStoreWrite := mdb.io.mutationWaitStoreWrite - mux.io.mdbWaitPlan.nextWaitStore := mdb.io.mutationNextWaitStore - mux.io.mdbWaitPlan.nextWaitStoreInfo := mdb.io.mutationNextWaitStoreInfo - mux.io.mdbWaitPlan.nextLineData := 0.U - mux.io.mdbWaitPlan.nextValidMask := 0.U - mux.io.mdbWaitPlan.nextDataComplete := false.B - mux.io.mdbWaitPlan.nextScbReturned := false.B - mux.io.mdbWaitPlan.nextStqReturned := false.B - mux.io.mdbWaitPlan.nextStoreSourceReturned := false.B - - liqPath.io.rowMutationRequestValid := mux.io.out.valid - liqPath.io.rowMutationRequestTargetMask := mux.io.out.targetMask - liqPath.io.rowMutationRequestTargetIndex := mux.io.out.targetIndex - liqPath.io.rowMutationSetWaitStatus := mux.io.out.setWaitStatus - liqPath.io.rowMutationKeepRepickStatus := mux.io.out.keepRepickStatus - liqPath.io.rowMutationClearReturnState := mux.io.out.clearReturnState - liqPath.io.rowMutationLineWrite := mux.io.out.lineWrite - liqPath.io.rowMutationWaitStoreWrite := mux.io.out.waitStoreWrite - liqPath.io.rowMutationNextWaitStore := mux.io.out.nextWaitStore - liqPath.io.rowMutationNextWaitStoreInfo := mux.io.out.nextWaitStoreInfo - liqPath.io.rowMutationNextLineData := mux.io.out.nextLineData - liqPath.io.rowMutationNextValidMask := mux.io.out.nextValidMask - liqPath.io.rowMutationNextDataComplete := mux.io.out.nextDataComplete - liqPath.io.rowMutationNextScbReturned := mux.io.out.nextScbReturned - liqPath.io.rowMutationNextStqReturned := mux.io.out.nextStqReturned - liqPath.io.rowMutationNextStoreSourceReturned := mux.io.out.nextStoreSourceReturned - liqPath.io.rowMutationAllowWaitTarget := - mux.io.selectedMdbWaitPlan && !mux.io.selectedSourceReturn - liqPath.io.rowMutationRequireScbReturned := mux.io.selectedSourceReturn - - io.reducedLoadReplayLiqRowMutationSelectedSourceReturn := mux.io.selectedSourceReturn - io.reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan := mux.io.selectedMdbWaitPlan - io.reducedLoadReplayLiqRowMutationSourceConflict := mux.io.conflict - - val bridge = Module(new LoadInflightRowMutationRequestBridge( - liqEntries = p.robEntries, - idEntries = p.robEntries, - sourceStoreEntries = storeEntries, - storeEntries = storeEntries, - pcWidth = p.pcWidth, - lsidWidth = p.lsidWidth - )) - bridge.io.enable := true.B - bridge.io.flush := false.B - bridge.io.requestValid := mdb.io.mutationValid - bridge.io.requestTargetMask := mdb.io.mutationTargetMask - bridge.io.requestTargetIndex := mdb.io.mutationTargetIndex - bridge.io.setWaitStatus := mdb.io.mutationSetWaitStatus - bridge.io.keepRepickStatus := false.B - bridge.io.clearReturnState := mdb.io.mutationClearReturnState - bridge.io.lineWrite := mdb.io.mutationLineWrite - bridge.io.waitStoreWrite := mdb.io.mutationWaitStoreWrite - bridge.io.nextWaitStore := mdb.io.mutationNextWaitStore - bridge.io.nextWaitStoreInfo := mdb.io.mutationNextWaitStoreInfo - bridge.io.nextLineData := 0.U - bridge.io.nextValidMask := 0.U - bridge.io.nextDataComplete := false.B - bridge.io.nextScbReturned := false.B - bridge.io.nextStqReturned := false.B - bridge.io.nextStoreSourceReturned := false.B - - val accepted = mux.io.selectedMdbWaitPlan && liqPath.io.rowMutationApplyValid - (accepted, bridge) - } -} -private object LinxCoreFrontendFetchRfAluTraceTopR659MdbVisibilityWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - mdb: ScalarLSUMDBPath, - lookupValid: Bool): Unit = { - io.reducedMdbFanoutLookupValid := lookupValid - io.reducedMdbFanoutLookupReady := mdb.io.loadLookupReady - io.reducedMdbFanoutLookupAccepted := mdb.io.lookupAccepted - io.reducedMdbFanoutLookupProcessed := mdb.io.lookupProcessed - io.reducedMdbFanoutLookupTableHit := mdb.io.lookupHit - io.reducedMdbFanoutLookupFirstAfterNuke := mdb.io.lookupFirstAfterNuke - io.reducedMdbFanoutLookupConfBlocked := mdb.io.lookupConfBlocked - io.reducedMdbFanoutLookupWeightBlocked := mdb.io.lookupWeightBlocked - io.reducedMdbFanoutDeleteValid := mdb.io.deleteValid - io.reducedMdbFanoutDeleteReady := mdb.io.deleteReady - io.reducedMdbFanoutDeleteAccepted := mdb.io.deleteAccepted - io.reducedMdbFanoutDeleteProcessed := mdb.io.deleteProcessed - io.reducedMdbFanoutPhaseStalledByFanout := mdb.io.phaseStalledByFanout - io.reducedMdbFanoutLuOutValid := mdb.io.lookupOutputValid - io.reducedMdbFanoutLuOutHit := mdb.io.lookupOutput.hit - io.reducedMdbFanoutLuOutStoreBidValid := mdb.io.lookupOutput.stInfo.bid.valid - io.reducedMdbFanoutLuOutStoreBidWrap := mdb.io.lookupOutput.stInfo.bid.wrap - io.reducedMdbFanoutLuOutStoreBidValue := mdb.io.lookupOutput.stInfo.bid.value - io.reducedMdbFanoutSuOutValid := mdb.io.storeOutputValid - io.reducedMdbFanoutSuOutHit := mdb.io.storeOutput.hit - io.reducedMdbFanoutSuOutStoreBidValid := mdb.io.storeOutput.stInfo.bid.valid - io.reducedMdbFanoutSuOutStoreBidWrap := mdb.io.storeOutput.stInfo.bid.wrap - io.reducedMdbFanoutSuOutStoreBidValue := mdb.io.storeOutput.stInfo.bid.value - io.reducedMdbFanoutRecordValid := mdb.io.recordValid - io.reducedMdbFanoutRecordReady := mdb.io.recordReady - io.reducedMdbFanoutRecordAccepted := mdb.io.recordAccepted - io.reducedMdbFanoutRecordProcessed := mdb.io.recordProcessed - io.reducedMdbFanoutBmdbReportValid := mdb.io.bmdbReportValid - io.reducedMdbFanoutBmdbLoadBidValid := mdb.io.bmdbLoadBid.valid - io.reducedMdbFanoutBmdbLoadBidWrap := mdb.io.bmdbLoadBid.wrap - io.reducedMdbFanoutBmdbLoadBidValue := mdb.io.bmdbLoadBid.value - io.reducedMdbFanoutBmdbStoreBidValid := mdb.io.bmdbStoreBid.valid - io.reducedMdbFanoutBmdbStoreBidWrap := mdb.io.bmdbStoreBid.wrap - io.reducedMdbFanoutBmdbStoreBidValue := mdb.io.bmdbStoreBid.value - io.reducedMdbFanoutBmdbStoreStid := mdb.io.bmdbStoreStid - io.reducedMdbFanoutDeleteMatched := mdb.io.deleteMatched - io.reducedMdbFanoutDeleteReleased := mdb.io.deleteReleased - io.reducedMdbFanoutDeleteDroppedBelowStall := mdb.io.deleteDroppedBelowStall - io.reducedMdbFanoutRecordOverflow := mdb.io.recordOverflow - io.reducedMdbFanoutRecordOrderIllegal := mdb.io.recordOrderIllegal - io.reducedMdbFanoutSsitValidMask := mdb.io.ssitValidMask - io.reducedMdbFanoutSuMatchedStore := mdb.io.storeMatched - io.reducedMdbFanoutSuStorePending := mdb.io.storePending - io.reducedMdbFanoutSuWakeupValid := mdb.io.storeWakeup.valid - io.reducedMdbFanoutSuWakeupIndex := mdb.io.storeWakeup.storeIndex - } -} -private object LinxCoreFrontendFetchRfAluTraceTopR465MdbLookupWaitPlanVisibilityWiring { - def connect(io: LinxCoreFrontendFetchRfAluTraceTopIO, mdb: ScalarLSUMDBPath): Unit = { - io.reducedMdbLookupWaitPlanLookupHit := mdb.io.lookupPlanLookupHit - io.reducedMdbLookupWaitPlanCandidateMask := mdb.io.lookupPlanCandidateMask - io.reducedMdbLookupWaitPlanTargetIndex := mdb.io.lookupPlanTargetIndex - io.reducedMdbLookupWaitPlanWaitIntentValid := mdb.io.lookupPlanWaitIntentValid - io.reducedMdbLookupWaitPlanRequestValid := mdb.io.lookupPlanRequestValid - io.reducedMdbLookupWaitPlanBlockedByNoTarget := mdb.io.lookupPlanBlockedByNoTarget - io.reducedMdbLookupWaitPlanBlockedByMissingStoreIndex := mdb.io.lookupPlanBlockedByMissingStoreIndex - io.reducedMdbLookupWaitPlanBlockedByMissingStoreLsId := mdb.io.lookupPlanBlockedByMissingStoreLsId - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR466MdbLookupWaitPlanBridgeVisibilityWiring { - def connect(io: LinxCoreFrontendFetchRfAluTraceTopIO, bridge: LoadInflightRowMutationRequestBridge): Unit = { - io.reducedMdbLookupWaitPlanBridge.active := bridge.io.active - io.reducedMdbLookupWaitPlanBridge.valid := bridge.io.bridgeValid - io.reducedMdbLookupWaitPlanBridge.sourceStoreIndexFits := bridge.io.sourceStoreIndexFits - io.reducedMdbLookupWaitPlanBridge.blockedByDisabled := bridge.io.blockedByDisabled - io.reducedMdbLookupWaitPlanBridge.blockedByFlush := bridge.io.blockedByFlush - io.reducedMdbLookupWaitPlanBridge.blockedByNoRequest := bridge.io.blockedByNoRequest - io.reducedMdbLookupWaitPlanBridge.invalidStoreIndexOutOfRange := bridge.io.invalidStoreIndexOutOfRange - io.reducedMdbLookupWaitPlanBridge.invalidConflictingStatusWrite := bridge.io.invalidConflictingStatusWrite - io.reducedMdbLookupWaitPlanBridge.invalidWaitStoreWithoutWaitStatus := bridge.io.invalidWaitStoreWithoutWaitStatus - io.reducedMdbLookupWaitPlanBridge.invalidReturnWithoutSplitSources := bridge.io.invalidReturnWithoutSplitSources - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR453ReplayLiqRefillTieOff { - def connect(path: ReducedLoadReplayLiqAllocPath): Unit = { - path.io.refillValid := false.B - path.io.refill := 0.U.asTypeOf(path.io.refill) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR428RowMutationVisibilityWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - liqPath: ReducedLoadReplayLiqAllocPath): Unit = { - io.reducedLoadReplayLiqRowMutationBridgeValid := liqPath.io.rowMutationBridgeValid - io.reducedLoadReplayLiqRowMutationSourceStoreIndexFits := liqPath.io.rowMutationSourceStoreIndexFits - io.reducedLoadReplayLiqRowMutationInvalidStoreIndexOutOfRange := liqPath.io.rowMutationInvalidStoreIndexOutOfRange - io.reducedLoadReplayLiqRowMutationInvalidConflictingStatusWrite := - liqPath.io.rowMutationInvalidConflictingStatusWrite - io.reducedLoadReplayLiqRowMutationInvalidWaitStoreWithoutWaitStatus := - liqPath.io.rowMutationInvalidWaitStoreWithoutWaitStatus - io.reducedLoadReplayLiqRowMutationInvalidReturnWithoutSplitSources := - liqPath.io.rowMutationInvalidReturnWithoutSplitSources - io.reducedLoadReplayLiqRowMutationWriteEnable := liqPath.io.rowMutationWriteEnable - io.reducedLoadReplayLiqRowMutationApplyValid := liqPath.io.rowMutationApplyValid - io.reducedLoadReplayLiqRowMutationTargetEvidenceValid := liqPath.io.rowMutationTargetEvidenceValid - io.reducedLoadReplayLiqRowMutationWriteConflict := liqPath.io.rowMutationWriteConflict - io.reducedLoadReplayLiqRowMutationBlockedByBridge := liqPath.io.rowMutationBlockedByBridge - io.reducedLoadReplayLiqRowMutationBlockedByControl := liqPath.io.rowMutationBlockedByControl - io.reducedLoadReplayLiqRowMutationControlBlockedByInvalidRow := - liqPath.io.rowMutationControlBlockedByInvalidRow - io.reducedLoadReplayLiqRowMutationControlBlockedByNotRepick := - liqPath.io.rowMutationControlBlockedByNotRepick - io.reducedLoadReplayLiqRowMutationControlBlockedByScbNotReturned := - liqPath.io.rowMutationControlBlockedByScbNotReturned - io.reducedLoadReplayLiqRowMutationControlBlockedByE4UpdateConflict := - liqPath.io.rowMutationControlBlockedByE4UpdateConflict - io.reducedLoadReplayLiqRowMutationControlBlockedByClearResolvedConflict := - liqPath.io.rowMutationControlBlockedByClearResolvedConflict - io.reducedLoadReplayLiqRowMutationControlBlockedByReplayWakeConflict := - liqPath.io.rowMutationControlBlockedByReplayWakeConflict - io.reducedLoadReplayLiqRowMutationControlBlockedByRefillConflict := - liqPath.io.rowMutationControlBlockedByRefillConflict - io.reducedLoadReplayLiqRowMutationControlBlockedByLaunchConflict := - liqPath.io.rowMutationControlBlockedByLaunchConflict - io.reducedLoadReplayLiqRowMutationControlBlockedByAllocationConflict := - liqPath.io.rowMutationControlBlockedByAllocationConflict - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR381SideEffectLiveControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - live: LoadReplayReturnSideEffectLiveControl, - enable: Bool, - flush: Bool, - liveRequested: Bool, - payloadValid: Bool, - writebackRequired: Bool, - wakeupRequired: Bool): Unit = { - live.io.enable := enable - live.io.flush := flush - live.io.liveRequested := liveRequested - live.io.payloadValid := payloadValid - live.io.writebackRequired := writebackRequired - live.io.wakeupRequired := wakeupRequired - - io.reducedLoadReplayLiqReturnSideEffectLiveCandidateValid := live.io.candidateValid - io.reducedLoadReplayLiqReturnSideEffectLiveRequiredMask := live.io.requiredMask - io.reducedLoadReplayLiqReturnSideEffectLiveEnableMask := live.io.liveEnableMask - io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByDisabled := live.io.blockedByDisabled - io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByFlush := live.io.blockedByFlush - io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByNoPayload := live.io.blockedByNoPayload - io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByLiveDisabled := live.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR489CompleteRepickReturnWiring { - def connect( - allocPath: ReducedLoadReplayLiqAllocPath, - sourceReadiness: LoadReplaySourceReturnReadiness, - consumerReady: LoadReplayReturnConsumerReady, - pipeBudget: LoadReplayReturnPipeBudget, - pipePermit: LoadReplayReturnPipePermit, - pipeSelect: LoadReplayReturnPipeSelect, - returnReadiness: LoadReplayReturnReadiness, - dataExtract: LoadReplayReturnDataExtract, - publishReady: LoadReplayReturnPublishReady, - lretPayload: LoadReplayReturnLretPayload, - enable: Bool, - allowLaunchDirectReturn: Bool, - e2BaseData: UInt, - e2BaseValidMask: UInt, - lretSinkReady: Bool, - wakeupSinkReady: Bool): (Bool, Bool) = { - val returnCompleteValid = allocPath.io.returnCompleteValid - val launchReturnPathValid = - allowLaunchDirectReturn && allocPath.io.launchValid && !returnCompleteValid - val returnPathValid = returnCompleteValid || launchReturnPathValid - val returnPathSourcesReturned = - Mux(returnCompleteValid, true.B, sourceReadiness.io.sourceReturned) - - consumerReady.io.enable := enable - consumerReady.io.launchValid := returnPathValid - consumerReady.io.sourcesReturned := returnPathSourcesReturned - consumerReady.io.specWakeup := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedSpecWakeup, allocPath.io.launchSelectedSpecWakeup) - consumerReady.io.stackValid := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedStackValid, allocPath.io.launchSelectedStackValid) - consumerReady.io.lretSinkReady := lretSinkReady - consumerReady.io.wakeupSinkReady := wakeupSinkReady - - pipeBudget.io.enable := enable - pipeBudget.io.launchValid := returnPathValid - pipeBudget.io.sourcesReturned := returnPathSourcesReturned - pipeBudget.io.pipeBudgetEnable := enable - pipeBudget.io.consumerReady := consumerReady.io.consumerReady - - pipePermit.io.enable := enable - pipePermit.io.launchValid := returnPathValid - pipePermit.io.sourcesReturned := returnPathSourcesReturned - pipePermit.io.pipeBudgetAvailable := pipeBudget.io.pipeBudgetAvailable - - pipeSelect.io.enable := enable - pipeSelect.io.launchValid := returnPathValid - pipeSelect.io.sourcesReturned := returnPathSourcesReturned - pipeSelect.io.pipeAvailableMask := pipePermit.io.pipeAvailableMask - - returnReadiness.io.enable := enable - returnReadiness.io.launchValid := returnPathValid - returnReadiness.io.sourcesReturned := returnPathSourcesReturned - returnReadiness.io.returnPipeAvailable := pipeSelect.io.pipeAvailable - returnReadiness.io.returnPipeIndex := pipeSelect.io.selectedPipeIndex - - dataExtract.io.enable := enable - dataExtract.io.returnValid := returnPathValid && returnPathSourcesReturned - dataExtract.io.lineData := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedLineData, e2BaseData) - dataExtract.io.lineValidMask := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedValidMask, e2BaseValidMask) - dataExtract.io.secondLineData := 0.U - dataExtract.io.secondLineValidMask := 0.U - dataExtract.io.addr := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedAddr, allocPath.io.launchSelectedAddr) - dataExtract.io.size := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedSize, allocPath.io.launchSelectedSize) - dataExtract.io.signExtend := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedReturnSignExtend, allocPath.io.launchSelectedReturnSignExtend) - - publishReady.io.enable := enable - publishReady.io.launchValid := returnPathValid - publishReady.io.dataValid := dataExtract.io.dataValid - publishReady.io.consumerReady := consumerReady.io.consumerReady - - lretPayload.io.enable := enable - lretPayload.io.launchValid := returnPathValid - lretPayload.io.dataValid := dataExtract.io.dataValid - lretPayload.io.selectedBid := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedBid, allocPath.io.launchSelectedBid) - lretPayload.io.selectedGid := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedGid, allocPath.io.launchSelectedGid) - lretPayload.io.selectedRid := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedRid, allocPath.io.launchSelectedRid) - val selectedScopeRow = - Mux( - returnCompleteValid, - allocPath.io.rows(allocPath.io.returnCompleteIndex), - allocPath.io.rows(allocPath.io.launchIndex)) - lretPayload.io.selectedLoadLsId := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedLoadLsId, allocPath.io.launchSelectedLoadLsId) - lretPayload.io.selectedLoadLsIdFullValid := selectedScopeRow.loadLsIdFullValid - lretPayload.io.selectedLoadLsIdFull := selectedScopeRow.loadLsIdFull - lretPayload.io.selectedPeId := selectedScopeRow.peId - lretPayload.io.selectedStid := selectedScopeRow.stid - lretPayload.io.selectedTid := selectedScopeRow.tid - lretPayload.io.selectedPc := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedPc, allocPath.io.launchSelectedPc) - lretPayload.io.selectedAddr := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedAddr, allocPath.io.launchSelectedAddr) - lretPayload.io.selectedSize := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedSize, allocPath.io.launchSelectedSize) - lretPayload.io.selectedDst := Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedDst, allocPath.io.launchSelectedDst) - lretPayload.io.returnData := dataExtract.io.data - lretPayload.io.returnPipeIndex := returnReadiness.io.selectedPipeIndex - lretPayload.io.specWakeup := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedSpecWakeup, allocPath.io.launchSelectedSpecWakeup) - lretPayload.io.stackValid := - Mux(returnCompleteValid, allocPath.io.returnCompleteSelectedStackValid, allocPath.io.launchSelectedStackValid) - - (returnCompleteValid, launchReturnPathValid) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR381ReturnPublishWiring { - def connect( - sideEffectReady: LoadReplayReturnSideEffectReady, - publishControl: LoadReplayReturnPublishControl, - publishRequest: LoadReplayReturnPublishRequest, - lretPayload: LoadReplayReturnLretPayload, - publishReady: LoadReplayReturnPublishReady, - writebackCandidate: LoadReplayReturnWritebackCandidate, - wakeupCandidate: LoadReplayReturnWakeupCandidate, - enable: Bool, - lretSinkReady: Bool, - writebackSinkReady: Bool, - wakeupSinkReady: Bool, - publishLiveEnable: Bool): Unit = { - sideEffectReady.io.enable := enable - sideEffectReady.io.payloadValid := lretPayload.io.payloadValid - sideEffectReady.io.lretSinkReady := lretSinkReady - sideEffectReady.io.writebackRequired := writebackCandidate.io.writeValid - sideEffectReady.io.writebackSinkReady := writebackSinkReady - sideEffectReady.io.wakeupRequired := wakeupCandidate.io.wakeupRequired - sideEffectReady.io.wakeupSinkReady := wakeupSinkReady - - publishControl.io.enable := enable - publishControl.io.liveEnable := publishLiveEnable - publishControl.io.payloadValid := lretPayload.io.payloadValid - publishControl.io.publishReady := publishReady.io.publishReady - publishControl.io.sideEffectsReady := sideEffectReady.io.sideEffectsReady - - publishRequest.io.publishFire := publishControl.io.publishFire - publishRequest.io.payloadValid := lretPayload.io.payloadValid - publishRequest.io.writebackRequired := writebackCandidate.io.writeValid - publishRequest.io.wakeupRequired := wakeupCandidate.io.wakeupRequired - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RequestPayloadWiring { - def connect( - completion: LoadReplayReturnPipeW2CompletionCandidate, - slot: LoadReplayReturnPipeW2Slot, - sideEffectRequest: LoadReplayReturnPipeW2SideEffectRequest, - resolveRequest: LoadReplayReturnPipeW2ResolveRequest, - writebackRequest: LoadReplayReturnPipeW2WritebackRequest, - wakeupRequest: LoadReplayReturnPipeW2WakeupRequest, - payloadPlan: LoadReplayReturnPipeW2SideEffectPayloadPlan, - sideEffectReady: LoadReplayReturnPipeW2SideEffectReady, - completionReadyGate: Bool, - sideEffectLiveControl: LoadReplayReturnPipeW2SideEffectLiveControl, - resolveSink: LoadReplayReturnPipeW2ResolveSinkReady, - writebackSink: LoadReplayReturnPipeW2WritebackSinkReady, - wakeupSink: LoadReplayReturnPipeW2WakeupSinkReady, - sideEffectLiveRequested: Bool, - resolveSinkReady: Bool, - writebackSinkReady: Bool, - enable: Bool, - flush: Bool): Unit = { - completion.io.enable := enable - completion.io.flush := flush - completion.io.sideEffectsReady := sideEffectReady.io.sideEffectsReady && completionReadyGate - completion.io.slotOccupied := slot.io.occupied - completion.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - completion.io.slotTargetIsLda := slot.io.entryTargetIsLda - completion.io.slotPipeIndex := slot.io.entryPipeIndex - completion.io.slotDst := slot.io.entryDst - completion.io.slotData := slot.io.entryData - completion.io.slotWakeupRequired := slot.io.entryWakeupRequired - - sideEffectRequest.io.sideEffectCandidateValid := completion.io.resolveRequired - sideEffectRequest.io.completeValid := completion.io.completeValid - sideEffectRequest.io.resolveValid := completion.io.resolveValid - sideEffectRequest.io.writebackValid := completion.io.writebackValid - sideEffectRequest.io.wakeupValid := completion.io.wakeupValid - - resolveRequest.io.resolveRequest := sideEffectRequest.io.resolveRequest - resolveRequest.io.slotOccupied := slot.io.occupied - resolveRequest.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - resolveRequest.io.slotTargetIsLda := slot.io.entryTargetIsLda - resolveRequest.io.slotPipeIndex := slot.io.entryPipeIndex - resolveRequest.io.slotBid := slot.io.entryBid - resolveRequest.io.slotGid := slot.io.entryGid - resolveRequest.io.slotRid := slot.io.entryRid - resolveRequest.io.slotLoadLsId := slot.io.entryLoadLsId - resolveRequest.io.slotPc := slot.io.entryPc - resolveRequest.io.slotAddr := slot.io.entryAddr - resolveRequest.io.slotSize := slot.io.entrySize - resolveRequest.io.slotDst := slot.io.entryDst - resolveRequest.io.slotData := slot.io.entryData - - writebackRequest.io.writebackRequest := sideEffectRequest.io.writebackRequest - writebackRequest.io.slotOccupied := slot.io.occupied - writebackRequest.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - writebackRequest.io.slotTargetIsLda := slot.io.entryTargetIsLda - writebackRequest.io.slotPipeIndex := slot.io.entryPipeIndex - writebackRequest.io.slotBid := slot.io.entryBid - writebackRequest.io.slotGid := slot.io.entryGid - writebackRequest.io.slotRid := slot.io.entryRid - writebackRequest.io.slotLoadLsId := slot.io.entryLoadLsId - writebackRequest.io.slotPc := slot.io.entryPc - writebackRequest.io.slotDst := slot.io.entryDst - writebackRequest.io.slotData := slot.io.entryData - - wakeupRequest.io.wakeupRequest := sideEffectRequest.io.wakeupRequest - wakeupRequest.io.slotOccupied := slot.io.occupied - wakeupRequest.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - wakeupRequest.io.slotTargetIsLda := slot.io.entryTargetIsLda - wakeupRequest.io.slotPipeIndex := slot.io.entryPipeIndex - wakeupRequest.io.slotBid := slot.io.entryBid - wakeupRequest.io.slotGid := slot.io.entryGid - wakeupRequest.io.slotRid := slot.io.entryRid - wakeupRequest.io.slotLoadLsId := slot.io.entryLoadLsId - wakeupRequest.io.slotPc := slot.io.entryPc - wakeupRequest.io.slotDst := slot.io.entryDst - wakeupRequest.io.slotWakeupRequired := slot.io.entryWakeupRequired - - payloadPlan.io.enable := enable - payloadPlan.io.flush := flush - payloadPlan.io.sideEffectCandidateValid := completion.io.resolveRequired - payloadPlan.io.requestValid := sideEffectRequest.io.requestValid - payloadPlan.io.resolveRequired := completion.io.resolveRequired - payloadPlan.io.writebackRequired := completion.io.writebackRequired - payloadPlan.io.wakeupRequired := completion.io.wakeupRequired - payloadPlan.io.resolveRequest := sideEffectRequest.io.resolveRequest - payloadPlan.io.writebackRequest := sideEffectRequest.io.writebackRequest - payloadPlan.io.wakeupRequest := sideEffectRequest.io.wakeupRequest - payloadPlan.io.resolvePayloadValid := resolveRequest.io.resolveValid - payloadPlan.io.writebackPayloadValid := writebackRequest.io.writebackValid - payloadPlan.io.wakeupPayloadValid := wakeupRequest.io.wakeupValid - - sideEffectReady.io.enable := enable - sideEffectReady.io.candidateValid := completion.io.resolveRequired - sideEffectReady.io.resolveRequired := completion.io.resolveRequired - sideEffectReady.io.resolveSinkReady := resolveSink.io.resolveSinkReady - sideEffectReady.io.writebackRequired := completion.io.writebackRequired - sideEffectReady.io.writebackSinkReady := writebackSink.io.writebackSinkReady - sideEffectReady.io.wakeupRequired := completion.io.wakeupRequired - sideEffectReady.io.wakeupSinkReady := wakeupSink.io.wakeupSinkReady - - sideEffectLiveControl.io.enable := enable - sideEffectLiveControl.io.flush := flush - sideEffectLiveControl.io.liveRequested := sideEffectLiveRequested - sideEffectLiveControl.io.sideEffectCandidateValid := completion.io.resolveRequired - sideEffectLiveControl.io.resolveRequired := completion.io.resolveRequired - sideEffectLiveControl.io.writebackRequired := completion.io.writebackRequired - sideEffectLiveControl.io.wakeupRequired := completion.io.wakeupRequired - - resolveSink.io.enable := enable - resolveSink.io.flush := flush - resolveSink.io.liveEnable := sideEffectLiveControl.io.resolveLiveEnable - resolveSink.io.resolveRequired := completion.io.resolveRequired - resolveSink.io.sinkReady := resolveSinkReady - - writebackSink.io.enable := enable - writebackSink.io.flush := flush - writebackSink.io.liveEnable := sideEffectLiveControl.io.writebackLiveEnable - writebackSink.io.writebackRequired := completion.io.writebackRequired - writebackSink.io.sinkReady := writebackSinkReady - - wakeupSink.io.enable := enable - wakeupSink.io.flush := flush - wakeupSink.io.liveEnable := sideEffectLiveControl.io.wakeupLiveEnable - wakeupSink.io.wakeupRequired := completion.io.wakeupRequired - wakeupSink.io.sinkReady := true.B - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2CompletionPermitWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - completionPermit: LoadReplayReturnPipeW2SideEffectCompletionPermit, - completion: LoadReplayReturnPipeW2CompletionCandidate, - readyJoin: LoadReplayReturnPipeW2SideEffectReady, - resolveSink: LoadReplayReturnPipeW2ResolveSinkReady, - writebackSink: LoadReplayReturnPipeW2WritebackSinkReady, - wakeupSink: LoadReplayReturnPipeW2WakeupSinkReady, - enable: Bool, - flush: Bool): Unit = { - completionPermit.io.enable := enable - completionPermit.io.flush := flush - completionPermit.io.sideEffectCandidateValid := completion.io.resolveRequired - completionPermit.io.resolveRequired := completion.io.resolveRequired - completionPermit.io.writebackRequired := completion.io.writebackRequired - completionPermit.io.wakeupRequired := completion.io.wakeupRequired - completionPermit.io.resolveSinkReady := resolveSink.io.resolveSinkReady - completionPermit.io.writebackSinkReady := writebackSink.io.writebackSinkReady - completionPermit.io.wakeupSinkReady := wakeupSink.io.wakeupSinkReady - completionPermit.io.readyJoinSideEffectsReady := readyJoin.io.sideEffectsReady - - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitCandidateValid := - completionPermit.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitRequiredMask := - completionPermit.io.requiredMask - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitMissingReadyMask := - completionPermit.io.missingReadyMask - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitPermitted := - completionPermit.io.completionPermitted - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitMatchesReadyJoin := - completionPermit.io.matchesReadyJoin - io.reducedLoadReplayLiqLretPipeW2SideEffectCompletionPermitBlocked := - completionPermit.io.blockedByDisabled || - completionPermit.io.blockedByFlush || - completionPermit.io.blockedByNoCandidate || - completionPermit.io.blockedByNoRequiredSink || - completionPermit.io.blockedByResolveSink || - completionPermit.io.blockedByWritebackSink || - completionPermit.io.blockedByWakeupSink || - completionPermit.io.blockedByReadyJoinMismatch - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2IssuePermitWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - issuePermit: LoadReplayReturnPipeW2SideEffectIssuePermit, - payloadPlan: LoadReplayReturnPipeW2SideEffectPayloadPlan, - resolveSink: LoadReplayReturnPipeW2ResolveSinkReady, - writebackSink: LoadReplayReturnPipeW2WritebackSinkReady, - wakeupSink: LoadReplayReturnPipeW2WakeupSinkReady, - enable: Bool, - flush: Bool): Unit = { - issuePermit.io.enable := enable - issuePermit.io.flush := flush - issuePermit.io.payloadPlanIssueValid := payloadPlan.io.issueValid - issuePermit.io.requiredMask := payloadPlan.io.requiredMask - issuePermit.io.resolveSinkReady := resolveSink.io.resolveSinkReady - issuePermit.io.writebackSinkReady := writebackSink.io.writebackSinkReady - issuePermit.io.wakeupSinkReady := wakeupSink.io.wakeupSinkReady - - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitCandidateValid := - issuePermit.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitSinkReadyMask := - issuePermit.io.sinkReadyMask - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitMissingReadyMask := - issuePermit.io.missingReadyMask - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAcceptedMask := - issuePermit.io.acceptedMask - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAllSinksReady := - issuePermit.io.allRequiredSinksReady - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitAccepted := - issuePermit.io.issueAccepted - io.reducedLoadReplayLiqLretPipeW2SideEffectIssuePermitBlocked := - issuePermit.io.blockedByDisabled || - issuePermit.io.blockedByFlush || - issuePermit.io.blockedByNoPlan || - issuePermit.io.blockedByNoRequiredSink || - issuePermit.io.blockedByResolveSink || - issuePermit.io.blockedByWritebackSink || - issuePermit.io.blockedByWakeupSink - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2FireVectorWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - fireVector: LoadReplayReturnPipeW2SideEffectFireVector, - issuePermit: LoadReplayReturnPipeW2SideEffectIssuePermit, - payloadPlan: LoadReplayReturnPipeW2SideEffectPayloadPlan, - enable: Bool, - flush: Bool): Unit = { - fireVector.io.enable := enable - fireVector.io.flush := flush - fireVector.io.issueAccepted := issuePermit.io.issueAccepted - fireVector.io.acceptedMask := issuePermit.io.acceptedMask - fireVector.io.requestMask := payloadPlan.io.requestMask - fireVector.io.payloadValidMask := payloadPlan.io.payloadValidMask - - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorCandidateValid := - fireVector.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorFireValid := - fireVector.io.fireValid - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorFireMask := - fireVector.io.fireMask - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorResolveFire := - fireVector.io.resolveFire - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorWritebackFire := - fireVector.io.writebackFire - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorWakeupFire := - fireVector.io.wakeupFire - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorRequestMatchesAccepted := - fireVector.io.requestMatchesAccepted - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorPayloadMatchesAccepted := - fireVector.io.payloadMatchesAccepted - io.reducedLoadReplayLiqLretPipeW2SideEffectFireVectorBlocked := - fireVector.io.blockedByDisabled || - fireVector.io.blockedByFlush || - fireVector.io.blockedByNoIssueAccept || - fireVector.io.blockedByNoAcceptedSink || - fireVector.io.blockedByRequestMismatch || - fireVector.io.blockedByPayloadMismatch || - fireVector.io.invalidAcceptedWithoutRequest || - fireVector.io.invalidAcceptedWithoutPayload - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ResolveFirePayloadModule { - def create(p: InterfaceParams): LoadReplayReturnPipeW2ResolveFirePayload = - Module(new LoadReplayReturnPipeW2ResolveFirePayload( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - sizeWidth = p.memSizeWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ResolveFirePayloadWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - firePayload: LoadReplayReturnPipeW2ResolveFirePayload, - fireVector: LoadReplayReturnPipeW2SideEffectFireVector, - resolveRequest: LoadReplayReturnPipeW2ResolveRequest, - enable: Bool, - flush: Bool): Unit = { - firePayload.io.enable := enable - firePayload.io.flush := flush - firePayload.io.resolveFire := fireVector.io.resolveFire - firePayload.io.resolvePayloadValid := resolveRequest.io.resolveValid - firePayload.io.resolveComplete := resolveRequest.io.isComplete - firePayload.io.resolveTargetIsAgu := resolveRequest.io.targetIsAgu - firePayload.io.resolveTargetIsLda := resolveRequest.io.targetIsLda - firePayload.io.resolveTargetPipeIndex := resolveRequest.io.targetPipeIndex - firePayload.io.resolveBid := resolveRequest.io.resolveBid - firePayload.io.resolveGid := resolveRequest.io.resolveGid - firePayload.io.resolveRid := resolveRequest.io.resolveRid - firePayload.io.resolveLoadLsId := resolveRequest.io.resolveLoadLsId - firePayload.io.resolvePc := resolveRequest.io.resolvePc - firePayload.io.resolveAddr := resolveRequest.io.resolveAddr - firePayload.io.resolveSize := resolveRequest.io.resolveSize - firePayload.io.resolveDst := resolveRequest.io.resolveDst - firePayload.io.resolveData := resolveRequest.io.resolveData - - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadCandidateValid := - firePayload.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPayloadValid := - firePayload.io.payloadValid - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadFireValid := - firePayload.io.fireValid - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsAgu := - firePayload.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsLda := - firePayload.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPipeIndex := - firePayload.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValid := - firePayload.io.fireBid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidWrap := - firePayload.io.fireBid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValue := - firePayload.io.fireBid.value - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValid := - firePayload.io.fireRid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidWrap := - firePayload.io.fireRid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValue := - firePayload.io.fireRid.value - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBlocked := - firePayload.io.blockedByDisabled || - firePayload.io.blockedByFlush || - firePayload.io.blockedByNoFire || - firePayload.io.blockedByNoPayload || - firePayload.io.blockedByIncomplete || - firePayload.io.blockedByInvalidTarget || - firePayload.io.blockedByInvalidIdentity - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidFireWithoutPayload := - firePayload.io.invalidFireWithoutPayload - io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidPayloadWithoutFire := - firePayload.io.invalidPayloadWithoutFire - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ResolveArbiterInputWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - arbiterInput: LoadReplayReturnPipeW2ResolveArbiterInput, - firePayload: LoadReplayReturnPipeW2ResolveFirePayload, - liveEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - arbiterInput.io.enable := enable - arbiterInput.io.flush := flush - arbiterInput.io.liveEnable := liveEnable - arbiterInput.io.firePayloadValid := firePayload.io.fireValid - arbiterInput.io.fireTargetIsAgu := firePayload.io.targetIsAgu - arbiterInput.io.fireTargetIsLda := firePayload.io.targetIsLda - arbiterInput.io.fireTargetPipeIndex := firePayload.io.targetPipeIndex - arbiterInput.io.fireBid := firePayload.io.fireBid - arbiterInput.io.fireGid := firePayload.io.fireGid - arbiterInput.io.fireRid := firePayload.io.fireRid - arbiterInput.io.fireLoadLsId := firePayload.io.fireLoadLsId - arbiterInput.io.firePc := firePayload.io.firePc - arbiterInput.io.fireAddr := firePayload.io.fireAddr - arbiterInput.io.fireSize := firePayload.io.fireSize - arbiterInput.io.fireDst := firePayload.io.fireDst - arbiterInput.io.fireData := firePayload.io.fireData - - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputCandidateValid := - arbiterInput.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputResolveValid := - arbiterInput.io.resolveValid - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputTargetIsAgu := - arbiterInput.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputTargetIsLda := - arbiterInput.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidValid := - arbiterInput.io.resolveBid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidWrap := - arbiterInput.io.resolveBid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBidValue := - arbiterInput.io.resolveBid.value - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidValid := - arbiterInput.io.resolveRid.valid - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidWrap := - arbiterInput.io.resolveRid.wrap - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidValue := - arbiterInput.io.resolveRid.value - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBlocked := - arbiterInput.io.blockedByDisabled || - arbiterInput.io.blockedByFlush || - arbiterInput.io.blockedByNoPayload || - arbiterInput.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputBlockedByLiveDisabled := - arbiterInput.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WritebackFirePayloadModule { - def create(p: InterfaceParams): LoadReplayReturnPipeW2WritebackFirePayload = - Module(new LoadReplayReturnPipeW2WritebackFirePayload( - idEntries = p.robEntries, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WritebackFirePayloadWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - firePayload: LoadReplayReturnPipeW2WritebackFirePayload, - fireVector: LoadReplayReturnPipeW2SideEffectFireVector, - writebackRequest: LoadReplayReturnPipeW2WritebackRequest, - enable: Bool, - flush: Bool): Unit = { - firePayload.io.enable := enable - firePayload.io.flush := flush - firePayload.io.writebackFire := fireVector.io.writebackFire - firePayload.io.writebackPayloadValid := writebackRequest.io.writebackValid - firePayload.io.writebackTargetValid := writebackRequest.io.targetValid - firePayload.io.writebackIdentityValid := writebackRequest.io.identityValid - firePayload.io.writebackDestinationValid := writebackRequest.io.destinationValid - firePayload.io.writebackGprDestination := writebackRequest.io.gprDestination - firePayload.io.writebackTargetIsAgu := writebackRequest.io.targetIsAgu - firePayload.io.writebackTargetIsLda := writebackRequest.io.targetIsLda - firePayload.io.writebackTargetPipeIndex := writebackRequest.io.targetPipeIndex - firePayload.io.writebackBid := writebackRequest.io.writebackBid - firePayload.io.writebackGid := writebackRequest.io.writebackGid - firePayload.io.writebackRid := writebackRequest.io.writebackRid - firePayload.io.writebackLoadLsId := writebackRequest.io.writebackLoadLsId - firePayload.io.writebackPc := writebackRequest.io.writebackPc - firePayload.io.writebackKind := writebackRequest.io.writebackKind - firePayload.io.writebackArchTag := writebackRequest.io.writebackArchTag - firePayload.io.writebackRelTag := writebackRequest.io.writebackRelTag - firePayload.io.writebackPhysTag := writebackRequest.io.writebackPhysTag - firePayload.io.writebackOldPhysTag := writebackRequest.io.writebackOldPhysTag - firePayload.io.writebackData := writebackRequest.io.writebackData - - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadCandidateValid := - firePayload.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPayloadValid := - firePayload.io.payloadValid - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadFireValid := - firePayload.io.fireValid - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsAgu := - firePayload.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsLda := - firePayload.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPipeIndex := - firePayload.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValid := - firePayload.io.fireBid.valid - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidWrap := - firePayload.io.fireBid.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValue := - firePayload.io.fireBid.value - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValid := - firePayload.io.fireRid.valid - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidWrap := - firePayload.io.fireRid.wrap - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValue := - firePayload.io.fireRid.value - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadDstPhysTag := - firePayload.io.firePhysTag - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadData := - firePayload.io.fireData - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBlocked := - firePayload.io.blockedByDisabled || - firePayload.io.blockedByFlush || - firePayload.io.blockedByNoFire || - firePayload.io.blockedByNoPayload || - firePayload.io.blockedByInvalidTarget || - firePayload.io.blockedByInvalidIdentity || - firePayload.io.blockedByNoDestination || - firePayload.io.blockedByNonGprDestination - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidFireWithoutPayload := - firePayload.io.invalidFireWithoutPayload - io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidPayloadWithoutFire := - firePayload.io.invalidPayloadWithoutFire - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WritebackArbiterInputWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - arbiterInput: LoadReplayReturnPipeW2WritebackArbiterInput, - firePayload: LoadReplayReturnPipeW2WritebackFirePayload, - liveEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - arbiterInput.io.enable := enable - arbiterInput.io.flush := flush - arbiterInput.io.liveEnable := liveEnable - arbiterInput.io.firePayloadValid := firePayload.io.fireValid - arbiterInput.io.firePhysTag := firePayload.io.firePhysTag - arbiterInput.io.fireData := firePayload.io.fireData - - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputCandidateValid := - arbiterInput.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteValid := - arbiterInput.io.writeValid - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteTag := - arbiterInput.io.writeTag - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputWriteData := - arbiterInput.io.writeData - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputBlocked := - arbiterInput.io.blockedByDisabled || - arbiterInput.io.blockedByFlush || - arbiterInput.io.blockedByNoPayload || - arbiterInput.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2WritebackArbiterInputBlockedByLiveDisabled := - arbiterInput.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WakeupFirePayloadModule { - def create(p: InterfaceParams): LoadReplayReturnPipeW2WakeupFirePayload = - Module(new LoadReplayReturnPipeW2WakeupFirePayload( - idEntries = p.robEntries, - pcWidth = p.pcWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WakeupFirePayloadWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - firePayload: LoadReplayReturnPipeW2WakeupFirePayload, - fireVector: LoadReplayReturnPipeW2SideEffectFireVector, - wakeupRequest: LoadReplayReturnPipeW2WakeupRequest, - enable: Bool, - flush: Bool): Unit = { - firePayload.io.enable := enable - firePayload.io.flush := flush - firePayload.io.wakeupFire := fireVector.io.wakeupFire - firePayload.io.wakeupPayloadValid := wakeupRequest.io.wakeupValid - firePayload.io.wakeupTargetValid := wakeupRequest.io.targetValid - firePayload.io.wakeupIdentityValid := wakeupRequest.io.identityValid - firePayload.io.wakeupRequired := wakeupRequest.io.wakeupRequired - firePayload.io.wakeupDestinationValid := wakeupRequest.io.destinationValid - firePayload.io.wakeupReducedGpr := wakeupRequest.io.reducedGprWakeupValid - firePayload.io.wakeupNonGpr := wakeupRequest.io.nonGprWakeup - firePayload.io.wakeupTargetIsAgu := wakeupRequest.io.targetIsAgu - firePayload.io.wakeupTargetIsLda := wakeupRequest.io.targetIsLda - firePayload.io.wakeupTargetPipeIndex := wakeupRequest.io.targetPipeIndex - firePayload.io.wakeupBid := wakeupRequest.io.wakeupBid - firePayload.io.wakeupGid := wakeupRequest.io.wakeupGid - firePayload.io.wakeupRid := wakeupRequest.io.wakeupRid - firePayload.io.wakeupLoadLsId := wakeupRequest.io.wakeupLoadLsId - firePayload.io.wakeupPc := wakeupRequest.io.wakeupPc - firePayload.io.wakeupKind := wakeupRequest.io.wakeupKind - firePayload.io.wakeupArchTag := wakeupRequest.io.wakeupArchTag - firePayload.io.wakeupRelTag := wakeupRequest.io.wakeupRelTag - firePayload.io.wakeupPhysTag := wakeupRequest.io.wakeupPhysTag - firePayload.io.wakeupOldPhysTag := wakeupRequest.io.wakeupOldPhysTag - - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadCandidateValid := - firePayload.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPayloadValid := - firePayload.io.payloadValid - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadFireValid := - firePayload.io.fireValid - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsAgu := - firePayload.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsLda := - firePayload.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPipeIndex := - firePayload.io.targetPipeIndex - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValid := - firePayload.io.fireBid.valid - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidWrap := - firePayload.io.fireBid.wrap - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValue := - firePayload.io.fireBid.value - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValid := - firePayload.io.fireRid.valid - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidWrap := - firePayload.io.fireRid.wrap - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValue := - firePayload.io.fireRid.value - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstKind := - firePayload.io.fireKind - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstPhysTag := - firePayload.io.firePhysTag - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadReducedGprWakeup := - firePayload.io.reducedGprWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadNonGprWakeup := - firePayload.io.nonGprWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBlocked := - firePayload.io.blockedByDisabled || - firePayload.io.blockedByFlush || - firePayload.io.blockedByNoFire || - firePayload.io.blockedByNoPayload || - firePayload.io.blockedByInvalidTarget || - firePayload.io.blockedByInvalidIdentity || - firePayload.io.blockedByWakeupNotRequired || - firePayload.io.blockedByNoDestination - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidFireWithoutPayload := - firePayload.io.invalidFireWithoutPayload - io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidPayloadWithoutFire := - firePayload.io.invalidPayloadWithoutFire - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2WakeupArbiterInputWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - arbiterInput: LoadReplayReturnPipeW2WakeupArbiterInput, - firePayload: LoadReplayReturnPipeW2WakeupFirePayload, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - retainedFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - liveEnable: Bool, - retainedFallbackLiveProbe: Bool, - suppressPhysicalReplay: Bool, - enable: Bool, - flush: Bool): Unit = { - arbiterInput.io.enable := enable - arbiterInput.io.flush := flush - arbiterInput.io.liveEnable := Mux(retainedFallbackLiveProbe, true.B, liveEnable && !suppressPhysicalReplay) - arbiterInput.io.firePayloadValid := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackWakeupValid, firePayload.io.fireValid && !suppressPhysicalReplay) - arbiterInput.io.fireReducedGprWakeup := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackReducedGprWakeup, firePayload.io.reducedGprWakeup) - arbiterInput.io.fireNonGprWakeup := Mux(retainedFallbackLiveProbe, false.B, firePayload.io.nonGprWakeup) - arbiterInput.io.fireTargetIsAgu := Mux(retainedFallbackLiveProbe, false.B, firePayload.io.targetIsAgu) - arbiterInput.io.fireTargetIsLda := Mux(retainedFallbackLiveProbe, true.B, firePayload.io.targetIsLda) - arbiterInput.io.fireTargetPipeIndex := Mux(retainedFallbackLiveProbe, 0.U, firePayload.io.targetPipeIndex) - arbiterInput.io.fireBid := Mux(retainedFallbackLiveProbe, retireRecord.io.record.bid, firePayload.io.fireBid) - arbiterInput.io.fireGid := Mux(retainedFallbackLiveProbe, retireRecord.io.record.gid, firePayload.io.fireGid) - arbiterInput.io.fireRid := Mux(retainedFallbackLiveProbe, retireRecord.io.record.rid, firePayload.io.fireRid) - arbiterInput.io.fireLoadLsId := - Mux(retainedFallbackLiveProbe, retireRecord.io.record.loadLsId, firePayload.io.fireLoadLsId) - arbiterInput.io.firePc := Mux(retainedFallbackLiveProbe, retireRecord.io.record.pc, firePayload.io.firePc) - arbiterInput.io.fireKind := - Mux(retainedFallbackLiveProbe, retireRecord.io.record.dst.kind, firePayload.io.fireKind) - arbiterInput.io.fireArchTag := - Mux(retainedFallbackLiveProbe, retireRecord.io.record.dst.archTag, firePayload.io.fireArchTag) - arbiterInput.io.fireRelTag := - Mux(retainedFallbackLiveProbe, retireRecord.io.record.dst.relTag, firePayload.io.fireRelTag) - arbiterInput.io.firePhysTag := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackWakeupTag, firePayload.io.firePhysTag) - arbiterInput.io.fireOldPhysTag := - Mux(retainedFallbackLiveProbe, retireRecord.io.record.dst.oldPhysTag, firePayload.io.fireOldPhysTag) - - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputCandidateValid := - arbiterInput.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputWakeupValid := - arbiterInput.io.wakeupValid - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputTargetIsAgu := - arbiterInput.io.targetIsAgu - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputTargetIsLda := - arbiterInput.io.targetIsLda - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidValid := - arbiterInput.io.wakeupBid.valid - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidWrap := - arbiterInput.io.wakeupBid.wrap - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBidValue := - arbiterInput.io.wakeupBid.value - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidValid := - arbiterInput.io.wakeupRid.valid - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidWrap := - arbiterInput.io.wakeupRid.wrap - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputRidValue := - arbiterInput.io.wakeupRid.value - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputDstKind := - arbiterInput.io.wakeupKind - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputDstPhysTag := - arbiterInput.io.wakeupPhysTag - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputReducedGprWakeup := - arbiterInput.io.reducedGprWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputNonGprWakeup := - arbiterInput.io.nonGprWakeup - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBlocked := - arbiterInput.io.blockedByDisabled || - arbiterInput.io.blockedByFlush || - arbiterInput.io.blockedByNoPayload || - arbiterInput.io.blockedByLiveDisabled - io.reducedLoadReplayLiqLretPipeW2WakeupArbiterInputBlockedByLiveDisabled := - arbiterInput.io.blockedByLiveDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2FireCompleteWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - fireComplete: LoadReplayReturnPipeW2SideEffectFireComplete, - fireVector: LoadReplayReturnPipeW2SideEffectFireVector, - resolveFirePayload: LoadReplayReturnPipeW2ResolveFirePayload, - writebackFirePayload: LoadReplayReturnPipeW2WritebackFirePayload, - wakeupFirePayload: LoadReplayReturnPipeW2WakeupFirePayload, - enable: Bool, - flush: Bool): Unit = { - fireComplete.io.enable := enable - fireComplete.io.flush := flush - fireComplete.io.fireVectorValid := fireVector.io.fireValid - fireComplete.io.fireMask := fireVector.io.fireMask - fireComplete.io.resolveFirePayloadValid := resolveFirePayload.io.fireValid - fireComplete.io.writebackFirePayloadValid := writebackFirePayload.io.fireValid - fireComplete.io.wakeupFirePayloadValid := wakeupFirePayload.io.fireValid - - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteCandidateValid := - fireComplete.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireMask := - fireComplete.io.observedFireMask - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadFireMask := - fireComplete.io.payloadFireMask - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteMissingPayloadFireMask := - fireComplete.io.missingPayloadFireMask - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteUnexpectedPayloadFireMask := - fireComplete.io.unexpectedPayloadFireMask - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadMatchesFire := - fireComplete.io.payloadMatchesFire - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete := - fireComplete.io.fireComplete - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFutureClearEligible := - fireComplete.io.futureClearEligible - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteBlocked := - fireComplete.io.blockedByDisabled || - fireComplete.io.blockedByFlush || - fireComplete.io.blockedByNoFireVector || - fireComplete.io.blockedByNoFireSink || - fireComplete.io.blockedByPayloadMismatch || - fireComplete.io.invalidFireWithoutPayload || - fireComplete.io.invalidPayloadWithoutFire - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidFireWithoutPayload := - fireComplete.io.invalidFireWithoutPayload - io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidPayloadWithoutFire := - fireComplete.io.invalidPayloadWithoutFire - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ClearIntentWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - slot: LoadReplayReturnPipeW2Slot, - completion: LoadReplayReturnPipeW2CompletionCandidate, - completionPermit: LoadReplayReturnPipeW2SideEffectCompletionPermit, - fireComplete: LoadReplayReturnPipeW2SideEffectFireComplete, - liveClearEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - clearIntent.io.enable := enable - clearIntent.io.flush := flush - clearIntent.io.slotOccupied := slot.io.occupied - clearIntent.io.completionClearSlot := completion.io.clearSlot - clearIntent.io.completionPermitted := completionPermit.io.completionPermitted - clearIntent.io.fireComplete := fireComplete.io.futureClearEligible - clearIntent.io.liveClearEnable := liveClearEnable - - io.reducedLoadReplayLiqLretPipeW2ClearIntentCandidateValid := - clearIntent.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ClearIntentPreClearEligible := - clearIntent.io.preClearEligible - io.reducedLoadReplayLiqLretPipeW2ClearIntentPermitEligible := - clearIntent.io.permitEligible - io.reducedLoadReplayLiqLretPipeW2ClearIntentPostFireEligible := - clearIntent.io.postFireEligible - io.reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent := - clearIntent.io.clearIntent - io.reducedLoadReplayLiqLretPipeW2ClearIntentLiveClear := - clearIntent.io.liveClear - io.reducedLoadReplayLiqLretPipeW2ClearIntentBlocked := - clearIntent.io.blockedByDisabled || - clearIntent.io.blockedByFlush || - clearIntent.io.blockedByNoSlot || - clearIntent.io.blockedByCompletionClear || - clearIntent.io.blockedByCompletionPermit || - clearIntent.io.blockedByFireComplete || - clearIntent.io.blockedByLiveClearDisabled || - clearIntent.io.blockedByCompletionPermitMismatch || - clearIntent.io.blockedByFireCompleteMismatch || - clearIntent.io.invalidEvidenceWithoutSlot - io.reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedPermit := - clearIntent.io.blockedByCompletionPermitMismatch - io.reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedFireComplete := - clearIntent.io.blockedByFireCompleteMismatch - io.reducedLoadReplayLiqLretPipeW2ClearIntentInvalidEvidenceWithoutSlot := - clearIntent.io.invalidEvidenceWithoutSlot - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2PostLretEnqueueHoldWiring { - def connect( - hold: LoadReplayReturnPipeW2PostLretEnqueueHold, - slot: LoadReplayReturnPipeW2Slot, - completion: LoadReplayReturnPipeW2CompletionCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - sink: ScalarLSULoadReturnQueueBank, - enable: Bool, - flush: Bool): Unit = { - hold.io.enable := enable - hold.io.flush := flush - hold.io.slotOccupied := slot.io.occupied - hold.io.completionClearSlot := completion.io.clearSlot - hold.io.liveClear := clearIntent.io.liveClear - hold.io.lretEnqueueAccepted := sink.io.enqueueAccepted - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - slot: LoadReplayReturnPipeW2Slot, - completion: LoadReplayReturnPipeW2CompletionCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - sink: ScalarLSULoadReturnQueueBank, - sinkEntry: LoadReplayReturnLretEntry, - enable: Bool, - flush: Bool): Unit = { - retireRecord.io.enable := enable - retireRecord.io.flush := flush - retireRecord.io.slotOccupied := slot.io.occupied - retireRecord.io.completionClearSlot := completion.io.clearSlot - retireRecord.io.clearIntent := clearIntent.io.clearIntent - retireRecord.io.liveClear := clearIntent.io.liveClear - retireRecord.io.lretEnqueueAccepted := sink.io.enqueueAccepted - val retirePayload = Wire(chiselTypeOf(sinkEntry)) - retirePayload := sinkEntry - retirePayload.valid := slot.io.entryValid - retirePayload.bid := slot.io.entryBid - retirePayload.gid := slot.io.entryGid - retirePayload.rid := slot.io.entryRid - retirePayload.loadLsId := slot.io.entryLoadLsId - retirePayload.pc := slot.io.entryPc - retirePayload.addr := slot.io.entryAddr - retirePayload.size := slot.io.entrySize - retirePayload.dst := slot.io.entryDst - retirePayload.sourceTraceValid := slot.io.entrySourceTraceValid - retirePayload.source0 := slot.io.entrySource0 - retirePayload.source1 := slot.io.entrySource1 - retirePayload.data := slot.io.entryData - retirePayload.pipeIndex := slot.io.entryPipeIndex - retirePayload.specWakeup := !slot.io.entryWakeupRequired - retirePayload.stackValid := false.B - retireRecord.io.retirePayload := retirePayload - - io.reducedLoadReplayLiqLretPipeW2RetireRecordCaptureCandidate := - retireRecord.io.captureCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPayloadValid := - retireRecord.io.payloadValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordCaptureValid := - retireRecord.io.captureValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordCaptureReady := - retireRecord.io.captureReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordCaptureAccepted := - retireRecord.io.captureAccepted - io.reducedLoadReplayLiqLretPipeW2RetireRecordCaptureDropped := - retireRecord.io.captureDropped - io.reducedLoadReplayLiqLretPipeW2RetireRecordRecordValid := - retireRecord.io.recordValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordRecordFire := - retireRecord.io.recordFire - io.reducedLoadReplayLiqLretPipeW2RetireRecordPending := - retireRecord.io.pending - io.reducedLoadReplayLiqLretPipeW2RetireRecordCapturedWithLretEnqueue := - retireRecord.io.capturedWithLretEnqueue - io.reducedLoadReplayLiqLretPipeW2RetireRecordRecordFromLretEnqueue := - retireRecord.io.recordFromLretEnqueue - io.reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByInvalidPayload := - retireRecord.io.blockedByInvalidPayload - io.reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByFull := - retireRecord.io.blockedByFull - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleEvidenceWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - evidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - physicalLifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - enable: Bool, - flush: Bool): Unit = { - evidence.io.enable := enable - evidence.io.flush := flush - evidence.io.captureAccepted := retireRecord.io.captureAccepted - evidence.io.captureLifecycleRowClearReady := physicalLifecycle.io.rowClearReady - evidence.io.captureRowClearIndex := physicalLifecycle.io.rowClearIndex - evidence.io.recordValid := retireRecord.io.recordValid - evidence.io.recordFire := retireRecord.io.recordFire - retireRecord.io.recordReady := evidence.io.providerRowClearReady - - io.reducedLoadReplayLiqLretPipeW2RetireRecordRecordReady := - evidence.io.providerRowClearReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleCandidateValid := - retireRecord.io.recordValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleSlotIdentityValid := - retireRecord.io.recordValid && - retireRecord.io.record.bid.valid && - retireRecord.io.record.gid.valid && - retireRecord.io.record.rid.valid && - retireRecord.io.record.loadLsId.valid - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleResolvedRowMatch := - evidence.io.providerValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRowClearReady := - evidence.io.providerRowClearReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByNoResolvedRow := - evidence.io.recordValidWithoutProvider - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByMultipleResolvedRows := - false.B - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByLifecycleClearDisabled := - evidence.io.providerRowClearReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureIntent := - evidence.io.captureIntent - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureFromLifecycle := - evidence.io.captureFromLifecycle - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureBlockedByNoLifecycle := - evidence.io.captureBlockedByNoLifecycle - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceClearAccepted := - evidence.io.clearAccepted - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValid := - evidence.io.providerValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValidWithoutRecord := - evidence.io.providerValidWithoutRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceRecordValidWithoutProvider := - evidence.io.recordValidWithoutProvider - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleClearFallbackWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - guard: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - evidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - physicalLifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - clearRequest: LoadReplayReturnPipeW2ReplayRowClearRequest, - fallbackEnable: Bool, - maskPhysicalInputs: Bool, - enable: Bool, - flush: Bool): Unit = { - guard.io.enable := enable - guard.io.flush := flush - guard.io.fallbackEnable := fallbackEnable - guard.io.captureAccepted := retireRecord.io.captureAccepted - guard.io.captureRowClearReady := physicalLifecycle.io.rowClearReady - guard.io.captureRowClearIndex := physicalLifecycle.io.rowClearIndex - guard.io.physicalClearAccepted := !maskPhysicalInputs && clearRequest.io.lifecycleClearAccepted - guard.io.physicalClearIndex := clearRequest.io.clearResolvedIndex - guard.io.recordValid := retireRecord.io.recordValid - guard.io.recordLifecycleClearReady := evidence.io.providerRowClearReady - guard.io.recordRowClearIndex := evidence.io.providerRowClearIndex - guard.io.recordFire := retireRecord.io.recordFire - - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCapturePhysicalClear := - guard.io.capturePhysicalClear - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCandidate := - guard.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackDuplicatePhysicalClear := - guard.io.duplicatePhysicalClear - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackClearValid := - guard.io.fallbackClearValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordFallbackOwnerPolicyWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - policy: LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - robGuard: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfGuard: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupGuard: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleClearGuard: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - globalFallbackEnable: Bool, - noPhysicalProbe: Bool, - fallbackEmitProbe: Bool, - fallbackLiveProbe: Bool, - enable: Bool, - flush: Bool): Unit = { - policy.io.enable := enable - policy.io.flush := flush - policy.io.globalFallbackEnable := globalFallbackEnable - policy.io.recordValid := retireRecord.io.recordValid - policy.io.robCandidate := robGuard.io.recordCandidate - policy.io.rfCandidate := rfGuard.io.recordCandidate - policy.io.wakeupCandidate := wakeupGuard.io.recordCandidate - policy.io.lifecycleClearCandidate := lifecycleClearGuard.io.recordCandidate - policy.io.robDuplicatePhysicalComplete := !noPhysicalProbe && robGuard.io.duplicatePhysicalComplete - policy.io.rfDuplicatePhysicalWriteback := !noPhysicalProbe && rfGuard.io.duplicatePhysicalWriteback - policy.io.wakeupDuplicatePhysicalWakeup := !noPhysicalProbe && wakeupGuard.io.duplicatePhysicalWakeup - policy.io.lifecycleClearDuplicatePhysicalClear := !noPhysicalProbe && lifecycleClearGuard.io.duplicatePhysicalClear - - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyCandidate := - policy.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyAllCandidatesReady := - policy.io.allFallbackCandidatesReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByPhysicalDuplicate := - policy.io.blockedByPhysicalDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyNoPhysicalProbeActive := - noPhysicalProbe && policy.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackEmitProbeActive := - fallbackEmitProbe && policy.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackLiveProbeActive := - fallbackLiveProbe && policy.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyRetainedSoleOwnerEligible := - policy.io.retainedSoleOwnerEligible - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByGlobalFallbackDisabled := - policy.io.blockedByGlobalFallbackDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicySideEffectEnable := - policy.io.sideEffectOwnerEnable - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackRfWritebackMuxWiring { - def connect( - arbiter: ReducedScalarWritebackArbiter, - physicalLiveControl: LoadReplayReturnPipeW2SideEffectLiveControl, - physicalInput: LoadReplayReturnPipeW2WritebackArbiterInput, - retainedFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - retainedFallbackLiveProbe: Bool, - retainedFallbackWritebackValid: Bool, - suppressPhysicalReplay: Bool): Unit = { - arbiter.io.replayEnable := - Mux(retainedFallbackLiveProbe, true.B, physicalLiveControl.io.writebackLiveEnable && !suppressPhysicalReplay) - arbiter.io.replayValid := - Mux(retainedFallbackLiveProbe, retainedFallbackWritebackValid, physicalInput.io.candidateValid && !suppressPhysicalReplay) - arbiter.io.replayTag := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackWritebackTag, physicalInput.io.writeTag) - arbiter.io.replayData := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackWritebackData, physicalInput.io.writeData) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackLiveSelectionWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - robArbiter: ReducedRobCompletionArbiter, - rfArbiter: ReducedScalarWritebackArbiter, - wakeupInput: LoadReplayReturnPipeW2WakeupArbiterInput, - lifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - robFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - retainedFallbackLiveProbeActive: Bool): Unit = { - io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackLiveCompleteSelected := - retainedFallbackLiveProbeActive && - robArbiter.io.selectedReplay && - robFallback.io.fallbackCompleteValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackLiveWritebackSelected := - retainedFallbackLiveProbeActive && - rfArbiter.io.selectedReplay && - rfFallback.io.fallbackWritebackValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackLiveWakeupSelected := - retainedFallbackLiveProbeActive && - wakeupInput.io.wakeupValid && - wakeupFallback.io.fallbackWakeupValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackLiveClearSelected := - retainedFallbackLiveProbeActive && - lifecycleEvidence.io.clearAccepted && - lifecycleFallback.io.fallbackClearValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordModelOrderProofWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - proof: LoadReplayReturnPipeW2RetireRecordModelOrderProof, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - robFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - ownerPolicy: LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy, - enable: Bool, - flush: Bool): Unit = { - proof.io.enable := enable - proof.io.flush := flush - proof.io.recordValid := retireRecord.io.recordValid - proof.io.robReturnSideEffectValid := robFallback.io.fallbackCompleteValid - proof.io.rfReturnSideEffectValid := rfFallback.io.fallbackWritebackValid - proof.io.wakeupReturnSideEffectValid := wakeupFallback.io.fallbackWakeupValid - proof.io.lifecycleEvidenceProviderValid := lifecycleEvidence.io.providerValid - proof.io.lifecycleClearFallbackValid := lifecycleFallback.io.fallbackClearValid - proof.io.sideEffectOwnerEnable := ownerPolicy.io.sideEffectOwnerEnable - - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRecordCandidate := - proof.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnSideEffectsReady := - proof.io.returnSideEffectsReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRetireClearEvidenceReady := - proof.io.retireClearEvidenceReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnThenRetireReady := - proof.io.returnThenRetireReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderFallbackOwnerEligible := - proof.io.fallbackOwnerModelOrderEligible - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingReturnSideEffect := - proof.io.blockedByMissingReturnSideEffect - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingRetireClearEvidence := - proof.io.blockedByMissingRetireClearEvidence - io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByOwnerDisabled := - proof.io.blockedByOwnerDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordDefaultPromotionReadinessWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - readiness: LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - ownerPolicy: LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy, - robFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - probeActive: Bool, - enable: Bool, - flush: Bool): Unit = { - readiness.io.enable := enable - readiness.io.flush := flush - readiness.io.recordValid := retireRecord.io.recordValid - readiness.io.fallbackCandidatesReady := ownerPolicy.io.allFallbackCandidatesReady - readiness.io.lifecycleEvidenceProviderValid := lifecycleEvidence.io.providerValid - readiness.io.robDuplicatePhysicalComplete := robFallback.io.duplicatePhysicalComplete - readiness.io.rfDuplicatePhysicalWriteback := rfFallback.io.duplicatePhysicalWriteback - readiness.io.wakeupDuplicatePhysicalWakeup := wakeupFallback.io.duplicatePhysicalWakeup - readiness.io.lifecycleClearDuplicatePhysicalClear := lifecycleFallback.io.duplicatePhysicalClear - readiness.io.probeActive := probeActive - - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionRecordCandidate := - readiness.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionPreArmModelOrderReady := - readiness.io.preArmModelOrderReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionAnyPhysicalDuplicate := - readiness.io.anyPhysicalDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionReady := - readiness.io.defaultPromotionReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByNoRecord := - readiness.io.blockedByNoRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingFallbackCandidate := - readiness.io.blockedByMissingFallbackCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingLifecycleEvidence := - readiness.io.blockedByMissingLifecycleEvidence - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByPhysicalDuplicate := - readiness.io.blockedByPhysicalDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByProbeActive := - readiness.io.blockedByProbeActive - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordDuplicateVectorWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - vector: LoadReplayReturnPipeW2RetireRecordDuplicateVector, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - readiness: LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness, - robFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - enable: Bool, - flush: Bool): Unit = { - vector.io.enable := enable - vector.io.flush := flush - vector.io.recordValid := retireRecord.io.recordValid - vector.io.preArmModelOrderReady := readiness.io.preArmModelOrderReady - vector.io.robDuplicatePhysicalComplete := robFallback.io.duplicatePhysicalComplete - vector.io.rfDuplicatePhysicalWriteback := rfFallback.io.duplicatePhysicalWriteback - vector.io.wakeupDuplicatePhysicalWakeup := wakeupFallback.io.duplicatePhysicalWakeup - vector.io.lifecycleClearDuplicatePhysicalClear := lifecycleFallback.io.duplicatePhysicalClear - - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorValid := - vector.io.duplicateVectorValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorReturnSideEffectBundle := - vector.io.returnSideEffectDuplicateBundle - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorModelOrderBundle := - vector.io.modelOrderDuplicateBundle - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorPartial := - vector.io.partialDuplicateVector - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorSingle := - vector.io.singleDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorMulti := - vector.io.multiDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorCount := - vector.io.duplicateCount - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorNextRequiresBundleTransfer := - vector.io.nextOwnerRequiresBundleTransfer - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoRecord := - vector.io.blockedByNoRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByPreArmNotReady := - vector.io.blockedByPreArmNotReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoDuplicate := - vector.io.blockedByNoDuplicate - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordBundleTransferPlanWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - plan: LoadReplayReturnPipeW2RetireRecordBundleTransferPlan, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - readiness: LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness, - vector: LoadReplayReturnPipeW2RetireRecordDuplicateVector, - probeActive: Bool, - enable: Bool, - flush: Bool): Unit = { - plan.io.enable := enable - plan.io.flush := flush - plan.io.recordValid := retireRecord.io.recordValid - plan.io.preArmModelOrderReady := readiness.io.preArmModelOrderReady - plan.io.defaultPromotionReady := readiness.io.defaultPromotionReady - plan.io.duplicateVectorValid := vector.io.duplicateVectorValid - plan.io.modelOrderDuplicateBundle := vector.io.modelOrderDuplicateBundle - plan.io.partialDuplicateVector := vector.io.partialDuplicateVector - plan.io.probeActive := probeActive - - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanCandidate := - plan.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanPreArmReady := - plan.io.preArmReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanModelOrderBundle := - plan.io.modelOrderBundle - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultTransferCandidate := - plan.io.defaultTransferCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanRequiresPhysicalBundleSuppression := - plan.io.requiresPhysicalBundleSuppression - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultPromotionAlreadyReady := - plan.io.defaultPromotionAlreadyReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoRecord := - plan.io.blockedByNoRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPreArmNotReady := - plan.io.blockedByPreArmNotReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoDuplicateVector := - plan.io.blockedByNoDuplicateVector - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPartialDuplicate := - plan.io.blockedByPartialDuplicate - io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByProbeActive := - plan.io.blockedByProbeActive - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressPlanWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - plan: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan, - transferPlan: LoadReplayReturnPipeW2RetireRecordBundleTransferPlan, - robFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - rfFallback: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - wakeupFallback: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - lifecycleFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - enable: Bool, - flush: Bool): Unit = { - plan.io.enable := enable - plan.io.flush := flush - plan.io.transferCandidate := transferPlan.io.defaultTransferCandidate - plan.io.requiresPhysicalBundleSuppression := - transferPlan.io.requiresPhysicalBundleSuppression - plan.io.robDuplicatePhysicalComplete := robFallback.io.duplicatePhysicalComplete - plan.io.rfDuplicatePhysicalWriteback := rfFallback.io.duplicatePhysicalWriteback - plan.io.wakeupDuplicatePhysicalWakeup := wakeupFallback.io.duplicatePhysicalWakeup - plan.io.lifecycleClearDuplicatePhysicalClear := lifecycleFallback.io.duplicatePhysicalClear - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanTransferCandidate := - plan.io.transferCandidateSeen - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressionRequired := - plan.io.suppressionRequired - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanPhysicalBundleComplete := - plan.io.physicalBundleComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAtomicSuppressCandidate := - plan.io.atomicSuppressCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRobComplete := - plan.io.suppressRobComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRfWriteback := - plan.io.suppressRfWriteback - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressWakeup := - plan.io.suppressWakeup - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressLifecycleClear := - plan.io.suppressLifecycleClear - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressMask := - plan.io.suppressMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAllOrNoneSuppress := - plan.io.allOrNoneSuppress - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoTransferCandidate := - plan.io.blockedByNoTransferCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoSuppressionRequirement := - plan.io.blockedByNoSuppressionRequirement - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByIncompletePhysicalBundle := - plan.io.blockedByIncompletePhysicalBundle - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressProbeWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - probe: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe, - plan: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan, - probeEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - probe.io.enable := enable - probe.io.flush := flush - probe.io.probeEnable := probeEnable - probe.io.atomicSuppressCandidate := plan.io.atomicSuppressCandidate - probe.io.suppressRobComplete := plan.io.suppressRobComplete - probe.io.suppressRfWriteback := plan.io.suppressRfWriteback - probe.io.suppressWakeup := plan.io.suppressWakeup - probe.io.suppressLifecycleClear := plan.io.suppressLifecycleClear - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeCandidate := - probe.io.suppressCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeEnabledCandidate := - probe.io.probeEnabledCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelected := - probe.io.selected - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelectedMask := - probe.io.selectedMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeAllOrNoneInputMask := - probe.io.allOrNoneInputMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByProbeDisabled := - probe.io.blockedByProbeDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByNoAtomicCandidate := - probe.io.blockedByNoAtomicCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByPartialMask := - probe.io.blockedByPartialMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressBoundaryWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - boundary: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary, - select: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect, - enable: Bool, - flush: Bool): Unit = { - boundary.io.enable := enable - boundary.io.flush := flush - boundary.io.selected := select.io.selected - boundary.io.selectedMask := select.io.selectedMask - boundary.io.allOrNoneInputMask := select.io.allOrNoneInputMask - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryCapture := - boundary.io.capture - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredValid := - boundary.io.registeredValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredMask := - boundary.io.registeredMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredFullMask := - boundary.io.registeredFullMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByNoSelection := - boundary.io.blockedByNoSelection - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByPartialMask := - boundary.io.blockedByPartialMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryClearedByFlush := - boundary.io.clearedByFlush - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressSelectWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - select: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect, - plan: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan, - probe: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe, - promoteEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - select.io.enable := enable - select.io.flush := flush - select.io.promoteEnable := promoteEnable - select.io.planAtomicSuppressCandidate := plan.io.atomicSuppressCandidate - select.io.planSuppressMask := plan.io.suppressMask - select.io.planAllOrNoneSuppress := plan.io.allOrNoneSuppress - select.io.probeSelected := probe.io.selected - select.io.probeSelectedMask := probe.io.selectedMask - select.io.probeAllOrNoneInputMask := probe.io.allOrNoneInputMask - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectPlanPromotedCandidate := - select.io.planPromotedCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelected := - select.io.selected - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedMask := - select.io.selectedMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectAllOrNoneInputMask := - select.io.allOrNoneInputMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromProbe := - select.io.selectedFromProbe - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromPromotion := - select.io.selectedFromPromotion - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPromoteDisabled := - select.io.blockedByPromoteDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByNoPlanCandidate := - select.io.blockedByNoPlanCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPartialPlanMask := - select.io.blockedByPartialPlanMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectInvalidProbePromotionMaskMismatch := - select.io.invalidProbePromotionMaskMismatch - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressIdentityProofWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - proof: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof, - boundary: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - enable: Bool, - flush: Bool): Unit = { - proof.io.enable := enable - proof.io.flush := flush - proof.io.capture := boundary.io.capture - proof.io.captureRid := retireRecord.io.record.rid - proof.io.captureLoadLsId := retireRecord.io.record.loadLsId - proof.io.captureLifecycleRowReady := lifecycleEvidence.io.providerRowClearReady - proof.io.captureLifecycleRowIndex := lifecycleEvidence.io.providerRowClearIndex - proof.io.registeredValid := boundary.io.registeredValid - proof.io.registeredFullMask := boundary.io.registeredFullMask - proof.io.recordValid := retireRecord.io.recordValid - proof.io.recordRid := retireRecord.io.record.rid - proof.io.recordLoadLsId := retireRecord.io.record.loadLsId - proof.io.lifecycleEvidenceProviderValid := lifecycleEvidence.io.providerValid - proof.io.lifecycleEvidenceRowClearIndex := lifecycleEvidence.io.providerRowClearIndex - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCaptureIdentity := - proof.io.captureIdentity - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCapturedIdentityValid := - proof.io.capturedIdentityValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRegisteredCandidate := - proof.io.registeredCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRetainedRecordAligned := - proof.io.retainedRecordAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifecycleRowAligned := - proof.io.lifecycleRowAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifetimeAligned := - proof.io.identityLifetimeAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityEligibleRegisteredMask := - proof.io.eligibleRegisteredMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNoCapturedIdentity := - proof.io.blockedByNoCapturedIdentity - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingRecord := - proof.io.blockedByMissingRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByRidMismatch := - proof.io.blockedByRidMismatch - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLoadLsIdMismatch := - proof.io.blockedByLoadLsIdMismatch - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingLifecycleEvidence := - proof.io.blockedByMissingLifecycleEvidence - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLifecycleRowMismatch := - proof.io.blockedByLifecycleRowMismatch - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNotFullMask := - proof.io.blockedByNotFullMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressOwnershipBoundaryWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - ownership: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary, - boundary: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - enable: Bool, - flush: Bool): Unit = { - ownership.io.enable := enable - ownership.io.flush := flush - ownership.io.capture := boundary.io.capture - ownership.io.captureRid := retireRecord.io.record.rid - ownership.io.captureLoadLsId := retireRecord.io.record.loadLsId - ownership.io.captureLifecycleRowReady := lifecycleEvidence.io.providerRowClearReady - ownership.io.captureLifecycleRowIndex := lifecycleEvidence.io.providerRowClearIndex - ownership.io.registeredValid := boundary.io.registeredValid - ownership.io.registeredFullMask := boundary.io.registeredFullMask - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCaptureOwnership := - ownership.io.captureOwnership - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCapturedOwnershipValid := - ownership.io.capturedOwnershipValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredCandidate := - ownership.io.registeredCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredRidValid := - ownership.io.registeredRidValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLoadLsIdValid := - ownership.io.registeredLoadLsIdValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLifecycleRowReady := - ownership.io.registeredLifecycleRowReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredBundleReady := - ownership.io.registeredOwnershipBundleReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipEligibleRegisteredMask := - ownership.io.eligibleRegisteredMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNoCapturedOwnership := - ownership.io.blockedByNoCapturedOwnership - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingRid := - ownership.io.blockedByMissingRid - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLoadLsId := - ownership.io.blockedByMissingLoadLsId - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLifecycleRow := - ownership.io.blockedByMissingLifecycleRow - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNotFullMask := - ownership.io.blockedByNotFullMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressLiveMaskWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - liveMask: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask, - ownership: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary, - liveMaskEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - liveMask.io.enable := enable - liveMask.io.flush := flush - liveMask.io.liveMaskEnable := liveMaskEnable - liveMask.io.eligibleRegisteredMask := ownership.io.eligibleRegisteredMask - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskCandidate := - liveMask.io.maskCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskEnabledCandidate := - liveMask.io.liveMaskCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRobComplete := - liveMask.io.suppressRobComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRfWriteback := - liveMask.io.suppressRfWriteback - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressWakeup := - liveMask.io.suppressWakeup - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressLifecycleClear := - liveMask.io.suppressLifecycleClear - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressMask := - liveMask.io.suppressMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskAllOrNone := - liveMask.io.allOrNoneMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByLiveMaskDisabled := - liveMask.io.blockedByLiveMaskDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByNoEligibleOwnership := - liveMask.io.blockedByNoEligibleOwnership - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressClearProofWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - proof: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof, - liveMask: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask, - fireComplete: LoadReplayReturnPipeW2SideEffectFireComplete, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - rowFill: LoadReplayReturnPipeW2RowFillEnableControl, - replayRowClearRequest: LoadReplayReturnPipeW2ReplayRowClearRequest, - enable: Bool, - flush: Bool): Unit = { - proof.io.enable := enable - proof.io.flush := flush - proof.io.liveMaskCandidate := liveMask.io.liveMaskCandidate - proof.io.suppressMask := liveMask.io.suppressMask - proof.io.fireComplete := fireComplete.io.fireComplete - proof.io.clearIntent := clearIntent.io.clearIntent - proof.io.liveClear := clearIntent.io.liveClear - proof.io.rowFillEnable := rowFill.io.rowFillEnable - proof.io.lifecycleClearEnable := replayRowClearRequest.io.lifecycleClearEnable - proof.io.lifecycleClearAccepted := replayRowClearRequest.io.lifecycleClearAccepted - - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofCandidate := - proof.io.candidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFullMask := - proof.io.fullMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFireCompleteAligned := - proof.io.fireCompleteAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofClearIntentAligned := - proof.io.clearIntentAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLiveClearAligned := - proof.io.liveClearAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofRowFillAligned := - proof.io.rowFillAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLifecycleClearSuppressed := - proof.io.lifecycleClearSuppressed - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofAllClearAligned := - proof.io.allClearAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByPartialMask := - proof.io.blockedByPartialMask - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoFireComplete := - proof.io.blockedByNoFireComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoClearIntent := - proof.io.blockedByNoClearIntent - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoLiveClear := - proof.io.blockedByNoLiveClear - io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoRowFill := - proof.io.blockedByNoRowFill - io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByLifecycleClearStillEnabled := - proof.io.blockedByLifecycleClearStillEnabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackOwnerWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - modules: LinxCoreFrontendFetchRfAluTraceTopW2Modules, - robArbiter: ReducedRobCompletionArbiter, - rfArbiter: ReducedScalarWritebackArbiter, - fallbackEmitProbe: Bool, - noPhysicalProbe: Bool, - fallbackLiveProbe: Bool, - fallbackLiveProbeActive: Bool, - physicalSuppressProbe: Bool, - physicalSuppressPromote: Bool, - physicalSuppressLiveMask: Bool, - enable: Bool, - flush: Bool): Unit = { - val fallbackProbe = fallbackEmitProbe || fallbackLiveProbe - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRobCompleteFallbackWiring.connect( - io, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecord, - modules.slot, - modules.robCompleteSource, - modules.retireRecordCommitRowCandidate, - modules.retireRecordFallbackOwnerPolicy.io.sideEffectOwnerEnable, - fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRfWritebackFallbackWiring.connect( - io, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecord, - modules.slot, - modules.writebackFirePayload, - modules.retireRecordFallbackOwnerPolicy.io.sideEffectOwnerEnable, - fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWakeupFallbackWiring.connect( - io, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecord, - modules.slot, - modules.wakeupFirePayload, - modules.retireRecordFallbackOwnerPolicy.io.sideEffectOwnerEnable, - fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleClearFallbackWiring.connect( - io, - modules.retireRecordLifecycleClearFallbackGuard, - modules.retireRecord, - modules.retireRecordLifecycleEvidence, - modules.replayRowLifecycleReady, - modules.replayRowClearRequest, - modules.retireRecordFallbackOwnerPolicy.io.sideEffectOwnerEnable, - fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordFallbackOwnerPolicyWiring.connect( - io, - modules.retireRecordFallbackOwnerPolicy, - modules.retireRecord, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - fallbackProbe, - noPhysicalProbe || fallbackProbe, - fallbackEmitProbe, - fallbackLiveProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetainedFallbackLiveSelectionWiring.connect( - io, - robArbiter, - rfArbiter, - modules.wakeupArbiterInput, - modules.retireRecordLifecycleEvidence, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - fallbackLiveProbeActive - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordModelOrderProofWiring.connect( - io, - modules.retireRecordModelOrderProof, - modules.retireRecord, - modules.retireRecordLifecycleEvidence, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - modules.retireRecordFallbackOwnerPolicy, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordDefaultPromotionReadinessWiring.connect( - io, - modules.retireRecordDefaultPromotionReadiness, - modules.retireRecord, - modules.retireRecordLifecycleEvidence, - modules.retireRecordFallbackOwnerPolicy, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - noPhysicalProbe || fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordDuplicateVectorWiring.connect( - io, - modules.retireRecordDuplicateVector, - modules.retireRecord, - modules.retireRecordDefaultPromotionReadiness, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordBundleTransferPlanWiring.connect( - io, - modules.retireRecordBundleTransferPlan, - modules.retireRecord, - modules.retireRecordDefaultPromotionReadiness, - modules.retireRecordDuplicateVector, - noPhysicalProbe || fallbackProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressPlanWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressPlan, - modules.retireRecordBundleTransferPlan, - modules.retireRecordRobCompleteFallbackGuard, - modules.retireRecordRfWritebackFallbackGuard, - modules.retireRecordWakeupFallbackGuard, - modules.retireRecordLifecycleClearFallbackGuard, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressProbeWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressProbe, - modules.retireRecordPhysicalBundleSuppressPlan, - physicalSuppressProbe, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressSelectWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressSelect, - modules.retireRecordPhysicalBundleSuppressPlan, - modules.retireRecordPhysicalBundleSuppressProbe, - physicalSuppressPromote, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressBoundaryWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressBoundary, - modules.retireRecordPhysicalBundleSuppressSelect, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressIdentityProofWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressIdentityProof, - modules.retireRecordPhysicalBundleSuppressBoundary, - modules.retireRecord, - modules.retireRecordLifecycleEvidence, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressOwnershipBoundaryWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressOwnershipBoundary, - modules.retireRecordPhysicalBundleSuppressBoundary, - modules.retireRecord, - modules.retireRecordLifecycleEvidence, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressLiveMaskWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressLiveMask, - modules.retireRecordPhysicalBundleSuppressOwnershipBoundary, - physicalSuppressLiveMask, - enable, - flush - ) - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordPhysicalBundleSuppressClearProofWiring.connect( - io, - modules.retireRecordPhysicalBundleSuppressClearProof, - modules.retireRecordPhysicalBundleSuppressLiveMask, - modules.sideEffectFireComplete, - modules.clearIntent, - modules.rowFillEnableControl, - modules.replayRowClearRequest, - enable, - flush - ) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordInstructionMetadataLatchWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - metadata: LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - slot: LoadReplayReturnPipeW2Slot, - sink: ScalarLSULoadReturnQueueBank, - sinkEntry: LoadReplayReturnLretEntry, - w2InstructionValid: Bool, - w2InstructionRaw: UInt, - w2InstructionLen: UInt, - drainInstructionCapture: Bool, - drainInstructionRaw: UInt, - drainInstructionLen: UInt, - enable: Bool, - flush: Bool): Unit = { - metadata.io.enable := enable - metadata.io.flush := flush - metadata.io.captureAccepted := retireRecord.io.captureAccepted - metadata.io.capturePayloadRid := slot.io.entryRid - metadata.io.w2Rid := slot.io.entryRid - metadata.io.w2InstructionValid := w2InstructionValid - metadata.io.w2InstructionRaw := w2InstructionRaw - metadata.io.w2InstructionLen := w2InstructionLen - metadata.io.drainInstructionCapture := drainInstructionCapture - metadata.io.drainRid := sink.io.drain.rid - metadata.io.drainInstructionRaw := drainInstructionRaw - metadata.io.drainInstructionLen := drainInstructionLen - metadata.io.recordFire := retireRecord.io.recordFire - metadata.io.recordFireRid := retireRecord.io.record.rid - metadata.io.recordValid := retireRecord.io.recordValid - metadata.io.recordRid := retireRecord.io.record.rid - - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureIntent := - metadata.io.captureIntent - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCapturePayloadRidValid := - metadata.io.capturePayloadRidValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidValid := - metadata.io.w2RidValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidMatchesCapture := - metadata.io.w2RidMatchesCapture - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2MetadataReady := - metadata.io.w2MetadataReady - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromW2 := - metadata.io.captureFromW2 - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromDrain := - metadata.io.captureFromDrain - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoPayloadRid := - metadata.io.captureBlockedByNoPayloadRid - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Rid := - metadata.io.captureBlockedByNoW2Rid - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByRidMismatch := - metadata.io.captureBlockedByRidMismatch - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Metadata := - metadata.io.captureBlockedByNoW2Metadata - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataClearAccepted := - metadata.io.clearAccepted - io.reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataProviderValid := - metadata.io.providerValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordLifecycleRequestProbeWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - probe: LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleRowClearReady: Bool, - atomicRequestActive: Bool, - rowFillCandidateValid: Bool, - rowFillEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - probe.io.enable := enable - probe.io.flush := flush - probe.io.retireRecordValid := retireRecord.io.recordValid - probe.io.lifecycleRowClearReady := lifecycleRowClearReady - probe.io.atomicRequestActive := atomicRequestActive - probe.io.rowFillCandidateValid := rowFillCandidateValid - probe.io.rowFillEnable := rowFillEnable - - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeCandidate := - probe.io.requestCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeLivePromotionCandidate := - probe.io.livePromotionCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoLifecycleRow := - probe.io.blockedByNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoAtomicRequest := - probe.io.blockedByNoAtomicRequest - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillCandidate := - probe.io.blockedByNoRowFillCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillEnable := - probe.io.blockedByNoRowFillEnable - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordAtomicRequestProbeWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - probe: LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleRowClearReady: Bool, - rowFillCandidateValid: Bool, - rowFillEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - probe.io.enable := enable - probe.io.flush := flush - probe.io.retireRecordValid := retireRecord.io.recordValid - probe.io.lifecycleRowClearReady := lifecycleRowClearReady - probe.io.rowFillCandidateValid := rowFillCandidateValid - probe.io.rowFillEnable := rowFillEnable - - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeEvidenceValid := - probe.io.requestEvidenceValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillCandidateAligned := - probe.io.rowFillCandidateAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillEnableAligned := - probe.io.rowFillEnableAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoLifecycleRow := - probe.io.blockedByNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillCandidate := - probe.io.blockedByNoRowFillCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillEnable := - probe.io.blockedByNoRowFillEnable - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopR376SourceTraceWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - allocPath: ReducedLoadReplayLiqAllocPath, - lretPayload: LoadReplayReturnLretPayload, - lretEntry: LoadReplayReturnLretEntry, - iexData: LoadReplayReturnIexDataCandidate, - pipeInsert: LoadReplayReturnIexPipeInsertCandidate, - residencySlot: LoadReplayReturnPipeResidencySlot, - w1Slot: LoadReplayReturnPipeW1Slot, - w2Slot: LoadReplayReturnPipeW2Slot, - returnCompleteSelected: Bool): Unit = { - lretPayload.io.selectedSourceTraceValid := - Mux(returnCompleteSelected, - allocPath.io.returnCompleteSelectedSourceTraceValid, - allocPath.io.launchSelectedSourceTraceValid) - lretPayload.io.selectedSource0 := - Mux(returnCompleteSelected, allocPath.io.returnCompleteSelectedSource0, allocPath.io.launchSelectedSource0) - lretPayload.io.selectedSource1 := - Mux(returnCompleteSelected, allocPath.io.returnCompleteSelectedSource1, allocPath.io.launchSelectedSource1) - - lretEntry.sourceTraceValid := lretPayload.io.payloadSourceTraceValid - lretEntry.source0 := lretPayload.io.payloadSource0 - lretEntry.source1 := lretPayload.io.payloadSource1 - - pipeInsert.io.memSourceTraceValid := iexData.io.memSourceTraceValid - pipeInsert.io.memSource0 := iexData.io.memSource0 - pipeInsert.io.memSource1 := iexData.io.memSource1 - - residencySlot.io.writeSourceTraceValid := pipeInsert.io.insertSourceTraceValid - residencySlot.io.writeSource0 := pipeInsert.io.insertSource0 - residencySlot.io.writeSource1 := pipeInsert.io.insertSource1 - - w1Slot.io.writeSourceTraceValid := residencySlot.io.entrySourceTraceValid - w1Slot.io.writeSource0 := residencySlot.io.entrySource0 - w1Slot.io.writeSource1 := residencySlot.io.entrySource1 - - w2Slot.io.writeSourceTraceValid := w1Slot.io.entrySourceTraceValid - w2Slot.io.writeSource0 := w1Slot.io.entrySource0 - w2Slot.io.writeSource1 := w1Slot.io.entrySource1 - - io.reducedLoadReplayLiqLretPayloadSourceTraceValid := lretPayload.io.payloadSourceTraceValid - io.reducedLoadReplayLiqLretPayloadSource0Valid := lretPayload.io.payloadSource0.valid - io.reducedLoadReplayLiqLretPayloadSource0Reg := lretPayload.io.payloadSource0.reg - io.reducedLoadReplayLiqLretPayloadSource0Data := lretPayload.io.payloadSource0.data - io.reducedLoadReplayLiqLretPayloadSource1Valid := lretPayload.io.payloadSource1.valid - io.reducedLoadReplayLiqLretPayloadSource1Reg := lretPayload.io.payloadSource1.reg - io.reducedLoadReplayLiqLretPayloadSource1Data := lretPayload.io.payloadSource1.data - - io.reducedLoadReplayLiqLretPipeW2SlotSourceTraceValid := w2Slot.io.entrySourceTraceValid - io.reducedLoadReplayLiqLretPipeW2SlotSource0Valid := w2Slot.io.entrySource0.valid - io.reducedLoadReplayLiqLretPipeW2SlotSource0Reg := w2Slot.io.entrySource0.reg - io.reducedLoadReplayLiqLretPipeW2SlotSource0Data := w2Slot.io.entrySource0.data - io.reducedLoadReplayLiqLretPipeW2SlotSource1Valid := w2Slot.io.entrySource1.valid - io.reducedLoadReplayLiqLretPipeW2SlotSource1Reg := w2Slot.io.entrySource1.reg - io.reducedLoadReplayLiqLretPipeW2SlotSource1Data := w2Slot.io.entrySource1.data - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2CommitRowTraceSourceWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - traceSource: LoadReplayReturnPipeW2CommitRowTraceSource, - robTraceLookup: ROBRowCommitTraceLookupResult, - instructionProviderValid: Bool, - instructionProviderRaw: UInt, - instructionProviderLen: UInt, - slot: LoadReplayReturnPipeW2Slot, - enable: Bool, - flush: Bool): Unit = { - traceSource.io.enable := enable - traceSource.io.flush := flush - traceSource.io.slotOccupied := slot.io.occupied - traceSource.io.instructionProviderValid := instructionProviderValid - traceSource.io.instructionProviderRaw := instructionProviderRaw - traceSource.io.instructionProviderLen := instructionProviderLen - traceSource.io.sourceTraceProviderValid := slot.io.entrySourceTraceValid - traceSource.io.source0Provider := slot.io.entrySource0 - traceSource.io.source1Provider := slot.io.entrySource1 - - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceReady := - traceSource.io.traceReady - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceInstructionReady := - traceSource.io.instructionMetadataReady - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceSourceReady := - traceSource.io.sourceTraceReady - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlocked := - traceSource.io.blockedByDisabled || - traceSource.io.blockedByFlush || - traceSource.io.blockedByNoSlot || - traceSource.io.blockedByNoInstructionMetadata || - traceSource.io.blockedByNoSourceTrace - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoMetadata := - traceSource.io.blockedByNoInstructionMetadata - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoSourceTrace := - traceSource.io.blockedByNoSourceTrace - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupRowValid := - robTraceLookup.rowValid - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupInstructionValid := - robTraceLookup.instructionProviderValid - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByNeedFlush := - robTraceLookup.blockedByNeedFlush - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByMissingInstruction := - robTraceLookup.blockedByMissingInstruction - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceDisabled := - robTraceLookup.blockedBySourceTraceDisabled - io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceBeforeCompletion := - robTraceLookup.blockedBySourceTraceBeforeCompletion - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2CommitRowCandidateWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - candidate: LoadReplayReturnPipeW2CommitRowCandidate, - traceSource: LoadReplayReturnPipeW2CommitRowTraceSource, - slot: LoadReplayReturnPipeW2Slot, - rowFillEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - candidate.io.enable := enable - candidate.io.flush := flush - candidate.io.rowFillEnable := rowFillEnable - candidate.io.slotOccupied := slot.io.occupied - candidate.io.slotTargetIsAgu := slot.io.entryTargetIsAgu - candidate.io.slotTargetIsLda := slot.io.entryTargetIsLda - candidate.io.slotBid := slot.io.entryBid - candidate.io.slotGid := slot.io.entryGid - candidate.io.slotRid := slot.io.entryRid - candidate.io.slotPc := slot.io.entryPc - candidate.io.slotAddr := slot.io.entryAddr - candidate.io.slotSize := slot.io.entrySize - candidate.io.slotDst := slot.io.entryDst - candidate.io.slotData := slot.io.entryData - candidate.io.instructionValid := traceSource.io.instructionValid - candidate.io.instructionRaw := traceSource.io.instructionRaw - candidate.io.instructionLen := traceSource.io.instructionLen - candidate.io.sourceTraceValid := traceSource.io.sourceTraceValid - candidate.io.source0 := traceSource.io.source0 - candidate.io.source1 := traceSource.io.source1 - - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateValid := - candidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateRowFillValid := - candidate.io.rowFillCandidateValid - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateCompleteRowValid := - candidate.io.completeRowValid - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlocked := - candidate.io.blockedByDisabled || - candidate.io.blockedByFlush || - candidate.io.blockedByNoSlot || - candidate.io.blockedByInvalidTarget || - candidate.io.blockedByInvalidIdentity || - candidate.io.blockedByNoInstructionMetadata || - candidate.io.blockedByNoSourceTrace || - candidate.io.blockedByInvalidSize || - candidate.io.blockedByNoDestination || - candidate.io.blockedByNonGprDestination || - candidate.io.blockedByRowFillDisabled - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoMetadata := - candidate.io.blockedByNoInstructionMetadata - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoSourceTrace := - candidate.io.blockedByNoSourceTrace - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByInvalidSize := - candidate.io.blockedByInvalidSize - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNonGprDestination := - candidate.io.blockedByNonGprDestination - io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByRowFillDisabled := - candidate.io.blockedByRowFillDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordCommitRowCandidateWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - candidate: LoadReplayReturnPipeW2RetireRecordCommitRowCandidate, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - instructionProviderValid: Bool, - instructionProviderRaw: UInt, - instructionProviderLen: UInt, - rowFillEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - candidate.io.enable := enable - candidate.io.flush := flush - candidate.io.rowFillEnable := rowFillEnable - candidate.io.recordValid := retireRecord.io.recordValid - candidate.io.record := retireRecord.io.record - candidate.io.instructionValid := instructionProviderValid - candidate.io.instructionRaw := instructionProviderRaw - candidate.io.instructionLen := instructionProviderLen - - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateValid := - candidate.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateRowFillValid := - candidate.io.rowFillCandidateValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateCompleteRowValid := - candidate.io.completeRowValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlocked := - candidate.io.blockedByDisabled || - candidate.io.blockedByFlush || - candidate.io.blockedByNoRecord || - candidate.io.blockedByInvalidIdentity || - candidate.io.blockedByNoInstructionMetadata || - candidate.io.blockedByNoSourceTrace || - candidate.io.blockedByInvalidSize || - candidate.io.blockedByNoDestination || - candidate.io.blockedByNonGprDestination || - candidate.io.blockedByRowFillDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoRecord := - candidate.io.blockedByNoRecord - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoMetadata := - candidate.io.blockedByNoInstructionMetadata - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoSourceTrace := - candidate.io.blockedByNoSourceTrace - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByInvalidSize := - candidate.io.blockedByInvalidSize - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNonGprDestination := - candidate.io.blockedByNonGprDestination - io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByRowFillDisabled := - candidate.io.blockedByRowFillDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRowFillEnableControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - control: LoadReplayReturnPipeW2RetireRecordRowFillEnableControl, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - lifecycleRowClearReady: Bool, - candidate: LoadReplayReturnPipeW2RetireRecordCommitRowCandidate, - rowFillRequested: Bool, - enable: Bool, - flush: Bool): Unit = { - control.io.enable := enable - control.io.flush := flush - control.io.rowFillRequested := rowFillRequested - control.io.retireRecordValid := retireRecord.io.recordValid - control.io.lifecycleRowClearReady := lifecycleRowClearReady - control.io.rowFillCandidateValid := candidate.io.rowFillCandidateValid - - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableRequestEvidenceValid := - control.io.requestEvidenceValid - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableCandidateAligned := - control.io.candidateAligned - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnable := - control.io.rowFillEnable - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByRequestDisabled := - control.io.blockedByRequestDisabled - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoLifecycleRow := - control.io.blockedByNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoRowFillCandidate := - control.io.blockedByNoRowFillCandidate - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopLiveLoadLiqCaptureWiring { - def connect( - capture: ReducedLiveLoadLiqCapture, - execute: ReducedScalarAluExecute, - loadDst: LoadReplayDestination, - loadLsId: ROBID, - loadLsIdFull: UInt, - enable: Bool, - flush: Bool): Unit = { - capture.io.captureEnable := enable - capture.io.flush := flush - capture.io.loadValid := execute.io.loadLookupValid && execute.io.loadLiqEligible - capture.io.loadPc := execute.io.loadLookupPc - capture.io.loadAddr := execute.io.loadLookupAddr - capture.io.loadSize := execute.io.loadLookupSize - capture.io.loadReturnSignExtend := execute.io.loadLookupReturnSignExtend - capture.io.loadDst := loadDst - capture.io.loadSourceTraceValid := execute.io.loadLookupSourceTraceValid - capture.io.loadSource0 := execute.io.loadLookupSource0 - capture.io.loadSource1 := execute.io.loadLookupSource1 - capture.io.loadBid := execute.io.loadLookupBid - capture.io.loadGid := execute.io.loadLookupGid - capture.io.loadRid := execute.io.loadLookupRid - capture.io.loadLsId := loadLsId - capture.io.loadLsIdFullValid := execute.io.loadLookupValid - capture.io.loadLsIdFull := loadLsIdFull - capture.io.youngestStoreId := execute.io.loadLookupBid - capture.io.youngestStoreLsId := loadLsId - capture.io.youngestStoreLsIdFullValid := execute.io.loadLookupValid - capture.io.youngestStoreLsIdFull := loadLsIdFull - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopRobCompleteArbiterWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - arbiter: ReducedRobCompletionArbiter, - retainer: ExecuteCompletionRetainer, - execute: ReducedScalarAluExecute, - servicePath: ReducedServiceRequestPath, - scalarScCompleteValid: Bool, - scalarScCompleteRow: CommitTraceRow, - scalarScCompleteRobValue: UInt, - replay: LoadReplayReturnPipeW2RobCompleteSource, - retainedFallback: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - retainedFallbackLiveProbe: Bool, - suppressPhysicalReplay: Bool): Unit = { - retainer.io.lanes(0).valid := execute.io.completeValid - retainer.io.lanes(0).key.valid := execute.io.completeValid - retainer.io.lanes(0).key.peId := execute.io.completePeId - retainer.io.lanes(0).key.stid := execute.io.completeStid - retainer.io.lanes(0).key.tid := execute.io.completeTid - retainer.io.lanes(0).key.pc := execute.io.completeRow.pc - retainer.io.lanes(0).key.bid := execute.io.releaseBid - retainer.io.lanes(0).key.gid := execute.io.releaseGid - retainer.io.lanes(0).key.rid := execute.io.releaseRid - retainer.io.lanes(0).key.rob.valid := execute.io.completeValid && execute.io.completeRow.rob.valid - retainer.io.lanes(0).key.rob.wrap := execute.io.completeRow.rob.wrap - retainer.io.lanes(0).key.rob.value := execute.io.completeRow.rob.value(retainer.io.completeRobValue.getWidth - 1, 0) - retainer.io.lanes(0).rowValid := execute.io.completeValid - retainer.io.lanes(0).row := execute.io.completeRow - execute.io.completeReady := retainer.io.laneReady(0) - retainer.io.lanes(1) := 0.U.asTypeOf(retainer.io.lanes(1)) - // Reduced top has no exact completion-key range-clear translator yet. - // Reset clears retained state; stale retained rows after recovery drain via - // the ROB path's ignored-completion result instead of an invented clear. - retainer.io.clear := 0.U.asTypeOf(retainer.io.clear) - retainer.io.outputReady := arbiter.io.selectedExecute && (path.io.completeAccepted || path.io.completeIgnored) - - arbiter.io.executeCompleteValid := retainer.io.completeValid - arbiter.io.executeCompleteRobValue := retainer.io.completeRobValue - arbiter.io.executeCompleteRowValid := retainer.io.completeRowValid - arbiter.io.executeCompleteRow := retainer.io.completeRow - arbiter.io.replayCompleteValid := - Mux( - retainedFallbackLiveProbe, - retainedFallback.io.fallbackCompleteValid, - replay.io.completeValid && !suppressPhysicalReplay) - arbiter.io.replayCompleteRobValue := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackCompleteRobValue, replay.io.completeRobValue) - arbiter.io.replayCompleteRowValid := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackCompleteRowValid, replay.io.completeRowValid) - arbiter.io.replayCompleteRow := - Mux(retainedFallbackLiveProbe, retainedFallback.io.fallbackCompleteRow, replay.io.completeRow) - val selectedServicePathComplete = servicePath.io.completeValid - val selectedScalarScComplete = !selectedServicePathComplete && scalarScCompleteValid - arbiter.io.serviceCompleteValid := selectedServicePathComplete || selectedScalarScComplete - arbiter.io.serviceCompleteRobValue := - Mux(selectedServicePathComplete, servicePath.io.completeRobValue, scalarScCompleteRobValue) - arbiter.io.serviceCompleteRowValid := selectedServicePathComplete || selectedScalarScComplete - arbiter.io.serviceCompleteRow := - Mux(selectedServicePathComplete, servicePath.io.completeRow, scalarScCompleteRow) - arbiter.io.templateCompleteValid := false.B - arbiter.io.templateCompleteRobValue := 0.U - arbiter.io.templateCompleteRowValid := false.B - arbiter.io.templateCompleteRow := 0.U.asTypeOf(arbiter.io.templateCompleteRow) - arbiter.io.templateCompleteParentSlot := 0.U - - path.io.completeValid := arbiter.io.completeValid - path.io.completeRobValue := arbiter.io.completeRobValue - path.io.completeRowValid := arbiter.io.completeRowValid - path.io.completeRow := arbiter.io.completeRow - - io.robCompleteArbiterSelectedExecute := arbiter.io.selectedExecute - io.robCompleteArbiterSelectedReplay := arbiter.io.selectedReplay - io.robCompleteArbiterSelectedService := arbiter.io.selectedService - io.robCompleteArbiterReplayBlockedByExecute := arbiter.io.replayBlockedByExecute - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRobCompleteFallbackWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - guard: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - slot: LoadReplayReturnPipeW2Slot, - physicalRobComplete: LoadReplayReturnPipeW2RobCompleteSource, - retainedCandidate: LoadReplayReturnPipeW2RetireRecordCommitRowCandidate, - fallbackEnable: Bool, - maskPhysicalInputs: Bool, - enable: Bool, - flush: Bool): Unit = { - guard.io.enable := enable - guard.io.flush := flush - guard.io.fallbackEnable := fallbackEnable - guard.io.captureAccepted := retireRecord.io.captureAccepted - guard.io.captureRid := slot.io.entryRid - guard.io.physicalCompleteValid := !maskPhysicalInputs && physicalRobComplete.io.completeValid - guard.io.physicalCompleteRobValue := physicalRobComplete.io.completeRobValue - guard.io.recordValid := retireRecord.io.recordValid - guard.io.recordRid := retireRecord.io.record.rid - guard.io.recordFire := retireRecord.io.recordFire - guard.io.retainedCompleteRowValid := retainedCandidate.io.completeRowValid - guard.io.retainedCompleteRow := retainedCandidate.io.completeRow - - io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCapturePhysicalComplete := - guard.io.capturePhysicalComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCandidate := - guard.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackDuplicatePhysicalComplete := - guard.io.duplicatePhysicalComplete - io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCompleteValid := - guard.io.fallbackCompleteValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRfWritebackFallbackWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - guard: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - slot: LoadReplayReturnPipeW2Slot, - physicalWriteback: LoadReplayReturnPipeW2WritebackFirePayload, - fallbackEnable: Bool, - maskPhysicalInputs: Bool, - enable: Bool, - flush: Bool): Unit = { - guard.io.enable := enable - guard.io.flush := flush - guard.io.fallbackEnable := fallbackEnable - guard.io.captureAccepted := retireRecord.io.captureAccepted - guard.io.captureRid := slot.io.entryRid - guard.io.physicalWritebackValid := !maskPhysicalInputs && physicalWriteback.io.fireValid - guard.io.physicalWritebackRid := physicalWriteback.io.fireRid - guard.io.physicalWritebackTag := physicalWriteback.io.firePhysTag - guard.io.physicalWritebackData := physicalWriteback.io.fireData - guard.io.recordValid := retireRecord.io.recordValid - guard.io.recordRid := retireRecord.io.record.rid - guard.io.recordWritebackValid := - retireRecord.io.recordValid && - retireRecord.io.record.dst.valid && - (retireRecord.io.record.dst.kind === DestinationKind.Gpr) - guard.io.recordWritebackTag := retireRecord.io.record.dst.physTag - guard.io.recordWritebackData := retireRecord.io.record.data - guard.io.recordFire := retireRecord.io.recordFire - - io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCapturePhysicalWriteback := - guard.io.capturePhysicalWriteback - io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCandidate := - guard.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackDuplicatePhysicalWriteback := - guard.io.duplicatePhysicalWriteback - io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackWritebackValid := - guard.io.fallbackWritebackValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWakeupFallbackWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - guard: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - slot: LoadReplayReturnPipeW2Slot, - physicalWakeup: LoadReplayReturnPipeW2WakeupFirePayload, - fallbackEnable: Bool, - maskPhysicalInputs: Bool, - enable: Bool, - flush: Bool): Unit = { - guard.io.enable := enable - guard.io.flush := flush - guard.io.fallbackEnable := fallbackEnable - guard.io.captureAccepted := retireRecord.io.captureAccepted - guard.io.captureRid := slot.io.entryRid - guard.io.physicalWakeupValid := !maskPhysicalInputs && physicalWakeup.io.fireValid - guard.io.physicalWakeupRid := physicalWakeup.io.fireRid - guard.io.physicalReducedGprWakeup := physicalWakeup.io.reducedGprWakeup - guard.io.physicalWakeupTag := physicalWakeup.io.firePhysTag - guard.io.recordValid := retireRecord.io.recordValid - guard.io.recordRid := retireRecord.io.record.rid - guard.io.recordWakeupValid := - retireRecord.io.recordValid && - !retireRecord.io.record.specWakeup && - !retireRecord.io.record.stackValid && - retireRecord.io.record.dst.valid && - (retireRecord.io.record.dst.kind =/= DestinationKind.None) - guard.io.recordReducedGprWakeup := - retireRecord.io.record.dst.valid && - (retireRecord.io.record.dst.kind === DestinationKind.Gpr) - guard.io.recordWakeupTag := retireRecord.io.record.dst.physTag - guard.io.recordFire := retireRecord.io.recordFire - - io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCapturePhysicalWakeup := - guard.io.capturePhysicalWakeup - io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCandidate := - guard.io.recordCandidate - io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackDuplicatePhysicalWakeup := - guard.io.duplicatePhysicalWakeup - io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackWakeupValid := - guard.io.fallbackWakeupValid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ClearCommitGuardWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - guard: LoadReplayReturnPipeW2ClearCommitGuard, - slot: LoadReplayReturnPipeW2Slot, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - resolveFirePayload: LoadReplayReturnPipeW2ResolveFirePayload, - robCompleteSource: LoadReplayReturnPipeW2RobCompleteSource, - enable: Bool, - flush: Bool): Unit = { - guard.io.enable := enable - guard.io.flush := flush - guard.io.slotOccupied := slot.io.occupied - guard.io.slotRid := slot.io.entryRid - guard.io.clearIntent := clearIntent.io.clearIntent - guard.io.liveClear := clearIntent.io.liveClear - guard.io.resolveFireValid := resolveFirePayload.io.fireValid - guard.io.resolveFireRid := resolveFirePayload.io.fireRid - guard.io.robCompleteValid := robCompleteSource.io.completeValid - guard.io.robCompleteRobValue := robCompleteSource.io.completeRobValue - - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardCandidateValid := - guard.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardCommitClearReady := - guard.io.commitClearReady - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardLiveClearReady := - guard.io.liveClearReady - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardResolveMatchesSlot := - guard.io.resolveMatchesSlot - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesSlot := - guard.io.robMatchesSlot - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesResolve := - guard.io.robMatchesResolve - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlocked := - guard.io.blockedByDisabled || - guard.io.blockedByFlush || - guard.io.blockedByNoSlot || - guard.io.blockedByNoClearIntent || - guard.io.blockedByLiveClearDisabled || - guard.io.blockedByInvalidSlotRid || - guard.io.blockedByNoResolveFire || - guard.io.blockedByInvalidResolveRid || - guard.io.blockedByNoRobComplete || - guard.io.blockedByResolveSlotMismatch || - guard.io.blockedByRobSlotMismatch || - guard.io.blockedByRobResolveMismatch || - guard.io.invalidResolveWithoutClear || - guard.io.invalidRobCompleteWithoutClear - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByNoRobComplete := - guard.io.blockedByNoRobComplete - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByResolveSlotMismatch := - guard.io.blockedByResolveSlotMismatch - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobSlotMismatch := - guard.io.blockedByRobSlotMismatch - io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobResolveMismatch := - guard.io.blockedByRobResolveMismatch - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RowFillEnableControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - control: LoadReplayReturnPipeW2RowFillEnableControl, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - liveRequest: LoadReplayReturnPipeW2AtomicRequestGate, - commitRowCandidate: LoadReplayReturnPipeW2CommitRowCandidate, - fireComplete: LoadReplayReturnPipeW2SideEffectFireComplete, - clearGuard: LoadReplayReturnPipeW2ClearCommitGuard, - enable: Bool, - flush: Bool): Unit = { - control.io.enable := enable - control.io.flush := flush - control.io.rowFillRequested := liveRequest.io.requestActive - control.io.rowFillCandidateValid := commitRowCandidate.io.rowFillCandidateValid - control.io.sideEffectFireComplete := fireComplete.io.fireComplete - control.io.clearCommitReady := clearGuard.io.commitClearReady - control.io.liveClearReady := clearGuard.io.liveClearReady - control.io.replayRowLifecycleReady := lifecycle.io.lifecycleReady - - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlCandidateValid := - control.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlPrerequisitesReady := - control.io.atomicPrerequisitesReady - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlRowFillEnable := - control.io.rowFillEnable - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlocked := - control.io.blockedByDisabled || - control.io.blockedByFlush || - control.io.blockedByRequestDisabled || - control.io.blockedByNoCandidate || - control.io.blockedByNoSideEffectCommit || - control.io.blockedByNoClearCommit || - control.io.blockedByLiveClearDisabled || - control.io.blockedByNoReplayRowLifecycle - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByRequestDisabled := - control.io.blockedByRequestDisabled - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoCandidate := - control.io.blockedByNoCandidate - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoSideEffectCommit := - control.io.blockedByNoSideEffectCommit - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoClearCommit := - control.io.blockedByNoClearCommit - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByLiveClearDisabled := - control.io.blockedByLiveClearDisabled - io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoReplayRowLifecycle := - control.io.blockedByNoReplayRowLifecycle - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2AtomicLiveRequestWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - liveRequest: LoadReplayReturnPipeW2AtomicRequestGate, - prereqSnapshot: LoadReplayReturnPipeW2AtomicPrereqSnapshot, - completion: LoadReplayReturnPipeW2CompletionCandidate, - sideEffectSinksPrereqReady: Bool, - clearCommitPrereqReady: Bool, - w1Advance: LoadReplayReturnPipeW1AdvanceCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - commitRowCandidate: LoadReplayReturnPipeW2CommitRowCandidate, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - slot: LoadReplayReturnPipeW2Slot, - liveModeEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - prereqSnapshot.io.enable := enable - prereqSnapshot.io.flush := flush - prereqSnapshot.io.captureEnable := true.B - prereqSnapshot.io.slotOccupied := slot.io.occupied - prereqSnapshot.io.slotBid := slot.io.entryBid - prereqSnapshot.io.slotGid := slot.io.entryGid - prereqSnapshot.io.slotRid := slot.io.entryRid - prereqSnapshot.io.slotLoadLsId := slot.io.entryLoadLsId - prereqSnapshot.io.sideEffectSinksReadyIn := sideEffectSinksPrereqReady - prereqSnapshot.io.clearCommitReadyIn := clearCommitPrereqReady - prereqSnapshot.io.rowFillCandidateValidIn := commitRowCandidate.io.rowFillCandidateValid - prereqSnapshot.io.lifecycleRowClearReadyIn := lifecycle.io.rowClearReady - - liveRequest.io.enable := enable - liveRequest.io.flush := flush - liveRequest.io.liveModeEnable := liveModeEnable - liveRequest.io.slotOccupied := slot.io.occupied - liveRequest.io.sideEffectCandidateValid := completion.io.resolveRequired - liveRequest.io.sideEffectRequiredMask := - Cat(completion.io.wakeupRequired, completion.io.writebackRequired, completion.io.resolveRequired) - liveRequest.io.sideEffectSinksReady := prereqSnapshot.io.sideEffectSinksReady - liveRequest.io.clearIntent := false.B - liveRequest.io.clearCommitReady := prereqSnapshot.io.clearCommitReady - liveRequest.io.rowFillCandidateValid := prereqSnapshot.io.rowFillCandidateValid - liveRequest.io.lifecycleRowClearReady := prereqSnapshot.io.lifecycleRowClearReady - liveRequest.io.writeCandidateValid := false.B - liveRequest.io.requestClearIntent := clearIntent.io.clearIntent - liveRequest.io.requestWriteCandidateValid := w1Advance.io.candidateValid - - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestActive := - liveRequest.io.active - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestRequestActive := - liveRequest.io.requestActive - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestEvidenceValid := - liveRequest.io.requestEvidenceValid - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestSideEffectLiveRequested := - liveRequest.io.sideEffectLiveRequested - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestPromotionRequested := - liveRequest.io.promotionRequested - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlocked := - liveRequest.io.blockedByDisabled || - liveRequest.io.blockedByFlush || - liveRequest.io.blockedByModeDisabled || - liveRequest.io.blockedByPolicy || - liveRequest.io.invalidRequestWithoutEvidence - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByRequestDisabled := - liveRequest.io.blockedByModeDisabled || liveRequest.io.blockedByPolicy - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoEvidence := - liveRequest.io.blockedByPolicyNoEvidence || liveRequest.io.invalidRequestWithoutEvidence - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByModeDisabled := - liveRequest.io.blockedByModeDisabled - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByPolicy := - liveRequest.io.blockedByPolicy - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoSideEffectSink := - liveRequest.io.blockedByPolicyNoSideEffectSink - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoClearCommit := - liveRequest.io.blockedByPolicyNoClearCommit - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRowFillCandidate := - liveRequest.io.blockedByPolicyNoRowFillCandidate - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoLifecycleRow := - liveRequest.io.blockedByPolicyNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRequiredSideEffect := - liveRequest.io.blockedByPolicyNoRequiredSideEffect - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleReadyWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - slot: LoadReplayReturnPipeW2Slot, - liq: ReducedLoadReplayLiqAllocPath, - enable: Bool, - flush: Bool): Unit = { - lifecycle.io.enable := enable - lifecycle.io.flush := flush - lifecycle.io.slotOccupied := slot.io.occupied - lifecycle.io.slotBid := slot.io.entryBid - lifecycle.io.slotGid := slot.io.entryGid - lifecycle.io.slotRid := slot.io.entryRid - lifecycle.io.slotLoadLsId := slot.io.entryLoadLsId - lifecycle.io.rows := liq.io.rows - - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCandidateValid := - lifecycle.io.candidateValid - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleSlotIdentityValid := - lifecycle.io.slotIdentityValid - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleResolvedRowMatch := - lifecycle.io.resolvedRowMatch - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleMatchCount := - lifecycle.io.matchCount - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearIndex := - lifecycle.io.rowClearIndex - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearReady := - lifecycle.io.rowClearReady - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleReady := - lifecycle.io.lifecycleReady - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlocked := - lifecycle.io.blockedByDisabled || - lifecycle.io.blockedByFlush || - lifecycle.io.blockedByNoSlot || - lifecycle.io.blockedByInvalidSlotIdentity || - lifecycle.io.blockedByNoResolvedRow || - lifecycle.io.blockedByMultipleResolvedRows || - lifecycle.io.blockedByLifecycleClearDisabled || - lifecycle.io.invalidLifecycleClearWithoutRow - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByNoResolvedRow := - lifecycle.io.blockedByNoResolvedRow - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByMultipleResolvedRows := - lifecycle.io.blockedByMultipleResolvedRows - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByLifecycleClearDisabled := - lifecycle.io.blockedByLifecycleClearDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleRequestControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - control: LoadReplayReturnPipeW2ReplayRowLifecycleRequestControl, - liveRequest: LoadReplayReturnPipeW2AtomicRequestGate, - commitRowCandidate: LoadReplayReturnPipeW2CommitRowCandidate, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - enable: Bool, - flush: Bool): Unit = { - control.io.enable := enable - control.io.flush := flush - control.io.atomicRequestActive := liveRequest.io.requestActive - control.io.rowFillCandidateValid := commitRowCandidate.io.rowFillCandidateValid - control.io.lifecycleRowClearReady := lifecycle.io.rowClearReady - - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlActive := - control.io.active - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlRequestCandidate := - control.io.requestCandidate - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlLifecycleClearRequestEnable := - control.io.lifecycleClearRequestEnable - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlocked := - control.io.blockedByDisabled || - control.io.blockedByFlush || - control.io.blockedByRequestInactive || - control.io.blockedByNoRowFillCandidate || - control.io.blockedByNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByRequestInactive := - control.io.blockedByRequestInactive - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoRowFillCandidate := - control.io.blockedByNoRowFillCandidate - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoLifecycleRow := - control.io.blockedByNoLifecycleRow - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleCommitPermitWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - permit: LoadReplayReturnPipeW2ReplayRowLifecycleCommitPermit, - clearRequest: LoadReplayReturnPipeW2ReplayRowClearRequest, - rowFill: LoadReplayReturnPipeW2RowFillEnableControl, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - enable: Bool, - flush: Bool): Unit = { - permit.io.enable := enable - permit.io.flush := flush - permit.io.lifecycleClearSelected := clearRequest.io.lifecycleClearSelected - permit.io.rowFillEnable := rowFill.io.rowFillEnable - permit.io.rowFillCandidateValid := rowFill.io.candidateValid - permit.io.lifecycleRowClearReady := lifecycle.io.rowClearReady - - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitCandidate := - permit.io.commitCandidate - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitRowFillPermit := - permit.io.rowFillPermit - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitLifecycleClearCommitEnable := - permit.io.lifecycleClearCommitEnable - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlocked := - permit.io.blockedByDisabled || - permit.io.blockedByFlush || - permit.io.blockedByNoSelection || - permit.io.blockedByNoRowFillEnable || - permit.io.blockedByNoRowFillCandidate || - permit.io.blockedByNoLifecycleRow || - permit.io.invalidRowFillWithoutSelection - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoSelection := - permit.io.blockedByNoSelection - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoRowFillEnable := - permit.io.blockedByNoRowFillEnable - io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitInvalidRowFillWithoutSelection := - permit.io.invalidRowFillWithoutSelection - } -} - -private case class LinxCoreFrontendFetchRfAluTraceTopW2Modules( - slot: LoadReplayReturnPipeW2Slot, - completionCandidate: LoadReplayReturnPipeW2CompletionCandidate, - sideEffectReady: LoadReplayReturnPipeW2SideEffectReady, - sideEffectLiveControl: LoadReplayReturnPipeW2SideEffectLiveControl, - atomicLiveRequestControl: LoadReplayReturnPipeW2AtomicRequestGate, - atomicPrereqSnapshot: LoadReplayReturnPipeW2AtomicPrereqSnapshot, - sideEffectCompletionPermit: LoadReplayReturnPipeW2SideEffectCompletionPermit, - sideEffectRequest: LoadReplayReturnPipeW2SideEffectRequest, - resolveRequest: LoadReplayReturnPipeW2ResolveRequest, - writebackRequest: LoadReplayReturnPipeW2WritebackRequest, - wakeupRequest: LoadReplayReturnPipeW2WakeupRequest, - sideEffectPayloadPlan: LoadReplayReturnPipeW2SideEffectPayloadPlan, - sideEffectIssuePermit: LoadReplayReturnPipeW2SideEffectIssuePermit, - sideEffectFireVector: LoadReplayReturnPipeW2SideEffectFireVector, - resolveFirePayload: LoadReplayReturnPipeW2ResolveFirePayload, - resolveArbiterInput: LoadReplayReturnPipeW2ResolveArbiterInput, - robCompleteSource: LoadReplayReturnPipeW2RobCompleteSource, - commitRowCandidate: LoadReplayReturnPipeW2CommitRowCandidate, - retireRecordCommitRowCandidate: LoadReplayReturnPipeW2RetireRecordCommitRowCandidate, - commitRowTraceSource: LoadReplayReturnPipeW2CommitRowTraceSource, - replayRowLifecycleReady: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - replayRowLifecycleRequestControl: LoadReplayReturnPipeW2ReplayRowLifecycleRequestControl, - replayRowLifecycleCommitPermit: LoadReplayReturnPipeW2ReplayRowLifecycleCommitPermit, - replayRowClearRequest: LoadReplayReturnPipeW2ReplayRowClearRequest, - rowFillEnableControl: LoadReplayReturnPipeW2RowFillEnableControl, - writebackFirePayload: LoadReplayReturnPipeW2WritebackFirePayload, - writebackArbiterInput: LoadReplayReturnPipeW2WritebackArbiterInput, - wakeupFirePayload: LoadReplayReturnPipeW2WakeupFirePayload, - wakeupArbiterInput: LoadReplayReturnPipeW2WakeupArbiterInput, - sideEffectFireComplete: LoadReplayReturnPipeW2SideEffectFireComplete, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - postLretEnqueueHold: LoadReplayReturnPipeW2PostLretEnqueueHold, - retireRecord: LoadReplayReturnPipeW2RetireRecord, - retireRecordInstructionMetadata: LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch, - retireRecordLifecycleEvidence: LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch, - retireRecordLifecycleClearFallbackGuard: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - retireRecordFallbackOwnerPolicy: LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy, - retireRecordModelOrderProof: LoadReplayReturnPipeW2RetireRecordModelOrderProof, - retireRecordDefaultPromotionReadiness: LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness, - retireRecordDuplicateVector: LoadReplayReturnPipeW2RetireRecordDuplicateVector, - retireRecordBundleTransferPlan: LoadReplayReturnPipeW2RetireRecordBundleTransferPlan, - retireRecordPhysicalBundleSuppressPlan: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan, - retireRecordPhysicalBundleSuppressProbe: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe, - retireRecordPhysicalBundleSuppressSelect: - LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect, - retireRecordPhysicalBundleSuppressBoundary: LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary, - retireRecordPhysicalBundleSuppressIdentityProof: - LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof, - retireRecordPhysicalBundleSuppressOwnershipBoundary: - LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary, - retireRecordPhysicalBundleSuppressLiveMask: - LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask, - retireRecordPhysicalBundleSuppressClearProof: - LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof, - retireRecordAtomicRequestProbe: LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe, - retireRecordLifecycleRequestProbe: LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe, - retireRecordRowFillEnableControl: LoadReplayReturnPipeW2RetireRecordRowFillEnableControl, - retireRecordRobCompleteFallbackGuard: LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard, - retireRecordRfWritebackFallbackGuard: LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard, - retireRecordWakeupFallbackGuard: LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard, - clearCommitGuard: LoadReplayReturnPipeW2ClearCommitGuard, - promotionControl: LoadReplayReturnPipeW2PromotionControl, - refillReady: LoadReplayReturnPipeW2RefillReady, - slotReplacePlan: LoadReplayReturnPipeW2SlotReplacePlan, - advanceControl: LoadReplayReturnPipeW2AdvanceControl, - resolveSinkReady: LoadReplayReturnPipeW2ResolveSinkReady, - writebackSinkReady: LoadReplayReturnPipeW2WritebackSinkReady, - wakeupSinkReady: LoadReplayReturnPipeW2WakeupSinkReady) - -private object LinxCoreFrontendFetchRfAluTraceTopW2Modules { - def create( - p: InterfaceParams, - traceParams: CommitTraceParams, - storeEntries: Int, - postLretEnqueueHoldCycles: Int): LinxCoreFrontendFetchRfAluTraceTopW2Modules = - LinxCoreFrontendFetchRfAluTraceTopW2Modules( - slot = Module(new LoadReplayReturnPipeW2Slot( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - completionCandidate = Module(new LoadReplayReturnPipeW2CompletionCandidate( - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - sideEffectReady = Module(new LoadReplayReturnPipeW2SideEffectReady), - sideEffectLiveControl = Module(new LoadReplayReturnPipeW2SideEffectLiveControl), - atomicLiveRequestControl = Module(new LoadReplayReturnPipeW2AtomicRequestGate), - atomicPrereqSnapshot = Module(new LoadReplayReturnPipeW2AtomicPrereqSnapshot(idEntries = p.robEntries)), - sideEffectCompletionPermit = Module(new LoadReplayReturnPipeW2SideEffectCompletionPermit), - sideEffectRequest = Module(new LoadReplayReturnPipeW2SideEffectRequest), - resolveRequest = Module(new LoadReplayReturnPipeW2ResolveRequest( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - sizeWidth = p.memSizeWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - writebackRequest = Module(new LoadReplayReturnPipeW2WritebackRequest( - idEntries = p.robEntries, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - wakeupRequest = Module(new LoadReplayReturnPipeW2WakeupRequest( - idEntries = p.robEntries, - pcWidth = p.pcWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - sideEffectPayloadPlan = Module(new LoadReplayReturnPipeW2SideEffectPayloadPlan), - sideEffectIssuePermit = Module(new LoadReplayReturnPipeW2SideEffectIssuePermit), - sideEffectFireVector = Module(new LoadReplayReturnPipeW2SideEffectFireVector), - resolveFirePayload = LinxCoreFrontendFetchRfAluTraceTopW2ResolveFirePayloadModule.create(p), - resolveArbiterInput = Module(new LoadReplayReturnPipeW2ResolveArbiterInput( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - sizeWidth = p.memSizeWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - robCompleteSource = Module(new LoadReplayReturnPipeW2RobCompleteSource( - idEntries = p.robEntries, - traceParams = traceParams - )), - commitRowCandidate = - LinxCoreFrontendFetchRfAluTraceTopW2CommitRowCandidateModule.create(p, traceParams), - retireRecordCommitRowCandidate = - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordCommitRowCandidateModule.create(p, traceParams), - commitRowTraceSource = Module(new LoadReplayReturnPipeW2CommitRowTraceSource(traceParams = traceParams)), - replayRowLifecycleReady = - LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleReadyModule.create(p, storeEntries), - replayRowLifecycleRequestControl = Module(new LoadReplayReturnPipeW2ReplayRowLifecycleRequestControl), - replayRowLifecycleCommitPermit = Module(new LoadReplayReturnPipeW2ReplayRowLifecycleCommitPermit), - replayRowClearRequest = Module(new LoadReplayReturnPipeW2ReplayRowClearRequest( - liqEntries = p.robEntries - )), - rowFillEnableControl = Module(new LoadReplayReturnPipeW2RowFillEnableControl), - writebackFirePayload = LinxCoreFrontendFetchRfAluTraceTopW2WritebackFirePayloadModule.create(p), - writebackArbiterInput = Module(new LoadReplayReturnPipeW2WritebackArbiterInput( - dataWidth = p.immWidth, - physRegWidth = p.physRegWidth - )), - wakeupFirePayload = LinxCoreFrontendFetchRfAluTraceTopW2WakeupFirePayloadModule.create(p), - wakeupArbiterInput = Module(new LoadReplayReturnPipeW2WakeupArbiterInput( - idEntries = p.robEntries, - pcWidth = p.pcWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - sideEffectFireComplete = Module(new LoadReplayReturnPipeW2SideEffectFireComplete), - clearIntent = Module(new LoadReplayReturnPipeW2ClearIntent), - postLretEnqueueHold = Module(new LoadReplayReturnPipeW2PostLretEnqueueHold( - holdCycles = postLretEnqueueHoldCycles)), - retireRecord = Module(new LoadReplayReturnPipeW2RetireRecord( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )), - retireRecordInstructionMetadata = - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordInstructionMetadataLatchModule.create(p, traceParams), - retireRecordLifecycleEvidence = - Module(new LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch(liqEntries = p.robEntries)), - retireRecordLifecycleClearFallbackGuard = - Module(new LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard(liqEntries = p.robEntries)), - retireRecordFallbackOwnerPolicy = - Module(new LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy), - retireRecordModelOrderProof = - Module(new LoadReplayReturnPipeW2RetireRecordModelOrderProof), - retireRecordDefaultPromotionReadiness = - Module(new LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness), - retireRecordDuplicateVector = - Module(new LoadReplayReturnPipeW2RetireRecordDuplicateVector), - retireRecordBundleTransferPlan = - Module(new LoadReplayReturnPipeW2RetireRecordBundleTransferPlan), - retireRecordPhysicalBundleSuppressPlan = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan), - retireRecordPhysicalBundleSuppressProbe = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe), - retireRecordPhysicalBundleSuppressSelect = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect), - retireRecordPhysicalBundleSuppressBoundary = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary), - retireRecordPhysicalBundleSuppressIdentityProof = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof( - idEntries = p.robEntries, - liqEntries = p.robEntries)), - retireRecordPhysicalBundleSuppressOwnershipBoundary = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary( - idEntries = p.robEntries, - liqEntries = p.robEntries)), - retireRecordPhysicalBundleSuppressLiveMask = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask), - retireRecordPhysicalBundleSuppressClearProof = - Module(new LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof), - retireRecordAtomicRequestProbe = Module(new LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe), - retireRecordLifecycleRequestProbe = Module(new LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe), - retireRecordRowFillEnableControl = Module(new LoadReplayReturnPipeW2RetireRecordRowFillEnableControl), - retireRecordRobCompleteFallbackGuard = - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRobCompleteFallbackGuardModule.create(p, traceParams), - retireRecordRfWritebackFallbackGuard = - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRfWritebackFallbackGuardModule.create(p), - retireRecordWakeupFallbackGuard = - LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWakeupFallbackGuardModule.create(p), - clearCommitGuard = Module(new LoadReplayReturnPipeW2ClearCommitGuard(idEntries = p.robEntries)), - promotionControl = Module(new LoadReplayReturnPipeW2PromotionControl), - refillReady = Module(new LoadReplayReturnPipeW2RefillReady), - slotReplacePlan = Module(new LoadReplayReturnPipeW2SlotReplacePlan), - advanceControl = Module(new LoadReplayReturnPipeW2AdvanceControl), - resolveSinkReady = Module(new LoadReplayReturnPipeW2ResolveSinkReady), - writebackSinkReady = Module(new LoadReplayReturnPipeW2WritebackSinkReady), - wakeupSinkReady = Module(new LoadReplayReturnPipeW2WakeupSinkReady) - ) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowLifecycleReadyModule { - def create(p: InterfaceParams, storeEntries: Int): LoadReplayReturnPipeW2ReplayRowLifecycleReady = - Module(new LoadReplayReturnPipeW2ReplayRowLifecycleReady( - liqEntries = p.robEntries, - idEntries = p.robEntries, - storeEntries = storeEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - lineBytes = 64, - sizeWidth = p.memSizeWidth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2CommitRowCandidateModule { - def create( - p: InterfaceParams, - traceParams: CommitTraceParams): LoadReplayReturnPipeW2CommitRowCandidate = - Module(new LoadReplayReturnPipeW2CommitRowCandidate( - idEntries = p.robEntries, - sizeWidth = p.memSizeWidth, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - traceParams = traceParams - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordCommitRowCandidateModule { - def create( - p: InterfaceParams, - traceParams: CommitTraceParams): LoadReplayReturnPipeW2RetireRecordCommitRowCandidate = - Module(new LoadReplayReturnPipeW2RetireRecordCommitRowCandidate( - idEntries = p.robEntries, - addrWidth = p.immWidth, - pcWidth = p.pcWidth, - dataWidth = p.immWidth, - sizeWidth = p.memSizeWidth, - returnPipeCount = 1, - archRegWidth = p.archRegWidth, - physRegWidth = p.physRegWidth, - traceParams = traceParams - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordInstructionMetadataLatchModule { - def create( - p: InterfaceParams, - traceParams: CommitTraceParams): LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch = - Module(new LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch( - idEntries = p.robEntries, - traceParams = traceParams - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRobCompleteFallbackGuardModule { - def create( - p: InterfaceParams, - traceParams: CommitTraceParams): LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard = - Module(new LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard( - idEntries = p.robEntries, - traceParams = traceParams - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordRfWritebackFallbackGuardModule { - def create(p: InterfaceParams): LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard = - Module(new LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard( - idEntries = p.robEntries, - dataWidth = p.immWidth, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RetireRecordWakeupFallbackGuardModule { - def create(p: InterfaceParams): LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard = - Module(new LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard( - idEntries = p.robEntries, - physRegWidth = p.physRegWidth - )) -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2ReplayRowClearRequestWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - clearRequest: LoadReplayReturnPipeW2ReplayRowClearRequest, - lifecycleRequest: LoadReplayReturnPipeW2ReplayRowLifecycleRequestControl, - lifecycleCommitPermit: LoadReplayReturnPipeW2ReplayRowLifecycleCommitPermit, - lifecycle: LoadReplayReturnPipeW2ReplayRowLifecycleReady, - retainedFallback: LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard, - liq: ReducedLoadReplayLiqAllocPath, - existingClearValid: Bool, - existingClearIndex: UInt, - retainedFallbackLiveProbe: Bool, - suppressPhysicalLifecycleClear: Bool, - enable: Bool, - flush: Bool): Unit = { - val retainedFallbackClearValid = retainedFallbackLiveProbe && retainedFallback.io.fallbackClearValid - val physicalLifecycleClearAllowed = !suppressPhysicalLifecycleClear - clearRequest.io.enable := enable - clearRequest.io.flush := flush - clearRequest.io.existingClearValid := existingClearValid - clearRequest.io.existingClearIndex := existingClearIndex - clearRequest.io.lifecycleClearRequestEnable := - lifecycleRequest.io.lifecycleClearRequestEnable && physicalLifecycleClearAllowed - clearRequest.io.lifecycleClearCommitEnable := - lifecycleCommitPermit.io.lifecycleClearCommitEnable && physicalLifecycleClearAllowed - clearRequest.io.lifecycleRowClearReady := lifecycle.io.rowClearReady - clearRequest.io.lifecycleRowClearIndex := lifecycle.io.rowClearIndex - clearRequest.io.clearResolvedAccepted := liq.io.clearResolvedAccepted && !retainedFallbackClearValid - - liq.io.clearResolvedValid := clearRequest.io.clearResolvedValid || retainedFallbackClearValid - liq.io.clearResolvedIndex := - Mux(retainedFallbackClearValid, retainedFallback.io.fallbackClearIndex, clearRequest.io.clearResolvedIndex) - lifecycle.io.lifecycleClearEnable := - clearRequest.io.lifecycleClearEnable && !retainedFallbackClearValid && physicalLifecycleClearAllowed - - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingCandidate := - clearRequest.io.existingClearCandidate - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleCandidate := - clearRequest.io.lifecycleClearCandidate - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleClearEnable := - clearRequest.io.lifecycleClearEnable - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleSelected := - clearRequest.io.lifecycleClearSelected - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedValid := - clearRequest.io.clearResolvedValid - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedIndex := - clearRequest.io.clearResolvedIndex - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingAccepted := - clearRequest.io.existingClearAccepted - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleAccepted := - clearRequest.io.lifecycleClearAccepted - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlocked := - clearRequest.io.blockedByDisabled || - clearRequest.io.blockedByFlush || - clearRequest.io.blockedByExistingClear || - clearRequest.io.blockedByLifecycleRequestDisabled || - clearRequest.io.blockedByNoLifecycleRow || - clearRequest.io.blockedByLifecycleCommitDisabled || - clearRequest.io.invalidLifecycleCommitWithoutSelection - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByExistingClear := - clearRequest.io.blockedByExistingClear - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleRequestDisabled := - clearRequest.io.blockedByLifecycleRequestDisabled - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByNoLifecycleRow := - clearRequest.io.blockedByNoLifecycleRow - io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleCommitDisabled := - clearRequest.io.blockedByLifecycleCommitDisabled - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopStoreLookupWiring { - def connect( - overlay: ReducedStoreMemoryOverlay, - residentForward: ReducedStoreResidentForward, - lookupArbiter: LoadLookupArbiter, - liq: ReducedLoadReplayLiqAllocPath, - execute: ReducedScalarAluExecute, - executeLoadLsId: ROBID, - path: DecodeRenameROBPath, - storeReqs: Vec[STQCommitDrainRequest], - storeAcceptedMask: UInt, - baseLoadData: UInt, - flush: Bool, - enable: Bool): Unit = { - val lookupIsReplay = lookupArbiter.io.replayGranted - val lookupValid = enable && lookupArbiter.io.lookupValid - val lookupSize = Mux(lookupIsReplay, liq.io.launchSelectedSize, execute.io.loadLookupSize) - val lookupBid = Mux(lookupIsReplay, liq.io.launchSelectedBid, execute.io.loadLookupBid) - val lookupLsId = Mux(lookupIsReplay, liq.io.launchSelectedLoadLsId, executeLoadLsId) - val replayRow = liq.io.rows(liq.io.launchIndex) - val lookupLsIdFullValid = Mux( - lookupIsReplay, - replayRow.youngestStoreLsIdFullValid, - execute.io.loadLookupValid) - val lookupLsIdFull = Mux( - lookupIsReplay, - replayRow.youngestStoreLsIdFull, - execute.io.loadLookupLsId) - - overlay.io.flush := flush - overlay.io.storeReqs := storeReqs - overlay.io.storeAcceptedMask := storeAcceptedMask - overlay.io.loadValid := lookupValid - overlay.io.loadAddr := lookupArbiter.io.lookupAddr - overlay.io.baseLoadData := baseLoadData - - residentForward.io.enable := enable - residentForward.io.loadValid := lookupValid - residentForward.io.loadAddr := lookupArbiter.io.lookupAddr - residentForward.io.loadSize := lookupSize - residentForward.io.loadBid := lookupBid - residentForward.io.loadLsId := lookupLsId - residentForward.io.loadLsIdFullValid := lookupLsIdFullValid - residentForward.io.loadLsIdFull := lookupLsIdFull - residentForward.io.baseLoadData := overlay.io.loadData - residentForward.io.rows := path.io.storeStqRows - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopScalarLrReservationWiring { - private def lineAddr(addr: UInt, width: Int): UInt = - Cat(addr(width - 1, 6), 0.U(6.W)) - - private def robIdToReducedLrBid(id: ROBID, robIndexWidth: Int): UInt = - Cat(0.U((64 - robIndexWidth - 1).W), id.wrap, id.value) - - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - owner: ScalarLrScReservationOwner, - arbiter: ReducedRobCompletionArbiter, - execute: ReducedScalarAluExecute, - robCompleteAccepted: Bool, - acceptedRecoveryFlush: FlushBus, - reducedStoreMemoryReqs: Vec[STQCommitDrainRequest], - reducedStoreMemoryAcceptedVec: Vec[Bool], - reducedStoreMemoryRequestCount: Int, - scalarScIssueFire: Bool, - scalarScIssueStid: UInt, - scalarScIssueLineAddr: UInt, - scalarScIssueData: UInt, - scalarScIssueBid: ROBID, - scalarScIssueGid: ROBID, - scalarScIssueRid: ROBID, - scalarScIssueLsId: UInt, - scalarScCommitReady: Bool, - coreParams: CoreParams, - p: InterfaceParams): Unit = { - val scalarLrInsn = - (execute.io.completeRow.insn(31, 0) & "hf000707f".U(32.W)) === "h2000000b".U(32.W) - val scalarLrSetCandidate = - execute.io.completeFire && - execute.io.completeRow.mem.valid && - !execute.io.completeRow.mem.isStore && - execute.io.completeRow.mem.size === 4.U && - scalarLrInsn - val scalarLrSetAccepted = scalarLrSetCandidate && arbiter.io.selectedExecute && robCompleteAccepted - val scalarLrLineAddr = lineAddr(execute.io.completeRow.mem.addr, p.immWidth) - val scalarLrCommittedStoreInvalidateMask = - VecInit((0 until reducedStoreMemoryRequestCount).map(idx => - reducedStoreMemoryAcceptedVec(idx) && reducedStoreMemoryReqs(idx).valid)).asUInt - val scalarLrCommittedStoreInvalidate = scalarLrCommittedStoreInvalidateMask.orR - val scalarLrCommittedStoreInvalidateReq = - reducedStoreMemoryReqs(PriorityEncoder(scalarLrCommittedStoreInvalidateMask)) - val scalarLrCommittedStoreInvalidateReg = RegInit(false.B) - val scalarLrCommittedStoreInvalidateReqReg = - Reg(chiselTypeOf(scalarLrCommittedStoreInvalidateReq)) - when(io.startValid || io.restartValid || acceptedRecoveryFlush.req.valid) { - scalarLrCommittedStoreInvalidateReg := false.B - scalarLrCommittedStoreInvalidateReqReg := 0.U.asTypeOf(scalarLrCommittedStoreInvalidateReqReg) - }.otherwise { - scalarLrCommittedStoreInvalidateReg := scalarLrCommittedStoreInvalidate - scalarLrCommittedStoreInvalidateReqReg := scalarLrCommittedStoreInvalidateReq - } - - owner.io.enable := true.B - owner.io.contextInvalidate := io.startValid || io.restartValid - owner.io.flushAll := io.startValid || io.restartValid - owner.io.flushValid := acceptedRecoveryFlush.req.valid - owner.io.flushStid := acceptedRecoveryFlush.req.stid - owner.io.flushIdentityValid := acceptedRecoveryFlush.req.valid - owner.io.flushIdentity.bid := robIdToReducedLrBid(acceptedRecoveryFlush.req.bid, p.robIndexWidth) - owner.io.flushIdentity.gid := acceptedRecoveryFlush.req.gid - owner.io.flushIdentity.rid := acceptedRecoveryFlush.req.rid - owner.io.flushIdentity.lsIdFull := acceptedRecoveryFlush.req.lsIdFull - - owner.io.lrCompleteValid := scalarLrSetCandidate - owner.io.lrCompleteAccepted := scalarLrSetAccepted - owner.io.lrStid := execute.io.releaseStid - owner.io.lrLineAddr := scalarLrLineAddr - owner.io.lrSize := 4.U(coreParams.scalarLsu.loadSizeWidth.W) - owner.io.lrRawData := execute.io.completeRow.mem.rdata - owner.io.lrIdentity.bid := robIdToReducedLrBid(execute.io.releaseBid, p.robIndexWidth) - owner.io.lrIdentity.gid := execute.io.releaseGid - owner.io.lrIdentity.rid := execute.io.releaseRid - owner.io.lrIdentity.lsIdFull := execute.io.completeLsId - - owner.io.scReqValid := scalarScIssueFire - owner.io.scReqStid := scalarScIssueStid - owner.io.scReqLineAddr := scalarScIssueLineAddr - owner.io.scReqSize := 4.U(coreParams.scalarLsu.loadSizeWidth.W) - owner.io.scReqData := scalarScIssueData - owner.io.scReqIdentity.bid := robIdToReducedLrBid(scalarScIssueBid, p.robIndexWidth) - owner.io.scReqIdentity.gid := scalarScIssueGid - owner.io.scReqIdentity.rid := scalarScIssueRid - owner.io.scReqIdentity.lsIdFull := scalarScIssueLsId - owner.io.scCommitReady := scalarScCommitReady - owner.io.committedStoreInvalidateValid := scalarLrCommittedStoreInvalidateReg - owner.io.committedStoreInvalidateStid := scalarLrCommittedStoreInvalidateReqReg.stid - owner.io.committedStoreInvalidateLineAddr := lineAddr(scalarLrCommittedStoreInvalidateReqReg.addr, p.immWidth) - - io.scalarLrReservationSetCandidate := scalarLrSetCandidate - io.scalarLrReservationSetAccepted := owner.io.lrSetAccepted - io.scalarLrReservationSetStid := execute.io.releaseStid - io.scalarLrReservationSetLineAddr := scalarLrLineAddr - io.scalarLrReservationSetRidValid := execute.io.releaseRid.valid - io.scalarLrReservationSetRidWrap := execute.io.releaseRid.wrap - io.scalarLrReservationSetRidValue := execute.io.releaseRid.value - io.scalarLrReservationValidStid0 := owner.io.reservationValidByStid(0) - io.scalarLrReservationLineStid0 := owner.io.reservationLineByStid(0) - io.scalarLrReservationCount := owner.io.reservationCount - io.scalarLrReservationProtocolError := owner.io.protocolError - io.scalarLrReservationBlockedByFlush := owner.io.blockedByFlush - io.scalarLrReservationCommittedStoreInvalidate := scalarLrCommittedStoreInvalidate - } -} - -final case class ScalarScIssueGate(candidate: Bool, ready: Bool) - -private object LinxCoreFrontendFetchRfAluTraceTopScalarScIssueWiring { - def connect( - issue: ScalarIssueFabric, - path: DecodeRenameROBPath, - storeStaAddressExecBridge: ReducedStoreStaAddressExecBridge, - owner: ScalarLrScReservationOwner, - issueFire: Bool, - issueAddr: UInt, - issueData: UInt, - issueUop: linxcore.common.RenamedUop, - p: InterfaceParams): ScalarScIssueGate = { - val scalarScOpcode = FrontendOpcodeDecodeTable.OP_SC_W.U(p.opcodeWidth.W) - val candidate = - issue.io.issueValid && issue.io.issueUop.opcode === scalarScOpcode - val atCommitHead = - path.io.commitHeadValid && candidate && - path.io.commitHeadStid === issue.io.issueUop.threadId && - issue.io.issueUop.bid.valid && issue.io.issueUop.gid.valid && issue.io.issueUop.rid.valid && - path.io.commitHeadBid.valid && path.io.commitHeadGid.valid && path.io.commitHeadRid.valid && - ROBID.equal(path.io.commitHeadBid, issue.io.issueUop.bid) && - ROBID.equal(path.io.commitHeadGid, issue.io.issueUop.gid) && - ROBID.equal(path.io.commitHeadRid, issue.io.issueUop.rid) - val storeQueueMatches = - path.io.storeStaQueueValid && path.io.storeStaQueue.valid && - path.io.storeStaQueue.uop.opcode === scalarScOpcode && - path.io.storeStaQueue.uop.threadId === issue.io.issueUop.threadId && - ROBID.equal(path.io.storeStaQueue.uop.bid, issue.io.issueUop.bid) && - ROBID.equal(path.io.storeStaQueue.uop.gid, issue.io.issueUop.gid) && - ROBID.equal(path.io.storeStaQueue.uop.rid, issue.io.issueUop.rid) && - path.io.storeStaQueue.uop.lsid === issue.io.issueUop.lsid - val addressReady = storeStaAddressExecBridge.io.exec.valid && storeQueueMatches - val ready = owner.io.scReqReady && atCommitHead && addressReady - - issueFire := issue.io.issueFire && candidate - issueAddr := storeStaAddressExecBridge.io.exec.addr - issueData := storeStaAddressExecBridge.io.exec.data - issueUop := issue.io.issueUop - - ScalarScIssueGate(candidate, ready) - } -} - -final case class ServiceStopMetadata(issueCandidate: Bool, stopAdjacent: Bool, nextStopInsn: UInt, nextStopLen: UInt) - -private object LinxCoreFrontendFetchRfAluTraceTopServiceStopMetadataWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - issue: ScalarIssueFabric, - servicePath: ReducedServiceRequestPath, - serviceOpcode: UInt, - serviceEnqueueFire: Bool, - acceptedMarkerDrainFire: Bool, - backendPipeFlush: Bool): ServiceStopMetadata = { - val p = path.p - val latestStopValid = RegInit(false.B) - val latestStopPc = RegInit(0.U(p.pcWidth.W)) - val latestStopInsn = RegInit(0.U(p.insnWidth.W)) - val latestStopLen = RegInit(0.U(p.lenWidth.W)) - val latestStopStid = RegInit(0.U(p.threadIdWidth.W)) - val latestStopBlockBidValid = RegInit(false.B) - val latestStopBlockBid = RegInit(0.U(p.blockBidWidth.W)) - val serviceDecodeStopPendingValid = RegInit(false.B) - val serviceDecodeStopPendingPc = RegInit(0.U(p.pcWidth.W)) - val serviceDecodeStopPendingInsn = RegInit(0.U(p.insnWidth.W)) - val serviceDecodeStopPendingLen = RegInit(0.U(p.lenWidth.W)) - val serviceDecodeStopPendingStid = RegInit(0.U(p.threadIdWidth.W)) - val serviceDecodeStopPendingBid = RegInit(ROBID.disabled(p.robEntries)) - val serviceDecodeStopPendingGid = RegInit(ROBID.disabled(p.robEntries)) - val serviceDecodeStopPendingRid = RegInit(ROBID.disabled(p.robEntries)) - val serviceDecodeStopPendingBlockBidValid = RegInit(false.B) - val serviceDecodeStopPendingBlockBid = RegInit(0.U(p.blockBidWidth.W)) - val serviceQueuedStopValid = RegInit(false.B) - val serviceQueuedStopPc = RegInit(0.U(p.pcWidth.W)) - val serviceQueuedStopInsn = RegInit(0.U(p.insnWidth.W)) - val serviceQueuedStopLen = RegInit(0.U(p.lenWidth.W)) - val serviceQueuedStopStid = RegInit(0.U(p.threadIdWidth.W)) - val serviceQueuedStopBid = RegInit(ROBID.disabled(p.robEntries)) - val serviceQueuedStopGid = RegInit(ROBID.disabled(p.robEntries)) - val serviceQueuedStopRid = RegInit(ROBID.disabled(p.robEntries)) - val serviceQueuedStopBlockBidValid = RegInit(false.B) - val serviceQueuedStopBlockBid = RegInit(0.U(p.blockBidWidth.W)) - val acceptedServiceStopMarkerFire = acceptedMarkerDrainFire && path.io.blockMarkerStop - val serviceMetadataFlush = backendPipeFlush || io.startValid || io.restartValid || io.frontendFlushValid - - when(serviceMetadataFlush) { - latestStopValid := false.B - latestStopPc := 0.U - latestStopInsn := 0.U - latestStopLen := 0.U - latestStopStid := 0.U - latestStopBlockBidValid := false.B - latestStopBlockBid := 0.U - serviceDecodeStopPendingValid := false.B - serviceDecodeStopPendingPc := 0.U - serviceDecodeStopPendingInsn := 0.U - serviceDecodeStopPendingLen := 0.U - serviceDecodeStopPendingStid := 0.U - serviceDecodeStopPendingBid := ROBID.disabled(p.robEntries) - serviceDecodeStopPendingGid := ROBID.disabled(p.robEntries) - serviceDecodeStopPendingRid := ROBID.disabled(p.robEntries) - serviceDecodeStopPendingBlockBidValid := false.B - serviceDecodeStopPendingBlockBid := 0.U - serviceQueuedStopValid := false.B - serviceQueuedStopPc := 0.U - serviceQueuedStopInsn := 0.U - serviceQueuedStopLen := 0.U - serviceQueuedStopStid := 0.U - serviceQueuedStopBid := ROBID.disabled(p.robEntries) - serviceQueuedStopGid := ROBID.disabled(p.robEntries) - serviceQueuedStopRid := ROBID.disabled(p.robEntries) - serviceQueuedStopBlockBidValid := false.B - serviceQueuedStopBlockBid := 0.U - }.elsewhen(acceptedServiceStopMarkerFire) { - latestStopValid := true.B - latestStopPc := path.io.blockMarkerPc - latestStopInsn := path.io.blockMarkerInsn - latestStopLen := path.io.blockMarkerLen - latestStopStid := io.threadId - latestStopBlockBidValid := path.io.blockMarkerActiveValid - latestStopBlockBid := path.io.blockMarkerActiveBid - } - - val liveMatches = - path.io.serviceAdjacentStop.valid && - path.io.serviceAdjacentStop.stid === issue.io.inputAcceptUop.threadId && - path.io.serviceAdjacentStop.bid.valid && path.io.serviceAdjacentStop.gid.valid && - path.io.serviceAdjacentStop.rid.valid && - ROBID.equal(path.io.serviceAdjacentStop.bid, issue.io.inputAcceptUop.bid) && - ROBID.equal(path.io.serviceAdjacentStop.gid, issue.io.inputAcceptUop.gid) && - ROBID.equal(path.io.serviceAdjacentStop.rid, issue.io.inputAcceptUop.rid) && - path.io.serviceAdjacentStop.blockBidValid && issue.io.inputAcceptUop.blockBidValid && - path.io.serviceAdjacentStop.blockBid === issue.io.inputAcceptUop.blockBid && - path.io.serviceAdjacentStop.pc === (issue.io.inputAcceptUop.pc + issue.io.inputAcceptUop.insnLen) - val pendingMatches = - serviceDecodeStopPendingValid && - serviceDecodeStopPendingStid === issue.io.inputAcceptUop.threadId && - serviceDecodeStopPendingBid.valid && serviceDecodeStopPendingGid.valid && - serviceDecodeStopPendingRid.valid && - ROBID.equal(serviceDecodeStopPendingBid, issue.io.inputAcceptUop.bid) && - ROBID.equal(serviceDecodeStopPendingGid, issue.io.inputAcceptUop.gid) && - ROBID.equal(serviceDecodeStopPendingRid, issue.io.inputAcceptUop.rid) && - serviceDecodeStopPendingBlockBidValid && issue.io.inputAcceptUop.blockBidValid && - serviceDecodeStopPendingBlockBid === issue.io.inputAcceptUop.blockBid && - serviceDecodeStopPendingPc === (issue.io.inputAcceptUop.pc + issue.io.inputAcceptUop.insnLen) - val enqueueAdjacentStop = serviceEnqueueFire && (liveMatches || pendingMatches) - val enqueueFromLive = serviceEnqueueFire && liveMatches - val enqueuePc = Mux(enqueueFromLive, path.io.serviceAdjacentStop.pc, serviceDecodeStopPendingPc) - val enqueueInsn = Mux(enqueueFromLive, path.io.serviceAdjacentStop.insn, serviceDecodeStopPendingInsn) - val enqueueLen = Mux(enqueueFromLive, path.io.serviceAdjacentStop.len, serviceDecodeStopPendingLen) - val enqueueStid = Mux(enqueueFromLive, path.io.serviceAdjacentStop.stid, serviceDecodeStopPendingStid) - val enqueueBid = Mux(enqueueFromLive, path.io.serviceAdjacentStop.bid, serviceDecodeStopPendingBid) - val enqueueGid = Mux(enqueueFromLive, path.io.serviceAdjacentStop.gid, serviceDecodeStopPendingGid) - val enqueueRid = Mux(enqueueFromLive, path.io.serviceAdjacentStop.rid, serviceDecodeStopPendingRid) - val enqueueBlockBidValid = - Mux(enqueueFromLive, path.io.serviceAdjacentStop.blockBidValid, serviceDecodeStopPendingBlockBidValid) - val enqueueBlockBid = - Mux(enqueueFromLive, path.io.serviceAdjacentStop.blockBid, serviceDecodeStopPendingBlockBid) - - when(!serviceMetadataFlush && path.io.serviceAdjacentStop.valid) { - serviceDecodeStopPendingValid := true.B - serviceDecodeStopPendingPc := path.io.serviceAdjacentStop.pc - serviceDecodeStopPendingInsn := path.io.serviceAdjacentStop.insn - serviceDecodeStopPendingLen := path.io.serviceAdjacentStop.len - serviceDecodeStopPendingStid := path.io.serviceAdjacentStop.stid - serviceDecodeStopPendingBid := path.io.serviceAdjacentStop.bid - serviceDecodeStopPendingGid := path.io.serviceAdjacentStop.gid - serviceDecodeStopPendingRid := path.io.serviceAdjacentStop.rid - serviceDecodeStopPendingBlockBidValid := path.io.serviceAdjacentStop.blockBidValid - serviceDecodeStopPendingBlockBid := path.io.serviceAdjacentStop.blockBid - }.elsewhen(serviceEnqueueFire && pendingMatches) { - serviceDecodeStopPendingValid := false.B - } - - when(enqueueAdjacentStop) { - serviceQueuedStopValid := true.B - serviceQueuedStopPc := enqueuePc - serviceQueuedStopInsn := enqueueInsn - serviceQueuedStopLen := enqueueLen - serviceQueuedStopStid := enqueueStid - serviceQueuedStopBid := enqueueBid - serviceQueuedStopGid := enqueueGid - serviceQueuedStopRid := enqueueRid - serviceQueuedStopBlockBidValid := enqueueBlockBidValid - serviceQueuedStopBlockBid := enqueueBlockBid - }.elsewhen(servicePath.io.issueReady) { - serviceQueuedStopValid := false.B - } - - val issueCandidate = issue.io.issueValid && issue.io.issueUop.opcode === serviceOpcode - val queuedMatches = - serviceQueuedStopValid && - serviceQueuedStopStid === issue.io.issueUop.threadId && - serviceQueuedStopBid.valid && serviceQueuedStopGid.valid && serviceQueuedStopRid.valid && - ROBID.equal(serviceQueuedStopBid, issue.io.issueUop.bid) && - ROBID.equal(serviceQueuedStopGid, issue.io.issueUop.gid) && - ROBID.equal(serviceQueuedStopRid, issue.io.issueUop.rid) && - serviceQueuedStopBlockBidValid && issue.io.issueUop.blockBidValid && - serviceQueuedStopBlockBid === issue.io.issueUop.blockBid && - serviceQueuedStopPc === (issue.io.issueUop.pc + issue.io.issueUop.insnLen) - val acceptedMarkerMatches = - latestStopValid && - latestStopStid === issue.io.issueUop.threadId && - latestStopBlockBidValid && issue.io.issueUop.blockBidValid && - latestStopBlockBid === issue.io.issueUop.blockBid && - latestStopPc === (issue.io.issueUop.pc + issue.io.issueUop.insnLen) - - ServiceStopMetadata( - issueCandidate, - queuedMatches || acceptedMarkerMatches, - Mux(queuedMatches, serviceQueuedStopInsn, latestStopInsn), - Mux(queuedMatches, serviceQueuedStopLen, latestStopLen)) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopIssueReleaseWiring { - def connect( - issue: ScalarIssueFabric, - execute: ReducedScalarAluExecute, - servicePath: ReducedServiceRequestPath, - scalarScReleaseValid: Bool, - scalarScReleaseBid: ROBID, - scalarScReleaseRid: ROBID, - scalarScReleaseStid: UInt, - controlFence: ScalarIssueExternalControlFence, - clearControlFence: Bool): Unit = { - issue.io.releaseValid := execute.io.releaseValid - issue.io.releaseBid := execute.io.releaseBid - issue.io.releaseRid := execute.io.releaseRid - issue.io.releaseStid := execute.io.releaseStid - val serviceOrScReleaseValid = servicePath.io.releaseValid || scalarScReleaseValid - issue.io.secondaryReleaseValid := execute.io.liqReleaseValid || serviceOrScReleaseValid - issue.io.secondaryReleaseBid := - Mux( - execute.io.liqReleaseValid, - execute.io.liqReleaseBid, - Mux(servicePath.io.releaseValid, servicePath.io.releaseBid, scalarScReleaseBid)) - issue.io.secondaryReleaseRid := - Mux( - execute.io.liqReleaseValid, - execute.io.liqReleaseRid, - Mux(servicePath.io.releaseValid, servicePath.io.releaseRid, scalarScReleaseRid)) - issue.io.secondaryReleaseStid := - Mux( - execute.io.liqReleaseValid, - execute.io.liqReleaseStid, - Mux(servicePath.io.releaseValid, servicePath.io.releaseStid, scalarScReleaseStid)) - issue.io.tertiaryReleaseValid := execute.io.earlyReleaseValid - issue.io.tertiaryReleaseBid := execute.io.earlyReleaseBid - issue.io.tertiaryReleaseRid := execute.io.earlyReleaseRid - issue.io.tertiaryReleaseStid := execute.io.earlyReleaseStid - controlFence.io.captureValid := execute.io.redirectValid - controlFence.io.captureBid := execute.io.releaseBid - controlFence.io.captureRid := execute.io.releaseRid - controlFence.io.captureStid := execute.io.releaseStid - controlFence.io.clear := clearControlFence - issue.io.externalControlFenceValid := controlFence.io.valid - issue.io.externalControlFenceBid := controlFence.io.bid - issue.io.externalControlFenceRid := controlFence.io.rid - issue.io.externalControlFenceStid := controlFence.io.stid - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopServicePathWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - issue: ScalarIssueFabric, - execute: ReducedScalarAluExecute, - servicePath: ReducedServiceRequestPath, - serviceEnqueueFire: Bool, - serviceIssueCandidate: Bool, - serviceStopAdjacent: Bool, - latestStopInsn: UInt, - latestStopLen: UInt, - backendPipeFlush: Bool, - serviceHigherPriorityRobCompleteIdle: Bool, - serviceHigherPriorityWritebackIdle: Bool): Unit = { - servicePath.io.enqueueValid := serviceEnqueueFire - servicePath.io.enqueueIdentity.stid := issue.io.inputAcceptUop.threadId - servicePath.io.enqueueIdentity.bid := issue.io.inputAcceptUop.bid - servicePath.io.enqueueIdentity.gid := issue.io.inputAcceptUop.gid - servicePath.io.enqueueIdentity.rid := issue.io.inputAcceptUop.rid - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A0Index) := path.io.templateSmapSnapshot(2) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A1Index) := path.io.templateSmapSnapshot(3) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A2Index) := path.io.templateSmapSnapshot(4) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A3Index) := path.io.templateSmapSnapshot(5) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A4Index) := path.io.templateSmapSnapshot(6) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A5Index) := path.io.templateSmapSnapshot(7) - servicePath.io.enqueuePhysTags(ReducedServiceRequestPath.A7Index) := path.io.templateSmapSnapshot(9) - servicePath.io.issueValid := serviceIssueCandidate - servicePath.io.issue.pc := issue.io.issueUop.pc - servicePath.io.issue.insnLen := issue.io.issueUop.insnLen - servicePath.io.issue.insnRaw := issue.io.issueUop.insnRaw - servicePath.io.issue.nextInsnLen := Mux(serviceStopAdjacent, latestStopLen, 0.U) - servicePath.io.issue.nextHalfword := Mux(serviceStopAdjacent, latestStopInsn(15, 0), 0.U) - servicePath.io.issue.nextInsnRaw := Mux(serviceStopAdjacent, latestStopInsn, 0.U) - servicePath.io.issue.identity.stid := issue.io.issueUop.threadId - servicePath.io.issue.identity.bid := issue.io.issueUop.bid - servicePath.io.issue.identity.gid := issue.io.issueUop.gid - servicePath.io.issue.identity.rid := issue.io.issueUop.rid - servicePath.io.atCommitHead := - path.io.commitHeadValid && serviceIssueCandidate && - path.io.commitHeadStid === issue.io.issueUop.threadId && - issue.io.issueUop.bid.valid && issue.io.issueUop.gid.valid && issue.io.issueUop.rid.valid && - path.io.commitHeadBid.valid && path.io.commitHeadGid.valid && path.io.commitHeadRid.valid && - ROBID.equal(path.io.commitHeadBid, issue.io.issueUop.bid) && - ROBID.equal(path.io.commitHeadGid, issue.io.issueUop.gid) && - ROBID.equal(path.io.commitHeadRid, issue.io.issueUop.rid) - servicePath.io.serviceRequest <> io.reducedServiceRequest - servicePath.io.serviceResponse <> io.reducedServiceResponse - servicePath.io.flush := backendPipeFlush || io.startValid || io.restartValid || io.frontendFlushValid - servicePath.io.completeReady := serviceHigherPriorityRobCompleteIdle - servicePath.io.releaseReady := !execute.io.liqReleaseValid - servicePath.io.writebackReady := serviceHigherPriorityWritebackIdle - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopServiceRfReadWiring { - def connect( - rf: ScalarGPRFile, - servicePath: ReducedServiceRequestPath, - serviceRfReadPort: Int): Unit = { - rf.io.readValid(serviceRfReadPort) := servicePath.io.rfReadValid - rf.io.readTag(serviceRfReadPort) := servicePath.io.rfReadTag - servicePath.io.rfReadReady := rf.io.readReady(serviceRfReadPort) - servicePath.io.rfReadData := rf.io.readData(serviceRfReadPort) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopRfReadWiring { - def connect( - rf: ScalarGPRFile, - issue: ScalarIssueFabric, - path: DecodeRenameROBPath, - storeStaAddressExecBridge: ReducedStoreStaAddressExecBridge, - scalarSpOrder: ScalarSpOrderOwner, - localTData: Vec[UInt], - localUData: Vec[UInt], - localTReady: Vec[Bool], - localUReady: Vec[Bool], - gprReadPorts: Int, - storeDispatchReadEnable: Bool, - scalarStidCount: Int): Unit = { - def stidIndex(stid: UInt): UInt = { - val width = math.max(1, log2Ceil(scalarStidCount)) - if (scalarStidCount == 1) 0.U(width.W) else stid(width - 1, 0) - } - - val staReadScalarSpAccess = ScalarSpAccess.classify(path.io.storeStaQueue.uop) - val staReadScalarSpStid = stidIndex(path.io.storeStaQueue.uop.threadId) - val staReadScalarSpGrant = - !staReadScalarSpAccess.valid || - (scalarSpOrder.io.issueHeadValidByStid(staReadScalarSpStid) && - ROBID.equal(path.io.storeStaQueue.uop.bid, scalarSpOrder.io.issueHeadBidByStid(staReadScalarSpStid)) && - ROBID.equal(path.io.storeStaQueue.uop.rid, scalarSpOrder.io.issueHeadRidByStid(staReadScalarSpStid))) - - for (idx <- 0 until 3) { - val readIsT = issue.io.readValid(idx) && (issue.io.readOperandClass(idx) === OperandClass.T) - val readIsU = issue.io.readValid(idx) && (issue.io.readOperandClass(idx) === OperandClass.U) - val readIsLocal = readIsT || readIsU - val readIsScalarSp = - issue.io.readValid(idx) && - (issue.io.readOperandClass(idx) === OperandClass.P) && - (issue.io.readRelTag(idx) === 1.U) - val rel = issue.io.readRelTag(idx)(1, 0) - val localReadData = Mux(readIsT, localTData(rel), localUData(rel)) - val scalarReadData = Mux(readIsScalarSp, issue.io.scalarSpReadSnapshot, rf.io.readData(idx)) - val staSrc = path.io.storeStaQueue.uop.src(idx) - val staReadValid = - storeDispatchReadEnable && path.io.storeStaQueueValid && path.io.storeStaQueue.valid && staSrc.valid - val staReadIsT = staReadValid && (staSrc.operandClass === OperandClass.T) - val staReadIsU = staReadValid && (staSrc.operandClass === OperandClass.U) - val staReadIsLocal = staReadIsT || staReadIsU - val staReadIsScalarSp = - staReadValid && - (staSrc.operandClass === OperandClass.P) && - (staSrc.relTag === 1.U) - val staReadIsRf = - staReadValid && - (staSrc.operandClass === OperandClass.P) && - !staReadIsScalarSp - val staRel = staSrc.relTag(1, 0) - val staLocalReadReady = Mux(staReadIsT, localTReady(staRel), Mux(staReadIsU, localUReady(staRel), false.B)) - val staLocalReadData = Mux(staReadIsT, localTData(staRel), localUData(staRel)) - val staScalarSpSnapshot = scalarSpOrder.io.issueSnapshotByStid(staReadScalarSpStid) - - rf.io.readValid(idx) := issue.io.readValid(idx) && !readIsLocal - rf.io.readTag(idx) := issue.io.readTags(idx) - rf.io.readValid(idx + gprReadPorts) := staReadIsRf - rf.io.readTag(idx + gprReadPorts) := staSrc.physTag - issue.io.readData(idx) := Mux(readIsLocal, localReadData, scalarReadData) - storeStaAddressExecBridge.io.srcReadReady(idx) := - Mux(staReadIsLocal, staLocalReadReady, - Mux(staReadIsScalarSp, staReadScalarSpGrant, rf.io.readReady(idx + gprReadPorts))) - storeStaAddressExecBridge.io.srcReadData(idx) := - Mux(staReadIsLocal, staLocalReadData, - Mux(staReadIsScalarSp, staScalarSpSnapshot, rf.io.readData(idx + gprReadPorts))) - } - for (idx <- 3 until gprReadPorts) { - rf.io.readValid(idx) := false.B - rf.io.readTag(idx) := 0.U - } - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopServiceDiagnosticsWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - servicePath: ReducedServiceRequestPath): Unit = { - io.reducedServiceRenameFence := servicePath.io.renameFence - io.reducedServiceControlFence := servicePath.io.controlFence - io.reducedServiceGatherBusy := servicePath.io.gatherBusy - io.reducedServiceOwnerBusy := servicePath.io.ownerBusy - io.reducedServiceSnapshotLookupMatch := servicePath.io.snapshotLookupMatch - io.reducedServiceTrappedInvalidRequestType := servicePath.io.trappedInvalidRequestType - io.reducedServiceTrappedIllegalSequence := servicePath.io.trappedIllegalSequence - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopScalarSpOrderWiring { - def connect( - top: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - owner: ScalarSpOrderOwner, - backendPipeFlush: Bool, - recoveryRestoreValid: Bool, - recoveryRestoreStid: UInt, - recoveryRestoreData: UInt): Unit = { - owner.io.flushValid := backendPipeFlush || top.startValid || top.restartValid - owner.io.initValid := top.rfInitValid && top.rfInitArchTag === 1.U - owner.io.initData := top.rfInitData - owner.io.recoveryRestoreValid := recoveryRestoreValid - owner.io.recoveryRestoreStid := recoveryRestoreStid - owner.io.recoveryRestoreData := recoveryRestoreData - owner.io.reserveValid := path.io.scalarSpReserveFire - owner.io.reserve := path.io.scalarSpReserve - owner.io.commit := path.io.commit - owner.io.commitValidMask := path.io.commitValidMask - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopPipeFlushWiring { - def recoveryIngressFence( - queryValid: Bool, - recoveryReady: Bool, - localReset: Bool, - useProductionD1Ingress: Boolean): Bool = { - // localReset is intentionally part of the combinational qualification. - // The fence owns no state: queryValid is the recovery transaction lifetime - // and therefore cannot leave a stale latch behind after reset/restart. - useProductionD1Ingress.B && !localReset && queryValid && recoveryReady - } - - def productionIfuCanonical( - flush: IfuInnerFlush, - useProductionD1Ingress: Boolean): Bool = - useProductionD1Ingress.B && - flush.valid && - flush.reason === IfuInnerFlushReason.BruRecovery - - def frontend(external: Bool, markerRedirectPending: Bool, productionBru: Bool): Bool = - external || markerRedirectPending || productionBru - - def backend( - external: Bool, - markerRedirectPending: Bool, - recoveryConsumed: Bool, - productionBru: Bool): Bool = - // The canonical backend recovery can be consumed before its exact BRU - // redirect reaches the production IFU. Correct-path D1 work may enter the - // decode/rename queue during that acknowledgement window, while still - // carrying reservations allocated before the IFU publishes the new epoch. - // Flush that transient backend ingress state again with the accepted BRU - // redirect; the IFU restart will replay it in the canonical epoch. - external || markerRedirectPending || recoveryConsumed || productionBru -} - -private object LinxCoreFrontendFetchRfAluTraceTopMarkerRedirectRecoveryWiring { - def connect( - top: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - execute: ReducedScalarAluExecute, - recovery: ScalarRedirectRecoverySource, - productionBruRecoveryUop: ValidIO[RenamedUop], - markerOnlyRedirectFire: Bool, - executeReducedLsId: ROBID, - p: InterfaceParams): Unit = { - val markerIdentityValid = - path.io.blockMarkerActiveValid && path.io.commitHeadValid && - path.io.commitHeadBid.valid && path.io.commitHeadRid.valid && - ROBID.equal( - FullBidRecoveryBridge.fullBidToRobId( - path.io.blockMarkerActiveBid, - path.io.blockMarkerActiveValid, - p.robEntries, - p.blockBidWidth), - path.io.commitHeadBid) - val commitHeadOH = UIntToOH(path.io.commitHeadRid.value, p.robEntries) - val markerHasYoungerRobRow = (path.io.occupiedMask & ~commitHeadOH).orR - - val productionBruRecovery = productionBruRecoveryUop.valid - recovery.io.event.valid := - productionBruRecovery || execute.io.redirectValid || - (markerOnlyRedirectFire && markerIdentityValid && markerHasYoungerRobRow) - recovery.io.event.blockBidValid := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.blockBidValid, - Mux(markerOnlyRedirectFire, path.io.blockMarkerActiveValid, execute.io.completeRow.blockBidValid)) - recovery.io.event.blockBid := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.blockBid, - Mux(markerOnlyRedirectFire, path.io.blockMarkerActiveBid, execute.io.completeRow.blockBid)) - recovery.io.event.bid := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.bid, - Mux(markerOnlyRedirectFire, path.io.commitHeadBid, execute.io.releaseBid)) - recovery.io.event.rid := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.rid, - Mux(markerOnlyRedirectFire, path.io.commitHeadRid, execute.io.releaseRid)) - recovery.io.event.lsId := - Mux( - productionBruRecovery || markerOnlyRedirectFire, - ROBID.disabled(p.robEntries), - executeReducedLsId) - recovery.io.event.lsIdFull := - Mux(productionBruRecovery || markerOnlyRedirectFire, 0.U, execute.io.completeLsId) - recovery.io.event.resolveLsIdValid := execute.io.redirectValid && !productionBruRecovery - recovery.io.event.stid := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.threadId, - Mux(markerOnlyRedirectFire, path.io.commitHeadStid, execute.io.releaseStid)) - recovery.io.event.peId := - Mux(productionBruRecovery, productionBruRecoveryUop.bits.peId, top.peId) - recovery.io.event.tid := - Mux(productionBruRecovery, productionBruRecoveryUop.bits.threadId, top.threadId) - // A production BRU recovery rebases its RID to the youngest completed row - // of the SETC's architectural block. The SETC's original uid is no longer - // the recovery pivot: forwarding that stale order would make GPR cleanup - // discard mappings written by the same-block tail that the rebased RID is - // explicitly preserving. Use the exact rebased RID for this transaction; - // ordinary execute redirects still carry their native order sidecar. - recovery.io.event.orderValid := execute.io.redirectValid && !productionBruRecovery - recovery.io.event.order := - Mux( - productionBruRecovery, - productionBruRecoveryUop.bits.uid.uid, - Mux(execute.io.redirectValid, execute.io.redirectOrder, 0.U)) - recovery.io.sourceReady := path.io.recoveryNonLsuSourceReady(0) - recovery.io.sourceResolved := path.io.recoverySourceResolvedMask(0) - recovery.io.payloadIntentConsumed := path.io.recoveryConsumedPayloadSourceMask(0) - recovery.io.cancel := top.frontendFlushValid || top.restartValid || top.startValid - - when(productionBruRecovery) { - assert(recovery.io.eventReady, "production BRU recovery identity must enter canonical backend recovery") - assert( - !(execute.io.redirectValid || markerOnlyRedirectFire), - "production BRU recovery must not collide with another scalar redirect producer") - } - - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopRedirectIssueCutWiring { - def cutsIssue( - top: LinxCoreFrontendFetchRfAluTraceTopIO, - issue: ScalarIssueFabric, - recovery: ScalarRedirectRecoverySource, - backendPipeFlush: Bool, - p: InterfaceParams): Bool = { - val cutValid = RegInit(false.B) - val cutRid = RegInit(ROBID.disabled(p.robEntries)) - when(backendPipeFlush || top.startValid || top.restartValid || recovery.io.sourceResolved) { - cutValid := false.B - cutRid := ROBID.disabled(p.robEntries) - }.elsewhen(recovery.io.eventAccepted) { - cutValid := recovery.io.event.rid.valid - cutRid := recovery.io.event.rid - } - - val acceptedCut = - recovery.io.eventAccepted && issue.io.issueValid && issue.io.issueUop.rid.valid && - recovery.io.event.rid.valid && - !ROBID.equal(issue.io.issueUop.rid, recovery.io.event.rid) - val retainedCut = - recovery.io.pending && cutValid && issue.io.issueValid && issue.io.issueUop.rid.valid && - !ROBID.equal(issue.io.issueUop.rid, cutRid) - acceptedCut || retainedCut - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopStaScalarSpWiring { - def connect( - path: DecodeRenameROBPath, - execute: ReducedScalarAluExecute, - staBridge: ReducedStoreStaAddressExecBridge, - execBridge: ReducedStoreExecResultBridge, - owner: ScalarSpOrderOwner, - storeDispatchEnabled: Bool, - p: InterfaceParams, - scalarStidCount: Int): Unit = { - val stidIndexWidth = math.max(1, log2Ceil(scalarStidCount)) - def stidIndex(stid: UInt): UInt = - if (scalarStidCount == 1) 0.U(stidIndexWidth.W) else stid(stidIndexWidth - 1, 0) - - val zeroStoreExec = 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - val access = ScalarSpAccess.classify(path.io.storeStaQueue.uop) - val stid = stidIndex(path.io.storeStaQueue.uop.threadId) - val headMatch = - !access.valid || - (owner.io.issueHeadValidByStid(stid) && - ROBID.equal(path.io.storeStaQueue.uop.bid, owner.io.issueHeadBidByStid(stid)) && - ROBID.equal(path.io.storeStaQueue.uop.rid, owner.io.issueHeadRidByStid(stid))) - val spDirectCandidate = staBridge.io.candidate && staBridge.io.supportedOpcode && access.valid - val grant = !spDirectCandidate || headMatch - val directExec = Wire(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - directExec := staBridge.io.exec - when(!grant) { - directExec.valid := false.B - } - - val selectedStaExec = - Mux(staBridge.io.candidate && staBridge.io.supportedOpcode, directExec, execBridge.io.staExec) - path.io.storeStaExec := Mux(storeDispatchEnabled, selectedStaExec, zeroStoreExec) - path.io.storeStdExec := Mux(storeDispatchEnabled, execBridge.io.stdExec, zeroStoreExec) - - val staTerminalValid = - path.io.storeSelectedSta && staBridge.io.candidate && staBridge.io.supportedOpcode && access.valid - val staTerminal = Wire(new ScalarSpTransaction(p)) - staTerminal := 0.U.asTypeOf(staTerminal) - staTerminal.access := access - staTerminal.stid := path.io.storeStaQueue.uop.threadId - staTerminal.bid := path.io.storeStaQueue.uop.bid - staTerminal.rid := path.io.storeStaQueue.uop.rid - staTerminal.epoch := 0.U - - owner.io.terminalValid := execute.io.scalarSpTerminalValid || staTerminalValid - owner.io.terminal := Mux(execute.io.scalarSpTerminalValid, execute.io.scalarSpTerminal, staTerminal) - owner.io.terminalProducedValid := - Mux(execute.io.scalarSpTerminalValid, execute.io.scalarSpProducedValid, staTerminalValid && access.write) - owner.io.terminalProducedData := - Mux(execute.io.scalarSpTerminalValid, execute.io.scalarSpProducedData, directExec.addr) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopStoreCommitIngressWiring { - def connect( - top: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - execute: ReducedScalarAluExecute, - storeExecBridge: ReducedStoreExecResultBridge, - storeStaAddressExecBridge: ReducedStoreStaAddressExecBridge, - storeCommitOwner: ReducedStoreCommitFreeOwner, - reducedStoreCommitDrain: STQCommitDrain, - reducedStoreScb: SCBRowBank, - reducedStoreFlush: Bool, - useReducedStoreDispatchStq: Bool, - useReducedStoreStaAddressExecBridge: Bool, - scalarStidCount: Int, - coreParams: CoreParams): Bool = { - storeExecBridge.io.flushValid := reducedStoreFlush - storeExecBridge.io.completeValid := execute.io.completeFire && useReducedStoreDispatchStq - storeExecBridge.io.completeStoreDispatch := execute.io.completeUop.isStore - storeExecBridge.io.completeRow := execute.io.completeRow - storeExecBridge.io.completeBid := execute.io.releaseBid - storeExecBridge.io.completeRid := execute.io.releaseRid - storeExecBridge.io.completeStid := execute.io.releaseStid - storeExecBridge.io.staQueueValid := path.io.storeStaQueueValid - storeExecBridge.io.staQueue := path.io.storeStaQueue - storeExecBridge.io.stdQueueValid := path.io.storeStdQueueValid - storeExecBridge.io.stdQueue := path.io.storeStdQueue - storeExecBridge.io.staConsumed := path.io.storeSelectedSta - storeExecBridge.io.stdConsumed := path.io.storeSelectedStd - storeStaAddressExecBridge.io.enable := useReducedStoreStaAddressExecBridge && useReducedStoreDispatchStq - storeStaAddressExecBridge.io.queueValid := path.io.storeStaQueueValid - storeStaAddressExecBridge.io.queue := path.io.storeStaQueue - storeCommitOwner.io.enable := useReducedStoreDispatchStq - storeCommitOwner.io.directFreeEnable := false.B - storeCommitOwner.io.flushValid := reducedStoreFlush - storeCommitOwner.io.activeStid := top.threadId - val storeCommitStidMatch = VecInit((0 until scalarStidCount).map { stid => - top.threadId === stid.U(top.threadId.getWidth.W) - }) - val storeCommitStidInRange = storeCommitStidMatch.asUInt.orR - storeCommitOwner.io.nonFlushValid := storeCommitStidInRange && - Mux1H(storeCommitStidMatch, path.io.blockNonFlushValid) - storeCommitOwner.io.nonFlushHeadBid := Mux( - storeCommitStidInRange, - Mux1H(storeCommitStidMatch, path.io.blockNonFlushHeadBid), - 0.U) - storeCommitOwner.io.nonFlushPrefixCount := Mux( - storeCommitStidInRange, - Mux1H(storeCommitStidMatch, path.io.blockNonFlushPrefixCount), - 0.U) - storeCommitOwner.io.oldestBlockValid := storeCommitStidInRange && - (Mux1H(storeCommitStidMatch, path.io.blockNonFlushValid) || - Mux1H(storeCommitStidMatch, path.io.blockNonFlushBlockedValid)) - storeCommitOwner.io.oldestBlockBid := Mux( - storeCommitStidInRange, - Mux1H(storeCommitStidMatch, path.io.blockNonFlushHeadBid), - 0.U) - storeCommitOwner.io.oldestRobValid := path.io.commitHeadValid - storeCommitOwner.io.oldestRobBid := path.io.commitHeadBid - storeCommitOwner.io.oldestRobLsId := path.io.commitHeadLsId - storeCommitOwner.io.oldestRobStid := path.io.commitHeadStid - storeCommitOwner.io.commit := path.io.commit - storeCommitOwner.io.commitValidMask := path.io.commitValidMask - storeCommitOwner.io.commitMemoryOrder := path.io.commitMemoryOrder - storeCommitOwner.io.stqRows := path.io.storeStqRows - storeCommitOwner.io.markCommitAccepted := path.io.storeMarkCommitAccepted - storeCommitOwner.io.markCommitIgnored := path.io.storeMarkCommitIgnored - storeCommitOwner.io.commitFreeAccepted := path.io.storeCommitFreeAccepted - storeCommitOwner.io.commitFreeIgnored := path.io.storeCommitFreeIgnored - storeCommitOwner.io.commitFreeAcceptedMask := path.io.storeCommitFreeAcceptedMask - storeCommitOwner.io.commitFreeIgnoredMask := path.io.storeCommitFreeIgnoredMask - - val reducedStoreScbReadyForDrain = useReducedStoreDispatchStq && reducedStoreScb.io.modelBatchReady && !reducedStoreFlush - reducedStoreCommitDrain.io.enqueueValid := useReducedStoreDispatchStq && path.io.storeMarkCommitAccepted - reducedStoreCommitDrain.io.enqueueIndex := storeCommitOwner.io.markCommitIndex - reducedStoreCommitDrain.io.enqueueBid := path.io.storeStqRows(storeCommitOwner.io.markCommitIndex).bid - reducedStoreCommitDrain.io.enqueueLsId := path.io.storeStqRows(storeCommitOwner.io.markCommitIndex).lsIdFull - reducedStoreCommitDrain.io.flushValid := reducedStoreFlush - reducedStoreCommitDrain.io.issueEnable := reducedStoreScbReadyForDrain - reducedStoreCommitDrain.io.primaryReadyMask := - Fill(coreParams.scalarLsu.stqEntries, reducedStoreScbReadyForDrain) - reducedStoreCommitDrain.io.secondaryReadyMask := - Fill(coreParams.scalarLsu.stqEntries, reducedStoreScbReadyForDrain) - reducedStoreCommitDrain.io.rows := path.io.storeStqRows - for (index <- 0 until coreParams.scalarLsu.stqEntries) { - reducedStoreCommitDrain.io.memoryAttributes(index).valid := - useReducedStoreDispatchStq && path.io.storeStqRows(index).valid - reducedStoreCommitDrain.io.memoryAttributes(index).memoryClass := - linxcore.lsu.STQMemoryClass.NormalCacheable - } - - reducedStoreScbReadyForDrain - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopIssueDiagnosticsWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - issue: ScalarIssueFabric, - scalarSpOrder: ScalarSpOrderOwner, - executeAccepted: Bool): Unit = { - val inputValid = issue.io.inValid - val outputValid = issue.io.issueValid - val accepted = executeAccepted - - io.issueQueueEnqueueFire := issue.io.inputAcceptFire - io.issueQueueInputValid := inputValid - io.issueQueueInputPc := Mux(inputValid, issue.io.in.pc, 0.U) - io.issueQueueInputOpcode := Mux(inputValid, issue.io.in.opcode, 0.U) - io.issueQueueInputBidValid := inputValid && issue.io.in.bid.valid - io.issueQueueInputBidWrap := inputValid && issue.io.in.bid.wrap - io.issueQueueInputBidValue := Mux(inputValid, issue.io.in.bid.value, 0.U) - io.issueQueueInputRidValid := inputValid && issue.io.in.rid.valid - io.issueQueueInputRidWrap := inputValid && issue.io.in.rid.wrap - io.issueQueueInputRidValue := Mux(inputValid, issue.io.in.rid.value, 0.U) - io.issueQueueInputStid := Mux(inputValid, issue.io.in.threadId, 0.U) - io.issueQueuePickFire := issue.io.pickFire - io.issueQueueIssueFire := issue.io.issueFire - io.issueQueueOutputValid := outputValid - io.issueQueueOutputPc := Mux(outputValid, issue.io.issueUop.pc, 0.U) - io.issueQueueOutputOpcode := Mux(outputValid, issue.io.issueUop.opcode, 0.U) - io.issueQueueOutputBidValid := outputValid && issue.io.issueUop.bid.valid - io.issueQueueOutputBidWrap := outputValid && issue.io.issueUop.bid.wrap - io.issueQueueOutputBidValue := Mux(outputValid, issue.io.issueUop.bid.value, 0.U) - io.issueQueueOutputRidValid := outputValid && issue.io.issueUop.rid.valid - io.issueQueueOutputRidWrap := outputValid && issue.io.issueUop.rid.wrap - io.issueQueueOutputRidValue := Mux(outputValid, issue.io.issueUop.rid.value, 0.U) - io.issueQueueOutputStid := Mux(outputValid, issue.io.issueUop.threadId, 0.U) - io.executeAcceptedIdentityValid := accepted - io.executeAcceptedPc := Mux(accepted, issue.io.issueUop.pc, 0.U) - io.executeAcceptedOpcode := Mux(accepted, issue.io.issueUop.opcode, 0.U) - io.executeAcceptedBidValid := accepted && issue.io.issueUop.bid.valid - io.executeAcceptedBidWrap := accepted && issue.io.issueUop.bid.wrap - io.executeAcceptedBidValue := Mux(accepted, issue.io.issueUop.bid.value, 0.U) - io.executeAcceptedRidValid := accepted && issue.io.issueUop.rid.valid - io.executeAcceptedRidWrap := accepted && issue.io.issueUop.rid.wrap - io.executeAcceptedRidValue := Mux(accepted, issue.io.issueUop.rid.value, 0.U) - io.executeAcceptedStid := Mux(accepted, issue.io.issueUop.threadId, 0.U) - io.issueQueueCancelFire := issue.io.cancelFire - io.issueQueueReleaseFire := issue.io.releaseFire - io.issueQueueCount := issue.io.count - io.issueQueueIssuedCount := issue.io.issuedCount - io.issueQueueNotIssuedCount := issue.io.notIssuedCount - io.issueQueueHeadValid := issue.io.headValid - io.issueQueueHeadIssued := issue.io.headIssued - io.issueQueueHeadPc := issue.io.headPc - io.issueQueueHeadOpcode := issue.io.headOpcode - io.issueQueueHeadStid := issue.io.headStid - io.issueQueueHeadBidValid := issue.io.headValid && issue.io.headBid.valid - io.issueQueueHeadBidWrap := issue.io.headValid && issue.io.headBid.wrap - io.issueQueueHeadBidValue := Mux(issue.io.headValid, issue.io.headBid.value, 0.U) - io.issueQueueHeadRidValid := issue.io.headValid && issue.io.headRid.valid - io.issueQueueHeadRidWrap := issue.io.headValid && issue.io.headRid.wrap - io.issueQueueHeadRidValue := Mux(issue.io.headValid, issue.io.headRid.value, 0.U) - io.issueQueueHeadSrcValidMask := issue.io.headSrcValidMask - io.issueQueueHeadSrcClass := issue.io.headSrcOperandClass - io.issueQueueHeadSrcPhysTag := issue.io.headSrcPhysTag - io.issueQueueHeadSrcRelTag := issue.io.headSrcRelTag - io.issueQueueSourceReadyMask := issue.io.sourceReadyMask - io.issueQueueAllSourcesReady := issue.io.allSourcesReady - io.issueQueueSelectedValid := issue.io.selectedValid - io.issueQueueSelectedIndex := issue.io.selectedIndex - io.issueQueueSelectedReadReady := issue.io.selectedReadReady - io.issueQueueI1Valid := issue.io.i1Valid - io.issueQueueI2Valid := issue.io.i2Valid - io.issueQueueStageBusy := issue.io.stageBusy - io.issueQueueBlockedBySource := issue.io.blockedBySource - io.issueQueueBlockedByRead := issue.io.blockedByRead - io.issueQueueBlockedByOutput := issue.io.blockedByOutput - io.issueQueueBlockedByIssued := issue.io.blockedByIssued - io.issueQueueBankOccupancy := issue.io.bankOccupancy - io.issueQueueBankPickMask := issue.io.bankPickMask - io.issueQueueBankReadAttemptMask := issue.io.bankReadAttemptMask - io.issueQueueBankReadGrantMask := issue.io.bankReadGrantMask - io.issueQueueBankIssueValidMask := issue.io.bankIssueValidMask - io.issueQueueBankIssueGrantMask := issue.io.bankIssueGrantMask - io.issueQueueSimultaneousPick := issue.io.simultaneousPick - io.issueQueueReadContention := issue.io.readContention - io.issueQueueReadArbitrationLoss := issue.io.readArbitrationLoss - io.issueQueueIssueContention := issue.io.issueContention - io.issueQueueControlFenceActive := issue.io.controlFenceActive - io.issueQueueControlFenceBlocked := issue.io.controlFenceBlocked - io.issueQueueBankControlBlockedMask := issue.io.bankControlBlockedMask - io.issueQueueStoreOrderBlocked := issue.io.storeOrderBlocked - io.issueQueueBankStoreOrderBlockedMask := issue.io.bankStoreOrderBlockedMask - io.issueQueueScalarSpOrderBlocked := issue.io.scalarSpOrderBlocked - io.issueQueueBankScalarSpOrderBlockedMask := issue.io.bankScalarSpOrderBlockedMask - io.issueQueueProtocolError := issue.io.protocolError - io.scalarSpStid0IssueHeadValid := scalarSpOrder.io.issueHeadValidByStid(0) - io.scalarSpStid0IssueHeadBidValid := scalarSpOrder.io.issueHeadValidByStid(0) && - scalarSpOrder.io.issueHeadBidByStid(0).valid - io.scalarSpStid0IssueHeadBidWrap := scalarSpOrder.io.issueHeadValidByStid(0) && - scalarSpOrder.io.issueHeadBidByStid(0).wrap - io.scalarSpStid0IssueHeadBidValue := Mux( - scalarSpOrder.io.issueHeadValidByStid(0), - scalarSpOrder.io.issueHeadBidByStid(0).value, - 0.U) - io.scalarSpStid0IssueHeadRidValid := scalarSpOrder.io.issueHeadValidByStid(0) && - scalarSpOrder.io.issueHeadRidByStid(0).valid - io.scalarSpStid0IssueHeadRidWrap := scalarSpOrder.io.issueHeadValidByStid(0) && - scalarSpOrder.io.issueHeadRidByStid(0).wrap - io.scalarSpStid0IssueHeadRidValue := Mux( - scalarSpOrder.io.issueHeadValidByStid(0), - scalarSpOrder.io.issueHeadRidByStid(0).value, - 0.U) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2PromotionControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - promotionControl: LoadReplayReturnPipeW2PromotionControl, - slot: LoadReplayReturnPipeW2Slot, - w1Advance: LoadReplayReturnPipeW1AdvanceCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - promotionRequested: Bool, - enable: Bool, - flush: Bool): Unit = { - promotionControl.io.enable := enable - promotionControl.io.flush := flush - promotionControl.io.promotionRequested := promotionRequested - promotionControl.io.slotOccupied := slot.io.occupied - promotionControl.io.clearIntent := clearIntent.io.clearIntent - promotionControl.io.writeCandidateValid := w1Advance.io.candidateValid - - io.reducedLoadReplayLiqLretPipeW2PromotionControlLivePromotion := - promotionControl.io.livePromotionEnable - io.reducedLoadReplayLiqLretPipeW2PromotionControlLiveClearEnable := - promotionControl.io.liveClearEnable - io.reducedLoadReplayLiqLretPipeW2PromotionControlAdvanceLivePromotion := - promotionControl.io.advanceLivePromotionEnable - io.reducedLoadReplayLiqLretPipeW2PromotionControlBlocked := - promotionControl.io.blockedByDisabled || - promotionControl.io.blockedByFlush || - promotionControl.io.blockedByPromotionDisabled || - promotionControl.io.blockedByClearIntent || - promotionControl.io.invalidClearIntentWithoutSlot - io.reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByPromotionDisabled := - promotionControl.io.blockedByPromotionDisabled - io.reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByClearIntent := - promotionControl.io.blockedByClearIntent - io.reducedLoadReplayLiqLretPipeW2PromotionControlInvalidClearIntentWithoutSlot := - promotionControl.io.invalidClearIntentWithoutSlot - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2RefillReadyWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - refillReady: LoadReplayReturnPipeW2RefillReady, - slot: LoadReplayReturnPipeW2Slot, - w1Advance: LoadReplayReturnPipeW1AdvanceCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - enable: Bool, - flush: Bool): Unit = { - refillReady.io.enable := enable - refillReady.io.flush := flush - refillReady.io.slotOccupied := slot.io.occupied - refillReady.io.currentAdvanceReady := !slot.io.occupied - refillReady.io.clearIntent := clearIntent.io.clearIntent - refillReady.io.liveClear := clearIntent.io.liveClear - - io.reducedLoadReplayLiqLretPipeW2RefillReadyEmpty := - refillReady.io.emptyReady - io.reducedLoadReplayLiqLretPipeW2RefillReadySameCycleEligible := - refillReady.io.sameCycleRefillEligible - io.reducedLoadReplayLiqLretPipeW2RefillReadySameCycleReady := - refillReady.io.sameCycleRefillReady - io.reducedLoadReplayLiqLretPipeW2RefillReadyFutureAdvance := - refillReady.io.futureAdvanceReady - io.reducedLoadReplayLiqLretPipeW2RefillReadyMatchesCurrent := - refillReady.io.currentMatchesFuture && - (w1Advance.io.blockedByAdvanceDisabled === (w1Advance.io.candidateValid && !refillReady.io.futureAdvanceReady)) - io.reducedLoadReplayLiqLretPipeW2RefillReadyBlocked := - refillReady.io.blockedByDisabled || - refillReady.io.blockedByFlush || - refillReady.io.blockedByOccupied || - refillReady.io.blockedByLiveClearDisabled || - refillReady.io.invalidLiveClearWithoutIntent - io.reducedLoadReplayLiqLretPipeW2RefillReadyInvalidLiveClearWithoutIntent := - refillReady.io.invalidLiveClearWithoutIntent - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2SlotReplacePlanWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - replacePlan: LoadReplayReturnPipeW2SlotReplacePlan, - slot: LoadReplayReturnPipeW2Slot, - w1Advance: LoadReplayReturnPipeW1AdvanceCandidate, - clearIntent: LoadReplayReturnPipeW2ClearIntent, - refillReady: LoadReplayReturnPipeW2RefillReady, - enable: Bool, - flush: Bool): Unit = { - replacePlan.io.enable := enable - replacePlan.io.flush := flush - replacePlan.io.slotOccupied := slot.io.occupied - replacePlan.io.writeValid := w1Advance.io.candidateValid - replacePlan.io.writeTargetIsAgu := w1Advance.io.targetIsAgu - replacePlan.io.writeTargetIsLda := w1Advance.io.targetIsLda - replacePlan.io.clearIntent := clearIntent.io.clearIntent - replacePlan.io.liveClear := clearIntent.io.liveClear - replacePlan.io.futureAdvanceReady := refillReady.io.futureAdvanceReady - replacePlan.io.currentSlotAccepted := slot.io.accepted - replacePlan.io.currentSlotBlockedByClear := slot.io.blockedByClear - - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanEmptyWriteEligible := - replacePlan.io.emptyWriteEligible - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleEligible := - replacePlan.io.sameCycleReplaceEligible - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleReady := - replacePlan.io.sameCycleReplaceReady - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanFutureWriteAccept := - replacePlan.io.futureWriteAccept - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanMatchesCurrent := - replacePlan.io.currentMatchesFutureWrite - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlocked := - replacePlan.io.blockedByDisabled || - replacePlan.io.blockedByFlush || - replacePlan.io.blockedByNoWrite || - replacePlan.io.blockedByInvalidTarget || - replacePlan.io.blockedByOccupiedNoClear || - replacePlan.io.blockedByLiveClearDisabled || - replacePlan.io.blockedByCurrentStorage || - replacePlan.io.blockedByCurrentClearPriority || - replacePlan.io.invalidFutureAdvanceWithoutLiveClear || - replacePlan.io.invalidCurrentAcceptWithoutFuture - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlockedByCurrentStorage := - replacePlan.io.blockedByCurrentStorage - io.reducedLoadReplayLiqLretPipeW2SlotReplacePlanInvalidFutureReadyWithoutLiveClear := - replacePlan.io.invalidFutureAdvanceWithoutLiveClear - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopW2AdvanceControlWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - advanceControl: LoadReplayReturnPipeW2AdvanceControl, - slot: LoadReplayReturnPipeW2Slot, - w1Advance: LoadReplayReturnPipeW1AdvanceCandidate, - refillReady: LoadReplayReturnPipeW2RefillReady, - replacePlan: LoadReplayReturnPipeW2SlotReplacePlan, - livePromotionEnable: Bool, - enable: Bool, - flush: Bool): Unit = { - advanceControl.io.enable := enable - advanceControl.io.flush := flush - advanceControl.io.livePromotionEnable := livePromotionEnable - advanceControl.io.currentAdvanceReady := !slot.io.occupied - advanceControl.io.futureAdvanceReady := refillReady.io.futureAdvanceReady - advanceControl.io.sameCycleReplaceReady := replacePlan.io.sameCycleReplaceReady - advanceControl.io.futureWriteAccept := replacePlan.io.futureWriteAccept - advanceControl.io.writeCandidateValid := w1Advance.io.candidateValid - - io.reducedLoadReplayLiqLretPipeW2AdvanceControlAdvanceEnable := - advanceControl.io.advanceEnable - io.reducedLoadReplayLiqLretPipeW2AdvanceControlReplaceOnClear := - advanceControl.io.replaceOnClear - io.reducedLoadReplayLiqLretPipeW2AdvanceControlUsesFutureAdvance := - advanceControl.io.usesFutureAdvance - io.reducedLoadReplayLiqLretPipeW2AdvanceControlBlocked := - advanceControl.io.blockedByDisabled || - advanceControl.io.blockedByFlush || - advanceControl.io.blockedByLivePromotionDisabled || - advanceControl.io.blockedByFutureAdvance || - advanceControl.io.invalidReplaceWithoutFutureWrite || - advanceControl.io.invalidFutureWriteWithoutAdvance - io.reducedLoadReplayLiqLretPipeW2AdvanceControlBlockedByLivePromotionDisabled := - advanceControl.io.blockedByLivePromotionDisabled - io.reducedLoadReplayLiqLretPipeW2AdvanceControlInvalidFutureWriteWithoutAdvance := - advanceControl.io.invalidFutureWriteWithoutAdvance - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopTemplateContextWiring { - def connect( - top: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - issue: ScalarIssueFabric, - execute: ReducedScalarAluExecute, - rf: ScalarGPRFile, - context: ReducedTemplateContextStack, - snapshots: ReducedTemplateSnapshotTable, - localReset: Bool, - conditionalFretWaiting: Bool, - liveConditionValid: Bool, - liveConditionTaken: Bool, - templateRfReadPort: Int, - p: InterfaceParams): Bool = { - val architecturalContextFlush = - top.startValid || top.restartValid || top.frontendFlushValid - snapshots.io.flush := localReset - snapshots.io.writeValid := path.io.templateSnapshotValid && path.io.templateSnapshotRid.valid - snapshots.io.writeRid := path.io.templateSnapshotRid.value - snapshots.io.writeMap := path.io.templateSmapSnapshot - snapshots.io.captureRid := execute.io.completeRobValue - snapshots.io.restoreRid := issue.io.issueUop.rid.value - - rf.io.readValid(templateRfReadPort) := context.io.captureReadValid - rf.io.readTag(templateRfReadPort) := context.io.captureReadTag - context.io.captureReadReady := rf.io.readReady(templateRfReadPort) - context.io.captureReadData := rf.io.readData(templateRfReadPort) - - val executeCompleteIsFentry = - execute.io.completeFire && - ((execute.io.completeRow.insn & "h707f".U) === "h0041".U) - context.io.flush := architecturalContextFlush - context.io.cancel := localReset && !architecturalContextFlush - context.io.captureStart := executeCompleteIsFentry && snapshots.io.captureValid - context.io.captureStartArch := execute.io.completeRow.insn(19, 15) - context.io.captureEndArch := execute.io.completeRow.insn(24, 20) - context.io.captureMap := snapshots.io.captureMap - - val issueIsFentry = - issue.io.issueValid && - issue.io.issueUop.opcode === FrontendOpcodeDecodeTable.OP_FENTRY.U(p.opcodeWidth.W) - val issueIsFretStk = - issue.io.issueValid && - issue.io.issueUop.opcode === FrontendOpcodeDecodeTable.OP_FRET_STK.U(p.opcodeWidth.W) - val issueFretFallbackValid = issueIsFretStk && issue.io.issueUop.fretStkFallbackTargetValid - val issueFretWillReturn = - issueIsFretStk && - ((liveConditionValid && !liveConditionTaken) || - (!liveConditionValid && !issueFretFallbackValid)) - - val restoreDoneValid = RegInit(false.B) - val restoreDoneRid = RegInit(ROBID.disabled(p.robEntries)) - val restoreActiveRid = RegInit(ROBID.disabled(p.robEntries)) - val restoreDoneMatch = - restoreDoneValid && issue.io.issueUop.rid.valid && - ROBID.equal(restoreDoneRid, issue.io.issueUop.rid) - val restoreSnapshotValid = issue.io.issueUop.rid.valid && snapshots.io.restoreValid - val restoreRequired = - issueFretWillReturn && context.io.frameCount =/= 0.U && - restoreSnapshotValid && !restoreDoneMatch - val restoreStart = - restoreRequired && !conditionalFretWaiting && - !context.io.captureBusy && !context.io.restoreBusy && !restoreActiveRid.valid - - context.io.restoreStart := restoreStart - context.io.restoreMap := snapshots.io.restoreMap - - when(localReset) { - restoreDoneValid := false.B - restoreDoneRid := ROBID.disabled(p.robEntries) - restoreActiveRid := ROBID.disabled(p.robEntries) - }.otherwise { - when(restoreStart) { - restoreActiveRid := issue.io.issueUop.rid - } - when(context.io.restoreDone) { - restoreDoneValid := true.B - restoreDoneRid := restoreActiveRid - restoreActiveRid := ROBID.disabled(p.robEntries) - }.elsewhen(issue.io.issueFire && restoreDoneMatch) { - restoreDoneValid := false.B - restoreDoneRid := ROBID.disabled(p.robEntries) - } - } - - (issueIsFentry && (context.io.captureBusy || executeCompleteIsFentry)) || - (issueFretWillReturn && context.io.captureBusy) || - restoreRequired - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopWritebackPrimaryWiring { - def connect( - arbiter: ReducedScalarWritebackArbiter, - execute: ReducedScalarAluExecute, - servicePath: ReducedServiceRequestPath, - scalarScWritebackValid: Bool, - scalarScWritebackTag: UInt, - scalarScWritebackData: UInt, - templateContext: ReducedTemplateContextStack, - physRegWidth: Int, - dataWidth: Int): Unit = { - arbiter.io.executeValid := execute.io.completeDstPhysValid - arbiter.io.executeTag := execute.io.completeDstPhysTag - arbiter.io.executeData := execute.io.completeDstData - - arbiter.io.serviceEnable := true.B - val selectedServicePathWriteback = servicePath.io.writebackValid - arbiter.io.serviceValid := selectedServicePathWriteback || scalarScWritebackValid - arbiter.io.serviceTag := - Mux(selectedServicePathWriteback, servicePath.io.writeback.physTag, scalarScWritebackTag) - arbiter.io.serviceData := - Mux(selectedServicePathWriteback, servicePath.io.writeback.data, scalarScWritebackData) - - arbiter.io.templateEnable := true.B - arbiter.io.templateValid := templateContext.io.restoreWriteValid - arbiter.io.templateTag := templateContext.io.restoreWriteTag - arbiter.io.templateData := templateContext.io.restoreWriteData - templateContext.io.restoreWriteReady := arbiter.io.selectedTemplate - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopBranchValidationWiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - execute: ReducedScalarAluExecute, - productionD1: D1DecodedLaneQueue, - localReset: Bool, - backendPipeFlush: Bool, - useProductionD1Ingress: Boolean, - p: InterfaceParams): (ValidIO[RenamedUop], Bool) = { - val productionBruRecoveryUop = Wire(Valid(new RenamedUop(p))) - val retainMispredictForFeedback = RegInit(false.B) - val pendingBackendRecovery = RegInit(false.B) - val backendRecoveryPublished = RegInit(false.B) - val backendCleanupDone = RegInit(false.B) - val ifuRecoverySeen = RegInit(false.B) - val pendingBackendRecoveryUop = RegInit(0.U.asTypeOf(new RenamedUop(p))) - val queue = withReset(localReset || (backendPipeFlush && !retainMispredictForFeedback)) { - Module(new Queue(new BackendBranchValidation(p), 4, pipe = true, flow = false)) - } - val dispatchQueue = withReset(localReset || backendPipeFlush) { - Module(new Queue(new BackendBranchValidation(p), 4, pipe = true, flow = false)) - } - val dispatchValidationPending = RegInit(false.B) - val dispatchValidationPendingMispredict = RegInit(false.B) - val dispatchUop = productionD1.io.out.bits.entries(productionD1.io.headLane) - val dispatchOwnsValidation = - dispatchUop.sob && - (dispatchUop.boundaryKind === BoundaryKind.Direct || - dispatchUop.boundaryKind === BoundaryKind.Call) - dispatchQueue.io.enq.valid := - useProductionD1Ingress.B && productionD1.io.out.fire && - dispatchUop.valid && dispatchUop.prediction.valid && dispatchOwnsValidation - dispatchQueue.io.enq.bits := 0.U.asTypeOf(dispatchQueue.io.enq.bits) - dispatchQueue.io.enq.bits.uop.valid := dispatchUop.valid - dispatchQueue.io.enq.bits.uop.peId := dispatchUop.peId - dispatchQueue.io.enq.bits.uop.threadId := dispatchUop.threadId - dispatchQueue.io.enq.bits.uop.pc := dispatchUop.pc - dispatchQueue.io.enq.bits.uop.checkpointId := dispatchUop.checkpointId - dispatchQueue.io.enq.bits.uop.uid := dispatchUop.uid - dispatchQueue.io.enq.bits.uop.boundaryKind := dispatchUop.boundaryKind - dispatchQueue.io.enq.bits.uop.boundaryTarget := dispatchUop.boundaryTarget - dispatchQueue.io.enq.bits.uop.prediction := dispatchUop.prediction - dispatchQueue.io.enq.bits.point := BranchValidationPoint.Dispatch - dispatchQueue.io.enq.bits.setcKind := SetcValidationKind.None - dispatchQueue.io.enq.bits.actualTaken := true.B - dispatchQueue.io.enq.bits.actualBranchPc := dispatchUop.pc - dispatchQueue.io.enq.bits.actualTarget := dispatchUop.boundaryTarget - dispatchQueue.io.enq.bits.actualFallthroughPc := dispatchUop.pc + dispatchUop.insnLen - dispatchQueue.io.enq.bits.actualKind := dispatchUop.boundaryKind - - val uop = execute.io.branchConditionUop - val prediction = uop.prediction - val setcOwnsValidation = - SetcBranchValidationOwnership.owns( - execute.io.branchConditionIsTarget, - prediction.kind) - val actualKind = - SetcBranchValidationOwnership.actualKind( - execute.io.branchConditionIsTarget, - prediction.kind) - val setcValidationValid = - useProductionD1Ingress.B && - execute.io.branchConditionValid && - prediction.valid && - setcOwnsValidation - val setcValidation = Wire(new BackendBranchValidation(p)) - setcValidation := 0.U.asTypeOf(setcValidation) - setcValidation.uop := uop - setcValidation.point := BranchValidationPoint.BruE1 - setcValidation.setcKind := - Mux( - execute.io.branchConditionIsTarget, - SetcValidationKind.Target, - SetcValidationKind.Condition) - setcValidation.actualTaken := - Mux(execute.io.branchConditionIsTarget, true.B, execute.io.branchConditionTaken) - setcValidation.actualBranchPc := prediction.branchPc - setcValidation.actualTarget := - Mux( - execute.io.branchConditionIsTarget, - execute.io.branchConditionTarget, - // LinxCoreModel resolves conditional SETC against the target in the - // SETC's own BlockCommand. The renamed uop snapshots that BID-scoped - // target at decode; predictor state and the live marker context are - // deliberately not architectural truth. - uop.boundaryTarget) - setcValidation.actualFallthroughPc := prediction.fallthroughPc - setcValidation.actualKind := actualKind - - // SETC completion cannot be backpressured after W2. Give it priority over - // the independently buffered Dispatch producer; neither event may be - // dropped when both owners resolve in the same cycle. - queue.io.enq.valid := setcValidationValid || dispatchQueue.io.deq.valid - queue.io.enq.bits := Mux(setcValidationValid, setcValidation, dispatchQueue.io.deq.bits) - dispatchQueue.io.deq.ready := queue.io.enq.ready && !setcValidationValid - val queuedValidationMispredict = - queue.io.deq.valid && BackendBranchValidationContract.mispredict(queue.io.deq.bits) - val validationCanPublish = - !queuedValidationMispredict || - queue.io.deq.bits.point === BranchValidationPoint.Dispatch || - path.io.recoveryBlockReady - io.backendValidation.valid := queue.io.deq.valid && validationCanPublish - io.backendValidation.bits := queue.io.deq.bits - queue.io.deq.ready := io.backendValidation.ready && validationCanPublish - - val completingValidationMispredict = - queue.io.enq.fire && BackendBranchValidationContract.mispredict(queue.io.enq.bits) - val completingBruValidationMispredict = - completingValidationMispredict && queue.io.enq.bits.point === BranchValidationPoint.BruE1 - val admittedValidationMispredict = - io.backendValidation.fire && - BackendBranchValidationContract.mispredict(io.backendValidation.bits) - - val activeRecoveryUop = Wire(new RenamedUop(p)) - activeRecoveryUop := pendingBackendRecoveryUop - val activeRecoveryValid = pendingBackendRecovery - - path.io.recoveryBlockQueryValid := useProductionD1Ingress.B && activeRecoveryValid - path.io.recoveryBlockQueryBid := activeRecoveryUop.blockBid - path.io.recoveryBlockQueryStid := activeRecoveryUop.threadId - // Hold commit in the SETC completion cycle, but start the block query from - // the registered recovery owner on the following cycle. The validation - // queue is pipelined, so feeding its dequeue-ready result back into the - // same-cycle enqueue identity would otherwise form a ready/valid loop. - path.io.commitHold := - useProductionD1Ingress.B && (completingBruValidationMispredict || activeRecoveryValid) - - val recoveryBlockReady = - activeRecoveryValid && path.io.recoveryBlockReady && - path.io.recoveryBlockPivotPresent && !backendRecoveryPublished - val productionBruFlush = - useProductionD1Ingress.B && - io.productionIfuFlush.valid && - io.productionIfuFlush.reason === IfuInnerFlushReason.BruRecovery - - when(localReset) { - dispatchValidationPending := false.B - dispatchValidationPendingMispredict := false.B - }.elsewhen(dispatchQueue.io.enq.fire) { - dispatchValidationPending := true.B - dispatchValidationPendingMispredict := - BackendBranchValidationContract.mispredict(dispatchQueue.io.enq.bits) - }.elsewhen( - dispatchValidationPending && !dispatchValidationPendingMispredict && - io.backendValidation.fire && - io.backendValidation.bits.point === BranchValidationPoint.Dispatch) { - dispatchValidationPending := false.B - dispatchValidationPendingMispredict := false.B - }.elsewhen( - dispatchValidationPending && dispatchValidationPendingMispredict && productionBruFlush) { - dispatchValidationPending := false.B - dispatchValidationPendingMispredict := false.B - }.elsewhen(backendPipeFlush && !retainMispredictForFeedback) { - dispatchValidationPending := false.B - dispatchValidationPendingMispredict := false.B - } - - when(localReset) { - retainMispredictForFeedback := false.B - }.elsewhen(completingValidationMispredict) { - retainMispredictForFeedback := true.B - }.elsewhen(admittedValidationMispredict) { - retainMispredictForFeedback := false.B - } - - val backendCleanupConsumed = - backendRecoveryPublished && backendPipeFlush && !productionBruFlush - val noBackendSuffixAfterIfuRecovery = - pendingBackendRecovery && ifuRecoverySeen && path.io.recoveryBlockReady && - !path.io.recoveryBlockPivotPresent && !backendRecoveryPublished - val recoveryTransactionComplete = - pendingBackendRecovery && - (ifuRecoverySeen || productionBruFlush) && - (backendCleanupDone || backendCleanupConsumed || noBackendSuffixAfterIfuRecovery) - - when(localReset) { - pendingBackendRecovery := false.B - backendRecoveryPublished := false.B - backendCleanupDone := false.B - ifuRecoverySeen := false.B - }.elsewhen(completingBruValidationMispredict) { - pendingBackendRecovery := true.B - pendingBackendRecoveryUop := queue.io.enq.bits.uop - backendRecoveryPublished := false.B - backendCleanupDone := false.B - ifuRecoverySeen := false.B - }.otherwise { - when(productionBruFlush) { - ifuRecoverySeen := true.B - } - when(recoveryBlockReady) { - backendRecoveryPublished := true.B - } - when(backendCleanupConsumed || noBackendSuffixAfterIfuRecovery) { - backendCleanupDone := true.B - } - when(recoveryTransactionComplete) { - pendingBackendRecovery := false.B - backendRecoveryPublished := false.B - backendCleanupDone := false.B - ifuRecoverySeen := false.B - } - } - - def matchesRecovery(uop: RenamedUop): Bool = { - val candidate = uop.prediction - uop.valid && candidate.valid && - uop.peId === io.productionIfuFlush.peId && - uop.threadId === io.productionIfuFlush.threadId && - candidate.transactionId === io.productionIfuFlush.transactionId && - candidate.predictionTag === io.productionIfuFlush.predictionTag && - candidate.fetchPacketUid === io.productionIfuFlush.fetchPacketUid && - candidate.fetchSeq === io.productionIfuFlush.fetchSeq && - candidate.epoch === io.productionIfuFlush.oldEpoch && - candidate.checkpointId === io.productionIfuFlush.checkpointId - } - - val expectedBruFlushPending = RegInit(false.B) - val expectedBruFlushUop = RegInit(0.U.asTypeOf(new RenamedUop(p))) - - when(completingValidationMispredict) { - assert( - !expectedBruFlushPending, - "production backend must serialize BRU recoveries until the IFU acknowledges the exact key") - expectedBruFlushPending := true.B - expectedBruFlushUop := queue.io.enq.bits.uop - }.elsewhen(productionBruFlush) { - expectedBruFlushPending := false.B - } - - // SETC may precede ordinary instructions in the same architectural block. - // Freeze commit as soon as a mismatch is known, but let the current block - // finish execution. Once every resident row with the SETC's exact full BID - // is complete, the IFU may remove still-unallocated wrong-path ingress. - // Only a resident next RID triggers canonical backend suffix cleanup; when - // no suffix has reached the ROB, the exact IFU BRU flush clears D1/dec-ren - // and completes the transaction without fabricating a ROB recovery. This - // avoids waiting for the successor that the BRU redirect itself must fetch. - // The validation queue survives until the IFU acknowledges the exact key. - productionBruRecoveryUop.valid := - useProductionD1Ingress.B && recoveryBlockReady - productionBruRecoveryUop.bits := activeRecoveryUop - productionBruRecoveryUop.bits.rid := path.io.recoveryBlockLastRid - - when(productionBruFlush) { - assert( - expectedBruFlushPending && matchesRecovery(expectedBruFlushUop), - "production IFU BRU flush must acknowledge the exact admitted backend validation identity") - } - - when(useProductionD1Ingress.B && execute.io.branchConditionValid && setcOwnsValidation) { - assert(prediction.valid, "SETC validation requires the final D1 prediction sidecar") - assert( - queue.io.enq.ready, - "production backend validation queue must accept every completing SETC") - } - // Do not admit the predicted body until Dispatch either validates the - // marker or the exact BRU recovery arrives. This keeps a mismatching - // direct/call from orphaning already-allocated body rows in the ROB. - (productionBruRecoveryUop, dispatchQueue.io.enq.ready && !dispatchValidationPending) - } -} - -private object LinxCoreFrontendFetchRfAluTraceTopProductionD1Wiring { - def connect( - io: LinxCoreFrontendFetchRfAluTraceTopIO, - path: DecodeRenameROBPath, - denseSlots: F4DenseSlotQueue, - productionD1: D1DecodedLaneQueue, - admittedMarkerDrainBarrier: Bool, - branchValidationIngressReady: Bool, - useProductionD1Ingress: Boolean, - p: InterfaceParams): Unit = { - val productionIngressFlush = Wire(new IfuInnerFlush(p)) - productionIngressFlush := io.productionIfuFlush - when(io.startValid || io.restartValid || io.frontendFlushValid) { - productionIngressFlush := 0.U.asTypeOf(productionIngressFlush) - productionIngressFlush.valid := true.B - productionIngressFlush.peId := io.peId - productionIngressFlush.threadId := io.threadId - productionIngressFlush.restartPc := Mux(io.restartValid, io.restartPc, io.startPc) - productionIngressFlush.scope := IfuPruneScope.KillAllThreadState - } - - productionD1.io.in.valid := io.productionD1.valid && useProductionD1Ingress.B - productionD1.io.in.bits := io.productionD1.bits - io.productionD1.ready := productionD1.io.in.ready && useProductionD1Ingress.B - productionD1.io.flush := productionIngressFlush - val productionHeadIsService = - productionD1.io.out.valid && - productionD1.io.out.bits.entries(productionD1.io.headLane).opcode === - FrontendOpcodeDecodeTable.OP_ACRC.U(p.opcodeWidth.W) - productionD1.io.out.ready := - path.io.decodeReady && !admittedMarkerDrainBarrier && useProductionD1Ingress.B && - (!productionHeadIsService || productionD1.io.nextValid) && - branchValidationIngressReady - - if (useProductionD1Ingress) { - path.io.predecodedD1Valid := - productionD1.io.out.valid && !admittedMarkerDrainBarrier && branchValidationIngressReady - path.io.predecodedD1 := productionD1.io.out.bits - path.io.predecodedNextValid := - productionD1.io.nextValid && !admittedMarkerDrainBarrier - path.io.predecodedNext := productionD1.io.nextUop - path.io.d1 := 0.U.asTypeOf(path.io.d1) - path.io.slots := 0.U.asTypeOf(path.io.slots) - path.io.validMask := 0.U - path.io.samePacketNextSlotValid := false.B - path.io.samePacketNextSlot := 0.U.asTypeOf(path.io.samePacketNextSlot) - } else { - path.io.d1 := denseSlots.io.outD1 - path.io.d1.valid := denseSlots.io.outD1.valid && !admittedMarkerDrainBarrier - path.io.slots := denseSlots.io.outSlots - path.io.validMask := Mux(admittedMarkerDrainBarrier, 0.U, denseSlots.io.outValidMask) - path.io.samePacketNextSlotValid := - denseSlots.io.outNextSamePacketSlotValid && !admittedMarkerDrainBarrier - path.io.samePacketNextSlot := denseSlots.io.outNextSamePacketSlot - } - } -} - -object LinxCoreFrontendFetchRfAluTraceTop { - def interfaceParamsFor(coreParams: CoreParams, physRegWidth: Int = 6): InterfaceParams = - InterfaceParams( - robEntries = coreParams.robEntries, - commitWidth = coreParams.commitWidth, - physRegWidth = physRegWidth, - lsidWidth = coreParams.lsidWidth - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth - ) -} - -object EmitLinxCoreFrontendFetchRfAluTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchRfAluTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 32, - gprMapQDepth = 256, - physRegs = 128), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-rf-alu-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchTraceTop.scala deleted file mode 100644 index 23ea4a70..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchTraceTop.scala +++ /dev/null @@ -1,253 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.backend.DecodeRenameROBPath -import linxcore.commit.{CommitTraceParams, CommitTracePort, CommitTraceRow} -import linxcore.common.{CoreParams, InterfaceParams} -import linxcore.frontend.{F4DecodeWindow, FrontendFetchPacketSource} -import linxcore.lsu.StoreDispatchExecResult -import linxcore.rob.{ROBEntryStatus, ROBID} - -class LinxCoreFrontendFetchTraceTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val decRenQueueDepth: Int = 4) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - private val sizeWidth = log2Ceil(p.robEntries + 1) - private val decRenCountWidth = log2Ceil(decRenQueueDepth + 1) - - val startValid = Input(Bool()) - val startPc = Input(UInt(p.pcWidth.W)) - val restartValid = Input(Bool()) - val restartPc = Input(UInt(p.pcWidth.W)) - val frontendFlushValid = Input(Bool()) - val peId = Input(UInt(p.peIdWidth.W)) - val threadId = Input(UInt(p.threadIdWidth.W)) - - val fetchReqReady = Input(Bool()) - val fetchRespValid = Input(Bool()) - val fetchRespWindow = Input(UInt(p.windowWidth.W)) - - val completeValid = Input(Bool()) - val completeRobValue = Input(UInt(ptrWidth.W)) - val deallocReady = Input(Bool()) - - val fetchReqValid = Output(Bool()) - val fetchReqPc = Output(UInt(p.pcWidth.W)) - val fetchRespReady = Output(Bool()) - val sourceActive = Output(Bool()) - val sourceWaitingResponse = Output(Bool()) - val sourcePacketValid = Output(Bool()) - val sourceReqFire = Output(Bool()) - val sourceRespFire = Output(Bool()) - val sourceOutFire = Output(Bool()) - val sourceAdvanceZero = Output(Bool()) - val sourceAdvanceBytes = Output(UInt(4.W)) - val sourceCurrentPc = Output(UInt(p.pcWidth.W)) - val sourceIssuedPc = Output(UInt(p.pcWidth.W)) - val sourceNextPktUid = Output(UInt(p.uopUidWidth.W)) - - val f4ValidMask = Output(UInt(p.decodeWidth.W)) - val f4SlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val decodeReady = Output(Bool()) - val selectedValid = Output(Bool()) - val selectedRobValue = Output(UInt(ptrWidth.W)) - val selectedBlockBid = Output(UInt(p.blockBidWidth.W)) - val decRenPushFire = Output(Bool()) - val decRenPopFire = Output(Bool()) - val decRenCount = Output(UInt(decRenCountWidth.W)) - val renamedOutValid = Output(Bool()) - val renamedAccepted = Output(Bool()) - val robAllocFire = Output(Bool()) - val robRenameUpdateFire = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeIgnored = Output(Bool()) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val deallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val deallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val outstandingCount = Output(UInt(sizeWidth.W)) - val commitHeadValid = Output(Bool()) - val commitHeadStatus = Output(ROBEntryStatus()) - val commitHeadRobValue = Output(UInt(ptrWidth.W)) - val occupiedMask = Output(UInt(p.robEntries.W)) - val completedMask = Output(UInt(p.robEntries.W)) - val retiredMask = Output(UInt(p.robEntries.W)) - val idle = Output(Bool()) -} - -class LinxCoreFrontendFetchTraceTop( - val coreParams: CoreParams = CoreParams(), - val decRenQueueDepth: Int = 4, - val storeDispatchQueueDepth: Int = 4, - val mapQDepth: Int = 32) - extends Module { - private val p = LinxCoreFrontendFetchTraceTop.interfaceParamsFor(coreParams) - private val traceParams = LinxCoreFrontendFetchTraceTop.traceParamsFor(p) - val io = IO(new LinxCoreFrontendFetchTraceTopIO(p, traceParams, decRenQueueDepth)) - - val source = Module(new FrontendFetchPacketSource(p)) - val f4 = Module(new F4DecodeWindow(p)) - val path = Module(new DecodeRenameROBPath( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - mapQDepth = mapQDepth - )) - DecodeRenameROBPath.tieOffPredecoded(path) - - source.io.startValid := io.startValid - source.io.startPc := io.startPc - source.io.restartValid := io.restartValid - source.io.restartPc := io.restartPc - source.io.flushValid := io.frontendFlushValid - source.io.peId := io.peId - source.io.threadId := io.threadId - source.io.reqReady := io.fetchReqReady - source.io.respValid := io.fetchRespValid - source.io.respWindow := io.fetchRespWindow - source.io.outReady := path.io.decodeReady - source.io.advanceBytes := f4.io.totalLenBytes - - f4.io.in := source.io.out - f4.io.flushValid := io.frontendFlushValid - - path.io.d1 := f4.io.d1 - path.io.slots := f4.io.slots - path.io.validMask := f4.io.validMask - path.io.samePacketNextSlotValid := false.B - path.io.samePacketNextSlot := 0.U.asTypeOf(path.io.samePacketNextSlot) - path.io.flushValid := io.frontendFlushValid - DecodeRenameROBPath.tieOffExplicitStoreCount(path) - DecodeRenameROBPath.tieOffStoreScResult(path) - path.io.storeAddressInsertPermit := true.B - path.io.renamedOutReady := true.B - path.io.storeStaExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeStdExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeMarkCommitValid := false.B - path.io.storeMarkCommitIndex := 0.U - path.io.storeCommitFreeValid := false.B - path.io.storeCommitFreeIndex := 0.U - path.io.storeCommitFreeMaskValid := false.B - path.io.storeCommitFreeMask := 0.U - path.io.deallocHoldMask := 0.U - path.io.checkpointValid := false.B - path.io.checkpointBid := ROBID.disabled(p.robEntries) - path.io.checkpointStid := 0.U - path.io.commitValid := false.B - path.io.commitBid := ROBID.disabled(p.robEntries) - path.io.commitBlockBid := 0.U - path.io.commitStid := 0.U - DecodeRenameROBPath.tieOffRecovery(path) - path.io.scalarCleanupOrderValid := false.B - path.io.scalarCleanupOrder := 0.U - path.io.completeValid := io.completeValid - path.io.completeRobValue := io.completeRobValue - path.io.completeRowValid := false.B - path.io.completeRow := 0.U.asTypeOf(new CommitTraceRow(traceParams)) - path.io.blockBranchTakenValid := false.B - path.io.blockBranchTaken := false.B - path.io.scalarRedirectValid := false.B - path.io.scalarRedirectStid := 0.U - path.io.deallocReady := io.deallocReady - path.io.robStatusLookupValid := false.B - path.io.robStatusLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupValid := false.B - path.io.robCommitTraceLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupSourceTraceEnable := false.B - - io.fetchReqValid := source.io.reqValid - io.fetchReqPc := source.io.reqPc - io.fetchRespReady := source.io.respReady - io.sourceActive := source.io.active - io.sourceWaitingResponse := source.io.waitingResponse - io.sourcePacketValid := source.io.packetValid - io.sourceReqFire := source.io.reqFire - io.sourceRespFire := source.io.respFire - io.sourceOutFire := source.io.outFire - io.sourceAdvanceZero := source.io.advanceZero - io.sourceAdvanceBytes := f4.io.totalLenBytes - io.sourceCurrentPc := source.io.currentPc - io.sourceIssuedPc := source.io.issuedPc - io.sourceNextPktUid := source.io.nextPktUid - - io.f4ValidMask := f4.io.validMask - io.f4SlotCount := f4.io.slotCount - io.decodeReady := path.io.decodeReady - io.selectedValid := path.io.selectedValid - io.selectedRobValue := path.io.selectedRobValue - io.selectedBlockBid := path.io.selectedBlockBid - io.decRenPushFire := path.io.decRenPushFire - io.decRenPopFire := path.io.decRenPopFire - io.decRenCount := path.io.decRenCount - io.renamedOutValid := path.io.renamedOutValid - io.renamedAccepted := path.io.accepted - io.robAllocFire := path.io.robAllocFire - io.robRenameUpdateFire := path.io.robRenameUpdateFire - io.completeAccepted := path.io.completeAccepted - io.completeIgnored := path.io.completeIgnored - - io.commit := path.io.commit - io.commitValidMask := path.io.commitValidMask - io.commitCount := path.io.commitCount - io.commitMonitorValidMask := path.io.commitMonitorValidMask - io.commitMonitorValidCount := path.io.commitMonitorValidCount - io.commitSkippedSlot := path.io.commitSkippedSlot - io.commitDuplicateIdentity := path.io.commitDuplicateIdentity - io.commitSlotMismatch := path.io.commitSlotMismatch - io.commitInvalidSideEffect := path.io.commitInvalidSideEffect - io.commitContractError := path.io.commitContractError - - io.deallocValidMask := path.io.deallocValidMask - io.deallocCount := path.io.deallocCount - io.empty := path.io.empty - io.full := path.io.full - io.size := path.io.size - io.outstandingCount := path.io.outstandingCount - io.commitHeadValid := path.io.commitHeadValid - io.commitHeadStatus := path.io.commitHeadStatus - io.commitHeadRobValue := path.io.commitHeadRobValue - io.occupiedMask := path.io.occupiedMask - io.completedMask := path.io.completedMask - io.retiredMask := path.io.retiredMask - io.idle := path.io.empty && !source.io.waitingResponse && !source.io.packetValid -} - -object LinxCoreFrontendFetchTraceTop { - def interfaceParamsFor(coreParams: CoreParams): InterfaceParams = - InterfaceParams( - robEntries = coreParams.robEntries, - commitWidth = coreParams.commitWidth - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth - ) -} - -object EmitLinxCoreFrontendFetchTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendFetchTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-fetch-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendRfAluTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendRfAluTraceTop.scala deleted file mode 100644 index 6ce13b07..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendRfAluTraceTop.scala +++ /dev/null @@ -1,415 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.backend.DecodeRenameROBPath -import linxcore.commit.{CommitTraceParams, CommitTracePort} -import linxcore.common.{CoreParams, FrontendDecodePacket, InterfaceParams} -import linxcore.execute.{ReducedScalarAluExecute, ScalarGPRFile, ScalarIssueFabric} -import linxcore.frontend.F4DecodeWindow -import linxcore.lsu.StoreDispatchExecResult -import linxcore.rob.{ROBEntryStatus, ROBID} - -class LinxCoreFrontendRfAluTraceTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val decRenQueueDepth: Int = 4, - val issueQueueDepth: Int = 4, - val physRegs: Int = 64, - val issueBankCount: Int = 2) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - private val sizeWidth = log2Ceil(p.robEntries + 1) - private val decRenCountWidth = log2Ceil(decRenQueueDepth + 1) - private val issueCountWidth = log2Ceil(issueQueueDepth + 1) - private val issueBankCountWidth = log2Ceil(issueQueueDepth / issueBankCount + 1) - - val in = Input(new FrontendDecodePacket(p)) - val rfInitValid = Input(Bool()) - val rfInitArchTag = Input(UInt(p.archRegWidth.W)) - val rfInitData = Input(UInt(p.immWidth.W)) - val frontendFlushValid = Input(Bool()) - val deallocReady = Input(Bool()) - - val f4ValidMask = Output(UInt(p.decodeWidth.W)) - val f4SlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val decodeReady = Output(Bool()) - val selectedValid = Output(Bool()) - val selectedRobValue = Output(UInt(ptrWidth.W)) - val selectedBlockBid = Output(UInt(p.blockBidWidth.W)) - val decRenPushFire = Output(Bool()) - val decRenPopFire = Output(Bool()) - val decRenCount = Output(UInt(decRenCountWidth.W)) - val renamedOutValid = Output(Bool()) - val renamedAccepted = Output(Bool()) - val executeAccepted = Output(Bool()) - val executeBusy = Output(Bool()) - val executeCompleteValid = Output(Bool()) - val executeCompleteRobValue = Output(UInt(ptrWidth.W)) - val executeUnsupported = Output(Bool()) - val executeUnsupportedOpcode = Output(UInt(p.opcodeWidth.W)) - val robAllocFire = Output(Bool()) - val robRenameUpdateFire = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeIgnored = Output(Bool()) - - val rfReadReadyMask = Output(UInt(3.W)) - val rfAllReadReady = Output(Bool()) - val rfReadyMask = Output(UInt(physRegs.W)) - val rfWriteValid = Output(Bool()) - val rfWriteTag = Output(UInt(p.physRegWidth.W)) - val rfWriteData = Output(UInt(p.immWidth.W)) - val rfStateError = Output(Bool()) - val issueQueueEnqueueFire = Output(Bool()) - val issueQueuePickFire = Output(Bool()) - val issueQueueIssueFire = Output(Bool()) - val issueQueueCancelFire = Output(Bool()) - val issueQueueReleaseFire = Output(Bool()) - val issueQueueCount = Output(UInt(issueCountWidth.W)) - val issueQueueIssuedCount = Output(UInt(issueCountWidth.W)) - val issueQueueNotIssuedCount = Output(UInt(issueCountWidth.W)) - val issueQueueHeadValid = Output(Bool()) - val issueQueueHeadIssued = Output(Bool()) - val issueQueueSourceReadyMask = Output(UInt(3.W)) - val issueQueueAllSourcesReady = Output(Bool()) - val issueQueueSelectedValid = Output(Bool()) - val issueQueueSelectedIndex = Output(UInt(log2Ceil(issueQueueDepth).W)) - val issueQueueSelectedReadReady = Output(Bool()) - val issueQueueI1Valid = Output(Bool()) - val issueQueueI2Valid = Output(Bool()) - val issueQueueStageBusy = Output(Bool()) - val issueQueueBlockedBySource = Output(Bool()) - val issueQueueBlockedByRead = Output(Bool()) - val issueQueueBlockedByOutput = Output(Bool()) - val issueQueueBlockedByIssued = Output(Bool()) - val issueQueueBankOccupancy = Output(Vec(issueBankCount, UInt(issueBankCountWidth.W))) - val issueQueueBankPickMask = Output(UInt(issueBankCount.W)) - val issueQueueBankReadAttemptMask = Output(UInt(issueBankCount.W)) - val issueQueueBankReadGrantMask = Output(UInt(issueBankCount.W)) - val issueQueueBankIssueValidMask = Output(UInt(issueBankCount.W)) - val issueQueueBankIssueGrantMask = Output(UInt(issueBankCount.W)) - val issueQueueSimultaneousPick = Output(Bool()) - val issueQueueReadContention = Output(Bool()) - val issueQueueReadArbitrationLoss = Output(Bool()) - val issueQueueIssueContention = Output(Bool()) - val issueQueueControlFenceActive = Output(Bool()) - val issueQueueControlFenceBlocked = Output(Bool()) - val issueQueueBankControlBlockedMask = Output(UInt(issueBankCount.W)) - val issueQueueStoreOrderBlocked = Output(Bool()) - val issueQueueBankStoreOrderBlockedMask = Output(UInt(issueBankCount.W)) - val issueQueueProtocolError = Output(Bool()) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val deallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val deallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val outstandingCount = Output(UInt(sizeWidth.W)) - val commitHeadValid = Output(Bool()) - val commitHeadStatus = Output(ROBEntryStatus()) - val commitHeadRobValue = Output(UInt(ptrWidth.W)) - val occupiedMask = Output(UInt(p.robEntries.W)) - val completedMask = Output(UInt(p.robEntries.W)) - val retiredMask = Output(UInt(p.robEntries.W)) - val idle = Output(Bool()) -} - -class LinxCoreFrontendRfAluTraceTop( - val coreParams: CoreParams = CoreParams(), - val decRenQueueDepth: Int = 4, - val issueQueueDepth: Int = 4, - val storeDispatchQueueDepth: Int = 4, - val mapQDepth: Int = 32, - val archRegs: Int = 24, - val physRegs: Int = 64) - extends Module { - private val p = LinxCoreFrontendRfAluTraceTop.interfaceParamsFor(coreParams) - require(physRegs == (1 << p.physRegWidth), - "physical GPR capacity must match the complete physical-tag namespace") - private val traceParams = LinxCoreFrontendRfAluTraceTop.traceParamsFor(p) - val io = IO(new LinxCoreFrontendRfAluTraceTopIO( - p, - traceParams, - decRenQueueDepth, - issueQueueDepth, - physRegs, - coreParams.scalarBackend.scalarIssueBanks - )) - - val f4 = Module(new F4DecodeWindow(p)) - f4.io.in := io.in - f4.io.flushValid := io.frontendFlushValid - - val path = Module(new DecodeRenameROBPath( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - mapQDepth = mapQDepth - )) - DecodeRenameROBPath.tieOffPredecoded(path) - - val rf = Module(new ScalarGPRFile( - archRegs = archRegs, - physRegs = physRegs, - dataWidth = p.immWidth, - readPorts = coreParams.scalarBackend.gprReadPorts, - writePorts = 1 - )) - val issue = Module(new ScalarIssueFabric( - p, - depth = issueQueueDepth, - bankCount = coreParams.scalarBackend.scalarIssueBanks - )) - val execute = Module(new ReducedScalarAluExecute(p, traceParams)) - execute.io.completeReady := true.B - val scalarSpValue = RegInit(0.U(p.immWidth.W)) - - path.io.d1 := f4.io.d1 - path.io.slots := f4.io.slots - path.io.validMask := f4.io.validMask - path.io.samePacketNextSlotValid := false.B - path.io.samePacketNextSlot := 0.U.asTypeOf(path.io.samePacketNextSlot) - path.io.flushValid := io.frontendFlushValid - DecodeRenameROBPath.tieOffExplicitStoreCount(path) - DecodeRenameROBPath.tieOffStoreScResult(path) - path.io.storeAddressInsertPermit := true.B - path.io.renamedOutReady := issue.io.inReady - path.io.storeStaExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeStdExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeMarkCommitValid := false.B - path.io.storeMarkCommitIndex := 0.U - path.io.storeCommitFreeValid := false.B - path.io.storeCommitFreeIndex := 0.U - path.io.storeCommitFreeMaskValid := false.B - path.io.storeCommitFreeMask := 0.U - path.io.deallocHoldMask := 0.U - path.io.checkpointValid := false.B - path.io.checkpointBid := ROBID.disabled(p.robEntries) - path.io.checkpointStid := 0.U - path.io.commitValid := false.B - path.io.commitBid := ROBID.disabled(p.robEntries) - path.io.commitBlockBid := 0.U - path.io.commitStid := 0.U - DecodeRenameROBPath.tieOffRecovery(path) - path.io.scalarCleanupOrderValid := false.B - path.io.scalarCleanupOrder := 0.U - path.io.completeValid := execute.io.completeValid - path.io.completeRobValue := execute.io.completeRobValue - path.io.completeRowValid := execute.io.completeValid - path.io.completeRow := execute.io.completeRow - path.io.blockBranchTakenValid := false.B - path.io.blockBranchTaken := false.B - path.io.scalarRedirectValid := false.B - path.io.scalarRedirectStid := 0.U - path.io.deallocReady := io.deallocReady - path.io.robStatusLookupValid := false.B - path.io.robStatusLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupValid := false.B - path.io.robCommitTraceLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupSourceTraceEnable := false.B - - issue.io.inValid := path.io.renamedOutValid && path.io.renamedOutReady - issue.io.in := path.io.renamedOut - issue.io.flushValid := io.frontendFlushValid - issue.io.releaseValid := execute.io.releaseValid - issue.io.releaseBid := execute.io.releaseBid - issue.io.releaseRid := execute.io.releaseRid - issue.io.releaseStid := execute.io.releaseStid - issue.io.secondaryReleaseValid := false.B - issue.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - issue.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - issue.io.secondaryReleaseStid := 0.U - issue.io.tertiaryReleaseValid := execute.io.earlyReleaseValid - issue.io.tertiaryReleaseBid := execute.io.earlyReleaseBid - issue.io.tertiaryReleaseRid := execute.io.earlyReleaseRid - issue.io.tertiaryReleaseStid := execute.io.earlyReleaseStid - issue.io.externalControlFenceValid := false.B - issue.io.externalControlFenceBid := ROBID.disabled(p.robEntries) - issue.io.externalControlFenceRid := ROBID.disabled(p.robEntries) - issue.io.externalControlFenceStid := 0.U - issue.io.scalarSpHeadValidByStid(0) := true.B - issue.io.scalarSpHeadBidByStid(0).valid := true.B - issue.io.scalarSpHeadBidByStid(0).wrap := false.B - issue.io.scalarSpHeadBidByStid(0).value := path.io.renamedOut.rid.value - issue.io.scalarSpHeadRidByStid(0).valid := true.B - issue.io.scalarSpHeadRidByStid(0).wrap := false.B - issue.io.scalarSpHeadRidByStid(0).value := path.io.renamedOut.rid.value - issue.io.scalarSpSnapshotByStid(0) := scalarSpValue - issue.io.readyMask := rf.io.readyMask - issue.io.pWakeupValid := rf.io.write(0).fire - issue.io.pWakeupTag := rf.io.write(0).tag - issue.io.localTReadyMask := 0.U - issue.io.localUReadyMask := 0.U - - val rfInitTagInRange = io.rfInitArchTag < archRegs.U - rf.io.initValid := io.rfInitValid && rfInitTagInRange - rf.io.initTag := io.rfInitArchTag - rf.io.initData := io.rfInitData - when(io.rfInitValid && io.rfInitArchTag === 1.U) { - scalarSpValue := io.rfInitData - } - for (idx <- 0 until 3) { - rf.io.readValid(idx) := issue.io.readValid(idx) - rf.io.readTag(idx) := issue.io.readTags(idx) - issue.io.readData(idx) := rf.io.readData(idx) - } - for (idx <- 3 until coreParams.scalarBackend.gprReadPorts) { - rf.io.readValid(idx) := false.B - rf.io.readTag(idx) := 0.U - } - rf.io.clearValid := issue.io.inputAcceptDstValid - rf.io.clearTag := issue.io.inputAcceptDstTag - rf.io.clearSecondValid := false.B - rf.io.clearSecondTag := 0.U - rf.io.write(0).requestValid := execute.io.completeDstPhysValid - rf.io.write(0).commit := execute.io.completeDstPhysValid - rf.io.write(0).tag := execute.io.completeDstPhysTag - rf.io.write(0).data := execute.io.completeDstData - when(execute.io.completeValid && execute.io.completeRow.wb.valid && execute.io.completeRow.wb.reg === 1.U) { - scalarSpValue := execute.io.completeRow.wb.data - } - - issue.io.issueReady := execute.io.inReady - execute.io.inValid := issue.io.issueValid - execute.io.in := issue.io.issueUop - execute.io.srcData := issue.io.issueSrcData - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := scalarSpValue - execute.io.flushValid := io.frontendFlushValid - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.f4ValidMask := f4.io.validMask - io.f4SlotCount := f4.io.slotCount - io.decodeReady := path.io.decodeReady - io.selectedValid := path.io.selectedValid - io.selectedRobValue := path.io.selectedRobValue - io.selectedBlockBid := path.io.selectedBlockBid - io.decRenPushFire := path.io.decRenPushFire - io.decRenPopFire := path.io.decRenPopFire - io.decRenCount := path.io.decRenCount - io.renamedOutValid := path.io.renamedOutValid - io.renamedAccepted := path.io.accepted - io.executeAccepted := execute.io.accepted - io.executeBusy := execute.io.busy - io.executeCompleteValid := execute.io.completeValid - io.executeCompleteRobValue := execute.io.completeRobValue - io.executeUnsupported := execute.io.unsupported - io.executeUnsupportedOpcode := execute.io.unsupportedOpcode - io.robAllocFire := path.io.robAllocFire - io.robRenameUpdateFire := path.io.robRenameUpdateFire - io.completeAccepted := path.io.completeAccepted - io.completeIgnored := path.io.completeIgnored - - io.rfReadReadyMask := VecInit(rf.io.readReady.take(3)).asUInt - io.rfAllReadReady := rf.io.readReady.take(3).reduce(_ && _) - io.rfReadyMask := rf.io.readyMask - io.rfWriteValid := rf.io.write(0).fire - io.rfWriteTag := execute.io.completeDstPhysTag - io.rfWriteData := execute.io.completeDstData - io.rfStateError := (io.rfInitValid && !rfInitTagInRange) || rf.io.protocolError || issue.io.protocolError - io.issueQueueEnqueueFire := issue.io.inputAcceptFire - io.issueQueuePickFire := issue.io.pickFire - io.issueQueueIssueFire := issue.io.issueFire - io.issueQueueCancelFire := issue.io.cancelFire - io.issueQueueReleaseFire := issue.io.releaseFire - io.issueQueueCount := issue.io.count - io.issueQueueIssuedCount := issue.io.issuedCount - io.issueQueueNotIssuedCount := issue.io.notIssuedCount - io.issueQueueHeadValid := issue.io.headValid - io.issueQueueHeadIssued := issue.io.headIssued - io.issueQueueSourceReadyMask := issue.io.sourceReadyMask - io.issueQueueAllSourcesReady := issue.io.allSourcesReady - io.issueQueueSelectedValid := issue.io.selectedValid - io.issueQueueSelectedIndex := issue.io.selectedIndex - io.issueQueueSelectedReadReady := issue.io.selectedReadReady - io.issueQueueI1Valid := issue.io.i1Valid - io.issueQueueI2Valid := issue.io.i2Valid - io.issueQueueStageBusy := issue.io.stageBusy - io.issueQueueBlockedBySource := issue.io.blockedBySource - io.issueQueueBlockedByRead := issue.io.blockedByRead - io.issueQueueBlockedByOutput := issue.io.blockedByOutput - io.issueQueueBlockedByIssued := issue.io.blockedByIssued - io.issueQueueBankOccupancy := issue.io.bankOccupancy - io.issueQueueBankPickMask := issue.io.bankPickMask - io.issueQueueBankReadAttemptMask := issue.io.bankReadAttemptMask - io.issueQueueBankReadGrantMask := issue.io.bankReadGrantMask - io.issueQueueBankIssueValidMask := issue.io.bankIssueValidMask - io.issueQueueBankIssueGrantMask := issue.io.bankIssueGrantMask - io.issueQueueSimultaneousPick := issue.io.simultaneousPick - io.issueQueueReadContention := issue.io.readContention - io.issueQueueReadArbitrationLoss := issue.io.readArbitrationLoss - io.issueQueueIssueContention := issue.io.issueContention - io.issueQueueControlFenceActive := issue.io.controlFenceActive - io.issueQueueControlFenceBlocked := issue.io.controlFenceBlocked - io.issueQueueBankControlBlockedMask := issue.io.bankControlBlockedMask - io.issueQueueStoreOrderBlocked := issue.io.storeOrderBlocked - io.issueQueueBankStoreOrderBlockedMask := issue.io.bankStoreOrderBlockedMask - io.issueQueueProtocolError := issue.io.protocolError - - io.commit := path.io.commit - io.commitValidMask := path.io.commitValidMask - io.commitCount := path.io.commitCount - io.commitMonitorValidMask := path.io.commitMonitorValidMask - io.commitMonitorValidCount := path.io.commitMonitorValidCount - io.commitSkippedSlot := path.io.commitSkippedSlot - io.commitDuplicateIdentity := path.io.commitDuplicateIdentity - io.commitSlotMismatch := path.io.commitSlotMismatch - io.commitInvalidSideEffect := path.io.commitInvalidSideEffect - io.commitContractError := path.io.commitContractError - - io.deallocValidMask := path.io.deallocValidMask - io.deallocCount := path.io.deallocCount - io.empty := path.io.empty - io.full := path.io.full - io.size := path.io.size - io.outstandingCount := path.io.outstandingCount - io.commitHeadValid := path.io.commitHeadValid - io.commitHeadStatus := path.io.commitHeadStatus - io.commitHeadRobValue := path.io.commitHeadRobValue - io.occupiedMask := path.io.occupiedMask - io.completedMask := path.io.completedMask - io.retiredMask := path.io.retiredMask - io.idle := path.io.empty && issue.io.empty && !execute.io.busy -} - -object LinxCoreFrontendRfAluTraceTop { - def interfaceParamsFor(coreParams: CoreParams): InterfaceParams = - InterfaceParams( - robEntries = coreParams.robEntries, - commitWidth = coreParams.commitWidth - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth - ) -} - -object EmitLinxCoreFrontendRfAluTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendRfAluTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-rf-alu-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendTraceTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreFrontendTraceTop.scala deleted file mode 100644 index 3c6d6da3..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreFrontendTraceTop.scala +++ /dev/null @@ -1,199 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.backend.DecodeRenameROBPath -import linxcore.commit.{CommitTraceParams, CommitTracePort, CommitTraceRow} -import linxcore.common.{CoreParams, FrontendDecodePacket, InterfaceParams} -import linxcore.frontend.F4DecodeWindow -import linxcore.lsu.StoreDispatchExecResult -import linxcore.rob.{ROBEntryStatus, ROBID} - -class LinxCoreFrontendTraceTopIO( - val p: InterfaceParams, - val traceParams: CommitTraceParams, - val decRenQueueDepth: Int = 4) - extends Bundle { - private val ptrWidth = log2Ceil(p.robEntries) - private val sizeWidth = log2Ceil(p.robEntries + 1) - private val decRenCountWidth = log2Ceil(decRenQueueDepth + 1) - - val in = Input(new FrontendDecodePacket(p)) - val frontendFlushValid = Input(Bool()) - val completeValid = Input(Bool()) - val completeRobValue = Input(UInt(ptrWidth.W)) - val deallocReady = Input(Bool()) - - val f4ValidMask = Output(UInt(p.decodeWidth.W)) - val f4SlotCount = Output(UInt(log2Ceil(p.decodeWidth + 1).W)) - val decodeReady = Output(Bool()) - val selectedValid = Output(Bool()) - val selectedRobValue = Output(UInt(ptrWidth.W)) - val selectedBlockBid = Output(UInt(p.blockBidWidth.W)) - val decRenPushFire = Output(Bool()) - val decRenPopFire = Output(Bool()) - val decRenCount = Output(UInt(decRenCountWidth.W)) - val renamedOutValid = Output(Bool()) - val renamedAccepted = Output(Bool()) - val robAllocFire = Output(Bool()) - val robRenameUpdateFire = Output(Bool()) - val completeAccepted = Output(Bool()) - val completeIgnored = Output(Bool()) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val deallocValidMask = Output(UInt(traceParams.commitWidth.W)) - val deallocCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val outstandingCount = Output(UInt(sizeWidth.W)) - val commitHeadValid = Output(Bool()) - val commitHeadStatus = Output(ROBEntryStatus()) - val commitHeadRobValue = Output(UInt(ptrWidth.W)) - val occupiedMask = Output(UInt(p.robEntries.W)) - val completedMask = Output(UInt(p.robEntries.W)) - val retiredMask = Output(UInt(p.robEntries.W)) - val idle = Output(Bool()) -} - -class LinxCoreFrontendTraceTop( - val coreParams: CoreParams = CoreParams(), - val decRenQueueDepth: Int = 4, - val storeDispatchQueueDepth: Int = 4, - val mapQDepth: Int = 32) - extends Module { - private val p = LinxCoreFrontendTraceTop.interfaceParamsFor(coreParams) - private val traceParams = LinxCoreFrontendTraceTop.traceParamsFor(p) - val io = IO(new LinxCoreFrontendTraceTopIO(p, traceParams, decRenQueueDepth)) - - val f4 = Module(new F4DecodeWindow(p)) - f4.io.in := io.in - f4.io.flushValid := io.frontendFlushValid - - val path = Module(new DecodeRenameROBPath( - p = p, - traceParams = traceParams, - decRenQueueDepth = decRenQueueDepth, - storeDispatchQueueDepth = storeDispatchQueueDepth, - mapQDepth = mapQDepth - )) - DecodeRenameROBPath.tieOffPredecoded(path) - - path.io.d1 := f4.io.d1 - path.io.slots := f4.io.slots - path.io.validMask := f4.io.validMask - path.io.samePacketNextSlotValid := false.B - path.io.samePacketNextSlot := 0.U.asTypeOf(path.io.samePacketNextSlot) - path.io.flushValid := io.frontendFlushValid - DecodeRenameROBPath.tieOffExplicitStoreCount(path) - DecodeRenameROBPath.tieOffStoreScResult(path) - path.io.storeAddressInsertPermit := true.B - path.io.renamedOutReady := true.B - path.io.storeStaExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeStdExec := 0.U.asTypeOf(new StoreDispatchExecResult(64, 64, p.peIdWidth, p.threadIdWidth, p.threadIdWidth)) - path.io.storeMarkCommitValid := false.B - path.io.storeMarkCommitIndex := 0.U - path.io.storeCommitFreeValid := false.B - path.io.storeCommitFreeIndex := 0.U - path.io.storeCommitFreeMaskValid := false.B - path.io.storeCommitFreeMask := 0.U - path.io.deallocHoldMask := 0.U - path.io.checkpointValid := false.B - path.io.checkpointBid := ROBID.disabled(p.robEntries) - path.io.checkpointStid := 0.U - path.io.commitValid := false.B - path.io.commitBid := ROBID.disabled(p.robEntries) - path.io.commitBlockBid := 0.U - path.io.commitStid := 0.U - DecodeRenameROBPath.tieOffRecovery(path) - path.io.scalarCleanupOrderValid := false.B - path.io.scalarCleanupOrder := 0.U - path.io.completeValid := io.completeValid - path.io.completeRobValue := io.completeRobValue - path.io.completeRowValid := false.B - path.io.completeRow := 0.U.asTypeOf(new CommitTraceRow(traceParams)) - path.io.blockBranchTakenValid := false.B - path.io.blockBranchTaken := false.B - path.io.scalarRedirectValid := false.B - path.io.scalarRedirectStid := 0.U - path.io.deallocReady := io.deallocReady - path.io.robStatusLookupValid := false.B - path.io.robStatusLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupValid := false.B - path.io.robCommitTraceLookupRid := ROBID.disabled(p.robEntries) - path.io.robCommitTraceLookupSourceTraceEnable := false.B - - io.f4ValidMask := f4.io.validMask - io.f4SlotCount := f4.io.slotCount - io.decodeReady := path.io.decodeReady - io.selectedValid := path.io.selectedValid - io.selectedRobValue := path.io.selectedRobValue - io.selectedBlockBid := path.io.selectedBlockBid - io.decRenPushFire := path.io.decRenPushFire - io.decRenPopFire := path.io.decRenPopFire - io.decRenCount := path.io.decRenCount - io.renamedOutValid := path.io.renamedOutValid - io.renamedAccepted := path.io.accepted - io.robAllocFire := path.io.robAllocFire - io.robRenameUpdateFire := path.io.robRenameUpdateFire - io.completeAccepted := path.io.completeAccepted - io.completeIgnored := path.io.completeIgnored - - io.commit := path.io.commit - io.commitValidMask := path.io.commitValidMask - io.commitCount := path.io.commitCount - io.commitMonitorValidMask := path.io.commitMonitorValidMask - io.commitMonitorValidCount := path.io.commitMonitorValidCount - io.commitSkippedSlot := path.io.commitSkippedSlot - io.commitDuplicateIdentity := path.io.commitDuplicateIdentity - io.commitSlotMismatch := path.io.commitSlotMismatch - io.commitInvalidSideEffect := path.io.commitInvalidSideEffect - io.commitContractError := path.io.commitContractError - - io.deallocValidMask := path.io.deallocValidMask - io.deallocCount := path.io.deallocCount - io.empty := path.io.empty - io.full := path.io.full - io.size := path.io.size - io.outstandingCount := path.io.outstandingCount - io.commitHeadValid := path.io.commitHeadValid - io.commitHeadStatus := path.io.commitHeadStatus - io.commitHeadRobValue := path.io.commitHeadRobValue - io.occupiedMask := path.io.occupiedMask - io.completedMask := path.io.completedMask - io.retiredMask := path.io.retiredMask - io.idle := path.io.empty -} - -object LinxCoreFrontendTraceTop { - def interfaceParamsFor(coreParams: CoreParams): InterfaceParams = - InterfaceParams( - robEntries = coreParams.robEntries, - commitWidth = coreParams.commitWidth - ) - - def traceParamsFor(p: InterfaceParams): CommitTraceParams = - CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth - ) -} - -object EmitLinxCoreFrontendTraceTop extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreFrontendTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8), - args = Array("--target-dir", "../generated/chisel-verilog/frontend-trace-top"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/LinxCoreTop.scala b/chisel/src/main/scala/linxcore/top/LinxCoreTop.scala deleted file mode 100644 index 4371d671..00000000 --- a/chisel/src/main/scala/linxcore/top/LinxCoreTop.scala +++ /dev/null @@ -1,206 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil -import linxcore.commit.{CommitTraceParams, CommitTracePort, CommitTraceRow} -import linxcore.common.{CoreParams, ScalarLsuParams} -import linxcore.lsu.{ScalarLSU, ScalarLSUIO} -import linxcore.rob.ReducedCommitROB - -class LinxCoreTopIO(val coreParams: CoreParams, val traceParams: CommitTraceParams) extends Bundle { - private val ptrWidth = log2Ceil(coreParams.robEntries) - private val sizeWidth = log2Ceil(coreParams.robEntries + 1) - private val gprTagWidth = log2Ceil(coreParams.scalarBackend.gprPhysRegs) - - val allocValid = Input(Bool()) - val allocReady = Output(Bool()) - val allocDuplicateIdentity = Output(Bool()) - val allocRow = Input(new CommitTraceRow(traceParams)) - - val completeValid = Input(Bool()) - val completeRobValue = Input(UInt(ptrWidth.W)) - val scalarLoadCompleteSelected = Output(Bool()) - val completeCollision = Output(Bool()) - - val scalarGprInitValid = Input(Bool()) - val scalarGprInitTag = Input(UInt(gprTagWidth.W)) - val scalarGprInitData = Input(UInt(coreParams.scalarLsu.dataWidth.W)) - val scalarGprClearValid = Input(Bool()) - val scalarGprClearTag = Input(UInt(gprTagWidth.W)) - val externalGprWriteValid = Input(Bool()) - val externalGprWriteTag = Input(UInt(gprTagWidth.W)) - val externalGprWriteData = Input(UInt(coreParams.scalarLsu.dataWidth.W)) - val externalGprWriteReady = Output(Bool()) - val externalGprWriteFire = Output(Bool()) - val scalarGprReadTag = Input(UInt(gprTagWidth.W)) - val scalarGprReadData = Output(UInt(coreParams.scalarLsu.dataWidth.W)) - val scalarGprReadReady = Output(Bool()) - val scalarGprReadyMask = Output(UInt(coreParams.scalarBackend.gprPhysRegs.W)) - val scalarLoadWritebackSelected = Output(Bool()) - val scalarLoadWakeupPublished = Output(Bool()) - val scalarLoadBlockedByExternalWrite = Output(Bool()) - val scalarLoadBlockedByUnsupportedDestination = Output(Bool()) - val scalarBackendContractError = Output(Bool()) - - val scalarLsu = new ScalarLSUIO(coreParams, coreParams.scalarLsu) - - val commit = Output(new CommitTracePort(traceParams)) - val commitValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitMonitorValidMask = Output(UInt(traceParams.commitWidth.W)) - val commitMonitorValidCount = Output(UInt(log2Ceil(traceParams.commitWidth + 1).W)) - val commitSkippedSlot = Output(Bool()) - val commitDuplicateIdentity = Output(Bool()) - val commitSlotMismatch = Output(Bool()) - val commitInvalidSideEffect = Output(Bool()) - val commitContractError = Output(Bool()) - - val empty = Output(Bool()) - val full = Output(Bool()) - val size = Output(UInt(sizeWidth.W)) - val headValid = Output(Bool()) - val headComplete = Output(Bool()) - val headRobValue = Output(UInt(ptrWidth.W)) - val idle = Output(Bool()) -} - -class LinxCoreTop(val coreParams: CoreParams = CoreParams()) extends Module { - private val traceParams = LinxCoreTop.traceParamsFor(coreParams) - val io = IO(new LinxCoreTopIO(coreParams, traceParams)) - - val commitRob = Module(new ReducedCommitROB( - entries = coreParams.robEntries, - traceParams = traceParams - )) - val scalarLsu = Module(new ScalarLSU(coreParams)) - val scalarLoadCompletion = Module(new ScalarLoadCompletionROBBridge(coreParams.robEntries)) - val scalarLoadGprSink = Module(new ScalarLoadGPRCompletionSink( - coreParams.scalarBackend, - coreParams.scalarLsu - )) - - scalarLsu.io <> io.scalarLsu - - commitRob.io.allocValid := io.allocValid - commitRob.io.allocRow := io.allocRow - io.allocReady := commitRob.io.allocReady - io.allocDuplicateIdentity := commitRob.io.allocDuplicateIdentity - - scalarLoadCompletion.io.externalCompleteValid := io.completeValid - scalarLoadCompletion.io.externalCompleteRobValue := io.completeRobValue - scalarLoadCompletion.io.loadLookupValid := scalarLsu.io.load.loadReturn.robLookupValid - scalarLoadCompletion.io.loadLookupRid := scalarLsu.io.load.loadReturn.robLookupRid - scalarLoadCompletion.io.robLookupRowValid := commitRob.io.lookupRowValid - scalarLoadCompletion.io.robLookupRowNeedFlush := commitRob.io.lookupRowNeedFlush - scalarLoadCompletion.io.loadCompletionCandidateValid := - scalarLsu.io.load.loadReturn.completionCandidateValid - scalarLoadCompletion.io.loadCompletionRid := - scalarLsu.io.load.loadReturn.completion.payload.rid - scalarLoadCompletion.io.loadResolveEnable := io.scalarLsu.load.loadReturn.resolveReady - scalarLoadCompletion.io.robExactCompleteReady := commitRob.io.exactCompleteReady - scalarLoadCompletion.io.loadResolveFire := scalarLsu.io.load.loadReturn.resolveFire - - scalarLoadGprSink.io.initValid := io.scalarGprInitValid - scalarLoadGprSink.io.initTag := io.scalarGprInitTag - scalarLoadGprSink.io.initData := io.scalarGprInitData - scalarLoadGprSink.io.clearValid := io.scalarGprClearValid - scalarLoadGprSink.io.clearTag := io.scalarGprClearTag - scalarLoadGprSink.io.externalWriteValid := io.externalGprWriteValid - scalarLoadGprSink.io.externalWriteTag := io.externalGprWriteTag - scalarLoadGprSink.io.externalWriteData := io.externalGprWriteData - scalarLoadGprSink.io.loadCandidateValid := - scalarLsu.io.load.loadReturn.completionCandidateValid - scalarLoadGprSink.io.loadDst := scalarLsu.io.load.loadReturn.completion.payload.dst - scalarLoadGprSink.io.loadData := scalarLsu.io.load.loadReturn.completion.payload.data - scalarLoadGprSink.io.loadSpecWakeup := - scalarLsu.io.load.loadReturn.completion.payload.specWakeup - scalarLoadGprSink.io.loadStackValid := - scalarLsu.io.load.loadReturn.completion.payload.stackValid - scalarLoadGprSink.io.loadResolveFire := scalarLsu.io.load.loadReturn.resolveFire - scalarLoadGprSink.io.loadWritebackFire := scalarLsu.io.load.loadReturn.writebackFire - scalarLoadGprSink.io.loadWakeupFire := scalarLsu.io.load.loadReturn.wakeupFire - scalarLoadGprSink.io.readTag := io.scalarGprReadTag - - commitRob.io.lookupValid := scalarLoadCompletion.io.robLookupValid - commitRob.io.lookupRid := scalarLoadCompletion.io.robLookupRid - scalarLsu.io.load.loadReturn.robRowValid := scalarLoadCompletion.io.loadRobRowValid - scalarLsu.io.load.loadReturn.robRowNeedFlush := scalarLoadCompletion.io.loadRobRowNeedFlush - scalarLsu.io.load.loadReturn.resolveReady := scalarLoadCompletion.io.loadResolveReady - scalarLsu.io.load.loadReturn.writebackReady := - io.scalarLsu.load.loadReturn.writebackReady && scalarLoadGprSink.io.loadWritebackReady - scalarLsu.io.load.loadReturn.wakeupReady := - io.scalarLsu.load.loadReturn.wakeupReady && scalarLoadGprSink.io.loadWakeupReady - commitRob.io.completeValid := scalarLoadCompletion.io.robCompleteValid - commitRob.io.completeRobValue := scalarLoadCompletion.io.robCompleteRobValue - commitRob.io.exactCompleteValid := scalarLoadCompletion.io.robExactCompleteValid - commitRob.io.exactCompleteRid := scalarLoadCompletion.io.robExactCompleteRid - io.scalarLoadCompleteSelected := scalarLoadCompletion.io.scalarLoadSelected - io.completeCollision := scalarLoadCompletion.io.collision - io.externalGprWriteReady := scalarLoadGprSink.io.externalWriteReady - io.externalGprWriteFire := scalarLoadGprSink.io.externalWriteFire - io.scalarGprReadData := scalarLoadGprSink.io.readData - io.scalarGprReadReady := scalarLoadGprSink.io.readReady - io.scalarGprReadyMask := scalarLoadGprSink.io.readyMask - io.scalarLoadWritebackSelected := scalarLoadGprSink.io.loadWritebackSelected - io.scalarLoadWakeupPublished := scalarLoadGprSink.io.loadWakeupPublished - io.scalarLoadBlockedByExternalWrite := scalarLoadGprSink.io.loadBlockedByExternalWrite - io.scalarLoadBlockedByUnsupportedDestination := - scalarLoadGprSink.io.loadBlockedByUnsupportedDestination - io.scalarBackendContractError := - scalarLoadCompletion.io.protocolError || scalarLoadGprSink.io.protocolError - - io.commit := commitRob.io.commit - io.commitValidMask := commitRob.io.commitValidMask - io.commitCount := commitRob.io.commitCount - io.commitMonitorValidMask := commitRob.io.commitMonitorValidMask - io.commitMonitorValidCount := commitRob.io.commitMonitorValidCount - io.commitSkippedSlot := commitRob.io.commitSkippedSlot - io.commitDuplicateIdentity := commitRob.io.commitDuplicateIdentity - io.commitSlotMismatch := commitRob.io.commitSlotMismatch - io.commitInvalidSideEffect := commitRob.io.commitInvalidSideEffect - io.commitContractError := commitRob.io.commitContractError || io.scalarBackendContractError - - io.empty := commitRob.io.empty - io.full := commitRob.io.full - io.size := commitRob.io.size - io.headValid := commitRob.io.headValid - io.headComplete := commitRob.io.headComplete - io.headRobValue := commitRob.io.headRobValue - - io.idle := - commitRob.io.empty && - scalarLsu.io.store.stqEmpty && - scalarLsu.io.store.drainEmpty && - (scalarLsu.io.store.scbEntryCount === 0.U) && - scalarLsu.io.store.scbRespBufferEmpty && - scalarLsu.io.load.empty && - !scalarLsu.io.recovery.sourcePending -} - -object LinxCoreTop { - def traceParamsFor(coreParams: CoreParams): CommitTraceParams = - CommitTraceParams( - commitWidth = coreParams.commitWidth, - robValueWidth = log2Ceil(coreParams.robEntries) - ) -} - -object Elaborate extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreTop, - args = Array("--target-dir", "../generated/chisel-verilog"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} - -object EmitLinxCoreTopXcheck extends App { - circt.stage.ChiselStage.emitSystemVerilogFile( - new LinxCoreTop(CoreParams( - robEntries = 8, - commitWidth = 2, - scalarLsu = ScalarLsuParams(liqEntries = 8) - )), - args = Array("--target-dir", "../generated/chisel-verilog/top-xcheck"), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBBridge.scala b/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBBridge.scala deleted file mode 100644 index 0b103db5..00000000 --- a/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBBridge.scala +++ /dev/null @@ -1,74 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.rob.ROBID - -class ScalarLoadCompletionROBBridgeIO(val entries: Int) extends Bundle { - private val ptrWidth = log2Ceil(entries) - - val externalCompleteValid = Input(Bool()) - val externalCompleteRobValue = Input(UInt(ptrWidth.W)) - - val loadLookupValid = Input(Bool()) - val loadLookupRid = Input(new ROBID(entries)) - val robLookupRowValid = Input(Bool()) - val robLookupRowNeedFlush = Input(Bool()) - val robLookupValid = Output(Bool()) - val robLookupRid = Output(new ROBID(entries)) - val loadRobRowValid = Output(Bool()) - val loadRobRowNeedFlush = Output(Bool()) - - val loadCompletionCandidateValid = Input(Bool()) - val loadCompletionRid = Input(new ROBID(entries)) - val loadResolveEnable = Input(Bool()) - val robExactCompleteReady = Input(Bool()) - val loadResolveReady = Output(Bool()) - val loadResolveFire = Input(Bool()) - - val robCompleteValid = Output(Bool()) - val robCompleteRobValue = Output(UInt(ptrWidth.W)) - val robExactCompleteValid = Output(Bool()) - val robExactCompleteRid = Output(new ROBID(entries)) - val scalarLoadSelected = Output(Bool()) - val collision = Output(Bool()) - val sameRowCollision = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ScalarLoadCompletionROBBridge(val entries: Int = 16) extends Module { - require(entries > 1 && (entries & (entries - 1)) == 0, - "entries must be a power of two greater than one") - - val io = IO(new ScalarLoadCompletionROBBridgeIO(entries)) - - val loadResolveReady = - io.loadResolveEnable && !io.externalCompleteValid && io.robExactCompleteReady - val scalarLoadSelected = io.loadResolveFire && loadResolveReady - val sameRowCollision = - io.externalCompleteValid && io.loadCompletionCandidateValid && - io.loadCompletionRid.valid && - (io.externalCompleteRobValue === io.loadCompletionRid.value) - val protocolError = - (io.loadResolveFire && !loadResolveReady) || - (io.loadResolveFire && !io.loadCompletionRid.valid) || - sameRowCollision - - io.robLookupValid := io.loadLookupValid - io.robLookupRid := io.loadLookupRid - io.loadRobRowValid := io.robLookupRowValid - io.loadRobRowNeedFlush := io.robLookupRowNeedFlush - io.loadResolveReady := loadResolveReady - io.robCompleteValid := io.externalCompleteValid - io.robCompleteRobValue := io.externalCompleteRobValue - io.robExactCompleteValid := scalarLoadSelected - io.robExactCompleteRid := io.loadCompletionRid - io.scalarLoadSelected := scalarLoadSelected - io.collision := io.externalCompleteValid && io.loadCompletionCandidateValid - io.sameRowCollision := sameRowCollision - io.protocolError := protocolError - - assert(!protocolError, - "scalar load completion must have unique source ownership, accepted sinks, and a valid RID") -} diff --git a/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBProbe.scala b/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBProbe.scala deleted file mode 100644 index b136eff6..00000000 --- a/chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBProbe.scala +++ /dev/null @@ -1,206 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.Cat -import circt.stage.ChiselStage - -import linxcore.commit.{CommitTraceParams, CommitTraceRow} -import linxcore.common.{DestinationKind, ScalarBackendParams, ScalarLsuParams} -import linxcore.lsu.LoadReplayDestination -import linxcore.rob.{ReducedCommitROB, ROBID} - -class ScalarLoadCompletionROBProbeIO extends Bundle { - val allocValid = Input(Bool()) - val allocTag = Input(UInt(3.W)) - val allocReady = Output(Bool()) - val allocRobValue = Output(UInt(3.W)) - val allocRobWrap = Output(Bool()) - - val externalCompleteValid = Input(Bool()) - val externalCompleteRobValue = Input(UInt(3.W)) - val loadValid = Input(Bool()) - val loadRidValid = Input(Bool()) - val loadRidWrap = Input(Bool()) - val loadRidValue = Input(UInt(3.W)) - val loadResolveEnable = Input(Bool()) - val loadWritebackEnable = Input(Bool()) - val loadWakeupEnable = Input(Bool()) - val loadDstValid = Input(Bool()) - val loadDstKind = Input(UInt(2.W)) - val loadDstTag = Input(UInt(7.W)) - val loadData = Input(UInt(64.W)) - val loadSpecWakeup = Input(Bool()) - val loadStackValid = Input(Bool()) - - val gprClearValid = Input(Bool()) - val gprClearTag = Input(UInt(7.W)) - val externalGprWriteValid = Input(Bool()) - val externalGprWriteTag = Input(UInt(7.W)) - val externalGprWriteData = Input(UInt(64.W)) - val gprReadTag = Input(UInt(7.W)) - val singlePortMode = Input(Bool()) - - val lookupRowValid = Output(Bool()) - val lookupBlockedByFree = Output(Bool()) - val lookupBlockedByStaleRid = Output(Bool()) - val loadResolveReady = Output(Bool()) - val scalarLoadSelected = Output(Bool()) - val collision = Output(Bool()) - val loadWritebackSelected = Output(Bool()) - val loadWakeupPublished = Output(Bool()) - val loadBlockedByExternalWrite = Output(Bool()) - val externalGprWriteFire = Output(Bool()) - val gprReadData = Output(UInt(64.W)) - val gprReadReady = Output(Bool()) - val protocolError = Output(Bool()) - val commitValid = Output(Bool()) - val commitRobValue = Output(UInt(3.W)) - val size = Output(UInt(4.W)) -} - -class ScalarLoadCompletionROBProbe extends Module { - private val entries = 8 - private val traceParams = CommitTraceParams(commitWidth = 1, robValueWidth = 3) - private val lsuParams = ScalarLsuParams(liqEntries = 8) - private val backendParams = ScalarBackendParams() - val io = IO(new ScalarLoadCompletionROBProbeIO) - - val rob = Module(new ReducedCommitROB(entries, traceParams)) - val bridge = Module(new ScalarLoadCompletionROBBridge(entries)) - val gprSink = Module(new ScalarLoadGPRCompletionSink(backendParams, lsuParams)) - val singleGprSink = Module(new ScalarLoadGPRCompletionSink( - backendParams.copy(gprWritePorts = 1), - lsuParams - )) - - val allocRow = Wire(new CommitTraceRow(traceParams)) - allocRow := 0.U.asTypeOf(allocRow) - allocRow.valid := io.allocValid - allocRow.identity.bid := io.allocTag - allocRow.identity.gid := 0.U - allocRow.identity.rid := io.allocTag - allocRow.blockBidValid := io.allocValid - allocRow.blockBid := io.allocTag - allocRow.pc := Cat(0.U(58.W), io.allocTag, 0.U(3.W)) - allocRow.insn := 0x13.U - allocRow.len := 4.U - allocRow.nextPc := allocRow.pc + 4.U - rob.io.allocValid := io.allocValid - rob.io.allocRow := allocRow - - val loadRid = Wire(new ROBID(entries)) - loadRid.valid := io.loadRidValid - loadRid.wrap := io.loadRidWrap - loadRid.value := io.loadRidValue - bridge.io.externalCompleteValid := io.externalCompleteValid - bridge.io.externalCompleteRobValue := io.externalCompleteRobValue - bridge.io.loadLookupValid := io.loadValid - bridge.io.loadLookupRid := loadRid - bridge.io.robLookupRowValid := rob.io.lookupRowValid - bridge.io.robLookupRowNeedFlush := rob.io.lookupRowNeedFlush - bridge.io.loadCompletionCandidateValid := io.loadValid - bridge.io.loadCompletionRid := loadRid - bridge.io.loadResolveEnable := io.loadResolveEnable - bridge.io.robExactCompleteReady := rob.io.exactCompleteReady - - val loadDst = Wire(new LoadReplayDestination(lsuParams.archRegWidth, lsuParams.physRegWidth)) - loadDst := LoadReplayDestination.none(lsuParams.archRegWidth, lsuParams.physRegWidth) - loadDst.valid := io.loadDstValid - loadDst.kind := io.loadDstKind.asTypeOf(DestinationKind()) - loadDst.physTag := io.loadDstTag - for (sink <- Seq(gprSink, singleGprSink)) { - sink.io.initValid := false.B - sink.io.initTag := 0.U - sink.io.initData := 0.U - sink.io.clearValid := io.gprClearValid - sink.io.clearTag := io.gprClearTag - sink.io.externalWriteValid := io.externalGprWriteValid - sink.io.externalWriteTag := io.externalGprWriteTag - sink.io.externalWriteData := io.externalGprWriteData - sink.io.loadCandidateValid := io.loadValid - sink.io.loadDst := loadDst - sink.io.loadData := io.loadData - sink.io.loadSpecWakeup := io.loadSpecWakeup - sink.io.loadStackValid := io.loadStackValid - sink.io.readTag := io.gprReadTag - } - - val loadWriteRequired = io.loadValid && io.loadDstValid && - (loadDst.kind === DestinationKind.Gpr) - val loadWakeupRequired = io.loadValid && io.loadDstValid && - (loadDst.kind =/= DestinationKind.None) && !io.loadSpecWakeup && !io.loadStackValid - val selectedWritebackReady = Mux( - io.singlePortMode, - singleGprSink.io.loadWritebackReady, - gprSink.io.loadWritebackReady - ) && io.loadWritebackEnable - val selectedWakeupReady = Mux( - io.singlePortMode, - singleGprSink.io.loadWakeupReady, - gprSink.io.loadWakeupReady - ) && io.loadWakeupEnable - val loadResolveFire = io.loadValid && rob.io.lookupRowValid && - bridge.io.loadResolveReady && selectedWritebackReady && selectedWakeupReady - val loadWritebackFire = loadResolveFire && loadWriteRequired - val loadWakeupFire = loadResolveFire && loadWakeupRequired - bridge.io.loadResolveFire := loadResolveFire - gprSink.io.loadResolveFire := loadResolveFire && !io.singlePortMode - gprSink.io.loadWritebackFire := loadWritebackFire && !io.singlePortMode - gprSink.io.loadWakeupFire := loadWakeupFire && !io.singlePortMode - singleGprSink.io.loadResolveFire := loadResolveFire && io.singlePortMode - singleGprSink.io.loadWritebackFire := loadWritebackFire && io.singlePortMode - singleGprSink.io.loadWakeupFire := loadWakeupFire && io.singlePortMode - - rob.io.lookupValid := bridge.io.robLookupValid - rob.io.lookupRid := bridge.io.robLookupRid - rob.io.completeValid := bridge.io.robCompleteValid - rob.io.completeRobValue := bridge.io.robCompleteRobValue - rob.io.exactCompleteValid := bridge.io.robExactCompleteValid - rob.io.exactCompleteRid := bridge.io.robExactCompleteRid - - io.allocReady := rob.io.allocReady - io.allocRobValue := rob.io.allocRid.value - io.allocRobWrap := rob.io.allocRid.wrap - io.lookupRowValid := rob.io.lookupRowValid - io.lookupBlockedByFree := rob.io.lookupBlockedByFree - io.lookupBlockedByStaleRid := rob.io.lookupBlockedByStaleRid - io.loadResolveReady := bridge.io.loadResolveReady && - selectedWritebackReady && selectedWakeupReady - io.scalarLoadSelected := bridge.io.scalarLoadSelected - io.collision := bridge.io.collision - io.loadWritebackSelected := Mux( - io.singlePortMode, - singleGprSink.io.loadWritebackSelected, - gprSink.io.loadWritebackSelected - ) - io.loadWakeupPublished := Mux( - io.singlePortMode, - singleGprSink.io.loadWakeupPublished, - gprSink.io.loadWakeupPublished - ) - io.loadBlockedByExternalWrite := Mux( - io.singlePortMode, - singleGprSink.io.loadBlockedByExternalWrite, - gprSink.io.loadBlockedByExternalWrite - ) - io.externalGprWriteFire := Mux( - io.singlePortMode, - singleGprSink.io.externalWriteFire, - gprSink.io.externalWriteFire - ) - io.gprReadData := Mux(io.singlePortMode, singleGprSink.io.readData, gprSink.io.readData) - io.gprReadReady := Mux(io.singlePortMode, singleGprSink.io.readReady, gprSink.io.readReady) - io.protocolError := bridge.io.protocolError || gprSink.io.protocolError || - singleGprSink.io.protocolError || rob.io.commitContractError - io.commitValid := rob.io.commit.rows(0).valid - io.commitRobValue := rob.io.commit.rows(0).rob.value - io.size := rob.io.size -} - -object EmitScalarLoadCompletionROBProbe extends App { - ChiselStage.emitSystemVerilogFile( - new ScalarLoadCompletionROBProbe, - args, - firtoolOpts = Array("--disable-all-randomization", "--strip-debug-info") - ) -} diff --git a/chisel/src/main/scala/linxcore/top/ScalarLoadGPRCompletionSink.scala b/chisel/src/main/scala/linxcore/top/ScalarLoadGPRCompletionSink.scala deleted file mode 100644 index 5254f3a6..00000000 --- a/chisel/src/main/scala/linxcore/top/ScalarLoadGPRCompletionSink.scala +++ /dev/null @@ -1,156 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.util.log2Ceil - -import linxcore.common.{DestinationKind, ScalarBackendParams, ScalarLsuParams} -import linxcore.execute.ScalarGPRFile -import linxcore.lsu.LoadReplayDestination - -class ScalarLoadGPRCompletionSinkIO( - val backend: ScalarBackendParams, - val lsu: ScalarLsuParams) - extends Bundle { - private val tagWidth = log2Ceil(backend.gprPhysRegs) - - val initValid = Input(Bool()) - val initTag = Input(UInt(tagWidth.W)) - val initData = Input(UInt(lsu.dataWidth.W)) - val clearValid = Input(Bool()) - val clearTag = Input(UInt(tagWidth.W)) - - val externalWriteValid = Input(Bool()) - val externalWriteTag = Input(UInt(tagWidth.W)) - val externalWriteData = Input(UInt(lsu.dataWidth.W)) - val externalWriteReady = Output(Bool()) - val externalWriteFire = Output(Bool()) - - val loadCandidateValid = Input(Bool()) - val loadDst = Input(new LoadReplayDestination(lsu.archRegWidth, lsu.physRegWidth)) - val loadData = Input(UInt(lsu.dataWidth.W)) - val loadSpecWakeup = Input(Bool()) - val loadStackValid = Input(Bool()) - val loadResolveFire = Input(Bool()) - val loadWritebackFire = Input(Bool()) - val loadWakeupFire = Input(Bool()) - val loadWritebackReady = Output(Bool()) - val loadWakeupReady = Output(Bool()) - - val readTag = Input(UInt(tagWidth.W)) - val readData = Output(UInt(lsu.dataWidth.W)) - val readReady = Output(Bool()) - val readyMask = Output(UInt(backend.gprPhysRegs.W)) - - val loadWriteRequired = Output(Bool()) - val loadWakeupRequired = Output(Bool()) - val loadWritebackSelected = Output(Bool()) - val loadWakeupPublished = Output(Bool()) - val loadBlockedByExternalWrite = Output(Bool()) - val loadBlockedByUnsupportedDestination = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ScalarLoadGPRCompletionSink( - val backend: ScalarBackendParams = ScalarBackendParams(), - val lsu: ScalarLsuParams = ScalarLsuParams()) - extends Module { - require(log2Ceil(backend.gprPhysRegs) == lsu.physRegWidth, - "scalar LSU physical tags must address the canonical GPR file") - - private val writePorts = backend.gprWritePorts - val io = IO(new ScalarLoadGPRCompletionSinkIO(backend, lsu)) - val gpr = Module(new ScalarGPRFile( - archRegs = backend.gprArchRegs, - physRegs = backend.gprPhysRegs, - dataWidth = lsu.dataWidth, - readPorts = 1, - writePorts = writePorts - )) - - val hasDestination = io.loadDst.valid && (io.loadDst.kind =/= DestinationKind.None) - val gprDestination = hasDestination && (io.loadDst.kind === DestinationKind.Gpr) - val localDestination = hasDestination && - ((io.loadDst.kind === DestinationKind.T) || (io.loadDst.kind === DestinationKind.U)) - val loadWriteRequest = io.loadCandidateValid && gprDestination - val loadWakeupRequest = io.loadCandidateValid && !io.loadSpecWakeup && - !io.loadStackValid && hasDestination - val externalSameTag = io.externalWriteValid && loadWriteRequest && - (io.externalWriteTag === io.loadDst.physTag) - val canUseSecondPort = writePorts > 1 - val loadPort = if (canUseSecondPort) 1 else 0 - val loadHasPort = !io.externalWriteValid || (canUseSecondPort.B && !externalSameTag) - - for (port <- 0 until writePorts) { - gpr.io.write(port).requestValid := false.B - gpr.io.write(port).commit := false.B - gpr.io.write(port).tag := 0.U - gpr.io.write(port).data := 0.U - } - gpr.io.write(0).requestValid := io.externalWriteValid - gpr.io.write(0).commit := io.externalWriteValid - gpr.io.write(0).tag := io.externalWriteTag - gpr.io.write(0).data := io.externalWriteData - - if (canUseSecondPort) { - gpr.io.write(loadPort).requestValid := loadWriteRequest && io.externalWriteValid && !externalSameTag - gpr.io.write(loadPort).commit := io.loadWritebackFire && io.externalWriteValid && !externalSameTag - gpr.io.write(loadPort).tag := io.loadDst.physTag - gpr.io.write(loadPort).data := io.loadData - } - when(loadWriteRequest && !io.externalWriteValid) { - gpr.io.write(0).requestValid := true.B - gpr.io.write(0).commit := io.loadWritebackFire - gpr.io.write(0).tag := io.loadDst.physTag - gpr.io.write(0).data := io.loadData - } - - val selectedPortReady = Mux( - io.externalWriteValid, - if (canUseSecondPort) gpr.io.write(loadPort).ready else false.B, - gpr.io.write(0).ready - ) - val loadGprReady = loadHasPort && selectedPortReady - val unsupportedWakeup = loadWakeupRequest && localDestination - val writebackReady = !loadWriteRequest || loadGprReady - val wakeupReady = !loadWakeupRequest || (gprDestination && loadGprReady) - - gpr.io.initValid := io.initValid - gpr.io.initTag := io.initTag - gpr.io.initData := io.initData - gpr.io.clearValid := io.clearValid - gpr.io.clearTag := io.clearTag - gpr.io.clearSecondValid := false.B - gpr.io.clearSecondTag := 0.U - gpr.io.readValid(0) := true.B - gpr.io.readTag(0) := io.readTag - - val expectedWritebackFire = io.loadResolveFire && loadWriteRequest - val expectedWakeupFire = io.loadResolveFire && loadWakeupRequest - val loadWritebackSelected = io.loadWritebackFire && loadGprReady - val loadWakeupPublished = io.loadWakeupFire && gprDestination && loadGprReady - val protocolError = - (io.loadWritebackFire =/= expectedWritebackFire) || - (io.loadWakeupFire =/= expectedWakeupFire) || - (io.loadResolveFire && !(writebackReady && wakeupReady)) || - (io.loadWritebackFire && !loadWritebackSelected) || - (io.loadWakeupFire && !loadWakeupPublished) || - gpr.io.protocolError - - io.externalWriteReady := gpr.io.write(0).ready - io.externalWriteFire := gpr.io.write(0).fire && io.externalWriteValid - io.loadWritebackReady := writebackReady - io.loadWakeupReady := wakeupReady - io.readData := gpr.io.readData(0) - io.readReady := gpr.io.readReady(0) - io.readyMask := gpr.io.readyMask - io.loadWriteRequired := loadWriteRequest - io.loadWakeupRequired := loadWakeupRequest - io.loadWritebackSelected := loadWritebackSelected - io.loadWakeupPublished := loadWakeupPublished - io.loadBlockedByExternalWrite := loadWriteRequest && !loadHasPort - io.loadBlockedByUnsupportedDestination := unsupportedWakeup - io.protocolError := protocolError || unsupportedWakeup - - assert(!protocolError, - "scalar load GPR writeback and wakeup must commit with exact W2 resolve") -} diff --git a/chisel/src/main/scala/linxcore/top/TOP.scala b/chisel/src/main/scala/linxcore/top/TOP.scala new file mode 100644 index 00000000..804512de --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/TOP.scala @@ -0,0 +1,89 @@ +package linxcore.top + +import chisel3._ +import linxcore.ctu.CTU +import linxcore.dtu.DTU +import linxcore.iex.IEX +import linxcore.ifu.IFU +import linxcore.lsu.LSU +import linxcore.ooo.OOO +import linxcore.params.CoreParams +import linxcore.top.interface.{TOPIO, TracePacket} + +/** The one public core composition boundary. + * + * TOP is deliberately state-free. Every retained transaction and every + * architectural decision remains in its public box owner; this module only + * connects typed channels and projects external endpoints. + */ +class TOP(val p: CoreParams) extends Module { + val io = IO(new TOPIO(p)) + + val ifu = Module(new IFU(p)) + val ctu = Module(new CTU(p)) + val ooo = Module(new OOO(p)) + val iex = Module(new IEX(p)) + val lsu = Module(new LSU(p)) + val dtu = Module(new DTU(p)) + + ctu.io.fromIfu <> ifu.io.toCtu + ooo.io.fromCtu <> ctu.io.toOoo + iex.io.ooo <> ooo.io.iex + lsu.io.iex <> iex.io.lsu + ifu.io.branchResolve <> iex.io.branchResolve + + ooo.io.recoveryToIfu <> ifu.io.recovery + ooo.io.recoveryToCtu <> ctu.io.recovery + ooo.io.recoveryToLsu <> lsu.io.recovery + + io.instructionMemoryRequest <> ifu.io.memoryRequest + ifu.io.memoryResponse <> io.instructionMemoryResponse + for (lane <- io.dataMemoryRequest.indices) { + io.dataMemoryRequest(lane) <> lsu.io.memoryRequest(lane) + lsu.io.memoryResponse(lane) <> io.dataMemoryResponse(lane) + } + + iex.io.pInit <> io.pInit + iex.io.bootstrapComplete := io.bootstrapComplete + io.bootstrapReady := iex.io.bootstrapReady + + ooo.io.interrupt <> io.interrupt + dtu.io.debugRequest <> io.debugRequest + io.debugResponse <> dtu.io.debugResponse + ooo.io.debugRequest <> dtu.io.controlRequest + dtu.io.controlResponse <> ooo.io.debugResponse + + for (lane <- io.systemIssue.indices) { + io.systemIssue(lane) <> ooo.io.systemIssue(lane) + } + io.cmdIssue <> iex.io.cmdIssue + + lsu.io.storeCommit <> ooo.io.storeCommit + ooo.io.storeResolve <> lsu.io.storeResolve + lsu.io.loadReissueRequest <> io.loadReissueRequest + io.memoryFault <> lsu.io.memoryFault + lsu.io.maintenance <> io.maintenance + io.maintenanceResult <> lsu.io.maintenanceResult + io.lsuQuiescent := lsu.io.quiescent + io.lsuProtocolError := lsu.io.protocolError + + io.commit <> ooo.io.commit + dtu.io.commitIn.valid := ooo.io.commit.fire + dtu.io.commitIn.bits := ooo.io.commit.bits + io.trap <> ooo.io.trap + + val traceSources = Seq( + ifu.io.trace, + ctu.io.trace, + ooo.io.trace, + iex.io.trace, + lsu.io.trace) + val tracePacker = Module(new TracePrefixPacker(p, traceSources.length)) + tracePacker.io.in.zip(traceSources).foreach { case (sink, source) => + sink <> source + } + dtu.io.traceIn <> tracePacker.io.out + dtu.io.traceOverflowDropped := tracePacker.io.dropped + io.trace <> dtu.io.traceOut + io.performanceCounters := dtu.io.performanceCounters +} diff --git a/chisel/src/main/scala/linxcore/top/TracePrefixPacker.scala b/chisel/src/main/scala/linxcore/top/TracePrefixPacker.scala new file mode 100644 index 00000000..37faf92e --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/TracePrefixPacker.scala @@ -0,0 +1,41 @@ +package linxcore.top + +import chisel3._ +import chisel3.util.{Decoupled, Mux1H, PopCount} +import linxcore.params.CoreParams +import linxcore.top.interface.TracePacket + +class TracePrefixPackerIO(val p: CoreParams, val sourceCount: Int) + extends Bundle { + val in = Flipped(Vec(sourceCount, Decoupled(new TracePacket(p)))) + val out = Decoupled(new TracePacket(p)) + val dropped = Output(UInt(64.W)) +} + +/** Nonbackpressured observation packer with deterministic source-prefix order. */ +class TracePrefixPacker(val p: CoreParams, val sourceCount: Int) extends Module { + require(sourceCount > 0) + val io = IO(new TracePrefixPackerIO(p, sourceCount)) + io.in.foreach(_.ready := true.B) + private val events = for { + source <- io.in + lane <- 0 until p.dtu.traceWidth + } yield (source.valid && lane.U < source.bits.count, source.bits.entries(lane)) + private val valid = VecInit(events.map(_._1)) + private val ordinal = events.indices.map { index => + if (index == 0) 0.U else PopCount(valid.take(index)) + } + private val count = PopCount(valid) + io.out.valid := count.orR + io.out.bits := 0.U.asTypeOf(io.out.bits) + io.out.bits.count := Mux(count > p.dtu.traceWidth.U, + p.dtu.traceWidth.U, count) + for (lane <- 0 until p.dtu.traceWidth) { + val matches = events.indices.map { index => + valid(index) && ordinal(index) === lane.U + } + io.out.bits.entries(lane) := Mux1H(matches, events.map(_._2)) + } + io.dropped := Mux(count > p.dtu.traceWidth.U, + count - p.dtu.traceWidth.U, 0.U) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/BranchFeedback.scala b/chisel/src/main/scala/linxcore/top/interface/BranchFeedback.scala new file mode 100644 index 00000000..2f312300 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/BranchFeedback.scala @@ -0,0 +1,60 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.common.BoundaryKind +import linxcore.params.CoreParams + +object BranchValidationKind extends ChiselEnum { + val Condition, Target = Value +} + +/** Exact backend result used to train B-SIDE and, on mismatch, start precise + * recovery. Prediction identity and resident ROB identity remain separate. + */ +class BranchValidationTxn(val p: CoreParams) extends Bundle { + val executionTransactionId = UInt(p.transactionIdWidth.W) + val rob = new RobIdentity(p) + val instruction = new InstructionIdentity(p) + val kind = BranchValidationKind() + + val predictionValid = Bool() + val predictionTag = UInt(p.transactionIdWidth.W) + val predictionTransactionId = UInt(p.transactionIdWidth.W) + val fetchPacketUid = UInt(p.instructionIdWidth.W) + val fetchSeq = UInt(p.instructionIdWidth.W) + val predictionEpoch = UInt(p.epochWidth.W) + val checkpointId = UInt(InterfaceWidth.index( + p.ifu.predictionCheckpointEntries).W) + val requestPc = UInt(p.pcWidth.W) + val predictedTaken = Bool() + val predictedBranchPc = UInt(p.pcWidth.W) + val predictedTarget = UInt(p.pcWidth.W) + val predictedFallthroughPc = UInt(p.pcWidth.W) + val predictedKind = BoundaryKind() + + val actualTaken = Bool() + val actualBranchPc = UInt(p.pcWidth.W) + val actualTarget = UInt(p.pcWidth.W) + val actualFallthroughPc = UInt(p.pcWidth.W) + val actualKind = BoundaryKind() +} + +/** B-SIDE training transaction after backend comparison. */ +class BranchResolveTxn(val p: CoreParams) extends Bundle { + val peId = UInt(p.peIdWidth.W) + val transactionId = UInt(p.transactionIdWidth.W) + val predictionTag = UInt(p.transactionIdWidth.W) + val stid = UInt(p.ooo.stidWidth.W) + val fetchPacketUid = UInt(p.instructionIdWidth.W) + val fetchSeq = UInt(p.instructionIdWidth.W) + val epoch = UInt(p.epochWidth.W) + val checkpointId = UInt(InterfaceWidth.index( + p.ifu.predictionCheckpointEntries).W) + val requestPc = UInt(p.pcWidth.W) + val branchPc = UInt(p.pcWidth.W) + val fallthroughPc = UInt(p.pcWidth.W) + val taken = Bool() + val target = UInt(p.pcWidth.W) + val kind = BoundaryKind() + val mispredict = Bool() +} diff --git a/chisel/src/main/scala/linxcore/top/interface/CTUIO.scala b/chisel/src/main/scala/linxcore/top/interface/CTUIO.scala new file mode 100644 index 00000000..c4e6a715 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/CTUIO.scala @@ -0,0 +1,12 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class CTUIO(val p: CoreParams) extends Bundle { + val fromIfu = Flipped(Decoupled(new FetchedPacket(p))) + val toOoo = Decoupled(new D1Packet(p)) + val recovery = Flipped(new RecoveryTargetIO(p)) + val trace = Decoupled(new TracePacket(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/CTUOOO.scala b/chisel/src/main/scala/linxcore/top/interface/CTUOOO.scala new file mode 100644 index 00000000..6cc55f8b --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/CTUOOO.scala @@ -0,0 +1,143 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +object FrontEndOpKind extends ChiselEnum { + val Encoded64, TemplateUop = Value +} + +object OperandKind extends ChiselEnum { + val None, Gpr, T, U, Immediate = Value +} + +object UopClass extends ChiselEnum { + val Alu, Bru, Agu, Std, System, Cmd, Boundary = Value +} + +/** Encoding-independent scalar memory address form emitted by D1. */ +object MemoryAddressMode extends ChiselEnum { + val None, BaseIndex, BaseOffset, PcOffset = Value +} + +/** D1-normalized transformation applied to a register index before addition. */ +object MemoryIndexMode extends ChiselEnum { + val Identity, SignExtend32, ZeroExtend32, Negate = Value +} + +/** Canonical decoded scalar memory controls. */ +class DecodedMemoryControl(val p: CoreParams) extends Bundle { + val valid = Bool() + val isLoad = Bool() + val isStore = Bool() + val addressMode = MemoryAddressMode() + val accessBytes = UInt(4.W) + val signExtend = Bool() + val offset = UInt(p.pcWidth.W) + val indexMode = MemoryIndexMode() + val indexShift = UInt(5.W) + val addressSourceMask = UInt(p.maxSourceOperands.W) + val dataSourceMask = UInt(p.maxSourceOperands.W) + val writebackValid = Bool() + val writebackPreIndex = Bool() + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) +} + +class FrontEndOp(val p: CoreParams) extends Bundle { + val kind = FrontEndOpKind() + val parent = new FetchedInstruction(p) + val templateOrdinal = UInt(8.W) + val templateCount = UInt(8.W) + val templateOpcode = UInt(p.opcodeWidth.W) + val templateRegister = UInt(p.archRegWidth.W) + val templateImmediate = UInt(p.dataWidth.W) +} + +class D1Packet(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.ctuOutputWidth).W) + val entries = Vec(p.widths.ctuOutputWidth, new FrontEndOp(p)) +} + +class DecodedSource(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = OperandKind() + val atag = UInt(p.archRegWidth.W) + val relativeIndex = UInt(p.archRegWidth.W) +} + +class DecodedDestination(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = OperandKind() + val atag = UInt(p.archRegWidth.W) + val relativeIndex = UInt(p.archRegWidth.W) +} + +/** Encoding-independent uop classification produced once by D1/D2. + * + * IEX consumes this payload directly when it binds an Issue Queue row. The + * classification therefore preserves Execution-pipe capability, splitting, + * speculation and side-effect information; later stages do not reconstruct + * those decisions from opcode or queue placement. + */ +class UopClassification(val p: CoreParams) extends Bundle { + private val uopCountWidth = p.ooo.recipeUopCountWidth + private val dispatchCountWidth = + PrefixPacketContract.countWidth(p.widths.dispatchWidth) + private val sourceCountWidth = + PrefixPacketContract.countWidth(p.maxSourceOperands) + private val destinationCountWidth = + PrefixPacketContract.countWidth(p.maxDestinationOperands) + + val valid = Bool() + val disposition = UInt(2.W) + val kind = UInt(4.W) + val uopCountMin = UInt(uopCountWidth.W) + val uopCountMax = UInt(uopCountWidth.W) + val complexBreak = Bool() + val splitKind = UInt(2.W) + val fusionHeadClass = UInt(2.W) + val fusionTailClass = UInt(2.W) + val fastResolveClass = UInt(3.W) + val implicitSourceMask = UInt(p.maxSourceOperands.W) + val implicitDestination = UInt(2.W) + val sideEffectOwner = UInt(3.W) + val requiresTargetValidation = Bool() + val mayTrap = Bool() + val mayTrapLate = Bool() + val mayRedirect = Bool() + val nonspeculative = Bool() + val pcReadRequired = Bool() + val pcReadClass = UInt(4.W) + val dispatchClass = UInt(4.W) + val dispatchWrites = UInt(dispatchCountWidth.W) + val dispatchDemand = + Vec(p.iex.issueQueueClasses, UInt(dispatchCountWidth.W)) + val executionPipeCapability = + Vec(p.iex.issueQueueClasses, UInt(p.iex.executionPipeKinds.W)) + val memoryRequestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val pSourceCount = UInt(sourceCountWidth.W) + val pDestinationCount = UInt(destinationCountWidth.W) + val tAllocationCount = UInt(destinationCountWidth.W) + val uAllocationCount = UInt(destinationCountWidth.W) +} + +class DecodedUop(val p: CoreParams) extends Bundle { + val valid = Bool() + val instruction = new FrontEndOp(p) + val rob = new RobIdentity(p) + val opcode = UInt(p.opcodeWidth.W) + val uopClass = UopClass() + val classification = new UopClassification(p) + val sources = Vec(p.maxSourceOperands, new DecodedSource(p)) + val destinations = + Vec(p.maxDestinationOperands, new DecodedDestination(p)) + val memory = new DecodedMemoryControl(p) + val immediateValid = Bool() + val immediate = UInt(p.dataWidth.W) + val earlyComplete = Bool() + val blockStart = Bool() + val blockStop = Bool() + val blockBoundary = Bool() +} diff --git a/chisel/src/main/scala/linxcore/top/interface/Commit.scala b/chisel/src/main/scala/linxcore/top/interface/Commit.scala new file mode 100644 index 00000000..0871b937 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/Commit.scala @@ -0,0 +1,30 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +class CommitEntry(val p: CoreParams) extends Bundle { + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val pc = UInt(p.pcWidth.W) + val pcBufferIndexOffset = new PcBufferIndexOffset(p) + val robGroupLast = Bool() + val instructionBits = UInt(p.instructionWidth.W) + val instructionLengthBytes = UInt(4.W) + val opcode = UInt(p.opcodeWidth.W) + val destination = new RenamedDestination(p) + val resultValid = Bool() + val result = UInt(p.dataWidth.W) + val memoryValid = Bool() + val memoryStore = Bool() + val memory = new MemoryIdentity(p) + val memoryOrder = new MemoryOrderMeta(p) + val storeData = UInt(p.dataWidth.W) + val storeMask = UInt((p.dataWidth / 8).W) + val trap = new TrapEvent(p) +} + +class CommitTxn(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.retireWidth).W) + val entries = Vec(p.widths.retireWidth, new CommitEntry(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/DTU.scala b/chisel/src/main/scala/linxcore/top/interface/DTU.scala new file mode 100644 index 00000000..031791b5 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/DTU.scala @@ -0,0 +1,49 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +object TraceSource extends ChiselEnum { + val Top, Ifu, Ctu, Ooo, Iex, Lsu = Value +} + +object TraceKind extends ChiselEnum { + val Pipeline, Commit, Recovery, Trap, Memory, Performance = Value +} + +class TraceEvent(val p: CoreParams) extends Bundle { + val source = TraceSource() + val kind = TraceKind() + val cycle = UInt(64.W) + val instructionValid = Bool() + val instruction = new InstructionIdentity(p) + val robValid = Bool() + val rob = new RobIdentity(p) + val pc = UInt(p.pcWidth.W) + val opcode = UInt(p.opcodeWidth.W) + val payload = UInt(p.dataWidth.W) +} + +class TracePacket(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.dtu.traceWidth).W) + val entries = Vec(p.dtu.traceWidth, new TraceEvent(p)) +} + +object DebugCommand extends ChiselEnum { + val Halt, Resume, Step, ReadRegister, WriteRegister = Value +} + +class DebugRequest(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val command = DebugCommand() + val stid = UInt(p.ooo.stidWidth.W) + val address = UInt(p.dataWidth.W) + val data = UInt(p.dataWidth.W) +} + +class DebugResponse(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val accepted = Bool() + val data = UInt(p.dataWidth.W) + val error = Bool() +} diff --git a/chisel/src/main/scala/linxcore/top/interface/DTUIO.scala b/chisel/src/main/scala/linxcore/top/interface/DTUIO.scala new file mode 100644 index 00000000..8050629b --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/DTUIO.scala @@ -0,0 +1,18 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class DTUIO(val p: CoreParams) extends Bundle { + val traceIn = Flipped(Decoupled(new TracePacket(p))) + val traceOverflowDropped = Input(UInt(64.W)) + val commitIn = Flipped(Decoupled(new CommitTxn(p))) + val debugRequest = Flipped(Decoupled(new DebugRequest(p))) + val debugResponse = Decoupled(new DebugResponse(p)) + val controlRequest = Decoupled(new DebugRequest(p)) + val controlResponse = Flipped(Decoupled(new DebugResponse(p))) + val traceOut = Decoupled(new TracePacket(p)) + val performanceCounters = Output(Vec( + p.dtu.performanceCounterCount, UInt(64.W))) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala b/chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala new file mode 100644 index 00000000..8f284e17 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala @@ -0,0 +1,235 @@ +package linxcore.top.interface + +import chisel3._ +import java.nio.charset.StandardCharsets +import java.nio.file.{Files, Path, Paths} +import linxcore.params.{CoreParams, ParamProfiles} + +final case class ManifestPort(name: String, width: Int) + +final case class ManifestEndpoint( + name: String, + contractId: String, + producer: String, + consumer: String, + lanes: Int, + payload: String, + ports: Seq[ManifestPort]) + +final case class ManifestProfile( + name: String, + width: Int, + endpoints: Seq[ManifestEndpoint]) + +final case class InterfaceManifestModel( + schema: Int, + profiles: Seq[ManifestProfile]) + +object InterfaceManifest { + private final case class EndpointDefinition( + name: String, + contractId: String, + producer: String, + consumer: String, + lanes: CoreParams => Int, + payload: CoreParams => Data) + + private val endpointDefinitions = Seq( + EndpointDefinition("top_io", "IFC-TOP-EXT-002", "Platform", "TOP", + _ => 1, p => new TOPIO(p)), + EndpointDefinition("ifu_to_ctu", "IFC-IFU-CTU-001", "IFU", "CTU", + _.widths.fetchWidth, p => new FetchedPacket(p)), + EndpointDefinition("ctu_to_ooo", "IFC-CTU-OOO-001", "CTU", "OOO", + _.widths.ctuOutputWidth, p => new D1Packet(p)), + EndpointDefinition("ooo_to_iex_alu", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.aluPipes, p => new DispatchTxn(p)), + EndpointDefinition("ooo_to_iex_bru", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.bruPipes, p => new DispatchTxn(p)), + EndpointDefinition("ooo_to_iex_agu", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.aguPipes, p => new DispatchTxn(p)), + EndpointDefinition("ooo_to_iex_std", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.stdPipes, p => new StoreDispatchTxn(p)), + EndpointDefinition("ooo_to_iex_system", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.systemMulticycleQueues, p => new DispatchTxn(p)), + EndpointDefinition("ooo_to_iex_cmd", "IFC-OOO-IEX-001", "OOO", "IEX", + _.iex.cmdIssueQueues, p => new DispatchTxn(p)), + EndpointDefinition("ooo_to_iex_rob_noflush", "IFC-OOO-IEX-001", "OOO", "IEX", + _ => 1, p => new RobNoflushTxn(p)), + EndpointDefinition("iex_to_ooo_rob_noflush_ready", "IFC-OOO-IEX-001", "IEX", "OOO", + _ => 1, p => new RobNoflushReadyTxn(p)), + EndpointDefinition("iex_to_ooo_rob_resolve", "IFC-OOO-IEX-001", "IEX", "OOO", + _.widths.issueWidth, p => new RobResolveTxn(p)), + EndpointDefinition("iex_to_ooo_system_issue", "IFC-OOO-IEX-001", "IEX", "OOO", + _.iex.systemMulticycleQueues, p => new SystemIssueTxn(p)), + EndpointDefinition("ooo_to_top_system_issue", "IFC-OOO-IEX-001", "OOO", "TOP", + _.iex.systemMulticycleQueues, p => new SystemIssueTxn(p)), + EndpointDefinition("iex_to_ooo_pc_buffer_read_address", "IFC-OOO-IEX-001", "IEX", "OOO", + _.ooo.pcReadPorts, p => new PcBufferReadAddress(p)), + EndpointDefinition("ooo_to_iex_pc_buffer_read_pc_base", "IFC-OOO-IEX-001", "OOO", "IEX", + _.ooo.pcReadPorts, p => UInt(p.pcWidth.W)), + EndpointDefinition("iex_to_lsu_load_issue", "IFC-IEX-LSU-001", "IEX", "LSU", + _.lsu.loadPipes, p => new LoadIssueTxn(p)), + EndpointDefinition("lsu_to_iex_load_allocation_preview", "IFC-IEX-LSU-001", + "LSU", "IEX", _.lsu.loadPipes, p => new LoadAllocationPreview(p)), + EndpointDefinition("lsu_to_iex_load_launch", "IFC-IEX-LSU-001", "LSU", "IEX", + _.lsu.loadPipes, p => new LoadLaunchTxn(p)), + EndpointDefinition("iex_to_lsu_store_reservation", "IFC-IEX-LSU-001", + "IEX", "LSU", _.lsu.storePipes, p => new StoreReservationTxn(p)), + EndpointDefinition("iex_to_lsu_store_address", "IFC-IEX-LSU-001", "IEX", "LSU", + _.lsu.storePipes, p => new StoreAddressTxn(p)), + EndpointDefinition("iex_to_lsu_store_data", "IFC-IEX-LSU-001", "IEX", "LSU", + _.lsu.storePipes, p => new StoreDataTxn(p)), + EndpointDefinition("lsu_to_iex_load_result", "IFC-IEX-LSU-001", "LSU", "IEX", + _.lsu.loadPipes, p => new LoadResultTxn(p)), + EndpointDefinition("lsu_to_iex_load_reissue", "IFC-IEX-LSU-001", "LSU", "IEX", + _.lsu.loadPipes, p => new LoadReissueTxn(p)), + EndpointDefinition("lsu_to_iex_load_repick", "IFC-IEX-LSU-001", "LSU", "IEX", + _.lsu.loadPipes, p => new LoadRepickTxn(p)), + EndpointDefinition("lsu_to_iex_load_cancel", "IFC-IEX-LSU-001", "LSU", "IEX", + _.lsu.loadPipes, p => new LoadCancelTxn(p)), + EndpointDefinition("ooo_to_lsu_store_commit", "IFC-IEX-LSU-001", "OOO", "LSU", + _ => 1, p => new StoreCommitAuthorizationTxn(p)), + EndpointDefinition("lsu_internal_store_classify", "IFC-IEX-LSU-001", + "LSU Translation", "LSU Commit Backend", _ => 1, + p => new StoreMemoryClassifyTxn(p)), + EndpointDefinition("external_cmd_issue", "IFC-TOP-EXT-001", "IEX", "External CMD", + _ => 1, p => new CmdIssueTxn(p)), + EndpointDefinition("owner_to_ooo_recovery_event", "IFC-RECOVERY-001", "IEX/LSU", + "OOO", _ => 1, p => new RecoveryEvent(p)), + EndpointDefinition("ooo_recovery_prepare", "IFC-RECOVERY-001", "OOO", "IFU/CTU/IEX/LSU", + _ => 1, p => new RecoveryPlan(p)), + EndpointDefinition("target_to_ooo_recovery_prepared", "IFC-RECOVERY-001", + "IFU/CTU/IEX/LSU", "OOO", _ => 1, p => new RecoveryPlan(p)), + EndpointDefinition("ooo_recovery_apply", "IFC-RECOVERY-001", "OOO", "IFU/CTU/IEX/LSU", + _ => 1, p => new RecoveryPlan(p)), + EndpointDefinition("ooo_recovery_abort", "IFC-RECOVERY-001", "OOO", "IFU/CTU/IEX/LSU", + _ => 1, p => new RecoveryPlan(p)), + EndpointDefinition("ooo_commit", "IFC-COMMIT-001", "OOO", "TOP/DTU", + _.widths.retireWidth, p => new CommitTxn(p)), + EndpointDefinition("box_to_dtu_trace", "IFC-DTU-001", "TOP/IFU/CTU/OOO/IEX/LSU", + "DTU", _.dtu.traceWidth, p => new TracePacket(p)), + EndpointDefinition("external_to_dtu_debug_request", "IFC-DTU-001", "External Debug", + "DTU", _ => 1, p => new DebugRequest(p)), + EndpointDefinition("dtu_to_ooo_debug_request", "IFC-DTU-001", "DTU", "OOO", + _ => 1, p => new DebugRequest(p)), + EndpointDefinition("ooo_to_dtu_debug_response", "IFC-DTU-001", "OOO", "DTU", + _ => 1, p => new DebugResponse(p)), + EndpointDefinition("dtu_to_external_debug_response", "IFC-DTU-001", "DTU", + "External Debug", _ => 1, p => new DebugResponse(p)), + EndpointDefinition("dtu_trace_export", "IFC-DTU-001", "DTU", "External Trace", + _.dtu.traceWidth, p => new TracePacket(p)), + EndpointDefinition("dtu_performance_counter", "IFC-DTU-001", "DTU", + "External Counter", _.dtu.performanceCounterCount, _ => UInt(64.W)), + EndpointDefinition("instruction_memory_request", "IFC-MEMORY-001", "IFU", "Memory", + _ => 1, p => new MemoryRequestTxn(p)), + EndpointDefinition("instruction_memory_response", "IFC-MEMORY-001", "Memory", "IFU", + _ => 1, p => new MemoryResponseTxn(p)), + EndpointDefinition("data_memory_request", "IFC-MEMORY-001", "LSU", "Memory", + p => p.lsu.loadPipes + p.lsu.storePipes, p => new MemoryRequestTxn(p)), + EndpointDefinition("data_memory_response", "IFC-MEMORY-001", "Memory", "LSU", + p => p.lsu.loadPipes + p.lsu.storePipes, p => new MemoryResponseTxn(p))) + + private def flatten(data: Data, prefix: String = ""): Seq[ManifestPort] = + data match { + case bundle: Bundle => + bundle.elements.toSeq.sortBy(_._1).flatMap { case (name, element) => + flatten(element, if (prefix.isEmpty) name else s"${prefix}_${name}") + } + case vector: Vec[_] => + vector.zipWithIndex.flatMap { case (element, index) => + flatten(element, if (prefix.isEmpty) index.toString + else s"${prefix}_${index}") + } + case element: Element => + Seq(ManifestPort(prefix, element.getWidth)) + } + + private[interface] def profileFor(name: String, p: CoreParams): ManifestProfile = + { + require( + new RecoveryTargetIO(p).elements.keySet == + Set("prepare", "prepared", "apply", "abort"), + "recovery manifest must be updated when RecoveryTargetIO changes") + ManifestProfile( + name = name, + width = p.widths.decodeWidth, + endpoints = endpointDefinitions.map { definition => + val payload = definition.payload(p) + ManifestEndpoint( + name = definition.name, + contractId = definition.contractId, + producer = definition.producer, + consumer = definition.consumer, + lanes = definition.lanes(p), + payload = payload.getClass.getSimpleName, + ports = flatten(payload)) + }) + } + + lazy val model: InterfaceManifestModel = + InterfaceManifestModel( + schema = 1, + profiles = Seq( + profileFor("W2", ParamProfiles.W2), + profileFor("W4", ParamProfiles.W4), + profileFor("W6", ParamProfiles.W6), + profileFor("W8", ParamProfiles.W8))) + + private def jsonString(value: String): String = { + val escaped = value.flatMap { + case '"' => "\\\"" + case '\\' => "\\\\" + case '\n' => "\\n" + case '\r' => "\\r" + case '\t' => "\\t" + case character => character.toString + } + s"\"$escaped\"" + } + + def renderJson: String = { + val profiles = model.profiles.map { profile => + val endpoints = profile.endpoints.map { endpoint => + val ports = endpoint.ports.map { port => + s"""{"name":${jsonString(port.name)},"width":${port.width}}""" + }.mkString("[", ",", "]") + s"""{"name":${jsonString(endpoint.name)},"contract_id":${jsonString(endpoint.contractId)},"producer":${jsonString(endpoint.producer)},"consumer":${jsonString(endpoint.consumer)},"lanes":${endpoint.lanes},"payload":${jsonString(endpoint.payload)},"ports":$ports}""" + }.mkString("[", ",", "]") + s"""{"name":${jsonString(profile.name)},"width":${profile.width},"endpoints":$endpoints}""" + }.mkString("[", ",", "]") + s"""{"schema":${model.schema},"profiles":$profiles} +""" + } + + def renderMarkdown: String = { + val rows = model.profiles.flatMap { profile => + profile.endpoints.map { endpoint => + val bits = endpoint.ports.map(_.width).sum + s"| ${profile.name} | `${endpoint.name}` | [[${endpoint.contractId}]] | ${endpoint.producer} | ${endpoint.consumer} | ${endpoint.lanes} | `${endpoint.payload}` | ${endpoint.ports.size} | $bits |" + } + } + Seq( + "# Generated TOP interface manifest", + "", + "This file is generated from the canonical Scala Bundle types. Do not edit it by hand.", + "", + "| Profile | Endpoint | Contract | Producer | Consumer | Lanes | Payload | Leaf ports | Payload bits |", + "|---|---|---|---|---|---:|---|---:|---:|") ++ rows mkString "\n" + } + "\n" +} + +object EmitInterfaceManifest extends App { + private def argument(name: String): Path = { + val index = args.indexOf(name) + require(index >= 0 && index + 1 < args.length, s"missing $name path") + Paths.get(args(index + 1)) + } + + private def write(path: Path, contents: String): Unit = { + Option(path.getParent).foreach(parent => Files.createDirectories(parent)) + Files.writeString(path, contents, StandardCharsets.UTF_8) + } + + write(argument("--json"), InterfaceManifest.renderJson) + write(argument("--markdown"), InterfaceManifest.renderMarkdown) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/IEXIO.scala b/chisel/src/main/scala/linxcore/top/interface/IEXIO.scala new file mode 100644 index 00000000..e0a48273 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/IEXIO.scala @@ -0,0 +1,27 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +/** Fire-qualified observation of the existing terminal P-file mutation. + * This is not an additional RF write port or state owner. + */ +class IEXTerminalPWriteObservation(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val ptag = UInt(p.ooo.gprTagWidth.W) + val generation = UInt(p.ooo.gprTagGenerationWidth.W) + val value = UInt(p.dataWidth.W) +} + +class IEXIO(val p: CoreParams) extends Bundle { + val pInit = Flipped(Decoupled(new PFileInitTxn(p))) + val bootstrapComplete = Input(Bool()) + val bootstrapReady = Output(Bool()) + val ooo = Flipped(new OOOIEXIO(p)) + val lsu = new IEXLSUIO(p) + val branchResolve = Decoupled(new BranchResolveTxn(p)) + val cmdIssue = Decoupled(new CmdIssueTxn(p)) + val trace = Decoupled(new TracePacket(p)) + val terminalPWrite = Valid(new IEXTerminalPWriteObservation(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/IEXLSU.scala b/chisel/src/main/scala/linxcore/top/interface/IEXLSU.scala new file mode 100644 index 00000000..834a2937 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/IEXLSU.scala @@ -0,0 +1,196 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class LoadIssueTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val pc = UInt(p.pcWidth.W) + val address = UInt(p.physicalAddressWidth.W) + val sizeBytes = UInt(4.W) + val signed = Bool() + val destination = new RenamedDestination(p) + val destinationRelativeIndex = UInt(p.archRegWidth.W) + val youngestStoreValid = Bool() + val youngestStoreLsid = UInt(p.lsidWidth.W) + val youngestStoreId = UInt(p.lsidWidth.W) +} + +/** Combinational LIQ allocation preview returned beside load-issue ready. + * The allocation becomes owned only when the matching load issue fires. + */ +class LoadAllocationPreview(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val allocationId = new MemoryTransactionIdentity(p) +} + +class LoadLaunchTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val allocationId = new MemoryTransactionIdentity(p) +} + +/** Atomic logical STQ reservation published before either STA or STD executes. + * Physical STQ placement and lease generation remain LSU-private. + */ +class StoreReservationTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val transaction = new MemoryTransactionIdentity(p) + val rob = new RobIdentity(p) + val memoryOrder = new MemoryOrderMeta(p) + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val pair = Bool() + val sizeBytes = UInt(4.W) + val aguPipe = UInt(InterfaceWidth.index(p.iex.aguPipes).W) + val stdPipe = UInt(InterfaceWidth.index(p.iex.stdPipes).W) +} + +/** IEX-authored initial store transaction bound back into the exact resident + * ROB entry. This preserves Option-A transaction generation through commit. + */ +class StoreTransactionBindingTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val transaction = new MemoryTransactionIdentity(p) + val memoryOrder = new MemoryOrderMeta(p) +} + +/** Exact semantic store-beat authorization; no physical STQ index is exposed. */ +class StoreCommitAuthorizationTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val transaction = new MemoryTransactionIdentity(p) + val logicalFirstLsid = UInt(p.lsidWidth.W) + val logicalFirstStoreId = UInt(p.lsidWidth.W) + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val beat = UInt(InterfaceWidth.index( + p.maxMemoryRequestsPerInstruction).W) +} + +object StoreMemoryClass extends ChiselEnum { + val NormalCacheable, NormalNonCacheable, Device, Fault = Value +} + +/** Independently retained translation/protection classification for one + * semantic store beat. LSU resolves it against the current exact lease. + */ +class StoreMemoryClassifyTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val transaction = new MemoryTransactionIdentity(p) + val logicalFirstLsid = UInt(p.lsidWidth.W) + val logicalFirstStoreId = UInt(p.lsidWidth.W) + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val beat = UInt(InterfaceWidth.index( + p.maxMemoryRequestsPerInstruction).W) + val memoryClass = StoreMemoryClass() + val faultCause = UInt(p.trapCauseWidth.W) +} + +/** Exact store dependency retained while LSU requests a structural load + * replay. This remains a semantic wait key: no physical LIQ row is exposed. + */ +class LoadStructuralWaitStoreTxn(val p: CoreParams) extends Bundle { + val valid = Bool() + val storeIndex = UInt(InterfaceWidth.index(p.lsu.storeQueueEntries).W) + val storeIdValid = Bool() + val storeIdValue = UInt(p.ooo.ridSlotWidth.W) + val storeIdWrap = Bool() + val storeLsidValid = Bool() + val storeLsidValue = UInt(p.ooo.ridSlotWidth.W) + val storeLsidWrap = Bool() + val storeLsidFullValid = Bool() + val storeLsidFull = UInt(p.lsidWidth.W) + val pc = UInt(p.pcWidth.W) +} + +/** LIQ attempt transition which returns to address translation. */ +class LoadReissueTxn(val p: CoreParams) extends Bundle { + val allocationId = new MemoryTransactionIdentity(p) + val currentIdentity = new MemoryIdentity(p) + val nextIdentity = new MemoryIdentity(p) + val address = UInt(p.physicalAddressWidth.W) + val structural = Bool() + val waitStore = new LoadStructuralWaitStoreTxn(p) +} + +/** External request to replay the currently owned attempt. The requester may + * identify only the current attempt; LSU alone authors the next generation. + */ +class LoadReplayRequestTxn(val p: CoreParams) extends Bundle { + val allocationId = new MemoryTransactionIdentity(p) + val currentIdentity = new MemoryIdentity(p) + val address = UInt(p.physicalAddressWidth.W) +} + +/** LSU-authored transition for a resident row that requires a new attempt. */ +class LoadRepickTxn(val p: CoreParams) extends Bundle { + val allocationId = new MemoryTransactionIdentity(p) + val currentIdentity = new MemoryIdentity(p) + val nextIdentity = new MemoryIdentity(p) + val structural = Bool() + val waitStore = new LoadStructuralWaitStoreTxn(p) +} + +/** Speculative-dependent cancellation for one exact current attempt. */ +class LoadCancelTxn(val p: CoreParams) extends Bundle { + val currentIdentity = new MemoryIdentity(p) +} + +class StoreAddressTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val memoryOrder = new MemoryOrderMeta(p) + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val pair = Bool() + val address = UInt(p.physicalAddressWidth.W) + val sizeBytes = UInt(4.W) +} + +class StoreDataTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val memoryOrder = new MemoryOrderMeta(p) + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val pair = Bool() + val sizeBytes = UInt(4.W) + val data = Vec(p.maxMemoryRequestsPerInstruction, UInt(p.dataWidth.W)) + val byteMask = Vec(p.maxMemoryRequestsPerInstruction, + UInt((p.dataWidth / 8).W)) +} + +class LoadResultTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val allocationId = new MemoryTransactionIdentity(p) + val data = UInt(p.dataWidth.W) + val destination = new RenamedDestination(p) + val destinationRelativeIndex = UInt(p.archRegWidth.W) + val trap = new TrapEvent(p) +} + +/** IEX-facing view of the IEX/LSU boundary. */ +class IEXLSUIO(val p: CoreParams) extends Bundle { + val storeReservation = Vec(p.lsu.storePipes, + Decoupled(new StoreReservationTxn(p))) + val loadAddress = + Vec(p.lsu.loadPipes, Decoupled(new LoadIssueTxn(p))) + val loadAllocation = Flipped(Vec(p.lsu.loadPipes, + Valid(new LoadAllocationPreview(p)))) + val loadLaunch = Flipped(Vec(p.lsu.loadPipes, + Valid(new LoadLaunchTxn(p)))) + val storeAddress = + Vec(p.lsu.storePipes, Decoupled(new StoreAddressTxn(p))) + val storeData = + Vec(p.lsu.storePipes, Decoupled(new StoreDataTxn(p))) + val loadResult = + Flipped(Vec(p.lsu.loadPipes, Decoupled(new LoadResultTxn(p)))) + val loadReissue = + Flipped(Vec(p.lsu.loadPipes, Decoupled(new LoadReissueTxn(p)))) + val loadRebindApply = + Vec(p.lsu.loadPipes, Decoupled(new LoadReissueTxn(p))) + val loadRepick = + Flipped(Vec(p.lsu.loadPipes, Decoupled(new LoadRepickTxn(p)))) + val loadCancel = + Flipped(Vec(p.lsu.loadPipes, Decoupled(new LoadCancelTxn(p)))) + val recoveryEvent = Flipped(Decoupled(new RecoveryEvent(p))) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/IFUCTU.scala b/chisel/src/main/scala/linxcore/top/interface/IFUCTU.scala new file mode 100644 index 00000000..18055575 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/IFUCTU.scala @@ -0,0 +1,43 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +object PredictionKind extends ChiselEnum { + val None, Fall, Conditional, Call, Return, Direct, Indirect = Value +} + +class PredictionMeta(val p: CoreParams) extends Bundle { + val valid = Bool() + val predictionTag = UInt(p.transactionIdWidth.W) + val transactionId = UInt(p.transactionIdWidth.W) + val fetchPacketUid = UInt(p.instructionIdWidth.W) + val fetchSeq = UInt(p.instructionIdWidth.W) + val checkpointId = + UInt(InterfaceWidth.index(p.ifu.predictionCheckpointEntries).W) + val requestPc = UInt(p.pcWidth.W) + val taken = Bool() + val branchPc = UInt(p.pcWidth.W) + val target = UInt(p.pcWidth.W) + val fallthroughPc = UInt(p.pcWidth.W) + val kind = PredictionKind() + val provider = UInt(4.W) + val stage = UInt(3.W) + val confidence = UInt(2.W) + val epoch = UInt(p.epochWidth.W) +} + +class FetchedInstruction(val p: CoreParams) extends Bundle { + val identity = new InstructionIdentity(p) + val pc = UInt(p.pcWidth.W) + val instruction = UInt(p.instructionWidth.W) + val lengthBytes = UInt(4.W) + val prediction = new PredictionMeta(p) + val fetchFault = Bool() + val fetchFaultCause = UInt(p.trapCauseWidth.W) +} + +class FetchedPacket(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.fetchWidth).W) + val entries = Vec(p.widths.fetchWidth, new FetchedInstruction(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/IFUIO.scala b/chisel/src/main/scala/linxcore/top/interface/IFUIO.scala new file mode 100644 index 00000000..11a2c7b1 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/IFUIO.scala @@ -0,0 +1,14 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class IFUIO(val p: CoreParams) extends Bundle { + val toCtu = Decoupled(new FetchedPacket(p)) + val memoryRequest = Decoupled(new MemoryRequestTxn(p)) + val memoryResponse = Flipped(Decoupled(new MemoryResponseTxn(p))) + val branchResolve = Flipped(Decoupled(new BranchResolveTxn(p))) + val recovery = Flipped(new RecoveryTargetIO(p)) + val trace = Decoupled(new TracePacket(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/Identity.scala b/chisel/src/main/scala/linxcore/top/interface/Identity.scala new file mode 100644 index 00000000..b5634da6 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/Identity.scala @@ -0,0 +1,48 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util.log2Ceil +import linxcore.params.CoreParams + +object InterfaceWidth { + def index(entries: Int): Int = math.max(1, log2Ceil(entries)) +} + +/** Architectural parent identity, independent of ROB residency. */ +class InstructionIdentity(val p: CoreParams) extends Bundle { + val peId = UInt(p.peIdWidth.W) + val stid = UInt(p.ooo.stidWidth.W) + val instructionId = UInt(p.instructionIdWidth.W) + val epoch = UInt(p.epochWidth.W) +} + +/** Complete identity of one resident logical uop member. + * + * Native BID and BROB generation intentionally remain separate domains. + */ +class RobIdentity(val p: CoreParams) extends Bundle { + val peId = UInt(p.peIdWidth.W) + val stid = UInt(p.ooo.stidWidth.W) + val ridSlot = UInt(p.ooo.ridSlotWidth.W) + val ridGeneration = UInt(p.ridGenerationWidth.W) + val memberIndex = UInt(p.ooo.robMemberIndexWidth.W) + val residentGeneration = UInt(p.residentGenerationWidth.W) + val bid = UInt(p.nativeBidWidth.W) + val brobGeneration = UInt(p.brobGenerationWidth.W) +} + +/** Wrap-qualified identity for an asynchronous memory transaction. */ +class MemoryTransactionIdentity(val p: CoreParams) extends Bundle { + val value = UInt(p.memoryTransactionIdWidth.W) + val generation = UInt(p.memoryTransactionGenerationWidth.W) +} + +/** Exact identity retained across LSU queues, attempts, and return pipes. */ +class MemoryIdentity(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val transaction = new MemoryTransactionIdentity(p) + val lsid = UInt(p.lsidWidth.W) + val attemptGeneration = UInt(p.memoryAttemptGenerationWidth.W) + val pipeId = UInt(InterfaceWidth.index( + math.max(p.lsu.loadPipes, p.lsu.storePipes)).W) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/LSUIO.scala b/chisel/src/main/scala/linxcore/top/interface/LSUIO.scala new file mode 100644 index 00000000..57c23e40 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/LSUIO.scala @@ -0,0 +1,50 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +object LSUMemoryFaultCause extends ChiselEnum { + val Alignment, Access = Value +} + +class LSUMemoryFaultTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryIdentity(p) + val address = UInt(p.physicalAddressWidth.W) + val write = Bool() + val cause = LSUMemoryFaultCause() +} + +object LSUMaintenanceCommand extends ChiselEnum { + val Fence, InvalidateTranslation, InvalidateLine, InvalidateAll = Value +} + +class LSUMaintenanceTxn(val p: CoreParams) extends Bundle { + val command = LSUMaintenanceCommand() + val address = UInt(p.physicalAddressWidth.W) +} + +class LSUMaintenanceResult(val p: CoreParams) extends Bundle { + val command = LSUMaintenanceCommand() + val address = UInt(p.physicalAddressWidth.W) + val success = Bool() +} + +class LSUIO(val p: CoreParams) extends Bundle { + val iex = Flipped(new IEXLSUIO(p)) + val storeResolve = Decoupled(new RobResolveTxn(p)) + val storeCommit = Flipped(Decoupled( + new StoreCommitAuthorizationTxn(p))) + val loadReissueRequest = Flipped(Decoupled(new LoadReplayRequestTxn(p))) + val memoryRequest = Vec(p.lsu.loadPipes + p.lsu.storePipes, + Decoupled(new MemoryRequestTxn(p))) + val memoryResponse = Flipped(Vec(p.lsu.loadPipes + p.lsu.storePipes, + Decoupled(new MemoryResponseTxn(p)))) + val recovery = Flipped(new RecoveryTargetIO(p)) + val memoryFault = Decoupled(new LSUMemoryFaultTxn(p)) + val maintenance = Flipped(Decoupled(new LSUMaintenanceTxn(p))) + val maintenanceResult = Decoupled(new LSUMaintenanceResult(p)) + val trace = Decoupled(new TracePacket(p)) + val quiescent = Output(Bool()) + val protocolError = Output(Bool()) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/Memory.scala b/chisel/src/main/scala/linxcore/top/interface/Memory.scala new file mode 100644 index 00000000..02d2c053 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/Memory.scala @@ -0,0 +1,66 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util.MuxLookup +import linxcore.params.CoreParams + +object MemoryCommand extends ChiselEnum { + val Read, Write, AcquireRead, AcquireWrite, Invalidate = Value +} + +object MemoryAccessKind extends ChiselEnum { + val InstructionLine, InstructionTranslation, Data, Device = Value +} + +/** Log2 byte-count encoding for every external memory transaction. + * + * The named values make a 64-byte line representable without widening or + * overloading the semantic 1/2/4/8-byte access fields used inside IEX/LSU. + */ +object MemorySize extends ChiselEnum { + val Bytes1, Bytes2, Bytes4, Bytes8, Bytes16, Bytes32, Bytes64 = Value + + def fromBytes(bytes: UInt): Type = MuxLookup(bytes, Bytes1)(Seq( + 1.U -> Bytes1, + 2.U -> Bytes2, + 4.U -> Bytes4, + 8.U -> Bytes8, + 16.U -> Bytes16, + 32.U -> Bytes32, + 64.U -> Bytes64)) + + def bytes(size: Type): UInt = MuxLookup(size.asUInt, 1.U(7.W))(Seq( + Bytes1.asUInt -> 1.U, + Bytes2.asUInt -> 2.U, + Bytes4.asUInt -> 4.U, + Bytes8.asUInt -> 8.U, + Bytes16.asUInt -> 16.U, + Bytes32.asUInt -> 32.U, + Bytes64.asUInt -> 64.U)) +} + +class MemoryRequestTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryTransactionIdentity(p) + val command = MemoryCommand() + val accessKind = MemoryAccessKind() + val address = UInt(p.physicalAddressWidth.W) + val data = UInt(p.dataWidth.W) + val byteMask = UInt((p.dataWidth / 8).W) + val size = MemorySize() + val instructionSide = Bool() +} + +class MemoryResponseTxn(val p: CoreParams) extends Bundle { + val identity = new MemoryTransactionIdentity(p) + val address = UInt(p.physicalAddressWidth.W) + val data = UInt(p.dataWidth.W) + val lineData = UInt((p.lsu.lineBytes * 8).W) + val denied = Bool() + val corrupt = Bool() + val errorCause = UInt(p.trapCauseWidth.W) + val attributesValid = Bool() + val readable = Bool() + val writable = Bool() + val cacheable = Bool() + val device = Bool() +} diff --git a/chisel/src/main/scala/linxcore/top/interface/OOOD1D2.scala b/chisel/src/main/scala/linxcore/top/interface/OOOD1D2.scala new file mode 100644 index 00000000..f31407e7 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/OOOD1D2.scala @@ -0,0 +1,62 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util.{Decoupled, log2Ceil} +import linxcore.params.CoreParams + +/** Typed precise-trap intent attached to the canonical D1 decode result. */ +class DecodeTrapIntent(val p: CoreParams) extends Bundle { + val valid = Bool() + val cause = UInt(p.trapCauseWidth.W) +} + +/** One normalized D1 result shared by encoded and CTU template operations. */ +class DecodedLane(val p: CoreParams) extends Bundle { + val uop = new DecodedUop(p) + val trap = new DecodeTrapIntent(p) +} + +class DecodedPacket(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.decodeWidth).W) + val entries = Vec(p.widths.decodeWidth, new DecodedLane(p)) +} + +class VirtualRobGroupIntent(val p: CoreParams) extends Bundle { + val valid = Bool() + val peId = UInt(p.peIdWidth.W) + val stid = UInt(p.ooo.stidWidth.W) + val ridSlot = UInt(p.ooo.ridSlotWidth.W) + val ridGeneration = UInt(p.ridGenerationWidth.W) +} + +class D2AdmissionLane(val p: CoreParams) extends Bundle { + val uop = new DecodedUop(p) + val trap = new DecodeTrapIntent(p) + val residentBound = Bool() + val brobBound = Bool() +} + +/** Immutable D2 virtual allocation transaction. Physical ROB/BROB publication + * is deliberately absent; D3 remains the unique tail mutator. + */ +class D2AdmissionGroup(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.decodeWidth).W) + val groupCount = UInt(PrefixPacketContract.countWidth(p.widths.decodeWidth).W) + val groups = Vec(p.widths.decodeWidth, new VirtualRobGroupIntent(p)) + val entries = Vec(p.widths.decodeWidth, new D2AdmissionLane(p)) +} + +/** Complete public IO of the Task-7 OOO D1/D2 slice. + * + * Later OOO tasks extend or replace this slice at the canonical `OOOIO` + * boundary; no implementation package owns a duplicate public contract. + */ +class OOOD1D2IO(val p: CoreParams) extends Bundle { + val fromCtu = Flipped(Decoupled(new D1Packet(p))) + val ridTailSlot = Input(Vec(p.ooo.stidCount, + UInt(p.ooo.ridSlotWidth.W))) + val ridTailGeneration = Input(Vec(p.ooo.stidCount, + UInt(p.ridGenerationWidth.W))) + val recovery = Flipped(new RecoveryTargetIO(p)) + val d2 = Decoupled(new D2AdmissionGroup(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/OOOD2D3.scala b/chisel/src/main/scala/linxcore/top/interface/OOOD2D3.scala new file mode 100644 index 00000000..0b2ad651 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/OOOD2D3.scala @@ -0,0 +1,129 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util.{Decoupled, Valid, log2Ceil} +import linxcore.params.CoreParams + +/** Exact rename-history row owned by the D2/D3 boundary. + * + * One row exists per architectural destination slot. Zero-destination uops + * still pass through D3 with an empty history vector so commit/recovery can + * preserve per-uop ordering without inventing a single-destination shape. + */ +class D3RenameHistory(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = OperandKind() + val atag = UInt(p.archRegWidth.W) + + val ptag = UInt(p.ooo.gprTagWidth.W) + val previousPtag = UInt(p.ooo.gprTagWidth.W) + val pGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + val previousPGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + val pMapQIndex = UInt(InterfaceWidth.index(p.ooo.gprMapQDepthPerStid).W) + val pMapQGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + + val ttag = UInt(p.ooo.tTagWidth.W) + val previousTtag = UInt(p.ooo.tTagWidth.W) + val tGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val tMapQIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val tMapQGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + + val utag = UInt(p.ooo.uTagWidth.W) + val previousUtag = UInt(p.ooo.uTagWidth.W) + val uGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val uMapQIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val uMapQGeneration = UInt(p.ooo.localSeqGenerationWidth.W) +} + +class D3LocalSeqSnapshot(val p: CoreParams, val entries: Int) extends Bundle { + val valid = Bool() + val tag = UInt(InterfaceWidth.index(entries).W) + val generation = UInt(p.ooo.localSeqGenerationWidth.W) +} + +class D3RenameLane(val p: CoreParams) extends Bundle { + val uop = new RenamedUop(p) + val trap = new DecodeTrapIntent(p) + val history = Vec(p.maxDestinationOperands, new D3RenameHistory(p)) + val tSeqBefore = new D3LocalSeqSnapshot(p, p.ooo.tuMapQDepthPerStid) + val uSeqBefore = new D3LocalSeqSnapshot(p, p.ooo.tuMapQDepthPerStid) + val residentBound = Bool() + val brobBound = Bool() + val blockStart = Bool() + val blockStop = Bool() + val earlyRobComplete = Bool() + val memoryOrder = new MemoryOrderMeta(p) + val pcBufferIndexOffset = new PcBufferIndexOffset(p) +} + +/** Full per-STID serial tail. This is program-order identity, never a + * physical LIQ/STQ index or a retry-attempt generation. + */ +class MemoryOrderState(val p: CoreParams) extends Bundle { + val lsid = UInt(p.lsidWidth.W) + val lid = UInt(p.lsidWidth.W) + val sid = UInt(p.lsidWidth.W) + val yostValid = Bool() + val yostLsid = UInt(p.lsidWidth.W) + val yostSid = UInt(p.lsidWidth.W) + val yoldValid = Bool() + val yoldLsid = UInt(p.lsidWidth.W) + val yoldLid = UInt(p.lsidWidth.W) +} + +class MemoryOrderReservation(val p: CoreParams) extends Bundle { + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val before = new MemoryOrderState(p) + val after = new MemoryOrderState(p) +} + +class D3RenameGroup(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val groupCount = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val groups = Vec(p.ooo.d3PrefixWidth, new VirtualRobGroupIntent(p)) + val entries = Vec(p.ooo.d3PrefixWidth, new D3RenameLane(p)) + val memoryOrder = new MemoryOrderReservation(p) +} + +/** Side-effect-free limit for the oldest complete portion of one retained D3 row. */ +class D3PrefixLimit(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val groupCount = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) +} + +class RenameCommitReleaseEntry(val p: CoreParams) extends Bundle { + val valid = Bool() + val rob = new RobIdentity(p) + /** Allocation epoch retained by T/U MapQ rows and exact release metadata. */ + val epoch = UInt(p.epochWidth.W) + val blockLast = Bool() + val history = Vec(p.maxDestinationOperands, new D3RenameHistory(p)) +} + +class RenameCommitReleaseTxn(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.retireWidth).W) + val lanes = Vec(p.widths.retireWidth, new RenameCommitReleaseEntry(p)) +} + +class RENUD2D3IO(val p: CoreParams) extends Bundle { + val fromD2 = Flipped(Decoupled(new D2AdmissionGroup(p))) + val candidate = Output(Valid(new D3RenameGroup(p))) + val reservedGroupCount = Output(Vec(p.ooo.stidCount, + UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W))) + val prefixLimit = Input(Valid(new D3PrefixLimit(p))) + val toD3 = Decoupled(new D3RenameGroup(p)) + val publicationIdentity = Input(Valid(new OOORobPrepared(p))) + val release = Flipped(Valid(new RenameCommitReleaseTxn(p))) + val releaseReady = Output(Bool()) + val releaseApply = Input(Bool()) + val recovery = Flipped(new RecoveryTargetIO(p)) + val debugPMap = Output(Vec(p.ooo.stidCount, + Vec(p.ooo.gprArchRegs, + UInt(p.ooo.gprTagWidth.W)))) + val debugTCount = Output(Vec(p.ooo.stidCount, + UInt(log2Ceil(p.ooo.tuMapQDepthPerStid + 1).W))) + val debugUCount = Output(Vec(p.ooo.stidCount, + UInt(log2Ceil(p.ooo.tuMapQDepthPerStid + 1).W))) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/OOOIEX.scala b/chisel/src/main/scala/linxcore/top/interface/OOOIEX.scala new file mode 100644 index 00000000..7fd70615 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/OOOIEX.scala @@ -0,0 +1,212 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class RenamedSource(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = OperandKind() + val atag = UInt(p.archRegWidth.W) + val ptag = UInt(p.ooo.gprTagWidth.W) + val ttag = UInt(p.ooo.tTagWidth.W) + val utag = UInt(p.ooo.uTagWidth.W) + val pGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + val tGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val uGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val tSeqIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val tSeqGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val uSeqIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val uSeqGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + /** Frontend epoch of the T/U allocation named by this source. */ + val localEpoch = UInt(p.epochWidth.W) + val ptagValid = Bool() + val ttagValid = Bool() + val utagValid = Bool() + val ready = Bool() +} + +class RenamedDestination(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = OperandKind() + val atag = UInt(p.archRegWidth.W) + val ptag = UInt(p.ooo.gprTagWidth.W) + val previousPtag = UInt(p.ooo.gprTagWidth.W) + val ttag = UInt(p.ooo.tTagWidth.W) + val previousTtag = UInt(p.ooo.tTagWidth.W) + val utag = UInt(p.ooo.uTagWidth.W) + val previousUtag = UInt(p.ooo.uTagWidth.W) + val pGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + val previousPtagValid = Bool() + val tGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val previousTtagValid = Bool() + val uGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val previousUtagValid = Bool() + val previousPGeneration = UInt(p.ooo.gprTagGenerationWidth.W) + val tSeqIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val tSeqGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val uSeqIndex = UInt(InterfaceWidth.index(p.ooo.tuMapQDepthPerStid).W) + val uSeqGeneration = UInt(p.ooo.localSeqGenerationWidth.W) + val ptagValid = Bool() + val ttagValid = Bool() + val utagValid = Bool() +} + +class RenamedUop(val p: CoreParams) extends Bundle { + val decoded = new DecodedUop(p) + val sources = Vec(p.maxSourceOperands, new RenamedSource(p)) + val destinations = + Vec(p.maxDestinationOperands, new RenamedDestination(p)) +} + +/** Stable program-order allocation metadata; never a physical residency ID. */ +class MemoryOrderMeta(val p: CoreParams) extends Bundle { + val requestCount = UInt( + PrefixPacketContract.countWidth(p.maxMemoryRequestsPerInstruction).W) + val firstLsid = UInt(p.lsidWidth.W) + val firstLid = UInt(p.lsidWidth.W) + val firstSid = UInt(p.lsidWidth.W) + val yostValid = Bool() + val yostLsid = UInt(p.lsidWidth.W) + val yostSid = UInt(p.lsidWidth.W) + val yoldValid = Bool() + val yoldLsid = UInt(p.lsidWidth.W) + val yoldLid = UInt(p.lsidWidth.W) +} + +class DispatchTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val uop = new RenamedUop(p) + val memoryOrder = new MemoryOrderMeta(p) + val trap = new DecodeTrapIntent(p) + val pcBufferIndexOffset = new PcBufferIndexOffset(p) +} + +/** One atomic store issue request. IEX accepts this beat once, then performs + * the internal STA/STD fork without exposing partial side effects to OOO. + */ +class StoreDispatchTxn(val p: CoreParams) extends Bundle { + val sta = new DispatchTxn(p) + val std = new DispatchTxn(p) + val aguPipe = UInt(InterfaceWidth.index(p.iex.aguPipes).W) + val stdPipe = UInt(InterfaceWidth.index(p.iex.stdPipes).W) +} + +class RobResolveTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val rob = new RobIdentity(p) + val destinationValid = Bool() + val destinationIndex = + UInt(InterfaceWidth.index(p.maxDestinationOperands).W) + val value = UInt(p.dataWidth.W) + val trap = new TrapEvent(p) +} + +/** Exact physical destination identity installed as not-ready by the common + * D3 publication fire. The destination carries the P generation or complete + * T/U `{tag, sequence, epoch}` allocation identity without reconstruction. + */ +class OperandAllocationClearTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val epoch = UInt(p.epochWidth.W) + val destination = new RenamedDestination(p) +} + +/** Architectural boot initialization for one exact physical GPR row. */ +class PFileInitTxn(val p: CoreParams) extends Bundle { + val stid = UInt(p.ooo.stidWidth.W) + val atag = UInt(InterfaceWidth.index(p.ooo.gprArchRegs).W) + val epoch = UInt(p.epochWidth.W) + val ptag = UInt(p.ooo.gprTagWidth.W) + val generation = UInt(p.ooo.gprTagGenerationWidth.W) + val value = UInt(p.dataWidth.W) +} + +class FastWritebackTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val epoch = UInt(p.epochWidth.W) + val destinationIndex = UInt(InterfaceWidth.index( + p.maxDestinationOperands).W) + val destination = new RenamedDestination(p) + val value = UInt(p.dataWidth.W) +} + +class FastWakeupTxn(val p: CoreParams) extends Bundle { + val rob = new RobIdentity(p) + val epoch = UInt(p.epochWidth.W) + val destination = new RenamedDestination(p) +} + +/** One atomic fast-result publication. IEX derives the wakeup from the exact + * writeback identity; OOO completes the ROB member on the same fire. + */ +class FastResultTxn(val p: CoreParams) extends Bundle { + val writeback = new FastWritebackTxn(p) +} + +/** Exact ROB-head authorization for one resident system or CMD side effect. */ +class RobNoflushTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) +} + +/** Exact NFRDY proof: legality is complete and every older effect is drained. */ +class RobNoflushReadyTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) +} + +/** Commit-control-owned no-destination system side effect. */ +class SystemIssueTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val opcode = UInt(p.opcodeWidth.W) + val immediate = UInt(p.dataWidth.W) +} + +/** Independently backpressured external CMD transaction. */ +class CmdIssueTxn(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val opcode = UInt(p.opcodeWidth.W) + val sourceValid = UInt(p.maxSourceOperands.W) + val sourceValues = Vec(p.maxSourceOperands, UInt(p.dataWidth.W)) +} + +/** OOO-facing view of the OOO/IEX boundary. */ +class OOOIEXIO(val p: CoreParams) extends Bundle { + val allocationClear = Vec( + p.ooo.d3PrefixWidth * p.maxDestinationOperands, + Valid(new OperandAllocationClearTxn(p))) + val fastResult = Decoupled(new FastResultTxn(p)) + val storeBinding = Flipped(Vec(p.iex.stdPipes, + Decoupled(new StoreTransactionBindingTxn(p)))) + val aluDispatch = + Vec(p.iex.aluPipes, Decoupled(new DispatchTxn(p))) + val bruDispatch = + Vec(p.iex.bruPipes, Decoupled(new DispatchTxn(p))) + val aguDispatch = + Vec(p.iex.aguPipes, Decoupled(new DispatchTxn(p))) + val storeDispatch = + Vec(p.iex.stdPipes, Decoupled(new StoreDispatchTxn(p))) + val systemDispatch = + Vec(p.iex.systemMulticycleQueues, Decoupled(new DispatchTxn(p))) + val cmdDispatch = + Vec(p.iex.cmdIssueQueues, Decoupled(new DispatchTxn(p))) + val pcBufferReadAddress = Flipped(Vec(p.ooo.pcReadPorts, + new PcBufferReadAddress(p))) + val pcBufferReadPcBase = Vec(p.ooo.pcReadPorts, + Valid(UInt(p.pcWidth.W))) + val robNoflushReady = Flipped(Decoupled(new RobNoflushReadyTxn(p))) + val robNoflush = Decoupled(new RobNoflushTxn(p)) + val robResolve = + Flipped(Vec(p.widths.issueWidth, Decoupled(new RobResolveTxn(p)))) + val systemIssue = Flipped(Vec(p.iex.systemMulticycleQueues, + Decoupled(new SystemIssueTxn(p)))) + val recoveryEvent = Flipped(Decoupled(new RecoveryEvent(p))) + val recovery = new RecoveryTargetIO(p) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/OOOIO.scala b/chisel/src/main/scala/linxcore/top/interface/OOOIO.scala new file mode 100644 index 00000000..ca5d7db9 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/OOOIO.scala @@ -0,0 +1,23 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class OOOIO(val p: CoreParams) extends Bundle { + val fromCtu = Flipped(Decoupled(new D1Packet(p))) + val iex = new OOOIEXIO(p) + val storeResolve = Flipped(Decoupled(new RobResolveTxn(p))) + val commit = Decoupled(new CommitTxn(p)) + val storeCommit = Decoupled(new StoreCommitAuthorizationTxn(p)) + val trap = Decoupled(new TrapEvent(p)) + val interrupt = Flipped(Valid(new InterruptRequest(p))) + val debugRequest = Flipped(Decoupled(new DebugRequest(p))) + val debugResponse = Decoupled(new DebugResponse(p)) + val recoveryToIfu = new RecoveryTargetIO(p) + val recoveryToCtu = new RecoveryTargetIO(p) + val recoveryToLsu = new RecoveryTargetIO(p) + val systemIssue = Vec(p.iex.systemMulticycleQueues, + Decoupled(new SystemIssueTxn(p))) + val trace = Decoupled(new TracePacket(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/OOORob.scala b/chisel/src/main/scala/linxcore/top/interface/OOORob.scala new file mode 100644 index 00000000..ff38b2d2 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/OOORob.scala @@ -0,0 +1,200 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class OOORobPreparedEntry(val p: CoreParams) extends Bundle { + val valid = Bool() + val rob = new RobIdentity(p) + val commit = new CommitEntry(p) + val rename = new RenameCommitReleaseEntry(p) +} + +class OOORobPrepared(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val entries = Vec(p.ooo.d3PrefixWidth, new OOORobPreparedEntry(p)) +} + +class OOORobReleaseEntry(val p: CoreParams) extends Bundle { + val valid = Bool() + val rob = new RobIdentity(p) +} + +class OOORobReleaseTxn(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.retireWidth).W) + val lanes = Vec(p.widths.retireWidth, new OOORobReleaseEntry(p)) +} + +class OOORobCommitPreviewEntry(val p: CoreParams) extends Bundle { + val valid = Bool() + val commit = new CommitEntry(p) + val rename = new RenameCommitReleaseEntry(p) +} + +class OOORobCommitPreview(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.retireWidth).W) + val entries = Vec(p.widths.retireWidth, new OOORobCommitPreviewEntry(p)) + val headValid = Bool() + val head = new RobIdentity(p) + val headTrap = new TrapEvent(p) +} + +class OOORobResidentHeadPreview(val p: CoreParams) extends Bundle { + val valid = Bool() + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val noflushEligible = Bool() +} + +/** Read-only identity and completion state of one STID's architectural ROB head. + * + * This is diagnostic visibility over the existing ROB owner. It must not be + * used as a second commit, recovery, or residency owner. + */ +class OOORobHeadStatus(val p: CoreParams) extends Bundle { + val valid = Bool() + val completed = Bool() + val retired = Bool() + val transactionId = UInt(p.transactionIdWidth.W) + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val pc = UInt(p.pcWidth.W) + val instructionBits = UInt(p.instructionWidth.W) + val opcode = UInt(p.opcodeWidth.W) +} + +class OOORobMemoryRecovery(val p: CoreParams) extends Bundle { + val valid = Bool() + val transactionId = UInt(p.transactionIdWidth.W) + val stid = UInt(p.ooo.stidWidth.W) + val oldTail = new MemoryOrderState(p) + val newTail = new MemoryOrderState(p) +} + +class BROBPreparedEntry(val p: CoreParams) extends Bundle { + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val bid = UInt(p.nativeBidWidth.W) + val brobGeneration = UInt(p.brobGenerationWidth.W) + val allocated = Bool() +} + +class BROBPrepared(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val entries = Vec(p.ooo.d3PrefixWidth, new BROBPreparedEntry(p)) +} + +class BROBReleaseTxn(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.widths.retireWidth).W) + val entries = Vec(p.widths.retireWidth, new RobIdentity(p)) +} + +class CommitControlTxn(val p: CoreParams) extends Bundle { + val commit = new CommitTxn(p) + val rename = new RenameCommitReleaseTxn(p) + val robRelease = new OOORobReleaseTxn(p) + val brobRelease = new BROBReleaseTxn(p) + val trap = new TrapEvent(p) +} + +class RecoveryCandidateLookup(val p: CoreParams) extends Bundle { + val event = new RecoveryEvent(p) +} + +class RecoveryCandidateStatus(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val trigger = new RobIdentity(p) + val eligible = Bool() + val rejected = Bool() + val ageToken = UInt(p.transactionIdWidth.W) + val headTrap = Bool() +} + +object RecoveryAge { + def tokenWidth(p: CoreParams): Int = p.transactionIdWidth + + def requireUnambiguousWindow(p: CoreParams): Unit = { + val tokenSpace = BigInt(1) << tokenWidth(p) + val maxLiveWindow = + BigInt(p.ooo.stidCount) * BigInt(p.ooo.robCapacityPerStid) + require( + tokenSpace > (maxLiveWindow * 2), + "recovery age token space must be more than twice the global live ROB window") + } + + def older(a: UInt, b: UInt): Bool = { + val diff = b - a + diff =/= 0.U && !diff(diff.getWidth - 1) + } +} + +object RecoveryPlanContract { + private def memberOrdinal(id: RobIdentity): UInt = + Cat(id.ridGeneration, id.ridSlot, id.memberIndex) + + def sameRobRequest(response: RecoveryPlan, request: RecoveryPlan): Bool = + response.phase === RecoveryPhase.Prepare && + request.phase === RecoveryPhase.Prepare && + response.transactionId === request.transactionId && + response.cause === request.cause && + response.trigger.asUInt === request.trigger.asUInt && + response.redirectPc === request.redirectPc && + response.newEpoch === request.newEpoch + + def sameTransactionIgnoringPhase(a: RecoveryPlan, b: RecoveryPlan): Bool = + a.transactionId === b.transactionId && + a.cause === b.cause && + a.trigger.asUInt === b.trigger.asUInt && + a.survivingTailValid === b.survivingTailValid && + a.survivingTail.asUInt === b.survivingTail.asUInt && + a.redirectPc === b.redirectPc && + a.newEpoch === b.newEpoch && + a.firstKilledValid === b.firstKilledValid && + a.firstKilled.asUInt === b.firstKilled.asUInt && + a.lastKilled.asUInt === b.lastKilled.asUInt && + a.killedGroupCount === b.killedGroupCount && + a.killedMemberCount === b.killedMemberCount + + def suffixMember(plan: RecoveryPlan, member: RobIdentity): Bool = { + val sameIdentitySpace = + member.peId === plan.trigger.peId && member.stid === plan.trigger.stid + val first = memberOrdinal(plan.firstKilled) + val last = memberOrdinal(plan.lastKilled) + val current = memberOrdinal(member) + val noWrap = first <= last + val inWindow = Mux(noWrap, + current >= first && current <= last, + current >= first || current <= last) + plan.firstKilledValid && sameIdentitySpace && inWindow + } + + def legalSuffixWindow(plan: RecoveryPlan): Bool = { + val empty = !plan.firstKilledValid && + plan.killedGroupCount === 0.U && plan.killedMemberCount === 0.U + val nonEmpty = plan.firstKilledValid && + plan.killedGroupCount =/= 0.U && + plan.killedMemberCount =/= 0.U && + plan.firstKilled.stid === plan.trigger.stid && + plan.lastKilled.stid === plan.trigger.stid + empty || nonEmpty + } +} + +class RecoveryPlanContractProbeIO(val p: CoreParams) extends Bundle { + val a = Input(new RecoveryPlan(p)) + val b = Input(new RecoveryPlan(p)) + val member = Input(new RobIdentity(p)) + val sameIgnoringPhase = Output(Bool()) + val memberKilled = Output(Bool()) + val legalWindow = Output(Bool()) +} + +class RecoveryPlanContractProbe(val p: CoreParams) extends Module { + val io = IO(new RecoveryPlanContractProbeIO(p)) + io.sameIgnoringPhase := + RecoveryPlanContract.sameTransactionIgnoringPhase(io.a, io.b) + io.memberKilled := RecoveryPlanContract.suffixMember(io.a, io.member) + io.legalWindow := RecoveryPlanContract.legalSuffixWindow(io.a) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/PCBuffer.scala b/chisel/src/main/scala/linxcore/top/interface/PCBuffer.scala new file mode 100644 index 00000000..5cbb0a55 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/PCBuffer.scala @@ -0,0 +1,27 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +/** PC buffer index and byte offset carried with one uop instead of a full PC. */ +class PcBufferIndexOffset(val p: CoreParams) extends Bundle { + val valid = Bool() + val pcBufferIndex = UInt(InterfaceWidth.index(p.ooo.pcBufferEntries).W) + val pcOffset = UInt(p.ooo.pcOffsetWidth.W) + val allocationEpoch = UInt(p.ooo.pcAllocationEpochWidth.W) +} + +/** Readyless I1 read address for the OOO-owned PC buffer. */ +class PcBufferReadAddress(val p: CoreParams) extends Bundle { + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val pcBufferIndex = UInt(InterfaceWidth.index(p.ooo.pcBufferEntries).W) + val allocationEpoch = UInt(p.ooo.pcAllocationEpochWidth.W) +} + +/** Side-effect-free D3 PC-buffer allocation result. */ +class PcBufferD3Prepared(val p: CoreParams) extends Bundle { + val count = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val groupCount = UInt(PrefixPacketContract.countWidth(p.ooo.d3PrefixWidth).W) + val lanes = Vec(p.ooo.d3PrefixWidth, new PcBufferIndexOffset(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/Packet.scala b/chisel/src/main/scala/linxcore/top/interface/Packet.scala new file mode 100644 index 00000000..6cf87896 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/Packet.scala @@ -0,0 +1,15 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util.log2Ceil + +object PrefixPacketContract { + def countWidth(maxWidth: Int): Int = { + require(maxWidth > 0, "packet width must be positive") + math.max(1, log2Ceil(maxWidth + 1)) + } + + /** A count-only packet represents entries [0, count); holes are impossible. */ + def countIsLegal(count: UInt, maxWidth: Int): Bool = + count <= maxWidth.U +} diff --git a/chisel/src/main/scala/linxcore/top/interface/Recovery.scala b/chisel/src/main/scala/linxcore/top/interface/Recovery.scala new file mode 100644 index 00000000..f780a437 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/Recovery.scala @@ -0,0 +1,52 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +object RecoveryCause extends ChiselEnum { + val Branch, Exception, Interrupt, MemoryOrder, Debug, CtuCancel = Value +} + +object RecoveryPhase extends ChiselEnum { + val Prepare, Apply, Abort = Value +} + +class RecoveryEvent(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val cause = RecoveryCause() + val trigger = new RobIdentity(p) + val instruction = new InstructionIdentity(p) + val redirectPc = UInt(p.pcWidth.W) + val trap = new TrapEvent(p) +} + +class RecoveryPlan(val p: CoreParams) extends Bundle { + val transactionId = UInt(p.transactionIdWidth.W) + val phase = RecoveryPhase() + val cause = RecoveryCause() + val trigger = new RobIdentity(p) + val survivingTailValid = Bool() + val survivingTail = new RobIdentity(p) + val redirectPc = UInt(p.pcWidth.W) + val newEpoch = UInt(p.epochWidth.W) + val firstKilledValid = Bool() + val firstKilled = new RobIdentity(p) + val lastKilled = new RobIdentity(p) + val killedGroupCount = + UInt(PrefixPacketContract.countWidth(p.ooo.robGroupsPerStid).W) + val killedMemberCount = + UInt(PrefixPacketContract.countWidth(p.ooo.robCapacityPerStid).W) +} + +/** OOO-facing recovery target protocol. + * + * The target prepares without mutation. Apply or abort is a later terminal + * broadcast carrying the same transaction identity. + */ +class RecoveryTargetIO(val p: CoreParams) extends Bundle { + val prepare = Decoupled(new RecoveryPlan(p)) + val prepared = Flipped(Decoupled(new RecoveryPlan(p))) + val apply = Valid(new RecoveryPlan(p)) + val abort = Valid(new RecoveryPlan(p)) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/TOPIO.scala b/chisel/src/main/scala/linxcore/top/interface/TOPIO.scala new file mode 100644 index 00000000..59e464a4 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/TOPIO.scala @@ -0,0 +1,36 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.util._ +import linxcore.params.CoreParams + +class TOPIO(val p: CoreParams) extends Bundle { + val instructionMemoryRequest = Decoupled(new MemoryRequestTxn(p)) + val instructionMemoryResponse = + Flipped(Decoupled(new MemoryResponseTxn(p))) + val dataMemoryRequest = Vec(p.lsu.loadPipes + p.lsu.storePipes, + Decoupled(new MemoryRequestTxn(p))) + val dataMemoryResponse = Flipped(Vec( + p.lsu.loadPipes + p.lsu.storePipes, + Decoupled(new MemoryResponseTxn(p)))) + val pInit = Flipped(Decoupled(new PFileInitTxn(p))) + val bootstrapComplete = Input(Bool()) + val bootstrapReady = Output(Bool()) + val interrupt = Flipped(Valid(new InterruptRequest(p))) + val debugRequest = Flipped(Decoupled(new DebugRequest(p))) + val debugResponse = Decoupled(new DebugResponse(p)) + val systemIssue = Vec(p.iex.systemMulticycleQueues, + Decoupled(new SystemIssueTxn(p))) + val cmdIssue = Decoupled(new CmdIssueTxn(p)) + val loadReissueRequest = Flipped(Decoupled(new LoadReplayRequestTxn(p))) + val memoryFault = Decoupled(new LSUMemoryFaultTxn(p)) + val maintenance = Flipped(Decoupled(new LSUMaintenanceTxn(p))) + val maintenanceResult = Decoupled(new LSUMaintenanceResult(p)) + val commit = Decoupled(new CommitTxn(p)) + val trap = Decoupled(new TrapEvent(p)) + val trace = Decoupled(new TracePacket(p)) + val performanceCounters = Output(Vec( + p.dtu.performanceCounterCount, UInt(64.W))) + val lsuQuiescent = Output(Bool()) + val lsuProtocolError = Output(Bool()) +} diff --git a/chisel/src/main/scala/linxcore/top/interface/TrapInterrupt.scala b/chisel/src/main/scala/linxcore/top/interface/TrapInterrupt.scala new file mode 100644 index 00000000..35c191c2 --- /dev/null +++ b/chisel/src/main/scala/linxcore/top/interface/TrapInterrupt.scala @@ -0,0 +1,25 @@ +package linxcore.top.interface + +import chisel3._ +import linxcore.params.CoreParams + +object TrapKind extends ChiselEnum { + val None, Exception, Interrupt, Debug = Value +} + +class TrapEvent(val p: CoreParams) extends Bundle { + val valid = Bool() + val kind = TrapKind() + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val cause = UInt(p.trapCauseWidth.W) + val targetPc = UInt(p.pcWidth.W) + val tval = UInt(p.dataWidth.W) +} + +class InterruptRequest(val p: CoreParams) extends Bundle { + val valid = Bool() + val stid = UInt(p.ooo.stidWidth.W) + val cause = UInt(p.trapCauseWidth.W) + val priority = UInt(8.W) +} diff --git a/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterBehaviorProbe.scala b/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterBehaviorProbe.scala deleted file mode 100644 index 4efc70c1..00000000 --- a/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterBehaviorProbe.scala +++ /dev/null @@ -1,136 +0,0 @@ -package linxcore.backend - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.{CommitTraceParams, CommitTraceRow} -import org.scalatest.funsuite.AnyFunSuite - -class ReducedRobCompletionArbiterBehaviorProbeIO extends Bundle { - val executeValid = Input(Bool()) - val executeSlot = Input(UInt(3.W)) - val executeRowValid = Input(Bool()) - val executeRowToken = Input(UInt(64.W)) - - val replayValid = Input(Bool()) - val replaySlot = Input(UInt(3.W)) - val replayRowValid = Input(Bool()) - val replayRowToken = Input(UInt(64.W)) - - val templateValid = Input(Bool()) - val templateSlot = Input(UInt(3.W)) - val templateRowValid = Input(Bool()) - val templateRowToken = Input(UInt(64.W)) - val templateParentSlot = Input(UInt(3.W)) - - val serviceValid = Input(Bool()) - val serviceSlot = Input(UInt(3.W)) - val serviceRowValid = Input(Bool()) - val serviceRowToken = Input(UInt(64.W)) - - val completeValid = Output(Bool()) - val completeSlot = Output(UInt(3.W)) - val completeRowValid = Output(Bool()) - val completeRowToken = Output(UInt(64.W)) - val completeRowSignature = Output(UInt(64.W)) - val completeRowMemToken = Output(UInt(64.W)) - val selectedExecute = Output(Bool()) - val selectedReplay = Output(Bool()) - val selectedService = Output(Bool()) - val selectedTemplate = Output(Bool()) - val selectedSourceMask = Output(UInt(4.W)) - val replayBlockedByExecute = Output(Bool()) - val serviceBlockedByExecute = Output(Bool()) - val serviceBlockedByReplay = Output(Bool()) - val templateBlockedByExecute = Output(Bool()) - val templateBlockedByReplay = Output(Bool()) - val completionContended = Output(Bool()) - val sameRobCompletionContention = Output(Bool()) - val differentRobCompletionContention = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ReducedRobCompletionArbiterBehaviorProbe extends Module { - private val traceParams = CommitTraceParams(robValueWidth = 3) - val io = IO(new ReducedRobCompletionArbiterBehaviorProbeIO) - - chisel3.layer.enable(chisel3.layers.Verification.Assert) - - private val arbiter = Module( - new ReducedRobCompletionArbiter( - ptrWidth = 3, - traceParams = traceParams)) - - private def driveRow(row: CommitTraceRow, valid: Bool, token: UInt): Unit = { - row := 0.U.asTypeOf(new CommitTraceRow(traceParams)) - row.valid := valid - row.seq := token - row.pc := token - row.insn := token ^ "h5a5a5a5a5a5a5a5a".U - row.nextPc := token + 8.U - row.mem.valid := valid - row.mem.wdata := token ^ "ha5a5a5a5a5a5a5a5".U - } - - arbiter.io.executeCompleteValid := io.executeValid - arbiter.io.executeCompleteRobValue := io.executeSlot - arbiter.io.executeCompleteRowValid := io.executeRowValid - driveRow(arbiter.io.executeCompleteRow, io.executeRowValid, io.executeRowToken) - - arbiter.io.replayCompleteValid := io.replayValid - arbiter.io.replayCompleteRobValue := io.replaySlot - arbiter.io.replayCompleteRowValid := io.replayRowValid - driveRow(arbiter.io.replayCompleteRow, io.replayRowValid, io.replayRowToken) - - arbiter.io.serviceCompleteValid := io.serviceValid - arbiter.io.serviceCompleteRobValue := io.serviceSlot - arbiter.io.serviceCompleteRowValid := io.serviceRowValid - driveRow(arbiter.io.serviceCompleteRow, io.serviceRowValid, io.serviceRowToken) - - arbiter.io.templateCompleteValid := io.templateValid - arbiter.io.templateCompleteRobValue := io.templateSlot - arbiter.io.templateCompleteRowValid := io.templateRowValid - driveRow(arbiter.io.templateCompleteRow, io.templateRowValid, io.templateRowToken) - arbiter.io.templateCompleteParentSlot := io.templateParentSlot - - io.completeValid := arbiter.io.completeValid - io.completeSlot := arbiter.io.completeRobValue - io.completeRowValid := arbiter.io.completeRowValid - io.completeRowToken := arbiter.io.completeRow.pc - io.completeRowSignature := arbiter.io.completeRow.nextPc - io.completeRowMemToken := arbiter.io.completeRow.mem.wdata - io.selectedExecute := arbiter.io.selectedExecute - io.selectedReplay := arbiter.io.selectedReplay - io.selectedService := arbiter.io.selectedService - io.selectedTemplate := arbiter.io.selectedTemplate - io.selectedSourceMask := arbiter.io.selectedSourceMask - io.replayBlockedByExecute := arbiter.io.replayBlockedByExecute - io.serviceBlockedByExecute := arbiter.io.serviceBlockedByExecute - io.serviceBlockedByReplay := arbiter.io.serviceBlockedByReplay - io.templateBlockedByExecute := arbiter.io.templateBlockedByExecute - io.templateBlockedByReplay := arbiter.io.templateBlockedByReplay - io.completionContended := arbiter.io.completionContended - io.sameRobCompletionContention := arbiter.io.sameRobCompletionContention - io.differentRobCompletionContention := arbiter.io.differentRobCompletionContention - io.protocolError := arbiter.io.protocolError -} - -object EmitReducedRobCompletionArbiterBehaviorProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-rob-completion-arbiter-behavior-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedRobCompletionArbiterBehaviorProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} - -class ReducedRobCompletionArbiterBehaviorProbeSpec extends AnyFunSuite { - test("elaborates a public wrapper around the real completion arbiter") { - val sv = ChiselStage.emitSystemVerilog(new ReducedRobCompletionArbiterBehaviorProbe) - - assert(sv.contains("module ReducedRobCompletionArbiterBehaviorProbe")) - assert(sv.contains("module ReducedRobCompletionArbiter")) - assert(!sv.toLowerCase.contains("exactcomplete")) - } -} diff --git a/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterSpec.scala b/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterSpec.scala deleted file mode 100644 index f4c119cb..00000000 --- a/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterSpec.scala +++ /dev/null @@ -1,503 +0,0 @@ -package linxcore.backend - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import circt.stage.ChiselStage -import linxcore.commit.{CommitTraceParams, CommitTraceRow} -import org.scalatest.funsuite.AnyFunSuite - -object ReducedRobCompletionArbiterReference { - final case class Source( - valid: Boolean, - robValue: Int, - rowValid: Boolean, - rowToken: Int) - - final case class Result( - completeValid: Boolean, - completeRobValue: Int, - completeRowValid: Boolean, - completeRowToken: Int, - selectedExecute: Boolean, - selectedReplay: Boolean, - selectedService: Boolean, - selectedTemplate: Boolean, - selectedSourceMask: Int, - replayBlockedByExecute: Boolean, - serviceBlockedByExecute: Boolean, - serviceBlockedByReplay: Boolean, - templateBlockedByExecute: Boolean, - templateBlockedByReplay: Boolean, - completionContended: Boolean, - sameRobCompletionContention: Boolean, - differentRobCompletionContention: Boolean, - protocolError: Boolean) - - def apply( - execute: Source, - replay: Source, - service: Source, - template: Source, - templateParentSlot: Int, - robEntries: Int = 8): Result = { - require( - !template.valid || template.robValue == templateParentSlot, - "template completion parent slot must match its slot-valued completion payload") - - def invalid(src: Source): Boolean = src.valid && (src.robValue < 0 || src.robValue >= robEntries) - - val executeCandidate = execute.valid && !invalid(execute) - val replayCandidate = replay.valid && !invalid(replay) - val serviceCandidate = service.valid && !invalid(service) - val templateCandidate = template.valid && !invalid(template) - val selectedExecute = executeCandidate - val selectedReplay = replayCandidate && !executeCandidate - val selectedService = serviceCandidate && !executeCandidate && !replayCandidate - val selectedTemplate = - templateCandidate && !executeCandidate && !replayCandidate && !serviceCandidate - val selected = - if (selectedExecute) Some(execute) - else if (selectedReplay) Some(replay) - else if (selectedService) Some(service) - else if (selectedTemplate) Some(template) - else None - val sourceMask = - (if (selectedExecute) 0x1 else 0) | - (if (selectedReplay) 0x2 else 0) | - (if (selectedService) 0x4 else 0) | - (if (selectedTemplate) 0x8 else 0) - - val sources = Seq(execute, replay, service, template) - val contended = sources.count(_.valid) >= 2 - val validRids = sources.filter(_.valid).map(_.robValue) - val differentRid = validRids.distinct.size > 1 - val invalidRid = sources.exists(invalid) - - Result( - completeValid = selected.nonEmpty, - completeRobValue = selected.map(_.robValue).getOrElse(0), - completeRowValid = selected.exists(_.rowValid), - completeRowToken = selected.map(_.rowToken).getOrElse(0), - selectedExecute = selectedExecute, - selectedReplay = selectedReplay, - selectedService = selectedService, - selectedTemplate = selectedTemplate, - selectedSourceMask = sourceMask, - replayBlockedByExecute = replay.valid && execute.valid, - serviceBlockedByExecute = service.valid && execute.valid, - serviceBlockedByReplay = service.valid && !execute.valid && replay.valid, - templateBlockedByExecute = template.valid && execute.valid, - templateBlockedByReplay = template.valid && !execute.valid && replay.valid, - completionContended = contended, - sameRobCompletionContention = contended && !differentRid, - differentRobCompletionContention = differentRid, - protocolError = invalidRid || differentRid) - } -} - -class ReducedRobCompletionArbiterProbeIO extends Bundle { - val executeValid = Input(Bool()) - val executeRobValue = Input(UInt(3.W)) - val executeRowValid = Input(Bool()) - val executeRowToken = Input(UInt(64.W)) - val replayValid = Input(Bool()) - val replayRobValue = Input(UInt(3.W)) - val replayRowValid = Input(Bool()) - val replayRowToken = Input(UInt(64.W)) - val serviceValid = Input(Bool()) - val serviceRobValue = Input(UInt(3.W)) - val serviceRowValid = Input(Bool()) - val serviceRowToken = Input(UInt(64.W)) - val templateValid = Input(Bool()) - val templateRobValue = Input(UInt(3.W)) - val templateRowValid = Input(Bool()) - val templateRowToken = Input(UInt(64.W)) - val templateParentSlot = Input(UInt(3.W)) - - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(3.W)) - val completeRowValid = Output(Bool()) - val completeRowToken = Output(UInt(64.W)) - val selectedExecute = Output(Bool()) - val selectedReplay = Output(Bool()) - val selectedService = Output(Bool()) - val selectedTemplate = Output(Bool()) - val selectedSourceMask = Output(UInt(4.W)) - val replayBlockedByExecute = Output(Bool()) - val serviceBlockedByExecute = Output(Bool()) - val serviceBlockedByReplay = Output(Bool()) - val templateBlockedByExecute = Output(Bool()) - val templateBlockedByReplay = Output(Bool()) - val completionContended = Output(Bool()) - val sameRobCompletionContention = Output(Bool()) - val differentRobCompletionContention = Output(Bool()) - val protocolError = Output(Bool()) -} - -class ReducedRobCompletionArbiterProbe extends Module { - private val traceParams = CommitTraceParams(robValueWidth = 3) - val io = IO(new ReducedRobCompletionArbiterProbeIO) - - chisel3.layer.enable(chisel3.layers.Verification.Assert) - - private val arbiter = Module( - new ReducedRobCompletionArbiter( - ptrWidth = 3, - traceParams = traceParams, - robEntries = 6)) - - private def driveRow(row: CommitTraceRow, valid: Bool, token: UInt): Unit = { - row := 0.U.asTypeOf(new CommitTraceRow(traceParams)) - row.valid := valid - row.seq := token - row.pc := token - row.insn := token ^ "h5a5a5a5a5a5a5a5a".U - row.nextPc := token + 4.U - } - - arbiter.io.executeCompleteValid := io.executeValid - arbiter.io.executeCompleteRobValue := io.executeRobValue - arbiter.io.executeCompleteRowValid := io.executeRowValid - driveRow(arbiter.io.executeCompleteRow, io.executeRowValid, io.executeRowToken) - - arbiter.io.replayCompleteValid := io.replayValid - arbiter.io.replayCompleteRobValue := io.replayRobValue - arbiter.io.replayCompleteRowValid := io.replayRowValid - driveRow(arbiter.io.replayCompleteRow, io.replayRowValid, io.replayRowToken) - - arbiter.io.serviceCompleteValid := io.serviceValid - arbiter.io.serviceCompleteRobValue := io.serviceRobValue - arbiter.io.serviceCompleteRowValid := io.serviceRowValid - driveRow(arbiter.io.serviceCompleteRow, io.serviceRowValid, io.serviceRowToken) - - arbiter.io.templateCompleteValid := io.templateValid - arbiter.io.templateCompleteRobValue := io.templateRobValue - arbiter.io.templateCompleteRowValid := io.templateRowValid - driveRow(arbiter.io.templateCompleteRow, io.templateRowValid, io.templateRowToken) - arbiter.io.templateCompleteParentSlot := io.templateParentSlot - - io.completeValid := arbiter.io.completeValid - io.completeRobValue := arbiter.io.completeRobValue - io.completeRowValid := arbiter.io.completeRowValid - io.completeRowToken := arbiter.io.completeRow.pc - io.selectedExecute := arbiter.io.selectedExecute - io.selectedReplay := arbiter.io.selectedReplay - io.selectedService := arbiter.io.selectedService - io.selectedTemplate := arbiter.io.selectedTemplate - io.selectedSourceMask := arbiter.io.selectedSourceMask - io.replayBlockedByExecute := arbiter.io.replayBlockedByExecute - io.serviceBlockedByExecute := arbiter.io.serviceBlockedByExecute - io.serviceBlockedByReplay := arbiter.io.serviceBlockedByReplay - io.templateBlockedByExecute := arbiter.io.templateBlockedByExecute - io.templateBlockedByReplay := arbiter.io.templateBlockedByReplay - io.completionContended := arbiter.io.completionContended - io.sameRobCompletionContention := arbiter.io.sameRobCompletionContention - io.differentRobCompletionContention := arbiter.io.differentRobCompletionContention - io.protocolError := arbiter.io.protocolError -} - -class ReducedRobCompletionArbiterSpec extends AnyFunSuite with ChiselSim { - import ReducedRobCompletionArbiterReference._ - - private val executePayload = Source(valid = false, robValue = 2, rowValid = true, rowToken = 0x11) - private val replayPayload = Source(valid = false, robValue = 5, rowValid = false, rowToken = 0x22) - private val servicePayload = Source(valid = false, robValue = 3, rowValid = true, rowToken = 0x33) - private val templatePayload = Source(valid = false, robValue = 4, rowValid = true, rowToken = 0x44) - - test("exhausts execute replay service template validity combinations") { - for (validBits <- 0 until 16) { - val execute = executePayload.copy(valid = (validBits & 0x8) != 0) - val replay = replayPayload.copy(valid = (validBits & 0x4) != 0) - val service = servicePayload.copy(valid = (validBits & 0x2) != 0) - val template = templatePayload.copy(valid = (validBits & 0x1) != 0) - val result = ReducedRobCompletionArbiterReference( - execute, - replay, - service, - template, - templateParentSlot = template.robValue) - val selected = - if (execute.valid) Some(("execute", execute)) - else if (replay.valid) Some(("replay", replay)) - else if (service.valid) Some(("service", service)) - else if (template.valid) Some(("template", template)) - else None - val selections = - Seq(result.selectedExecute, result.selectedReplay, result.selectedService, result.selectedTemplate) - - assert(result.completeValid == selected.nonEmpty, s"validBits=$validBits") - assert(result.completeRobValue == selected.map(_._2.robValue).getOrElse(0), s"validBits=$validBits") - assert(result.completeRowValid == selected.exists(_._2.rowValid), s"validBits=$validBits") - assert(result.completeRowToken == selected.map(_._2.rowToken).getOrElse(0), s"validBits=$validBits") - assert(selections.count(identity) == selected.size, s"validBits=$validBits") - assert(result.selectedExecute == selected.exists(_._1 == "execute"), s"validBits=$validBits") - assert(result.selectedReplay == selected.exists(_._1 == "replay"), s"validBits=$validBits") - assert(result.selectedService == selected.exists(_._1 == "service"), s"validBits=$validBits") - assert(result.selectedTemplate == selected.exists(_._1 == "template"), s"validBits=$validBits") - assert(result.replayBlockedByExecute == (replay.valid && execute.valid), s"validBits=$validBits") - assert(result.serviceBlockedByExecute == (service.valid && execute.valid), s"validBits=$validBits") - assert( - result.serviceBlockedByReplay == (service.valid && !execute.valid && replay.valid), - s"validBits=$validBits") - assert(result.templateBlockedByExecute == (template.valid && execute.valid), s"validBits=$validBits") - assert( - result.templateBlockedByReplay == (template.valid && !execute.valid && replay.valid), - s"validBits=$validBits") - } - } - - test("forwards row-valid and row payload only from selected row-carrying sources") { - val rowSources = Seq(executePayload, replayPayload, servicePayload, templatePayload) - - for { - selectedIndex <- rowSources.indices - rowValid <- Seq(false, true) - } { - val selectedSource = rowSources(selectedIndex).copy(valid = true, rowValid = rowValid) - val execute = if (selectedIndex == 0) selectedSource else executePayload - val replay = if (selectedIndex == 1) selectedSource else replayPayload - val service = if (selectedIndex == 2) selectedSource else servicePayload - val template = if (selectedIndex == 3) selectedSource else templatePayload - val result = ReducedRobCompletionArbiterReference( - execute, - replay, - service, - template, - templateParentSlot = template.robValue) - - assert(result.completeRobValue == selectedSource.robValue) - assert(result.completeRowValid == rowValid) - assert(result.completeRowToken == selectedSource.rowToken) - } - } - - test("service-only completion selects RID and forwards the owner trace row") { - val result = ReducedRobCompletionArbiterReference( - executePayload, - replayPayload, - servicePayload.copy(valid = true), - templatePayload, - templateParentSlot = templatePayload.robValue) - - assert(result.completeValid) - assert(result.completeRobValue == servicePayload.robValue) - assert(result.completeRowValid) - assert(result.completeRowToken == servicePayload.rowToken) - assert(result.selectedService) - assert(result.selectedSourceMask == 0x4) - assert(!result.protocolError) - } - - test("template-only completion remains a real lowest-priority row source") { - val result = ReducedRobCompletionArbiterReference( - executePayload, - replayPayload, - servicePayload, - templatePayload.copy(valid = true), - templateParentSlot = templatePayload.robValue) - - assert(result.completeValid) - assert(result.completeRobValue == templatePayload.robValue) - assert(result.completeRowValid) - assert(result.completeRowToken == templatePayload.rowToken) - assert(result.selectedTemplate) - assert(result.selectedSourceMask == 0x8) - } - - test("sanitizes every completion output while idle") { - val result = ReducedRobCompletionArbiterReference( - executePayload, - replayPayload, - servicePayload, - templatePayload, - templateParentSlot = templatePayload.robValue) - - assert(!result.completeValid) - assert(result.completeRobValue == 0) - assert(!result.completeRowValid) - assert(result.completeRowToken == 0) - assert(!result.selectedExecute) - assert(!result.selectedReplay) - assert(!result.selectedService) - assert(!result.selectedTemplate) - assert(result.selectedSourceMask == 0) - assert(!result.replayBlockedByExecute) - assert(!result.serviceBlockedByExecute) - assert(!result.serviceBlockedByReplay) - assert(!result.templateBlockedByExecute) - assert(!result.templateBlockedByReplay) - assert(!result.completionContended) - assert(!result.protocolError) - } - - test("flags same-RID and different-RID contention without issuing duplicate completions") { - val same = ReducedRobCompletionArbiterReference( - executePayload.copy(valid = true, robValue = 2), - replayPayload.copy(valid = true, robValue = 2), - servicePayload.copy(valid = true, robValue = 2), - templatePayload.copy(valid = true, robValue = 2), - templateParentSlot = 2) - assert(same.completeRobValue == 2) - assert(same.selectedExecute) - assert(same.completionContended) - assert(same.sameRobCompletionContention) - assert(!same.differentRobCompletionContention) - assert(!same.protocolError) - - val different = ReducedRobCompletionArbiterReference( - executePayload.copy(valid = false), - replayPayload.copy(valid = true, robValue = 1), - servicePayload.copy(valid = true, robValue = 3), - templatePayload.copy(valid = true, robValue = 3), - templateParentSlot = 3) - assert(different.completeRobValue == 1) - assert(different.selectedReplay) - assert(different.completionContended) - assert(!different.sameRobCompletionContention) - assert(different.differentRobCompletionContention) - assert(different.protocolError) - } - - test("invalid RID is rejected while lower-priority valid sources remain selectable") { - val serviceInvalid = ReducedRobCompletionArbiterReference( - executePayload, - replayPayload, - servicePayload.copy(valid = true, robValue = 6), - templatePayload, - templateParentSlot = templatePayload.robValue, - robEntries = 6) - assert(!serviceInvalid.completeValid) - assert(serviceInvalid.protocolError) - - val executeInvalidReplayValid = ReducedRobCompletionArbiterReference( - executePayload.copy(valid = true, robValue = 7), - replayPayload.copy(valid = true, robValue = 4), - servicePayload, - templatePayload, - templateParentSlot = templatePayload.robValue, - robEntries = 6) - assert(executeInvalidReplayValid.completeValid) - assert(executeInvalidReplayValid.selectedReplay) - assert(executeInvalidReplayValid.completeRobValue == 4) - assert(executeInvalidReplayValid.protocolError) - } - - test("rejects a valid template payload whose parent slot disagrees") { - val mismatchedTemplate = templatePayload.copy(valid = true) - - intercept[IllegalArgumentException] { - ReducedRobCompletionArbiterReference( - executePayload, - replayPayload, - servicePayload, - mismatchedTemplate, - templateParentSlot = mismatchedTemplate.robValue + 1) - } - } - - test("Chisel ReducedRobCompletionArbiter elaborates service and template source interface") { - val sv = ChiselStage.emitSystemVerilog( - new ReducedRobCompletionArbiter( - ptrWidth = 3, - traceParams = CommitTraceParams(robValueWidth = 3), - robEntries = 6)) - - assert(sv.contains("module ReducedRobCompletionArbiter")) - assert(sv.contains("io_executeCompleteValid")) - assert(sv.contains("io_replayCompleteValid")) - assert(sv.contains("io_serviceCompleteValid")) - assert(sv.contains("io_serviceCompleteRobValue")) - assert(sv.contains("io_templateCompleteValid")) - assert(sv.contains("io_templateCompleteRobValue")) - assert(sv.contains("io_templateCompleteParentSlot")) - assert(sv.contains("io_selectedExecute")) - assert(sv.contains("io_selectedReplay")) - assert(sv.contains("io_selectedService")) - assert(sv.contains("io_selectedTemplate")) - assert(sv.contains("io_selectedSourceMask")) - assert(sv.contains("io_replayBlockedByExecute")) - assert(sv.contains("io_serviceBlockedByExecute")) - assert(sv.contains("io_serviceBlockedByReplay")) - assert(sv.contains("io_templateBlockedByExecute")) - assert(sv.contains("io_templateBlockedByReplay")) - assert(sv.contains("io_completionContended")) - assert(sv.contains("io_sameRobCompletionContention")) - assert(sv.contains("io_differentRobCompletionContention")) - assert(sv.contains("io_protocolError")) - assert(!sv.contains("exactComplete")) - } - - test("Chisel behavior is combinational for service, template, priority, and invalid RID cases") { - simulate(new ReducedRobCompletionArbiterProbe) { dut => - dut.io.executeValid.poke(false.B) - dut.io.executeRobValue.poke(2.U) - dut.io.executeRowValid.poke(true.B) - dut.io.executeRowToken.poke(0x11.U) - dut.io.replayValid.poke(false.B) - dut.io.replayRobValue.poke(5.U) - dut.io.replayRowValid.poke(true.B) - dut.io.replayRowToken.poke(0x22.U) - dut.io.serviceValid.poke(true.B) - dut.io.serviceRobValue.poke(3.U) - dut.io.serviceRowValid.poke(true.B) - dut.io.serviceRowToken.poke(0x33.U) - dut.io.templateValid.poke(false.B) - dut.io.templateRobValue.poke(4.U) - dut.io.templateRowValid.poke(true.B) - dut.io.templateRowToken.poke(0x44.U) - dut.io.templateParentSlot.poke(4.U) - dut.io.completeValid.expect(true.B) - dut.io.completeRobValue.expect(3.U) - dut.io.completeRowValid.expect(true.B) - dut.io.completeRowToken.expect(0x33.U) - dut.io.selectedService.expect(true.B) - dut.io.selectedSourceMask.expect(4.U) - dut.io.protocolError.expect(false.B) - - dut.io.serviceValid.poke(false.B) - dut.io.templateValid.poke(true.B) - dut.io.completeRobValue.expect(4.U) - dut.io.completeRowValid.expect(true.B) - dut.io.completeRowToken.expect(0x44.U) - dut.io.selectedTemplate.expect(true.B) - dut.io.selectedSourceMask.expect(8.U) - - dut.io.executeValid.poke(true.B) - dut.io.replayValid.poke(true.B) - dut.io.serviceValid.poke(true.B) - dut.io.templateValid.poke(true.B) - dut.io.executeRobValue.poke(2.U) - dut.io.replayRobValue.poke(2.U) - dut.io.serviceRobValue.poke(2.U) - dut.io.templateRobValue.poke(2.U) - dut.io.templateParentSlot.poke(2.U) - dut.io.completeRobValue.expect(2.U) - dut.io.selectedExecute.expect(true.B) - dut.io.selectedSourceMask.expect(1.U) - dut.io.completionContended.expect(true.B) - dut.io.sameRobCompletionContention.expect(true.B) - dut.io.protocolError.expect(false.B) - - dut.io.executeValid.poke(false.B) - dut.io.replayValid.poke(true.B) - dut.io.serviceValid.poke(true.B) - dut.io.templateValid.poke(true.B) - dut.io.replayRobValue.poke(1.U) - dut.io.serviceRobValue.poke(3.U) - dut.io.templateRobValue.poke(3.U) - dut.io.templateParentSlot.poke(3.U) - dut.io.completeRobValue.expect(1.U) - dut.io.selectedReplay.expect(true.B) - dut.io.selectedSourceMask.expect(2.U) - dut.io.differentRobCompletionContention.expect(true.B) - dut.io.protocolError.expect(true.B) - - dut.io.replayValid.poke(false.B) - dut.io.serviceValid.poke(true.B) - dut.io.templateValid.poke(false.B) - dut.io.serviceRobValue.poke(6.U) - dut.io.completeValid.expect(false.B) - dut.io.protocolError.expect(true.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala b/chisel/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala deleted file mode 100644 index 454fc68a..00000000 --- a/chisel/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala +++ /dev/null @@ -1,596 +0,0 @@ -package linxcore.bctrl - -import circt.stage.ChiselStage -import chisel3._ -import chisel3.util.{Decoupled, Mux1H} -import linxcore.commit.CommitTraceParams -import linxcore.common._ -import linxcore.execute.ScalarIssueFabric -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.recovery.RecoveryCleanupIntent -import linxcore.rename.ScalarDecodeRenameBridge - -class TemplateHandoffProbeKey(val p: InterfaceParams) extends Bundle { - val generation = UInt(16.W) - val stid = UInt(p.threadIdWidth.W) - val bidValid = Bool() - val bidWrap = Bool() - val bidValue = UInt(p.robIndexWidth.W) - val gidValid = Bool() - val gidWrap = Bool() - val gidValue = UInt(p.robIndexWidth.W) - val ridValid = Bool() - val ridWrap = Bool() - val ridValue = UInt(p.robIndexWidth.W) - val robSlot = UInt(p.robIndexWidth.W) -} - -class TemplateAcceptedSidecarHandoffProbeIO( - val p: InterfaceParams, - val archRegs: Int, - val physTagWidth: Int, - val stidCount: Int) - extends Bundle { - val acceptValid = Input(Bool()) - val acceptOpcode = Input(UInt(p.opcodeWidth.W)) - val acceptStid = Input(UInt(p.threadIdWidth.W)) - val acceptPeId = Input(UInt(p.peIdWidth.W)) - val acceptPc = Input(UInt(p.pcWidth.W)) - val acceptRaw = Input(UInt(p.insnWidth.W)) - val acceptImm = Input(UInt(p.immWidth.W)) - val acceptRangeM = Input(UInt(p.archRegWidth.W)) - val acceptRangeN = Input(UInt(p.archRegWidth.W)) - val acceptBidValid = Input(Bool()) - val acceptBidWrap = Input(Bool()) - val acceptBidValue = Input(UInt(p.robIndexWidth.W)) - val acceptGidValid = Input(Bool()) - val acceptGidWrap = Input(Bool()) - val acceptGidValue = Input(UInt(p.robIndexWidth.W)) - val acceptRidValid = Input(Bool()) - val acceptRidWrap = Input(Bool()) - val acceptRidValue = Input(UInt(p.robIndexWidth.W)) - val acceptUid = Input(UInt(p.uopUidWidth.W)) - val acceptBlockBidValid = Input(Bool()) - val acceptBlockBid = Input(UInt(p.blockBidWidth.W)) - val robAllocReady = Input(Bool()) - - val readyMask = Input(UInt((1 << physTagWidth).W)) - val pWakeupValid = Input(Bool()) - val pWakeupTag = Input(UInt(physTagWidth.W)) - val localTReadyMask = Input(UInt(4.W)) - val localUReadyMask = Input(UInt(4.W)) - val readData = Input(Vec(3, UInt(p.immWidth.W))) - val scalarSpHeadValid = Input(Vec(stidCount, Bool())) - val scalarSpHeadBidValue = Input(Vec(stidCount, UInt(p.robIndexWidth.W))) - val scalarSpHeadRidValue = Input(Vec(stidCount, UInt(p.robIndexWidth.W))) - val scalarSpSnapshot = Input(Vec(stidCount, UInt(p.immWidth.W))) - - // Each bit flips one field after the request is built from the real issue - // payload. This is stateless fault injection, not an identity matcher. - val issueKeyFaultMask = Input(UInt(12.W)) - val parentRequestReadyOverride = Input(Bool()) - val cancelValid = Input(Bool()) - val cancelKey = Input(new TemplateHandoffProbeKey(p)) - val releaseDecodeValid = Input(Bool()) - val releaseDecodeKey = Input(new TemplateHandoffProbeKey(p)) - val releaseIssueValid = Input(Bool()) - val releaseIssueKey = Input(new TemplateHandoffProbeKey(p)) - val releaseMemoryValid = Input(Bool()) - val releaseMemoryKey = Input(new TemplateHandoffProbeKey(p)) - - val selectedTemplate = Input(Bool()) - val parentCommitValid = Input(Bool()) - val parentCommitKey = Input(new TemplateHandoffProbeKey(p)) - val storeGrant = Input(Bool()) - val recoveryValid = Input(Bool()) - val recoveryKey = Input(new TemplateHandoffProbeKey(p)) - val recoveryKillsActive = Input(Bool()) - val globalClear = Input(Bool()) - val rfReadReady = Input(Bool()) - val rfReadResponseValid = Input(Bool()) - val rfReadResponseChildIndex = Input(UInt(5.W)) - val rfReadResponsePhysTag = Input(UInt(physTagWidth.W)) - val rfReadResponseData = Input(UInt(p.immWidth.W)) - val loadReady = Input(Bool()) - val loadResponseValid = Input(Bool()) - val loadResponseChildIndex = Input(UInt(5.W)) - val loadResponseAddr = Input(UInt(p.immWidth.W)) - val loadResponseData = Input(UInt(p.immWidth.W)) - val storeReady = Input(Bool()) - val rfWriteReady = Input(Bool()) - - val bridgeAccepted = Output(Bool()) - val bridgeInReady = Output(Bool()) - val bridgeOutValid = Output(Bool()) - val bridgeTemplateSnapshotValid = Output(Bool()) - val bridgeTemplateSnapshotGeneration = Output(UInt(16.W)) - val bridgeTemplateSmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - val bridgeTemplateCmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - val sidecarValid = Output(Bool()) - val sidecarReady = Output(Bool()) - val sidecarFire = Output(Bool()) - val sidecarGeneration = Output(UInt(16.W)) - val sidecarStid = Output(UInt(p.threadIdWidth.W)) - val sidecarRaw = Output(UInt(p.insnWidth.W)) - val sidecarRangeM = Output(UInt(p.archRegWidth.W)) - val sidecarRangeN = Output(UInt(p.archRegWidth.W)) - val sidecarSrc0Imm = Output(UInt(p.immWidth.W)) - val sidecarSmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - val sidecarCmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - - val issueInputReady = Output(Bool()) - val issueValid = Output(Bool()) - val issueReady = Output(Bool()) - val issueFire = Output(Bool()) - val issuedTemplateGenerationValid = Output(Bool()) - val issuedTemplateGeneration = Output(UInt(16.W)) - val issuedStid = Output(UInt(p.threadIdWidth.W)) - val issuedRaw = Output(UInt(p.insnWidth.W)) - val issuedBidValue = Output(UInt(p.robIndexWidth.W)) - val issuedGidValue = Output(UInt(p.robIndexWidth.W)) - val issuedRidValue = Output(UInt(p.robIndexWidth.W)) - val issuedSrcData0 = Output(UInt(p.immWidth.W)) - val parentRequestValid = Output(Bool()) - val parentRequestReady = Output(Bool()) - val parentTransfer = Output(Bool()) - val sidecarOccupiedMask = Output(UInt(stidCount.W)) - val sidecarDecodeFenceMask = Output(UInt(stidCount.W)) - val sidecarIssueFenceMask = Output(UInt(stidCount.W)) - val sidecarMemoryFenceMask = Output(UInt(stidCount.W)) - val enqueueCount = Output(UInt(32.W)) - val transferCount = Output(UInt(32.W)) - val mismatchDropCount = Output(UInt(32.W)) - val staleGenerationDropCount = Output(UInt(32.W)) - - val sequencerActive = Output(Bool()) - val activeGeneration = Output(UInt(16.W)) - val activeStid = Output(UInt(p.threadIdWidth.W)) - val activePeId = Output(UInt(p.peIdWidth.W)) - val activePc = Output(UInt(p.pcWidth.W)) - val activeOpcode = Output(UInt(p.opcodeWidth.W)) - val activeRaw = Output(UInt(p.insnWidth.W)) - val activeBidValid = Output(Bool()) - val activeBidWrap = Output(Bool()) - val activeBidValue = Output(UInt(p.robIndexWidth.W)) - val activeGidValid = Output(Bool()) - val activeGidWrap = Output(Bool()) - val activeGidValue = Output(UInt(p.robIndexWidth.W)) - val activeRidValid = Output(Bool()) - val activeRidWrap = Output(Bool()) - val activeRidValue = Output(UInt(p.robIndexWidth.W)) - val activeRobSlot = Output(UInt(p.robIndexWidth.W)) - val activeBlockBidValid = Output(Bool()) - val activeBlockBid = Output(UInt(p.blockBidWidth.W)) - val activeCommitBid = Output(UInt(32.W)) - val activeCommitGid = Output(UInt(32.W)) - val activeCommitRid = Output(UInt(32.W)) - val activeSmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - val activeCmap = Output(Vec(archRegs, UInt(physTagWidth.W))) - val activeOldSp = Output(UInt(p.immWidth.W)) - val activeSrcData = Output(Vec(3, UInt(p.immWidth.W))) - val rfReadRequestValid = Output(Bool()) - val rfReadRequestChildIndex = Output(UInt(5.W)) - val rfReadRequestArchReg = Output(UInt(p.archRegWidth.W)) - val rfReadRequestPhysTag = Output(UInt(physTagWidth.W)) - val loadRequestValid = Output(Bool()) - val loadRequestChildIndex = Output(UInt(5.W)) - val loadRequestArchReg = Output(UInt(p.archRegWidth.W)) - val loadRequestAddr = Output(UInt(p.immWidth.W)) - val decodeFence = Output(Bool()) - val issueFence = Output(Bool()) - val memoryFence = Output(Bool()) - val completionValid = Output(Bool()) - val completionResult = Output(UInt(p.immWidth.W)) - val completionNewSp = Output(UInt(p.immWidth.W)) - val terminal = Output(Bool()) - val selfRestartObserved = Output(Bool()) - val cancelObserved = Output(Bool()) -} - -class TemplateAcceptedSidecarHandoffProbe extends Module { - private val p = InterfaceParams() - private val traceParams = CommitTraceParams() - private val archRegs = 24 - private val physTagWidth = p.physRegWidth - private val stidCount = 2 - - val io = IO(new TemplateAcceptedSidecarHandoffProbeIO(p, archRegs, physTagWidth, stidCount)) - - private def isTemplate(opcode: UInt): Bool = - opcode === FrontendOpcodeDecodeTable.OP_FENTRY.U || - opcode === FrontendOpcodeDecodeTable.OP_FEXIT.U || - opcode === FrontendOpcodeDecodeTable.OP_FRET_RA.U || - opcode === FrontendOpcodeDecodeTable.OP_FRET_STK.U - - private def assignRobId( - dst: linxcore.rob.ROBID, - valid: Bool, - wrap: Bool, - value: UInt): Unit = { - dst.valid := valid - dst.wrap := wrap - dst.value := value - } - - private def assignKey( - dst: TemplateParentIdentity, - key: TemplateHandoffProbeKey, - template: TemplateParentIdentity): Unit = { - dst := template - dst.generation := key.generation - dst.stid := key.stid - assignRobId(dst.bid, key.bidValid, key.bidWrap, key.bidValue) - assignRobId(dst.gid, key.gidValid, key.gidWrap, key.gidValue) - assignRobId(dst.rid, key.ridValid, key.ridWrap, key.ridValue) - dst.robSlot := key.robSlot - } - - val bridge = Module(new ScalarDecodeRenameBridge( - p = p, - traceParams = traceParams, - scalarArchRegs = archRegs, - scalarStidCount = stidCount - )) - val issue = Module(new ScalarIssueFabric(p = p, depth = 8, bankCount = 2, stidCount = stidCount)) - val sidecar = Module(new TemplateRenameSidecarTable(p, archRegs, physTagWidth, stidCount)) - val sequencer = Module(new BlockControlTemplateSequencer(p, archRegs, physTagWidth)) - - val decoded = Wire(new DecodedUop(p)) - decoded := 0.U.asTypeOf(decoded) - decoded.valid := io.acceptValid - decoded.peId := io.acceptPeId - decoded.threadId := io.acceptStid - decoded.pc := io.acceptPc - decoded.opcode := io.acceptOpcode - decoded.uopType := 0.U - decoded.imm := io.acceptImm - decoded.immValid := true.B - decoded.src(0).valid := true.B - decoded.src(0).operandClass := OperandClass.P - decoded.src(0).archTag := io.acceptRangeM - decoded.src(0).relTag := io.acceptRangeM - decoded.src(1).valid := true.B - decoded.src(1).operandClass := OperandClass.P - decoded.src(1).archTag := io.acceptRangeN - decoded.src(1).relTag := io.acceptRangeN - decoded.src(2).valid := true.B - decoded.src(2).operandClass := OperandClass.P - decoded.src(2).archTag := 2.U - decoded.src(2).relTag := 2.U - decoded.dst(0).valid := false.B - decoded.dst(0).kind := DestinationKind.Gpr - assignRobId(decoded.bid, io.acceptBidValid, io.acceptBidWrap, io.acceptBidValue) - assignRobId(decoded.gid, io.acceptGidValid, io.acceptGidWrap, io.acceptGidValue) - assignRobId(decoded.rid, io.acceptRidValid, io.acceptRidWrap, io.acceptRidValue) - decoded.insnLen := 4.U - decoded.insnRaw := io.acceptRaw - decoded.blockBidValid := io.acceptBlockBidValid - decoded.blockBid := io.acceptBlockBid - decoded.uid.uid := io.acceptUid - - bridge.io.in := decoded - bridge.io.activeStid := io.acceptStid - val acceptedTemplateSidecar = Wire(Decoupled(new TemplateRenameSidecar(p, archRegs, physTagWidth))) - bridge.io.outReady := issue.io.inReady && Mux(isTemplate(io.acceptOpcode), acceptedTemplateSidecar.ready, true.B) - bridge.io.robAllocReady := io.robAllocReady - bridge.io.checkpointValid := false.B - bridge.io.checkpointBid := 0.U.asTypeOf(bridge.io.checkpointBid) - bridge.io.checkpointStid := 0.U - bridge.io.commitValid := false.B - bridge.io.commitBid := 0.U.asTypeOf(bridge.io.commitBid) - bridge.io.commitBlockBid := 0.U - bridge.io.commitStid := 0.U - bridge.io.cleanup := 0.U.asTypeOf(new RecoveryCleanupIntent(p.robEntries)) - bridge.io.cleanupOrderValid := false.B - bridge.io.cleanupOrder := 0.U - - acceptedTemplateSidecar.valid := bridge.io.templateSnapshotValid - acceptedTemplateSidecar.bits := 0.U.asTypeOf(acceptedTemplateSidecar.bits) - acceptedTemplateSidecar.bits.identity.generation := bridge.io.templateSnapshotGeneration - acceptedTemplateSidecar.bits.identity.stid := io.acceptStid - acceptedTemplateSidecar.bits.identity.peId := io.acceptPeId - acceptedTemplateSidecar.bits.identity.pc := io.acceptPc - acceptedTemplateSidecar.bits.identity.raw := io.acceptRaw - acceptedTemplateSidecar.bits.identity.opcode := io.acceptOpcode - acceptedTemplateSidecar.bits.identity.bid := decoded.bid - acceptedTemplateSidecar.bits.identity.gid := decoded.gid - acceptedTemplateSidecar.bits.identity.rid := decoded.rid - acceptedTemplateSidecar.bits.identity.robSlot := decoded.rid.value - acceptedTemplateSidecar.bits.identity.blockBidValid := io.acceptBlockBidValid - acceptedTemplateSidecar.bits.identity.blockBid := io.acceptBlockBid - acceptedTemplateSidecar.bits.identity.commitIdentityBid := io.acceptBidValue - acceptedTemplateSidecar.bits.identity.commitIdentityGid := io.acceptGidValue - acceptedTemplateSidecar.bits.identity.commitIdentityRid := io.acceptRidValue - acceptedTemplateSidecar.bits.src0Imm := io.acceptImm - acceptedTemplateSidecar.bits.rangeM := io.acceptRangeM - acceptedTemplateSidecar.bits.rangeN := io.acceptRangeN - acceptedTemplateSidecar.bits.map.smap := bridge.io.templateSmapSnapshot - acceptedTemplateSidecar.bits.map.cmap := bridge.io.templateCmapSnapshot - sidecar.io.enqueue <> acceptedTemplateSidecar - - issue.io.inValid := bridge.io.outValid - issue.io.in := bridge.io.out - issue.io.flushValid := false.B - issue.io.releaseValid := false.B - issue.io.releaseBid := 0.U.asTypeOf(issue.io.releaseBid) - issue.io.releaseRid := 0.U.asTypeOf(issue.io.releaseRid) - issue.io.releaseStid := 0.U - issue.io.secondaryReleaseValid := false.B - issue.io.secondaryReleaseBid := 0.U.asTypeOf(issue.io.secondaryReleaseBid) - issue.io.secondaryReleaseRid := 0.U.asTypeOf(issue.io.secondaryReleaseRid) - issue.io.secondaryReleaseStid := 0.U - issue.io.tertiaryReleaseValid := false.B - issue.io.tertiaryReleaseBid := 0.U.asTypeOf(issue.io.tertiaryReleaseBid) - issue.io.tertiaryReleaseRid := 0.U.asTypeOf(issue.io.tertiaryReleaseRid) - issue.io.tertiaryReleaseStid := 0.U - issue.io.externalControlFenceValid := false.B - issue.io.externalControlFenceBid := 0.U.asTypeOf(issue.io.externalControlFenceBid) - issue.io.externalControlFenceRid := 0.U.asTypeOf(issue.io.externalControlFenceRid) - issue.io.externalControlFenceStid := 0.U - for (stid <- 0 until stidCount) { - issue.io.scalarSpHeadValidByStid(stid) := io.scalarSpHeadValid(stid) - assignRobId( - issue.io.scalarSpHeadBidByStid(stid), - true.B, - io.acceptBidWrap, - io.scalarSpHeadBidValue(stid) - ) - assignRobId( - issue.io.scalarSpHeadRidByStid(stid), - true.B, - io.acceptRidWrap, - io.scalarSpHeadRidValue(stid) - ) - issue.io.scalarSpSnapshotByStid(stid) := io.scalarSpSnapshot(stid) - } - issue.io.readyMask := io.readyMask - issue.io.pWakeupValid := io.pWakeupValid - issue.io.pWakeupTag := io.pWakeupTag - issue.io.localTReadyMask := io.localTReadyMask - issue.io.localUReadyMask := io.localUReadyMask - issue.io.readData := io.readData - - val issued = issue.io.issueUop - val issuedTemplate = isTemplate(issued.opcode) - val acceptedGenerationValidByStid = RegInit(VecInit(Seq.fill(stidCount)(false.B))) - val acceptedGenerationByStid = Reg(Vec(stidCount, UInt(16.W))) - val issuedStidMatches = VecInit((0 until stidCount).map(idx => issued.threadId === idx.U(p.threadIdWidth.W))) - val issuedStidInRange = issuedStidMatches.asUInt.orR - val issueTemplateGenerationValid = - issuedTemplate && issuedStidInRange && Mux1H(issuedStidMatches, acceptedGenerationValidByStid) - val issueTemplateGeneration = Mux1H(issuedStidMatches, acceptedGenerationByStid) - - when(acceptedTemplateSidecar.fire) { - for (idx <- 0 until stidCount) { - when(acceptedTemplateSidecar.bits.identity.stid === idx.U(p.threadIdWidth.W)) { - acceptedGenerationValidByStid(idx) := true.B - acceptedGenerationByStid(idx) := acceptedTemplateSidecar.bits.identity.generation - } - } - } - when(io.cancelValid) { - for (idx <- 0 until stidCount) { - when(io.cancelKey.stid === idx.U(p.threadIdWidth.W)) { - acceptedGenerationValidByStid(idx) := false.B - } - } - } - when(io.globalClear) { - acceptedGenerationValidByStid := VecInit(Seq.fill(stidCount)(false.B)) - } - - val issueRequest = Wire(new TemplateIssueRequest(p)) - issueRequest := 0.U.asTypeOf(issueRequest) - issueRequest.identity.generation := issueTemplateGeneration - issueRequest.identity.stid := issued.threadId - issueRequest.identity.peId := issued.peId - issueRequest.identity.pc := issued.pc - issueRequest.identity.raw := issued.insnRaw - issueRequest.identity.opcode := issued.opcode - issueRequest.identity.bid := issued.bid - issueRequest.identity.gid := issued.gid - issueRequest.identity.rid := issued.rid - issueRequest.identity.robSlot := issued.rid.value - issueRequest.identity.blockBidValid := issued.blockBidValid - issueRequest.identity.blockBid := issued.blockBid - issueRequest.identity.commitIdentityBid := issued.bid.value - issueRequest.identity.commitIdentityGid := issued.gid.value - issueRequest.identity.commitIdentityRid := issued.rid.value - issueRequest.oldSp := issue.io.scalarSpIssueSnapshot - issueRequest.srcData0 := issue.io.issueSrcData(0) - issueRequest.srcData1 := issue.io.issueSrcData(1) - issueRequest.srcData2 := issue.io.issueSrcData(2) - - when(io.issueKeyFaultMask(0)) { - issueRequest.identity.stid := issued.threadId ^ 1.U - } - when(io.issueKeyFaultMask(1)) { - issueRequest.identity.bid.valid := !issued.bid.valid - } - when(io.issueKeyFaultMask(2)) { - issueRequest.identity.bid.wrap := !issued.bid.wrap - } - when(io.issueKeyFaultMask(3)) { - issueRequest.identity.bid.value := issued.bid.value ^ 1.U - } - when(io.issueKeyFaultMask(4)) { - issueRequest.identity.gid.valid := !issued.gid.valid - } - when(io.issueKeyFaultMask(5)) { - issueRequest.identity.gid.wrap := !issued.gid.wrap - } - when(io.issueKeyFaultMask(6)) { - issueRequest.identity.gid.value := issued.gid.value ^ 1.U - } - when(io.issueKeyFaultMask(7)) { - issueRequest.identity.rid.valid := !issued.rid.valid - } - when(io.issueKeyFaultMask(8)) { - issueRequest.identity.rid.wrap := !issued.rid.wrap - } - when(io.issueKeyFaultMask(9)) { - issueRequest.identity.rid.value := issued.rid.value ^ 1.U - } - when(io.issueKeyFaultMask(10)) { - issueRequest.identity.robSlot := issued.rid.value ^ 1.U - } - when(io.issueKeyFaultMask(11)) { - issueRequest.identity.generation := issueTemplateGeneration ^ 1.U - } - - sidecar.io.issue.valid := issue.io.issueValid && issuedTemplate && issueTemplateGenerationValid - sidecar.io.issue.bits := issueRequest - issue.io.issueReady := - Mux(issuedTemplate, sidecar.io.issue.ready && issueTemplateGenerationValid, true.B) - - sidecar.io.cancel.valid := io.cancelValid - assignKey(sidecar.io.cancel.bits, io.cancelKey, issueRequest.identity) - sidecar.io.releaseDecodeFence.valid := io.releaseDecodeValid - assignKey(sidecar.io.releaseDecodeFence.bits, io.releaseDecodeKey, issueRequest.identity) - sidecar.io.releaseIssueFence.valid := io.releaseIssueValid - assignKey(sidecar.io.releaseIssueFence.bits, io.releaseIssueKey, issueRequest.identity) - sidecar.io.releaseMemoryFence.valid := io.releaseMemoryValid - assignKey(sidecar.io.releaseMemoryFence.bits, io.releaseMemoryKey, issueRequest.identity) - sidecar.io.globalClear := io.globalClear - - // Preserve a point-to-point Decoupled transfer while allowing the testbench - // to apply downstream backpressure. Neither endpoint can fire alone. - sequencer.io.parentRequest.valid := - sidecar.io.parentRequest.valid && io.parentRequestReadyOverride - sequencer.io.parentRequest.bits := sidecar.io.parentRequest.bits - sidecar.io.parentRequest.ready := - sequencer.io.parentRequest.ready && io.parentRequestReadyOverride - - sequencer.io.rfReadRequest.ready := io.rfReadReady - sequencer.io.rfReadResponse.valid := io.rfReadResponseValid - sequencer.io.rfReadResponse.bits := 0.U.asTypeOf(sequencer.io.rfReadResponse.bits) - sequencer.io.rfReadResponse.bits.parent := sequencer.io.activeIdentity - sequencer.io.rfReadResponse.bits.childIndex := io.rfReadResponseChildIndex - sequencer.io.rfReadResponse.bits.physTag := io.rfReadResponsePhysTag - sequencer.io.rfReadResponse.bits.data := io.rfReadResponseData - sequencer.io.loadRequest.ready := io.loadReady - sequencer.io.loadResponse.valid := io.loadResponseValid - sequencer.io.loadResponse.bits := 0.U.asTypeOf(sequencer.io.loadResponse.bits) - sequencer.io.loadResponse.bits.parent := sequencer.io.activeIdentity - sequencer.io.loadResponse.bits.childIndex := io.loadResponseChildIndex - sequencer.io.loadResponse.bits.addr := io.loadResponseAddr - sequencer.io.loadResponse.bits.data := io.loadResponseData - sequencer.io.selectedTemplate := io.selectedTemplate - sequencer.io.parentCommit.valid := io.parentCommitValid - assignKey(sequencer.io.parentCommit.bits, io.parentCommitKey, sequencer.io.activeIdentity) - sequencer.io.storeGrant := io.storeGrant - sequencer.io.recovery.valid := io.recoveryValid - assignKey(sequencer.io.recovery.bits, io.recoveryKey, sequencer.io.activeIdentity) - sequencer.io.recoveryKillsActive := io.recoveryKillsActive - sequencer.io.globalClear := io.globalClear - sequencer.io.storeRequest.ready := io.storeReady - sequencer.io.rfWriteRequest.ready := io.rfWriteReady - - when(bridge.io.accepted && isTemplate(io.acceptOpcode)) { - assert(acceptedTemplateSidecar.fire) - } - when(io.acceptValid && isTemplate(io.acceptOpcode) && !acceptedTemplateSidecar.ready) { - assert(!bridge.io.accepted) - } - assert(sidecar.io.parentRequest.fire === sequencer.io.parentRequest.fire) - - io.bridgeAccepted := bridge.io.accepted - io.bridgeInReady := bridge.io.inReady - io.bridgeOutValid := bridge.io.outValid - io.bridgeTemplateSnapshotValid := bridge.io.templateSnapshotValid - io.bridgeTemplateSnapshotGeneration := bridge.io.templateSnapshotGeneration - io.bridgeTemplateSmap := bridge.io.templateSmapSnapshot - io.bridgeTemplateCmap := bridge.io.templateCmapSnapshot - io.sidecarValid := acceptedTemplateSidecar.valid - io.sidecarReady := acceptedTemplateSidecar.ready - io.sidecarFire := acceptedTemplateSidecar.fire - io.sidecarGeneration := acceptedTemplateSidecar.bits.identity.generation - io.sidecarStid := acceptedTemplateSidecar.bits.identity.stid - io.sidecarRaw := acceptedTemplateSidecar.bits.identity.raw - io.sidecarRangeM := acceptedTemplateSidecar.bits.rangeM - io.sidecarRangeN := acceptedTemplateSidecar.bits.rangeN - io.sidecarSrc0Imm := acceptedTemplateSidecar.bits.src0Imm - io.sidecarSmap := acceptedTemplateSidecar.bits.map.smap - io.sidecarCmap := acceptedTemplateSidecar.bits.map.cmap - - io.issueInputReady := issue.io.inReady - io.issueValid := issue.io.issueValid - io.issueReady := issue.io.issueReady - io.issueFire := issue.io.issueFire - io.issuedTemplateGenerationValid := issueTemplateGenerationValid - io.issuedTemplateGeneration := issueTemplateGeneration - io.issuedStid := issued.threadId - io.issuedRaw := issued.insnRaw - io.issuedBidValue := issued.bid.value - io.issuedGidValue := issued.gid.value - io.issuedRidValue := issued.rid.value - io.issuedSrcData0 := issue.io.issueSrcData(0) - io.parentRequestValid := sidecar.io.parentRequest.valid - io.parentRequestReady := sidecar.io.parentRequest.ready - io.parentTransfer := sidecar.io.parentRequest.fire - io.sidecarOccupiedMask := sidecar.io.occupiedMask - io.sidecarDecodeFenceMask := sidecar.io.decodeFenceMask - io.sidecarIssueFenceMask := sidecar.io.issueFenceMask - io.sidecarMemoryFenceMask := sidecar.io.memoryFenceMask - io.enqueueCount := sidecar.io.enqueueCount - io.transferCount := sidecar.io.transferCount - io.mismatchDropCount := sidecar.io.mismatchDropCount - io.staleGenerationDropCount := sidecar.io.staleGenerationDropCount - - val activeIdentity = sequencer.io.activeIdentity - io.sequencerActive := sequencer.io.activeValid - io.activeGeneration := activeIdentity.generation - io.activeStid := activeIdentity.stid - io.activePeId := activeIdentity.peId - io.activePc := activeIdentity.pc - io.activeOpcode := activeIdentity.opcode - io.activeRaw := activeIdentity.raw - io.activeBidValid := activeIdentity.bid.valid - io.activeBidWrap := activeIdentity.bid.wrap - io.activeBidValue := activeIdentity.bid.value - io.activeGidValid := activeIdentity.gid.valid - io.activeGidWrap := activeIdentity.gid.wrap - io.activeGidValue := activeIdentity.gid.value - io.activeRidValid := activeIdentity.rid.valid - io.activeRidWrap := activeIdentity.rid.wrap - io.activeRidValue := activeIdentity.rid.value - io.activeRobSlot := activeIdentity.robSlot - io.activeBlockBidValid := activeIdentity.blockBidValid - io.activeBlockBid := activeIdentity.blockBid - io.activeCommitBid := activeIdentity.commitIdentityBid - io.activeCommitGid := activeIdentity.commitIdentityGid - io.activeCommitRid := activeIdentity.commitIdentityRid - io.activeSmap := sequencer.io.activeMap.smap - io.activeCmap := sequencer.io.activeMap.cmap - io.activeOldSp := sequencer.io.activeOldSp - io.activeSrcData := sequencer.io.activeSrcData - io.rfReadRequestValid := sequencer.io.rfReadRequest.valid - io.rfReadRequestChildIndex := sequencer.io.rfReadRequest.bits.childIndex - io.rfReadRequestArchReg := sequencer.io.rfReadRequest.bits.archReg - io.rfReadRequestPhysTag := sequencer.io.rfReadRequest.bits.physTag - io.loadRequestValid := sequencer.io.loadRequest.valid - io.loadRequestChildIndex := sequencer.io.loadRequest.bits.childIndex - io.loadRequestArchReg := sequencer.io.loadRequest.bits.archReg - io.loadRequestAddr := sequencer.io.loadRequest.bits.addr - io.decodeFence := sequencer.io.decodeFence - io.issueFence := sequencer.io.issueFence - io.memoryFence := sequencer.io.memoryFence - io.completionValid := sequencer.io.completion.valid - io.completionResult := sequencer.io.completion.bits.result - io.completionNewSp := sequencer.io.completion.bits.newSp - io.terminal := sequencer.io.terminal - io.selfRestartObserved := sequencer.io.selfRestartObserved - io.cancelObserved := sequencer.io.cancelObserved -} - -object EmitTemplateAcceptedSidecarHandoffProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/bctrl-template-accepted-sidecar-handoff-probe") - - ChiselStage.emitSystemVerilogFile( - new TemplateAcceptedSidecarHandoffProbe, - Array("--target-dir", targetDir), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") - ) -} diff --git a/chisel/src/test/scala/linxcore/ctu/CTUSpec.scala b/chisel/src/test/scala/linxcore/ctu/CTUSpec.scala new file mode 100644 index 00000000..09bdcd51 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ctu/CTUSpec.scala @@ -0,0 +1,372 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import _root_.circt.stage.ChiselStage +import linxcore.common.{TemplateForm, TemplateRowKind} +import linxcore.params.{CoreParams, ParamProfiles, SimulationParamProfiles} +import linxcore.top.interface.{FrontEndOpKind, RecoveryCause, RecoveryPhase} +import org.scalatest.funsuite.AnyFunSuite + +class CTUSpec extends AnyFunSuite with ChiselSim { + private def clear(dut: CTU): Unit = { + dut.io.fromIfu.valid.poke(false.B) + dut.io.fromIfu.bits.poke(0.U.asTypeOf(dut.io.fromIfu.bits)) + dut.io.toOoo.ready.poke(false.B) + dut.io.trace.ready.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def macroInstruction(base: BigInt, m: Int, n: Int): BigInt = + base | (BigInt(m) << 15) | (BigInt(n) << 20) + + private def enqueue( + dut: CTU, + instructions: Seq[(BigInt, Int)], + firstId: Int = 1, + stid: Int = 0, + epoch: Int = 1): Unit = { + dut.io.fromIfu.bits.poke(0.U.asTypeOf(dut.io.fromIfu.bits)) + dut.io.fromIfu.bits.count.poke(instructions.size.U) + instructions.zipWithIndex.foreach { case ((raw, length), lane) => + val entry = dut.io.fromIfu.bits.entries(lane) + entry.identity.peId.poke(1.U) + entry.identity.stid.poke(stid.U) + entry.identity.instructionId.poke((firstId + lane).U) + entry.identity.epoch.poke(epoch.U) + entry.pc.poke((0x1000 + lane * 8).U) + entry.instruction.poke(raw.U) + entry.lengthBytes.poke(length.U) + entry.prediction.valid.poke(true.B) + entry.prediction.transactionId.poke((100 + lane).U) + entry.prediction.epoch.poke(epoch.U) + } + dut.io.fromIfu.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromIfu.ready.peek().litToBoolean && cycles < 16) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 16, "CTU input did not become ready") + dut.io.fromIfu.ready.expect(true.B) + dut.clock.step() + dut.io.fromIfu.valid.poke(false.B) + } + + private def waitForOutput(dut: CTU): Unit = { + var cycles = 0 + while (!dut.io.toOoo.valid.peek().litToBoolean && cycles < 16) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 16, "CTU output did not become valid") + } + + private def drainIds(dut: CTU, count: Int): Seq[BigInt] = { + val result = scala.collection.mutable.ArrayBuffer.empty[BigInt] + dut.io.toOoo.ready.poke(true.B) + while (result.size < count) { + waitForOutput(dut) + val lanes = dut.io.toOoo.bits.count.peek().litValue.toInt + (0 until lanes).foreach { lane => + result += dut.io.toOoo.bits.entries(lane) + .parent.identity.instructionId.peek().litValue + } + dut.clock.step() + } + result.toSeq + } + + test("passes an ordinary width-wide packet without changing identity or prediction") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + enqueue(dut, Seq( + BigInt("0005", 16) -> 2, + BigInt("0009", 16) -> 2, + BigInt("0011", 16) -> 2, + BigInt("0015", 16) -> 2)) + + waitForOutput(dut) + dut.io.toOoo.valid.expect(true.B) + dut.io.toOoo.bits.count.expect(4.U) + (0 until 4).foreach { lane => + dut.io.toOoo.bits.entries(lane).kind.expect(FrontEndOpKind.Encoded64) + dut.io.toOoo.bits.entries(lane).parent.identity.instructionId + .expect((lane + 1).U) + dut.io.toOoo.bits.entries(lane).parent.prediction.transactionId + .expect((100 + lane).U) + } + } + } + + test("expands FENTRY into the generated row recipe and spans output packets") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + val raw = macroInstruction(base = 0x41, m = 2, n = 7) | + (BigInt(8) << 25) // frameImmediate = 8 * 8 = 64 bytes + enqueue(dut, Seq(raw -> 4), firstId = 20) + dut.io.toOoo.ready.poke(true.B) + + val kinds = scala.collection.mutable.ArrayBuffer.empty[BigInt] + val registers = scala.collection.mutable.ArrayBuffer.empty[BigInt] + val immediates = scala.collection.mutable.ArrayBuffer.empty[BigInt] + while (kinds.size < 9) { + waitForOutput(dut) + val lanes = dut.io.toOoo.bits.count.peek().litValue.toInt + (0 until lanes).foreach { lane => + val op = dut.io.toOoo.bits.entries(lane) + op.kind.expect(FrontEndOpKind.TemplateUop) + op.parent.identity.instructionId.expect(20.U) + op.templateOrdinal.expect(kinds.size.U) + op.templateCount.expect(9.U) + kinds += op.templateOpcode.peek().litValue + registers += op.templateRegister.peek().litValue + immediates += op.templateImmediate.peek().litValue + } + dut.clock.step() + } + + assert(kinds.head == TemplateRowKind.VFORM.asUInt.litValue) + assert(kinds(1) == TemplateRowKind.SP_SUB.asUInt.litValue) + assert(kinds.slice(2, 8).forall(_ == TemplateRowKind.STORE.asUInt.litValue)) + assert(immediates(1) == 64) + assert(registers.slice(2, 8) == Seq(2, 3, 4, 5, 6, 7)) + assert(immediates.slice(2, 8) == Seq(56, 48, 40, 32, 24, 16)) + assert(kinds.last == TemplateRowKind.FINAL.asUInt.litValue) + } + } + + test("expands FEXIT and never lets a younger packet cross the template parent") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + val fexit = macroInstruction(base = 0x1041, m = 4, n = 6) + enqueue(dut, Seq(BigInt("0005", 16) -> 2, fexit -> 4), firstId = 30) + val first = drainIds(dut, 1) + assert(first == Seq(30)) + + val template = drainIds(dut, 6) + assert(template.forall(_ == 31)) + + enqueue(dut, Seq(BigInt("0009", 16) -> 2), firstId = 40) + assert(drainIds(dut, 1) == Seq(40)) + } + } + + test("uses the complete return-template row counts and rejects malformed ranges") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + val fretRa = macroInstruction(base = 0x2041, m = 2, n = 3) + val fretStk = macroInstruction(base = 0x3041, m = 2, n = 3) + enqueue(dut, Seq(fretRa -> 4), firstId = 80) + dut.io.toOoo.ready.poke(true.B) + waitForOutput(dut) + dut.io.toOoo.bits.entries(0).templateCount.expect(7.U) + assert(drainIds(dut, 7).forall(_ == 80)) + + enqueue(dut, Seq(fretStk -> 4), firstId = 81) + waitForOutput(dut) + dut.io.toOoo.bits.entries(0).templateCount.expect(8.U) + assert(drainIds(dut, 8).forall(_ == 81)) + + val malformed = macroInstruction(base = 0x41, m = 0, n = 3) + enqueue(dut, Seq(malformed -> 4), firstId = 82) + waitForOutput(dut) + dut.io.toOoo.bits.count.expect(1.U) + dut.io.toOoo.bits.entries(0).kind.expect(FrontEndOpKind.Encoded64) + dut.io.toOoo.bits.entries(0).parent.identity.instructionId.expect(82.U) + } + } + + test("W2 W4 W6 W8 simulation profiles execute every public template form") { + Seq(2, 4, 6, 8).foreach { width => + simulate(new CTU(SimulationParamProfiles.forWidth(width))) { dut => + clear(dut) + val forms = Seq( + macroInstruction(0x41, 2, 3), + macroInstruction(0x1041, 2, 3), + macroInstruction(0x2041, 2, 3), + macroInstruction(0x3041, 2, 3)) + forms.zipWithIndex.foreach { case (raw, index) => + val instructionId = 100 + index + enqueue(dut, Seq(raw -> 4), firstId = instructionId) + waitForOutput(dut) + dut.io.toOoo.bits.entries(0).kind.expect(FrontEndOpKind.TemplateUop) + val rows = dut.io.toOoo.bits.entries(0).templateCount + .peek().litValue.toInt + assert(rows > 2, s"W$width template $index was truncated to $rows rows") + assert(drainIds(dut, rows).forall(_ == instructionId)) + } + } + } + } + + test("holds buffered output stable while OOO is backpressured") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + enqueue(dut, Seq(BigInt("0005", 16) -> 2), firstId = 50) + waitForOutput(dut) + dut.io.toOoo.valid.expect(true.B) + val heldCount = dut.io.toOoo.bits.count.peek().litValue + val heldId = dut.io.toOoo.bits.entries(0) + .parent.identity.instructionId.peek().litValue + val heldInstruction = dut.io.toOoo.bits.entries(0) + .parent.instruction.peek().litValue + dut.clock.step(4) + dut.io.toOoo.bits.count.expect(heldCount.U) + dut.io.toOoo.bits.entries(0).parent.identity.instructionId + .expect(heldId.U) + dut.io.toOoo.bits.entries(0).parent.instruction + .expect(heldInstruction.U) + dut.io.fromIfu.ready.expect(true.B) + } + } + + test("prepare is non-mutating and apply prunes only the target STID") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + enqueue(dut, Seq(BigInt("0005", 16) -> 2), firstId = 60, stid = 0) + enqueue(dut, Seq(BigInt("0009", 16) -> 2), firstId = 70, stid = 1) + + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(99.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.bits.newEpoch.poke(2.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.bits.transactionId.expect(99.U) + dut.io.toOoo.valid.expect(false.B) + + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.transactionId.poke(99.U) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.apply.bits.trigger.stid.poke(0.U) + dut.io.recovery.apply.bits.newEpoch.poke(2.U) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + waitForOutput(dut) + dut.io.toOoo.valid.expect(true.B) + dut.io.toOoo.bits.entries(0).parent.identity.instructionId.expect(70.U) + } + } + + test("a matching recovery abort releases the fence without changing work") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + enqueue(dut, Seq(BigInt("0005", 16) -> 2), firstId = 75) + waitForOutput(dut) + + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(101.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Debug) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.bits.newEpoch.poke(4.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.toOoo.valid.expect(false.B) + + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.recovery.abort.bits.transactionId.poke(101.U) + dut.io.recovery.abort.bits.phase.poke(RecoveryPhase.Abort) + dut.io.recovery.abort.bits.cause.poke(RecoveryCause.Debug) + dut.io.recovery.abort.bits.trigger.stid.poke(0.U) + dut.io.recovery.abort.bits.newEpoch.poke(4.U) + dut.io.recovery.abort.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + + waitForOutput(dut) + dut.io.toOoo.bits.entries(0).parent.identity.instructionId.expect(75.U) + } + } + + test("retains exactly one template trace while its consumer is stalled") { + simulate(new CTU(ParamProfiles.W4)) { dut => + clear(dut) + dut.io.trace.ready.poke(false.B) + val fentry = macroInstruction(base = 0x41, m = 2, n = 3) + enqueue(dut, Seq(fentry -> 4), firstId = 90) + waitForOutput(dut) + + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.count.expect(1.U) + dut.io.trace.bits.entries(0).instruction.instructionId.expect(90.U) + dut.io.trace.bits.entries(0).payload.expect(5.U) + dut.clock.step(3) + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.entries(0).instruction.instructionId.expect(90.U) + + dut.io.trace.ready.poke(true.B) + dut.clock.step() + dut.io.trace.valid.expect(false.B) + } + } + + test("packetizes an ordinary full-width prefix at W2 W4 W6 and W8") { + Seq( + 2 -> ParamProfiles.W2, + 4 -> ParamProfiles.W4, + 6 -> ParamProfiles.W6, + 8 -> ParamProfiles.W8).foreach { case (width, p) => + simulate(new CTU(p)) { dut => + clear(dut) + val instructions = + Seq.tabulate(width)(lane => (BigInt(5 + lane * 4), 2)) + enqueue(dut, instructions, firstId = 100 + width) + waitForOutput(dut) + dut.io.toOoo.bits.count.expect(width.U) + (0 until width).foreach { lane => + dut.io.toOoo.bits.entries(lane).parent.identity.instructionId + .expect((100 + width + lane).U) + } + } + } + } + + test("the CTU hierarchy does not instantiate backend state owners") { + val sv = ChiselStage.emitSystemVerilog(new CTU(ParamProfiles.W4)) + assert(sv.contains("module CTU")) + assert(sv.contains("module TemplateDecode")) + assert(sv.contains("module TemplateExpand")) + assert(sv.contains("module InstructionBuffer")) + Seq("ROB", "BROB", "Rename", "IssueQueue", "LSU").foreach { owner => + assert(!sv.contains(s"module $owner")) + } + } + + test("elaborates W2 W4 W6 and W8 with the configured packet widths") { + Seq( + 2 -> ParamProfiles.W2, + 4 -> ParamProfiles.W4, + 6 -> ParamProfiles.W6, + 8 -> ParamProfiles.W8).foreach { case (width, p: CoreParams) => + val chirrtl = ChiselStage.emitCHIRRTL(new CTU(p)) + assert(chirrtl.contains("module CTU")) + assert(p.widths.fetchWidth == width) + assert(p.widths.ctuOutputWidth == width) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ctu/InstructionBufferSpec.scala b/chisel/src/test/scala/linxcore/ctu/InstructionBufferSpec.scala new file mode 100644 index 00000000..c7c4c5e3 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ctu/InstructionBufferSpec.scala @@ -0,0 +1,138 @@ +package linxcore.ctu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.ParamProfiles +import linxcore.top.interface.{D1Packet, FrontEndOpKind, RecoveryCause, RecoveryPhase} +import org.scalatest.funsuite.AnyFunSuite + +class InstructionBufferSpec extends AnyFunSuite with ChiselSim { + private val p = ParamProfiles.W4 + + private def clear(dut: InstructionBuffer): Unit = { + dut.io.enq.valid.poke(false.B) + dut.io.enq.bits.poke(0.U.asTypeOf(dut.io.enq.bits)) + dut.io.deq.ready.poke(false.B) + dut.io.prune.valid.poke(false.B) + dut.io.prune.bits.poke(0.U.asTypeOf(dut.io.prune.bits)) + } + + private def pokePacket( + packet: D1Packet, + ids: Seq[Int], + stid: Int = 0, + epoch: Int = 1): Unit = { + packet.poke(0.U.asTypeOf(packet)) + packet.count.poke(ids.size.U) + ids.zipWithIndex.foreach { case (id, lane) => + packet.entries(lane).kind.poke(FrontEndOpKind.Encoded64) + packet.entries(lane).parent.identity.stid.poke(stid.U) + packet.entries(lane).parent.identity.instructionId.poke(id.U) + packet.entries(lane).parent.identity.epoch.poke(epoch.U) + packet.entries(lane).parent.instruction.poke((0x1000 + id).U) + packet.entries(lane).parent.prediction.transactionId.poke((0x2000 + id).U) + } + } + + private def enqueue( + dut: InstructionBuffer, + ids: Seq[Int], + stid: Int = 0, + epoch: Int = 1): Unit = { + pokePacket(dut.io.enq.bits, ids, stid, epoch) + dut.io.enq.valid.poke(true.B) + dut.io.enq.ready.expect(true.B) + dut.clock.step() + dut.io.enq.valid.poke(false.B) + } + + test("retains a dense prefix and keeps every payload bit stable under backpressure") { + simulate(new InstructionBuffer(p, depth = 8)) { dut => + clear(dut) + enqueue(dut, Seq(10, 11, 12, 13)) + + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.count.expect(4.U) + val heldCount = dut.io.deq.bits.count.peek().litValue + val heldIds = dut.io.deq.bits.entries.map( + _.parent.identity.instructionId.peek().litValue) + val heldInstructions = dut.io.deq.bits.entries.map( + _.parent.instruction.peek().litValue) + dut.clock.step(3) + dut.io.deq.bits.count.expect(heldCount.U) + heldIds.zipWithIndex.foreach { case (id, lane) => + dut.io.deq.bits.entries(lane).parent.identity.instructionId.expect(id.U) + } + heldInstructions.zipWithIndex.foreach { case (instruction, lane) => + dut.io.deq.bits.entries(lane).parent.instruction.expect(instruction.U) + } + + dut.io.deq.ready.poke(true.B) + dut.clock.step() + dut.io.deq.valid.expect(false.B) + dut.io.occupancy.expect(0.U) + } + } + + test("uses pre-cycle free space so downstream ready never bypasses to enqueue ready") { + simulate(new InstructionBuffer(p, depth = 4)) { dut => + clear(dut) + enqueue(dut, Seq(1, 2, 3, 4)) + + pokePacket(dut.io.enq.bits, Seq(5)) + dut.io.enq.valid.poke(true.B) + dut.io.deq.ready.poke(false.B) + dut.io.enq.ready.expect(false.B) + dut.io.deq.ready.poke(true.B) + dut.io.enq.ready.expect(false.B) + + dut.clock.step() + dut.io.enq.ready.expect(true.B) + } + } + + test("compacts only the recovering STID and preserves unrelated FIFO order") { + simulate(new InstructionBuffer(p, depth = 12)) { dut => + clear(dut) + enqueue(dut, Seq(10, 11), stid = 0) + enqueue(dut, Seq(20, 21), stid = 1) + enqueue(dut, Seq(12), stid = 0) + + dut.io.prune.bits.poke(0.U.asTypeOf(dut.io.prune.bits)) + dut.io.prune.bits.transactionId.poke(77.U) + dut.io.prune.bits.phase.poke(RecoveryPhase.Apply) + dut.io.prune.bits.cause.poke(RecoveryCause.Branch) + dut.io.prune.bits.trigger.stid.poke(0.U) + dut.io.prune.bits.newEpoch.poke(2.U) + dut.io.prune.valid.poke(true.B) + dut.io.deq.ready.poke(true.B) + dut.io.deq.valid.expect(false.B) + dut.clock.step() + dut.io.prune.valid.poke(false.B) + + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.count.expect(2.U) + dut.io.deq.bits.entries(0).parent.identity.instructionId.expect(20.U) + dut.io.deq.bits.entries(1).parent.identity.instructionId.expect(21.U) + dut.io.occupancy.expect(2.U) + } + } + + test("accepts and drains simultaneous independent prefixes without reordering") { + simulate(new InstructionBuffer(p, depth = 8)) { dut => + clear(dut) + enqueue(dut, Seq(1, 2)) + + pokePacket(dut.io.enq.bits, Seq(3, 4)) + dut.io.enq.valid.poke(true.B) + dut.io.deq.ready.poke(true.B) + dut.io.deq.bits.entries(0).parent.identity.instructionId.expect(1.U) + dut.io.deq.bits.entries(1).parent.identity.instructionId.expect(2.U) + dut.clock.step() + dut.io.enq.valid.poke(false.B) + + dut.io.deq.bits.entries(0).parent.identity.instructionId.expect(3.U) + dut.io.deq.bits.entries(1).parent.identity.instructionId.expect(4.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/dtu/DTUSpec.scala b/chisel/src/test/scala/linxcore/dtu/DTUSpec.scala new file mode 100644 index 00000000..d39de4d7 --- /dev/null +++ b/chisel/src/test/scala/linxcore/dtu/DTUSpec.scala @@ -0,0 +1,131 @@ +package linxcore.dtu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import _root_.circt.stage.ChiselStage +import linxcore.params.ParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class DTUSpec extends AnyFunSuite with ChiselSim { + private val p = ParamProfiles.W4 + + private def clear(dut: DTU): Unit = { + dut.io.traceIn.valid.poke(false.B) + dut.io.traceIn.bits.poke(0.U.asTypeOf(dut.io.traceIn.bits)) + dut.io.traceOverflowDropped.poke(0.U) + dut.io.commitIn.valid.poke(false.B) + dut.io.commitIn.bits.poke(0.U.asTypeOf(dut.io.commitIn.bits)) + dut.io.debugRequest.valid.poke(false.B) + dut.io.debugRequest.bits.poke(0.U.asTypeOf(dut.io.debugRequest.bits)) + dut.io.controlRequest.ready.poke(false.B) + dut.io.controlResponse.valid.poke(false.B) + dut.io.controlResponse.bits.poke(0.U.asTypeOf(dut.io.controlResponse.bits)) + dut.io.debugResponse.ready.poke(false.B) + dut.io.traceOut.ready.poke(false.B) + } + + test("trace observation never backpressures a stalled exporter") { + simulate(new DTU(p)) { dut => + clear(dut) + dut.io.traceIn.valid.poke(true.B) + dut.io.traceIn.bits.count.poke(1.U) + dut.io.traceIn.bits.entries(0).cycle.poke(11.U) + dut.io.traceIn.ready.expect(true.B) + dut.clock.step() + + dut.io.traceOut.valid.expect(true.B) + dut.io.traceOut.bits.entries(0).cycle.expect(11.U) + dut.io.traceIn.bits.entries(0).cycle.poke(12.U) + dut.io.traceIn.ready.expect(true.B) + dut.clock.step() + + dut.io.traceOut.valid.expect(true.B) + dut.io.traceOut.bits.entries(0).cycle.expect(11.U) + dut.io.performanceCounters(PerformanceCounterIndex.TraceAccepted) + .expect(1.U) + dut.io.performanceCounters(PerformanceCounterIndex.TraceDropped) + .expect(1.U) + } + } + + test("trace event counters include explicit concurrent-source overflow") { + simulate(new DTU(p)) { dut => + clear(dut) + dut.io.traceOut.ready.poke(true.B) + dut.io.traceIn.valid.poke(true.B) + dut.io.traceIn.bits.count.poke(4.U) + dut.io.traceOverflowDropped.poke(3.U) + dut.clock.step() + dut.io.traceIn.valid.poke(false.B) + dut.io.traceOverflowDropped.poke(0.U) + dut.io.performanceCounters(PerformanceCounterIndex.TraceAccepted) + .expect(4.U) + dut.io.performanceCounters(PerformanceCounterIndex.TraceDropped) + .expect(3.U) + } + } + + test("commit observations count retired entries without controlling commit") { + simulate(new DTU(p)) { dut => + clear(dut) + dut.io.commitIn.valid.poke(true.B) + dut.io.commitIn.bits.count.poke(3.U) + dut.io.commitIn.ready.expect(true.B) + dut.clock.step() + dut.io.commitIn.valid.poke(false.B) + + dut.io.performanceCounters(PerformanceCounterIndex.CommitTransactions) + .expect(1.U) + dut.io.performanceCounters(PerformanceCounterIndex.CommittedInstructions) + .expect(3.U) + } + } + + test("halt and resume requests are retained for the OOO control owner") { + simulate(new DTU(p)) { dut => + clear(dut) + dut.io.debugRequest.valid.poke(true.B) + dut.io.debugRequest.bits.transactionId.poke(0x31.U) + dut.io.debugRequest.bits.command.poke(DebugCommand.Halt) + dut.io.debugRequest.bits.stid.poke(1.U) + dut.io.debugRequest.ready.expect(true.B) + dut.clock.step() + dut.io.debugRequest.valid.poke(false.B) + + dut.io.controlRequest.valid.expect(true.B) + dut.io.controlRequest.bits.transactionId.expect(0x31.U) + dut.io.controlRequest.bits.command.expect(DebugCommand.Halt) + dut.clock.step(3) + dut.io.controlRequest.valid.expect(true.B) + dut.io.controlRequest.bits.transactionId.expect(0x31.U) + + dut.io.controlRequest.ready.poke(true.B) + dut.clock.step() + dut.io.controlRequest.ready.poke(false.B) + dut.io.controlResponse.valid.poke(true.B) + dut.io.controlResponse.bits.transactionId.poke(0x31.U) + dut.io.controlResponse.bits.accepted.poke(true.B) + dut.io.debugResponse.valid.expect(true.B) + dut.io.debugResponse.bits.transactionId.expect(0x31.U) + dut.io.debugResponse.bits.accepted.expect(true.B) + dut.io.debugResponse.ready.poke(true.B) + dut.clock.step() + } + } + + test("DTU IO exposes observations and requests but no recovery authority") { + val io = new DTUIO(p) + assert(io.elements.keySet == Set( + "traceIn", "traceOverflowDropped", "commitIn", "debugRequest", "debugResponse", + "controlRequest", "controlResponse", "traceOut", + "performanceCounters")) + assert(!io.elements.keySet.exists(_.toLowerCase.contains("recovery"))) + + val sv = ChiselStage.emitSystemVerilog(new DTU(p)) + assert(sv.contains("module DTU")) + assert(!sv.contains("RecoveryPlan")) + assert(!sv.contains("CommitControl")) + assert(!sv.contains("RecoveryControl")) + } +} diff --git a/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteProbe.scala b/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteProbe.scala deleted file mode 100644 index b8f733a4..00000000 --- a/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteProbe.scala +++ /dev/null @@ -1,222 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.{FrontendOpcodeDecodeTable, FrontendRegAliasClassify} - -class CompressedWordLoadExecuteProbeIO extends Bundle { - val inValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val insnLen = Input(UInt(4.W)) - val imm = Input(UInt(64.W)) - val src0Data = Input(UInt(64.W)) - val src1Data = Input(UInt(64.W)) - val loadLookupData = Input(UInt(64.W)) - val loadLookupWaitBlocked = Input(Bool()) - val loadLiqEnable = Input(Bool()) - val loadLiqAccepted = Input(Bool()) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val dstArchTag = Input(UInt(6.W)) - val dstPhysTag = Input(UInt(6.W)) - val srcArchTag = Input(UInt(6.W)) - val srcPhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val loadWaitHold = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(64.W)) - val loadLookupSize = Output(UInt(4.W)) - val loadLookupReturnSignExtend = Output(Bool()) - val loadLookupPc = Output(UInt(64.W)) - val loadLookupBidValid = Output(Bool()) - val loadLookupBidWrap = Output(Bool()) - val loadLookupBidValue = Output(UInt(6.W)) - val loadLookupGidValid = Output(Bool()) - val loadLookupGidWrap = Output(Bool()) - val loadLookupGidValue = Output(UInt(6.W)) - val loadLookupRidValid = Output(Bool()) - val loadLookupRidWrap = Output(Bool()) - val loadLookupRidValue = Output(UInt(6.W)) - val loadLookupLsId = Output(UInt(32.W)) - val loadLookupDstValid = Output(Bool()) - val loadLookupDstKind = Output(UInt(2.W)) - val loadLookupDstArchTag = Output(UInt(6.W)) - val loadLookupDstRelTag = Output(UInt(6.W)) - val loadLookupDstPhysTag = Output(UInt(6.W)) - - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(6.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(6.W)) - val completeRowWbData = Output(UInt(64.W)) - val completeRowMemValid = Output(Bool()) - val completeRowMemIsStore = Output(Bool()) - val completeRowMemAddr = Output(UInt(64.W)) - val completeRowMemRdata = Output(UInt(64.W)) - val completeRowMemSize = Output(UInt(4.W)) -} - -class CompressedWordLoadExecuteProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new CompressedWordLoadExecuteProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := io.opcode - execute.io.in.dispatchTarget := DispatchTarget.Alu - execute.io.in.imm := io.imm - execute.io.in.immValid := true.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := true.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := io.insnLen - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.srcArchTag - execute.io.in.src(0).physTag := io.srcPhysTag - execute.io.in.src(0).ready := true.B - val classifiedDst = FrontendRegAliasClassify.destination(p, true.B, io.dstArchTag) - execute.io.in.dst(0).valid := true.B - execute.io.in.dst(0).kind := classifiedDst.kind - execute.io.in.dst(0).archTag := classifiedDst.archTag - execute.io.in.dst(0).relTag := classifiedDst.relTag - execute.io.in.dst(0).physTag := io.dstPhysTag - - execute.io.srcData(0) := io.src0Data - execute.io.srcData(1) := io.src1Data - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := io.loadLookupData - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := io.loadLookupWaitBlocked - execute.io.loadLiqEnable := io.loadLiqEnable - execute.io.loadLiqAccepted := io.loadLiqAccepted - execute.io.stackPointerData := 0.U - execute.io.flushValid := false.B - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.loadWaitHold := execute.io.loadWaitHold - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.loadLookupValid := execute.io.loadLookupValid - io.loadLookupAddr := execute.io.loadLookupAddr - io.loadLookupSize := execute.io.loadLookupSize - io.loadLookupReturnSignExtend := execute.io.loadLookupReturnSignExtend - io.loadLookupPc := execute.io.loadLookupPc - io.loadLookupBidValid := execute.io.loadLookupBid.valid - io.loadLookupBidWrap := execute.io.loadLookupBid.wrap - io.loadLookupBidValue := execute.io.loadLookupBid.value - io.loadLookupGidValid := execute.io.loadLookupGid.valid - io.loadLookupGidWrap := execute.io.loadLookupGid.wrap - io.loadLookupGidValue := execute.io.loadLookupGid.value - io.loadLookupRidValid := execute.io.loadLookupRid.valid - io.loadLookupRidWrap := execute.io.loadLookupRid.wrap - io.loadLookupRidValue := execute.io.loadLookupRid.value - io.loadLookupLsId := execute.io.loadLookupLsId - io.loadLookupDstValid := execute.io.loadLookupDst.valid - io.loadLookupDstKind := execute.io.loadLookupDst.kind.asUInt - io.loadLookupDstArchTag := execute.io.loadLookupDst.archTag - io.loadLookupDstRelTag := execute.io.loadLookupDst.relTag - io.loadLookupDstPhysTag := execute.io.loadLookupDst.physTag - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowPc := execute.io.completeRow.pc - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.completeRowMemValid := execute.io.completeRow.mem.valid - io.completeRowMemIsStore := execute.io.completeRow.mem.isStore - io.completeRowMemAddr := execute.io.completeRow.mem.addr - io.completeRowMemRdata := execute.io.completeRow.mem.rdata - io.completeRowMemSize := execute.io.completeRow.mem.size -} - -object EmitCompressedWordLoadExecuteProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-compressed-word-load-execute-probe") - - ChiselStage.emitSystemVerilogFile( - new CompressedWordLoadExecuteProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteSpec.scala b/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteSpec.scala deleted file mode 100644 index 64f1a419..00000000 --- a/chisel/src/test/scala/linxcore/execute/CompressedWordLoadExecuteSpec.scala +++ /dev/null @@ -1,59 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import linxcore.common.DestinationKind -import linxcore.frontend.FrontendOpcodeDecodeTable -import org.scalatest.funsuite.AnyFunSuite - -class CompressedWordLoadExecuteSpec extends AnyFunSuite { - private val mask64 = (BigInt(1) << 64) - 1 - - private def signed(value: BigInt, width: Int): BigInt = { - val mask = (BigInt(1) << width) - 1 - val sign = BigInt(1) << (width - 1) - val masked = value & mask - if ((masked & sign) != 0) masked - (BigInt(1) << width) else masked - } - - test("computes C.LWI address from signed simm5 scaled by four") { - val base = BigInt("40010080", 16) - val simm5 = BigInt("1d", 16) - - assert((base + (signed(simm5, 5) << 2)) == BigInt("40010074", 16)) - } - - test("sign extends C.LWI low word load result to architectural t") { - val loadData = BigInt("0000000080010020", 16) - - assert((signed(loadData, 32) & mask64) == BigInt("ffffffff80010020", 16)) - } - - test("uses local T destination kind for architectural tag 31") { - assert(DestinationKind.T.asUInt.litValue == 2) - } - - test("keeps C.LDI immediate already scaled and returns full doubleword") { - val base = BigInt("40010080", 16) - val decodedImm = BigInt("ffffffffffffffe8", 16) - val loadData = BigInt("8001002000010003", 16) - - assert(((base + signed(decodedImm, 64)) & mask64) == BigInt("40010068", 16)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_C_LDI, - src0 = base, - src1 = 0, - imm = decodedImm, - loadData = loadData).contains(loadData)) - } - - test("elaborates wrapper around real ReducedScalarAluExecute") { - val sv = ChiselStage.emitSystemVerilog(new CompressedWordLoadExecuteProbe) - - assert(sv.contains("module CompressedWordLoadExecuteProbe")) - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("io_loadLookupValid")) - assert(sv.contains("io_loadLookupDstKind")) - assert(sv.contains("io_loadLookupDstRelTag")) - assert(sv.contains("io_completeRowMemAddr")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluAddiwProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluAddiwProbe.scala deleted file mode 100644 index 564aad77..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluAddiwProbe.scala +++ /dev/null @@ -1,205 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.{FrontendOpcodeDecodeTable, FrontendRegAliasClassify} - -class ReducedScalarAluAddiwProbeIO extends Bundle { - val inValid = Input(Bool()) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val uimm12 = Input(UInt(12.W)) - val src0Data = Input(UInt(64.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val src0ArchTag = Input(UInt(6.W)) - val src0PhysTag = Input(UInt(6.W)) - val dstArchTag = Input(UInt(6.W)) - val dstPhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(8.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(8.W)) - val completeRowWbData = Output(UInt(64.W)) - val branchConditionValid = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) -} - -class ReducedScalarAluAddiwProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluAddiwProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := FrontendOpcodeDecodeTable.OP_ADDIW.U - execute.io.in.dispatchTarget := DispatchTarget.Alu - execute.io.in.imm := io.uimm12 - execute.io.in.immValid := true.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := false.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := 4.U - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.src0ArchTag - execute.io.in.src(0).physTag := io.src0PhysTag - execute.io.in.src(0).ready := true.B - val classifiedDst = FrontendRegAliasClassify.destination(p, true.B, io.dstArchTag) - execute.io.in.dst(0).valid := true.B - execute.io.in.dst(0).kind := classifiedDst.kind - execute.io.in.dst(0).archTag := classifiedDst.archTag - execute.io.in.dst(0).relTag := classifiedDst.relTag - execute.io.in.dst(0).physTag := io.dstPhysTag - - execute.io.srcData(0) := io.src0Data - execute.io.srcData(1) := 0.U - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := 0.U - execute.io.flushValid := false.B - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.branchConditionValid := execute.io.branchConditionValid - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid -} - -object EmitReducedScalarAluAddiwProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-addiw-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluAddiwProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluExecuteSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluExecuteSpec.scala deleted file mode 100644 index 5249afcb..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluExecuteSpec.scala +++ /dev/null @@ -1,1921 +0,0 @@ -package linxcore.execute - -import chisel3._ -import circt.stage.ChiselStage -import chisel3.simulator.scalatest.ChiselSim -import linxcore.commit.CommitTraceParams -import linxcore.common.{DestinationKind, DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.FrontendOpcodeDecodeTable -import org.scalatest.funsuite.AnyFunSuite - -class ReducedScalarAluExecuteSpec extends AnyFunSuite with ChiselSim { - private val unsupportedHlDualDstOps = Seq( - FrontendOpcodeDecodeTable.OP_HL_MUL, - FrontendOpcodeDecodeTable.OP_HL_MULU, - FrontendOpcodeDecodeTable.OP_HL_DIV, - FrontendOpcodeDecodeTable.OP_HL_DIVU, - FrontendOpcodeDecodeTable.OP_HL_DIVW, - FrontendOpcodeDecodeTable.OP_HL_DIVUW, - FrontendOpcodeDecodeTable.OP_HL_REM, - FrontendOpcodeDecodeTable.OP_HL_REMU, - FrontendOpcodeDecodeTable.OP_HL_REMW, - FrontendOpcodeDecodeTable.OP_HL_REMUW) - - private def initExecute(dut: ReducedScalarAluExecute): Unit = { - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - } - - private def pokeAlu( - dut: ReducedScalarAluExecute, - opcode: Int, - rid: Int, - pc: BigInt, - src0: BigInt, - src1: BigInt, - imm: BigInt = 0, - dispatchTarget: DispatchTarget.Type = DispatchTarget.Alu): Unit = { - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.peId.poke((rid + 1).U) - dut.io.in.threadId.poke((rid + 2).U) - dut.io.in.pc.poke(pc.U) - dut.io.in.opcode.poke(opcode.U) - dut.io.in.dispatchTarget.poke(dispatchTarget) - dut.io.in.insnLen.poke(4.U) - dut.io.in.insnRaw.poke(0.U) - dut.io.in.imm.poke(imm.U) - dut.io.in.bid.valid.poke(true.B) - dut.io.in.bid.value.poke(0.U) - dut.io.in.gid.valid.poke(true.B) - dut.io.in.gid.value.poke(0.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(rid.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke((rid + 10).U) - dut.io.in.dst(0).physTag.poke((rid + 20).U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.in.src(1).valid.poke(true.B) - dut.io.in.src(1).operandClass.poke(OperandClass.P) - dut.io.in.src(1).archTag.poke(3.U) - dut.io.srcData(0).poke(src0.U) - dut.io.srcData(1).poke(src1.U) - dut.io.inValid.poke(true.B) - } - - test("E1 load lookup owns the read port ahead of an older W2 byte replay") { - assert(ReducedScalarAluExecute.referenceLoadLookupOwner(e1LoadValid = true, w2ByteReplayValid = true) == "e1") - assert(ReducedScalarAluExecute.referenceLoadLookupOwner(e1LoadValid = false, w2ByteReplayValid = true) == "w2-replay") - assert(ReducedScalarAluExecute.referenceLoadLookupOwner(e1LoadValid = false, w2ByteReplayValid = false) == "none") - } - - test("reference results match the model-derived reduced scalar ALU subset") { - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ADD, 10, 32, 0).contains(42)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_ADD, - insnRaw = BigInt("1f8e0785", 16), - src0 = BigInt("40010070", 16), - src1 = BigInt("ffffffffffffffff", 16), - imm = 0).contains(BigInt("40010068", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ADDW, 10, 32, 0).contains(42)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ADDW, - BigInt("7fffffff", 16), - 1, - 0).contains(BigInt("ffffffff80000000", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ADDI, 7, 0, 0x7ff).contains(2054)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SUBI, - src0 = 0, - src1 = 0, - imm = 24).contains(BigInt("ffffffffffffffe8", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SUBIW, - src0 = BigInt("80000001", 16), - src1 = 0, - imm = 2).contains(BigInt("000000007fffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SUBIW, - src0 = 0, - src1 = 0, - imm = 1).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ANDIW, 0, 0, 255).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ANDIW, - BigInt("ffffffffffffffff", 16), - 0, - BigInt("ffffffffffffffff", 16)).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ADDTPC, - pc = BigInt("400054f8", 16), - src0 = 0, - src1 = 0, - imm = 0x9000).contains(BigInt("4000e000", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SETRET, - pc = BigInt("40005506", 16), - src0 = 0, - src1 = 0, - imm = 4).contains(BigInt("4000550a", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SETRET, - pc = BigInt("138cc", 16), - src0 = 0, - src1 = 0, - imm = 6).contains(BigInt("138d2", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SETRET, - pc = BigInt("10012", 16), - src0 = 0, - src1 = 0, - imm = BigInt("fffffffffffffffa", 16)).contains(BigInt("1000c", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_EQI, - src0 = 0, - src1 = 0, - imm = 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_EQI, - src0 = 1, - src1 = 0, - imm = 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_LTU, - src0 = 22, - src1 = BigInt("7fffffff", 16), - imm = 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_LTU, - src0 = BigInt("ffffffffffffffff", 16), - src1 = 1, - imm = 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_LT, - src0 = BigInt("ffffffffffffffff", 16), - src1 = 1, - imm = 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_GEU, - src0 = BigInt("ffffffffffffffff", 16), - src1 = 1, - imm = 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_ANDI, - src0 = BigInt("100", 16), - src1 = 0, - imm = BigInt("180", 16)).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_CMP_ORI, - src0 = 0, - src1 = 0, - imm = 0).contains(0)) - assert(ReducedScalarAluExecute.referenceCsel( - srcL = BigInt("1111222233334444", 16), - srcR = BigInt("aaaabbbbccccdddd", 16), - srcP = 1).equals(BigInt("1111222233334444", 16))) - assert(ReducedScalarAluExecute.referenceCsel( - srcL = BigInt("1111222233334444", 16), - srcR = BigInt("aaaabbbbccccdddd", 16), - srcP = 0).equals(BigInt("aaaabbbbccccdddd", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_FENTRY, - src0 = BigInt("4000550a", 16), - src1 = BigInt("4ffefff0", 16), - imm = 576).contains(BigInt("4ffefdb0", 16))) - assert(ReducedScalarAluExecute.referenceFentryFirstSaveAddress(BigInt("387f0", 16)) == BigInt("387e8", 16)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_LUI, - 0, - 0, - BigInt("12345000", 16)).contains(BigInt("12345000", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_LUI, - 0, - 0, - BigInt("ffffffff80000000", 16)).contains(BigInt("ffffffff80000000", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_LUI, 0, 0, 1).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_LIS, - src0 = 0, - src1 = 0, - imm = BigInt("ffffffff80000001", 16)).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_LIU, - src0 = 0, - src1 = 0, - imm = BigInt("0000000080000001", 16)).contains(BigInt("0000000080000001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_ADDI, - src0 = BigInt("fffffffffff00000", 16), - src1 = 0, - imm = BigInt("ffffff", 16)).contains(BigInt("0000000000efffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SUBI, - src0 = 0, - src1 = 0, - imm = BigInt("ffffff", 16)).contains(BigInt("ffffffffff000001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_ADDIW, - src0 = BigInt("7fffffff", 16), - src1 = 0, - imm = 1).contains(BigInt("ffffffff80000000", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_ANDIW, - src0 = BigInt("00000000800000ff", 16), - src1 = 0, - imm = BigInt("ffffffffff800000", 16)).contains(BigInt("ffffffff80000000", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_ORI, - src0 = BigInt("0000000012340000", 16), - src1 = 0, - imm = BigInt("ffffffffffffffff", 16)).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_ORIW, - src0 = BigInt("0000000070000000", 16), - src1 = 0, - imm = BigInt("fffffffff0000001", 16)).contains(BigInt("fffffffff0000001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_XORI, - src0 = BigInt("aaaaaaaaaaaaaaaa", 16), - src1 = 0, - imm = BigInt("ffffffffffffffff", 16)).contains(BigInt("5555555555555555", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_XORIW, - src0 = BigInt("000000007fffffff", 16), - src1 = 0, - imm = BigInt("ffffffffffffffff", 16)).contains(BigInt("ffffffff80000000", 16))) - // ISA pseudocode and QEMU's linx_hl_swi_writeback agree: PO stores at - // the old base, then writes base + (simm << 2) to the destination. - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SWI_PO, - src0 = 8, - src1 = 0x166a0, - imm = 1).contains(0x166a4)) - assert(ReducedScalarAluExecute.referenceHlSwiPoAddress(0x166a0) == 0x166a0) - assert(ReducedScalarAluExecute.referenceHlSwiPoData(BigInt("deadbeefcafef00d", 16)) == BigInt("cafef00d", 16)) - // Sail, QEMU, LLVM and LinxCoreModel agree: HL.SDI.PO stores at the old - // base, then writes base + (simm17 << 3) to RegDst. - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SDI_PO, - src0 = BigInt("0123456789abcdef", 16), - src1 = BigInt("00000000000166a0", 16), - imm = BigInt("ffffffffffffffff", 16)).contains(BigInt("0000000000016698", 16))) - assert(ReducedScalarAluExecute.referenceHlSdiPoAddress(BigInt("166a0", 16)) == BigInt("166a0", 16)) - assert(ReducedScalarAluExecute.referenceHlSdiPoData(BigInt("0123456789abcdef", 16)) == BigInt("0123456789abcdef", 16)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SLL, 1, 32, 0).contains(BigInt("100000000", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SLLI, 1, 0, 3).contains(8)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SRL, BigInt("100000000", 16), 32, 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SRA, BigInt("100000000", 16), 32, 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRA, - BigInt("fffffffffffff000", 16), - 4, - 0).contains(BigInt("ffffffffffffff00", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SSRSET, - BigInt("40010058", 16), - 0, - 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_OR, BigInt("100000000", 16), 0x5a, 0).contains(BigInt("10000005a", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ORW, - BigInt("80000000", 16), - 1, - 0).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ORIW, - BigInt("80000000", 16), - 0, - 1).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_MOVI, 0, 0, 0x15).contains(0x15)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_MOVR, 0x1234, 0, 0).contains(0x1234)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SWIP, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SWIP_U, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SDIP, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SDIP_U, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LDIP, - src0 = BigInt("07fffe48", 16), - src1 = 0, - imm = 3, - loadData = 45).contains(45)) - assert(ReducedScalarAluExecute.referenceHlImmediateLoadPairSecondAddress( - FrontendOpcodeDecodeTable.OP_HL_LDIP, - base = BigInt("07fffe48", 16), - imm = 3) == BigInt("07fffe68", 16)) - assert(ReducedScalarAluExecute.referenceHlImmediateLoadPairSecondAddress( - FrontendOpcodeDecodeTable.OP_HL_LDIP_U, - base = BigInt("1000", 16), - imm = BigInt("ffffffffffffffff", 16)) == BigInt("1007", 16)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LBI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = BigInt("ffffffffffffffff", 16), - loadData = BigInt("80", 16)).contains(BigInt("ffffffffffffff80", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LBUI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = 7, - loadData = BigInt("ff", 16)).contains(BigInt("ff", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LHI_U, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = BigInt("fffffffffffffffe", 16), - loadData = BigInt("8000", 16)).contains(BigInt("ffffffffffff8000", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LWUI_U, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = BigInt("fffffffffffffffc", 16), - loadData = BigInt("ffffffff80000001", 16)).contains(BigInt("80000001", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LDI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = 3, - loadData = BigInt("0123456789abcdef", 16)).contains(BigInt("0123456789abcdef", 16))) - assert(ReducedScalarAluExecute.referenceHlLongOffsetLoadAddress( - FrontendOpcodeDecodeTable.OP_HL_LWI, - srcL = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffd", 16)) == BigInt("40010074", 16)) - assert(ReducedScalarAluExecute.referenceHlLongOffsetLoadAddress( - FrontendOpcodeDecodeTable.OP_HL_LWI_U, - srcL = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffd", 16)) == BigInt("4001007d", 16)) - assert(ReducedScalarAluExecute.referenceHlLongOffsetStoreAddress( - FrontendOpcodeDecodeTable.OP_HL_SWI, - srcR = BigInt("40010080", 16), - imm = 5) == BigInt("40010094", 16)) - assert(ReducedScalarAluExecute.referenceHlLongOffsetStoreAddress( - FrontendOpcodeDecodeTable.OP_HL_SWI_U, - srcR = BigInt("40010080", 16), - imm = 5) == BigInt("40010085", 16)) - assert(ReducedScalarAluExecute.referenceHlLongOffsetStoreAddress( - FrontendOpcodeDecodeTable.OP_HL_SDI, - srcR = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffe", 16)) == BigInt("40010070", 16)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SBI, 0x12, 0x40010080L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_HL_SDI_U, 0x12, 0x40010080L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ADD, 0x1234, 0x100, 0).contains(0x1334)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SLLI, - src0 = BigInt("4000000000000001", 16), - src1 = 0, - imm = 1).contains(BigInt("8000000000000002", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SRLI, - src0 = BigInt("8000000000000002", 16), - src1 = 0, - imm = 1).contains(BigInt("4000000000000001", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ADDI, 0x1234, 0, 0).contains(0x1234)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ADDI, 0x1234, 0, 0x10).contains(0x1244)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_ADDI, - 0x1234, - 0, - BigInt("ffffffffffffffff", 16)).contains(0x1233)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_ADDI, - BigInt("ffffffffffffffff", 16), - 0, - 1).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_ADDI, - src0 = 31, - src1 = 0, - imm = 1).contains(32)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ADDI, 0x1234, 0, 0x10).contains(0x1244)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_LUI, 0, 0, 0x1244).contains(0x1244)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_AND, 0xff0f, 0x33f0, 0).contains(0x3300)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SEXT_B, - BigInt("80", 16), - 0, - 0).contains(BigInt("ffffffffffffff80", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SEXT_H, - BigInt("8001", 16), - 0, - 0).contains(BigInt("ffffffffffff8001", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SEXT_W, - BigInt("80000001", 16), - 0, - 0).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ZEXT_B, BigInt("ff80", 16), 0, 0) - .contains(0x80)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ZEXT_H, BigInt("ffff8001", 16), 0, 0) - .contains(0x8001)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_ZEXT_W, BigInt("ffffffff80000001", 16), 0, 0) - .contains(BigInt("80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_LDI, 0x4ffefdb0L, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SDI, 0x4ffefdb0L, 0x40005679L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SWI, 0x4000ff90L, 2, 40).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_LDI, 0x4fff0048L, 0, BigInt("fffffffffffffffe", 16)).contains(0)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LDI, - src0 = 0x4000ecc8L, - src1 = 0, - imm = 0, - loadData = 0x6ffffffbL).contains(0x6ffffffbL)) - assert(ReducedScalarAluExecute.referenceLwiAddress( - srcL = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffd", 16)) == BigInt("40010074", 16)) - assert(ReducedScalarAluExecute.referenceLwiUAddress( - srcL = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffd", 16)) == BigInt("4001007d", 16)) - assert(ReducedScalarAluExecute.referenceLwiAddress( - srcL = BigInt("40010080", 16), - imm = 5) == BigInt("40010094", 16)) - assert(ReducedScalarAluExecute.referenceLwiUAddress( - srcL = BigInt("40010080", 16), - imm = 5) == BigInt("40010085", 16)) - assert(ReducedScalarAluExecute.referenceLhiAddress( - srcL = BigInt("40010080", 16), - imm = 0) == BigInt("40010080", 16)) - assert(ReducedScalarAluExecute.referenceLhiAddress( - srcL = BigInt("40010080", 16), - imm = 7) == BigInt("4001008e", 16)) - assert(ReducedScalarAluExecute.referenceLhiAddress( - srcL = BigInt("40010080", 16), - imm = BigInt("fffffffffffffffc", 16)) == BigInt("40010078", 16)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LHI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = 0, - loadData = BigInt("7fff", 16)).contains(BigInt("7fff", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LHI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = 0, - loadData = BigInt("8000", 16)).contains(BigInt("ffffffffffff8000", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LHUI, - src0 = BigInt("40010080", 16), - src1 = 0, - imm = 0, - loadData = BigInt("ffff", 16)).contains(BigInt("ffff", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LWI, - src0 = 0x40010080L, - src1 = 0, - imm = BigInt("fffffffffffffffd", 16), - loadData = BigInt("80010020", 16)).contains(BigInt("ffffffff80010020", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LWI_U, - src0 = 0x40010080L, - src1 = 0, - imm = BigInt("fffffffffffffffd", 16), - loadData = BigInt("00010020", 16)).contains(BigInt("00010020", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LBUI, - src0 = 1, - src1 = 0, - imm = BigInt("ffffffffffffffff", 16), - loadData = 0x1234L).contains(0x34)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LBI, - src0 = 1, - src1 = 0, - imm = 0, - loadData = 0x80).contains(BigInt("ffffffffffffff80", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LB, - src0 = 1, - src1 = 0, - imm = 0, - loadData = 0x7f).contains(0x7f)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LD_PCR, - src0 = 0, - src1 = 0, - imm = 0xa728, - loadData = 0x4000574cL).contains(0x4000574cL)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SB_PCR, - src0 = 1, - src1 = 0, - imm = 0x9dfa).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SD_PCR, - src0 = 0x4fff0008L, - src1 = 0, - imm = 0xa43a).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SH_PCR, - src0 = 1, - src1 = 0, - imm = 0x9dfa).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_SW_PCR, - src0 = 1, - src1 = 0, - imm = 0x9dfa).contains(0)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LD_PCR, - src0 = 0, - src1 = 0, - imm = 0x100, - loadData = 0x1234L).contains(0x1234L)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SETC_EQ, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_C_SETC_EQ, 0, 0).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_C_SETC_EQ, 8, 256).contains(false)) - assert(ReducedScalarAluExecute.referenceBranchCondition( - FrontendOpcodeDecodeTable.OP_C_SETC_EQ, - src0 = 0x4fff0018L, - src1 = 0, - src0Valid = false, - src1Valid = true).contains(true)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SETC_NE, 0x4fff0018L, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_C_SETC_NE, 8, 256).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_C_SETC_NE, 256, 256).contains(false)) - assert(ReducedScalarAluExecute.referenceBranchCondition( - FrontendOpcodeDecodeTable.OP_C_SETC_NE, - src0 = 0x4fff0018L, - src1 = 0, - src0Valid = false, - src1Valid = true).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SETC_TGT, 0x4000574cL, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_C_SETC_TGT, 0x4000574cL, 0).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition( - FrontendOpcodeDecodeTable.OP_C_SETC_TGT, - src0 = 0, - src1 = 0, - src0Valid = false).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_FRET_STK, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_FRET_STK, - src0 = 0, - src1 = 0, - imm = 8, - loadData = 0x40005cb0L).contains(0x40005cb0L)) - assert(ReducedScalarAluExecute.referenceFretStkNextPc( - pc = BigInt("40005788", 16), - lenBytes = 4, - setcTarget = None, - fallbackTarget = Some(BigInt("40005f2c", 16))) == BigInt("40005f2c", 16)) - assert(ReducedScalarAluExecute.referenceFretStkNextPc( - pc = BigInt("4000570a", 16), - lenBytes = 4, - setcTarget = Some(BigInt("4000574c", 16)), - fallbackTarget = Some(BigInt("40005f2c", 16))) == BigInt("4000574c", 16)) - assert(ReducedScalarAluExecute.referenceFretStkNextPc( - pc = BigInt("40005788", 16), - lenBytes = 4, - setcTarget = None, - fallbackTarget = None) == BigInt("4000578c", 16)) - assert(ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = false, - conditionTaken = false)) - assert(ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = true, - conditionTaken = false)) - assert(!ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = true, - conditionTaken = true)) - assert(!ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = false, - conditionValid = false, - conditionTaken = false)) - assert(!ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = false, - conditionTaken = false, - targetPending = true)) - assert(!ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = true, - conditionTaken = true, - targetPending = true)) - assert(ReducedScalarAluExecute.referenceFretStkLoadsReturn( - restoresRa = true, - conditionValid = true, - conditionTaken = false, - targetPending = true)) - assert(ReducedScalarAluExecute.referenceFretStkSnapshotLoadsReturn( - restoresRa = true, - contextValid = true, - snapshotConditionValid = true, - snapshotConditionTaken = false, - snapshotTargetPending = true, - liveConditionValid = false, - liveConditionTaken = false, - liveTargetPending = true)) - assert(!ReducedScalarAluExecute.referenceFretStkSnapshotLoadsReturn( - restoresRa = true, - contextValid = false, - snapshotConditionValid = true, - snapshotConditionTaken = false, - snapshotTargetPending = true, - liveConditionValid = false, - liveConditionTaken = false, - liveTargetPending = true)) - assert(!ReducedScalarAluExecute.referenceFretStkDecodeContextValid( - isFretStk = true, - activeBlockConditional = true, - conditionValid = false)) - assert(ReducedScalarAluExecute.referenceFretStkSnapshotLoadsReturn( - restoresRa = true, - contextValid = ReducedScalarAluExecute.referenceFretStkDecodeContextValid( - isFretStk = true, - activeBlockConditional = true, - conditionValid = false), - snapshotConditionValid = false, - snapshotConditionTaken = false, - snapshotTargetPending = true, - liveConditionValid = true, - liveConditionTaken = false, - liveTargetPending = true)) - assert(ReducedScalarAluExecute.referenceFretStkDecodeContextValid( - isFretStk = true, - activeBlockConditional = false, - conditionValid = false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SETC_LT, 0, 1, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition( - FrontendOpcodeDecodeTable.OP_SETC_LT, - BigInt("ffffffffffffffff", 16), - 1).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition( - FrontendOpcodeDecodeTable.OP_SETC_LT, - 1, - BigInt("ffffffffffffffff", 16)).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SETC_LTU, 36, 0x6ffffffbL, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_LTU, 36, 0x6ffffffbL).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_LTU, 0x6ffffffbL, 36).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SETC_LTUI, 0x130, 3, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_LTUI, 2, 3).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_LTUI, 0x130, 3).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SETC_TGT, 0x4000574cL, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_TGT, 0x4000574cL, 0).contains(true)) - assert(ReducedScalarAluExecute.referenceBranchCondition(FrontendOpcodeDecodeTable.OP_SETC_TGT, 0, 0).contains(false)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SBI, 0, 0x4fff0038L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SD, 0, 0x4fff0040L, 21).contains(0)) - assert(ReducedScalarAluExecute.referenceSdIndexedAddress(0x4fff0040L, 21).equals(BigInt("4fff00e8", 16))) - assert(ReducedScalarAluExecute.referenceSdIndexedData(0x400055f2L).equals(BigInt("400055f2", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SDI, 0, 0x4fff0128L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SHI, 0xdeadbeefL, 0x4fff0100L, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceShiAddress(srcR = BigInt("4fff0100", 16), imm = 0).equals(BigInt("4fff0100", 16))) - assert(ReducedScalarAluExecute.referenceShiAddress(srcR = BigInt("4fff0100", 16), imm = 7).equals(BigInt("4fff010e", 16))) - assert(ReducedScalarAluExecute.referenceShiAddress( - srcR = BigInt("4fff0100", 16), - imm = BigInt("fffffffffffffffc", 16)).equals(BigInt("4fff00f8", 16))) - assert(ReducedScalarAluExecute.referenceShiData(BigInt("deadbeefcafebabe", 16)).equals(BigInt("deadbeefcafebabe", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_MULW, 6, 7, 0).contains(42)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MULW, - BigInt("ffffffff", 16), - 2, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_DIVU, 100, 7, 0).contains(14)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_DIV, - BigInt("ffffffffffffff9c", 16), - 7, - 0).contains(BigInt("fffffffffffffff2", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_DIVUW, - BigInt("fffffffe", 16), - 1, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_DIV, 123, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_REMU, 100, 7, 0).contains(2)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_REM, - BigInt("ffffffffffffff9c", 16), - 7, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_REMUW, - BigInt("fffffffe", 16), - BigInt("ffffffff", 16), - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_REM, 123, 0, 0).contains(123)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_C_SUB, 10, 3, 0).contains(7)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SUBW, - BigInt("80000000", 16), - 1, - 0).contains(BigInt("000000007fffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_SUB, - 0, - BigInt("4ffefbf8", 16), - 0).contains(BigInt("ffffffffb0010408", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ANDI, BigInt("f0", 16), 0, 3) - .contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_AND, - BigInt("f0f0", 16), - BigInt("0ff0", 16), - 0).contains(BigInt("00f0", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_ANDW, - insnRaw = BigInt("06000000", 16), - src0 = BigInt("ffffffffffffffff", 16), - src1 = BigInt("80000001", 16), - imm = 0).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_ANDW, - insnRaw = BigInt("08000000", 16), - src0 = BigInt("ffffffffffffffff", 16), - src1 = BigInt("80000001", 16), - imm = 0).contains(2)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_ANDW, - insnRaw = BigInt("0c000000", 16), - src0 = BigInt("ffffffffffffffff", 16), - src1 = BigInt("7ffffffe", 16), - imm = 0).contains(2)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_ANDI, - BigInt("ffff", 16), - 0, - BigInt("fffffffffffffff0", 16)).contains(BigInt("fff0", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_ORI, 0, 0, 0x18) - .contains(0x18)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_XORI, - 0, - 0, - BigInt("ffffffffffffffff", 16)).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_XOR, - BigInt("ff00", 16), - BigInt("0ff0", 16), - 0).contains(BigInt("f0f0", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_XORW, - BigInt("80000000", 16), - 1, - 0).contains(BigInt("ffffffff80000001", 16))) - val wrapFieldInsn = (BigInt(60) << 26) | (BigInt(7) << 20) - val wrapFieldValue = (BigInt(1) << 60) | BigInt(1) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BXU, - wrapFieldInsn, - wrapFieldValue, - 0, - 0).contains(0x11)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BXS, - wrapFieldInsn, - BigInt(1) << 3, - 0, - 0).contains(BigInt("ffffffffffffff80", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BCNT, - wrapFieldInsn, - wrapFieldValue, - 0, - 0).contains(2)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_CLZ, - wrapFieldInsn, - BigInt(1) << 60, - 0, - 0).contains(7)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_CTZ, - wrapFieldInsn, - BigInt(1) << 1, - 0, - 0).contains(5)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BIC, - wrapFieldInsn, - BigInt("ffffffffffffffff", 16), - 0, - 0).contains(BigInt("0ffffffffffffff0", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BIS, - wrapFieldInsn, - 0, - 0, - 0).contains(BigInt("f00000000000000f", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MAX, - BigInt("ffffffffffffffff", 16), - 1, - 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MIN, - BigInt("ffffffffffffffff", 16), - 1, - 0).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MAXU, - BigInt("ffffffffffffffff", 16), - 1, - 0).contains(BigInt("ffffffffffffffff", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MINU, - BigInt("ffffffffffffffff", 16), - 1, - 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MULU, - BigInt("ffffffffffffffff", 16), - 2, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MULUW, - BigInt("ffffffff", 16), - 2, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_XORIW, - BigInt("80000000", 16), - 0, - 1).contains(BigInt("ffffffff80000001", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SUB, 0x130, 0x18, 0) - .contains(0x118)) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_MUL, 6, 7, 0).contains(42)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_MUL, - BigInt("ffffffffffffffff", 16), - 2, - 0).contains(BigInt("fffffffffffffffe", 16))) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SWI, 0, 0x4ffefbf8L, 0) - .contains(0)) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LD, 1, 2, 3, BigInt("deadbeefcafef00d", 16)) - .contains(BigInt("deadbeefcafef00d", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LWUI, 1, 0, 3, BigInt("ffffffff80000001", 16)) - .contains(BigInt("80000001", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_LR_W, 0, 0, 0, BigInt("80000000", 16)) - .contains(BigInt("ffffffff80000000", 16))) - assert(ReducedScalarAluExecute.referenceResultWithLoad( - FrontendOpcodeDecodeTable.OP_HL_LB_PCR, 0, 0, 0, BigInt("80", 16)) - .contains(BigInt("ffffffffffffff80", 16))) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_ANDI, BigInt("100", 16), 0, BigInt("180", 16)).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_EQI, BigInt("ffffffffffffffff", 16), 0, BigInt("ffffffffffffffff", 16)).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_GEI, BigInt("ffffffffffffffff", 16), 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_GEUI, BigInt("ffffffffffffffff", 16), 0, 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_LTI, BigInt("ffffffffffffffff", 16), 0, 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_LTUI, BigInt("ffffffffffffffff", 16), 0, 1).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_NEI, BigInt("100", 16), 0, BigInt("101", 16)).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_ORI, 0, 0, 0).contains(0)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_HL_CMP_ORI, 0, 0, BigInt("ffffffffffffffff", 16)).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_CMP_EQI, 0, 0, 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_C_OR, BigInt("100", 16), BigInt("11", 16), 0).contains(BigInt("111", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BXU, BigInt("01fc1167", 16), BigInt("ffffffff89abcdef", 16), 0, 0) - .contains(BigInt("89abcdef", 16))) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_BCNT, BigInt("03f26fe7", 16), BigInt("f0f0", 16), 0, 0).contains(8)) - assert(ReducedScalarAluExecute.referenceResultWithInsn( - FrontendOpcodeDecodeTable.OP_CLZ, BigInt("01f1df67", 16), BigInt("00008000", 16), 0, 0).contains(16)) - assert(ReducedScalarAluExecute.referenceMadd(5, 6, 7) == 47) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_LHI_U, 1, 2, 3).isEmpty) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_LHUI_U, 1, 2, 3).isEmpty) - assert(ReducedScalarAluExecute.referenceResult(FrontendOpcodeDecodeTable.OP_SHI_U, 1, 2, 3).isEmpty) - unsupportedHlDualDstOps.foreach { opcode => - assert(ReducedScalarAluExecute.referenceResult(opcode, 7, 3, 0).isEmpty) - } - } - - test("ReducedScalarAluExecute elaborates completion-row writeback payloads") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarAluExecute(p, trace)) - - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("io_completeValid")) - assert(sv.contains("io_completeRobValue")) - assert(sv.contains("io_completePeId")) - assert(sv.contains("io_completeStid")) - assert(sv.contains("io_completeTid")) - assert(sv.contains("io_completeRow_wb_valid")) - assert(sv.contains("io_completeRow_dst_data")) - assert(sv.contains("io_completeLsId")) - assert(sv.contains("io_loadLookupGid_value")) - assert(sv.contains("io_loadLookupRid_value")) - assert(sv.contains("io_releaseGid_value")) - assert(sv.contains("io_completeDstPhysValid")) - assert(sv.contains("io_completeDstPhysTag")) - assert(sv.contains("io_completeDstData")) - assert(sv.contains("io_stackPointerData")) - assert(sv.contains("io_branchConditionValid")) - assert(sv.contains("io_branchConditionTaken")) - assert(sv.contains("io_fretStkConditionValid")) - assert(sv.contains("io_fretStkConditionTaken")) - assert(sv.contains("fretStkContextValid")) - assert(sv.contains("fretStkFallbackTargetValid")) - assert(sv.contains("io_flushValid")) - assert(sv.contains("io_fretStkFallbackTargetValid")) - assert(sv.contains("io_fretStkFallbackTarget")) - assert(sv.contains("io_releaseValid")) - assert(sv.contains("io_releaseBid_value")) - assert(sv.contains("io_releaseRid_value")) - assert(sv.contains("io_releaseStid")) - assert(sv.contains("io_earlyReleaseValid")) - assert(sv.contains("io_earlyReleaseBid_value")) - assert(sv.contains("io_earlyReleaseGid_value")) - assert(sv.contains("io_earlyReleaseRid_value")) - assert(sv.contains("io_earlyReleaseStid")) - assert(sv.contains("io_liqReleaseValid")) - assert(sv.contains("io_liqReleaseBid_value")) - assert(sv.contains("io_liqReleaseRid_value")) - assert(sv.contains("io_liqReleaseStid")) - assert(sv.contains("io_loadLookupPc")) - assert(sv.contains("io_loadLookupSize")) - assert(sv.contains("io_loadLiqEligible")) - assert(sv.contains("io_loadLookupBid_value")) - assert(sv.contains("io_loadLookupLsId")) - assert(sv.contains("io_loadLookupWaitBlocked")) - assert(sv.contains("io_loadLiqEnable")) - assert(sv.contains("io_loadLiqAccepted")) - assert(sv.contains("io_loadWaitHold")) - assert(sv.contains("io_unsupportedOpcode")) - assert(sv.contains("12'h16B")) - assert(sv.contains("12'h16E")) - assert(sv.contains("4'h2")) - } - - test("HL CMP immediate forms produce ISA boolean results in the ALU pipeline") { - val cases = Seq( - (FrontendOpcodeDecodeTable.OP_HL_CMP_EQI, BigInt("ffffffffffffffff", 16), BigInt("ffffffffffffffff", 16), BigInt(1)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_GEI, BigInt("ffffffffffffffff", 16), BigInt(0), BigInt(0)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_GEUI, BigInt("ffffffffffffffff", 16), BigInt(0), BigInt(1)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_LTI, BigInt("ffffffffffffffff", 16), BigInt(0), BigInt(1)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_LTUI, BigInt("ffffffffffffffff", 16), BigInt(1), BigInt(0)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_NEI, BigInt("100", 16), BigInt("101", 16), BigInt(1)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_ORI, BigInt(0), BigInt(0), BigInt(0)), - (FrontendOpcodeDecodeTable.OP_HL_CMP_ORI, BigInt(0), BigInt("ffffffffffffffff", 16), BigInt(1))) - val p = InterfaceParams(robEntries = 16, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - for (((opcode, src0, imm, expected), index) <- cases.zipWithIndex) { - val rid = index + 1 - pokeAlu(dut, opcode, rid, BigInt("40008000", 16) + (index * 4), src0, 0, imm = imm) - dut.io.inReady.expect(true.B) - dut.io.accepted.expect(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - dut.clock.step(2) - dut.io.completeValid.expect(true.B) - dut.io.unsupported.expect(false.B) - dut.io.completeRobValue.expect(rid.U) - dut.io.completeDstData.expect(expected.U) - dut.io.completeRow.wb.valid.expect(true.B) - dut.io.completeRow.wb.data.expect(expected.U) - dut.clock.step() - } - } - } - - test("safe fixed scalar ALU inputs accept every cycle and complete in identity order") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - def pokeAlu(opcode: Int, rid: Int, pc: BigInt, src0: BigInt, src1: BigInt, imm: BigInt = 0): Unit = { - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.peId.poke((rid + 1).U) - dut.io.in.threadId.poke((rid + 2).U) - dut.io.in.pc.poke(pc.U) - dut.io.in.opcode.poke(opcode.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.insnLen.poke(4.U) - dut.io.in.insnRaw.poke(0.U) - dut.io.in.imm.poke(imm.U) - dut.io.in.bid.valid.poke(true.B) - dut.io.in.bid.value.poke(0.U) - dut.io.in.gid.valid.poke(true.B) - dut.io.in.gid.value.poke(0.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(rid.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke((rid + 10).U) - dut.io.in.dst(0).physTag.poke((rid + 20).U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.in.src(1).valid.poke(true.B) - dut.io.in.src(1).operandClass.poke(OperandClass.P) - dut.io.in.src(1).archTag.poke(3.U) - dut.io.srcData(0).poke(src0.U) - dut.io.srcData(1).poke(src1.U) - dut.io.inValid.poke(true.B) - } - - def expectComplete(rid: Int, pc: BigInt, data: BigInt): Unit = { - dut.io.completeValid.expect(true.B) - dut.io.releaseValid.expect(false.B) - dut.io.completeRobValue.expect(rid.U) - dut.io.completePeId.expect((rid + 1).U) - dut.io.completeStid.expect((rid + 2).U) - dut.io.completeTid.expect((rid + 2).U) - dut.io.completeRow.pc.expect(pc.U) - dut.io.completeRow.identity.rid.expect(rid.U) - dut.io.completeDstData.expect(data.U) - } - - pokeAlu(FrontendOpcodeDecodeTable.OP_ADD, 1, BigInt("40001000", 16), 5, 6) - dut.io.inReady.expect(true.B) - dut.io.accepted.expect(true.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.clock.step() - - pokeAlu(FrontendOpcodeDecodeTable.OP_ADDI, 2, BigInt("40001004", 16), 20, 0, imm = 2) - dut.io.inReady.expect(true.B) - dut.io.accepted.expect(true.B) - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect(1.U) - dut.io.earlyReleaseStid.expect(3.U) - dut.clock.step() - - pokeAlu(FrontendOpcodeDecodeTable.OP_ADD, 3, BigInt("40001008", 16), 30, 3) - dut.io.inReady.expect(true.B) - dut.io.accepted.expect(true.B) - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect(2.U) - dut.io.earlyReleaseStid.expect(4.U) - dut.clock.step() - dut.io.inValid.poke(false.B) - - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect(3.U) - dut.io.earlyReleaseStid.expect(5.U) - expectComplete(1, BigInt("40001000", 16), 11) - dut.clock.step() - dut.io.earlyReleaseValid.expect(false.B) - expectComplete(2, BigInt("40001004", 16), 22) - dut.clock.step() - expectComplete(3, BigInt("40001008", 16), 33) - dut.clock.step() - dut.io.completeValid.expect(false.B) - dut.io.releaseValid.expect(false.B) - } - } - - test("W2 completion backpressure holds payloads stable and fires once when ready returns") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 1, BigInt("40002000", 16), 5, 6) - dut.clock.step() - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADDI, 2, BigInt("40002004", 16), 10, 0, imm = 7) - dut.clock.step() - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 3, BigInt("40002008", 16), 30, 4) - dut.clock.step() - - dut.io.completeReady.poke(false.B) - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 4, BigInt("4000200c", 16), 40, 5) - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(false.B) - dut.io.completeAccepted.expect(false.B) - dut.io.releaseValid.expect(false.B) - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect(3.U) - dut.io.completeRobValue.expect(1.U) - dut.io.completeRow.pc.expect(BigInt("40002000", 16).U) - dut.io.completeDstData.expect(11.U) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - dut.clock.step() - for (_ <- 0 until 2) { - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(false.B) - dut.io.completeAccepted.expect(false.B) - dut.io.releaseValid.expect(false.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.io.completeRobValue.expect(1.U) - dut.io.completeRow.pc.expect(BigInt("40002000", 16).U) - dut.io.completeDstData.expect(11.U) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - dut.clock.step() - } - - dut.io.completeReady.poke(true.B) - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(true.B) - dut.io.completeAccepted.expect(true.B) - dut.io.releaseValid.expect(false.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.io.completeRobValue.expect(1.U) - dut.clock.step() - - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect(4.U) - dut.io.inValid.poke(false.B) - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(true.B) - dut.io.completeRobValue.expect(2.U) - dut.io.completeDstData.expect(17.U) - } - } - - test("SETC publishes one branch resolution only with accepted W2 completion") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - dut.io.completeReady.poke(false.B) - pokeAlu( - dut, - FrontendOpcodeDecodeTable.OP_C_SETC_EQ, - rid = 1, - pc = BigInt("40005636", 16), - src0 = 0, - src1 = 0, - dispatchTarget = DispatchTarget.Bru) - dut.clock.step() - dut.io.inValid.poke(false.B) - - var waited = 0 - while (!dut.io.completeValid.peek().litToBoolean && waited < 8) { - dut.io.branchConditionValid.expect(false.B) - dut.clock.step() - waited += 1 - } - assert(waited < 8, "SETC did not reach W2") - - for (_ <- 0 until 2) { - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(false.B) - dut.io.branchConditionValid.expect(false.B) - dut.clock.step() - } - - dut.io.completeReady.poke(true.B) - dut.io.completeFire.expect(true.B) - dut.io.branchConditionValid.expect(true.B) - dut.io.branchConditionTaken.expect(true.B) - dut.clock.step() - dut.io.branchConditionValid.expect(false.B) - } - } - - test("FRET.STK consumes a SETC target only from the same full BID") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - - def completeSetc(blockBid: Int, target: BigInt, rid: Int): Unit = { - pokeAlu( - dut, - FrontendOpcodeDecodeTable.OP_C_SETC_TGT, - rid = rid, - pc = BigInt("40006000", 16) + rid * 2, - src0 = target, - src1 = 0, - dispatchTarget = DispatchTarget.Bru) - dut.io.in.blockBidValid.poke(true.B) - dut.io.in.blockBid.poke(blockBid.U) - dut.clock.step() - dut.io.inValid.poke(false.B) - var waited = 0 - while (!dut.io.branchConditionValid.peek().litToBoolean && waited < 8) { - dut.clock.step() - waited += 1 - } - assert(waited < 8, "SETC.TGT did not reach W2") - dut.io.branchConditionIsTarget.expect(true.B) - dut.clock.step() - } - - def completeFret(blockBid: Int, fallback: BigInt, rid: Int): BigInt = { - pokeAlu( - dut, - FrontendOpcodeDecodeTable.OP_FRET_STK, - rid = rid, - pc = BigInt("40006100", 16) + rid * 4, - src0 = 0, - src1 = 0, - dispatchTarget = DispatchTarget.Bru) - dut.io.in.blockBidValid.poke(true.B) - dut.io.in.blockBid.poke(blockBid.U) - dut.io.in.fretStkContextValid.poke(true.B) - dut.io.in.fretStkConditionValid.poke(true.B) - dut.io.in.fretStkConditionTaken.poke(true.B) - dut.io.in.fretStkFallbackTargetValid.poke(true.B) - dut.io.in.fretStkFallbackTarget.poke(fallback.U) - dut.clock.step() - dut.io.inValid.poke(false.B) - var waited = 0 - while (!dut.io.redirectValid.peek().litToBoolean && waited < 8) { - dut.clock.step() - waited += 1 - } - assert(waited < 8, "FRET.STK did not reach W2") - val redirect = dut.io.redirectPc.peek().litValue - dut.clock.step() - redirect - } - - val setcTarget = BigInt("36c6", 16) - val fallback = BigInt("621c", 16) - completeSetc(blockBid = 0x21, setcTarget, rid = 1) - assert(completeFret(blockBid = 0x22, fallback, rid = 2) == fallback) - - completeSetc(blockBid = 0x23, setcTarget, rid = 3) - assert(completeFret(blockBid = 0x23, fallback, rid = 4) == setcTarget) - } - } - - test("dense four-entry ALU stream survives a mid-stream W2 stall without dropping or reordering") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 1, BigInt("40003000", 16), 1, 10) - dut.io.inReady.expect(true.B) - dut.clock.step() - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 2, BigInt("40003004", 16), 2, 20) - dut.io.inReady.expect(true.B) - dut.clock.step() - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 3, BigInt("40003008", 16), 3, 30) - dut.io.inReady.expect(true.B) - dut.clock.step() - - dut.io.completeReady.poke(false.B) - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 4, BigInt("4000300c", 16), 4, 40) - for (_ <- 0 until 2) { - dut.io.completeValid.expect(true.B) - dut.io.completeFire.expect(false.B) - dut.io.completeRobValue.expect(1.U) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - dut.clock.step() - } - - dut.io.completeReady.poke(true.B) - dut.io.inReady.expect(true.B) - dut.io.accepted.expect(true.B) - dut.io.completeFire.expect(true.B) - dut.io.completeRobValue.expect(1.U) - dut.io.completeDstData.expect(11.U) - dut.clock.step() - - dut.io.inValid.poke(false.B) - dut.io.completeFire.expect(true.B) - dut.io.completeRobValue.expect(2.U) - dut.io.completeDstData.expect(22.U) - dut.clock.step() - dut.io.completeFire.expect(true.B) - dut.io.completeRobValue.expect(3.U) - dut.io.completeDstData.expect(33.U) - dut.clock.step() - dut.io.completeFire.expect(true.B) - dut.io.completeRobValue.expect(4.U) - dut.io.completeDstData.expect(44.U) - dut.clock.step() - dut.io.completeValid.expect(false.B) - } - } - - test("malformed dispatch target does not use the pipe-safe ALU bypass") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_ADD, 1, BigInt("40004000", 16), 1, 2) - dut.io.inReady.expect(true.B) - dut.clock.step() - - pokeAlu( - dut, - FrontendOpcodeDecodeTable.OP_ADD, - 2, - BigInt("40004004", 16), - 3, - 4, - dispatchTarget = DispatchTarget.Bru) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - dut.clock.step() - - dut.io.inReady.expect(true.B) - dut.io.completeValid.expect(false.B) - dut.io.completeFire.expect(false.B) - } - } - - test("unsupported W2 entries diagnose and release once without ROB-complete readiness") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - initExecute(dut) - dut.io.completeReady.poke(false.B) - - pokeAlu(dut, FrontendOpcodeDecodeTable.OP_INVALID, 5, BigInt("40005000", 16), 0, 0) - dut.io.inReady.expect(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - dut.clock.step() - dut.clock.step() - - dut.io.completeValid.expect(false.B) - dut.io.completeFire.expect(false.B) - dut.io.unsupported.expect(true.B) - dut.io.unsupportedOpcode.expect(FrontendOpcodeDecodeTable.OP_INVALID.U) - dut.io.releaseValid.expect(true.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.io.releaseRid.value.expect(5.U) - dut.clock.step() - - dut.io.unsupported.expect(false.B) - dut.io.releaseValid.expect(false.B) - dut.io.busy.expect(false.B) - - for ((opcode, index) <- unsupportedHlDualDstOps.zipWithIndex) { - val rid = index % p.robEntries - pokeAlu(dut, opcode, rid, BigInt("40005010", 16) + index * 4, 7, 3) - dut.io.inReady.expect(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - dut.clock.step() - dut.clock.step() - - dut.io.completeValid.expect(false.B) - dut.io.completeFire.expect(false.B) - dut.io.unsupported.expect(true.B) - dut.io.unsupportedOpcode.expect(opcode.U) - dut.io.releaseValid.expect(true.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.io.releaseRid.value.expect(rid.U) - dut.clock.step() - - dut.io.unsupported.expect(false.B) - dut.io.releaseValid.expect(false.B) - dut.io.busy.expect(false.B) - } - } - } - - test("unsafe inputs keep old execute backpressure around pipe-safe ALU ops") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_ADD.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(1.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke(10.U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.in.src(1).valid.poke(true.B) - dut.io.in.src(1).operandClass.poke(OperandClass.P) - dut.io.in.src(1).archTag.poke(3.U) - dut.io.inValid.poke(true.B) - dut.io.inReady.expect(true.B) - dut.clock.step() - - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_LR_W.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(2.U) - dut.io.in.isLoad.poke(true.B) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.inValid.poke(true.B) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - dut.clock.step() - - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_LR_W.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(3.U) - dut.io.in.isLoad.poke(true.B) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.inValid.poke(true.B) - dut.io.inReady.expect(true.B) - dut.clock.step() - - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_ADD.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.isLoad.poke(false.B) - dut.io.in.rid.value.poke(4.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke(11.U) - dut.io.inReady.expect(false.B) - dut.io.accepted.expect(false.B) - } - } - - test("flush clears every stage of a dense safe ALU pipeline") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - for (rid <- 1 to 3) { - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_ADD.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(rid.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke((rid + 10).U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(2.U) - dut.io.in.src(1).valid.poke(true.B) - dut.io.in.src(1).operandClass.poke(OperandClass.P) - dut.io.in.src(1).archTag.poke(3.U) - dut.io.srcData(0).poke(rid.U) - dut.io.srcData(1).poke(rid.U) - dut.io.inValid.poke(true.B) - dut.io.inReady.expect(true.B) - if (rid == 1) { - dut.io.earlyReleaseValid.expect(false.B) - } else { - dut.io.earlyReleaseValid.expect(true.B) - dut.io.earlyReleaseRid.value.expect((rid - 1).U) - } - dut.clock.step() - } - - dut.io.inValid.poke(false.B) - dut.io.completeValid.expect(true.B) - dut.io.flushValid.poke(true.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.clock.step() - dut.io.flushValid.poke(false.B) - dut.io.completeValid.expect(false.B) - dut.io.earlyReleaseValid.expect(false.B) - dut.io.releaseValid.expect(false.B) - dut.io.busy.expect(false.B) - } - } - - test("LR.W uses scalar load lookup address and sign-extends the returned word") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(BigInt("80000000", 16).U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_LR_W.U) - dut.io.in.insnRaw.poke(BigInt("2000000b", 16).U) - dut.io.in.insnLen.poke(4.U) - dut.io.in.pc.poke(BigInt("40001000", 16).U) - dut.io.in.bid.valid.poke(true.B) - dut.io.in.bid.value.poke(1.U) - dut.io.in.gid.valid.poke(true.B) - dut.io.in.gid.value.poke(2.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(3.U) - dut.io.in.lsid.poke(5.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke(7.U) - dut.io.in.dst(0).physTag.poke(9.U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(4.U) - dut.io.srcData(0).poke(BigInt("0000000000002000", 16).U) - - dut.io.inReady.expect(true.B) - dut.io.inValid.poke(true.B) - dut.clock.step() - - dut.io.inValid.poke(false.B) - dut.io.loadLookupValid.expect(true.B) - dut.io.loadLookupAddr.expect(BigInt("0000000000002000", 16).U) - dut.io.loadLookupSize.expect(4.U) - dut.io.loadLookupReturnSignExtend.expect(true.B) - dut.io.loadLookupBid.value.expect(1.U) - dut.io.loadLookupGid.value.expect(2.U) - dut.io.loadLookupRid.value.expect(3.U) - dut.io.loadLookupLsId.expect(5.U) - - var cycles = 0 - while (!dut.io.completeValid.peek().litToBoolean && cycles < 8) { - dut.clock.step() - cycles += 1 - } - dut.io.completeValid.expect(true.B) - dut.io.unsupported.expect(false.B) - dut.io.completeDstPhysValid.expect(true.B) - dut.io.completeDstPhysTag.expect(9.U) - dut.io.completeDstData.expect(BigInt("ffffffff80000000", 16).U) - dut.io.completeRow.mem.valid.expect(true.B) - dut.io.completeRow.mem.isStore.expect(false.B) - dut.io.completeRow.mem.addr.expect(BigInt("0000000000002000", 16).U) - dut.io.completeRow.mem.rdata.expect(BigInt("ffffffff80000000", 16).U) - dut.io.completeRow.mem.size.expect(4.U) - } - } - - test("LR.W waits for the staged load-return data even when LIQ is enabled") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(true.B) - dut.io.loadLiqAccepted.poke(true.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_LR_W.U) - dut.io.in.insnRaw.poke(BigInt("2000000b", 16).U) - dut.io.in.insnLen.poke(4.U) - dut.io.in.pc.poke(BigInt("40001000", 16).U) - dut.io.in.bid.valid.poke(true.B) - dut.io.in.bid.value.poke(1.U) - dut.io.in.gid.valid.poke(true.B) - dut.io.in.gid.value.poke(2.U) - dut.io.in.rid.valid.poke(true.B) - dut.io.in.rid.value.poke(3.U) - dut.io.in.lsid.poke(5.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).physTag.poke(9.U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.srcData(0).poke(BigInt("0000000000002000", 16).U) - - dut.io.inValid.poke(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - - dut.io.loadLookupValid.expect(true.B) - dut.io.loadLiqEligible.expect(false.B) - dut.io.loadLookupWaitBlocked.poke(true.B) - dut.io.loadLookupData.poke(BigInt("000000007fffffff", 16).U) - dut.clock.step() - dut.io.completeValid.expect(false.B) - dut.io.loadWaitHold.expect(true.B) - - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLookupData.poke(BigInt("0000000080000000", 16).U) - dut.clock.step() - dut.clock.step() - - dut.io.completeValid.expect(true.B) - dut.io.completeDstPhysValid.expect(true.B) - dut.io.completeDstPhysTag.expect(9.U) - dut.io.completeDstData.expect(BigInt("ffffffff80000000", 16).U) - dut.io.completeRow.mem.valid.expect(true.B) - dut.io.completeRow.mem.rdata.expect(BigInt("ffffffff80000000", 16).U) - } - } - - test("generated execute datapath covers new scalar bit, min/max, multiply, and HL-immediate operations") { - val p = InterfaceParams(robEntries = 8, commitWidth = 2) - val trace = CommitTraceParams(commitWidth = 2, robValueWidth = p.robIndexWidth) - simulate(new ReducedScalarAluExecute(p, trace)) { dut => - dut.io.inValid.poke(false.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.srcData.foreach(_.poke(0.U)) - dut.io.loadLookupData.poke(0.U) - dut.io.loadPairFirstLookupData.poke(0.U) - dut.io.loadLookupWaitBlocked.poke(false.B) - dut.io.loadLiqEnable.poke(false.B) - dut.io.loadLiqAccepted.poke(false.B) - dut.io.stackPointerData.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.fretStkFallbackTargetValid.poke(false.B) - dut.io.fretStkFallbackTarget.poke(0.U) - dut.io.fretStkConditionValid.poke(false.B) - dut.io.fretStkConditionTaken.poke(false.B) - dut.io.completeReady.poke(true.B) - - def execute( - opcode: Int, - insn: BigInt, - src0: BigInt, - src1: BigInt, - expected: BigInt, - imm: BigInt = 0): Unit = { - dut.io.inReady.expect(true.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.opcode.poke(opcode.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).physTag.poke(7.U) - dut.io.in.insnRaw.poke(insn.U) - dut.io.in.imm.poke(imm.U) - dut.io.srcData(0).poke(src0.U) - dut.io.srcData(1).poke(src1.U) - dut.io.inValid.poke(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - var cycles = 0 - while (!dut.io.completeValid.peek().litToBoolean && cycles < 8) { - dut.clock.step() - cycles += 1 - } - dut.io.completeValid.expect(true.B) - dut.io.unsupported.expect(false.B) - dut.io.completeDstData.expect(expected.U) - dut.clock.step() - } - - val wrapFieldInsn = (BigInt(60) << 26) | (BigInt(7) << 20) - execute( - FrontendOpcodeDecodeTable.OP_BXU, - wrapFieldInsn, - (BigInt(1) << 60) | BigInt(1), - 0, - 0x11) - execute( - FrontendOpcodeDecodeTable.OP_BIC, - wrapFieldInsn, - BigInt("ffffffffffffffff", 16), - 0, - BigInt("0ffffffffffffff0", 16)) - execute( - FrontendOpcodeDecodeTable.OP_CTZ, - wrapFieldInsn, - BigInt(1) << 1, - 0, - 5) - execute( - FrontendOpcodeDecodeTable.OP_MAX, - 0, - BigInt("ffffffffffffffff", 16), - 1, - 1) - execute( - FrontendOpcodeDecodeTable.OP_MULUW, - 0, - BigInt("ffffffff", 16), - 2, - BigInt("fffffffffffffffe", 16)) - execute( - FrontendOpcodeDecodeTable.OP_HL_ADDIW, - 0, - BigInt("7fffffff", 16), - 0, - BigInt("ffffffff80000000", 16), - imm = 1) - execute( - FrontendOpcodeDecodeTable.OP_HL_ORI, - 0, - BigInt("0000000012340000", 16), - 0, - BigInt("ffffffffffffffff", 16), - imm = BigInt("ffffffffffffffff", 16)) - execute( - FrontendOpcodeDecodeTable.OP_HL_XORIW, - 0, - BigInt("000000007fffffff", 16), - 0, - BigInt("ffffffff80000000", 16), - imm = BigInt("ffffffffffffffff", 16)) - execute( - FrontendOpcodeDecodeTable.OP_C_SLLI, - 0, - BigInt("4000000000000001", 16), - 0, - BigInt("8000000000000002", 16), - imm = 1) - execute( - FrontendOpcodeDecodeTable.OP_C_SRLI, - 0, - BigInt("8000000000000002", 16), - 0, - BigInt("4000000000000001", 16), - imm = 1) - execute( - FrontendOpcodeDecodeTable.OP_HL_LIS, - 0, - 0, - 0, - BigInt("ffffffff80000001", 16), - imm = BigInt("ffffffff80000001", 16)) - execute( - FrontendOpcodeDecodeTable.OP_HL_LIU, - 0, - 0, - 0, - BigInt("0000000080000001", 16), - imm = BigInt("0000000080000001", 16)) - - dut.io.inReady.expect(true.B) - dut.io.in.poke(0.U.asTypeOf(dut.io.in)) - dut.io.in.valid.poke(true.B) - dut.io.in.pc.poke(BigInt("40005d32", 16).U) - dut.io.in.opcode.poke(FrontendOpcodeDecodeTable.OP_HL_SDI_PO.U) - dut.io.in.dispatchTarget.poke(DispatchTarget.Alu) - dut.io.in.imm.poke(BigInt("ffffffffffffffff", 16).U) - dut.io.in.insnLen.poke(6.U) - dut.io.in.dst(0).valid.poke(true.B) - dut.io.in.dst(0).kind.poke(DestinationKind.Gpr) - dut.io.in.dst(0).archTag.poke(3.U) - dut.io.in.dst(0).physTag.poke(17.U) - dut.io.in.src(0).valid.poke(true.B) - dut.io.in.src(0).operandClass.poke(OperandClass.P) - dut.io.in.src(0).archTag.poke(5.U) - dut.io.in.src(1).valid.poke(true.B) - dut.io.in.src(1).operandClass.poke(OperandClass.P) - dut.io.in.src(1).archTag.poke(6.U) - dut.io.srcData(0).poke(BigInt("0123456789abcdef", 16).U) - dut.io.srcData(1).poke(BigInt("00000000000166a0", 16).U) - dut.io.inValid.poke(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - var hlSdiPoCycles = 0 - while (!dut.io.completeValid.peek().litToBoolean && hlSdiPoCycles < 8) { - dut.clock.step() - hlSdiPoCycles += 1 - } - dut.io.completeValid.expect(true.B) - dut.io.unsupported.expect(false.B) - dut.io.completeDstPhysValid.expect(true.B) - dut.io.completeDstPhysTag.expect(17.U) - dut.io.completeDstData.expect(BigInt("0000000000016698", 16).U) - dut.io.completeRow.wb.valid.expect(true.B) - dut.io.completeRow.wb.reg.expect(3.U) - dut.io.completeRow.wb.data.expect(BigInt("0000000000016698", 16).U) - dut.io.completeRow.mem.valid.expect(true.B) - dut.io.completeRow.mem.isStore.expect(true.B) - dut.io.completeRow.mem.addr.expect(BigInt("00000000000166a0", 16).U) - dut.io.completeRow.mem.wdata.expect(BigInt("0123456789abcdef", 16).U) - dut.io.completeRow.mem.size.expect(8.U) - dut.clock.step() - } - } - - test("word and immediate shifts match ISA, QEMU, and LinxCoreModel semantics") { - val signExtendedMin = BigInt("ffffffff80000000", 16) - val signExtendedAllOnes = BigInt("ffffffffffffffff", 16) - - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SLLIW, - src0 = BigInt("1234567880000001", 16), - src1 = 0, - imm = 31).contains(signExtendedMin)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SLLW, - src0 = 1, - src1 = 63, - imm = 0).contains(signExtendedMin)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRLIW, - src0 = BigInt("ffffffff80000000", 16), - src1 = 0, - imm = 31).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRLW, - src0 = BigInt("ffffffff80000000", 16), - src1 = 63, - imm = 0).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRAIW, - src0 = BigInt("0000000080000000", 16), - src1 = 0, - imm = 31).contains(signExtendedAllOnes)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRAW, - src0 = BigInt("0000000080000000", 16), - src1 = 63, - imm = 0).contains(signExtendedAllOnes)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRLI, - src0 = BigInt("8000000000000000", 16), - src1 = 0, - imm = 63).contains(1)) - assert(ReducedScalarAluExecute.referenceResult( - FrontendOpcodeDecodeTable.OP_SRAI, - src0 = BigInt("8000000000000000", 16), - src1 = 0, - imm = 63).contains(signExtendedAllOnes)) - } - - test("FRET.STK only restores SP on the stack-return path") { - val outerFrameSp = BigInt("37028", 16) - assert(ReducedScalarAluExecute.referenceFretStkProducedSp( - stackPointerData = outerFrameSp, - frameSize = 16, - loadsReturn = false) == outerFrameSp) - assert(ReducedScalarAluExecute.referenceFretStkProducedSp( - stackPointerData = outerFrameSp, - frameSize = 16, - loadsReturn = true) == BigInt("37038", 16)) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluFretConditionProbeSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluFretConditionProbeSpec.scala deleted file mode 100644 index 1e3f4118..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluFretConditionProbeSpec.scala +++ /dev/null @@ -1,397 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.FrontendOpcodeDecodeTable -import org.scalatest.funsuite.AnyFunSuite - -import java.nio.charset.StandardCharsets -import java.nio.file.{Files, Path} -import scala.sys.process._ - -class ReducedScalarAluFretConditionProbeIO extends Bundle { - val inValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val imm = Input(UInt(64.W)) - val src0Data = Input(UInt(64.W)) - val src1Data = Input(UInt(64.W)) - val stackPointerData = Input(UInt(64.W)) - val loadLookupData = Input(UInt(64.W)) - val fretStkContextValid = Input(Bool()) - val fretStkConditionValid = Input(Bool()) - val fretStkConditionTaken = Input(Bool()) - val fretStkFallbackTargetValid = Input(Bool()) - val fretStkFallbackTarget = Input(UInt(64.W)) - val liveConditionValid = Input(Bool()) - val liveConditionTaken = Input(Bool()) - val flushValid = Input(Bool()) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val completeValid = Output(Bool()) - val branchConditionValid = Output(Bool()) - val branchConditionTaken = Output(Bool()) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(64.W)) - val redirectValid = Output(Bool()) - val redirectPc = Output(UInt(64.W)) - val unsupported = Output(Bool()) -} - -class ReducedScalarAluFretConditionProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluFretConditionProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := io.opcode - execute.io.in.dispatchTarget := DispatchTarget.Alu - execute.io.in.imm := io.imm - execute.io.in.immValid := true.B - execute.io.in.rid.valid := true.B - execute.io.in.rid.wrap := false.B - execute.io.in.rid.value := 3.U - execute.io.in.bid.valid := true.B - execute.io.in.bid.wrap := false.B - execute.io.in.bid.value := 1.U - execute.io.in.gid.valid := true.B - execute.io.in.gid.wrap := false.B - execute.io.in.gid.value := 2.U - execute.io.in.lsid := 0.U - execute.io.in.isLoad := false.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := 4.U - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := 0x55.U - execute.io.in.fretStkContextValid := io.fretStkContextValid - execute.io.in.fretStkConditionValid := io.fretStkConditionValid - execute.io.in.fretStkConditionTaken := io.fretStkConditionTaken - execute.io.in.fretStkFallbackTargetValid := io.fretStkFallbackTargetValid - execute.io.in.fretStkFallbackTarget := io.fretStkFallbackTarget - for (idx <- 0 until 2) { - execute.io.in.src(idx).valid := true.B - execute.io.in.src(idx).operandClass := OperandClass.P - execute.io.in.src(idx).archTag := idx.U - execute.io.in.src(idx).physTag := (idx + 10).U - execute.io.in.src(idx).ready := true.B - } - - execute.io.srcData(0) := io.src0Data - execute.io.srcData(1) := io.src1Data - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := io.loadLookupData - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := io.stackPointerData - execute.io.flushValid := io.flushValid - execute.io.fretStkFallbackTargetValid := io.fretStkFallbackTargetValid - execute.io.fretStkFallbackTarget := io.fretStkFallbackTarget - execute.io.fretStkConditionValid := io.liveConditionValid - execute.io.fretStkConditionTaken := io.liveConditionTaken - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.completeValid := execute.io.completeValid - io.branchConditionValid := execute.io.branchConditionValid - io.branchConditionTaken := execute.io.branchConditionTaken - io.loadLookupValid := execute.io.loadLookupValid - io.loadLookupAddr := execute.io.loadLookupAddr - io.redirectValid := execute.io.redirectValid - io.redirectPc := execute.io.redirectPc - io.unsupported := execute.io.unsupported -} - -object ReducedScalarAluFretConditionReference { - final case class Result(loadReturn: Boolean, redirect: Boolean) - - def apply( - contextValid: Boolean, - snapshotConditionValid: Boolean, - snapshotConditionTaken: Boolean, - liveConditionValid: Boolean, - liveConditionTaken: Boolean, - fallbackTargetValid: Boolean): Result = { - val conditionValid = if (contextValid) snapshotConditionValid else liveConditionValid - val conditionTaken = if (contextValid) snapshotConditionTaken else liveConditionTaken - val loadReturn = conditionValid && !conditionTaken && fallbackTargetValid - val redirect = fallbackTargetValid && conditionValid && conditionTaken - Result(loadReturn = loadReturn, redirect = redirect) - } -} - -class ReducedScalarAluFretConditionProbeSpec extends AnyFunSuite { - private val fretStkRaInsn = BigInt("02a53041", 16) - private val setcNeInsn = BigInt("00000000", 16) - private val fallbackPc = BigInt("12988", 16) - - private def writeUtf8(path: Path, text: String): Unit = - Files.write(path, text.getBytes(StandardCharsets.UTF_8)) - - private def compileAndRunHarness(harnessName: String, harnessBody: String): Unit = { - val dir = Files.createTempDirectory("linxcore-fret-condition-probe-") - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarAluFretConditionProbe) - writeUtf8(dir.resolve("ReducedScalarAluFretConditionProbe.sv"), sv) - writeUtf8(dir.resolve("layers-ReducedScalarAluFretConditionProbe-Verification.sv"), "") - writeUtf8(dir.resolve(s"$harnessName.cpp"), harnessBody) - val cmd = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--Mdir", - dir.resolve("obj_dir").toString, - "-Wno-fatal", - dir.resolve("ReducedScalarAluFretConditionProbe.sv").toString, - dir.resolve(s"$harnessName.cpp").toString, - "--top-module", - "ReducedScalarAluFretConditionProbe") - val status = Process(cmd, dir.toFile).! - assert(status == 0, s"verilator harness $harnessName failed with status $status in $dir") - } - - private def baseHarness(body: String): String = - s""" -#include "VReducedScalarAluFretConditionProbe.h" -#include "verilated.h" -#include - -static void eval_cycle(VReducedScalarAluFretConditionProbe& top) { - top.eval(); -} - -static void tick(VReducedScalarAluFretConditionProbe& top) { - top.clock = 0; - top.eval(); - top.clock = 1; - top.eval(); - top.clock = 0; - top.eval(); -} - -static void clear_inputs(VReducedScalarAluFretConditionProbe& top) { - top.io_inValid = 0; - top.io_opcode = 0; - top.io_pc = 0; - top.io_insnRaw = 0; - top.io_imm = 0; - top.io_src0Data = 0; - top.io_src1Data = 0; - top.io_stackPointerData = 0; - top.io_loadLookupData = 0; - top.io_fretStkContextValid = 0; - top.io_fretStkConditionValid = 0; - top.io_fretStkConditionTaken = 0; - top.io_fretStkFallbackTargetValid = 0; - top.io_fretStkFallbackTarget = 0; - top.io_liveConditionValid = 0; - top.io_liveConditionTaken = 0; - top.io_flushValid = 0; -} - -static void reset(VReducedScalarAluFretConditionProbe& top) { - clear_inputs(top); - top.reset = 1; - tick(top); - tick(top); - top.reset = 0; - tick(top); -} - -static void drive_fret(VReducedScalarAluFretConditionProbe& top, - bool context_valid, - bool snapshot_valid, - bool snapshot_taken, - bool live_valid, - bool live_taken, - bool fallback_valid = true) { - clear_inputs(top); - top.io_inValid = 1; - top.io_opcode = ${FrontendOpcodeDecodeTable.OP_FRET_STK}; - top.io_pc = 0x1299aULL; - top.io_insnRaw = 0x${fretStkRaInsn.toString(16)}ULL; - top.io_imm = 8; - top.io_stackPointerData = 0x388d0ULL; - top.io_loadLookupData = 0x12345678ULL; - top.io_fretStkContextValid = context_valid; - top.io_fretStkConditionValid = snapshot_valid; - top.io_fretStkConditionTaken = snapshot_taken; - top.io_fretStkFallbackTargetValid = fallback_valid; - top.io_fretStkFallbackTarget = 0x${fallbackPc.toString(16)}ULL; - top.io_liveConditionValid = live_valid; - top.io_liveConditionTaken = live_taken; -} - -int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluFretConditionProbe top; - reset(top); - $body - top.final(); - return 0; -} -""" - - test("does not fire FRET when context is invalid and no live SETC condition exists") { - val expected = ReducedScalarAluFretConditionReference( - contextValid = false, - snapshotConditionValid = false, - snapshotConditionTaken = false, - liveConditionValid = false, - liveConditionTaken = false, - fallbackTargetValid = true) - assert(!expected.loadReturn) - assert(!expected.redirect) - - compileAndRunHarness( - "fret_no_condition", - baseHarness(""" - drive_fret(top, false, false, false, false, false); - eval_cycle(top); - if (!top.io_inReady) return 10; - tick(top); - clear_inputs(top); - bool saw_load = false; - bool saw_redirect = false; - for (int i = 0; i < 5; ++i) { - eval_cycle(top); - saw_load = saw_load || top.io_loadLookupValid; - saw_redirect = saw_redirect || top.io_redirectValid; - tick(top); - } - if (saw_load) return 11; - if (saw_redirect) return 12; -""")) - } - - test("allows FRET to fire from a same-cycle W2 SETC condition") { - val expected = ReducedScalarAluFretConditionReference( - contextValid = false, - snapshotConditionValid = false, - snapshotConditionTaken = false, - liveConditionValid = true, - liveConditionTaken = true, - fallbackTargetValid = true) - assert(!expected.loadReturn) - assert(expected.redirect) - - compileAndRunHarness( - "fret_w2_condition", - baseHarness(s""" - clear_inputs(top); - top.io_inValid = 1; - top.io_opcode = ${FrontendOpcodeDecodeTable.OP_C_SETC_NE}; - top.io_pc = 0x12998ULL; - top.io_insnRaw = 0x${setcNeInsn.toString(16)}ULL; - top.io_src0Data = 0x44ULL; - top.io_src1Data = 0x0ULL; - eval_cycle(top); - if (!top.io_inReady) return 20; - tick(top); - clear_inputs(top); - tick(top); - drive_fret(top, false, false, false, false, false); - eval_cycle(top); - if (!top.io_inReady) return 21; - tick(top); - clear_inputs(top); - eval_cycle(top); - if (!top.io_branchConditionValid) return 22; - if (!top.io_branchConditionTaken) return 23; - bool saw_redirect = false; - for (int i = 0; i < 5; ++i) { - eval_cycle(top); - saw_redirect = saw_redirect || (top.io_redirectValid && top.io_redirectPc == 0x${fallbackPc.toString(16)}ULL); - tick(top); - } - if (!saw_redirect) return 24; -""")) - } - - test("allows FRET to fire from a latched live condition") { - val expected = ReducedScalarAluFretConditionReference( - contextValid = false, - snapshotConditionValid = false, - snapshotConditionTaken = false, - liveConditionValid = true, - liveConditionTaken = true, - fallbackTargetValid = true) - assert(!expected.loadReturn) - assert(expected.redirect) - - compileAndRunHarness( - "fret_latched_condition", - baseHarness(s""" - drive_fret(top, false, false, false, true, true); - eval_cycle(top); - if (!top.io_inReady) return 30; - tick(top); - clear_inputs(top); - bool saw_redirect = false; - for (int i = 0; i < 5; ++i) { - eval_cycle(top); - saw_redirect = saw_redirect || (top.io_redirectValid && top.io_redirectPc == 0x${fallbackPc.toString(16)}ULL); - tick(top); - } - if (!saw_redirect) return 31; -""")) - } - - test("an explicit empty FRET snapshot ignores a younger live marker target") { - compileAndRunHarness( - "fret_empty_snapshot", - baseHarness(s""" - drive_fret(top, true, false, false, false, false, false); - eval_cycle(top); - if (!top.io_inReady) return 40; - tick(top); - - // Model decode installing an unrelated younger marker in the cycle after - // issue. The accepted FRET snapshot says that neither a condition nor a - // fallback target belonged to this return, so it must load RA instead of - // redirecting to the new marker. - clear_inputs(top); - top.io_fretStkFallbackTargetValid = 1; - top.io_fretStkFallbackTarget = 0x${fallbackPc.toString(16)}ULL; - top.io_liveConditionValid = 1; - top.io_liveConditionTaken = 1; - top.io_loadLookupData = 0x12345678ULL; - bool saw_load = false; - bool saw_return = false; - bool saw_younger_redirect = false; - for (int i = 0; i < 6; ++i) { - eval_cycle(top); - saw_load = saw_load || top.io_loadLookupValid; - saw_return = saw_return || (top.io_redirectValid && top.io_redirectPc == 0x12345678ULL); - saw_younger_redirect = saw_younger_redirect || - (top.io_redirectValid && top.io_redirectPc == 0x${fallbackPc.toString(16)}ULL); - tick(top); - } - if (!saw_load) return 41; - if (!saw_return) return 42; - if (saw_younger_redirect) return 43; -""")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluHlSdiPrProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluHlSdiPrProbe.scala deleted file mode 100644 index cb07afb8..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluHlSdiPrProbe.scala +++ /dev/null @@ -1,251 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.{FrontendOpcodeDecodeTable, FrontendRegAliasClassify} - -class ReducedScalarAluHlSdiPrProbeIO extends Bundle { - val inValid = Input(Bool()) - val flushValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnLen = Input(UInt(4.W)) - val insnRaw = Input(UInt(64.W)) - val imm = Input(UInt(64.W)) - val srcDData = Input(UInt(64.W)) - val srcRData = Input(UInt(64.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val srcDArchTag = Input(UInt(6.W)) - val srcDPhysTag = Input(UInt(6.W)) - val srcRArchTag = Input(UInt(6.W)) - val srcRPhysTag = Input(UInt(6.W)) - val dstValid = Input(Bool()) - val dstArchTag = Input(UInt(6.W)) - val dstPhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val loadWaitHold = Output(Bool()) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(64.W)) - val loadLookupSize = Output(UInt(4.W)) - val loadLiqEligible = Output(Bool()) - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeSrc1PhysValid = Output(Bool()) - val completeSrc1PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowSrc1Reg = Output(UInt(8.W)) - val completeRowSrc1Data = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(8.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(8.W)) - val completeRowWbData = Output(UInt(64.W)) - val completeRowMemValid = Output(Bool()) - val completeRowMemIsStore = Output(Bool()) - val completeRowMemAddr = Output(UInt(64.W)) - val completeRowMemWdata = Output(UInt(64.W)) - val completeRowMemRdata = Output(UInt(64.W)) - val completeRowMemSize = Output(UInt(4.W)) - val branchConditionValid = Output(Bool()) - val redirectValid = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) - val liqReleaseValid = Output(Bool()) -} - -class ReducedScalarAluHlSdiPrProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluHlSdiPrProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - val classifiedDst = FrontendRegAliasClassify.destination(p, io.dstValid, io.dstArchTag) - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := io.opcode - execute.io.in.dispatchTarget := DispatchTarget.Lsu - execute.io.in.imm := io.imm - execute.io.in.immValid := true.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := false.B - execute.io.in.isStore := true.B - execute.io.in.insnLen := io.insnLen - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.srcDArchTag - execute.io.in.src(0).physTag := io.srcDPhysTag - execute.io.in.src(0).ready := true.B - execute.io.in.src(1).valid := true.B - execute.io.in.src(1).operandClass := OperandClass.P - execute.io.in.src(1).archTag := io.srcRArchTag - execute.io.in.src(1).physTag := io.srcRPhysTag - execute.io.in.src(1).ready := true.B - execute.io.in.dst(0).valid := io.dstValid - execute.io.in.dst(0).kind := classifiedDst.kind - execute.io.in.dst(0).archTag := classifiedDst.archTag - execute.io.in.dst(0).relTag := classifiedDst.relTag - execute.io.in.dst(0).physTag := io.dstPhysTag - - execute.io.srcData(0) := io.srcDData - execute.io.srcData(1) := io.srcRData - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := 0.U - execute.io.flushValid := io.flushValid - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.loadWaitHold := execute.io.loadWaitHold - io.loadLookupValid := execute.io.loadLookupValid - io.loadLookupAddr := execute.io.loadLookupAddr - io.loadLookupSize := execute.io.loadLookupSize - io.loadLiqEligible := execute.io.loadLiqEligible - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeSrc1PhysValid := execute.io.completeSrcPhysValid(1) - io.completeSrc1PhysTag := execute.io.completeSrcPhysTag(1) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowSrc1Reg := execute.io.completeRow.src1.reg - io.completeRowSrc1Data := execute.io.completeRow.src1.data - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.completeRowMemValid := execute.io.completeRow.mem.valid - io.completeRowMemIsStore := execute.io.completeRow.mem.isStore - io.completeRowMemAddr := execute.io.completeRow.mem.addr - io.completeRowMemWdata := execute.io.completeRow.mem.wdata - io.completeRowMemRdata := execute.io.completeRow.mem.rdata - io.completeRowMemSize := execute.io.completeRow.mem.size - io.branchConditionValid := execute.io.branchConditionValid - io.redirectValid := execute.io.redirectValid - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid - io.liqReleaseValid := execute.io.liqReleaseValid -} - -object EmitReducedScalarAluHlSdiPrProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-hl-sdi-pr-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluHlSdiPrProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluLbuProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluLbuProbe.scala deleted file mode 100644 index 6b005229..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluLbuProbe.scala +++ /dev/null @@ -1,308 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.{FrontendOpcodeDecodeTable, FrontendRegAliasClassify} - -class ReducedScalarAluLbuProbeIO extends Bundle { - val inValid = Input(Bool()) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val srcLData = Input(UInt(64.W)) - val srcRData = Input(UInt(64.W)) - val loadLookupData = Input(UInt(64.W)) - val loadLookupWaitBlocked = Input(Bool()) - val loadLiqEnable = Input(Bool()) - val loadLiqAccepted = Input(Bool()) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val srcLArchTag = Input(UInt(6.W)) - val srcLPhysTag = Input(UInt(6.W)) - val srcRArchTag = Input(UInt(6.W)) - val srcRPhysTag = Input(UInt(6.W)) - val dstArchTag = Input(UInt(6.W)) - val dstPhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val loadWaitHold = Output(Bool()) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(64.W)) - val loadLookupSize = Output(UInt(4.W)) - val loadLookupReturnSignExtend = Output(Bool()) - val loadLiqEligible = Output(Bool()) - val loadLookupPc = Output(UInt(64.W)) - val loadLookupBidValid = Output(Bool()) - val loadLookupBidWrap = Output(Bool()) - val loadLookupBidValue = Output(UInt(6.W)) - val loadLookupGidValid = Output(Bool()) - val loadLookupGidWrap = Output(Bool()) - val loadLookupGidValue = Output(UInt(6.W)) - val loadLookupRidValid = Output(Bool()) - val loadLookupRidWrap = Output(Bool()) - val loadLookupRidValue = Output(UInt(6.W)) - val loadLookupLsId = Output(UInt(32.W)) - val loadLookupDstValid = Output(Bool()) - val loadLookupDstKind = Output(UInt(2.W)) - val loadLookupDstArchTag = Output(UInt(6.W)) - val loadLookupDstPhysTag = Output(UInt(6.W)) - val loadLookupSourceTraceValid = Output(Bool()) - val loadLookupSource0Valid = Output(Bool()) - val loadLookupSource0Reg = Output(UInt(8.W)) - val loadLookupSource0Data = Output(UInt(64.W)) - val loadLookupSource1Valid = Output(Bool()) - val loadLookupSource1Reg = Output(UInt(8.W)) - val loadLookupSource1Data = Output(UInt(64.W)) - - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeSrc1PhysValid = Output(Bool()) - val completeSrc1PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowSrc1Reg = Output(UInt(8.W)) - val completeRowSrc1Data = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(8.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(8.W)) - val completeRowWbData = Output(UInt(64.W)) - val completeRowMemValid = Output(Bool()) - val completeRowMemIsStore = Output(Bool()) - val completeRowMemAddr = Output(UInt(64.W)) - val completeRowMemRdata = Output(UInt(64.W)) - val completeRowMemSize = Output(UInt(4.W)) - val branchConditionValid = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) - val liqReleaseValid = Output(Bool()) - val liqReleaseBidValid = Output(Bool()) - val liqReleaseBidWrap = Output(Bool()) - val liqReleaseBidValue = Output(UInt(6.W)) - val liqReleaseRidValid = Output(Bool()) - val liqReleaseRidWrap = Output(Bool()) - val liqReleaseRidValue = Output(UInt(6.W)) - val liqReleaseStid = Output(UInt(8.W)) -} - -class ReducedScalarAluLbuProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluLbuProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := FrontendOpcodeDecodeTable.OP_LBU.U - execute.io.in.dispatchTarget := DispatchTarget.Lsu - execute.io.in.imm := 0.U - execute.io.in.immValid := false.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := true.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := 4.U - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.srcLArchTag - execute.io.in.src(0).physTag := io.srcLPhysTag - execute.io.in.src(0).ready := true.B - execute.io.in.src(1).valid := true.B - execute.io.in.src(1).operandClass := OperandClass.P - execute.io.in.src(1).archTag := io.srcRArchTag - execute.io.in.src(1).physTag := io.srcRPhysTag - execute.io.in.src(1).ready := true.B - val classifiedDst = FrontendRegAliasClassify.destination(p, true.B, io.dstArchTag) - execute.io.in.dst(0).valid := true.B - execute.io.in.dst(0).kind := classifiedDst.kind - execute.io.in.dst(0).archTag := classifiedDst.archTag - execute.io.in.dst(0).relTag := classifiedDst.relTag - execute.io.in.dst(0).physTag := io.dstPhysTag - - execute.io.srcData(0) := io.srcLData - execute.io.srcData(1) := io.srcRData - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := io.loadLookupData - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := io.loadLookupWaitBlocked - execute.io.loadLiqEnable := io.loadLiqEnable - execute.io.loadLiqAccepted := io.loadLiqAccepted - execute.io.stackPointerData := 0.U - execute.io.flushValid := false.B - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.loadWaitHold := execute.io.loadWaitHold - io.loadLookupValid := execute.io.loadLookupValid - io.loadLookupAddr := execute.io.loadLookupAddr - io.loadLookupSize := execute.io.loadLookupSize - io.loadLookupReturnSignExtend := execute.io.loadLookupReturnSignExtend - io.loadLiqEligible := execute.io.loadLiqEligible - io.loadLookupPc := execute.io.loadLookupPc - io.loadLookupBidValid := execute.io.loadLookupBid.valid - io.loadLookupBidWrap := execute.io.loadLookupBid.wrap - io.loadLookupBidValue := execute.io.loadLookupBid.value - io.loadLookupGidValid := execute.io.loadLookupGid.valid - io.loadLookupGidWrap := execute.io.loadLookupGid.wrap - io.loadLookupGidValue := execute.io.loadLookupGid.value - io.loadLookupRidValid := execute.io.loadLookupRid.valid - io.loadLookupRidWrap := execute.io.loadLookupRid.wrap - io.loadLookupRidValue := execute.io.loadLookupRid.value - io.loadLookupLsId := execute.io.loadLookupLsId - io.loadLookupDstValid := execute.io.loadLookupDst.valid - io.loadLookupDstKind := execute.io.loadLookupDst.kind.asUInt - io.loadLookupDstArchTag := execute.io.loadLookupDst.archTag - io.loadLookupDstPhysTag := execute.io.loadLookupDst.physTag - io.loadLookupSourceTraceValid := execute.io.loadLookupSourceTraceValid - io.loadLookupSource0Valid := execute.io.loadLookupSource0.valid - io.loadLookupSource0Reg := execute.io.loadLookupSource0.reg - io.loadLookupSource0Data := execute.io.loadLookupSource0.data - io.loadLookupSource1Valid := execute.io.loadLookupSource1.valid - io.loadLookupSource1Reg := execute.io.loadLookupSource1.reg - io.loadLookupSource1Data := execute.io.loadLookupSource1.data - - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeSrc1PhysValid := execute.io.completeSrcPhysValid(1) - io.completeSrc1PhysTag := execute.io.completeSrcPhysTag(1) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowSrc1Reg := execute.io.completeRow.src1.reg - io.completeRowSrc1Data := execute.io.completeRow.src1.data - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.completeRowMemValid := execute.io.completeRow.mem.valid - io.completeRowMemIsStore := execute.io.completeRow.mem.isStore - io.completeRowMemAddr := execute.io.completeRow.mem.addr - io.completeRowMemRdata := execute.io.completeRow.mem.rdata - io.completeRowMemSize := execute.io.completeRow.mem.size - io.branchConditionValid := execute.io.branchConditionValid - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid - io.liqReleaseValid := execute.io.liqReleaseValid - io.liqReleaseBidValid := execute.io.liqReleaseBid.valid - io.liqReleaseBidWrap := execute.io.liqReleaseBid.wrap - io.liqReleaseBidValue := execute.io.liqReleaseBid.value - io.liqReleaseRidValid := execute.io.liqReleaseRid.valid - io.liqReleaseRidWrap := execute.io.liqReleaseRid.wrap - io.liqReleaseRidValue := execute.io.liqReleaseRid.value - io.liqReleaseStid := execute.io.liqReleaseStid -} - -object EmitReducedScalarAluLbuProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-lbu-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluLbuProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSbProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSbProbe.scala deleted file mode 100644 index 036bec58..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSbProbe.scala +++ /dev/null @@ -1,258 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.FrontendOpcodeDecodeTable - -class ReducedScalarAluSbProbeIO extends Bundle { - val inValid = Input(Bool()) - val flushValid = Input(Bool()) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val srcDData = Input(UInt(64.W)) - val srcLData = Input(UInt(64.W)) - val srcRData = Input(UInt(64.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val srcDArchTag = Input(UInt(6.W)) - val srcDPhysTag = Input(UInt(6.W)) - val srcLArchTag = Input(UInt(6.W)) - val srcLPhysTag = Input(UInt(6.W)) - val srcRArchTag = Input(UInt(6.W)) - val srcRPhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val loadWaitHold = Output(Bool()) - val loadLookupValid = Output(Bool()) - val loadLookupAddr = Output(UInt(64.W)) - val loadLookupSize = Output(UInt(4.W)) - val loadLiqEligible = Output(Bool()) - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeSrc1PhysValid = Output(Bool()) - val completeSrc1PhysTag = Output(UInt(6.W)) - val completeSrc2PhysValid = Output(Bool()) - val completeSrc2PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowSrc1Reg = Output(UInt(8.W)) - val completeRowSrc1Data = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowWbValid = Output(Bool()) - val completeRowMemValid = Output(Bool()) - val completeRowMemIsStore = Output(Bool()) - val completeRowMemAddr = Output(UInt(64.W)) - val completeRowMemWdata = Output(UInt(64.W)) - val completeRowMemRdata = Output(UInt(64.W)) - val completeRowMemSize = Output(UInt(4.W)) - val branchConditionValid = Output(Bool()) - val redirectValid = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) - val liqReleaseValid = Output(Bool()) - val liqReleaseBidValid = Output(Bool()) - val liqReleaseBidWrap = Output(Bool()) - val liqReleaseBidValue = Output(UInt(6.W)) - val liqReleaseRidValid = Output(Bool()) - val liqReleaseRidWrap = Output(Bool()) - val liqReleaseRidValue = Output(UInt(6.W)) - val liqReleaseStid = Output(UInt(8.W)) -} - -class ReducedScalarAluSbProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluSbProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := FrontendOpcodeDecodeTable.OP_SB.U - execute.io.in.dispatchTarget := DispatchTarget.Lsu - execute.io.in.imm := 0.U - execute.io.in.immValid := false.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := false.B - execute.io.in.isStore := true.B - execute.io.in.insnLen := 4.U - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.srcDArchTag - execute.io.in.src(0).physTag := io.srcDPhysTag - execute.io.in.src(0).ready := true.B - execute.io.in.src(1).valid := true.B - execute.io.in.src(1).operandClass := OperandClass.P - execute.io.in.src(1).archTag := io.srcLArchTag - execute.io.in.src(1).physTag := io.srcLPhysTag - execute.io.in.src(1).ready := true.B - execute.io.in.src(2).valid := true.B - execute.io.in.src(2).operandClass := OperandClass.P - execute.io.in.src(2).archTag := io.srcRArchTag - execute.io.in.src(2).physTag := io.srcRPhysTag - execute.io.in.src(2).ready := true.B - execute.io.in.dst(0).valid := false.B - - execute.io.srcData(0) := io.srcDData - execute.io.srcData(1) := io.srcLData - execute.io.srcData(2) := io.srcRData - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := 0.U - execute.io.flushValid := io.flushValid - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.loadWaitHold := execute.io.loadWaitHold - io.loadLookupValid := execute.io.loadLookupValid - io.loadLookupAddr := execute.io.loadLookupAddr - io.loadLookupSize := execute.io.loadLookupSize - io.loadLiqEligible := execute.io.loadLiqEligible - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeSrc1PhysValid := execute.io.completeSrcPhysValid(1) - io.completeSrc1PhysTag := execute.io.completeSrcPhysTag(1) - io.completeSrc2PhysValid := execute.io.completeSrcPhysValid(2) - io.completeSrc2PhysTag := execute.io.completeSrcPhysTag(2) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowSrc1Reg := execute.io.completeRow.src1.reg - io.completeRowSrc1Data := execute.io.completeRow.src1.data - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowMemValid := execute.io.completeRow.mem.valid - io.completeRowMemIsStore := execute.io.completeRow.mem.isStore - io.completeRowMemAddr := execute.io.completeRow.mem.addr - io.completeRowMemWdata := execute.io.completeRow.mem.wdata - io.completeRowMemRdata := execute.io.completeRow.mem.rdata - io.completeRowMemSize := execute.io.completeRow.mem.size - io.branchConditionValid := execute.io.branchConditionValid - io.redirectValid := execute.io.redirectValid - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid - io.liqReleaseValid := execute.io.liqReleaseValid - io.liqReleaseBidValid := execute.io.liqReleaseBid.valid - io.liqReleaseBidWrap := execute.io.liqReleaseBid.wrap - io.liqReleaseBidValue := execute.io.liqReleaseBid.value - io.liqReleaseRidValid := execute.io.liqReleaseRid.valid - io.liqReleaseRidWrap := execute.io.liqReleaseRid.wrap - io.liqReleaseRidValue := execute.io.liqReleaseRid.value - io.liqReleaseStid := execute.io.liqReleaseStid -} - -object EmitReducedScalarAluSbProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-sb-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluSbProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcCompareProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcCompareProbe.scala deleted file mode 100644 index 5a7255b4..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcCompareProbe.scala +++ /dev/null @@ -1,214 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} - -class ReducedScalarAluSetcCompareProbeIO extends Bundle { - val inValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val src0Data = Input(UInt(64.W)) - val src1Data = Input(UInt(64.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val src0ArchTag = Input(UInt(6.W)) - val src0PhysTag = Input(UInt(6.W)) - val src1ArchTag = Input(UInt(6.W)) - val src1PhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeSrc1PhysValid = Output(Bool()) - val completeSrc1PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowSrc1Reg = Output(UInt(8.W)) - val completeRowSrc1Data = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(8.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(8.W)) - val completeRowWbData = Output(UInt(64.W)) - val branchConditionValid = Output(Bool()) - val branchConditionTaken = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) -} - -class ReducedScalarAluSetcCompareProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluSetcCompareProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := io.opcode - execute.io.in.dispatchTarget := DispatchTarget.Alu - execute.io.in.imm := 0.U - execute.io.in.immValid := false.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := false.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := 4.U - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.src0ArchTag - execute.io.in.src(0).physTag := io.src0PhysTag - execute.io.in.src(0).ready := true.B - execute.io.in.src(1).valid := true.B - execute.io.in.src(1).operandClass := OperandClass.P - execute.io.in.src(1).archTag := io.src1ArchTag - execute.io.in.src(1).physTag := io.src1PhysTag - execute.io.in.src(1).ready := true.B - - execute.io.srcData(0) := io.src0Data - execute.io.srcData(1) := io.src1Data - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := 0.U - execute.io.flushValid := false.B - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeSrc1PhysValid := execute.io.completeSrcPhysValid(1) - io.completeSrc1PhysTag := execute.io.completeSrcPhysTag(1) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowSrc1Reg := execute.io.completeRow.src1.reg - io.completeRowSrc1Data := execute.io.completeRow.src1.data - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.branchConditionValid := execute.io.branchConditionValid - io.branchConditionTaken := execute.io.branchConditionTaken - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid -} - -object EmitReducedScalarAluSetcCompareProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-setc-compare-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluSetcCompareProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcImmediateBehaviorProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcImmediateBehaviorProbe.scala deleted file mode 100644 index cb4ebde9..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcImmediateBehaviorProbe.scala +++ /dev/null @@ -1,219 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.commit.CommitTraceParams -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.FrontendOpcodeDecodeTable - -class ReducedScalarAluSetcImmediateBehaviorProbeIO extends Bundle { - val inValid = Input(Bool()) - val flushValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val imm = Input(UInt(64.W)) - val src0Data = Input(UInt(64.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val lsid = Input(UInt(32.W)) - val blockBid = Input(UInt(64.W)) - val src0ArchTag = Input(UInt(6.W)) - val src0PhysTag = Input(UInt(6.W)) - - val inReady = Output(Bool()) - val accepted = Output(Bool()) - val busy = Output(Bool()) - val unsupported = Output(Bool()) - val unsupportedOpcode = Output(UInt(12.W)) - val completeValid = Output(Bool()) - val completeRobValue = Output(UInt(6.W)) - val completeLsId = Output(UInt(32.W)) - val completeDstPhysValid = Output(Bool()) - val completeDstPhysTag = Output(UInt(6.W)) - val completeDstData = Output(UInt(64.W)) - val completeSrc0PhysValid = Output(Bool()) - val completeSrc0PhysTag = Output(UInt(6.W)) - val completeSrc1PhysValid = Output(Bool()) - val completeSrc1PhysTag = Output(UInt(6.W)) - val completeRowValid = Output(Bool()) - val completeRowBid = Output(UInt(32.W)) - val completeRowGid = Output(UInt(32.W)) - val completeRowRid = Output(UInt(32.W)) - val completeRowRobValid = Output(Bool()) - val completeRowRobWrap = Output(Bool()) - val completeRowRobValue = Output(UInt(6.W)) - val completeRowBlockBidValid = Output(Bool()) - val completeRowBlockBid = Output(UInt(64.W)) - val completeRowPc = Output(UInt(64.W)) - val completeRowInsn = Output(UInt(64.W)) - val completeRowLen = Output(UInt(4.W)) - val completeRowSrc0Valid = Output(Bool()) - val completeRowSrc0Reg = Output(UInt(8.W)) - val completeRowSrc0Data = Output(UInt(64.W)) - val completeRowSrc1Valid = Output(Bool()) - val completeRowSrc1Reg = Output(UInt(8.W)) - val completeRowSrc1Data = Output(UInt(64.W)) - val completeRowDstValid = Output(Bool()) - val completeRowDstReg = Output(UInt(8.W)) - val completeRowDstData = Output(UInt(64.W)) - val completeRowWbValid = Output(Bool()) - val completeRowWbReg = Output(UInt(8.W)) - val completeRowWbData = Output(UInt(64.W)) - val branchConditionValid = Output(Bool()) - val branchConditionTaken = Output(Bool()) - val releaseValid = Output(Bool()) - val releaseBidValid = Output(Bool()) - val releaseBidWrap = Output(Bool()) - val releaseBidValue = Output(UInt(6.W)) - val releaseGidValid = Output(Bool()) - val releaseGidWrap = Output(Bool()) - val releaseGidValue = Output(UInt(6.W)) - val releaseRidValid = Output(Bool()) - val releaseRidWrap = Output(Bool()) - val releaseRidValue = Output(UInt(6.W)) - val releaseStid = Output(UInt(8.W)) -} - -class ReducedScalarAluSetcImmediateBehaviorProbe extends Module { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - val io = IO(new ReducedScalarAluSetcImmediateBehaviorProbeIO) - val execute = Module(new ReducedScalarAluExecute(p, trace)) - execute.io.completeReady := true.B - - execute.io.inValid := io.inValid - execute.io.in := 0.U.asTypeOf(execute.io.in) - execute.io.in.valid := io.inValid - execute.io.in.peId := 0.U - execute.io.in.threadId := 0.U - execute.io.in.pc := io.pc - execute.io.in.opcode := io.opcode - execute.io.in.dispatchTarget := DispatchTarget.Alu - execute.io.in.imm := io.imm - execute.io.in.immValid := true.B - execute.io.in.rid.valid := io.ridValid - execute.io.in.rid.wrap := io.ridWrap - execute.io.in.rid.value := io.ridValue - execute.io.in.bid.valid := io.bidValid - execute.io.in.bid.wrap := io.bidWrap - execute.io.in.bid.value := io.bidValue - execute.io.in.gid.valid := io.gidValid - execute.io.in.gid.wrap := io.gidWrap - execute.io.in.gid.value := io.gidValue - execute.io.in.lsid := io.lsid - execute.io.in.isLoad := false.B - execute.io.in.isStore := false.B - execute.io.in.insnLen := Mux( - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_ANDI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_EQI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_GEI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_GEUI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_LTI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_LTUI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_NEI.U || - io.opcode === FrontendOpcodeDecodeTable.OP_HL_SETC_ORI.U, - 6.U, - 4.U) - execute.io.in.insnRaw := io.insnRaw - execute.io.in.blockBidValid := true.B - execute.io.in.blockBid := io.blockBid - execute.io.in.src(0).valid := true.B - execute.io.in.src(0).operandClass := OperandClass.P - execute.io.in.src(0).archTag := io.src0ArchTag - execute.io.in.src(0).physTag := io.src0PhysTag - execute.io.in.src(0).ready := true.B - - execute.io.srcData(0) := io.src0Data - execute.io.srcData(1) := 0.U - execute.io.srcData(2) := 0.U - execute.io.loadLookupData := 0.U - execute.io.loadPairFirstLookupData := 0.U - execute.io.loadLookupWaitBlocked := false.B - execute.io.loadLiqEnable := false.B - execute.io.loadLiqAccepted := false.B - execute.io.stackPointerData := 0.U - execute.io.flushValid := io.flushValid - execute.io.fretStkFallbackTargetValid := false.B - execute.io.fretStkFallbackTarget := 0.U - execute.io.fretStkConditionValid := false.B - execute.io.fretStkConditionTaken := false.B - - io.inReady := execute.io.inReady - io.accepted := execute.io.accepted - io.busy := execute.io.busy - io.unsupported := execute.io.unsupported - io.unsupportedOpcode := execute.io.unsupportedOpcode - io.completeValid := execute.io.completeValid - io.completeRobValue := execute.io.completeRobValue - io.completeLsId := execute.io.completeLsId - io.completeDstPhysValid := execute.io.completeDstPhysValid - io.completeDstPhysTag := execute.io.completeDstPhysTag - io.completeDstData := execute.io.completeDstData - io.completeSrc0PhysValid := execute.io.completeSrcPhysValid(0) - io.completeSrc0PhysTag := execute.io.completeSrcPhysTag(0) - io.completeSrc1PhysValid := execute.io.completeSrcPhysValid(1) - io.completeSrc1PhysTag := execute.io.completeSrcPhysTag(1) - io.completeRowValid := execute.io.completeRow.valid - io.completeRowBid := execute.io.completeRow.identity.bid - io.completeRowGid := execute.io.completeRow.identity.gid - io.completeRowRid := execute.io.completeRow.identity.rid - io.completeRowRobValid := execute.io.completeRow.rob.valid - io.completeRowRobWrap := execute.io.completeRow.rob.wrap - io.completeRowRobValue := execute.io.completeRow.rob.value - io.completeRowBlockBidValid := execute.io.completeRow.blockBidValid - io.completeRowBlockBid := execute.io.completeRow.blockBid - io.completeRowPc := execute.io.completeRow.pc - io.completeRowInsn := execute.io.completeRow.insn - io.completeRowLen := execute.io.completeRow.len - io.completeRowSrc0Valid := execute.io.completeRow.src0.valid - io.completeRowSrc0Reg := execute.io.completeRow.src0.reg - io.completeRowSrc0Data := execute.io.completeRow.src0.data - io.completeRowSrc1Valid := execute.io.completeRow.src1.valid - io.completeRowSrc1Reg := execute.io.completeRow.src1.reg - io.completeRowSrc1Data := execute.io.completeRow.src1.data - io.completeRowDstValid := execute.io.completeRow.dst.valid - io.completeRowDstReg := execute.io.completeRow.dst.reg - io.completeRowDstData := execute.io.completeRow.dst.data - io.completeRowWbValid := execute.io.completeRow.wb.valid - io.completeRowWbReg := execute.io.completeRow.wb.reg - io.completeRowWbData := execute.io.completeRow.wb.data - io.branchConditionValid := execute.io.branchConditionValid - io.branchConditionTaken := execute.io.branchConditionTaken - io.releaseValid := execute.io.releaseValid - io.releaseBidValid := execute.io.releaseBid.valid - io.releaseBidWrap := execute.io.releaseBid.wrap - io.releaseBidValue := execute.io.releaseBid.value - io.releaseGidValid := execute.io.releaseGid.valid - io.releaseGidWrap := execute.io.releaseGid.wrap - io.releaseGidValue := execute.io.releaseGid.value - io.releaseRidValid := execute.io.releaseRid.valid - io.releaseRidWrap := execute.io.releaseRid.wrap - io.releaseRidValue := execute.io.releaseRid.value - io.releaseStid := execute.io.releaseStid -} - -object EmitReducedScalarAluSetcImmediateBehaviorProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-alu-setc-immediate-behavior-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarAluSetcImmediateBehaviorProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarDividerSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarDividerSpec.scala deleted file mode 100644 index f8943997..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarDividerSpec.scala +++ /dev/null @@ -1,88 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class ReducedScalarDividerSpec extends AnyFunSuite with ChiselSim { - private val Mask64 = (BigInt(1) << 64) - 1 - - private def clear(dut: ReducedScalarDivider): Unit = { - dut.io.reqValid.poke(false.B) - dut.io.lhs.poke(0.U) - dut.io.rhs.poke(0.U) - dut.io.signed.poke(false.B) - dut.io.word.poke(false.B) - dut.io.remainder.poke(false.B) - dut.io.respReady.poke(false.B) - dut.io.flush.poke(false.B) - } - - private def divide( - dut: ReducedScalarDivider, - lhs: BigInt, - rhs: BigInt, - signed: Boolean, - word: Boolean, - remainder: Boolean, - expected: BigInt): Unit = { - dut.io.reqReady.expect(true.B) - dut.io.reqValid.poke(true.B) - dut.io.lhs.poke((lhs & Mask64).U) - dut.io.rhs.poke((rhs & Mask64).U) - dut.io.signed.poke(signed.B) - dut.io.word.poke(word.B) - dut.io.remainder.poke(remainder.B) - dut.clock.step() - dut.io.reqValid.poke(false.B) - dut.clock.step(if (rhs == 0) 0 else if (word) 32 else 64) - dut.io.respValid.expect(true.B) - dut.io.result.expect((expected & Mask64).U) - dut.io.respReady.poke(true.B) - dut.clock.step() - dut.io.respReady.poke(false.B) - dut.io.respValid.expect(false.B) - } - - test("iterative divider implements Sail scalar DIV and REM conventions") { - simulate(new ReducedScalarDivider) { dut => - clear(dut) - divide(dut, 100, 7, signed = false, word = false, remainder = false, expected = 14) - divide(dut, 100, 7, signed = false, word = false, remainder = true, expected = 2) - divide(dut, -100, 7, signed = true, word = false, remainder = false, expected = -14) - divide(dut, -100, 7, signed = true, word = false, remainder = true, expected = -2) - divide(dut, BigInt(1) << 63, -1, signed = true, word = false, remainder = false, expected = BigInt(1) << 63) - divide(dut, BigInt(1) << 63, -1, signed = true, word = false, remainder = true, expected = 0) - divide(dut, 0x1234, 0, signed = false, word = false, remainder = false, expected = 0) - divide(dut, 0x1234, 0, signed = false, word = false, remainder = true, expected = 0x1234) - } - } - - test("word results always sign-extend, including DIVUW and REMUW") { - simulate(new ReducedScalarDivider) { dut => - clear(dut) - divide(dut, BigInt("fffffffe", 16), 1, signed = false, word = true, remainder = false, expected = BigInt("fffffffffffffffe", 16)) - divide(dut, BigInt("fffffffe", 16), BigInt("ffffffff", 16), signed = false, word = true, remainder = true, expected = BigInt("fffffffffffffffe", 16)) - divide(dut, BigInt("80000000", 16), -1, signed = true, word = true, remainder = false, expected = BigInt("ffffffff80000000", 16)) - divide(dut, BigInt("80000000", 16), -1, signed = true, word = true, remainder = true, expected = 0) - divide(dut, BigInt("80000001", 16), 0, signed = false, word = true, remainder = true, expected = BigInt("ffffffff80000001", 16)) - } - } - - test("flush cancels an in-flight division") { - simulate(new ReducedScalarDivider) { dut => - clear(dut) - dut.io.reqValid.poke(true.B) - dut.io.lhs.poke(100.U) - dut.io.rhs.poke(3.U) - dut.clock.step() - dut.io.reqValid.poke(false.B) - dut.clock.step(5) - dut.io.flush.poke(true.B) - dut.clock.step() - dut.io.flush.poke(false.B) - dut.io.respValid.expect(false.B) - dut.io.reqReady.expect(true.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarFpExecuteSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarFpExecuteSpec.scala deleted file mode 100644 index 78b840f2..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarFpExecuteSpec.scala +++ /dev/null @@ -1,167 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import circt.stage.ChiselStage -import linxcore.frontend.FrontendOpcodeDecodeTable -import org.scalatest.funsuite.AnyFunSuite - -class ReducedScalarFpExecuteSpec extends AnyFunSuite with ChiselSim { - private val Mask64 = (BigInt(1) << 64) - 1 - - private def insn(dstType: Int, srcType: Int): BigInt = - ReducedScalarFpExecute.scalarFpInsn(dstType, srcType) - - private def drive( - dut: ReducedScalarFpExecute, - opcode: Int, - insnRaw: BigInt, - srcL: BigInt, - srcR: BigInt, - expected: BigInt): Unit = { - dut.io.inValid.poke(true.B) - dut.io.outReady.poke(true.B) - dut.io.flush.poke(false.B) - dut.io.opcode.poke(opcode.U) - dut.io.insnRaw.poke(insnRaw.U) - dut.io.srcL.poke((srcL & Mask64).U) - dut.io.srcR.poke((srcR & Mask64).U) - dut.io.inReady.expect(true.B) - dut.io.outValid.expect(true.B) - dut.io.unsupported.expect(false.B) - dut.io.outData.expect((expected & Mask64).U) - } - - test("FEQ fd/fs is ordered, treats both signed zero encodings as equal, and returns false for NaN") { - simulate(new ReducedScalarFpExecute) { dut => - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFd, ReducedScalarFpExecute.SrcTypeFd), - BigInt("3ff0000000000000", 16), - BigInt("3ff0000000000000", 16), - 1) - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFd, ReducedScalarFpExecute.SrcTypeFd), - BigInt("8000000000000000", 16), - BigInt("0000000000000000", 16), - 1) - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFs, ReducedScalarFpExecute.SrcTypeFs), - BigInt("000000003f800000", 16), - BigInt("000000003f800000", 16), - 1) - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFs, ReducedScalarFpExecute.SrcTypeFs), - BigInt("0000000080000000", 16), - BigInt("0000000000000000", 16), - 1) - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFs, ReducedScalarFpExecute.SrcTypeFs), - BigInt("000000007fc00001", 16), - BigInt("000000007fc00001", 16), - 0) - drive( - dut, - FrontendOpcodeDecodeTable.OP_FEQ, - insn(ReducedScalarFpExecute.DstTypeFd, ReducedScalarFpExecute.SrcTypeFd), - BigInt("7ff8000000000001", 16), - BigInt("7ff8000000000001", 16), - 0) - } - } - - test("FCVT fs2fd expands IEEE single-precision bit patterns into double precision") { - simulate(new ReducedScalarFpExecute) { dut => - val op = FrontendOpcodeDecodeTable.OP_FCVT - val fs2fd = insn(ReducedScalarFpExecute.DstTypeFd, ReducedScalarFpExecute.SrcTypeFs) - Seq( - BigInt("000000003f800000", 16) -> BigInt("3ff0000000000000", 16), - BigInt("00000000c0200000", 16) -> BigInt("c004000000000000", 16), - BigInt("0000000000000000", 16) -> BigInt("0000000000000000", 16), - BigInt("0000000080000000", 16) -> BigInt("8000000000000000", 16), - BigInt("0000000000000001", 16) -> BigInt("36a0000000000000", 16), - BigInt("000000007f800000", 16) -> BigInt("7ff0000000000000", 16) - ).foreach { case (src, expected) => - drive(dut, op, fs2fd, src, 0, expected) - } - } - } - - test("UCVTF ud2fs rounds uint64 to f32 with round-to-nearest-even") { - simulate(new ReducedScalarFpExecute) { dut => - val op = FrontendOpcodeDecodeTable.OP_UCVTF - val ud2fs = insn(ReducedScalarFpExecute.DstTypeFs, ReducedScalarFpExecute.SrcTypeFd) - Seq( - BigInt(0), - BigInt(1), - (BigInt(1) << 24) - 1, - BigInt(1) << 24, - (BigInt(1) << 24) + 1, - (BigInt(1) << 24) + 3, - (BigInt(1) << 40) + (BigInt(1) << 16), - (BigInt(1) << 63) - 1, - BigInt(1) << 63, - (BigInt(1) << 64) - 1 - ).foreach { value => - val expected = ReducedScalarFpExecute.referenceResult(op, ud2fs, value, 0).get - drive(dut, op, ud2fs, value, 0, expected) - } - } - } - - test("ready/valid contract is combinational and flush masks the same-cycle result") { - simulate(new ReducedScalarFpExecute) { dut => - val feqFs = insn(ReducedScalarFpExecute.DstTypeFs, ReducedScalarFpExecute.SrcTypeFs) - dut.io.inValid.poke(true.B) - dut.io.outReady.poke(false.B) - dut.io.flush.poke(false.B) - dut.io.opcode.poke(FrontendOpcodeDecodeTable.OP_FEQ.U) - dut.io.insnRaw.poke(feqFs.U) - dut.io.srcL.poke(BigInt("3f800000", 16).U) - dut.io.srcR.poke(BigInt("3f800000", 16).U) - dut.io.inReady.expect(false.B) - dut.io.outValid.expect(true.B) - dut.io.outData.expect(1.U) - - dut.io.outReady.poke(true.B) - dut.io.flush.poke(true.B) - dut.io.inReady.expect(true.B) - dut.io.outValid.expect(false.B) - - dut.io.flush.poke(false.B) - dut.io.outValid.expect(true.B) - dut.io.outData.expect(1.U) - } - } - - test("unsupported encodings are reported without claiming subset completion") { - simulate(new ReducedScalarFpExecute) { dut => - dut.io.inValid.poke(true.B) - dut.io.outReady.poke(true.B) - dut.io.flush.poke(false.B) - dut.io.opcode.poke(FrontendOpcodeDecodeTable.OP_UCVTF.U) - dut.io.insnRaw.poke(insn(ReducedScalarFpExecute.DstTypeFd, ReducedScalarFpExecute.SrcTypeFs).U) - dut.io.srcL.poke(0.U) - dut.io.srcR.poke(0.U) - dut.io.outValid.expect(true.B) - dut.io.unsupported.expect(true.B) - dut.io.outData.expect(0.U) - } - } - - test("ReducedScalarFpExecute elaborates standalone synthesizable RTL") { - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarFpExecute) - assert(sv.contains("module ReducedScalarFpExecute")) - assert(!sv.contains("$realtobits")) - assert(!sv.contains("DPI")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarIssuePickSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarIssuePickSpec.scala deleted file mode 100644 index 68a6402e..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarIssuePickSpec.scala +++ /dev/null @@ -1,56 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import linxcore.common.InterfaceParams -import org.scalatest.funsuite.AnyFunSuite - -class ReducedScalarIssuePickSpec extends AnyFunSuite { - test("interface exposes selected-row RF read and issue-confirm diagnostics") { - val p = InterfaceParams() - val io = new ReducedScalarIssuePickIO(p, depth = 4) - - assert(io.selectableMask.getWidth == 4) - assert(io.entries.length == 4) - assert(io.notIssuedCount.getWidth == 3) - assert(io.flushValid.getWidth == 1) - assert(io.readValid.length == 3) - assert(io.readTags.head.getWidth == 6) - assert(io.readData.head.getWidth == 64) - assert(io.readGrant.getWidth == 1) - assert(io.readAttemptValid.getWidth == 1) - assert(io.readFire.getWidth == 1) - assert(io.readUop.getWidth == io.entries.head.getWidth) - assert(io.issueUop.getWidth == io.entries.head.getWidth) - assert(io.issueSrcData.head.getWidth == 64) - assert(io.pickFire.getWidth == 1) - assert(io.cancelIndex.getWidth == 2) - assert(io.i1Valid.getWidth == 1) - assert(io.i2Valid.getWidth == 1) - assert(io.selectedIndex.getWidth == 2) - } - - test("ReducedScalarIssuePick elaborates pick, read-confirm, and block outputs") { - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarIssuePick(InterfaceParams(), depth = 4)) - - assert(sv.contains("module ReducedScalarIssuePick")) - assert(sv.contains("io_selectableMask")) - assert(sv.contains("io_readValid")) - assert(sv.contains("io_readGrant")) - assert(sv.contains("io_readAttemptValid")) - assert(sv.contains("rrBase")) - assert(sv.contains("io_pickFire")) - assert(sv.contains("io_issueValid")) - assert(sv.contains("io_issueFire")) - assert(sv.contains("io_cancelFire")) - assert(sv.contains("io_i1Valid")) - assert(sv.contains("io_i2Valid")) - assert(sv.contains("io_stageBusy")) - assert(sv.contains("io_selectedValid")) - assert(sv.contains("io_selectedIndex")) - assert(sv.contains("io_selectedReadReady")) - assert(sv.contains("io_blockedByRead")) - assert(sv.contains("io_blockedBySource")) - assert(sv.contains("io_blockedByOutput")) - assert(sv.contains("io_blockedByIssued")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarIssueQueueSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarIssueQueueSpec.scala deleted file mode 100644 index 182990db..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarIssueQueueSpec.scala +++ /dev/null @@ -1,787 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Enum, is, switch} -import linxcore.common.{BoundaryKind, DestinationKind, DispatchTarget, InterfaceParams, OperandClass, RenamedDestination, RenamedUop} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rob.ROBID -import org.scalatest.funsuite.AnyFunSuite - -import java.nio.file.Files -import scala.sys.process._ - -class ReducedScalarIssueQueueSameBankSpOrderProbeIO(val p: InterfaceParams) extends Bundle { - val done = Output(Bool()) - val failure = Output(Bool()) - val firstIssueRid = Output(UInt(p.robIndexWidth.W)) - val secondIssueRid = Output(UInt(p.robIndexWidth.W)) -} - -class ReducedScalarIssueQueueSameBankSpOrderProbe extends Module { - val p = InterfaceParams(robEntries = 16) - val io = IO(new ReducedScalarIssueQueueSameBankSpOrderProbeIO(p)) - - val queue = Module(new ReducedScalarIssueQueue(p, depth = 4, stidCount = 1)) - val cycle = RegInit(0.U(8.W)) - cycle := cycle + 1.U - - val producerReady = RegInit(false.B) - val olderIssueSeen = RegInit(false.B) - val youngerIssueSeen = RegInit(false.B) - val firstIssueRid = RegInit(0.U(p.robIndexWidth.W)) - val secondIssueRid = RegInit(0.U(p.robIndexWidth.W)) - val failure = RegInit(false.B) - - val Seq( - sEnqueueOlder, - sEnqueueYounger, - sHoldOlderBlocked, - sWakeOlder, - sWaitOlder, - sWaitYounger, - sDone) = Enum(7) - val state = RegInit(sEnqueueOlder) - - def uop(ridValue: Int, opcode: Int, src0Valid: Boolean, dstSp: Boolean): linxcore.common.RenamedUop = { - val row = Wire(new linxcore.common.RenamedUop(p)) - row := 0.U.asTypeOf(row) - row.valid := true.B - row.threadId := 0.U - row.pc := (0x10000L + ridValue).U - row.opcode := opcode.U(p.opcodeWidth.W) - row.dispatchTarget := DispatchTarget.Alu - row.bid.valid := true.B - row.bid.wrap := false.B - row.bid.value := 0.U - row.rid.valid := true.B - row.rid.wrap := false.B - row.rid.value := ridValue.U - row.src(0).valid := src0Valid.B - row.src(0).operandClass := OperandClass.P - row.src(0).archTag := 11.U - row.src(0).relTag := 11.U - row.src(0).physTag := 9.U - row.src(1).valid := true.B - row.src(1).operandClass := OperandClass.P - row.src(1).archTag := 1.U - row.src(1).relTag := 1.U - row.src(1).physTag := 1.U - row.dst(0).valid := dstSp.B - row.dst(0).kind := Mux(dstSp.B, DestinationKind.Gpr, DestinationKind.None) - row.dst(0).archTag := 1.U - row.dst(0).relTag := 1.U - row.dst(0).physTag := 2.U - row - } - - val older = uop( - ridValue = 10, - opcode = FrontendOpcodeDecodeTable.OP_HL_SDI_PR, - src0Valid = true, - dstSp = true) - val younger = uop( - ridValue = 11, - opcode = FrontendOpcodeDecodeTable.OP_FENTRY, - src0Valid = false, - dstSp = true) - - queue.io.inValid := state === sEnqueueOlder || state === sEnqueueYounger - queue.io.in := Mux(state === sEnqueueOlder, older, younger) - queue.io.flushValid := false.B - queue.io.releaseValid := queue.io.issueFire - queue.io.releaseBid.valid := true.B - queue.io.releaseBid.wrap := false.B - queue.io.releaseBid.value := 0.U - queue.io.releaseRid.valid := queue.io.issueFire - queue.io.releaseRid.wrap := false.B - queue.io.releaseRid.value := queue.io.issueUop.rid.value - queue.io.releaseStid := 0.U - queue.io.secondaryReleaseValid := false.B - queue.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - queue.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - queue.io.secondaryReleaseStid := 0.U - queue.io.tertiaryReleaseValid := false.B - queue.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - queue.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - queue.io.tertiaryReleaseStid := 0.U - queue.io.scalarSpHeadValidByStid(0) := true.B - queue.io.scalarSpHeadBidByStid(0).valid := true.B - queue.io.scalarSpHeadBidByStid(0).wrap := false.B - queue.io.scalarSpHeadBidByStid(0).value := 0.U - queue.io.scalarSpHeadRidByStid(0).valid := true.B - queue.io.scalarSpHeadRidByStid(0).wrap := false.B - queue.io.scalarSpHeadRidByStid(0).value := Mux(olderIssueSeen, 11.U, 10.U) - queue.io.readyMask := Mux(producerReady, 1.U << 9.U, 0.U) - queue.io.pWakeupValid := state === sWakeOlder - queue.io.pWakeupTag := 9.U - queue.io.localTReadyMask := 0.U - queue.io.localUReadyMask := 0.U - queue.io.readGrant := true.B - queue.io.issueReady := true.B - for (lane <- 0 until 3) { - queue.io.readData(lane) := (0x200 + lane).U - } - - when(queue.io.readAttemptValid && !olderIssueSeen && queue.io.readUop.rid.value === 11.U) { - failure := true.B - } - when(queue.io.issueFire) { - when(!olderIssueSeen && queue.io.issueUop.rid.value =/= 10.U) { - failure := true.B - } - when(olderIssueSeen && !youngerIssueSeen && queue.io.issueUop.rid.value =/= 11.U) { - failure := true.B - } - when(!olderIssueSeen) { - olderIssueSeen := true.B - firstIssueRid := queue.io.issueUop.rid.value - }.elsewhen(!youngerIssueSeen) { - youngerIssueSeen := true.B - secondIssueRid := queue.io.issueUop.rid.value - } - } - when(cycle > 60.U && !youngerIssueSeen) { - failure := true.B - } - - switch(state) { - is(sEnqueueOlder) { - when(queue.io.enqueueFire) { - state := sEnqueueYounger - } - } - is(sEnqueueYounger) { - when(queue.io.enqueueFire) { - state := sHoldOlderBlocked - } - } - is(sHoldOlderBlocked) { - when(cycle > 8.U) { - state := sWakeOlder - } - } - is(sWakeOlder) { - producerReady := true.B - state := sWaitOlder - } - is(sWaitOlder) { - when(olderIssueSeen) { - state := sWaitYounger - } - } - is(sWaitYounger) { - when(youngerIssueSeen) { - state := sDone - } - } - } - - io.done := state === sDone - io.failure := failure - io.firstIssueRid := firstIssueRid - io.secondIssueRid := secondIssueRid -} - -class ReducedScalarIssueQueueHeadIdentityProbeIO(val p: InterfaceParams) extends Bundle { - val done = Output(Bool()) - val failure = Output(Bool()) -} - -class ReducedScalarIssueQueueHeadIdentityProbe extends Module { - val p = InterfaceParams(robEntries = 16) - val io = IO(new ReducedScalarIssueQueueHeadIdentityProbeIO(p)) - - val queue = Module(new ReducedScalarIssueQueue(p, depth = 4, stidCount = 1)) - val cycle = RegInit(0.U(8.W)) - val observedEmpty = RegInit(false.B) - val observedHead = RegInit(false.B) - val failure = RegInit(false.B) - cycle := cycle + 1.U - - val row = Wire(new linxcore.common.RenamedUop(p)) - row := 0.U.asTypeOf(row) - row.valid := true.B - row.threadId := 5.U - row.pc := "h1234".U - row.opcode := FrontendOpcodeDecodeTable.OP_ADDI.U(p.opcodeWidth.W) - row.dispatchTarget := DispatchTarget.Alu - row.bid.valid := true.B - row.bid.wrap := true.B - row.bid.value := 6.U - row.rid.valid := true.B - row.rid.wrap := false.B - row.rid.value := 7.U - - queue.io.inValid := cycle === 1.U - queue.io.in := row - queue.io.flushValid := false.B - queue.io.releaseValid := false.B - queue.io.releaseBid := ROBID.disabled(p.robEntries) - queue.io.releaseRid := ROBID.disabled(p.robEntries) - queue.io.releaseStid := 0.U - queue.io.secondaryReleaseValid := false.B - queue.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - queue.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - queue.io.secondaryReleaseStid := 0.U - queue.io.tertiaryReleaseValid := false.B - queue.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - queue.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - queue.io.tertiaryReleaseStid := 0.U - queue.io.scalarSpHeadValidByStid(0) := false.B - queue.io.scalarSpHeadBidByStid(0) := ROBID.disabled(p.robEntries) - queue.io.scalarSpHeadRidByStid(0) := ROBID.disabled(p.robEntries) - queue.io.readyMask := 0.U - queue.io.pWakeupValid := false.B - queue.io.pWakeupTag := 0.U - queue.io.localTReadyMask := 0.U - queue.io.localUReadyMask := 0.U - queue.io.readGrant := false.B - queue.io.issueReady := false.B - for (lane <- 0 until 3) { - queue.io.readData(lane) := 0.U - } - - when(cycle === 0.U) { - observedEmpty := !queue.io.headValid && - queue.io.headStid === 0.U && - !queue.io.headBid.valid && - !queue.io.headBid.wrap && - queue.io.headBid.value === 0.U && - !queue.io.headRid.valid && - !queue.io.headRid.wrap && - queue.io.headRid.value === 0.U - } - when(cycle >= 2.U && queue.io.headValid) { - observedHead := queue.io.headStid === 5.U && - queue.io.headBid.valid && - queue.io.headBid.wrap && - queue.io.headBid.value === 6.U && - queue.io.headRid.valid && - !queue.io.headRid.wrap && - queue.io.headRid.value === 7.U - } - when(cycle > 20.U && !(observedEmpty && observedHead)) { - failure := true.B - } - - io.done := observedEmpty && observedHead - io.failure := failure -} - -class ReducedScalarIssueQueueSpec extends AnyFunSuite with ChiselSim { - private val SimP = InterfaceParams(robEntries = 16) - private val AllReadyMask = (BigInt(1) << (1 << SimP.physRegWidth)) - 1 - - private def pokeRobId(id: ROBID, valid: Boolean, wrap: Boolean, value: Int): Unit = { - id.valid.poke(valid.B) - id.wrap.poke(wrap.B) - id.value.poke(value.U) - } - - private def pokeDst(dst: RenamedDestination, valid: Boolean, archTag: Int, physTag: Int): Unit = { - dst.valid.poke(valid.B) - dst.kind.poke(if (valid) DestinationKind.Gpr else DestinationKind.None) - dst.archTag.poke(archTag.U) - dst.relTag.poke(archTag.U) - dst.physTag.poke(physTag.U) - dst.oldPhysTag.poke(0.U) - } - - private def pokeRow( - row: RenamedUop, - ridValue: Int, - opcode: Int = FrontendOpcodeDecodeTable.OP_ADDI, - dispatch: DispatchTarget.Type = DispatchTarget.Alu, - srcTags: Seq[Int] = Seq.empty, - dstTag: Option[Int] = Some(8), - dstArch: Int = 8, - isLoad: Boolean = false, - isStore: Boolean = false, - storeSplitIntent: Boolean = false, - isLoadStorePair: Boolean = false, - isStorePcr: Boolean = false, - cacheMaintainNoSplit: Boolean = false, - pairFirstDstTag: Option[Int] = None, - fretStkContextValid: Boolean = false, - fretStkConditionValid: Boolean = false, - fretStkFallbackTargetValid: Boolean = false): Unit = { - row.poke(0.U.asTypeOf(row)) - row.valid.poke(true.B) - row.peId.poke(0.U) - row.threadId.poke(0.U) - row.pc.poke((0x10000L + ridValue).U) - row.opcode.poke(opcode.U(SimP.opcodeWidth.W)) - row.dispatchTarget.poke(dispatch) - for (lane <- 0 until 3) { - val valid = lane < srcTags.length - val tag = if (valid) srcTags(lane) else 0 - row.src(lane).valid.poke(valid.B) - row.src(lane).operandClass.poke(OperandClass.P) - row.src(lane).archTag.poke(tag.U) - row.src(lane).relTag.poke(tag.U) - row.src(lane).physTag.poke(tag.U) - row.src(lane).ready.poke(valid.B) - row.src(lane).producer.poke(0.U) - row.src(lane).literalValid.poke(false.B) - row.src(lane).literal.poke(0.U) - } - pokeDst(row.dst(0), dstTag.isDefined, dstArch, dstTag.getOrElse(0)) - pokeDst(row.pairFirstDst, pairFirstDstTag.isDefined, dstArch + 1, pairFirstDstTag.getOrElse(0)) - row.imm.poke(0.U) - row.immType.poke(0.U) - row.immValid.poke(false.B) - pokeRobId(row.bid, valid = true, wrap = false, value = 0) - pokeRobId(row.gid, valid = true, wrap = false, value = 0) - pokeRobId(row.rid, valid = true, wrap = false, value = ridValue) - row.lsid.poke(0.U) - row.isLoad.poke(isLoad.B) - row.isStore.poke(isStore.B) - row.storeSplitIntent.poke(storeSplitIntent.B) - row.isLoadStorePair.poke(isLoadStorePair.B) - row.isStorePcr.poke(isStorePcr.B) - row.cacheMaintainNoSplit.poke(cacheMaintainNoSplit.B) - row.spAccess.valid.poke(false.B) - row.spAccess.read.poke(false.B) - row.spAccess.write.poke(false.B) - row.sob.poke(false.B) - row.eob.poke(false.B) - row.isLastInBlock.poke(false.B) - row.boundaryKind.poke(BoundaryKind.Fall) - row.boundaryTarget.poke(0.U) - row.predTaken.poke(false.B) - row.fretStkContextValid.poke(fretStkContextValid.B) - row.fretStkConditionValid.poke(fretStkConditionValid.B) - row.fretStkFallbackTargetValid.poke(fretStkFallbackTargetValid.B) - row.fretStkFallbackTarget.poke(0.U) - row.resolvedD2.poke(false.B) - row.insnLen.poke(4.U) - row.insnRaw.poke(0.U) - row.checkpointId.poke(0.U) - row.blockUid.poke(0.U) - row.blockBidValid.poke(false.B) - row.blockBid.poke(0.U) - row.uid.uid.poke(ridValue.U) - row.uid.parentUid.poke(0.U) - row.uid.kind.poke(0.U) - row.uid.fetchPacketUid.poke(0.U) - row.uid.fetchSlot.poke(0.U) - row.uid.replayDepth.poke(0.U) - row.uid.templateKind.poke(0.U) - } - - private def initQueue(dut: ReducedScalarIssueQueue): Unit = { - dut.io.inValid.poke(false.B) - pokeRow(dut.io.in, ridValue = 0, dstTag = None) - dut.io.flushValid.poke(false.B) - dut.io.releaseValid.poke(false.B) - pokeRobId(dut.io.releaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.releaseRid, valid = false, wrap = false, value = 0) - dut.io.releaseStid.poke(0.U) - dut.io.secondaryReleaseValid.poke(false.B) - pokeRobId(dut.io.secondaryReleaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.secondaryReleaseRid, valid = false, wrap = false, value = 0) - dut.io.secondaryReleaseStid.poke(0.U) - dut.io.tertiaryReleaseValid.poke(false.B) - pokeRobId(dut.io.tertiaryReleaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.tertiaryReleaseRid, valid = false, wrap = false, value = 0) - dut.io.tertiaryReleaseStid.poke(0.U) - dut.io.scalarSpHeadValidByStid(0).poke(false.B) - pokeRobId(dut.io.scalarSpHeadBidByStid(0), valid = false, wrap = false, value = 0) - pokeRobId(dut.io.scalarSpHeadRidByStid(0), valid = false, wrap = false, value = 0) - dut.io.readyMask.poke(AllReadyMask.U) - dut.io.pWakeupValid.poke(false.B) - dut.io.pWakeupTag.poke(0.U) - dut.io.localTReadyMask.poke(0.U) - dut.io.localUReadyMask.poke(0.U) - dut.io.readGrant.poke(true.B) - dut.io.issueReady.poke(true.B) - for (lane <- 0 until 3) { - dut.io.readData(lane).poke((0x600 + lane).U) - } - } - - private def setScalarSpHead(dut: ReducedScalarIssueQueue, valid: Boolean, ridValue: Int): Unit = { - dut.io.scalarSpHeadValidByStid(0).poke(valid.B) - pokeRobId(dut.io.scalarSpHeadBidByStid(0), valid = valid, wrap = false, value = 0) - pokeRobId(dut.io.scalarSpHeadRidByStid(0), valid = valid, wrap = false, value = ridValue) - } - - private def enqueue(dut: ReducedScalarIssueQueue, ridValue: Int, configure: RenamedUop => Unit): Unit = { - dut.io.inValid.poke(true.B) - configure(dut.io.in) - dut.io.inReady.expect(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - } - - private def pokeRelease( - valid: Bool, - bid: ROBID, - rid: ROBID, - stid: UInt, - fire: Boolean, - ridValue: Int): Unit = { - valid.poke(fire.B) - pokeRobId(bid, valid = fire, wrap = false, value = 0) - pokeRobId(rid, valid = fire, wrap = false, value = ridValue) - stid.poke(0.U) - } - - test("interface exposes enqueue, RF-read query, issue, and release handshakes") { - val p = InterfaceParams() - val io = new ReducedScalarIssueQueueIO(p, depth = 4, stidCount = 1) - - assert(io.in.getWidth > 0) - assert(io.releaseBid.value.getWidth == p.robIndexWidth) - assert(io.releaseRid.value.getWidth == p.robIndexWidth) - assert(io.releaseStid.getWidth == p.threadIdWidth) - assert(io.secondaryReleaseBid.value.getWidth == p.robIndexWidth) - assert(io.secondaryReleaseRid.value.getWidth == p.robIndexWidth) - assert(io.secondaryReleaseStid.getWidth == p.threadIdWidth) - assert(io.tertiaryReleaseBid.value.getWidth == p.robIndexWidth) - assert(io.tertiaryReleaseRid.value.getWidth == p.robIndexWidth) - assert(io.tertiaryReleaseStid.getWidth == p.threadIdWidth) - assert(io.scalarSpHeadValidByStid.length == 1) - assert(io.scalarSpHeadBidByStid.head.value.getWidth == p.robIndexWidth) - assert(io.scalarSpHeadRidByStid.head.value.getWidth == p.robIndexWidth) - assert(io.readyMask.getWidth == 64) - assert(io.pWakeupTag.getWidth == 6) - assert(io.pWakeupMatchCount.getWidth == 4) - assert(io.localTReadyMask.getWidth == 4) - assert(io.localUReadyMask.getWidth == 4) - assert(io.readValid.length == 3) - assert(io.readTags.head.getWidth == 6) - assert(io.readRelTag.head.getWidth == 6) - assert(io.readData.head.getWidth == 64) - assert(io.readGrant.getWidth == 1) - assert(io.readAttemptValid.getWidth == 1) - assert(io.readUop.getWidth == io.in.getWidth) - assert(io.issueUop.getWidth == io.in.getWidth) - assert(io.issueSrcData.head.getWidth == 64) - assert(io.count.getWidth == 3) - assert(io.issuedCount.getWidth == 3) - assert(io.notIssuedCount.getWidth == 3) - assert(io.headPc.getWidth == 64) - assert(io.headOpcode.getWidth == 12) - assert(io.headStid.getWidth == p.threadIdWidth) - assert(io.headBid.valid.getWidth == 1) - assert(io.headBid.wrap.getWidth == 1) - assert(io.headBid.value.getWidth == p.robIndexWidth) - assert(io.headRid.valid.getWidth == 1) - assert(io.headRid.wrap.getWidth == 1) - assert(io.headRid.value.getWidth == p.robIndexWidth) - assert(io.headSrcValidMask.getWidth == 3) - assert(io.headSrcOperandClass.length == 3) - assert(io.headSrcPhysTag.head.getWidth == 6) - assert(io.headSrcRelTag.head.getWidth == 6) - assert(io.sourceReadyMask.getWidth == 3) - assert(io.selectedIndex.getWidth == 2) - assert(io.selectedReadReady.getWidth == 1) - assert(io.pickFire.getWidth == 1) - assert(io.cancelFire.getWidth == 1) - assert(io.i1Valid.getWidth == 1) - assert(io.i2Valid.getWidth == 1) - assert(io.stageBusy.getWidth == 1) - assert(io.enqueueDstTag.getWidth == 6) - } - - test("ReducedScalarIssueQueue elaborates capacity, oldest-ready selection, and read-confirm diagnostics") { - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarIssueQueue(InterfaceParams(), depth = 4, stidCount = 1)) - - assert(sv.contains("module ReducedScalarIssueQueue")) - assert(sv.contains("module ReducedScalarIssuePick")) - assert(sv.contains("io_inReady")) - assert(sv.contains("io_pWakeupValid")) - assert(sv.contains("io_pWakeupMatched")) - assert(sv.contains("io_pWakeupMatchCount")) - assert(sv.contains("io_readValid")) - assert(sv.contains("io_readOperandClass")) - assert(sv.contains("io_readGrant")) - assert(sv.contains("io_readAttemptValid")) - assert(sv.contains("io_issueValid")) - assert(sv.contains("io_enqueueFire")) - assert(sv.contains("io_pickFire")) - assert(sv.contains("io_issueFire")) - assert(sv.contains("io_cancelFire")) - assert(sv.contains("io_releaseFire")) - assert(sv.contains("io_secondaryReleaseValid")) - assert(sv.contains("io_tertiaryReleaseValid")) - assert(sv.contains("io_scalarSpHeadValidByStid")) - assert(sv.contains("io_headIssued")) - assert(sv.contains("io_headPc")) - assert(sv.contains("io_headStid")) - assert(sv.contains("io_headBid_valid")) - assert(sv.contains("io_headBid_wrap")) - assert(sv.contains("io_headBid_value")) - assert(sv.contains("io_headRid_valid")) - assert(sv.contains("io_headRid_wrap")) - assert(sv.contains("io_headRid_value")) - assert(sv.contains("io_headSrcValidMask")) - assert(sv.contains("io_headSrcPhysTag")) - assert(sv.contains("io_sourceReadyMask")) - assert(sv.contains("io_selectedValid")) - assert(sv.contains("io_selectedIndex")) - assert(sv.contains("io_selectedReadReady")) - assert(sv.contains("io_i1Valid")) - assert(sv.contains("io_i2Valid")) - assert(sv.contains("io_stageBusy")) - assert(sv.contains("io_blockedByRead")) - assert(sv.contains("io_blockedByIssued")) - assert(sv.contains("io_blockedBySource")) - assert(sv.contains("io_blockedByOutput")) - } - - test("committed P wakeup matches only global P operands with the same physical tag") { - def matches(valid: Boolean, issued: Boolean, operandClass: String, tag: Int, wakeTag: Int): Boolean = - valid && !issued && operandClass == "P" && tag == wakeTag - - assert(matches(valid = true, issued = false, operandClass = "P", tag = 40, wakeTag = 40)) - assert(!matches(valid = true, issued = true, operandClass = "P", tag = 40, wakeTag = 40)) - assert(!matches(valid = true, issued = false, operandClass = "T", tag = 40, wakeTag = 40)) - assert(!matches(valid = true, issued = false, operandClass = "P", tag = 41, wakeTag = 40)) - } - - test("same-bank scalar SP rows require owner-head eligibility before pick") { - final case class Row( - rid: Int, - scalarSp: Boolean, - sourceReady: Boolean, - issued: Boolean = false) - - def selectable(row: Row, headRid: Int): Boolean = - !row.issued && row.sourceReady && (!row.scalarSp || row.rid == headRid) - - def firstSelectable(rows: Seq[Row], headRid: Int): Option[Int] = - rows.indexWhere(selectable(_, headRid)) match { - case -1 => None - case idx => Some(idx) - } - - val olderBlocked = Row(rid = 10, scalarSp = true, sourceReady = false) - val youngerFrame = Row(rid = 11, scalarSp = true, sourceReady = true) - - assert(firstSelectable(Seq(olderBlocked, youngerFrame), headRid = 10).isEmpty) - - val olderWoken = olderBlocked.copy(sourceReady = true) - val first = firstSelectable(Seq(olderWoken, youngerFrame), headRid = 10) - assert(first.contains(0)) - assert(!selectable(youngerFrame, headRid = 10)) - - val afterOlderIssued = Seq(olderWoken.copy(issued = true), youngerFrame) - assert(firstSelectable(afterOlderIssued, headRid = 11).contains(1)) - } - - test("DUT issues older same-bank scalar SP head before younger ready frame row") { - val tmp = Files.createTempDirectory("reduced-scalar-iq-sp-order") - val svPath = tmp.resolve("ReducedScalarIssueQueueSameBankSpOrderProbe.sv") - val tbPath = tmp.resolve("tb.cpp") - val objDir = tmp.resolve("obj") - Files.createDirectories(objDir) - ChiselStage.emitSystemVerilogFile( - new ReducedScalarIssueQueueSameBankSpOrderProbe, - args = Array("--target-dir", tmp.toString), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - Files.writeString(tbPath, """#include "VReducedScalarIssueQueueSameBankSpOrderProbe.h" -#include "verilated.h" -#include - -static void tick(VReducedScalarIssueQueueSameBankSpOrderProbe* top, VerilatedContext* context) { - top->clock = 0; - top->eval(); - context->timeInc(1); - top->clock = 1; - top->eval(); - context->timeInc(1); -} - -int main(int argc, char** argv) { - VerilatedContext context; - context.commandArgs(argc, argv); - VReducedScalarIssueQueueSameBankSpOrderProbe top{&context}; - top.reset = 1; - for (int i = 0; i < 3; ++i) { - tick(&top, &context); - } - - top.reset = 0; - for (int cycle = 0; cycle < 100; ++cycle) { - tick(&top, &context); - if (top.io_failure) { - std::cerr << "same-bank scalar-SP issue-order probe failed at cycle " << cycle - << " first=" << static_cast(top.io_firstIssueRid) - << " second=" << static_cast(top.io_secondIssueRid) << "\n"; - return 1; - } - if (top.io_done) { - if (top.io_firstIssueRid != 10 || top.io_secondIssueRid != 11) { - std::cerr << "unexpected issue order first=" << static_cast(top.io_firstIssueRid) - << " second=" << static_cast(top.io_secondIssueRid) << "\n"; - return 1; - } - return 0; - } - } - std::cerr << "same-bank scalar-SP issue-order probe timed out\n"; - return 1; -} -""") - val command = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--top-module", - "ReducedScalarIssueQueueSameBankSpOrderProbe", - svPath.toString, - tbPath.toString, - "-Mdir", - objDir.toString - ) - val compileExit = Process(command, tmp.toFile).! - assert(compileExit == 0) - val runExit = Process(Seq(objDir.resolve("VReducedScalarIssueQueueSameBankSpOrderProbe").toString), tmp.toFile).! - assert(runExit == 0) - } - - test("DUT releases primary, secondary, and tertiary identities in one cycle") { - simulate(new ReducedScalarIssueQueue(SimP, depth = 4, stidCount = 1)) { dut => - initQueue(dut) - - enqueue(dut, 1, pokeRow(_, ridValue = 1, dstTag = Some(9))) - enqueue(dut, 2, pokeRow(_, ridValue = 2, dstTag = Some(10))) - enqueue(dut, 3, pokeRow(_, ridValue = 3, dstTag = Some(11))) - dut.io.count.expect(3.U) - - for (rid <- 1 to 3) { - dut.io.issueFire.expect(true.B) - dut.io.issueUop.rid.value.expect(rid.U) - dut.clock.step() - } - dut.io.issuedCount.expect(3.U) - - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, 1) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = true, - 2) - pokeRelease( - dut.io.tertiaryReleaseValid, - dut.io.tertiaryReleaseBid, - dut.io.tertiaryReleaseRid, - dut.io.tertiaryReleaseStid, - fire = true, - 3) - dut.io.releaseFire.expect(true.B) - dut.clock.step() - dut.io.count.expect(0.U) - dut.io.empty.expect(true.B) - } - } - - test("DUT de-duplicates same-identity release across primary and tertiary ports") { - simulate(new ReducedScalarIssueQueue(SimP, depth = 4, stidCount = 1)) { dut => - initQueue(dut) - - enqueue(dut, 5, pokeRow(_, ridValue = 5, dstTag = Some(12))) - enqueue(dut, 6, pokeRow(_, ridValue = 6, dstTag = Some(13))) - enqueue(dut, 7, pokeRow(_, ridValue = 7, dstTag = Some(14))) - dut.io.count.expect(3.U) - - for (rid <- 5 to 7) { - dut.io.issueFire.expect(true.B) - dut.io.issueUop.rid.value.expect(rid.U) - dut.clock.step() - } - dut.io.issuedCount.expect(3.U) - - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, 5) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = true, - 5) - pokeRelease( - dut.io.tertiaryReleaseValid, - dut.io.tertiaryReleaseBid, - dut.io.tertiaryReleaseRid, - dut.io.tertiaryReleaseStid, - fire = true, - 5) - dut.io.releaseFire.expect(true.B) - dut.clock.step() - dut.io.count.expect(2.U) - dut.io.headRid.value.expect(6.U) - } - } - - test("DUT exposes empty-invalid and resident head transaction identity") { - val tmp = Files.createTempDirectory("reduced-scalar-iq-head-identity") - val svPath = tmp.resolve("ReducedScalarIssueQueueHeadIdentityProbe.sv") - val tbPath = tmp.resolve("tb.cpp") - val objDir = tmp.resolve("obj") - Files.createDirectories(objDir) - ChiselStage.emitSystemVerilogFile( - new ReducedScalarIssueQueueHeadIdentityProbe, - args = Array("--target-dir", tmp.toString), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - Files.writeString(tbPath, """#include "VReducedScalarIssueQueueHeadIdentityProbe.h" -#include "verilated.h" -#include - -static void tick(VReducedScalarIssueQueueHeadIdentityProbe* top, VerilatedContext* context) { - top->clock = 0; - top->eval(); - context->timeInc(1); - top->clock = 1; - top->eval(); - context->timeInc(1); -} - -int main(int argc, char** argv) { - VerilatedContext context; - context.commandArgs(argc, argv); - VReducedScalarIssueQueueHeadIdentityProbe top{&context}; - top.reset = 1; - for (int i = 0; i < 3; ++i) { - tick(&top, &context); - } - top.reset = 0; - for (int cycle = 0; cycle < 40; ++cycle) { - tick(&top, &context); - if (top.io_failure) { - std::cerr << "head identity probe failed at cycle " << cycle << "\n"; - return 1; - } - if (top.io_done) { - return 0; - } - } - std::cerr << "head identity probe timed out\n"; - return 1; -} -""") - val command = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--top-module", - "ReducedScalarIssueQueueHeadIdentityProbe", - svPath.toString, - tbPath.toString, - "-Mdir", - objDir.toString - ) - val compileExit = Process(command, tmp.toFile).! - assert(compileExit == 0) - val runExit = Process(Seq(objDir.resolve("VReducedScalarIssueQueueHeadIdentityProbe").toString), tmp.toFile).! - assert(runExit == 0) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterBehaviorProbe.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterBehaviorProbe.scala deleted file mode 100644 index 059e011a..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterBehaviorProbe.scala +++ /dev/null @@ -1,120 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import org.scalatest.funsuite.AnyFunSuite - -class ReducedScalarWritebackArbiterBehaviorProbeIO extends Bundle { - val executeValid = Input(Bool()) - val executeTag = Input(UInt(6.W)) - val executeData = Input(UInt(64.W)) - - val replayEnable = Input(Bool()) - val replayValid = Input(Bool()) - val replayTag = Input(UInt(6.W)) - val replayData = Input(UInt(64.W)) - - val serviceEnable = Input(Bool()) - val serviceValid = Input(Bool()) - val serviceTag = Input(UInt(6.W)) - val serviceData = Input(UInt(64.W)) - - val templateEnable = Input(Bool()) - val templateValid = Input(Bool()) - val templateTag = Input(UInt(6.W)) - val templateData = Input(UInt(64.W)) - - val rfPortReady = Input(Bool()) - - val writeValid = Output(Bool()) - val writeTag = Output(UInt(6.W)) - val writeData = Output(UInt(64.W)) - val writeFire = Output(Bool()) - val templateAdvance = Output(Bool()) - - val selectedExecute = Output(Bool()) - val selectedReplay = Output(Bool()) - val selectedService = Output(Bool()) - val selectedTemplate = Output(Bool()) - val replayBlockedByDisabled = Output(Bool()) - val replayBlockedByExecute = Output(Bool()) - val serviceBlockedByDisabled = Output(Bool()) - val serviceBlockedByExecute = Output(Bool()) - val serviceBlockedByReplay = Output(Bool()) - val templateBlockedByDisabled = Output(Bool()) - val templateBlockedByExecute = Output(Bool()) - val templateBlockedByReplay = Output(Bool()) - val templateBlockedByService = Output(Bool()) -} - -class ReducedScalarWritebackArbiterBehaviorProbe extends Module { - val io = IO(new ReducedScalarWritebackArbiterBehaviorProbeIO) - - private val arbiter = Module(new ReducedScalarWritebackArbiter()) - - arbiter.io.executeValid := io.executeValid - arbiter.io.executeTag := io.executeTag - arbiter.io.executeData := io.executeData - - arbiter.io.replayEnable := io.replayEnable - arbiter.io.replayValid := io.replayValid - arbiter.io.replayTag := io.replayTag - arbiter.io.replayData := io.replayData - - arbiter.io.serviceEnable := io.serviceEnable - arbiter.io.serviceValid := io.serviceValid - arbiter.io.serviceTag := io.serviceTag - arbiter.io.serviceData := io.serviceData - - arbiter.io.templateEnable := io.templateEnable - arbiter.io.templateValid := io.templateValid - arbiter.io.templateTag := io.templateTag - arbiter.io.templateData := io.templateData - - private val selectedTemplate = arbiter.io.selectedTemplate - - io.writeValid := arbiter.io.writeValid - io.writeTag := arbiter.io.writeTag - io.writeData := arbiter.io.writeData - io.writeFire := arbiter.io.writeValid && io.rfPortReady - io.templateAdvance := selectedTemplate && arbiter.io.writeValid && io.rfPortReady - - io.selectedExecute := arbiter.io.selectedExecute - io.selectedReplay := arbiter.io.selectedReplay - io.selectedService := arbiter.io.selectedService - io.selectedTemplate := selectedTemplate - io.replayBlockedByDisabled := arbiter.io.replayBlockedByDisabled - io.replayBlockedByExecute := arbiter.io.replayBlockedByExecute - io.serviceBlockedByDisabled := arbiter.io.serviceBlockedByDisabled - io.serviceBlockedByExecute := arbiter.io.serviceBlockedByExecute - io.serviceBlockedByReplay := arbiter.io.serviceBlockedByReplay - io.templateBlockedByDisabled := arbiter.io.templateBlockedByDisabled - io.templateBlockedByExecute := arbiter.io.templateBlockedByExecute - io.templateBlockedByReplay := arbiter.io.templateBlockedByReplay - io.templateBlockedByService := arbiter.io.templateBlockedByService -} - -object EmitReducedScalarWritebackArbiterBehaviorProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/backend-reduced-scalar-writeback-arbiter-behavior-probe") - - ChiselStage.emitSystemVerilogFile( - new ReducedScalarWritebackArbiterBehaviorProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} - -class ReducedScalarWritebackArbiterBehaviorProbeSpec extends AnyFunSuite { - test("elaborates a public wrapper around the real scalar writeback arbiter") { - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarWritebackArbiterBehaviorProbe) - - assert(sv.contains("module ReducedScalarWritebackArbiterBehaviorProbe")) - assert(sv.contains("module ReducedScalarWritebackArbiter")) - assert(sv.contains("io_serviceEnable")) - assert(sv.contains("io_selectedService")) - assert(sv.contains("io_templateEnable")) - assert(sv.contains("io_selectedTemplate")) - assert(sv.contains("io_templateAdvance")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterSpec.scala deleted file mode 100644 index c0b55c36..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterSpec.scala +++ /dev/null @@ -1,254 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedScalarWritebackArbiterReference { - final case class Result( - writeValid: Boolean, - writeTag: Int, - writeData: BigInt, - selectedExecute: Boolean, - selectedReplay: Boolean, - selectedService: Boolean, - selectedTemplate: Boolean, - replayBlockedByDisabled: Boolean, - replayBlockedByExecute: Boolean, - serviceBlockedByDisabled: Boolean, - serviceBlockedByExecute: Boolean, - serviceBlockedByReplay: Boolean, - templateBlockedByDisabled: Boolean, - templateBlockedByExecute: Boolean, - templateBlockedByReplay: Boolean, - templateBlockedByService: Boolean) - - def apply( - executeValid: Boolean, - executeTag: Int, - executeData: BigInt, - replayEnable: Boolean, - replayValid: Boolean, - replayTag: Int, - replayData: BigInt, - serviceEnable: Boolean = false, - serviceValid: Boolean = false, - serviceTag: Int = 0, - serviceData: BigInt = 0, - templateEnable: Boolean = false, - templateValid: Boolean = false, - templateTag: Int = 0, - templateData: BigInt = 0): Result = { - val replayCandidate = replayEnable && replayValid - val serviceCandidate = serviceEnable && serviceValid - val templateCandidate = templateEnable && templateValid - val selectedExecute = executeValid - val selectedReplay = replayCandidate && !executeValid - val selectedService = serviceCandidate && !executeValid && !replayCandidate - val selectedTemplate = templateCandidate && !executeValid && !replayCandidate && !serviceCandidate - val selectedTag = - if (selectedExecute) executeTag - else if (selectedReplay) replayTag - else if (selectedService) serviceTag - else if (selectedTemplate) templateTag - else 0 - val selectedData = - if (selectedExecute) executeData - else if (selectedReplay) replayData - else if (selectedService) serviceData - else if (selectedTemplate) templateData - else BigInt(0) - - Result( - writeValid = selectedExecute || selectedReplay || selectedService || selectedTemplate, - writeTag = selectedTag, - writeData = selectedData, - selectedExecute = selectedExecute, - selectedReplay = selectedReplay, - selectedService = selectedService, - selectedTemplate = selectedTemplate, - replayBlockedByDisabled = !replayEnable && replayValid, - replayBlockedByExecute = replayCandidate && executeValid, - serviceBlockedByDisabled = !serviceEnable && serviceValid, - serviceBlockedByExecute = serviceCandidate && executeValid, - serviceBlockedByReplay = serviceCandidate && !executeValid && replayCandidate, - templateBlockedByDisabled = !templateEnable && templateValid, - templateBlockedByExecute = templateCandidate && executeValid, - templateBlockedByReplay = templateCandidate && !executeValid && replayCandidate, - templateBlockedByService = templateCandidate && !executeValid && !replayCandidate && serviceCandidate) - } -} - -class ReducedScalarWritebackArbiterSpec extends AnyFunSuite with ChiselSim { - import ReducedScalarWritebackArbiterReference._ - - test("selects execute writeback with priority over replay") { - val result = ReducedScalarWritebackArbiterReference( - executeValid = true, - executeTag = 5, - executeData = BigInt("1111222233334444", 16), - replayEnable = true, - replayValid = true, - replayTag = 42, - replayData = BigInt("aaaabbbbccccdddd", 16)) - - assert(result.writeValid) - assert(result.writeTag == 5) - assert(result.writeData == BigInt("1111222233334444", 16)) - assert(result.selectedExecute) - assert(!result.selectedReplay) - assert(!result.selectedService) - assert(!result.selectedTemplate) - assert(result.replayBlockedByExecute) - assert(!result.replayBlockedByDisabled) - } - - test("selects replay writeback when enabled and execute is idle") { - val result = ReducedScalarWritebackArbiterReference( - executeValid = false, - executeTag = 5, - executeData = 0x1111, - replayEnable = true, - replayValid = true, - replayTag = 42, - replayData = BigInt("aaaabbbbccccdddd", 16)) - - assert(result.writeValid) - assert(result.writeTag == 42) - assert(result.writeData == BigInt("aaaabbbbccccdddd", 16)) - assert(!result.selectedExecute) - assert(result.selectedReplay) - assert(!result.selectedService) - assert(!result.selectedTemplate) - assert(!result.replayBlockedByExecute) - assert(!result.replayBlockedByDisabled) - } - - test("blocks replay while disabled and suppresses stale write fields") { - val result = ReducedScalarWritebackArbiterReference( - executeValid = false, - executeTag = 5, - executeData = 0x1111, - replayEnable = false, - replayValid = true, - replayTag = 42, - replayData = 0x2222) - - assert(!result.writeValid) - assert(result.writeTag == 0) - assert(result.writeData == 0) - assert(!result.selectedExecute) - assert(!result.selectedReplay) - assert(!result.selectedService) - assert(!result.selectedTemplate) - assert(!result.replayBlockedByExecute) - assert(result.replayBlockedByDisabled) - } - - test("selects service after replay and before template") { - val result = ReducedScalarWritebackArbiterReference( - executeValid = false, - executeTag = 5, - executeData = 0x1111, - replayEnable = false, - replayValid = false, - replayTag = 42, - replayData = 0x2222, - serviceEnable = true, - serviceValid = true, - serviceTag = 17, - serviceData = BigInt("8877665544332211", 16), - templateEnable = true, - templateValid = true, - templateTag = 23, - templateData = 0x3333) - - assert(result.writeValid) - assert(result.writeTag == 17) - assert(result.writeData == BigInt("8877665544332211", 16)) - assert(result.selectedService) - assert(!result.selectedTemplate) - assert(result.templateBlockedByService) - } - - test("Chisel priority keeps service behind replay and ahead of template") { - simulate(new ReducedScalarWritebackArbiter()) { dut => - dut.io.executeValid.poke(false.B) - dut.io.executeTag.poke(5.U) - dut.io.executeData.poke(0x1111.U) - dut.io.replayEnable.poke(true.B) - dut.io.replayValid.poke(true.B) - dut.io.replayTag.poke(42.U) - dut.io.replayData.poke(0x2222.U) - dut.io.serviceEnable.poke(true.B) - dut.io.serviceValid.poke(true.B) - dut.io.serviceTag.poke(17.U) - dut.io.serviceData.poke(BigInt("8877665544332211", 16).U) - dut.io.templateEnable.poke(true.B) - dut.io.templateValid.poke(true.B) - dut.io.templateTag.poke(23.U) - dut.io.templateData.poke(0x3333.U) - - dut.io.writeValid.expect(true.B) - dut.io.writeTag.expect(42.U) - dut.io.selectedReplay.expect(true.B) - dut.io.selectedService.expect(false.B) - dut.io.serviceBlockedByReplay.expect(true.B) - dut.io.templateBlockedByService.expect(false.B) - - dut.io.replayValid.poke(false.B) - dut.io.writeValid.expect(true.B) - dut.io.writeTag.expect(17.U) - dut.io.writeData.expect(BigInt("8877665544332211", 16).U) - dut.io.selectedService.expect(true.B) - dut.io.selectedTemplate.expect(false.B) - dut.io.templateBlockedByService.expect(true.B) - - dut.io.serviceValid.poke(false.B) - dut.io.writeValid.expect(true.B) - dut.io.writeTag.expect(23.U) - dut.io.selectedTemplate.expect(true.B) - } - } - - test("selects template only after execute replay and service are idle") { - val result = ReducedScalarWritebackArbiterReference( - executeValid = false, - executeTag = 5, - executeData = 0x1111, - replayEnable = true, - replayValid = false, - replayTag = 42, - replayData = 0x2222, - serviceEnable = true, - serviceValid = false, - serviceTag = 17, - serviceData = 0x3333, - templateEnable = true, - templateValid = true, - templateTag = 23, - templateData = BigInt("abcdef", 16)) - - assert(result.writeValid) - assert(result.writeTag == 23) - assert(result.writeData == BigInt("abcdef", 16)) - assert(!result.selectedService) - assert(result.selectedTemplate) - } - - test("Chisel ReducedScalarWritebackArbiter elaborates arbitration diagnostics") { - val sv = ChiselStage.emitSystemVerilog(new ReducedScalarWritebackArbiter) - - assert(sv.contains("module ReducedScalarWritebackArbiter")) - assert(sv.contains("io_executeValid")) - assert(sv.contains("io_replayEnable")) - assert(sv.contains("io_selectedExecute")) - assert(sv.contains("io_selectedReplay")) - assert(sv.contains("io_selectedService")) - assert(sv.contains("io_selectedTemplate")) - assert(sv.contains("io_replayBlockedByExecute")) - assert(sv.contains("io_serviceBlockedByReplay")) - assert(sv.contains("io_templateBlockedByService")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ReducedTemplateContextStackSpec.scala b/chisel/src/test/scala/linxcore/execute/ReducedTemplateContextStackSpec.scala deleted file mode 100644 index 6b5319e6..00000000 --- a/chisel/src/test/scala/linxcore/execute/ReducedTemplateContextStackSpec.scala +++ /dev/null @@ -1,113 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class ReducedTemplateContextStackSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: ReducedTemplateContextStack): Unit = { - dut.io.flush.poke(false.B) - dut.io.cancel.poke(false.B) - dut.io.captureStart.poke(false.B) - dut.io.captureStartArch.poke(0.U) - dut.io.captureEndArch.poke(0.U) - dut.io.captureReadReady.poke(false.B) - dut.io.captureReadData.poke(0.U) - dut.io.restoreStart.poke(false.B) - dut.io.restoreWriteReady.poke(false.B) - for (arch <- 0 until 24) { - dut.io.captureMap(arch).poke(arch.U) - dut.io.restoreMap(arch).poke((arch + 24).U) - } - } - - private def capture( - dut: ReducedTemplateContextStack, - start: Int, - end: Int, - dataBase: Int): Unit = { - dut.io.captureStartArch.poke(start.U) - dut.io.captureEndArch.poke(end.U) - dut.io.captureStart.poke(true.B) - dut.clock.step() - dut.io.captureStart.poke(false.B) - while (dut.io.captureBusy.peek().litToBoolean) { - val tag = dut.io.captureReadTag.peek().litValue.toInt - dut.io.captureReadReady.poke(true.B) - dut.io.captureReadData.poke((dataBase + tag).U) - dut.clock.step() - } - dut.io.captureReadReady.poke(false.B) - } - - private def restore(dut: ReducedTemplateContextStack): Seq[(Int, Int)] = { - dut.io.restoreStart.poke(true.B) - dut.clock.step() - dut.io.restoreStart.poke(false.B) - val writes = scala.collection.mutable.ArrayBuffer.empty[(Int, Int)] - while (dut.io.restoreBusy.peek().litToBoolean) { - writes += (( - dut.io.restoreWriteTag.peek().litValue.toInt, - dut.io.restoreWriteData.peek().litValue.toInt)) - dut.io.restoreWriteReady.poke(true.B) - dut.clock.step() - } - dut.io.restoreWriteReady.poke(false.B) - writes.toSeq - } - - test("nested template frames restore in LIFO register-ring order") { - simulate(new ReducedTemplateContextStack(frameDepth = 4)) { dut => - clear(dut) - - capture(dut, start = 10, end = 12, dataBase = 1000) - dut.io.frameCount.expect(1.U) - capture(dut, start = 22, end = 3, dataBase = 2000) - dut.io.frameCount.expect(2.U) - - assert(restore(dut) == Seq( - (46, 2022), - (47, 2023), - (26, 2002), - (27, 2003))) - dut.io.frameCount.expect(1.U) - - assert(restore(dut) == Seq( - (34, 1010), - (35, 1011), - (36, 1012))) - dut.io.frameCount.expect(0.U) - dut.io.overflow.expect(false.B) - dut.io.underflow.expect(false.B) - } - } - - test("suffix recovery cancels an in-flight restore without popping the committed frame") { - simulate(new ReducedTemplateContextStack(frameDepth = 4)) { dut => - clear(dut) - capture(dut, start = 10, end = 12, dataBase = 1000) - dut.io.frameCount.expect(1.U) - - dut.io.restoreStart.poke(true.B) - dut.clock.step() - dut.io.restoreStart.poke(false.B) - dut.io.restoreBusy.expect(true.B) - dut.io.restoreWriteReady.poke(true.B) - dut.clock.step() - - dut.io.cancel.poke(true.B) - dut.clock.step() - dut.io.cancel.poke(false.B) - dut.io.restoreWriteReady.poke(false.B) - dut.io.restoreBusy.expect(false.B) - dut.io.restoreDone.expect(false.B) - dut.io.frameCount.expect(1.U) - - assert(restore(dut) == Seq( - (34, 1010), - (35, 1011), - (36, 1012))) - dut.io.frameCount.expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ScalarGPRFileSpec.scala b/chisel/src/test/scala/linxcore/execute/ScalarGPRFileSpec.scala deleted file mode 100644 index f75605cd..00000000 --- a/chisel/src/test/scala/linxcore/execute/ScalarGPRFileSpec.scala +++ /dev/null @@ -1,62 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ScalarGPRFileReference { - final case class Write(request: Boolean, commit: Boolean, tag: Int, data: Long) - final case class Result(fire: Vector[Boolean], ready: Vector[Boolean]) - - def arbitrate(writes: Vector[Write]): Result = { - val ready = writes.indices.map { port => - writes(port).request && !writes.indices.take(port).exists { higher => - writes(higher).request && writes(higher).tag == writes(port).tag - } - }.toVector - Result( - fire = writes.indices.map(port => ready(port) && writes(port).commit).toVector, - ready = ready - ) - } -} - -class ScalarGPRFileSpec extends AnyFunSuite { - import ScalarGPRFileReference._ - - test("request reserves a write port but only commit mutates state") { - val held = arbitrate(Vector(Write(request = true, commit = false, tag = 40, data = 1))) - assert(held.ready == Vector(true)) - assert(held.fire == Vector(false)) - - val committed = arbitrate(Vector(Write(request = true, commit = true, tag = 40, data = 1))) - assert(committed.fire == Vector(true)) - } - - test("higher port priority blocks only a duplicate tag") { - val duplicate = arbitrate(Vector( - Write(request = true, commit = true, tag = 40, data = 1), - Write(request = true, commit = true, tag = 40, data = 2))) - assert(duplicate.ready == Vector(true, false)) - assert(duplicate.fire == Vector(true, false)) - - val independent = arbitrate(Vector( - Write(request = true, commit = true, tag = 40, data = 1), - Write(request = true, commit = true, tag = 41, data = 2))) - assert(independent.fire == Vector(true, true)) - } - - test("canonical scalar GPR file elaborates parameterized ports and ready state") { - val sv = ChiselStage.emitSystemVerilog(new ScalarGPRFile( - archRegs = 24, - physRegs = 128, - dataWidth = 64, - readPorts = 2, - writePorts = 2 - )) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("io_write_0_requestValid")) - assert(sv.contains("io_write_1_blockedByHigherSameTag")) - assert(sv.contains("io_readyMask")) - assert(sv.contains("io_protocolError")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ScalarIssueCandidateArbiterSpec.scala b/chisel/src/test/scala/linxcore/execute/ScalarIssueCandidateArbiterSpec.scala deleted file mode 100644 index 73f072d9..00000000 --- a/chisel/src/test/scala/linxcore/execute/ScalarIssueCandidateArbiterSpec.scala +++ /dev/null @@ -1,31 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import linxcore.common.InterfaceParams -import org.scalatest.funsuite.AnyFunSuite - -class ScalarIssueCandidateArbiterSpec extends AnyFunSuite { - test("candidate arbiter exposes per-STID oldest and round-robin grant state") { - val io = new ScalarIssueCandidateArbiterIO(InterfaceParams(), candidates = 2) - - assert(io.valid.length == 2) - assert(io.stid.length == 2) - assert(io.rid.length == 2) - assert(io.grant.length == 2) - assert(io.selectedIndex.getWidth == 1) - assert(io.candidateCount.getWidth == 2) - assert(io.rrBase.getWidth == 1) - } - - test("candidate arbiter elaborates fair grant and invalid-RID diagnostics") { - val sv = ChiselStage.emitSystemVerilog( - new ScalarIssueCandidateArbiter(InterfaceParams(), candidates = 2)) - - assert(sv.contains("module ScalarIssueCandidateArbiter")) - assert(sv.contains("io_grant_0")) - assert(sv.contains("io_selectedIndex")) - assert(sv.contains("io_contended")) - assert(sv.contains("io_invalidRid")) - assert(sv.contains("rrBase")) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ScalarIssueFabricSpec.scala b/chisel/src/test/scala/linxcore/execute/ScalarIssueFabricSpec.scala deleted file mode 100644 index fdf1532c..00000000 --- a/chisel/src/test/scala/linxcore/execute/ScalarIssueFabricSpec.scala +++ /dev/null @@ -1,1091 +0,0 @@ -package linxcore.execute - -import circt.stage.ChiselStage -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Enum, is, switch} -import linxcore.common.{DestinationKind, DispatchTarget, InterfaceParams, OperandClass, RenamedUop} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rob.ROBID -import org.scalatest.funsuite.AnyFunSuite - -import java.nio.file.Files -import scala.sys.process._ - -class ScalarIssueFabricHeadIdentityProbeIO(val p: InterfaceParams) extends Bundle { - val done = Output(Bool()) - val failure = Output(Bool()) -} - -class ScalarIssueFabricHeadIdentityProbe extends Module { - val p = InterfaceParams(robEntries = 16) - val io = IO(new ScalarIssueFabricHeadIdentityProbeIO(p)) - - val fabric = Module(new ScalarIssueFabric(p, depth = 8, bankCount = 2, stidCount = 1)) - val cycle = RegInit(0.U(8.W)) - val producerReady = RegInit(false.B) - val observedFirstBank = RegInit(false.B) - val observedSecondBank = RegInit(false.B) - val failure = RegInit(false.B) - cycle := cycle + 1.U - - val Seq(sEnqueueFirst, sEnqueueSecond, sObserveFirst, sDrainFirst, sObserveSecond, sDone) = Enum(6) - val state = RegInit(sEnqueueFirst) - - def row(stid: Int, bidWrap: Boolean, bidValue: Int, ridWrap: Boolean, ridValue: Int, pc: Long): linxcore.common.RenamedUop = { - val uop = Wire(new linxcore.common.RenamedUop(p)) - uop := 0.U.asTypeOf(uop) - uop.valid := true.B - uop.threadId := stid.U - uop.pc := pc.U - uop.opcode := FrontendOpcodeDecodeTable.OP_ADDI.U(p.opcodeWidth.W) - uop.dispatchTarget := DispatchTarget.Alu - uop.bid.valid := true.B - uop.bid.wrap := bidWrap.B - uop.bid.value := bidValue.U - uop.rid.valid := true.B - uop.rid.wrap := ridWrap.B - uop.rid.value := ridValue.U - uop.src(0).valid := true.B - uop.src(0).operandClass := OperandClass.P - uop.src(0).archTag := 8.U - uop.src(0).relTag := 8.U - uop.src(0).physTag := 8.U - uop - } - - val first = row(stid = 1, bidWrap = true, bidValue = 2, ridWrap = false, ridValue = 3, pc = 0x1000L) - val second = row(stid = 4, bidWrap = false, bidValue = 5, ridWrap = true, ridValue = 6, pc = 0x2000L) - - fabric.io.inValid := state === sEnqueueFirst || state === sEnqueueSecond - fabric.io.in := Mux(state === sEnqueueFirst, first, second) - fabric.io.flushValid := false.B - fabric.io.releaseValid := fabric.io.issueFire - fabric.io.releaseBid := fabric.io.issueUop.bid - fabric.io.releaseRid := fabric.io.issueUop.rid - fabric.io.releaseStid := fabric.io.issueUop.threadId - fabric.io.secondaryReleaseValid := false.B - fabric.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseStid := 0.U - fabric.io.tertiaryReleaseValid := false.B - fabric.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseStid := 0.U - fabric.io.externalControlFenceValid := false.B - fabric.io.externalControlFenceBid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceRid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceStid := 0.U - fabric.io.scalarSpHeadValidByStid(0) := false.B - fabric.io.scalarSpHeadBidByStid(0) := ROBID.disabled(p.robEntries) - fabric.io.scalarSpHeadRidByStid(0) := ROBID.disabled(p.robEntries) - fabric.io.scalarSpSnapshotByStid(0) := 0.U - fabric.io.readyMask := Mux(producerReady, 1.U << 8.U, 0.U) - fabric.io.pWakeupValid := false.B - fabric.io.pWakeupTag := 0.U - fabric.io.localTReadyMask := 0.U - fabric.io.localUReadyMask := 0.U - fabric.io.issueReady := true.B - for (lane <- 0 until 3) { - fabric.io.readData(lane) := (0x300 + lane).U - } - - val firstIdentity = - fabric.io.headValid && - fabric.io.headPc === 0x1000.U && - fabric.io.headStid === 1.U && - fabric.io.headBid.valid && - fabric.io.headBid.wrap && - fabric.io.headBid.value === 2.U && - fabric.io.headRid.valid && - !fabric.io.headRid.wrap && - fabric.io.headRid.value === 3.U - val secondIdentity = - fabric.io.headValid && - fabric.io.headPc === 0x2000.U && - fabric.io.headStid === 4.U && - fabric.io.headBid.valid && - !fabric.io.headBid.wrap && - fabric.io.headBid.value === 5.U && - fabric.io.headRid.valid && - fabric.io.headRid.wrap && - fabric.io.headRid.value === 6.U - - when(state === sObserveFirst && fabric.io.bankOccupancy(0) === 1.U && fabric.io.bankOccupancy(1) === 1.U) { - observedFirstBank := firstIdentity - when(!firstIdentity) { - failure := true.B - } - } - when(state === sObserveSecond && fabric.io.bankOccupancy(0) === 0.U && fabric.io.bankOccupancy(1) === 1.U) { - observedSecondBank := secondIdentity - when(!secondIdentity) { - failure := true.B - } - } - when(cycle > 80.U && !observedSecondBank) { - failure := true.B - } - - switch(state) { - is(sEnqueueFirst) { - when(fabric.io.enqueueFire) { - state := sEnqueueSecond - } - } - is(sEnqueueSecond) { - when(fabric.io.enqueueFire) { - state := sObserveFirst - } - } - is(sObserveFirst) { - when(observedFirstBank) { - producerReady := true.B - state := sDrainFirst - } - } - is(sDrainFirst) { - when(fabric.io.releaseFire) { - producerReady := false.B - state := sObserveSecond - } - } - is(sObserveSecond) { - when(observedSecondBank) { - state := sDone - } - } - } - - io.done := state === sDone - io.failure := failure -} - -class ScalarIssueFabricRedirectAgeProbeIO extends Bundle { - val done = Output(Bool()) - val failure = Output(Bool()) - val observedRedirectBlocked = Output(Bool()) -} - -class ScalarIssueFabricRedirectAgeProbe extends Module { - val p = InterfaceParams(robEntries = 16) - val io = IO(new ScalarIssueFabricRedirectAgeProbeIO) - - val fabric = Module(new ScalarIssueFabric(p, depth = 8, bankCount = 2, stidCount = 1)) - val cycle = RegInit(0.U(8.W)) - val enqueueCount = RegInit(0.U(2.W)) - val olderReady = RegInit(false.B) - val olderIssueSeen = RegInit(false.B) - val redirectIssueSeen = RegInit(false.B) - val observedRedirectBlocked = RegInit(false.B) - val failure = RegInit(false.B) - val releasePending = RegInit(false.B) - val releaseBid = Reg(new ROBID(p.robEntries)) - val releaseRid = Reg(new ROBID(p.robEntries)) - val releaseStid = Reg(UInt(p.threadIdWidth.W)) - cycle := cycle + 1.U - - def row( - opcode: Int, - dispatch: DispatchTarget.Type, - bidValue: Int, - ridWrap: Boolean, - ridValue: Int, - pc: Long): linxcore.common.RenamedUop = { - val uop = Wire(new linxcore.common.RenamedUop(p)) - uop := 0.U.asTypeOf(uop) - uop.valid := true.B - uop.threadId := 0.U - uop.pc := pc.U - uop.opcode := opcode.U(p.opcodeWidth.W) - uop.dispatchTarget := dispatch - uop.bid.valid := true.B - uop.bid.wrap := false.B - uop.bid.value := bidValue.U - uop.rid.valid := true.B - uop.rid.wrap := ridWrap.B - uop.rid.value := ridValue.U - uop - } - - // RID is globally ordered within one STID even when the rows cross a BID - // boundary. With 16 ROB rows, (wrap=1,value=1) is newer than - // (wrap=0,value=14). - val older = row( - FrontendOpcodeDecodeTable.OP_ADDI, - DispatchTarget.Alu, - bidValue = 3, - ridWrap = false, - ridValue = 14, - pc = 0x1000L) - older.src(0).valid := true.B - older.src(0).operandClass := OperandClass.P - older.src(0).archTag := 8.U - older.src(0).relTag := 8.U - older.src(0).physTag := 8.U - val redirect = - row( - FrontendOpcodeDecodeTable.OP_FRET_STK, - DispatchTarget.Cmd, - bidValue = 4, - ridWrap = true, - ridValue = 1, - pc = 0x1004L) - - fabric.io.inValid := enqueueCount =/= 2.U - fabric.io.in := Mux(enqueueCount === 0.U, older, redirect) - when(fabric.io.enqueueFire) { - enqueueCount := enqueueCount + 1.U - } - fabric.io.flushValid := false.B - fabric.io.releaseValid := releasePending - fabric.io.releaseBid := releaseBid - fabric.io.releaseRid := releaseRid - fabric.io.releaseStid := releaseStid - fabric.io.secondaryReleaseValid := false.B - fabric.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseStid := 0.U - fabric.io.tertiaryReleaseValid := false.B - fabric.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseStid := 0.U - fabric.io.externalControlFenceValid := false.B - fabric.io.externalControlFenceBid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceRid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceStid := 0.U - fabric.io.scalarSpHeadValidByStid(0) := true.B - fabric.io.scalarSpHeadBidByStid(0) := redirect.bid - fabric.io.scalarSpHeadRidByStid(0) := redirect.rid - fabric.io.scalarSpSnapshotByStid(0) := 0.U - fabric.io.readyMask := Mux(olderReady, 1.U << 8.U, 0.U) - fabric.io.pWakeupValid := false.B - fabric.io.pWakeupTag := 0.U - fabric.io.localTReadyMask := 0.U - fabric.io.localUReadyMask := 0.U - fabric.io.issueReady := true.B - for (lane <- 0 until 3) { - fabric.io.readData(lane) := (0x400 + lane).U - } - - releasePending := false.B - when(fabric.io.issueFire) { - releasePending := true.B - releaseBid := fabric.io.issueUop.bid - releaseRid := fabric.io.issueUop.rid - releaseStid := fabric.io.issueUop.threadId - val issuedOlder = - ROBID.equal(fabric.io.issueUop.bid, older.bid) && - ROBID.equal(fabric.io.issueUop.rid, older.rid) - val issuedRedirect = - ROBID.equal(fabric.io.issueUop.bid, redirect.bid) && - ROBID.equal(fabric.io.issueUop.rid, redirect.rid) - when(issuedOlder) { - olderIssueSeen := true.B - }.elsewhen(issuedRedirect) { - redirectIssueSeen := true.B - when(!olderIssueSeen) { - failure := true.B - } - }.otherwise { - failure := true.B - } - } - when(fabric.io.controlFenceBlocked) { - observedRedirectBlocked := true.B - } - when(enqueueCount === 2.U && cycle > 10.U) { - olderReady := true.B - } - when(cycle > 80.U && !redirectIssueSeen) { - failure := true.B - } - - io.done := olderIssueSeen && redirectIssueSeen - io.failure := failure - io.observedRedirectBlocked := observedRedirectBlocked -} - -class ScalarIssueFabricDifferentStidProbeIO extends Bundle { - val done = Output(Bool()) - val failure = Output(Bool()) -} - -class ScalarIssueFabricDifferentStidProbe extends Module { - val p = InterfaceParams(robEntries = 16) - val io = IO(new ScalarIssueFabricDifferentStidProbeIO) - - val fabric = Module(new ScalarIssueFabric(p, depth = 8, bankCount = 2, stidCount = 2)) - val cycle = RegInit(0.U(8.W)) - val enqueueCount = RegInit(0.U(2.W)) - val redirectIssueSeen = RegInit(false.B) - val failure = RegInit(false.B) - cycle := cycle + 1.U - - def row( - stid: Int, - opcode: Int, - dispatch: DispatchTarget.Type, - bidValue: Int, - ridWrap: Boolean, - ridValue: Int, - pc: Long): linxcore.common.RenamedUop = { - val uop = Wire(new linxcore.common.RenamedUop(p)) - uop := 0.U.asTypeOf(uop) - uop.valid := true.B - uop.threadId := stid.U - uop.pc := pc.U - uop.opcode := opcode.U(p.opcodeWidth.W) - uop.dispatchTarget := dispatch - uop.bid.valid := true.B - uop.bid.wrap := false.B - uop.bid.value := bidValue.U - uop.rid.valid := true.B - uop.rid.wrap := ridWrap.B - uop.rid.value := ridValue.U - uop - } - - val olderOtherStid = row( - stid = 1, - opcode = FrontendOpcodeDecodeTable.OP_ADDI, - dispatch = DispatchTarget.Alu, - bidValue = 3, - ridWrap = false, - ridValue = 14, - pc = 0x2000L) - olderOtherStid.src(0).valid := true.B - olderOtherStid.src(0).operandClass := OperandClass.P - olderOtherStid.src(0).archTag := 8.U - olderOtherStid.src(0).relTag := 8.U - olderOtherStid.src(0).physTag := 8.U - val redirect = row( - stid = 0, - opcode = FrontendOpcodeDecodeTable.OP_FRET_STK, - dispatch = DispatchTarget.Cmd, - bidValue = 4, - ridWrap = true, - ridValue = 1, - pc = 0x2004L) - - fabric.io.inValid := enqueueCount =/= 2.U - fabric.io.in := Mux(enqueueCount === 0.U, olderOtherStid, redirect) - when(fabric.io.enqueueFire) { - enqueueCount := enqueueCount + 1.U - } - fabric.io.flushValid := false.B - fabric.io.releaseValid := false.B - fabric.io.releaseBid := ROBID.disabled(p.robEntries) - fabric.io.releaseRid := ROBID.disabled(p.robEntries) - fabric.io.releaseStid := 0.U - fabric.io.secondaryReleaseValid := false.B - fabric.io.secondaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.secondaryReleaseStid := 0.U - fabric.io.tertiaryReleaseValid := false.B - fabric.io.tertiaryReleaseBid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseRid := ROBID.disabled(p.robEntries) - fabric.io.tertiaryReleaseStid := 0.U - fabric.io.externalControlFenceValid := false.B - fabric.io.externalControlFenceBid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceRid := ROBID.disabled(p.robEntries) - fabric.io.externalControlFenceStid := 0.U - fabric.io.scalarSpHeadValidByStid(0) := true.B - fabric.io.scalarSpHeadBidByStid(0) := redirect.bid - fabric.io.scalarSpHeadRidByStid(0) := redirect.rid - fabric.io.scalarSpSnapshotByStid(0) := 0.U - fabric.io.scalarSpHeadValidByStid(1) := false.B - fabric.io.scalarSpHeadBidByStid(1) := ROBID.disabled(p.robEntries) - fabric.io.scalarSpHeadRidByStid(1) := ROBID.disabled(p.robEntries) - fabric.io.scalarSpSnapshotByStid(1) := 0.U - fabric.io.readyMask := 0.U - fabric.io.pWakeupValid := false.B - fabric.io.pWakeupTag := 0.U - fabric.io.localTReadyMask := 0.U - fabric.io.localUReadyMask := 0.U - fabric.io.issueReady := true.B - for (lane <- 0 until 3) { - fabric.io.readData(lane) := (0x500 + lane).U - } - - when(fabric.io.controlFenceBlocked) { - failure := true.B - } - when(fabric.io.issueFire) { - val isRedirect = - (fabric.io.issueUop.threadId === redirect.threadId) && - ROBID.equal(fabric.io.issueUop.bid, redirect.bid) && - ROBID.equal(fabric.io.issueUop.rid, redirect.rid) - when(isRedirect) { - redirectIssueSeen := true.B - when(fabric.io.count =/= 2.U || - fabric.io.bankOccupancy(0) =/= 1.U || - fabric.io.bankOccupancy(1) =/= 1.U) { - failure := true.B - } - }.otherwise { - failure := true.B - } - } - when(cycle > 80.U && !redirectIssueSeen) { - failure := true.B - } - - io.done := redirectIssueSeen - io.failure := failure -} - -class ScalarIssueFabricSpec extends AnyFunSuite with ChiselSim { - private val SimP = InterfaceParams(robEntries = 16) - private val AllReadyMask = (BigInt(1) << (1 << SimP.physRegWidth)) - 1 - - private def pokeRobId(id: ROBID, valid: Boolean, wrap: Boolean, value: Int): Unit = { - id.valid.poke(valid.B) - id.wrap.poke(wrap.B) - id.value.poke(value.U) - } - - private def pokeFabricRow(row: RenamedUop, ridValue: Int, dstTag: Int): Unit = { - row.poke(0.U.asTypeOf(row)) - row.valid.poke(true.B) - row.threadId.poke(0.U) - row.pc.poke((0x20000L + ridValue).U) - row.opcode.poke(FrontendOpcodeDecodeTable.OP_ADDI.U(SimP.opcodeWidth.W)) - row.dispatchTarget.poke(DispatchTarget.Alu) - pokeRobId(row.bid, valid = true, wrap = false, value = 0) - pokeRobId(row.gid, valid = true, wrap = false, value = 0) - pokeRobId(row.rid, valid = true, wrap = false, value = ridValue) - row.src(0).valid.poke(true.B) - row.src(0).operandClass.poke(OperandClass.P) - row.src(0).archTag.poke(8.U) - row.src(0).relTag.poke(8.U) - row.src(0).physTag.poke(8.U) - row.dst(0).valid.poke(true.B) - row.dst(0).kind.poke(DestinationKind.Gpr) - row.dst(0).archTag.poke(dstTag.U) - row.dst(0).relTag.poke(dstTag.U) - row.dst(0).physTag.poke(dstTag.U) - } - - private def initFabric(dut: ScalarIssueFabric): Unit = { - dut.io.inValid.poke(false.B) - pokeFabricRow(dut.io.in, ridValue = 0, dstTag = 9) - dut.io.flushValid.poke(false.B) - dut.io.releaseValid.poke(false.B) - pokeRobId(dut.io.releaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.releaseRid, valid = false, wrap = false, value = 0) - dut.io.releaseStid.poke(0.U) - dut.io.secondaryReleaseValid.poke(false.B) - pokeRobId(dut.io.secondaryReleaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.secondaryReleaseRid, valid = false, wrap = false, value = 0) - dut.io.secondaryReleaseStid.poke(0.U) - dut.io.tertiaryReleaseValid.poke(false.B) - pokeRobId(dut.io.tertiaryReleaseBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.tertiaryReleaseRid, valid = false, wrap = false, value = 0) - dut.io.tertiaryReleaseStid.poke(0.U) - dut.io.externalControlFenceValid.poke(false.B) - pokeRobId(dut.io.externalControlFenceBid, valid = false, wrap = false, value = 0) - pokeRobId(dut.io.externalControlFenceRid, valid = false, wrap = false, value = 0) - dut.io.externalControlFenceStid.poke(0.U) - dut.io.scalarSpHeadValidByStid(0).poke(false.B) - pokeRobId(dut.io.scalarSpHeadBidByStid(0), valid = false, wrap = false, value = 0) - pokeRobId(dut.io.scalarSpHeadRidByStid(0), valid = false, wrap = false, value = 0) - dut.io.scalarSpSnapshotByStid(0).poke(0.U) - dut.io.readyMask.poke(AllReadyMask.U) - dut.io.pWakeupValid.poke(false.B) - dut.io.pWakeupTag.poke(0.U) - dut.io.localTReadyMask.poke(0.U) - dut.io.localUReadyMask.poke(0.U) - dut.io.issueReady.poke(true.B) - for (lane <- 0 until 3) { - dut.io.readData(lane).poke((0x700 + lane).U) - } - } - - private def pokeRelease( - valid: Bool, - bid: ROBID, - rid: ROBID, - stid: UInt, - fire: Boolean, - ridValue: Int): Unit = { - valid.poke(fire.B) - pokeRobId(bid, valid = fire, wrap = false, value = 0) - pokeRobId(rid, valid = fire, wrap = false, value = ridValue) - stid.poke(0.U) - } - - private def enqueueFabric( - dut: ScalarIssueFabric, - ridValue: Int, - expectedBankEnqueues: Int, - expectedMask: Int, - opcode: Int = FrontendOpcodeDecodeTable.OP_ADDI, - dispatch: DispatchTarget.Type = DispatchTarget.Alu, - isStore: Boolean = false, - expectedBankRid0: Option[Int] = None, - expectedBankRid1: Option[Int] = None): Unit = { - dut.io.inValid.poke(true.B) - pokeFabricRow(dut.io.in, ridValue = ridValue, dstTag = 10 + ridValue) - dut.io.in.opcode.poke(opcode.U(SimP.opcodeWidth.W)) - dut.io.in.dispatchTarget.poke(dispatch) - dut.io.in.isStore.poke(isStore.B) - dut.io.inReady.expect(true.B) - dut.io.inputAcceptFire.expect(true.B) - dut.io.inputAcceptUop.rid.value.expect(ridValue.U) - dut.io.inputAcceptDstValid.expect(true.B) - dut.io.inputAcceptDstTag.expect((10 + ridValue).U) - dut.io.enqueueFire.expect(true.B) - dut.io.enqueueCount.expect(expectedBankEnqueues.U) - dut.io.bankEnqueueFireMask.expect(expectedMask.U) - expectedBankRid0.foreach(rid => dut.io.bankEnqueueUop(0).rid.value.expect(rid.U)) - expectedBankRid1.foreach(rid => dut.io.bankEnqueueUop(1).rid.value.expect(rid.U)) - dut.clock.step() - dut.io.inValid.poke(false.B) - } - - private def issueCycle( - dut: ScalarIssueFabric, - issueRid: Int, - releaseRid: Option[Int] = None): Unit = { - releaseRid match { - case Some(rid) => - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, rid) - case None => - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - } - dut.io.inValid.poke(false.B) - dut.io.issueReady.poke(true.B) - dut.io.issueFire.expect(true.B) - dut.io.issueUop.rid.value.expect(issueRid.U) - dut.clock.step() - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - } - - private def releaseIssuedPair(dut: ScalarIssueFabric, firstRid: Int, secondRid: Int): Unit = { - dut.io.inValid.poke(false.B) - dut.io.issueReady.poke(false.B) - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, firstRid) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = true, - secondRid) - dut.io.releaseFire.expect(true.B) - dut.clock.step() - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = false, - 0) - } - - private def enqueueFabricWithReleases( - dut: ScalarIssueFabric, - ridValue: Int, - expectedBankEnqueues: Int, - expectedMask: Int, - primaryReleaseRid: Option[Int] = None, - secondaryReleaseRid: Option[Int] = None, - expectedBankRid0: Option[Int] = None, - expectedBankRid1: Option[Int] = None): Unit = { - primaryReleaseRid match { - case Some(rid) => - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, rid) - case None => - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - } - secondaryReleaseRid match { - case Some(rid) => - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = true, - rid) - case None => - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = false, - 0) - } - enqueueFabric( - dut, - ridValue = ridValue, - expectedBankEnqueues = expectedBankEnqueues, - expectedMask = expectedMask, - expectedBankRid0 = expectedBankRid0, - expectedBankRid1 = expectedBankRid1) - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = false, - 0) - } - - test("fabric preserves total capacity while exposing bank arbitration") { - val p = InterfaceParams() - val io = new ScalarIssueFabricIO(p, depth = 8, bankCount = 2) - - assert(io.count.getWidth == 4) - assert(io.inputAcceptUop.pc.getWidth == p.pcWidth) - assert(io.inputAcceptDstTag.getWidth == p.physRegWidth) - assert(io.enqueueCount.getWidth == 2) - assert(io.bankEnqueueFireMask.getWidth == 2) - assert(io.bankEnqueueUop.length == 2) - assert(io.selectedIndex.getWidth == 3) - assert(io.bankOccupancy.length == 2) - assert(io.bankOccupancy.head.getWidth == 3) - assert(io.bankPickMask.getWidth == 2) - assert(io.bankReadAttemptMask.getWidth == 2) - assert(io.bankReadGrantMask.getWidth == 2) - assert(io.bankIssueValidMask.getWidth == 2) - assert(io.bankIssueGrantMask.getWidth == 2) - assert(io.bankControlBlockedMask.getWidth == 2) - assert(io.bankStoreOrderBlockedMask.getWidth == 2) - assert(io.tertiaryReleaseBid.value.getWidth == p.robIndexWidth) - assert(io.tertiaryReleaseRid.value.getWidth == p.robIndexWidth) - assert(io.tertiaryReleaseStid.getWidth == p.threadIdWidth) - assert(io.scalarSpHeadValidByStid.length == 1) - assert(io.scalarSpHeadBidByStid.head.value.getWidth == p.robIndexWidth) - assert(io.scalarSpHeadRidByStid.head.value.getWidth == p.robIndexWidth) - assert(io.bankScalarSpOrderBlockedMask.getWidth == 2) - assert(io.headStid.getWidth == p.threadIdWidth) - assert(io.headBid.valid.getWidth == 1) - assert(io.headBid.wrap.getWidth == 1) - assert(io.headBid.value.getWidth == p.robIndexWidth) - assert(io.headRid.valid.getWidth == 1) - assert(io.headRid.wrap.getWidth == 1) - assert(io.headRid.value.getWidth == p.robIndexWidth) - } - - test("fabric elaborates resident banks plus I1 and I2 arbiters") { - val sv = ChiselStage.emitSystemVerilog( - new ScalarIssueFabric(InterfaceParams(), depth = 8, bankCount = 2)) - - assert(sv.contains("module ScalarIssueFabric")) - assert(sv.contains("module ReducedScalarIssueQueue")) - assert(sv.contains("module ScalarIssueIngressSkid2")) - assert(sv.contains("module ScalarIssueCandidateArbiter")) - assert(sv.contains("io_inputAcceptFire")) - assert(sv.contains("io_inputAcceptDstValid")) - assert(sv.contains("io_enqueueCount")) - assert(sv.contains("io_bankEnqueueFireMask")) - assert(sv.contains("io_bankOccupancy_0")) - assert(sv.contains("io_readContention")) - assert(sv.contains("io_readArbitrationLoss")) - assert(sv.contains("io_issueContention")) - assert(sv.contains("io_controlFenceActive")) - assert(sv.contains("io_controlFenceBlocked")) - assert(sv.contains("io_storeOrderBlocked")) - assert(sv.contains("io_tertiaryReleaseValid")) - assert(sv.contains("io_scalarSpHeadValidByStid")) - assert(sv.contains("io_scalarSpOrderBlocked")) - assert(sv.contains("io_headStid")) - assert(sv.contains("io_headBid_valid")) - assert(sv.contains("io_headBid_wrap")) - assert(sv.contains("io_headBid_value")) - assert(sv.contains("io_headRid_valid")) - assert(sv.contains("io_headRid_wrap")) - assert(sv.contains("io_headRid_value")) - } - - test("DUT preserves empty zero-bubble enqueue through the ingress skid") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - dut.io.count.expect(1.U) - dut.io.bankOccupancy(0).expect(1.U) - dut.io.bankOccupancy(1).expect(0.U) - dut.io.empty.expect(false.B) - } - } - - test("DUT dual-enqueues a skid resident plus current input to different ready banks") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 2, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 3, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 4, expectedBankEnqueues = 1, expectedMask = 2) - dut.io.bankOccupancy(0).expect(2.U) - dut.io.bankOccupancy(1).expect(2.U) - - enqueueFabric(dut, ridValue = 5, expectedBankEnqueues = 0, expectedMask = 0) - dut.io.count.expect(5.U) - dut.io.bankOccupancy(0).expect(2.U) - dut.io.bankOccupancy(1).expect(2.U) - - issueCycle(dut, issueRid = 1) - issueCycle(dut, issueRid = 2) - enqueueFabricWithReleases( - dut, - ridValue = 6, - expectedBankEnqueues = 2, - expectedMask = 3, - primaryReleaseRid = Some(1), - secondaryReleaseRid = Some(2), - expectedBankRid0 = Some(5), - expectedBankRid1 = Some(6)) - dut.io.count.expect(4.U) - dut.io.bankOccupancy(0).expect(2.U) - dut.io.bankOccupancy(1).expect(2.U) - } - } - - test("DUT does not enqueue the younger input when only the younger bank is ready") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 2, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 3, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 4, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 5, expectedBankEnqueues = 0, expectedMask = 0) - - issueCycle(dut, issueRid = 1) - issueCycle(dut, issueRid = 2) - issueCycle(dut, issueRid = 3, releaseRid = Some(2)) - dut.io.bankOccupancy(0).expect(2.U) - dut.io.bankOccupancy(1).expect(1.U) - - enqueueFabric(dut, ridValue = 6, expectedBankEnqueues = 0, expectedMask = 0) - dut.io.full.expect(true.B) - dut.io.count.expect(5.U) - } - } - - test("DUT separates input accept metadata from later skid resident bank enqueue") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 2, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 3, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 4, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 5, expectedBankEnqueues = 0, expectedMask = 0) - - issueCycle(dut, issueRid = 1) - dut.io.inValid.poke(false.B) - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, 1) - dut.io.issueReady.poke(false.B) - dut.io.inputAcceptFire.expect(false.B) - dut.io.inputAcceptDstValid.expect(false.B) - dut.io.enqueueFire.expect(false.B) - dut.io.enqueueCount.expect(1.U) - dut.io.bankEnqueueFireMask.expect(1.U) - dut.io.bankEnqueueUop(0).rid.value.expect(5.U) - dut.clock.step() - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = false, 0) - } - } - - test("DUT same-bank current input causes older-only bank enqueue and captures younger") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 2, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 3, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 4, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 5, expectedBankEnqueues = 0, expectedMask = 0) - - issueCycle(dut, issueRid = 1) - enqueueFabricWithReleases( - dut, - ridValue = 6, - expectedBankEnqueues = 1, - expectedMask = 1, - primaryReleaseRid = Some(1)) - dut.io.count.expect(5.U) - dut.io.bankOccupancy(0).expect(2.U) - dut.io.bankOccupancy(1).expect(2.U) - dut.io.full.expect(false.B) - } - } - - test("DUT flush clears skid residents and full ingress backpressure") { - simulate(new ScalarIssueFabric(SimP, depth = 4, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - dut.io.issueReady.poke(false.B) - - enqueueFabric(dut, ridValue = 1, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 2, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 3, expectedBankEnqueues = 1, expectedMask = 1) - enqueueFabric(dut, ridValue = 4, expectedBankEnqueues = 1, expectedMask = 2) - enqueueFabric(dut, ridValue = 5, expectedBankEnqueues = 0, expectedMask = 0) - enqueueFabric(dut, ridValue = 6, expectedBankEnqueues = 0, expectedMask = 0) - dut.io.full.expect(true.B) - dut.io.inReady.expect(false.B) - - dut.io.flushValid.poke(true.B) - dut.io.inReady.expect(false.B) - dut.io.enqueueCount.expect(0.U) - dut.io.bankEnqueueFireMask.expect(0.U) - dut.clock.step() - dut.io.flushValid.poke(false.B) - - dut.io.empty.expect(true.B) - dut.io.count.expect(0.U) - dut.io.full.expect(false.B) - dut.io.inReady.expect(true.B) - } - } - - test("DUT fans primary, secondary, and tertiary release ports into resident banks") { - simulate(new ScalarIssueFabric(SimP, depth = 8, bankCount = 2, stidCount = 1)) { dut => - initFabric(dut) - - for (rid <- 1 to 3) { - dut.io.inValid.poke(true.B) - pokeFabricRow(dut.io.in, ridValue = rid, dstTag = 10 + rid) - dut.io.inReady.expect(true.B) - dut.clock.step() - } - dut.io.inValid.poke(false.B) - dut.io.count.expect(3.U) - - for (rid <- 1 to 3) { - dut.io.issueFire.expect(true.B) - dut.io.issueUop.rid.value.expect(rid.U) - dut.clock.step() - } - dut.io.issuedCount.expect(3.U) - - pokeRelease(dut.io.releaseValid, dut.io.releaseBid, dut.io.releaseRid, dut.io.releaseStid, fire = true, 1) - pokeRelease( - dut.io.secondaryReleaseValid, - dut.io.secondaryReleaseBid, - dut.io.secondaryReleaseRid, - dut.io.secondaryReleaseStid, - fire = true, - 2) - pokeRelease( - dut.io.tertiaryReleaseValid, - dut.io.tertiaryReleaseBid, - dut.io.tertiaryReleaseRid, - dut.io.tertiaryReleaseStid, - fire = true, - 3) - dut.io.releaseFire.expect(true.B) - dut.clock.step() - dut.io.count.expect(0.U) - dut.io.empty.expect(true.B) - } - } - - test("DUT muxes passive head transaction identity from selected head bank") { - val tmp = Files.createTempDirectory("scalar-issue-fabric-head-identity") - val svPath = tmp.resolve("ScalarIssueFabricHeadIdentityProbe.sv") - val tbPath = tmp.resolve("tb.cpp") - val objDir = tmp.resolve("obj") - Files.createDirectories(objDir) - ChiselStage.emitSystemVerilogFile( - new ScalarIssueFabricHeadIdentityProbe, - args = Array("--target-dir", tmp.toString), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - Files.writeString(tbPath, """#include "VScalarIssueFabricHeadIdentityProbe.h" -#include "verilated.h" -#include - -static void tick(VScalarIssueFabricHeadIdentityProbe* top, VerilatedContext* context) { - top->clock = 0; - top->eval(); - context->timeInc(1); - top->clock = 1; - top->eval(); - context->timeInc(1); -} - -int main(int argc, char** argv) { - VerilatedContext context; - context.commandArgs(argc, argv); - VScalarIssueFabricHeadIdentityProbe top{&context}; - top.reset = 1; - for (int i = 0; i < 3; ++i) { - tick(&top, &context); - } - top.reset = 0; - for (int cycle = 0; cycle < 100; ++cycle) { - tick(&top, &context); - if (top.io_failure) { - std::cerr << "fabric head identity probe failed at cycle " << cycle << "\n"; - return 1; - } - if (top.io_done) { - return 0; - } - } - std::cerr << "fabric head identity probe timed out\n"; - return 1; -} -""") - val command = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--top-module", - "ScalarIssueFabricHeadIdentityProbe", - svPath.toString, - tbPath.toString, - "-Mdir", - objDir.toString - ) - val compileExit = Process(command, tmp.toFile).! - assert(compileExit == 0) - val runExit = Process(Seq(objDir.resolve("VScalarIssueFabricHeadIdentityProbe").toString), tmp.toFile).! - assert(runExit == 0) - } - - test("redirecting control waits across BID and RID wrap for an older same-STID resident") { - val tmp = Files.createTempDirectory("scalar-issue-fabric-redirect-age") - val svPath = tmp.resolve("ScalarIssueFabricRedirectAgeProbe.sv") - val tbPath = tmp.resolve("tb.cpp") - val objDir = tmp.resolve("obj") - Files.createDirectories(objDir) - ChiselStage.emitSystemVerilogFile( - new ScalarIssueFabricRedirectAgeProbe, - args = Array("--target-dir", tmp.toString), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - Files.writeString(tbPath, """#include "VScalarIssueFabricRedirectAgeProbe.h" -#include "verilated.h" -#include - -static void tick(VScalarIssueFabricRedirectAgeProbe* top, VerilatedContext* context) { - top->clock = 0; - top->eval(); - context->timeInc(1); - top->clock = 1; - top->eval(); - context->timeInc(1); -} - -int main(int argc, char** argv) { - VerilatedContext context; - context.commandArgs(argc, argv); - VScalarIssueFabricRedirectAgeProbe top{&context}; - top.reset = 1; - for (int i = 0; i < 3; ++i) { - tick(&top, &context); - } - top.reset = 0; - for (int cycle = 0; cycle < 100; ++cycle) { - tick(&top, &context); - if (top.io_failure) { - std::cerr << "redirect age probe failed at cycle " << cycle << "\n"; - return 1; - } - if (top.io_done) { - if (!top.io_observedRedirectBlocked) { - std::cerr << "redirect was ordered but never observed blocked\n"; - return 1; - } - return 0; - } - } - std::cerr << "redirect age probe timed out\n"; - return 1; -} -""") - val command = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--top-module", - "ScalarIssueFabricRedirectAgeProbe", - svPath.toString, - tbPath.toString, - "-Mdir", - objDir.toString - ) - val compileExit = Process(command, tmp.toFile).! - assert(compileExit == 0) - val runExit = Process(Seq(objDir.resolve("VScalarIssueFabricRedirectAgeProbe").toString), tmp.toFile).! - assert(runExit == 0) - } - - test("redirecting control does not wait for an older resident from another STID") { - val tmp = Files.createTempDirectory("scalar-issue-fabric-redirect-different-stid") - val svPath = tmp.resolve("ScalarIssueFabricDifferentStidProbe.sv") - val tbPath = tmp.resolve("tb.cpp") - val objDir = tmp.resolve("obj") - Files.createDirectories(objDir) - ChiselStage.emitSystemVerilogFile( - new ScalarIssueFabricDifferentStidProbe, - args = Array("--target-dir", tmp.toString), - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) - Files.writeString(tbPath, """#include "VScalarIssueFabricDifferentStidProbe.h" -#include "verilated.h" -#include - -static void tick(VScalarIssueFabricDifferentStidProbe* top, VerilatedContext* context) { - top->clock = 0; - top->eval(); - context->timeInc(1); - top->clock = 1; - top->eval(); - context->timeInc(1); -} - -int main(int argc, char** argv) { - VerilatedContext context; - context.commandArgs(argc, argv); - VScalarIssueFabricDifferentStidProbe top{&context}; - top.reset = 1; - for (int i = 0; i < 3; ++i) { - tick(&top, &context); - } - top.reset = 0; - for (int cycle = 0; cycle < 100; ++cycle) { - tick(&top, &context); - if (top.io_failure) { - std::cerr << "different-STID redirect probe failed at cycle " << cycle << "\n"; - return 1; - } - if (top.io_done) { - return 0; - } - } - std::cerr << "different-STID redirect probe timed out\n"; - return 1; -} -""") - val command = Seq( - "verilator", - "--cc", - "--exe", - "--build", - "--top-module", - "ScalarIssueFabricDifferentStidProbe", - svPath.toString, - tbPath.toString, - "-Mdir", - objDir.toString - ) - val compileExit = Process(command, tmp.toFile).! - assert(compileExit == 0) - val runExit = Process(Seq(objDir.resolve("VScalarIssueFabricDifferentStidProbe").toString), tmp.toFile).! - assert(runExit == 0) - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ScalarIssueIngressSkid2Spec.scala b/chisel/src/test/scala/linxcore/execute/ScalarIssueIngressSkid2Spec.scala deleted file mode 100644 index 301f8278..00000000 --- a/chisel/src/test/scala/linxcore/execute/ScalarIssueIngressSkid2Spec.scala +++ /dev/null @@ -1,464 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, DispatchTarget, InterfaceParams, OperandClass, RenamedUop} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rob.ROBID -import org.scalatest.funsuite.AnyFunSuite - -class ScalarIssueIngressSkid2Spec extends AnyFunSuite with ChiselSim { - private val P = InterfaceParams(robEntries = 16) - - private def pokeRobId(id: ROBID, valid: Boolean, wrap: Boolean, value: Int): Unit = { - id.valid.poke(valid.B) - id.wrap.poke(wrap.B) - id.value.poke(value.U) - } - - private def pokeRow( - row: RenamedUop, - pc: Long, - ridValue: Int, - bankHint: Int, - opcode: Int = FrontendOpcodeDecodeTable.OP_ADDI, - dispatch: DispatchTarget.Type = DispatchTarget.Alu, - isStore: Boolean = false, - isLoad: Boolean = false, - pairFirst: Boolean = false, - bidWrap: Boolean = false, - ridWrap: Boolean = false, - lsid: Long = 0x100L): Unit = { - row.poke(0.U.asTypeOf(row)) - row.valid.poke(true.B) - row.peId.poke(2.U) - row.threadId.poke(0.U) - row.pc.poke(pc.U) - row.opcode.poke(opcode.U(P.opcodeWidth.W)) - row.dispatchTarget.poke(dispatch) - for (idx <- 0 until 3) { - row.src(idx).valid.poke((idx != 2).B) - row.src(idx).operandClass.poke(OperandClass.P) - row.src(idx).archTag.poke((8 + idx).U) - row.src(idx).relTag.poke((8 + idx).U) - row.src(idx).physTag.poke((12 + ridValue + idx).U) - } - row.dst(0).valid.poke(true.B) - row.dst(0).kind.poke(DestinationKind.Gpr) - row.dst(0).archTag.poke(5.U) - row.dst(0).relTag.poke(5.U) - row.dst(0).physTag.poke((32 + ridValue).U) - row.pairFirstDst.valid.poke(pairFirst.B) - row.pairFirstDst.kind.poke(DestinationKind.Gpr) - row.pairFirstDst.archTag.poke(6.U) - row.pairFirstDst.relTag.poke(6.U) - row.pairFirstDst.physTag.poke((40 + ridValue).U) - row.imm.poke((0x5550L + ridValue).U) - row.immValid.poke(true.B) - pokeRobId(row.bid, valid = true, wrap = bidWrap, value = 2 + bankHint) - pokeRobId(row.gid, valid = true, wrap = true, value = 7 + bankHint) - pokeRobId(row.rid, valid = true, wrap = ridWrap, value = ridValue) - row.lsid.poke(lsid.U) - row.isLoad.poke(isLoad.B) - row.isStore.poke(isStore.B) - row.blockBidValid.poke(true.B) - row.blockBid.poke((0x80 + bankHint).U) - row.uid.uid.poke((0x20 + ridValue).U) - row.uid.parentUid.poke((0x120 + ridValue).U) - row.uid.fetchSlot.poke(bankHint.U) - } - - private def init(dut: ScalarIssueIngressSkid2): Unit = { - dut.io.inValid.poke(false.B) - pokeRow(dut.io.in, pc = 0x1000L, ridValue = 1, bankHint = 0) - dut.io.inBank.poke(0.U) - dut.io.flushValid.poke(false.B) - dut.io.drainCanConsume(0).poke(false.B) - dut.io.drainCanConsume(1).poke(false.B) - } - - private def enqueue( - dut: ScalarIssueIngressSkid2, - pc: Long, - ridValue: Int, - bank: Int, - opcode: Int = FrontendOpcodeDecodeTable.OP_ADDI, - dispatch: DispatchTarget.Type = DispatchTarget.Alu, - isStore: Boolean = false, - isLoad: Boolean = false, - pairFirst: Boolean = false, - bidWrap: Boolean = false, - ridWrap: Boolean = false, - lsid: Long = 0x100L): Unit = { - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(bank.U) - pokeRow( - dut.io.in, - pc = pc, - ridValue = ridValue, - bankHint = bank, - opcode = opcode, - dispatch = dispatch, - isStore = isStore, - isLoad = isLoad, - pairFirst = pairFirst, - bidWrap = bidWrap, - ridWrap = ridWrap, - lsid = lsid) - dut.io.inReady.expect(true.B) - dut.clock.step() - dut.io.inValid.poke(false.B) - } - - test("empty skid can flow input directly to consume credit without capture") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(1.U) - pokeRow(dut.io.in, pc = 0x0800L, ridValue = 1, bankHint = 1) - dut.io.drainCanConsume(1).poke(true.B) - - dut.io.empty.expect(true.B) - dut.io.inReady.expect(true.B) - dut.io.drainPresent(0).expect(false.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x0800L.U) - dut.io.drainPreview(1).rid.value.expect(1.U) - dut.io.drainFire(1).expect(true.B) - dut.io.olderOnlyFire.expect(true.B) - dut.clock.step() - - dut.io.inValid.poke(false.B) - dut.io.empty.expect(true.B) - dut.io.drainPresent(1).expect(false.B) - } - } - - test("empty skid captures current input when consume credit is absent") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(0.U) - pokeRow(dut.io.in, pc = 0x0840L, ridValue = 2, bankHint = 0) - dut.io.drainCanConsume(0).poke(false.B) - - dut.io.inReady.expect(true.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x0840L.U) - dut.io.drainFire(0).expect(false.B) - dut.clock.step() - - dut.io.count.expect(1.U) - dut.io.inValid.poke(false.B) - pokeRow(dut.io.in, pc = 0x0880L, ridValue = 3, bankHint = 1) - dut.io.inBank.poke(1.U) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x0840L.U) - dut.io.drainPreview(0).rid.value.expect(2.U) - } - } - - test("one resident and current input can dual fire in order") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x08c0L, ridValue = 3, bank = 0) - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(1.U) - pokeRow(dut.io.in, pc = 0x08c4L, ridValue = 4, bankHint = 1) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(true.B) - - dut.io.count.expect(1.U) - dut.io.inReady.expect(true.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(true.B) - dut.io.drainFire(0).expect(true.B) - dut.io.drainFire(1).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x08c0L.U) - dut.io.drainPreview(1).pc.expect(0x08c4L.U) - dut.clock.step() - - dut.io.empty.expect(true.B) - } - } - - test("one resident older-only fire captures current input as next older") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x0900L, ridValue = 5, bank = 0) - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(1.U) - pokeRow(dut.io.in, pc = 0x0904L, ridValue = 6, bankHint = 1) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(false.B) - - dut.io.inReady.expect(true.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(false.B) - dut.io.olderOnlyFire.expect(true.B) - dut.io.drainFire(0).expect(true.B) - dut.io.drainFire(1).expect(false.B) - dut.io.drainPreview(0).pc.expect(0x0900L.U) - dut.io.drainPreview(1).pc.expect(0x0904L.U) - dut.clock.step() - - dut.io.inValid.poke(false.B) - dut.io.count.expect(1.U) - dut.io.drainPresent(0).expect(false.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x0904L.U) - dut.io.drainPreview(1).rid.value.expect(6.U) - } - } - - test("one resident younger-only credit captures current input without reordering") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x0940L, ridValue = 7, bank = 0) - dut.io.inValid.poke(true.B) - dut.io.inBank.poke(1.U) - pokeRow(dut.io.in, pc = 0x0944L, ridValue = 8, bankHint = 1) - dut.io.drainCanConsume(0).poke(false.B) - dut.io.drainCanConsume(1).poke(true.B) - - dut.io.inReady.expect(true.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(false.B) - dut.io.olderOnlyFire.expect(false.B) - dut.io.drainFire(0).expect(false.B) - dut.io.drainFire(1).expect(false.B) - dut.io.drainPreview(0).pc.expect(0x0940L.U) - dut.io.drainPreview(1).pc.expect(0x0944L.U) - dut.clock.step() - - dut.io.inValid.poke(false.B) - dut.io.count.expect(2.U) - dut.io.full.expect(true.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x0940L.U) - dut.io.drainPreview(0).rid.value.expect(7.U) - dut.io.drainPreview(1).pc.expect(0x0944L.U) - dut.io.drainPreview(1).rid.value.expect(8.U) - } - } - - test("drains two fixed scalar ALU rows to different banks in one cycle") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x1000L, ridValue = 1, bank = 0) - enqueue(dut, pc = 0x1004L, ridValue = 2, bank = 1) - dut.io.count.expect(2.U) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(true.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x1000L.U) - dut.io.drainPreview(1).pc.expect(0x1004L.U) - dut.clock.step() - dut.io.empty.expect(true.B) - } - } - - test("same-bank candidates drain only the older row") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x2000L, ridValue = 3, bank = 0) - enqueue(dut, pc = 0x2004L, ridValue = 4, bank = 0) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.dualDrainEligible.expect(false.B) - dut.io.olderOnlyFire.expect(true.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(false.B) - dut.io.drainPreview(0).pc.expect(0x2000L.U) - dut.clock.step() - dut.io.count.expect(1.U) - dut.io.drainPreview(0).pc.expect(0x2004L.U) - } - } - - test("unsafe younger row keeps the pair on older-only drain") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x3000L, ridValue = 5, bank = 0) - enqueue( - dut, - pc = 0x3004L, - ridValue = 6, - bank = 1, - opcode = FrontendOpcodeDecodeTable.OP_SDI, - dispatch = DispatchTarget.Alu, - isStore = true) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.dualDrainEligible.expect(false.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(false.B) - dut.io.drainPreview(0).pc.expect(0x3000L.U) - dut.clock.step() - dut.io.count.expect(1.U) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x3004L.U) - } - } - - test("backpressure holds registered payload stable") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x4000L, ridValue = 7, bank = 1) - dut.io.drainCanConsume(0).poke(false.B) - dut.io.drainCanConsume(1).poke(false.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x4000L.U) - dut.io.drainPreview(1).rid.value.expect(7.U) - dut.clock.step(3) - dut.io.count.expect(1.U) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x4000L.U) - dut.io.drainPreview(1).rid.value.expect(7.U) - } - } - - test("dual presentation does not depend on younger consume credit and compacts in order") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x4800L, ridValue = 13, bank = 0) - enqueue(dut, pc = 0x4804L, ridValue = 14, bank = 1) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(false.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(false.B) - dut.io.olderOnlyFire.expect(true.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x4800L.U) - dut.io.drainPreview(1).pc.expect(0x4804L.U) - dut.io.drainPreview(1).rid.value.expect(14.U) - dut.clock.step() - - dut.io.count.expect(1.U) - dut.io.drainCanConsume(0).poke(false.B) - dut.io.drainCanConsume(1).poke(false.B) - dut.io.drainPresent(0).expect(false.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x4804L.U) - dut.io.drainPreview(1).rid.value.expect(14.U) - dut.clock.step(2) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x4804L.U) - dut.io.drainPreview(1).rid.value.expect(14.U) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.olderOnlyFire.expect(true.B) - dut.clock.step() - dut.io.empty.expect(true.B) - } - } - - test("younger-only consume credit does not fire or dequeue a dual-eligible pair") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x4c00L, ridValue = 6, bank = 0) - enqueue(dut, pc = 0x4c04L, ridValue = 7, bank = 1) - dut.io.drainCanConsume(0).poke(false.B) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.dualDrainEligible.expect(true.B) - dut.io.dualDrainFire.expect(false.B) - dut.io.olderOnlyFire.expect(false.B) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainFire(0).expect(false.B) - dut.io.drainFire(1).expect(false.B) - dut.io.drainPreview(0).pc.expect(0x4c00L.U) - dut.io.drainPreview(1).pc.expect(0x4c04L.U) - dut.clock.step() - - dut.io.count.expect(2.U) - dut.io.drainPresent(0).expect(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(0).pc.expect(0x4c00L.U) - dut.io.drainPreview(1).pc.expect(0x4c04L.U) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(false.B) - dut.io.drainFire(0).expect(true.B) - dut.io.drainFire(1).expect(false.B) - dut.clock.step() - dut.io.count.expect(1.U) - dut.io.drainPresent(0).expect(false.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).pc.expect(0x4c04L.U) - } - } - - test("flush clears both resident rows and suppresses drain") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x5000L, ridValue = 8, bank = 0) - enqueue(dut, pc = 0x5004L, ridValue = 9, bank = 1) - dut.io.flushValid.poke(true.B) - dut.io.inReady.expect(false.B) - dut.io.drainPresent(0).expect(false.B) - dut.io.drainPresent(1).expect(false.B) - dut.clock.step() - dut.io.flushValid.poke(false.B) - dut.io.empty.expect(true.B) - dut.io.inReady.expect(true.B) - } - } - - test("wrap and full RenamedUop identity sidecars are preserved") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue( - dut, - pc = 0x6000L, - ridValue = 10, - bank = 1, - bidWrap = true, - ridWrap = true, - lsid = 0x12345678L) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.drainPresent(1).expect(true.B) - dut.io.drainPreview(1).peId.expect(2.U) - dut.io.drainPreview(1).pc.expect(0x6000L.U) - dut.io.drainPreview(1).bid.valid.expect(true.B) - dut.io.drainPreview(1).bid.wrap.expect(true.B) - dut.io.drainPreview(1).bid.value.expect(3.U) - dut.io.drainPreview(1).gid.valid.expect(true.B) - dut.io.drainPreview(1).gid.wrap.expect(true.B) - dut.io.drainPreview(1).gid.value.expect(8.U) - dut.io.drainPreview(1).rid.valid.expect(true.B) - dut.io.drainPreview(1).rid.wrap.expect(true.B) - dut.io.drainPreview(1).rid.value.expect(10.U) - dut.io.drainPreview(1).lsid.expect(0x12345678L.U) - dut.io.drainPreview(1).src(0).physTag.expect(22.U) - dut.io.drainPreview(1).dst(0).physTag.expect(42.U) - dut.io.drainPreview(1).blockBidValid.expect(true.B) - dut.io.drainPreview(1).blockBid.expect(0x81.U) - dut.io.drainPreview(1).uid.uid.expect(0x2a.U) - dut.io.drainPreview(1).uid.parentUid.expect(0x12a.U) - dut.io.drainPreview(1).uid.fetchSlot.expect(1.U) - } - } - - test("full plus dequeue keeps upstream backpressured until the next cycle") { - simulate(new ScalarIssueIngressSkid2(P)) { dut => - init(dut) - enqueue(dut, pc = 0x7000L, ridValue = 11, bank = 0) - enqueue(dut, pc = 0x7004L, ridValue = 12, bank = 1) - pokeRow(dut.io.in, pc = 0x7008L, ridValue = 13, bankHint = 0) - dut.io.inBank.poke(0.U) - dut.io.inValid.poke(true.B) - dut.io.full.expect(true.B) - dut.io.inReady.expect(false.B) - dut.io.drainCanConsume(0).poke(true.B) - dut.io.drainCanConsume(1).poke(true.B) - dut.io.dualDrainFire.expect(true.B) - dut.clock.step() - dut.io.inReady.expect(true.B) - dut.io.count.expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/execute/ScalarSpOrderOwnerSpec.scala b/chisel/src/test/scala/linxcore/execute/ScalarSpOrderOwnerSpec.scala deleted file mode 100644 index 7674a7c1..00000000 --- a/chisel/src/test/scala/linxcore/execute/ScalarSpOrderOwnerSpec.scala +++ /dev/null @@ -1,90 +0,0 @@ -package linxcore.execute - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.commit.CommitTraceParams -import linxcore.common.InterfaceParams -import org.scalatest.funsuite.AnyFunSuite - -class ScalarSpOrderOwnerSpec extends AnyFunSuite with ChiselSim { - private val p = InterfaceParams() - private val trace = CommitTraceParams( - commitWidth = p.commitWidth, - robValueWidth = p.robIndexWidth, - blockBidWidth = p.blockBidWidth, - pcWidth = p.pcWidth, - insnWidth = p.insnWidth, - lenWidth = p.lenWidth) - - private def clearInputs(dut: ScalarSpOrderOwner): Unit = { - dut.io.flushValid.poke(false.B) - dut.io.initValid.poke(false.B) - dut.io.initData.poke(0.U) - dut.io.recoveryRestoreValid.poke(false.B) - dut.io.recoveryRestoreStid.poke(0.U) - dut.io.recoveryRestoreData.poke(0.U) - dut.io.reserveValid.poke(false.B) - dut.io.reserve.poke(0.U.asTypeOf(dut.io.reserve)) - dut.io.terminalValid.poke(false.B) - dut.io.terminal.poke(0.U.asTypeOf(dut.io.terminal)) - dut.io.terminalProducedValid.poke(false.B) - dut.io.terminalProducedData.poke(0.U) - dut.io.commit.poke(0.U.asTypeOf(dut.io.commit)) - dut.io.commitValidMask.poke(0.U) - } - - test("redirect recovery preserves the returning FRET stack-pointer value") { - simulate(new ScalarSpOrderOwner(p, trace, depth = 4, stidCount = 1)) { dut => - clearInputs(dut) - dut.io.initValid.poke(true.B) - dut.io.initData.poke(0x1000.U) - dut.clock.step() - clearInputs(dut) - dut.io.currentSp.expect(0x1000.U) - - dut.io.reserveValid.poke(true.B) - dut.io.reserve.access.valid.poke(true.B) - dut.io.reserve.access.read.poke(true.B) - dut.io.reserve.access.write.poke(true.B) - dut.io.reserve.stid.poke(0.U) - dut.io.reserve.bid.valid.poke(true.B) - dut.io.reserve.bid.wrap.poke(false.B) - dut.io.reserve.bid.value.poke(2.U) - dut.io.reserve.rid.valid.poke(true.B) - dut.io.reserve.rid.wrap.poke(false.B) - dut.io.reserve.rid.value.poke(3.U) - dut.io.reserve.epoch.poke(0.U) - dut.clock.step() - clearInputs(dut) - dut.io.issueHeadValid.expect(true.B) - - dut.io.terminalValid.poke(true.B) - dut.io.terminal.access.valid.poke(true.B) - dut.io.terminal.access.read.poke(true.B) - dut.io.terminal.access.write.poke(true.B) - dut.io.terminal.stid.poke(0.U) - dut.io.terminal.bid.valid.poke(true.B) - dut.io.terminal.bid.wrap.poke(false.B) - dut.io.terminal.bid.value.poke(2.U) - dut.io.terminal.rid.valid.poke(true.B) - dut.io.terminal.rid.wrap.poke(false.B) - dut.io.terminal.rid.value.poke(3.U) - dut.io.terminal.epoch.poke(0.U) - dut.io.terminalProducedValid.poke(true.B) - dut.io.terminalProducedData.poke(0x1080.U) - dut.clock.step() - clearInputs(dut) - - dut.io.flushValid.poke(true.B) - dut.io.recoveryRestoreValid.poke(true.B) - dut.io.recoveryRestoreStid.poke(0.U) - dut.io.recoveryRestoreData.poke(0x1080.U) - dut.clock.step() - clearInputs(dut) - - dut.io.currentSp.expect(0x1080.U) - dut.io.issueHeadValid.expect(false.B) - dut.io.protocolError.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/frontend/FrontendDecodeStageSpec.scala b/chisel/src/test/scala/linxcore/frontend/FrontendDecodeStageSpec.scala index da97b026..81216c46 100644 --- a/chisel/src/test/scala/linxcore/frontend/FrontendDecodeStageSpec.scala +++ b/chisel/src/test/scala/linxcore/frontend/FrontendDecodeStageSpec.scala @@ -216,6 +216,9 @@ object FrontendDecodeStageReference { case FrontendOpcodeDecodeTable.ImmSIMM12_7_S5_25_7 => imm = Some(sext((bitRange(word, 11, 7) << 7) | bitRange(word, 31, 25), 12)) case FrontendOpcodeDecodeTable.ImmSIMM17 => imm = Some((sext(bitRange(word, 31, 15), 17) << 1) & Mask64) + case FrontendOpcodeDecodeTable.ImmSIMM22 => + val raw = (bitRange(word, 11, 7) << 17) | bitRange(word, 31, 15) + imm = Some((sext(raw, 22) << 1) & Mask64) case FrontendOpcodeDecodeTable.ImmSIMM25 => val raw = sext(bitRange(word, 31, 7), 25) if (opcodeIs(rule, diff --git a/chisel/src/test/scala/linxcore/frontend/FrontendOperandDecodeSpec.scala b/chisel/src/test/scala/linxcore/frontend/FrontendOperandDecodeSpec.scala new file mode 100644 index 00000000..cf288662 --- /dev/null +++ b/chisel/src/test/scala/linxcore/frontend/FrontendOperandDecodeSpec.scala @@ -0,0 +1,49 @@ +package linxcore.frontend + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +class FrontendOperandDecodeSpec extends AnyFunSuite with ChiselSim { + test("compact memory decode preserves its signed encoded offset") { + simulate(new FrontendOperandDecode()) { dut => + dut.io.active.poke(true.B) + dut.io.meta.poke(0.U.asTypeOf(dut.io.meta)) + dut.io.meta.lenBytes.poke(2.U) + dut.io.meta.immKind.poke(FrontendOpcodeDecodeTable.ImmSIMM5_11_S5.U) + + for (opcode <- Seq( + FrontendOpcodeDecodeTable.OP_C_LWI, + FrontendOpcodeDecodeTable.OP_C_LDI, + FrontendOpcodeDecodeTable.OP_C_SWI, + FrontendOpcodeDecodeTable.OP_C_SDI)) { + dut.io.meta.opcode.poke(opcode.U) + dut.io.insn.poke((BigInt(0x1e) << 11).U) + dut.io.immValid.expect(true.B) + dut.io.imm.expect(BigInt("fffffffffffffffe", 16).U) + } + } + } + + test("J decodes its signed halfword displacement as a byte offset") { + simulate(new FrontendOperandDecode()) { dut => + dut.io.active.poke(true.B) + dut.io.meta.poke(0.U.asTypeOf(dut.io.meta)) + dut.io.meta.opcode.poke(FrontendOpcodeDecodeTable.OP_J.U) + dut.io.meta.lenBytes.poke(4.U) + dut.io.meta.immKind.poke(FrontendOpcodeDecodeTable.ImmSIMM22.U) + + // simm22 = 2 is split as [11:7] @ [31:15]. J scales it by two. + dut.io.insn.poke((BigInt(2) << 15).U) + dut.io.immValid.expect(true.B) + dut.io.imm.expect(4.U) + + // Preserve sign before applying the byte scaling. + val negativeOne = ((BigInt(1) << 17) - 1) << 15 | + ((BigInt(1) << 5) - 1) << 7 + dut.io.insn.poke(negativeOne.U) + dut.io.immValid.expect(true.B) + dut.io.imm.expect(BigInt("fffffffffffffffe", 16).U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/frontend/OooIfuBranchFeedbackBridgeSpec.scala b/chisel/src/test/scala/linxcore/frontend/OooIfuBranchFeedbackBridgeSpec.scala new file mode 100644 index 00000000..3a5d27bc --- /dev/null +++ b/chisel/src/test/scala/linxcore/frontend/OooIfuBranchFeedbackBridgeSpec.scala @@ -0,0 +1,102 @@ +package linxcore.frontend + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.common.BoundaryKind +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface.{BranchValidationKind, RecoveryCause} +import org.scalatest.funsuite.AnyFunSuite + +class OooIfuBranchFeedbackBridgeSpec extends AnyFunSuite with ChiselSim { + private val p = SimulationParamProfiles.W2 + + private def clear(dut: OooIfuBranchFeedbackBridge): Unit = { + dut.io.validation.valid.poke(false.B) + dut.io.validation.bits.poke(0.U.asTypeOf(dut.io.validation.bits)) + dut.io.resolve.ready.poke(true.B) + dut.io.recovery.ready.poke(true.B) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + } + + private def pokeConditional( + dut: OooIfuBranchFeedbackBridge, + predictedTaken: Boolean, + actualTaken: Boolean): Unit = { + val event = dut.io.validation.bits + event.poke(0.U.asTypeOf(event)) + event.rob.peId.poke(3.U) + event.rob.stid.poke(0.U) + event.rob.ridSlot.poke(7.U) + event.rob.ridGeneration.poke(2.U) + event.rob.memberIndex.poke(1.U) + event.rob.residentGeneration.poke(4.U) + event.rob.bid.poke(9.U) + event.rob.brobGeneration.poke(5.U) + event.instruction.peId.poke(3.U) + event.instruction.stid.poke(0.U) + event.instruction.instructionId.poke(91.U) + event.instruction.epoch.poke(11.U) + event.kind.poke(BranchValidationKind.Condition) + event.predictionValid.poke(true.B) + event.predictionTag.poke(55.U) + event.predictionTransactionId.poke(56.U) + event.fetchPacketUid.poke(57.U) + event.fetchSeq.poke(58.U) + event.predictionEpoch.poke(11.U) + event.checkpointId.poke(1.U) + event.requestPc.poke(0x1000.U) + event.predictedTaken.poke(predictedTaken.B) + event.predictedBranchPc.poke(0x1010.U) + event.predictedTarget.poke(0x1080.U) + event.predictedFallthroughPc.poke(0x1020.U) + event.predictedKind.poke(BoundaryKind.Cond) + event.actualTaken.poke(actualTaken.B) + event.actualBranchPc.poke(0x1010.U) + event.actualTarget.poke(0x1080.U) + event.actualFallthroughPc.poke(0x1020.U) + event.actualKind.poke(BoundaryKind.Cond) + dut.io.validation.valid.poke(true.B) + } + + test("publishes conditional training without recovery when prediction matches") { + simulate(new OooIfuBranchFeedbackBridge(p)) { dut => + clear(dut) + pokeConditional(dut, predictedTaken = false, actualTaken = false) + dut.io.validation.ready.expect(true.B) + dut.clock.step() + dut.io.validation.valid.poke(false.B) + + dut.io.resolve.valid.expect(true.B) + dut.io.resolve.bits.mispredict.expect(false.B) + dut.io.resolve.bits.taken.expect(false.B) + dut.io.recovery.valid.expect(false.B) + dut.clock.step() + } + } + + test("publishes exact ROB recovery atomically with mismatching training") { + simulate(new OooIfuBranchFeedbackBridge(p)) { dut => + clear(dut) + dut.io.resolve.ready.poke(false.B) + pokeConditional(dut, predictedTaken = false, actualTaken = true) + dut.clock.step() + dut.io.validation.valid.poke(false.B) + + dut.io.resolve.valid.expect(true.B) + dut.io.resolve.bits.mispredict.expect(true.B) + dut.io.recovery.valid.expect(false.B) + dut.io.resolve.ready.poke(true.B) + dut.io.recovery.ready.poke(true.B) + dut.io.resolve.valid.expect(true.B) + dut.io.resolve.bits.mispredict.expect(true.B) + dut.io.recovery.valid.expect(true.B) + dut.io.recovery.bits.cause.expect(RecoveryCause.Branch) + dut.io.recovery.bits.trigger.ridSlot.expect(7.U) + dut.io.recovery.bits.trigger.memberIndex.expect(1.U) + dut.io.recovery.bits.redirectPc.expect(0x1080.U) + dut.clock.step() + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/DTUActivationTraceSpec.scala b/chisel/src/test/scala/linxcore/iex/DTUActivationTraceSpec.scala new file mode 100644 index 00000000..63e3e89f --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/DTUActivationTraceSpec.scala @@ -0,0 +1,125 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.ooo.OooOpcodeRecipeTable +import linxcore.top.interface.FrontEndOpKind +import org.scalatest.funsuite.AnyFunSuite + +class DTUActivationTraceSpec extends AnyFunSuite with ChiselSim { + private val compact = { + val base = OOOIEXLSUActivationParams.W4 + base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 4, + brobEntriesPerStid = 4)) + } + + private def initialize(dut: OOOIEXLSUActivationProbe): Unit = { + dut.io.program.valid.poke(false.B) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.commitReady.poke(true.B) + dut.io.trapReady.poke(true.B) + dut.io.cmdReady.poke(true.B) + dut.io.systemReady.poke(true.B) + dut.io.oooTraceReady.poke(true.B) + dut.io.iexTraceReady.poke(false.B) + dut.io.recoveryReady.poke(true.B) + dut.io.lsuTraceReady.poke(true.B) + dut.io.memoryReady.foreach(_.poke(true.B)) + dut.io.memoryResponseValid.poke(false.B) + dut.io.memoryResponseId.poke(0.U) + dut.io.memoryResponseGeneration.poke(0.U) + dut.io.memoryResponseAddress.poke(0.U) + dut.io.memoryResponseData.poke(0.U) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.loadResultInject.valid.poke(false.B) + dut.io.loadResultInject.bits.poke( + 0.U.asTypeOf(dut.io.loadResultInject.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + while (!dut.io.bootstrapComplete.peek().litToBoolean) dut.clock.step() + } + + private def sendClosedPair(dut: OOOIEXLSUActivationProbe): Unit = { + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x1000), + (addi, addi.value | (BigInt(5) << 7) | (BigInt(7) << 20), 0x1004), + (addi, addi.value | (BigInt(6) << 7) | (BigInt(9) << 20), 0x1008), + (stop, stop.value, 0x100c)) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(encodings.size.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((lane + 1).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + } + + test("stalled external trace export cannot suppress terminal or commit progress") { + simulate(new OOOIEXLSUActivationProbe(compact)) { dut => + initialize(dut) + sendClosedPair(dut) + + var firstCycles = 0 + while ((!dut.io.dtuTraceValid.peek().litToBoolean || + dut.io.dtuTraceAcceptedCount.peek().litValue < 1 || + dut.io.rfWriteCount.peek().litValue < 1) && firstCycles < 64) { + dut.clock.step() + firstCycles += 1 + } + dut.io.dtuTraceValid.expect(true.B) + dut.io.dtuTraceAcceptedCount.expect(1.U) + dut.io.rfWriteCount.expect(1.U) + val retained = dut.io.dtuTrace.peek() + dut.clock.step(3) + dut.io.dtuTraceValid.expect(true.B) + dut.io.dtuTrace.expect(retained) + + var cycles = 0 + while ((dut.io.rfWriteCount.peek().litValue < 2 || + dut.io.resolveCount.peek().litValue < 2 || + dut.io.commitCount.peek().litValue < 1 || + dut.io.dtuTraceAcceptedCount.peek().litValue < 2 || + dut.io.dtuTraceDroppedCount.peek().litValue < 1) && cycles < 96) { + dut.clock.step() + cycles += 1 + } + + val finalCounts = + s"rf=${dut.io.rfWriteCount.peek().litValue} " + + s"resolve=${dut.io.resolveCount.peek().litValue} " + + s"commit=${dut.io.commitCount.peek().litValue} " + + s"accepted=${dut.io.dtuTraceAcceptedCount.peek().litValue} " + + s"dropped=${dut.io.dtuTraceDroppedCount.peek().litValue}" + info(finalCounts) + assert(dut.io.rfWriteCount.peek().litValue == 2, finalCounts) + assert(dut.io.resolveCount.peek().litValue == 2, finalCounts) + assert(dut.io.commitCount.peek().litValue == 1, finalCounts) + assert(dut.io.dtuTraceAcceptedCount.peek().litValue == 2, finalCounts) + assert(dut.io.dtuTraceDroppedCount.peek().litValue == 1, finalCounts) + dut.io.dtuTraceValid.expect(true.B) + dut.io.dtuTrace.expect(retained) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXIssueSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXIssueSpec.scala new file mode 100644 index 00000000..ebf7bfe4 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXIssueSpec.scala @@ -0,0 +1,38 @@ +package linxcore.iex + +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class IEXIssueSpec extends AnyFunSuite { + private def publicModule(chirrtl: String, name: String): String = { + val marker = s"module $name :" + val start = chirrtl.indexOf(marker) + assert(start >= 0, s"missing public module $name") + val next = chirrtl.indexOf("\n module ", start + marker.length) + if (next < 0) chirrtl.substring(start) else chirrtl.substring(start, next) + } + + test("public IEX owns the canonical classed dispatch boundary at every width") { + Seq(2, 4, 6, 8).foreach { width => + val p = SimulationParamProfiles.forWidth(width) + val chirrtl = ChiselStage.emitCHIRRTL(new IEX(p)) + assert(chirrtl.contains("circuit IEX")) + assert(chirrtl.contains("module OooIexIssue")) + assert(chirrtl.contains("module OooIexOperandFiles")) + assert(!chirrtl.contains("module ReducedScalarIssueQueue")) + } + } + + test("public IEX shell contains no retained state or arbitration") { + val chirrtl = ChiselStage.emitCHIRRTL(new IEX(SimulationParamProfiles.W4)) + val shell = publicModule(chirrtl, "IEX") + + assert(!shell.contains(" reg "), shell) + assert(!shell.contains(" of Queue"), shell) + assert(!shell.contains(" of RRArbiter"), shell) + assert(!shell.contains("bootstrapSeen"), shell) + assert(!shell.contains("resolveTransport"), shell) + assert(!shell.contains("traceTransport"), shell) + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala new file mode 100644 index 00000000..fc31c110 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala @@ -0,0 +1,477 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util.{Decoupled, Valid} +import linxcore.ooo._ +import linxcore.params.{CoreParams, ParamProfiles, SimulationParamProfiles} +import linxcore.top.interface.{D3RenameGroup, DispatchTxn, + PcBufferD3Prepared, UopClass} +import org.scalatest.funsuite.AnyFunSuite + +private class IEXPcReadHarnessIO(val core: CoreParams, val p: OooParams) + extends Bundle { + val prepare = Flipped(Valid(new D3RenameGroup(core))) + val prepareReady = Output(Bool()) + val prepared = Output(new PcBufferD3Prepared(core)) + val publishFire = Input(Bool()) + val p1 = Flipped(Decoupled(new OooIexP1Request(p))) + val i2 = Decoupled(new OooIexI2Transaction(p)) +} + +/** Real canonical PC owner, readyless read arbiter, and retained I2 lane. */ +private class IEXPcReadHarness(val core: CoreParams) extends Module { + val p = OooIexPhysicalProfile.fromCoreParams(core).params + val io = IO(new IEXPcReadHarnessIO(core, p)) + val pc = Module(new OooPcBuffer(core)) + val reads = Module(new OooIexAtomicReadArbiter(core, p)) + val lane = Module(new OooIexP1I2Lane(core, p)) + + pc.io.prepare := io.prepare + pc.io.selectedLimit := pc.io.prefixOffer + io.prepareReady := pc.io.prepareReady + io.prepared := pc.io.prepared + pc.io.publicationIdentity.valid := io.publishFire + pc.io.publicationIdentity.bits := + 0.U.asTypeOf(pc.io.publicationIdentity.bits) + pc.io.publicationIdentity.bits.count := pc.io.prepared.count + for (laneIndex <- 0 until core.ooo.d3PrefixWidth) { + pc.io.publicationIdentity.bits.entries(laneIndex).valid := + laneIndex.U < pc.io.prepared.count + pc.io.publicationIdentity.bits.entries(laneIndex).rob := + io.prepare.bits.entries(laneIndex).uop.decoded.rob + } + pc.io.publishFire := io.publishFire + pc.io.commitPreview.valid := false.B + pc.io.commitPreview.bits := 0.U.asTypeOf(pc.io.commitPreview.bits) + pc.io.commitApply := false.B + pc.io.recovery.prepare.valid := false.B + pc.io.recovery.prepare.bits := + 0.U.asTypeOf(pc.io.recovery.prepare.bits) + pc.io.recovery.prepared.ready := true.B + pc.io.recovery.apply.valid := false.B + pc.io.recovery.apply.bits := 0.U.asTypeOf(pc.io.recovery.apply.bits) + pc.io.recovery.abort.valid := false.B + pc.io.recovery.abort.bits := 0.U.asTypeOf(pc.io.recovery.abort.bits) + + lane.io.p1 <> io.p1 + reads.io.attempts.foreach(_ := 0.U.asTypeOf(reads.io.attempts.head)) + reads.io.attempts(0) := lane.io.readAttempt + lane.io.readDecisionValid := reads.io.decisionValid(0) + lane.io.readGrant := reads.io.grant(0) + lane.io.sourceDataValid := reads.io.sourceDataValid(0) + lane.io.sourceData := reads.io.sourceData(0) + lane.io.pcDataValid := reads.io.pcDataValid(0) + lane.io.pcData := reads.io.pcData(0) + reads.io.pReadResponses.foreach { response => + response.valid := true.B + response.bits := "h1122334455667788".U + } + reads.io.tReadResponses.foreach(_ := 0.U.asTypeOf( + reads.io.tReadResponses.head)) + reads.io.uReadResponses.foreach(_ := 0.U.asTypeOf( + reads.io.uReadResponses.head)) + for (port <- 0 until p.pcReadPorts) { + pc.io.readAddress(port) := reads.io.pcReadRequests(port).bits + reads.io.pcReadResponses(port) := pc.io.readPcBase(port) + } + lane.io.bypass.foreach(_ := 0.U.asTypeOf(lane.io.bypass.head)) + lane.io.loadCancel.foreach(_ := 0.U.asTypeOf(lane.io.loadCancel.head)) + lane.io.stageCancel.foreach { cancel => + cancel.valid := false.B + cancel.bits := 0.U.asTypeOf(cancel.bits) + } + lane.io.recoveryApply.valid := false.B + lane.io.recoveryApply.bits := 0.U.asTypeOf(lane.io.recoveryApply.bits) + lane.io.repick.ready := true.B + io.i2 <> lane.io.i2 +} + +/** Canonical neutral-name mechanism coverage for the private IEX cutover. */ +class IEXMechanismSpec extends AnyFunSuite with ChiselSim { + private def pokeAluDispatch( + txn: DispatchTxn, + transactionId: Int, + ridSlot: Int, + source: Boolean = false): Unit = { + txn.poke(0.U.asTypeOf(txn)) + txn.transactionId.poke(transactionId.U) + txn.uop.decoded.valid.poke(true.B) + txn.uop.decoded.uopClass.poke(UopClass.Alu) + txn.uop.decoded.opcode.poke(0x31.U) + txn.uop.decoded.rob.peId.poke(3.U) + txn.uop.decoded.rob.stid.poke(0.U) + txn.uop.decoded.rob.ridSlot.poke(ridSlot.U) + txn.uop.decoded.rob.ridGeneration.poke(1.U) + txn.uop.decoded.rob.memberIndex.poke(0.U) + txn.uop.decoded.rob.residentGeneration.poke(7.U) + // Keep the identity legal when directed simulation narrows the local + // BROB namespace together with its retained capacity. + txn.uop.decoded.rob.bid.poke(ridSlot.U) + txn.uop.decoded.rob.brobGeneration.poke(11.U) + txn.uop.decoded.instruction.parent.identity.peId.poke(3.U) + txn.uop.decoded.instruction.parent.identity.stid.poke(0.U) + txn.uop.decoded.instruction.parent.identity.instructionId.poke( + transactionId.U) + txn.uop.decoded.instruction.parent.identity.epoch.poke(7.U) + val classification = txn.uop.decoded.classification + classification.valid.poke(true.B) + classification.disposition.poke(OooOpcodeDisposition.Dispatch.U) + classification.kind.poke(OooOpcodeRecipeKind.Single.U) + classification.uopCountMin.poke(1.U) + classification.uopCountMax.poke(1.U) + classification.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) + classification.dispatchWrites.poke(1.U) + classification.dispatchClass.poke(OooDispatchClass.Alu.U) + classification.dispatchDemand(OooDispatchClass.Alu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Alu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) + if (source) { + txn.uop.sources(0).valid.poke(true.B) + txn.uop.sources(0).kind.poke(linxcore.top.interface.OperandKind.Gpr) + txn.uop.sources(0).ptagValid.poke(true.B) + txn.uop.sources(0).ptag.poke(17.U) + txn.uop.sources(0).pGeneration.poke(9.U) + txn.uop.sources(0).ready.poke(true.B) + } + } + + test("W2 W4 W6 W8 derive matching main and bounded issue topology") { + Seq(2, 4, 6, 8).foreach { width => + val core = ParamProfiles.forWidth(width) + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val simulationCore = SimulationParamProfiles.forWidth(width) + val simulationProfile = + OooIexPhysicalProfile.fromCoreParams(simulationCore) + assert(profile.params.dispatchWidth == width) + assert(profile.params.iexIssueDomainCount == + profile.pickerFunctions.length) + assert(profile.transferConfigs.length == profile.pickerFunctions.length) + assert(profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.SimpleAlu)) == + core.iex.aluPipes) + assert(profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.Branch)) == + core.iex.bruPipes) + assert(profile.pickerFunctions.count( + _.hasCapability(OooIexDomainCapability.LoadAddress)) == + core.iex.aguPipes) + assert(simulationProfile.pickerFunctions == profile.pickerFunctions) + assert(simulationProfile.transferConfigs == profile.transferConfigs) + } + } + + test("shared-resource ownership denies a peer and rotates after acceptance") { + val p = OooParams(iexIssueDomainCount = 2) + val capability = OooIexDomainCapability.MultiCycleAlu + val resources = Seq(OooIexSharedResourceConfig( + "shared-mul", capability, Seq(0, 1))) + simulate(new OooIexSharedResourceArbiter(p, resources)) { dut => + val mask = OooIexDomainCapability.mask(capability) + dut.io.requestValid.poke(3.U) + dut.io.capabilities.foreach(_.poke(mask.U)) + dut.io.accepted.poke(0.U) + dut.io.eligible.expect(1.U) + dut.io.conflicted.expect(2.U) + dut.io.accepted.poke(1.U) + dut.clock.step() + dut.io.accepted.poke(0.U) + dut.io.eligible.expect(2.U) + dut.io.conflicted.expect(1.U) + } + } + + test("P1 fabric claims parallel ALU domains and isolates a denied peer") { + val core = SimulationParamProfiles.W4 + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p = profile.params + val aguClass = OooDispatchClass.Agu - 1 + val aguOwners = profile.transferConfigs.filter( + _.classBankEnables(aguClass) != 0) + val aguCapabilityMask = OooIexDomainCapability.mask( + OooIexDomainCapability.LoadAddress) | + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress) + assert(aguOwners.nonEmpty) + assert(aguOwners.forall(owner => + (owner.capabilities & ~aguCapabilityMask) == 0)) + assert(aguOwners.combinations(2).exists { pair => + (pair.head.classBankEnables(aguClass) & + pair.last.classBankEnables(aguClass)) != 0 && + (pair.head.capabilities & pair.last.capabilities) == 0 + }) + simulate(new OooIexIssueP1Fabric(core)) { dut => + dut.io.dispatch.aluDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.bruDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.aguDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.storeDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.systemDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.cmdDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.wakeup.foreach(_.poke(0.U.asTypeOf(dut.io.wakeup.head))) + dut.io.loadCancel.foreach(_.poke(0.U.asTypeOf(dut.io.loadCancel.head))) + dut.io.operandReadyBits.poke(0.U.asTypeOf(dut.io.operandReadyBits)) + dut.io.releases.foreach { release => + release.valid.poke(false.B) + release.bits.poke(0.U.asTypeOf(release.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + for (domain <- 0 until p.iexIssueDomainCount) { + dut.io.pickBankEnables(domain).zip( + profile.transferConfigs(domain).classBankEnables).foreach { + case (target, mask) => target.poke(mask.U) + } + dut.io.readDecisionValid(domain).poke(false.B) + dut.io.readGrant(domain).poke(false.B) + dut.io.sourceDataValid(domain).poke(0.U) + dut.io.sourceData(domain).foreach(_.poke(0.U)) + dut.io.pcDataValid(domain).poke(false.B) + dut.io.pcData(domain).poke(0.U) + dut.io.i2(domain).ready.poke(false.B) + } + dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) + dut.io.stageCancels.flatten.foreach { cancel => + cancel.valid.poke(false.B) + cancel.bits.poke(0.U.asTypeOf(cancel.bits)) + } + dut.io.bypass.foreach(_.poke(0.U.asTypeOf(dut.io.bypass.head))) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + pokeAluDispatch(dut.io.dispatch.aluDispatch(0).bits, 40, 1) + pokeAluDispatch(dut.io.dispatch.aluDispatch(1).bits, 41, 2) + dut.io.dispatch.aluDispatch(0).valid.poke(true.B) + dut.io.dispatch.aluDispatch(1).valid.poke(true.B) + dut.io.dispatch.aluDispatch(0).ready.expect(true.B) + dut.io.dispatch.aluDispatch(1).ready.expect(true.B) + dut.clock.step() + dut.io.dispatch.aluDispatch.foreach(_.valid.poke(false.B)) + dut.clock.step(3) + + val contenders = dut.io.readAttempts.zipWithIndex.filter { + case (attempt, _) => attempt.valid.peek().litToBoolean + } + assert(contenders.length == 2) + val winner = contenders.head._2 + val loser = contenders.last._2 + dut.io.readDecisionValid(winner).poke(true.B) + dut.io.readGrant(winner).poke(true.B) + dut.io.readDecisionValid(loser).poke(true.B) + dut.io.readGrant(loser).poke(false.B) + dut.io.retryFeedback(loser).valid.expect(true.B) + dut.clock.step() + dut.io.i2(winner).valid.expect(true.B) + dut.io.i2(loser).valid.expect(false.B) + } + } + + test("composed operand files return missing data as an exact IQ repick") { + val core = SimulationParamProfiles.W2 + val profile = OooIexPhysicalProfile.fromCoreParams(core) + val p = profile.params + simulate(new OooIexIssueReadFabric(core)) { dut => + dut.io.dispatch.aluDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + Seq(dut.io.dispatch.bruDispatch, dut.io.dispatch.aguDispatch, + dut.io.dispatch.systemDispatch, dut.io.dispatch.cmdDispatch) + .foreach(_.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + }) + dut.io.dispatch.storeDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.wakeup.foreach(_.poke(0.U.asTypeOf(dut.io.wakeup.head))) + dut.io.loadCancel.foreach(_.poke(0.U.asTypeOf(dut.io.loadCancel.head))) + dut.io.releases.foreach { release => + release.valid.poke(false.B) + release.bits.poke(0.U.asTypeOf(release.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) + dut.io.stageCancels.flatten.foreach { cancel => + cancel.valid.poke(false.B) + cancel.bits.poke(0.U.asTypeOf(cancel.bits)) + } + dut.io.pcReadResponses.foreach( + _.poke(0.U.asTypeOf(dut.io.pcReadResponses.head))) + dut.io.bypass.foreach(_.poke(0.U.asTypeOf(dut.io.bypass.head))) + dut.io.pInit.poke(0.U.asTypeOf(dut.io.pInit)) + dut.io.pClear.foreach(_.poke(0.U.asTypeOf(dut.io.pClear.head))) + dut.io.pWrite.foreach(_.poke(0.U.asTypeOf(dut.io.pWrite.head))) + dut.io.tClear.foreach(_.poke(0.U.asTypeOf(dut.io.tClear.head))) + dut.io.uClear.foreach(_.poke(0.U.asTypeOf(dut.io.uClear.head))) + dut.io.tWrite.foreach(_.poke(0.U.asTypeOf(dut.io.tWrite.head))) + dut.io.uWrite.foreach(_.poke(0.U.asTypeOf(dut.io.uWrite.head))) + dut.io.i2.foreach(_.ready.poke(false.B)) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + // Admit the source while its exact physical-register owner is ready, + // then clear that owner before the retained I1 read. This exercises the + // intended ready-at-admission/data-missing-at-read retry path. + dut.io.pInit.valid.poke(true.B) + dut.io.pInit.bits.key.stid.poke(0.U) + dut.io.pInit.bits.key.epoch.poke(7.U) + dut.io.pInit.bits.key.ptag.poke(17.U) + dut.io.pInit.bits.key.generation.poke(9.U) + dut.io.pInit.bits.data.poke("h1122334455667788".U) + dut.clock.step() + dut.io.pInit.valid.poke(false.B) + + val channel = dut.io.dispatch.aluDispatch.head + pokeAluDispatch(channel.bits, 70, 1, source = true) + channel.valid.poke(true.B) + channel.ready.expect(true.B) + dut.clock.step() + channel.valid.poke(false.B) + dut.io.pClear(0).valid.poke(true.B) + dut.io.pClear(0).bits.stid.poke(0.U) + dut.io.pClear(0).bits.epoch.poke(7.U) + dut.io.pClear(0).bits.ptag.poke(17.U) + dut.io.pClear(0).bits.generation.poke(9.U) + dut.clock.step() + dut.io.pClear(0).valid.poke(false.B) + + var sawInvalid = false + var sawRetry = false + for (_ <- 0 until 8) { + sawInvalid ||= dut.io.readRejected.exists( + _.valid.peek().litToBoolean) + sawRetry ||= dut.io.retryFeedback.exists( + _.valid.peek().litToBoolean) + dut.clock.step() + } + assert(sawInvalid) + assert(sawRetry) + assert(dut.io.sharedMalformedMask.peek().litValue == 0) + } + } + + private def pokeRob( + target: linxcore.top.interface.RobIdentity, + rid: Int): Unit = { + target.peId.poke(3.U) + target.stid.poke(0.U) + target.ridSlot.poke(rid.U) + target.ridGeneration.poke(0.U) + target.memberIndex.poke(0.U) + target.residentGeneration.poke((20 + rid).U) + target.bid.poke(rid.U) + target.brobGeneration.poke((7 + rid).U) + } + + test("real PC buffer base reaches a retained I2 transaction") { + val core = SimulationParamProfiles.W2 + simulate(new IEXPcReadHarness(core)) { dut => + val p = dut.p + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.p1.valid.poke(false.B) + dut.io.p1.bits.poke(0.U.asTypeOf(dut.io.p1.bits)) + dut.io.i2.ready.poke(false.B) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + val entry = dut.io.prepare.bits.entries(0) + dut.io.prepare.bits.count.poke(1.U) + dut.io.prepare.bits.groupCount.poke(1.U) + dut.io.prepare.bits.groups(0).valid.poke(true.B) + dut.io.prepare.bits.groups(0).peId.poke(3.U) + dut.io.prepare.bits.groups(0).stid.poke(0.U) + dut.io.prepare.bits.groups(0).ridSlot.poke(1.U) + entry.uop.decoded.valid.poke(true.B) + pokeRob(entry.uop.decoded.rob, 1) + entry.uop.decoded.instruction.parent.pc.poke("h80000120".U) + entry.uop.decoded.instruction.parent.lengthBytes.poke(2.U) + entry.uop.decoded.instruction.parent.identity.peId.poke(3.U) + entry.uop.decoded.instruction.parent.identity.stid.poke(0.U) + entry.uop.decoded.instruction.parent.identity.instructionId.poke(9.U) + entry.uop.decoded.instruction.parent.identity.epoch.poke(1.U) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + val token = dut.io.prepared.lanes(0) + val index = token.pcBufferIndex.peek().litValue + val epoch = token.allocationEpoch.peek().litValue + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + val request = dut.io.p1.bits + request.poke(0.U.asTypeOf(request)) + request.row.schedule.valid.poke(true.B) + request.row.schedule.peId.poke(3.U) + request.row.schedule.stid.poke(0.U) + request.row.schedule.epoch.poke(1.U) + request.row.schedule.transactionId.poke(9.U) + request.row.schedule.member.group.valid.poke(true.B) + request.row.schedule.member.group.peId.poke(3.U) + request.row.schedule.member.group.stid.poke(0.U) + request.row.schedule.member.group.ridSlot.poke(1.U) + request.row.schedule.member.bid.valid.poke(true.B) + request.row.schedule.reservation.valid.poke(true.B) + request.row.schedule.reservation.uopClass.poke(OooUopClass.Alu) + request.row.schedule.reservation.bank.poke(0.U) + request.row.schedule.reservation.speculativeSlot.poke(0.U) + request.row.payload.uopKey.primaryParent.valid.poke(true.B) + request.row.payload.uopKey.primaryParent.peId.poke(3.U) + request.row.payload.uopKey.primaryParent.stid.poke(0.U) + request.row.payload.parentCount.poke(1.U) + request.row.payload.parentPcTokens(0).valid.poke(true.B) + request.row.payload.parentPcTokens(0).index.poke(index.U) + request.row.payload.parentPcTokens(0).byteOffset.poke(6.U) + request.row.payload.parentPcTokens(0).allocationEpoch.poke(epoch.U) + request.pcReadRequired.poke(true.B) + request.pcParentIndex.poke(0.U) + dut.io.p1.valid.poke(true.B) + dut.clock.step() + dut.io.p1.valid.poke(false.B) + dut.clock.step() + dut.io.i2.valid.expect(true.B) + dut.io.i2.bits.pcValid.expect(true.B) + dut.io.i2.bits.pc.expect("h80000126".U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXPipesSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXPipesSpec.scala new file mode 100644 index 00000000..6e59db58 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXPipesSpec.scala @@ -0,0 +1,29 @@ +package linxcore.iex + +import circt.stage.ChiselStage +import linxcore.ooo.{OooIexDomainCapability, OooIexPhysicalProfile} +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class IEXPipesSpec extends AnyFunSuite { + test("W4 public IEX exposes the frozen physical execution topology") { + val p = SimulationParamProfiles.W4 + val profile = OooIexPhysicalProfile.fromCoreParams(p) + def lanes(capability: Int): Int = + profile.pickerFunctions.count(_.hasCapability(capability)) + assert(lanes(OooIexDomainCapability.SimpleAlu) == 2) + assert(lanes(OooIexDomainCapability.Branch) == 1) + assert(lanes(OooIexDomainCapability.LoadAddress) == 2) + assert(lanes(OooIexDomainCapability.StoreAddress) == 2) + assert(lanes(OooIexDomainCapability.StoreData) == 2) + assert(p.iex.systemMulticycleQueues == 1) + assert(p.iex.cmdIssueQueues == 1) + assert(p.lsu.loadPipes == 2) + assert(p.lsu.storePipes == 2) + val sv = ChiselStage.emitSystemVerilog(new IEX(p)) + assert(sv.contains("module OooIexAluPipeline")) + assert(sv.contains("module OooIexBruPipeline")) + assert(sv.contains("module OooIexAguPipeline")) + assert(sv.contains("OooIexSystemCmdTerminal")) + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala new file mode 100644 index 00000000..e06910ec --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala @@ -0,0 +1,742 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util.log2Ceil +import linxcore.common.OperandClass +import linxcore.ooo.{OooDispatchClass, OooIexDomainCapability, OooIexIssue, + OooIexIssueIO, OooIexIssueSlotState, OooIexPhysicalProfile, + OooIexWakeupKind, + OooLateSplitKind, OooOpcodeDisposition, OooOpcodeRecipeKind, + OooSideEffectOwner, OooUopClass} +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface.{DispatchTxn, OperandKind, StoreDispatchTxn, + UopClass} +import org.scalatest.funsuite.AnyFunSuite + +/** Contract for the private canonical OOO-to-IEX admission seam. + * + * OooIexIssue consumes canonical classed dispatch directly and owns the + * resulting IQ reservation. These tests protect that post-cutover contract + * without reconstructing the displaced grouped S1 lease. + */ +class IEXPrivateIngressSpec extends AnyFunSuite with ChiselSim { + private val core = SimulationParamProfiles.W4.copy( + iex = SimulationParamProfiles.W4.iex.copy( + scalarIssueEntries = 4, + scalarIssueBanks = 2)) + private val physical = OooIexPhysicalProfile.fromCoreParams(core).params + + private def clearDispatch(dut: OooIexIssue): Unit = { + dut.io.dispatch.aluDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.bruDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.aguDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.storeDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.systemDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + dut.io.dispatch.cmdDispatch.foreach { channel => + channel.valid.poke(false.B) + channel.bits.poke(0.U.asTypeOf(channel.bits)) + } + } + + private def clearControls(dut: OooIexIssue): Unit = { + clearDispatch(dut) + dut.io.storeReserve.foreach(_.ready.poke(true.B)) + dut.io.wakeup.foreach { wakeup => + wakeup.valid.poke(false.B) + } + dut.io.loadCancel.foreach { cancel => + cancel.valid.poke(false.B) + } + dut.io.loadCancelRetries.flatten.foreach { retry => + retry.valid.poke(false.B) + } + dut.io.releases.foreach { release => + release.valid.poke(false.B) + } + dut.io.queries.foreach { query => + query.uopClass.poke(OooUopClass.Alu) + if (dut.p.iqBankCount > 1) query.bank.poke(0.U) + if (dut.p.iqEntriesPerBank > 1) query.entry.poke(0.U) + } + dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) + dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) + dut.io.picks.foreach(_.ready.poke(false.B)) + dut.io.pickRetries.foreach { retry => + retry.valid.poke(false.B) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.operandReadyBits.poke( + 0.U.asTypeOf(dut.io.operandReadyBits)) + } + + private def pokeRobIdentity( + txn: DispatchTxn, + stid: Int, + ridSlot: Int, + memberIndex: Int): Unit = { + val rob = txn.uop.decoded.rob + rob.peId.poke(3.U) + rob.stid.poke(stid.U) + rob.ridSlot.poke(ridSlot.U) + rob.ridGeneration.poke(5.U) + rob.memberIndex.poke(memberIndex.U) + rob.residentGeneration.poke(7.U) + rob.bid.poke(2.U) + rob.brobGeneration.poke(11.U) + } + + private def pokeDispatch( + dut: OooIexIssue, + txn: DispatchTxn, + transactionId: BigInt, + uopClass: UopClass.Type, + sourceReady: Boolean = true, + stid: Int = 0, + ridSlot: Int = 1, + memberIndex: Int = 0, + trapValid: Boolean = false, + trapCause: Int = 0): Unit = { + txn.poke(0.U.asTypeOf(txn)) + txn.transactionId.poke(transactionId.U) + txn.uop.decoded.valid.poke(true.B) + txn.uop.decoded.uopClass.poke(uopClass) + txn.uop.decoded.opcode.poke(0x31.U) + val classification = txn.uop.decoded.classification + val uopClassValue = uopClass.asUInt.litValue.toInt + val aluValue = UopClass.Alu.asUInt.litValue.toInt + val bruValue = UopClass.Bru.asUInt.litValue.toInt + val aguValue = UopClass.Agu.asUInt.litValue.toInt + val stdValue = UopClass.Std.asUInt.litValue.toInt + val systemValue = UopClass.System.asUInt.litValue.toInt + val cmdValue = UopClass.Cmd.asUInt.litValue.toInt + classification.valid.poke(true.B) + classification.disposition.poke(OooOpcodeDisposition.Dispatch.U) + classification.kind.poke( + (if (uopClassValue == stdValue) OooOpcodeRecipeKind.ScalarStore + else if (uopClassValue == aguValue) OooOpcodeRecipeKind.ScalarLoad + else OooOpcodeRecipeKind.Single).U) + classification.uopCountMin.poke(1.U) + classification.uopCountMax.poke( + (if (uopClassValue == stdValue) 2 else 1).U) + classification.sideEffectOwner.poke( + (if (uopClassValue == stdValue || uopClassValue == aguValue) + OooSideEffectOwner.Lsu + else if (uopClassValue == bruValue) OooSideEffectOwner.Bctrl + else if (uopClassValue == systemValue || uopClassValue == cmdValue) + OooSideEffectOwner.Commit + else OooSideEffectOwner.Iex).U) + classification.dispatchWrites.poke( + (if (uopClassValue == stdValue) 2 else 1).U) + if (uopClassValue == aluValue) { + classification.dispatchClass.poke(OooDispatchClass.Alu.U) + classification.dispatchDemand(OooDispatchClass.Alu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Alu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) + } else if (uopClassValue == bruValue) { + classification.dispatchClass.poke(OooDispatchClass.Bru.U) + classification.dispatchDemand(OooDispatchClass.Bru - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Bru - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.Branch).U) + } else if (uopClassValue == aguValue) { + classification.dispatchClass.poke(OooDispatchClass.Agu.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress).U) + } else if (uopClassValue == stdValue) { + classification.dispatchClass.poke(OooDispatchClass.Std.U) + classification.splitKind.poke(OooLateSplitKind.StoreAddressData.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.dispatchDemand(OooDispatchClass.Std - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress).U) + classification.executionPipeCapability(OooDispatchClass.Std - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreData).U) + } else if (uopClassValue == systemValue) { + classification.dispatchClass.poke(OooDispatchClass.Sys.U) + classification.dispatchDemand(OooDispatchClass.Sys - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Sys - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.System).U) + } else if (uopClassValue == cmdValue) { + classification.dispatchClass.poke(OooDispatchClass.Cmd.U) + classification.dispatchDemand(OooDispatchClass.Cmd - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Cmd - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.EngineCommand).U) + } + if (uopClassValue == aguValue || uopClassValue == stdValue) { + val memory = txn.uop.decoded.memory + memory.valid.poke(true.B) + memory.isLoad.poke((uopClassValue == aguValue).B) + memory.isStore.poke((uopClassValue == stdValue).B) + memory.requestCount.poke(1.U) + memory.accessBytes.poke(8.U) + memory.addressSourceMask.poke(1.U) + memory.dataSourceMask.poke( + (if (uopClassValue == stdValue) 1 else 0).U) + classification.memoryRequestCount.poke(1.U) + txn.memoryOrder.requestCount.poke(1.U) + txn.memoryOrder.firstLsid.poke((0x100 + ridSlot).U) + txn.memoryOrder.firstLid.poke((0x20 + ridSlot).U) + txn.memoryOrder.firstSid.poke((0x40 + ridSlot).U) + } + txn.trap.valid.poke(trapValid.B) + txn.trap.cause.poke(trapCause.U) + pokeRobIdentity(txn, stid, ridSlot, memberIndex) + txn.uop.decoded.instruction.parent.identity.peId.poke(3.U) + txn.uop.decoded.instruction.parent.identity.stid.poke(stid.U) + txn.uop.decoded.instruction.parent.identity.epoch.poke(7.U) + + val source = txn.uop.sources(0) + source.valid.poke(true.B) + source.kind.poke(OperandKind.Gpr) + source.atag.poke(6.U) + source.ptagValid.poke(true.B) + source.ptag.poke(17.U) + source.pGeneration.poke(9.U) + source.ready.poke(sourceReady.B) + dut.io.operandReadyBits.ptag(17).valid.poke(true.B) + dut.io.operandReadyBits.ptag(17).ready.poke(sourceReady.B) + dut.io.operandReadyBits.ptag(17).stid.poke(stid.U) + dut.io.operandReadyBits.ptag(17).epoch.poke(7.U) + dut.io.operandReadyBits.ptag(17).generation.poke(9.U) + } + + private def accept(channel: chisel3.util.DecoupledIO[DispatchTxn], + dut: OooIexIssue): Unit = { + channel.ready.expect(true.B) + dut.clock.step() + channel.valid.poke(false.B) + dut.clock.step(2) + } + + private def residentCount(dut: OooIexIssue, uopClass: Int): BigInt = + (0 until dut.p.iqBankCount).map { bank => + dut.io.residentEntries(uopClass)(bank).peek().litValue + }.sum + + private def findResident( + dut: OooIexIssue, + uopClass: OooUopClass.Type): (Int, Int) = { + for { + bank <- 0 until dut.p.iqBankCount + entry <- 0 until dut.p.iqEntriesPerBank + } { + dut.io.queries(0).uopClass.poke(uopClass) + if (dut.p.iqBankCount > 1) dut.io.queries(0).bank.poke(bank.U) + if (dut.p.iqEntriesPerBank > 1) dut.io.queries(0).entry.poke(entry.U) + if (dut.io.queryStates(0).peek().litValue == + OooIexIssueSlotState.ResidentS3.asUInt.litValue) + return (bank, entry) + } + fail(s"no resident row found for $uopClass") + } + + private def findResidentByTransaction( + dut: OooIexIssue, + uopClass: OooUopClass.Type, + transactionId: BigInt): (Int, Int) = { + for { + bank <- 0 until dut.p.iqBankCount + entry <- 0 until dut.p.iqEntriesPerBank + } { + dut.io.queries(0).uopClass.poke(uopClass) + if (dut.p.iqBankCount > 1) dut.io.queries(0).bank.poke(bank.U) + if (dut.p.iqEntriesPerBank > 1) dut.io.queries(0).entry.poke(entry.U) + if (dut.io.queryStates(0).peek().litValue == + OooIexIssueSlotState.ResidentS3.asUInt.litValue && + dut.io.queryRows(0).transactionId.peek().litValue == transactionId) + return (bank, entry) + } + fail(s"no resident $uopClass row found for transaction $transactionId") + } + + test("W4 exposes classed canonical dispatch vectors without grouped lease ports") { + val io = new OooIexIssueIO(core) + + assert(io.dispatch.aluDispatch.length == 2) + assert(io.dispatch.bruDispatch.length == 1) + assert(io.dispatch.aguDispatch.length == 2) + assert(io.dispatch.storeDispatch.length == 2) + assert(io.dispatch.systemDispatch.length == 1) + assert(io.dispatch.cmdDispatch.length == 1) + assert(io.dispatch.aluDispatch.head.bits.isInstanceOf[DispatchTxn]) + assert(io.dispatch.storeDispatch.head.bits.isInstanceOf[StoreDispatchTxn]) + assert(!io.elements.contains("s1")) + assert(!io.elements.contains("dispatchReleases")) + } + + test("accepts one canonical ALU DispatchTxn directly into IQ residency") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 41, + uopClass = UopClass.Alu) + channel.bits.uop.decoded.classification.nonspeculative.poke(true.B) + channel.bits.uop.decoded.classification.pcReadRequired.poke(true.B) + channel.bits.uop.decoded.classification.pcReadClass.poke(6.U) + channel.valid.poke(true.B) + + accept(channel, dut) + + assert(residentCount(dut, OooUopClass.Alu.asUInt.litValue.toInt) == 1) + findResident(dut, OooUopClass.Alu) + dut.io.queryRows(0).transactionId.expect(41.U) + dut.io.queryRows(0).recipe.nonspeculative.expect(true.B) + dut.io.queryRows(0).recipe.pcReadRequired.expect(true.B) + dut.io.queryRows(0).recipe.pcReadClass.expect(6.U) + dut.io.queryRows(0).recipe.dispatchCapabilities( + OooDispatchClass.Alu - 1).expect( + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) + dut.io.queryRows(0).memoryTransactionValid.expect(false.B) + dut.io.queryRows(0).initialLoadAttemptValid.expect(false.B) + } + } + + test("spills ALU admission into an eligible bank when the first bank is full") { + val compactCore = core.copy( + iex = core.iex.copy(scalarIssueEntries = 4, scalarIssueBanks = 2)) + simulate(new OooIexIssue(compactCore)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + val aluClass = OooUopClass.Alu.asUInt.litValue.toInt + + Seq(47, 48).foreach { transactionId => + pokeDispatch(dut, channel.bits, transactionId, + uopClass = UopClass.Alu) + channel.valid.poke(true.B) + accept(channel, dut) + } + dut.io.residentEntries(aluClass)(0).expect(2.U) + dut.io.residentEntries(aluClass)(1).expect(0.U) + + pokeDispatch(dut, channel.bits, transactionId = 49, + uopClass = UopClass.Alu) + channel.valid.poke(true.B) + channel.ready.expect(true.B) + dut.clock.step() + channel.valid.poke(false.B) + dut.clock.step(2) + + dut.io.residentEntries(aluClass)(0).expect(2.U) + dut.io.residentEntries(aluClass)(1).expect(1.U) + findResidentByTransaction(dut, OooUopClass.Alu, 49) + dut.io.queryRows(0).reservation.bank.expect(1.U) + } + } + + test("allocates memory identity at IQ admission and shares it across STA and STD") { + simulate(new OooIexIssue(core, requireStoreReservation = true)) { dut => + clearControls(dut) + val load = dut.io.dispatch.aguDispatch(0) + pokeDispatch(dut, load.bits, transactionId = 51, + uopClass = UopClass.Agu, stid = 0, ridSlot = 1) + load.valid.poke(true.B) + accept(load, dut) + findResidentByTransaction(dut, OooUopClass.Agu, 51) + dut.io.queryRows(0).memoryTransactionValid.expect(true.B) + dut.io.queryRows(0).memoryTransaction.value.expect(0.U) + dut.io.queryRows(0).memoryTransaction.generation.expect(0.U) + dut.io.queryRows(0).initialLoadAttemptValid.expect(true.B) + dut.io.queryRows(0).initialLoadAttemptGeneration.expect(1.U) + + val channel = dut.io.dispatch.storeDispatch(1) + pokeDispatch(dut, channel.bits.sta, transactionId = 52, + uopClass = UopClass.Std, stid = 0, ridSlot = 2) + pokeDispatch(dut, channel.bits.std, transactionId = 52, + uopClass = UopClass.Std, stid = 0, ridSlot = 2) + channel.bits.sta.memoryOrder.requestCount.poke(1.U) + channel.bits.sta.memoryOrder.firstLsid.poke(0x1234.U) + channel.bits.sta.memoryOrder.firstSid.poke(0x55.U) + channel.bits.std.memoryOrder.poke(channel.bits.sta.memoryOrder.peek()) + channel.bits.aguPipe.poke(0.U) + channel.bits.stdPipe.poke(1.U) + channel.valid.poke(true.B) + + channel.ready.expect(true.B) + dut.io.storeReserve(1).valid.expect(true.B) + dut.io.storeReserve(1).bits.transactionId.expect(52.U) + dut.io.storeReserve(1).bits.reservation.uopClass.expect(OooUopClass.Agu) + dut.io.storeReserve(1).bits.memoryTransactionValid.expect(true.B) + dut.io.storeReserve(1).bits.memoryTransaction.value.expect(1.U) + dut.io.storeReserve(1).bits.memoryTransaction.generation.expect(0.U) + dut.io.storeReserve(1).bits.initialLoadAttemptValid.expect(false.B) + dut.io.storeReserve(1).bits.initialLoadAttemptGeneration.expect(0.U) + dut.clock.step() + channel.valid.poke(false.B) + assert(residentCount(dut, OooUopClass.Agu.asUInt.litValue.toInt) == 1) + assert(residentCount(dut, OooUopClass.Std.asUInt.litValue.toInt) == 0) + dut.clock.step(2) + + assert(residentCount(dut, OooUopClass.Agu.asUInt.litValue.toInt) == 2) + assert(residentCount(dut, OooUopClass.Std.asUInt.litValue.toInt) == 1) + findResidentByTransaction(dut, OooUopClass.Agu, 52) + dut.io.queryRows(0).memoryTransaction.value.expect(1.U) + dut.io.queryRows(0).initialLoadAttemptValid.expect(false.B) + findResidentByTransaction(dut, OooUopClass.Std, 52) + dut.io.queryRows(0).memoryTransaction.value.expect(1.U) + dut.io.queryRows(0).memoryTransaction.generation.expect(0.U) + dut.io.queryRows(0).initialLoadAttemptValid.expect(false.B) + dut.io.queryRows(0).initialLoadAttemptGeneration.expect(0.U) + } + } + + test("rejects malformed memory admission without consuming IEX identity") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aguDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 57, + uopClass = UopClass.Agu, ridSlot = 1) + channel.bits.uop.decoded.memory.valid.poke(false.B) + channel.valid.poke(true.B) + channel.ready.expect(false.B) + dut.clock.step(2) + assert(residentCount(dut, OooUopClass.Agu.asUInt.litValue.toInt) == 0) + + channel.bits.uop.decoded.memory.valid.poke(true.B) + accept(channel, dut) + findResidentByTransaction(dut, OooUopClass.Agu, 57) + dut.io.queryRows(0).memoryTransaction.value.expect(0.U) + dut.io.queryRows(0).initialLoadAttemptGeneration.expect(1.U) + } + } + + test("does not mutate IQ state while a blocked canonical payload stays stable") { + val compactCore = core.copy( + iex = core.iex.copy(scalarIssueEntries = 4, scalarIssueBanks = 2)) + simulate(new OooIexIssue(compactCore)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + Seq(61, 62, 63, 64).foreach { transactionId => + pokeDispatch(dut, channel.bits, transactionId, + uopClass = UopClass.Alu) + channel.valid.poke(true.B) + accept(channel, dut) + } + assert(residentCount(dut, OooUopClass.Alu.asUInt.litValue.toInt) == 4) + + pokeDispatch(dut, channel.bits, transactionId = 65, + uopClass = UopClass.Alu) + channel.valid.poke(true.B) + val retainedPayload = channel.bits.peek().litValue + channel.ready.expect(false.B) + dut.clock.step(3) + + channel.ready.expect(false.B) + assert(channel.bits.peek().litValue == retainedPayload) + assert(residentCount(dut, OooUopClass.Alu.asUInt.litValue.toInt) == 4) + } + } + + test("preserves initial renamed-source readiness when the row becomes resident") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 74, + uopClass = UopClass.Alu, sourceReady = false) + channel.valid.poke(true.B) + accept(channel, dut) + + findResident(dut, OooUopClass.Alu) + dut.io.queryRows(0).sources(0).valid.expect(true.B) + dut.io.queryRows(0).sources(0).ptag.expect(17.U) + dut.io.queryRows(0).sources(0).ptagGeneration.expect(9.U) + dut.io.queryRows(0).sources(0).ready.expect(false.B) + dut.io.queryPickables(0).expect(false.B) + } + } + + test("load-canceled private stages return the exact in-flight IQ row") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 740, + uopClass = UopClass.Alu) + channel.valid.poke(true.B) + accept(channel, dut) + + val aluClass = OooUopClass.Alu.asUInt.litValue.toInt + val (bank, entry) = findResidentByTransaction( + dut, OooUopClass.Alu, 740) + val capability = OooIexDomainCapability.mask( + OooIexDomainCapability.SimpleAlu) + val domain = OooIexPhysicalProfile.fromCoreParams(core).transferConfigs + .zipWithIndex.collectFirst { + case (config, index) + if (config.classBankEnables(aluClass) & (1 << bank)) != 0 && + (config.capabilities & capability) != 0 => index + }.get + + dut.io.pickBankEnables(domain)(aluClass).poke((1 << bank).U) + dut.io.picks(domain).ready.poke(false.B) + var pickVisible = false + for (_ <- 0 until 4 if !pickVisible) { + pickVisible = dut.io.picks(domain).valid.peek().litToBoolean + if (!pickVisible) dut.clock.step() + } + assert(pickVisible) + dut.io.picks(domain).ready.poke(true.B) + dut.clock.step() + dut.io.picks(domain).ready.poke(false.B) + + dut.io.queries(0).uopClass.poke(OooUopClass.Alu) + dut.io.queries(0).bank.poke(bank.U) + dut.io.queries(0).entry.poke(entry.U) + dut.io.queryRows(0).schedule.inFlight.expect(true.B) + + val retry = dut.io.loadCancelRetries(domain)(1) + retry.bits.member.poke(dut.io.queryRows(0).member.peek()) + retry.bits.reservation.poke(dut.io.queryRows(0).reservation.peek()) + retry.valid.poke(true.B) + dut.clock.step() + retry.valid.poke(false.B) + + dut.io.queryRows(0).schedule.inFlight.expect(false.B) + dut.io.queryStates(0).expect(OooIexIssueSlotState.ResidentS3) + } + } + + test("accepts an exact PTag generation across frontend epochs") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 741, + uopClass = UopClass.Alu, sourceReady = false) + channel.bits.uop.decoded.instruction.parent.identity.epoch.poke(8.U) + dut.io.operandReadyBits.ptag(17).ready.poke(true.B) + // The committed physical mapping was created in epoch 7. Generation + // 9 remains its exact reuse identity for a consumer in epoch 8. + dut.io.operandReadyBits.ptag(17).epoch.poke(7.U) + channel.valid.poke(true.B) + accept(channel, dut) + + findResidentByTransaction(dut, OooUopClass.Alu, 741) + dut.io.queryRows(0).sources(0).ready.expect(true.B) + } + } + + test("wakes-resident-p-source-across-frontend-epochs") { + simulate(new OooIexIssue(SimulationParamProfiles.W2)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 742, + uopClass = UopClass.Alu, sourceReady = false) + channel.bits.uop.decoded.instruction.parent.identity.epoch.poke(8.U) + channel.valid.poke(true.B) + accept(channel, dut) + + findResidentByTransaction(dut, OooUopClass.Alu, 742) + dut.io.queryRows(0).sources(0).ready.expect(false.B) + + val wakeup = dut.io.wakeup(0) + wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) + wakeup.bits.kind.poke(OooIexWakeupKind.Committed) + wakeup.bits.stid.poke(0.U) + // A P mapping can be produced in an older frontend epoch. Its + // generation, rather than that producer epoch, qualifies the wakeup. + wakeup.bits.epoch.poke(7.U) + wakeup.bits.operandClass.poke(OperandClass.P) + wakeup.bits.ptag.poke(17.U) + wakeup.bits.ptagGeneration.poke(9.U) + wakeup.valid.poke(true.B) + dut.clock.step() + wakeup.valid.poke(false.B) + + dut.io.queryRows(0).sources(0).ready.expect(true.B) + + pokeDispatch(dut, channel.bits, transactionId = 743, + uopClass = UopClass.Alu, sourceReady = false, ridSlot = 2) + channel.bits.uop.decoded.instruction.parent.identity.epoch.poke(9.U) + channel.valid.poke(true.B) + accept(channel, dut) + findResidentByTransaction(dut, OooUopClass.Alu, 743) + dut.io.queryRows(0).sources(0).specReady.expect(false.B) + + wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) + wakeup.bits.kind.poke(OooIexWakeupKind.SpeculativeLoad) + wakeup.bits.stid.poke(0.U) + wakeup.bits.epoch.poke(7.U) + wakeup.bits.operandClass.poke(OperandClass.P) + wakeup.bits.ptag.poke(17.U) + wakeup.bits.ptagGeneration.poke(9.U) + wakeup.bits.load.valid.poke(true.B) + wakeup.valid.poke(true.B) + dut.clock.step() + wakeup.valid.poke(false.B) + + dut.io.queryRows(0).sources(0).specReady.expect(true.B) + + pokeDispatch(dut, channel.bits, transactionId = 744, + uopClass = UopClass.Alu, sourceReady = false, ridSlot = 3) + channel.bits.uop.decoded.instruction.parent.identity.epoch.poke(10.U) + channel.valid.poke(true.B) + accept(channel, dut) + findResidentByTransaction(dut, OooUopClass.Alu, 744) + dut.io.queryRows(0).sources(0).ready.expect(false.B) + + // A file write and row admission can cross the same edge after the + // one-cycle wakeup. The resident row must converge from the exact + // generation-qualified readiness state instead of waiting forever for + // a second wakeup pulse. + dut.io.operandReadyBits.ptag(17).ready.poke(true.B) + dut.io.queryRows(0).sources(0).ready.expect(true.B) + dut.io.queryRows(0).sources(0).specReady.expect(false.B) + dut.clock.step() + dut.io.queryRows(0).sources(0).ready.expect(true.B) + } + } + + test("accepts-exact-local-source-owner-epoch-across-frontend-epochs") { + simulate(new OooIexIssue(SimulationParamProfiles.W2)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 745, + uopClass = UopClass.Alu, sourceReady = false) + channel.bits.uop.decoded.instruction.parent.identity.epoch.poke(11.U) + val source = channel.bits.uop.sources(0) + source.kind.poke(OperandKind.T) + source.ptagValid.poke(false.B) + source.ttagValid.poke(true.B) + source.ttag.poke(4.U) + source.tSeqIndex.poke(4.U) + source.tSeqGeneration.poke(0.U) + source.localEpoch.poke(9.U) + val ready = dut.io.operandReadyBits.ttag(0)(4) + ready.allocated.poke(true.B) + ready.ready.poke(true.B) + ready.epoch.poke(9.U) + ready.sequence.valid.poke(true.B) + ready.sequence.index.poke(4.U) + ready.sequence.generation.poke(0.U) + channel.valid.poke(true.B) + accept(channel, dut) + + findResidentByTransaction(dut, OooUopClass.Alu, 745) + dut.io.queryRows(0).sources(0).localEpoch.expect(9.U) + dut.io.queryRows(0).sources(0).ready.expect(true.B) + } + } + + test("unequal identity and physical tag capacities reject aliases for P T and U readiness") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + assert(physical.pTagWidth > log2Ceil(physical.pPhysRegs)) + assert(physical.tTagWidth > log2Ceil(physical.tPhysRegs)) + assert(physical.uTagWidth > log2Ceil(physical.uPhysRegs)) + + def configureLocalSource( + source: linxcore.top.interface.RenamedSource, + kind: OperandKind.Type, + tag: Int, + sequenceIndex: Int, + sequenceGeneration: Int): Unit = { + source.valid.poke(true.B) + source.kind.poke(kind) + source.ready.poke(false.B) + if (kind == OperandKind.T) { + source.ttagValid.poke(true.B) + source.ttag.poke(tag.U) + source.tSeqIndex.poke(sequenceIndex.U) + source.tSeqGeneration.poke(sequenceGeneration.U) + } else { + source.utagValid.poke(true.B) + source.utag.poke(tag.U) + source.uSeqIndex.poke(sequenceIndex.U) + source.uSeqGeneration.poke(sequenceGeneration.U) + } + } + + def configureLocalReady( + entry: linxcore.ooo.OooIexLocalReadyBitsEntry, + sequenceIndex: Int, + sequenceGeneration: Int): Unit = { + entry.allocated.poke(true.B) + entry.ready.poke(true.B) + entry.epoch.poke(7.U) + entry.sequence.valid.poke(true.B) + entry.sequence.index.poke(sequenceIndex.U) + entry.sequence.generation.poke(sequenceGeneration.U) + } + + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 75, + uopClass = UopClass.Alu, sourceReady = false) + configureLocalSource(channel.bits.uop.sources(1), OperandKind.T, + tag = 3, sequenceIndex = 1, sequenceGeneration = 2) + configureLocalSource(channel.bits.uop.sources(2), OperandKind.U, + tag = 4, sequenceIndex = 3, sequenceGeneration = 4) + dut.io.operandReadyBits.ptag(17).ready.poke(true.B) + configureLocalReady(dut.io.operandReadyBits.ttag(0)(3), + sequenceIndex = 1, sequenceGeneration = 2) + configureLocalReady(dut.io.operandReadyBits.utag(0)(4), + sequenceIndex = 3, sequenceGeneration = 4) + channel.valid.poke(true.B) + accept(channel, dut) + findResidentByTransaction(dut, OooUopClass.Alu, 75) + dut.io.queryRows(0).sources(0).ready.expect(true.B) + dut.io.queryRows(0).sources(1).ready.expect(true.B) + dut.io.queryRows(0).sources(2).ready.expect(true.B) + + pokeDispatch(dut, channel.bits, transactionId = 76, + uopClass = UopClass.Alu, sourceReady = false) + channel.bits.uop.sources(0).ptag.poke(physical.pPhysRegs.U) + configureLocalSource(channel.bits.uop.sources(1), OperandKind.T, + tag = physical.tPhysRegs, sequenceIndex = 5, + sequenceGeneration = 6) + configureLocalSource(channel.bits.uop.sources(2), OperandKind.U, + tag = physical.uPhysRegs, sequenceIndex = 7, + sequenceGeneration = 8) + dut.io.operandReadyBits.ptag(0).valid.poke(true.B) + dut.io.operandReadyBits.ptag(0).ready.poke(true.B) + dut.io.operandReadyBits.ptag(0).stid.poke(0.U) + dut.io.operandReadyBits.ptag(0).epoch.poke(7.U) + dut.io.operandReadyBits.ptag(0).generation.poke(9.U) + configureLocalReady(dut.io.operandReadyBits.ttag(0)(0), + sequenceIndex = 5, sequenceGeneration = 6) + configureLocalReady(dut.io.operandReadyBits.utag(0)(0), + sequenceIndex = 7, sequenceGeneration = 8) + channel.valid.poke(true.B) + accept(channel, dut) + findResidentByTransaction(dut, OooUopClass.Alu, 76) + dut.io.queryRows(0).sources(0).ready.expect(false.B) + dut.io.queryRows(0).sources(1).ready.expect(false.B) + dut.io.queryRows(0).sources(2).ready.expect(false.B) + } + } + + test("retains the precise decode trap without reconstructing it") { + simulate(new OooIexIssue(core)) { dut => + clearControls(dut) + val channel = dut.io.dispatch.aluDispatch(0) + pokeDispatch(dut, channel.bits, transactionId = 83, + uopClass = UopClass.Alu, trapValid = true, trapCause = 0x2d) + channel.valid.poke(true.B) + accept(channel, dut) + + findResident(dut, OooUopClass.Alu) + dut.io.queryRows(0).preciseTrap.expect(true.B) + dut.io.queryRows(0).trapCause.expect(0x2d.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXPrivateTerminalSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXPrivateTerminalSpec.scala new file mode 100644 index 00000000..a208daf8 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXPrivateTerminalSpec.scala @@ -0,0 +1,846 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.common.DestinationKind +import linxcore.ooo._ +import linxcore.params.{CoreParams, SimulationParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class IEXPrivateTerminalSpec extends AnyFunSuite with ChiselSim { + private val core: CoreParams = SimulationParamProfiles.W4 + + private def pokeMember( + target: RobMemberKey, + ridSlot: Int = 2, + memberIndex: Int = 0): Unit = { + target.poke(0.U.asTypeOf(target)) + target.group.valid.poke(true.B) + target.group.peId.poke(3.U) + target.group.stid.poke(0.U) + target.group.ridSlot.poke(ridSlot.U) + target.group.ridGeneration.poke(5.U) + target.bid.valid.poke(true.B) + target.bid.value.poke(2.U) + target.brobGeneration.poke(7.U) + target.memberIndex.poke(memberIndex.U) + target.residentGeneration.poke(8.U) + } + + private def pokeRob( + target: RobIdentity, + ridSlot: Int = 2, + memberIndex: Int = 0): Unit = { + target.poke(0.U.asTypeOf(target)) + target.peId.poke(3.U) + target.stid.poke(0.U) + target.ridSlot.poke(ridSlot.U) + target.ridGeneration.poke(5.U) + target.memberIndex.poke(memberIndex.U) + target.residentGeneration.poke(8.U) + target.bid.poke(2.U) + target.brobGeneration.poke(7.U) + } + + private def expectRob( + target: RobIdentity, + ridSlot: Int = 2, + memberIndex: Int = 0): Unit = { + target.peId.expect(3.U) + target.stid.expect(0.U) + target.ridSlot.expect(ridSlot.U) + target.ridGeneration.expect(5.U) + target.memberIndex.expect(memberIndex.U) + target.residentGeneration.expect(8.U) + target.bid.expect(2.U) + target.brobGeneration.expect(7.U) + } + + private def expectInstruction(target: InstructionIdentity): Unit = { + target.peId.expect(3.U) + target.stid.expect(0.U) + target.instructionId.expect(91.U) + target.epoch.expect(11.U) + } + + private def pokeDestination( + target: OooIexDestinationState, + kind: DestinationKind.Type, + ordinal: Int): Unit = { + target.poke(0.U.asTypeOf(target)) + target.valid.poke(true.B) + target.kind.poke(kind) + target.atag.poke((4 + ordinal).U) + target.ptag.poke((30 + ordinal).U) + target.ptagGeneration.poke(9.U) + target.localTag.poke((4 + ordinal).U) + target.localSequence.valid.poke(true.B) + target.localSequence.index.poke((4 + ordinal).U) + target.localSequence.generation.poke(13.U) + } + + private def pokeExecute( + execute: OooIexExecuteTransaction, + owner: OooUopClass.Type, + dispatchClass: Int, + sideEffectOwner: Int, + destinations: Seq[DestinationKind.Type], + ridSlot: Int = 2): Unit = { + execute.poke(0.U.asTypeOf(execute)) + execute.ownerClass.poke(owner) + val row = execute.i2.row.schedule + row.valid.poke(true.B) + row.peId.poke(3.U) + row.stid.poke(0.U) + row.epoch.poke(11.U) + row.transactionId.poke(43.U) + pokeMember(row.member, ridSlot) + row.reservation.valid.poke(true.B) + row.reservation.uopClass.poke(owner) + + val payload = execute.i2.row.payload + payload.opcode.poke(0x51.U) + payload.recipe.valid.poke(true.B) + payload.recipe.opcode.poke(0x51.U) + payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + payload.recipe.dispatchClass.poke(dispatchClass.U) + payload.recipe.sideEffectOwner.poke(sideEffectOwner.U) + payload.uopKey.primaryParent.valid.poke(true.B) + payload.uopKey.primaryParent.peId.poke(3.U) + payload.uopKey.primaryParent.stid.poke(0.U) + payload.uopKey.primaryParent.instructionId.poke(91.U) + payload.uopKey.uopCount.poke(1.U) + destinations.zipWithIndex.foreach { case (kind, ordinal) => + pokeDestination(row.destinations(ordinal), kind, ordinal) + } + } + + private def pokeAlu( + dut: OooIexTerminalPublish, + destinations: Seq[DestinationKind.Type] = Seq(DestinationKind.Gpr), + values: Seq[BigInt] = Seq(BigInt(0x100))): Unit = { + val terminal = dut.io.alu.bits + terminal.poke(0.U.asTypeOf(terminal)) + pokeExecute( + terminal.execute, + OooUopClass.Alu, + OooDispatchClass.Alu, + OooSideEffectOwner.Iex, + destinations) + destinations.zip(values).zipWithIndex.foreach { + case ((kind, value), ordinal) => + terminal.writebacks(ordinal).valid.poke(true.B) + pokeDestination(terminal.writebacks(ordinal).destination, kind, ordinal) + terminal.writebacks(ordinal).data.poke(value.U) + } + dut.io.alu.valid.poke(true.B) + } + + private def pokeNoDestinationBru(dut: OooIexTerminalPublish): Unit = { + val terminal = dut.io.bru.bits + terminal.poke(0.U.asTypeOf(terminal)) + pokeExecute( + terminal.execute, + OooUopClass.Bru, + OooDispatchClass.Bru, + OooSideEffectOwner.Bctrl, + Seq.empty) + val prediction = terminal.execute.i2.row.payload.primaryPrediction + prediction.valid.poke(true.B) + prediction.predictionTag.poke(51.U) + prediction.transactionId.poke(52.U) + prediction.fetchPacketUid.poke(53.U) + prediction.fetchSeq.poke(54.U) + prediction.requestPc.poke(0x1000.U) + prediction.branchPc.poke(0x1010.U) + prediction.target.poke(0x1080.U) + prediction.fallthroughPc.poke(0x1020.U) + prediction.kind.poke(linxcore.common.BoundaryKind.Cond) + prediction.checkpointId.poke(1.U) + prediction.epoch.poke(11.U) + terminal.bctrl.valid.poke(true.B) + terminal.bctrl.kind.poke(OooIexBctrlUpdateKind.Condition) + terminal.bctrl.condition.poke(true.B) + dut.io.bru.valid.poke(true.B) + } + + private def pokeTrapLoad(dut: OooIexTerminalPublish): Unit = { + val result = dut.io.load.bits + result.poke(0.U.asTypeOf(result)) + pokeExecute( + result.agu.execute, + OooUopClass.Agu, + OooDispatchClass.Agu, + OooSideEffectOwner.Lsu, + Seq(DestinationKind.Gpr), + ridSlot = 2) + pokeDestination(result.agu.destination, DestinationKind.Gpr, 0) + result.load.valid.poke(true.B) + pokeMember(result.load.producer, ridSlot = 2) + result.load.generation.poke(17.U) + result.data.poke(0x5555.U) + result.faultValid.poke(true.B) + result.faultCause.poke(23.U) + dut.io.load.valid.poke(true.B) + } + + private def pokePlan( + target: RecoveryPlan, + phase: RecoveryPhase.Type, + transactionId: BigInt = 70, + redirectPc: BigInt = 0x8000, + newEpoch: Int = 12): Unit = { + target.poke(0.U.asTypeOf(target)) + target.transactionId.poke(transactionId.U) + target.phase.poke(phase) + target.cause.poke(RecoveryCause.Exception) + pokeRob(target.trigger, ridSlot = 1) + target.survivingTailValid.poke(true.B) + pokeRob(target.survivingTail, ridSlot = 1) + target.redirectPc.poke(redirectPc.U) + target.newEpoch.poke(newEpoch.U) + target.firstKilledValid.poke(true.B) + pokeRob(target.firstKilled, ridSlot = 2) + pokeRob(target.lastKilled, ridSlot = 2) + target.killedGroupCount.poke(1.U) + target.killedMemberCount.poke(1.U) + } + + private def expectPlan( + target: RecoveryPlan, + phase: RecoveryPhase.Type, + transactionId: BigInt = 70, + redirectPc: BigInt = 0x8000, + newEpoch: Int = 12): Unit = { + target.transactionId.expect(transactionId.U) + target.phase.expect(phase) + target.cause.expect(RecoveryCause.Exception) + expectRob(target.trigger, ridSlot = 1) + target.survivingTailValid.expect(true.B) + expectRob(target.survivingTail, ridSlot = 1) + target.redirectPc.expect(redirectPc.U) + target.newEpoch.expect(newEpoch.U) + target.firstKilledValid.expect(true.B) + expectRob(target.firstKilled, ridSlot = 2) + expectRob(target.lastKilled, ridSlot = 2) + target.killedGroupCount.expect(1.U) + target.killedMemberCount.expect(1.U) + } + + private def clear(dut: OooIexTerminalPublish): Unit = { + dut.io.alu.valid.poke(false.B) + dut.io.alu.bits.poke(0.U.asTypeOf(dut.io.alu.bits)) + dut.io.bru.valid.poke(false.B) + dut.io.bru.bits.poke(0.U.asTypeOf(dut.io.bru.bits)) + dut.io.load.valid.poke(false.B) + dut.io.load.bits.poke(0.U.asTypeOf(dut.io.load.bits)) + dut.io.pWrite.foreach(_.ready.poke(true.B)) + dut.io.tWrite.foreach(_.ready.poke(true.B)) + dut.io.uWrite.foreach(_.ready.poke(true.B)) + dut.io.wakeup.foreach(_.ready.poke(true.B)) + dut.io.bctrl.ready.poke(true.B) + dut.io.trace.ready.poke(true.B) + dut.io.robResolve.ready.poke(true.B) + dut.io.recoveryEvent.ready.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def resetAndClear(dut: OooIexTerminalPublish): Unit = { + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + } + + private def clearSystemCmd(dut: OooIexSystemCmdTerminal): Unit = { + dut.io.system.foreach { source => + source.valid.poke(false.B) + source.bits.poke(0.U.asTypeOf(source.bits)) + } + dut.io.cmd.foreach { source => + source.valid.poke(false.B) + source.bits.poke(0.U.asTypeOf(source.bits)) + } + dut.io.robNoflushReady.ready.poke(false.B) + dut.io.robNoflush.valid.poke(false.B) + dut.io.robNoflush.bits.poke(0.U.asTypeOf(dut.io.robNoflush.bits)) + dut.io.systemIssue.foreach(_.ready.poke(true.B)) + dut.io.cmdIssue.ready.poke(true.B) + dut.io.robResolve.ready.poke(true.B) + dut.io.trace.ready.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def resetAndClearSystemCmd(dut: OooIexSystemCmdTerminal): Unit = { + clearSystemCmd(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + } + + private def pokeSystem(dut: OooIexSystemCmdTerminal): Unit = { + val execute = dut.io.system.head.bits + pokeExecute( + execute, + OooUopClass.Sys, + OooDispatchClass.Sys, + OooSideEffectOwner.Commit, + Seq.empty) + execute.i2.row.payload.immediateValid.poke(true.B) + execute.i2.row.payload.immediate.poke(0x1234.U) + dut.io.system.head.valid.poke(true.B) + } + + private def pokeCmd(dut: OooIexSystemCmdTerminal): Unit = { + val execute = dut.io.cmd.head.bits + pokeExecute( + execute, + OooUopClass.Cmd, + OooDispatchClass.Cmd, + OooSideEffectOwner.Commit, + Seq.empty) + execute.i2.sourceMask.poke("b011".U) + execute.i2.row.sources(0).valid.poke(true.B) + execute.i2.row.sources(1).valid.poke(true.B) + execute.i2.sourceData(0).poke(0x1111.U) + execute.i2.sourceData(1).poke(0x2222.U) + dut.io.cmd.head.valid.poke(true.B) + } + + private def pokePermit( + dut: OooIexSystemCmdTerminal, + transactionId: BigInt = 43, + ridSlot: Int = 2): Unit = { + dut.io.robNoflush.bits.poke(0.U.asTypeOf(dut.io.robNoflush.bits)) + dut.io.robNoflush.bits.transactionId.poke(transactionId.U) + dut.io.robNoflush.bits.instruction.peId.poke(3.U) + dut.io.robNoflush.bits.instruction.stid.poke(0.U) + dut.io.robNoflush.bits.instruction.instructionId.poke(91.U) + dut.io.robNoflush.bits.instruction.epoch.poke(11.U) + pokeRob(dut.io.robNoflush.bits.rob, ridSlot) + dut.io.robNoflush.valid.poke(true.B) + } + + test("publishes destination ordinal zero while every destination fires atomically") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu( + dut, + Seq(DestinationKind.T, DestinationKind.U), + Seq(BigInt(0x1111), BigInt(0x2222))) + + dut.io.robResolve.valid.expect(true.B) + dut.io.robResolve.bits.transactionId.expect(43.U) + expectRob(dut.io.robResolve.bits.rob) + dut.io.robResolve.bits.destinationValid.expect(true.B) + dut.io.robResolve.bits.destinationIndex.expect(0.U) + dut.io.robResolve.bits.value.expect(0x1111.U) + dut.io.robResolve.bits.trap.valid.expect(false.B) + dut.io.tWrite(0).valid.expect(true.B) + dut.io.uWrite(1).valid.expect(true.B) + dut.io.wakeup(0).valid.expect(true.B) + dut.io.wakeup(1).valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.recoveryEvent.valid.expect(false.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("publishes zero destination fields for a resolved no-destination member") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeNoDestinationBru(dut) + + dut.io.robResolve.valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.source.expect(OooIexTerminalSource.Bru) + dut.io.trace.bits.member.group.peId.expect(3.U) + dut.io.trace.bits.member.group.stid.expect(0.U) + dut.io.trace.bits.member.group.ridSlot.expect(2.U) + dut.io.trace.bits.member.bid.value.expect(2.U) + dut.io.trace.bits.member.brobGeneration.expect(7.U) + dut.io.robResolve.bits.destinationValid.expect(false.B) + dut.io.robResolve.bits.destinationIndex.expect(0.U) + dut.io.robResolve.bits.value.expect(0.U) + dut.io.pWrite.foreach(_.valid.expect(false.B)) + dut.io.tWrite.foreach(_.valid.expect(false.B)) + dut.io.uWrite.foreach(_.valid.expect(false.B)) + dut.io.wakeup.foreach(_.valid.expect(false.B)) + dut.io.bctrl.valid.expect(true.B) + dut.io.bctrl.bits.transactionId.expect(43.U) + dut.io.bctrl.bits.prediction.predictionTag.expect(51.U) + dut.io.bctrl.bits.prediction.fetchPacketUid.expect(53.U) + dut.io.bctrl.bits.prediction.fetchSeq.expect(54.U) + dut.io.bctrl.bits.prediction.branchPc.expect(0x1010.U) + dut.io.recoveryEvent.valid.expect(false.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("does not let an unused recovery-event sink block an ordinary resolve") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.recoveryEvent.ready.poke(false.B) + + dut.io.recoveryEvent.valid.expect(false.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.pWrite(0).valid.expect(true.B) + dut.io.wakeup(0).valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("holds RF wakeup trace and resolve until one ordinary terminal fire") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.robResolve.ready.poke(false.B) + + dut.io.alu.ready.expect(false.B) + dut.io.pWrite(0).valid.expect(false.B) + dut.io.wakeup(0).valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + + dut.io.robResolve.ready.poke(true.B) + dut.io.alu.ready.expect(true.B) + dut.io.pWrite(0).valid.expect(true.B) + dut.io.wakeup(0).valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("suppresses RF and wakeup for a trap and emits the exact trap recovery event") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeTrapLoad(dut) + + dut.io.pWrite.foreach(_.valid.expect(false.B)) + dut.io.tWrite.foreach(_.valid.expect(false.B)) + dut.io.uWrite.foreach(_.valid.expect(false.B)) + dut.io.wakeup.foreach(_.valid.expect(false.B)) + dut.io.robResolve.valid.expect(true.B) + dut.io.robResolve.bits.transactionId.expect(43.U) + expectRob(dut.io.robResolve.bits.rob) + dut.io.robResolve.bits.destinationValid.expect(false.B) + dut.io.robResolve.bits.destinationIndex.expect(0.U) + dut.io.robResolve.bits.value.expect(0.U) + dut.io.robResolve.bits.trap.valid.expect(true.B) + dut.io.robResolve.bits.trap.kind.expect(TrapKind.Exception) + expectInstruction(dut.io.robResolve.bits.trap.instruction) + expectRob(dut.io.robResolve.bits.trap.rob) + dut.io.robResolve.bits.trap.cause.expect(23.U) + dut.io.robResolve.bits.trap.targetPc.expect(0.U) + dut.io.robResolve.bits.trap.tval.expect(0.U) + + dut.io.recoveryEvent.valid.expect(true.B) + dut.io.recoveryEvent.bits.transactionId.expect(43.U) + dut.io.recoveryEvent.bits.cause.expect(RecoveryCause.Exception) + expectRob(dut.io.recoveryEvent.bits.trigger) + expectInstruction(dut.io.recoveryEvent.bits.instruction) + dut.io.recoveryEvent.bits.redirectPc.expect(0.U) + dut.io.recoveryEvent.bits.trap.valid.expect(true.B) + dut.io.recoveryEvent.bits.trap.kind.expect(TrapKind.Exception) + expectInstruction(dut.io.recoveryEvent.bits.trap.instruction) + expectRob(dut.io.recoveryEvent.bits.trap.rob) + dut.io.recoveryEvent.bits.trap.cause.expect(23.U) + dut.io.recoveryEvent.bits.trap.targetPc.expect(0.U) + dut.io.recoveryEvent.bits.trap.tval.expect(0.U) + dut.io.terminalFire.expect(true.B) + } + } + + test("holds trap trace resolve and recovery event until one terminal fire") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeTrapLoad(dut) + dut.io.recoveryEvent.ready.poke(false.B) + + dut.io.load.ready.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + + dut.io.recoveryEvent.ready.poke(true.B) + dut.io.load.ready.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.recoveryEvent.valid.expect(true.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("returns the complete canonical recovery plan during prepare without mutation") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.robResolve.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + + dut.io.recovery.prepare.ready.expect(true.B) + dut.io.recovery.prepared.valid.expect(true.B) + expectPlan(dut.io.recovery.prepared.bits, RecoveryPhase.Prepare) + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + } + } + + test("preserves a held terminal transaction after matching recovery abort") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.robResolve.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + dut.io.recovery.prepared.valid.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.abort.valid.poke(true.B) + pokePlan(dut.io.recovery.abort.bits, RecoveryPhase.Abort) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + dut.io.robResolve.ready.poke(true.B) + + dut.io.alu.ready.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.source.expect(OooIexTerminalSource.Cmd) + dut.io.terminalFire.expect(true.B) + } + } + + test("keeps a held terminal fenced after nonmatching apply until matching abort") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.robResolve.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + dut.io.recovery.prepared.valid.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(true.B) + pokePlan( + dut.io.recovery.apply.bits, + RecoveryPhase.Apply, + redirectPc = 0x9000, + newEpoch = 13) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.robResolve.ready.poke(true.B) + + dut.io.alu.ready.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + + dut.io.robResolve.ready.poke(false.B) + dut.io.recovery.abort.valid.poke(true.B) + pokePlan(dut.io.recovery.abort.bits, RecoveryPhase.Abort) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + dut.io.robResolve.ready.poke(true.B) + + dut.io.alu.ready.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("never resolves a terminal transaction killed by the matching recovery apply") { + simulate(new OooIexTerminalPublish(core)) { dut => + resetAndClear(dut) + pokeAlu(dut) + dut.io.robResolve.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + dut.io.recovery.prepared.valid.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(true.B) + pokePlan(dut.io.recovery.apply.bits, RecoveryPhase.Apply) + + dut.io.alu.ready.expect(true.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.pWrite.foreach(_.valid.expect(false.B)) + dut.io.wakeup.foreach(_.valid.expect(false.B)) + dut.io.trace.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.alu.valid.poke(false.B) + dut.io.robResolve.ready.poke(true.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.recoveryEvent.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + } + } + + test("fires one head-authorized system side effect and no-value resolve atomically") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeSystem(dut) + + dut.io.system.head.ready.expect(false.B) + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.robNoflushReady.bits.transactionId.expect(43.U) + expectInstruction(dut.io.robNoflushReady.bits.instruction) + expectRob(dut.io.robNoflushReady.bits.rob) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + + pokePermit(dut) + dut.io.robNoflushReady.ready.poke(true.B) + dut.io.robNoflush.ready.expect(true.B) + dut.io.system.head.ready.expect(true.B) + dut.io.systemIssue.head.valid.expect(true.B) + dut.io.systemIssue.head.bits.transactionId.expect(43.U) + dut.io.systemIssue.head.bits.opcode.expect(0x51.U) + dut.io.systemIssue.head.bits.immediate.expect(0x1234.U) + dut.io.cmdIssue.valid.expect(false.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.robResolve.bits.destinationValid.expect(false.B) + dut.io.robResolve.bits.destinationIndex.expect(0.U) + dut.io.robResolve.bits.value.expect(0.U) + dut.io.robResolve.bits.trap.valid.expect(false.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("holds CMD permit issue and resolve while the external sink is blocked") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeCmd(dut) + pokePermit(dut) + dut.io.cmdIssue.ready.poke(false.B) + + dut.io.robNoflush.ready.expect(false.B) + dut.io.cmd.head.ready.expect(false.B) + dut.io.cmdIssue.valid.expect(true.B) + val held = dut.io.cmdIssue.bits.peek() + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + dut.clock.step(2) + dut.io.cmdIssue.valid.expect(true.B) + dut.io.cmdIssue.bits.expect(held) + + dut.io.cmdIssue.ready.poke(true.B) + dut.io.robNoflushReady.ready.poke(true.B) + dut.io.robNoflush.ready.expect(true.B) + dut.io.cmd.head.ready.expect(true.B) + dut.io.cmdIssue.valid.expect(true.B) + dut.io.cmdIssue.bits.sourceValid.expect("b011".U) + dut.io.cmdIssue.bits.sourceValues(0).expect(0x1111.U) + dut.io.cmdIssue.bits.sourceValues(1).expect(0x2222.U) + dut.io.robResolve.valid.expect(true.B) + dut.io.terminalFire.expect(true.B) + } + } + + test("a waiting CMD publishes its proof after an older System fires") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeSystem(dut) + pokeCmd(dut) + pokeMember(dut.io.cmd.head.bits.i2.row.schedule.member, ridSlot = 3) + + dut.io.robNoflushReady.ready.poke(true.B) + dut.io.robNoflushReady.valid.expect(true.B) + expectRob(dut.io.robNoflushReady.bits.rob, ridSlot = 2) + pokePermit(dut) + dut.io.system.head.ready.expect(true.B) + dut.io.cmd.head.ready.expect(false.B) + dut.io.systemIssue.head.valid.expect(true.B) + dut.io.cmdIssue.valid.expect(false.B) + dut.clock.step() + + dut.io.system.head.valid.poke(false.B) + dut.io.robNoflush.valid.poke(false.B) + dut.io.robNoflushReady.valid.expect(true.B) + expectRob(dut.io.robNoflushReady.bits.rob, ridSlot = 3) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.cmdIssue.valid.expect(false.B) + + pokePermit(dut, ridSlot = 3) + dut.io.cmd.head.ready.expect(true.B) + dut.io.cmdIssue.valid.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.source.expect(OooIexTerminalSource.Cmd) + dut.io.terminalFire.expect(true.B) + } + } + + test("System permit withdrawal and trace backpressure preserve one exact resident row") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeSystem(dut) + pokePermit(dut) + dut.io.trace.ready.poke(false.B) + dut.io.robNoflushReady.ready.poke(true.B) + dut.io.robNoflush.ready.expect(false.B) + dut.io.system.head.ready.expect(false.B) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.trace.valid.expect(true.B) + dut.io.terminalFire.expect(false.B) + dut.clock.step(2) + + dut.io.robNoflush.valid.poke(false.B) + dut.io.trace.ready.poke(true.B) + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.io.system.head.ready.expect(false.B) + dut.clock.step() + + pokePermit(dut, transactionId = 44) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.io.system.head.ready.expect(false.B) + + pokePermit(dut) + dut.io.systemIssue.head.valid.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.trace.valid.expect(true.B) + dut.io.system.head.ready.expect(true.B) + dut.io.terminalFire.expect(true.B) + dut.clock.step() + dut.io.system.head.valid.poke(false.B) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + } + } + + test("fails closed on a destination-producing system row and a stale permit") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeSystem(dut) + pokeDestination( + dut.io.system.head.bits.i2.row.destinations(0), + DestinationKind.Gpr, + 0) + dut.io.robNoflushReady.valid.expect(false.B) + dut.io.system.head.ready.expect(false.B) + dut.io.systemIssue.head.valid.expect(false.B) + + dut.io.system.head.bits.i2.row.destinations(0).valid.poke(false.B) + pokePermit(dut, transactionId = 44) + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.robNoflush.ready.expect(false.B) + dut.io.systemIssue.head.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + } + } + + test("fences a killed system row from prepare through nonmatching apply and resumes on abort") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeSystem(dut) + dut.io.recovery.prepared.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + + dut.io.robNoflushReady.valid.expect(false.B) + dut.io.system.head.ready.expect(false.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + expectPlan(dut.io.recovery.prepared.bits, RecoveryPhase.Prepare) + + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(true.B) + pokePlan( + dut.io.recovery.apply.bits, + RecoveryPhase.Apply, + redirectPc = 0x9000, + newEpoch = 13) + dut.io.robNoflushReady.valid.expect(false.B) + dut.io.system.head.ready.expect(false.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.robNoflushReady.valid.expect(false.B) + + dut.io.recovery.abort.valid.poke(true.B) + pokePlan(dut.io.recovery.abort.bits, RecoveryPhase.Abort) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.system.head.ready.expect(false.B) + } + } + + test("matching apply releases a killed CMD row without permit side effects") { + simulate(new OooIexSystemCmdTerminal(core)) { dut => + resetAndClearSystemCmd(dut) + pokeCmd(dut) + dut.io.recovery.prepared.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(true.B) + pokePlan(dut.io.recovery.apply.bits, RecoveryPhase.Apply) + + dut.io.cmd.head.ready.expect(true.B) + dut.io.robNoflushReady.valid.expect(false.B) + dut.io.robNoflush.ready.expect(false.B) + dut.io.cmdIssue.valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + } + } + + test("a peer STID command remains eligible during another STID recovery") { + val peerCore = core.copy(ooo = core.ooo.copy( + stidCount = 2, + pcBufferEntries = 8, + gprPhysRegs = 64)) + simulate(new OooIexSystemCmdTerminal(peerCore)) { dut => + resetAndClearSystemCmd(dut) + pokeCmd(dut) + val execute = dut.io.cmd.head.bits + execute.i2.row.stid.poke(1.U) + execute.i2.row.member.group.stid.poke(1.U) + execute.i2.row.uopKey.primaryParent.stid.poke(1.U) + dut.io.recovery.prepare.valid.poke(true.B) + pokePlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare) + + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.robNoflushReady.bits.instruction.stid.expect(1.U) + dut.io.robNoflushReady.bits.rob.stid.expect(1.U) + dut.io.cmd.head.ready.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXTerminalSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXTerminalSpec.scala new file mode 100644 index 00000000..efd24c54 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXTerminalSpec.scala @@ -0,0 +1,16 @@ +package linxcore.iex + +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class IEXTerminalSpec extends AnyFunSuite { + test("public IEX retains one atomic typed terminal owner") { + val chirrtl = ChiselStage.emitCHIRRTL(new IEX(SimulationParamProfiles.W4)) + assert(chirrtl.contains("module OooIexTerminalFabric")) + assert(chirrtl.contains("module OooIexTerminalPublish")) + assert(chirrtl.contains("robResolve")) + assert(chirrtl.contains("recoveryEvent")) + assert(chirrtl.contains("cmdIssue")) + } +} diff --git a/chisel/src/test/scala/linxcore/iex/IEXTerminalTraceIndependenceSpec.scala b/chisel/src/test/scala/linxcore/iex/IEXTerminalTraceIndependenceSpec.scala new file mode 100644 index 00000000..366d17f8 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/IEXTerminalTraceIndependenceSpec.scala @@ -0,0 +1,124 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.common.DestinationKind +import linxcore.ooo._ +import linxcore.params.{CoreParams, SimulationParamProfiles} +import org.scalatest.funsuite.AnyFunSuite + +class IEXTerminalTraceIndependenceSpec extends AnyFunSuite with ChiselSim { + private val core: CoreParams = SimulationParamProfiles.W4 + + private def initialize(dut: OooIexTerminalPublish): Unit = { + dut.io.alu.valid.poke(false.B) + dut.io.alu.bits.poke(0.U.asTypeOf(dut.io.alu.bits)) + dut.io.bru.valid.poke(false.B) + dut.io.bru.bits.poke(0.U.asTypeOf(dut.io.bru.bits)) + dut.io.load.valid.poke(false.B) + dut.io.load.bits.poke(0.U.asTypeOf(dut.io.load.bits)) + dut.io.pWrite.foreach(_.ready.poke(true.B)) + dut.io.tWrite.foreach(_.ready.poke(true.B)) + dut.io.uWrite.foreach(_.ready.poke(true.B)) + dut.io.wakeup.foreach(_.ready.poke(true.B)) + dut.io.bctrl.ready.poke(true.B) + dut.io.trace.ready.poke(false.B) + dut.io.robResolve.ready.poke(true.B) + dut.io.recoveryEvent.ready.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + } + + private def pokeDestination(target: OooIexDestinationState): Unit = { + target.poke(0.U.asTypeOf(target)) + target.valid.poke(true.B) + target.kind.poke(DestinationKind.Gpr) + target.atag.poke(4.U) + target.ptag.poke(30.U) + target.ptagGeneration.poke(9.U) + } + + private def pokeAlu(dut: OooIexTerminalPublish): Unit = { + val terminal = dut.io.alu.bits + terminal.poke(0.U.asTypeOf(terminal)) + val execute = terminal.execute + execute.ownerClass.poke(OooUopClass.Alu) + val row = execute.i2.row.schedule + row.valid.poke(true.B) + row.peId.poke(3.U) + row.stid.poke(0.U) + row.epoch.poke(11.U) + row.transactionId.poke(43.U) + row.member.group.valid.poke(true.B) + row.member.group.peId.poke(3.U) + row.member.group.stid.poke(0.U) + row.member.group.ridSlot.poke(2.U) + row.member.group.ridGeneration.poke(5.U) + row.member.bid.valid.poke(true.B) + row.member.bid.value.poke(2.U) + row.member.brobGeneration.poke(7.U) + row.member.memberIndex.poke(0.U) + row.member.residentGeneration.poke(8.U) + row.reservation.valid.poke(true.B) + row.reservation.uopClass.poke(OooUopClass.Alu) + pokeDestination(row.destinations(0)) + + val payload = execute.i2.row.payload + payload.opcode.poke(0x51.U) + payload.recipe.valid.poke(true.B) + payload.recipe.opcode.poke(0x51.U) + payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + payload.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) + payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) + payload.uopKey.primaryParent.valid.poke(true.B) + payload.uopKey.primaryParent.peId.poke(3.U) + payload.uopKey.primaryParent.stid.poke(0.U) + payload.uopKey.primaryParent.instructionId.poke(91.U) + payload.uopKey.uopCount.poke(1.U) + + terminal.writebacks(0).valid.poke(true.B) + pokeDestination(terminal.writebacks(0).destination) + terminal.writebacks(0).data.poke(0x1234.U) + dut.io.alu.valid.poke(true.B) + } + + test("trace backpressure cannot stall or duplicate architectural publication") { + simulate(new OooIexTerminalPublish(core)) { dut => + initialize(dut) + pokeAlu(dut) + + dut.io.alu.ready.expect(true.B) + dut.io.pWrite(0).valid.expect(true.B) + dut.io.pWrite(0).bits.data.expect(0x1234.U) + dut.io.wakeup(0).valid.expect(true.B) + dut.io.robResolve.valid.expect(true.B) + dut.io.robResolve.bits.transactionId.expect(43.U) + dut.io.terminalFire.expect(true.B) + dut.io.architecturalAccepted.valid.expect(true.B) + dut.io.architecturalAccepted.bits.transactionId.expect(43.U) + dut.io.trace.valid.expect(true.B) + dut.io.trace.ready.expect(false.B) + dut.clock.step() + + dut.io.alu.valid.poke(false.B) + for (_ <- 0 until 3) { + dut.io.pWrite(0).valid.expect(false.B) + dut.io.wakeup(0).valid.expect(false.B) + dut.io.robResolve.valid.expect(false.B) + dut.io.terminalFire.expect(false.B) + dut.io.architecturalAccepted.valid.expect(false.B) + dut.io.trace.valid.expect(false.B) + dut.clock.step() + } + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala b/chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala new file mode 100644 index 00000000..513d02cb --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala @@ -0,0 +1,458 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +import linxcore.common.{CoreParams, DestinationKind, ScalarLsuParams} +import linxcore.ooo._ +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} + +class LoadIexIssuePipelineSpec extends AnyFunSuite with ChiselSim { + private val p = OooParams( + stidCount = 4, + instructionDecodeWidth = 2, + decodedUopWidth = 2, + renameWidth = 2, + dispatchWidth = 2, + retireGroupWidth = 2, + robGroupsPerStid = 8, + robBankCount = 2, + robRecoveryScanGroupsPerCycle = 2, + robNonFlushScanGroupsPerCycle = 2, + brobEntriesPerStid = 16, + pcBufferEntries = 16, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 2, + pcWritePorts = 3, + iqBankCount = 2, + iqEntriesPerBank = 4, + iqFreeSelectLeafEntries = 2, + tuRetireSourceDepthPerStid = 16, + lsidWidth = 40) + + private val core = CoreParams( + robEntries = 8, + lsidWidth = 40, + scalarLsu = ScalarLsuParams( + stqEntries = 4, + liqEntries = 4, + loadReturnPipeCount = 3, + stidCount = 4)) + + test("derives the W4 two-lane issue geometry from the canonical LSU profile") { + val twoPipeCore = core.copy( + scalarLsu = core.scalarLsu.copy(loadReturnPipeCount = 2)) + + simulate(new LoadIexIssuePipeline(p, twoPipeCore)) { dut => + assert(dut.io.agu.length == 2) + assert(dut.io.rejected.length == 2) + } + } + + private def clear(dut: LoadIexIssuePipeline): Unit = { + dut.io.agu.foreach { lane => + lane.valid.poke(false.B) + lane.bits.poke(0.U.asTypeOf(lane.bits)) + } + dut.io.alloc.ready.poke(false.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def pokeRecoveryPlan( + plan: RecoveryPlan, + phase: RecoveryPhase.Type, + transactionId: Int, + stid: Int, + firstRid: Int, + lastRid: Int): Unit = { + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(transactionId.U) + plan.phase.poke(phase) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(stid.U) + plan.trigger.ridSlot.poke(firstRid.U) + plan.trigger.ridGeneration.poke(5.U) + plan.trigger.memberIndex.poke(1.U) + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(stid.U) + plan.firstKilled.ridSlot.poke(firstRid.U) + plan.firstKilled.ridGeneration.poke(5.U) + plan.firstKilled.memberIndex.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(stid.U) + plan.lastKilled.ridSlot.poke(lastRid.U) + plan.lastKilled.ridGeneration.poke(5.U) + plan.lastKilled.memberIndex.poke(1.U) + plan.killedGroupCount.poke((lastRid - firstRid + 1).U) + plan.killedMemberCount.poke((lastRid - firstRid + 1).U) + } + + private def pokeRequest( + dut: LoadIexIssuePipeline, + lane: Int, + ridSlot: Int, + nativeBid: Int, + firstLsid: BigInt, + firstLoadId: BigInt, + storeTail: BigInt, + transactionValue: BigInt = 0, + transactionGeneration: BigInt = 0, + attemptGeneration: BigInt = 1, + pcValid: Boolean = true, + stid: Int = -1): Unit = { + val input = dut.io.agu(lane) + val requestStid = if (stid >= 0) stid else lane + 1 + val youngestStoreLsid = if (storeTail != 0) firstLsid - 3 else BigInt(0) + input.bits.poke(0.U.asTypeOf(input.bits)) + input.valid.poke(true.B) + input.bits.pcValid.poke(pcValid.B) + input.bits.pc.poke((0x4000 + ridSlot * 4).U) + input.bits.address.poke((0x8000 + ridSlot * 8).U) + input.bits.accessBytes.poke(8.U) + input.bits.signExtend.poke(true.B) + + val execute = input.bits.execute + execute.ownerClass.poke(OooUopClass.Agu) + val row = execute.i2.row + row.schedule.valid.poke(true.B) + row.schedule.peId.poke(3.U) + row.schedule.stid.poke(requestStid.U) + row.schedule.epoch.poke(7.U) + row.schedule.memoryTransactionValid.poke(true.B) + row.schedule.memoryTransaction.value.poke(transactionValue.U) + row.schedule.memoryTransaction.generation.poke(transactionGeneration.U) + row.schedule.initialLoadAttemptValid.poke(true.B) + row.schedule.initialLoadAttemptGeneration.poke(attemptGeneration.U) + row.schedule.member.group.valid.poke(true.B) + row.schedule.member.group.peId.poke(3.U) + row.schedule.member.group.stid.poke(requestStid.U) + row.schedule.member.group.ridSlot.poke(ridSlot.U) + row.schedule.member.group.ridGeneration.poke(5.U) + row.schedule.member.bid.valid.poke(true.B) + row.schedule.member.bid.value.poke(nativeBid.U) + row.schedule.member.brobGeneration.poke(9.U) + row.schedule.member.memberIndex.poke(1.U) + row.schedule.member.residentGeneration.poke(11.U) + row.schedule.reservation.valid.poke(true.B) + row.schedule.reservation.uopClass.poke(OooUopClass.Agu) + + row.payload.opcode.poke(101.U) + row.payload.recipe.valid.poke(true.B) + row.payload.recipe.opcode.poke(101.U) + row.payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + row.payload.recipe.recipeKind.poke(OooOpcodeRecipeKind.ScalarLoad.U) + row.payload.recipe.dispatchClass.poke(OooDispatchClass.Agu.U) + row.payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) + row.payload.recipe.memoryRequestCount.poke(1.U) + row.payload.memory.valid.poke(true.B) + row.payload.memory.isLoad.poke(true.B) + row.payload.memory.isStore.poke(false.B) + row.payload.memoryOrder.valid.poke(true.B) + row.payload.memoryOrder.memoryValid.poke(true.B) + row.payload.memoryOrder.isLoad.poke(true.B) + row.payload.memoryOrder.isStore.poke(false.B) + row.payload.memoryOrder.requestCount.poke(1.U) + row.payload.memoryOrder.firstLsid.poke(firstLsid.U) + row.payload.memoryOrder.firstTypeId.poke(firstLoadId.U) + row.payload.memoryOrder.before.lsid.poke(firstLsid.U) + row.payload.memoryOrder.before.loadId.poke(firstLoadId.U) + row.payload.memoryOrder.before.storeId.poke(storeTail.U) + row.payload.memoryOrder.before.youngestStoreLsidValid + .poke((storeTail != 0).B) + row.payload.memoryOrder.before.youngestStoreLsid + .poke(youngestStoreLsid.U) + row.payload.memoryOrder.after.lsid.poke((firstLsid + 1).U) + row.payload.memoryOrder.after.loadId.poke((firstLoadId + 1).U) + row.payload.memoryOrder.after.storeId.poke(storeTail.U) + row.payload.memoryOrder.after.youngestStoreLsidValid + .poke((storeTail != 0).B) + row.payload.memoryOrder.after.youngestStoreLsid + .poke(youngestStoreLsid.U) + + row.schedule.destinations(0).valid.poke(true.B) + row.schedule.destinations(0).kind.poke(DestinationKind.Gpr) + row.schedule.destinations(0).atag.poke(6.U) + row.schedule.destinations(0).ptag.poke((31 + lane).U) + row.schedule.destinations(0).ptagGeneration.poke(4.U) + row.payload.previousPDestinations(0).valid.poke(true.B) + row.payload.previousPDestinations(0).ptag.poke((21 + lane).U) + row.payload.previousPDestinations(0).ptagGeneration.poke(3.U) + input.bits.destination.valid.poke(true.B) + input.bits.destination.kind.poke(DestinationKind.Gpr) + input.bits.destination.atag.poke(6.U) + input.bits.destination.ptag.poke((31 + lane).U) + input.bits.destination.ptagGeneration.poke(4.U) + } + + test("maps the exact OOO producer and 40-bit memory order into one LIQ alloc") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + val lsid = BigInt("100000001", 16) + pokeRequest(dut, lane = 2, ridSlot = 6, nativeBid = 13, + firstLsid = lsid, firstLoadId = 9, storeTail = 4, + transactionValue = 0x1234, transactionGeneration = 7, + attemptGeneration = 9) + + dut.io.alloc.valid.expect(true.B) + dut.io.agu(2).ready.expect(false.B) + dut.io.accepted.valid.expect(false.B) + dut.io.alloc.bits.attempt.producer.nativeBid.expect(13.U) + dut.io.alloc.bits.attempt.producer.ridSlot.expect(6.U) + dut.io.alloc.bits.attempt.producer.ridGeneration.expect(5.U) + dut.io.alloc.bits.attempt.producer.memberIndex.expect(1.U) + dut.io.alloc.bits.attempt.producer.residentGeneration.expect(11.U) + dut.io.alloc.bits.attempt.generation.expect(9.U) + dut.io.accepted.bits.load.transaction.value.expect(0x1234.U) + dut.io.accepted.bits.load.transaction.generation.expect(7.U) + dut.clock.step(2) + dut.io.alloc.valid.expect(true.B) + dut.io.alloc.bits.attempt.generation.expect(9.U) + dut.io.accepted.bits.load.transaction.value.expect(0x1234.U) + dut.io.accepted.bits.load.transaction.generation.expect(7.U) + dut.io.alloc.bits.bid.valid.expect(true.B) + dut.io.alloc.bits.bid.value.expect(5.U) + dut.io.alloc.bits.bid.wrap.expect(true.B) + dut.io.alloc.bits.gid.valid.expect(true.B) + dut.io.alloc.bits.gid.value.expect(6.U) + dut.io.alloc.bits.gid.wrap.expect(true.B) + dut.io.alloc.bits.rid.valid.expect(true.B) + dut.io.alloc.bits.rid.value.expect(6.U) + dut.io.alloc.bits.rid.wrap.expect(true.B) + dut.io.alloc.bits.loadLsId.valid.expect(true.B) + dut.io.alloc.bits.loadLsId.value.expect(1.U) + dut.io.alloc.bits.loadLsId.wrap.expect(false.B) + dut.io.alloc.bits.loadLsIdFull.expect(lsid.U) + dut.io.alloc.bits.loadLsIdFullValid.expect(true.B) + dut.io.alloc.bits.youngestStoreId.valid.expect(true.B) + dut.io.alloc.bits.youngestStoreId.value.expect(3.U) + dut.io.alloc.bits.youngestStoreId.wrap.expect(false.B) + dut.io.alloc.bits.youngestStoreLsId.valid.expect(true.B) + dut.io.alloc.bits.youngestStoreLsId.value.expect(6.U) + dut.io.alloc.bits.youngestStoreLsId.wrap.expect(true.B) + dut.io.alloc.bits.youngestStoreLsIdFull.expect((lsid - 3).U) + dut.io.alloc.bits.youngestStoreLsIdFullValid.expect(true.B) + dut.io.alloc.bits.pc.expect((0x4000 + 6 * 4).U) + dut.io.alloc.bits.addr.expect((0x8000 + 6 * 8).U) + dut.io.alloc.bits.returnPipeIndex.expect(2.U) + dut.io.alloc.bits.dst.physTag.expect(33.U) + dut.io.alloc.bits.dst.oldPhysTag.expect(23.U) + dut.io.alloc.bits.specWakeup.expect(false.B) + + dut.io.alloc.ready.poke(true.B) + dut.io.agu(2).ready.expect(true.B) + dut.io.accepted.valid.expect(true.B) + dut.io.accepted.bits.lane.expect(2.U) + dut.io.accepted.bits.load.generation.expect(9.U) + dut.clock.step() + + dut.io.agu(2).valid.poke(false.B) + pokeRequest(dut, lane = 2, ridSlot = 7, nativeBid = 14, + firstLsid = lsid + 1, firstLoadId = 10, storeTail = 4, + transactionValue = 0x1235, transactionGeneration = 7, + attemptGeneration = 10) + dut.io.alloc.bits.attempt.generation.expect(10.U) + dut.io.accepted.bits.load.transaction.value.expect(0x1235.U) + dut.io.accepted.bits.load.transaction.generation.expect(7.U) + } + } + + test("maps a compact-load T destination into the canonical LIQ identity") { + val identityCore = core.copy(robEntries = math.max( + p.robIdentityGroupsPerStid, 1 << (p.nativeBidWidth - 1))) + simulate(new LoadIexIssuePipeline(p, identityCore)) { dut => + clear(dut) + pokeRequest(dut, lane = 0, ridSlot = 2, nativeBid = 4, + firstLsid = 7, firstLoadId = 5, storeTail = 0) + val row = dut.io.agu(0).bits.execute.i2.row + row.schedule.destinations(0).kind.poke(DestinationKind.T) + row.schedule.destinations(0).atag.poke(31.U) + row.schedule.destinations(0).relativeIndex.poke(2.U) + row.schedule.destinations(0).localTag.poke(3.U) + row.schedule.destinations(0).localSequence.valid.poke(true.B) + row.schedule.destinations(0).localSequence.index.poke(9.U) + row.schedule.destinations(0).localSequence.generation.poke(4.U) + row.payload.previousPDestinations(0).valid.poke(false.B) + dut.io.agu(0).bits.destination.poke( + row.schedule.destinations(0).peek()) + dut.io.alloc.ready.poke(true.B) + + dut.io.alloc.valid.expect(true.B) + dut.io.agu(0).ready.expect(true.B) + dut.io.alloc.bits.dst.kind.expect(DestinationKind.T) + dut.io.alloc.bits.dst.archTag.expect(31.U) + dut.io.alloc.bits.dst.relTag.expect(2.U) + dut.io.alloc.bits.dst.physTag.expect(3.U) + dut.io.alloc.bits.dst.oldPhysTag.expect(0.U) + } + } + + test("rejects a load without the retained IEX transaction or initial attempt") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + pokeRequest(dut, lane = 0, ridSlot = 1, nativeBid = 2, + firstLsid = 1, firstLoadId = 1, storeTail = 0) + dut.io.alloc.ready.poke(true.B) + + dut.io.agu(0).bits.execute.i2.row.schedule.memoryTransactionValid + .poke(false.B) + dut.io.alloc.valid.expect(false.B) + dut.io.rejected(0).valid.expect(true.B) + dut.io.rejected(0).bits.identityExact.expect(false.B) + + dut.io.agu(0).bits.execute.i2.row.schedule.memoryTransactionValid + .poke(true.B) + dut.io.agu(0).bits.execute.i2.row.schedule.initialLoadAttemptValid + .poke(false.B) + dut.io.alloc.valid.expect(false.B) + dut.io.rejected(0).valid.expect(true.B) + dut.io.rejected(0).bits.loadShapeExact.expect(false.B) + } + } + + test("arbitrates three retained AGUs fairly without adding residency") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + for (lane <- 0 until 3) { + pokeRequest(dut, lane, ridSlot = lane + 1, nativeBid = lane + 3, + firstLsid = 20 + lane, firstLoadId = 10 + lane, storeTail = 0, + transactionValue = lane, attemptGeneration = lane + 1) + } + dut.io.alloc.ready.poke(true.B) + + var accepted = Set.empty[Int] + for (_ <- 0 until 3) { + dut.io.accepted.valid.expect(true.B) + val lane = dut.io.accepted.bits.lane.peek().litValue.toInt + assert(!accepted.contains(lane), s"lane $lane granted twice") + accepted += lane + dut.io.alloc.bits.returnPipeIndex.expect(lane.U) + dut.clock.step() + dut.io.agu(lane).valid.poke(false.B) + } + assert(accepted == Set(0, 1, 2)) + dut.io.alloc.valid.expect(false.B) + } + } + + test("fails closed for missing PC") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + pokeRequest(dut, lane = 0, ridSlot = 1, nativeBid = 2, + firstLsid = 1, firstLoadId = 1, storeTail = 0, pcValid = false) + dut.io.alloc.ready.poke(true.B) + dut.io.alloc.valid.expect(false.B) + dut.io.agu(0).ready.expect(false.B) + dut.io.rejected(0).valid.expect(true.B) + dut.io.rejected(0).bits.pcExact.expect(false.B) + + pokeRequest(dut, lane = 0, ridSlot = 1, nativeBid = 2, + firstLsid = 1, firstLoadId = 1, storeTail = 0) + dut.io.alloc.valid.expect(true.B) + dut.io.alloc.bits.attempt.generation.expect(1.U) + dut.clock.step() + + dut.io.agu(0).valid.poke(false.B) + pokeRequest(dut, lane = 0, ridSlot = 2, nativeBid = 3, + firstLsid = 2, firstLoadId = 2, storeTail = 0, + transactionValue = 1, attemptGeneration = 2) + dut.io.alloc.bits.attempt.generation.expect(2.U) + } + } + + test("prepares without mutation fences only the target STID and lets peers progress") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + pokeRequest(dut, lane = 0, ridSlot = 2, nativeBid = 4, + firstLsid = 9, firstLoadId = 3, storeTail = 0) + pokeRequest(dut, lane = 1, ridSlot = 4, nativeBid = 6, + firstLsid = 11, firstLoadId = 5, storeTail = 0, + transactionValue = 1, attemptGeneration = 2) + dut.io.alloc.ready.poke(true.B) + pokeRecoveryPlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare, + transactionId = 17, stid = 1, firstRid = 2, lastRid = 3) + dut.io.recovery.prepare.valid.poke(true.B) + + dut.io.recovery.prepare.ready.expect(true.B) + dut.io.agu(0).ready.expect(false.B) + dut.io.alloc.valid.expect(true.B) + dut.io.accepted.bits.lane.expect(1.U) + dut.io.agu(1).ready.expect(true.B) + dut.clock.step() + + dut.io.agu(1).valid.poke(false.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.bits.transactionId.expect(17.U) + dut.io.recovery.prepared.bits.phase.expect(RecoveryPhase.Prepare) + dut.io.agu(0).ready.expect(false.B) + + pokeRecoveryPlan(dut.io.recovery.abort.bits, RecoveryPhase.Abort, + transactionId = 17, stid = 1, firstRid = 2, lastRid = 3) + dut.io.recovery.abort.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + + dut.io.alloc.valid.expect(true.B) + dut.io.agu(0).ready.expect(true.B) + // IEX allocated both identities before this bridge. Prepare and abort + // preserve the target request's original initial attempt exactly. + dut.io.alloc.bits.attempt.generation.expect(1.U) + } + } + + test("Apply drains only an exact suffix member without allocating or rewinding generation") { + simulate(new LoadIexIssuePipeline(p, core)) { dut => + clear(dut) + pokeRequest(dut, lane = 0, ridSlot = 2, nativeBid = 4, + firstLsid = 9, firstLoadId = 3, storeTail = 0, stid = 2) + pokeRequest(dut, lane = 1, ridSlot = 4, nativeBid = 6, + firstLsid = 10, firstLoadId = 4, storeTail = 0, + transactionValue = 1, attemptGeneration = 2, stid = 2) + dut.io.alloc.ready.poke(true.B) + pokeRecoveryPlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare, + transactionId = 23, stid = 2, firstRid = 2, lastRid = 3) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.alloc.valid.expect(false.B) + dut.io.agu(0).ready.expect(false.B) + dut.io.agu(1).ready.expect(false.B) + dut.io.accepted.valid.expect(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + dut.io.recovery.prepared.ready.poke(false.B) + + pokeRecoveryPlan(dut.io.recovery.apply.bits, RecoveryPhase.Apply, + transactionId = 23, stid = 2, firstRid = 2, lastRid = 3) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.alloc.valid.expect(false.B) + dut.io.accepted.valid.expect(false.B) + dut.io.agu(0).ready.expect(true.B) + dut.io.rejected(0).valid.expect(true.B) + dut.io.rejected(0).bits.killed.expect(true.B) + dut.io.agu(1).ready.expect(false.B) + dut.io.rejected(1).valid.expect(false.B) + dut.clock.step() + + dut.io.agu(0).valid.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.alloc.valid.expect(true.B) + dut.io.agu(1).ready.expect(true.B) + dut.io.alloc.bits.attempt.generation.expect(2.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/OOOIEXDirectDualStoreSpec.scala b/chisel/src/test/scala/linxcore/iex/OOOIEXDirectDualStoreSpec.scala new file mode 100644 index 00000000..ea4e9768 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/OOOIEXDirectDualStoreSpec.scala @@ -0,0 +1,237 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util.{Decoupled, PopCount} +import linxcore.ooo.{OOOD3S1Graph, OooDispatchClass, + OooIexDomainCapability, OooLateSplitKind, OooOpcodeDisposition, + OooOpcodeRecipeKind, OooSideEffectOwner} +import linxcore.params.{CoreParams, SimulationParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class OOOIEXDirectD3StoreHarnessIO(val p: CoreParams) extends Bundle { + val fromD2 = Flipped(Decoupled(new D2AdmissionGroup(p))) + val bootstrapReady = Output(Bool()) + val robTailSlot = Output(UInt(p.ooo.ridSlotWidth.W)) + val storeDispatchCount = Output(UInt(32.W)) + val storeReservationCount = Output(UInt(32.W)) + val storeBindingCount = Output(UInt(32.W)) + val storeBindingMismatchCount = Output(UInt(32.W)) + val storeDispatchValid = Output(Vec(p.iex.stdPipes, Bool())) + val storeDispatchReady = Output(Vec(p.iex.stdPipes, Bool())) + val storeBindingValid = Output(Vec(p.iex.stdPipes, Bool())) + val storeBindingReady = Output(Vec(p.iex.stdPipes, Bool())) +} + +class OOOIEXDirectD3StoreHarness(val p: CoreParams) extends Module { + val io = IO(new OOOIEXDirectD3StoreHarnessIO(p)) + + private val ooo = Module(new OOOD3S1Graph(p)) + private val iex = Module(new IEX(p)) + iex.io.branchResolve.ready := true.B + ooo.io.fromD2 <> io.fromD2 + iex.io.ooo <> ooo.io.iex + ooo.io.storeResolve.valid := false.B + ooo.io.storeResolve.bits := 0.U.asTypeOf(ooo.io.storeResolve.bits) + + private val bootCount = p.ooo.stidCount * p.ooo.gprArchRegs + private val bootIndex = RegInit(0.U(chisel3.util.log2Ceil(bootCount + 1).W)) + private val bootActive = bootIndex < bootCount.U + iex.io.pInit.valid := bootActive + iex.io.pInit.bits := 0.U.asTypeOf(iex.io.pInit.bits) + iex.io.pInit.bits.stid := bootIndex / p.ooo.gprArchRegs.U + iex.io.pInit.bits.atag := bootIndex % p.ooo.gprArchRegs.U + iex.io.pInit.bits.epoch := 1.U + iex.io.pInit.bits.ptag := bootIndex + when(iex.io.pInit.fire) { bootIndex := bootIndex + 1.U } + iex.io.bootstrapComplete := !bootActive + io.bootstrapReady := iex.io.bootstrapReady + + iex.io.lsu.storeReservation.foreach(_.ready := true.B) + iex.io.lsu.loadAddress.foreach(_.ready := true.B) + iex.io.lsu.loadAllocation.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.loadLaunch.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.storeAddress.foreach(_.ready := true.B) + iex.io.lsu.storeData.foreach(_.ready := true.B) + iex.io.lsu.loadResult.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.loadReissue.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.loadRebindApply.foreach(_.ready := true.B) + iex.io.lsu.loadRepick.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.loadCancel.foreach { port => + port.valid := false.B + port.bits := 0.U.asTypeOf(port.bits) + } + iex.io.lsu.recoveryEvent.valid := false.B + iex.io.lsu.recoveryEvent.bits := 0.U.asTypeOf(iex.io.lsu.recoveryEvent.bits) + iex.io.cmdIssue.ready := true.B + iex.io.trace.ready := true.B + + ooo.io.commit.ready := true.B + ooo.io.storeCommit.ready := true.B + ooo.io.trap.ready := true.B + ooo.io.interrupt.valid := false.B + ooo.io.interrupt.bits := 0.U.asTypeOf(ooo.io.interrupt.bits) + ooo.io.debugRequest.valid := false.B + ooo.io.debugRequest.bits := 0.U.asTypeOf(ooo.io.debugRequest.bits) + ooo.io.debugResponse.ready := true.B + ooo.io.systemIssue.foreach(_.ready := true.B) + ooo.io.trace.ready := true.B + Seq(ooo.io.recoveryToD1, ooo.io.recoveryToIfu, + ooo.io.recoveryToCtu, ooo.io.recoveryToLsu).foreach { target => + target.prepare.ready := true.B + target.prepared.valid := false.B + target.prepared.bits := 0.U.asTypeOf(target.prepared.bits) + } + + private val dispatchFire = iex.io.ooo.storeDispatch.map(_.fire).reduce(_ || _) + private val dispatchCount = RegInit(0.U(32.W)) + when(dispatchFire) { + dispatchCount := dispatchCount + PopCount(iex.io.ooo.storeDispatch.map(_.fire)) + } + private val reservationFires = PopCount(iex.io.lsu.storeReservation.map(_.fire)) + private val reservationCount = RegInit(0.U(32.W)) + when(reservationFires.orR) { + reservationCount := reservationCount + reservationFires + } + private val bindingFires = PopCount(iex.io.ooo.storeBinding.map(_.fire)) + private val bindingCount = RegInit(0.U(32.W)) + when(bindingFires.orR) { + bindingCount := bindingCount + bindingFires + } + private val bindingMismatches = VecInit( + iex.io.ooo.storeBinding.zipWithIndex.map { case (binding, lane) => + val expected = Wire(new MemoryOrderMeta(p)) + expected := 0.U.asTypeOf(expected) + expected.requestCount := 1.U + expected.firstLsid := lane.U + expected.firstSid := lane.U + expected.yostValid := (lane > 0).B + binding.fire && binding.bits.memoryOrder.asUInt =/= expected.asUInt + }) + private val bindingMismatchCount = RegInit(0.U(32.W)) + when(bindingMismatches.asUInt.orR) { + bindingMismatchCount := bindingMismatchCount + PopCount(bindingMismatches) + } + io.robTailSlot := ooo.io.ridTailSlot.head + io.storeDispatchCount := dispatchCount + io.storeReservationCount := reservationCount + io.storeBindingCount := bindingCount + io.storeBindingMismatchCount := bindingMismatchCount + io.storeDispatchValid := VecInit(iex.io.ooo.storeDispatch.map(_.valid)) + io.storeDispatchReady := VecInit(iex.io.ooo.storeDispatch.map(_.ready)) + io.storeBindingValid := VecInit(iex.io.ooo.storeBinding.map(_.valid)) + io.storeBindingReady := VecInit(iex.io.ooo.storeBinding.map(_.ready)) +} + +class OOOIEXDirectDualStoreBoundarySpec extends AnyFunSuite with ChiselSim { + private val p = SimulationParamProfiles.W4 + + private def pokeStorePrefix(dut: OOOIEXDirectD3StoreHarness): Unit = { + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(2.U) + for (lane <- 0 until 2) { + val group = dut.io.fromD2.bits.groups(lane) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(lane.U) + group.ridGeneration.poke(0.U) + + val uop = dut.io.fromD2.bits.entries(lane).uop + uop.valid.poke(true.B) + uop.instruction.parent.identity.peId.poke(1.U) + uop.instruction.parent.identity.stid.poke(0.U) + uop.instruction.parent.identity.instructionId.poke((20 + lane).U) + uop.instruction.parent.identity.epoch.poke(1.U) + uop.instruction.parent.pc.poke((0x2400 + lane * 4).U) + uop.instruction.parent.lengthBytes.poke(4.U) + uop.rob.peId.poke(1.U) + uop.rob.stid.poke(0.U) + uop.rob.ridSlot.poke(lane.U) + uop.rob.ridGeneration.poke(0.U) + uop.rob.memberIndex.poke(0.U) + uop.uopClass.poke(UopClass.Std) + uop.blockStart.poke(true.B) + uop.blockStop.poke(true.B) + uop.memory.valid.poke(true.B) + uop.memory.isStore.poke(true.B) + uop.memory.requestCount.poke(1.U) + uop.memory.addressMode.poke(MemoryAddressMode.BaseOffset) + uop.memory.accessBytes.poke(8.U) + + val classification = uop.classification + classification.valid.poke(true.B) + classification.disposition.poke(OooOpcodeDisposition.Dispatch.U) + classification.kind.poke(OooOpcodeRecipeKind.ScalarStore.U) + classification.uopCountMin.poke(1.U) + classification.uopCountMax.poke(2.U) + classification.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) + classification.dispatchClass.poke(OooDispatchClass.Std.U) + classification.splitKind.poke(OooLateSplitKind.StoreAddressData.U) + classification.dispatchWrites.poke(2.U) + classification.memoryRequestCount.poke(1.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.dispatchDemand(OooDispatchClass.Std - 1).poke(1.U) + classification.executionPipeCapability( + OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress).U) + classification.executionPipeCapability( + OooDispatchClass.Std - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreData).U) + } + } + + test("empty ROB accepts a direct W4 dual-store D3 prefix without a dispatch queue") { + simulate(new OOOIEXDirectD3StoreHarness(p)) { dut => + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + while (!dut.io.bootstrapReady.peek().litToBoolean) dut.clock.step() + + pokeStorePrefix(dut) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + var cycles = 0 + while (dut.io.storeDispatchCount.peek().litValue < 2 && cycles < 16) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 16, + s"the no-Queue D3 graph deadlocked before dual-store dispatch: " + + s"robTail=${dut.io.robTailSlot.peek().litValue} " + + s"count=${dut.io.storeDispatchCount.peek().litValue} " + + s"reservation=${dut.io.storeReservationCount.peek().litValue} " + + s"binding=${dut.io.storeBindingCount.peek().litValue} " + + s"dispatchValid=${dut.io.storeDispatchValid.map(_.peek().litValue)} " + + s"dispatchReady=${dut.io.storeDispatchReady.map(_.peek().litValue)} " + + s"bindingValid=${dut.io.storeBindingValid.map(_.peek().litValue)} " + + s"bindingReady=${dut.io.storeBindingReady.map(_.peek().litValue)}") + dut.io.storeDispatchCount.expect(2.U) + dut.io.storeReservationCount.expect(2.U) + dut.io.storeBindingCount.expect(2.U) + dut.io.storeBindingMismatchCount.expect(0.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/OOOIEXIntegrationSpec.scala b/chisel/src/test/scala/linxcore/iex/OOOIEXIntegrationSpec.scala new file mode 100644 index 00000000..9b959e9f --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/OOOIEXIntegrationSpec.scala @@ -0,0 +1,19 @@ +package linxcore.iex + +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class OOOIEXIntegrationSpec extends AnyFunSuite { + test("OOO and IEX elaborate one canonical classed dispatch graph") { + Seq(2, 4, 6, 8).foreach { width => + val rtl = ChiselStage.emitCHIRRTL( + new OOOIEXLSUActivationProbe( + SimulationParamProfiles.forWidth(width))) + assert(rtl.contains("module OOO")) + assert(rtl.contains("module IEX")) + assert(rtl.contains("module OooIexExecutionPipeline")) + assert(!rtl.contains("module ReducedScalarIssueQueue")) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationProbe.scala b/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationProbe.scala new file mode 100644 index 00000000..03f1667c --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationProbe.scala @@ -0,0 +1,566 @@ +package linxcore.iex + +import chisel3._ +import chisel3.util.{Arbiter, Decoupled, DecoupledIO, Queue} +import linxcore.dtu.{DTU, PerformanceCounterIndex} +import linxcore.lsu.LSU +import linxcore.ooo.OOO +import linxcore.params.{CoreParams, ParamProfiles, SimulationParamProfiles} +import linxcore.top.interface.{D1Packet, LoadReplayRequestTxn, LoadResultTxn, + MemoryIdentity, MemoryTransactionIdentity, RecoveryCause, TraceKind, + TracePacket} + +/** Capacity-bounded generated-RTL profile. Principal W4 pipe counts and all + * public identity widths remain main-profile-identical; only retained local + * storage is reduced to the already-proven Task-14 minimum geometry. + */ +object OOOIEXLSUActivationParams { + private val w2Base = SimulationParamProfiles.W2 + val W2: CoreParams = w2Base.copy( + ooo = w2Base.ooo.copy( + stidCount = 1, + robGroupsPerStid = 8, + maxInstructionsPerRobGroup = 1, + maxUopsPerInstruction = 12, + robBankCount = 2, + brobEntriesPerStid = 8, + pcBufferEntries = 4, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 4, + gprPhysRegs = 32, + gprMapQDepthPerStid = 4, + tPhysRegs = 4, + uPhysRegs = 4, + tuMapQDepthPerStid = 4), + iex = w2Base.iex.copy(scalarIssueEntries = 4), + lsu = w2Base.lsu.copy( + loadQueueEntries = 2, + storeQueueEntries = 4, + loadReturnQueueEntries = 2, + storeCommitQueueEntries = 2, + scbEntries = 4, + loadMissQueueEntries = 2, + loadRefillQueueEntries = 2, + resolveQueueEntries = 4, + mdbSsitEntries = 4, + mdbCommandQueueEntries = 4, + mdbOutputQueueEntries = 4, + mdbWaitPlanQueueEntries = 4, + mdbRecoveryQueueEntries = 4, + mdbFailedWaitTimeoutCycles = 8, + l1dSets = 2, + l1dWays = 2)) + + private val main = ParamProfiles.W4 + val W4: CoreParams = main.copy( + ooo = main.ooo.copy( + stidCount = 2, + stidIdentityEntries = main.ooo.stidIdentityEntries, + robGroupsPerStid = 8, + robIdentityGroupsPerStid = main.ooo.robIdentityGroupsPerStid, + maxInstructionsPerRobGroup = 1, + robIdentityMembersPerGroup = main.ooo.robIdentityMembersPerGroup, + maxUopsPerInstruction = 12, + uopIdentityEntriesPerInstruction = + main.ooo.uopIdentityEntriesPerInstruction, + robBankCount = 4, + brobEntriesPerStid = 8, + brobIdentityEntriesPerStid = main.ooo.brobIdentityEntriesPerStid, + pcBufferEntries = 8, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 4, + gprPhysRegs = 64, + gprTagIdentityEntries = main.ooo.gprTagIdentityEntries, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + tTagIdentityEntries = main.ooo.tTagIdentityEntries, + uPhysRegs = 8, + uTagIdentityEntries = main.ooo.uTagIdentityEntries, + tuMapQDepthPerStid = 8), + iex = main.iex.copy(scalarIssueEntries = 4), + lsu = main.lsu.copy( + loadQueueEntries = 2, + storeQueueEntries = 4, + loadReturnQueueEntries = 2, + storeCommitQueueEntries = 2, + scbEntries = 4, + loadMissQueueEntries = 2, + loadRefillQueueEntries = 2, + resolveQueueEntries = 4, + mdbSsitEntries = 4, + mdbCommandQueueEntries = 4, + mdbOutputQueueEntries = 4, + mdbWaitPlanQueueEntries = 4, + mdbRecoveryQueueEntries = 4, + mdbFailedWaitTimeoutCycles = 8, + l1dSets = 2, + l1dWays = 2)) +} + +class OOOIEXLSUActivationProbeIO(val p: CoreParams) extends Bundle { + val program = Flipped(Decoupled(new D1Packet(p))) + val commitReady = Input(Bool()) + val trapReady = Input(Bool()) + val cmdReady = Input(Bool()) + val systemReady = Input(Bool()) + val oooTraceReady = Input(Bool()) + val iexTraceReady = Input(Bool()) + val recoveryReady = Input(Bool()) + val lsuTraceReady = Input(Bool()) + val memoryReady = Input(Vec(p.lsu.loadPipes + p.lsu.storePipes, Bool())) + val memoryResponseValid = Input(Bool()) + val memoryResponseId = Input(UInt(p.memoryTransactionIdWidth.W)) + val memoryResponseGeneration = + Input(UInt(p.memoryTransactionGenerationWidth.W)) + val memoryResponseAddress = Input(UInt(p.physicalAddressWidth.W)) + val memoryResponseData = Input(UInt(p.dataWidth.W)) + val memoryResponseReady = Output(Bool()) + val loadReissueRequest = Flipped(Decoupled(new LoadReplayRequestTxn(p))) + val loadResultInject = Flipped(Decoupled(new LoadResultTxn(p))) + val bootstrapComplete = Output(Bool()) + val bootstrapInitCount = Output(UInt(32.W)) + + val ingressCount = Output(UInt(32.W)) + val aluCount = Output(UInt(32.W)) + val bruCount = Output(UInt(32.W)) + val aguCount = Output(UInt(32.W)) + val stdCount = Output(UInt(32.W)) + val systemCount = Output(UInt(32.W)) + val cmdCount = Output(UInt(32.W)) + val systemIssueCount = Output(UInt(32.W)) + val cmdIssueCount = Output(UInt(32.W)) + val resolveCount = Output(UInt(32.W)) + val rfWriteCount = Output(UInt(32.W)) + val branchCount = Output(UInt(32.W)) + val recoveryEventCount = Output(UInt(32.W)) + val recoveryApplyCount = Output(UInt(32.W)) + val iexTerminalTraceCount = Output(UInt(32.W)) + val loadCount = Output(UInt(32.W)) + val loadLaunchCount = Output(UInt(32.W)) + val loadAttemptLaunchCount = Output(UInt(32.W)) + val loadAttemptCancelCount = Output(UInt(32.W)) + val loadResultCount = Output(UInt(32.W)) + val loadLaneIssueCount = Output(Vec(p.lsu.loadPipes, UInt(32.W))) + val lastLoadIssueIdentityByLane = Output(Vec(p.lsu.loadPipes, + new MemoryIdentity(p))) + val lastLoadAllocationIdByLane = Output(Vec(p.lsu.loadPipes, + new MemoryTransactionIdentity(p))) + val lastLoadAddressByLane = Output(Vec(p.lsu.loadPipes, + UInt(p.physicalAddressWidth.W))) + val lastLoadIssueIdentity = Output(new MemoryIdentity(p)) + val lastLoadAllocationId = Output(new MemoryTransactionIdentity(p)) + val lastLoadDestination = Output( + new linxcore.top.interface.RenamedDestination(p)) + val lastLoadDestinationRelativeIndex = Output(UInt(p.archRegWidth.W)) + val lastLoadLaunchIdentity = Output(new MemoryIdentity(p)) + val firstLoadAttemptLaunchIdentity = Output(new MemoryIdentity(p)) + val lastLoadAttemptLaunchIdentity = Output(new MemoryIdentity(p)) + val lastLoadRebindCurrent = Output(new MemoryIdentity(p)) + val lastLoadRebindNext = Output(new MemoryIdentity(p)) + val lastLoadResultIdentity = Output(new MemoryIdentity(p)) + val storeAddressCount = Output(UInt(32.W)) + val storeDataCount = Output(UInt(32.W)) + val memoryCount = Output(UInt(32.W)) + val commitCount = Output(UInt(32.W)) + val traceCount = Output(UInt(32.W)) + val dtuTraceValid = Output(Bool()) + val dtuTrace = Output(new TracePacket(p)) + val dtuTraceAcceptedCount = Output(UInt(64.W)) + val dtuTraceDroppedCount = Output(UInt(64.W)) + val stid0Progress = Output(UInt(32.W)) + val stid1Progress = Output(UInt(32.W)) + val stid0CommitProgress = Output(UInt(32.W)) + val stid1CommitProgress = Output(UInt(32.W)) + val dispatchStallCount = Output(UInt(32.W)) + val memoryStallCount = Output(UInt(32.W)) + val lastResolveValue = Output(UInt(p.dataWidth.W)) + val lastRfWriteValue = Output(UInt(p.dataWidth.W)) + val lastRfWritePtag = Output(UInt(p.ooo.gprTagWidth.W)) + val lastRfWriteGeneration = Output(UInt(p.ooo.gprTagGenerationWidth.W)) + val lastBranchTarget = Output(UInt(p.pcWidth.W)) + val lastLoadAddress = Output(UInt(p.physicalAddressWidth.W)) + val lastStoreAddress = Output(UInt(p.physicalAddressWidth.W)) + val lastStoreData = Output(UInt(p.dataWidth.W)) + val lastMemoryId = Output(UInt(p.memoryTransactionIdWidth.W)) + val lastMemoryGeneration = Output( + UInt(p.memoryTransactionGenerationWidth.W)) + val lastMemoryAddress = Output(UInt(p.physicalAddressWidth.W)) +} + +/** Retained subsystem composition used by the generated-RTL activation gate. + * It contains no state beyond the three mainline owners. + */ +class OOOIEXLSUActivationProbe(val p: CoreParams) extends Module { + val io = IO(new OOOIEXLSUActivationProbeIO(p)) + + private val ooo = Module(new OOO(p)) + private val iex = Module(new IEX(p)) + iex.io.branchResolve.ready := true.B + private val lsu = Module(new LSU(p)) + private val dtu = Module(new DTU(p)) + + private def queued[T <: Data](source: DecoupledIO[T], + sink: DecoupledIO[T]): Unit = { + val boundary = Module(new Queue(chiselTypeOf(source.bits), 1, + pipe = false, flow = false)) + boundary.io.enq <> source + sink <> boundary.io.deq + } + for (lane <- ooo.io.iex.aluDispatch.indices) { + queued(ooo.io.iex.aluDispatch(lane), iex.io.ooo.aluDispatch(lane)) + } + for (lane <- ooo.io.iex.bruDispatch.indices) { + queued(ooo.io.iex.bruDispatch(lane), iex.io.ooo.bruDispatch(lane)) + } + for (lane <- ooo.io.iex.aguDispatch.indices) { + queued(ooo.io.iex.aguDispatch(lane), iex.io.ooo.aguDispatch(lane)) + } + for (lane <- ooo.io.iex.storeDispatch.indices) { + queued(ooo.io.iex.storeDispatch(lane), iex.io.ooo.storeDispatch(lane)) + } + for (lane <- ooo.io.iex.systemDispatch.indices) { + queued(ooo.io.iex.systemDispatch(lane), iex.io.ooo.systemDispatch(lane)) + } + for (lane <- ooo.io.iex.cmdDispatch.indices) { + queued(ooo.io.iex.cmdDispatch(lane), iex.io.ooo.cmdDispatch(lane)) + } + iex.io.ooo.allocationClear := ooo.io.iex.allocationClear + queued(ooo.io.iex.fastResult, iex.io.ooo.fastResult) + ooo.io.iex.storeBinding <> iex.io.ooo.storeBinding + ooo.io.iex.pcBufferReadAddress := iex.io.ooo.pcBufferReadAddress + iex.io.ooo.pcBufferReadPcBase := ooo.io.iex.pcBufferReadPcBase + ooo.io.iex.robNoflushReady <> iex.io.ooo.robNoflushReady + queued(ooo.io.iex.robNoflush, iex.io.ooo.robNoflush) + for (lane <- ooo.io.iex.robResolve.indices) { + ooo.io.iex.robResolve(lane) <> iex.io.ooo.robResolve(lane) + } + for (lane <- ooo.io.iex.systemIssue.indices) { + ooo.io.iex.systemIssue(lane) <> iex.io.ooo.systemIssue(lane) + } + ooo.io.iex.recoveryEvent.valid := iex.io.ooo.recoveryEvent.valid && + io.recoveryReady + ooo.io.iex.recoveryEvent.bits := iex.io.ooo.recoveryEvent.bits + iex.io.ooo.recoveryEvent.ready := ooo.io.iex.recoveryEvent.ready && + io.recoveryReady + ooo.io.iex.recovery <> iex.io.ooo.recovery + for (lane <- iex.io.lsu.storeReservation.indices) { + iex.io.lsu.storeReservation(lane) <> lsu.io.iex.storeReservation(lane) + } + for (lane <- iex.io.lsu.loadAddress.indices) { + iex.io.lsu.loadAddress(lane) <> lsu.io.iex.loadAddress(lane) + iex.io.lsu.loadAllocation(lane) <> lsu.io.iex.loadAllocation(lane) + iex.io.lsu.loadLaunch(lane) <> lsu.io.iex.loadLaunch(lane) + iex.io.lsu.loadReissue(lane) <> lsu.io.iex.loadReissue(lane) + iex.io.lsu.loadRebindApply(lane) <> lsu.io.iex.loadRebindApply(lane) + iex.io.lsu.loadRepick(lane) <> lsu.io.iex.loadRepick(lane) + iex.io.lsu.loadCancel(lane) <> lsu.io.iex.loadCancel(lane) + } + val loadResultArbiter = Module(new Arbiter(new LoadResultTxn(p), 2)) + loadResultArbiter.io.in(0) <> io.loadResultInject + loadResultArbiter.io.in(1) <> lsu.io.iex.loadResult.head + iex.io.lsu.loadResult.head <> loadResultArbiter.io.out + for (lane <- 1 until iex.io.lsu.loadResult.length) { + iex.io.lsu.loadResult(lane) <> lsu.io.iex.loadResult(lane) + } + for (lane <- iex.io.lsu.storeAddress.indices) { + iex.io.lsu.storeAddress(lane) <> lsu.io.iex.storeAddress(lane) + iex.io.lsu.storeData(lane) <> lsu.io.iex.storeData(lane) + } + iex.io.lsu.recoveryEvent <> lsu.io.iex.recoveryEvent + ooo.io.recoveryToLsu <> lsu.io.recovery + + val bootCount = p.ooo.stidCount * p.ooo.gprArchRegs + val bootIndex = RegInit(0.U(chisel3.util.log2Ceil(bootCount + 1).W)) + val bootActive = bootIndex < bootCount.U + iex.io.pInit.valid := bootActive + iex.io.pInit.bits := 0.U.asTypeOf(iex.io.pInit.bits) + iex.io.pInit.bits.stid := bootIndex / p.ooo.gprArchRegs.U + iex.io.pInit.bits.atag := bootIndex % p.ooo.gprArchRegs.U + iex.io.pInit.bits.epoch := 1.U + iex.io.pInit.bits.ptag := bootIndex + when(iex.io.pInit.fire) { bootIndex := bootIndex + 1.U } + iex.io.bootstrapComplete := !bootActive + val bootstrapDone = iex.io.bootstrapReady + io.bootstrapComplete := bootstrapDone + ooo.io.fromCtu.valid := io.program.valid && bootstrapDone + ooo.io.fromCtu.bits := io.program.bits + io.program.ready := ooo.io.fromCtu.ready && bootstrapDone + ooo.io.commit.ready := io.commitReady + ooo.io.trap.ready := io.trapReady + ooo.io.interrupt.valid := false.B + ooo.io.interrupt.bits := 0.U.asTypeOf(ooo.io.interrupt.bits) + dtu.io.debugRequest.valid := false.B + dtu.io.debugRequest.bits := 0.U.asTypeOf(dtu.io.debugRequest.bits) + ooo.io.debugRequest <> dtu.io.controlRequest + dtu.io.controlResponse <> ooo.io.debugResponse + dtu.io.debugResponse.ready := true.B + dtu.io.commitIn.valid := ooo.io.commit.fire + dtu.io.commitIn.bits := ooo.io.commit.bits + dtu.io.traceIn <> iex.io.trace + dtu.io.traceOverflowDropped := 0.U + dtu.io.traceOut.ready := io.iexTraceReady + io.dtuTraceValid := dtu.io.traceOut.valid + io.dtuTrace := dtu.io.traceOut.bits + io.dtuTraceAcceptedCount := + dtu.io.performanceCounters(PerformanceCounterIndex.TraceAccepted) + io.dtuTraceDroppedCount := + dtu.io.performanceCounters(PerformanceCounterIndex.TraceDropped) + ooo.io.trace.ready := true.B + ooo.io.systemIssue.foreach(_.ready := io.systemReady) + for (target <- Seq(ooo.io.recoveryToIfu, ooo.io.recoveryToCtu)) { + val pending = RegInit(false.B) + val retained = Reg(chiselTypeOf(target.prepare.bits)) + target.prepare.ready := !pending + target.prepared.valid := pending + target.prepared.bits := retained + when(target.prepare.fire) { + pending := true.B + retained := target.prepare.bits + }.elsewhen(target.prepared.fire) { + pending := false.B + } + } + + iex.io.cmdIssue.ready := io.cmdReady + lsu.io.storeCommit <> ooo.io.storeCommit + ooo.io.storeResolve <> lsu.io.storeResolve + lsu.io.memoryFault.ready := true.B + lsu.io.maintenance.valid := false.B + lsu.io.maintenance.bits := 0.U.asTypeOf(lsu.io.maintenance.bits) + lsu.io.maintenanceResult.ready := true.B + lsu.io.loadReissueRequest <> io.loadReissueRequest + for (lane <- lsu.io.memoryRequest.indices) { + lsu.io.memoryRequest(lane).ready := io.memoryReady(lane) + } + lsu.io.memoryResponse.foreach { response => + response.valid := false.B + response.bits := 0.U.asTypeOf(response.bits) + } + lsu.io.memoryResponse.head.valid := io.memoryResponseValid + lsu.io.memoryResponse.head.bits.identity.value := io.memoryResponseId + lsu.io.memoryResponse.head.bits.identity.generation := + io.memoryResponseGeneration + lsu.io.memoryResponse.head.bits.address := io.memoryResponseAddress + lsu.io.memoryResponse.head.bits.data := io.memoryResponseData + io.memoryResponseReady := lsu.io.memoryResponse.head.ready + lsu.io.trace.ready := true.B + + private def countWhen(event: Bool): UInt = { + val count = RegInit(0.U(32.W)) + when(event) { count := count + 1.U } + count + } + private def anyFire(ports: Seq[DecoupledIO[_ <: Data]]): Bool = + ports.map(_.fire).reduce(_ || _) + private def anyBlocked(ports: Seq[DecoupledIO[_ <: Data]]): Bool = + ports.map(port => port.valid && !port.ready).reduce(_ || _) + + val aluFire = anyFire(iex.io.ooo.aluDispatch.toSeq) + val bruFire = anyFire(iex.io.ooo.bruDispatch.toSeq) + val aguFire = anyFire(iex.io.ooo.aguDispatch.toSeq) + val stdFire = anyFire(iex.io.ooo.storeDispatch.toSeq) + val systemFire = anyFire(iex.io.ooo.systemDispatch.toSeq) + val cmdFire = anyFire(iex.io.ooo.cmdDispatch.toSeq) + val systemIssueFire = anyFire(ooo.io.systemIssue.toSeq) + val cmdIssueFire = iex.io.cmdIssue.fire + val resolveFire = anyFire(ooo.io.iex.robResolve.toSeq) + val loadFire = anyFire(lsu.io.iex.loadAddress.toSeq) + val loadLaunchFire = lsu.io.iex.loadLaunch.map(_.valid).reduce(_ || _) + val countedLoadAttempt = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val countedLoadAttemptValid = RegInit(false.B) + val firstLoadAttemptLaunch = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val lastLoadAttemptLaunch = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val launchAttemptIdentity = lsu.io.iex.loadLaunch.head.bits.identity + val sameCountedLoadAttempt = countedLoadAttemptValid && + launchAttemptIdentity.transaction.asUInt === + countedLoadAttempt.transaction.asUInt && + launchAttemptIdentity.attemptGeneration === + countedLoadAttempt.attemptGeneration + val loadAttemptLaunchFire = loadLaunchFire && + !sameCountedLoadAttempt + when(loadAttemptLaunchFire) { + countedLoadAttempt := launchAttemptIdentity + when(!countedLoadAttemptValid) { + firstLoadAttemptLaunch := launchAttemptIdentity + } + lastLoadAttemptLaunch := launchAttemptIdentity + countedLoadAttemptValid := true.B + } + val loadRebindFire = anyFire(iex.io.lsu.loadRebindApply.toSeq) + val loadResultFire = anyFire(iex.io.lsu.loadResult.toSeq) + val storeAddressFire = anyFire(lsu.io.iex.storeAddress.toSeq) + val storeDataFire = anyFire(lsu.io.iex.storeData.toSeq) + val memoryFire = anyFire(lsu.io.memoryRequest.toSeq) + val traceFire = dtu.io.traceIn.fire + + io.ingressCount := countWhen(io.program.fire) + io.bootstrapInitCount := countWhen(iex.io.pInit.fire) + io.aluCount := countWhen(aluFire) + io.bruCount := countWhen(bruFire) + io.aguCount := countWhen(aguFire) + io.stdCount := countWhen(stdFire) + io.systemCount := countWhen(systemFire) + io.cmdCount := countWhen(cmdFire) + io.systemIssueCount := countWhen(systemIssueFire) + io.cmdIssueCount := countWhen(cmdIssueFire) + io.resolveCount := countWhen(resolveFire) + val rfWriteFire = iex.io.terminalPWrite.valid + io.rfWriteCount := countWhen(rfWriteFire) + io.branchCount := countWhen(iex.io.ooo.recoveryEvent.fire && + iex.io.ooo.recoveryEvent.bits.cause === RecoveryCause.Branch) + io.recoveryEventCount := countWhen(iex.io.ooo.recoveryEvent.fire) + io.recoveryApplyCount := countWhen(iex.io.ooo.recovery.apply.valid) + io.iexTerminalTraceCount := countWhen(dtu.io.traceIn.fire) + io.loadCount := countWhen(loadFire) + io.loadLaunchCount := countWhen(loadLaunchFire) + io.loadAttemptLaunchCount := countWhen(loadAttemptLaunchFire) + io.loadAttemptCancelCount := countWhen(loadRebindFire) + io.loadResultCount := countWhen(loadResultFire) + for (lane <- 0 until p.lsu.loadPipes) { + io.loadLaneIssueCount(lane) := countWhen( + lsu.io.iex.loadAddress(lane).fire) + } + val lastLoadIssueIdentity = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val lastLoadAllocationId = RegInit( + 0.U.asTypeOf(new MemoryTransactionIdentity(p))) + val lastLoadIssueIdentityByLane = RegInit(VecInit(Seq.fill(p.lsu.loadPipes)( + 0.U.asTypeOf(new MemoryIdentity(p))))) + val lastLoadAllocationIdByLane = RegInit(VecInit(Seq.fill(p.lsu.loadPipes)( + 0.U.asTypeOf(new MemoryTransactionIdentity(p))))) + val lastLoadAddressByLane = RegInit(VecInit(Seq.fill(p.lsu.loadPipes)( + 0.U(p.physicalAddressWidth.W)))) + val lastLoadDestination = RegInit(0.U.asTypeOf( + new linxcore.top.interface.RenamedDestination(p))) + val lastLoadDestinationRelativeIndex = RegInit(0.U(p.archRegWidth.W)) + val lastLoadLaunchIdentity = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val lastLoadRebindCurrent = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val lastLoadRebindNext = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + val lastLoadResultIdentity = RegInit(0.U.asTypeOf(new MemoryIdentity(p))) + for (lane <- lsu.io.iex.loadAddress.indices) { + when(lsu.io.iex.loadAddress(lane).fire) { + lastLoadIssueIdentityByLane(lane) := + lsu.io.iex.loadAddress(lane).bits.identity + lastLoadAllocationIdByLane(lane) := + lsu.io.iex.loadAllocation(lane).bits.allocationId + lastLoadAddressByLane(lane) := lsu.io.iex.loadAddress(lane).bits.address + lastLoadIssueIdentity := lsu.io.iex.loadAddress(lane).bits.identity + lastLoadAllocationId := + lsu.io.iex.loadAllocation(lane).bits.allocationId + lastLoadDestination := lsu.io.iex.loadAddress(lane).bits.destination + lastLoadDestinationRelativeIndex := + lsu.io.iex.loadAddress(lane).bits.destinationRelativeIndex + } + } + for (lane <- lsu.io.iex.loadLaunch.indices) { + when(lsu.io.iex.loadLaunch(lane).valid) { + lastLoadLaunchIdentity := lsu.io.iex.loadLaunch(lane).bits.identity + } + } + for (lane <- iex.io.lsu.loadRebindApply.indices) { + when(iex.io.lsu.loadRebindApply(lane).fire) { + lastLoadRebindCurrent := + iex.io.lsu.loadRebindApply(lane).bits.currentIdentity + lastLoadRebindNext := iex.io.lsu.loadRebindApply(lane).bits.nextIdentity + } + } + for (lane <- iex.io.lsu.loadResult.indices) { + when(iex.io.lsu.loadResult(lane).fire) { + lastLoadResultIdentity := iex.io.lsu.loadResult(lane).bits.identity + } + } + io.lastLoadIssueIdentity := lastLoadIssueIdentity + io.lastLoadAllocationId := lastLoadAllocationId + io.lastLoadIssueIdentityByLane := lastLoadIssueIdentityByLane + io.lastLoadAllocationIdByLane := lastLoadAllocationIdByLane + io.lastLoadAddressByLane := lastLoadAddressByLane + io.lastLoadDestination := lastLoadDestination + io.lastLoadDestinationRelativeIndex := lastLoadDestinationRelativeIndex + io.lastLoadLaunchIdentity := lastLoadLaunchIdentity + io.firstLoadAttemptLaunchIdentity := firstLoadAttemptLaunch + io.lastLoadAttemptLaunchIdentity := lastLoadAttemptLaunch + io.lastLoadRebindCurrent := lastLoadRebindCurrent + io.lastLoadRebindNext := lastLoadRebindNext + io.lastLoadResultIdentity := lastLoadResultIdentity + io.storeAddressCount := countWhen(storeAddressFire) + io.storeDataCount := countWhen(storeDataFire) + io.memoryCount := countWhen(memoryFire) + io.commitCount := countWhen(ooo.io.commit.fire) + io.traceCount := countWhen(traceFire) + io.dispatchStallCount := countWhen(anyBlocked( + iex.io.ooo.aluDispatch.toSeq ++ iex.io.ooo.bruDispatch.toSeq ++ + iex.io.ooo.aguDispatch.toSeq ++ iex.io.ooo.storeDispatch.toSeq ++ + iex.io.ooo.systemDispatch.toSeq ++ iex.io.ooo.cmdDispatch.toSeq) || + anyBlocked(ooo.io.systemIssue.toSeq) || + (iex.io.cmdIssue.valid && !iex.io.cmdIssue.ready)) + io.memoryStallCount := countWhen(lsu.io.memoryRequest.map( + port => port.valid && !port.ready).reduce(_ || _)) + + val stid0Resolve = ooo.io.iex.robResolve.map(port => + port.fire && port.bits.rob.stid === 0.U).reduce(_ || _) + val stid1Resolve = ooo.io.iex.robResolve.map(port => + port.fire && port.bits.rob.stid === 1.U).reduce(_ || _) + io.stid0Progress := countWhen(stid0Resolve) + io.stid1Progress := countWhen(stid1Resolve) + val stid0Commit = ooo.io.commit.fire && + ooo.io.commit.bits.entries.zipWithIndex.map { case (entry, index) => + index.U < ooo.io.commit.bits.count && entry.instruction.stid === 0.U + }.reduce(_ || _) + val stid1Commit = ooo.io.commit.fire && + ooo.io.commit.bits.entries.zipWithIndex.map { case (entry, index) => + index.U < ooo.io.commit.bits.count && entry.instruction.stid === 1.U + }.reduce(_ || _) + io.stid0CommitProgress := countWhen(stid0Commit) + io.stid1CommitProgress := countWhen(stid1Commit) + + val lastResolveValue = RegInit(0.U(p.dataWidth.W)) + for (port <- ooo.io.iex.robResolve) { + when(port.fire) { lastResolveValue := port.bits.value } + } + io.lastResolveValue := lastResolveValue + val lastRfWriteValue = RegInit(0.U(p.dataWidth.W)) + when(rfWriteFire) { lastRfWriteValue := iex.io.terminalPWrite.bits.value } + io.lastRfWriteValue := lastRfWriteValue + val lastRfWritePtag = RegInit(0.U(p.ooo.gprTagWidth.W)) + val lastRfWriteGeneration = RegInit(0.U( + p.ooo.gprTagGenerationWidth.W)) + when(rfWriteFire) { + lastRfWritePtag := iex.io.terminalPWrite.bits.ptag + lastRfWriteGeneration := iex.io.terminalPWrite.bits.generation + } + io.lastRfWritePtag := lastRfWritePtag + io.lastRfWriteGeneration := lastRfWriteGeneration + val lastBranchTarget = RegInit(0.U(p.pcWidth.W)) + when(iex.io.ooo.recoveryEvent.fire) { + lastBranchTarget := iex.io.ooo.recoveryEvent.bits.redirectPc + } + io.lastBranchTarget := lastBranchTarget + val lastLoadAddress = RegInit(0.U(p.physicalAddressWidth.W)) + for (port <- lsu.io.iex.loadAddress) { + when(port.fire) { lastLoadAddress := port.bits.address } + } + io.lastLoadAddress := lastLoadAddress + val lastStoreAddress = RegInit(0.U(p.physicalAddressWidth.W)) + for (port <- lsu.io.iex.storeAddress) { + when(port.fire) { lastStoreAddress := port.bits.address } + } + io.lastStoreAddress := lastStoreAddress + val lastStoreData = RegInit(0.U(p.dataWidth.W)) + for (port <- lsu.io.iex.storeData) { + when(port.fire) { lastStoreData := port.bits.data.head } + } + io.lastStoreData := lastStoreData + val lastMemoryId = RegInit(0.U(p.memoryTransactionIdWidth.W)) + val lastMemoryGeneration = RegInit( + 0.U(p.memoryTransactionGenerationWidth.W)) + val lastMemoryAddress = RegInit(0.U(p.physicalAddressWidth.W)) + for (port <- lsu.io.memoryRequest) { + when(port.fire) { + lastMemoryId := port.bits.identity.value + lastMemoryGeneration := port.bits.identity.generation + lastMemoryAddress := port.bits.address + } + } + io.lastMemoryId := lastMemoryId + io.lastMemoryGeneration := lastMemoryGeneration + io.lastMemoryAddress := lastMemoryAddress +} diff --git a/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationSpec.scala b/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationSpec.scala new file mode 100644 index 00000000..9eb36e9d --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationSpec.scala @@ -0,0 +1,883 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.ooo.{OooOpcodeRecipeRule, OooOpcodeRecipeTable} +import linxcore.top.interface.FrontEndOpKind +import org.scalatest.funsuite.AnyFunSuite + +class OOOIEXLSUActivationSpec extends AnyFunSuite with ChiselSim { + private def initialize(dut: OOOIEXLSUActivationProbe): Unit = { + dut.io.program.valid.poke(false.B) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.commitReady.poke(true.B) + dut.io.trapReady.poke(true.B) + dut.io.cmdReady.poke(true.B) + dut.io.systemReady.poke(true.B) + dut.io.oooTraceReady.poke(true.B) + dut.io.iexTraceReady.poke(true.B) + dut.io.recoveryReady.poke(true.B) + dut.io.lsuTraceReady.poke(true.B) + dut.io.memoryReady.foreach(_.poke(true.B)) + dut.io.memoryResponseValid.poke(false.B) + dut.io.memoryResponseId.poke(0.U) + dut.io.memoryResponseGeneration.poke(0.U) + dut.io.memoryResponseAddress.poke(0.U) + dut.io.memoryResponseData.poke(0.U) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.loadResultInject.valid.poke(false.B) + dut.io.loadResultInject.bits.poke( + 0.U.asTypeOf(dut.io.loadResultInject.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + while (!dut.io.bootstrapComplete.peek().litToBoolean) dut.clock.step() + dut.io.bootstrapInitCount.expect( + (dut.p.ooo.stidCount * dut.p.ooo.gprArchRegs).U) + } + + test("joint W4 mainline graph accepts a canonical encoded program row") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + val entry = dut.io.program.bits.entries.head + dut.io.program.bits.count.poke(1.U) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke(1.U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(0x1000.U) + entry.parent.instruction.poke( + (addi.value | (BigInt(5) << 7) | (BigInt(7) << 20)).U) + entry.parent.lengthBytes.poke(addi.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(0x1000.U) + entry.parent.prediction.fallthroughPc.poke(0x1004.U) + entry.parent.prediction.epoch.poke(1.U) + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + dut.io.ingressCount.expect(1.U) + + var activated = false + for (_ <- 0 until 40) { + activated ||= dut.io.aluCount.peek().litValue > 0 && + dut.io.rfWriteCount.peek().litValue > 0 + dut.clock.step() + } + assert(activated, + s"the accepted canonical row must reach public ALU dispatch: " + + s"alu=${dut.io.aluCount.peek().litValue} " + + s"resolve=${dut.io.resolveCount.peek().litValue} " + + s"commit=${dut.io.commitCount.peek().litValue} " + + s"stall=${dut.io.dispatchStallCount.peek().litValue} " + + s"trace=${dut.io.traceCount.peek().litValue}") + dut.io.rfWriteCount.expect(1.U) + dut.io.lastRfWriteValue.expect(7.U) + dut.io.lastRfWritePtag.expect(48.U) + dut.io.lastRfWriteGeneration.expect(0.U) + } + } + + test("public closed SDI block emits matching store address and data") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W2)) { dut => + initialize(dut) + + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val sdi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_SDI").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x2000), + (sdi, sdi.value | (BigInt(0x88) << 20), 0x2004), + (stop, stop.value, 0x2008)) + dut.io.program.bits.count.poke(2.U) + encodings.take(2).zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((lane + 1).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(1.U) + val (stopRule, stopRaw, stopPc) = encodings.last + val stopEntry = dut.io.program.bits.entries.head + stopEntry.kind.poke(FrontEndOpKind.Encoded64) + stopEntry.parent.identity.peId.poke(1.U) + stopEntry.parent.identity.stid.poke(0.U) + stopEntry.parent.identity.instructionId.poke(3.U) + stopEntry.parent.identity.epoch.poke(1.U) + stopEntry.parent.pc.poke(stopPc.U) + stopEntry.parent.instruction.poke(stopRaw.U) + stopEntry.parent.lengthBytes.poke(stopRule.lenBytes.U) + stopEntry.parent.prediction.valid.poke(true.B) + stopEntry.parent.prediction.requestPc.poke(stopPc.U) + stopEntry.parent.prediction.fallthroughPc.poke( + (stopPc + stopRule.lenBytes).U) + stopEntry.parent.prediction.epoch.poke(1.U) + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.storeAddressCount.peek().litValue == 0 || + dut.io.storeDataCount.peek().litValue == 0) && cycles < 96) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.storeAddressCount.peek().litValue == 1, + s"SDI must emit one public store address; " + + s"sta=${dut.io.storeAddressCount.peek().litValue} " + + s"std=${dut.io.storeDataCount.peek().litValue}") + assert(dut.io.storeDataCount.peek().litValue == 1, + s"SDI must emit one public store data payload; " + + s"sta=${dut.io.storeAddressCount.peek().litValue} " + + s"std=${dut.io.storeDataCount.peek().litValue}") + + while (dut.io.commitCount.peek().litValue == 0 && cycles < 192) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.commitCount.peek().litValue == 1, + s"LSU must resolve the joined STA/STD store so the closed block can commit; " + + s"sta=${dut.io.storeAddressCount.peek().litValue} " + + s"std=${dut.io.storeDataCount.peek().litValue} " + + s"commit=${dut.io.commitCount.peek().litValue}") + } + } + + test("loadreplay preserves transaction and rejects the stale attempt") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val load = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_LDI").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x2800), + (load, load.value | (BigInt(0x180) << 20) | (BigInt(5) << 7), + 0x2804), + (stop, stop.value, 0x2808)) + dut.io.program.bits.count.poke(encodings.length.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((70 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.loadCount.peek().litValue != 1 || + dut.io.loadLaunchCount.peek().litValue != 1 || + dut.io.loadAttemptLaunchCount.peek().litValue != 1 || + dut.io.memoryCount.peek().litValue != 1) && cycles < 192) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 192, "initial load must allocate, launch, and miss once") + val initialAttempt = + dut.io.lastLoadIssueIdentity.attemptGeneration.peek().litValue + val transactionValue = + dut.io.lastLoadIssueIdentity.transaction.value.peek().litValue + val transactionGeneration = + dut.io.lastLoadIssueIdentity.transaction.generation.peek().litValue + val initial = dut.io.lastLoadIssueIdentity.peek() + val allocation = dut.io.lastLoadAllocationId.peek() + + val reissue = dut.io.loadReissueRequest + reissue.bits.poke(0.U.asTypeOf(reissue.bits)) + reissue.bits.allocationId.poke(allocation) + reissue.bits.currentIdentity.poke(initial) + reissue.bits.address.poke(dut.io.lastLoadAddress.peek()) + reissue.valid.poke(true.B) + cycles = 0 + while (!reissue.ready.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64, "exact current-attempt replay request must be accepted") + dut.clock.step() + reissue.valid.poke(false.B) + dut.io.loadAttemptCancelCount.expect(1.U) + dut.io.lastLoadRebindCurrent.expect(initial) + dut.io.lastLoadRebindNext.transaction.value.expect(transactionValue.U) + dut.io.lastLoadRebindNext.transaction.generation + .expect(transactionGeneration.U) + dut.io.lastLoadRebindNext.attemptGeneration.expect((initialAttempt + 1).U) + + cycles = 0 + while ((dut.io.loadLaunchCount.peek().litValue != 2 || + dut.io.loadAttemptLaunchCount.peek().litValue != 2 || + dut.io.memoryCount.peek().litValue != 2) && cycles < 128) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 128, + "accepted rebind must return the LIQ row to one new-attempt launch") + dut.io.lastLoadLaunchIdentity.transaction.value.expect(transactionValue.U) + dut.io.lastLoadLaunchIdentity.transaction.generation + .expect(transactionGeneration.U) + dut.io.lastLoadLaunchIdentity.attemptGeneration + .expect((initialAttempt + 1).U) + dut.io.firstLoadAttemptLaunchIdentity.transaction.value + .expect(transactionValue.U) + dut.io.firstLoadAttemptLaunchIdentity.transaction.generation + .expect(transactionGeneration.U) + dut.io.firstLoadAttemptLaunchIdentity.attemptGeneration + .expect(initialAttempt.U) + dut.io.lastLoadAttemptLaunchIdentity.transaction.value + .expect(transactionValue.U) + dut.io.lastLoadAttemptLaunchIdentity.transaction.generation + .expect(transactionGeneration.U) + dut.io.lastLoadAttemptLaunchIdentity.attemptGeneration + .expect((initialAttempt + 1).U) + + val stale = dut.io.loadResultInject + stale.bits.poke(0.U.asTypeOf(stale.bits)) + stale.bits.identity.poke(initial) + stale.bits.allocationId.poke(allocation) + stale.bits.data.poke("hdeadbeef".U) + stale.bits.destination.poke(dut.io.lastLoadDestination.peek()) + stale.bits.destinationRelativeIndex.poke( + dut.io.lastLoadDestinationRelativeIndex.peek()) + val resolveBefore = dut.io.resolveCount.peek().litValue + val writeBefore = dut.io.rfWriteCount.peek().litValue + val commitBefore = dut.io.commitCount.peek().litValue + stale.valid.poke(true.B) + cycles = 0 + while (!stale.ready.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64, "stale old-attempt result must be accepted and dropped") + dut.clock.step() + stale.valid.poke(false.B) + dut.clock.step(8) + dut.io.resolveCount.expect(resolveBefore.U) + dut.io.rfWriteCount.expect(writeBefore.U) + dut.io.commitCount.expect(commitBefore.U) + dut.io.loadLaunchCount.expect(2.U) + dut.io.loadAttemptLaunchCount.expect(2.U) + dut.io.memoryCount.expect(2.U) + dut.io.loadAttemptCancelCount.expect(1.U) + + dut.io.memoryResponseId.poke(dut.io.lastMemoryId.peek()) + dut.io.memoryResponseGeneration.poke( + dut.io.lastMemoryGeneration.peek()) + dut.io.memoryResponseAddress.poke(dut.io.lastMemoryAddress.peek()) + dut.io.memoryResponseData.poke("h1122334455667788".U) + dut.io.memoryResponseValid.poke(true.B) + cycles = 0 + while (!dut.io.memoryResponseReady.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64, "new-attempt lower-memory response must be accepted") + dut.clock.step() + dut.io.memoryResponseValid.poke(false.B) + + cycles = 0 + while ((dut.io.resolveCount.peek().litValue != resolveBefore + 1 || + dut.io.rfWriteCount.peek().litValue != writeBefore + 1 || + dut.io.commitCount.peek().litValue != commitBefore + 1) && + cycles < 192) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 192, + "new attempt must complete with exactly one resolve, writeback, and commit") + dut.io.lastLoadResultIdentity.transaction.value.expect(transactionValue.U) + dut.io.lastLoadResultIdentity.transaction.generation + .expect(transactionGeneration.U) + dut.io.lastLoadResultIdentity.attemptGeneration + .expect((initialAttempt + 1).U) + dut.io.lastResolveValue.expect("h1122334455667788".U) + dut.io.lastRfWriteValue.expect("h1122334455667788".U) + dut.clock.step(16) + dut.io.loadAttemptCancelCount.expect(1.U) + dut.io.loadAttemptLaunchCount.expect(2.U) + dut.io.loadLaunchCount.expect(3.U) + dut.io.memoryCount.expect(2.U) + dut.io.lastLoadLaunchIdentity.transaction.value.expect(transactionValue.U) + dut.io.lastLoadLaunchIdentity.transaction.generation + .expect(transactionGeneration.U) + dut.io.lastLoadLaunchIdentity.attemptGeneration + .expect((initialAttempt + 1).U) + dut.io.resolveCount.expect((resolveBefore + 1).U) + dut.io.rfWriteCount.expect((writeBefore + 1).U) + dut.io.commitCount.expect((commitBefore + 1).U) + } + } + + test("joint lane1 allocation after a prior row accepts exact replay") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val load = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_LDI").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x2a00), + (load, load.value | (BigInt(0x180) << 20) | (BigInt(5) << 7), + 0x2a04), + (load, load.value | (BigInt(0x188) << 20) | (BigInt(6) << 7), + 0x2a08), + (stop, stop.value, 0x2a0c)) + dut.io.program.bits.count.poke(encodings.length.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((90 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.loadLaneIssueCount(0).peek().litValue == 0 || + dut.io.loadLaneIssueCount(1).peek().litValue == 0) && cycles < 192) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 192, + "two joint loads must allocate distinct rows and launch once") + dut.io.lastLoadIssueIdentityByLane(1).pipeId.expect(1.U, + "the second load must retain the nonzero AGU/return-pipe lane") + + val lane1Identity = dut.io.lastLoadIssueIdentityByLane(1).peek() + val lane1Attempt = + dut.io.lastLoadIssueIdentityByLane(1).attemptGeneration.peek().litValue + val lane1TransactionValue = + dut.io.lastLoadIssueIdentityByLane(1).transaction.value.peek().litValue + val lane1TransactionGeneration = + dut.io.lastLoadIssueIdentityByLane(1).transaction.generation.peek() + .litValue + val lane1Allocation = dut.io.lastLoadAllocationIdByLane(1).peek() + val reissue = dut.io.loadReissueRequest + reissue.bits.poke(0.U.asTypeOf(reissue.bits)) + reissue.bits.allocationId.poke(lane1Allocation) + reissue.bits.currentIdentity.poke(lane1Identity) + reissue.bits.address.poke(dut.io.lastLoadAddressByLane(1).peek()) + reissue.valid.poke(true.B) + cycles = 0 + while (!reissue.ready.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64, + "lane-1 metadata must bind its own allocation preview for exact replay") + dut.clock.step() + reissue.valid.poke(false.B) + dut.io.lastLoadRebindCurrent.expect(lane1Identity) + dut.io.lastLoadRebindNext.pipeId.expect(1.U) + dut.io.lastLoadRebindNext.transaction.value.expect( + lane1TransactionValue.U) + dut.io.lastLoadRebindNext.transaction.generation.expect( + lane1TransactionGeneration.U) + dut.io.lastLoadRebindNext.attemptGeneration.expect( + (lane1Attempt + 1).U) + dut.io.loadAttemptCancelCount.expect(1.U) + } + } + + test("public direct J publishes one exact branch recovery target") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val jump = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_J").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x3000), + // J encodes simm22=2 as [11:7]@[31:15], hence a four-byte target. + (jump, jump.value | (BigInt(2) << 15), 0x3004), + (stop, stop.value, 0x3008)) + dut.io.program.bits.count.poke(encodings.length.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((lane + 1).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while (dut.io.branchCount.peek().litValue == 0 && cycles < 128) { + dut.clock.step() + cycles += 1 + } + dut.io.bruCount.expect(1.U) + dut.io.branchCount.expect(1.U) + dut.io.lastBranchTarget.expect(0x3008.U) + } + } + + test("public peer closed block expands through its exact BROB last row") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + val encodings = Seq( + (start, start.value, 0x5000), + (addi, addi.value | (BigInt(5) << 7) | (BigInt(7) << 20), 0x5004), + (addi, addi.value | (BigInt(6) << 7) | (BigInt(7) << 20), 0x5008), + (stop, stop.value, 0x500c)) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(encodings.size.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(1.U) + entry.parent.identity.instructionId.poke((16 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.stid1Progress.peek().litValue < 2 || + dut.io.stid1CommitProgress.peek().litValue == 0) && cycles < 256) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.stid1Progress.peek().litValue == 2 && + dut.io.stid1CommitProgress.peek().litValue > 0, + s"peer block must resolve both body rows and commit its exact close; " + + s"resolve=${dut.io.stid1Progress.peek().litValue} " + + s"commit=${dut.io.stid1CommitProgress.peek().litValue}") + val commitProgress = dut.io.stid1CommitProgress.peek().litValue + dut.clock.step(16) + dut.io.stid1Progress.expect(2.U) + dut.io.stid1CommitProgress.expect(commitProgress.U) + } + } + + test("public System and CMD terminals publish exactly once under CMD backpressure") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val system = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_TLB_IALL").get + val cmd = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_B_HINT").get + val encodings = Seq( + (start, start.value, 0x6000), + (system, system.value, 0x6004), + (cmd, cmd.value, 0x6008), + (stop, stop.value, 0x600c)) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(encodings.size.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((24 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.cmdReady.poke(false.B) + dut.io.systemReady.poke(false.B) + val traceBefore = dut.io.iexTerminalTraceCount.peek().litValue + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.systemCount.peek().litValue == 0 || + dut.io.cmdCount.peek().litValue == 0) && cycles < 128) { + dut.clock.step() + cycles += 1 + } + dut.io.systemCount.expect(1.U) + dut.io.cmdCount.expect(1.U) + dut.io.systemIssueCount.expect(0.U) + dut.io.cmdIssueCount.expect(0.U) + dut.io.iexTerminalTraceCount.expect(traceBefore.U) + dut.clock.step(8) + dut.io.systemIssueCount.expect(0.U) + dut.io.cmdIssueCount.expect(0.U) + + dut.io.systemReady.poke(true.B) + cycles = 0 + while (dut.io.systemIssueCount.peek().litValue == 0 && cycles < 128) { + dut.clock.step() + cycles += 1 + } + dut.io.systemIssueCount.expect(1.U) + dut.io.cmdIssueCount.expect(0.U) + dut.clock.step(8) + dut.io.systemIssueCount.expect(1.U) + dut.io.cmdIssueCount.expect(0.U) + + dut.io.cmdReady.poke(true.B) + cycles = 0 + while ((dut.io.cmdIssueCount.peek().litValue == 0 || + dut.io.stid0CommitProgress.peek().litValue == 0) && cycles < 256) { + dut.clock.step() + cycles += 1 + } + dut.io.systemIssueCount.expect(1.U) + assert(dut.io.cmdIssueCount.peek().litValue == 1 && + dut.io.iexTerminalTraceCount.peek().litValue == traceBefore + 2 && + dut.io.stid0CommitProgress.peek().litValue > 0, + s"System/CMD block must commit exactly once; " + + s"systemIssue=${dut.io.systemIssueCount.peek().litValue} " + + s"cmdIssue=${dut.io.cmdIssueCount.peek().litValue} " + + s"resolve=${dut.io.resolveCount.peek().litValue} " + + s"commit=${dut.io.stid0CommitProgress.peek().litValue}") + val commitProgress = dut.io.stid0CommitProgress.peek().litValue + dut.clock.step(16) + dut.io.systemIssueCount.expect(1.U) + dut.io.cmdIssueCount.expect(1.U) + dut.io.stid0CommitProgress.expect(commitProgress.U) + } + } + + test("stalled younger CMD is killed by an older open-current BRU recovery") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val jump = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_J").get + val cmd = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_B_HINT").get + val encodings = Seq( + (start, start.value, 0x7000), + (jump, jump.value | (BigInt(2) << 15), 0x7004), + (cmd, cmd.value, 0x7008), + (stop, stop.value, 0x700c)) + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(encodings.size.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((40 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.cmdReady.poke(false.B) + dut.io.recoveryReady.poke(false.B) + val traceBefore = dut.io.iexTerminalTraceCount.peek().litValue + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + var cycles = 0 + while ((dut.io.bruCount.peek().litValue == 0 || + dut.io.cmdCount.peek().litValue == 0) && cycles < 128) { + dut.clock.step() + cycles += 1 + } + dut.io.bruCount.expect(1.U) + dut.io.cmdCount.expect(1.U) + dut.io.branchCount.expect(0.U) + dut.io.cmdIssueCount.expect(0.U) + dut.clock.step(8) + dut.io.branchCount.expect(0.U) + dut.io.cmdIssueCount.expect(0.U) + + dut.io.recoveryReady.poke(true.B) + cycles = 0 + while ((dut.io.branchCount.peek().litValue == 0 || + dut.io.recoveryApplyCount.peek().litValue == 0) && cycles < 256) { + dut.clock.step() + cycles += 1 + } + dut.io.branchCount.expect(1.U) + dut.io.recoveryApplyCount.expect(1.U) + dut.io.cmdIssueCount.expect(0.U) + dut.io.iexTerminalTraceCount.expect((traceBefore + 1).U) + + dut.clock.step(8) + + // Recovery killed the original closing marker and therefore reopens the + // surviving branch's PC/BROB owners. Publish the redirected epoch's + // closing marker before requiring those owners to drain. + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(1.U) + val redirectedStop = dut.io.program.bits.entries.head + redirectedStop.kind.poke(FrontEndOpKind.Encoded64) + redirectedStop.parent.identity.peId.poke(1.U) + redirectedStop.parent.identity.stid.poke(0.U) + redirectedStop.parent.identity.instructionId.poke(60.U) + redirectedStop.parent.identity.epoch.poke(2.U) + redirectedStop.parent.pc.poke(0x7008.U) + redirectedStop.parent.instruction.poke(stop.value.U) + redirectedStop.parent.lengthBytes.poke(stop.lenBytes.U) + redirectedStop.parent.prediction.valid.poke(true.B) + redirectedStop.parent.prediction.requestPc.poke(0x7008.U) + redirectedStop.parent.prediction.fallthroughPc.poke(0x700c.U) + redirectedStop.parent.prediction.epoch.poke(2.U) + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + + cycles = 0 + while (dut.io.stid0CommitProgress.peek().litValue == 0 && cycles < 256) { + dut.clock.step() + cycles += 1 + } + dut.io.cmdReady.poke(true.B) + dut.clock.step(8) + dut.io.cmdIssueCount.expect(0.U) + assert(dut.io.stid0CommitProgress.peek().litValue > 0, + s"older open-current BRU recovery must kill the stalled younger CMD " + + s"and drain after redirected closure; " + + s"commit=${dut.io.stid0CommitProgress.peek().litValue}") + val commitProgress = dut.io.stid0CommitProgress.peek().litValue + dut.clock.step(16) + dut.io.stid0CommitProgress.expect(commitProgress.U) + dut.io.cmdIssueCount.expect(0.U) + } + } + + test("backlogged branch recovery fences its commit and permits peer STID progress") { + simulate(new OOOIEXLSUActivationProbe(OOOIEXLSUActivationParams.W4)) { dut => + initialize(dut) + + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val jump = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_J").get + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + + def sendClosed(stid: Int, bodyRaw: BigInt, bodyRule: + OooOpcodeRecipeRule, basePc: Int, + firstInstructionId: Int): Unit = { + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + val encodings = Seq( + (start, start.value, basePc), + (bodyRule, bodyRaw, basePc + 4), + (stop, stop.value, basePc + 8)) + dut.io.program.bits.count.poke(3.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(stid.U) + entry.parent.identity.instructionId.poke( + (firstInstructionId + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + } + + def sendPeerPair(): Unit = { + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + val addRaw = addi.value | (BigInt(5) << 7) | (BigInt(7) << 20) + val encodings = Seq( + (start, start.value, 0x5000), + (addi, addRaw, 0x5004), + (addi, addi.value | (BigInt(6) << 7) | + (BigInt(7) << 20), 0x5008), + (stop, stop.value, 0x500c)) + dut.io.program.bits.count.poke(4.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.program.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(1.U) + entry.parent.identity.instructionId.poke((16 + lane).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + } + + def sendRedirectStop(): Unit = { + dut.io.program.bits.poke(0.U.asTypeOf(dut.io.program.bits)) + dut.io.program.bits.count.poke(1.U) + val entry = dut.io.program.bits.entries.head + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke(32.U) + entry.parent.identity.epoch.poke(2.U) + entry.parent.pc.poke(0x4008.U) + entry.parent.instruction.poke(stop.value.U) + entry.parent.lengthBytes.poke(stop.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(0x4008.U) + entry.parent.prediction.fallthroughPc.poke(0x400c.U) + entry.parent.prediction.epoch.poke(2.U) + dut.io.program.valid.poke(true.B) + while (!dut.io.program.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.program.valid.poke(false.B) + } + + dut.io.recoveryReady.poke(false.B) + sendClosed(0, jump.value | (BigInt(2) << 15), jump, + basePc = 0x4000, firstInstructionId = 1) + var cycles = 0 + while (dut.io.bruCount.peek().litValue == 0 && cycles < 128) { + dut.clock.step() + cycles += 1 + } + dut.io.bruCount.expect(1.U) + dut.clock.step(16) + dut.io.branchCount.expect(0.U) + dut.io.stid0Progress.expect(0.U) + dut.io.stid0CommitProgress.expect(0.U) + + sendPeerPair() + cycles = 0 + while (dut.io.stid1Progress.peek().litValue == 0 && cycles < 128) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.stid1Progress.peek().litValue > 0, + s"the peer STID must resolve while branch recovery is backpressured; " + + s"alu=${dut.io.aluCount.peek().litValue} " + + s"rf=${dut.io.rfWriteCount.peek().litValue} " + + s"resolve=${dut.io.resolveCount.peek().litValue} " + + s"trace=${dut.io.iexTerminalTraceCount.peek().litValue}") + dut.io.stid0Progress.expect(0.U) + dut.io.stid0CommitProgress.expect(0.U) + dut.clock.step(8) + val traceCountBeforeRecovery = + dut.io.iexTerminalTraceCount.peek().litValue + + dut.io.recoveryReady.poke(true.B) + cycles = 0 + while ((dut.io.branchCount.peek().litValue == 0 || + dut.io.recoveryApplyCount.peek().litValue == 0 || + dut.io.stid0Progress.peek().litValue == 0) && cycles < 256) { + dut.clock.step() + cycles += 1 + } + dut.clock.step(8) + dut.io.branchCount.expect(1.U) + dut.io.recoveryApplyCount.expect(1.U) + dut.io.stid0Progress.expect(1.U) + dut.io.iexTerminalTraceCount.expect((traceCountBeforeRecovery + 2).U) + dut.clock.step(16) + if (dut.io.stid0CommitProgress.peek().litValue == 0) { + sendRedirectStop() + } + cycles = 0 + while (dut.io.stid0CommitProgress.peek().litValue == 0 && cycles < 256) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.stid0CommitProgress.peek().litValue > 0, + s"surviving branch block must close and release after redirected " + + s"target lifecycle; commit=${dut.io.stid0CommitProgress.peek().litValue}") + val commitProgress = dut.io.stid0CommitProgress.peek().litValue + dut.clock.step(16) + dut.io.branchCount.expect(1.U) + dut.io.recoveryApplyCount.expect(1.U) + dut.io.stid0CommitProgress.expect(commitProgress.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/OooIexLoadTerminalMetadataSpec.scala b/chisel/src/test/scala/linxcore/iex/OooIexLoadTerminalMetadataSpec.scala new file mode 100644 index 00000000..fc43cc82 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/OooIexLoadTerminalMetadataSpec.scala @@ -0,0 +1,727 @@ +package linxcore.iex + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +import linxcore.common.{CoreParams, DestinationKind, ScalarLsuParams} +import linxcore.ooo._ +import linxcore.top.interface.RecoveryPhase + +class OooIexLoadTerminalMetadataSpec extends AnyFunSuite with ChiselSim { + private val p = OooParams( + stidCount = 4, + instructionDecodeWidth = 2, + decodedUopWidth = 2, + renameWidth = 2, + dispatchWidth = 2, + retireGroupWidth = 2, + robGroupsPerStid = 8, + robIdentityGroupsPerStid = 64, + robBankCount = 2, + robRecoveryScanGroupsPerCycle = 2, + robNonFlushScanGroupsPerCycle = 2, + brobEntriesPerStid = 16, + pcBufferEntries = 16, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 2, + pcWritePorts = 3, + iqBankCount = 2, + iqEntriesPerBank = 4, + iqFreeSelectLeafEntries = 2, + tuRetireSourceDepthPerStid = 16, + lsidWidth = 40) + + private val core = CoreParams( + robEntries = 64, + lsidWidth = 40, + scalarLsu = ScalarLsuParams( + stqEntries = 4, + liqEntries = 4, + loadReturnPipeCount = 3, + stidCount = 4)) + + test("fixture preserves a wide ROB identity projection over bounded physical rows") { + assert(p.robGroupsPerStid == 8) + assert(p.robIdentityGroupsPerStid == 64) + assert(core.robEntries == p.robIdentityGroupsPerStid) + assert(p.ridSlotWidth == 6) + } + + test("derives the W4 two-lane terminal geometry from the canonical LSU profile") { + val twoPipeCore = core.copy( + scalarLsu = core.scalarLsu.copy(loadReturnPipeCount = 2)) + + simulate(new OooIexLoadTerminalMetadata(p, twoPipeCore)) { dut => + assert(dut.io.speculativeWakeup.length == 2) + assert(dut.io.loadCancel.length == 2) + assert(dut.io.loadBypass.length == 2) + } + } + + private def defaults(dut: OooIexLoadTerminalMetadata): Unit = { + dut.io.alloc.valid.poke(false.B) + dut.io.alloc.bits.poke(0.U.asTypeOf(dut.io.alloc.bits)) + dut.io.rebind.valid.poke(false.B) + dut.io.rebind.bits.poke(0.U.asTypeOf(dut.io.rebind.bits)) + dut.io.attemptLaunch.valid.poke(false.B) + dut.io.attemptLaunch.bits.poke( + 0.U.asTypeOf(dut.io.attemptLaunch.bits)) + dut.io.completion.valid.poke(false.B) + dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) + dut.io.result.ready.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke( + 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke( + 0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke( + 0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + + private def pokeMember( + member: RobMemberKey, + ridSlot: Int, + memberIndex: Int = 1, + stid: Int = 1): Unit = { + member.poke(0.U.asTypeOf(member)) + member.group.valid.poke(true.B) + member.group.peId.poke(3.U) + member.group.stid.poke(stid.U) + member.group.ridSlot.poke(ridSlot.U) + member.group.ridGeneration.poke(5.U) + member.bid.valid.poke(true.B) + member.bid.value.poke((ridSlot + 4).U) + member.brobGeneration.poke(9.U) + member.memberIndex.poke(memberIndex.U) + member.residentGeneration.poke(11.U) + } + + private def pokeAttemptFromLoad( + attempt: linxcore.lsu.LoadAttemptIdentity, + load: OooIexLoadGeneration): Unit = { + attempt.poke(0.U.asTypeOf(attempt)) + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(load.producer.group.peId.peek()) + attempt.producer.stid.poke(load.producer.group.stid.peek()) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke(load.producer.bid.value.peek()) + attempt.producer.brobGeneration.poke( + load.producer.brobGeneration.peek()) + attempt.producer.ridSlot.poke(load.producer.group.ridSlot.peek()) + attempt.producer.ridGeneration.poke( + load.producer.group.ridGeneration.peek()) + attempt.producer.memberIndex.poke(load.producer.memberIndex.peek()) + attempt.producer.residentGeneration.poke( + load.producer.residentGeneration.peek()) + attempt.transactionValue.poke(load.transaction.value.peek()) + attempt.transactionGeneration.poke(load.transaction.generation.peek()) + attempt.generation.poke(load.generation.peek()) + } + + private def pokeRebind( + dut: OooIexLoadTerminalMetadata, + slot: Int, + ridSlot: Int, + currentGeneration: Int, + nextGeneration: Int, + transactionValue: BigInt, + transactionGeneration: BigInt): Unit = { + val rebind = dut.io.rebind.bits + rebind.poke(0.U.asTypeOf(rebind)) + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(slot.U) + rebind.currentLoad.valid.poke(true.B) + pokeMember(rebind.currentLoad.producer, ridSlot) + rebind.currentLoad.transaction.value.poke(transactionValue.U) + rebind.currentLoad.transaction.generation.poke(transactionGeneration.U) + rebind.currentLoad.generation.poke(currentGeneration.U) + pokeAttemptFromLoad(rebind.currentAttempt, rebind.currentLoad) + rebind.nextLoad.valid.poke(true.B) + pokeMember(rebind.nextLoad.producer, ridSlot) + rebind.nextLoad.transaction.value.poke(transactionValue.U) + rebind.nextLoad.transaction.generation.poke(transactionGeneration.U) + rebind.nextLoad.generation.poke(nextGeneration.U) + pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) + dut.io.rebind.valid.poke(true.B) + } + + private def pokeAlloc( + dut: OooIexLoadTerminalMetadata, + slot: Int, + rowGeneration: Int, + ridSlot: Int, + attemptGeneration: Int, + stid: Int = 1, + transactionValue: BigInt = 0, + transactionGeneration: BigInt = 0, + tDestination: Boolean = false): Unit = { + val alloc = dut.io.alloc.bits + alloc.poke(0.U.asTypeOf(alloc)) + alloc.loadId.valid.poke(true.B) + alloc.loadId.slot.poke(slot.U) + alloc.loadId.generation.poke(rowGeneration.U) + alloc.load.valid.poke(true.B) + pokeMember(alloc.load.producer, ridSlot, stid = stid) + alloc.load.transaction.value.poke(transactionValue.U) + alloc.load.transaction.generation.poke(transactionGeneration.U) + alloc.load.generation.poke(attemptGeneration.U) + + val row = alloc.request.execute.i2.row + row.schedule.valid.poke(true.B) + row.schedule.peId.poke(3.U) + row.schedule.stid.poke(stid.U) + row.schedule.epoch.poke(7.U) + row.schedule.memoryTransactionValid.poke(true.B) + row.schedule.memoryTransaction.value.poke(transactionValue.U) + row.schedule.memoryTransaction.generation.poke(transactionGeneration.U) + row.schedule.initialLoadAttemptValid.poke(true.B) + row.schedule.initialLoadAttemptGeneration.poke(attemptGeneration.U) + pokeMember(row.schedule.member, ridSlot, stid = stid) + row.schedule.destinations(0).valid.poke(true.B) + row.schedule.destinations(0).kind.poke( + (if (tDestination) DestinationKind.T else DestinationKind.Gpr)) + row.schedule.destinations(0).atag.poke((if (tDestination) 31 else 6).U) + if (tDestination) { + row.schedule.destinations(0).relativeIndex.poke(2.U) + row.schedule.destinations(0).localTag.poke((3 + slot).U) + row.schedule.destinations(0).localSequence.valid.poke(true.B) + row.schedule.destinations(0).localSequence.index.poke((9 + slot).U) + row.schedule.destinations(0).localSequence.generation.poke(4.U) + row.payload.previousPDestinations(0).valid.poke(false.B) + } else { + row.schedule.destinations(0).ptag.poke((31 + slot).U) + row.schedule.destinations(0).ptagGeneration.poke(4.U) + row.payload.previousPDestinations(0).valid.poke(true.B) + row.payload.previousPDestinations(0).ptag.poke((21 + slot).U) + row.payload.previousPDestinations(0).ptagGeneration.poke(3.U) + } + alloc.request.destination.poke(row.schedule.destinations(0).peek()) + alloc.request.address.poke((0x8000 + slot * 8).U) + alloc.request.accessBytes.poke(8.U) + pokeAttemptFromLoad(alloc.attempt, alloc.load) + dut.io.alloc.valid.poke(true.B) + } + + private def acceptAlloc(dut: OooIexLoadTerminalMetadata): Unit = { + dut.io.alloc.ready.expect(true.B) + dut.clock.step() + dut.io.alloc.valid.poke(false.B) + } + + private def pokeCompletion( + dut: OooIexLoadTerminalMetadata, + slot: Int, + rowGeneration: Int, + ridSlot: Int, + attemptGeneration: Int, + fault: Boolean = false, + stid: Int = 1, + transactionValue: BigInt = 0, + transactionGeneration: BigInt = 0, + pipeIndex: Int = 0, + tDestination: Boolean = false): Unit = { + val completion = dut.io.completion.bits + completion.poke(0.U.asTypeOf(completion)) + completion.peId.poke(3.U) + completion.stid.poke(stid.U) + completion.tid.poke(stid.U) + completion.payload.valid.poke(true.B) + completion.payload.loadId.valid.poke(true.B) + completion.payload.loadId.slot.poke(slot.U) + completion.payload.loadId.generation.poke(rowGeneration.U) + completion.payload.attempt.valid.poke(true.B) + completion.payload.attempt.producer.valid.poke(true.B) + completion.payload.attempt.producer.peId.poke(3.U) + completion.payload.attempt.producer.stid.poke(stid.U) + completion.payload.attempt.producer.nativeBidValid.poke(true.B) + completion.payload.attempt.producer.nativeBid.poke((ridSlot + 4).U) + completion.payload.attempt.producer.brobGeneration.poke(9.U) + completion.payload.attempt.producer.ridSlot.poke(ridSlot.U) + completion.payload.attempt.producer.ridGeneration.poke(5.U) + completion.payload.attempt.producer.memberIndex.poke(1.U) + completion.payload.attempt.producer.residentGeneration.poke(11.U) + completion.payload.attempt.transactionValue.poke(transactionValue.U) + completion.payload.attempt.transactionGeneration.poke( + transactionGeneration.U) + completion.payload.attempt.generation.poke(attemptGeneration.U) + completion.payload.transactionValid.poke(true.B) + completion.payload.transactionValue.poke(transactionValue.U) + completion.payload.transactionGeneration.poke(transactionGeneration.U) + completion.payload.pipeIndex.poke(pipeIndex.U) + completion.payload.dst.valid.poke(true.B) + completion.payload.dst.kind.poke( + (if (tDestination) DestinationKind.T else DestinationKind.Gpr)) + completion.payload.dst.archTag.poke((if (tDestination) 31 else 6).U) + completion.payload.dst.relTag.poke((if (tDestination) 2 else 0).U) + completion.payload.dst.physTag.poke( + (if (tDestination) 3 + slot else 31 + slot).U) + completion.payload.dst.oldPhysTag.poke( + (if (tDestination) 0 else 21 + slot).U) + completion.payload.data.poke( + (if (fault) BigInt(0) else BigInt("1122334455667788", 16)).U) + completion.payload.faultValid.poke(fault.B) + completion.payload.faultCause.poke((if (fault) 0x55 else 0).U) + dut.io.completion.valid.poke(true.B) + } + + test("retains exact terminal metadata under backpressure and clears only on atomic fire") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 2, rowGeneration = 1, ridSlot = 3, + attemptGeneration = 7) + acceptAlloc(dut) + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 2, rowGeneration = 1, ridSlot = 3, + attemptGeneration = 7) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(false.B) + dut.io.result.bits.agu.destination.ptag.expect(33.U) + dut.io.result.bits.agu.destination.ptagGeneration.expect(4.U) + dut.io.result.bits.data.expect(BigInt("1122334455667788", 16).U) + dut.clock.step(3) + dut.io.occupied.expect(1.U) + dut.io.result.valid.expect(true.B) + + // The canonical LIQ slot cannot be reused while its terminal metadata + // still owns the older physical row lease. + pokeAlloc(dut, slot = 2, rowGeneration = 0, ridSlot = 4, + attemptGeneration = 8) + dut.io.alloc.ready.expect(false.B) + dut.io.allocRejected.valid.expect(true.B) + dut.io.allocRejected.bits.resident.expect(true.B) + dut.io.alloc.valid.poke(false.B) + + dut.io.result.ready.poke(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.result.ready.poke(false.B) + dut.io.empty.expect(true.B) + } + } + + test("retains a compact-load T destination through terminal publication") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, tDestination = true) + acceptAlloc(dut) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, tDestination = true) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.agu.destination.kind.expect(DestinationKind.T) + dut.io.result.bits.agu.destination.atag.expect(31.U) + dut.io.result.bits.agu.destination.relativeIndex.expect(2.U) + dut.io.result.bits.agu.destination.localTag.expect(4.U) + dut.io.result.bits.agu.destination.localSequence.valid.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.empty.expect(true.B) + } + } + + test("rejects allocation that does not match the IQ-retained transaction and initial attempt") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 0, rowGeneration = 0, ridSlot = 1, + attemptGeneration = 7, transactionValue = 19, + transactionGeneration = 3) + + dut.io.alloc.bits.request.execute.i2.row.schedule.memoryTransaction.value + .poke(20.U) + dut.io.alloc.ready.expect(false.B) + dut.io.allocRejected.valid.expect(true.B) + dut.io.allocRejected.bits.producerExact.expect(false.B) + + dut.io.alloc.bits.request.execute.i2.row.schedule.memoryTransaction.value + .poke(19.U) + dut.io.alloc.bits.request.execute.i2.row.schedule + .initialLoadAttemptGeneration.poke(8.U) + dut.io.alloc.ready.expect(false.B) + dut.io.allocRejected.valid.expect(true.B) + dut.io.allocRejected.bits.attemptExact.expect(false.B) + } + } + + test("requires exact rebind generation and rejects the stale attempt after replay") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3) + acceptAlloc(dut) + + val rebind = dut.io.rebind.bits + rebind.poke(0.U.asTypeOf(rebind)) + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(1.U) + rebind.currentLoad.valid.poke(true.B) + pokeMember(rebind.currentLoad.producer, ridSlot = 2) + rebind.currentLoad.transaction.value.poke(19.U) + rebind.currentLoad.transaction.generation.poke(3.U) + rebind.currentLoad.generation.poke(5.U) + pokeAttemptFromLoad(rebind.currentAttempt, rebind.currentLoad) + rebind.nextLoad.valid.poke(true.B) + pokeMember(rebind.nextLoad.producer, ridSlot = 2) + rebind.nextLoad.transaction.value.poke(20.U) + rebind.nextLoad.transaction.generation.poke(3.U) + rebind.nextLoad.generation.poke(6.U) + pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) + dut.io.rebind.valid.poke(true.B) + dut.io.rebind.ready.expect(false.B) + dut.io.rebindRejected.valid.expect(true.B) + + rebind.nextLoad.transaction.value.poke(19.U) + pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) + dut.io.rebind.ready.expect(true.B) + dut.clock.step() + dut.io.rebind.valid.poke(false.B) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 7, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 4, transactionValue = 19, + transactionGeneration = 3) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 20, + transactionGeneration = 3) + dut.io.completion.ready.expect(true.B) + dut.io.completionRejected.bits.transactionExact.expect(false.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3, pipeIndex = 1) + dut.io.completion.ready.expect(true.B) + dut.io.completionRejected.bits.pipeExact.expect(false.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3) + dut.io.completion.bits.payload.valid.poke(false.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3) + dut.io.occupied.expect(1.U) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B) + dut.io.completionRejected.valid.expect(true.B) + dut.io.completionRejected.bits.attemptExact.expect(false.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 6, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.load.transaction.value.expect(19.U) + dut.io.result.bits.load.transaction.generation.expect(3.U) + dut.io.result.bits.load.generation.expect(6.U) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.empty.expect(true.B) + } + } + + test("three replays need no stale completion capacity and drain old attempts in arbitrary order") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3) + acceptAlloc(dut) + + pokeRebind(dut, slot = 1, ridSlot = 2, currentGeneration = 5, + nextGeneration = 6, transactionValue = 19, + transactionGeneration = 3) + dut.io.rebind.ready.expect(true.B) + dut.clock.step() + pokeRebind(dut, slot = 1, ridSlot = 2, currentGeneration = 6, + nextGeneration = 7, transactionValue = 19, + transactionGeneration = 3) + dut.io.rebind.ready.expect(true.B) + dut.clock.step() + pokeRebind(dut, slot = 1, ridSlot = 2, currentGeneration = 7, + nextGeneration = 8, transactionValue = 19, + transactionGeneration = 3) + dut.io.rebind.ready.expect(true.B, + "rebind liveness must not depend on a finite stale-attempt table") + dut.clock.step() + dut.io.rebind.valid.poke(false.B) + dut.io.result.ready.poke(true.B) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 9, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(false.B) + dut.io.completionRejected.valid.expect(true.B) + dut.io.completion.ready.expect(true.B, + "a future untracked attempt must reject-and-drain") + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 7, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 5, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B, + "an arbitrarily old attempt must reject-and-drain without retained history") + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 6, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, + attemptGeneration = 8, transactionValue = 19, + transactionGeneration = 3) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.empty.expect(true.B) + } + } + + test("recovery fences terminal publication and prunes only the exact killed member") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 0, rowGeneration = 0, ridSlot = 1, + attemptGeneration = 1) + acceptAlloc(dut) + pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 2) + acceptAlloc(dut) + pokeAlloc(dut, slot = 2, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 3, stid = 2) + acceptAlloc(dut) + dut.io.occupied.expect(3.U) + + val plan = dut.io.recoveryPrepare.bits + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(73.U) + plan.phase.poke(RecoveryPhase.Prepare) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(1.U) + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(1.U) + plan.firstKilled.ridSlot.poke(3.U) + plan.firstKilled.ridGeneration.poke(5.U) + plan.firstKilled.memberIndex.poke(1.U) + plan.lastKilled.poke(plan.firstKilled.peek()) + plan.killedGroupCount.poke(1.U) + plan.killedMemberCount.poke(1.U) + dut.io.recoveryPrepareReady.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepared.valid.expect(false.B) + dut.io.occupied.expect(3.U) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepareReady.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepared.valid.expect(true.B) + dut.io.recoveryPrepared.bits.transactionId.expect(73.U) + dut.io.recoveryKilledMask.expect(2.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 2, fault = true) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(false.B) + + // A peer completion is not fenced by the target-STID recovery. + pokeCompletion(dut, slot = 2, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 3, stid = 2) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.occupied.expect(2.U) + + // A target-STID allocation remains held, while the same free canonical + // slot can be allocated immediately by a peer STID. + pokeAlloc(dut, slot = 2, rowGeneration = 1, ridSlot = 4, + attemptGeneration = 4, stid = 1) + dut.io.alloc.ready.expect(false.B) + pokeAlloc(dut, slot = 2, rowGeneration = 1, ridSlot = 4, + attemptGeneration = 4, stid = 2) + acceptAlloc(dut) + dut.io.occupied.expect(3.U) + + val rebind = dut.io.rebind.bits + rebind.poke(0.U.asTypeOf(rebind)) + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(1.U) + rebind.currentLoad.valid.poke(true.B) + pokeMember(rebind.currentLoad.producer, ridSlot = 3, stid = 1) + rebind.currentLoad.generation.poke(2.U) + pokeAttemptFromLoad(rebind.currentAttempt, rebind.currentLoad) + rebind.nextLoad.valid.poke(true.B) + pokeMember(rebind.nextLoad.producer, ridSlot = 3, stid = 1) + rebind.nextLoad.generation.poke(3.U) + pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) + dut.io.rebind.valid.poke(true.B) + dut.io.rebind.ready.expect(false.B) + + rebind.loadId.slot.poke(2.U) + rebind.loadId.generation.poke(1.U) + pokeMember(rebind.currentLoad.producer, ridSlot = 4, stid = 2) + rebind.currentLoad.generation.poke(4.U) + pokeAttemptFromLoad(rebind.currentAttempt, rebind.currentLoad) + pokeMember(rebind.nextLoad.producer, ridSlot = 4, stid = 2) + rebind.nextLoad.generation.poke(5.U) + pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) + dut.io.rebind.ready.expect(true.B) + dut.clock.step() + dut.io.rebind.valid.poke(false.B) + + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recoveryApply.bits.transactionId.poke(74.U) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApplyAccepted.expect(false.B) + dut.io.recoveryApplyRejected.expect(true.B) + dut.clock.step() + dut.io.occupied.expect(3.U) + + dut.io.recoveryApply.bits.transactionId.poke(73.U) + pokeCompletion(dut, slot = 2, rowGeneration = 1, ridSlot = 4, + attemptGeneration = 5, stid = 2) + dut.io.recoveryApplyAccepted.expect(true.B) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.completion.valid.poke(false.B) + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 0, rowGeneration = 0, ridSlot = 1, + attemptGeneration = 1, fault = true) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.faultValid.expect(true.B) + dut.io.result.bits.faultCause.expect(0x55.U) + dut.io.result.bits.data.expect(0.U) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.empty.expect(true.B) + } + } + + test("accepts only the matching recovery abort and retains every metadata entry") { + simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => + defaults(dut) + pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 9) + acceptAlloc(dut) + pokeAlloc(dut, slot = 2, rowGeneration = 0, ridSlot = 4, + attemptGeneration = 10, stid = 2) + acceptAlloc(dut) + + val prepare = dut.io.recoveryPrepare.bits + prepare.poke(0.U.asTypeOf(prepare)) + prepare.transactionId.poke(91.U) + prepare.phase.poke(RecoveryPhase.Prepare) + prepare.trigger.peId.poke(3.U) + prepare.trigger.stid.poke(1.U) + prepare.firstKilledValid.poke(true.B) + prepare.firstKilled.peId.poke(3.U) + prepare.firstKilled.stid.poke(1.U) + prepare.firstKilled.ridSlot.poke(3.U) + prepare.firstKilled.ridGeneration.poke(5.U) + prepare.firstKilled.memberIndex.poke(1.U) + prepare.lastKilled.poke(prepare.firstKilled.peek()) + prepare.killedGroupCount.poke(1.U) + prepare.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepareReady.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepared.valid.expect(true.B) + dut.io.occupied.expect(2.U) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepareReady.expect(false.B) + dut.io.recoveryRejected.expect(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(92.U) + dut.io.recoveryPrepareReady.expect(false.B) + dut.io.recoveryRejected.expect(true.B) + dut.io.recoveryPrepare.valid.poke(false.B) + + dut.io.recoveryAbort.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.io.recoveryAbort.bits.transactionId.poke(92.U) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbortAccepted.expect(false.B) + dut.io.recoveryAbortRejected.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepared.valid.expect(true.B) + dut.io.occupied.expect(2.U) + + dut.io.recoveryAbort.bits.transactionId.poke(91.U) + pokeCompletion(dut, slot = 2, rowGeneration = 0, ridSlot = 4, + attemptGeneration = 10, stid = 2) + dut.io.result.ready.poke(true.B) + dut.io.recoveryAbortAccepted.expect(true.B) + dut.io.recoveryAbortRejected.expect(false.B) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.completion.valid.poke(false.B) + dut.io.recoveryPrepared.valid.expect(false.B) + dut.io.occupied.expect(1.U) + + pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 3, + attemptGeneration = 9) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.empty.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/iex/Task15WarningMatrixSpec.scala b/chisel/src/test/scala/linxcore/iex/Task15WarningMatrixSpec.scala new file mode 100644 index 00000000..1b60f694 --- /dev/null +++ b/chisel/src/test/scala/linxcore/iex/Task15WarningMatrixSpec.scala @@ -0,0 +1,21 @@ +package linxcore.ooo + +import circt.stage.ChiselStage +import linxcore.iex.IEX +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +/** Bounded elaboration-only warning matrix for the reviewed Task-15 owners. */ +class Task15WarningMatrixSpec extends AnyFunSuite { + test("W2 W4 W6 W8 IEX and ROB warning matrix") { + Seq(2, 4, 6, 8).foreach { width => + println(s"TASK15_WARNING_MATRIX_BEGIN W$width") + val p = SimulationParamProfiles.forWidth(width) + ChiselStage.emitCHIRRTL(new IEX(p)) + ChiselStage.emitCHIRRTL(new ROB(p)) + ChiselStage.emitCHIRRTL(new PRename(p)) + ChiselStage.emitCHIRRTL(new BROB(p)) + println(s"TASK15_WARNING_MATRIX_END W$width") + } + } +} diff --git a/chisel/src/test/scala/linxcore/ifu/IFUCTUIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ifu/IFUCTUIntegrationSpec.scala new file mode 100644 index 00000000..55fadc17 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ifu/IFUCTUIntegrationSpec.scala @@ -0,0 +1,113 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import linxcore.params.ParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class IFUCTUIntegrationSpec extends AnyFunSuite with ChiselSim { + private def clear(dut: IFU): Unit = { + dut.io.toCtu.ready.poke(false.B) + dut.io.memoryRequest.ready.poke(false.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.trace.ready.poke(true.B) + } + + private def serveMemoryUntilCtu(dut: IFU, limit: Int = 600): Unit = { + var cycles = 0 + while (!dut.io.toCtu.valid.peek().litToBoolean && cycles < limit) { + if (dut.io.memoryRequest.valid.peek().litToBoolean) { + val request = dut.io.memoryRequest.bits.peek() + val address = request.address.litValue + val value = request.identity.value.litValue + val generation = request.identity.generation.litValue + val accessKind = request.accessKind.litValue + dut.clock.step() + + val data = + if (accessKind == MemoryAccessKind.InstructionTranslation.litValue) { + address >> 8 + } else { + BigInt("0008000600040002", 16) + } + dut.io.memoryResponse.valid.poke(true.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.value.poke(value.U) + dut.io.memoryResponse.bits.identity.generation.poke(generation.U) + dut.io.memoryResponse.bits.data.poke(data.U) + dut.io.memoryResponse.ready.expect(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + } else { + dut.clock.step() + } + cycles += 1 + } + assert(cycles < limit, "IFU did not deliver a CTU packet") + } + + test("W2 W4 W6 and W8 public IFU retain fixed 64-bit CTU traffic backpressure and scoped recovery") { + Seq(2, 4, 6, 8).foreach { width => + val p = ParamProfiles.forWidth(width) + assert(p.instructionWidth == 64) + simulate(new IFU(p)) { dut => + assert(dut.io.toCtu.bits.entries.length == width) + assert(dut.io.toCtu.bits.entries(0).instruction.getWidth == 64) + clear(dut) + dut.io.memoryRequest.ready.poke(true.B) + serveMemoryUntilCtu(dut) + + dut.io.toCtu.valid.expect(true.B) + val heldPc = dut.io.toCtu.bits.entries(0).pc.peek().litValue + val heldInstruction = dut.io.toCtu.bits.entries(0).instruction.peek().litValue + dut.clock.step(4) + dut.io.toCtu.valid.expect(true.B) + assert(dut.io.toCtu.bits.entries(0).pc.peek().litValue == heldPc) + assert(dut.io.toCtu.bits.entries(0).instruction.peek().litValue == heldInstruction) + + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(99.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.bits.redirectPc.poke(0x80.U) + dut.io.recovery.prepare.bits.newEpoch.poke(3.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.toCtu.valid.expect(false.B) + + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.transactionId.poke(99.U) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.apply.bits.trigger.stid.poke(0.U) + dut.io.recovery.apply.bits.redirectPc.poke(0x80.U) + dut.io.recovery.apply.bits.newEpoch.poke(3.U) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + } + } + } + + test("W2 W4 W6 and W8 IFU elaboration exposes explicit prediction and recovery boundaries") { + Seq(2, 4, 6, 8).foreach { width => + val sv = ChiselStage.emitSystemVerilog(new IFU(ParamProfiles.forWidth(width))) + assert(sv.contains("module IFU")) + assert(sv.contains("module BSide")) + assert(sv.contains("module IFURecovery")) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala b/chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala new file mode 100644 index 00000000..af10f13c --- /dev/null +++ b/chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala @@ -0,0 +1,367 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import linxcore.params.ParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class IFUISideSpec extends AnyFunSuite with ChiselSim { + private def clearFetchBuffer(dut: FetchBuffer): Unit = { + dut.io.enq.valid.poke(false.B) + dut.io.enq.bits.poke(0.U.asTypeOf(dut.io.enq.bits)) + dut.io.deq.ready.poke(false.B) + dut.io.prune.valid.poke(false.B) + dut.io.prune.bits.poke(0.U.asTypeOf(dut.io.prune.bits)) + } + + private def enqueueFour( + dut: FetchBuffer, + baseId: Int, + stid: Int, + lengths: Seq[Int] = Seq(2, 4, 6, 8)): Unit = { + dut.io.enq.bits.poke(0.U.asTypeOf(dut.io.enq.bits)) + dut.io.enq.bits.count.poke(4.U) + for (lane <- 0 until 4) { + dut.io.enq.bits.entries(lane).identity.stid.poke(stid.U) + dut.io.enq.bits.entries(lane).identity.instructionId.poke((baseId + lane).U) + dut.io.enq.bits.entries(lane).pc.poke((0x1000 + (baseId + lane) * 2).U) + dut.io.enq.bits.entries(lane).instruction.poke((0x100 + baseId + lane).U) + dut.io.enq.bits.entries(lane).lengthBytes.poke(lengths(lane).U) + } + dut.io.enq.valid.poke(true.B) + dut.io.enq.ready.expect(true.B) + dut.clock.step() + dut.io.enq.valid.poke(false.B) + } + + test("repacketizes the retained instruction stream for W2 W4 W6 and W8") { + Seq(2, 4, 6, 8).foreach { width => + val p = ParamProfiles.forWidth(width) + simulate(new FetchBuffer(p, ingressWidth = 4, depth = 16)) { dut => + clearFetchBuffer(dut) + enqueueFour(dut, baseId = 10, stid = 0) + + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.count.expect(math.min(width, 4).U) + for (lane <- 0 until math.min(width, 4)) { + dut.io.deq.bits.entries(lane).identity.instructionId.expect((10 + lane).U) + dut.io.deq.bits.entries(lane).lengthBytes.expect(Seq(2, 4, 6, 8)(lane).U) + } + + val heldCount = dut.io.deq.bits.count.peek().litValue + val heldIds = (0 until math.min(width, 4)).map( + lane => + dut.io.deq.bits.entries(lane).identity.instructionId.peek().litValue) + dut.clock.step(3) + assert(dut.io.deq.bits.count.peek().litValue == heldCount) + heldIds.zipWithIndex.foreach { case (id, lane) => + assert( + dut.io.deq.bits.entries(lane).identity.instructionId.peek().litValue == id) + } + + dut.io.deq.ready.poke(true.B) + dut.clock.step() + if (width == 2) { + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.count.expect(2.U) + dut.io.deq.bits.entries(0).identity.instructionId.expect(12.U) + dut.io.deq.bits.entries(1).identity.instructionId.expect(13.U) + } else { + dut.io.deq.valid.expect(false.B) + } + } + } + } + + test("scoped recovery removes only the selected STID and preserves survivor order") { + val base = ParamProfiles.W4 + val p = base.copy(ooo = base.ooo.copy(stidCount = 2)) + simulate(new FetchBuffer(p, ingressWidth = 4, depth = 16)) { dut => + clearFetchBuffer(dut) + enqueueFour(dut, baseId = 20, stid = 0) + enqueueFour(dut, baseId = 30, stid = 1) + + dut.io.prune.bits.poke(0.U.asTypeOf(dut.io.prune.bits)) + dut.io.prune.bits.trigger.stid.poke(0.U) + dut.io.prune.valid.poke(true.B) + dut.io.deq.valid.expect(false.B) + dut.clock.step() + dut.io.prune.valid.poke(false.B) + + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.count.expect(4.U) + for (lane <- 0 until 4) { + dut.io.deq.bits.entries(lane).identity.stid.expect(1.U) + dut.io.deq.bits.entries(lane).identity.instructionId.expect((30 + lane).U) + } + } + } + + test("the canonical IFU elaborates every principal delivery width") { + Seq(2, 4, 6, 8).foreach { width => + val sv = + ChiselStage.emitSystemVerilog(new IFU(ParamProfiles.forWidth(width))) + assert(sv.contains("module IFU")) + assert(sv.contains("module FetchBuffer")) + } + } + + test("replays ITLB and I-cache misses, rejects a stale response, and assembles a cross-line instruction") { + val base = ParamProfiles.W4 + val p = base.copy( + ooo = base.ooo.copy(stidCount = 2), + ifu = base.ifu.copy( + lineBytes = 16, + pageBytes = 256, + itlbEntries = 4, + l1iSets = 4, + missEntries = 4, + joinEntries = 4, + maxGroupsPerTransaction = 4, + resetVector = 0x10e)) + + simulate(new IFU(p)) { dut => + clearIfu(dut) + dut.io.memoryRequest.ready.poke(true.B) + + var staleInjected = false + var cycles = 0 + while (!dut.io.toCtu.valid.peek().litToBoolean && cycles < 600) { + if (dut.io.memoryRequest.valid.peek().litToBoolean) { + val request = dut.io.memoryRequest.bits.peek() + val address = request.address.litValue + val value = request.identity.value.litValue + val generation = request.identity.generation.litValue + val accessKind = request.accessKind.litValue + dut.clock.step() + + if (!staleInjected) { + dut.io.memoryResponse.valid.poke(true.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.value.poke((value + 1).U) + dut.io.memoryResponse.bits.identity.generation.poke(generation.U) + dut.io.memoryResponse.bits.data.poke(0xdead.U) + dut.io.memoryResponse.ready.expect(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + staleInjected = true + } + + val data = + if (accessKind == MemoryAccessKind.InstructionTranslation.litValue) { + BigInt(2) + } else { + if (address == BigInt(0x200)) { + BigInt(0) + } else if (address == BigInt(0x208)) { + BigInt(1) << 48 + } else if (address == BigInt(0x210)) { + BigInt(0x0010) + } else if (address == BigInt(0x218)) { + BigInt("0080007000600050", 16) + } else { + BigInt(0) + } + } + dut.io.memoryResponse.valid.poke(true.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.value.poke(value.U) + dut.io.memoryResponse.bits.identity.generation.poke(generation.U) + dut.io.memoryResponse.bits.data.poke(data.U) + dut.io.memoryResponse.ready.expect(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + } else { + dut.clock.step() + } + cycles += 1 + } + + assert(staleInjected, "test never exercised stale memory-response rejection") + assert(cycles < 600, "cross-line instruction did not reach CTU") + dut.io.toCtu.bits.count.expect(1.U) + dut.io.toCtu.bits.entries(0).pc.expect(0x10e.U) + dut.io.toCtu.bits.entries(0).lengthBytes.expect(4.U) + dut.io.toCtu.bits.entries(0).instruction.expect(0x00100001.U) + dut.io.toCtu.bits.entries(0).identity.stid.expect(0.U) + dut.io.memoryRequest.ready.poke(false.B) + + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(77.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.prepare.bits.trigger.stid.poke(1.U) + dut.io.recovery.prepare.bits.redirectPc.poke(0x300.U) + dut.io.recovery.prepare.bits.newEpoch.poke(9.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.bits.transactionId.expect(77.U) + dut.io.toCtu.valid.expect(false.B) + + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.transactionId.poke(77.U) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.apply.bits.trigger.stid.poke(1.U) + dut.io.recovery.apply.bits.redirectPc.poke(0x300.U) + dut.io.recovery.apply.bits.newEpoch.poke(9.U) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.toCtu.valid.expect(false.B) + + var recoveryCycles = 0 + while (!dut.io.recovery.prepare.ready.peek().litToBoolean && + recoveryCycles < 16) { + dut.clock.step() + recoveryCycles += 1 + } + assert(recoveryCycles < 16, "applied IFU recovery did not release its fence") + + dut.io.toCtu.valid.expect(true.B) + dut.io.toCtu.bits.entries(0).identity.stid.expect(0.U) + dut.io.trace.ready.poke(false.B) + dut.io.toCtu.ready.poke(true.B) + dut.clock.step() + + dut.io.memoryRequest.ready.poke(true.B) + var stidOneCycles = 0 + while ((!dut.io.toCtu.valid.peek().litToBoolean || + dut.io.toCtu.bits.entries(0).identity.stid.peek().litValue != 1) && + stidOneCycles < 600) { + if (dut.io.memoryRequest.valid.peek().litToBoolean) { + val request = dut.io.memoryRequest.bits.peek() + val address = request.address.litValue + val value = request.identity.value.litValue + val generation = request.identity.generation.litValue + val accessKind = request.accessKind.litValue + dut.clock.step() + + val data = + if (accessKind == MemoryAccessKind.InstructionTranslation.litValue) { + address >> 8 + } else { + BigInt(0) + } + dut.io.memoryResponse.valid.poke(true.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.value.poke(value.U) + dut.io.memoryResponse.bits.identity.generation.poke(generation.U) + dut.io.memoryResponse.bits.data.poke(data.U) + dut.io.memoryResponse.ready.expect(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + } else { + dut.clock.step() + } + stidOneCycles += 1 + } + assert(stidOneCycles < 600, "redirected STID did not make independent progress") + dut.io.toCtu.bits.entries(0).identity.stid.expect(1.U) + assert(dut.io.toCtu.bits.entries(0).pc.peek().litValue >= 0x300) + dut.io.trace.valid.expect(true.B) + dut.io.trace.bits.entries(0).instruction.stid.expect(0.U) + + dut.io.memoryRequest.ready.poke(false.B) + dut.io.toCtu.ready.poke(false.B) + dut.io.trace.ready.poke(true.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(78.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Exception) + dut.io.recovery.prepare.bits.trigger.stid.poke(1.U) + dut.io.recovery.prepare.bits.redirectPc.poke(0x400.U) + dut.io.recovery.prepare.bits.newEpoch.poke(10.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.transactionId.poke(78.U) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.bits.cause.poke(RecoveryCause.Exception) + dut.io.recovery.apply.bits.trigger.stid.poke(1.U) + dut.io.recovery.apply.bits.redirectPc.poke(0x400.U) + dut.io.recovery.apply.bits.newEpoch.poke(10.U) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + var faultRecoveryCycles = 0 + while (!dut.io.recovery.prepare.ready.peek().litToBoolean && + faultRecoveryCycles < 16) { + dut.clock.step() + faultRecoveryCycles += 1 + } + assert( + faultRecoveryCycles < 16, + "fault-path recovery did not release its fence") + + dut.io.toCtu.ready.poke(true.B) + dut.io.memoryRequest.ready.poke(true.B) + var faultCycles = 0 + while ((!dut.io.toCtu.valid.peek().litToBoolean || + !dut.io.toCtu.bits.entries(0).fetchFault.peek().litToBoolean || + dut.io.toCtu.bits.entries(0).identity.stid.peek().litValue != 1) && + faultCycles < 600) { + if (dut.io.memoryRequest.valid.peek().litToBoolean) { + val request = dut.io.memoryRequest.bits.peek() + val address = request.address.litValue + val value = request.identity.value.litValue + val generation = request.identity.generation.litValue + val accessKind = request.accessKind.litValue + dut.clock.step() + + dut.io.memoryResponse.valid.poke(true.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.value.poke(value.U) + dut.io.memoryResponse.bits.identity.generation.poke(generation.U) + if (accessKind == MemoryAccessKind.InstructionTranslation.litValue) { + dut.io.memoryResponse.bits.data.poke((address >> 8).U) + } else if (address >= 0x400 && address < 0x410) { + dut.io.memoryResponse.bits.denied.poke(true.B) + dut.io.memoryResponse.bits.errorCause.poke(0x55.U) + } + dut.io.memoryResponse.ready.expect(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + } else { + dut.clock.step() + } + faultCycles += 1 + } + assert(faultCycles < 600, "instruction-line error did not become a fetch fault") + dut.io.toCtu.bits.count.expect(1.U) + dut.io.toCtu.bits.entries(0).identity.stid.expect(1.U) + dut.io.toCtu.bits.entries(0).pc.expect(0x400.U) + dut.io.toCtu.bits.entries(0).fetchFault.expect(true.B) + dut.io.toCtu.bits.entries(0).fetchFaultCause.expect(0x55.U) + } + } + + private def clearIfu(dut: IFU): Unit = { + dut.io.toCtu.ready.poke(false.B) + dut.io.memoryRequest.ready.poke(false.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.trace.ready.poke(true.B) + } +} diff --git a/chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala b/chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala new file mode 100644 index 00000000..91cc66c9 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala @@ -0,0 +1,532 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import linxcore.common.{BoundaryKind, InterfaceParams} +import linxcore.frontend._ +import org.scalatest.funsuite.AnyFunSuite + +class IFUPredictionSpec extends AnyFunSuite with ChiselSim { + private val p = InterfaceParams() + private val lineBytes = 16 + + private def module = + new BSide( + p = p, + lineBytes = lineBytes, + threadCount = 1, + boundaryEntries = 8, + responseEntries = 8, + trainingEntries = 4, + nanoEntries = 8, + ubtbEntries = 8, + pbtbEntries = 8, + bimEntries = 8, + tageEntries = 8, + ibtbEntries = 8, + loopEntries = 8, + rasDepth = 8) + + private def clear(dut: BSide): Unit = { + dut.io.request.valid.poke(false.B) + dut.io.request.bits.poke(0.U.asTypeOf(dut.io.request.bits)) + dut.io.boundary.valid.poke(false.B) + dut.io.boundary.bits.poke(0.U.asTypeOf(dut.io.boundary.bits)) + dut.io.resolve.valid.poke(false.B) + dut.io.resolve.bits.poke(0.U.asTypeOf(dut.io.resolve.bits)) + dut.io.response.ready.poke(false.B) + dut.io.innerFlush.ready.poke(true.B) + dut.io.prune.poke(0.U.asTypeOf(dut.io.prune)) + } + + private def sendBoundary( + dut: BSide, + transactionId: Int, + requestPc: BigInt, + branchPc: BigInt = 0, + target: BigInt = 0, + fallthroughPc: BigInt = 0, + kind: BoundaryKind.Type = BoundaryKind.Fall, + staticTaken: Boolean = false, + hasBoundary: Boolean = true, + continuationReady: Boolean = true): Unit = { + dut.io.boundary.bits.poke(0.U.asTypeOf(dut.io.boundary.bits)) + dut.io.boundary.valid.poke(true.B) + dut.io.boundary.bits.valid.poke(hasBoundary.B) + dut.io.boundary.bits.peId.poke(1.U) + dut.io.boundary.bits.transactionId.poke(transactionId.U) + dut.io.boundary.bits.threadId.poke(0.U) + dut.io.boundary.bits.fetchPacketUid.poke(transactionId.U) + dut.io.boundary.bits.fetchSeq.poke(transactionId.U) + dut.io.boundary.bits.epoch.poke(0.U) + dut.io.boundary.bits.checkpointId.poke((transactionId & 0x1f).U) + dut.io.boundary.bits.branchPc.poke(branchPc.U) + dut.io.boundary.bits.target.poke(target.U) + val completedFallthrough = + if (!hasBoundary && fallthroughPc == 0) + (requestPc & ~BigInt(lineBytes - 1)) + lineBytes + else fallthroughPc + dut.io.boundary.bits.fallthroughPc.poke(completedFallthrough.U) + dut.io.boundary.bits.kind.poke(kind) + dut.io.boundary.bits.staticTaken.poke(staticTaken.B) + dut.io.boundary.bits.continuationReady.poke(continuationReady.B) + dut.io.boundary.ready.expect(true.B) + dut.clock.step() + dut.io.boundary.valid.poke(false.B) + } + + private def sendRequest(dut: BSide, transactionId: Int, pc: BigInt): Unit = { + dut.io.request.bits.poke(0.U.asTypeOf(dut.io.request.bits)) + dut.io.request.valid.poke(true.B) + dut.io.request.bits.pc.poke(pc.U) + dut.io.request.bits.lineVa.poke((pc & ~BigInt(lineBytes - 1)).U) + dut.io.request.bits.transactionId.poke(transactionId.U) + dut.io.request.bits.identity.peId.poke(1.U) + dut.io.request.bits.identity.threadId.poke(0.U) + dut.io.request.bits.identity.fetchPacketUid.poke(transactionId.U) + dut.io.request.bits.identity.fetchSeq.poke(transactionId.U) + dut.io.request.bits.identity.checkpointId.poke((transactionId & 0x1f).U) + dut.io.request.bits.identity.epoch.poke(0.U) + dut.io.request.ready.expect(true.B) + dut.clock.step() + dut.io.request.valid.poke(false.B) + } + + private def pokeResolve( + dut: BSide, + transactionId: Int, + predictionTag: Int, + requestPc: BigInt, + branchPc: BigInt, + target: BigInt, + fallthroughPc: BigInt, + kind: BoundaryKind.Type, + taken: Boolean, + mispredict: Boolean = false, + epoch: Int = 0): Unit = { + dut.io.resolve.bits.poke(0.U.asTypeOf(dut.io.resolve.bits)) + dut.io.resolve.valid.poke(true.B) + dut.io.resolve.bits.peId.poke(1.U) + dut.io.resolve.bits.transactionId.poke(transactionId.U) + dut.io.resolve.bits.predictionTag.poke(predictionTag.U) + dut.io.resolve.bits.threadId.poke(0.U) + dut.io.resolve.bits.fetchPacketUid.poke(transactionId.U) + dut.io.resolve.bits.fetchSeq.poke(transactionId.U) + dut.io.resolve.bits.epoch.poke(epoch.U) + dut.io.resolve.bits.checkpointId.poke((transactionId & 0x1f).U) + dut.io.resolve.bits.requestPc.poke(requestPc.U) + dut.io.resolve.bits.branchPc.poke(branchPc.U) + dut.io.resolve.bits.target.poke(target.U) + dut.io.resolve.bits.fallthroughPc.poke(fallthroughPc.U) + dut.io.resolve.bits.kind.poke(kind) + dut.io.resolve.bits.taken.poke(taken.B) + dut.io.resolve.bits.mispredict.poke(mispredict.B) + dut.io.resolve.ready.expect(true.B) + dut.clock.step() + dut.io.resolve.valid.poke(false.B) + } + + private def waitForFinal(dut: BSide, limit: Int = 32): Unit = { + dut.io.response.ready.poke(true.B) + var cycles = 0 + var finalSeen = false + while (!finalSeen && cycles < limit) { + finalSeen = + dut.io.response.valid.peek().litToBoolean && + dut.io.response.bits.finalResponse.peek().litToBoolean + if (!finalSeen) { + dut.clock.step() + cycles += 1 + } + } + assert(finalSeen, s"final prediction response missing after $cycles cycles") + } + + private def waitForResponse(dut: BSide, limit: Int = 24): Unit = { + var cycles = 0 + while (!dut.io.response.valid.peek().litToBoolean && cycles < limit) { + dut.clock.step() + cycles += 1 + } + assert(dut.io.response.valid.peek().litToBoolean, s"prediction response missing after $cycles cycles") + } + + private def applyCanonicalCorrection( + dut: BSide, + transactionId: Int, + predictionTag: Int, + taken: Boolean, + kind: BoundaryKind.Type, + oldEpoch: Int = 0, + newEpoch: Int = 1, + scope: IfuPruneScope.Type = IfuPruneScope.PreserveTriggerKillYounger, + reason: IfuInnerFlushReason.Type = IfuInnerFlushReason.PredictionCorrection, + rasPushAddress: BigInt = 0): Unit = { + dut.io.prune.poke(0.U.asTypeOf(dut.io.prune)) + dut.io.prune.valid.poke(true.B) + dut.io.prune.peId.poke(1.U) + dut.io.prune.threadId.poke(0.U) + dut.io.prune.transactionId.poke(transactionId.U) + dut.io.prune.fetchPacketUid.poke(transactionId.U) + dut.io.prune.fetchSeq.poke(transactionId.U) + dut.io.prune.oldEpoch.poke(oldEpoch.U) + dut.io.prune.newEpoch.poke(newEpoch.U) + dut.io.prune.checkpointId.poke((transactionId & 0x1f).U) + dut.io.prune.reason.poke(reason) + dut.io.prune.scope.poke(scope) + dut.io.prune.historyKeyValid.poke(true.B) + dut.io.prune.predictionTag.poke(predictionTag.U) + dut.io.prune.ghrAction.poke(GhrRecoveryAction.RestoreTrigger) + dut.io.prune.ghrAppendValid.poke((kind == BoundaryKind.Cond).B) + dut.io.prune.ghrAppendTaken.poke(taken.B) + dut.io.prune.rasAction.poke(RasRecoveryAction.RestoreTrigger) + dut.io.prune.rasUpdate.poke( + (if (!taken) RasUpdateAction.None + else if (kind == BoundaryKind.Call || kind == BoundaryKind.ICall) RasUpdateAction.Push + else if (kind == BoundaryKind.Ret) RasUpdateAction.Pop + else RasUpdateAction.None)) + dut.io.prune.rasPushAddress.poke(rasPushAddress.U) + dut.clock.step() + dut.io.prune.valid.poke(false.B) + } + + private def resetSpeculativeHistory(dut: BSide): Unit = { + dut.io.prune.poke(0.U.asTypeOf(dut.io.prune)) + dut.io.prune.valid.poke(true.B) + dut.io.prune.reason.poke(IfuInnerFlushReason.FetchReplay) + dut.io.prune.scope.poke(IfuPruneScope.KillAllThreadState) + dut.io.prune.ghrAction.poke(GhrRecoveryAction.Reset) + dut.io.prune.rasAction.poke(RasRecoveryAction.Reset) + dut.clock.step() + dut.io.prune.valid.poke(false.B) + } + + private def trainPrediction( + dut: BSide, + transactionId: Int, + requestPc: BigInt, + branchPc: BigInt, + target: BigInt, + fallthroughPc: BigInt, + kind: BoundaryKind.Type, + taken: Boolean): Int = { + sendBoundary( + dut = dut, + transactionId = transactionId, + requestPc = requestPc, + branchPc = branchPc, + target = target, + fallthroughPc = fallthroughPc, + kind = kind, + staticTaken = taken) + sendRequest(dut, transactionId, requestPc) + waitForFinal(dut) + val predictionTag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.clock.step() + dut.io.response.ready.poke(false.B) + applyCanonicalCorrection( + dut, + transactionId, + predictionTag, + taken, + kind, + rasPushAddress = fallthroughPc) + pokeResolve( + dut, + transactionId, + predictionTag, + requestPc, + branchPc, + target, + fallthroughPc, + kind, + taken, + epoch = 1) + dut.clock.step() + predictionTag + } + + private class ProviderRankProbe extends Module { + val io = IO(Output(Vec(6, UInt(Prediction.ProviderRankWidth.W)))) + io(0) := Prediction.providerRank(BSideStage.Sequential) + io(1) := Prediction.providerRank(BSideStage.BF0) + io(2) := Prediction.providerRank(BSideStage.BF1) + io(3) := Prediction.providerRank(BSideStage.BF2) + io(4) := Prediction.providerRank(BSideStage.BF3) + io(5) := Prediction.providerRank(BSideStage.BF4) + } + + private def bSideWithTables(nano: Int, ub: Int, pb: Int, bim: Int = -1, tage: Int = 8): BSide = + new BSide( + p = p, + lineBytes = lineBytes, + threadCount = 1, + boundaryEntries = 8, + responseEntries = 8, + trainingEntries = 4, + nanoEntries = nano, + ubtbEntries = ub, + pbtbEntries = pb, + bimEntries = if (bim < 0) pb else bim, + tageEntries = tage, + ibtbEntries = 8, + loopEntries = 8, + rasDepth = 8) + + test("B-SIDE provider order prefers BF4 over BF3 over BF2 over BF1 over BF0 over sequential") { + simulate(new ProviderRankProbe) { dut => + dut.io(0).expect(0.U) + dut.io(1).expect(1.U) + dut.io(2).expect(2.U) + dut.io(3).expect(3.U) + dut.io(4).expect(4.U) + dut.io(5).expect(5.U) + } + + simulate(module) { dut => + clear(dut) + sendRequest(dut, transactionId = 20, pc = 0x2000) + dut.clock.step(8) + dut.io.response.valid.expect(false.B) + sendBoundary(dut, transactionId = 20, requestPc = 0x2000, hasBoundary = false) + waitForResponse(dut) + dut.io.response.bits.finalResponse.expect(true.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Sequential) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF4) + dut.io.response.bits.prediction.fallthroughPc.expect(0x2010.U) + } + + simulate(module) { dut => + clear(dut) + + trainPrediction( + dut, + transactionId = 40, + requestPc = 0x3000, + branchPc = 0x3004, + target = 0x900, + fallthroughPc = 0x3006, + kind = BoundaryKind.Cond, + taken = true) + sendBoundary(dut, 3, 0x3000, 0x3004, 0x900, 0x3006, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 3, 0x3000) + waitForResponse(dut) + dut.io.response.bits.finalResponse.expect(false.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.NanoBtb) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF0) + } + + simulate(bSideWithTables(nano = 1, ub = 8, pb = 8)) { dut => + clear(dut) + trainPrediction(dut, 50, 0x5000, 0x5004, 0x5400, 0x5006, BoundaryKind.Direct, taken = true) + trainPrediction(dut, 51, 0x5010, 0x5014, 0x5410, 0x5016, BoundaryKind.Direct, taken = true) + sendBoundary(dut, 4, 0x5000, 0x5004, 0x5400, 0x5006, BoundaryKind.Direct, staticTaken = true) + sendRequest(dut, 4, 0x5000) + waitForResponse(dut) + dut.io.response.bits.finalResponse.expect(false.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.UBtb) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF1) + } + + simulate(bSideWithTables(nano = 1, ub = 1, pb = 8)) { dut => + clear(dut) + trainPrediction(dut, 60, 0x5200, 0x5204, 0x5600, 0x5206, BoundaryKind.Cond, taken = true) + trainPrediction(dut, 61, 0x5210, 0x5214, 0x5610, 0x5216, BoundaryKind.Cond, taken = true) + sendBoundary(dut, 5, 0x5200, 0x5204, 0x5600, 0x5206, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 5, 0x5200) + waitForResponse(dut) + dut.io.response.bits.finalResponse.expect(false.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Bim) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF2) + } + + simulate(bSideWithTables(nano = 1, ub = 1, pb = 16, bim = 1)) { dut => + clear(dut) + trainPrediction(dut, 80, 0x5300, 0x5304, 0x5700, 0x5306, BoundaryKind.Cond, taken = false) + trainPrediction(dut, 81, 0x5310, 0x5314, 0x5710, 0x5316, BoundaryKind.Cond, taken = true) + trainPrediction(dut, 82, 0x5330, 0x5334, 0x5730, 0x5336, BoundaryKind.Cond, taken = true) + trainPrediction(dut, 83, 0x5350, 0x5354, 0x5750, 0x5356, BoundaryKind.Cond, taken = true) + resetSpeculativeHistory(dut) + + sendBoundary(dut, 6, 0x5300, 0x5304, 0x5700, 0x5306, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 6, 0x5300) + waitForResponse(dut, limit = 32) + dut.io.response.bits.finalResponse.expect(false.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Bim) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF2) + dut.io.response.bits.prediction.taken.expect(true.B) + val bf2Tag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.io.response.ready.poke(true.B) + dut.clock.step() + dut.io.response.ready.poke(false.B) + applyCanonicalCorrection(dut, 6, bf2Tag, taken = true, BoundaryKind.Cond) + + waitForResponse(dut, limit = 32) + dut.io.response.bits.finalResponse.expect(false.B) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.ShortTage) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF3) + dut.io.response.bits.prediction.taken.expect(false.B) + } + + simulate(module) { dut => + clear(dut) + + sendBoundary(dut, 1, 0x1000, 0x1008, 0x1100, 0x1010, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 1, 0x1000) + waitForFinal(dut) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Static) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF4) + val tag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.clock.step() + dut.io.response.ready.poke(false.B) + + applyCanonicalCorrection(dut, 1, tag, taken = true, BoundaryKind.Cond) + pokeResolve(dut, 1, tag, 0x1000, 0x1008, 0x1100, 0x1010, BoundaryKind.Cond, taken = false) + + sendBoundary(dut, 9, 0x1000, 0x1008, 0x1200, 0x1010, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 9, 0x1000) + waitForFinal(dut) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF4) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.LongTage) + dut.io.response.bits.prediction.taken.expect(false.B) + dut.io.response.bits.prediction.target.expect(0x1200.U) + } + } + + test("stale training is rejected without mutating provider history") { + simulate(module) { dut => + clear(dut) + pokeResolve( + dut, + transactionId = 2, + predictionTag = 3, + requestPc = 0x2000, + branchPc = 0x2008, + target = 0x2200, + fallthroughPc = 0x2010, + kind = BoundaryKind.Cond, + taken = true) + dut.io.staleTraining.expect(true.B) + dut.io.historyCount.expect(0.U) + dut.clock.step() + + sendBoundary(dut, 10, 0x2000, 0x2008, 0x2100, 0x2010, BoundaryKind.Cond, staticTaken = false) + sendRequest(dut, 10, 0x2000) + waitForFinal(dut) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Static) + dut.io.response.bits.prediction.target.expect(0x2100.U) + } + } + + test("checkpoint-owned recovery restores exact GHR state and kills younger history") { + simulate(module) { dut => + clear(dut) + sendBoundary(dut, 11, 0x4100, 0x4104, 0x4400, 0x4106, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 11, 0x4100) + waitForFinal(dut) + val olderTag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.io.response.ready.poke(true.B) + dut.io.innerFlush.valid.expect(true.B) + dut.clock.step() + dut.io.response.ready.poke(false.B) + dut.io.speculativeGhr(0).expect(0.U) + + applyCanonicalCorrection(dut, 11, olderTag, taken = true, BoundaryKind.Cond) + dut.io.speculativeGhr(0).expect(1.U) + dut.io.historyCount.expect(1.U) + + sendRequest(dut, 12, 0x4200) + dut.io.historyCount.expect(2.U) + applyCanonicalCorrection(dut, 11, olderTag, taken = false, BoundaryKind.Cond) + dut.io.speculativeGhr(0).expect(0.U) + dut.io.historyCount.expect(1.U) + dut.io.historyValidMask.expect((BigInt(1) << olderTag).U) + } + } + + test("RAS state mutates only at canonical B-SIDE prune and feeds return prediction") { + simulate(module) { dut => + clear(dut) + sendBoundary(dut, 21, 0x7000, 0x7002, 0x7100, 0x7004, BoundaryKind.Call, staticTaken = true) + sendRequest(dut, 21, 0x7000) + waitForFinal(dut) + val callTag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.io.response.ready.poke(true.B) + dut.io.innerFlush.valid.expect(true.B) + dut.clock.step() + dut.io.response.ready.poke(false.B) + dut.io.speculativeRasCount(0).expect(0.U) + + applyCanonicalCorrection( + dut, + transactionId = 21, + predictionTag = callTag, + taken = true, + kind = BoundaryKind.Call, + rasPushAddress = 0x7004) + dut.io.speculativeRasCount(0).expect(1.U) + + sendBoundary(dut, 22, 0x7100, 0x7102, 0, 0x7104, BoundaryKind.Ret, staticTaken = true) + sendRequest(dut, 22, 0x7100) + waitForFinal(dut) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.FinalRas) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF4) + dut.io.response.bits.prediction.target.expect(0x7004.U) + } + } + + test("BTB TAGE BIM and loop state train only through exact public B-SIDE resolution") { + simulate(module) { dut => + clear(dut) + for (iteration <- 0 until 3) { + trainPrediction( + dut, + transactionId = 70 + iteration, + requestPc = 0x7400, + branchPc = 0x7404, + target = 0x7800, + fallthroughPc = 0x7406, + kind = BoundaryKind.Cond, + taken = false) + } + + sendBoundary(dut, 30, 0x7400, 0x7404, 0x7800, 0x7406, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 30, 0x7400) + waitForFinal(dut) + dut.io.response.bits.prediction.stage.expect(BSideStage.BF4) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Loop) + dut.io.response.bits.prediction.taken.expect(false.B) + + val exactTag = dut.io.response.bits.prediction.predictionTag.peek().litValue.toInt + dut.clock.step() + dut.io.response.ready.poke(false.B) + applyCanonicalCorrection(dut, 30, exactTag, taken = false, BoundaryKind.Cond) + dut.clock.step() + pokeResolve( + dut, + transactionId = 30, + predictionTag = exactTag + 1, + requestPc = 0x7400, + branchPc = 0x7404, + target = 0x7c00, + fallthroughPc = 0x7406, + kind = BoundaryKind.Cond, + taken = true) + dut.io.staleTraining.expect(true.B) + dut.clock.step() + + sendBoundary(dut, 31, 0x7400, 0x7404, 0x7800, 0x7406, BoundaryKind.Cond, staticTaken = true) + sendRequest(dut, 31, 0x7400) + waitForFinal(dut) + dut.io.response.bits.prediction.provider.expect(PredictionProvider.Loop) + dut.io.response.bits.prediction.taken.expect(false.B) + } + } + + test("prediction boundary elaborates under the new IFU package") { + val sv = ChiselStage.emitSystemVerilog(module) + assert(sv.contains("module BSide")) + assert(!sv.contains("module BSidePredictionPipeline_1")) + } +} diff --git a/chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala b/chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala new file mode 100644 index 00000000..a86f55a4 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala @@ -0,0 +1,158 @@ +package linxcore.ifu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.common.{BoundaryKind, InterfaceParams} +import linxcore.frontend._ +import org.scalatest.funsuite.AnyFunSuite + +class IFURecoverySpec extends AnyFunSuite with ChiselSim { + private val p = InterfaceParams() + + private def clear(dut: IFURecovery): Unit = { + dut.io.epochSeed.valid.poke(false.B) + dut.io.epochSeed.bits.poke(0.U.asTypeOf(dut.io.epochSeed.bits)) + dut.io.backend.valid.poke(false.B) + dut.io.backend.bits.poke(0.U.asTypeOf(dut.io.backend.bits)) + dut.io.itlb.valid.poke(false.B) + dut.io.itlb.bits.poke(0.U.asTypeOf(dut.io.itlb.bits)) + dut.io.prediction.valid.poke(false.B) + dut.io.prediction.bits.poke(0.U.asTypeOf(dut.io.prediction.bits)) + dut.io.out.ready.poke(false.B) + } + + private def pokeProposal( + port: chisel3.util.DecoupledIO[IfuInnerFlush], + transactionId: Int, + reason: IfuInnerFlushReason.Type, + restartPc: BigInt): Unit = { + port.bits.poke(0.U.asTypeOf(port.bits)) + port.valid.poke(true.B) + port.bits.valid.poke(true.B) + port.bits.threadId.poke(0.U) + port.bits.transactionId.poke(transactionId.U) + port.bits.fetchSeq.poke(transactionId.U) + port.bits.oldEpoch.poke(0.U) + port.bits.restartPc.poke(restartPc.U) + port.bits.reason.poke(reason) + port.bits.scope.poke(IfuPruneScope.KillAllThreadState) + } + + test("backend typed recovery overrides a held prediction correction") { + simulate(new IFURecovery(p, threadCount = 1)) { dut => + clear(dut) + pokeProposal(dut.io.prediction, 7, IfuInnerFlushReason.PredictionCorrection, 0x100) + dut.io.prediction.ready.expect(true.B) + dut.clock.step() + + clear(dut) + pokeProposal(dut.io.backend, 7, IfuInnerFlushReason.BruRecovery, 0x200) + dut.io.out.ready.poke(true.B) + dut.io.out.valid.expect(false.B) + dut.io.backend.ready.expect(true.B) + dut.io.acceptedBackend.expect(true.B) + dut.clock.step() + + clear(dut) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.reason.expect(IfuInnerFlushReason.BruRecovery) + dut.io.out.bits.restartPc.expect(0x200.U) + } + } + + test("redirect priority and retained hold preserve backpressure") { + simulate(new IFURecovery(p, threadCount = 1)) { dut => + clear(dut) + pokeProposal(dut.io.backend, 1, IfuInnerFlushReason.BruRecovery, 0x1000) + pokeProposal(dut.io.itlb, 2, IfuInnerFlushReason.ItlbMiss, 0x2000) + pokeProposal(dut.io.prediction, 3, IfuInnerFlushReason.PredictionCorrection, 0x3000) + dut.io.backend.ready.expect(true.B) + dut.io.itlb.ready.expect(false.B) + dut.io.prediction.ready.expect(false.B) + dut.clock.step() + + clear(dut) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.transactionId.expect(1.U) + dut.io.backend.ready.expect(false.B) + dut.clock.step(3) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.restartPc.expect(0x1000.U) + dut.io.out.ready.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + } + } + + test("backend feedback accepts only OOO-authored validation and emits no IEX control port") { + simulate(new IFUBackendFeedback(p)) { dut => + val ports = dut.io.elements.keySet + assert(ports.contains("validation")) + assert(ports.contains("resolve")) + assert(ports.contains("backendRecovery")) + assert(!ports.exists(_.toLowerCase.contains("iex"))) + } + + val sv = circt.stage.ChiselStage.emitSystemVerilog( + new IFUBackendFeedback(p)) + assert(sv.contains("module IFUBackendFeedback")) + assert(sv.contains("validation")) + assert(!sv.contains("iex")) + assert(!sv.contains("Iex")) + } + + test("mispredict training and recovery remain atomic at the OOO feedback boundary") { + simulate(new IFUBackendFeedback(p)) { dut => + dut.io.validation.valid.poke(false.B) + dut.io.validation.bits.poke(0.U.asTypeOf(dut.io.validation.bits)) + dut.io.resolve.ready.poke(false.B) + dut.io.backendRecovery.ready.poke(false.B) + + val event = dut.io.validation.bits + event.uop.valid.poke(true.B) + event.uop.peId.poke(3.U) + event.uop.threadId.poke(0.U) + event.uop.checkpointId.poke(7.U) + event.uop.uid.fetchPacketUid.poke(0x66.U) + event.uop.prediction.valid.poke(true.B) + event.uop.prediction.predictionTag.poke(0x44.U) + event.uop.prediction.transactionId.poke(0x55.U) + event.uop.prediction.fetchPacketUid.poke(0x66.U) + event.uop.prediction.fetchSeq.poke(0x77.U) + event.uop.prediction.requestPc.poke(0x2000.U) + event.uop.prediction.taken.poke(false.B) + event.uop.prediction.branchPc.poke(0x2080.U) + event.uop.prediction.target.poke(0x3000.U) + event.uop.prediction.fallthroughPc.poke(0x2100.U) + event.uop.prediction.kind.poke(BoundaryKind.Cond) + event.uop.prediction.provider.poke(PredictionProvider.LongTage.asUInt) + event.uop.prediction.stage.poke(BSideStage.BF4.asUInt) + event.uop.prediction.confidence.poke(3.U) + event.uop.prediction.checkpointId.poke(7.U) + event.uop.prediction.epoch.poke(2.U) + event.point.poke(BranchValidationPoint.BruE1) + event.setcKind.poke(SetcValidationKind.Condition) + event.actualTaken.poke(true.B) + event.actualBranchPc.poke(0x2080.U) + event.actualTarget.poke(0x5000.U) + event.actualFallthroughPc.poke(0x2100.U) + event.actualKind.poke(BoundaryKind.Cond) + dut.io.validation.valid.poke(true.B) + dut.io.validation.ready.expect(true.B) + dut.clock.step() + dut.io.validation.valid.poke(false.B) + + dut.io.resolve.ready.poke(true.B) + dut.io.backendRecovery.ready.poke(false.B) + dut.io.resolve.valid.expect(false.B) + dut.io.backendRecovery.valid.expect(true.B) + dut.clock.step() + + dut.io.backendRecovery.ready.poke(true.B) + dut.io.resolve.valid.expect(true.B) + dut.io.backendRecovery.valid.expect(true.B) + dut.io.resolve.bits.mispredict.expect(true.B) + dut.io.backendRecovery.bits.restartPc.expect(0x5000.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/DSideTranslationReviewFixSpec.scala b/chisel/src/test/scala/linxcore/lsu/DSideTranslationReviewFixSpec.scala new file mode 100644 index 00000000..4cc9c00f --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/DSideTranslationReviewFixSpec.scala @@ -0,0 +1,161 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{MemoryAccessAttributes, PhysicalMemoryRegion, + SimulationParamProfiles} +import org.scalatest.funsuite.AnyFunSuite + +class DSideTranslationReviewFixSpec extends AnyFunSuite with ChiselSim { + test("Decoupled lookup retains the complete load across a PTW miss") { + val p = SimulationParamProfiles.W4 + simulate(new DSideTranslation(p, entries = 2, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.result.ready.poke(false.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lookup.bits.load.address.poke(BigInt("8000000000001238", 16).U) + dut.io.lookup.bits.load.sizeBytes.poke(8.U) + dut.io.lookup.bits.load.identity.transaction.value.poke(37.U) + dut.io.lookup.bits.load.identity.transaction.generation.poke(9.U) + dut.io.lookup.bits.load.destination.ptag.poke(11.U) + dut.io.lookup.valid.poke(true.B) + dut.io.lookup.ready.expect(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val identity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.identity.poke(identity) + dut.io.memoryResponse.bits.data.poke(0x42.U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(true.B) + dut.io.memoryResponse.bits.cacheable.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + + dut.io.result.valid.expect(true.B) + dut.io.result.bits.request.load.identity.transaction.value.expect(37.U) + dut.io.result.bits.request.load.identity.transaction.generation.expect(9.U) + dut.io.result.bits.request.load.destination.ptag.expect(11.U) + dut.io.result.bits.physicalAddress.expect(0x42238.U) + dut.io.result.ready.poke(true.B) + dut.clock.step() + dut.io.quiescent.expect(true.B) + } + } + + test("Decoupled lookup retains the complete STA across a PTW miss") { + val p = SimulationParamProfiles.W4 + simulate(new DSideTranslation(p, entries = 2, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.result.ready.poke(false.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lookup.bits.isStore.poke(true.B) + dut.io.lookup.bits.store.address.poke(BigInt("8000000000003450", 16).U) + dut.io.lookup.bits.store.sizeBytes.poke(8.U) + dut.io.lookup.bits.store.identity.transaction.value.poke(41.U) + dut.io.lookup.bits.store.identity.transaction.generation.poke(12.U) + dut.io.lookup.bits.store.identity.lsid.poke(17.U) + dut.io.lookup.bits.store.memoryOrder.firstSid.poke(23.U) + dut.io.lookup.bits.store.requestCount.poke(1.U) + dut.io.lookup.bits.store.pair.poke(true.B) + dut.io.lookup.valid.poke(true.B) + dut.io.lookup.ready.expect(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val identity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.identity.poke(identity) + dut.io.memoryResponse.bits.data.poke(0x52.U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(true.B) + dut.io.memoryResponse.bits.cacheable.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + + dut.io.result.valid.expect(true.B) + dut.io.result.bits.request.store.identity.transaction.value.expect(41.U) + dut.io.result.bits.request.store.identity.transaction.generation.expect(12.U) + dut.io.result.bits.request.store.identity.lsid.expect(17.U) + dut.io.result.bits.request.store.memoryOrder.firstSid.expect(23.U) + dut.io.result.bits.request.store.requestCount.expect(1.U) + dut.io.result.bits.request.store.pair.expect(true.B) + dut.io.result.bits.physicalAddress.expect(0x52450.U) + dut.io.result.ready.poke(true.B) + dut.clock.step() + dut.io.quiescent.expect(true.B) + } + } + + test("one canonical physical attribute source governs identity and translated mappings") { + val base = SimulationParamProfiles.W4 + val p = base.copy(lsu = base.lsu.copy(physicalMemoryRegions = Seq( + PhysicalMemoryRegion(0x1000, BigInt("fffffffffffff000", 16), + MemoryAccessAttributes(writable = false))))) + simulate(new DSideTranslation(p, entries = 2, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.result.ready.poke(false.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lookup.bits.isStore.poke(true.B) + dut.io.lookup.bits.store.address.poke(0x1000.U) + dut.io.lookup.bits.store.sizeBytes.poke(8.U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + dut.io.result.bits.accessFault.expect(true.B) + dut.io.result.ready.poke(true.B) + dut.clock.step() + + dut.io.result.ready.poke(false.B) + dut.io.lookup.bits.store.address.poke(BigInt("8000000000002000", 16).U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val identity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.identity.poke(identity) + dut.io.memoryResponse.bits.data.poke(1.U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(true.B) + dut.io.memoryResponse.bits.cacheable.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.accessFault.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala b/chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala new file mode 100644 index 00000000..e207991a --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala @@ -0,0 +1,201 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{MemoryAccessAttributes, PhysicalMemoryRegion, + SimulationParamProfiles} +import linxcore.top.interface.{IEXLSUIO, LSUIO, StoreCommitAuthorizationTxn, + StoreMemoryClass, StoreMemoryClassifyTxn, StoreReservationTxn} +import org.scalatest.funsuite.AnyFunSuite + +class IEXLSUIntegrationSpec extends AnyFunSuite with ChiselSim { + test("public boundaries carry semantic store reservation commit and classification") { + val p = SimulationParamProfiles.W4 + val iexLsu = new IEXLSUIO(p) + val lsu = new LSUIO(p) + assert(iexLsu.storeReservation.length == p.lsu.storePipes) + assert(iexLsu.storeReservation.head.bits + .isInstanceOf[StoreReservationTxn]) + assert(lsu.storeResolve.bits + .isInstanceOf[linxcore.top.interface.RobResolveTxn]) + assert(lsu.storeCommit.bits.isInstanceOf[StoreCommitAuthorizationTxn]) + assert(StoreMemoryClass.all.toSet == Set( + StoreMemoryClass.NormalCacheable, + StoreMemoryClass.NormalNonCacheable, + StoreMemoryClass.Device, + StoreMemoryClass.Fault)) + } + + test("public LSU joins reservation STA STD classification and commit by exact identity") { + val storeAddress = BigInt("7000000000000000", 16) + val base = SimulationParamProfiles.W4 + val p = base.copy(lsu = base.lsu.copy(physicalMemoryRegions = Seq( + PhysicalMemoryRegion(storeAddress, + BigInt("ffff000000000000", 16), + MemoryAccessAttributes(cacheable = false, device = true))))) + simulate(new LSU(p)) { dut => + dut.io.iex.storeReservation.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeAddress.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeData.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadAddress.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadResult.foreach(_.ready.poke(true.B)) + dut.io.iex.loadReissue.foreach(_.ready.poke(true.B)) + dut.io.iex.loadRebindApply.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadRepick.foreach(_.ready.poke(true.B)) + dut.io.iex.loadCancel.foreach(_.ready.poke(true.B)) + dut.io.iex.recoveryEvent.ready.poke(true.B) + dut.io.storeResolve.ready.poke(false.B) + dut.io.storeCommit.valid.poke(false.B) + dut.io.storeCommit.bits.poke(0.U.asTypeOf(dut.io.storeCommit.bits)) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.memoryRequest.foreach(_.ready.poke(true.B)) + dut.io.memoryResponse.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.memoryFault.ready.poke(true.B) + dut.io.maintenance.valid.poke(false.B) + dut.io.maintenance.bits.poke(0.U.asTypeOf(dut.io.maintenance.bits)) + dut.io.maintenanceResult.ready.poke(true.B) + dut.io.trace.ready.poke(true.B) + + def pokeRob(rob: linxcore.top.interface.RobIdentity): Unit = { + rob.peId.poke(1.U) + rob.stid.poke(0.U) + rob.ridSlot.poke(2.U) + rob.ridGeneration.poke(1.U) + rob.memberIndex.poke(1.U) + rob.residentGeneration.poke(1.U) + rob.bid.poke(1.U) + rob.brobGeneration.poke(1.U) + } + def pokeIdentity(identity: linxcore.top.interface.MemoryIdentity): Unit = { + identity.poke(0.U.asTypeOf(identity)) + pokeRob(identity.rob) + identity.transaction.value.poke(1.U) + identity.transaction.generation.poke(1.U) + identity.lsid.poke(11.U) + } + + val reserve = dut.io.iex.storeReservation(0) + reserve.bits.poke(0.U.asTypeOf(reserve.bits)) + reserve.bits.transactionId.poke(7.U) + reserve.bits.transaction.value.poke(1.U) + reserve.bits.transaction.generation.poke(1.U) + pokeRob(reserve.bits.rob) + reserve.bits.memoryOrder.requestCount.poke(1.U) + reserve.bits.memoryOrder.firstLsid.poke(11.U) + reserve.bits.memoryOrder.firstSid.poke(13.U) + reserve.bits.requestCount.poke(1.U) + reserve.bits.sizeBytes.poke(8.U) + reserve.valid.poke(true.B) + reserve.ready.expect(true.B) + dut.clock.step() + reserve.valid.poke(false.B) + + val sta = dut.io.iex.storeAddress(0) + sta.bits.poke(0.U.asTypeOf(sta.bits)) + pokeIdentity(sta.bits.identity) + sta.bits.memoryOrder.requestCount.poke(1.U) + sta.bits.memoryOrder.firstLsid.poke(11.U) + sta.bits.memoryOrder.firstSid.poke(13.U) + sta.bits.requestCount.poke(1.U) + sta.bits.address.poke(storeAddress.U) + sta.bits.sizeBytes.poke(8.U) + sta.valid.poke(true.B) + sta.ready.expect(true.B) + dut.clock.step() + sta.valid.poke(false.B) + + val std = dut.io.iex.storeData(1) + std.bits.poke(0.U.asTypeOf(std.bits)) + pokeIdentity(std.bits.identity) + std.bits.memoryOrder.requestCount.poke(1.U) + std.bits.memoryOrder.firstLsid.poke(11.U) + std.bits.memoryOrder.firstSid.poke(13.U) + std.bits.requestCount.poke(1.U) + std.bits.sizeBytes.poke(8.U) + std.bits.data(0).poke("h1122334455667788".U) + std.bits.byteMask(0).poke("hff".U) + std.valid.poke(true.B) + std.ready.expect(true.B) + dut.clock.step() + std.valid.poke(false.B) + var resolveCycles = 0 + while (!dut.io.storeResolve.valid.peek().litToBoolean && + resolveCycles < 12) { + dut.clock.step() + resolveCycles += 1 + } + + dut.io.storeResolve.valid.expect(true.B) + dut.io.storeResolve.bits.transactionId.expect(7.U) + dut.io.storeResolve.bits.rob.ridSlot.expect(2.U) + dut.io.storeResolve.bits.rob.memberIndex.expect(1.U) + dut.io.storeResolve.ready.poke(true.B) + dut.clock.step() + dut.io.storeResolve.ready.poke(false.B) + + val storeMemory = dut.io.memoryRequest(p.lsu.loadPipes) + storeMemory.ready.poke(false.B) + + val commit = dut.io.storeCommit + commit.bits.poke(0.U.asTypeOf(commit.bits)) + pokeRob(commit.bits.rob) + commit.bits.logicalFirstLsid.poke(11.U) + commit.bits.logicalFirstStoreId.poke(13.U) + commit.bits.requestCount.poke(1.U) + commit.bits.beat.poke(0.U) + commit.valid.poke(true.B) + commit.ready.expect(true.B) + dut.clock.step() + commit.valid.poke(false.B) + + var requestCycles = 0 + while (!storeMemory.valid.peek().litToBoolean && requestCycles < 32) { + dut.clock.step() + requestCycles += 1 + } + assert(requestCycles < 32, + "a committed non-cacheable store must reach its canonical memory lane") + storeMemory.bits.command.expect(linxcore.top.interface.MemoryCommand.Write) + storeMemory.bits.address.expect(storeAddress.U) + storeMemory.bits.data.expect("h1122334455667788".U) + val responseId = storeMemory.bits.identity.peek() + storeMemory.ready.poke(true.B) + dut.clock.step() + + val storeResponse = dut.io.memoryResponse(p.lsu.loadPipes) + storeResponse.bits.poke(0.U.asTypeOf(storeResponse.bits)) + storeResponse.bits.identity.poke(responseId) + storeResponse.valid.poke(true.B) + while (!storeResponse.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + storeResponse.valid.poke(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala new file mode 100644 index 00000000..bca51b05 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala @@ -0,0 +1,675 @@ +package linxcore.lsu + +import chisel3._ +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface.{LSUMaintenanceCommand, LSUMemoryFaultCause, + RecoveryCause, RecoveryPhase, StoreMemoryClass} +import org.scalatest.funsuite.AnyFunSuite + +class LSUIntegrationSpec extends AnyFunSuite with LSUMemoryTestSupport { + + private def pokeRob( + rob: linxcore.top.interface.RobIdentity): Unit = { + rob.peId.poke(1.U) + rob.stid.poke(0.U) + rob.ridSlot.poke(2.U) + rob.ridGeneration.poke(1.U) + rob.memberIndex.poke(0.U) + rob.residentGeneration.poke(1.U) + rob.bid.poke(1.U) + rob.brobGeneration.poke(1.U) + } + + test("translated_committed_store_projects_exact_transaction_data_and_mask") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("8000000000003000", 16) + simulate(new LSU(p)) { dut => + initialize(dut) + + val reserve = dut.io.iex.storeReservation(0) + reserve.bits.poke(0.U.asTypeOf(reserve.bits)) + reserve.bits.transactionId.poke(11.U) + reserve.bits.transaction.value.poke(11.U) + reserve.bits.transaction.generation.poke(1.U) + pokeRob(reserve.bits.rob) + reserve.bits.memoryOrder.requestCount.poke(1.U) + reserve.bits.memoryOrder.firstLsid.poke(21.U) + reserve.bits.memoryOrder.firstSid.poke(31.U) + reserve.bits.requestCount.poke(1.U) + reserve.bits.sizeBytes.poke(8.U) + reserve.valid.poke(true.B) + reserve.ready.expect(true.B) + dut.clock.step() + reserve.valid.poke(false.B) + + val sta = dut.io.iex.storeAddress(0) + sta.bits.poke(0.U.asTypeOf(sta.bits)) + pokeRob(sta.bits.identity.rob) + sta.bits.identity.transaction.value.poke(11.U) + sta.bits.identity.transaction.generation.poke(1.U) + sta.bits.identity.lsid.poke(21.U) + sta.bits.memoryOrder.requestCount.poke(1.U) + sta.bits.memoryOrder.firstLsid.poke(21.U) + sta.bits.memoryOrder.firstSid.poke(31.U) + sta.bits.requestCount.poke(1.U) + sta.bits.address.poke(virtualAddress.U) + sta.bits.sizeBytes.poke(8.U) + sta.valid.poke(true.B) + sta.ready.expect(true.B) + dut.clock.step() + sta.valid.poke(false.B) + + val request = dut.io.memoryRequest(0) + var cycles = 0 + while (!request.valid.peek().litToBoolean && cycles < 16) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 16, "store DTLB miss did not reach lower memory") + request.bits.address.expect(virtualAddress.U) + val identity = request.bits.identity.peek() + dut.clock.step() + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.poke(identity) + val pageNumberWidth = p.physicalAddressWidth - 12 + val devicePpn = (BigInt(0xff) << (pageNumberWidth - 8)) | 0x53 + response.bits.data.poke(devicePpn.U) + response.bits.attributesValid.poke(true.B) + response.bits.readable.poke(true.B) + response.bits.writable.poke(true.B) + response.bits.cacheable.poke(false.B) + response.bits.device.poke(true.B) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + dut.clock.step() + + val std = dut.io.iex.storeData(1) + std.bits.poke(0.U.asTypeOf(std.bits)) + pokeRob(std.bits.identity.rob) + std.bits.identity.transaction.value.poke(11.U) + std.bits.identity.transaction.generation.poke(1.U) + std.bits.identity.lsid.poke(21.U) + std.bits.memoryOrder.requestCount.poke(1.U) + std.bits.memoryOrder.firstLsid.poke(21.U) + std.bits.memoryOrder.firstSid.poke(31.U) + std.bits.requestCount.poke(1.U) + std.bits.sizeBytes.poke(8.U) + std.bits.data(0).poke("h1122334455667788".U) + std.bits.byteMask(0).poke("hff".U) + std.valid.poke(true.B) + while (!std.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + std.valid.poke(false.B) + + val storeMemory = dut.io.memoryRequest(p.lsu.loadPipes) + storeMemory.ready.poke(false.B) + val commit = dut.io.storeCommit + commit.bits.poke(0.U.asTypeOf(commit.bits)) + pokeRob(commit.bits.rob) + commit.bits.transaction.value.poke(11.U) + commit.bits.transaction.generation.poke(1.U) + commit.bits.logicalFirstLsid.poke(21.U) + commit.bits.logicalFirstStoreId.poke(31.U) + commit.bits.requestCount.poke(1.U) + commit.valid.poke(true.B) + while (!commit.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + commit.valid.poke(false.B) + + cycles = 0 + while (!storeMemory.valid.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32, "translated committed store did not reach memory") + storeMemory.bits.command.expect( + linxcore.top.interface.MemoryCommand.Write) + storeMemory.bits.identity.value.expect(11.U) + storeMemory.bits.identity.generation.expect(1.U) + storeMemory.bits.accessKind.expect( + linxcore.top.interface.MemoryAccessKind.Device) + storeMemory.bits.address.expect((devicePpn << 12).U) + storeMemory.bits.data.expect("h1122334455667788".U) + storeMemory.bits.byteMask.expect("hff".U) + storeMemory.ready.poke(true.B) + dut.clock.step() + } + } + + test("recovery preparation waits for an outstanding lower-memory transaction to drain") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, 0x1800) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + + val request = dut.io.memoryRequest(0) + var cycles = 0 + while (!request.valid.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32, "cache miss did not reach lower memory") + val identity = request.bits.identity.peek() + val address = request.bits.address.peek() + dut.clock.step() + + val prepare = dut.io.recovery.prepare + prepare.bits.poke(0.U.asTypeOf(prepare.bits)) + prepare.bits.transactionId.poke(91.U) + prepare.bits.phase.poke(RecoveryPhase.Prepare) + prepare.bits.cause.poke(RecoveryCause.Branch) + prepare.bits.trigger.poke( + dut.io.iex.loadAddress(0).bits.identity.rob.peek()) + prepare.bits.redirectPc.poke(0x400.U) + prepare.bits.newEpoch.poke(2.U) + prepare.bits.firstKilledValid.poke(true.B) + prepare.bits.firstKilled.poke( + dut.io.iex.loadAddress(0).bits.identity.rob.peek()) + prepare.bits.lastKilled.poke( + dut.io.iex.loadAddress(0).bits.identity.rob.peek()) + prepare.bits.killedGroupCount.poke(1.U) + prepare.bits.killedMemberCount.poke(1.U) + prepare.valid.poke(true.B) + prepare.ready.expect(true.B) + dut.clock.step() + prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(false.B) + dut.io.quiescent.expect(false.B) + + dut.io.recovery.prepared.ready.poke(false.B) + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.poke(identity) + response.bits.address.poke(address) + response.bits.data.poke("h8877665544332211".U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + var cyclesAfterResponse = 0 + while (!dut.io.recovery.prepared.valid.peek().litToBoolean && cyclesAfterResponse < 16) { + dut.clock.step() + cyclesAfterResponse += 1 + } + assert(cyclesAfterResponse < 16, + "recovery did not publish quiescence after the exact response drained") + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + + val apply = dut.io.recovery.apply + apply.bits.poke(prepare.bits.peek()) + apply.bits.phase.poke(RecoveryPhase.Apply) + apply.valid.poke(true.B) + dut.clock.step() + apply.valid.poke(false.B) + var quiescentCycles = 0 + while (!dut.io.quiescent.peek().litToBoolean && quiescentCycles < 16) { + dut.clock.step() + quiescentCycles += 1 + } + assert(quiescentCycles < 16, "LSU did not become quiescent after recovery apply") + } + } + + test("translation transactions participate in common recovery quiescence") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("8000000000007000", 16) + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, virtualAddress, transaction = 19) + + val request = dut.io.memoryRequest(0) + var requestCycles = 0 + while (!request.valid.peek().litToBoolean && requestCycles < 16) { + dut.clock.step() + requestCycles += 1 + } + assert(requestCycles < 16, "translation request did not reach memory") + val identity = request.bits.identity.peek() + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + + val prepare = dut.io.recovery.prepare + prepare.bits.poke(0.U.asTypeOf(prepare.bits)) + prepare.bits.transactionId.poke(92.U) + prepare.bits.phase.poke(RecoveryPhase.Prepare) + prepare.bits.cause.poke(RecoveryCause.Branch) + prepare.bits.redirectPc.poke(0x500.U) + prepare.bits.newEpoch.poke(3.U) + dut.io.recovery.prepared.ready.poke(false.B) + prepare.valid.poke(true.B) + dut.clock.step() + prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(false.B) + dut.io.quiescent.expect(false.B) + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.poke(identity) + response.bits.data.poke(0x77.U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + var preparedCycles = 0 + while (!dut.io.recovery.prepared.valid.peek().litToBoolean && preparedCycles < 16) { + dut.clock.step() + preparedCycles += 1 + } + assert(preparedCycles < 16, "translation drain did not release recovery preparation") + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + + val apply = dut.io.recovery.apply + apply.bits.poke(prepare.bits.peek()) + apply.bits.phase.poke(RecoveryPhase.Apply) + apply.valid.poke(true.B) + dut.clock.step() + apply.valid.poke(false.B) + dut.io.quiescent.expect(true.B) + } + } + +} + +trait CacheableStorePublicTestSupport extends LSUMemoryTestSupport { + this: org.scalatest.TestSuite => + + protected def pokeStoreRob( + rob: linxcore.top.interface.RobIdentity): Unit = { + rob.peId.poke(1.U); rob.stid.poke(0.U); rob.ridSlot.poke(2.U) + rob.ridGeneration.poke(1.U); rob.memberIndex.poke(0.U) + rob.residentGeneration.poke(1.U); rob.bid.poke(1.U) + rob.brobGeneration.poke(1.U) + } + + protected def publishCacheableStore(dut: LSU, address: BigInt): + (BigInt, BigInt) = { + val reserve = dut.io.iex.storeReservation(0) + reserve.bits.poke(0.U.asTypeOf(reserve.bits)) + reserve.bits.transactionId.poke(61.U) + reserve.bits.transaction.value.poke(61.U) + reserve.bits.transaction.generation.poke(1.U) + pokeStoreRob(reserve.bits.rob) + reserve.bits.memoryOrder.requestCount.poke(1.U) + reserve.bits.memoryOrder.firstLsid.poke(21.U) + reserve.bits.memoryOrder.firstSid.poke(31.U) + reserve.bits.requestCount.poke(1.U) + reserve.bits.sizeBytes.poke(8.U) + reserve.valid.poke(true.B) + while (!reserve.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + reserve.valid.poke(false.B) + + val sta = dut.io.iex.storeAddress(0) + sta.bits.poke(0.U.asTypeOf(sta.bits)) + pokeStoreRob(sta.bits.identity.rob) + sta.bits.identity.transaction.value.poke(61.U) + sta.bits.identity.transaction.generation.poke(1.U) + sta.bits.identity.lsid.poke(21.U) + sta.bits.identity.pipeId.poke(0.U) + sta.bits.memoryOrder.requestCount.poke(1.U) + sta.bits.memoryOrder.firstLsid.poke(21.U) + sta.bits.memoryOrder.firstSid.poke(31.U) + sta.bits.requestCount.poke(1.U) + sta.bits.address.poke(address.U) + sta.bits.sizeBytes.poke(8.U) + sta.valid.poke(true.B) + while (!sta.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + sta.valid.poke(false.B) + + val std = dut.io.iex.storeData(0) + std.bits.poke(0.U.asTypeOf(std.bits)) + pokeStoreRob(std.bits.identity.rob) + std.bits.identity.transaction.value.poke(61.U) + std.bits.identity.transaction.generation.poke(1.U) + std.bits.identity.lsid.poke(21.U) + std.bits.memoryOrder.requestCount.poke(1.U) + std.bits.memoryOrder.firstLsid.poke(21.U) + std.bits.memoryOrder.firstSid.poke(31.U) + std.bits.requestCount.poke(1.U) + std.bits.sizeBytes.poke(8.U) + std.bits.data(0).poke("h1122334455667788".U) + std.bits.byteMask(0).poke("hff".U) + std.valid.poke(true.B) + while (!std.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + std.valid.poke(false.B) + + val commit = dut.io.storeCommit + commit.bits.poke(0.U.asTypeOf(commit.bits)) + pokeStoreRob(commit.bits.rob) + commit.bits.logicalFirstLsid.poke(21.U) + commit.bits.logicalFirstStoreId.poke(31.U) + commit.bits.requestCount.poke(1.U) + commit.valid.poke(true.B) + var commitCycles = 0 + while (!commit.ready.peek().litToBoolean && commitCycles < 32) { + dut.clock.step(); commitCycles += 1 + } + assert(commitCycles < 32, "cacheable store commit did not become ready") + dut.clock.step() + commit.valid.poke(false.B) + + val ownership = dut.io.memoryRequest(dut.p.lsu.loadPipes + 1) + var cycles = 0 + while (!ownership.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 64, "cacheable store did not request ownership") + val value = ownership.bits.identity.value.peek().litValue + val generation = ownership.bits.identity.generation.peek().litValue + dut.clock.step() + (value, generation) + } +} + +class LSURound2PublicSpec extends AnyFunSuite + with CacheableStorePublicTestSupport { + + test("presented maintenance immediately fences concurrent load and store admission") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, 0x1800, transaction = 40) + val reservation = dut.io.iex.storeReservation(0) + reservation.bits.poke(0.U.asTypeOf(reservation.bits)) + reservation.valid.poke(true.B) + dut.io.maintenance.bits.command.poke(LSUMaintenanceCommand.Fence) + dut.io.maintenance.bits.address.poke(0.U) + dut.io.maintenance.valid.poke(true.B) + + dut.io.maintenance.ready.expect(true.B) + dut.io.iex.loadAddress(0).ready.expect(false.B) + reservation.ready.expect(false.B) + dut.clock.step() + dut.io.maintenance.valid.poke(false.B) + dut.io.iex.loadAddress(0).valid.poke(false.B) + reservation.valid.poke(false.B) + + dut.io.maintenanceResult.valid.expect(false.B) + dut.clock.step() + dut.io.maintenanceResult.valid.expect(false.B) + dut.clock.step() + dut.io.maintenanceResult.valid.expect(true.B) + dut.io.protocolError.expect(false.B) + } + } + + test("recovery prepared waits through retained public SCB response and retry states") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + val (value, generation) = publishCacheableStore(dut, 0x4800) + + val prepare = dut.io.recovery.prepare + prepare.bits.poke(0.U.asTypeOf(prepare.bits)) + prepare.bits.transactionId.poke(94.U) + prepare.bits.phase.poke(RecoveryPhase.Prepare) + prepare.bits.cause.poke(RecoveryCause.Branch) + prepare.valid.poke(true.B) + val response = dut.io.memoryResponse(p.lsu.loadPipes + 1) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(value.U) + response.bits.identity.generation.poke(generation.U) + response.valid.poke(true.B) + dut.clock.step() + prepare.valid.poke(false.B) + response.valid.poke(false.B) + + dut.io.recovery.prepared.valid.expect(false.B) + dut.clock.step() + dut.io.recovery.prepared.valid.expect(false.B) + var cycles = 0 + while (!dut.io.recovery.prepared.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 64, "SCB retry completion did not release recovery") + } + } + + test("public dirty line invalidation fails closed") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + val (value, generation) = publishCacheableStore(dut, 0x5800) + val response = dut.io.memoryResponse(p.lsu.loadPipes + 1) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(value.U) + response.bits.identity.generation.poke(generation.U) + response.valid.poke(true.B) + dut.clock.step() + response.valid.poke(false.B) + var drain = 0 + while (!dut.io.quiescent.peek().litToBoolean && drain < 64) { + dut.clock.step(); drain += 1 + } + assert(drain < 64, "cacheable store did not become a dirty L1D line") + + pokeLoad(dut, 0x5800, transaction = 62) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + var loadCycles = 0 + while (!dut.io.iex.loadResult(0).valid.peek().litToBoolean && + loadCycles < 32) { + dut.clock.step(); loadCycles += 1 + } + assert(loadCycles < 32, "dirty store line was not publicly readable") + dut.io.iex.loadResult(0).bits.data.expect("h1122334455667788".U) + dut.clock.step() + + dut.io.maintenance.bits.command.poke(LSUMaintenanceCommand.InvalidateLine) + dut.io.maintenance.bits.address.poke(0x5800.U) + dut.io.maintenance.valid.poke(true.B) + dut.io.maintenance.ready.expect(true.B) + dut.clock.step() + dut.io.maintenance.valid.poke(false.B) + while (!dut.io.maintenanceResult.valid.peek().litToBoolean) dut.clock.step() + dut.io.maintenanceResult.bits.success.expect(false.B) + dut.io.protocolError.expect(true.B) + } + } +} + +class LSUIntegrationReviewFixSpec extends AnyFunSuite with LSUMemoryTestSupport { + + test("misaligned and denied requests complete once through the precise LSU fault boundary") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + dut.io.memoryFault.ready.poke(false.B) + pokeLoad(dut, 0x1003, transaction = 41) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + dut.clock.step() + dut.io.memoryFault.valid.expect(true.B) + dut.io.memoryFault.bits.identity.transaction.value.expect(41.U) + dut.io.memoryFault.bits.cause.expect(LSUMemoryFaultCause.Alignment) + dut.clock.step(2) + dut.io.memoryFault.valid.expect(true.B) + dut.io.memoryFault.ready.poke(true.B) + dut.clock.step() + dut.io.memoryFault.valid.expect(false.B) + + val virtualAddress = BigInt("800000000000a000", 16) + pokeLoad(dut, virtualAddress, transaction = 42) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + val request = dut.io.memoryRequest(0) + while (!request.valid.peek().litToBoolean) dut.clock.step() + val identity = request.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse(0).bits.poke(0.U.asTypeOf(dut.io.memoryResponse(0).bits)) + dut.io.memoryResponse(0).bits.identity.poke(identity) + dut.io.memoryResponse(0).bits.data.poke(0xa1.U) + dut.io.memoryResponse(0).bits.attributesValid.poke(true.B) + dut.io.memoryResponse(0).bits.readable.poke(false.B) + dut.io.memoryResponse(0).bits.writable.poke(false.B) + dut.io.memoryResponse(0).bits.cacheable.poke(false.B) + dut.io.memoryResponse(0).valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse(0).valid.poke(false.B) + dut.clock.step() + dut.io.memoryFault.valid.expect(true.B) + dut.io.memoryFault.bits.identity.transaction.value.expect(42.U) + dut.io.memoryFault.bits.cause.expect(LSUMemoryFaultCause.Access) + dut.clock.step() + dut.io.memoryFault.valid.expect(false.B) + } + } + + test("wrong-lane translation and data responses complete exact owners without stranding recovery") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("800000000000b000", 16) + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, virtualAddress, transaction = 43) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + while (!dut.io.memoryRequest(0).valid.peek().litToBoolean) dut.clock.step() + val translationIdentity = dut.io.memoryRequest(0).bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse(1).bits.poke(0.U.asTypeOf(dut.io.memoryResponse(1).bits)) + dut.io.memoryResponse(1).bits.identity.poke(translationIdentity) + dut.io.memoryResponse(1).bits.data.poke(0xb1.U) + dut.io.memoryResponse(1).bits.attributesValid.poke(true.B) + dut.io.memoryResponse(1).bits.readable.poke(true.B) + dut.io.memoryResponse(1).bits.writable.poke(true.B) + dut.io.memoryResponse(1).bits.cacheable.poke(true.B) + dut.io.memoryResponse(1).valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse(1).valid.poke(false.B) + dut.clock.step() + + var dataLaneOption = (0 until p.lsu.loadPipes).find( + lane => dut.io.memoryRequest(lane).valid.peek().litToBoolean) + var dataRequestCycles = 0 + while (dataLaneOption.isEmpty && dataRequestCycles < 32) { + dut.clock.step() + dataRequestCycles += 1 + dataLaneOption = (0 until p.lsu.loadPipes).find( + lane => dut.io.memoryRequest(lane).valid.peek().litToBoolean) + } + assert(dataLaneOption.nonEmpty, + "translated load did not publish its data request") + val dataLane = dataLaneOption.get + val dataIdentity = dut.io.memoryRequest(dataLane).bits.identity.peek() + val dataAddress = dut.io.memoryRequest(dataLane).bits.address.peek() + val wrongLane = 1 - dataLane + dut.clock.step() + dut.io.memoryResponse(wrongLane).bits.poke( + 0.U.asTypeOf(dut.io.memoryResponse(wrongLane).bits)) + dut.io.memoryResponse(wrongLane).bits.identity.poke(dataIdentity) + dut.io.memoryResponse(wrongLane).bits.address.poke(dataAddress) + dut.io.memoryResponse(wrongLane).bits.data.poke("h0102030405060708".U) + dut.io.memoryResponse(wrongLane).valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse(wrongLane).valid.poke(false.B) + var resultCycles = 0 + while (!dut.io.iex.loadResult(0).valid.peek().litToBoolean && resultCycles < 32) { + dut.clock.step() + resultCycles += 1 + } + assert(resultCycles < 32, "wrong-lane exact data response stranded the load") + dut.clock.step() + dut.io.quiescent.expect(true.B) + } + } + + test("public maintenance retains fence and invalidation until their completion is accepted") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + dut.io.maintenanceResult.ready.poke(false.B) + dut.io.maintenance.bits.command.poke(LSUMaintenanceCommand.Fence) + dut.io.maintenance.bits.address.poke(0.U) + dut.io.maintenance.valid.poke(true.B) + dut.io.maintenance.ready.expect(true.B) + dut.clock.step() + dut.io.maintenance.valid.poke(false.B) + while (!dut.io.maintenanceResult.valid.peek().litToBoolean) dut.clock.step() + dut.io.quiescent.expect(false.B) + dut.clock.step(2) + dut.io.maintenanceResult.valid.expect(true.B) + dut.io.maintenanceResult.ready.poke(true.B) + dut.clock.step() + dut.io.quiescent.expect(true.B) + + for (command <- Seq( + LSUMaintenanceCommand.InvalidateTranslation, + LSUMaintenanceCommand.InvalidateLine, + LSUMaintenanceCommand.InvalidateAll)) { + dut.io.maintenance.bits.command.poke(command) + dut.io.maintenance.bits.address.poke(0x1000.U) + dut.io.maintenance.valid.poke(true.B) + while (!dut.io.maintenance.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.maintenance.valid.poke(false.B) + while (!dut.io.maintenanceResult.valid.peek().litToBoolean) dut.clock.step() + dut.io.maintenanceResult.bits.command.expect(command) + dut.io.maintenanceResult.bits.success.expect(true.B) + dut.clock.step() + } + dut.io.protocolError.expect(false.B) + } + } + + test("recovery prepared waits for a retained load return to be consumed") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + dut.io.iex.loadResult(0).ready.poke(false.B) + pokeLoad(dut, 0x3800, transaction = 44) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + while (!dut.io.memoryRequest(0).valid.peek().litToBoolean) dut.clock.step() + val identity = dut.io.memoryRequest(0).bits.identity.peek() + val address = dut.io.memoryRequest(0).bits.address.peek() + dut.clock.step() + dut.io.memoryResponse(0).bits.poke(0.U.asTypeOf(dut.io.memoryResponse(0).bits)) + dut.io.memoryResponse(0).bits.identity.poke(identity) + dut.io.memoryResponse(0).bits.address.poke(address) + dut.io.memoryResponse(0).bits.data.poke("h123456789abcdef0".U) + dut.io.memoryResponse(0).valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse(0).valid.poke(false.B) + while (!dut.io.iex.loadResult(0).valid.peek().litToBoolean) dut.clock.step() + + val prepare = dut.io.recovery.prepare + prepare.bits.poke(0.U.asTypeOf(prepare.bits)) + prepare.bits.transactionId.poke(93.U) + prepare.bits.phase.poke(RecoveryPhase.Prepare) + prepare.bits.cause.poke(RecoveryCause.Branch) + prepare.valid.poke(true.B) + dut.clock.step() + prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(false.B) + dut.clock.step(2) + dut.io.recovery.prepared.valid.expect(false.B) + dut.io.iex.loadResult(0).ready.poke(true.B) + dut.clock.step() + var preparedCycles = 0 + while (!dut.io.recovery.prepared.valid.peek().litToBoolean && preparedCycles < 64) { + dut.clock.step() + preparedCycles += 1 + } + assert(preparedCycles < 64, "retained LRET did not release recovery quiescence") + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala new file mode 100644 index 00000000..f2097a15 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala @@ -0,0 +1,328 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface.{RecoveryCause, RecoveryPhase} +import org.scalatest.funsuite.AnyFunSuite + +class LSULoadSpec extends AnyFunSuite with ChiselSim { + private def initialize(dut: LSU): Unit = { + dut.io.iex.storeReservation.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeData.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadResult.foreach(_.ready.poke(true.B)) + dut.io.iex.loadReissue.foreach(_.ready.poke(true.B)) + dut.io.iex.loadRebindApply.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadRepick.foreach(_.ready.poke(true.B)) + dut.io.iex.loadCancel.foreach(_.ready.poke(true.B)) + dut.io.iex.recoveryEvent.ready.poke(true.B) + dut.io.storeCommit.valid.poke(false.B) + dut.io.storeCommit.bits.poke(0.U.asTypeOf(dut.io.storeCommit.bits)) + dut.io.storeResolve.ready.poke(true.B) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.memoryRequest.foreach(_.ready.poke(true.B)) + dut.io.memoryResponse.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.trace.ready.poke(true.B) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + } + + test("public LSU retains the two-pipe LIQ replay refill and return graph") { + val chirrtl = ChiselStage.emitCHIRRTL(new LSU(SimulationParamProfiles.W4)) + assert(chirrtl.contains("module LoadInflightQueue")) + assert(chirrtl.contains("module ScalarLSUMDBPath")) + assert(chirrtl.contains("module LoadMissQueue")) + assert(chirrtl.contains("module LoadRefillTransport")) + assert(chirrtl.contains("module ScalarLSULoadReturnPipeline")) + assert(!chirrtl.contains("module ReducedLoadReplayLiqAllocPath")) + } + + test("public load issue receives an atomic LIQ binding miss refill and exact result") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + dut.io.iex.storeReservation.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeData.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadResult.foreach(_.ready.poke(true.B)) + dut.io.iex.loadReissue.foreach(_.ready.poke(true.B)) + dut.io.iex.loadRepick.foreach(_.ready.poke(true.B)) + dut.io.iex.loadCancel.foreach(_.ready.poke(true.B)) + dut.io.iex.recoveryEvent.ready.poke(true.B) + dut.io.storeCommit.valid.poke(false.B) + dut.io.storeCommit.bits.poke(0.U.asTypeOf(dut.io.storeCommit.bits)) + dut.io.storeResolve.ready.poke(true.B) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.memoryRequest.foreach(_.ready.poke(true.B)) + dut.io.memoryResponse.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.trace.ready.poke(true.B) + + val issue = dut.io.iex.loadAddress(0) + issue.bits.poke(0.U.asTypeOf(issue.bits)) + issue.bits.identity.rob.peId.poke(1.U) + issue.bits.identity.rob.stid.poke(0.U) + issue.bits.identity.rob.ridSlot.poke(1.U) + issue.bits.identity.rob.ridGeneration.poke(1.U) + issue.bits.identity.rob.memberIndex.poke(0.U) + issue.bits.identity.rob.residentGeneration.poke(1.U) + issue.bits.identity.rob.bid.poke(1.U) + issue.bits.identity.rob.brobGeneration.poke(1.U) + issue.bits.identity.lsid.poke(3.U) + issue.bits.identity.attemptGeneration.poke(1.U) + issue.bits.identity.pipeId.poke(0.U) + issue.bits.address.poke(0x1800.U) + issue.bits.sizeBytes.poke(8.U) + issue.bits.destination.valid.poke(true.B) + issue.bits.destination.atag.poke(2.U) + issue.bits.destination.ptag.poke(3.U) + issue.bits.destination.previousPtag.poke(4.U) + issue.bits.destinationRelativeIndex.poke(2.U) + issue.valid.poke(true.B) + issue.ready.expect(true.B) + dut.io.iex.loadAllocation(0).valid.expect(true.B) + val allocated = dut.io.iex.loadAllocation(0).bits.allocationId.value.peek().litValue + dut.clock.step() + issue.valid.poke(false.B) + + var launched = false + for (_ <- 0 until 4) { + if (dut.io.iex.loadLaunch(0).valid.peek().litToBoolean) { + dut.io.iex.loadLaunch(0).bits.allocationId.value.expect(allocated.U) + dut.io.iex.loadLaunch(0).bits.identity.rob.ridSlot.expect(1.U) + launched = true + } + dut.clock.step() + } + assert(launched, "accepted LIQ allocation must publish its exact launch") + + val request = dut.io.memoryRequest(0) + var requestCycles = 0 + while (!request.valid.peek().litToBoolean && requestCycles < 32) { + dut.clock.step() + requestCycles += 1 + } + assert(requestCycles < 32, "a load miss must publish a lower-memory request") + val requestId = request.bits.identity.value.peek().litValue + val requestGeneration = request.bits.identity.generation.peek().litValue + val requestAddress = request.bits.address.peek().litValue + dut.clock.step() + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(requestId.U) + response.bits.identity.generation.poke(requestGeneration.U) + response.bits.address.poke(requestAddress.U) + response.bits.data.poke("h1122334455667788".U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + val result = dut.io.iex.loadResult(0) + var resultCycles = 0 + while (!result.valid.peek().litToBoolean && resultCycles < 192) { + dut.io.iex.loadResult.drop(1).foreach(_.valid.expect(false.B, + "a semantic lane-0 completion must not be routed by an internal return-pipeline slot")) + dut.clock.step() + resultCycles += 1 + } + assert(resultCycles < 192, + "an accepted lower-memory response must relaunch and complete the exact LIQ row") + result.bits.identity.rob.ridSlot.expect(1.U) + result.bits.identity.attemptGeneration.expect(1.U) + result.bits.data.expect("h1122334455667788".U) + } + } + + test("second load lane is live and LSU alone authors its next replay attempt") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + + val issue = dut.io.iex.loadAddress(1) + issue.bits.poke(0.U.asTypeOf(issue.bits)) + issue.bits.identity.rob.peId.poke(1.U) + issue.bits.identity.rob.stid.poke(0.U) + issue.bits.identity.rob.ridSlot.poke(3.U) + issue.bits.identity.rob.ridGeneration.poke(4.U) + issue.bits.identity.rob.memberIndex.poke(1.U) + issue.bits.identity.rob.residentGeneration.poke(5.U) + issue.bits.identity.rob.bid.poke(2.U) + issue.bits.identity.rob.brobGeneration.poke(6.U) + issue.bits.identity.transaction.value.poke(0x55.U) + issue.bits.identity.transaction.generation.poke(7.U) + issue.bits.identity.lsid.poke(9.U) + issue.bits.identity.attemptGeneration.poke(11.U) + issue.bits.identity.pipeId.poke(1.U) + issue.bits.address.poke(0x3800.U) + issue.bits.sizeBytes.poke(8.U) + issue.bits.destination.valid.poke(true.B) + issue.bits.destination.atag.poke(2.U) + issue.bits.destination.ptag.poke(3.U) + issue.bits.destination.previousPtag.poke(4.U) + issue.bits.destinationRelativeIndex.poke(2.U) + issue.valid.poke(true.B) + issue.ready.expect(true.B) + dut.io.iex.loadAllocation(0).valid.expect(false.B) + dut.io.iex.loadAllocation(1).valid.expect(true.B) + val allocation = dut.io.iex.loadAllocation(1).bits.allocationId.peek() + val current = issue.bits.identity.peek() + dut.clock.step() + issue.valid.poke(false.B) + + var launched = false + for (_ <- 0 until 8) { + if (dut.io.iex.loadLaunch(1).valid.peek().litToBoolean) launched = true + dut.io.iex.loadLaunch(0).valid.expect(false.B) + dut.clock.step() + } + assert(launched, "lane-1 allocation must publish a lane-1 launch") + + val replay = dut.io.loadReissueRequest + replay.bits.poke(0.U.asTypeOf(replay.bits)) + replay.bits.allocationId.poke(allocation) + replay.bits.currentIdentity.poke(current) + replay.bits.address.poke(0x3800.U) + replay.valid.poke(true.B) + replay.ready.expect(true.B) + dut.io.iex.loadReissue(0).valid.expect(false.B) + dut.io.iex.loadReissue(1).valid.expect(true.B) + dut.io.iex.loadReissue(1).bits.currentIdentity.expect(current) + dut.io.iex.loadReissue(1).bits.nextIdentity.transaction.value.expect(0x55.U) + dut.io.iex.loadReissue(1).bits.nextIdentity.transaction.generation.expect(7.U) + dut.io.iex.loadReissue(1).bits.nextIdentity.attemptGeneration.expect(12.U) + dut.clock.step() + replay.valid.poke(false.B) + } + } + + test("typed recovery prunes the affected STID while a peer STID remains replayable") { + val base = SimulationParamProfiles.W4 + val p = base.copy(ooo = base.ooo.copy(stidCount = 2)) + simulate(new LSU(p)) { dut => + initialize(dut) + dut.io.memoryRequest.foreach(_.ready.poke(false.B)) + + def issue(lane: Int, stid: Int, rid: Int, transaction: Int, + lsid: Int, address: Int) = { + val port = dut.io.iex.loadAddress(lane) + port.bits.poke(0.U.asTypeOf(port.bits)) + port.bits.identity.rob.peId.poke(1.U) + port.bits.identity.rob.stid.poke(stid.U) + port.bits.identity.rob.ridSlot.poke(rid.U) + port.bits.identity.rob.ridGeneration.poke(1.U) + port.bits.identity.rob.residentGeneration.poke(1.U) + port.bits.identity.rob.bid.poke(1.U) + port.bits.identity.rob.brobGeneration.poke(1.U) + port.bits.identity.transaction.value.poke(transaction.U) + port.bits.identity.transaction.generation.poke(1.U) + port.bits.identity.lsid.poke(lsid.U) + port.bits.identity.attemptGeneration.poke(1.U) + port.bits.identity.pipeId.poke(lane.U) + port.bits.address.poke(address.U) + port.bits.sizeBytes.poke(8.U) + port.bits.destination.valid.poke(true.B) + port.valid.poke(true.B) + while (!port.ready.peek().litToBoolean) dut.clock.step() + val allocation = dut.io.iex.loadAllocation(lane).bits.allocationId.peek() + val identity = port.bits.identity.peek() + dut.clock.step() + port.valid.poke(false.B) + (allocation, identity) + } + + val (killedAllocation, killedIdentity) = + issue(0, 0, 2, 0x21, 10, 0x4000) + val (peerAllocation, peerIdentity) = + issue(1, 1, 3, 0x22, 11, 0x5000) + dut.clock.step(6) + + def pokePlan(phase: RecoveryPhase.Type): Unit = { + val plan = if (phase == RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits else dut.io.recovery.apply.bits + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(0x77.U) + plan.phase.poke(phase) + plan.cause.poke(RecoveryCause.Branch) + plan.trigger.poke(killedIdentity.rob) + plan.firstKilledValid.poke(true.B) + plan.firstKilled.poke(killedIdentity.rob) + plan.lastKilled.poke(killedIdentity.rob) + plan.killedGroupCount.poke(1.U) + plan.killedMemberCount.poke(1.U) + } + pokePlan(RecoveryPhase.Prepare) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + pokePlan(RecoveryPhase.Apply) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + val replay = dut.io.loadReissueRequest + replay.bits.poke(0.U.asTypeOf(replay.bits)) + replay.bits.allocationId.poke(killedAllocation) + replay.bits.currentIdentity.poke(killedIdentity) + replay.bits.address.poke(0x4000.U) + replay.valid.poke(true.B) + replay.ready.expect(true.B, + "a stale killed replay is a drainable rejection event") + dut.io.iex.loadReissue.foreach(_.valid.expect(false.B)) + dut.clock.step() + replay.bits.allocationId.poke(peerAllocation) + replay.bits.currentIdentity.poke(peerIdentity) + replay.bits.address.poke(0x5000.U) + replay.ready.expect(true.B) + dut.io.iex.loadReissue(1).valid.expect(true.B) + dut.clock.step() + replay.valid.poke(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSUMechanismSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSUMechanismSpec.scala new file mode 100644 index 00000000..8696e222 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSUMechanismSpec.scala @@ -0,0 +1,78 @@ +package linxcore.lsu + +import circt.stage.ChiselStage +import linxcore.common.{CoreParams => ScalarCoreParams, ScalarLsuParams} +import linxcore.params.{ParamProfiles, SimulationParamProfiles} +import org.scalatest.funsuite.AnyFunSuite + +class LSUMechanismSpec extends AnyFunSuite { + private val widths = Seq(2, 4, 6, 8) + + private def unequalCore(width: Int): ScalarCoreParams = { + val main = ParamProfiles.forWidth(width) + val centralized = main.copy( + ooo = main.ooo.copy( + robGroupsPerStid = 8, + maxInstructionsPerRobGroup = 1, + robBankCount = 8), + lsu = main.lsu.copy( + loadQueueEntries = 4, + storeQueueEntries = 16, + loadReturnQueueEntries = 2, + storeCommitQueueEntries = 4, + scbEntries = 4), + lsidWidth = 40) + val projected = ScalarCoreParams.fromMainline(centralized) + projected.copy(scalarLsu = projected.scalarLsu.copy( + loadMissQueueEntries = 2, + loadRefillQueueEntries = 2, + resolveQueueEntries = 4, + mdbSsitEntries = 4, + mdbCommandQueueEntries = 4, + mdbOutputQueueEntries = 4, + mdbWaitPlanQueueEntries = 4, + mdbRecoveryQueueEntries = 4, + mdbFailedWaitTimeoutCycles = 8, + l1dSets = 2, + l1dWays = 2)) + } + + test("W2 W4 W6 and W8 elaborate two-pipe LSU with independent STQ ROB and LSID sizes") { + widths.foreach { width => + val main = ParamProfiles.forWidth(width) + val simulation = SimulationParamProfiles.forWidth(width) + val core = unequalCore(width) + val io = new ScalarLSULoadPathIO(core, core.scalarLsu) + val chirrtl = ChiselStage.emitCHIRRTL(new ScalarLSULoadPath( + core, + useExternalStqForwarding = true, + stqForwardRobEntries = 8, + stqForwardTokenWidth = 40)) + + assert((main.lsu.loadPipes, main.lsu.storePipes) == (2, 2)) + assert((simulation.lsu.loadPipes, simulation.lsu.storePipes) == (2, 2)) + assert(core.commitWidth == width) + assert(core.scalarLsu.loadReturnPipeCount == 2) + assert(core.scalarLsu.commitIssueWidth == 2) + assert(core.scalarLsu.stqEntries == 16) + assert(core.robEntries == 8) + assert(core.lsidWidth == 40) + assert(io.e2Stores.length == 16) + assert(io.e2Stores.head.storeIndex.getWidth == 4) + assert(io.alloc.bid.value.getWidth == 3) + assert(io.alloc.bid.wrap.getWidth == 1) + assert(io.alloc.loadLsIdFull.getWidth == 40) + assert(io.alloc.returnPipeIndex.getWidth == 1) + assert(io.loadReturn.w1ValidMask.getWidth == 2) + assert(chirrtl.contains("module LoadInflightQueue")) + assert(chirrtl.contains("module ScalarLSUMDBPath")) + assert(chirrtl.contains("module LoadMissQueue")) + assert(chirrtl.contains("module LoadRefillTransport")) + assert(chirrtl.contains("module ScalarLSULoadReturnPipeline")) + assert(chirrtl.contains("module ScalarL1D")) + assert(chirrtl.contains("module STQLoadForwardResultPipeline")) + assert(chirrtl.contains("stqForward_queries_1_valid")) + assert(!chirrtl.contains("stqForward_queries_2_valid")) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala b/chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala new file mode 100644 index 00000000..373c25c8 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala @@ -0,0 +1,662 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{MemoryAccessAttributes, PhysicalMemoryRegion, + SimulationParamProfiles} +import linxcore.top.interface.{MemoryAccessKind, MemorySize} +import org.scalatest.funsuite.AnyFunSuite + +trait LSUMemoryTestSupport extends ChiselSim { + this: org.scalatest.TestSuite => + def initialize(dut: LSU): Unit = { + dut.io.iex.storeReservation.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeData.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadResult.foreach(_.ready.poke(true.B)) + dut.io.iex.loadReissue.foreach(_.ready.poke(true.B)) + dut.io.iex.loadRebindApply.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadRepick.foreach(_.ready.poke(true.B)) + dut.io.iex.loadCancel.foreach(_.ready.poke(true.B)) + dut.io.iex.recoveryEvent.ready.poke(true.B) + dut.io.storeCommit.valid.poke(false.B) + dut.io.storeCommit.bits.poke(0.U.asTypeOf(dut.io.storeCommit.bits)) + dut.io.storeResolve.ready.poke(true.B) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.memoryRequest.foreach(_.ready.poke(true.B)) + dut.io.memoryResponse.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.memoryFault.ready.poke(true.B) + dut.io.maintenance.valid.poke(false.B) + dut.io.maintenance.bits.poke(0.U.asTypeOf(dut.io.maintenance.bits)) + dut.io.maintenanceResult.ready.poke(true.B) + dut.io.trace.ready.poke(true.B) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + } + + def pokeLoad(dut: LSU, address: BigInt, transaction: Int = 5): Unit = { + val issue = dut.io.iex.loadAddress(0) + issue.bits.poke(0.U.asTypeOf(issue.bits)) + issue.bits.identity.rob.peId.poke(1.U) + issue.bits.identity.rob.stid.poke(0.U) + issue.bits.identity.rob.ridSlot.poke(1.U) + issue.bits.identity.rob.ridGeneration.poke(2.U) + issue.bits.identity.rob.memberIndex.poke(0.U) + issue.bits.identity.rob.residentGeneration.poke(3.U) + issue.bits.identity.rob.bid.poke(1.U) + issue.bits.identity.rob.brobGeneration.poke(4.U) + issue.bits.identity.transaction.value.poke(transaction.U) + issue.bits.identity.transaction.generation.poke(1.U) + issue.bits.identity.lsid.poke(7.U) + issue.bits.identity.attemptGeneration.poke(1.U) + issue.bits.identity.pipeId.poke(0.U) + issue.bits.pc.poke(0x80.U) + issue.bits.address.poke(address.U) + issue.bits.sizeBytes.poke(8.U) + issue.bits.destination.valid.poke(true.B) + issue.bits.destination.atag.poke(2.U) + issue.bits.destination.ptag.poke(3.U) + issue.bits.destination.previousPtag.poke(4.U) + issue.bits.destinationRelativeIndex.poke(2.U) + issue.valid.poke(true.B) + } +} + +class LSUMemorySpec extends AnyFunSuite with LSUMemoryTestSupport { + + test("a virtual load misses in DTLB before allocating LIQ and ignores a stale translation response") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("8000000000001238", 16) + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, virtualAddress) + + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.io.iex.loadAllocation(0).valid.expect(false.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + + val request = dut.io.memoryRequest(0) + var cycles = 0 + while (!request.valid.peek().litToBoolean && cycles < 16) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 16, "DTLB miss did not publish its retained page request") + request.bits.address.expect(BigInt("8000000000001000", 16).U) + request.bits.size.expect(MemorySize.Bytes8) + val requestId = request.bits.identity.value.peek().litValue + val requestGeneration = request.bits.identity.generation.peek().litValue + dut.clock.step() + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(requestId.U) + response.bits.identity.generation.poke((requestGeneration + 1).U) + response.bits.data.poke(0x42.U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + dut.io.iex.loadAllocation(0).valid.expect(false.B) + + response.bits.identity.value.poke(requestId.U) + response.bits.identity.generation.poke(requestGeneration.U) + response.bits.data.poke(0x42.U) + response.bits.attributesValid.poke(true.B) + response.bits.readable.poke(true.B) + response.bits.writable.poke(true.B) + response.bits.cacheable.poke(true.B) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + dut.io.iex.loadAllocation(0).valid.expect(true.B) + dut.io.iex.loadAllocation(0).bits.identity.transaction.value.expect(5.U) + } + } + + test("translation classifies alignment protection cacheable and device accesses") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("8000000000002000", 16) + simulate(new DSideTranslation(p, entries = 4, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.result.ready.poke(false.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke( + 0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lookup.bits.load.address.poke(0x1003.U) + dut.io.lookup.bits.load.sizeBytes.poke(8.U) + dut.io.lookup.valid.poke(true.B) + dut.io.lookup.ready.expect(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.alignmentFault.expect(true.B) + dut.io.result.ready.poke(true.B) + dut.clock.step() + + dut.io.result.ready.poke(false.B) + dut.io.lookup.bits.load.address.poke(virtualAddress.U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val deniedIdentity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.poke( + 0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.poke(deniedIdentity) + dut.io.memoryResponse.bits.denied.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.accessFault.expect(true.B) + dut.io.result.ready.poke(true.B) + dut.clock.step() + + dut.io.invalidate.poke(true.B) + dut.clock.step() + dut.io.invalidate.poke(false.B) + dut.io.result.ready.poke(false.B) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val deviceIdentity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + val pageNumberWidth = p.physicalAddressWidth - 12 + val devicePpn = BigInt(0xff) << (pageNumberWidth - 8) + dut.io.memoryResponse.bits.poke( + 0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.poke(deviceIdentity) + dut.io.memoryResponse.bits.data.poke(devicePpn.U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(false.B) + dut.io.memoryResponse.bits.cacheable.poke(false.B) + dut.io.memoryResponse.bits.device.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.device.expect(true.B) + dut.io.result.bits.cacheable.expect(false.B) + } + } + + test("cache miss rejects a response generation mismatch then refills and returns exact data") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, 0x2800, transaction = 9) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + + val request = dut.io.memoryRequest(0) + var requestCycles = 0 + while (!request.valid.peek().litToBoolean && requestCycles < 32) { + dut.clock.step() + requestCycles += 1 + } + assert(requestCycles < 32, "load miss did not reach lower memory") + val requestId = request.bits.identity.value.peek().litValue + val requestGeneration = request.bits.identity.generation.peek().litValue + val requestAddress = request.bits.address.peek().litValue + dut.clock.step() + + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(requestId.U) + response.bits.identity.generation.poke((requestGeneration + 1).U) + response.bits.address.poke(requestAddress.U) + response.bits.data.poke("hdeadbeefdeadbeef".U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + for (_ <- 0 until 8) { + dut.io.iex.loadResult(0).valid.expect(false.B) + dut.clock.step() + } + + response.bits.identity.generation.poke(requestGeneration.U) + response.bits.data.poke("h1122334455667788".U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + var resultCycles = 0 + while (!dut.io.iex.loadResult(0).valid.peek().litToBoolean && + resultCycles < 192) { + dut.clock.step() + resultCycles += 1 + } + assert(resultCycles < 192, + "exact response did not retry the cache miss to completion") + dut.io.iex.loadResult(0).bits.data.expect("h1122334455667788".U) + } + } + + test("translated device loads route to the device lower-memory class") { + val p = SimulationParamProfiles.W4 + val virtualAddress = BigInt("8000000000004000", 16) + simulate(new LSU(p)) { dut => + initialize(dut) + pokeLoad(dut, virtualAddress, transaction = 12) + + val request = dut.io.memoryRequest(0) + while (!request.valid.peek().litToBoolean) dut.clock.step() + val translationIdentity = request.bits.identity.peek() + dut.clock.step() + val pageNumberWidth = p.physicalAddressWidth - 12 + val devicePpn = BigInt(0xff) << (pageNumberWidth - 8) + val response = dut.io.memoryResponse(0) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.poke(translationIdentity) + response.bits.data.poke(devicePpn.U) + response.bits.attributesValid.poke(true.B) + response.bits.readable.poke(true.B) + response.bits.writable.poke(true.B) + response.bits.device.poke(true.B) + response.valid.poke(true.B) + dut.clock.step() + response.valid.poke(false.B) + + while (!dut.io.iex.loadAddress(0).ready.peek().litToBoolean) + dut.clock.step() + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + var missCycles = 0 + while (!request.valid.peek().litToBoolean && missCycles < 32) { + dut.clock.step() + missCycles += 1 + } + assert(missCycles < 32, "translated device load did not reach lower memory") + request.bits.accessKind.expect(MemoryAccessKind.Device) + } + } + + test("lower transaction recovery handles zero-cycle completion and retains stale generations") { + val p = SimulationParamProfiles.W4 + simulate(new LSULowerTransactionRecovery( + p, lanes = 2, entries = 4)) { dut => + dut.io.prepareFire.poke(false.B) + dut.io.applyFire.poke(false.B) + dut.io.abortFire.poke(false.B) + dut.io.requestFire.foreach(_.poke(false.B)) + dut.io.requestIdentity.foreach( + _.poke(0.U.asTypeOf(dut.io.requestIdentity.head))) + dut.io.responseFire.foreach(_.poke(false.B)) + dut.io.responseIdentity.foreach( + _.poke(0.U.asTypeOf(dut.io.responseIdentity.head))) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.requestIdentity(0).value.poke(7.U) + dut.io.requestIdentity(0).generation.poke(3.U) + dut.io.responseIdentity(0).poke(dut.io.requestIdentity(0).peek()) + dut.io.requestFire(0).poke(true.B) + dut.io.responseFire(0).poke(true.B) + dut.clock.step() + dut.io.requestFire(0).poke(false.B) + dut.io.responseFire(0).poke(false.B) + dut.io.outstandingCount.expect(0.U) + dut.io.quiescent.expect(true.B) + + dut.io.requestFire(0).poke(true.B) + dut.clock.step() + dut.io.requestFire(0).poke(false.B) + dut.io.outstandingCount.expect(1.U) + dut.io.responseIdentity(0).value.poke(7.U) + dut.io.responseIdentity(0).generation.poke(4.U) + dut.io.responseFire(0).poke(true.B) + dut.io.staleResponse.expect(true.B) + dut.clock.step() + dut.io.responseFire(0).poke(false.B) + dut.io.outstandingCount.expect(1.U) + + dut.io.responseIdentity(0).generation.poke(3.U) + dut.io.responseFire(0).poke(true.B) + dut.clock.step() + dut.io.responseFire(0).poke(false.B) + dut.io.outstandingCount.expect(0.U) + dut.io.quiescent.expect(true.B) + } + } + + test("translation captures a miss only on lookup fire and keeps its namespace across wrap") { + val base = SimulationParamProfiles.W4 + val p = base.copy(lsu = base.lsu.copy(dTranslationCounterBits = 2)) + simulate(new DSideTranslation(p, entries = 2, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.lookup.bits.load.sizeBytes.poke(8.U) + dut.io.result.ready.poke(true.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.clock.step(2) + dut.io.memoryRequest.valid.expect(false.B) + + for (page <- 1 to 5) { + dut.io.lookup.bits.load.address.poke( + (BigInt("8000000000000000", 16) + page * 4096).U) + dut.io.lookup.bits.load.identity.transaction.value.poke((20 + page).U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val value = dut.io.memoryRequest.bits.identity.value.peek().litValue + val generation = + dut.io.memoryRequest.bits.identity.generation.peek().litValue + assert((value >> (p.memoryTransactionIdWidth - 1)) == 1) + assert((generation >> + (p.memoryTransactionGenerationWidth - 1)) == 1) + val identity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.poke(identity) + dut.io.memoryResponse.bits.data.poke((0x40 + page).U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(true.B) + dut.io.memoryResponse.bits.cacheable.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.request.load.identity.transaction.value.expect( + (20 + page).U) + dut.clock.step() + dut.io.invalidate.poke(true.B) + dut.clock.step() + dut.io.invalidate.poke(false.B) + } + } + } + + test("translation enforces independent low mapping and refill read write permissions") { + val base = SimulationParamProfiles.W4 + val mask = BigInt("fffffffffffff000", 16) + val p = base.copy(lsu = base.lsu.copy(physicalMemoryRegions = Seq( + PhysicalMemoryRegion(0x1000, mask, + MemoryAccessAttributes(writable = false)), + PhysicalMemoryRegion(0x2000, mask, + MemoryAccessAttributes(readable = false))))) + simulate(new DSideTranslation(p, entries = 4, pageBytes = 4096)) { dut => + dut.io.lookup.valid.poke(false.B) + dut.io.lookup.bits.poke(0.U.asTypeOf(dut.io.lookup.bits)) + dut.io.result.ready.poke(false.B) + dut.io.invalidate.poke(false.B) + dut.io.memoryRequest.ready.poke(true.B) + dut.io.memoryResponse.valid.poke(false.B) + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lookup.bits.isStore.poke(true.B) + dut.io.lookup.bits.store.address.poke(0x1000.U) + dut.io.lookup.bits.store.sizeBytes.poke(8.U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + dut.io.result.bits.accessFault.expect(true.B) + dut.io.result.ready.poke(true.B) + dut.clock.step() + + dut.io.result.ready.poke(false.B) + dut.io.lookup.bits.isStore.poke(false.B) + dut.io.lookup.bits.load.address.poke(BigInt("8000000000009000", 16).U) + dut.io.lookup.bits.load.sizeBytes.poke(8.U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + while (!dut.io.memoryRequest.valid.peek().litToBoolean) dut.clock.step() + val identity = dut.io.memoryRequest.bits.identity.peek() + dut.clock.step() + dut.io.memoryResponse.bits.poke(0.U.asTypeOf(dut.io.memoryResponse.bits)) + dut.io.memoryResponse.bits.identity.poke(identity) + dut.io.memoryResponse.bits.data.poke(1.U) + dut.io.memoryResponse.bits.attributesValid.poke(true.B) + dut.io.memoryResponse.bits.readable.poke(true.B) + dut.io.memoryResponse.bits.writable.poke(true.B) + dut.io.memoryResponse.bits.cacheable.poke(true.B) + dut.io.memoryResponse.valid.poke(true.B) + dut.clock.step() + dut.io.memoryResponse.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.accessFault.expect(false.B) + dut.io.result.ready.poke(true.B) + dut.clock.step() + + dut.io.result.ready.poke(false.B) + dut.io.lookup.bits.isStore.poke(true.B) + dut.io.lookup.bits.store.address.poke(BigInt("8000000000009000", 16).U) + dut.io.lookup.bits.store.sizeBytes.poke(8.U) + dut.io.lookup.valid.poke(true.B) + dut.clock.step() + dut.io.lookup.valid.poke(false.B) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.accessFault.expect(true.B) + } + } + + test("a full lower ledger turns over a response slot and matches an exact response globally") { + val p = SimulationParamProfiles.W4 + simulate(new LSULowerTransactionRecovery(p, lanes = 2, entries = 4)) { dut => + dut.io.prepareFire.poke(false.B) + dut.io.applyFire.poke(false.B) + dut.io.abortFire.poke(false.B) + dut.io.requestFire.foreach(_.poke(false.B)) + dut.io.requestIdentity.foreach(_.poke(0.U.asTypeOf(dut.io.requestIdentity.head))) + dut.io.responseFire.foreach(_.poke(false.B)) + dut.io.responseIdentity.foreach(_.poke(0.U.asTypeOf(dut.io.responseIdentity.head))) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + for (id <- 1 to 2) { + dut.io.requestIdentity(0).value.poke(id.U) + dut.io.requestIdentity(0).generation.poke(1.U) + dut.io.requestFire(0).poke(true.B) + dut.clock.step() + } + dut.io.requestFire(0).poke(false.B) + dut.io.outstandingCount.expect(2.U) + + dut.io.responseIdentity(1).value.poke(1.U) + dut.io.responseIdentity(1).generation.poke(1.U) + dut.io.responseFire(1).poke(true.B) + dut.io.requestIdentity(0).value.poke(3.U) + dut.io.requestIdentity(0).generation.poke(1.U) + dut.io.requestFire(0).poke(true.B) + dut.clock.step() + dut.io.responseFire(1).poke(false.B) + dut.io.requestFire(0).poke(false.B) + dut.io.outstandingCount.expect(2.U) + dut.io.protocolError.expect(false.B) + + for (id <- Seq(2, 3)) { + dut.io.responseIdentity(0).value.poke(id.U) + dut.io.responseIdentity(0).generation.poke(1.U) + dut.io.responseFire(0).poke(true.B) + dut.clock.step() + } + dut.io.responseFire(0).poke(false.B) + dut.io.quiescent.expect(true.B) + } + } + + test("LR SC reservation recovery clears only the exact memory identity") { + simulate(new ScalarLrScReservationOwner()) { dut => + dut.io.enable.poke(true.B) + dut.io.contextInvalidate.poke(false.B) + dut.io.flushAll.poke(false.B) + dut.io.flushValid.poke(false.B) + dut.io.flushStid.poke(0.U) + dut.io.flushIdentityValid.poke(false.B) + dut.io.flushIdentity.poke(0.U.asTypeOf(dut.io.flushIdentity)) + dut.io.lrCompleteValid.poke(false.B) + dut.io.lrCompleteAccepted.poke(false.B) + dut.io.lrStid.poke(0.U) + dut.io.lrLineAddr.poke(0.U) + dut.io.lrSize.poke(0.U) + dut.io.lrRawData.poke(0.U) + dut.io.lrIdentity.poke(0.U.asTypeOf(dut.io.lrIdentity)) + dut.io.scReqValid.poke(false.B) + dut.io.scReqStid.poke(0.U) + dut.io.scReqLineAddr.poke(0.U) + dut.io.scReqSize.poke(0.U) + dut.io.scReqData.poke(0.U) + dut.io.scReqIdentity.poke(0.U.asTypeOf(dut.io.scReqIdentity)) + dut.io.scCommitReady.poke(false.B) + dut.io.committedStoreInvalidateValid.poke(false.B) + dut.io.committedStoreInvalidateStid.poke(0.U) + dut.io.committedStoreInvalidateLineAddr.poke(0.U) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + dut.io.lrCompleteValid.poke(true.B) + dut.io.lrCompleteAccepted.poke(true.B) + dut.io.lrStid.poke(0.U) + dut.io.lrLineAddr.poke(0x5000.U) + dut.io.lrSize.poke(8.U) + dut.io.lrIdentity.bid.poke(3.U) + dut.io.lrIdentity.gid.valid.poke(true.B) + dut.io.lrIdentity.gid.value.poke(4.U) + dut.io.lrIdentity.rid.valid.poke(true.B) + dut.io.lrIdentity.rid.value.poke(5.U) + dut.io.lrIdentity.lsIdFull.poke(99.U) + dut.clock.step() + dut.io.lrCompleteValid.poke(false.B) + dut.io.lrCompleteAccepted.poke(false.B) + dut.io.reservationValidByStid(0).expect(true.B) + + dut.io.flushValid.poke(true.B) + dut.io.flushIdentityValid.poke(true.B) + dut.io.flushIdentity.poke(dut.io.lrIdentity.peek()) + dut.io.flushIdentity.lsIdFull.poke(100.U) + dut.clock.step() + dut.io.reservationValidByStid(0).expect(true.B) + + dut.io.flushIdentity.lsIdFull.poke(99.U) + dut.clock.step() + dut.io.flushValid.poke(false.B) + dut.io.flushIdentityValid.poke(false.B) + dut.io.reservationValidByStid(0).expect(false.B) + } + } + + test("L1D maintenance preserves peer lines and fails closed on dirty line or global invalidation") { + simulate(new ScalarL1D( + sets = 2, ways = 2, scbEntries = 2, + addrWidth = 64, lineBytes = 64)) { dut => + dut.io.loadLookupValid.poke(false.B) + dut.io.loadLookupLineAddr.poke(0.U) + dut.io.storeLookupValid.poke(false.B) + dut.io.storeLookupLineAddr.poke(0.U) + dut.io.grantWriteValid.poke(false.B) + dut.io.grantWriteLineAddr.poke(0.U) + dut.io.grantWriteData.poke(0.U) + dut.io.storeUpdate.poke(0.U.asTypeOf(dut.io.storeUpdate)) + dut.io.refill.poke(0.U.asTypeOf(dut.io.refill)) + dut.io.evictionReady.poke(true.B) + dut.io.invalidateAll.poke(false.B) + dut.io.invalidateLineValid.poke(false.B) + dut.io.invalidateLineAddr.poke(0.U) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + for ((address, data) <- Seq( + (BigInt(0x1000), BigInt(0x11)), + (BigInt(0x1040), BigInt(0x22)))) { + dut.io.refill.valid.poke(true.B) + dut.io.refill.lineAddr.poke(address.U) + dut.io.refill.data.poke(data.U) + dut.io.refill.writable.poke(true.B) + dut.io.refillReady.expect(true.B) + dut.clock.step() + } + dut.io.refill.valid.poke(false.B) + dut.io.invalidateLineAddr.poke(0x1000.U) + dut.io.invalidateLineValid.poke(true.B) + dut.clock.step() + dut.io.invalidateLineValid.poke(false.B) + + dut.io.loadLookupValid.poke(true.B) + dut.io.loadLookupLineAddr.poke(0x1000.U) + dut.io.loadLookup.readHit.expect(false.B) + dut.io.loadLookupLineAddr.poke(0x1040.U) + dut.io.loadLookup.readHit.expect(true.B) + dut.io.loadLookup.data.expect(0x22.U) + + dut.io.storeUpdate.lineAddr.poke(0x1040.U) + dut.io.storeUpdate.byteMask.poke(1.U) + dut.io.storeUpdate.data.poke(0xaa.U) + dut.io.storeUpdate.valid.poke(true.B) + dut.clock.step() + dut.io.storeUpdate.valid.poke(false.B) + dut.io.dirtyCount.expect(1.U) + + dut.io.invalidateLineAddr.poke(0x1040.U) + dut.io.invalidateLineValid.poke(true.B) + dut.io.protocolError.expect(true.B) + dut.clock.step() + dut.io.invalidateLineValid.poke(false.B) + dut.io.loadLookup.readHit.expect(true.B) + dut.io.dirtyCount.expect(1.U) + + dut.io.invalidateAll.poke(true.B) + dut.io.protocolError.expect(true.B) + dut.clock.step() + dut.io.invalidateAll.poke(false.B) + dut.io.loadLookup.readHit.expect(true.B) + dut.io.loadLookup.data.expect(0xaa.U) + dut.io.dirtyCount.expect(1.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSURecoveryIdentitySpec.scala b/chisel/src/test/scala/linxcore/lsu/LSURecoveryIdentitySpec.scala new file mode 100644 index 00000000..a6b1e10b --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSURecoveryIdentitySpec.scala @@ -0,0 +1,154 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface.{MemoryIdentity, MemoryTransactionIdentity, + RecoveryCause, RecoveryPhase} +import org.scalatest.funsuite.AnyFunSuite + +class LSURecoveryIdentitySpec extends AnyFunSuite with ChiselSim { + private def initialize(dut: LSU): Unit = { + dut.io.iex.storeReservation.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.storeData.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadAddress.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadResult.foreach(_.ready.poke(true.B)) + dut.io.iex.loadReissue.foreach(_.ready.poke(true.B)) + dut.io.iex.loadRebindApply.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.loadRepick.foreach(_.ready.poke(true.B)) + dut.io.iex.loadCancel.foreach(_.ready.poke(true.B)) + dut.io.iex.recoveryEvent.ready.poke(true.B) + dut.io.storeCommit.valid.poke(false.B) + dut.io.storeCommit.bits.poke(0.U.asTypeOf(dut.io.storeCommit.bits)) + dut.io.storeResolve.ready.poke(true.B) + dut.io.loadReissueRequest.valid.poke(false.B) + dut.io.loadReissueRequest.bits.poke( + 0.U.asTypeOf(dut.io.loadReissueRequest.bits)) + dut.io.memoryRequest.foreach(_.ready.poke(false.B)) + dut.io.memoryResponse.foreach { port => + port.valid.poke(false.B); port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.trace.ready.poke(true.B) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + } + + private def issue(dut: LSU, lane: Int, member: Int, transaction: Int, + lsid: BigInt): (MemoryTransactionIdentity, MemoryIdentity) = { + val port = dut.io.iex.loadAddress(lane) + port.bits.poke(0.U.asTypeOf(port.bits)) + port.bits.identity.rob.peId.poke(1.U) + port.bits.identity.rob.stid.poke(0.U) + port.bits.identity.rob.ridSlot.poke(2.U) + port.bits.identity.rob.ridGeneration.poke(3.U) + port.bits.identity.rob.memberIndex.poke(member.U) + port.bits.identity.rob.residentGeneration.poke(4.U) + port.bits.identity.rob.bid.poke(1.U) + port.bits.identity.rob.brobGeneration.poke(5.U) + port.bits.identity.transaction.value.poke(transaction.U) + port.bits.identity.transaction.generation.poke(6.U) + port.bits.identity.lsid.poke(lsid.U) + port.bits.identity.attemptGeneration.poke(1.U) + port.bits.identity.pipeId.poke(lane.U) + port.bits.address.poke((0x4000 + member * 8).U) + port.bits.sizeBytes.poke(8.U) + port.bits.destination.valid.poke(true.B) + port.bits.destination.atag.poke((2 + member).U) + port.bits.destination.ptag.poke((12 + member).U) + port.bits.destination.previousPtag.poke((22 + member).U) + port.bits.destinationRelativeIndex.poke((2 + member).U) + port.valid.poke(true.B) + port.ready.expect(true.B) + val allocation = dut.io.iex.loadAllocation(lane).bits.allocationId.peek() + val identity = port.bits.identity.peek() + dut.clock.step() + port.valid.poke(false.B) + (allocation, identity) + } + + test("recovery fails closed without an exact full LSID and preserves an older same-group row across wrap") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + + val prepare = dut.io.recovery.prepare + prepare.bits.poke(0.U.asTypeOf(prepare.bits)) + prepare.bits.transactionId.poke(0x71.U) + prepare.bits.phase.poke(RecoveryPhase.Prepare) + prepare.bits.cause.poke(RecoveryCause.Branch) + prepare.bits.trigger.peId.poke(1.U) + prepare.bits.trigger.stid.poke(0.U) + prepare.bits.firstKilledValid.poke(true.B) + prepare.bits.firstKilled.poke(prepare.bits.trigger.peek()) + prepare.bits.lastKilled.poke(prepare.bits.trigger.peek()) + prepare.bits.killedGroupCount.poke(1.U) + prepare.bits.killedMemberCount.poke(1.U) + prepare.valid.poke(true.B) + prepare.ready.expect(false.B, + "an unresolved first-killed boundary must not acknowledge prepare") + dut.clock.step() + dut.io.recovery.prepared.valid.expect(false.B) + prepare.valid.poke(false.B) + + val lsidModulus = BigInt(1) << p.lsidWidth + val (olderAllocation, olderIdentity) = + issue(dut, lane = 0, member = 0, transaction = 0x31, + lsid = lsidModulus - 2) + val (killedAllocation, killedIdentity) = + issue(dut, lane = 1, member = 1, transaction = 0x32, lsid = 1) + + prepare.bits.trigger.poke(killedIdentity.rob) + prepare.bits.firstKilled.poke(killedIdentity.rob) + prepare.bits.lastKilled.poke(killedIdentity.rob) + prepare.valid.poke(true.B) + prepare.ready.expect(true.B) + dut.clock.step() + prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + + dut.io.recovery.apply.bits.poke(dut.io.recovery.prepared.bits.peek()) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + val replay = dut.io.loadReissueRequest + replay.bits.poke(0.U.asTypeOf(replay.bits)) + replay.bits.allocationId.poke(killedAllocation) + replay.bits.currentIdentity.poke(killedIdentity) + replay.bits.address.poke(0x4008.U) + replay.valid.poke(true.B) + replay.ready.expect(true.B) + dut.io.iex.loadReissue.foreach(_.valid.expect(false.B)) + dut.clock.step() + + replay.bits.allocationId.poke(olderAllocation) + replay.bits.currentIdentity.poke(olderIdentity) + replay.bits.address.poke(0x4000.U) + replay.ready.expect(true.B) + dut.io.iex.loadReissue(0).valid.expect(true.B, + "the older same-group row before LSID wrap must survive") + dut.clock.step() + replay.valid.poke(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSURefillLineDataSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSURefillLineDataSpec.scala new file mode 100644 index 00000000..3ab2645e --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSURefillLineDataSpec.scala @@ -0,0 +1,30 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class LSURefillLineDataSpec extends AnyFunSuite with ChiselSim { + test("nonuniform 64-byte response preserves bytes at multiple offsets") { + val p = SimulationParamProfiles.W2 + simulate(new LSURefillLineData(p)) { dut => + dut.io.response.poke(0.U.asTypeOf(dut.io.response)) + val bytes = (0 until p.lsu.lineBytes).map(index => + BigInt((index * 37 + 11) & 0xff)) + val line = bytes.zipWithIndex.map { case (byte, index) => + byte << (index * 8) + }.reduce(_ | _) + dut.io.response.data.poke(bytes.take(8).zipWithIndex.map { + case (byte, index) => byte << (index * 8) + }.reduce(_ | _).U) + dut.io.response.lineData.poke(line.U) + dut.io.lineData.expect(line.U) + val observed = dut.io.lineData.peek().litValue + Seq(0, 7, 8, 31, 47, 63).foreach { offset => + assert(((observed >> (offset * 8)) & 0xff) == bytes(offset)) + } + assert(bytes.slice(8, 16).distinct.size > 1) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSURound3PublicSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSURound3PublicSpec.scala new file mode 100644 index 00000000..6728b029 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSURound3PublicSpec.scala @@ -0,0 +1,95 @@ +package linxcore.lsu + +import chisel3._ +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class LSURound3PublicSpec extends AnyFunSuite + with CacheableStorePublicTestSupport { + + private def expectFailedOwnershipResponse( + dut: LSU, + denied: Boolean, + corrupt: Boolean): Unit = { + val p = dut.p + val (value, generation) = publishCacheableStore(dut, 0x6808) + val response = dut.io.memoryResponse(p.lsu.loadPipes + 1) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(value.U) + response.bits.identity.generation.poke(generation.U) + response.bits.denied.poke(denied.B) + response.bits.corrupt.poke(corrupt.B) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + dut.io.protocolError.expect(true.B) + dut.io.quiescent.expect(false.B) + pokeLoad(dut, 0x6808, transaction = 71) + dut.io.iex.loadAddress(0).ready.expect(false.B) + } + + test("denied AcquireWrite fails closed without completing the public SCB path") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + expectFailedOwnershipResponse(dut, denied = true, corrupt = false) + } + } + + test("corrupt AcquireWrite fails closed without completing the public SCB path") { + val p = SimulationParamProfiles.W4 + simulate(new LSU(p)) { dut => + initialize(dut) + expectFailedOwnershipResponse(dut, denied = false, corrupt = true) + } + } + + test("AcquireWrite preserves untouched cacheline bytes around the exact store") { + val p = SimulationParamProfiles.W4 + val originalLine = (0 until 64).foldLeft(BigInt(0)) { (line, byte) => + line | (BigInt(byte) << (byte * 8)) + } + simulate(new LSU(p)) { dut => + initialize(dut) + val (value, generation) = publishCacheableStore(dut, 0x6808) + val response = dut.io.memoryResponse(p.lsu.loadPipes + 1) + response.bits.poke(0.U.asTypeOf(response.bits)) + response.bits.identity.value.poke(value.U) + response.bits.identity.generation.poke(generation.U) + response.bits.lineData.poke(originalLine.U) + response.valid.poke(true.B) + response.ready.expect(true.B) + dut.clock.step() + response.valid.poke(false.B) + + var drainCycles = 0 + while (!dut.io.quiescent.peek().litToBoolean && drainCycles < 64) { + dut.clock.step() + drainCycles += 1 + } + assert(drainCycles < 64, "successful ownership response did not drain") + + def expectLoad(address: BigInt, transaction: Int, expected: BigInt): Unit = { + pokeLoad(dut, address, transaction) + dut.io.iex.loadAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.iex.loadAddress(0).valid.poke(false.B) + var cycles = 0 + while (!dut.io.iex.loadResult(0).valid.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32, f"load at 0x$address%x did not return") + dut.io.iex.loadResult(0).bits.data.expect(expected.U) + dut.clock.step() + } + + expectLoad(0x6800, 72, BigInt("0706050403020100", 16)) + expectLoad(0x6808, 73, BigInt("1122334455667788", 16)) + expectLoad(0x6810, 74, BigInt("1716151413121110", 16)) + dut.io.protocolError.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSUStoreSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSUStoreSpec.scala new file mode 100644 index 00000000..77c8af8c --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSUStoreSpec.scala @@ -0,0 +1,16 @@ +package linxcore.lsu + +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class LSUStoreSpec extends AnyFunSuite { + test("public LSU retains one canonical STQ SCB and L1D owner graph") { + val chirrtl = ChiselStage.emitCHIRRTL(new LSU(SimulationParamProfiles.W4)) + assert(chirrtl.contains("circuit LSU")) + assert(chirrtl.contains("module STQEntryBank")) + assert(chirrtl.contains("module SCBRowBank")) + assert(chirrtl.contains("module ScalarL1D")) + assert(!chirrtl.contains("module ReducedStoreMemoryOverlay")) + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LSUStructuralBlockIntegrationSpec.scala b/chisel/src/test/scala/linxcore/lsu/LSUStructuralBlockIntegrationSpec.scala new file mode 100644 index 00000000..4b98b81e --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LSUStructuralBlockIntegrationSpec.scala @@ -0,0 +1,19 @@ +package linxcore.lsu + +import circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class LSUStructuralBlockIntegrationSpec extends AnyFunSuite { + test("public-LSU-retains-and-retries-structural-STQ-results") { + val systemVerilog = ChiselStage.emitSystemVerilog( + new LSU(SimulationParamProfiles.W4)) + + assert(systemVerilog.contains("module LoadStructuralBlockPolicy")) + assert(systemVerilog.contains("io_iex_loadRepick_0_bits_structural")) + assert(systemVerilog.contains("io_iex_loadRebindApply_0_bits_structural")) + assert(!systemVerilog.contains( + ".io_structuralRetryValid\n (_structuralBlock_io_retry_valid)")) + assert(systemVerilog.contains(".io_hardBlock_ready\n (_structuralBlock_io_hardBlock_ready)")) + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LoadAttemptBindingSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadAttemptBindingSpec.scala index 7c04b2c7..f140713a 100644 --- a/chisel/src/test/scala/linxcore/lsu/LoadAttemptBindingSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/LoadAttemptBindingSpec.scala @@ -2,6 +2,7 @@ package linxcore.lsu import chisel3._ import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage import org.scalatest.funsuite.AnyFunSuite import linxcore.common.ScalarLsuParams @@ -35,6 +36,19 @@ class LoadAttemptBindingHarnessIO( val launchValid = Input(Bool()) val launchAccepted = Output(Bool()) val resolveSources = Input(Bool()) + val forwardResultValid = Input(Bool()) + val forwardResult = Input(new LoadInflightForwardResult( + idEntries = idEntries, storeEntries = 4, lsidWidth = 40)) + val forwardResultAccepted = Output(Bool()) + val forwardResultRejected = Output(Bool()) + val forwardResultRejectedByLoadId = Output(Bool()) + val forwardResultRejectedByAttempt = Output(Bool()) + val forwardResultRejectedByPipe = Output(Bool()) + val forwardResultRejectedByLifecycle = Output(Bool()) + val forwardResultRejectedPermanent = Output(Bool()) + val forwardResultRetryRequired = Output(Bool()) + val forwardResultRetryByRecovery = Output(Bool()) + val forwardResultRetryByMutationConflict = Output(Bool()) val clearRow0 = Input(Bool()) val clearAccepted = Output(Bool()) val lhqRecordValid = Output(Bool()) @@ -42,9 +56,13 @@ class LoadAttemptBindingHarnessIO( val rowStatus = Output(LoadInflightStatus()) val rowLoadId = Output(new ROBID(liqEntries)) val rowAttempt = Output(new LoadAttemptIdentity) + val rowDataComplete = Output(Bool()) + val rowLineData = Output(UInt(512.W)) + val repickMask = Output(UInt(liqEntries.W)) } -class LoadAttemptBindingHarness extends Module { +class LoadAttemptBindingHarness( + val useExternalForwardResult: Boolean = false) extends Module { private val liqEntries = 4 private val idEntries = 8 private val storeEntries = 4 @@ -55,7 +73,8 @@ class LoadAttemptBindingHarness extends Module { liqEntries = liqEntries, idEntries = idEntries, storeEntries = storeEntries, - lsidWidth = 40)) + lsidWidth = 40, + useExternalForwardResult = useExternalForwardResult)) liq.io.flush := io.flush liq.io.preciseFlush := 0.U.asTypeOf(liq.io.preciseFlush) @@ -63,8 +82,12 @@ class LoadAttemptBindingHarness extends Module { liq.io.alloc := io.alloc liq.io.attemptRebindValid := io.rebindValid liq.io.attemptRebind := io.rebind + liq.io.structuralRetryValid := false.B + liq.io.structuralRetry := 0.U.asTypeOf(liq.io.structuralRetry) liq.io.launchValid := io.launchValid liq.io.launchIndex := 0.U + liq.io.launchIntentValid := io.launchValid + liq.io.launchIntentIndex := 0.U liq.io.pickValid := false.B liq.io.pickIndex := 0.U liq.io.scbReturnValid := false.B @@ -78,6 +101,8 @@ class LoadAttemptBindingHarness extends Module { liq.io.e2ScbReturned := io.resolveSources liq.io.e2StqReturned := io.resolveSources liq.io.e2ReturnReady := io.resolveSources + liq.io.forwardResultValid := io.forwardResultValid + liq.io.forwardResult := io.forwardResult liq.io.replayWakeValid := false.B liq.io.replayWake := 0.U.asTypeOf(liq.io.replayWake) liq.io.refillValid := false.B @@ -115,12 +140,30 @@ class LoadAttemptBindingHarness extends Module { io.blockedByStaleAttempt := liq.io.attemptRebindBlockedByStaleAttempt io.blockedByNextAttempt := liq.io.attemptRebindBlockedByNextAttempt io.launchAccepted := liq.io.launchAccepted + io.forwardResultAccepted := liq.io.forwardResultAccepted + io.forwardResultRejected := liq.io.forwardResultRejected + io.forwardResultRejectedByLoadId := + liq.io.forwardResultRejectedByLoadId + io.forwardResultRejectedByAttempt := + liq.io.forwardResultRejectedByAttempt + io.forwardResultRejectedByPipe := liq.io.forwardResultRejectedByPipe + io.forwardResultRejectedByLifecycle := + liq.io.forwardResultRejectedByLifecycle + io.forwardResultRejectedPermanent := + liq.io.forwardResultRejectedPermanent + io.forwardResultRetryRequired := liq.io.forwardResultRetryRequired + io.forwardResultRetryByRecovery := liq.io.forwardResultRetryByRecovery + io.forwardResultRetryByMutationConflict := + liq.io.forwardResultRetryByMutationConflict io.clearAccepted := liq.io.clearResolvedAccepted io.lhqRecordValid := liq.io.lhqRecordValid io.rowValid := liq.io.rows(0).valid io.rowStatus := liq.io.rows(0).status io.rowLoadId := liq.io.rows(0).loadId io.rowAttempt := liq.io.rows(0).attempt + io.rowDataComplete := liq.io.rows(0).dataComplete + io.rowLineData := liq.io.rows(0).lineData + io.repickMask := liq.io.repickMask } class LoadAttemptBindingSpec extends AnyFunSuite with ChiselSim { @@ -132,9 +175,181 @@ class LoadAttemptBindingSpec extends AnyFunSuite with ChiselSim { dut.io.rebind.poke(0.U.asTypeOf(dut.io.rebind)) dut.io.launchValid.poke(false.B) dut.io.resolveSources.poke(false.B) + dut.io.forwardResultValid.poke(false.B) + dut.io.forwardResult.poke(0.U.asTypeOf(dut.io.forwardResult)) dut.io.clearRow0.poke(false.B) } + private def pokeForwardResult( + dut: LoadAttemptBindingHarness, + generation: BigInt, + data: BigInt = BigInt("8877665544332211", 16)): Unit = { + dut.io.forwardResult.poke(0.U.asTypeOf(dut.io.forwardResult)) + dut.io.forwardResult.identity.loadId.valid.poke(true.B) + dut.io.forwardResult.identity.loadId.slot.poke(0.U) + dut.io.forwardResult.identity.loadId.generation.poke(0.U) + pokeAttempt(dut.io.forwardResult.identity.attempt, + nativeBid = 6, ridSlot = 17, generation = generation) + dut.io.forwardResult.identity.returnPipeIndex.poke(0.U) + dut.io.forwardResult.lineData.poke(data.U) + dut.io.forwardResult.validMask.poke("hffffffffffffffff".U) + dut.io.forwardResult.loadByteMask.poke("hff".U) + dut.io.forwardResult.dataComplete.poke(true.B) + dut.io.forwardResult.sourcesReturned.poke(true.B) + dut.io.forwardResult.scbReturned.poke(true.B) + dut.io.forwardResult.stqReturned.poke(true.B) + dut.io.forwardResult.wakeupValid.poke(true.B) + dut.io.forwardResult.missKind.poke(LoadForwardMissKind.NoMiss) + } + + test("external forwarding applies only to the exact canonical row attempt") { + simulate(new LoadAttemptBindingHarness( + useExternalForwardResult = true)) { dut => + clear(dut) + dut.io.allocValid.poke(true.B) + dut.io.alloc.size.poke(8.U) + pokeAttempt(dut.io.alloc.attempt, + nativeBid = 6, ridSlot = 17, generation = 3) + dut.clock.step() + dut.io.allocValid.poke(false.B) + + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + dut.io.rowStatus.expect(LoadInflightStatus.Repick) + + pokeForwardResult(dut, generation = 2) + dut.io.forwardResultValid.poke(true.B) + dut.io.forwardResultAccepted.expect(false.B) + dut.io.forwardResultRejected.expect(true.B) + dut.io.forwardResultRejectedByAttempt.expect(true.B) + dut.io.forwardResultRejectedPermanent.expect(true.B) + dut.io.forwardResultRetryRequired.expect(false.B) + dut.clock.step() + dut.io.rowDataComplete.expect(false.B) + + pokeForwardResult(dut, generation = 3) + dut.io.forwardResult.identity.loadId.generation.poke(1.U) + dut.io.forwardResultAccepted.expect(false.B) + dut.io.forwardResultRejectedByLoadId.expect(true.B) + dut.clock.step() + dut.io.rowDataComplete.expect(false.B) + + pokeForwardResult(dut, generation = 3) + dut.io.forwardResult.identity.returnPipeIndex.poke(1.U) + dut.io.forwardResultAccepted.expect(false.B) + dut.io.forwardResultRejectedByPipe.expect(true.B) + dut.clock.step() + dut.io.rowDataComplete.expect(false.B) + + val expected = BigInt("8877665544332211", 16) + pokeForwardResult(dut, generation = 3, data = expected) + dut.io.forwardResultAccepted.expect(true.B) + dut.io.forwardResultRejected.expect(false.B) + dut.io.lhqRecordValid.expect(true.B) + dut.clock.step() + dut.io.forwardResultValid.poke(false.B) + dut.io.rowDataComplete.expect(true.B) + dut.io.rowLineData.expect(expected.U) + + pokeForwardResult(dut, generation = 3, data = expected) + dut.io.forwardResultValid.poke(true.B) + dut.io.forwardResultAccepted.expect(false.B) + dut.io.forwardResultRejected.expect(true.B) + dut.io.forwardResultRejectedByLifecycle.expect(true.B) + dut.io.forwardResultRejectedPermanent.expect(true.B) + dut.io.forwardResultRetryRequired.expect(false.B) + } + } + + test("recovery collision is retryable while stale lifecycle is permanent") { + simulate(new LoadAttemptBindingHarness( + useExternalForwardResult = true)) { dut => + clear(dut) + dut.io.allocValid.poke(true.B) + dut.io.alloc.size.poke(8.U) + pokeAttempt(dut.io.alloc.attempt, + nativeBid = 6, ridSlot = 17, generation = 3) + dut.clock.step() + dut.io.allocValid.poke(false.B) + + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + + pokeForwardResult(dut, generation = 3) + dut.io.forwardResultValid.poke(true.B) + dut.io.flush.poke(true.B) + dut.io.forwardResultAccepted.expect(false.B) + dut.io.forwardResultRejected.expect(true.B) + dut.io.forwardResultRejectedPermanent.expect(false.B) + dut.io.forwardResultRetryRequired.expect(true.B) + dut.io.forwardResultRetryByRecovery.expect(true.B) + dut.io.forwardResultRetryByMutationConflict.expect(false.B) + } + } + + test("an exact replay-wait result marks only its resident row repick-required") { + simulate(new LoadAttemptBindingHarness( + useExternalForwardResult = true)) { dut => + clear(dut) + dut.io.allocValid.poke(true.B) + dut.io.alloc.size.poke(8.U) + pokeAttempt(dut.io.alloc.attempt, + nativeBid = 6, ridSlot = 17, generation = 3) + dut.clock.step() + dut.io.allocValid.poke(false.B) + + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + + pokeForwardResult(dut, generation = 3) + dut.io.forwardResult.sourcesReturned.poke(false.B) + dut.io.forwardResult.wakeupValid.poke(false.B) + dut.io.forwardResult.missKind.poke(LoadForwardMissKind.AwaitingSources) + dut.io.forwardResultValid.poke(true.B) + dut.io.forwardResultAccepted.expect(true.B) + dut.clock.step() + dut.io.forwardResultValid.poke(false.B) + + dut.io.rowStatus.expect(LoadInflightStatus.Wait) + dut.io.repickMask.expect(1.U, + "AwaitingSources must request a new LSU-authored attempt, not a same-attempt physical pass") + + val current = dut.io.rowAttempt.peek() + dut.io.rebind.poke(0.U.asTypeOf(dut.io.rebind)) + dut.io.rebind.loadId.poke(dut.io.rowLoadId.peek()) + dut.io.rebind.current.poke(current) + dut.io.rebind.next.poke(current) + dut.io.rebind.next.generation.poke(4.U) + dut.io.rebindValid.poke(true.B) + dut.io.rebindReady.expect(true.B) + dut.io.rebindAccepted.expect(true.B) + dut.clock.step() + dut.io.rebindValid.poke(false.B) + + dut.io.rowStatus.expect(LoadInflightStatus.Wait) + dut.io.rowAttempt.generation.expect(4.U) + dut.io.repickMask.expect(0.U) + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B, + "the LSU-authored next attempt must become launchable only after common rebind fire") + } + } + + test("external forwarding mode elaborates without the compatibility CAM") { + val sv = ChiselStage.emitSystemVerilog( + new LoadAttemptBindingHarness(useExternalForwardResult = true)) + assert(sv.contains("module LoadAttemptBindingHarness")) + assert(!sv.contains("module LoadForwardPipeline")) + assert(!sv.contains("module LoadStoreForwarding")) + assert(sv.contains("io_forwardResultAccepted")) + } + private def pokeAttempt( attempt: LoadAttemptIdentity, nativeBid: Int, diff --git a/chisel/src/test/scala/linxcore/lsu/LoadAttemptRebindTransitionSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadAttemptRebindTransitionSpec.scala new file mode 100644 index 00000000..faf439aa --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LoadAttemptRebindTransitionSpec.scala @@ -0,0 +1,128 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +private class LoadAttemptRebindTransitionHarnessIO extends Bundle { + val current = Input(new LoadInflightRow( + liqEntries = 4, idEntries = 8, storeEntries = 4)) + val nextAttempt = Input(new LoadAttemptIdentity) + val lifecycleReady = Output(Bool()) + val next = Output(new LoadInflightRow( + liqEntries = 4, idEntries = 8, storeEntries = 4)) +} + +private class LoadAttemptRebindTransitionHarness extends Module { + val io = IO(new LoadAttemptRebindTransitionHarnessIO) + io.lifecycleReady := + LoadAttemptRebindTransition.lifecycleReady(io.current.status) + io.next := LoadAttemptRebindTransition.next(io.current, io.nextAttempt) +} + +class LoadAttemptRebindTransitionSpec extends AnyFunSuite with ChiselSim { + private def pokeAttempt(attempt: LoadAttemptIdentity, + generation: Int): Unit = { + attempt.poke(0.U.asTypeOf(attempt)) + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(3.U) + attempt.producer.stid.poke(1.U) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke(6.U) + attempt.producer.brobGeneration.poke(7.U) + attempt.producer.ridSlot.poke(5.U) + attempt.producer.ridGeneration.poke(4.U) + attempt.producer.memberIndex.poke(2.U) + attempt.producer.residentGeneration.poke(9.U) + attempt.generation.poke(generation.U) + } + + private def pokeDirtyRow(dut: LoadAttemptRebindTransitionHarness, + status: LoadInflightStatus.Type): Unit = { + val row = dut.io.current + row.poke(0.U.asTypeOf(row)) + row.valid.poke(true.B) + row.status.poke(status) + row.loadId.valid.poke(true.B) + row.loadId.value.poke(2.U) + row.loadId.wrap.poke(true.B) + row.pc.poke(0x1234.U) + row.addr.poke(0x5678.U) + row.loadLsIdFullValid.poke(true.B) + row.loadLsIdFull.poke(0x45.U) + row.returnPipeIndex.poke(0.U) + pokeAttempt(row.attempt, 8) + row.forwardPending.poke(true.B) + row.lineData.poke(0xdead.U) + row.validMask.poke(0xff.U) + row.loadByteMask.poke(0xf0.U) + row.forwardMask.poke(0x0f.U) + row.waitMask.poke(0x33.U) + row.secondSegmentActive.poke(true.B) + row.firstSegmentDone.poke(true.B) + row.firstLineData.poke(0xbeef.U) + row.firstValidMask.poke(0xaa.U) + row.firstLoadByteMask.poke(0x55.U) + row.firstForwardMask.poke(0x11.U) + row.waitStore.poke(true.B) + row.storeBypass.poke(true.B) + row.dataComplete.poke(true.B) + row.sourcesReturned.poke(true.B) + row.scbReturned.poke(true.B) + row.stqReturned.poke(true.B) + row.l1Hit.poke(true.B) + row.l1Miss.poke(true.B) + row.missKind.poke(LoadForwardMissKind.DataNotComplete) + pokeAttempt(dut.io.nextAttempt, 9) + } + + for (status <- Seq(LoadInflightStatus.Wait, LoadInflightStatus.L1DcMiss, + LoadInflightStatus.L2Wait)) { + test(s"accepted ${status.toString} rebind preserves ownership and clears old-attempt evidence") { + simulate(new LoadAttemptRebindTransitionHarness) { dut => + pokeDirtyRow(dut, status) + dut.io.lifecycleReady.expect(true.B) + dut.io.next.valid.expect(true.B) + dut.io.next.status.expect(LoadInflightStatus.Wait) + dut.io.next.loadId.valid.expect(true.B) + dut.io.next.loadId.value.expect(2.U) + dut.io.next.loadId.wrap.expect(true.B) + dut.io.next.pc.expect(0x1234.U) + dut.io.next.addr.expect(0x5678.U) + dut.io.next.loadLsIdFull.expect(0x45.U) + dut.io.next.returnPipeIndex.expect(0.U) + dut.io.next.attempt.generation.expect(9.U) + dut.io.next.attempt.producer.expect(dut.io.current.attempt.producer.peek()) + dut.io.next.forwardPending.expect(false.B) + dut.io.next.lineData.expect(0.U) + dut.io.next.validMask.expect(0.U) + dut.io.next.loadByteMask.expect(0.U) + dut.io.next.forwardMask.expect(0.U) + dut.io.next.waitMask.expect(0.U) + dut.io.next.secondSegmentActive.expect(false.B) + dut.io.next.firstSegmentDone.expect(false.B) + dut.io.next.firstLineData.expect(0.U) + dut.io.next.waitStore.expect(false.B) + dut.io.next.storeBypass.expect(false.B) + dut.io.next.dataComplete.expect(false.B) + dut.io.next.sourcesReturned.expect(false.B) + dut.io.next.scbReturned.expect(false.B) + dut.io.next.stqReturned.expect(false.B) + dut.io.next.l1Hit.expect(false.B) + dut.io.next.l1Miss.expect(false.B) + dut.io.next.missKind.expect(LoadForwardMissKind.NoMiss) + } + } + } + + test("terminal and in-flight nonreplayable states reject rebind") { + simulate(new LoadAttemptRebindTransitionHarness) { dut => + for (status <- Seq(LoadInflightStatus.Idle, LoadInflightStatus.Repick, + LoadInflightStatus.Resolved)) { + pokeDirtyRow(dut, status) + dut.io.lifecycleReady.expect(false.B) + } + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LoadForwardResultRetainerSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadForwardResultRetainerSpec.scala new file mode 100644 index 00000000..3f25bb8d --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LoadForwardResultRetainerSpec.scala @@ -0,0 +1,79 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +class LoadForwardResultRetainerSpec extends AnyFunSuite with ChiselSim { + private def pokeResult( + result: LoadInflightForwardResult, + slot: Int, + generation: Int): Unit = { + result.poke(0.U.asTypeOf(result)) + result.identity.loadId.valid.poke(true.B) + result.identity.loadId.slot.poke(slot.U) + result.identity.loadId.generation.poke(generation.U) + } + + test("retains a retryable head and drains it only on accept or permanent stale") { + simulate(new LoadForwardResultRetainer( + idEntries = 8, + storeEntries = 4, + depth = 3, + lsidWidth = 40)) { dut => + dut.io.flush.poke(false.B) + dut.io.in.valid.poke(false.B) + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.sinkAccepted.poke(false.B) + dut.io.sinkRejectedPermanent.poke(false.B) + dut.io.sinkRetryRequired.poke(false.B) + dut.clock.step() + + pokeResult(dut.io.in.bits, slot = 1, generation = 2) + dut.io.in.valid.poke(true.B) + dut.io.in.ready.expect(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + + dut.io.outValid.expect(true.B) + dut.io.out.identity.loadId.slot.expect(1.U) + dut.io.sinkRetryRequired.poke(true.B) + dut.clock.step(2) + dut.io.outValid.expect(true.B) + dut.io.out.identity.loadId.slot.expect(1.U) + dut.io.count.expect(1.U) + + dut.io.sinkRetryRequired.poke(false.B) + dut.io.sinkAccepted.poke(true.B) + dut.clock.step() + dut.io.sinkAccepted.poke(false.B) + dut.io.outValid.expect(false.B) + dut.io.count.expect(0.U) + + pokeResult(dut.io.in.bits, slot = 2, generation = 3) + dut.io.in.valid.poke(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + dut.io.outValid.expect(true.B) + dut.io.sinkRejectedPermanent.poke(true.B) + dut.clock.step() + dut.io.sinkRejectedPermanent.poke(false.B) + dut.io.outValid.expect(false.B) + dut.io.count.expect(0.U) + + pokeResult(dut.io.in.bits, slot = 3, generation = 4) + dut.io.in.valid.poke(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + dut.io.outValid.expect(true.B) + dut.io.sinkRetryRequired.poke(true.B) + dut.io.flush.poke(true.B) + dut.clock.step() + dut.io.flush.poke(false.B) + dut.io.sinkRetryRequired.poke(false.B) + dut.io.outValid.expect(false.B) + dut.io.count.expect(0.U) + dut.io.protocolError.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala index 97626a52..2bda9104 100644 --- a/chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala @@ -46,7 +46,7 @@ object LoadMissQueueReference { def miss(lineAddr: BigInt, dependent: Dependent): String = { val lineMatches = rows.zipWithIndex.collect { - case (Some(row), idx) if row.lineAddr == lineAddr => idx + case (Some(row), idx) if row.lineAddr == lineAddr && row.dependents.nonEmpty => idx } require(lineMatches.size <= 1, "duplicate line owner") val occupiedElsewhere = rows.zipWithIndex.exists { @@ -131,6 +131,21 @@ object LoadMissQueueReference { def hardFlush(): Int = prune(_ => true) + def cancel(dependent: Dependent): Boolean = { + val matches = rows.zipWithIndex.collect { + case (Some(row), idx) + if row.dependents.get(dependent.loadIndex).contains(dependent) => idx + } + if (matches.size != 1) false + else { + val idx = matches.head + val row = rows(idx).get + rows = rows.updated(idx, Some(row.copy( + dependents = row.dependents - dependent.loadIndex))) + true + } + } + def response( missId: MissId, lineAddr: BigInt, @@ -153,7 +168,7 @@ object LoadMissQueueReference { accepted = true, matched = true, stale = false, - refill = isRead, + refill = isRead && deps.nonEmpty, dependents = if (isRead) deps else Set.empty) } } @@ -207,12 +222,31 @@ class LoadMissQueueSpec extends AnyFunSuite { assert(q.orphanMask == (1 << request.missId.slot)) assert(q.pending) - assert(q.miss(0x1000, Dependent(loadIndex = 2, stid = 0)) == "coalesced") + assert(q.miss(0x1000, Dependent(loadIndex = 2, stid = 0)) == "allocated") + val replay = q.acceptRequest(ready = true).get val response = q.response(request.missId, request.lineAddr) - assert(response.refill && response.dependents == Set(2)) + assert(!response.refill && response.dependents.isEmpty) + val replayResponse = q.response(replay.missId, replay.lineAddr) + assert(replayResponse.refill && replayResponse.dependents == Set(2)) assert(!q.pending) } + test("exact attempt cancel tombstones old traffic and isolates replay") { + val q = new QueueModel(entries = 4) + val old = Dependent(loadIndex = 3, loadGeneration = false, bid = 2) + val next = old.copy(loadGeneration = true) + assert(q.miss(0x1800, old) == "allocated") + val oldRequest = q.acceptRequest(ready = true).get + assert(!q.cancel(next)) + assert(q.cancel(old)) + assert(q.orphanMask == (1 << oldRequest.missId.slot)) + assert(q.miss(0x1800, next) == "allocated") + val nextRequest = q.acceptRequest(ready = true).get + assert(nextRequest.missId != oldRequest.missId) + assert(!q.response(oldRequest.missId, oldRequest.lineAddr).refill) + assert(q.response(nextRequest.missId, nextRequest.lineAddr).refill) + } + test("unissued empty entries cancel without traffic") { val q = new QueueModel(entries = 2) q.miss(0x1000, Dependent(loadIndex = 0)) diff --git a/chisel/src/test/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControlSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControlSpec.scala deleted file mode 100644 index cf543b93..00000000 --- a/chisel/src/test/scala/linxcore/lsu/LoadReplayReturnReducedScalarShapeControlSpec.scala +++ /dev/null @@ -1,99 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object LoadReplayReturnReducedScalarShapeControlReference { - final case class Result( - active: Boolean, - reducedScalarShapeValid: Boolean, - reducedSingleLane: Boolean, - scalarLoadPair: Boolean, - vectorOrMemMultiLane: Boolean, - retLaneBefore: Int, - returnedLaneCount: Int, - realReqCnt: Int, - isMemIex: Boolean, - isTload: Boolean, - subInstCntBefore: Int, - isVectorMachine: Boolean, - blockedByDisabled: Boolean, - blockedByFlush: Boolean) - - def apply(enable: Boolean, flush: Boolean): Result = { - val active = enable && !flush - - Result( - active = active, - reducedScalarShapeValid = active, - reducedSingleLane = true, - scalarLoadPair = false, - vectorOrMemMultiLane = false, - retLaneBefore = 0, - returnedLaneCount = 1, - realReqCnt = 1, - isMemIex = false, - isTload = false, - subInstCntBefore = 0, - isVectorMachine = false, - blockedByDisabled = !enable, - blockedByFlush = enable && flush) - } -} - -class LoadReplayReturnReducedScalarShapeControlSpec extends AnyFunSuite { - import LoadReplayReturnReducedScalarShapeControlReference._ - - test("publishes the ordinary scalar one-lane non-TLOAD shape when active") { - val result = LoadReplayReturnReducedScalarShapeControlReference( - enable = true, - flush = false) - - assert(result.active) - assert(result.reducedScalarShapeValid) - assert(result.reducedSingleLane) - assert(!result.scalarLoadPair) - assert(!result.vectorOrMemMultiLane) - assert(result.retLaneBefore == 0) - assert(result.returnedLaneCount == 1) - assert(result.realReqCnt == 1) - assert(!result.isMemIex) - assert(!result.isTload) - assert(result.subInstCntBefore == 0) - assert(!result.isVectorMachine) - } - - test("reports disabled and flush blockers without changing shape constants") { - val disabled = LoadReplayReturnReducedScalarShapeControlReference( - enable = false, - flush = false) - assert(disabled.blockedByDisabled) - assert(!disabled.active) - assert(!disabled.reducedScalarShapeValid) - assert(disabled.reducedSingleLane) - assert(disabled.returnedLaneCount == 1) - assert(disabled.realReqCnt == 1) - - val flushed = LoadReplayReturnReducedScalarShapeControlReference( - enable = true, - flush = true) - assert(flushed.blockedByFlush) - assert(!flushed.active) - assert(!flushed.reducedScalarShapeValid) - assert(flushed.reducedSingleLane) - assert(!flushed.isVectorMachine) - } - - test("Chisel LoadReplayReturnReducedScalarShapeControl elaborates shape diagnostics") { - val sv = ChiselStage.emitSystemVerilog( - new LoadReplayReturnReducedScalarShapeControl(countWidth = 8)) - - assert(sv.contains("module LoadReplayReturnReducedScalarShapeControl")) - assert(sv.contains("io_reducedScalarShapeValid")) - assert(sv.contains("io_reducedSingleLane")) - assert(sv.contains("io_scalarLoadPair")) - assert(sv.contains("io_vectorOrMemMultiLane")) - assert(sv.contains("io_isMemIex")) - assert(sv.contains("io_isVectorMachine")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/LoadReplaySourceReturnStoreSnapshotPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadReplaySourceReturnStoreSnapshotPathSpec.scala index f591b7c6..6d2ba312 100644 --- a/chisel/src/test/scala/linxcore/lsu/LoadReplaySourceReturnStoreSnapshotPathSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/LoadReplaySourceReturnStoreSnapshotPathSpec.scala @@ -1827,18 +1827,12 @@ class LoadReplaySourceReturnStoreSnapshotPathSpec extends AnyFunSuite { tidWidth = 8, storeEntries = 16, lsidWidth = 40) - val liqIo = new ReducedLoadReplayLiqAllocPathIO( - liqEntries = 4, - idEntries = 8, - storeEntries = 16) - assert(pathIo.responseWaitStoreIndex.getWidth == 4) assert(pathIo.responseApplyWaitStoreInfo.storeIndex.getWidth == 4) assert(pathIo.rowStatePlanNextWaitStoreInfo.storeIndex.getWidth == 4) assert(pathIo.rowMutationNextWaitStoreInfo.storeIndex.getWidth == 4) assert(responseQueueIo.enqueue.waitStoreIndex.getWidth == 4) assert(responseQueueIo.headWaitStoreIndex.getWidth == 4) - assert(liqIo.rowMutationNextWaitStoreInfo.storeIndex.getWidth == 4) assert(pathIo.responseApplyWaitStoreInfo.storeId.value.getWidth == 3) assert(pathIo.selectedLoadLsIdFull.getWidth == 40) assert(pathIo.requestPayload.loadLsIdFull.getWidth == 40) diff --git a/chisel/src/test/scala/linxcore/lsu/LoadStructuralBlockPolicySpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadStructuralBlockPolicySpec.scala new file mode 100644 index 00000000..72ed0ec3 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LoadStructuralBlockPolicySpec.scala @@ -0,0 +1,165 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +class LoadStructuralBlockPolicySpec extends AnyFunSuite with ChiselSim { + private def clear(dut: LoadStructuralBlockPolicy): Unit = { + dut.io.hardFlush.poke(false.B) + dut.io.recoveryKill.poke(false.B) + dut.io.recoveryFire.poke(false.B) + dut.io.hardBlock.valid.poke(false.B) + dut.io.hardBlock.bits.poke(0.U.asTypeOf(dut.io.hardBlock.bits)) + dut.io.retry.ready.poke(false.B) + } + + private def pokeAttempt( + attempt: LoadAttemptIdentity, + generation: BigInt): Unit = { + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(2.U) + attempt.producer.stid.poke(1.U) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke(7.U) + attempt.producer.brobGeneration.poke(11.U) + attempt.producer.ridSlot.poke(13.U) + attempt.producer.ridGeneration.poke(17.U) + attempt.producer.memberIndex.poke(19.U) + attempt.producer.residentGeneration.poke(23.U) + attempt.generation.poke(generation.U) + } + + private def pokeBaseHardBlock( + dut: LoadStructuralBlockPolicy, + generation: BigInt = 9): Unit = { + dut.io.hardBlock.bits.poke(0.U.asTypeOf(dut.io.hardBlock.bits)) + dut.io.hardBlock.bits.query.loadId.valid.poke(true.B) + dut.io.hardBlock.bits.query.loadId.slot.poke(3.U) + dut.io.hardBlock.bits.query.loadId.generation.poke(1.U) + pokeAttempt(dut.io.hardBlock.bits.query.attempt, generation) + dut.io.hardBlock.bits.query.returnPipeIndex.poke(2.U) + dut.io.hardBlock.bits.query.loadLsIdFullValid.poke(true.B) + dut.io.hardBlock.bits.query.loadLsIdFull.poke("h456".U) + dut.io.hardBlock.bits.unknownOlderMask.poke(4.U) + dut.io.hardBlock.bits.unknownWaitStore.valid.poke(true.B) + dut.io.hardBlock.bits.unknownWaitStore.storeIndex.poke(2.U) + dut.io.hardBlock.bits.unknownWaitStore.storeId.valid.poke(true.B) + dut.io.hardBlock.bits.unknownWaitStore.storeId.value.poke(5.U) + dut.io.hardBlock.bits.unknownWaitStore.storeLsId.valid.poke(true.B) + dut.io.hardBlock.bits.unknownWaitStore.storeLsId.value.poke(6.U) + dut.io.hardBlock.bits.unknownWaitStore.storeLsIdFullValid.poke(true.B) + dut.io.hardBlock.bits.unknownWaitStore.storeLsIdFull.poke("h123".U) + dut.io.hardBlock.bits.unknownWaitStore.pc.poke("h80000100".U) + } + + private def newPolicy = new LoadStructuralBlockPolicy( + robEntries = 8, + liqEntries = 4, + stqEntries = 4, + stidWidth = 4, + lsidWidth = 40, + tokenWidth = 11) + + test("unknown older store retains an exact wait retry under backpressure") { + simulate(newPolicy) { dut => + clear(dut) + pokeBaseHardBlock(dut) + dut.io.hardBlock.valid.poke(true.B) + dut.io.hardBlock.ready.expect(true.B) + dut.clock.step() + + dut.io.hardBlock.valid.poke(false.B) + for (_ <- 0 until 3) { + dut.io.pending.expect(true.B) + dut.io.unsupported.expect(false.B) + dut.io.disposition.expect(LoadStructuralBlockDisposition.WaitStore) + dut.io.retry.valid.expect(true.B) + dut.io.retry.bits.loadId.valid.expect(true.B) + dut.io.retry.bits.loadId.slot.expect(3.U) + dut.io.retry.bits.loadId.generation.expect(1.U) + dut.io.retry.bits.current.generation.expect(9.U) + dut.io.retry.bits.next.generation.expect(10.U) + dut.io.retry.bits.returnPipeIndex.expect(2.U) + dut.io.retry.bits.waitStore.expect(true.B) + dut.io.retry.bits.waitStoreInfo.storeIndex.expect(2.U) + dut.io.retry.bits.waitStoreInfo.storeId.value.expect(5.U) + dut.io.retry.bits.waitStoreInfo.storeLsIdFull.expect("h123".U) + dut.clock.step() + } + + dut.io.retry.ready.poke(true.B) + dut.io.retry.valid.expect(true.B) + dut.clock.step() + dut.io.pending.expect(false.B) + dut.io.empty.expect(true.B) + } + } + + test("stale snapshot outranks an unknown wait store") { + simulate(newPolicy) { dut => + clear(dut) + pokeBaseHardBlock(dut) + dut.io.hardBlock.bits.staleSnapshotMask.poke(2.U) + dut.io.hardBlock.valid.poke(true.B) + dut.clock.step() + + dut.io.hardBlock.valid.poke(false.B) + dut.io.disposition.expect(LoadStructuralBlockDisposition.RetrySnapshot) + dut.io.retry.valid.expect(true.B) + dut.io.retry.bits.waitStore.expect(false.B) + dut.io.retry.bits.waitStoreInfo.valid.expect(false.B) + dut.io.retry.bits.next.generation.expect(10.U) + } + } + + test("missing ordering authority remains fail closed until hard flush") { + simulate(newPolicy) { dut => + clear(dut) + pokeBaseHardBlock(dut) + dut.io.hardBlock.bits.fullLsIdMissingMask.poke(1.U) + dut.io.hardBlock.valid.poke(true.B) + dut.clock.step() + + dut.io.hardBlock.valid.poke(false.B) + dut.io.pending.expect(true.B) + dut.io.unsupported.expect(true.B) + dut.io.disposition.expect(LoadStructuralBlockDisposition.Unsupported) + dut.io.protocolError.expect(true.B) + dut.io.retry.valid.expect(false.B) + dut.clock.step(3) + dut.io.pending.expect(true.B) + dut.io.protocolError.expect(true.B) + + dut.io.hardFlush.poke(true.B) + dut.clock.step() + dut.io.pending.expect(false.B) + dut.io.protocolError.expect(false.B) + dut.io.empty.expect(true.B) + } + } + + test("only an exact typed recovery kill clears a resident record") { + simulate(newPolicy) { dut => + clear(dut) + pokeBaseHardBlock(dut) + dut.io.hardBlock.valid.poke(true.B) + dut.clock.step() + + dut.io.hardBlock.valid.poke(false.B) + dut.io.recoveryKill.poke(false.B) + dut.io.recoveryReady.expect(false.B) + dut.io.recoveryFire.poke(true.B) + dut.clock.step() + dut.io.pending.expect(true.B) + + dut.io.recoveryKill.poke(true.B) + dut.io.recoveryReady.expect(true.B) + dut.io.recoveryFire.poke(true.B) + dut.clock.step() + dut.io.pending.expect(false.B) + dut.io.empty.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/LoadStructuralRetrySpec.scala b/chisel/src/test/scala/linxcore/lsu/LoadStructuralRetrySpec.scala new file mode 100644 index 00000000..94810352 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/LoadStructuralRetrySpec.scala @@ -0,0 +1,260 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +class LoadStructuralRetryHarnessIO( + val liqEntries: Int, + val idEntries: Int, + val storeEntries: Int) extends Bundle { + val flush = Input(Bool()) + val allocValid = Input(Bool()) + val alloc = Input(new LoadInflightAlloc( + liqEntries = liqEntries, + idEntries = idEntries, + returnPipeCount = 3, + lsidWidth = 40)) + val allocAccepted = Output(Bool()) + val launchValid = Input(Bool()) + val launchAccepted = Output(Bool()) + val retryValid = Input(Bool()) + val retry = Input(new LoadStructuralBlockRetry( + idEntries, storeEntries, lsidWidth = 40)) + val retryReady = Output(Bool()) + val retryAccepted = Output(Bool()) + val blockedByAttempt = Output(Bool()) + val blockedByPipe = Output(Bool()) + val blockedByWaitStore = Output(Bool()) + val blockedByMutation = Output(Bool()) + val mutationConflict = Input(Bool()) + val row = Output(new LoadInflightRow( + liqEntries = liqEntries, + idEntries = idEntries, + storeEntries = storeEntries, + returnPipeCount = 3, + lsidWidth = 40)) +} + +class LoadStructuralRetryHarness extends Module { + private val liqEntries = 4 + private val idEntries = 8 + private val storeEntries = 4 + + val io = IO(new LoadStructuralRetryHarnessIO( + liqEntries, idEntries, storeEntries)) + + val liq = Module(new LoadInflightQueue( + liqEntries = liqEntries, + idEntries = idEntries, + storeEntries = storeEntries, + returnPipeCount = 3, + lsidWidth = 40, + useExternalForwardResult = true)) + + liq.io.flush := io.flush + liq.io.preciseFlush := 0.U.asTypeOf(liq.io.preciseFlush) + liq.io.allocValid := io.allocValid + liq.io.alloc := io.alloc + liq.io.attemptRebindValid := false.B + liq.io.attemptRebind := 0.U.asTypeOf(liq.io.attemptRebind) + liq.io.structuralRetryValid := io.retryValid + liq.io.structuralRetry := io.retry + liq.io.launchValid := io.launchValid + liq.io.launchIndex := 0.U + liq.io.launchIntentValid := io.launchValid + liq.io.launchIntentIndex := 0.U + liq.io.pickValid := false.B + liq.io.pickIndex := 0.U + liq.io.scbReturnValid := false.B + liq.io.scbReturnIndex := 0.U + liq.io.markResolvedValid := false.B + liq.io.markResolvedIndex := 0.U + liq.io.e2Stores := 0.U.asTypeOf(liq.io.e2Stores) + liq.io.e2BaseData := 0.U + liq.io.e2BaseValidMask := 0.U + liq.io.e2LoadDataReturned := false.B + liq.io.e2ScbReturned := false.B + liq.io.e2StqReturned := false.B + liq.io.e2ReturnReady := false.B + liq.io.forwardResultValid := false.B + liq.io.forwardResult := 0.U.asTypeOf(liq.io.forwardResult) + liq.io.replayWakeValid := false.B + liq.io.replayWake := 0.U.asTypeOf(liq.io.replayWake) + liq.io.refillValid := false.B + liq.io.refill := 0.U.asTypeOf(liq.io.refill) + liq.io.clearResolvedValid := false.B + liq.io.clearResolvedIndex := 0.U + liq.io.rowMutationValid := io.mutationConflict + liq.io.rowMutationTargetIndex := 0.U + liq.io.rowMutationSetWaitStatus := false.B + liq.io.rowMutationKeepRepickStatus := false.B + liq.io.rowMutationClearReturnState := false.B + liq.io.rowMutationLineWrite := false.B + liq.io.rowMutationWaitStoreWrite := false.B + liq.io.rowMutationNextWaitStore := false.B + liq.io.rowMutationNextWaitStoreInfo := + 0.U.asTypeOf(liq.io.rowMutationNextWaitStoreInfo) + liq.io.rowMutationNextLineData := 0.U + liq.io.rowMutationNextValidMask := 0.U + liq.io.rowMutationNextDataComplete := false.B + liq.io.rowMutationNextScbReturned := false.B + liq.io.rowMutationNextStqReturned := false.B + liq.io.rowMutationNextStoreSourceReturned := false.B + liq.io.rowMutationAllowWaitTarget := false.B + liq.io.rowMutationRequireScbReturned := false.B + + io.allocAccepted := liq.io.allocAccepted + io.launchAccepted := liq.io.launchAccepted + io.retryReady := liq.io.structuralRetryReady + io.retryAccepted := liq.io.structuralRetryAccepted + io.blockedByAttempt := liq.io.structuralRetryBlockedByAttempt + io.blockedByPipe := liq.io.structuralRetryBlockedByPipe + io.blockedByWaitStore := liq.io.structuralRetryBlockedByWaitStore + io.blockedByMutation := liq.io.structuralRetryBlockedByMutation + io.row := liq.io.rows(0) +} + +class LoadStructuralRetrySpec extends AnyFunSuite with ChiselSim { + private def pokeAttempt( + attempt: LoadAttemptIdentity, + generation: BigInt): Unit = { + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(2.U) + attempt.producer.stid.poke(1.U) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke(7.U) + attempt.producer.brobGeneration.poke(11.U) + attempt.producer.ridSlot.poke(13.U) + attempt.producer.ridGeneration.poke(17.U) + attempt.producer.memberIndex.poke(19.U) + attempt.producer.residentGeneration.poke(23.U) + attempt.generation.poke(generation.U) + } + + private def clear(dut: LoadStructuralRetryHarness): Unit = { + dut.io.flush.poke(false.B) + dut.io.allocValid.poke(false.B) + dut.io.alloc.poke(0.U.asTypeOf(dut.io.alloc)) + dut.io.launchValid.poke(false.B) + dut.io.retryValid.poke(false.B) + dut.io.retry.poke(0.U.asTypeOf(dut.io.retry)) + dut.io.mutationConflict.poke(false.B) + } + + private def allocateAndLaunch(dut: LoadStructuralRetryHarness): Unit = { + dut.io.alloc.poke(0.U.asTypeOf(dut.io.alloc)) + dut.io.alloc.size.poke(8.U) + dut.io.alloc.returnPipeIndex.poke(2.U) + pokeAttempt(dut.io.alloc.attempt, generation = 5) + dut.io.allocValid.poke(true.B) + dut.io.allocAccepted.expect(true.B) + dut.clock.step() + dut.io.allocValid.poke(false.B) + + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + dut.io.row.status.expect(LoadInflightStatus.Repick) + dut.io.row.forwardPending.expect(true.B) + } + + private def pokeRetry(dut: LoadStructuralRetryHarness): Unit = { + dut.io.retry.poke(0.U.asTypeOf(dut.io.retry)) + dut.io.retry.loadId.valid.poke(true.B) + dut.io.retry.loadId.slot.poke(0.U) + dut.io.retry.loadId.generation.poke(0.U) + pokeAttempt(dut.io.retry.current, generation = 5) + pokeAttempt(dut.io.retry.next, generation = 6) + dut.io.retry.returnPipeIndex.poke(2.U) + dut.io.retry.waitStore.poke(true.B) + dut.io.retry.waitStoreInfo.valid.poke(true.B) + dut.io.retry.waitStoreInfo.storeIndex.poke(3.U) + dut.io.retry.waitStoreInfo.storeId.valid.poke(true.B) + dut.io.retry.waitStoreInfo.storeId.value.poke(4.U) + dut.io.retry.waitStoreInfo.storeLsId.valid.poke(true.B) + dut.io.retry.waitStoreInfo.storeLsId.value.poke(5.U) + dut.io.retry.waitStoreInfo.storeLsIdFullValid.poke(true.B) + dut.io.retry.waitStoreInfo.storeLsIdFull.poke("h123".U) + dut.io.retry.waitStoreInfo.pc.poke("h80000100".U) + } + + test("exact structural retry atomically returns a pending row to wait") { + simulate(new LoadStructuralRetryHarness) { dut => + clear(dut) + allocateAndLaunch(dut) + pokeRetry(dut) + dut.io.retryValid.poke(true.B) + dut.io.retryReady.expect(true.B) + dut.io.retryAccepted.expect(true.B) + dut.clock.step() + + dut.io.retryValid.poke(false.B) + dut.io.row.status.expect(LoadInflightStatus.Wait) + dut.io.row.forwardPending.expect(false.B) + dut.io.row.attempt.generation.expect(6.U) + dut.io.row.waitStore.expect(true.B) + dut.io.row.waitStoreInfo.storeIndex.expect(3.U) + dut.io.row.waitStoreInfo.storeLsIdFull.expect("h123".U) + dut.io.row.dataComplete.expect(false.B) + dut.io.row.sourcesReturned.expect(false.B) + } + } + + test("stale attempt and wrong return pipe cannot mutate the row") { + simulate(new LoadStructuralRetryHarness) { dut => + clear(dut) + allocateAndLaunch(dut) + pokeRetry(dut) + dut.io.retry.current.generation.poke(4.U) + dut.io.retryValid.poke(true.B) + dut.io.retryReady.expect(false.B) + dut.io.blockedByAttempt.expect(true.B) + dut.clock.step() + dut.io.row.attempt.generation.expect(5.U) + dut.io.row.forwardPending.expect(true.B) + + pokeRetry(dut) + dut.io.retry.returnPipeIndex.poke(1.U) + dut.io.retryReady.expect(false.B) + dut.io.blockedByPipe.expect(true.B) + dut.clock.step() + dut.io.row.attempt.generation.expect(5.U) + dut.io.row.forwardPending.expect(true.B) + } + } + + test("malformed wait-store key cannot create an unwakeable wait") { + simulate(new LoadStructuralRetryHarness) { dut => + clear(dut) + allocateAndLaunch(dut) + pokeRetry(dut) + dut.io.retry.waitStoreInfo.storeLsIdFullValid.poke(false.B) + dut.io.retryValid.poke(true.B) + dut.io.retryReady.expect(false.B) + dut.io.blockedByWaitStore.expect(true.B) + dut.clock.step() + dut.io.row.status.expect(LoadInflightStatus.Repick) + dut.io.row.forwardPending.expect(true.B) + dut.io.row.waitStore.expect(false.B) + } + } + + test("same-row mutation intent blocks structural retry without partial update") { + simulate(new LoadStructuralRetryHarness) { dut => + clear(dut) + allocateAndLaunch(dut) + pokeRetry(dut) + dut.io.retryValid.poke(true.B) + dut.io.mutationConflict.poke(true.B) + dut.io.retryReady.expect(false.B) + dut.io.blockedByMutation.expect(true.B) + dut.clock.step() + dut.io.row.status.expect(LoadInflightStatus.Repick) + dut.io.row.forwardPending.expect(true.B) + dut.io.row.attempt.generation.expect(5.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLiveLoadLiqCaptureSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLiveLoadLiqCaptureSpec.scala deleted file mode 100644 index d588dbbb..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLiveLoadLiqCaptureSpec.scala +++ /dev/null @@ -1,74 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLiveLoadLiqCaptureReference { - final case class Step( - candidateValid: Boolean, - accepted: Boolean, - blockedByAlloc: Boolean) - - def step(enable: Boolean, flush: Boolean, loadValid: Boolean, allocReady: Boolean): Step = { - val candidateValid = enable && !flush && loadValid - Step( - candidateValid = candidateValid, - accepted = candidateValid && allocReady, - blockedByAlloc = candidateValid && !allocReady) - } -} - -class ReducedLiveLoadLiqCaptureSpec extends AnyFunSuite { - import ReducedLiveLoadLiqCaptureReference._ - - test("admits an enabled valid E1 load only when the LIQ adapter is ready") { - val accepted = step(enable = true, flush = false, loadValid = true, allocReady = true) - assert(accepted.candidateValid) - assert(accepted.accepted) - assert(!accepted.blockedByAlloc) - - val blocked = step(enable = true, flush = false, loadValid = true, allocReady = false) - assert(blocked.candidateValid) - assert(!blocked.accepted) - assert(blocked.blockedByAlloc) - } - - test("flush and disabled admission suppress an otherwise valid load") { - val flushed = step(enable = true, flush = true, loadValid = true, allocReady = true) - val disabled = step(enable = false, flush = false, loadValid = true, allocReady = true) - - assert(!flushed.candidateValid && !flushed.accepted && !flushed.blockedByAlloc) - assert(!disabled.candidateValid && !disabled.accepted && !disabled.blockedByAlloc) - } - - test("ReducedLiveLoadLiqCapture elaborates the E1 metadata and allocation handshake") { - val io = new ReducedLiveLoadLiqCaptureIO(idEntries = 8, lsidWidth = 40) - val sv = ChiselStage.emitSystemVerilog( - new ReducedLiveLoadLiqCapture( - idEntries = 8, archRegWidth = 5, physRegWidth = 6, lsidWidth = 40)) - - assert(io.loadLsIdFull.getWidth == 40) - assert(io.candidate.loadLsIdFull.getWidth == 40) - assert(io.youngestStoreLsIdFull.getWidth == 40) - assert(io.candidate.youngestStoreLsIdFull.getWidth == 40) - - assert(sv.contains("module ReducedLiveLoadLiqCapture")) - assert(sv.contains("io_captureEnable")) - assert(sv.contains("io_loadValid")) - assert(sv.contains("io_loadDst_oldPhysTag")) - assert(sv.contains("io_loadSource0_data")) - assert(sv.contains("io_loadBid_value")) - assert(sv.contains("io_loadLsId_value")) - assert(sv.contains("io_loadLsIdFullValid")) - assert(sv.contains("io_loadLsIdFull")) - assert(sv.contains("io_candidate_loadLsIdFullValid")) - assert(sv.contains("io_candidate_loadLsIdFull")) - assert(sv.contains("io_youngestStoreLsIdFull")) - assert(sv.contains("io_candidate_youngestStoreLsIdFull")) - assert(sv.contains("io_youngestStoreLsId_value")) - assert(sv.contains("io_candidateValid")) - assert(sv.contains("io_candidate_dst_physTag")) - assert(sv.contains("io_captureAccepted")) - assert(sv.contains("io_blockedByAlloc")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayCompletionDrainSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayCompletionDrainSpec.scala deleted file mode 100644 index ea8d41b8..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayCompletionDrainSpec.scala +++ /dev/null @@ -1,123 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLoadReplayCompletionDrainReference { - import ReducedLoadWaitReplaySlotReference.{Id, Relaunch} - - final case class Completion( - valid: Boolean = true, - memLoad: Boolean = true, - pc: BigInt, - addr: BigInt, - size: Int, - bid: Id, - gid: Id, - rid: Id, - lsId: Id) - final case class Result( - consumeReady: Boolean, - matchValid: Boolean, - mismatch: Boolean, - pcMismatch: Boolean, - addrMismatch: Boolean, - sizeMismatch: Boolean, - bidMismatch: Boolean, - gidMismatch: Boolean, - ridMismatch: Boolean, - lsIdMismatch: Boolean) - - def step(candidate: Option[Relaunch], completion: Completion): Result = { - val comparable = candidate.isDefined && completion.valid && completion.memLoad - val pcMismatch = comparable && candidate.get.pc != completion.pc - val addrMismatch = comparable && candidate.get.addr != completion.addr - val sizeMismatch = comparable && candidate.get.size != completion.size - val bidMismatch = comparable && candidate.get.bid != completion.bid - val gidMismatch = comparable && candidate.get.gid != completion.gid - val ridMismatch = comparable && candidate.get.rid != completion.rid - val lsIdMismatch = comparable && candidate.get.lsId != completion.lsId - val mismatch = pcMismatch || addrMismatch || sizeMismatch || bidMismatch || gidMismatch || ridMismatch || lsIdMismatch - val matchValid = comparable && !mismatch - Result( - consumeReady = matchValid, - matchValid = matchValid, - mismatch = comparable && mismatch, - pcMismatch = pcMismatch, - addrMismatch = addrMismatch, - sizeMismatch = sizeMismatch, - bidMismatch = bidMismatch, - gidMismatch = gidMismatch, - ridMismatch = ridMismatch, - lsIdMismatch = lsIdMismatch) - } - - def id(value: Int, wrap: Boolean = false): Id = - Id(valid = true, wrap = wrap, value = value) - - def candidate: Relaunch = - Relaunch( - pc = 0x4000, - addr = 0x1008, - size = 8, - bid = id(6), - lsId = id(3), - gid = id(2), - rid = id(7), - youngestStoreId = id(6), - youngestStoreLsId = id(3)) - - def completion: Completion = - Completion(pc = 0x4000, addr = 0x1008, size = 8, bid = id(6), gid = id(2), rid = id(7), lsId = id(3)) -} - -class ReducedLoadReplayCompletionDrainSpec extends AnyFunSuite { - import ReducedLoadReplayCompletionDrainReference._ - - test("matching load completion consumes the queued replay candidate") { - val result = step(Some(candidate), completion) - - assert(result.matchValid) - assert(result.consumeReady) - assert(!result.mismatch) - } - - test("non-load completion leaves the candidate pending without mismatch") { - val result = step(Some(candidate), completion.copy(memLoad = false)) - - assert(!result.matchValid) - assert(!result.consumeReady) - assert(!result.mismatch) - } - - test("mismatched load completion reports identity differences without consuming") { - val result = step(Some(candidate), completion.copy(addr = 0x1010, rid = id(5), lsId = id(4))) - - assert(!result.matchValid) - assert(!result.consumeReady) - assert(result.mismatch) - assert(result.addrMismatch) - assert(result.ridMismatch) - assert(result.lsIdMismatch) - assert(!result.pcMismatch) - } - - test("absent candidate ignores load completions") { - val result = step(None, completion) - - assert(!result.matchValid) - assert(!result.consumeReady) - assert(!result.mismatch) - } - - test("Chisel ReducedLoadReplayCompletionDrain elaborates match diagnostics") { - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadReplayCompletionDrain(idEntries = 8)) - - assert(sv.contains("module ReducedLoadReplayCompletionDrain")) - assert(sv.contains("io_consumeReady")) - assert(sv.contains("io_matchValid")) - assert(sv.contains("io_gidMismatch")) - assert(sv.contains("io_ridMismatch")) - assert(sv.contains("io_lsIdMismatch")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapterSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapterSpec.scala deleted file mode 100644 index 7d070303..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapterSpec.scala +++ /dev/null @@ -1,157 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLoadReplayLiqAllocAdapterReference { - import ReducedLoadWaitReplaySlotReference.{Dst, Id, Relaunch} - - final case class Alloc( - bid: Id, - gid: Id, - rid: Id, - loadLsId: Id, - pc: BigInt, - addr: BigInt, - size: Int, - returnSignExtend: Boolean, - dst: Dst, - youngestStoreId: Id, - youngestStoreLsId: Id, - isTile: Boolean, - specWakeup: Boolean, - stackValid: Boolean) - - final case class Step( - allocValid: Boolean, - alloc: Option[Alloc], - consumeReady: Boolean, - blockedByAlloc: Boolean, - candidateUsable: Boolean) - - def id(value: Int, wrap: Boolean = false): Id = - Id(valid = true, wrap = wrap, value = value) - - def candidate: Relaunch = - Relaunch( - pc = 0x4000, - addr = 0x1008, - size = 8, - bid = id(6), - lsId = id(3), - gid = id(2), - rid = id(7), - dst = Dst(valid = true, kind = 1, archTag = 10, relTag = 10, physTag = 42, oldPhysTag = 10), - youngestStoreId = id(4), - youngestStoreLsId = id(1)) - - def step( - candidate: Option[Relaunch], - allocReady: Boolean = true, - flush: Boolean = false): Step = { - val usable = !flush && candidate.isDefined - val alloc = candidate.filter(_ => usable).map { relaunch => - Alloc( - bid = relaunch.bid, - gid = relaunch.gid, - rid = relaunch.rid, - loadLsId = relaunch.lsId, - pc = relaunch.pc, - addr = relaunch.addr, - size = relaunch.size, - returnSignExtend = relaunch.returnSignExtend, - dst = relaunch.dst, - youngestStoreId = relaunch.youngestStoreId, - youngestStoreLsId = relaunch.youngestStoreLsId, - isTile = false, - specWakeup = false, - stackValid = false) - } - - Step( - allocValid = usable, - alloc = alloc, - consumeReady = usable && allocReady, - blockedByAlloc = usable && !allocReady, - candidateUsable = usable) - } -} - -class ReducedLoadReplayLiqAllocAdapterSpec extends AnyFunSuite { - import ReducedLoadReplayLiqAllocAdapterReference._ - - test("maps replay candidate identity and forwarding snapshot into LIQ allocation") { - val result = step(Some(candidate), allocReady = true) - val alloc = result.alloc.get - - assert(result.allocValid) - assert(result.consumeReady) - assert(!result.blockedByAlloc) - assert(alloc.bid == id(6)) - assert(alloc.gid == id(2)) - assert(alloc.rid == id(7)) - assert(alloc.loadLsId == id(3)) - assert(alloc.youngestStoreId == id(4)) - assert(alloc.youngestStoreLsId == id(1)) - assert(alloc.pc == 0x4000) - assert(alloc.addr == 0x1008) - assert(alloc.size == 8) - assert(!alloc.returnSignExtend) - assert(alloc.dst.valid) - assert(alloc.dst.physTag == 42) - assert(!alloc.isTile) - assert(!alloc.specWakeup) - assert(!alloc.stackValid) - } - - test("backpressure keeps allocation valid but does not consume queue head") { - val result = step(Some(candidate), allocReady = false) - - assert(result.allocValid) - assert(!result.consumeReady) - assert(result.blockedByAlloc) - assert(result.alloc.nonEmpty) - } - - test("absent candidate and flush suppress allocation and consume") { - val absent = step(None, allocReady = true) - assert(!absent.allocValid) - assert(!absent.consumeReady) - assert(!absent.blockedByAlloc) - assert(absent.alloc.isEmpty) - - val flushed = step(Some(candidate), allocReady = true, flush = true) - assert(!flushed.allocValid) - assert(!flushed.consumeReady) - assert(!flushed.blockedByAlloc) - assert(flushed.alloc.isEmpty) - } - - test("Chisel ReducedLoadReplayLiqAllocAdapter elaborates LIQ alloc handshake") { - val io = new ReducedLoadReplayLiqAllocAdapterIO(liqEntries = 4, idEntries = 8, lsidWidth = 40) - assert(io.candidate.loadLsIdFull.getWidth == 40) - assert(io.candidate.youngestStoreLsIdFull.getWidth == 40) - assert(io.alloc.loadLsIdFull.getWidth == 40) - assert(io.alloc.youngestStoreLsIdFull.getWidth == 40) - - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadReplayLiqAllocAdapter( - liqEntries = 4, idEntries = 8, lsidWidth = 40)) - - assert(sv.contains("module ReducedLoadReplayLiqAllocAdapter")) - assert(sv.contains("io_allocValid")) - assert(sv.contains("io_alloc_loadLsId_value")) - assert(sv.contains("io_candidate_loadLsIdFullValid")) - assert(sv.contains("io_candidate_loadLsIdFull")) - assert(sv.contains("io_alloc_loadLsIdFullValid")) - assert(sv.contains("io_alloc_loadLsIdFull")) - assert(sv.contains("io_candidate_youngestStoreLsIdFull")) - assert(sv.contains("io_alloc_youngestStoreLsIdFull")) - assert(sv.contains("io_alloc_returnSignExtend")) - assert(sv.contains("io_alloc_dst_physTag")) - assert(sv.contains("io_alloc_youngestStoreId_value")) - assert(sv.contains("io_alloc_youngestStoreLsId_value")) - assert(sv.contains("io_consumeReady")) - assert(sv.contains("io_blockedByAlloc")) - assert(sv.contains("io_candidateUsable")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPathSpec.scala deleted file mode 100644 index 1b5f3a18..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPathSpec.scala +++ /dev/null @@ -1,209 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLoadReplayLiqAllocPathReference { - import ReducedLoadReplayLiqAllocAdapterReference.{candidate, id} - import ReducedLoadWaitReplaySlotReference.Relaunch - - final case class Row(candidate: Relaunch, loadIdWrap: Boolean, loadIdValue: Int) - final case class Step( - consumeReady: Boolean, - allocValid: Boolean, - allocReady: Boolean, - allocAccepted: Boolean, - blockedByAlloc: Boolean, - residentCount: Int, - rows: Vector[Row]) - - final class Model(entries: Int) { - require(entries > 1 && (entries & (entries - 1)) == 0) - - private var rows = Vector.empty[Row] - private var allocPtr = 0 - private var allocWrap = false - - def step( - flush: Boolean = false, - candidateIn: Option[Relaunch] = None, - externalReady: Boolean = true): Step = { - val usable = !flush && candidateIn.isDefined - val allocReady = !flush && externalReady && !rows.exists(_.loadIdValue == allocPtr) - val accepted = usable && allocReady - val beforeFlushRows = rows - - if (flush) { - rows = Vector.empty - allocPtr = 0 - allocWrap = false - } else if (accepted) { - rows = rows :+ Row(candidateIn.get, allocWrap, allocPtr) - if (allocPtr == entries - 1) { - allocPtr = 0 - allocWrap = !allocWrap - } else { - allocPtr += 1 - } - } - - Step( - consumeReady = accepted, - allocValid = usable, - allocReady = allocReady, - allocAccepted = accepted, - blockedByAlloc = usable && !allocReady, - residentCount = rows.size, - rows = if (flush) Vector.empty else if (accepted) rows else beforeFlushRows) - } - - def defaultCandidate(pc: BigInt, lsId: Int, youngestStoreLsId: Int): Relaunch = - candidate.copy(pc = pc, lsId = id(lsId), youngestStoreLsId = id(youngestStoreLsId)) - } -} - -class ReducedLoadReplayLiqAllocPathSpec extends AnyFunSuite { - import ReducedLoadReplayLiqAllocPathReference._ - - test("allocates replay candidates into LIQ rows in allocation-pointer order") { - val model = new Model(entries = 2) - val first = model.defaultCandidate(pc = 0x4000, lsId = 3, youngestStoreLsId = 1) - val second = model.defaultCandidate(pc = 0x4010, lsId = 4, youngestStoreLsId = 2) - - val s0 = model.step(candidateIn = Some(first)) - val s1 = model.step(candidateIn = Some(second)) - - assert(s0.consumeReady && s0.allocAccepted && s0.residentCount == 1) - assert(s1.consumeReady && s1.allocAccepted && s1.residentCount == 2) - assert(s1.rows.map(_.loadIdValue) == Vector(0, 1)) - assert(s1.rows.head.candidate.lsId.value == 3) - assert(s1.rows.head.candidate.youngestStoreLsId.value == 1) - assert(s1.rows(1).candidate.lsId.value == 4) - assert(s1.rows(1).candidate.youngestStoreLsId.value == 2) - } - - test("full LIQ backpressures the replay queue head without consuming it") { - val model = new Model(entries = 2) - - assert(model.step(candidateIn = Some(model.defaultCandidate(0x4000, 1, 1))).allocAccepted) - assert(model.step(candidateIn = Some(model.defaultCandidate(0x4010, 2, 2))).allocAccepted) - val full = model.step(candidateIn = Some(model.defaultCandidate(0x4020, 3, 3))) - - assert(full.allocValid) - assert(!full.allocReady) - assert(!full.consumeReady) - assert(!full.allocAccepted) - assert(full.blockedByAlloc) - assert(full.residentCount == 2) - } - - test("external MDB credit backpressures the candidate without consuming it") { - val model = new Model(entries = 2) - val candidate = model.defaultCandidate(0x4000, 1, 1) - - val blocked = model.step(candidateIn = Some(candidate), externalReady = false) - val accepted = model.step(candidateIn = Some(candidate), externalReady = true) - - assert(blocked.allocValid) - assert(!blocked.allocReady) - assert(!blocked.consumeReady) - assert(!blocked.allocAccepted) - assert(blocked.blockedByAlloc) - assert(blocked.residentCount == 0) - assert(accepted.allocAccepted) - assert(accepted.residentCount == 1) - assert(accepted.rows.head.candidate == candidate) - } - - test("flush clears resident LIQ rows and suppresses candidate consumption") { - val model = new Model(entries = 2) - - assert(model.step(candidateIn = Some(model.defaultCandidate(0x4000, 1, 1))).allocAccepted) - val flushed = model.step(flush = true, candidateIn = Some(model.defaultCandidate(0x4010, 2, 2))) - val afterFlush = model.step(candidateIn = Some(model.defaultCandidate(0x4020, 3, 3))) - - assert(!flushed.allocValid) - assert(!flushed.consumeReady) - assert(flushed.residentCount == 0) - assert(afterFlush.allocAccepted) - assert(afterFlush.rows.head.loadIdValue == 0) - assert(!afterFlush.rows.head.loadIdWrap) - } - - test("Chisel ReducedLoadReplayLiqAllocPath elaborates adapter and LIQ row owner") { - val io = new ReducedLoadReplayLiqAllocPathIO( - liqEntries = 4, idEntries = 8, storeEntries = 4, lsidWidth = 40) - assert(io.rowMutationNextWaitStoreInfo.storeLsIdFull.getWidth == 40) - assert(io.allocPayload.loadLsIdFull.getWidth == 40) - assert(io.rows.head.waitStoreInfo.storeLsIdFull.getWidth == 40) - - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadReplayLiqAllocPath( - liqEntries = 4, idEntries = 8, storeEntries = 4, lsidWidth = 40)) - - assert(sv.contains("module ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("ReducedLoadReplayLiqAllocAdapter")) - assert(sv.contains("LoadInflightQueue")) - assert(sv.contains("LoadInflightLaunchSelect")) - assert(sv.contains("LoadInflightRowMutationRequestBridge")) - assert(sv.contains("io_rowMutationRequestValid")) - assert(sv.contains("io_rowMutationNextWaitStoreInfo_storeLsIdFull")) - assert(sv.contains("io_rowMutationBridgeValid")) - assert(sv.contains("io_rowMutationWriteEnable")) - assert(sv.contains("io_rowMutationInvalidStoreIndexOutOfRange")) - assert(sv.contains("io_rowMutationControlBlockedByInvalidRow")) - assert(sv.contains("io_rowMutationControlBlockedByScbNotReturned")) - assert(sv.contains("io_rowMutationControlBlockedByAllocationConflict")) - assert(sv.contains("io_candidateConsumeReady")) - assert(sv.contains("io_candidateBlockedByAlloc")) - assert(sv.contains("io_allocExternalReady")) - assert(sv.contains("io_allocAccepted")) - assert(sv.contains("io_allocPayload_pc")) - assert(sv.contains("io_allocPayload_loadLsId_value")) - assert(sv.contains("io_launchEnable")) - assert(sv.contains("io_e2Stores_0_valid")) - assert(sv.contains("io_e2StqReturned")) - assert(sv.contains("io_replayWakeValid")) - assert(sv.contains("io_replayWake_source")) - assert(sv.contains("io_replayWakeStoreUnitFullMatchMask")) - assert(sv.contains("LoadReplayWakeMatchDiagnostics")) - assert(sv.contains("io_replayWakeMergeMask")) - assert(sv.contains("io_replayWakeCompletedMask")) - assert(sv.contains("io_refillValid")) - assert(sv.contains("io_refillAccepted")) - assert(sv.contains("io_refillWakeMask")) - assert(sv.contains("io_launchDataHitMask")) - assert(sv.contains("io_launchCandidateMask")) - assert(sv.contains("io_launchValid")) - assert(sv.contains("io_launchSelectedBid_value")) - assert(sv.contains("io_launchSelectedLoadLsId_value")) - assert(sv.contains("io_launchSelectedPc")) - assert(sv.contains("io_launchSelectedAddr")) - assert(sv.contains("io_launchSelectedDst_physTag")) - assert(sv.contains("io_launchSelectedSourceTraceValid")) - assert(sv.contains("io_launchSelectedSource0_data")) - assert(sv.contains("io_launchSelectedSource1_data")) - assert(sv.contains("io_launchSelectedRequestByteMask")) - assert(sv.contains("io_launchSelectedSpecWakeup")) - assert(sv.contains("io_launchSelectedStackValid")) - assert(sv.contains("io_launchDriveValid")) - assert(sv.contains("io_launchReady")) - assert(sv.contains("io_launchAccepted")) - assert(sv.contains("io_pickValid")) - assert(sv.contains("io_pickIndex")) - assert(sv.contains("io_pickReady")) - assert(sv.contains("io_pickAccepted")) - assert(sv.contains("io_scbReturnValid")) - assert(sv.contains("io_scbReturnIndex")) - assert(sv.contains("io_scbReturnReady")) - assert(sv.contains("io_scbReturnAccepted")) - assert(sv.contains("io_e4UpdateValid")) - assert(sv.contains("io_lhqRecordValid")) - assert(sv.contains("io_lhqRecord_pc")) - assert(sv.contains("io_missPending")) - assert(sv.contains("io_rows_0_loadLsId_value")) - assert(sv.contains("io_rows_0_dst_physTag")) - assert(sv.contains("io_rows_0_sourceTraceValid")) - assert(sv.contains("io_rows_0_source0_data")) - assert(sv.contains("io_rows_0_youngestStoreLsId_value")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueueSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueueSpec.scala deleted file mode 100644 index 8eb3797b..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueueSpec.scala +++ /dev/null @@ -1,183 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLoadReplayRelaunchQueueReference { - import ReducedLoadWaitReplaySlotReference.{Dst, Id, Relaunch} - - final case class Step( - enqueueReady: Boolean, - enqueueAccepted: Boolean, - enqueueDropped: Boolean, - outValid: Boolean, - out: Option[Relaunch], - outFire: Boolean, - pending: Boolean, - full: Boolean, - empty: Boolean, - count: Int) - - final class Model(depth: Int) { - private var queue = Vector.empty[Relaunch] - - def step( - flush: Boolean = false, - enqueue: Option[Relaunch] = None, - outReady: Boolean = false): Step = { - val oldHead = if (flush) None else queue.headOption - val outValid = oldHead.isDefined - val outFire = outValid && outReady - val enqueueReady = !flush && (queue.size < depth || outFire) - val enqueueAccepted = enqueue.isDefined && enqueueReady - val enqueueDropped = enqueue.isDefined && !flush && !enqueueReady - - val next = - if (flush) { - Vector.empty[Relaunch] - } else { - val afterPop = if (outFire) queue.drop(1) else queue - if (enqueueAccepted) afterPop :+ enqueue.get else afterPop - } - queue = next - - Step( - enqueueReady = enqueueReady, - enqueueAccepted = enqueueAccepted, - enqueueDropped = enqueueDropped, - outValid = outValid, - out = oldHead, - outFire = outFire, - pending = queue.nonEmpty, - full = queue.size == depth, - empty = queue.isEmpty, - count = queue.size) - } - } - - def id(value: Int, wrap: Boolean = false): Id = - Id(valid = true, wrap = wrap, value = value) - - def relaunch(pc: BigInt, addr: BigInt, lsId: Int): Relaunch = - Relaunch( - pc = pc, - addr = addr, - size = 8, - returnSignExtend = lsId == 1, - bid = id(6), - lsId = id(lsId), - dst = Dst(valid = true, kind = 1, archTag = 10 + lsId, relTag = 10 + lsId, physTag = 40 + lsId, oldPhysTag = 10 + lsId), - gid = id(2), - rid = id(7), - youngestStoreId = id(6), - youngestStoreLsId = id(lsId)) -} - -class ReducedLoadReplayRelaunchQueueSpec extends AnyFunSuite { - import ReducedLoadReplayRelaunchQueueReference._ - - test("stores relaunch candidates in FIFO order") { - val model = new Model(depth = 2) - val first = relaunch(pc = 0x4000, addr = 0x1000, lsId = 1) - val second = relaunch(pc = 0x4010, addr = 0x1080, lsId = 2) - - val enqueueFirst = model.step(enqueue = Some(first)) - assert(enqueueFirst.enqueueAccepted) - assert(!enqueueFirst.outValid) - assert(enqueueFirst.pending) - - val enqueueSecond = model.step(enqueue = Some(second)) - assert(enqueueSecond.enqueueAccepted) - assert(enqueueSecond.out.contains(first)) - assert(enqueueSecond.full) - - val popFirst = model.step(outReady = true) - assert(popFirst.outFire) - assert(popFirst.out.contains(first)) - assert(popFirst.out.exists(_.returnSignExtend)) - assert(popFirst.out.exists(_.dst.physTag == 41)) - assert(popFirst.count == 1) - - val popSecond = model.step(outReady = true) - assert(popSecond.outFire) - assert(popSecond.out.contains(second)) - assert(popSecond.out.exists(!_.returnSignExtend)) - assert(popSecond.empty) - } - - test("simultaneous dequeue opens space for a new relaunch candidate") { - val model = new Model(depth = 1) - val first = relaunch(pc = 0x4000, addr = 0x1000, lsId = 1) - val second = relaunch(pc = 0x4010, addr = 0x1080, lsId = 2) - - assert(model.step(enqueue = Some(first)).enqueueAccepted) - val simultaneous = model.step(enqueue = Some(second), outReady = true) - - assert(simultaneous.enqueueReady) - assert(simultaneous.enqueueAccepted) - assert(!simultaneous.enqueueDropped) - assert(simultaneous.outFire) - assert(simultaneous.out.contains(first)) - assert(simultaneous.full) - - val next = model.step() - assert(next.out.contains(second)) - } - - test("drops a one-cycle candidate when the queue is full and not drained") { - val model = new Model(depth = 1) - val first = relaunch(pc = 0x4000, addr = 0x1000, lsId = 1) - val second = relaunch(pc = 0x4010, addr = 0x1080, lsId = 2) - - assert(model.step(enqueue = Some(first)).enqueueAccepted) - val dropped = model.step(enqueue = Some(second)) - - assert(!dropped.enqueueReady) - assert(!dropped.enqueueAccepted) - assert(dropped.enqueueDropped) - assert(dropped.out.contains(first)) - assert(dropped.full) - } - - test("flush clears queued relaunch candidates and suppresses admission") { - val model = new Model(depth = 2) - val first = relaunch(pc = 0x4000, addr = 0x1000, lsId = 1) - val second = relaunch(pc = 0x4010, addr = 0x1080, lsId = 2) - - assert(model.step(enqueue = Some(first)).enqueueAccepted) - val flushed = model.step(flush = true, enqueue = Some(second), outReady = true) - - assert(!flushed.enqueueReady) - assert(!flushed.enqueueAccepted) - assert(!flushed.enqueueDropped) - assert(!flushed.outValid) - assert(flushed.empty) - } - - test("Chisel ReducedLoadReplayRelaunchQueue elaborates with queue diagnostics") { - val io = new ReducedLoadReplayRelaunchQueueIO(idEntries = 8, depth = 2, lsidWidth = 40) - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadReplayRelaunchQueue( - idEntries = 8, depth = 2, lsidWidth = 40)) - - assert(io.enqueue.loadLsIdFull.getWidth == 40) - assert(io.out.loadLsIdFull.getWidth == 40) - assert(io.enqueue.youngestStoreLsIdFull.getWidth == 40) - assert(io.out.youngestStoreLsIdFull.getWidth == 40) - - assert(sv.contains("module ReducedLoadReplayRelaunchQueue")) - assert(sv.contains("io_enqueueAccepted")) - assert(sv.contains("io_enqueueDropped")) - assert(sv.contains("io_out_valid")) - assert(sv.contains("io_out_returnSignExtend")) - assert(sv.contains("io_out_dst_physTag")) - assert(sv.contains("io_out_gid_value")) - assert(sv.contains("io_out_rid_value")) - assert(sv.contains("io_out_loadLsId_value")) - assert(sv.contains("io_out_loadLsIdFullValid")) - assert(sv.contains("io_out_loadLsIdFull")) - assert(sv.contains("io_out_youngestStoreLsIdFull")) - assert(sv.contains("io_out_youngestStoreId_value")) - assert(sv.contains("io_out_youngestStoreLsId_value")) - assert(sv.contains("io_count")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedLoadWaitReplaySlotSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedLoadWaitReplaySlotSpec.scala deleted file mode 100644 index ff58b75b..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedLoadWaitReplaySlotSpec.scala +++ /dev/null @@ -1,298 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedLoadWaitReplaySlotReference { - final case class Id(valid: Boolean = false, wrap: Boolean = false, value: Int = 0) - final case class Dst( - valid: Boolean = false, - kind: Int = 0, - archTag: Int = 0, - relTag: Int = 0, - physTag: Int = 0, - oldPhysTag: Int = 0) - final case class Source(valid: Boolean = false, reg: Int = 0, data: BigInt = 0) - final case class Wait( - valid: Boolean = false, - index: Int = 0, - storeId: Id = Id(), - storeLsId: Id = Id(), - pc: BigInt = 0) - final case class Capture( - pc: BigInt, - addr: BigInt, - size: Int, - bid: Id, - lsId: Id, - waitKey: Wait, - gid: Id = Id(), - rid: Id = Id(), - youngestStoreId: Option[Id] = None, - youngestStoreLsId: Option[Id] = None, - returnSignExtend: Boolean = false, - dst: Dst = Dst(), - sourceTraceValid: Boolean = false, - source0: Source = Source(), - source1: Source = Source()) - final case class Wake(storeId: Id, storeLsId: Id, pc: BigInt) - final case class Relaunch( - pc: BigInt, - addr: BigInt, - size: Int, - bid: Id, - lsId: Id, - dst: Dst = Dst(), - gid: Id = Id(), - rid: Id = Id(), - youngestStoreId: Id = Id(), - youngestStoreLsId: Id = Id(), - returnSignExtend: Boolean = false, - sourceTraceValid: Boolean = false, - source0: Source = Source(), - source1: Source = Source()) - final case class State( - active: Boolean = false, - pc: BigInt = 0, - addr: BigInt = 0, - size: Int = 0, - returnSignExtend: Boolean = false, - bid: Id = Id(), - lsId: Id = Id(), - gid: Id = Id(), - rid: Id = Id(), - dst: Dst = Dst(), - sourceTraceValid: Boolean = false, - source0: Source = Source(), - source1: Source = Source(), - youngestStoreId: Id = Id(), - youngestStoreLsId: Id = Id(), - waitKey: Wait = Wait()) - final case class Result( - state: State, - captureAccepted: Boolean, - waitStoreClear: Boolean, - relaunch: Option[Relaunch]) - - def step( - state: State, - flush: Boolean = false, - capture: Option[Capture] = None, - wake: Option[Wake] = None): Result = { - val captureAccepted = !flush && capture.exists(_.waitKey.valid) - val waitStoreClear = state.active && wake.exists { event => - state.waitKey.valid && - state.waitKey.storeId == event.storeId && - state.waitKey.storeLsId == event.storeLsId && - state.waitKey.pc == event.pc - } - val relaunch = - if (waitStoreClear && !captureAccepted && !flush) { - Some(Relaunch( - pc = state.pc, - addr = state.addr, - size = state.size, - bid = state.bid, - lsId = state.lsId, - dst = state.dst, - gid = state.gid, - rid = state.rid, - youngestStoreId = state.youngestStoreId, - youngestStoreLsId = state.youngestStoreLsId, - returnSignExtend = state.returnSignExtend, - sourceTraceValid = state.sourceTraceValid, - source0 = state.source0, - source1 = state.source1)) - } else { - None - } - val next = - if (flush) { - State() - } else if (captureAccepted) { - val captured = capture.get - State( - active = true, - pc = captured.pc, - addr = captured.addr, - size = captured.size, - returnSignExtend = captured.returnSignExtend, - bid = captured.bid, - lsId = captured.lsId, - gid = captured.gid, - rid = captured.rid, - dst = captured.dst, - sourceTraceValid = captured.sourceTraceValid, - source0 = captured.source0, - source1 = captured.source1, - youngestStoreId = captured.youngestStoreId.getOrElse(captured.bid), - youngestStoreLsId = captured.youngestStoreLsId.getOrElse(captured.lsId), - waitKey = captured.waitKey) - } else if (waitStoreClear) { - State() - } else { - state - } - - Result(next, captureAccepted, waitStoreClear, relaunch) - } -} - -class ReducedLoadWaitReplaySlotSpec extends AnyFunSuite { - import ReducedLoadWaitReplaySlotReference._ - - private def id(value: Int, wrap: Boolean = false): Id = - Id(valid = true, wrap = wrap, value = value) - - private def wait(pc: BigInt, storeId: Id, storeLsId: Id = Id()): Wait = - Wait(valid = true, index = storeId.value, storeId = storeId, storeLsId = storeLsId, pc = pc) - - test("capture holds a wait-store identity until a matching replay wake clears it") { - val storeId = id(4) - val captured = Capture( - pc = 0x4000, - addr = 0x1008, - size = 8, - returnSignExtend = true, - bid = id(6), - lsId = id(3), - gid = id(2), - rid = id(7), - youngestStoreId = Some(id(5)), - youngestStoreLsId = Some(id(4)), - dst = Dst(valid = true, kind = 1, archTag = 10, relTag = 10, physTag = 42, oldPhysTag = 10), - sourceTraceValid = true, - source0 = Source(valid = true, reg = 2, data = 0x1122), - source1 = Source(valid = true, reg = 3, data = 0x3344), - waitKey = wait(pc = 0x3450, storeId = storeId)) - - val afterCapture = step(State(), capture = Some(captured)) - assert(afterCapture.captureAccepted) - assert(afterCapture.state.active) - assert(afterCapture.state.waitKey.pc == 0x3450) - - val afterWake = - step(afterCapture.state, wake = Some(Wake(storeId = storeId, storeLsId = Id(), pc = 0x3450))) - assert(afterWake.waitStoreClear) - assert(afterWake.relaunch.contains(Relaunch( - pc = 0x4000, - addr = 0x1008, - size = 8, - returnSignExtend = true, - bid = id(6), - lsId = id(3), - dst = Dst(valid = true, kind = 1, archTag = 10, relTag = 10, physTag = 42, oldPhysTag = 10), - gid = id(2), - rid = id(7), - youngestStoreId = id(5), - youngestStoreLsId = id(4), - sourceTraceValid = true, - source0 = Source(valid = true, reg = 2, data = 0x1122), - source1 = Source(valid = true, reg = 3, data = 0x3344)))) - assert(!afterWake.state.active) - } - - test("mismatched replay wake leaves the registered wait slot active") { - val storeId = id(2) - val state = step( - State(), - capture = Some(Capture(0x4100, 0x1080, 8, id(6), id(1), wait(pc = 0x3570, storeId = storeId)))).state - - val afterWrongPc = - step(state, wake = Some(Wake(storeId = storeId, storeLsId = Id(), pc = 0x3574))) - assert(!afterWrongPc.waitStoreClear) - assert(afterWrongPc.relaunch.isEmpty) - assert(afterWrongPc.state.active) - assert(afterWrongPc.state.waitKey.pc == 0x3570) - } - - test("a later capture overwrites the previous wait key") { - val firstStore = id(1) - val secondStore = id(5) - val first = step( - State(), - capture = Some(Capture(0x4000, 0x1000, 8, id(6), id(0), wait(pc = 0x3000, storeId = firstStore)))).state - val second = step( - first, - capture = Some(Capture(0x4010, 0x2000, 8, id(7), id(2), wait(pc = 0x3010, storeId = secondStore)))).state - - val oldWake = step(second, wake = Some(Wake(storeId = firstStore, storeLsId = Id(), pc = 0x3000))) - assert(!oldWake.waitStoreClear) - assert(oldWake.relaunch.isEmpty) - assert(oldWake.state.active) - - val newWake = step(oldWake.state, wake = Some(Wake(storeId = secondStore, storeLsId = Id(), pc = 0x3010))) - assert(newWake.waitStoreClear) - assert(newWake.relaunch.contains(Relaunch( - pc = 0x4010, - addr = 0x2000, - size = 8, - returnSignExtend = false, - bid = id(7), - lsId = id(2), - youngestStoreId = id(7), - youngestStoreLsId = id(2)))) - assert(!newWake.state.active) - } - - test("flush clears the registered wait slot") { - val active = step( - State(), - capture = Some(Capture(0x4100, 0x1080, 8, id(6), id(1), wait(pc = 0x3570, storeId = id(2))))).state - - val flushed = step(active, flush = true) - assert(!flushed.captureAccepted) - assert(!flushed.state.active) - } - - test("Chisel ReducedLoadWaitReplaySlot elaborates through LoadReplayWakeup") { - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadWaitReplaySlot(idEntries = 8, storeEntries = 8)) - - assert(sv.contains("module ReducedLoadWaitReplaySlot")) - assert(sv.contains("module LoadReplayWakeup")) - assert(sv.contains("io_captureAccepted")) - assert(sv.contains("io_waitStoreClear")) - assert(sv.contains("io_storedWaitStore_valid")) - assert(sv.contains("io_relaunch_valid")) - assert(sv.contains("io_captureReturnSignExtend")) - assert(sv.contains("io_captureDst_physTag")) - assert(sv.contains("io_captureSourceTraceValid")) - assert(sv.contains("io_captureSource0_data")) - assert(sv.contains("io_relaunch_returnSignExtend")) - assert(sv.contains("io_relaunch_dst_physTag")) - assert(sv.contains("io_relaunch_sourceTraceValid")) - assert(sv.contains("io_relaunch_source1_data")) - assert(sv.contains("io_relaunch_gid_value")) - assert(sv.contains("io_relaunch_rid_value")) - assert(sv.contains("io_relaunch_loadLsId_value")) - assert(sv.contains("io_relaunch_youngestStoreId_value")) - assert(sv.contains("io_relaunch_youngestStoreLsId_value")) - } - - test("wait slot preserves full selected-store authority at 40-bit LSID width") { - val io = new ReducedLoadWaitReplaySlotIO( - idEntries = 8, - storeEntries = 8, - lsidWidth = 40) - val sv = ChiselStage.emitSystemVerilog(new ReducedLoadWaitReplaySlot( - idEntries = 8, - storeEntries = 8, - lsidWidth = 40)) - - assert(io.captureWaitStore.storeLsIdFull.getWidth == 40) - assert(io.captureLsIdFull.getWidth == 40) - assert(io.relaunch.loadLsIdFull.getWidth == 40) - assert(io.captureYoungestStoreLsIdFull.getWidth == 40) - assert(io.relaunch.youngestStoreLsIdFull.getWidth == 40) - assert(io.storedWaitStore.storeLsIdFull.getWidth == 40) - assert(io.replayWake.storeLsIdFull.getWidth == 40) - assert(sv.contains("io_storedWaitStore_storeLsIdFull")) - assert(sv.contains("io_replayWake_storeLsIdFull")) - assert(sv.contains("io_captureLsIdFullValid")) - assert(sv.contains("io_captureLsIdFull")) - assert(sv.contains("io_relaunch_loadLsIdFullValid")) - assert(sv.contains("io_relaunch_loadLsIdFull")) - assert(sv.contains("io_captureYoungestStoreLsIdFull")) - assert(sv.contains("io_relaunch_youngestStoreLsIdFull")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreCommitFreeOwnerSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreCommitFreeOwnerSpec.scala deleted file mode 100644 index 5013ae30..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreCommitFreeOwnerSpec.scala +++ /dev/null @@ -1,310 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import linxcore.commit.CommitTraceParams -import org.scalatest.funsuite.AnyFunSuite - -object ReducedStoreCommitFreeOwnerReference { - final case class Id(value: Int = 0, wrap: Boolean = false, valid: Boolean = true) - sealed trait Status - case object Wait extends Status - case object Commit extends Status - case object Idle extends Status - final case class Row( - index: Int, - bid: Id = Id(), - gid: Id = Id(), - rid: Id = Id(), - stid: Int = 0, - status: Status = Wait, - storeAll: Boolean = true, - addrReady: Boolean = true, - dataReady: Boolean = true) - final case class CommitRow( - bid: Id = Id(), - gid: Id = Id(), - rid: Id = Id(), - rob: Id = Id(valid = false), - store: Boolean = true, - blockBid: Int = 0, - blockBidValid: Boolean = true) - final case class StepResult( - seen: Boolean, - matched: Boolean, - unmatched: Boolean, - blockedByNonFlush: Boolean, - matchMask: Int, - markValid: Boolean, - markIndex: Option[Int], - freeValid: Boolean, - freeIndex: Option[Int], - pendingMark: Int, - pendingFree: Int) - - final class Model(entries: Int) { - private var pendingMark = 0 - private var pendingFree = 0 - private var pendingCommitIdentities = Vector.empty[CommitRow] - - private def markable(row: Row, activeStid: Int): Boolean = - row.rid.valid && row.stid == activeStid && row.status == Wait && - row.storeAll && row.addrReady && row.dataReady - - private def first(mask: Int): Option[Int] = - (0 until entries).find(idx => ((mask >> idx) & 1) == 1) - - private def sameCommitIdentity(row: Row, commit: CommitRow): Boolean = - row.bid.valid && row.gid.valid && row.rid.valid && - row.bid.value == commit.bid.value && - row.gid.value == commit.gid.value && - row.rid.value == commit.rid.value - - def step( - rows: Seq[Row], - commits: Seq[CommitRow] = Seq.empty, - activeStid: Int = 0, - markAccepted: Boolean = false, - freeAccepted: Boolean = false, - enable: Boolean = true, - flush: Boolean = false, - directFreeEnable: Boolean = true, - nonFlushHead: Int = 0, - nonFlushPrefixCount: Int = Int.MaxValue): StepResult = { - val markValid = enable && !flush && pendingMark != 0 - val markIndex = first(pendingMark) - val markOh = markIndex.map(1 << _).getOrElse(0) - val freeValid = enable && directFreeEnable && !flush && pendingFree != 0 - val freeIndex = first(pendingFree) - val freeOh = freeIndex.map(1 << _).getOrElse(0) - - val storeCommits = commits.filter(_.store) - def blockSafe(commit: CommitRow): Boolean = - commit.blockBidValid && commit.blockBid - nonFlushHead >= 0 && - commit.blockBid - nonFlushHead < nonFlushPrefixCount - val markSources = (pendingCommitIdentities ++ storeCommits).filter(blockSafe) - val slotMatched = storeCommits.map { commit => - blockSafe(commit) && rows.exists(row => markable(row, activeStid) && sameCommitIdentity(row, commit)) - } - val alreadyPending = storeCommits.map { commit => - pendingCommitIdentities.exists(pending => - pending.bid.value == commit.bid.value && - pending.gid.value == commit.gid.value && - pending.rid.value == commit.rid.value) - } - val matchMask = rows.foldLeft(0) { case (mask, row) => - if (markable(row, activeStid) && markSources.exists(commit => sameCommitIdentity(row, commit))) mask | (1 << row.index) else mask - } - val pendingMatched = pendingCommitIdentities.filter { commit => - blockSafe(commit) && rows.exists(row => markable(row, activeStid) && sameCommitIdentity(row, commit)) - } - val newlyPending = storeCommits.zip(slotMatched).zip(alreadyPending).collect { - case ((commit, matched), isPending) if !matched && !isPending => commit - } - - if (!enable || flush) { - pendingMark = 0 - pendingFree = 0 - pendingCommitIdentities = Vector.empty - } else { - val markClear = if (markAccepted) markOh else 0 - val freeAdd = if (markAccepted) markOh else 0 - val freeClear = if (freeAccepted) freeOh else 0 - pendingMark = (pendingMark | matchMask) & ~markClear - pendingFree = - if (directFreeEnable) (pendingFree | freeAdd) & ~freeClear - else 0 - pendingCommitIdentities = - (pendingCommitIdentities.filterNot(pendingMatched.contains) ++ newlyPending).take(entries) - } - - StepResult( - seen = storeCommits.nonEmpty, - matched = slotMatched.contains(true), - unmatched = slotMatched.contains(false), - blockedByNonFlush = storeCommits.exists(commit => !blockSafe(commit)), - matchMask = matchMask, - markValid = markValid, - markIndex = markIndex.filter(_ => markValid), - freeValid = freeValid, - freeIndex = freeIndex.filter(_ => freeValid), - pendingMark = pendingMark, - pendingFree = pendingFree - ) - } - } -} - -class ReducedStoreCommitFreeOwnerSpec extends AnyFunSuite { - import ReducedStoreCommitFreeOwnerReference._ - - test("reference maps committed store ROB rows to pending STQ mark bits") { - val model = new Model(entries = 8) - val rows = Seq(Row(index = 3, bid = Id(value = 2), gid = Id(value = 0), rid = Id(value = 5, wrap = true), stid = 1)) - - val captured = model.step( - rows = rows, - commits = Seq(CommitRow(bid = Id(value = 2), gid = Id(value = 0), rid = Id(value = 5), rob = Id(value = 5, wrap = false))), - activeStid = 1) - assert(captured.seen) - assert(captured.matched) - assert(!captured.unmatched) - assert(captured.matchMask == (1 << 3)) - assert(captured.pendingMark == (1 << 3)) - - val mark = model.step(rows = rows, activeStid = 1) - assert(mark.markValid) - assert(mark.markIndex.contains(3)) - } - - test("reference matches committed stores by commit identity rather than physical ROB sideband") { - val model = new Model(entries = 8) - val rows = Seq(Row(index = 4, bid = Id(value = 3, wrap = true), gid = Id(value = 1), rid = Id(value = 6, wrap = true))) - - val captured = model.step( - rows = rows, - commits = Seq(CommitRow(bid = Id(value = 3), gid = Id(value = 1), rid = Id(value = 6), rob = Id(value = 2, wrap = false)))) - - assert(captured.seen) - assert(captured.matched) - assert(!captured.unmatched) - assert(captured.matchMask == (1 << 4)) - } - - test("reference turns accepted marks into later frees and clears accepted frees") { - val model = new Model(entries = 8) - val waitRows = Seq(Row(index = 2, rid = Id(value = 2), stid = 0)) - - model.step(rows = waitRows, commits = Seq(CommitRow(rid = Id(value = 2)))) - val marked = model.step(rows = waitRows, markAccepted = true) - assert(marked.markValid) - assert(marked.pendingMark == 0) - assert(marked.pendingFree == (1 << 2)) - - val commitRows = Seq(Row(index = 2, rid = Id(value = 2), status = Commit)) - val free = model.step(rows = commitRows) - assert(free.freeValid) - assert(free.freeIndex.contains(2)) - - val cleared = model.step(rows = commitRows, freeAccepted = true) - assert(cleared.pendingFree == 0) - } - - test("reference buffers committed store identity until the STQ row becomes markable") { - val model = new Model(entries = 8) - val store = CommitRow(bid = Id(value = 4), gid = Id(value = 0), rid = Id(value = 3)) - - val earlyCommit = model.step(rows = Seq.empty, commits = Seq(store)) - assert(earlyCommit.seen) - assert(!earlyCommit.matched) - assert(earlyCommit.unmatched) - assert(earlyCommit.pendingMark == 0) - - val rowAppears = model.step(rows = Seq(Row(index = 6, bid = Id(value = 4), gid = Id(value = 0), rid = Id(value = 3)))) - assert(rowAppears.matchMask == (1 << 6)) - assert(rowAppears.pendingMark == (1 << 6)) - - val mark = model.step(rows = Seq(Row(index = 6, bid = Id(value = 4), gid = Id(value = 0), rid = Id(value = 3)))) - assert(mark.markValid) - assert(mark.markIndex.contains(6)) - } - - test("reference retains a committed store until its full block BID enters the strong prefix") { - val model = new Model(entries = 8) - val row = Row(index = 5, bid = Id(value = 2), gid = Id(value = 1), rid = Id(value = 6)) - val store = CommitRow( - bid = Id(value = 2), - gid = Id(value = 1), - rid = Id(value = 6), - blockBid = 9) - - val blocked = model.step( - rows = Seq(row), - commits = Seq(store), - nonFlushHead = 8, - nonFlushPrefixCount = 1) - assert(blocked.blockedByNonFlush) - assert(!blocked.matched) - assert(blocked.pendingMark == 0) - - val released = model.step( - rows = Seq(row), - nonFlushHead = 8, - nonFlushPrefixCount = 2) - assert(released.matchMask == (1 << 5)) - assert(released.pendingMark == (1 << 5)) - } - - test("reference can disable direct free tracking after mark acceptance") { - val model = new Model(entries = 8) - val rows = Seq(Row(index = 2, rid = Id(value = 2), stid = 0)) - - model.step(rows = rows, commits = Seq(CommitRow(rid = Id(value = 2)))) - val marked = model.step(rows = rows, markAccepted = true, directFreeEnable = false) - - assert(marked.markValid) - assert(marked.pendingMark == 0) - assert(marked.pendingFree == 0) - assert(!model.step(rows = rows, directFreeEnable = false).freeValid) - } - - test("reference reports unmatched store commits and ignores non-ready rows") { - val model = new Model(entries = 4) - val rows = Seq(Row(index = 1, rid = Id(value = 1), dataReady = false)) - - val result = model.step(rows = rows, commits = Seq(CommitRow(rid = Id(value = 1)))) - assert(result.seen) - assert(!result.matched) - assert(result.unmatched) - assert(result.matchMask == 0) - assert(result.pendingMark == 0) - } - - test("ReducedStoreCommitFreeOwner elaborates mark and free diagnostics") { - val sv = ChiselStage.emitSystemVerilog( - new ReducedStoreCommitFreeOwner( - entries = 8, - traceParams = CommitTraceParams(commitWidth = 2, robValueWidth = 3), - mapQDepth = 8) - ) - - assert(sv.contains("module ReducedStoreCommitFreeOwner")) - assert(sv.contains("io_directFreeEnable")) - assert(sv.contains("io_markCommitValid")) - assert(sv.contains("io_commitFreeValid")) - assert(sv.contains("io_commitStoreMatched")) - assert(sv.contains("io_nonFlushHeadBid")) - assert(sv.contains("io_nonFlushPrefixCount")) - assert(sv.contains("io_commitStoreBlockedByNonFlush")) - assert(sv.contains("io_pendingMarkMask")) - assert(sv.contains("io_pendingFreeMask")) - assert(sv.contains("io_idle")) - } - - test("ReducedStoreCommitFreeOwner separates 16 physical STQ rows from 8 ROB identities") { - val dut = new ReducedStoreCommitFreeOwnerIO( - entries = 16, - traceParams = CommitTraceParams(commitWidth = 2, robValueWidth = 3), - mapQDepth = 8, - lsidWidth = 40, - robEntries = 8) - - assert(dut.stqRows.length == 16) - assert(dut.matchMask.getWidth == 16) - assert(dut.markCommitIndex.getWidth == 4) - assert(dut.oldestRobBid.value.getWidth == 3) - assert(dut.commitMemoryOrder.head.rid.value.getWidth == 3) - assert(dut.stqRows.head.bid.value.getWidth == 3) - assert(dut.stqRows.head.lsIdFull.getWidth == 40) - assert(dut.commitMemoryOrder.head.lsId.getWidth == 40) - - val sv = ChiselStage.emitSystemVerilog( - new ReducedStoreCommitFreeOwner( - entries = 16, - traceParams = CommitTraceParams(commitWidth = 2, robValueWidth = 3), - mapQDepth = 8, - lsidWidth = 40, - robEntries = 8) - ) - assert(sv.contains("module ReducedStoreCommitFreeOwner")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreExecResultBridgeSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreExecResultBridgeSpec.scala deleted file mode 100644 index 5f6b531d..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreExecResultBridgeSpec.scala +++ /dev/null @@ -1,180 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import linxcore.commit.CommitTraceParams -import linxcore.common.InterfaceParams -import org.scalatest.funsuite.AnyFunSuite - -object ReducedStoreExecResultBridgeReference { - final case class Key(bid: Int, rid: Int, stid: Int = 0) - final case class Result(key: Key, addr: BigInt, data: BigInt, size: Int) - final case class Head(key: Key, splitHalf: Boolean = false) - final case class StepResult( - staMatch: Boolean, - stdMatch: Boolean, - captureFire: Boolean, - captureBlocked: Boolean, - pending: Vector[Result]) - - final class Model(depth: Int, stdDelayCycles: Int = 0) { - private var pending = Vector.empty[Result] - private var stdDelay = Map.empty[Key, Int] - - def step( - complete: Option[Result] = None, - completeStoreDispatch: Boolean = true, - staHead: Option[Head] = None, - stdHead: Option[Head] = None, - staConsumed: Boolean = false, - stdConsumed: Boolean = false): StepResult = { - val staMatch = staHead.exists(head => pending.exists(_.key == head.key)) - val stdMatch = stdHead.exists { head => - pending.exists(_.key == head.key) && stdDelay.getOrElse(head.key, 0) == 0 - } - val afterConsume = pending.filterNot { result => - val staClears = staConsumed && staHead.exists(head => head.key == result.key && !head.splitHalf) - val stdClears = stdConsumed && stdHead.exists(_.key == result.key) - staClears || stdClears - } - val dispatchComplete = complete.filter(_ => completeStoreDispatch) - val duplicate = dispatchComplete.exists(result => afterConsume.exists(_.key == result.key)) - val captureFire = dispatchComplete.nonEmpty && !duplicate && afterConsume.size < depth - val captureBlocked = dispatchComplete.nonEmpty && !duplicate && afterConsume.size >= depth - pending = if (captureFire) afterConsume :+ dispatchComplete.get else afterConsume - val consumedKeys = pending.map(_.key).toSet - val decremented = stdDelay.collect { - case (key, remaining) if consumedKeys.contains(key) && remaining > 1 => key -> (remaining - 1) - } - val staDelayKey = - if (stdDelayCycles > 0 && staConsumed) - staHead.collect { case Head(key, true) => key } - else None - stdDelay = staDelayKey.map(key => decremented + (key -> stdDelayCycles)).getOrElse(decremented) - StepResult(staMatch, stdMatch, captureFire, captureBlocked, pending) - } - } -} - -class ReducedStoreExecResultBridgeSpec extends AnyFunSuite { - import ReducedStoreExecResultBridgeReference._ - - test("reference captures stores and only matches the current STA or STD queue head") { - val model = new Model(depth = 4) - val store0 = Result(Key(bid = 1, rid = 3), addr = 0x1000, data = 0x1234, size = 8) - - val captured = model.step(complete = Some(store0)) - assert(captured.captureFire) - assert(captured.pending.map(_.key) == Vector(store0.key)) - - val miss = model.step(staHead = Some(Head(Key(bid = 1, rid = 4)))) - assert(!miss.staMatch) - - val hit = model.step(staHead = Some(Head(store0.key))) - assert(hit.staMatch) - assert(!hit.stdMatch) - } - - test("reference keeps split-store data after STA and releases it after matching STD") { - val model = new Model(depth = 4) - val split = Result(Key(bid = 2, rid = 5), addr = 0x2080, data = 0xaabb, size = 4) - - assert(model.step(complete = Some(split)).captureFire) - val sta = model.step(staHead = Some(Head(split.key, splitHalf = true)), staConsumed = true) - assert(sta.staMatch) - assert(sta.pending.map(_.key) == Vector(split.key)) - - val std = model.step(stdHead = Some(Head(split.key, splitHalf = true)), stdConsumed = true) - assert(std.stdMatch) - assert(std.pending.isEmpty) - } - - test("reference can delay split-store STD after STA consumption") { - val model = new Model(depth = 4, stdDelayCycles = 2) - val split = Result(Key(bid = 6, rid = 2), addr = 0x4080, data = 0xfeed, size = 8) - - assert(model.step(complete = Some(split)).captureFire) - val sta = model.step(staHead = Some(Head(split.key, splitHalf = true)), staConsumed = true) - assert(sta.staMatch) - assert(sta.pending.map(_.key) == Vector(split.key)) - - val blocked0 = model.step(stdHead = Some(Head(split.key, splitHalf = true))) - assert(!blocked0.stdMatch) - assert(blocked0.pending.map(_.key) == Vector(split.key)) - - val blocked1 = model.step(stdHead = Some(Head(split.key, splitHalf = true))) - assert(!blocked1.stdMatch) - assert(blocked1.pending.map(_.key) == Vector(split.key)) - - val released = model.step(stdHead = Some(Head(split.key, splitHalf = true)), stdConsumed = true) - assert(released.stdMatch) - assert(released.pending.isEmpty) - } - - test("reference releases an unsplit store after STA consumption") { - val model = new Model(depth = 4) - val unsplit = Result(Key(bid = 4, rid = 1), addr = 0x3000, data = 0x55, size = 1) - - assert(model.step(complete = Some(unsplit)).captureFire) - val consumed = model.step(staHead = Some(Head(unsplit.key)), staConsumed = true) - assert(consumed.staMatch) - assert(consumed.pending.isEmpty) - } - - test("reference ignores implicit memory effects without store-dispatch ownership") { - val model = new Model(depth = 4) - val implicitCallStore = Result(Key(bid = 7, rid = 9), addr = 0x4000, data = 0x1234, size = 8) - - val ignored = model.step( - complete = Some(implicitCallStore), - completeStoreDispatch = false) - assert(!ignored.captureFire) - assert(!ignored.captureBlocked) - assert(ignored.pending.isEmpty) - } - - test("reference reports overflow when no buffered result slot is free") { - val model = new Model(depth = 2) - - assert(model.step(complete = Some(Result(Key(0, 0), 0x1000, 0, 8))).captureFire) - assert(model.step(complete = Some(Result(Key(0, 1), 0x1008, 1, 8))).captureFire) - val blocked = model.step(complete = Some(Result(Key(0, 2), 0x1010, 2, 8))) - assert(blocked.captureBlocked) - assert(blocked.pending.map(_.key) == Vector(Key(0, 0), Key(0, 1))) - } - - test("ReducedStoreExecResultBridge elaborates matched STA and STD result outputs") { - val sv = ChiselStage.emitSystemVerilog( - new ReducedStoreExecResultBridge( - p = InterfaceParams(robEntries = 8), - traceParams = CommitTraceParams(commitWidth = 2, robValueWidth = 3), - bufferEntries = 4, - mapQDepth = 8) - ) - - assert(sv.contains("module ReducedStoreExecResultBridge")) - assert(sv.contains("io_completeStoreValid")) - assert(sv.contains("io_completeStoreDispatch")) - assert(sv.contains("io_captureFire")) - assert(sv.contains("io_captureBlocked")) - assert(sv.contains("io_captureDuplicate")) - assert(sv.contains("io_staExec_valid")) - assert(sv.contains("io_stdExec_valid")) - assert(sv.contains("io_staMatch")) - assert(sv.contains("io_stdMatch")) - assert(sv.contains("io_bufferCount")) - } - - test("ReducedStoreExecResultBridge elaborates the opt-in split STD delay path") { - val sv = ChiselStage.emitSystemVerilog( - new ReducedStoreExecResultBridge( - p = InterfaceParams(robEntries = 8), - traceParams = CommitTraceParams(commitWidth = 2, robValueWidth = 3), - bufferEntries = 4, - mapQDepth = 8, - stdDelayCycles = 2) - ) - - assert(sv.contains("module ReducedStoreExecResultBridge")) - assert(sv.contains("io_stdExec_valid")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreMemoryOverlaySpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreMemoryOverlaySpec.scala deleted file mode 100644 index 6b7c80ec..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreMemoryOverlaySpec.scala +++ /dev/null @@ -1,183 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ReducedStoreMemoryOverlayReference { - final case class Request(valid: Boolean, accepted: Boolean, addr: BigInt, data: BigInt, size: Int) - final case class Line(lineAddr: BigInt, data: Vector[Int], mask: BigInt) - final case class StepResult(lines: Seq[Line], lineCount: Int, dropped: Seq[Boolean]) - final case class LoadResult(data: BigInt, forwardMask: BigInt) - - final class Model(entries: Int) { - private var lines = Vector.empty[Line] - - def snapshot: Seq[Line] = lines - - def step(reqs: Seq[Request], flush: Boolean = false): StepResult = { - val dropped = Array.fill(reqs.size)(false) - - if (flush) { - lines = Vector.empty - } else { - reqs.zipWithIndex.foreach { case (req, lane) => - if (req.valid && req.accepted) { - val lineAddr = req.addr & ~BigInt(0x3f) - val hit = lines.indexWhere(_.lineAddr == lineAddr) - val target = - if (hit >= 0) { - hit - } else if (lines.size < entries) { - lines = lines :+ Line(lineAddr, Vector.fill(64)(0), BigInt(0)) - lines.size - 1 - } else { - -1 - } - - if (target < 0) { - dropped(lane) = true - } else { - lines = lines.updated(target, merge(lines(target), req)) - } - } - } - } - - StepResult(lines = lines, lineCount = lines.size, dropped = dropped.toSeq) - } - - def load(addr: BigInt, baseData: BigInt, valid: Boolean = true): LoadResult = { - var data = BigInt(0) - var forwardMask = BigInt(0) - for (idx <- 0 until 8) { - val byteAddr = addr + idx - val lineAddr = byteAddr & ~BigInt(0x3f) - val offset = (byteAddr & 0x3f).toInt - val baseByte = ((baseData >> (idx * 8)) & 0xff).toInt - val line = lines.find(line => line.lineAddr == lineAddr && ((line.mask >> offset) & 1) == 1) - val selected = if (valid) line.map(_.data(offset)).getOrElse(baseByte) else baseByte - if (valid && line.nonEmpty) { - forwardMask |= BigInt(1) << idx - } - data |= BigInt(selected) << (idx * 8) - } - LoadResult(data, forwardMask) - } - - private def merge(line: Line, req: Request): Line = { - val off = (req.addr & 0x3f).toInt - var data = line.data - var mask = line.mask - for (idx <- 0 until req.size) { - val byte = ((req.data >> (idx * 8)) & 0xff).toInt - data = data.updated(off + idx, byte) - mask |= BigInt(1) << (off + idx) - } - line.copy(data = data, mask = mask) - } - } -} - -class ReducedStoreMemoryOverlaySpec extends AnyFunSuite { - import ReducedStoreMemoryOverlayReference._ - - test("accepted same-line stores merge and overlay load bytes over base data") { - val overlay = new Model(entries = 4) - overlay.step(Seq(Request(valid = true, accepted = true, addr = 0x1002, data = BigInt("1122334455667788", 16), size = 4))) - val result = overlay.step(Seq(Request(valid = true, accepted = true, addr = 0x1006, data = BigInt("aabb", 16), size = 2))) - val load = overlay.load(addr = 0x1000, baseData = BigInt("ffeeddccbbaa9988", 16)) - - assert(result.lineCount == 1) - assert(result.lines.head.mask == BigInt("fc", 16)) - assert(result.lines.head.data.slice(2, 8) == Seq(0x88, 0x77, 0x66, 0x55, 0xbb, 0xaa)) - assert(load.forwardMask == BigInt("fc", 16)) - assert(load.data == BigInt("aabb556677889988", 16)) - } - - test("accepted mask gates store visibility") { - val overlay = new Model(entries = 2) - overlay.step(Seq(Request(valid = true, accepted = false, addr = 0x2000, data = BigInt("0102030405060708", 16), size = 8))) - val load = overlay.load(addr = 0x2000, baseData = BigInt("8877665544332211", 16)) - - assert(overlay.snapshot.isEmpty) - assert(load.forwardMask == BigInt(0)) - assert(load.data == BigInt("8877665544332211", 16)) - } - - test("same-cycle overlapping requests rely on parent old-to-young lane order") { - val overlay = new Model(entries = 2) - overlay.step(Seq( - Request(valid = true, accepted = true, addr = 0x2800, data = BigInt("1122", 16), size = 2), - Request(valid = true, accepted = true, addr = 0x2800, data = BigInt("3344", 16), size = 2) - )) - val load = overlay.load(addr = 0x2800, baseData = BigInt(0)) - - assert(load.forwardMask == BigInt("03", 16)) - assert((load.data & BigInt("ffff", 16)) == BigInt("3344", 16)) - } - - test("cross-line load merges bytes from adjacent accepted store fragments") { - val overlay = new Model(entries = 4) - overlay.step(Seq( - Request(valid = true, accepted = true, addr = 0x203e, data = BigInt("7788", 16), size = 2), - Request(valid = true, accepted = true, addr = 0x2040, data = BigInt("112233445566", 16), size = 6) - )) - val load = overlay.load(addr = 0x203c, baseData = BigInt("deadbeefcafebabe", 16)) - - assert(overlay.snapshot.map(_.lineAddr) == Seq(BigInt(0x2000), BigInt(0x2040))) - assert(load.forwardMask == BigInt("fc", 16)) - assert(load.data == BigInt("334455667788babe", 16)) - } - - test("capacity diagnostics report accepted stores that have no matching or free line") { - val overlay = new Model(entries = 1) - overlay.step(Seq(Request(valid = true, accepted = true, addr = 0x3000, data = 0x11, size = 1))) - val dropped = overlay.step(Seq(Request(valid = true, accepted = true, addr = 0x3040, data = 0x22, size = 1))) - val load = overlay.load(addr = 0x3040, baseData = BigInt("0102030405060708", 16)) - - assert(dropped.dropped == Seq(true)) - assert(dropped.lineCount == 1) - assert(load.forwardMask == BigInt(0)) - assert(load.data == BigInt("0102030405060708", 16)) - } - - test("flush clears recorded committed-store overlay lines") { - val overlay = new Model(entries = 2) - overlay.step(Seq(Request(valid = true, accepted = true, addr = 0x4000, data = 0x44, size = 1))) - val result = overlay.step(Seq.empty, flush = true) - - assert(result.lines.isEmpty) - assert(result.lineCount == 0) - assert(overlay.load(addr = 0x4000, baseData = 0x55).data == BigInt(0x55)) - } - - test("Chisel ReducedStoreMemoryOverlay elaborates with store and load overlay IO") { - val sv = ChiselStage.emitSystemVerilog(new ReducedStoreMemoryOverlay(stqEntries = 8, requestCount = 4, lineEntries = 4)) - - assert(sv.contains("module ReducedStoreMemoryOverlay")) - assert(sv.contains("io_storeReqs_0_valid")) - assert(sv.contains("io_storeAcceptedMask")) - assert(sv.contains("io_loadForwardMask")) - assert(sv.contains("io_storeDroppedMask")) - assert(sv.contains("io_lines_0_byteMask")) - } - - test("physical STQ indices remain independent of ROB identity width") { - val io = new ReducedStoreMemoryOverlayIO( - stqEntries = 16, - requestCount = 4, - lineEntries = 4, - robEntries = 8, - lsidWidth = 40) - - assert(io.storeReqs.head.stqIndex.getWidth == 4) - assert(io.storeReqs.head.bid.value.getWidth == 3) - assert(io.storeReqs.head.lsId.getWidth == 40) - - val sv = ChiselStage.emitSystemVerilog( - new ReducedStoreMemoryOverlay( - stqEntries = 16, requestCount = 4, lineEntries = 4, robEntries = 8, lsidWidth = 40)) - assert(sv.contains("module ReducedStoreMemoryOverlay")) - assert(sv.contains("io_storeReqs_0_bid_value")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreResidentForwardSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreResidentForwardSpec.scala deleted file mode 100644 index 4f566247..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreResidentForwardSpec.scala +++ /dev/null @@ -1,275 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import linxcore.rob.ROBID -import org.scalatest.funsuite.AnyFunSuite - -object ReducedStoreResidentForwardReference { - final case class Id(value: Int = 0, wrap: Boolean = false) - final case class Row( - valid: Boolean = true, - waitState: Boolean = true, - addrReady: Boolean = true, - dataReady: Boolean = true, - scalar: Boolean = true, - bid: Id = Id(), - lsId: Id = Id(), - lsIdFullValid: Boolean = true, - lsIdFull: Option[BigInt] = None, - pc: BigInt = 0, - addr: BigInt = 0x1000, - data: BigInt = 0, - size: Int = 8) - final case class WaitStore(index: Int, bid: Id, lsId: Id, pc: BigInt) - final case class Result( - data: BigInt, - forwardMask: BigInt, - waitMask: BigInt, - eligibleMask: BigInt, - waitBlocked: Boolean, - waitStore: Option[WaitStore], - crosses: Boolean) - - private val LoadBytes = 8 - private val LineBytes = 64 - private val Mask64 = (BigInt(1) << 64) - 1 - - private def less(lhs: Id, rhs: Id): Boolean = - if (lhs.wrap == rhs.wrap) lhs.value < rhs.value else lhs.value > rhs.value - - private def lessEqual(lhs: Id, rhs: Id): Boolean = - less(lhs, rhs) || lhs == rhs - - private def lessFull(lhs: BigInt, rhs: BigInt, width: Int): Boolean = { - val mask = (BigInt(1) << width) - 1 - val distance = (rhs - lhs) & mask - lhs != rhs && distance < (BigInt(1) << (width - 1)) - } - - private def rowFull(row: Row): BigInt = row.lsIdFull.getOrElse(BigInt(row.lsId.value)) - - private def beforeOrSame(row: Row, loadBid: Id, loadFullValid: Boolean, loadFull: BigInt, width: Int): Boolean = - less(row.bid, loadBid) || - (row.bid == loadBid && row.lsIdFullValid && loadFullValid && - (rowFull(row) == loadFull || lessFull(rowFull(row), loadFull, width))) - - private def greaterRow(lhs: Row, rhs: Row, width: Int): Boolean = - less(rhs.bid, lhs.bid) || - (lhs.bid == rhs.bid && lhs.lsIdFullValid && rhs.lsIdFullValid && - lessFull(rowFull(rhs), rowFull(lhs), width)) - - private def crosses(addr: BigInt, size: Int): Boolean = - ((addr & 0x3f) + size) > LineBytes - - private def overlap(aAddr: BigInt, aSize: Int, bAddr: BigInt, bSize: Int): Boolean = - aAddr < (bAddr + bSize) && bAddr < (aAddr + aSize) - - private def lineAddr(addr: BigInt): BigInt = addr & ~BigInt(0x3f) - - private def byte(data: BigInt, idx: Int): Int = - ((data >> (idx * 8)) & 0xff).toInt - - def apply( - enable: Boolean, - loadValid: Boolean, - loadAddr: BigInt, - loadSize: Int, - loadBid: Id, - loadLsId: Id, - baseData: BigInt, - rows: Seq[Row], - loadLsIdFullValid: Boolean = true, - loadLsIdFull: Option[BigInt] = None, - lsidWidth: Int = 32): Result = { - val loadFull = loadLsIdFull.getOrElse(BigInt(loadLsId.value)) - val queryValid = enable && loadValid && loadSize != 0 && !crosses(loadAddr, loadSize) - var out = baseData & Mask64 - var fmask = BigInt(0) - var wmask = BigInt(0) - var emask = BigInt(0) - var waitStore: Option[WaitStore] = None - - if (queryValid) { - for (idx <- rows.indices) { - val row = rows(idx) - val eligible = - row.valid && - row.waitState && - row.addrReady && - row.scalar && - !crosses(row.addr, row.size) && - lineAddr(row.addr) == lineAddr(loadAddr) && - overlap(row.addr, row.size, loadAddr, loadSize) && - beforeOrSame(row, loadBid, loadLsIdFullValid, loadFull, lsidWidth) - if (eligible) { - emask |= BigInt(1) << idx - } - } - - for (loadByte <- 0 until LoadBytes) { - val addr = loadAddr + loadByte - if (loadByte < loadSize) { - val candidates = rows.zipWithIndex.filter { case (row, idx) => - ((emask >> idx) & 1) == 1 && addr >= row.addr && addr < (row.addr + row.size) - } - if (candidates.nonEmpty) { - val nearest = candidates.reduce { (best, candidate) => - if (greaterRow(candidate._1, best._1, lsidWidth)) candidate else best - } - val (nearestRow, nearestIndex) = nearest - val storeByte = byte(nearestRow.data, (addr - nearestRow.addr).toInt) - if (nearestRow.dataReady) { - out = (out & ~(BigInt(0xff) << (loadByte * 8))) | (BigInt(storeByte) << (loadByte * 8)) - fmask |= BigInt(1) << loadByte - } else { - wmask |= BigInt(1) << loadByte - val current = waitStore - val currentRow = current.flatMap(wait => rows.lift(wait.index)) - if (currentRow.isEmpty || greaterRow(nearestRow, currentRow.get, lsidWidth)) { - waitStore = Some(WaitStore(nearestIndex, nearestRow.bid, nearestRow.lsId, nearestRow.pc)) - } - } - } - } - } - } - - val wait = queryValid && wmask != 0 - Result( - data = if (wait) baseData & Mask64 else out, - forwardMask = if (wait) 0 else fmask, - waitMask = wmask, - eligibleMask = emask, - waitBlocked = wait, - waitStore = if (wait) waitStore else None, - crosses = enable && loadValid && crosses(loadAddr, loadSize)) - } -} - -class ReducedStoreResidentForwardSpec extends AnyFunSuite { - import ReducedStoreResidentForwardReference._ - - private def id(value: Int, wrap: Boolean = false): Id = Id(value, wrap) - - test("ready resident store forwards bytes over committed overlay data") { - val result = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = 0x1000, - loadSize = 8, - loadBid = id(3), - loadLsId = id(3), - baseData = BigInt("ffeeddccbbaa9988", 16), - rows = Seq(Row(bid = id(2), lsId = id(7), addr = 0x1002, data = BigInt("11223344", 16), size = 4))) - - assert(result.data == BigInt("ffee112233449988", 16)) - assert(result.forwardMask == BigInt("3c", 16)) - assert(result.waitMask == 0) - assert(result.eligibleMask == 1) - } - - test("same-BID resident stores use LSID to pick the nearest older source") { - val result = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = 0x2000, - loadSize = 2, - loadBid = id(4), - loadLsId = id(5), - baseData = 0, - rows = Seq( - Row(bid = id(4), lsId = id(3), addr = 0x2000, data = BigInt("1111", 16), size = 2), - Row(bid = id(4), lsId = id(5), addr = 0x2000, data = BigInt("5555", 16), size = 2), - Row(bid = id(4), lsId = id(6), addr = 0x2000, data = BigInt("6666", 16), size = 2) - )) - - assert((result.data & BigInt("ffff", 16)) == BigInt("5555", 16)) - assert(result.forwardMask == BigInt("03", 16)) - assert(result.eligibleMask == BigInt("03", 16)) - } - - test("same-BID resident forwarding selects by full LSID and refuses missing authority") { - val result = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = 0x2100, - loadSize = 2, - loadBid = id(4), - loadLsId = id(5), - loadLsIdFull = Some(BigInt("0100000005", 16)), - lsidWidth = 40, - baseData = 0, - rows = Seq( - Row(bid = id(4), lsId = id(3), lsIdFull = Some(BigInt("0000000003", 16)), addr = 0x2100, data = BigInt("1111", 16), size = 2), - Row(bid = id(4), lsId = id(3), lsIdFull = Some(BigInt("0100000004", 16)), addr = 0x2100, data = BigInt("4444", 16), size = 2), - Row(bid = id(4), lsId = id(3), lsIdFullValid = false, addr = 0x2100, data = BigInt("7777", 16), size = 2))) - - assert((result.data & BigInt("ffff", 16)) == BigInt("4444", 16)) - assert(result.eligibleMask == BigInt("03", 16)) - } - - test("not-ready nearest store reports wait and preserves base data") { - val result = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = 0x3000, - loadSize = 2, - loadBid = id(8), - loadLsId = id(0), - baseData = BigInt("8877665544332211", 16), - rows = Seq(Row(dataReady = false, bid = id(7), lsId = id(1), pc = 0x44, addr = 0x3000, data = BigInt("aaaa", 16), size = 2))) - - assert(result.waitBlocked) - assert(result.waitStore.contains(WaitStore(index = 0, bid = id(7), lsId = id(1), pc = 0x44))) - assert(result.waitMask == BigInt("03", 16)) - assert(result.forwardMask == 0) - assert(result.data == BigInt("8877665544332211", 16)) - } - - test("cross-line loads stay on the base overlay path for the ready-only packet") { - val result = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = 0x403e, - loadSize = 8, - loadBid = id(2), - loadLsId = id(0), - baseData = BigInt("0102030405060708", 16), - rows = Seq(Row(bid = id(1), lsId = id(0), addr = 0x403e, data = BigInt("aaaa", 16), size = 2))) - - assert(result.crosses) - assert(result.forwardMask == 0) - assert(result.data == BigInt("0102030405060708", 16)) - } - - test("Chisel ReducedStoreResidentForward elaborates resident STQ forwarding diagnostics") { - val sv = ChiselStage.emitSystemVerilog(new ReducedStoreResidentForward(entries = 8)) - - assert(sv.contains("module ReducedStoreResidentForward")) - assert(sv.contains("ResidentStoreForwardStoreSnapshot")) - assert(sv.contains("io_loadForwardMask")) - assert(sv.contains("io_waitMask")) - assert(sv.contains("io_eligibleStoreMask")) - assert(sv.contains("io_waitStore_pc")) - assert(sv.contains("io_waitStore_storeId_value")) - assert(sv.contains("io_loadCrossesLine")) - } - - test("resident forwarding separates physical STQ rows from ROB identity width") { - val io = new ReducedStoreResidentForwardIO(entries = 16, robEntries = 8) - - assert(io.rows.length == 16) - assert(io.eligibleStoreMask.getWidth == 16) - assert(io.waitStore.storeIndex.getWidth == 4) - assert(io.loadBid.value.getWidth == 3) - assert(io.waitStore.storeId.value.getWidth == 3) - } - - test("resident forwarding preserves parameterized full LSID authority after selection") { - val io = new ReducedStoreResidentForwardIO(entries = 16, robEntries = 8, lsidWidth = 40) - - assert(io.rows.head.lsIdFull.getWidth == 40) - assert(io.loadLsIdFull.getWidth == 40) - assert(io.waitStore.storeLsIdFull.getWidth == 40) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecBridgeSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecBridgeSpec.scala deleted file mode 100644 index 4c9f38dd..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecBridgeSpec.scala +++ /dev/null @@ -1,406 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.InterfaceParams -import linxcore.common.OperandClass -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rename.StoreSplitStoreType -import org.scalatest.funsuite.AnyFunSuite - -object ReducedStoreStaAddressExecBridgeReference { - final case class Source(valid: Boolean, ready: Boolean, data: BigInt) - final case class QueueHead( - opcode: Int, - pc: BigInt = 0, - imm: BigInt = 0, - valid: Boolean = true, - queueValid: Boolean = true, - addrHalf: Boolean = true, - allStore: Boolean = false, - sources: Vector[Source] = Vector.fill(3)(Source(valid = false, ready = true, data = 0))) - final case class Result( - candidate: Boolean, - supported: Boolean, - sourceMask: Int, - sourceReady: Boolean, - execValid: Boolean, - addr: BigInt, - data: BigInt, - size: Int) - - private def scaled(imm: BigInt, shift: Int): BigInt = - imm << shift - - private def pcrSize(opcode: Int): Int = - opcode match { - case FrontendOpcodeDecodeTable.OP_HL_SB_PCR => 1 - case FrontendOpcodeDecodeTable.OP_HL_SH_PCR => 2 - case FrontendOpcodeDecodeTable.OP_HL_SW_PCR => 4 - case _ => 8 - } - - def decide(head: QueueHead, enable: Boolean = true): Result = { - val candidate = enable && head.queueValid && head.valid && (head.addrHalf || head.allStore) - val (supported, mask, addr, size) = - head.opcode match { - case FrontendOpcodeDecodeTable.OP_HL_SB_PCR | - FrontendOpcodeDecodeTable.OP_HL_SD_PCR | - FrontendOpcodeDecodeTable.OP_HL_SH_PCR | - FrontendOpcodeDecodeTable.OP_HL_SW_PCR => - (true, 0, head.pc + head.imm, pcrSize(head.opcode)) - case FrontendOpcodeDecodeTable.OP_SDI => - (true, 0x2, head.sources(1).data + scaled(head.imm, 3), 8) - case FrontendOpcodeDecodeTable.OP_SWI => - (true, 0x2, head.sources(1).data + scaled(head.imm, 2), 4) - case FrontendOpcodeDecodeTable.OP_SHI => - (true, 0x2, head.sources(1).data + scaled(head.imm, 1), 2) - case FrontendOpcodeDecodeTable.OP_SBI => - (true, 0x2, head.sources(1).data + head.imm, 1) - case FrontendOpcodeDecodeTable.OP_SD => - (true, 0x6, head.sources(1).data + scaled(head.sources(2).data, 3), 8) - case FrontendOpcodeDecodeTable.OP_SC_W => - (true, 0x3, head.sources(1).data, 4) - case FrontendOpcodeDecodeTable.OP_C_SDI => - (true, 0x1, head.sources(0).data + scaled(head.imm, 3), 8) - case FrontendOpcodeDecodeTable.OP_C_SWI => - (true, 0x1, head.sources(0).data + scaled(head.imm, 2), 4) - case _ => - (false, 0, BigInt(0), 0) - } - val sourceReady = (0 until 3).forall { idx => - ((mask & (1 << idx)) == 0) || (head.sources(idx).valid && head.sources(idx).ready) - } - Result( - candidate = candidate, - supported = supported, - sourceMask = mask, - sourceReady = sourceReady, - execValid = candidate && supported && sourceReady, - addr = addr, - data = if (head.opcode == FrontendOpcodeDecodeTable.OP_SC_W) head.sources(0).data else 0, - size = size) - } -} - -class ReducedStoreStaAddressExecBridgeSpec extends AnyFunSuite with ChiselSim { - import ReducedStoreStaAddressExecBridgeReference._ - - private def source(data: BigInt, valid: Boolean = true, ready: Boolean = true): Source = - Source(valid = valid, ready = ready, data = data) - - test("reference emits an early OP_SDI STA result from the ready base source only") { - val result = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SDI, - imm = 3, - sources = Vector(source(0xdead), source(0x1000), source(0)))) - - assert(result.candidate) - assert(result.supported) - assert(result.sourceMask == 0x2) - assert(result.sourceReady) - assert(result.execValid) - assert(result.addr == 0x1018) - assert(result.size == 8) - } - - test("reference blocks OP_SDI STA when the address base source is not ready") { - val result = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SDI, - imm = 3, - sources = Vector(source(0xdead), source(0x1000, ready = false), source(0)))) - - assert(result.candidate) - assert(result.supported) - assert(result.sourceMask == 0x2) - assert(!result.sourceReady) - assert(!result.execValid) - } - - test("reference emits OP_SHI STA addresses from sign-extended SIMM12 scaled by two") { - val positive = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 7, - sources = Vector(source(0xdead), source(0x1000), source(0xbeef, ready = false)))) - val zero = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 0, - sources = Vector(source(0, ready = false), source(0x2200), source(0, valid = false)))) - val negative = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = -4, - sources = Vector(source(0), source(0x2000), source(0, valid = false, ready = false)))) - - assert(positive.supported) - assert(positive.sourceMask == 0x2) - assert(positive.sourceReady) - assert(positive.execValid) - assert(positive.addr == 0x100e) - assert(positive.size == 2) - - assert(zero.sourceMask == 0x2) - assert(zero.sourceReady) - assert(zero.execValid) - assert(zero.addr == 0x2200) - assert(zero.size == 2) - - assert(negative.sourceMask == 0x2) - assert(negative.sourceReady) - assert(negative.execValid) - assert(negative.addr == 0x1ff8) - assert(negative.size == 2) - } - - test("reference blocks OP_SHI only on the base source and leaves store data independent") { - val baseNotReady = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 5, - sources = Vector(source(0xaaaa), source(0x1000, ready = false), source(0xbbbb)))) - val dataNotReady = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 5, - sources = Vector(source(0xaaaa, ready = false), source(0x1000), source(0xbbbb, valid = false, ready = false)))) - - assert(baseNotReady.candidate) - assert(baseNotReady.supported) - assert(baseNotReady.sourceMask == 0x2) - assert(!baseNotReady.sourceReady) - assert(!baseNotReady.execValid) - - assert(dataNotReady.candidate) - assert(dataNotReady.supported) - assert(dataNotReady.sourceMask == 0x2) - assert(dataNotReady.sourceReady) - assert(dataNotReady.execValid) - assert(dataNotReady.addr == 0x100a) - assert(dataNotReady.size == 2) - } - - test("reference gates OP_SHI candidates exactly and does not support OP_SHI_U") { - val notQueueValid = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 1, - queueValid = false, - sources = Vector(source(0), source(0x1000), source(0)))) - val notPayloadValid = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 1, - valid = false, - sources = Vector(source(0), source(0x1000), source(0)))) - val notAddrHalf = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 1, - addrHalf = false, - sources = Vector(source(0), source(0x1000), source(0)))) - val disabled = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI, - imm = 1, - sources = Vector(source(0), source(0x1000), source(0))), - enable = false) - val unsignedSibling = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SHI_U, - imm = 1, - sources = Vector(source(0), source(0x1000), source(0)))) - - assert(!notQueueValid.candidate) - assert(notQueueValid.supported) - assert(!notQueueValid.execValid) - assert(!notPayloadValid.candidate) - assert(notPayloadValid.supported) - assert(!notPayloadValid.execValid) - assert(!notAddrHalf.candidate) - assert(notAddrHalf.supported) - assert(!notAddrHalf.execValid) - assert(!disabled.candidate) - assert(disabled.supported) - assert(!disabled.execValid) - assert(unsignedSibling.candidate) - assert(!unsignedSibling.supported) - assert(unsignedSibling.sourceMask == 0) - assert(!unsignedSibling.execValid) - } - - test("reference keeps adjacent byte and word immediate-store STA behavior unchanged") { - val byteStore = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SBI, - imm = 7, - sources = Vector(source(0), source(0x3000), source(0, valid = false)))) - val wordStore = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SWI, - imm = 7, - sources = Vector(source(0), source(0x3000), source(0, valid = false)))) - - assert(byteStore.supported) - assert(byteStore.sourceMask == 0x2) - assert(byteStore.execValid) - assert(byteStore.addr == 0x3007) - assert(byteStore.size == 1) - - assert(wordStore.supported) - assert(wordStore.sourceMask == 0x2) - assert(wordStore.execValid) - assert(wordStore.addr == 0x301c) - assert(wordStore.size == 4) - } - - test("reference emits OP_SC_W address from SrcR, data from SrcL, and size four") { - val result = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SC_W, - sources = Vector(source(0x55667788), source(0x4400), source(0xdead, valid = false, ready = false)))) - - assert(result.supported) - assert(result.sourceMask == 0x3) - assert(result.sourceReady) - assert(result.execValid) - assert(result.addr == 0x4400) - assert(result.data == 0x55667788) - assert(result.size == 4) - } - - test("reference blocks OP_SC_W on SrcL or SrcR but not SrcP") { - val srcLBlocked = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SC_W, - sources = Vector(source(0x55, ready = false), source(0x1000), source(0x2000)))) - val srcRBlocked = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SC_W, - sources = Vector(source(0x55), source(0x1000, ready = false), source(0x2000)))) - val srcPIgnored = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_SC_W, - sources = Vector(source(0x55), source(0x1000), source(0x2000, valid = false, ready = false)))) - - assert(!srcLBlocked.sourceReady) - assert(!srcLBlocked.execValid) - assert(!srcRBlocked.sourceReady) - assert(!srcRBlocked.execValid) - assert(srcPIgnored.sourceReady) - assert(srcPIgnored.execValid) - } - - test("bridge executes OP_SC_W All payload from SrcL data and SrcR address without SrcP") { - simulate(new ReducedStoreStaAddressExecBridge( - p = InterfaceParams(), - mapQDepth = 32, - peIdWidth = InterfaceParams().peIdWidth, - stidWidth = InterfaceParams().threadIdWidth, - tidWidth = InterfaceParams().threadIdWidth, - sizeWidth = InterfaceParams().memSizeWidth - )) { dut => - dut.io.enable.poke(true.B) - dut.io.queueValid.poke(true.B) - dut.io.queue.poke(0.U.asTypeOf(dut.io.queue)) - dut.io.queue.valid.poke(true.B) - dut.io.queue.storeType.poke(StoreSplitStoreType.All) - dut.io.queue.uop.valid.poke(true.B) - dut.io.queue.uop.opcode.poke(FrontendOpcodeDecodeTable.OP_SC_W.U) - dut.io.queue.uop.isStore.poke(true.B) - dut.io.queue.uop.threadId.poke(3.U) - dut.io.queue.uop.src(0).valid.poke(true.B) - dut.io.queue.uop.src(0).operandClass.poke(OperandClass.P) - dut.io.queue.uop.src(1).valid.poke(true.B) - dut.io.queue.uop.src(1).operandClass.poke(OperandClass.P) - dut.io.queue.uop.src(2).valid.poke(false.B) - dut.io.queue.uop.src(2).operandClass.poke(OperandClass.P) - dut.io.srcReadReady(0).poke(true.B) - dut.io.srcReadReady(1).poke(true.B) - dut.io.srcReadReady(2).poke(false.B) - dut.io.srcReadData(0).poke(0x55667788L.U) - dut.io.srcReadData(1).poke(0x4400.U) - dut.io.srcReadData(2).poke(0xdead.U) - - dut.io.candidate.expect(true.B) - dut.io.supportedOpcode.expect(true.B) - dut.io.addrSourceMask.expect("b011".U) - dut.io.addrSourceReady.expect(true.B) - dut.io.exec.valid.expect(true.B) - dut.io.exec.addr.expect(0x4400.U) - dut.io.exec.data.expect(0x55667788L.U) - dut.io.exec.size.expect(4.U) - } - } - - test("bridge executes split OP_SC_W Addr payload only when SrcL data and SrcR address are both ready") { - simulate(new ReducedStoreStaAddressExecBridge( - p = InterfaceParams(), - mapQDepth = 32, - peIdWidth = InterfaceParams().peIdWidth, - stidWidth = InterfaceParams().threadIdWidth, - tidWidth = InterfaceParams().threadIdWidth, - sizeWidth = InterfaceParams().memSizeWidth - )) { dut => - dut.io.enable.poke(true.B) - dut.io.queueValid.poke(true.B) - dut.io.queue.poke(0.U.asTypeOf(dut.io.queue)) - dut.io.queue.valid.poke(true.B) - dut.io.queue.storeType.poke(StoreSplitStoreType.Addr) - dut.io.queue.uop.valid.poke(true.B) - dut.io.queue.uop.opcode.poke(FrontendOpcodeDecodeTable.OP_SC_W.U) - dut.io.queue.uop.isStore.poke(true.B) - dut.io.queue.uop.src(0).valid.poke(true.B) - dut.io.queue.uop.src(0).operandClass.poke(OperandClass.P) - dut.io.queue.uop.src(1).valid.poke(true.B) - dut.io.queue.uop.src(1).operandClass.poke(OperandClass.P) - dut.io.queue.uop.src(2).valid.poke(false.B) - dut.io.srcReadReady(0).poke(true.B) - dut.io.srcReadReady(1).poke(false.B) - dut.io.srcReadReady(2).poke(false.B) - dut.io.srcReadData(0).poke(0x11223344L.U) - dut.io.srcReadData(1).poke(0x8800.U) - dut.io.srcReadData(2).poke(0.U) - - dut.io.candidate.expect(true.B) - dut.io.addrSourceMask.expect("b011".U) - dut.io.addrSourceReady.expect(false.B) - dut.io.exec.valid.expect(false.B) - - dut.io.srcReadReady(1).poke(true.B) - dut.io.addrSourceReady.expect(true.B) - dut.io.exec.valid.expect(true.B) - dut.io.exec.addr.expect(0x8800.U) - dut.io.exec.data.expect(0x11223344L.U) - dut.io.exec.size.expect(4.U) - } - } - - test("reference lets PCR-store STA compute address without RF source readiness") { - val result = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_HL_SW_PCR, - pc = 0x4000, - imm = 0x24, - sources = Vector(source(0xaaaa, ready = false), source(0, valid = false), source(0, valid = false)))) - - assert(result.supported) - assert(result.sourceMask == 0) - assert(result.sourceReady) - assert(result.execValid) - assert(result.addr == 0x4024) - assert(result.size == 4) - } - - test("reference exposes compressed-store STA source loss after payload source-zeroing") { - val result = decide(QueueHead( - opcode = FrontendOpcodeDecodeTable.OP_C_SDI, - imm = 2, - sources = Vector(source(0x2000, valid = false), source(24), source(0, valid = false)))) - - assert(result.supported) - assert(result.sourceMask == 0x1) - assert(!result.sourceReady) - assert(!result.execValid) - } - - test("bridge elaborates with the reduced top interface parameters") { - val p = InterfaceParams() - val sv = ChiselStage.emitSystemVerilog(new ReducedStoreStaAddressExecBridge( - p = p, - mapQDepth = 32, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth - )) - assert(sv.contains("module ReducedStoreStaAddressExecBridge")) - assert(sv.contains("12'h193")) - assert(sv.contains("io_srcReadData_1 + {io_queue_uop_imm[62:0], 1'h0}")) - assert(sv.contains("4'h2")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecHlSdiPrProbe.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecHlSdiPrProbe.scala deleted file mode 100644 index b3532373..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecHlSdiPrProbe.scala +++ /dev/null @@ -1,153 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.rename.StoreSplitStoreType - -class ReducedStoreStaAddressExecHlSdiPrProbeIO extends Bundle { - val enable = Input(Bool()) - val queueValid = Input(Bool()) - val payloadValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val imm = Input(UInt(64.W)) - val storeType = Input(UInt(2.W)) - val peId = Input(UInt(8.W)) - val threadId = Input(UInt(8.W)) - val lsid = Input(UInt(32.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val srcValid = Input(Vec(3, Bool())) - val srcReady = Input(Vec(3, Bool())) - val srcData = Input(Vec(3, UInt(64.W))) - val srcArchTag = Input(Vec(3, UInt(6.W))) - val srcPhysTag = Input(Vec(3, UInt(6.W))) - - val candidate = Output(Bool()) - val supportedOpcode = Output(Bool()) - val addrSourceMask = Output(UInt(3.W)) - val addrSourceReady = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByUnsupported = Output(Bool()) - val execValid = Output(Bool()) - val execAddr = Output(UInt(64.W)) - val execData = Output(UInt(64.W)) - val execSize = Output(UInt(4.W)) - val execPeId = Output(UInt(8.W)) - val execStid = Output(UInt(8.W)) - val execTid = Output(UInt(8.W)) - val execStackValid = Output(Bool()) - val execScalarIex = Output(Bool()) - val execSimtLane = Output(UInt(8.W)) - val queueOpcode = Output(UInt(12.W)) - val queueInsnRaw = Output(UInt(64.W)) - val queueImm = Output(UInt(64.W)) - val queueStoreType = Output(UInt(2.W)) - val queueSrcValid = Output(Vec(3, Bool())) - val queueSrcReady = Output(Vec(3, Bool())) - val queueSrcData = Output(Vec(3, UInt(64.W))) - val queueSrcArchTag = Output(Vec(3, UInt(6.W))) - val queueSrcPhysTag = Output(Vec(3, UInt(6.W))) -} - -class ReducedStoreStaAddressExecHlSdiPrProbe extends Module { - private val p = InterfaceParams() - - val io = IO(new ReducedStoreStaAddressExecHlSdiPrProbeIO) - val bridge = Module(new ReducedStoreStaAddressExecBridge( - p = p, - mapQDepth = 32, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - sizeWidth = p.memSizeWidth - )) - - bridge.io.enable := io.enable - bridge.io.queueValid := io.queueValid - bridge.io.queue := 0.U.asTypeOf(bridge.io.queue) - bridge.io.queue.valid := io.payloadValid - bridge.io.queue.storeType := Mux( - io.storeType === 1.U, - StoreSplitStoreType.Addr, - Mux(io.storeType === 2.U, StoreSplitStoreType.Data, StoreSplitStoreType.All)) - bridge.io.queue.uop.valid := io.payloadValid - bridge.io.queue.uop.peId := io.peId - bridge.io.queue.uop.threadId := io.threadId - bridge.io.queue.uop.pc := io.pc - bridge.io.queue.uop.opcode := io.opcode - bridge.io.queue.uop.dispatchTarget := DispatchTarget.Lsu - bridge.io.queue.uop.imm := io.imm - bridge.io.queue.uop.immValid := true.B - bridge.io.queue.uop.rid.valid := io.ridValid - bridge.io.queue.uop.rid.wrap := io.ridWrap - bridge.io.queue.uop.rid.value := io.ridValue - bridge.io.queue.uop.bid.valid := io.bidValid - bridge.io.queue.uop.bid.wrap := io.bidWrap - bridge.io.queue.uop.bid.value := io.bidValue - bridge.io.queue.uop.gid.valid := io.gidValid - bridge.io.queue.uop.gid.wrap := io.gidWrap - bridge.io.queue.uop.gid.value := io.gidValue - bridge.io.queue.uop.lsid := io.lsid - bridge.io.queue.uop.isLoad := false.B - bridge.io.queue.uop.isStore := true.B - bridge.io.queue.uop.storeSplitIntent := true.B - bridge.io.queue.uop.insnLen := 6.U - bridge.io.queue.uop.insnRaw := io.insnRaw - - for (idx <- 0 until 3) { - bridge.io.queue.uop.src(idx).valid := io.srcValid(idx) - bridge.io.queue.uop.src(idx).operandClass := OperandClass.P - bridge.io.queue.uop.src(idx).archTag := io.srcArchTag(idx) - bridge.io.queue.uop.src(idx).physTag := io.srcPhysTag(idx) - bridge.io.queue.uop.src(idx).ready := io.srcReady(idx) - bridge.io.srcReadReady(idx) := io.srcReady(idx) - bridge.io.srcReadData(idx) := io.srcData(idx) - } - - io.candidate := bridge.io.candidate - io.supportedOpcode := bridge.io.supportedOpcode - io.addrSourceMask := bridge.io.addrSourceMask - io.addrSourceReady := bridge.io.addrSourceReady - io.blockedBySource := bridge.io.blockedBySource - io.blockedByUnsupported := bridge.io.blockedByUnsupported - io.execValid := bridge.io.exec.valid - io.execAddr := bridge.io.exec.addr - io.execData := bridge.io.exec.data - io.execSize := bridge.io.exec.size - io.execPeId := bridge.io.exec.peId - io.execStid := bridge.io.exec.stid - io.execTid := bridge.io.exec.tid - io.execStackValid := bridge.io.exec.stackValid - io.execScalarIex := bridge.io.exec.scalarIex - io.execSimtLane := bridge.io.exec.simtLane - io.queueOpcode := bridge.io.queue.uop.opcode - io.queueInsnRaw := bridge.io.queue.uop.insnRaw - io.queueImm := bridge.io.queue.uop.imm - io.queueStoreType := io.storeType - io.queueSrcValid := io.srcValid - io.queueSrcReady := io.srcReady - io.queueSrcData := io.srcData - io.queueSrcArchTag := io.srcArchTag - io.queueSrcPhysTag := io.srcPhysTag -} - -object EmitReducedStoreStaAddressExecHlSdiPrProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/lsu-reduced-store-sta-address-exec-hl-sdi-pr-probe-r857") - - ChiselStage.emitSystemVerilogFile( - new ReducedStoreStaAddressExecHlSdiPrProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecSbProbe.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecSbProbe.scala deleted file mode 100644 index b5f13cea..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecSbProbe.scala +++ /dev/null @@ -1,152 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import chisel3._ -import linxcore.common.{DispatchTarget, InterfaceParams, OperandClass} -import linxcore.frontend.FrontendOpcodeDecodeTable -import linxcore.rename.StoreSplitStoreType - -class ReducedStoreStaAddressExecSbProbeIO extends Bundle { - val enable = Input(Bool()) - val queueValid = Input(Bool()) - val payloadValid = Input(Bool()) - val opcode = Input(UInt(12.W)) - val pc = Input(UInt(64.W)) - val insnRaw = Input(UInt(64.W)) - val imm = Input(UInt(64.W)) - val storeType = Input(UInt(2.W)) - val peId = Input(UInt(8.W)) - val threadId = Input(UInt(8.W)) - val lsid = Input(UInt(32.W)) - val bidValid = Input(Bool()) - val bidWrap = Input(Bool()) - val bidValue = Input(UInt(6.W)) - val gidValid = Input(Bool()) - val gidWrap = Input(Bool()) - val gidValue = Input(UInt(6.W)) - val ridValid = Input(Bool()) - val ridWrap = Input(Bool()) - val ridValue = Input(UInt(6.W)) - val srcValid = Input(Vec(3, Bool())) - val srcReady = Input(Vec(3, Bool())) - val srcData = Input(Vec(3, UInt(64.W))) - val srcArchTag = Input(Vec(3, UInt(6.W))) - val srcPhysTag = Input(Vec(3, UInt(6.W))) - - val candidate = Output(Bool()) - val supportedOpcode = Output(Bool()) - val addrSourceMask = Output(UInt(3.W)) - val addrSourceReady = Output(Bool()) - val blockedBySource = Output(Bool()) - val blockedByUnsupported = Output(Bool()) - val execValid = Output(Bool()) - val execAddr = Output(UInt(64.W)) - val execData = Output(UInt(64.W)) - val execSize = Output(UInt(4.W)) - val execPeId = Output(UInt(8.W)) - val execStid = Output(UInt(8.W)) - val execTid = Output(UInt(8.W)) - val execStackValid = Output(Bool()) - val execScalarIex = Output(Bool()) - val execSimtLane = Output(UInt(8.W)) - val queueOpcode = Output(UInt(12.W)) - val queueInsnRaw = Output(UInt(64.W)) - val queueStoreType = Output(UInt(2.W)) - val queueSrcValid = Output(Vec(3, Bool())) - val queueSrcReady = Output(Vec(3, Bool())) - val queueSrcData = Output(Vec(3, UInt(64.W))) - val queueSrcArchTag = Output(Vec(3, UInt(6.W))) - val queueSrcPhysTag = Output(Vec(3, UInt(6.W))) -} - -class ReducedStoreStaAddressExecSbProbe extends Module { - private val p = InterfaceParams() - - val io = IO(new ReducedStoreStaAddressExecSbProbeIO) - val bridge = Module(new ReducedStoreStaAddressExecBridge( - p = p, - mapQDepth = 32, - peIdWidth = p.peIdWidth, - stidWidth = p.threadIdWidth, - tidWidth = p.threadIdWidth, - sizeWidth = p.memSizeWidth - )) - - bridge.io.enable := io.enable - bridge.io.queueValid := io.queueValid - bridge.io.queue := 0.U.asTypeOf(bridge.io.queue) - bridge.io.queue.valid := io.payloadValid - bridge.io.queue.storeType := Mux( - io.storeType === 1.U, - StoreSplitStoreType.Addr, - Mux(io.storeType === 2.U, StoreSplitStoreType.Data, StoreSplitStoreType.All)) - bridge.io.queue.uop.valid := io.payloadValid - bridge.io.queue.uop.peId := io.peId - bridge.io.queue.uop.threadId := io.threadId - bridge.io.queue.uop.pc := io.pc - bridge.io.queue.uop.opcode := io.opcode - bridge.io.queue.uop.dispatchTarget := DispatchTarget.Lsu - bridge.io.queue.uop.imm := io.imm - bridge.io.queue.uop.immValid := true.B - bridge.io.queue.uop.rid.valid := io.ridValid - bridge.io.queue.uop.rid.wrap := io.ridWrap - bridge.io.queue.uop.rid.value := io.ridValue - bridge.io.queue.uop.bid.valid := io.bidValid - bridge.io.queue.uop.bid.wrap := io.bidWrap - bridge.io.queue.uop.bid.value := io.bidValue - bridge.io.queue.uop.gid.valid := io.gidValid - bridge.io.queue.uop.gid.wrap := io.gidWrap - bridge.io.queue.uop.gid.value := io.gidValue - bridge.io.queue.uop.lsid := io.lsid - bridge.io.queue.uop.isLoad := false.B - bridge.io.queue.uop.isStore := true.B - bridge.io.queue.uop.storeSplitIntent := true.B - bridge.io.queue.uop.insnLen := 4.U - bridge.io.queue.uop.insnRaw := io.insnRaw - - for (idx <- 0 until 3) { - bridge.io.queue.uop.src(idx).valid := io.srcValid(idx) - bridge.io.queue.uop.src(idx).operandClass := OperandClass.P - bridge.io.queue.uop.src(idx).archTag := io.srcArchTag(idx) - bridge.io.queue.uop.src(idx).physTag := io.srcPhysTag(idx) - bridge.io.queue.uop.src(idx).ready := io.srcReady(idx) - bridge.io.srcReadReady(idx) := io.srcReady(idx) - bridge.io.srcReadData(idx) := io.srcData(idx) - } - - io.candidate := bridge.io.candidate - io.supportedOpcode := bridge.io.supportedOpcode - io.addrSourceMask := bridge.io.addrSourceMask - io.addrSourceReady := bridge.io.addrSourceReady - io.blockedBySource := bridge.io.blockedBySource - io.blockedByUnsupported := bridge.io.blockedByUnsupported - io.execValid := bridge.io.exec.valid - io.execAddr := bridge.io.exec.addr - io.execData := bridge.io.exec.data - io.execSize := bridge.io.exec.size - io.execPeId := bridge.io.exec.peId - io.execStid := bridge.io.exec.stid - io.execTid := bridge.io.exec.tid - io.execStackValid := bridge.io.exec.stackValid - io.execScalarIex := bridge.io.exec.scalarIex - io.execSimtLane := bridge.io.exec.simtLane - io.queueOpcode := bridge.io.queue.uop.opcode - io.queueInsnRaw := bridge.io.queue.uop.insnRaw - io.queueStoreType := io.storeType - io.queueSrcValid := io.srcValid - io.queueSrcReady := io.srcReady - io.queueSrcData := io.srcData - io.queueSrcArchTag := io.srcArchTag - io.queueSrcPhysTag := io.srcPhysTag -} - -object EmitReducedStoreStaAddressExecSbProbe extends App { - val targetDir = args.sliding(2, 1).collectFirst { - case Array("--target-dir", dir) => dir - }.getOrElse("generated/chisel-verilog/lsu-reduced-store-sta-address-exec-sb-probe-r813") - - ChiselStage.emitSystemVerilogFile( - new ReducedStoreStaAddressExecSbProbe, - firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info"), - args = Array("--target-dir", targetDir)) -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala deleted file mode 100644 index ed6687a8..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala +++ /dev/null @@ -1,205 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -class ReducedStoreWaitReplayChiselPathSpec extends AnyFunSuite { - import ReducedLoadWaitReplaySlotReference.{Capture, Id => SlotId, Wake} - import ReducedStoreResidentForwardReference.{Id => ForwardId, Row => ForwardRow} - import ResidentStoreReplayWakeupReference.{Row => WakeRow, WaitStore} - - private def forwardId(value: Int, wrap: Boolean = false): ForwardId = - ForwardId(value = value, wrap = wrap) - - private def slotId(value: Int, wrap: Boolean = false): SlotId = - SlotId(valid = true, wrap = wrap, value = value) - - private def wakeId(value: Int, wrap: Boolean = false): STQFlushPruneReference.Id = - STQFlushPruneReference.Id(valid = true, wrap = wrap, value = value) - - test("STA-only resident store is the required timing window for wait replay capture") { - val storeBidValue = 7 - val storeLsIdValue = 1 - val loadBidValue = 8 - val loadLsIdValue = 3 - val storePc = BigInt(0x4400) - val loadPc = BigInt(0x5000) - val loadAddr = BigInt(0x3000) - val storeData = BigInt("1122334455667788", 16) - val baseData = BigInt("ffeeddccbbaa9988", 16) - - val readyAtLookup = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = loadAddr, - loadSize = 8, - loadBid = forwardId(loadBidValue), - loadLsId = forwardId(loadLsIdValue), - baseData = baseData, - rows = Seq(ForwardRow( - dataReady = true, - bid = forwardId(storeBidValue), - lsId = forwardId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - - assert(!readyAtLookup.waitBlocked) - assert(readyAtLookup.forwardMask == BigInt("ff", 16)) - assert(readyAtLookup.waitStore.isEmpty) - - val staOnlyAtLookup = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = loadAddr, - loadSize = 8, - loadBid = forwardId(loadBidValue), - loadLsId = forwardId(loadLsIdValue), - baseData = baseData, - rows = Seq(ForwardRow( - dataReady = false, - bid = forwardId(storeBidValue), - lsId = forwardId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - - assert(staOnlyAtLookup.waitBlocked) - assert(staOnlyAtLookup.forwardMask == 0) - assert(staOnlyAtLookup.waitStore.nonEmpty) - - val waitKey = staOnlyAtLookup.waitStore.get - val captured = ReducedLoadWaitReplaySlotReference.step( - ReducedLoadWaitReplaySlotReference.State(), - capture = Some(Capture( - pc = loadPc, - addr = loadAddr, - size = 8, - bid = slotId(loadBidValue), - lsId = slotId(loadLsIdValue), - waitKey = ReducedLoadWaitReplaySlotReference.Wait( - valid = true, - index = waitKey.index, - storeId = slotId(waitKey.bid.value, waitKey.bid.wrap), - storeLsId = slotId(waitKey.lsId.value, waitKey.lsId.wrap), - pc = waitKey.pc), - gid = slotId(0), - rid = slotId(4), - youngestStoreId = Some(slotId(storeBidValue)), - youngestStoreLsId = Some(slotId(storeLsIdValue))))) - - assert(captured.captureAccepted) - assert(captured.state.active) - - val notReadyWake = ResidentStoreReplayWakeupReference( - enable = true, - waitStore = WaitStore(index = waitKey.index, storeId = wakeId(storeBidValue), storeLsId = wakeId(storeLsIdValue), pc = storePc), - rows = Seq(WakeRow( - dataReady = false, - bid = wakeId(storeBidValue), - lsId = wakeId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - assert(notReadyWake.identityMatch) - assert(!notReadyWake.wakeValid) - - val readyWake = ResidentStoreReplayWakeupReference( - enable = true, - waitStore = WaitStore(index = waitKey.index, storeId = wakeId(storeBidValue), storeLsId = wakeId(storeLsIdValue), pc = storePc), - rows = Seq(WakeRow( - bid = wakeId(storeBidValue), - lsId = wakeId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - assert(readyWake.wakeValid) - - val cleared = ReducedLoadWaitReplaySlotReference.step( - captured.state, - wake = Some(Wake(storeId = slotId(storeBidValue), storeLsId = slotId(storeLsIdValue), pc = storePc))) - - assert(cleared.waitStoreClear) - assert(cleared.relaunch.exists(_.youngestStoreLsId.value == storeLsIdValue)) - } - - test("Chisel wait-replay path probe elaborates the real STQ to LIQ owner chain") { - val sv = ChiselStage.emitSystemVerilog(new ReducedStoreWaitReplayChiselPathProbe(entries = 8, liqEntries = 4)) - - assert(sv.contains("module ReducedStoreWaitReplayChiselPathProbe")) - assert(sv.contains("STQEntryBank")) - assert(sv.contains("ReducedStoreResidentForward")) - assert(sv.contains("ReducedLoadWaitReplaySlot")) - assert(sv.contains("ResidentStoreReplayWakeup")) - assert(sv.contains("ReducedLoadReplayRelaunchQueue")) - assert(sv.contains("ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("io_forwardWaitBlocked")) - assert(sv.contains("io_waitSlotCaptureAccepted")) - assert(sv.contains("io_wakeSelectedRowReady")) - assert(sv.contains("io_relaunchQueueOutFire")) - assert(sv.contains("io_liqAllocAccepted")) - assert(sv.contains("io_liqRefillAccepted")) - assert(sv.contains("io_liqReplayWakeValid")) - assert(sv.contains("io_liqReplayWake_source")) - assert(sv.contains("io_liqReplayWakeCompletedMask")) - assert(sv.contains("io_liqLaunchAccepted")) - assert(sv.contains("io_liqLaunchSelectedLoadLsId_value")) - assert(sv.contains("io_liqE2LoadDataReturned")) - assert(sv.contains("io_liqE4UpdateValid")) - assert(sv.contains("io_liqLhqRecordValid")) - assert(sv.contains("io_liqLhqRecordLoadLsId_value")) - assert(sv.contains("io_liqResolvedMask")) - assert(sv.contains("LoadResolveQueue")) - assert(sv.contains("io_resolveQueuePushAccepted")) - assert(sv.contains("io_resolveQueueRetireValid")) - assert(sv.contains("io_resolveQueueRetireCount")) - assert(sv.contains("io_resolveQueueFirstLoadLsId_value")) - assert(sv.contains("MDBConflictDetect")) - assert(sv.contains("io_mdbStore_valid")) - assert(sv.contains("io_mdbResolveCandidateMask")) - assert(sv.contains("io_mdbNukeFlush")) - assert(sv.contains("io_mdbConflictLoadLsId_value")) - assert(sv.contains("MDBQueueFanout")) - assert(sv.contains("io_mdbFanoutRecordAccepted")) - assert(sv.contains("io_mdbFanoutBmdbReportValid")) - assert(sv.contains("io_mdbFanoutSsitValidMask")) - assert(sv.contains("io_mdbLookupValid")) - assert(sv.contains("io_mdbFanoutLookupAccepted")) - assert(sv.contains("io_mdbDeleteValid")) - assert(sv.contains("io_mdbFanoutDeleteAccepted")) - assert(sv.contains("io_mdbFanoutDeleteReleased")) - assert(sv.contains("io_mdbFanoutLuOutHit")) - assert(sv.contains("io_mdbFanoutSuWakeupValid")) - assert(sv.contains("LoadReplayMdbLookupWaitPlan")) - assert(sv.contains("io_mdbLookupUseLiveLoad")) - assert(sv.contains("io_mdbLookupWaitPlanBlockedByNoTarget")) - assert(sv.contains("io_rowMutationBridgeValid")) - assert(sv.contains("io_rowMutationWriteEnable")) - assert(sv.contains("io_rowMutationControlBlockedByScbNotReturned")) - assert(sv.contains("io_liqWaitStoreMask")) - assert(sv.contains("io_liqScbReturnedMask")) - assert(sv.contains("io_liqClearResolvedAccepted")) - assert(sv.contains("io_liqFirstYoungestStoreLsId_value")) - } - - test("generated wait-replay fixture keeps full LSID width independent of ROB capacity") { - val io = new ReducedStoreWaitReplayChiselPathProbeIO( - entries = 8, - liqEntries = 4, - addrWidth = 64, - dataWidth = 64, - pcWidth = 64, - lineBytes = 64, - sizeWidth = 7, - lsidWidth = 40) - - assert(io.storeInsert.lsIdFull.getWidth == 40) - assert(io.loadLsIdFull.getWidth == 40) - assert(io.liqReplayWake.storeLsIdFull.getWidth == 40) - assert(io.mdbStore.lsIdFull.getWidth == 40) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayToLiqPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayToLiqPathSpec.scala deleted file mode 100644 index 7024fb8e..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayToLiqPathSpec.scala +++ /dev/null @@ -1,152 +0,0 @@ -package linxcore.lsu - -import org.scalatest.funsuite.AnyFunSuite - -class ReducedStoreWaitReplayToLiqPathSpec extends AnyFunSuite { - import ReducedLoadReplayLiqAllocPathReference.Model - import ReducedLoadReplayRelaunchQueueReference.{Model => QueueModel} - import ReducedLoadWaitReplaySlotReference.{Capture, Id => SlotId, Wake} - import ReducedStoreResidentForwardReference.{Id => ForwardId, Row => ForwardRow} - import ResidentStoreReplayWakeupReference.{Row => WakeRow, WaitStore} - - private def forwardId(value: Int, wrap: Boolean = false): ForwardId = - ForwardId(value = value, wrap = wrap) - - private def slotId(value: Int, wrap: Boolean = false): SlotId = - SlotId(valid = true, wrap = wrap, value = value) - - private def wakeId(value: Int, wrap: Boolean = false): STQFlushPruneReference.Id = - STQFlushPruneReference.Id(valid = true, wrap = wrap, value = value) - - test("not-ready resident store captures, wakes, queues, and allocates a replay LIQ row") { - val storeBidValue = 7 - val storeLsIdValue = 1 - val loadBidValue = 8 - val loadLsIdValue = 3 - val storePc = BigInt(0x4400) - val loadPc = BigInt(0x5000) - val loadAddr = BigInt(0x3000) - val storeData = BigInt("1122334455667788", 16) - val baseData = BigInt("ffeeddccbbaa9988", 16) - - val forward = ReducedStoreResidentForwardReference( - enable = true, - loadValid = true, - loadAddr = loadAddr, - loadSize = 8, - loadBid = forwardId(loadBidValue), - loadLsId = forwardId(loadLsIdValue), - baseData = baseData, - rows = Seq(ForwardRow( - dataReady = false, - bid = forwardId(storeBidValue), - lsId = forwardId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - - assert(forward.waitBlocked) - assert(forward.forwardMask == 0) - assert(forward.waitMask == BigInt("ff", 16)) - assert(forward.data == baseData) - assert(forward.waitStore.nonEmpty) - - val waitKey = forward.waitStore.get - val afterCapture = ReducedLoadWaitReplaySlotReference.step( - ReducedLoadWaitReplaySlotReference.State(), - capture = Some(Capture( - pc = loadPc, - addr = loadAddr, - size = 8, - bid = slotId(loadBidValue), - lsId = slotId(loadLsIdValue), - waitKey = ReducedLoadWaitReplaySlotReference.Wait( - valid = true, - index = waitKey.index, - storeId = slotId(waitKey.bid.value, waitKey.bid.wrap), - storeLsId = slotId(waitKey.lsId.value, waitKey.lsId.wrap), - pc = waitKey.pc), - gid = slotId(0), - rid = slotId(4), - youngestStoreId = Some(slotId(storeBidValue)), - youngestStoreLsId = Some(slotId(storeLsIdValue))))) - - assert(afterCapture.captureAccepted) - assert(afterCapture.state.active) - assert(afterCapture.state.waitKey.pc == storePc) - - val notReadyWake = ResidentStoreReplayWakeupReference( - enable = true, - waitStore = WaitStore( - index = waitKey.index, - storeId = wakeId(storeBidValue), - storeLsId = wakeId(storeLsIdValue), - pc = storePc), - rows = Seq(WakeRow( - dataReady = false, - bid = wakeId(storeBidValue), - lsId = wakeId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - - assert(notReadyWake.selected) - assert(notReadyWake.identityMatch) - assert(!notReadyWake.ready) - assert(!notReadyWake.wakeValid) - - val readyWake = ResidentStoreReplayWakeupReference( - enable = true, - waitStore = WaitStore( - index = waitKey.index, - storeId = wakeId(storeBidValue), - storeLsId = wakeId(storeLsIdValue), - pc = storePc), - rows = Seq(WakeRow( - bid = wakeId(storeBidValue), - lsId = wakeId(storeLsIdValue), - pc = storePc, - addr = loadAddr, - data = storeData, - size = 8))) - - assert(readyWake.wakeValid) - assert(readyWake.wake.exists(_.validMask == BigInt("ff", 16))) - assert((readyWake.wake.get.data & ((BigInt(1) << 64) - 1)) == storeData) - - val afterWake = ReducedLoadWaitReplaySlotReference.step( - afterCapture.state, - wake = Some(Wake( - storeId = slotId(storeBidValue), - storeLsId = slotId(storeLsIdValue), - pc = storePc))) - - assert(afterWake.waitStoreClear) - assert(!afterWake.state.active) - val relaunch = afterWake.relaunch.getOrElse(fail("matching wake did not relaunch captured load")) - assert(relaunch.pc == loadPc) - assert(relaunch.addr == loadAddr) - assert(relaunch.lsId.value == loadLsIdValue) - assert(relaunch.youngestStoreId.value == storeBidValue) - assert(relaunch.youngestStoreLsId.value == storeLsIdValue) - - val queue = new QueueModel(depth = 2) - val queued = queue.step(enqueue = Some(relaunch)) - assert(queued.enqueueAccepted) - assert(queued.pending) - val head = queue.step(outReady = true) - assert(head.outFire) - assert(head.out.contains(relaunch)) - - val liq = new Model(entries = 4) - val allocated = liq.step(candidateIn = head.out) - assert(allocated.allocValid) - assert(allocated.allocReady) - assert(allocated.allocAccepted) - assert(allocated.residentCount == 1) - assert(allocated.rows.head.candidate.pc == loadPc) - assert(allocated.rows.head.candidate.youngestStoreLsId.value == storeLsIdValue) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/SCBCommitBridgeSpec.scala b/chisel/src/test/scala/linxcore/lsu/SCBCommitBridgeSpec.scala deleted file mode 100644 index 1a73e99f..00000000 --- a/chisel/src/test/scala/linxcore/lsu/SCBCommitBridgeSpec.scala +++ /dev/null @@ -1,146 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object SCBCommitBridgeReference { - final case class Request(valid: Boolean, addr: BigInt, data: BigInt, size: Int, stqIndex: Int, last: Boolean) - final case class Line(lineAddr: BigInt, mask: BigInt) - final case class StepResult( - modelBatchReady: Boolean, - accepted: Seq[Boolean], - stalled: Seq[Boolean], - freeMask: BigInt, - lines: Seq[Line]) - - final class Model(entries: Int, requestCount: Int) { - private var lines = Vector.empty[Line] - - def seed(lineAddrs: Seq[BigInt]): Unit = { - require(lineAddrs.size <= entries) - lines = lineAddrs.map(addr => Line(addr & ~BigInt(0x3f), BigInt(1))).toVector - } - - def step(reqs: Seq[Request]): StepResult = { - require(reqs.size == requestCount) - val accepted = Array.fill(reqs.size)(false) - val stalled = Array.fill(reqs.size)(false) - var freeMask = BigInt(0) - val modelBatchReady = (entries - lines.size) >= requestCount - - if (!modelBatchReady) { - reqs.zipWithIndex.foreach { case (req, lane) => - stalled(lane) = req.valid - } - return StepResult(modelBatchReady, accepted.toSeq, stalled.toSeq, freeMask, lines) - } - - reqs.zipWithIndex.foreach { case (req, lane) => - if (req.valid) { - val lineAddr = req.addr & ~BigInt(0x3f) - val hit = lines.indexWhere(_.lineAddr == lineAddr) - val target = - if (hit >= 0) hit - else if (lines.size < entries) { - lines = lines :+ Line(lineAddr, BigInt(0)) - lines.size - 1 - } else { - -1 - } - - if (target < 0) { - stalled(lane) = true - } else { - val merged = merge(lines(target), req) - lines = lines.updated(target, merged) - accepted(lane) = true - if (req.last) { - freeMask = freeMask | (BigInt(1) << req.stqIndex) - } - } - } - } - - StepResult(modelBatchReady, accepted.toSeq, stalled.toSeq, freeMask, lines) - } - - private def merge(line: Line, req: Request): Line = { - val off = (req.addr & 0x3f).toInt - val bytes = (0 until req.size).foldLeft(BigInt(0)) { case (mask, idx) => mask | (BigInt(1) << (off + idx)) } - line.copy(mask = line.mask | bytes) - } - } -} - -class SCBCommitBridgeSpec extends AnyFunSuite { - import SCBCommitBridgeReference._ - - test("model batch gate admits a single-line store only when enough free entries remain for the width") { - val bridge = new Model(entries = 4, requestCount = 2) - bridge.seed(Seq(0x1000, 0x2000)) - val result = bridge.step(Seq( - Request(valid = true, addr = 0x3004, data = 0x1122, size = 2, stqIndex = 1, last = true), - Request(valid = false, addr = 0, data = 0, size = 0, stqIndex = 0, last = false) - )) - - assert(result.modelBatchReady) - assert(result.accepted == Seq(true, false)) - assert(result.stalled == Seq(false, false)) - assert(result.freeMask == (BigInt(1) << 1)) - assert(result.lines.exists(line => line.lineAddr == BigInt(0x3000) && line.mask == (BigInt(3) << 4))) - } - - test("split store frees the STQ row only on the accepted last fragment") { - val bridge = new Model(entries = 4, requestCount = 2) - val result = bridge.step(Seq( - Request(valid = true, addr = 0x403e, data = BigInt("7788", 16), size = 2, stqIndex = 3, last = false), - Request(valid = true, addr = 0x4040, data = BigInt("112233445566", 16), size = 6, stqIndex = 3, last = true) - )) - - assert(result.modelBatchReady) - assert(result.accepted == Seq(true, true)) - assert(result.freeMask == (BigInt(1) << 3)) - assert(result.lines.map(_.lineAddr) == Seq(BigInt(0x4000), BigInt(0x4040))) - assert(result.lines.head.mask == (BigInt(3) << 62)) - assert(result.lines(1).mask == BigInt("3f", 16)) - } - - test("model-full batch gate stalls even same-line hits when free entries are below commit width") { - val bridge = new Model(entries = 2, requestCount = 2) - bridge.seed(Seq(0x5000)) - val result = bridge.step(Seq( - Request(valid = true, addr = 0x5008, data = 0xaa, size = 1, stqIndex = 0, last = true), - Request(valid = false, addr = 0, data = 0, size = 0, stqIndex = 1, last = false) - )) - - assert(!result.modelBatchReady) - assert(result.accepted == Seq(false, false)) - assert(result.stalled == Seq(true, false)) - assert(result.freeMask == BigInt(0)) - assert(result.lines == Seq(Line(BigInt(0x5000), BigInt(1)))) - } - - test("batch gate admits all request lanes when free count equals commit width") { - val bridge = new Model(entries = 2, requestCount = 2) - val result = bridge.step(Seq( - Request(valid = true, addr = 0x6000, data = 0x11, size = 1, stqIndex = 0, last = true), - Request(valid = true, addr = 0x6040, data = 0x22, size = 1, stqIndex = 1, last = true) - )) - - assert(result.modelBatchReady) - assert(result.accepted == Seq(true, true)) - assert(result.stalled == Seq(false, false)) - assert(result.freeMask == BigInt(3)) - assert(result.lines.map(_.lineAddr) == Seq(BigInt(0x6000), BigInt(0x6040))) - } - - test("Chisel SCBCommitBridge elaborates with model batch and STQ free outputs") { - val sv = ChiselStage.emitSystemVerilog(new SCBCommitBridge(stqEntries = 8, scbEntries = 4, requestCount = 2)) - - assert(sv.contains("module SCBCommitBridge")) - assert(sv.contains("SCBCommitIngress")) - assert(sv.contains("io_modelBatchReady")) - assert(sv.contains("io_stalledMask")) - assert(sv.contains("io_commitFreeMask")) - } -} diff --git a/chisel/src/test/scala/linxcore/lsu/SCBLoadSnapshotLookupSpec.scala b/chisel/src/test/scala/linxcore/lsu/SCBLoadSnapshotLookupSpec.scala new file mode 100644 index 00000000..f8ff5fcb --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/SCBLoadSnapshotLookupSpec.scala @@ -0,0 +1,41 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +class SCBLoadSnapshotLookupSpec extends AnyFunSuite with ChiselSim { + test("accepts one exact row and rejects stale or ambiguous snapshots") { + simulate(new SCBLoadSnapshotLookup(2, 16, 64)) { dut => + dut.io.rows.foreach(_.poke(0.U.asTypeOf(dut.io.rows.head))) + dut.io.lineAddress.poke(0x1200.U) + + dut.io.rows(0).valid.poke(true.B) + dut.io.rows(0).state.poke(SCBEntryState.Valid) + dut.io.rows(0).lineAddr.poke(0x1200.U) + dut.io.rows(0).byteMask.poke(0x5a.U) + dut.io.rows(0).data.poke(0x1234.U) + dut.io.returned.expect(true.B) + dut.io.ambiguous.expect(false.B) + dut.io.validMask.expect(0x5a.U) + dut.io.data.expect(0x1234.U) + + dut.io.rows(0).state.poke(SCBEntryState.Miss) + dut.io.returned.expect(true.B) + dut.io.ambiguous.expect(false.B) + dut.io.validMask.expect(0.U) + dut.io.data.expect(0.U) + + dut.io.rows(0).state.poke(SCBEntryState.Valid) + dut.io.rows(1).valid.poke(true.B) + dut.io.rows(1).state.poke(SCBEntryState.Valid) + dut.io.rows(1).lineAddr.poke(0x1200.U) + dut.io.rows(1).byteMask.poke(0xa5.U) + dut.io.rows(1).data.poke(0x5678.U) + dut.io.returned.expect(false.B) + dut.io.ambiguous.expect(true.B) + dut.io.validMask.expect(0.U) + dut.io.data.expect(0.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/SCBRowBankSpec.scala b/chisel/src/test/scala/linxcore/lsu/SCBRowBankSpec.scala index 3eadef18..1e5c299f 100644 --- a/chisel/src/test/scala/linxcore/lsu/SCBRowBankSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/SCBRowBankSpec.scala @@ -245,6 +245,9 @@ class SCBRowBankSpec extends AnyFunSuite with ChiselSim { dut.io.l2RequestReady.poke(true.B) dut.io.rawRespValid.poke(false.B) dut.io.rawRespTxnId.poke(0.U) + dut.io.rawRespTransactionValue.poke(0.U) + dut.io.rawRespTransactionGeneration.poke(0.U) + dut.io.rawRespError.poke(false.B) dut.io.rawRespWrite.poke(false.B) dut.io.rawRespUpgrade.poke(false.B) } @@ -498,6 +501,56 @@ class SCBRowBankSpec extends AnyFunSuite with ChiselSim { assert(sv.contains("io_stateError")) } + test("SCB quiescence covers resident rows ownership response buffering and retry") { + simulate(new SCBRowBank( + stqEntries = 8, scbEntries = 2, requestCount = 1, + responseBufferDepth = 2, robEntries = 8, + memoryTransactionIdWidth = 8, + memoryTransactionGenerationWidth = 4)) { dut => + idleRowBank(dut) + dut.io.quiescent.expect(true.B) + + pokeReq(dut.io.reqs(0), addr = 0x8000, stqIndex = 1, + segment = 0, last = true, bid = 1, gid = 1, rid = 1, lsId = 1) + dut.clock.step() + idleRowBank(dut) + dut.io.quiescent.expect(false.B) + + dut.io.evictEnable.poke(true.B) + dut.io.dcacheTagHit.poke(true.B) + dut.io.dcacheWriteHit.poke(false.B) + while (!dut.io.l2Request.valid.peek().litToBoolean) dut.clock.step() + val shortId = dut.io.l2Request.txnTid.peek() + val value = dut.io.l2Request.transactionValue.peek() + val generation = dut.io.l2Request.transactionGeneration.peek() + dut.clock.step() + idleRowBank(dut) + + dut.io.dcacheReady.poke(false.B) + dut.io.rawRespTxnId.poke(shortId) + dut.io.rawRespTransactionValue.poke(value) + dut.io.rawRespTransactionGeneration.poke(generation) + dut.io.rawRespUpgrade.poke(true.B) + dut.io.rawRespValid.poke(true.B) + dut.clock.step() + dut.io.rawRespValid.poke(false.B) + dut.io.quiescent.expect(false.B) + assert(dut.io.respBufferHeadValid.peek().litToBoolean || + dut.io.responseRetryHeadValid.peek().litToBoolean, + "accepted ownership response must remain represented until retry") + + dut.io.dcacheReady.poke(true.B) + dut.io.dcacheTagHit.poke(true.B) + dut.io.dcacheWriteHit.poke(true.B) + var drainCycles = 0 + while (!dut.io.quiescent.peek().litToBoolean && drainCycles < 16) { + dut.clock.step() + drainCycles += 1 + } + assert(drainCycles < 16, "SCB row/response/retry state did not drain") + } + } + test("physical STQ indices remain wider than ROB identity in a 16 by 8 configuration") { val io = new SCBRowBankIO( stqEntries = 16, diff --git a/chisel/src/test/scala/linxcore/lsu/SCBTemplateOwnershipBehaviorProbe.scala b/chisel/src/test/scala/linxcore/lsu/SCBTemplateOwnershipBehaviorProbe.scala index af554ac9..8283f6a4 100644 --- a/chisel/src/test/scala/linxcore/lsu/SCBTemplateOwnershipBehaviorProbe.scala +++ b/chisel/src/test/scala/linxcore/lsu/SCBTemplateOwnershipBehaviorProbe.scala @@ -53,6 +53,7 @@ class SCBTemplateOwnershipBehaviorProbe extends Module { bank.io.l2RequestReady := false.B bank.io.rawRespValid := false.B bank.io.rawRespTxnId := 0.U + bank.io.rawRespError := false.B bank.io.rawRespWrite := false.B bank.io.rawRespUpgrade := false.B diff --git a/chisel/src/test/scala/linxcore/lsu/STQCommittedStoreSerializerSpec.scala b/chisel/src/test/scala/linxcore/lsu/STQCommittedStoreSerializerSpec.scala index 46b943cc..37b46456 100644 --- a/chisel/src/test/scala/linxcore/lsu/STQCommittedStoreSerializerSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/STQCommittedStoreSerializerSpec.scala @@ -179,4 +179,46 @@ class STQCommittedStoreSerializerSpec extends AnyFunSuite with ChiselSim { dut.io.batch.ready.expect(false.B) } } + + test("serialized store response reuse requires the exact public generation") { + simulate(new STQCommittedStoreSerializer( + stqEntries = 8, robEntries = 8, issueWidth = 2, + transactionIdWidth = 2, transactionGenerationWidth = 2)) { dut => + clear(dut) + var firstValue = BigInt(0) + var firstGeneration = BigInt(0) + for (request <- 0 until 5) { + pokeBatch(dut, beats = 1, fragmentsPerBeat = 1) + dut.clock.step() + dut.io.batch.valid.poke(false.B) + val value = dut.io.request.bits.transactionId.peek().litValue + val generation = dut.io.request.bits.transactionGeneration.peek().litValue + if (request == 0) { + firstValue = value + firstGeneration = generation + } + if (request == 4) { + assert(value == firstValue, "test must exercise value reuse") + assert(generation != firstGeneration, "reused value needs a new generation") + } + dut.io.request.ready.poke(true.B) + dut.clock.step() + dut.io.request.ready.poke(false.B) + + dut.io.response.valid.poke(true.B) + dut.io.response.bits.transactionId.poke(value.U) + dut.io.response.bits.transactionGeneration.poke( + (if (request == 4) firstGeneration else generation).U) + if (request == 4) { + dut.io.staleResponse.expect(true.B) + dut.io.response.ready.expect(false.B) + dut.clock.step() + dut.io.response.bits.transactionGeneration.poke(generation.U) + } + dut.io.response.ready.expect(true.B) + dut.clock.step() + dut.io.response.valid.poke(false.B) + } + } + } } diff --git a/chisel/src/test/scala/linxcore/lsu/STQLoadForwardResultPipelineSpec.scala b/chisel/src/test/scala/linxcore/lsu/STQLoadForwardResultPipelineSpec.scala index 12349578..ed0f573f 100644 --- a/chisel/src/test/scala/linxcore/lsu/STQLoadForwardResultPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/STQLoadForwardResultPipelineSpec.scala @@ -10,6 +10,7 @@ class STQLoadForwardResultPipelineSpec extends AnyFunSuite with ChiselSim { dut.io.flush.poke(false.B) dut.io.response.valid.poke(false.B) dut.io.response.bits.poke(0.U.asTypeOf(dut.io.response.bits)) + dut.io.normalReady.poke(true.B) dut.io.returnReady.poke(true.B) dut.io.hardBlock.ready.poke(true.B) } @@ -24,6 +25,19 @@ class STQLoadForwardResultPipelineSpec extends AnyFunSuite with ChiselSim { data: BigInt): Unit = { dut.io.response.bits.poke(0.U.asTypeOf(dut.io.response.bits)) dut.io.response.bits.query.token.poke(token.U) + dut.io.response.bits.query.loadId.valid.poke(true.B) + dut.io.response.bits.query.loadId.slot.poke((token & 3).U) + dut.io.response.bits.query.loadId.generation.poke((token & 1).U) + dut.io.response.bits.query.attempt.valid.poke(true.B) + dut.io.response.bits.query.attempt.producer.valid.poke(true.B) + dut.io.response.bits.query.attempt.producer.nativeBidValid.poke(true.B) + dut.io.response.bits.query.attempt.producer.stid.poke(1.U) + dut.io.response.bits.query.attempt.generation.poke(token.U) + dut.io.response.bits.query.returnPipeIndex.poke((token % 3).U) + dut.io.response.bits.query.stid.poke(1.U) + dut.io.response.bits.query.loadBid.valid.poke(true.B) + dut.io.response.bits.query.loadLsIdFullValid.poke(true.B) + dut.io.response.bits.query.size.poke(8.U) dut.io.response.bits.query.baseValidMask.poke(baseMask.U) dut.io.response.bits.query.loadDataReturned.poke(true.B) dut.io.response.bits.query.scbReturned.poke(true.B) @@ -66,20 +80,83 @@ class STQLoadForwardResultPipelineSpec extends AnyFunSuite with ChiselSim { dut.io.response.valid.poke(false.B) dut.io.e3Valid.expect(true.B) + dut.io.e3Identity.loadId.slot.expect(1.U) + dut.io.e3Identity.attempt.generation.expect(17.U) + dut.io.e3Identity.returnPipeIndex.expect(2.U) dut.io.e3LoadByteMask.expect(0xf.U) dut.io.e3ForwardMask.expect(0xc.U) dut.clock.step() dut.io.e4Valid.expect(true.B) + dut.io.e4Identity.loadId.slot.expect(1.U) + dut.io.e4Identity.attempt.generation.expect(17.U) + dut.io.e4Identity.returnPipeIndex.expect(2.U) dut.io.e4ValidMask.expect(0xf.U) dut.io.e4DataComplete.expect(true.B) dut.io.e4SourcesReturned.expect(true.B) + dut.io.e4ScbReturned.expect(true.B) + dut.io.e4StqReturned.expect(true.B) dut.io.e4WakeupValid.expect(true.B) dut.io.e4MissKind.expect(LoadForwardMissKind.NoMiss) dut.io.e4LineData.expect(BigInt("ddccbbaa", 16).U) } } + test("normal result credit backpressures data responses but not hard blocks") { + simulate(new STQLoadForwardResultPipeline( + robEntries = 8, stqEntries = 4, lsidWidth = 40)) { dut => + clear(dut) + pokeBaseResponse(dut, token = 23, loadMask = 0xff, + baseMask = 0xff, forwardMask = 0, waitMask = 0, + data = BigInt("8877665544332211", 16)) + dut.io.normalReady.poke(false.B) + dut.io.response.valid.poke(true.B) + dut.io.response.ready.expect(false.B) + dut.io.accepted.expect(false.B) + dut.clock.step(2) + dut.io.e3Valid.expect(false.B) + dut.io.e4Valid.expect(false.B) + + dut.io.response.bits.unknownOlderMask.poke(1.U) + dut.io.response.ready.expect(true.B) + dut.io.hardBlock.valid.expect(true.B) + dut.io.hardBlockAccepted.expect(true.B) + } + } + + test("back to back responses keep exact canonical identities aligned") { + simulate(new STQLoadForwardResultPipeline( + robEntries = 8, stqEntries = 4, lsidWidth = 40)) { dut => + clear(dut) + pokeBaseResponse(dut, token = 21, loadMask = 0xff, + baseMask = 0xff, forwardMask = 0, waitMask = 0, + data = BigInt("1111111111111111", 16)) + dut.io.response.valid.poke(true.B) + dut.clock.step() + + pokeBaseResponse(dut, token = 22, loadMask = 0xff, + baseMask = 0xff, forwardMask = 0, waitMask = 0, + data = BigInt("2222222222222222", 16)) + dut.io.response.valid.poke(true.B) + dut.io.e3Identity.attempt.generation.expect(21.U) + dut.clock.step() + + dut.io.response.valid.poke(false.B) + dut.io.e4Valid.expect(true.B) + dut.io.e4Identity.attempt.generation.expect(21.U) + dut.io.e3Valid.expect(true.B) + dut.io.e3Identity.attempt.generation.expect(22.U) + dut.clock.step() + + dut.io.e4Valid.expect(true.B) + dut.io.e4Identity.attempt.generation.expect(22.U) + dut.io.flush.poke(true.B) + dut.clock.step() + dut.io.e3Valid.expect(false.B) + dut.io.e4Valid.expect(false.B) + } + } + test("selected not-ready store remains an ordinary precise replay result") { simulate(new STQLoadForwardResultPipeline( robEntries = 8, stqEntries = 4, lsidWidth = 40)) { dut => diff --git a/chisel/src/test/scala/linxcore/lsu/STQLoadForwardingPipelineSpec.scala b/chisel/src/test/scala/linxcore/lsu/STQLoadForwardingPipelineSpec.scala index f72581a7..8e9eb460 100644 --- a/chisel/src/test/scala/linxcore/lsu/STQLoadForwardingPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/STQLoadForwardingPipelineSpec.scala @@ -90,9 +90,19 @@ class STQLoadForwardingPipelineSpec extends AnyFunSuite with ChiselSim { bid: Int, lsid: BigInt, address: BigInt, - size: Int): Unit = { + size: Int, + pipeIndex: Int = 0): Unit = { query.poke(0.U.asTypeOf(query)) query.token.poke(token.U) + query.loadId.valid.poke(true.B) + query.loadId.slot.poke((token & 3).U) + query.loadId.generation.poke((token & 1).U) + query.attempt.valid.poke(true.B) + query.attempt.producer.valid.poke(true.B) + query.attempt.producer.nativeBidValid.poke(true.B) + query.attempt.producer.stid.poke(1.U) + query.attempt.generation.poke(token.U) + query.returnPipeIndex.poke(pipeIndex.U) query.stid.poke(1.U) pokeId(query.loadBid, bid) query.loadLsIdFullValid.poke(true.B) @@ -107,7 +117,7 @@ class STQLoadForwardingPipelineSpec extends AnyFunSuite with ChiselSim { clear(dut) for (pipe <- 0 until 3) { pokeQuery(dut.io.queries(pipe).bits, 0x20 + pipe, 3, 30, - 0x1000 + pipe * 8, 8) + 0x1000 + pipe * 8, 8, pipeIndex = pipe) dut.io.queries(pipe).valid.poke(true.B) dut.io.queries(pipe).ready.expect(true.B) } @@ -222,6 +232,39 @@ class STQLoadForwardingPipelineSpec extends AnyFunSuite with ChiselSim { } } + test("canonical load attempt and return pipe identity fail closed") { + simulate(new STQLoadForwardingPipeline( + loadPipes = 2, stqEntries = 4, robEntries = 8, lsidWidth = 40)) { dut => + clear(dut) + pokeQuery(dut.io.queries(1).bits, 22, 3, 30, 0x4800, 8, + pipeIndex = 0) + dut.io.queries(1).valid.poke(true.B) + dut.clock.step() + dut.io.queries(1).valid.poke(false.B) + dut.clock.step() + dut.io.responses(1).bits.queryIdentityInvalid.expect(true.B) + dut.io.responses(1).bits.blocked.expect(true.B) + + pokeQuery(dut.io.queries(0).bits, 23, 3, 30, 0x4800, 8) + dut.io.queries(0).bits.attempt.producer.stid.poke(2.U) + dut.io.queries(0).valid.poke(true.B) + dut.clock.step() + dut.io.queries(0).valid.poke(false.B) + dut.clock.step() + dut.io.responses(0).bits.queryIdentityInvalid.expect(true.B) + dut.io.responses(0).bits.blocked.expect(true.B) + + pokeQuery(dut.io.queries(0).bits, 24, 3, 30, 0x4800, 8) + dut.io.queries(0).bits.loadId.valid.poke(false.B) + dut.io.queries(0).valid.poke(true.B) + dut.clock.step() + dut.io.queries(0).valid.poke(false.B) + dut.clock.step() + dut.io.responses(0).bits.queryIdentityInvalid.expect(true.B) + dut.io.responses(0).bits.blocked.expect(true.B) + } + } + test("recovery prepare suppresses response fire without losing residency") { simulate(new STQLoadForwardingPipeline( loadPipes = 1, stqEntries = 4, robEntries = 8, lsidWidth = 40)) { dut => diff --git a/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadForwardIntegrationSpec.scala b/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadForwardIntegrationSpec.scala new file mode 100644 index 00000000..a237fc59 --- /dev/null +++ b/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadForwardIntegrationSpec.scala @@ -0,0 +1,330 @@ +package linxcore.lsu + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +import linxcore.common.{CoreParams, ScalarLsuParams} +import linxcore.rob.ROBID + +class ScalarLSULoadForwardIntegrationHarnessIO extends Bundle { + val flush = Input(Bool()) + val preciseFlush = Input(Bool()) + val nativeBid = Input(UInt(LoadAttemptIdentity.IndexWidth.W)) + val allocValid = Input(Bool()) + val allocAccepted = Output(Bool()) + val launchValid = Input(Bool()) + val launchAccepted = Output(Bool()) + val queryReady = Input(Bool()) + val queryValid = Output(Bool()) + val queryAccepted = Output(Bool()) + val queryCaptured = Output(Bool()) + val queryLoadId = Output(new LoadCanonicalRowIdentity) + val queryAttempt = Output(new LoadAttemptIdentity) + val responseValid = Input(Bool()) + val responseReady = Output(Bool()) + val resultAccepted = Output(Bool()) + val resultPending = Output(Bool()) + val pathEmpty = Output(Bool()) + val rowDataComplete = Output(Bool()) + val rowLineData = Output(UInt(512.W)) + val protocolError = Output(Bool()) +} + +class ScalarLSULoadForwardIntegrationHarness extends Module { + private val lsu = ScalarLsuParams( + stqEntries = 4, + commitQueueEntries = 4, + commitIssueWidth = 1, + scbEntries = 4, + liqEntries = 4, + loadMissQueueEntries = 2, + loadRefillQueueEntries = 2, + resolveQueueEntries = 8, + mdbSsitEntries = 4, + mdbCommandQueueEntries = 4, + mdbOutputQueueEntries = 4, + mdbWaitPlanQueueEntries = 4, + mdbRecoveryQueueEntries = 4, + mdbFailedWaitTimeoutCycles = 8, + loadReturnQueueEntries = 2, + loadReturnPipeCount = 2, + l1dSets = 2, + l1dWays = 2, + mapQDepth = 8) + private val core = CoreParams(robEntries = 8, lsidWidth = 40, scalarLsu = lsu) + + val io = IO(new ScalarLSULoadForwardIntegrationHarnessIO) + val path = Module(new ScalarLSULoadPath( + core, + useExternalStqForwarding = true, + stqForwardRobEntries = 8, + stqForwardTokenWidth = 40)) + val forward = path.stqForward.get + + path.io.flush := io.flush + path.io.preciseFlush := 0.U.asTypeOf(path.io.preciseFlush) + path.io.l1dInvalidateAll := false.B + path.io.l1dInvalidateLineValid := false.B + path.io.l1dInvalidateLineAddress := 0.U + path.io.preciseFlush.req.valid := io.preciseFlush + path.io.preciseFlush.req.stid := 1.U + path.io.allocValid := io.allocValid + path.io.alloc := 0.U.asTypeOf(path.io.alloc) + path.io.alloc.bid := ROBID.zero(8) + path.io.alloc.gid := ROBID.zero(8) + path.io.alloc.rid := ROBID.zero(8) + path.io.alloc.loadLsId := ROBID.zero(8) + path.io.alloc.loadLsIdFullValid := true.B + path.io.alloc.loadLsIdFull := 11.U + path.io.alloc.attempt.valid := true.B + path.io.alloc.attempt.producer.valid := true.B + path.io.alloc.attempt.producer.peId := 0.U + path.io.alloc.attempt.producer.stid := 0.U + path.io.alloc.attempt.producer.nativeBidValid := true.B + path.io.alloc.attempt.producer.nativeBid := io.nativeBid + path.io.alloc.attempt.producer.brobGeneration := 2.U + path.io.alloc.attempt.producer.ridSlot := 3.U + path.io.alloc.attempt.producer.ridGeneration := 4.U + path.io.alloc.attempt.producer.memberIndex := 1.U + path.io.alloc.attempt.producer.residentGeneration := 6.U + path.io.alloc.attempt.generation := 7.U + path.io.alloc.addr := 0.U + path.io.alloc.size := 8.U + path.io.alloc.returnPipeIndex := 1.U + path.io.alloc.youngestStoreId := ROBID.disabled(8) + path.io.alloc.youngestStoreLsId := ROBID.disabled(8) + path.io.attemptRebindValid := false.B + path.io.attemptRebind := 0.U.asTypeOf(path.io.attemptRebind) + path.io.structuralRetryValid := false.B + path.io.structuralRetry := 0.U.asTypeOf(path.io.structuralRetry) + path.io.launchValid := io.launchValid + path.io.launchIndex := 0.U + path.io.pickValid := false.B + path.io.pickIndex := 0.U + path.io.scbReturnValid := false.B + path.io.scbReturnIndex := 0.U + + path.io.e2Stores := 0.U.asTypeOf(path.io.e2Stores) + path.io.e2ScbReturned := false.B + path.io.e2StqReturned := false.B + path.io.replayWakeValid := false.B + path.io.replayWake := 0.U.asTypeOf(path.io.replayWake) + path.io.refillValid := false.B + path.io.refill := 0.U.asTypeOf(path.io.refill) + path.io.missRequestReady := true.B + path.io.missResponseValid := false.B + path.io.missResponse := 0.U.asTypeOf(path.io.missResponse) + path.io.resolveRetireValid := false.B + path.io.resolveRetireBid := ROBID.disabled(8) + path.io.resolveRetireLsId := ROBID.disabled(8) + path.io.resolveRetireLsIdFullValid := false.B + path.io.resolveRetireLsIdFull := 0.U + path.io.l1dEvictionReady := true.B + path.io.loadReturn.robRowValid := true.B + path.io.loadReturn.robRowNeedFlush := false.B + path.io.loadReturn.resolveReady := true.B + path.io.loadReturn.writebackReady := true.B + path.io.loadReturn.wakeupReady := true.B + + path.scbCache.update := 0.U.asTypeOf(path.scbCache.update) + path.scbCache.lookupValid := false.B + path.scbCache.lookupLineAddr := 0.U + path.scbCache.grantWriteValid := false.B + path.scbCache.grantWriteLineAddr := 0.U + path.scbCache.grantWriteData := 0.U + path.mdbStore.probe := 0.U.asTypeOf(path.mdbStore.probe) + path.mdbStore.probeCommit := false.B + path.mdbStore.rows := 0.U.asTypeOf(path.mdbStore.rows) + path.recovery.ready := true.B + + forward.scb.returned := true.B + forward.scb.validMask := 0.U + forward.scb.data := 0.U + for (pipe <- 0 until 2) { + forward.queries(pipe).ready := io.queryReady + forward.responses(pipe).valid := false.B + forward.responses(pipe).bits := 0.U.asTypeOf(forward.responses(pipe).bits) + } + forward.hardBlock.ready := true.B + + val capturedQuery = RegInit(0.U.asTypeOf(chiselTypeOf(forward.queries(1).bits))) + val capturedQueryValid = RegInit(false.B) + when(forward.queries(1).fire) { + capturedQuery := forward.queries(1).bits + capturedQueryValid := true.B + } + forward.responses(1).valid := io.responseValid && capturedQueryValid + forward.responses(1).bits.query := capturedQuery + forward.responses(1).bits.loadByteMask := "hff".U + forward.responses(1).bits.forwardMask := "hff".U + forward.responses(1).bits.mergedLineData := "h8877665544332211".U + forward.responses(1).bits.bypassComplete := true.B + + io.allocAccepted := path.io.allocAccepted + io.launchAccepted := path.io.launchAccepted + io.queryValid := forward.queries(1).valid + io.queryAccepted := forward.queryAccepted + io.queryCaptured := capturedQueryValid + io.queryLoadId := forward.queries(1).bits.loadId + io.queryAttempt := forward.queries(1).bits.attempt + io.responseReady := forward.responses(1).ready && capturedQueryValid + io.resultAccepted := forward.resultAccepted + io.resultPending := forward.resultPending + io.pathEmpty := path.io.empty + io.rowDataComplete := path.io.liqRows(0).dataComplete + io.rowLineData := path.io.liqRows(0).lineData + io.protocolError := forward.protocolError || path.io.transferProtocolError || + (io.responseValid && !capturedQueryValid) +} + +class ScalarLSULoadForwardIntegrationSpec extends AnyFunSuite with ChiselSim { + test("two-pipe forwarding preserves query result recovery and identity behavior") { + simulate(new ScalarLSULoadForwardIntegrationHarness) { dut => + def resetHarness(nativeBid: Int = 5, queryReady: Boolean = false): Unit = { + dut.io.flush.poke(false.B) + dut.io.preciseFlush.poke(false.B) + dut.io.nativeBid.poke(nativeBid.U) + dut.io.allocValid.poke(false.B) + dut.io.launchValid.poke(false.B) + dut.io.queryReady.poke(queryReady.B) + dut.io.responseValid.poke(false.B) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + dut.clock.step() + } + + def allocateAndLaunch(): Unit = { + dut.io.allocValid.poke(true.B) + dut.io.allocAccepted.expect(true.B) + dut.clock.step() + dut.io.allocValid.poke(false.B) + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + } + + withClue("retained exact result: ") { + resetHarness() + dut.io.allocValid.poke(true.B) + dut.io.allocAccepted.expect(true.B) + dut.clock.step() + dut.io.allocValid.poke(false.B) + dut.io.launchValid.poke(true.B) + dut.io.queryValid.expect(false.B) + dut.io.launchAccepted.expect(true.B) + dut.clock.step() + dut.io.launchValid.poke(false.B) + dut.io.queryValid.expect(true.B) + dut.io.launchAccepted.expect(false.B) + dut.io.queryAccepted.expect(false.B) + dut.io.queryLoadId.valid.expect(true.B) + dut.io.queryLoadId.slot.expect(0.U) + dut.io.queryAttempt.generation.expect(7.U) + dut.clock.step(2) + dut.io.queryValid.expect(true.B) + dut.io.queryLoadId.slot.expect(0.U) + dut.io.queryAttempt.generation.expect(7.U) + dut.io.queryReady.poke(true.B) + dut.clock.step() + dut.io.queryValid.expect(false.B) + dut.io.queryCaptured.expect(true.B) + dut.io.responseValid.poke(true.B) + dut.io.responseReady.expect(true.B) + dut.clock.step() + dut.io.responseValid.poke(false.B) + + var accepted = false + var completed = false + var lineData = BigInt(0) + for (_ <- 0 until 6) { + accepted ||= dut.io.resultAccepted.peek().litToBoolean + if (dut.io.rowDataComplete.peek().litToBoolean) { + completed = true + lineData = dut.io.rowLineData.peek().litValue + } + dut.clock.step() + } + assert(accepted, "the exact retained STQ E4 result must reach LIQ") + assert(completed, "the accepted result must complete the canonical row") + assert(lineData == BigInt("8877665544332211", 16)) + dut.io.protocolError.expect(false.B) + } + + withClue("hard recovery: ") { + resetHarness() + allocateAndLaunch() + dut.io.queryValid.expect(true.B) + dut.io.pathEmpty.expect(false.B) + dut.io.flush.poke(true.B) + dut.clock.step() + dut.io.flush.poke(false.B) + dut.io.queryValid.expect(false.B) + dut.io.resultPending.expect(false.B) + dut.io.pathEmpty.expect(true.B) + dut.io.protocolError.expect(false.B) + } + + withClue("precise recovery retained query: ") { + resetHarness() + allocateAndLaunch() + dut.io.queryValid.expect(true.B) + dut.io.preciseFlush.poke(true.B) + dut.io.queryValid.expect(false.B) + dut.io.pathEmpty.expect(false.B) + dut.clock.step() + dut.io.preciseFlush.poke(false.B) + dut.io.queryValid.expect(true.B) + dut.io.queryLoadId.valid.expect(true.B) + dut.io.queryAttempt.generation.expect(7.U) + dut.io.queryReady.poke(true.B) + dut.clock.step() + dut.io.queryValid.expect(false.B) + dut.io.protocolError.expect(false.B) + } + + withClue("precise recovery retained E4: ") { + resetHarness(queryReady = true) + allocateAndLaunch() + dut.clock.step() + dut.io.queryCaptured.expect(true.B) + dut.io.responseValid.poke(true.B) + dut.io.responseReady.expect(true.B) + dut.clock.step() + dut.io.responseValid.poke(false.B) + dut.clock.step() + dut.io.preciseFlush.poke(true.B) + dut.io.pathEmpty.expect(false.B) + dut.clock.step() + dut.io.preciseFlush.poke(false.B) + + var accepted = false + var completed = false + for (_ <- 0 until 8) { + accepted ||= dut.io.resultAccepted.peek().litToBoolean + completed ||= dut.io.rowDataComplete.peek().litToBoolean + dut.clock.step() + } + assert(accepted, "surviving E4 must be retained until LIQ can revalidate it") + assert(completed, "post-recovery exact apply must complete the surviving row") + dut.io.protocolError.expect(false.B) + } + + withClue("unrepresentable native BID: ") { + resetHarness(nativeBid = 13, queryReady = true) + dut.io.allocValid.poke(true.B) + dut.io.allocAccepted.expect(true.B) + dut.clock.step() + dut.io.allocValid.poke(false.B) + dut.io.launchValid.poke(true.B) + dut.io.launchAccepted.expect(false.B) + dut.io.queryValid.expect(false.B) + dut.io.protocolError.expect(true.B) + dut.clock.step() + dut.io.queryValid.expect(false.B) + } + } + } +} diff --git a/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadPathSpec.scala index cdb7a09d..b1d0ea6c 100644 --- a/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadPathSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/ScalarLSULoadPathSpec.scala @@ -157,6 +157,38 @@ class ScalarLSULoadPathSpec extends AnyFunSuite { assert(sv.contains("module LoadMissQueue")) } + test("scalar load path elaborates two canonical STQ result lanes without the compatibility CAM") { + val lsu = ScalarLsuParams( + stqEntries = 8, + commitQueueEntries = 4, + commitIssueWidth = 1, + scbEntries = 4, + liqEntries = 4, + loadMissQueueEntries = 2, + resolveQueueEntries = 8, + loadReturnQueueEntries = 2, + loadReturnPipeCount = 2, + mapQDepth = 8 + ) + val sv = ChiselStage.emitSystemVerilog(new ScalarLSULoadPath( + CoreParams(robEntries = 8, lsidWidth = 40, scalarLsu = lsu), + useExternalStqForwarding = true, + stqForwardRobEntries = 8, + stqForwardTokenWidth = 40)) + + assert(sv.contains("module STQLoadForwardResultPipeline")) + assert(sv.contains("module LoadForwardResultRetainer")) + assert(sv.contains("module LoadSourceLineMerge")) + assert(!sv.contains("module LoadForwardPipeline")) + assert(!sv.contains("module LoadStoreForwarding")) + assert(sv.contains("stqForward_queries_1_valid")) + assert(sv.contains("stqForward_responses_1_valid")) + assert(!sv.contains("stqForward_queries_2_valid")) + assert(sv.contains("stqForward_hardBlock_valid")) + assert(sv.contains("stqForward_resultPending")) + assert(sv.contains("stqForward_protocolError")) + } + test("load-return launch credit is reserved independently per STID and pipe") { val depth = 2 val lanes = Array.fill(4)((0, 0)) // resident, reserved diff --git a/chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala b/chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala index 156a2579..6c1d4d66 100644 --- a/chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala +++ b/chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala @@ -1,6 +1,8 @@ package linxcore.lsu import circt.stage.ChiselStage +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim import linxcore.common.{CoreParams, ScalarLsuParams} import org.scalatest.funsuite.AnyFunSuite @@ -39,7 +41,7 @@ object ScalarLSUMDBPathReference { } } -class ScalarLSUMDBPathSpec extends AnyFunSuite { +class ScalarLSUMDBPathSpec extends AnyFunSuite with ChiselSim { import ScalarLSUMDBPathReference._ private val lsu = ScalarLsuParams( @@ -88,6 +90,39 @@ class ScalarLSUMDBPathSpec extends AnyFunSuite { assert(consumed == RecoveryState(pending = false, None)) } + test("a presented but uncommitted store candidate may wait without protocol error") { + simulate(new ScalarLSUMDBPathProbe) { dut => + dut.io.flush.poke(false.B) + dut.io.loadValid.poke(false.B) + dut.io.loadResolved.poke(false.B) + dut.io.loadBid.poke(0.U) + dut.io.loadLsId.poke(0.U) + dut.io.loadPc.poke(0.U) + dut.io.loadAddr.poke(0.U) + dut.io.loadSize.poke(0.U) + dut.io.loadWaitStore.poke(false.B) + dut.io.storeProbeValid.poke(false.B) + dut.io.storeAddrOnly.poke(false.B) + dut.io.storeBid.poke(0.U) + dut.io.storeLsId.poke(0.U) + dut.io.storePc.poke(0.U) + dut.io.storeAddr.poke(0.U) + dut.io.storeSize.poke(0.U) + dut.io.lookupValid.poke(false.B) + dut.io.mutationAccepted.poke(false.B) + dut.io.recoveryReady.poke(false.B) + dut.io.integratedAllocValid.poke(false.B) + dut.io.integratedTrainValid.poke(false.B) + dut.io.integratedSeedWaitValid.poke(false.B) + dut.io.flush.poke(true.B) + dut.io.storeProbeValid.poke(true.B) + dut.io.storeProbeReady.expect(false.B) + dut.io.protocolError.expect(false.B) + dut.clock.step(2) + dut.io.protocolError.expect(false.B) + } + } + test("MDB conflict, queue, wait, and recovery payloads retain configured full LSID width") { val wideCore = core.copy(lsidWidth = 40) val io = new ScalarLSUMDBPathIO(wideCore, lsu) diff --git a/chisel/src/test/scala/linxcore/lsu/ScalarLSUSpec.scala b/chisel/src/test/scala/linxcore/lsu/ScalarLSUSpec.scala deleted file mode 100644 index 5640e25e..00000000 --- a/chisel/src/test/scala/linxcore/lsu/ScalarLSUSpec.scala +++ /dev/null @@ -1,132 +0,0 @@ -package linxcore.lsu - -import circt.stage.ChiselStage -import linxcore.common.{CoreParams, ScalarLsuParams} -import org.scalatest.funsuite.AnyFunSuite - -class ScalarLSUSpec extends AnyFunSuite { - test("scalar LSU sizing separates ROB identity from store capacity") { - val lsu = ScalarLsuParams( - stqEntries = 8, - commitQueueEntries = 4, - commitIssueWidth = 1, - scbEntries = 4, - scbResponseBufferDepth = 2, - stidCount = 2, - liqEntries = 4, - loadMissQueueEntries = 2, - loadRefillQueueEntries = 4, - resolveQueueEntries = 8, - loadReturnQueueEntries = 2, - loadReturnPipeCount = 3, - mapQDepth = 8 - ) - val core = CoreParams(robEntries = 32, commitWidth = 2, scalarLsu = lsu) - - assert(core.robEntries == 32) - assert(core.scalarLsu.stqEntries == 8) - assert(core.scalarLsu.commitQueueEntries == 4) - assert(core.scalarLsu.mdbRecoveryQueueEntries == 8) - assert(core.scalarLsu.loadMissQueueEntries == 2) - assert(core.scalarLsu.loadRefillQueueEntries == 4) - assert(core.scalarLsu.stidCount == 2) - } - - test("Chisel ScalarLSU owns the parameterized STQ-to-SCB store path") { - val lsu = ScalarLsuParams( - stqEntries = 8, - commitQueueEntries = 4, - commitIssueWidth = 1, - scbEntries = 4, - scbResponseBufferDepth = 2, - stidCount = 2, - liqEntries = 4, - loadMissQueueEntries = 2, - resolveQueueEntries = 8, - loadReturnQueueEntries = 2, - loadReturnPipeCount = 3, - mapQDepth = 8 - ) - val sv = ChiselStage.emitSystemVerilog( - new ScalarLSU(CoreParams(robEntries = 32, commitWidth = 2, scalarLsu = lsu)) - ) - - assert(sv.contains("module ScalarLSU")) - assert(sv.contains("module STQSCBCommitPath")) - assert(sv.contains("module STQEntryBank")) - assert(sv.contains("module STQCommitDrain")) - assert(sv.contains("module SCBRowBank")) - assert(sv.contains("module ScalarLSULoadPath")) - assert(sv.contains("module LoadInflightQueue")) - assert(sv.contains("module LoadMissQueue")) - assert(sv.contains("module LoadRefillTransport")) - assert(sv.contains("module LoadResolveQueue")) - assert(sv.contains("module ScalarLSUMDBPath")) - assert(sv.contains("module ScalarLSULoadReturnQueueBank")) - assert(sv.contains("module MDBConflictDetect")) - assert(sv.contains("module MDBQueueFanout")) - assert(sv.contains("module MDBSSIT")) - assert("""(?s)module ScalarLSU\(.*?input\s+\[4:0\]\s+io_store_flush_req_bid_value""".r.findFirstIn(sv).nonEmpty) - assert(sv.contains("io_store_stqRows_7_valid")) - assert(sv.contains("io_load_liqRows_3_valid")) - assert(sv.contains("io_load_resolveEntries_7_valid")) - assert(sv.contains("io_load_mdbConflictFlush_req_valid")) - assert(sv.contains("module ScalarLSURecoverySource")) - assert(sv.contains("module ScalarLSURecoveryBoundary")) - assert(sv.contains("module RecoveryEligibilityControl")) - assert(sv.contains("module RingFullBidRecoveryBridge")) - assert(!sv.contains("module RecoveryCleanupControl")) - assert(sv.contains("io_recovery_fullBidLookupRequest_rid_value")) - assert(sv.contains("io_recovery_sourceBlockedByLookupMiss")) - assert(sv.contains("io_recovery_sourceEligible")) - assert(sv.contains("io_recovery_source_blockBid")) - assert(sv.contains("io_recovery_sourceReady")) - assert(sv.contains("io_recovery_oldestValid_1")) - assert(sv.contains("io_recovery_sourceStidInRange")) - assert(sv.contains("io_load_mdbSsitValidMask")) - assert(sv.contains("io_load_loadReturn_robLookupValid")) - assert(sv.contains("io_load_loadReturn_resolveReady")) - assert(sv.contains("io_load_loadReturn_completionSelectedPipe")) - assert(sv.contains("io_load_loadReturn_resolveFire")) - assert(sv.contains("io_load_loadReturn_w1ValidMask")) - assert(sv.contains("io_load_loadReturn_w2ValidMask")) - assert(sv.contains("io_load_loadReturn_laneCounts_5")) - assert(sv.contains("io_load_loadReturn_publicationAccepted")) - assert(sv.contains("io_load_missRequest_missId_wrap")) - assert(sv.contains("io_load_missQueueProtocolError")) - assert(sv.contains("io_load_refillReady")) - assert(sv.contains("io_load_refillTransportDualIngress")) - assert(sv.contains("scbRespDecodedUpgrade")) - assert(sv.contains("grantWriteValid")) - assert(!sv.contains("io_load_scbDCacheLookupValid")) - assert(!sv.contains("io_load_scbDCacheUpdate")) - } - - test("ScalarLSURecoverySource elaborates exact promotion without local cleanup arbitration") { - val sv = ChiselStage.emitSystemVerilog(new ScalarLSURecoverySource(entries = 8, bidWidth = 16)) - - assert(sv.contains("module ScalarLSURecoverySource")) - assert(sv.contains("module RecoveryEligibilityControl")) - assert(sv.contains("module RingFullBidRecoveryBridge")) - assert(!sv.contains("module RecoveryCleanupControl")) - assert(sv.contains("io_fullBidLookupRequest_rid_value")) - assert(sv.contains("io_source_blockBid")) - assert(sv.contains("io_sourceReady")) - assert(sv.contains("io_blockedByStaleLookup")) - } - - test("ScalarLSURecoveryBoundary selects an STID-local watermark before exact promotion") { - val sv = ChiselStage.emitSystemVerilog(new ScalarLSURecoveryBoundary( - entries = 8, - stidCount = 2, - bidWidth = 16, - stidWidth = 2 - )) - - assert(sv.contains("module ScalarLSURecoveryBoundary")) - assert(sv.contains("module ScalarLSURecoverySource")) - assert(sv.contains("io_oldestValid_1")) - assert(sv.contains("io_stidInRange")) - assert(sv.contains("io_fullBidLookupRequest_rid_value")) - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/CTUOOOIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/CTUOOOIntegrationSpec.scala new file mode 100644 index 00000000..8e7f062c --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/CTUOOOIntegrationSpec.scala @@ -0,0 +1,183 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util.Decoupled +import linxcore.ctu.CTU +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface.{D2AdmissionGroup, FetchedPacket, + FrontEndOpKind, RecoveryTargetIO} +import org.scalatest.funsuite.AnyFunSuite + +private class CTUOOOHarnessIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new FetchedPacket(p))) + val d2 = Decoupled(new D2AdmissionGroup(p)) +} + +private class CTUOOOHarness(val p: CoreParams) extends Module { + val io = IO(new CTUOOOHarnessIO(p)) + val ctu = Module(new CTU(p)) + val ooo = Module(new OOOD1D2Stage(p)) + ctu.io.fromIfu <> io.in + ooo.io.fromCtu <> ctu.io.toOoo + io.d2 <> ooo.io.d2 + ctu.io.trace.ready := true.B + ooo.io.ridTailSlot.foreach(_ := 0.U) + ooo.io.ridTailGeneration.foreach(_ := 0.U) + + private def idleRecovery(target: RecoveryTargetIO): Unit = { + target.prepare.valid := false.B + target.prepare.bits := 0.U.asTypeOf(target.prepare.bits) + target.prepared.ready := true.B + target.apply.valid := false.B + target.apply.bits := 0.U.asTypeOf(target.apply.bits) + target.abort.valid := false.B + target.abort.bits := 0.U.asTypeOf(target.abort.bits) + } + idleRecovery(ctu.io.recovery) + idleRecovery(ooo.io.recovery) +} + +class CTUOOOIntegrationSpec extends AnyFunSuite with ChiselSim { + private def rule(symbol: String): OooOpcodeRecipeTable.Rule = + OooOpcodeRecipeTable.Rules.find(_.symbol == symbol).get + + private def clear(dut: CTUOOOHarness): Unit = { + dut.io.in.valid.poke(false.B) + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.d2.ready.poke(false.B) + } + + private def send(dut: CTUOOOHarness, raw: BigInt, len: Int, id: Int): Unit = { + sendPacket(dut, Seq((raw, len, id))) + } + + private def sendPacket( + dut: CTUOOOHarness, + instructions: Seq[(BigInt, Int, Int)]): Unit = { + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.in.bits.count.poke(instructions.size.U) + instructions.zipWithIndex.foreach { case ((raw, len, id), lane) => + val entry = dut.io.in.bits.entries(lane) + entry.identity.peId.poke(1.U) + entry.identity.stid.poke(0.U) + entry.identity.instructionId.poke(id.U) + entry.identity.epoch.poke(4.U) + entry.pc.poke((0x1000 + lane * 8).U) + entry.instruction.poke(raw.U) + entry.lengthBytes.poke(len.U) + entry.prediction.valid.poke(true.B) + entry.prediction.transactionId.poke((0x500 + id).U) + entry.prediction.epoch.poke(4.U) + } + dut.io.in.valid.poke(true.B) + var cycles = 0 + while (!dut.io.in.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.in.valid.poke(false.B) + } + + private def waitD2(dut: CTUOOOHarness): Unit = { + var cycles = 0 + while (!dut.io.d2.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64) + } + + test("ordinary encoded traffic survives CTU and OOO backpressure exactly once") { + simulate(new CTUOOOHarness(ParamProfiles.W4)) { dut => + clear(dut) + send(dut, rule("OP_ADD").value, rule("OP_ADD").lenBytes, 41) + waitD2(dut) + dut.io.d2.bits.count.expect(1.U) + dut.io.d2.bits.entries(0).uop.opcode.expect(rule("OP_ADD").opcode.U) + dut.io.d2.bits.entries(0).uop.instruction.parent.identity.instructionId + .expect(41.U) + val heldId = dut.io.d2.bits.entries(0).uop.instruction.parent.identity + .instructionId.peek().litValue + val heldOpcode = dut.io.d2.bits.entries(0).uop.opcode.peek().litValue + dut.clock.step(4) + dut.io.d2.bits.entries(0).uop.instruction.parent.identity.instructionId + .expect(heldId.U) + dut.io.d2.bits.entries(0).uop.opcode.expect(heldOpcode.U) + dut.io.d2.ready.poke(true.B) + dut.clock.step() + dut.io.d2.valid.expect(false.B) + } + } + + test("CTU template expansion reaches OOO as ordered non-recursive uops") { + simulate(new CTUOOOHarness(ParamProfiles.W4)) { dut => + clear(dut) + val fentry = rule("OP_FENTRY").value | + (BigInt(2) << 15) | (BigInt(3) << 20) + send(dut, fentry, rule("OP_FENTRY").lenBytes, 77) + dut.io.d2.ready.poke(true.B) + + var seen = 0 + while (seen < 5) { + waitD2(dut) + val count = dut.io.d2.bits.count.peek().litValue.toInt + (0 until count).foreach { lane => + val row = dut.io.d2.bits.entries(lane).uop + row.instruction.parent.identity.instructionId.expect(77.U) + row.instruction.templateOrdinal.expect((seen + lane).U) + row.instruction.templateCount.expect(5.U) + } + seen += count + dut.clock.step() + } + assert(seen == 5) + } + } + + test("a repacked ordinary plus template prefix drains in order after OOO backpressure") { + simulate(new CTUOOOHarness(ParamProfiles.W4)) { dut => + clear(dut) + + // Occupy the per-STID D2 row so CTU's InstructionBuffer must retain and + // repack the following ordinary instruction and expanded template rows. + send(dut, rule("OP_ADD").value, rule("OP_ADD").lenBytes, 5) + waitD2(dut) + + val fentry = rule("OP_FENTRY").value | + (BigInt(2) << 15) | (BigInt(3) << 20) + sendPacket(dut, Seq( + (rule("OP_ADD").value, rule("OP_ADD").lenBytes, 41), + (fentry, rule("OP_FENTRY").lenBytes, 77))) + dut.clock.step(8) + + // Drain the older row, then hold each following row while inspecting it. + dut.io.d2.ready.poke(true.B) + dut.clock.step() + dut.io.d2.ready.poke(false.B) + + val observed = scala.collection.mutable.ArrayBuffer.empty[(BigInt, BigInt, BigInt)] + while (observed.size < 6) { + waitD2(dut) + val count = dut.io.d2.bits.count.peek().litValue.toInt + (0 until count).foreach { lane => + val row = dut.io.d2.bits.entries(lane).uop.instruction + observed += (( + row.parent.identity.instructionId.peek().litValue, + row.kind.peek().litValue, + row.templateOrdinal.peek().litValue)) + } + dut.io.d2.ready.poke(true.B) + dut.clock.step() + dut.io.d2.ready.poke(false.B) + } + + assert(observed.map(_._1) == Seq(41, 77, 77, 77, 77, 77)) + assert(observed.head._2 == FrontEndOpKind.Encoded64.asUInt.litValue) + assert(observed.tail.forall(_._2 == FrontEndOpKind.TemplateUop.asUInt.litValue)) + assert(observed.tail.map(_._3) == Seq(0, 1, 2, 3, 4)) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/CommitControlDebugSpec.scala b/chisel/src/test/scala/linxcore/ooo/CommitControlDebugSpec.scala new file mode 100644 index 00000000..4e28029d --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/CommitControlDebugSpec.scala @@ -0,0 +1,145 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class CommitControlDebugSpec extends AnyFunSuite with ChiselSim { + private val p: CoreParams = { + val base = ParamProfiles.W4 + base.copy(ooo = base.ooo.copy( + stidCount = 2, + stidIdentityEntries = 2, + robGroupsPerStid = 4, + robBankCount = 4, + brobEntriesPerStid = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 64)) + } + + private def clear(dut: CommitControl): Unit = { + dut.io.rob.valid.poke(false.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.residentHeads.foreach(_.poke(0.U.asTypeOf(dut.io.residentHeads.head))) + dut.io.recoveryFence.foreach(_.poke(false.B)) + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.pcBufferCommitReady.poke(true.B) + dut.io.debugRequest.valid.poke(false.B) + dut.io.debugRequest.bits.poke(0.U.asTypeOf(dut.io.debugRequest.bits)) + dut.io.debugResponse.ready.poke(false.B) + dut.io.out.ready.poke(true.B) + dut.io.robNoflushReady.valid.poke(false.B) + dut.io.robNoflushReady.bits.poke(0.U.asTypeOf(dut.io.robNoflushReady.bits)) + dut.io.robNoflush.ready.poke(false.B) + } + + test("one boundary selector orders normal commit, interrupt, synchronous fault, halt, and resume") { + simulate(new CommitControl(p)) { dut => + clear(dut) + + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.stid.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(1.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.valid.expect(false.B) + dut.io.out.bits.commit.count.expect(1.U) + dut.clock.step() + + dut.io.rob.valid.poke(false.B) + dut.clock.step() + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.interruptBoundary.ridSlot.poke(0.U) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).stid.poke(0.U) + dut.io.interrupts(0).cause.poke(7.U) + dut.io.interrupts(0).priority.poke(3.U) + dut.io.interrupts(1).valid.poke(true.B) + dut.io.interrupts(1).stid.poke(1.U) + dut.io.interrupts(1).cause.poke(9.U) + dut.io.interrupts(1).priority.poke(15.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Interrupt) + dut.io.out.bits.trap.cause.expect(7.U) + dut.clock.step() + + dut.io.rob.valid.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.clock.step() + dut.io.debugRequest.valid.poke(true.B) + dut.io.debugRequest.bits.transactionId.poke(0x44.U) + dut.io.debugRequest.bits.command.poke(DebugCommand.Halt) + dut.io.debugRequest.bits.stid.poke(0.U) + dut.io.debugRequest.ready.expect(true.B) + dut.clock.step() + + dut.io.debugRequest.valid.poke(false.B) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.kind.poke(TrapKind.Exception) + dut.io.rob.bits.entries(0).commit.trap.cause.poke(0x21.U) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.interruptBoundary.ridSlot.poke(1.U) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).stid.poke(0.U) + dut.io.interrupts(0).cause.poke(0x12.U) + dut.io.interrupts(0).priority.poke(15.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Exception) + dut.io.out.bits.trap.cause.expect(0x21.U) + dut.clock.step() + + dut.io.rob.valid.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.clock.step() + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.interruptBoundary.ridSlot.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Debug) + dut.io.out.bits.trap.rob.ridSlot.expect(0.U) + dut.clock.step() + + dut.io.rob.valid.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.halted.expect(true.B) + dut.io.debugResponse.valid.expect(true.B) + dut.io.debugResponse.bits.transactionId.expect(0x44.U) + dut.io.debugResponse.bits.accepted.expect(true.B) + dut.io.debugResponse.ready.poke(true.B) + dut.clock.step() + + dut.io.debugResponse.ready.poke(false.B) + dut.io.debugRequest.valid.poke(true.B) + dut.io.debugRequest.bits.transactionId.poke(0x45.U) + dut.io.debugRequest.bits.command.poke(DebugCommand.Resume) + dut.io.debugRequest.bits.stid.poke(0.U) + dut.io.debugRequest.ready.expect(true.B) + dut.clock.step() + dut.io.debugRequest.valid.poke(false.B) + dut.io.halted.expect(false.B) + dut.io.debugResponse.valid.expect(true.B) + dut.io.debugResponse.bits.transactionId.expect(0x45.U) + dut.io.debugResponse.bits.accepted.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOCommitApplyPolicySpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOCommitApplyPolicySpec.scala new file mode 100644 index 00000000..eda53735 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOCommitApplyPolicySpec.scala @@ -0,0 +1,37 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import org.scalatest.funsuite.AnyFunSuite + +private class OOOCommitApplyPolicyProbeIO extends Bundle { + val transactionFire = Input(Bool()) + val commitCount = Input(UInt(4.W)) + val robTransactionApply = Output(Bool()) + val releaseOwnersApply = Output(Bool()) +} + +private class OOOCommitApplyPolicyProbe extends Module { + val io = IO(new OOOCommitApplyPolicyProbeIO) + io.robTransactionApply := io.transactionFire + io.releaseOwnersApply := OOOCommitApplyPolicy.releaseFire( + io.transactionFire, io.commitCount) +} + +class OOOCommitApplyPolicySpec extends AnyFunSuite with ChiselSim { + test("trap-only acceptance applies ROB transaction but no release owner") { + simulate(new OOOCommitApplyPolicyProbe) { dut => + dut.io.transactionFire.poke(true.B) + dut.io.commitCount.poke(0.U) + dut.io.robTransactionApply.expect(true.B) + dut.io.releaseOwnersApply.expect(false.B) + + dut.io.commitCount.poke(1.U) + dut.io.robTransactionApply.expect(true.B) + dut.io.releaseOwnersApply.expect(true.B) + + dut.io.transactionFire.poke(false.B) + dut.io.releaseOwnersApply.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOD3ContinuousPrefixSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOD3ContinuousPrefixSpec.scala new file mode 100644 index 00000000..0c01b46c --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOD3ContinuousPrefixSpec.scala @@ -0,0 +1,342 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +import scala.collection.mutable.ArrayBuffer + +private final case class OOOD3PublishedPrefixLane( + transactionId: BigInt, + instructionId: BigInt, + ridSlot: BigInt, + ridGeneration: BigInt, + firstLsid: BigInt, + ptag: BigInt, + pcBufferIndex: BigInt, + allocationEpoch: BigInt) + +class OOOD3ContinuousPrefixSpec extends AnyFunSuite with ChiselSim { + private def clear(dut: OOOD3S1Graph): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.pcBufferReadAddress.foreach( + _.poke(0.U.asTypeOf(dut.io.iex.pcBufferReadAddress.head))) + dut.io.iex.robNoflushReady.valid.poke(false.B) + dut.io.iex.robNoflushReady.bits.poke( + 0.U.asTypeOf(dut.io.iex.robNoflushReady.bits)) + dut.io.iex.robNoflush.ready.poke(true.B) + dut.io.iex.robResolve.foreach { resolve => + resolve.valid.poke(false.B) + resolve.bits.poke(0.U.asTypeOf(resolve.bits)) + } + dut.io.iex.recoveryEvent.valid.poke(false.B) + dut.io.iex.recoveryEvent.bits.poke( + 0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.commit.ready.poke(false.B) + dut.io.trap.ready.poke(true.B) + dut.io.interrupt.valid.poke(false.B) + dut.io.interrupt.bits.poke(0.U.asTypeOf(dut.io.interrupt.bits)) + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + dut.io.trace.ready.poke(true.B) + } + + private def pokeLoadGroups( + dut: OOOD3S1Graph, + count: Int, + ridSlot: Int, + ridGeneration: Int, + instructionBase: Int, + pcBase: Long): Unit = { + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(count.U) + dut.io.fromD2.bits.groupCount.poke(count.U) + for (lane <- 0 until count) { + val absoluteRid = ridSlot + lane + val laneRidSlot = absoluteRid % dut.p.ooo.robGroupsPerStid + val laneRidGeneration = + ridGeneration + absoluteRid / dut.p.ooo.robGroupsPerStid + val group = dut.io.fromD2.bits.groups(lane) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(laneRidSlot.U) + group.ridGeneration.poke(laneRidGeneration.U) + + val uop = dut.io.fromD2.bits.entries(lane).uop + uop.valid.poke(true.B) + uop.instruction.parent.identity.peId.poke(1.U) + uop.instruction.parent.identity.stid.poke(0.U) + uop.instruction.parent.identity.instructionId.poke( + (instructionBase + lane).U) + uop.instruction.parent.identity.epoch.poke(1.U) + uop.instruction.parent.pc.poke((pcBase + lane * 0x1000L).U) + uop.instruction.parent.lengthBytes.poke(4.U) + uop.rob.peId.poke(1.U) + uop.rob.stid.poke(0.U) + uop.rob.ridSlot.poke(laneRidSlot.U) + uop.rob.ridGeneration.poke(laneRidGeneration.U) + uop.rob.memberIndex.poke(0.U) + uop.uopClass.poke(UopClass.Agu) + uop.blockStart.poke(true.B) + uop.blockStop.poke(true.B) + // Keep each ROB group and PC base indivisible without turning the load + // into an early-complete boundary uop; every published lane must still + // reach canonical AGU dispatch so identity continuity is observable. + uop.blockBoundary.poke(false.B) + uop.destinations(0).valid.poke(true.B) + uop.destinations(0).kind.poke(OperandKind.Gpr) + uop.destinations(0).atag.poke((lane + 1).U) + uop.memory.valid.poke(true.B) + uop.memory.isLoad.poke(true.B) + uop.memory.requestCount.poke(1.U) + uop.memory.addressMode.poke(MemoryAddressMode.BaseOffset) + uop.memory.accessBytes.poke(8.U) + uop.memory.writebackValid.poke(true.B) + + val classification = uop.classification + classification.valid.poke(true.B) + classification.disposition.poke(OooOpcodeDisposition.Dispatch.U) + classification.kind.poke(OooOpcodeRecipeKind.Single.U) + classification.uopCountMin.poke(1.U) + classification.uopCountMax.poke(1.U) + classification.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) + classification.dispatchClass.poke(OooDispatchClass.Agu.U) + classification.dispatchWrites.poke(1.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress).U) + } + } + + private def pokeLoadPrefix(dut: OOOD3S1Graph): Unit = + pokeLoadGroups(dut, count = 8, ridSlot = 0, ridGeneration = 0, + instructionBase = 0x80, pcBase = 0x1000L) + + private def acceptLoadGroups(dut: OOOD3S1Graph): Unit = { + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + } + + private def collectAguPublications( + dut: OOOD3S1Graph, + count: Int): Seq[OOOD3PublishedPrefixLane] = { + val published = ArrayBuffer.empty[OOOD3PublishedPrefixLane] + var cycles = 0 + while (published.size < count && cycles < 32) { + for (pipe <- 0 until dut.io.iex.aguDispatch.length) { + val dispatch = dut.io.iex.aguDispatch(pipe) + if (dispatch.valid.peek().litToBoolean) { + val bits = dispatch.bits.peek() + assert(bits.uop.destinations(0).ptagValid.litToBoolean) + published += OOOD3PublishedPrefixLane( + bits.transactionId.litValue, + bits.uop.decoded.instruction.parent.identity.instructionId.litValue, + bits.uop.decoded.rob.ridSlot.litValue, + bits.uop.decoded.rob.ridGeneration.litValue, + bits.memoryOrder.firstLsid.litValue, + bits.uop.destinations(0).ptag.litValue, + bits.pcBufferIndexOffset.pcBufferIndex.litValue, + bits.pcBufferIndexOffset.allocationEpoch.litValue, + ) + } + } + dut.clock.step() + cycles += 1 + } + assert(published.size == count, + s"timed out after ${published.size} of $count AGU publications") + published.toSeq + } + + private def resolve( + dut: OOOD3S1Graph, + ridSlot: Int, + ridGeneration: Int): Unit = { + val completion = dut.io.iex.robResolve(0) + completion.bits.poke(0.U.asTypeOf(completion.bits)) + completion.bits.rob.peId.poke(1.U) + completion.bits.rob.stid.poke(0.U) + completion.bits.rob.ridSlot.poke(ridSlot.U) + completion.bits.rob.ridGeneration.poke(ridGeneration.U) + completion.bits.rob.memberIndex.poke(0.U) + completion.valid.poke(true.B) + completion.ready.expect(true.B) + dut.clock.step() + completion.valid.poke(false.B) + } + + test("W8 publishes one retained D3 transaction as three three two") { + val p = SimulationParamProfiles.W8 + val robCapacity = BigInt(p.ooo.robGroupsPerStid) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + pokeLoadPrefix(dut) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + val acceptedPrefixSizes = ArrayBuffer.empty[BigInt] + val tailTransitions = ArrayBuffer.empty[(BigInt, BigInt)] + val published = ArrayBuffer.empty[OOOD3PublishedPrefixLane] + var previousTail = (BigInt(0), BigInt(0)) + var cycles = 0 + while ((published.size < 8 || previousTail != (BigInt(0), BigInt(1))) && + cycles < 96) { + for (pipe <- 0 until dut.io.iex.aguDispatch.length) { + val dispatch = dut.io.iex.aguDispatch(pipe) + if (dispatch.valid.peek().litToBoolean) { + val bits = dispatch.bits.peek() + assert(bits.uop.destinations(0).ptagValid.litToBoolean) + published += OOOD3PublishedPrefixLane( + bits.transactionId.litValue, + bits.uop.decoded.instruction.parent.identity.instructionId.litValue, + bits.uop.decoded.rob.ridSlot.litValue, + bits.uop.decoded.rob.ridGeneration.litValue, + bits.memoryOrder.firstLsid.litValue, + bits.uop.destinations(0).ptag.litValue, + bits.pcBufferIndexOffset.pcBufferIndex.litValue, + bits.pcBufferIndexOffset.allocationEpoch.litValue, + ) + } + } + val tail = ( + dut.io.ridTailSlot(0).peek().litValue, + dut.io.ridTailGeneration(0).peek().litValue) + if (tail != previousTail) { + acceptedPrefixSizes += + (tail._2 - previousTail._2) * robCapacity + tail._1 - previousTail._1 + tailTransitions += tail + previousTail = tail + } + dut.clock.step() + cycles += 1 + } + + assert(cycles < 96, + s"retained W8 D3 suffix made no forward progress: " + + s"published=${published.size}, prefixSizes=${acceptedPrefixSizes.mkString(",")}, " + + s"tail=$previousTail, " + + s"transitions=${tailTransitions.mkString(",")}") + assert(acceptedPrefixSizes.toSeq == Seq(BigInt(3), BigInt(3), BigInt(2))) + assert(acceptedPrefixSizes.scanLeft(BigInt(0))(_ + _).tail.toSeq == + Seq(BigInt(3), BigInt(6), BigInt(8))) + assert(tailTransitions.toSeq == Seq( + (BigInt(3), BigInt(0)), + (BigInt(6), BigInt(0)), + (BigInt(0), BigInt(1)))) + assert(published.map(_.transactionId).toSeq == (0 until 8).map(BigInt(_))) + assert(published.map(_.ridSlot).toSeq == (0 until 8).map(BigInt(_))) + assert(published.forall(_.ridGeneration == 0)) + assert(published.map(_.firstLsid).toSeq == (0 until 8).map(BigInt(_))) + assert(published.map(_.ptag).distinct.size == 8) + assert(published.map(_.pcBufferIndex).toSeq == + (0 until 8).map(BigInt(_))) + assert(published.forall(_.allocationEpoch == 0)) + + for (lane <- 0 until 8) { + val address = dut.io.iex.pcBufferReadAddress.head + address.valid.poke(true.B) + address.stid.poke(0.U) + address.pcBufferIndex.poke(lane.U) + address.allocationEpoch.poke(0.U) + dut.io.iex.pcBufferReadPcBase.head.valid.expect(true.B) + dut.io.iex.pcBufferReadPcBase.head.bits.expect( + (0x1000L + lane * 0x1000L).U) + } + dut.io.commit.valid.expect(false.B) + } + } + + test("ROB and BROB capacity limit the oldest feasible complete D3 prefix") { + val base = SimulationParamProfiles.W4 + val p = base.copy(ooo = base.ooo.copy( + pcBufferEntries = 8, + pcBankCount = 4, + )) + assert(p.ooo.robGroupsPerStid == 4) + assert(p.ooo.brobEntriesPerStid == 4) + assert(p.ooo.pcBufferEntries == 8) + assert(p.ooo.pcWritePorts == 3) + + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + + pokeLoadGroups(dut, count = 2, ridSlot = 0, ridGeneration = 0, + instructionBase = 0x10, pcBase = 0x1000L) + acceptLoadGroups(dut) + val resident = collectAguPublications(dut, count = 2) + assert(resident.map(_.transactionId) == Seq(BigInt(0), BigInt(1))) + assert(resident.map(_.ridSlot) == Seq(BigInt(0), BigInt(1))) + assert(resident.forall(_.ridGeneration == 0)) + dut.io.ridTailSlot(0).expect(2.U) + dut.io.ridTailGeneration(0).expect(0.U) + + // Three distinct PC bases fit the PC buffer and its three write ports, + // while the resident pair leaves only two ROB and BROB groups free. + pokeLoadGroups(dut, count = 3, ridSlot = 2, ridGeneration = 0, + instructionBase = 0x20, pcBase = 0x4000L) + acceptLoadGroups(dut) + val oldestFeasible = collectAguPublications(dut, count = 2) + dut.io.ridTailSlot(0).expect(0.U) + dut.io.ridTailGeneration(0).expect(1.U) + assert(oldestFeasible.map(_.transactionId) == + Seq(BigInt(2), BigInt(3))) + assert(oldestFeasible.map(_.instructionId) == + Seq(BigInt(0x20), BigInt(0x21))) + assert(oldestFeasible.map(row => (row.ridSlot, row.ridGeneration)) == + Seq((BigInt(2), BigInt(0)), (BigInt(3), BigInt(0)))) + assert(oldestFeasible.map(_.firstLsid) == Seq(BigInt(2), BigInt(3))) + assert(oldestFeasible.map(_.pcBufferIndex) == Seq(BigInt(2), BigInt(3))) + + resolve(dut, ridSlot = 0, ridGeneration = 0) + var cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32, + "retained same-STID suffix must not block the resident commit that frees its capacity") + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.ridSlot.expect(0.U) + dut.io.commit.ready.poke(true.B) + dut.clock.step() + dut.io.commit.ready.poke(false.B) + + val retriedSuffix = collectAguPublications(dut, count = 1) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.ridTailGeneration(0).expect(1.U) + val published = oldestFeasible ++ retriedSuffix + assert(published.map(_.transactionId) == + Seq(BigInt(2), BigInt(3), BigInt(4))) + assert(published.map(_.instructionId) == + Seq(BigInt(0x20), BigInt(0x21), BigInt(0x22))) + assert(published.map(row => (row.ridSlot, row.ridGeneration)) == Seq( + (BigInt(2), BigInt(0)), + (BigInt(3), BigInt(0)), + (BigInt(0), BigInt(1)))) + assert(published.map(_.firstLsid) == + Seq(BigInt(2), BigInt(3), BigInt(4))) + assert(published.map(_.pcBufferIndex) == + Seq(BigInt(2), BigInt(3), BigInt(4))) + assert(published.map(_.ptag).distinct.size == 3) + assert(published.forall(_.allocationEpoch == 0)) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOD3SameCycleReplacementSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOD3SameCycleReplacementSpec.scala new file mode 100644 index 00000000..da58f5de --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOD3SameCycleReplacementSpec.scala @@ -0,0 +1,230 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class OOOD3SameCycleReplacementSpec extends AnyFunSuite with ChiselSim { + private val p = SimulationParamProfiles.W2 + + private def clear(dut: OOOD3S1Graph): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(false.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.fastResult.ready.poke(true.B) + dut.io.iex.pcBufferReadAddress.foreach( + _.poke(0.U.asTypeOf(dut.io.iex.pcBufferReadAddress.head))) + dut.io.iex.robNoflushReady.valid.poke(false.B) + dut.io.iex.robNoflushReady.bits.poke( + 0.U.asTypeOf(dut.io.iex.robNoflushReady.bits)) + dut.io.iex.robNoflush.ready.poke(true.B) + dut.io.iex.robResolve.foreach { resolve => + resolve.valid.poke(false.B) + resolve.bits.poke(0.U.asTypeOf(resolve.bits)) + } + dut.io.iex.recoveryEvent.valid.poke(false.B) + dut.io.iex.recoveryEvent.bits.poke( + 0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.commit.ready.poke(false.B) + dut.io.trap.ready.poke(true.B) + dut.io.interrupt.valid.poke(false.B) + dut.io.interrupt.bits.poke(0.U.asTypeOf(dut.io.interrupt.bits)) + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + dut.io.trace.ready.poke(true.B) + } + + private def pokeLoad( + dut: OOOD3S1Graph, + instructionId: Int, + ridSlot: Int, + ridGeneration: Int, + atag: Int, + pc: BigInt): Unit = { + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + + val group = dut.io.fromD2.bits.groups(0) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(ridSlot.U) + group.ridGeneration.poke(ridGeneration.U) + + val uop = dut.io.fromD2.bits.entries(0).uop + uop.valid.poke(true.B) + uop.instruction.parent.identity.peId.poke(1.U) + uop.instruction.parent.identity.stid.poke(0.U) + uop.instruction.parent.identity.instructionId.poke(instructionId.U) + uop.instruction.parent.identity.epoch.poke(3.U) + uop.instruction.parent.pc.poke(pc.U) + uop.instruction.parent.lengthBytes.poke(4.U) + uop.rob.peId.poke(1.U) + uop.rob.stid.poke(0.U) + uop.rob.ridSlot.poke(ridSlot.U) + uop.rob.ridGeneration.poke(ridGeneration.U) + uop.rob.memberIndex.poke(0.U) + uop.uopClass.poke(UopClass.Agu) + uop.blockStart.poke(true.B) + uop.blockStop.poke(true.B) + uop.destinations(0).valid.poke(true.B) + uop.destinations(0).kind.poke(OperandKind.Gpr) + uop.destinations(0).atag.poke(atag.U) + uop.memory.valid.poke(true.B) + uop.memory.isLoad.poke(true.B) + uop.memory.requestCount.poke(1.U) + uop.memory.addressMode.poke(MemoryAddressMode.BaseOffset) + uop.memory.accessBytes.poke(8.U) + uop.memory.writebackValid.poke(true.B) + + val classification = uop.classification + classification.valid.poke(true.B) + classification.disposition.poke(OooOpcodeDisposition.Dispatch.U) + classification.kind.poke(OooOpcodeRecipeKind.Single.U) + classification.uopCountMin.poke(1.U) + classification.uopCountMax.poke(1.U) + classification.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) + classification.dispatchClass.poke(OooDispatchClass.Agu.U) + classification.dispatchWrites.poke(1.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.executionPipeCapability( + OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask( + OooIexDomainCapability.LoadAddress).U) + } + + private def expectRob( + target: RobIdentity, + ridSlot: Int, + ridGeneration: Int): Unit = { + target.peId.expect(1.U) + target.stid.expect(0.U) + target.ridSlot.expect(ridSlot.U) + target.ridGeneration.expect(ridGeneration.U) + target.memberIndex.expect(0.U) + target.residentGeneration.expect(0.U) + target.bid.expect(ridSlot.U) + target.brobGeneration.expect(ridGeneration.U) + } + + test("accepts a same-STID replacement on the final D3 publication edge") { + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + + pokeLoad( + dut, + instructionId = 0x80, + ridSlot = 0, + ridGeneration = 0, + atag = 1, + pc = 0x1000) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + + // The old row is now the complete retained D3 prefix. Present its + // same-STID successor while the old row publishes into blocked AGU + // dispatch. Both transfers must occur on this edge. + pokeLoad( + dut, + instructionId = 0x81, + ridSlot = 1, + ridGeneration = 0, + atag = 2, + pc = 0x2000) + dut.io.fromD2.valid.poke(true.B) + dut.io.iex.allocationClear(0).valid.expect(true.B) + expectRob( + dut.io.iex.allocationClear(0).bits.rob, + ridSlot = 0, + ridGeneration = 0) + dut.io.iex.allocationClear(0).bits.destination.ptagValid.expect(true.B) + val oldAllocatedPtag = + dut.io.iex.allocationClear(0).bits.destination.ptag.peek().litValue + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + dut.io.ridTailSlot(0).expect(1.U) + dut.io.ridTailGeneration(0).expect(0.U) + dut.io.iex.aguDispatch(0).valid.expect(true.B) + val oldLive = dut.io.iex.aguDispatch(0).bits + oldLive.uop.decoded.instruction.parent.identity.instructionId + .expect(0x80.U) + oldLive.transactionId.expect(0.U) + expectRob(oldLive.uop.decoded.rob, ridSlot = 0, ridGeneration = 0) + oldLive.uop.destinations(0).ptagValid.expect(true.B) + oldLive.uop.destinations(0).ptag.expect(oldAllocatedPtag.U) + oldLive.memoryOrder.requestCount.expect(1.U) + oldLive.memoryOrder.firstLsid.expect(0.U) + oldLive.memoryOrder.firstLid.expect(0.U) + oldLive.memoryOrder.firstSid.expect(0.U) + oldLive.memoryOrder.yostValid.expect(false.B) + oldLive.memoryOrder.yoldValid.expect(false.B) + val oldDispatch = dut.io.iex.aguDispatch(0).bits.peek() + + dut.clock.step(2) + dut.io.iex.aguDispatch(0).valid.expect(true.B) + dut.io.iex.aguDispatch(0).bits.expect(oldDispatch) + dut.io.iex.allocationClear.foreach(_.valid.expect(false.B)) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.ridTailGeneration(0).expect(0.U) + + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.io.iex.allocationClear(0).valid.expect(true.B) + expectRob( + dut.io.iex.allocationClear(0).bits.rob, + ridSlot = 1, + ridGeneration = 0) + dut.io.iex.allocationClear(0).bits.destination.ptagValid.expect(true.B) + val newAllocatedPtag = + dut.io.iex.allocationClear(0).bits.destination.ptag.peek().litValue + assert(newAllocatedPtag != oldAllocatedPtag, + "same-cycle replacement reused the still-live physical destination") + assert(newAllocatedPtag == oldAllocatedPtag + 1, + "same-cycle replacement transiently released or skipped its reservation") + dut.clock.step() + dut.io.iex.aguDispatch(0).ready.poke(false.B) + + dut.io.ridTailSlot(0).expect(0.U) + dut.io.ridTailGeneration(0).expect(1.U) + dut.io.iex.aguDispatch(0).valid.expect(true.B) + val newDispatch = dut.io.iex.aguDispatch(0).bits + newDispatch.uop.decoded.instruction.parent.identity.instructionId + .expect(0x81.U) + newDispatch.transactionId.expect(1.U) + expectRob(newDispatch.uop.decoded.rob, ridSlot = 1, ridGeneration = 0) + newDispatch.uop.destinations(0).ptagValid.expect(true.B) + newDispatch.uop.destinations(0).ptag.expect(newAllocatedPtag.U) + newDispatch.memoryOrder.requestCount.expect(1.U) + newDispatch.memoryOrder.firstLsid.expect(1.U) + newDispatch.memoryOrder.firstLid.expect(1.U) + newDispatch.memoryOrder.firstSid.expect(0.U) + newDispatch.memoryOrder.yostValid.expect(false.B) + newDispatch.memoryOrder.yoldValid.expect(true.B) + newDispatch.memoryOrder.yoldLsid.expect(0.U) + newDispatch.memoryOrder.yoldLid.expect(0.U) + + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + dut.io.iex.aguDispatch.foreach(_.valid.expect(false.B)) + dut.io.iex.allocationClear.foreach(_.valid.expect(false.B)) + dut.io.commit.valid.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOODecodeSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOODecodeSpec.scala new file mode 100644 index 00000000..a0ce3ef4 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOODecodeSpec.scala @@ -0,0 +1,414 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.common.TemplateRowKind +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface.{FrontEndOpKind, OperandKind, RecoveryCause, + RecoveryPhase, UopClass} +import org.scalatest.funsuite.AnyFunSuite + +class OOODecodeSpec extends AnyFunSuite with ChiselSim { + private def rule(symbol: String): OooOpcodeRecipeTable.Rule = + OooOpcodeRecipeTable.Rules.find(_.symbol == symbol).getOrElse( + fail(s"missing generated recipe for $symbol")) + + private def clearDec(dut: DEC): Unit = { + dut.io.in.valid.poke(false.B) + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.out.ready.poke(true.B) + } + + private def clearOoo(dut: OOOD1D2Stage): Unit = { + dut.io.fromCtu.valid.poke(false.B) + dut.io.fromCtu.bits.poke(0.U.asTypeOf(dut.io.fromCtu.bits)) + dut.io.d2.ready.poke(true.B) + dut.io.ridTailSlot.foreach(_.poke(0.U)) + dut.io.ridTailGeneration.foreach(_.poke(0.U)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def pokeEncoded( + packet: linxcore.top.interface.D1Packet, + lane: Int, + symbol: String, + instructionId: Int, + stid: Int = 0, + epoch: Int = 1, + rawOverride: Option[BigInt] = None): Unit = { + val entry = packet.entries(lane) + val selected = rule(symbol) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(3.U) + entry.parent.identity.stid.poke(stid.U) + entry.parent.identity.instructionId.poke(instructionId.U) + entry.parent.identity.epoch.poke(epoch.U) + entry.parent.pc.poke((0x1000 + lane * 8).U) + entry.parent.instruction.poke(rawOverride.getOrElse(selected.value).U) + entry.parent.lengthBytes.poke(selected.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.predictionTag.poke((0x100 + lane).U) + entry.parent.prediction.transactionId.poke((0x200 + lane).U) + entry.parent.prediction.checkpointId.poke((lane + 1).U) + entry.parent.prediction.requestPc.poke((0x1000 + lane * 8).U) + entry.parent.prediction.taken.poke((lane == 1).B) + entry.parent.prediction.target.poke((0x4000 + lane * 8).U) + entry.parent.prediction.fallthroughPc.poke( + (0x1000 + lane * 8 + selected.lenBytes).U) + entry.parent.prediction.provider.poke(2.U) + entry.parent.prediction.confidence.poke(3.U) + entry.parent.prediction.epoch.poke(epoch.U) + } + + test("normalizes 16 32 48 and 64-bit containers without losing decode metadata") { + simulate(new DEC(ParamProfiles.W4)) { dut => + clearDec(dut) + dut.io.in.bits.count.poke(4.U) + Seq("OP_C_SETRET", "OP_ADD", "OP_LD", "OP_V_ADD") + .zipWithIndex.foreach { case (symbol, lane) => + pokeEncoded(dut.io.in.bits, lane, symbol, 10 + lane) + } + dut.io.in.valid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.count.expect(4.U) + Seq("OP_C_SETRET", "OP_ADD", "OP_LD", "OP_V_ADD") + .zipWithIndex.foreach { case (symbol, lane) => + val decoded = dut.io.out.bits.entries(lane) + decoded.uop.opcode.expect(rule(symbol).opcode.U) + decoded.uop.instruction.parent.lengthBytes + .expect(rule(symbol).lenBytes.U) + decoded.uop.instruction.parent.identity.instructionId + .expect((10 + lane).U) + decoded.uop.instruction.parent.prediction.predictionTag + .expect((0x100 + lane).U) + decoded.trap.valid.expect(false.B) + } + dut.io.out.bits.entries(1).uop.uopClass.expect(UopClass.Alu) + val encodedLoad = dut.io.out.bits.entries(2).uop.memory + encodedLoad.valid.expect(true.B) + encodedLoad.isLoad.expect(true.B) + encodedLoad.requestCount.expect(rule("OP_LD").memoryRequestCount.U) + } + } + + test("classifies a standalone pure stop marker as early-complete boundary metadata") { + simulate(new DEC(ParamProfiles.W4)) { dut => + clearDec(dut) + dut.io.in.bits.count.poke(1.U) + pokeEncoded(dut.io.in.bits, 0, "OP_BSTOP", 90, epoch = 2) + dut.io.in.valid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.count.expect(1.U) + val decoded = dut.io.out.bits.entries.head + decoded.trap.valid.expect(false.B) + decoded.uop.uopClass.expect(UopClass.Boundary) + decoded.uop.blockStart.expect(false.B) + decoded.uop.blockStop.expect(true.B) + decoded.uop.blockBoundary.expect(true.B) + decoded.uop.earlyComplete.expect(true.B) + } + } + + test("bypasses encoded decode for one CTU template child") { + simulate(new DEC(ParamProfiles.W4)) { dut => + clearDec(dut) + val op = dut.io.in.bits.entries(0) + dut.io.in.bits.count.poke(1.U) + op.kind.poke(FrontEndOpKind.TemplateUop) + op.parent.identity.peId.poke(3.U) + op.parent.identity.stid.poke(0.U) + op.parent.identity.instructionId.poke(91.U) + op.parent.identity.epoch.poke(7.U) + op.parent.pc.poke(0x8000.U) + op.parent.instruction.poke(rule("OP_FENTRY").value.U) + op.parent.lengthBytes.poke(rule("OP_FENTRY").lenBytes.U) + op.parent.prediction.valid.poke(true.B) + op.parent.prediction.transactionId.poke(0x1234.U) + op.templateOrdinal.poke(2.U) + op.templateCount.poke(9.U) + op.templateOpcode.poke(TemplateRowKind.STORE.asUInt) + op.templateRegister.poke(23.U) + op.templateImmediate.poke(248.U) + dut.io.in.valid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.count.expect(1.U) + val decoded = dut.io.out.bits.entries(0) + decoded.uop.instruction.kind.expect(FrontEndOpKind.TemplateUop) + decoded.uop.instruction.templateOrdinal.expect(2.U) + decoded.uop.instruction.templateCount.expect(9.U) + decoded.uop.opcode.expect(rule("OP_SDI").opcode.U) + decoded.uop.uopClass.expect(UopClass.Std) + decoded.uop.sources(0).valid.expect(true.B) + decoded.uop.sources(0).kind.expect(OperandKind.Gpr) + decoded.uop.sources(0).atag.expect(23.U) + decoded.uop.sources(1).valid.expect(true.B) + decoded.uop.sources(1).kind.expect(OperandKind.Gpr) + decoded.uop.sources(1).atag.expect(1.U) + decoded.uop.classification.pSourceCount.expect(2.U) + decoded.uop.classification.pDestinationCount.expect(0.U) + decoded.uop.memory.valid.expect(true.B) + decoded.uop.memory.isStore.expect(true.B) + decoded.uop.memory.requestCount.expect(1.U) + decoded.uop.immediateValid.expect(true.B) + decoded.uop.immediate.expect(248.U) + decoded.uop.memory.offset.expect(248.U) + decoded.uop.instruction.parent.identity.instructionId.expect(91.U) + decoded.uop.instruction.parent.prediction.transactionId.expect(0x1234.U) + decoded.trap.valid.expect(false.B) + } + } + + test("turns a fetch-faulted template child into the same typed trap intent") { + simulate(new DEC(ParamProfiles.W2)) { dut => + clearDec(dut) + val op = dut.io.in.bits.entries(0) + dut.io.in.bits.count.poke(1.U) + op.kind.poke(FrontEndOpKind.TemplateUop) + op.parent.identity.peId.poke(3.U) + op.parent.identity.stid.poke(0.U) + op.parent.identity.instructionId.poke(92.U) + op.parent.identity.epoch.poke(0x8004.U) + op.parent.fetchFault.poke(true.B) + op.parent.fetchFaultCause.poke(0x12345678.U) + op.templateOrdinal.poke(0.U) + op.templateCount.poke(1.U) + op.templateOpcode.poke(TemplateRowKind.VFORM.asUInt) + dut.io.in.valid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.entries(0).trap.valid.expect(true.B) + dut.io.out.bits.entries(0).trap.cause.expect(0x12345678.U) + dut.io.out.bits.entries(0).uop.earlyComplete.expect(true.B) + dut.io.out.bits.entries(0).uop.instruction.parent.identity.epoch + .expect(0x8004.U) + } + } + + test("VFORM_rob_only completes without consuming an issue queue") { + simulate(new DEC(ParamProfiles.W2)) { dut => + clearDec(dut) + val op = dut.io.in.bits.entries(0) + dut.io.in.bits.count.poke(1.U) + op.kind.poke(FrontEndOpKind.TemplateUop) + op.parent.identity.peId.poke(3.U) + op.parent.identity.stid.poke(0.U) + op.parent.identity.instructionId.poke(93.U) + op.parent.identity.epoch.poke(4.U) + op.templateOrdinal.poke(0.U) + op.templateCount.poke(5.U) + op.templateOpcode.poke(TemplateRowKind.VFORM.asUInt) + dut.io.in.valid.poke(true.B) + + val decoded = dut.io.out.bits.entries(0).uop + decoded.uopClass.expect(UopClass.System) + decoded.blockStart.expect(true.B) + decoded.earlyComplete.expect(true.B) + decoded.classification.disposition.expect( + OooOpcodeDisposition.FastResolve.U) + decoded.classification.dispatchWrites.expect(0.U) + decoded.classification.dispatchDemand.foreach(_.expect(0.U)) + } + } + + test("SP_SUB carries an exact scalar SP source and destination") { + simulate(new DEC(ParamProfiles.W2)) { dut => + clearDec(dut) + val op = dut.io.in.bits.entries(0) + dut.io.in.bits.count.poke(1.U) + op.kind.poke(FrontEndOpKind.TemplateUop) + op.parent.identity.peId.poke(3.U) + op.parent.identity.stid.poke(0.U) + op.parent.identity.instructionId.poke(94.U) + op.parent.identity.epoch.poke(4.U) + op.templateOrdinal.poke(1.U) + op.templateCount.poke(5.U) + op.templateOpcode.poke(TemplateRowKind.SP_SUB.asUInt) + op.templateImmediate.poke(64.U) + dut.io.in.valid.poke(true.B) + + val decoded = dut.io.out.bits.entries(0).uop + decoded.uopClass.expect(UopClass.Alu) + decoded.opcode.expect(rule("OP_SUBI").opcode.U) + decoded.sources(0).valid.expect(true.B) + decoded.sources(0).kind.expect(OperandKind.Gpr) + decoded.sources(0).atag.expect(1.U) + decoded.destinations(0).valid.expect(true.B) + decoded.destinations(0).kind.expect(OperandKind.Gpr) + decoded.destinations(0).atag.expect(1.U) + decoded.classification.pSourceCount.expect(1.U) + decoded.classification.pDestinationCount.expect(1.U) + decoded.classification.dispatchWrites.expect(1.U) + } + } + + test("merges mixed encoded and template lanes without fusing across the tag boundary") { + simulate(new DEC(ParamProfiles.W4)) { dut => + clearDec(dut) + dut.io.in.bits.count.poke(3.U) + pokeEncoded(dut.io.in.bits, 0, "OP_BSTART_FALL", 20) + val template = dut.io.in.bits.entries(1) + template.kind.poke(FrontEndOpKind.TemplateUop) + template.parent.identity.peId.poke(3.U) + template.parent.identity.stid.poke(0.U) + template.parent.identity.instructionId.poke(21.U) + template.parent.identity.epoch.poke(1.U) + template.templateOrdinal.poke(0.U) + template.templateCount.poke(1.U) + template.templateOpcode.poke(TemplateRowKind.VFORM.asUInt) + pokeEncoded(dut.io.in.bits, 2, "OP_ADD", 22) + dut.io.in.valid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.count.expect(3.U) + Seq(20, 21, 22).zipWithIndex.foreach { case (id, lane) => + dut.io.out.bits.entries(lane).uop.instruction.parent.identity + .instructionId.expect(id.U) + } + dut.io.out.bits.entries(0).uop.blockBoundary.expect(true.B) + dut.io.out.bits.entries(1).uop.instruction.kind + .expect(FrontEndOpKind.TemplateUop) + dut.io.out.bits.entries(2).uop.opcode.expect(rule("OP_ADD").opcode.U) + } + } + + test("preserves operands and produces typed precise traps") { + simulate(new DEC(ParamProfiles.W2)) { dut => + clearDec(dut) + dut.io.in.bits.count.poke(2.U) + val add = rule("OP_ADD").value | + (BigInt(5) << 7) | (BigInt(6) << 15) | (BigInt(7) << 20) + pokeEncoded(dut.io.in.bits, 0, "OP_ADD", 30, rawOverride = Some(add)) + pokeEncoded(dut.io.in.bits, 1, "OP_ADD", 31, + rawOverride = Some(BigInt("ffffffffffffffff", 16))) + dut.io.in.valid.poke(true.B) + + val first = dut.io.out.bits.entries(0) + first.uop.destinations(0).valid.expect(true.B) + first.uop.destinations(0).kind.expect(OperandKind.Gpr) + first.uop.destinations(0).atag.expect(5.U) + first.uop.sources(0).valid.expect(true.B) + first.uop.sources(0).atag.expect(6.U) + first.uop.sources(1).atag.expect(7.U) + dut.io.out.bits.entries(1).trap.valid.expect(true.B) + dut.io.out.bits.entries(1).trap.cause + .expect(OooD1TrapCause.IllegalEncoding.U) + } + } + + test("retains an atomic D2 prefix with full-width virtual RID intent") { + val p = ParamProfiles.W8.copy( + ooo = ParamProfiles.W8.ooo.copy(robGroupsPerStid = 8)) + simulate(new OOOD1D2Stage(p)) { dut => + clearOoo(dut) + dut.io.ridTailSlot(0).poke(7.U) + dut.io.ridTailGeneration(0).poke(0x8001.U) + dut.io.fromCtu.bits.count.poke(8.U) + (0 until 8).foreach { lane => + pokeEncoded(dut.io.fromCtu.bits, lane, "OP_ADD", 100 + lane) + } + dut.io.d2.ready.poke(false.B) + dut.io.fromCtu.valid.poke(true.B) + dut.io.fromCtu.ready.expect(true.B) + dut.clock.step() + dut.io.fromCtu.valid.poke(false.B) + + dut.io.d2.valid.expect(true.B) + dut.io.d2.bits.count.expect(8.U) + dut.io.d2.bits.groupCount.expect(2.U) + (0 until 8).foreach { lane => + val row = dut.io.d2.bits.entries(lane) + row.uop.rob.ridSlot.expect((if (lane < 4) 7 else 0).U) + row.uop.rob.ridGeneration + .expect((if (lane < 4) 0x8001 else 0x8002).U) + row.uop.rob.memberIndex.expect((lane % 4).U) + row.brobBound.expect(false.B) + } + val heldId = dut.io.d2.bits.entries(7).uop.instruction.parent.identity + .instructionId.peek().litValue + val heldGeneration = dut.io.d2.bits.entries(7).uop.rob.ridGeneration + .peek().litValue + dut.clock.step(3) + dut.io.d2.bits.entries(7).uop.instruction.parent.identity.instructionId + .expect(heldId.U) + dut.io.d2.bits.entries(7).uop.rob.ridGeneration + .expect(heldGeneration.U) + dut.io.fromCtu.ready.expect(false.B) + } + } + + test("elaborates W2 W4 W6 and W8 without fixed lane assumptions") { + Seq(2, 4, 6, 8).foreach { width => + simulate(new OOOD1D2Stage(ParamProfiles.forWidth(width))) { dut => + clearOoo(dut) + dut.io.fromCtu.bits.count.poke(width.U) + (0 until width).foreach { lane => + pokeEncoded(dut.io.fromCtu.bits, lane, "OP_ADD", 200 + lane) + } + dut.io.fromCtu.valid.poke(true.B) + dut.io.fromCtu.ready.expect(true.B) + dut.clock.step() + dut.io.d2.valid.expect(true.B) + dut.io.d2.bits.count.expect(width.U) + } + } + } + + test("prepare fences one STID and matching apply cancels only its retained row") { + val p = ParamProfiles.W2.copy( + ooo = ParamProfiles.W2.ooo.copy(stidCount = 2)) + simulate(new OOOD1D2Stage(p)) { dut => + clearOoo(dut) + dut.io.d2.ready.poke(false.B) + + def accept(stid: Int, id: Int): Unit = { + dut.io.fromCtu.bits.poke(0.U.asTypeOf(dut.io.fromCtu.bits)) + dut.io.fromCtu.bits.count.poke(1.U) + pokeEncoded(dut.io.fromCtu.bits, 0, "OP_ADD", id, stid = stid) + dut.io.fromCtu.valid.poke(true.B) + dut.io.fromCtu.ready.expect(true.B) + dut.clock.step() + dut.io.fromCtu.valid.poke(false.B) + } + accept(0, 300) + accept(1, 301) + + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(55.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.transactionId.poke(55.U) + dut.io.recovery.apply.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.apply.bits.trigger.stid.poke(0.U) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + dut.io.d2.valid.expect(true.B) + dut.io.d2.bits.entries(0).uop.instruction.parent.identity.stid.expect(1.U) + dut.io.d2.bits.entries(0).uop.instruction.parent.identity.instructionId + .expect(301.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala new file mode 100644 index 00000000..0ebd4bc1 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala @@ -0,0 +1,416 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class OOODispatchSpec extends AnyFunSuite with ChiselSim { + private def clear(dut: Dispatch): Unit = { + dut.io.in.valid.poke(false.B) + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + } + + private def publish( + dut: Dispatch, + classes: Seq[UopClass.Type], + early: Set[Int] = Set.empty, + trapCauses: Map[Int, BigInt] = Map.empty, + fastResolve: Map[Int, Int] = Map.empty): Unit = { + val count = classes.length + dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.in.bits.count.poke(count.U) + dut.io.in.bits.groupCount.poke(count.U) + dut.io.robPrepared.count.poke(count.U) + dut.io.brobPrepared.count.poke(count.U) + classes.zipWithIndex.foreach { case (cls, lane) => + val raw = dut.io.in.bits.entries(lane).uop.decoded.rob + val classification = + dut.io.in.bits.entries(lane).uop.decoded.classification + val classValue = cls.asUInt.litValue.toInt + val aluValue = UopClass.Alu.asUInt.litValue.toInt + val bruValue = UopClass.Bru.asUInt.litValue.toInt + val aguValue = UopClass.Agu.asUInt.litValue.toInt + val stdValue = UopClass.Std.asUInt.litValue.toInt + val systemValue = UopClass.System.asUInt.litValue.toInt + val cmdValue = UopClass.Cmd.asUInt.litValue.toInt + val boundaryValue = UopClass.Boundary.asUInt.litValue.toInt + dut.io.in.bits.groups(lane).valid.poke(true.B) + dut.io.in.bits.groups(lane).peId.poke(1.U) + dut.io.in.bits.groups(lane).stid.poke(0.U) + dut.io.in.bits.groups(lane).ridSlot.poke(lane.U) + dut.io.in.bits.entries(lane).uop.decoded.valid.poke(true.B) + dut.io.in.bits.entries(lane).uop.decoded.uopClass.poke(cls) + classification.valid.poke(true.B) + classification.disposition.poke( + (if (classValue == boundaryValue) OooOpcodeDisposition.FastResolve + else OooOpcodeDisposition.Dispatch).U) + classification.kind.poke( + (if (classValue == stdValue) OooOpcodeRecipeKind.ScalarStore + else if (classValue == aguValue) OooOpcodeRecipeKind.ScalarLoad + else if (classValue == boundaryValue) OooOpcodeRecipeKind.Boundary + else OooOpcodeRecipeKind.Single).U) + classification.uopCountMin.poke( + (if (classValue == boundaryValue) 0 else 1).U) + classification.uopCountMax.poke( + (if (classValue == stdValue) 2 else 1).U) + classification.sideEffectOwner.poke( + (if (classValue == stdValue || classValue == aguValue) + OooSideEffectOwner.Lsu + else if (classValue == bruValue || classValue == boundaryValue) + OooSideEffectOwner.Bctrl + else if (classValue == systemValue || classValue == cmdValue) + OooSideEffectOwner.Commit + else OooSideEffectOwner.Iex).U) + classification.dispatchWrites.poke( + (if (classValue == boundaryValue) 0 + else if (classValue == stdValue) 2 + else 1).U) + if (classValue == aluValue) { + classification.dispatchClass.poke(OooDispatchClass.Alu.U) + classification.dispatchDemand(OooDispatchClass.Alu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Alu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) + } else if (classValue == bruValue) { + classification.dispatchClass.poke(OooDispatchClass.Bru.U) + classification.dispatchDemand(OooDispatchClass.Bru - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Bru - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.Branch).U) + } else if (classValue == aguValue) { + classification.dispatchClass.poke(OooDispatchClass.Agu.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress).U) + } else if (classValue == stdValue) { + classification.dispatchClass.poke(OooDispatchClass.Std.U) + classification.splitKind.poke(OooLateSplitKind.StoreAddressData.U) + classification.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) + classification.dispatchDemand(OooDispatchClass.Std - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Agu - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreAddress).U) + classification.executionPipeCapability(OooDispatchClass.Std - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.StoreData).U) + } else if (classValue == systemValue) { + classification.dispatchClass.poke(OooDispatchClass.Sys.U) + classification.dispatchDemand(OooDispatchClass.Sys - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Sys - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.System).U) + } else if (classValue == cmdValue) { + classification.dispatchClass.poke(OooDispatchClass.Cmd.U) + classification.dispatchDemand(OooDispatchClass.Cmd - 1).poke(1.U) + classification.executionPipeCapability(OooDispatchClass.Cmd - 1).poke( + OooIexDomainCapability.mask(OooIexDomainCapability.EngineCommand).U) + } else { + assert(classValue == boundaryValue) + classification.fastResolveClass.poke( + OooFastResolveClass.BoundaryMetadata.U) + classification.nonspeculative.poke(true.B) + classification.dispatchClass.poke(OooDispatchClass.None.U) + } + fastResolve.get(lane).foreach { fastClass => + classification.disposition.poke(OooOpcodeDisposition.FastResolve.U) + classification.fastResolveClass.poke(fastClass.U) + classification.dispatchClass.poke(OooDispatchClass.None.U) + classification.dispatchWrites.poke(0.U) + classification.dispatchDemand.foreach(_.poke(0.U)) + classification.executionPipeCapability.foreach(_.poke(0.U)) + } + dut.io.in.bits.entries(lane).uop.decoded.opcode.poke((0x120 + lane).U) + dut.io.in.bits.entries(lane).uop.decoded.immediateValid.poke(true.B) + dut.io.in.bits.entries(lane).uop.decoded.immediate.poke((0x500 + lane).U) + dut.io.in.bits.entries(lane).uop.decoded.instruction.parent.identity.instructionId.poke((0x80 + lane).U) + dut.io.in.bits.entries(lane).trap.valid.poke(trapCauses.contains(lane).B) + dut.io.in.bits.entries(lane).trap.cause.poke(trapCauses.getOrElse(lane, BigInt(0)).U) + dut.io.in.bits.entries(lane).pcBufferIndexOffset.valid.poke(true.B) + dut.io.in.bits.entries(lane).pcBufferIndexOffset.pcBufferIndex.poke( + (lane + 4).U) + dut.io.in.bits.entries(lane).pcBufferIndexOffset.pcOffset.poke( + (lane * 8).U) + dut.io.in.bits.entries(lane).pcBufferIndexOffset.allocationEpoch.poke( + (lane + 7).U) + dut.io.in.bits.entries(lane).uop.sources(0).valid.poke(true.B) + dut.io.in.bits.entries(lane).uop.sources(0).kind.poke(OperandKind.Gpr) + dut.io.in.bits.entries(lane).uop.sources(0).atag.poke((4 + lane).U) + dut.io.in.bits.entries(lane).uop.sources(0).ptag.poke((20 + lane).U) + dut.io.in.bits.entries(lane).uop.sources(0).ptagValid.poke(true.B) + dut.io.in.bits.entries(lane).uop.sources(0).ready.poke(true.B) + dut.io.in.bits.entries(lane).uop.destinations(0).valid.poke(true.B) + dut.io.in.bits.entries(lane).uop.destinations(0).kind.poke(OperandKind.Gpr) + dut.io.in.bits.entries(lane).uop.destinations(0).atag.poke((8 + lane).U) + dut.io.in.bits.entries(lane).uop.destinations(0).ptag.poke((24 + lane).U) + dut.io.in.bits.entries(lane).uop.destinations(0).ptagValid.poke(true.B) + raw.peId.poke(1.U); raw.stid.poke(0.U); raw.ridSlot.poke(lane.U) + raw.ridGeneration.poke(2.U); raw.memberIndex.poke(0.U) + dut.io.in.bits.entries(lane).earlyRobComplete.poke(early(lane).B) + + dut.io.robPrepared.entries(lane).valid.poke(true.B) + dut.io.robPrepared.entries(lane).rob.poke(raw.peek()) + dut.io.robPrepared.entries(lane).rob.bid.poke((9 + lane).U) + dut.io.robPrepared.entries(lane).rob.brobGeneration.poke(3.U) + dut.io.robPrepared.entries(lane).rob.residentGeneration.poke(5.U) + dut.io.brobPrepared.entries(lane).valid.poke(true.B) + dut.io.brobPrepared.entries(lane).stid.poke(0.U) + dut.io.brobPrepared.entries(lane).bid.poke((9 + lane).U) + dut.io.brobPrepared.entries(lane).brobGeneration.poke(3.U) + } + dut.io.in.valid.poke(true.B) + dut.io.in.ready.expect(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + } + + test("maps every canonical D3 field and keeps STA plus STD trap and CMD classing exact") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + publish( + dut, + Seq(UopClass.Alu, UopClass.Std, UopClass.Cmd, UopClass.Boundary), + early = Set(3), + trapCauses = Map(1 -> OooD1TrapCause.IllegalEncoding)) + + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.uop.decoded.opcode.expect(0x120.U) + dut.io.iex.aluDispatch(0).bits.uop.decoded.immediate.expect(0x500.U) + dut.io.iex.aluDispatch(0).bits.uop.sources(0).atag.expect(4.U) + dut.io.iex.aluDispatch(0).bits.uop.sources(0).ptag.expect(20.U) + dut.io.iex.aluDispatch(0).bits.uop.destinations(0).atag.expect(8.U) + dut.io.iex.aluDispatch(0).bits.uop.destinations(0).ptag.expect(24.U) + dut.io.iex.aluDispatch(0).bits.uop.decoded.rob.bid.expect(9.U) + dut.io.iex.aluDispatch(0).bits.uop.decoded.rob.brobGeneration.expect(3.U) + dut.io.iex.aluDispatch(0).bits.uop.decoded.rob.residentGeneration.expect(5.U) + dut.io.iex.aluDispatch(0).bits.pcBufferIndexOffset.pcBufferIndex.expect(4.U) + dut.io.iex.aluDispatch(0).bits.pcBufferIndexOffset.pcOffset.expect(0.U) + dut.io.iex.aluDispatch(0).bits.pcBufferIndexOffset.allocationEpoch.expect(7.U) + dut.io.iex.storeDispatch(0).valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.sta.transactionId.expect( + dut.io.iex.storeDispatch(0).bits.std.transactionId.peek()) + dut.io.iex.storeDispatch(0).bits.sta.uop.decoded.opcode.expect( + dut.io.iex.storeDispatch(0).bits.std.uop.decoded.opcode.peek()) + dut.io.iex.storeDispatch(0).bits.sta.uop.decoded.rob.bid.expect( + dut.io.iex.storeDispatch(0).bits.std.uop.decoded.rob.bid.peek()) + dut.io.iex.storeDispatch(0).bits.sta.trap.valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.sta.trap.cause.expect( + OooD1TrapCause.IllegalEncoding.U) + dut.io.iex.storeDispatch(0).bits.std.trap.expect( + dut.io.iex.storeDispatch(0).bits.sta.trap.peek()) + dut.io.iex.storeDispatch(0).bits.sta.pcBufferIndexOffset.expect( + dut.io.iex.storeDispatch(0).bits.std.pcBufferIndexOffset.peek()) + dut.io.iex.storeDispatch(0).bits.sta.pcBufferIndexOffset.pcBufferIndex + .expect(5.U) + dut.io.iex.storeDispatch(0).bits.sta.pcBufferIndexOffset.pcOffset + .expect(8.U) + dut.io.iex.storeDispatch(0).bits.sta.pcBufferIndexOffset.allocationEpoch + .expect(8.U) + dut.io.iex.cmdDispatch(0).valid.expect(true.B) + dut.io.iex.systemDispatch(0).valid.expect(false.B) + dut.clock.step() + dut.io.pending.expect(false.B) + } + } + + test("retries only the undispatched continuous suffix") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + publish(dut, Seq(UopClass.Alu, UopClass.Alu, UopClass.Alu, UopClass.Cmd)) + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.uop.decoded.opcode.expect(0x120.U) + dut.io.iex.aluDispatch(1).valid.expect(true.B) + dut.io.iex.aluDispatch(1).bits.uop.decoded.opcode.expect(0x121.U) + dut.io.iex.cmdDispatch(0).valid.expect(false.B) + dut.clock.step() + dut.io.pending.expect(true.B) + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.uop.decoded.opcode.expect(0x122.U) + dut.io.iex.cmdDispatch(0).valid.expect(true.B) + dut.io.iex.cmdDispatch(0).bits.uop.decoded.opcode.expect(0x123.U) + dut.clock.step() + dut.io.pending.expect(false.B) + } + } + + test("fast-result producers bypass classed dispatch without blocking younger work") { + simulate(new Dispatch(ParamProfiles.W2)) { dut => + clear(dut) + publish( + dut, + Seq(UopClass.System, UopClass.Bru), + fastResolve = Map(0 -> OooFastResolveClass.ImmediateProducer)) + + dut.io.iex.systemDispatch.foreach(_.valid.expect(false.B)) + dut.io.iex.bruDispatch(0).valid.expect(true.B) + dut.io.iex.bruDispatch(0).bits.uop.decoded.opcode.expect(0x121.U) + dut.clock.step() + dut.io.pending.expect(false.B) + } + } + + test("holds valid and payload stable until a wait-for-valid consumer accepts") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + dut.io.iex.aluDispatch.foreach(_.ready.poke(false.B)) + publish(dut, Seq(UopClass.Alu), + trapCauses = Map(0 -> OooD1TrapCause.IllegalEncoding)) + + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.trap.valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.trap.cause.expect( + OooD1TrapCause.IllegalEncoding.U) + val held = dut.io.iex.aluDispatch(0).bits.peek() + dut.clock.step(3) + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.expect(held) + dut.io.iex.aluDispatch(0).bits.trap.valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.trap.cause.expect( + OooD1TrapCause.IllegalEncoding.U) + + dut.io.iex.aluDispatch(0).ready.poke(true.B) + dut.clock.step() + dut.io.pending.expect(false.B) + } + } + + test("requires atomic AGU and STD credit and suppresses recovery-coincident dispatch") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + dut.io.iex.storeDispatch.foreach(_.ready.poke(false.B)) + publish(dut, Seq(UopClass.Std), + trapCauses = Map(0 -> OooD1TrapCause.IllegalEncoding)) + dut.io.iex.aguDispatch(0).valid.expect(false.B) + dut.io.iex.storeDispatch(0).valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.sta.trap.cause.expect( + OooD1TrapCause.IllegalEncoding.U) + dut.io.iex.storeDispatch(0).bits.std.trap.expect( + dut.io.iex.storeDispatch(0).bits.sta.trap.peek()) + val held = dut.io.iex.storeDispatch(0).bits.peek() + dut.clock.step() + dut.io.pending.expect(true.B) + dut.io.iex.aguDispatch(0).valid.expect(false.B) + dut.io.iex.storeDispatch(0).valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.expect(held) + dut.io.iex.storeDispatch(0).bits.sta.trap.valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.std.trap.expect( + dut.io.iex.storeDispatch(0).bits.sta.trap.peek()) + + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(17.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(dut.io.recovery.prepared.bits.peek()) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.iex.aguDispatch(0).valid.expect(false.B) + dut.io.iex.storeDispatch(0).valid.expect(false.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.pending.expect(false.B) + } + } + + test("activates both W4 store lanes as one accepted prefix") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + publish(dut, Seq(UopClass.Std, UopClass.Std)) + dut.io.iex.storeDispatch(0).valid.expect(true.B) + dut.io.iex.storeDispatch(0).bits.sta.uop.decoded.opcode.expect(0x120.U) + dut.io.iex.storeDispatch(1).valid.expect(true.B) + dut.io.iex.storeDispatch(1).bits.sta.uop.decoded.opcode.expect(0x121.U) + dut.clock.step() + dut.io.pending.expect(false.B) + } + } + + test("every accepted input is retained even without a separate publication pulse") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + dut.io.iex.aluDispatch.foreach(_.ready.poke(false.B)) + dut.io.in.bits.count.poke(1.U) + dut.io.in.bits.groupCount.poke(1.U) + dut.io.in.bits.groups(0).valid.poke(true.B) + dut.io.in.bits.entries(0).uop.decoded.valid.poke(true.B) + dut.io.in.bits.entries(0).uop.decoded.uopClass.poke(UopClass.Alu) + dut.io.robPrepared.count.poke(1.U) + dut.io.robPrepared.entries(0).valid.poke(true.B) + dut.io.brobPrepared.count.poke(1.U) + dut.io.brobPrepared.entries(0).valid.poke(true.B) + dut.io.in.valid.poke(true.B) + + dut.io.in.ready.expect(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + dut.io.pending.expect(true.B) + } + } + + test("rejects mismatched owner preparation without mutation and abort preserves the suffix") { + simulate(new Dispatch(ParamProfiles.W4)) { dut => + clear(dut) + dut.io.iex.aluDispatch.foreach(_.ready.poke(false.B)) + dut.io.in.bits.count.poke(1.U) + dut.io.in.bits.groupCount.poke(1.U) + dut.io.in.bits.groups(0).valid.poke(true.B) + dut.io.in.bits.entries(0).uop.decoded.valid.poke(true.B) + dut.io.in.bits.entries(0).uop.decoded.uopClass.poke(UopClass.Alu) + dut.io.robPrepared.count.poke(1.U) + dut.io.robPrepared.entries(0).valid.poke(true.B) + dut.io.brobPrepared.entries(0).valid.poke(true.B) + dut.io.in.valid.poke(true.B) + + dut.io.in.ready.expect(false.B) + dut.clock.step() + dut.io.pending.expect(false.B) + + dut.io.brobPrepared.count.poke(1.U) + dut.io.brobPrepared.entries(0).stid.poke(1.U) + dut.io.in.ready.expect(false.B) + dut.io.brobPrepared.entries(0).stid.poke(0.U) + dut.io.in.ready.expect(true.B) + dut.clock.step() + dut.io.in.valid.poke(false.B) + dut.io.pending.expect(true.B) + + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(31.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(dut.io.recovery.prepared.bits.peek()) + dut.io.recovery.abort.bits.phase.poke(RecoveryPhase.Abort) + dut.io.recovery.abort.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + dut.io.pending.expect(true.B) + } + } + + test("elaborates the dispatch mechanism at W2 W4 W6 and W8") { + Seq(2, 4, 6, 8).foreach { width => + val p: CoreParams = ParamProfiles.forWidth(width) + simulate(new Dispatch(p)) { dut => clear(dut) } + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOExternalD1CommitSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOExternalD1CommitSpec.scala new file mode 100644 index 00000000..ffc0975f --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOExternalD1CommitSpec.scala @@ -0,0 +1,240 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.iex.OOOIEXLSUActivationParams +import linxcore.params.{ParamProfiles, SimulationParamProfiles} +import linxcore.common.TemplateRowKind +import linxcore.top.interface.FrontEndOpKind +import org.scalatest.funsuite.AnyFunSuite + +class OOOExternalD1CommitSpec extends AnyFunSuite with ChiselSim { + private def initialize(dut: OOO): Unit = { + dut.io.fromCtu.valid.poke(false.B) + dut.io.fromCtu.bits.poke(0.U.asTypeOf(dut.io.fromCtu.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(false.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.fastResult.ready.poke(true.B) + dut.io.iex.pcBufferReadAddress.foreach( + _.poke(0.U.asTypeOf(dut.io.iex.pcBufferReadAddress.head))) + dut.io.iex.robNoflushReady.valid.poke(false.B) + dut.io.iex.robNoflushReady.bits.poke( + 0.U.asTypeOf(dut.io.iex.robNoflushReady.bits)) + dut.io.iex.robNoflush.ready.poke(true.B) + dut.io.iex.robResolve.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.systemIssue.foreach(_.valid.poke(false.B)) + dut.io.iex.systemIssue.foreach( + _.bits.poke(0.U.asTypeOf(dut.io.iex.systemIssue.head.bits))) + dut.io.iex.recoveryEvent.valid.poke(false.B) + dut.io.iex.recoveryEvent.bits.poke( + 0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.storeResolve.valid.poke(false.B) + dut.io.storeResolve.bits.poke(0.U.asTypeOf(dut.io.storeResolve.bits)) + dut.io.commit.ready.poke(true.B) + dut.io.trap.ready.poke(true.B) + dut.io.interrupt.valid.poke(false.B) + dut.io.interrupt.bits.poke(0.U.asTypeOf(dut.io.interrupt.bits)) + Seq(dut.io.recoveryToIfu, dut.io.recoveryToCtu, + dut.io.recoveryToLsu, dut.io.iex.recovery).foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + dut.io.trace.ready.poke(true.B) + dut.reset.poke(true.B) + dut.clock.step(2) + dut.reset.poke(false.B) + } + + test("external D1 body without block markers cannot pass BROB commit preflight") { + val base = ParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + pcBufferEntries = 8, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8)) + simulate(new OOO(p)) { dut => + initialize(dut) + + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + val entry = dut.io.fromCtu.bits.entries.head + dut.io.fromCtu.bits.count.poke(1.U) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke(1.U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(0x1004.U) + entry.parent.instruction.poke( + (addi.value | (BigInt(5) << 7) | (BigInt(7) << 20)).U) + entry.parent.lengthBytes.poke(addi.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(0x1004.U) + entry.parent.prediction.fallthroughPc.poke(0x1008.U) + entry.parent.prediction.epoch.poke(1.U) + dut.io.fromCtu.valid.poke(true.B) + while (!dut.io.fromCtu.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.fromCtu.valid.poke(false.B) + + var cycles = 0 + while (!dut.io.iex.aluDispatch.head.valid.peek().litToBoolean && + cycles < 64) { dut.clock.step(); cycles += 1 } + assert(cycles < 64) + val identity = dut.io.iex.aluDispatch.head.bits.uop.decoded.rob.peek() + dut.io.iex.aluDispatch.head.ready.poke(true.B) + dut.clock.step() + val completion = dut.io.iex.robResolve.head + completion.bits.poke(0.U.asTypeOf(completion.bits)) + completion.bits.rob.poke(identity) + completion.valid.poke(true.B) + completion.ready.expect(true.B) + dut.clock.step() + completion.valid.poke(false.B) + + dut.clock.step(64) + dut.io.commit.valid.expect(false.B) + } + } + + test("external D1 closed block passes BROB and PC preflight then commits") { + val p = OOOIEXLSUActivationParams.W4 + simulate(new OOO(p)) { dut => + initialize(dut) + val start = OooOpcodeRecipeTable.Rules.find( + _.symbol == "OP_BSTART_FALL").get + val addi = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_ADDI").get + val stop = OooOpcodeRecipeTable.Rules.find(_.symbol == "OP_BSTOP").get + val encodings = Seq( + (start, start.value, 0x1000), + (addi, addi.value | (BigInt(5) << 7) | (BigInt(7) << 20), 0x1004), + (stop, stop.value, 0x1008)) + dut.io.fromCtu.bits.count.poke(encodings.length.U) + encodings.zipWithIndex.foreach { case ((rule, raw, pc), lane) => + val entry = dut.io.fromCtu.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.Encoded64) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke((lane + 1).U) + entry.parent.identity.epoch.poke(1.U) + entry.parent.pc.poke(pc.U) + entry.parent.instruction.poke(raw.U) + entry.parent.lengthBytes.poke(rule.lenBytes.U) + entry.parent.prediction.valid.poke(true.B) + entry.parent.prediction.requestPc.poke(pc.U) + entry.parent.prediction.fallthroughPc.poke((pc + rule.lenBytes).U) + entry.parent.prediction.epoch.poke(1.U) + } + dut.io.fromCtu.valid.poke(true.B) + while (!dut.io.fromCtu.ready.peek().litToBoolean) dut.clock.step() + dut.clock.step() + dut.io.fromCtu.valid.poke(false.B) + + var cycles = 0 + while (!dut.io.iex.aluDispatch.head.valid.peek().litToBoolean && + cycles < 64) { dut.clock.step(); cycles += 1 } + assert(cycles < 64) + val identity = dut.io.iex.aluDispatch.head.bits.uop.decoded.rob.peek() + dut.io.iex.aluDispatch.head.ready.poke(true.B) + dut.clock.step() + val completion = dut.io.iex.robResolve.head + completion.bits.poke(0.U.asTypeOf(completion.bits)) + completion.bits.rob.poke(identity) + completion.bits.destinationValid.poke(true.B) + completion.bits.value.poke(7.U) + completion.valid.poke(true.B) + completion.ready.expect(true.B) + dut.clock.step() + completion.valid.poke(false.B) + + cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 64) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries.head.rob.expect(identity) + dut.clock.step() + dut.io.commit.valid.expect(false.B) + } + } + + test("d1-reserved-tail reserves ROB groups beyond an unpublished RENU prefix") { + val p = SimulationParamProfiles.W2 + simulate(new OOO(p)) { dut => + initialize(dut) + dut.io.iex.storeDispatch.foreach(_.ready.poke(false.B)) + + def sendTemplate( + opcodes: Seq[TemplateRowKind.Type], + firstOrdinal: Int): Unit = { + dut.io.fromCtu.bits.poke(0.U.asTypeOf(dut.io.fromCtu.bits)) + dut.io.fromCtu.bits.count.poke(opcodes.length.U) + opcodes.zipWithIndex.foreach { case (opcode, lane) => + val entry = dut.io.fromCtu.bits.entries(lane) + entry.kind.poke(FrontEndOpKind.TemplateUop) + entry.parent.identity.peId.poke(1.U) + entry.parent.identity.stid.poke(0.U) + entry.parent.identity.instructionId.poke(7.U) + entry.parent.identity.epoch.poke(2.U) + entry.parent.pc.poke(0x1000.U) + entry.parent.lengthBytes.poke(4.U) + entry.templateOrdinal.poke((firstOrdinal + lane).U) + entry.templateCount.poke(6.U) + entry.templateOpcode.poke(opcode.asUInt) + entry.templateRegister.poke((10 + lane).U) + entry.templateImmediate.poke((0x20 - (firstOrdinal + lane) * 8).U) + } + dut.io.fromCtu.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromCtu.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.fromCtu.valid.poke(false.B) + } + + sendTemplate( + Seq(TemplateRowKind.VFORM, TemplateRowKind.SP_SUB), + firstOrdinal = 0) + sendTemplate( + Seq(TemplateRowKind.STORE, TemplateRowKind.STORE), + firstOrdinal = 2) + + // The first prefix remains unpublished behind the ALU sink while the + // second D1 row is already retained. Its virtual ROB allocation must + // start after both groups reserved by the older RENU prefix. + dut.clock.step(2) + dut.io.iex.aluDispatch.head.valid.expect(true.B) + dut.io.iex.aluDispatch.head.ready.poke(true.B) + + var cycles = 0 + while (!dut.io.iex.storeDispatch.head.valid.peek().litToBoolean && + cycles < 32) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 32, "second template chunk deadlocked on a stale ROB tail") + dut.io.iex.storeDispatch(0).bits.sta.uop.decoded.rob.ridSlot.expect(2.U) + dut.io.iex.storeDispatch(0).bits.sta.uop.decoded.rob.memberIndex.expect(0.U) + dut.io.iex.storeDispatch(1).bits.sta.uop.decoded.rob.ridSlot.expect(2.U) + dut.io.iex.storeDispatch(1).bits.sta.uop.decoded.rob.memberIndex.expect(1.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala new file mode 100644 index 00000000..82802fc1 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala @@ -0,0 +1,642 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import linxcore.params.{CoreParams, SimulationParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +private object OOOIntegrationSpec { + final case class Shape(p: Boolean, t: Boolean, u: Boolean) + final case class PhysicalTag(index: BigInt, generation: BigInt) + final case class Published( + identity: RobIdentity, + p: Option[PhysicalTag], + t: Option[PhysicalTag], + u: Option[PhysicalTag], + pc: BigInt, + pcBufferValid: Boolean, + pcBufferIndex: BigInt, + pcOffset: BigInt, + pcAllocationEpoch: BigInt) +} + +class OOOIntegrationSpec extends AnyFunSuite with ChiselSim { + import OOOIntegrationSpec.{PhysicalTag, Published, Shape} + test("elaborates the canonical owner graph at W2 W4 W6 and W8") { + Seq(2, 4, 6, 8).foreach { width => + val p: CoreParams = SimulationParamProfiles.forWidth(width) + val chirrtl = ChiselStage.emitCHIRRTL(new OOO(p)) + assert(chirrtl.contains("circuit OOO")) + Seq("RENU", "ROB", "BROB", "Dispatch", "CommitControl", + "RecoveryControl", "OooPcBuffer").foreach(owner => + assert(chirrtl.contains(s"module $owner"))) + assert(chirrtl.contains("module OooD3ReservationAllocator")) + assert(chirrtl.contains("inst pcBuffer of OooPcBuffer")) + Seq("OooO3RenameCoordinator", "OooS1GroupedRob", "OooBrob", + "OooPRename", "OooTURename").foreach(displacedModule => + assert(!chirrtl.contains(s"module $displacedModule"))) + } + } + + test("public OOO carries both store bindings inward and ready outward") { + val p = SimulationParamProfiles.W4 + val chirrtl = ChiselStage.emitCHIRRTL(new OOO(p)) + val bindingLines = chirrtl.linesIterator + .filter(line => line.trim.startsWith("connect") && + line.contains("storeBinding")) + .mkString("\n") + + for (lane <- 0 until p.iex.stdPipes) { + withClue(bindingLines) { + assert(chirrtl.contains( + s"connect d3s1.io.iex.storeBinding[$lane].valid, io.iex.storeBinding[$lane].valid")) + assert(chirrtl.contains( + s"connect d3s1.io.iex.storeBinding[$lane].bits.rob.peId, io.iex.storeBinding[$lane].bits.rob.peId")) + assert(chirrtl.contains( + s"connect d3s1.io.iex.storeBinding[$lane].bits.transaction.value, io.iex.storeBinding[$lane].bits.transaction.value")) + assert(chirrtl.contains( + s"connect d3s1.io.iex.storeBinding[$lane].bits.memoryOrder.requestCount, io.iex.storeBinding[$lane].bits.memoryOrder.requestCount")) + assert(chirrtl.contains( + s"connect io.iex.storeBinding[$lane].ready, d3s1.io.iex.storeBinding[$lane].ready")) + } + } + } + + private def clear(dut: OOOD3S1Graph): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.fastResult.ready.poke(true.B) + dut.io.iex.storeBinding.foreach { binding => + binding.valid.poke(false.B) + binding.bits.poke(0.U.asTypeOf(binding.bits)) + } + dut.io.iex.pcBufferReadAddress.foreach { address => + address.poke(0.U.asTypeOf(address)) + } + dut.io.iex.robNoflushReady.valid.poke(false.B) + dut.io.iex.robNoflushReady.bits.poke( + 0.U.asTypeOf(dut.io.iex.robNoflushReady.bits)) + dut.io.iex.robNoflush.ready.poke(true.B) + dut.io.iex.robResolve.foreach { in => + in.valid.poke(false.B) + in.bits.poke(0.U.asTypeOf(in.bits)) + } + dut.io.iex.recoveryEvent.valid.poke(false.B) + dut.io.iex.recoveryEvent.bits.poke(0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.commit.ready.poke(true.B) + dut.io.storeCommit.ready.poke(true.B) + dut.io.trap.ready.poke(true.B) + dut.io.interrupt.valid.poke(false.B) + dut.io.interrupt.bits.poke(0.U.asTypeOf(dut.io.interrupt.bits)) + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + dut.io.trace.ready.poke(true.B) + } + + private def driveTargetAcks(dut: OOOD3S1Graph): Unit = { + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + val preparing = target.prepare.valid.peek().litToBoolean + target.prepared.valid.poke(preparing.B) + if (preparing) target.prepared.bits.poke(target.prepare.bits.peek()) + } + } + + private def publish( + dut: OOOD3S1Graph, + stid: Int, + shapes: Seq[Shape]): Seq[Published] = { + require(shapes.nonEmpty) + val tail = dut.io.ridTailSlot(stid).peek().litValue.toInt + val generation = dut.io.ridTailGeneration(stid).peek().litValue + val capacity = dut.p.ooo.robGroupsPerStid + dut.io.iex.aluDispatch.foreach(_.ready.poke(false.B)) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(shapes.length.U) + dut.io.fromD2.bits.groupCount.poke(shapes.length.U) + shapes.zipWithIndex.foreach { case (shape, lane) => + val absolute = tail + lane + val slot = absolute % capacity + val gen = generation + absolute / capacity + val group = dut.io.fromD2.bits.groups(lane) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(stid.U) + group.ridSlot.poke(slot.U) + group.ridGeneration.poke(gen.U) + val row = dut.io.fromD2.bits.entries(lane).uop + row.valid.poke(true.B) + row.instruction.parent.identity.peId.poke(1.U) + row.instruction.parent.identity.stid.poke(stid.U) + row.instruction.parent.identity.instructionId.poke((100 + stid * 10 + lane).U) + row.instruction.parent.identity.epoch.poke(3.U) + row.instruction.parent.pc.poke((0x1000 + stid * 0x100 + lane * 8).U) + row.rob.peId.poke(1.U) + row.rob.stid.poke(stid.U) + row.rob.ridSlot.poke(slot.U) + row.rob.ridGeneration.poke(gen.U) + row.rob.memberIndex.poke(0.U) + row.uopClass.poke(UopClass.Alu) + row.classification.valid.poke(true.B) + row.classification.dispatchClass.poke(OooDispatchClass.Alu.U) + row.classification.executionPipeCapability( + OooDispatchClass.Alu - 1).poke( + (BigInt(1) << OooIexDomainCapability.SimpleAlu).U) + row.blockStart.poke(true.B) + row.blockStop.poke(true.B) + var destination = 0 + if (shape.p) { + row.destinations(destination).valid.poke(true.B) + row.destinations(destination).kind.poke(OperandKind.Gpr) + row.destinations(destination).atag.poke((stid + lane + 1).U) + destination += 1 + } + if (shape.t) { + row.destinations(destination).valid.poke(true.B) + row.destinations(destination).kind.poke(OperandKind.T) + row.destinations(destination).relativeIndex.poke(0.U) + destination += 1 + } + if (shape.u) { + row.destinations(destination).valid.poke(true.B) + row.destinations(destination).kind.poke(OperandKind.U) + row.destinations(destination).relativeIndex.poke(0.U) + } + } + dut.io.fromD2.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromD2.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val published = shapes.indices.map { lane => + cycles = 0 + while (!dut.io.iex.aluDispatch(0).valid.peek().litToBoolean && cycles < 16) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 16) + val held = dut.io.iex.aluDispatch(0).bits.peek() + dut.clock.step() + dut.io.iex.aluDispatch(0).valid.expect(true.B) + dut.io.iex.aluDispatch(0).bits.expect(held) + var destination = 0 + def nextTag(kind: OperandKind.Type): PhysicalTag = { + val row = held.uop.destinations(destination) + destination += 1 + kind match { + case OperandKind.Gpr => PhysicalTag( + row.ptag.litValue, + row.pGeneration.litValue, + ) + case OperandKind.T => PhysicalTag( + row.ttag.litValue, + row.tGeneration.litValue, + ) + case OperandKind.U => PhysicalTag( + row.utag.litValue, + row.uGeneration.litValue, + ) + } + } + val shape = shapes(lane) + val observation = Published( + held.uop.decoded.rob, + if (shape.p) Some(nextTag(OperandKind.Gpr)) else None, + if (shape.t) Some(nextTag(OperandKind.T)) else None, + if (shape.u) Some(nextTag(OperandKind.U)) else None, + held.uop.decoded.instruction.parent.pc.litValue, + held.pcBufferIndexOffset.valid.litToBoolean, + held.pcBufferIndexOffset.pcBufferIndex.litValue, + held.pcBufferIndexOffset.pcOffset.litValue, + held.pcBufferIndexOffset.allocationEpoch.litValue, + ) + dut.io.iex.aluDispatch(0).ready.poke(true.B) + dut.clock.step() + dut.io.iex.aluDispatch(0).ready.poke(false.B) + observation + } + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + published + } + + private def complete(dut: OOOD3S1Graph, identity: RobIdentity): Unit = { + dut.io.commit.ready.poke(false.B) + val completion = dut.io.iex.robResolve(0) + completion.bits.poke(0.U.asTypeOf(completion.bits)) + completion.bits.rob.poke(identity) + completion.valid.poke(true.B) + completion.ready.expect(true.B) + dut.clock.step() + completion.valid.poke(false.B) + } + + private def expectPcRead( + dut: OOOD3S1Graph, + row: Published, + expectedValid: Boolean): Unit = { + val address = dut.io.iex.pcBufferReadAddress(0) + address.valid.poke(true.B) + address.stid.poke(row.identity.stid) + address.pcBufferIndex.poke(row.pcBufferIndex.U) + address.allocationEpoch.poke(row.pcAllocationEpoch.U) + dut.io.iex.pcBufferReadPcBase(0).valid.expect(expectedValid.B) + if (expectedValid) { + dut.io.iex.pcBufferReadPcBase(0).bits.expect((row.pc - row.pcOffset).U) + } + } + + private def expectCommit( + dut: OOOD3S1Graph, + identities: Seq[RobIdentity], + label: String): Unit = { + dut.io.commit.ready.poke(false.B) + var cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64, s"timed out waiting for $label commit") + dut.io.commit.bits.count.expect(identities.length.U) + identities.zipWithIndex.foreach { case (identity, lane) => + dut.io.commit.bits.entries(lane).rob.expect(identity) + } + val held = dut.io.commit.bits.peek() + dut.clock.step(2) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.expect(held) + dut.io.commit.ready.poke(true.B) + dut.clock.step() + dut.io.commit.valid.expect(false.B) + } + + private def expectNoCommit(dut: OOOD3S1Graph, cycles: Int = 3): Unit = { + dut.io.commit.ready.poke(false.B) + (0 until cycles).foreach { _ => + dut.io.commit.valid.expect(false.B) + dut.clock.step() + } + } + + private def recover( + dut: OOOD3S1Graph, + cause: RecoveryCause.Type, + trigger: RobIdentity, + transactionId: Int): Unit = { + dut.io.iex.recoveryEvent.bits.poke(0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.iex.recoveryEvent.bits.transactionId.poke(transactionId.U) + dut.io.iex.recoveryEvent.bits.cause.poke(cause) + dut.io.iex.recoveryEvent.bits.trigger.poke(trigger) + dut.io.iex.recoveryEvent.valid.poke(true.B) + var sent = false + var applied = false + var cycles = 0 + while (!applied && cycles < 96) { + driveTargetAcks(dut) + sent ||= dut.io.iex.recoveryEvent.ready.peek().litToBoolean + applied = dut.io.recoveryToD1.apply.valid.peek().litToBoolean + dut.clock.step() + if (sent) dut.io.iex.recoveryEvent.valid.poke(false.B) + cycles += 1 + } + assert(applied, s"recovery $transactionId timed out") + driveTargetAcks(dut) + dut.clock.step() + } + + test("commits one completed canonical OOO publication exactly once") { + val base = SimulationParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8, + )) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.io.commit.ready.poke(false.B) + val identity = publish( + dut, + stid = 0, + Seq(Shape(p = true, t = false, u = false)), + ).head.identity + dut.io.commit.valid.expect(false.B) + + val completion = dut.io.iex.robResolve(0) + completion.bits.poke(0.U.asTypeOf(completion.bits)) + completion.bits.rob.poke(identity) + completion.valid.poke(true.B) + completion.ready.expect(true.B) + dut.clock.step() + completion.valid.poke(false.B) + + var cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.expect(identity) + val heldCommit = dut.io.commit.bits.peek() + dut.clock.step(2) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.expect(heldCommit) + + dut.io.commit.ready.poke(true.B) + dut.clock.step() + (0 until 3).foreach { _ => + dut.io.commit.valid.expect(false.B) + dut.clock.step() + } + } + } + + test("backpressured fast result cannot commit before atomic writeback wakeup and resolve") { + val base = SimulationParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8, + )) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.io.commit.ready.poke(false.B) + dut.io.iex.fastResult.ready.poke(false.B) + + val row = dut.io.fromD2.bits.entries(0).uop + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.fromD2.bits.groups(0).valid.poke(true.B) + dut.io.fromD2.bits.groups(0).peId.poke(1.U) + dut.io.fromD2.bits.groups(0).stid.poke(0.U) + row.valid.poke(true.B) + row.instruction.parent.identity.peId.poke(1.U) + row.instruction.parent.identity.stid.poke(0.U) + row.instruction.parent.identity.instructionId.poke(77.U) + row.instruction.parent.identity.epoch.poke(5.U) + row.instruction.parent.pc.poke(0x4000.U) + row.instruction.parent.lengthBytes.poke(4.U) + row.rob.peId.poke(1.U) + row.rob.stid.poke(0.U) + row.uopClass.poke(UopClass.Boundary) + row.classification.valid.poke(true.B) + row.classification.disposition.poke(OooOpcodeDisposition.FastResolve.U) + row.classification.fastResolveClass.poke( + OooFastResolveClass.ImmediateProducer.U) + row.classification.pDestinationCount.poke(1.U) + row.immediateValid.poke(true.B) + row.immediate.poke(0x30.U) + row.earlyComplete.poke(true.B) + row.blockStart.poke(true.B) + row.blockStop.poke(true.B) + row.destinations(0).valid.poke(true.B) + row.destinations(0).kind.poke(OperandKind.Gpr) + row.destinations(0).atag.poke(3.U) + + dut.io.fromD2.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromD2.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + cycles = 0 + while (!dut.io.iex.fastResult.valid.peek().litToBoolean && + cycles < 32) { + dut.io.commit.valid.expect(false.B) + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + val held = dut.io.iex.fastResult.bits.peek() + dut.io.iex.fastResult.bits.writeback.value.expect(0x4030.U) + (0 until 3).foreach { _ => + dut.io.commit.valid.expect(false.B) + dut.io.iex.fastResult.valid.expect(true.B) + dut.io.iex.fastResult.bits.expect(held) + dut.clock.step() + } + + dut.io.iex.fastResult.ready.poke(true.B) + dut.io.iex.fastResult.valid.expect(true.B) + dut.clock.step() + dut.io.iex.fastResult.valid.expect(false.B) + + cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.expect(held.writeback.rob) + } + } + + test("publishes the PC buffer binding and frees it only on common commit") { + val base = SimulationParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + pcBufferEntries = 8, + pcBankCount = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8, + )) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.io.commit.ready.poke(false.B) + val row = publish( + dut, + stid = 0, + Seq(Shape(p = true, t = false, u = false)), + ).head + assert(row.pcBufferValid) + expectPcRead(dut, row, expectedValid = true) + + complete(dut, row.identity) + var cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64) + dut.clock.step(2) + expectPcRead(dut, row, expectedValid = true) + + dut.io.commit.ready.poke(true.B) + dut.clock.step() + expectPcRead(dut, row, expectedValid = false) + } + } + + test("retains one authoritative commit while the ROB preview expands") { + val base = SimulationParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8, + )) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.io.commit.ready.poke(false.B) + val rows = publish( + dut, + stid = 0, + Seq( + Shape(p = true, t = false, u = false), + Shape(p = true, t = false, u = false), + ), + ) + + complete(dut, rows.head.identity) + var cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.expect(rows.head.identity) + + complete(dut, rows(1).identity) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.expect(rows.head.identity) + + dut.io.commit.ready.poke(true.B) + dut.clock.step() + dut.io.commit.ready.poke(false.B) + cycles = 0 + while (!dut.io.commit.valid.peek().litToBoolean && cycles < 64) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 64) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).rob.expect(rows(1).identity) + dut.io.commit.ready.poke(true.B) + dut.clock.step() + dut.io.commit.valid.expect(false.B) + } + } + + test("matches a four-STID reference across canonical publish and recovery") { + val base = SimulationParamProfiles.W2 + val p = base.copy(ooo = base.ooo.copy(stidCount = 4, + stidIdentityEntries = 4, + robGroupsPerStid = 8, brobEntriesPerStid = 8, + pcBufferEntries = 16, + gprPhysRegs = 128, gprMapQDepthPerStid = 8, + tPhysRegs = 16, uPhysRegs = 16, tuMapQDepthPerStid = 8)) + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + val shapes = Seq( + Seq(Shape(p = true, t = false, u = false), Shape(p = false, t = true, u = false)), + Seq(Shape(p = false, t = false, u = true), Shape(p = false, t = false, u = false)), + Seq(Shape(p = true, t = true, u = false), Shape(p = false, t = false, u = true)), + Seq(Shape(p = false, t = true, u = true), Shape(p = false, t = false, u = false))) + val rows = shapes.indices.map(stid => publish(dut, stid, shapes(stid))) + + (0 until 4).foreach { stid => + dut.io.ridTailSlot(stid).expect(2.U) + } + val stid1Tail = dut.io.ridTailSlot(1).peek() + val stid2Tail = dut.io.ridTailSlot(2).peek() + val stid1PreRecoveryPeerU = rows(1).head.u + assert(stid1PreRecoveryPeerU.nonEmpty) + expectPcRead(dut, rows(0)(1), expectedValid = true) + expectPcRead(dut, rows(1).head, expectedValid = true) + + recover(dut, RecoveryCause.Branch, rows(0).head.identity, transactionId = 0x51) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.ridTailSlot(1).expect(stid1Tail) + dut.io.ridTailSlot(2).expect(stid2Tail) + expectPcRead(dut, rows(0).head, expectedValid = true) + expectPcRead(dut, rows(0)(1), expectedValid = false) + expectPcRead(dut, rows(1).head, expectedValid = true) + + complete(dut, rows(1).head.identity) + expectCommit(dut, Seq(rows(1).head.identity), + "peer STID1 head after Branch recovery") + val stid1PeerProbe = publish( + dut, + stid = 1, + Seq(Shape(p = false, t = false, u = true)), + ).head + assert(stid1PeerProbe.u.nonEmpty) + assert(stid1PeerProbe.u.get != stid1PreRecoveryPeerU.get) + val stid1TailAfterProbe = dut.io.ridTailSlot(1).peek() + + complete(dut, rows(0)(1).identity) + expectNoCommit(dut) + complete(dut, rows(0).head.identity) + expectCommit(dut, Seq(rows(0).head.identity), "STID0 survivor") + val stid0Probe = publish( + dut, + stid = 0, + Seq(Shape(p = false, t = true, u = false)), + ).head + assert(stid0Probe.t == rows(0)(1).t) + + recover(dut, RecoveryCause.MemoryOrder, rows(3).head.identity, + transactionId = 0x52) + dut.io.ridTailSlot(3).expect(0.U) + dut.io.ridTailSlot(1).expect(stid1TailAfterProbe) + dut.io.ridTailSlot(2).expect(stid2Tail) + + complete(dut, rows(2).head.identity) + expectCommit(dut, Seq(rows(2).head.identity), + "peer STID2 head after MemoryOrder recovery") + val stid2PeerProbe = publish( + dut, + stid = 2, + Seq(Shape(p = false, t = false, u = true)), + ).head + assert(stid2PeerProbe.u != rows(2)(1).u) + + rows(3).foreach(row => complete(dut, row.identity)) + expectNoCommit(dut) + val stid3Probe = publish( + dut, + stid = 3, + Seq(Shape(p = false, t = true, u = true)), + ).head + assert(stid3Probe.t == rows(3).head.t) + assert(stid3Probe.u == rows(3).head.u) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala new file mode 100644 index 00000000..f7323ecc --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala @@ -0,0 +1,325 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.ParamProfiles +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +private object OOOMemoryOrderIntegrationSpec { + final case class Id(peId: BigInt, stid: BigInt, ridSlot: BigInt, + ridGeneration: BigInt, memberIndex: BigInt, residentGeneration: BigInt, + bid: BigInt, brobGeneration: BigInt) + final case class Observed(transactionId: BigInt, requestCount: BigInt, + firstLsid: BigInt, firstLid: BigInt, firstSid: BigInt, + yostValid: Boolean, yoldValid: Boolean, id: Id) +} + +class OOOMemoryOrderIntegrationSpec extends AnyFunSuite with ChiselSim { + import OOOMemoryOrderIntegrationSpec.{Id, Observed} + private val p = { + val base = ParamProfiles.W2 + base.copy(ooo = base.ooo.copy(stidCount = 2, + robGroupsPerStid = 8, + robBankCount = 2, + brobEntriesPerStid = 8, + gprPhysRegs = 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8)) + } + + private def clear(dut: OOOD3S1Graph): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.iex.aluDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.bruDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.aguDispatch.foreach(_.ready.poke(false.B)) + dut.io.iex.storeDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.systemDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.cmdDispatch.foreach(_.ready.poke(true.B)) + dut.io.iex.pcBufferReadAddress.foreach { address => + address.poke(0.U.asTypeOf(address)) + } + dut.io.iex.robNoflushReady.valid.poke(false.B) + dut.io.iex.robNoflushReady.bits.poke( + 0.U.asTypeOf(dut.io.iex.robNoflushReady.bits)) + dut.io.iex.robNoflush.ready.poke(true.B) + dut.io.iex.robResolve.foreach { port => + port.valid.poke(false.B) + port.bits.poke(0.U.asTypeOf(port.bits)) + } + dut.io.iex.recoveryEvent.valid.poke(false.B) + dut.io.iex.recoveryEvent.bits.poke(0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.commit.ready.poke(true.B) + dut.io.trap.ready.poke(true.B) + dut.io.interrupt.valid.poke(false.B) + dut.io.interrupt.bits.poke(0.U.asTypeOf(dut.io.interrupt.bits)) + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + dut.io.trace.ready.poke(true.B) + } + + private def submitLoad( + dut: OOOD3S1Graph, + instructionId: Int, + stid: Int = 0): Unit = { + val tail = dut.io.ridTailSlot(stid).peek().litValue + val generation = dut.io.ridTailGeneration(stid).peek().litValue + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.fromD2.bits.groups(0).valid.poke(true.B) + dut.io.fromD2.bits.groups(0).peId.poke(1.U) + dut.io.fromD2.bits.groups(0).stid.poke(stid.U) + dut.io.fromD2.bits.groups(0).ridSlot.poke(tail.U) + dut.io.fromD2.bits.groups(0).ridGeneration.poke(generation.U) + val row = dut.io.fromD2.bits.entries(0).uop + row.valid.poke(true.B) + row.instruction.parent.identity.peId.poke(1.U) + row.instruction.parent.identity.stid.poke(stid.U) + row.instruction.parent.identity.instructionId.poke(instructionId.U) + row.instruction.parent.identity.epoch.poke(3.U) + row.rob.peId.poke(1.U) + row.rob.stid.poke(stid.U) + row.rob.ridSlot.poke(tail.U) + row.rob.ridGeneration.poke(generation.U) + row.blockStart.poke(true.B) + row.blockStop.poke(true.B) + row.uopClass.poke(UopClass.Agu) + row.memory.valid.poke(true.B) + row.memory.isLoad.poke(true.B) + row.memory.requestCount.poke(1.U) + dut.io.fromD2.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromD2.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + } + + private def observeLoad(dut: OOOD3S1Graph): Observed = { + var cycles = 0 + while (!dut.io.iex.aguDispatch(0).valid.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + val bits = dut.io.iex.aguDispatch(0).bits + val id = bits.uop.decoded.rob + Observed(bits.transactionId.peek().litValue, + bits.memoryOrder.requestCount.peek().litValue, + bits.memoryOrder.firstLsid.peek().litValue, + bits.memoryOrder.firstLid.peek().litValue, + bits.memoryOrder.firstSid.peek().litValue, + bits.memoryOrder.yostValid.peek().litToBoolean, + bits.memoryOrder.yoldValid.peek().litToBoolean, + Id(id.peId.peek().litValue, id.stid.peek().litValue, + id.ridSlot.peek().litValue, id.ridGeneration.peek().litValue, + id.memberIndex.peek().litValue, id.residentGeneration.peek().litValue, + id.bid.peek().litValue, id.brobGeneration.peek().litValue)) + } + + private def publishLoad( + dut: OOOD3S1Graph, + instructionId: Int, + stid: Int = 0): Observed = { + submitLoad(dut, instructionId, stid) + observeLoad(dut) + } + + private def submitSystem(dut: OOOD3S1Graph, instructionId: Int): Unit = { + val tail = dut.io.ridTailSlot(0).peek().litValue + val generation = dut.io.ridTailGeneration(0).peek().litValue + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.fromD2.bits.groups(0).valid.poke(true.B) + dut.io.fromD2.bits.groups(0).peId.poke(1.U) + dut.io.fromD2.bits.groups(0).stid.poke(0.U) + dut.io.fromD2.bits.groups(0).ridSlot.poke(tail.U) + dut.io.fromD2.bits.groups(0).ridGeneration.poke(generation.U) + val row = dut.io.fromD2.bits.entries(0).uop + row.valid.poke(true.B) + row.instruction.parent.identity.peId.poke(1.U) + row.instruction.parent.identity.stid.poke(0.U) + row.instruction.parent.identity.instructionId.poke(instructionId.U) + row.instruction.parent.identity.epoch.poke(3.U) + row.rob.peId.poke(1.U) + row.rob.stid.poke(0.U) + row.rob.ridSlot.poke(tail.U) + row.rob.ridGeneration.poke(generation.U) + row.blockStart.poke(true.B) + row.blockStop.poke(true.B) + row.uopClass.poke(UopClass.System) + dut.io.fromD2.valid.poke(true.B) + var cycles = 0 + while (!dut.io.fromD2.ready.peek().litToBoolean && cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + } + + private def pokeId(target: RobIdentity, id: Id): Unit = { + target.peId.poke(id.peId.U); target.stid.poke(id.stid.U) + target.ridSlot.poke(id.ridSlot.U) + target.ridGeneration.poke(id.ridGeneration.U) + target.memberIndex.poke(id.memberIndex.U) + target.residentGeneration.poke(id.residentGeneration.U) + target.bid.poke(id.bid.U); target.brobGeneration.poke(id.brobGeneration.U) + } + + private def driveTargetAcks(dut: OOOD3S1Graph): Unit = { + Seq(dut.io.recoveryToD1, dut.io.iex.recovery, dut.io.recoveryToIfu, + dut.io.recoveryToCtu, dut.io.recoveryToLsu).foreach { target => + target.prepared.valid.poke(target.prepare.valid.peek()) + if (target.prepare.valid.peek().litToBoolean) { + target.prepared.bits.poke(target.prepare.bits.peek()) + } + } + } + + private def recover(dut: OOOD3S1Graph, id: Id, transactionId: Int): Unit = { + dut.io.iex.recoveryEvent.bits.poke(0.U.asTypeOf(dut.io.iex.recoveryEvent.bits)) + dut.io.iex.recoveryEvent.bits.transactionId.poke(transactionId.U) + dut.io.iex.recoveryEvent.bits.cause.poke(RecoveryCause.MemoryOrder) + pokeId(dut.io.iex.recoveryEvent.bits.trigger, id) + dut.io.iex.recoveryEvent.valid.poke(true.B) + var sent = false + var applied = false + var cycles = 0 + while (!applied && cycles < 96) { + driveTargetAcks(dut) + sent ||= dut.io.iex.recoveryEvent.ready.peek().litToBoolean + applied = dut.io.recoveryToD1.apply.valid.peek().litToBoolean + dut.clock.step() + if (sent) dut.io.iex.recoveryEvent.valid.poke(false.B) + cycles += 1 + } + assert(sent, s"recovery event $transactionId was not accepted") + assert(applied, s"recovery $transactionId timed out") + } + + test("publishes DEC memory demand as stable full-order metadata") { + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + val first = publishLoad(dut, instructionId = 100) + assert(first.requestCount == 1) + assert(first.firstLsid == 0) + assert(first.firstLid == 0) + assert(first.firstSid == 0) + assert(!first.yostValid) + assert(!first.yoldValid) + val held = dut.io.iex.aguDispatch(0).bits.peek() + dut.clock.step(3) + dut.io.iex.aguDispatch(0).valid.expect(true.B) + dut.io.iex.aguDispatch(0).bits.expect(held) + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + + val peerFirst = publishLoad(dut, instructionId = 200, stid = 1) + assert(peerFirst.firstLsid == 0) + assert(peerFirst.firstLid == 0) + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + + val second = publishLoad(dut, instructionId = 101) + assert(second.firstLsid == 1) + assert(second.firstLid == 1) + assert(second.firstSid == 0) + assert(!second.yostValid) + assert(second.yoldValid) + assert(second.transactionId > first.transactionId) + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + recover(dut, second.id, transactionId = 0x91) + + val peerSecond = publishLoad(dut, instructionId = 201, stid = 1) + assert(peerSecond.firstLsid == 1, + "target-STID recovery must preserve peer LSID") + assert(peerSecond.firstLid == 1, + "target-STID recovery must preserve peer LID") + assert(peerSecond.yoldValid) + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + + val replacement = publishLoad(dut, instructionId = 102) + assert(replacement.firstLsid == 1) + assert(replacement.firstLid == 1) + assert(replacement.firstSid == 0) + assert(replacement.yoldValid) + assert(replacement.transactionId > second.transactionId, + "dispatch transaction IDs must not rewind with memory-order recovery") + } + } + + test("common D3 backpressure preserves one unpublished memory-order prefix") { + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + val first = publishLoad(dut, instructionId = 300) + val held = dut.io.iex.aguDispatch(0).bits.peek() + val tailAfterFirst = dut.io.ridTailSlot(0).peek() + + submitLoad(dut, instructionId = 301) + dut.clock.step(3) + dut.io.ridTailSlot(0).expect(tailAfterFirst) + dut.io.iex.aguDispatch(0).valid.expect(true.B) + dut.io.iex.aguDispatch(0).bits.expect(held) + + dut.io.iex.aguDispatch(0).ready.poke(true.B) + dut.clock.step() + val second = observeLoad(dut) + assert(first.firstLsid == 0) + assert(second.firstLsid == 1) + assert(second.firstLid == 1) + assert(second.transactionId > first.transactionId) + dut.io.ridTailSlot(0).expect(2.U) + } + } + + test("ROB head and exact NFRDY proof authorize one system member once") { + simulate(new OOOD3S1Graph(p)) { dut => + clear(dut) + dut.io.iex.systemDispatch.foreach(_.ready.poke(false.B)) + dut.io.iex.robNoflush.ready.poke(false.B) + submitSystem(dut, instructionId = 400) + + var cycles = 0 + while (!dut.io.iex.systemDispatch(0).valid.peek().litToBoolean && + cycles < 32) { + dut.clock.step(); cycles += 1 + } + assert(cycles < 32) + val dispatch = dut.io.iex.systemDispatch(0).bits + dut.io.iex.robNoflush.valid.expect(false.B, + "ROB head shape is not a legality/drain proof") + + dut.io.iex.robNoflushReady.bits.transactionId.poke( + dispatch.transactionId.peek()) + dut.io.iex.robNoflushReady.bits.instruction.poke( + dispatch.uop.decoded.instruction.parent.identity.peek()) + dut.io.iex.robNoflushReady.bits.rob.poke( + dispatch.uop.decoded.rob.peek()) + dut.io.iex.robNoflushReady.valid.poke(true.B) + dut.io.iex.robNoflush.valid.expect(true.B) + val permit = dut.io.iex.robNoflush.bits.peek() + dut.clock.step(2) + dut.io.iex.robNoflush.valid.expect(true.B) + dut.io.iex.robNoflush.bits.expect(permit) + + dut.io.iex.robNoflush.ready.poke(true.B) + dut.clock.step() + dut.io.iex.robNoflush.valid.expect(false.B, + "the unresolved resident head must not receive a second permit") + dut.io.iex.robNoflushReady.ready.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOOPcBufferIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOOPcBufferIntegrationSpec.scala new file mode 100644 index 00000000..c2678233 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOOPcBufferIntegrationSpec.scala @@ -0,0 +1,16 @@ +package linxcore.ooo + +import circt.stage.ChiselStage +import linxcore.params.ParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class OOOPcBufferIntegrationSpec extends AnyFunSuite { + test("canonical W2 W4 W6 and W8 graphs contain exactly one PC buffer owner") { + Seq(2, 4, 6, 8).foreach { width => + val chirrtl = ChiselStage.emitCHIRRTL( + new OOOD3S1Graph(ParamProfiles.forWidth(width))) + val instance = "inst pcBuffer of OooPcBuffer" + assert(chirrtl.sliding(instance.length).count(_ == instance) == 1) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala b/chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala new file mode 100644 index 00000000..6fd1544d --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala @@ -0,0 +1,2888 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import chisel3.util.{Decoupled, Valid} +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class RobBrobPublicationCoordinatorIO(val p: CoreParams) extends Bundle { + val prepare = Flipped(Decoupled(new D3RenameGroup(p))) + val robPrepared = Output(new OOORobPrepared(p)) + val brobPrepared = Output(new BROBPrepared(p)) + val robCommitReady = Input(Bool()) + val robCommit = Output(new OOORobCommitPreview(p)) + val robCommitValid = Output(Bool()) + val robCommitApply = Input(Bool()) + val robRelease = Flipped(Valid(new OOORobReleaseTxn(p))) + val robReleaseReady = Output(Bool()) + val robReleaseApply = Input(Bool()) + val brobRelease = Flipped(Valid(new BROBReleaseTxn(p))) + val brobReleaseReady = Output(Bool()) + val brobReleaseApply = Input(Bool()) + val robRecoveryPrepare = Flipped(Decoupled(new RecoveryPlan(p))) + val robRecoveryPrepared = Valid(new RecoveryPlan(p)) + val robRecoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val robRecoveryAbort = Flipped(Valid(new RecoveryPlan(p))) + val brobRecoveryPrepare = Flipped(Decoupled(new RecoveryPlan(p))) + val brobRecoveryPrepared = Valid(new RecoveryPlan(p)) + val brobRecoveryApply = Flipped(Valid(new RecoveryPlan(p))) + val brobRecoveryAbort = Flipped(Valid(new RecoveryPlan(p))) +} + +class RobBrobPublicationCoordinator(val p: CoreParams) extends Module { + val io = IO(new RobBrobPublicationCoordinatorIO(p)) + + private val rob = Module(new ROB(p)) + private val brob = Module(new BROB(p)) + + rob.io.candidate.valid := io.prepare.valid + rob.io.candidate.bits := io.prepare.bits + rob.io.prepare.valid := io.prepare.valid + rob.io.prepare.bits := io.prepare.bits + rob.io.publicationTransactionBase := 0.U + brob.io.candidate.valid := io.prepare.valid + brob.io.candidate.bits := io.prepare.bits + brob.io.prepare.valid := io.prepare.valid + brob.io.prepare.bits := io.prepare.bits + rob.io.brobPrepared := brob.io.prepared + brob.io.robPrepared := rob.io.prepared + io.prepare.ready := rob.io.prepare.ready && brob.io.prepare.ready + val publishFire = io.prepare.valid && io.prepare.ready + rob.io.publishFire := publishFire + brob.io.publishFire := publishFire + io.robPrepared := rob.io.prepared + io.brobPrepared := brob.io.prepared + + rob.io.completion.valid := false.B + rob.io.completion.bits := 0.U.asTypeOf(rob.io.completion.bits) + rob.io.commit.ready := io.robCommitReady + io.robCommitValid := rob.io.commit.valid + io.robCommit := rob.io.commit.bits + rob.io.commitApply := io.robCommitApply + + rob.io.release.valid := io.robRelease.valid + rob.io.release.bits := io.robRelease.bits + io.robReleaseReady := rob.io.releaseReady + rob.io.releaseApply := io.robReleaseApply + brob.io.release.valid := io.brobRelease.valid + brob.io.release.bits := io.brobRelease.bits + io.brobReleaseReady := brob.io.releaseReady + brob.io.releaseApply := io.brobReleaseApply + + rob.io.recoveryPrepare.valid := io.robRecoveryPrepare.valid + rob.io.recoveryPrepare.bits := io.robRecoveryPrepare.bits + io.robRecoveryPrepare.ready := rob.io.recoveryPrepare.ready + io.robRecoveryPrepared := rob.io.recoveryPrepared + rob.io.recoveryApply.valid := io.robRecoveryApply.valid + rob.io.recoveryApply.bits := io.robRecoveryApply.bits + rob.io.recoveryAbort.valid := io.robRecoveryAbort.valid + rob.io.recoveryAbort.bits := io.robRecoveryAbort.bits + for (source <- 0 until 2) { + rob.io.recoveryCandidate(source).valid := false.B + rob.io.recoveryCandidate(source).bits := 0.U.asTypeOf( + rob.io.recoveryCandidate(source).bits) + } + + brob.io.recoveryPrepare.valid := io.brobRecoveryPrepare.valid + brob.io.recoveryPrepare.bits := io.brobRecoveryPrepare.bits + io.brobRecoveryPrepare.ready := brob.io.recoveryPrepare.ready + io.brobRecoveryPrepared := brob.io.recoveryPrepared + brob.io.recoveryApply.valid := io.brobRecoveryApply.valid + brob.io.recoveryApply.bits := io.brobRecoveryApply.bits + brob.io.recoveryAbort.valid := io.brobRecoveryAbort.valid + brob.io.recoveryAbort.bits := io.brobRecoveryAbort.bits +} + +class OOORecoverySpec extends AnyFunSuite with ChiselSim { + private def params: CoreParams = { + val base = ParamProfiles.W4 + base.copy( + ooo = base.ooo.copy( + stidCount = 2, + robGroupsPerStid = 4, + maxInstructionsPerRobGroup = 2, + robBankCount = 4, + brobEntriesPerStid = 4, + retireWidth = base.widths.retireWidth, + gprPhysRegs = 64, + gprMapQDepthPerStid = 64, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8)) + } + + private def clearRob(dut: ROB): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.publicationTransactionBase.poke(0.U) + dut.io.completion.valid.poke(false.B) + dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) + dut.io.commit.ready.poke(false.B) + dut.io.commitApply.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + dut.io.recoveryCandidate.foreach { candidate => + candidate.valid.poke(false.B) + candidate.bits.poke(0.U.asTypeOf(candidate.bits)) + } + } + + private def lane( + group: D3RenameGroup, + lane: Int, + id: Int, + rid: Int, + groupCount: Int = -1, + stid: Int = 0, + member: Int = 0, + blockStart: Boolean = false, + blockStop: Boolean = false): Unit = { + group.count.poke((lane + 1).U) + group.memoryOrder.valid.poke(true.B) + group.memoryOrder.stid.poke(stid.U) + group.memoryOrder.count.poke((lane + 1).U) + group.groupCount.poke((if (groupCount >= 0) groupCount else lane + 1).U) + group.groups(lane).valid.poke(true.B) + group.groups(lane).peId.poke(1.U) + group.groups(lane).stid.poke(stid.U) + group.groups(lane).ridSlot.poke(rid.U) + group.groups(lane).ridGeneration.poke(0.U) + val row = group.entries(lane) + row.uop.decoded.valid.poke(true.B) + row.uop.decoded.instruction.parent.identity.peId.poke(1.U) + row.uop.decoded.instruction.parent.identity.stid.poke(stid.U) + row.uop.decoded.instruction.parent.identity.instructionId.poke(id.U) + row.uop.decoded.instruction.parent.identity.epoch.poke(1.U) + row.uop.decoded.rob.peId.poke(1.U) + row.uop.decoded.rob.stid.poke(stid.U) + row.uop.decoded.rob.ridSlot.poke(rid.U) + row.uop.decoded.rob.ridGeneration.poke(0.U) + row.uop.decoded.rob.memberIndex.poke(member.U) + row.uop.decoded.rob.bid.poke(rid.U) + row.uop.decoded.rob.brobGeneration.poke(0.U) + row.blockStart.poke(blockStart.B) + row.blockStop.poke(blockStop.B) + row.history(0).valid.poke(true.B) + } + + private def publish(dut: ROB, count: Int): Seq[RobIdentity] = { + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.brobPrepared.count.poke(count.U) + (0 until count).foreach { laneIndex => + val row = dut.io.prepare.bits.entries(laneIndex) + val continuesPreviousBlock = laneIndex > 0 && + !row.blockStart.peek().litToBoolean + dut.io.brobPrepared.entries(laneIndex).valid.poke(true.B) + dut.io.brobPrepared.entries(laneIndex).stid.poke( + row.uop.decoded.rob.stid.peek()) + dut.io.brobPrepared.entries(laneIndex).bid.poke( + if (continuesPreviousBlock) + dut.io.brobPrepared.entries(laneIndex - 1).bid.peek() + else row.uop.decoded.rob.bid.peek()) + dut.io.brobPrepared.entries(laneIndex).brobGeneration.poke( + if (continuesPreviousBlock) + dut.io.brobPrepared.entries(laneIndex - 1).brobGeneration.peek() + else row.uop.decoded.rob.brobGeneration.peek()) + dut.io.brobPrepared.entries(laneIndex).allocated.poke( + row.blockStart.peek()) + } + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(true.B) + val ids = (0 until count).map(lane => dut.io.prepared.entries(lane).rob.peek()) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + + private def clearRecoveryControl(dut: RecoveryControl): Unit = { + dut.io.events.foreach { event => + event.valid.poke(false.B) + event.bits.poke(0.U.asTypeOf(event.bits)) + } + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts(0)))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.abort.poke(false.B) + dut.io.robCandidateStatus.foreach { status => + status.valid.poke(false.B) + status.bits.poke(0.U.asTypeOf(status.bits)) + } + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepared.bits.poke(0.U.asTypeOf(dut.io.robPrepared.bits)) + dut.io.robAbort.valid.expect(false.B) + (0 until dut.io.targets.length).foreach { target => + dut.io.targets(target).prepare.ready.poke(true.B) + dut.io.targets(target).prepared.valid.poke(false.B) + dut.io.targets(target).prepared.bits.poke(0.U.asTypeOf( + dut.io.targets(target).prepared.bits)) + } + } + + private def clearBrob(dut: BROB): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + + private def bindBrobPrepared( + dut: BROB, + count: Int, + residentGenerations: Seq[Int] = Seq.empty): Seq[RobIdentity] = { + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.robPrepared.count.poke(count.U) + (0 until count).foreach { laneIndex => + dut.io.robPrepared.entries(laneIndex).valid.poke(true.B) + dut.io.robPrepared.entries(laneIndex).rob.poke( + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.peek()) + dut.io.robPrepared.entries(laneIndex).rob.bid.poke( + dut.io.prepared.entries(laneIndex).bid.peek()) + dut.io.robPrepared.entries(laneIndex).rob.brobGeneration.poke( + dut.io.prepared.entries(laneIndex).brobGeneration.peek()) + val residentGeneration = + if (laneIndex < residentGenerations.length) residentGenerations(laneIndex) + else 0 + dut.io.robPrepared.entries(laneIndex).rob.residentGeneration.poke( + residentGeneration.U) + } + (0 until count).map(laneIndex => + dut.io.robPrepared.entries(laneIndex).rob.peek()) + } + + private def pokeBoundRob( + target: RobIdentity, + raw: RobIdentity, + bid: Int, + brobGeneration: Int, + residentGeneration: Int): Unit = { + target.poke(raw) + target.bid.poke(bid.U) + target.brobGeneration.poke(brobGeneration.U) + target.residentGeneration.poke(residentGeneration.U) + } + + private def clearCoordinator(dut: RobBrobPublicationCoordinator): Unit = { + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.robCommitReady.poke(true.B) + dut.io.robCommitApply.poke(false.B) + dut.io.robRelease.valid.poke(false.B) + dut.io.robRelease.bits.poke(0.U.asTypeOf(dut.io.robRelease.bits)) + dut.io.robReleaseApply.poke(false.B) + dut.io.brobRelease.valid.poke(false.B) + dut.io.brobRelease.bits.poke(0.U.asTypeOf(dut.io.brobRelease.bits)) + dut.io.brobReleaseApply.poke(false.B) + dut.io.robRecoveryPrepare.valid.poke(false.B) + dut.io.robRecoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.robRecoveryPrepare.bits)) + dut.io.robRecoveryApply.valid.poke(false.B) + dut.io.robRecoveryApply.bits.poke(0.U.asTypeOf(dut.io.robRecoveryApply.bits)) + dut.io.robRecoveryAbort.valid.poke(false.B) + dut.io.robRecoveryAbort.bits.poke(0.U.asTypeOf(dut.io.robRecoveryAbort.bits)) + dut.io.brobRecoveryPrepare.valid.poke(false.B) + dut.io.brobRecoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.brobRecoveryPrepare.bits)) + dut.io.brobRecoveryApply.valid.poke(false.B) + dut.io.brobRecoveryApply.bits.poke(0.U.asTypeOf(dut.io.brobRecoveryApply.bits)) + dut.io.brobRecoveryAbort.valid.poke(false.B) + dut.io.brobRecoveryAbort.bits.poke(0.U.asTypeOf(dut.io.brobRecoveryAbort.bits)) + } + + private def retireCoordinatorHead( + dut: RobBrobPublicationCoordinator, + count: Int): Unit = { + dut.io.robCommitReady.poke(true.B) + dut.io.robCommitValid.expect(true.B) + dut.io.robCommit.count.expect(count.U) + dut.io.robCommitApply.poke(true.B) + dut.clock.step() + dut.io.robCommitApply.poke(false.B) + } + + private def releaseCoordinator( + dut: RobBrobPublicationCoordinator, + ids: Seq[RobIdentity]): Unit = { + dut.io.robRelease.valid.poke(true.B) + dut.io.robRelease.bits.count.poke(ids.length.U) + dut.io.brobRelease.valid.poke(true.B) + dut.io.brobRelease.bits.count.poke(ids.length.U) + ids.zipWithIndex.foreach { case (id, laneIndex) => + dut.io.robRelease.bits.lanes(laneIndex).valid.poke(true.B) + dut.io.robRelease.bits.lanes(laneIndex).rob.poke(id) + dut.io.brobRelease.bits.entries(laneIndex).poke(id) + } + dut.io.robReleaseReady.expect(true.B) + dut.io.brobReleaseReady.expect(true.B) + dut.io.robReleaseApply.poke(true.B) + dut.io.brobReleaseApply.poke(true.B) + dut.clock.step() + dut.io.robRelease.valid.poke(false.B) + dut.io.robReleaseApply.poke(false.B) + dut.io.brobRelease.valid.poke(false.B) + dut.io.brobReleaseApply.poke(false.B) + } + + private def authorizeCandidate( + dut: RecoveryControl, + source: Int, + transactionId: Int, + stid: Int, + rid: Int, + age: Int, + member: Int = 0, + eligible: Boolean = true, + headTrap: Boolean = false): Unit = { + val status = dut.io.robCandidateStatus(source) + status.valid.poke(true.B) + status.bits.transactionId.poke(transactionId.U) + status.bits.trigger.stid.poke(stid.U) + status.bits.trigger.ridSlot.poke(rid.U) + status.bits.trigger.ridGeneration.poke(0.U) + status.bits.trigger.memberIndex.poke(member.U) + status.bits.eligible.poke(eligible.B) + status.bits.rejected.poke((!eligible).B) + status.bits.ageToken.poke(age.U) + status.bits.headTrap.poke(headTrap.B) + } + + private def driveRecoveryEvent( + dut: RecoveryControl, + source: Int, + transactionId: Int, + cause: RecoveryCause.Type, + stid: Int, + rid: Int, + redirectPc: Int = 0x4000): Unit = { + dut.io.events(source).valid.poke(true.B) + dut.io.events(source).bits.transactionId.poke(transactionId.U) + dut.io.events(source).bits.cause.poke(cause) + dut.io.events(source).bits.trigger.peId.poke(0.U) + dut.io.events(source).bits.trigger.stid.poke(stid.U) + dut.io.events(source).bits.trigger.ridSlot.poke(rid.U) + dut.io.events(source).bits.trigger.ridGeneration.poke(0.U) + dut.io.events(source).bits.trigger.memberIndex.poke(0.U) + dut.io.events(source).bits.redirectPc.poke(redirectPc.U) + dut.io.events(source).bits.instruction.epoch.poke(3.U) + } + + private def preparedFromSeed( + dut: RecoveryControl, + firstKilledRid: Int = 1, + lastKilledRid: Int = 2): Unit = { + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.io.robPrepared.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.robPrepared.bits.firstKilledValid.poke(true.B) + dut.io.robPrepared.bits.firstKilled.poke(dut.io.robPrepare.bits.trigger.peek()) + dut.io.robPrepared.bits.firstKilled.ridSlot.poke(firstKilledRid.U) + dut.io.robPrepared.bits.lastKilled.poke(dut.io.robPrepare.bits.trigger.peek()) + dut.io.robPrepared.bits.lastKilled.ridSlot.poke(lastKilledRid.U) + dut.io.robPrepared.bits.killedGroupCount.poke(2.U) + dut.io.robPrepared.bits.killedMemberCount.poke(2.U) + } + + private def pokePreparedResponse( + dut: RecoveryControl, + transactionId: Int, + cause: RecoveryCause.Type, + peId: Int, + stid: Int, + rid: Int, + ridGeneration: Int, + member: Int, + residentGeneration: Int, + bid: Int, + brobGeneration: Int, + redirectPc: Int, + newEpoch: Int, + phase: RecoveryPhase.Type = RecoveryPhase.Prepare, + firstKilledRid: Int = 1, + lastKilledRid: Int = 2): Unit = { + dut.io.robPrepared.bits.poke(0.U.asTypeOf(dut.io.robPrepared.bits)) + dut.io.robPrepared.bits.transactionId.poke(transactionId.U) + dut.io.robPrepared.bits.phase.poke(phase) + dut.io.robPrepared.bits.cause.poke(cause) + dut.io.robPrepared.bits.trigger.peId.poke(peId.U) + dut.io.robPrepared.bits.trigger.stid.poke(stid.U) + dut.io.robPrepared.bits.trigger.ridSlot.poke(rid.U) + dut.io.robPrepared.bits.trigger.ridGeneration.poke(ridGeneration.U) + dut.io.robPrepared.bits.trigger.memberIndex.poke(member.U) + dut.io.robPrepared.bits.trigger.residentGeneration.poke(residentGeneration.U) + dut.io.robPrepared.bits.trigger.bid.poke(bid.U) + dut.io.robPrepared.bits.trigger.brobGeneration.poke(brobGeneration.U) + dut.io.robPrepared.bits.redirectPc.poke(redirectPc.U) + dut.io.robPrepared.bits.newEpoch.poke(newEpoch.U) + dut.io.robPrepared.bits.firstKilledValid.poke(true.B) + dut.io.robPrepared.bits.firstKilled.peId.poke(peId.U) + dut.io.robPrepared.bits.firstKilled.stid.poke(stid.U) + dut.io.robPrepared.bits.firstKilled.ridSlot.poke(firstKilledRid.U) + dut.io.robPrepared.bits.firstKilled.ridGeneration.poke(ridGeneration.U) + dut.io.robPrepared.bits.lastKilled.peId.poke(peId.U) + dut.io.robPrepared.bits.lastKilled.stid.poke(stid.U) + dut.io.robPrepared.bits.lastKilled.ridSlot.poke(lastKilledRid.U) + dut.io.robPrepared.bits.lastKilled.ridGeneration.poke(ridGeneration.U) + dut.io.robPrepared.bits.killedGroupCount.poke(2.U) + dut.io.robPrepared.bits.killedMemberCount.poke(2.U) + } + + private def pokeRound6SeedEvent(dut: RecoveryControl): Unit = { + driveRecoveryEvent(dut, 0, 0x160, RecoveryCause.MemoryOrder, stid = 0, + rid = 1, redirectPc = 0x4100) + authorizeCandidate(dut, 0, 0x160, stid = 0, rid = 1, age = 1) + dut.io.robPrepared.valid.poke(false.B) + } + + private def pokeRound6Response( + dut: RecoveryControl, + transactionId: Int = 0x160, + cause: RecoveryCause.Type = RecoveryCause.MemoryOrder, + peId: Int = 0, + stid: Int = 0, + rid: Int = 1, + ridGeneration: Int = 0, + member: Int = 0, + residentGeneration: Int = 0, + bid: Int = 0, + brobGeneration: Int = 0, + redirectPc: Int = 0x4100, + newEpoch: Int = 4, + phase: RecoveryPhase.Type = RecoveryPhase.Prepare, + firstKilledRid: Int = 2, + lastKilledRid: Int = 3): Unit = { + pokePreparedResponse(dut, transactionId, cause, peId, stid, rid, + ridGeneration, member, residentGeneration, bid, brobGeneration, + redirectPc, newEpoch, phase, firstKilledRid, lastKilledRid) + } + + private def fireStableRound6Response( + dut: RecoveryControl, + pokeResponse: () => Unit, + maxCycles: Int = 4): Unit = { + dut.io.robPrepared.valid.poke(true.B) + pokeResponse() + var cycles = 0 + while (!dut.io.robPrepared.ready.peek().litToBoolean && cycles < maxCycles) { + dut.clock.step() + cycles += 1 + } + dut.io.robPrepared.ready.expect(true.B) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + } + + test("ROB recovery prepare returns the exact suffix and apply prunes only target STID") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 1, rid = 0, groupCount = 3, stid = 0) + lane(dut.io.prepare.bits, 1, id = 2, rid = 1, groupCount = 3, stid = 0) + lane(dut.io.prepare.bits, 2, id = 3, rid = 2, groupCount = 3, stid = 0) + val ids = publish(dut, 3) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 4, rid = 0, groupCount = 1, stid = 1) + publish(dut, 1) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x44.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(ids(1)) + dut.io.recoveryPrepare.bits.redirectPc.poke(0x1000.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.valid.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilledValid.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilled.ridSlot.expect(1.U) + dut.io.recoveryPrepared.bits.lastKilled.ridSlot.expect(2.U) + dut.io.recoveryPrepared.bits.killedGroupCount.expect(2.U) + dut.io.recoveryPrepared.bits.killedMemberCount.expect(2.U) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(3.U) + + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.ridTailSlot(1).expect(1.U) + } + } + + test("ROB idle_matching_payload does not publish a recovery response") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 1, rid = 0, groupCount = 1, stid = 0) + val resident = publish(dut, 1).head + + // The inactive Decoupled payload is intentionally all-zero and therefore + // matches the first resident identity. Ready may remain combinationally + // high, but a response is illegal until the request is valid. + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke( + 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.trigger.poke(resident) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.valid.expect(false.B) + } + } + + test("ROB reuses the recovered tail as the next commit head after survivor retirement") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 300, rid = 0, groupCount = 3, stid = 0) + lane(dut.io.prepare.bits, 1, id = 301, rid = 1, groupCount = 3, stid = 0) + lane(dut.io.prepare.bits, 2, id = 302, rid = 2, groupCount = 3, stid = 0) + (0 until 3).foreach { index => + dut.io.prepare.bits.entries(index).earlyRobComplete.poke(true.B) + } + val ids = publish(dut, 3) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x160.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids.head) + dut.io.recoveryPrepare.ready.expect(true.B) + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.head.expect(ids.head) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes.head.valid.poke(true.B) + dut.io.release.bits.lanes.head.rob.poke(ids.head) + dut.io.releaseReady.expect(true.B) + dut.io.commit.ready.poke(true.B) + dut.io.commitApply.poke(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.commitApply.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 303, rid = 1, groupCount = 1, stid = 0) + dut.io.prepare.bits.entries.head.earlyRobComplete.poke(true.B) + val redirected = publish(dut, 1).head + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.head.expect(redirected) + dut.io.commit.bits.entries.head.valid.expect(true.B) + dut.io.commit.bits.entries.head.commit.trap.valid.expect(false.B) + } + } + + test("ROB staletrap is absent after recovery removes the last row") { + simulate(new ROB(params)) { dut => + clearRob(dut) + dut.io.commit.ready.poke(true.B) + lane(dut.io.prepare.bits, 0, id = 310, rid = 0, groupCount = 1, + stid = 0) + dut.io.prepare.bits.entries.head.earlyRobComplete.poke(true.B) + dut.io.prepare.bits.entries.head.trap.valid.poke(true.B) + dut.io.prepare.bits.entries.head.trap.cause.poke(7.U) + val id = publish(dut, 1).head + dut.io.commit.valid.expect(true.B) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x162.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Exception) + dut.io.recoveryPrepare.bits.trigger.poke(id) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(id) + dut.io.recoveryPrepare.bits.lastKilled.poke(id) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.commit.valid.expect(false.B) + } + } + + test("branch recovery from member zero kills member one in the same group") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 10, rid = 0, groupCount = 2, stid = 0) + lane(dut.io.prepare.bits, 1, id = 11, rid = 0, groupCount = 2, stid = 0) + dut.io.prepare.bits.entries(1).uop.decoded.rob.memberIndex.poke(1.U) + lane(dut.io.prepare.bits, 2, id = 12, rid = 1, groupCount = 2, stid = 0) + val ids = publish(dut, 3) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x45.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids(0)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilled.memberIndex.expect(1.U) + dut.io.recoveryPrepared.bits.firstKilled.ridSlot.expect(0.U) + dut.io.recoveryPrepared.bits.killedMemberCount.expect(2.U) + } + } + + test("full ROB branch recovery at the youngest member preserves the memory tail") { + val base = params + val p = base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 4, + maxInstructionsPerRobGroup = 1, + robBankCount = 4, + brobEntriesPerStid = 4)) + simulate(new ROB(p)) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + for (laneIndex <- 0 until 4) { + lane(dut.io.prepare.bits, laneIndex, id = 80 + laneIndex, + rid = laneIndex, groupCount = 4, stid = 0, member = 0) + val row = dut.io.prepare.bits.entries(laneIndex) + row.uop.decoded.memory.valid.poke(true.B) + row.uop.decoded.memory.isLoad.poke(true.B) + row.uop.decoded.memory.requestCount.poke(1.U) + row.memoryOrder.requestCount.poke(1.U) + row.memoryOrder.firstLsid.poke(laneIndex.U) + row.memoryOrder.firstLid.poke(laneIndex.U) + } + dut.io.prepare.bits.memoryOrder.after.lsid.poke(4.U) + dut.io.prepare.bits.memoryOrder.after.lid.poke(4.U) + val ids = publish(dut, 4) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x4f.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids.last) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.valid.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilledValid.expect(false.B) + dut.io.recoveryPrepared.bits.killedMemberCount.expect(0.U) + dut.io.recoveryPrepared.bits.killedGroupCount.expect(0.U) + dut.io.recoveryPrepared.bits.survivingTail.expect(ids.last) + dut.io.memoryRecoveryPrepared.oldTail.lsid.expect(4.U) + dut.io.memoryRecoveryPrepared.newTail.lsid.expect(4.U) + dut.io.memoryRecoveryPrepared.oldTail.lid.expect(4.U) + dut.io.memoryRecoveryPrepared.newTail.lid.expect(4.U) + } + } + + test("ROB recovery distinguishes killed members from affected groups") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 20, rid = 0, groupCount = 2, + stid = 0, member = 0) + lane(dut.io.prepare.bits, 1, id = 21, rid = 0, groupCount = 2, + stid = 0, member = 1) + lane(dut.io.prepare.bits, 2, id = 22, rid = 1, groupCount = 2, + stid = 0, member = 0) + val ids = publish(dut, 3) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x51.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids(0)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilled.ridSlot.expect(0.U) + dut.io.recoveryPrepared.bits.firstKilled.memberIndex.expect(1.U) + dut.io.recoveryPrepared.bits.lastKilled.ridSlot.expect(1.U) + dut.io.recoveryPrepared.bits.killedMemberCount.expect(2.U) + dut.io.recoveryPrepared.bits.killedGroupCount.expect(2.U) + dut.io.recoveryPrepared.bits.survivingTailValid.expect(true.B) + dut.io.recoveryPrepared.bits.survivingTail.memberIndex.expect(0.U) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(1.U) + } + } + + test("ROB recovery from member one preserves trigger and kills only younger groups") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 30, rid = 0, groupCount = 2, + stid = 0, member = 0) + lane(dut.io.prepare.bits, 1, id = 31, rid = 0, groupCount = 2, + stid = 0, member = 1) + lane(dut.io.prepare.bits, 2, id = 32, rid = 1, groupCount = 2, + stid = 0, member = 0) + val ids = publish(dut, 3) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x52.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids(1)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.recoveryPrepared.bits.firstKilled.ridSlot.expect(1.U) + dut.io.recoveryPrepared.bits.firstKilled.memberIndex.expect(0.U) + dut.io.recoveryPrepared.bits.killedMemberCount.expect(1.U) + dut.io.recoveryPrepared.bits.killedGroupCount.expect(1.U) + dut.io.recoveryPrepared.bits.survivingTail.memberIndex.expect(1.U) + } + } + + test("BROB recovery preserves older surviving blocks and unrelated STID") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishBlock(id: Int, rid: Int, stid: Int = 0): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = rid, groupCount = 1, + stid = stid, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + clearBrob() + val older = publishBlock(40, 0) + val younger = publishBlock(41, 1) + publishBlock(42, 0, stid = 1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x53.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(younger) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(younger) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(older) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 43, rid = 1, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + } + } + + test("BROB blocks release between retained recovery prepare and apply") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishBlock(id: Int, rid: Int): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = rid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + clearBrob() + val older = publishBlock(50, 0) + val younger = publishBlock(51, 1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x61.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(younger) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(younger) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(older) + dut.io.releaseReady.expect(false.B) + } + } + + test("BROB recovery preserves a partially killed open current block") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + clearBrob() + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 60, rid = 0, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = 61, rid = 0, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = false) + dut.io.prepare.valid.poke(true.B) + val openIds = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + val survivor = openIds(0) + val killed = openIds(1) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x62.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killed) + dut.io.recoveryPrepare.bits.lastKilled.poke(killed) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 62, rid = 0, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val closingIds = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + val closing = closingIds(0) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.entries(0).poke(survivor) + dut.io.release.bits.entries(1).poke(closing) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB reopens a released recovery survivor for redirected closure") { + simulate(new BROB(params)) { dut => + clearBrob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 320, rid = 0, groupCount = 3, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = 321, rid = 1, groupCount = 3, + stid = 0, member = 0, blockStart = false, blockStop = false) + lane(dut.io.prepare.bits, 2, id = 322, rid = 2, groupCount = 3, + stid = 0, member = 0, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val initial = bindBrobPrepared(dut, 3) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x161.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(initial.head) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(initial.head) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(initial(1)) + dut.io.recoveryPrepare.bits.lastKilled.poke(initial(2)) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + dut.io.recoveryPrepare.ready.expect(true.B) + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries.head.poke(initial.head) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + dut.io.debugUsed(0).expect(0.U) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 323, rid = 1, groupCount = 1, + stid = 0, member = 0, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val redirected = bindBrobPrepared(dut, 1).head + dut.io.prepared.entries.head.allocated.expect(true.B) + dut.io.prepared.entries.head.bid.expect(1.U) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + dut.io.debugUsed(0).expect(1.U) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries.head.poke(redirected) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB recovery shortens a closed block that straddles the killed suffix") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishClosedBlock( + baseId: Int, + rid: Int, + stid: Int = 0): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = rid, groupCount = 1, + stid = stid, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = rid, groupCount = 1, + stid = stid, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(rid.U) + dut.io.prepared.entries(1).bid.expect(rid.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + + clearBrob() + val closed = publishClosedBlock(baseId = 70, rid = 0) + val survivor = closed(0) + val killed = closed(1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x63.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killed) + dut.io.recoveryPrepare.bits.lastKilled.poke(killed) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 72, rid = 1, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val nextIds = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(1.U) + dut.io.prepared.entries(0).brobGeneration.expect(0.U) + val next = nextIds(0) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(survivor) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.release.bits.entries(0).poke(next) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB shortened cross-group block releases through its surviving tail") { + simulate(new BROB(params)) { dut => + clearBrob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 80, rid = 0, groupCount = 3, + blockStart = true) + lane(dut.io.prepare.bits, 1, id = 81, rid = 1, groupCount = 3) + lane(dut.io.prepare.bits, 2, id = 82, rid = 2, groupCount = 3, + blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 3) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + val survivor = ids(1) + val killed = ids(2) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x64.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killed) + dut.io.recoveryPrepare.bits.lastKilled.poke(killed) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.entries(0).poke(ids(0)) + dut.io.release.bits.entries(1).poke(survivor) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB recovery reuses wholly killed younger slots after a closed straddler") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishClosedBlock(baseId: Int, bid: Int): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = bid, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(bid.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + def publishSingleBlock(id: Int, bid: Int): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(bid.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + + clearBrob() + val straddler = publishClosedBlock(baseId = 90, bid = 0) + val younger = publishSingleBlock(id = 92, bid = 1) + val survivor = straddler(0) + val killedInsideStraddler = straddler(1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x65.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killedInsideStraddler) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + val first = publishSingleBlock(id = 93, bid = 1) + val second = publishSingleBlock(id = 94, bid = 2) + val third = publishSingleBlock(id = 95, bid = 3) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 96, rid = 0, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(survivor) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.release.bits.entries(0).poke(first) + dut.io.releaseReady.expect(true.B) + dut.io.release.bits.entries(0).poke(second) + dut.io.releaseReady.expect(false.B) + dut.io.release.bits.entries(0).poke(third) + dut.io.releaseReady.expect(false.B) + } + } + + test("BROB recovery computes wrapped straddler successor generation") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishSingleBlock(id: Int, bid: Int, gen: Int): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(bid.U) + dut.io.prepared.entries(0).brobGeneration.expect(gen.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + def releaseOne(rob: RobIdentity): Unit = { + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(rob) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + } + def publishClosedBlock(baseId: Int, bid: Int, gen: Int): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = bid, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.bits.entries(1).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(bid.U) + dut.io.prepared.entries(0).brobGeneration.expect(gen.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + + clearBrob() + releaseOne(publishSingleBlock(id = 100, bid = 0, gen = 0)) + releaseOne(publishSingleBlock(id = 101, bid = 1, gen = 0)) + releaseOne(publishSingleBlock(id = 102, bid = 2, gen = 0)) + val straddler = publishClosedBlock(baseId = 103, bid = 3, gen = 0) + val younger = publishSingleBlock(id = 105, bid = 0, gen = 1) + val survivor = straddler(0) + val killedInsideStraddler = straddler(1) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x66.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killedInsideStraddler) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + val next = publishSingleBlock(id = 106, bid = 0, gen = 1) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(survivor) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.release.bits.entries(0).poke(next) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB recovery rejects malformed suffix BID and generation identities") { + def expectRejected(corrupt: BROB => Unit): Unit = { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishClosedBlock(baseId: Int, bid: Int): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = bid, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + def publishSingleBlock(id: Int, bid: Int): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + + clearBrob() + val straddler = publishClosedBlock(baseId = 110, bid = 0) + val younger = publishSingleBlock(id = 112, bid = 1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x67.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(straddler(0)) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(straddler(0)) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(straddler(1)) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + corrupt(dut) + dut.io.recoveryPrepare.ready.expect(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.entries(0).poke(straddler(0)) + dut.io.release.bits.entries(1).poke(straddler(1)) + dut.io.releaseReady.expect(true.B) + } + } + + expectRejected(_.io.recoveryPrepare.bits.firstKilled.bid.poke(1.U)) + expectRejected(_.io.recoveryPrepare.bits.firstKilled.brobGeneration.poke(1.U)) + expectRejected(_.io.recoveryPrepare.bits.lastKilled.bid.poke(0.U)) + expectRejected(_.io.recoveryPrepare.bits.lastKilled.brobGeneration.poke(1.U)) + expectRejected(_.io.recoveryPrepare.bits.firstKilled.bid.poke( + params.ooo.brobEntriesPerStid.U)) + expectRejected(_.io.recoveryPrepare.bits.lastKilled.bid.poke( + params.ooo.brobEntriesPerStid.U)) + } + + test("BROB recovery rejects stale reused-BID generation after wrap") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + def publishSingleBlock(id: Int, bid: Int, gen: Int): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids(0) + } + def releaseOne(rob: RobIdentity): Unit = { + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(rob) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + } + def publishClosedBlock(baseId: Int, bid: Int, gen: Int): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = bid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = bid, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.bits.entries(1).uop.decoded.rob.brobGeneration.poke(gen.U) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + + clearBrob() + releaseOne(publishSingleBlock(id = 120, bid = 0, gen = 0)) + releaseOne(publishSingleBlock(id = 121, bid = 1, gen = 0)) + releaseOne(publishSingleBlock(id = 122, bid = 2, gen = 0)) + val straddler = publishClosedBlock(baseId = 123, bid = 3, gen = 0) + val younger = publishSingleBlock(id = 125, bid = 0, gen = 1) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x68.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(straddler(0)) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(straddler(0)) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(straddler(1)) + dut.io.recoveryPrepare.bits.lastKilled.poke(younger) + dut.io.recoveryPrepare.bits.lastKilled.brobGeneration.poke(0.U) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + dut.io.recoveryPrepare.ready.expect(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.entries(0).poke(straddler(0)) + dut.io.release.bits.entries(1).poke(straddler(1)) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(younger) + dut.io.releaseReady.expect(true.B) + } + } + + test("BROB publishes allocator-bound identities when D3 residency is unbound") { + simulate(new BROB(params)) { dut => + def publishRawSingle( + id: Int, + rid: Int, + ridGeneration: Int = 0, + residentGeneration: Int = 1): (RobIdentity, Int, Int) = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = id, rid = rid, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.bits.entries(0).uop.decoded.rob.ridGeneration.poke( + ridGeneration.U) + dut.io.prepare.bits.entries(0).uop.decoded.rob.bid.poke(0.U) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(0.U) + dut.io.prepare.bits.entries(0).uop.decoded.rob.residentGeneration.poke(0.U) + dut.io.prepare.valid.poke(true.B) + val bound = bindBrobPrepared(dut, 1, Seq(residentGeneration)) + dut.io.prepare.ready.expect(true.B) + val bid = dut.io.prepared.entries(0).bid.peek().litValue.toInt + val gen = dut.io.prepared.entries(0).brobGeneration.peek().litValue.toInt + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + (bound(0), bid, gen) + } + def releaseOne(raw: RobIdentity, bid: Int, gen: Int): Unit = { + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + pokeBoundRob(dut.io.release.bits.entries(0), raw, bid, gen, + residentGeneration = 1) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + } + def publishRawClosed(baseId: Int): (RobIdentity, RobIdentity, Int, Int) = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = baseId, rid = 3, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = baseId + 1, rid = 3, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + for (laneIndex <- 0 until 2) { + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.bid.poke(0.U) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.brobGeneration.poke(0.U) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.residentGeneration.poke(0.U) + } + dut.io.prepare.valid.poke(true.B) + val bound = bindBrobPrepared(dut, 2, Seq(7, 8)) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(3.U) + dut.io.prepared.entries(1).bid.expect(3.U) + val gen = dut.io.prepared.entries(0).brobGeneration.peek().litValue.toInt + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + (bound(0), bound(1), 3, gen) + } + + clearBrob(dut) + val prefill0 = publishRawSingle(130, rid = 0) + releaseOne(prefill0._1, prefill0._2, prefill0._3) + val prefill1 = publishRawSingle(131, rid = 1) + releaseOne(prefill1._1, prefill1._2, prefill1._3) + val prefill2 = publishRawSingle(132, rid = 2) + releaseOne(prefill2._1, prefill2._2, prefill2._3) + val (survivorRaw, killedRaw, straddlerBid, straddlerGen) = + publishRawClosed(133) + val (youngerRaw, youngerBid, youngerGen) = + publishRawSingle(135, rid = 0, ridGeneration = 1, + residentGeneration = 9) + assert(youngerBid == 0) + assert(youngerGen == 1) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x169.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + pokeBoundRob(dut.io.recoveryPrepare.bits.trigger, survivorRaw, + straddlerBid, straddlerGen, residentGeneration = 7) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + pokeBoundRob(dut.io.recoveryPrepare.bits.survivingTail, survivorRaw, + straddlerBid, straddlerGen, residentGeneration = 7) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + pokeBoundRob(dut.io.recoveryPrepare.bits.firstKilled, killedRaw, + straddlerBid, straddlerGen, residentGeneration = 8) + pokeBoundRob(dut.io.recoveryPrepare.bits.lastKilled, youngerRaw, + youngerBid, youngerGen, residentGeneration = 9) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(2.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(2.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + pokeBoundRob(dut.io.release.bits.entries(0), survivorRaw, straddlerBid, + straddlerGen, residentGeneration = 7) + dut.io.releaseReady.expect(true.B) + } + } + + test("ROB and BROB coordinate bound publication for unbound D3 residency") { + simulate(new RobBrobPublicationCoordinator(params)) { dut => + def publishUnbound( + baseId: Int, + rid: Int, + ridGeneration: Int, + count: Int, + blockStopLast: Boolean): Seq[RobIdentity] = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + for (laneIndex <- 0 until count) { + lane(dut.io.prepare.bits, laneIndex, id = baseId + laneIndex, rid = rid, + groupCount = 1, stid = 0, member = laneIndex, + blockStart = laneIndex == 0, blockStop = blockStopLast && laneIndex == count - 1) + dut.io.prepare.bits.entries(laneIndex).earlyRobComplete.poke(true.B) + dut.io.prepare.bits.entries(laneIndex).brobBound.poke(false.B) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.ridGeneration.poke( + ridGeneration.U) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.bid.poke(0.U) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.brobGeneration.poke(0.U) + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.residentGeneration.poke(0.U) + } + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(true.B) + val ids = (0 until count).map(laneIndex => + dut.io.robPrepared.entries(laneIndex).rob.peek()) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + ids + } + + def publishRetireReleaseSingle( + baseId: Int, + rid: Int, + expectedBid: Int, + expectedBrobGeneration: Int, + expectedResidentGeneration: Int): Unit = { + val ids = publishUnbound(baseId, rid = rid, ridGeneration = 0, + count = 1, blockStopLast = true) + assert(ids.head.bid.litValue == expectedBid) + assert(ids.head.brobGeneration.litValue == expectedBrobGeneration) + assert(ids.head.residentGeneration.litValue == expectedResidentGeneration) + retireCoordinatorHead(dut, 1) + releaseCoordinator(dut, ids) + } + + clearCoordinator(dut) + publishRetireReleaseSingle(140, rid = 0, expectedBid = 0, + expectedBrobGeneration = 0, expectedResidentGeneration = 0) + publishRetireReleaseSingle(141, rid = 1, expectedBid = 1, + expectedBrobGeneration = 0, expectedResidentGeneration = 0) + publishRetireReleaseSingle(142, rid = 2, expectedBid = 2, + expectedBrobGeneration = 0, expectedResidentGeneration = 0) + + val straddler = publishUnbound(143, rid = 3, ridGeneration = 0, + count = 2, blockStopLast = true) + assert(straddler(0).bid.litValue == 3) + assert(straddler(1).bid.litValue == 3) + assert(straddler(0).brobGeneration.litValue == 0) + assert(straddler(1).brobGeneration.litValue == 0) + assert(straddler(0).residentGeneration.litValue == 0) + assert(straddler(1).residentGeneration.litValue == 0) + retireCoordinatorHead(dut, 2) + + val younger = publishUnbound(145, rid = 0, ridGeneration = 1, + count = 1, blockStopLast = true) + assert(younger.head.bid.litValue == 0) + assert(younger.head.brobGeneration.litValue == 1) + assert(younger.head.residentGeneration.litValue == 1) + retireCoordinatorHead(dut, 1) + + dut.io.robRecoveryPrepare.valid.poke(true.B) + dut.io.robRecoveryPrepare.bits.transactionId.poke(0x16a.U) + dut.io.robRecoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.robRecoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.robRecoveryPrepare.bits.trigger.poke(straddler(0)) + dut.io.robRecoveryPrepare.bits.redirectPc.poke(0x6000.U) + dut.io.robRecoveryPrepare.bits.newEpoch.poke(4.U) + dut.io.robRecoveryPrepare.ready.expect(true.B) + dut.io.robRecoveryPrepared.valid.expect(true.B) + dut.io.robRecoveryPrepared.bits.firstKilledValid.expect(true.B) + assert(dut.io.robRecoveryPrepared.bits.firstKilled.peek().litValue === + straddler(1).litValue) + assert(dut.io.robRecoveryPrepared.bits.lastKilled.peek().litValue === + younger.head.litValue) + assert(dut.io.robRecoveryPrepared.bits.survivingTail.peek().litValue === + straddler(0).litValue) + + dut.io.brobRecoveryPrepare.valid.poke(true.B) + dut.io.brobRecoveryPrepare.bits.poke(dut.io.robRecoveryPrepared.bits.peek()) + dut.io.brobRecoveryPrepare.ready.expect(true.B) + dut.clock.step() + val plan = dut.io.robRecoveryPrepared.bits.peek() + dut.io.robRecoveryPrepare.valid.poke(false.B) + dut.io.brobRecoveryPrepare.valid.poke(false.B) + dut.io.robRecoveryApply.valid.poke(true.B) + dut.io.robRecoveryApply.bits.poke(plan) + dut.io.robRecoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.brobRecoveryApply.valid.poke(true.B) + dut.io.brobRecoveryApply.bits.poke(plan) + dut.io.brobRecoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.robRecoveryApply.valid.poke(false.B) + dut.io.brobRecoveryApply.valid.poke(false.B) + + releaseCoordinator(dut, Seq(straddler(0))) + } + } + + test("BROB abort preserves a closed block that straddles recovery") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + clearBrob() + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 80, rid = 0, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = false) + lane(dut.io.prepare.bits, 1, id = 81, rid = 0, groupCount = 1, + stid = 0, member = 1, blockStart = false, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + val survivor = ids(0) + val killed = ids(1) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x64.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(survivor) + dut.io.recoveryPrepare.bits.survivingTailValid.poke(true.B) + dut.io.recoveryPrepare.bits.survivingTail.poke(survivor) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(killed) + dut.io.recoveryPrepare.bits.lastKilled.poke(killed) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + dut.io.recoveryAbort.valid.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.entries(0).poke(survivor) + dut.io.release.bits.entries(1).poke(killed) + dut.io.releaseReady.expect(true.B) + } + } + + test("RecoveryPlanContract ignores only phase and checks wrapped suffix membership") { + simulate(new RecoveryPlanContractProbe(params)) { dut => + dut.io.a.transactionId.poke(7.U) + dut.io.a.phase.poke(RecoveryPhase.Prepare) + dut.io.a.trigger.stid.poke(0.U) + dut.io.a.trigger.peId.poke(1.U) + dut.io.a.trigger.ridSlot.poke(3.U) + dut.io.a.trigger.ridGeneration.poke(2.U) + dut.io.a.firstKilledValid.poke(true.B) + dut.io.a.firstKilled.peId.poke(1.U) + dut.io.a.firstKilled.stid.poke(0.U) + dut.io.a.firstKilled.ridSlot.poke(3.U) + dut.io.a.firstKilled.ridGeneration.poke(2.U) + dut.io.a.firstKilled.memberIndex.poke(1.U) + dut.io.a.lastKilled.peId.poke(1.U) + dut.io.a.lastKilled.stid.poke(0.U) + dut.io.a.lastKilled.ridSlot.poke(1.U) + dut.io.a.lastKilled.ridGeneration.poke(3.U) + dut.io.a.lastKilled.memberIndex.poke(0.U) + dut.io.a.killedGroupCount.poke(3.U) + dut.io.a.killedMemberCount.poke(3.U) + dut.io.b.poke(dut.io.a.peek()) + dut.io.b.phase.poke(RecoveryPhase.Apply) + dut.io.member.stid.poke(0.U) + dut.io.member.peId.poke(1.U) + dut.io.member.ridGeneration.poke(3.U) + dut.io.member.ridSlot.poke(0.U) + dut.io.member.memberIndex.poke(0.U) + dut.io.sameIgnoringPhase.expect(true.B) + dut.io.memberKilled.expect(true.B) + dut.io.legalWindow.expect(true.B) + + dut.io.member.ridGeneration.poke(1.U) + dut.io.memberKilled.expect(false.B) + dut.io.member.ridGeneration.poke(2.U) + dut.io.member.ridSlot.poke(3.U) + dut.io.member.memberIndex.poke(0.U) + dut.io.memberKilled.expect(false.B) + } + } + + test("RecoveryControl waits for three identical prepares and emits one common apply") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0x80.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(1.U) + dut.io.events(0).bits.redirectPc.poke(0x2000.U) + authorizeCandidate(dut, 0, 0x80, stid = 0, rid = 1, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.trigger.ridSlot.expect(1.U) + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.io.robPrepared.bits.firstKilledValid.poke(true.B) + dut.io.robPrepared.bits.firstKilled.ridSlot.poke(1.U) + dut.io.robPrepared.bits.lastKilled.ridSlot.poke(2.U) + dut.io.robPrepared.bits.killedGroupCount.poke(2.U) + dut.io.robPrepared.bits.killedMemberCount.poke(2.U) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + (0 until 3).foreach { target => + dut.io.targets(target).prepare.valid.expect(true.B) + dut.io.targets(target).apply.valid.expect(false.B) + } + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.io.targets(1).prepared.valid.poke(true.B) + dut.io.targets(1).prepared.bits.poke(dut.io.targets(1).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(2).prepared.valid.poke(true.B) + dut.io.targets(2).prepared.bits.poke(dut.io.targets(2).prepare.bits.peek()) + dut.clock.step() + (0 until 3).foreach { target => + dut.io.targets(target).apply.valid.expect(true.B) + dut.io.targets(target).apply.bits.transactionId.expect(0x80.U) + } + dut.clock.step() + } + } + + test("abort is non-mutating for a retained recovery transaction") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0x90.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.Debug) + dut.io.events(0).bits.trigger.stid.poke(0.U) + authorizeCandidate(dut, 0, 0x90, stid = 0, rid = 0, age = 1) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + dut.io.abort.poke(true.B) + dut.clock.step() + dut.io.targets(0).abort.valid.expect(true.B) + dut.io.targets(0).abort.bits.phase.expect(RecoveryPhase.Abort) + } + } + + test("RecoveryControl retains source one and selects the older retained event") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(1).valid.poke(true.B) + dut.io.events(1).bits.transactionId.poke(0xa1.U) + dut.io.events(1).bits.cause.poke(RecoveryCause.Branch) + dut.io.events(1).bits.trigger.stid.poke(0.U) + dut.io.events(1).bits.trigger.ridSlot.poke(1.U) + authorizeCandidate(dut, 1, 0xa1, stid = 0, rid = 1, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xa1.U) + + dut.io.robPrepare.ready.poke(false.B) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xa0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(3.U) + dut.clock.step() + dut.io.events(1).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xa1.U) + } + } + + test("RecoveryControl sends prepare once per target and ignores mismatched acknowledgements") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xb0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + authorizeCandidate(dut, 0, 0xb0, stid = 0, rid = 0, age = 1) + (0 until 3).foreach { target => + dut.io.targets(target).prepare.ready.poke(target != 2) + dut.io.targets(target).prepared.valid.poke(false.B) + dut.io.targets(target).prepared.bits.poke(0.U.asTypeOf( + dut.io.targets(target).prepared.bits)) + } + dut.clock.step() + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(1).prepare.valid.expect(true.B) + dut.clock.step() + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.targets(1).prepare.valid.expect(false.B) + dut.io.targets(2).prepare.valid.expect(true.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.io.targets(0).prepared.bits.transactionId.poke(0xff.U) + dut.io.targets(1).prepared.valid.poke(true.B) + dut.io.targets(1).prepared.bits.poke(dut.io.targets(1).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(2).prepare.ready.poke(true.B) + dut.io.targets(0).prepared.bits.transactionId.poke(0xb0.U) + dut.io.targets(2).prepared.valid.poke(true.B) + dut.io.targets(2).prepared.bits.poke(dut.io.targets(2).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(true.B) + } + } + + test("RecoveryControl ignores target acknowledgements before prepare fires") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xb1.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + authorizeCandidate(dut, 0, 0xb1, stid = 0, rid = 0, age = 1) + dut.io.targets(0).prepare.ready.poke(false.B) + dut.clock.step() + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(0).prepare.ready.poke(true.B) + dut.io.targets(0).prepared.valid.poke(false.B) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.io.targets(0).prepared.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(0).prepared.bits.phase.poke(RecoveryPhase.Prepare) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(true.B) + } + } + + test("RecoveryControl does not carry stale target acknowledgements across abort retry") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xb2.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + authorizeCandidate(dut, 0, 0xb2, stid = 0, rid = 0, age = 1) + dut.io.targets(0).prepare.ready.poke(false.B) + dut.clock.step() + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.clock.step() + dut.io.abort.poke(true.B) + dut.clock.step() + dut.io.abort.poke(false.B) + dut.io.targets(0).prepared.valid.poke(false.B) + dut.io.targets(0).apply.valid.expect(false.B) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + } + + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.robPrepare.ready.poke(false.B) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xb3.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(1.U) + authorizeCandidate(dut, 0, 0xb3, stid = 0, rid = 1, age = 1) + dut.io.targets(0).prepare.ready.poke(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.io.robPrepare.ready.poke(true.B) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.io.targets(0).prepared.bits.transactionId.poke(0xb2.U) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.clock.step() + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(true.B) + } + } + + test("RecoveryControl drains held matching target acknowledgements before retry") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + def startAttempt(): Unit = { + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xb4.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(0.U) + authorizeCandidate(dut, 0, 0xb4, stid = 0, rid = 0, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + } + + def preparedPlanFromRequest(): RecoveryPlan = { + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.io.robPrepared.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.robPrepared.bits.firstKilledValid.poke(true.B) + dut.io.robPrepared.bits.firstKilled.poke(dut.io.robPrepare.bits.trigger.peek()) + dut.io.robPrepared.bits.firstKilled.ridSlot.poke(0.U) + dut.io.robPrepared.bits.lastKilled.poke(dut.io.robPrepare.bits.trigger.peek()) + dut.io.robPrepared.bits.lastKilled.ridSlot.poke(0.U) + dut.io.robPrepared.bits.killedGroupCount.poke(1.U) + dut.io.robPrepared.bits.killedMemberCount.poke(1.U) + dut.io.robPrepared.bits.peek() + } + + def holdMatchingTargetPrepared(plan: RecoveryPlan): Unit = { + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(plan) + dut.io.targets(0).prepared.bits.phase.poke(RecoveryPhase.Prepare) + } + + def acceptRobPlanWhileHoldingTarget(plan: RecoveryPlan): Unit = { + holdMatchingTargetPrepared(plan) + dut.io.targets(0).prepared.ready.expect(true.B) + dut.clock.step() + dut.io.targets(0).prepared.valid.poke(false.B) + } + + clearRecoveryControl(dut) + startAttempt() + val firstPlan = preparedPlanFromRequest() + acceptRobPlanWhileHoldingTarget(firstPlan) + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.abort.poke(true.B) + dut.clock.step() + dut.io.abort.poke(false.B) + dut.io.targets(0).prepared.valid.poke(false.B) + dut.io.targets(0).apply.valid.expect(false.B) + dut.clock.step() + + startAttempt() + val retryPlan = preparedPlanFromRequest() + acceptRobPlanWhileHoldingTarget(retryPlan) + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + + dut.io.targets(0).prepared.valid.poke(false.B) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(false.B) + holdMatchingTargetPrepared(retryPlan) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(true.B) + } + } + + test("RecoveryControl selects precise trap before interrupt and gates interrupt at boundary") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xc0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.Exception) + dut.io.events(0).bits.trap.valid.poke(true.B) + dut.io.events(0).bits.trigger.ridSlot.poke(0.U) + authorizeCandidate(dut, 0, 0xc0, stid = 0, rid = 0, age = 1, + headTrap = true) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.ridSlot.poke(0.U) + dut.io.robPrepare.ready.poke(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.cause.expect(RecoveryCause.Exception) + dut.io.events(0).valid.poke(false.B) + dut.io.abort.poke(true.B) + dut.clock.step() + dut.io.abort.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + dut.io.interruptBoundaryValid.poke(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.cause.expect(RecoveryCause.Interrupt) + } + } + + test("RecoveryControl does not let enum Exception outrank an older ordinary event") { + simulate(new RecoveryControl(params, targetCount = 3)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xe0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.Exception) + dut.io.events(0).bits.trigger.stid.poke(1.U) + dut.io.events(0).bits.trigger.ridSlot.poke(3.U) + dut.io.events(1).valid.poke(true.B) + dut.io.events(1).bits.transactionId.poke(0xe1.U) + dut.io.events(1).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(1).bits.trigger.stid.poke(0.U) + dut.io.events(1).bits.trigger.ridSlot.poke(1.U) + authorizeCandidate(dut, 0, 0xe0, stid = 1, rid = 3, age = 5) + authorizeCandidate(dut, 1, 0xe1, stid = 0, rid = 1, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xe1.U) + dut.io.robPrepare.bits.cause.expect(RecoveryCause.MemoryOrder) + } + } + + test("RecoveryControl does not deadlock on stale source zero when source one can be eligible") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xf0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(3.U) + dut.io.events(1).valid.poke(true.B) + dut.io.events(1).bits.transactionId.poke(0xf1.U) + dut.io.events(1).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(1).bits.trigger.stid.poke(1.U) + dut.io.events(1).bits.trigger.ridSlot.poke(0.U) + authorizeCandidate(dut, 0, 0xf0, stid = 0, rid = 3, age = 1, + eligible = false) + authorizeCandidate(dut, 1, 0xf1, stid = 1, rid = 0, age = 0) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xf1.U) + } + } + + test("RecoveryControl waits for every active producer status before selecting") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xd0.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(2.U) + dut.io.events(1).valid.poke(true.B) + dut.io.events(1).bits.transactionId.poke(0xd1.U) + dut.io.events(1).bits.cause.poke(RecoveryCause.Branch) + dut.io.events(1).bits.trigger.stid.poke(0.U) + dut.io.events(1).bits.trigger.ridSlot.poke(1.U) + authorizeCandidate(dut, 0, 0xd0, stid = 0, rid = 2, age = 5) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + dut.io.robCandidateStatus(0).valid.poke(false.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + authorizeCandidate(dut, 1, 0xd1, stid = 0, rid = 1, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xd1.U) + } + } + + test("RecoveryControl retains an early status until a slower peer resolves") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xd2.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(3.U) + dut.io.events(1).valid.poke(true.B) + dut.io.events(1).bits.transactionId.poke(0xd3.U) + dut.io.events(1).bits.cause.poke(RecoveryCause.Branch) + dut.io.events(1).bits.trigger.stid.poke(0.U) + dut.io.events(1).bits.trigger.ridSlot.poke(0.U) + authorizeCandidate(dut, 1, 0xd3, stid = 0, rid = 0, age = 1) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + dut.io.robCandidateStatus(1).valid.poke(false.B) + authorizeCandidate(dut, 0, 0xd2, stid = 0, rid = 3, age = 5) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0xd3.U) + } + } + + test("RecoveryControl does not let interrupt bypass an unresolved producer") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0xd4.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.events(0).bits.trigger.ridSlot.poke(1.U) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).priority.poke(3.U) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + authorizeCandidate(dut, 0, 0xd4, stid = 0, rid = 1, age = 1, + eligible = false) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.cause.expect(RecoveryCause.Interrupt) + } + } + + test("ROB ignores wrong-phase and duplicate recovery apply without mutating twice") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 200, rid = 0, groupCount = 2, + stid = 0) + lane(dut.io.prepare.bits, 1, id = 201, rid = 1, groupCount = 2, + stid = 0) + val ids = publish(dut, 2) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x120.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(ids(1)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Prepare) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x121.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(ids(1)) + dut.io.recoveryPrepare.ready.expect(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(1.U) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x122.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids(0)) + dut.io.recoveryPrepare.ready.expect(true.B) + } + } + + test("ROB abort clears only the matching retained recovery transaction") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 210, rid = 0, groupCount = 1, + stid = 0) + val id = publish(dut, 1).head + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x130.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(id) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.transactionId.poke(0x131.U) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.poke(prepared) + dut.io.recoveryPrepare.bits.transactionId.poke(0x132.U) + dut.io.recoveryPrepare.ready.expect(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.poke(prepared) + dut.io.recoveryPrepare.bits.transactionId.poke(0x133.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.io.ridTailSlot(0).expect(1.U) + } + } + + test("BROB abort clears matching retained recovery and leaves state releasable") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + clearBrob() + lane(dut.io.prepare.bits, 0, id = 220, rid = 0, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + val id = ids(0) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x140.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(id) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(id) + dut.io.recoveryPrepare.bits.lastKilled.poke(id) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.transactionId.poke(0x141.U) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 221, rid = 1, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(id) + dut.io.releaseReady.expect(true.B) + } + } + + test("RecoveryControl abort before ROB request fire cancels without terminals") { + simulate(new RecoveryControl(params, targetCount = 2)) { dut => + clearRecoveryControl(dut) + driveRecoveryEvent(dut, 0, 0x150, RecoveryCause.MemoryOrder, stid = 0, + rid = 1) + authorizeCandidate(dut, 0, 0x150, stid = 0, rid = 1, age = 1) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.abort.poke(true.B) + dut.io.robPrepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.targets(1).abort.valid.expect(false.B) + dut.clock.step() + + dut.io.abort.poke(false.B) + driveRecoveryEvent(dut, 0, 0x151, RecoveryCause.Branch, stid = 0, + rid = 2) + authorizeCandidate(dut, 0, 0x151, stid = 0, rid = 2, age = 2) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0x151.U) + } + } + + test("RecoveryControl abort after ROB request waits for exact ROB abort plan") { + simulate(new RecoveryControl(params, targetCount = 2)) { dut => + clearRecoveryControl(dut) + driveRecoveryEvent(dut, 0, 0x152, RecoveryCause.MemoryOrder, stid = 0, + rid = 1) + authorizeCandidate(dut, 0, 0x152, stid = 0, rid = 1, age = 1) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepare.valid.expect(true.B) + dut.clock.step() + dut.io.abort.poke(true.B) + dut.io.robAbort.valid.expect(false.B) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.targets(1).abort.valid.expect(false.B) + dut.clock.step() + + dut.io.robPrepared.valid.poke(true.B) + preparedFromSeed(dut, firstKilledRid = 1, lastKilledRid = 2) + dut.clock.step() + dut.io.robAbort.valid.expect(true.B) + dut.io.robAbort.bits.transactionId.expect(0x152.U) + dut.io.robAbort.bits.phase.expect(RecoveryPhase.Abort) + dut.io.robAbort.bits.firstKilledValid.expect(true.B) + dut.io.robAbort.bits.firstKilled.ridSlot.expect(1.U) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.targets(1).abort.valid.expect(false.B) + + dut.io.abort.poke(false.B) + dut.io.robPrepared.valid.poke(false.B) + dut.clock.step() + driveRecoveryEvent(dut, 0, 0x153, RecoveryCause.Branch, stid = 0, + rid = 3) + authorizeCandidate(dut, 0, 0x153, stid = 0, rid = 3, age = 3) + dut.clock.step() + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepare.bits.transactionId.expect(0x153.U) + } + } + + test("RecoveryControl final target ack with abort emits only abort") { + simulate(new RecoveryControl(params, targetCount = 2)) { dut => + clearRecoveryControl(dut) + driveRecoveryEvent(dut, 0, 0x154, RecoveryCause.MemoryOrder, stid = 0, + rid = 1) + authorizeCandidate(dut, 0, 0x154, stid = 0, rid = 1, age = 1) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + preparedFromSeed(dut, firstKilledRid = 1, lastKilledRid = 2) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + (0 until 2).foreach { target => + dut.io.targets(target).prepared.valid.poke(true.B) + dut.io.targets(target).prepared.bits.poke( + dut.io.targets(target).prepare.bits.peek()) + } + dut.io.abort.poke(true.B) + dut.clock.step() + + dut.io.targets(0).apply.valid.expect(false.B) + dut.io.targets(1).apply.valid.expect(false.B) + dut.io.targets(0).abort.valid.expect(true.B) + dut.io.targets(1).abort.valid.expect(true.B) + dut.io.robAbort.valid.expect(true.B) + dut.io.robAbort.bits.transactionId.expect(0x154.U) + } + } + + test("RecoveryControl abort during visible apply does not schedule post-apply abort") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + driveRecoveryEvent(dut, 0, 0x155, RecoveryCause.MemoryOrder, stid = 0, + rid = 1) + authorizeCandidate(dut, 0, 0x155, stid = 0, rid = 1, age = 1) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + preparedFromSeed(dut, firstKilledRid = 1, lastKilledRid = 1) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + dut.io.targets(0).prepared.valid.poke(true.B) + dut.io.targets(0).prepared.bits.poke(dut.io.targets(0).prepare.bits.peek()) + dut.clock.step() + dut.io.targets(0).apply.valid.expect(true.B) + dut.io.abort.poke(true.B) + dut.clock.step() + dut.io.abort.poke(false.B) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + } + } + + test("RecoveryControl ignores unsolicited ROB response before request fires") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + pokeRound6SeedEvent(dut) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(false.B) + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.robPrepare.valid.expect(true.B) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + + dut.io.robPrepare.ready.poke(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepare.bits.transactionId.expect(0x160.U) + dut.io.targets(0).prepare.bits.firstKilled.ridSlot.expect(2.U) + } + } + + test("RecoveryControl drains held ROB response when abort suppresses request") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + pokeRound6SeedEvent(dut) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(false.B) + dut.io.abort.poke(true.B) + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.robPrepare.valid.expect(false.B) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + + dut.io.abort.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + pokeRound6SeedEvent(dut) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.clock.step() + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepare.bits.transactionId.expect(0x160.U) + dut.io.targets(0).prepare.bits.firstKilled.ridSlot.expect(2.U) + } + } + + test("RecoveryControl drains same-cycle mismatched ROB response while request fires once") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + pokeRound6SeedEvent(dut) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(true.B) + pokeRound6Response(dut, transactionId = 0x161) + dut.io.robPrepare.valid.expect(true.B) + dut.io.robPrepared.ready.expect(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + + dut.io.robPrepared.valid.poke(false.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepare.bits.transactionId.expect(0x160.U) + dut.io.targets(0).prepare.bits.firstKilled.ridSlot.expect(2.U) + } + } + + test("RecoveryControl waits through mismatched ROB responses in WaitRob") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + pokeRound6SeedEvent(dut) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepare.valid.expect(true.B) + dut.clock.step() + dut.io.robPrepare.valid.expect(false.B) + + val mismatches = Seq[() => Unit]( + () => pokeRound6Response(dut, transactionId = 0x161), + () => pokeRound6Response(dut, cause = RecoveryCause.Branch), + () => pokeRound6Response(dut, peId = 1), + () => pokeRound6Response(dut, stid = 1), + () => pokeRound6Response(dut, rid = 2), + () => pokeRound6Response(dut, ridGeneration = 1), + () => pokeRound6Response(dut, member = 1), + () => pokeRound6Response(dut, residentGeneration = 1), + () => pokeRound6Response(dut, bid = 1), + () => pokeRound6Response(dut, brobGeneration = 1), + () => pokeRound6Response(dut, redirectPc = 0x4200), + () => pokeRound6Response(dut, newEpoch = 5), + () => pokeRound6Response(dut, phase = RecoveryPhase.Apply)) + mismatches.foreach { pokeMismatch => + fireStableRound6Response(dut, pokeMismatch) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + dut.io.robPrepare.valid.expect(false.B) + } + + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.targets(0).prepare.valid.expect(true.B) + dut.io.targets(0).prepare.bits.transactionId.expect(0x160.U) + dut.io.targets(0).prepare.bits.firstKilled.ridSlot.expect(2.U) + dut.io.targets(0).prepare.bits.lastKilled.ridSlot.expect(3.U) + } + } + + test("RecoveryControl waits through mismatched ROB responses in WaitRobAbort") { + simulate(new RecoveryControl(params, targetCount = 1)) { dut => + clearRecoveryControl(dut) + pokeRound6SeedEvent(dut) + dut.clock.step() + + dut.io.events(0).valid.poke(false.B) + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepare.valid.expect(true.B) + dut.clock.step() + dut.io.abort.poke(true.B) + dut.clock.step() + + val mismatches = Seq[() => Unit]( + () => pokeRound6Response(dut, transactionId = 0x161), + () => pokeRound6Response(dut, cause = RecoveryCause.Branch), + () => pokeRound6Response(dut, peId = 1), + () => pokeRound6Response(dut, stid = 1), + () => pokeRound6Response(dut, rid = 2), + () => pokeRound6Response(dut, ridGeneration = 1), + () => pokeRound6Response(dut, member = 1), + () => pokeRound6Response(dut, residentGeneration = 1), + () => pokeRound6Response(dut, bid = 1), + () => pokeRound6Response(dut, brobGeneration = 1), + () => pokeRound6Response(dut, redirectPc = 0x4200), + () => pokeRound6Response(dut, newEpoch = 5), + () => pokeRound6Response(dut, phase = RecoveryPhase.Abort)) + mismatches.foreach { pokeMismatch => + fireStableRound6Response(dut, pokeMismatch) + dut.io.targets(0).prepare.valid.expect(false.B) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.robAbort.valid.expect(false.B) + dut.io.robPrepare.valid.expect(false.B) + } + + fireStableRound6Response(dut, + () => pokeRound6Response(dut, firstKilledRid = 2, lastKilledRid = 3)) + dut.io.robAbort.valid.expect(true.B) + dut.io.robAbort.bits.transactionId.expect(0x160.U) + dut.io.robAbort.bits.phase.expect(RecoveryPhase.Abort) + dut.io.robAbort.bits.firstKilled.ridSlot.expect(2.U) + dut.io.targets(0).abort.valid.expect(false.B) + dut.io.targets(0).prepare.valid.expect(false.B) + } + } + + test("ROB simultaneous matching apply and abort is non-mutating") { + simulate(new ROB(params)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 230, rid = 0, groupCount = 2, + stid = 0) + lane(dut.io.prepare.bits, 1, id = 231, rid = 1, groupCount = 2, + stid = 0) + val ids = publish(dut, 2) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x156.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(ids(1)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.ridTailSlot(0).expect(2.U) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.poke(prepared) + dut.io.recoveryPrepare.bits.transactionId.poke(0x157.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.ready.expect(true.B) + } + } + + test("BROB simultaneous matching apply and abort is non-mutating") { + simulate(new BROB(params)) { dut => + def clearBrob(): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + clearBrob() + lane(dut.io.prepare.bits, 0, id = 240, rid = 0, groupCount = 1, + stid = 0, member = 0, blockStart = true, blockStop = true) + dut.io.prepare.valid.poke(true.B) + val ids = bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + val id = ids(0) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x158.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.recoveryPrepare.bits.trigger.poke(id) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.poke(id) + dut.io.recoveryPrepare.bits.lastKilled.poke(id) + dut.io.recoveryPrepare.bits.killedMemberCount.poke(1.U) + dut.io.recoveryPrepare.bits.killedGroupCount.poke(1.U) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + val prepared = dut.io.recoveryPrepared.bits.peek() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(prepared) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recoveryAbort.valid.poke(true.B) + dut.io.recoveryAbort.bits.poke(prepared) + dut.io.recoveryAbort.bits.phase.poke(RecoveryPhase.Abort) + dut.clock.step() + + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).poke(id) + dut.io.releaseReady.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala b/chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala new file mode 100644 index 00000000..58b09c1b --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala @@ -0,0 +1,1270 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class OOORobCommitSpec extends AnyFunSuite with ChiselSim { + private def params(width: Int, stids: Int = 1): CoreParams = { + val base = ParamProfiles.forWidth(width) + val groups = Iterator.iterate(1)(_ * 2).dropWhile(_ < math.max(4, width)).next() + base.copy( + ooo = base.ooo.copy( + stidCount = stids, + stidIdentityEntries = math.max(2, stids), + robGroupsPerStid = groups, + maxInstructionsPerRobGroup = 2, + robBankCount = groups, + brobEntriesPerStid = 4, + retireWidth = base.widths.retireWidth, + gprPhysRegs = if (stids == 1 && width <= 4) 32 else 64, + gprMapQDepthPerStid = if (stids == 1 && width <= 4) 32 else 64, + tPhysRegs = math.max(8, groups * 2), + uPhysRegs = math.max(8, groups * 2), + tuMapQDepthPerStid = math.max(16, groups * 2))) + } + + private def clearRob(dut: ROB): Unit = { + dut.io.candidate.valid.poke(false.B) + dut.io.candidate.bits.poke(0.U.asTypeOf(dut.io.candidate.bits)) + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publicationTransactionBase.poke(0.U) + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.publishFire.poke(false.B) + dut.io.completion.valid.poke(false.B) + dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) + dut.io.storeBinding.foreach { binding => + binding.valid.poke(false.B) + binding.bits.poke(0.U.asTypeOf(binding.bits)) + } + dut.io.commit.ready.poke(true.B) + dut.io.commitApply.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + dut.io.recoveryCandidate.foreach { candidate => + candidate.valid.poke(false.B) + candidate.bits.poke(0.U.asTypeOf(candidate.bits)) + } + } + + private def clearCommitControlExtensions(dut: CommitControl): Unit = { + dut.io.residentHeads.foreach(_.poke(0.U.asTypeOf(dut.io.residentHeads.head))) + dut.io.recoveryFence.foreach(_.poke(false.B)) + dut.io.pcBufferCommitReady.poke(true.B) + dut.io.debugRequest.valid.poke(false.B) + dut.io.debugRequest.bits.poke(0.U.asTypeOf(dut.io.debugRequest.bits)) + dut.io.debugResponse.ready.poke(true.B) + dut.io.robNoflushReady.valid.poke(false.B) + dut.io.robNoflushReady.bits.poke(0.U.asTypeOf(dut.io.robNoflushReady.bits)) + dut.io.robNoflush.ready.poke(false.B) + } + + private def clearBrob(dut: BROB): Unit = { + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recoveryAbort.valid.poke(false.B) + dut.io.recoveryAbort.bits.poke(0.U.asTypeOf(dut.io.recoveryAbort.bits)) + } + + private def bindBrobPrepared( + dut: BROB, + count: Int): Seq[RobIdentity] = { + dut.io.robPrepared.poke(0.U.asTypeOf(dut.io.robPrepared)) + dut.io.robPrepared.count.poke(count.U) + (0 until count).foreach { laneIndex => + dut.io.robPrepared.entries(laneIndex).valid.poke(true.B) + dut.io.robPrepared.entries(laneIndex).rob.poke( + dut.io.prepare.bits.entries(laneIndex).uop.decoded.rob.peek()) + dut.io.robPrepared.entries(laneIndex).rob.bid.poke( + dut.io.prepared.entries(laneIndex).bid.peek()) + dut.io.robPrepared.entries(laneIndex).rob.brobGeneration.poke( + dut.io.prepared.entries(laneIndex).brobGeneration.peek()) + } + (0 until count).map(laneIndex => + dut.io.robPrepared.entries(laneIndex).rob.peek()) + } + + private def lane( + group: D3RenameGroup, + lane: Int, + id: Int, + rid: Int, + member: Int, + early: Boolean = false, + boundary: Boolean = false, + blockStart: Boolean = false, + blockStop: Boolean = false, + secondDest: Boolean = false, + groupCount: Int = -1, + stid: Int = 0): Unit = { + group.count.poke((lane + 1).U) + group.groupCount.poke((if (groupCount >= 0) groupCount else lane + 1).U) + group.memoryOrder.valid.poke(true.B) + group.memoryOrder.stid.poke(stid.U) + group.memoryOrder.count.poke((lane + 1).U) + if (rid < group.groups.length) { + group.groups(rid).valid.poke(true.B) + group.groups(rid).peId.poke(1.U) + group.groups(rid).stid.poke(stid.U) + group.groups(rid).ridSlot.poke(rid.U) + group.groups(rid).ridGeneration.poke(0.U) + } + val row = group.entries(lane) + row.uop.decoded.valid.poke(true.B) + row.uop.decoded.instruction.parent.identity.peId.poke(1.U) + row.uop.decoded.instruction.parent.identity.stid.poke(stid.U) + row.uop.decoded.instruction.parent.identity.instructionId.poke(id.U) + row.uop.decoded.instruction.parent.identity.epoch.poke(3.U) + row.uop.decoded.rob.peId.poke(1.U) + row.uop.decoded.rob.stid.poke(stid.U) + row.uop.decoded.rob.ridSlot.poke(rid.U) + row.uop.decoded.rob.ridGeneration.poke(0.U) + row.uop.decoded.rob.memberIndex.poke(member.U) + row.uop.decoded.blockBoundary.poke(boundary.B) + row.uop.destinations(0).valid.poke(true.B) + row.uop.destinations(0).kind.poke(OperandKind.Gpr) + row.uop.destinations(0).atag.poke(1.U) + row.history(0).valid.poke(true.B) + row.history(0).kind.poke(OperandKind.Gpr) + row.history(0).atag.poke(1.U) + row.history(0).ptag.poke(((8 + id) % 24).U) + row.history(0).previousPtag.poke(1.U) + if (secondDest) { + row.uop.destinations(1).valid.poke(true.B) + row.uop.destinations(1).kind.poke(OperandKind.Gpr) + row.uop.destinations(1).atag.poke(2.U) + row.history(1).valid.poke(true.B) + row.history(1).kind.poke(OperandKind.Gpr) + row.history(1).atag.poke(2.U) + row.history(1).ptag.poke(((18 + id) % 24).U) + row.history(1).previousPtag.poke(2.U) + } + row.earlyRobComplete.poke(early.B) + row.residentBound.poke(false.B) + row.brobBound.poke(false.B) + row.blockStart.poke(blockStart.B) + row.blockStop.poke(blockStop.B) + row.uop.decoded.immediateValid.poke(blockStart.B) + row.uop.decoded.immediate.poke((if (blockStop) 1 else 0).U) + } + + private def publish(dut: ROB, count: Int): Seq[RobIdentity] = { + bindBrobPrepared(dut, count) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(true.B) + (0 until count).foreach { lane => + dut.io.prepared.entries(lane).valid.expect(true.B) + } + val ids = (0 until count).map(lane => dut.io.prepared.entries(lane).rob.peek()) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + ids + } + + private def bindBrobPrepared(dut: ROB, count: Int): Unit = { + dut.io.brobPrepared.poke(0.U.asTypeOf(dut.io.brobPrepared)) + dut.io.brobPrepared.count.poke(count.U) + (0 until count).foreach { laneIndex => + val row = dut.io.prepare.bits.entries(laneIndex) + val continuesPreviousBlock = laneIndex > 0 && + !row.blockStart.peek().litToBoolean + dut.io.brobPrepared.entries(laneIndex).valid.poke(true.B) + dut.io.brobPrepared.entries(laneIndex).stid.poke( + row.uop.decoded.rob.stid.peek()) + dut.io.brobPrepared.entries(laneIndex).bid.poke( + if (continuesPreviousBlock) + dut.io.brobPrepared.entries(laneIndex - 1).bid.peek() + else row.uop.decoded.rob.bid.peek()) + dut.io.brobPrepared.entries(laneIndex).brobGeneration.poke( + if (continuesPreviousBlock) + dut.io.brobPrepared.entries(laneIndex - 1).brobGeneration.peek() + else row.uop.decoded.rob.brobGeneration.peek()) + dut.io.brobPrepared.entries(laneIndex).allocated.poke( + row.blockStart.peek()) + } + } + + private def complete(dut: ROB, rob: RobIdentity, accepted: Boolean): Unit = { + dut.io.completion.bits.rob.poke(rob) + dut.io.completion.valid.poke(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completionAccepted.valid.expect(accepted.B) + dut.io.completionRejected.valid.expect((!accepted).B) + dut.io.completion.valid.poke(false.B) + } + + private def retirePreview(dut: ROB): Unit = { + dut.io.commit.valid.expect(true.B) + dut.io.commitApply.poke(true.B) + dut.clock.step() + dut.io.commitApply.poke(false.B) + } + + test("ROB publishes grouped D3 prefix, binds exact tails, and rejects stale reuse") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 1, rid = 0, member = 0, + early = true, groupCount = 1) + lane(dut.io.prepare.bits, 1, id = 2, rid = 0, member = 1, + early = true, groupCount = 1) + val ids = publish(dut, 2) + assert(ids(0).ridSlot.litValue == 0) + assert(ids(1).memberIndex.litValue == 1) + dut.io.ridTailSlot(0).expect(1.U) + + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(2.U) + dut.io.commit.bits.entries(0).commit.rob.memberIndex.expect(0.U) + dut.io.commit.bits.entries(1).commit.rob.memberIndex.expect(1.U) + retirePreview(dut) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(ids(0)) + dut.io.release.bits.lanes(1).valid.poke(true.B) + dut.io.release.bits.lanes(1).rob.poke(ids(1)) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 3, rid = 1, member = 0, + groupCount = 1) + val reused = publish(dut, 1).head + complete(dut, ids.head, accepted = false) + complete(dut, reused, accepted = true) + } + } + + test("ROB-head-status-reports-exact-oldest-completion-owner") { + simulate(new ROB(params(2))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 41, rid = 0, member = 0, + groupCount = 1) + dut.io.prepare.bits.entries(0).uop.decoded.instruction.parent.pc + .poke("h10100".U) + dut.io.prepare.bits.entries(0).uop.decoded.instruction.parent.instruction + .poke("h1234".U) + dut.io.prepare.bits.entries(0).uop.decoded.opcode.poke("h5a".U) + val rob = publish(dut, 1).head + + dut.io.headStatus(0).valid.expect(true.B) + dut.io.headStatus(0).completed.expect(false.B) + dut.io.headStatus(0).retired.expect(false.B) + dut.io.headStatus(0).instruction.instructionId.expect(41.U) + dut.io.headStatus(0).rob.expect(rob) + dut.io.headStatus(0).pc.expect("h10100".U) + dut.io.headStatus(0).instructionBits.expect("h1234".U) + dut.io.headStatus(0).opcode.expect("h5a".U) + + complete(dut, rob, accepted = true) + dut.io.headStatus(0).valid.expect(true.B) + dut.io.headStatus(0).completed.expect(true.B) + + retirePreview(dut) + dut.io.headStatus(0).valid.expect(false.B) + } + } + + test("ROB store binding fails closed and preserves wrapped transaction generations") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 7, rid = 0, member = 0, + early = true, groupCount = 1) + val row = dut.io.prepare.bits.entries(0) + row.uop.decoded.memory.valid.poke(true.B) + row.uop.decoded.memory.isStore.poke(true.B) + row.memoryOrder.requestCount.poke(1.U) + row.memoryOrder.firstLsid.poke(21.U) + row.memoryOrder.firstSid.poke(31.U) + val resident = publish(dut, 1).head + + val binding = dut.io.storeBinding.head + binding.bits.poke(0.U.asTypeOf(binding.bits)) + binding.bits.rob.poke(resident) + binding.bits.memoryOrder.poke(row.memoryOrder.peek()) + binding.bits.transaction.value.poke(9.U) + binding.bits.transaction.generation.poke( + ((BigInt(1) << binding.bits.transaction.generation.getWidth) - 1).U) + binding.bits.rob.residentGeneration.poke( + (resident.residentGeneration.litValue + 1).U) + binding.valid.poke(true.B) + binding.ready.expect(false.B, + "a stale reused ROB identity must not mutate the resident store") + + binding.bits.rob.poke(resident) + binding.ready.expect(true.B) + dut.clock.step() + binding.valid.poke(false.B) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.entries(0).commit.memory.transaction.value.expect(9.U) + dut.io.commit.bits.entries(0).commit.memory.transaction.generation.expect( + ((BigInt(1) << binding.bits.transaction.generation.getWidth) - 1).U) + } + } + + test("ROB accepts both W4 store-binding lanes for distinct exact residents") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 17, rid = 0, member = 0, + early = true, groupCount = 2) + lane(dut.io.prepare.bits, 1, id = 18, rid = 1, member = 0, + early = true, groupCount = 2) + for (laneIndex <- 0 until 2) { + val row = dut.io.prepare.bits.entries(laneIndex) + row.uop.decoded.memory.valid.poke(true.B) + row.uop.decoded.memory.isStore.poke(true.B) + row.memoryOrder.requestCount.poke(1.U) + row.memoryOrder.firstLsid.poke((41 + laneIndex).U) + row.memoryOrder.firstSid.poke((51 + laneIndex).U) + } + val residents = publish(dut, 2) + for (laneIndex <- 0 until 2) { + val binding = dut.io.storeBinding(laneIndex) + binding.bits.poke(0.U.asTypeOf(binding.bits)) + binding.bits.rob.poke(residents(laneIndex)) + binding.bits.memoryOrder.poke( + dut.io.prepare.bits.entries(laneIndex).memoryOrder.peek()) + binding.bits.transaction.value.poke((61 + laneIndex).U) + binding.bits.transaction.generation.poke((7 + laneIndex).U) + binding.valid.poke(true.B) + binding.ready.expect(true.B) + } + dut.clock.step() + dut.io.storeBinding.foreach(_.valid.poke(false.B)) + dut.io.commit.bits.entries(0).commit.memory.transaction.value.expect(61.U) + dut.io.commit.bits.entries(1).commit.memory.transaction.value.expect(62.U) + } + } + + test("ROB exposes NFRDY for the oldest unresolved row after a completed prefix") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 10, rid = 0, member = 0, + groupCount = 2) + lane(dut.io.prepare.bits, 1, id = 11, rid = 1, member = 0, + groupCount = 2) + dut.io.prepare.bits.entries(1).uop.decoded.uopClass.poke(UopClass.System) + dut.io.prepare.bits.entries(1).uop.destinations.foreach(_.valid.poke(false.B)) + val ids = publish(dut, 2) + + dut.io.residentHeads(0).valid.expect(false.B, + "a younger system row is not the resident head") + complete(dut, ids.head, accepted = true) + dut.io.residentHeads(0).valid.expect(true.B) + dut.io.residentHeads(0).rob.expect(ids(1)) + dut.io.residentHeads(0).transactionId.expect(1.U) + dut.io.residentHeads(0).noflushEligible.expect(true.B) + + complete(dut, ids(1), accepted = true) + dut.io.residentHeads(0).valid.expect(false.B, + "a resolved system row cannot remain NFRDY-authorizable") + } + } + + test("ROB commits two members from one group before the next group") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 30, rid = 0, member = 0, + early = true, groupCount = 2) + lane(dut.io.prepare.bits, 1, id = 31, rid = 0, member = 1, + early = true, groupCount = 2) + lane(dut.io.prepare.bits, 2, id = 32, rid = 1, member = 0, + early = true, groupCount = 2) + publish(dut, 3) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(3.U) + dut.io.commit.bits.entries(0).commit.rob.ridSlot.expect(0.U) + dut.io.commit.bits.entries(0).commit.rob.memberIndex.expect(0.U) + dut.io.commit.bits.entries(1).commit.rob.ridSlot.expect(0.U) + dut.io.commit.bits.entries(1).commit.rob.memberIndex.expect(1.U) + dut.io.commit.bits.entries(2).commit.rob.ridSlot.expect(1.U) + } + } + + test("ROB-commit-preview-stops-before-the-next-BROB-block") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 33, rid = 0, member = 0, + early = true, blockStart = true, blockStop = true, groupCount = 2) + lane(dut.io.prepare.bits, 1, id = 34, rid = 1, member = 0, + early = true, blockStart = true, blockStop = true, groupCount = 2) + dut.io.prepare.bits.entries(0).uop.decoded.rob.bid.poke(0.U) + dut.io.prepare.bits.entries(1).uop.decoded.rob.bid.poke(1.U) + publish(dut, 2) + + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.ridSlot.expect(0.U) + dut.io.commit.bits.entries(0).commit.rob.bid.expect(0.U) + + retirePreview(dut) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.ridSlot.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.bid.expect(1.U) + } + } + + test("ROB commits an eligible STID1 prefix when STID0 has no completed head") { + simulate(new ROB(params(4, stids = 2))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 40, rid = 0, member = 0, + early = true, groupCount = 1, stid = 1) + publish(dut, 1) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.stid.expect(1.U) + } + } + + test("ROB commits only the oldest continuous completed prefix and retains under backpressure") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 10, rid = 0, member = 0, + early = true, groupCount = 3) + lane(dut.io.prepare.bits, 1, id = 11, rid = 1, member = 0, + groupCount = 3) + lane(dut.io.prepare.bits, 2, id = 12, rid = 2, member = 0, + early = true, groupCount = 3) + val ids = publish(dut, 3) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.ready.poke(false.B) + dut.clock.step(2) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.ridSlot + .expect(ids(0).ridSlot.litValue.U) + complete(dut, ids(1), accepted = true) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.ready.poke(true.B) + retirePreview(dut) + dut.io.commit.bits.count.expect(2.U) + } + } + + test("BROB allocates per STID in order and release of one STID does not block another") { + simulate(new BROB(params(4, stids = 2))) { dut => + clearBrob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 20, rid = 0, member = 0, + blockStart = true, groupCount = 1, stid = 0) + dut.io.prepare.valid.poke(true.B) + bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(0.U) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).stid.poke(0.U) + dut.io.release.bits.entries(0).bid.poke(0.U) + dut.io.release.bits.entries(0).brobGeneration.poke(1.U) + dut.clock.step() + dut.io.releaseRejected.valid.expect(true.B) + dut.io.release.valid.poke(false.B) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 21, rid = 0, member = 0, + blockStart = true, groupCount = 1, stid = 1) + dut.io.prepare.valid.poke(true.B) + bindBrobPrepared(dut, 1) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).bid.expect(0.U) + } + } + + test("CommitControl preserves secondary destination history and trap beats interrupt") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.kind.poke(TrapKind.Exception) + dut.io.rob.bits.entries(0).rename.history(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).rename.history(1).valid.poke(true.B) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).priority.poke(7.U) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.out.ready.poke(false.B) + dut.io.robReleaseReady.poke(false.B) + dut.io.renameReleaseReady.poke(false.B) + dut.io.brobReleaseReady.poke(false.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(1.U) + dut.io.out.bits.trap.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Exception) + dut.io.out.bits.rename.count.expect(1.U) + dut.io.out.bits.rename.lanes(0).history(1).valid.expect(true.B) + dut.io.rob.bits.count.poke(0.U) + dut.io.interrupts(0).valid.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.clock.step() + dut.io.out.bits.commit.count.expect(1.U) + dut.io.out.ready.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + } + } + + test("CommitControl tracks an expanding exact ROB prefix before owner readiness") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.valid.poke(true.B) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(false.B) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.peId.poke(1.U) + dut.io.rob.bits.entries(0).commit.rob.stid.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(2.U) + dut.io.rob.bits.entries(0).commit.rob.ridGeneration.poke(3.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.residentGeneration.poke(4.U) + dut.io.rob.bits.entries(0).commit.rob.bid.poke(1.U) + dut.io.rob.bits.entries(0).commit.rob.brobGeneration.poke(5.U) + dut.io.rob.bits.entries(0).commit.robGroupLast.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + + dut.io.rob.bits.count.poke(2.U) + dut.io.rob.bits.entries(1).valid.poke(true.B) + dut.io.rob.bits.entries(1).commit.rob.peId.poke(1.U) + dut.io.rob.bits.entries(1).commit.rob.stid.poke(0.U) + dut.io.rob.bits.entries(1).commit.rob.ridSlot.poke(3.U) + dut.io.rob.bits.entries(1).commit.rob.ridGeneration.poke(6.U) + dut.io.rob.bits.entries(1).commit.rob.memberIndex.poke(0.U) + dut.io.rob.bits.entries(1).commit.rob.residentGeneration.poke(7.U) + dut.io.rob.bits.entries(1).commit.rob.bid.poke(1.U) + dut.io.rob.bits.entries(1).commit.rob.brobGeneration.poke(5.U) + dut.io.rob.bits.entries(1).commit.robGroupLast.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.brobRelease.count.expect(2.U) + dut.io.out.bits.brobRelease.entries(0).expect( + dut.io.rob.bits.entries(0).commit.rob.peek()) + dut.io.out.bits.brobRelease.entries(1).expect( + dut.io.rob.bits.entries(1).commit.rob.peek()) + dut.io.out.bits.robRelease.count.expect(2.U) + dut.io.out.bits.rename.count.expect(2.U) + for (lane <- 2 until params(4).widths.retireWidth) { + dut.io.out.bits.robRelease.lanes(lane).valid.expect(false.B) + dut.io.out.bits.brobRelease.entries(lane).expect( + 0.U.asTypeOf(dut.io.out.bits.brobRelease.entries(lane))) + } + } + } + + test("CommitControl projects the maximum exact retire prefix") { + val p = params(4) + simulate(new CommitControl(p)) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.valid.poke(true.B) + dut.io.out.ready.poke(false.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.rob.bits.count.poke(p.widths.retireWidth.U) + for (lane <- 0 until p.widths.retireWidth) { + val rob = dut.io.rob.bits.entries(lane).commit.rob + dut.io.rob.bits.entries(lane).valid.poke(true.B) + rob.peId.poke(1.U) + rob.ridSlot.poke(lane.U) + rob.ridGeneration.poke((lane + 1).U) + rob.memberIndex.poke((lane % p.ooo.maxInstructionsPerRobGroup).U) + rob.residentGeneration.poke((lane + 2).U) + rob.bid.poke(1.U) + rob.brobGeneration.poke(9.U) + } + dut.io.out.valid.expect(true.B) + dut.io.out.bits.brobRelease.count.expect(p.widths.retireWidth.U) + for (lane <- 0 until p.widths.retireWidth) { + dut.io.out.bits.brobRelease.entries(lane).expect( + dut.io.rob.bits.entries(lane).commit.rob.peek()) + } + } + } + + test("CommitControl emits exactly one common fire after all owner readiness") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.out.ready.poke(true.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.robReleaseReady.poke(false.B) + dut.io.renameReleaseReady.poke(false.B) + dut.io.brobReleaseReady.poke(false.B) + dut.io.out.valid.expect(false.B) + dut.clock.step(2) + dut.io.out.valid.expect(false.B) + dut.io.robReleaseReady.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + dut.io.renameReleaseReady.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.valid.expect(true.B) + dut.clock.step() + dut.io.out.valid.expect(false.B) + } + } + + test("CommitControl zero-lane trap and interrupt bypass ordinary release readiness") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.headValid.poke(true.B) + dut.io.rob.bits.head.stid.poke(0.U) + dut.io.rob.bits.headTrap.valid.poke(true.B) + dut.io.rob.bits.headTrap.kind.poke(TrapKind.Exception) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(false.B) + dut.io.renameReleaseReady.poke(false.B) + dut.io.brobReleaseReady.poke(false.B) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(0.U) + dut.io.out.bits.trap.kind.expect(TrapKind.Exception) + dut.clock.step() + dut.io.out.valid.expect(false.B) + dut.io.rob.valid.poke(false.B) + dut.clock.step() + + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).priority.poke(1.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(0.U) + dut.io.out.bits.trap.kind.expect(TrapKind.Interrupt) + } + } + + test("CommitControl accepts distinct back-to-back previews while ROB valid stays high") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.entries(0).rob.ridSlot.expect(0.U) + dut.clock.step() + + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(1.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.entries(0).rob.ridSlot.expect(1.U) + dut.clock.step() + dut.io.out.valid.expect(false.B) + } + } + + test("CommitControl accepts expanded prefix with the same first ROB identity") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(1.U) + dut.clock.step() + + dut.io.rob.bits.count.poke(2.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.rob.bits.entries(1).valid.poke(true.B) + dut.io.rob.bits.entries(1).commit.rob.ridSlot.poke(1.U) + dut.io.rob.bits.entries(1).commit.rob.memberIndex.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(2.U) + } + } + + test("CommitControl accepts same-head trap changes and ordinary-to-trap transitions") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.rob.bits.headValid.poke(true.B) + dut.io.rob.bits.head.stid.poke(0.U) + dut.io.rob.bits.head.ridSlot.poke(0.U) + dut.io.rob.bits.headTrap.valid.poke(true.B) + dut.io.rob.bits.headTrap.kind.poke(TrapKind.Exception) + dut.io.rob.bits.headTrap.cause.poke(0x10.U) + dut.io.rob.bits.headTrap.rob.stid.poke(0.U) + dut.io.rob.bits.headTrap.rob.ridSlot.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.cause.expect(0x10.U) + dut.clock.step() + + dut.io.rob.bits.headTrap.cause.poke(0x11.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.cause.expect(0x11.U) + dut.clock.step() + + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.stid.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(1.U) + dut.clock.step() + + dut.io.rob.bits.count.poke(0.U) + dut.io.rob.bits.headValid.poke(true.B) + dut.io.rob.bits.head.stid.poke(0.U) + dut.io.rob.bits.head.ridSlot.poke(0.U) + dut.io.rob.bits.headTrap.valid.poke(true.B) + dut.io.rob.bits.headTrap.kind.poke(TrapKind.Exception) + dut.io.rob.bits.headTrap.cause.poke(0x12.U) + dut.io.rob.bits.headTrap.rob.stid.poke(0.U) + dut.io.rob.bits.headTrap.rob.ridSlot.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(0.U) + dut.io.out.bits.trap.cause.expect(0x12.U) + } + } + + test("CommitControl holds a backpressured transaction and then accepts advanced preview") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.out.ready.poke(false.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.clock.step() + + dut.io.rob.bits.count.poke(2.U) + dut.io.rob.bits.entries(1).valid.poke(true.B) + dut.io.rob.bits.entries(1).commit.rob.ridSlot.poke(1.U) + dut.io.rob.bits.entries(1).commit.rob.memberIndex.poke(0.U) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(1.U) + dut.io.out.ready.poke(true.B) + dut.clock.step() + dut.io.out.valid.expect(true.B) + dut.io.out.bits.commit.count.expect(2.U) + } + } + + test("CommitControl does not repeat when only inactive lanes change") { + simulate(new CommitControl(params(4))) { dut => + clearCommitControlExtensions(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.rob.ridSlot.poke(0.U) + dut.io.rob.bits.entries(0).commit.rob.memberIndex.poke(0.U) + dut.io.rob.bits.entries(1).commit.rob.ridSlot.poke(1.U) + dut.io.out.ready.poke(true.B) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.valid.expect(true.B) + dut.clock.step() + + dut.io.rob.bits.entries(1).commit.rob.ridSlot.poke(2.U) + dut.io.rob.bits.entries(1).rename.history(0).valid.poke(true.B) + dut.io.rob.bits.entries(1).rename.history(0).ptag.poke(9.U) + dut.io.out.valid.expect(false.B) + } + } + + test("CommitControl requires exact NFRDY and never repeats a resident head") { + simulate(new CommitControl(params(4, stids = 2))) { dut => + dut.io.rob.valid.poke(false.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.out.ready.poke(true.B) + clearCommitControlExtensions(dut) + + def pokeHead(stid: Int, transactionId: Int, instructionId: Int, + ridSlot: Int): Unit = { + val head = dut.io.residentHeads(stid) + head.valid.poke(true.B) + head.noflushEligible.poke(true.B) + head.transactionId.poke(transactionId.U) + head.instruction.peId.poke(3.U) + head.instruction.stid.poke(stid.U) + head.instruction.instructionId.poke(instructionId.U) + head.rob.peId.poke(3.U) + head.rob.stid.poke(stid.U) + head.rob.ridSlot.poke(ridSlot.U) + head.rob.ridGeneration.poke(2.U) + head.rob.memberIndex.poke(0.U) + } + def pokeNfrdy(stid: Int, transactionId: Int, instructionId: Int, + ridSlot: Int): Unit = { + val ready = dut.io.robNoflushReady + ready.valid.poke(true.B) + ready.bits.transactionId.poke(transactionId.U) + ready.bits.instruction.peId.poke(3.U) + ready.bits.instruction.stid.poke(stid.U) + ready.bits.instruction.instructionId.poke(instructionId.U) + ready.bits.rob.peId.poke(3.U) + ready.bits.rob.stid.poke(stid.U) + ready.bits.rob.ridSlot.poke(ridSlot.U) + ready.bits.rob.ridGeneration.poke(2.U) + ready.bits.rob.memberIndex.poke(0.U) + } + + pokeHead(0, 0x123, 0x456, 1) + dut.io.robNoflush.valid.expect(false.B, + "ROB shape alone is not legality/drain authority") + pokeNfrdy(0, 0x122, 0x456, 1) + dut.io.robNoflush.valid.expect(false.B) + dut.io.robNoflushReady.ready.expect(true.B, + "a stale NFRDY proof must drain without granting authorization") + pokeNfrdy(0, 0x123, 0x456, 1) + dut.io.robNoflush.valid.expect(true.B) + dut.io.robNoflush.bits.transactionId.expect(0x123.U) + dut.io.robNoflush.bits.instruction.instructionId.expect(0x456.U) + dut.io.robNoflush.bits.rob.ridSlot.expect(1.U) + val retained = dut.io.robNoflush.bits.peek() + dut.clock.step(2) + dut.io.robNoflush.valid.expect(true.B) + dut.io.robNoflush.bits.expect(retained) + + dut.io.recoveryFence(1).poke(true.B) + dut.io.robNoflush.valid.expect(true.B) + dut.io.recoveryFence(1).poke(false.B) + dut.io.recoveryFence(0).poke(true.B) + dut.io.robNoflush.valid.expect(false.B) + dut.io.robNoflushReady.ready.expect(false.B, + "recovery fencing must not consume an exact unaccepted NFRDY proof") + dut.clock.step() + dut.io.recoveryFence(0).poke(false.B) + dut.io.robNoflush.valid.expect(true.B) + + dut.io.residentHeads(0).noflushEligible.poke(false.B) + dut.io.robNoflush.valid.expect(false.B, + "a stalled authorization must not outlive head eligibility") + dut.io.residentHeads(0).noflushEligible.poke(true.B) + dut.io.robNoflush.valid.expect(true.B) + + dut.io.robNoflush.ready.poke(true.B) + dut.clock.step() + dut.io.robNoflush.valid.expect(false.B) + + pokeHead(1, 0x220, 0x550, 2) + pokeNfrdy(1, 0x220, 0x550, 2) + dut.io.robNoflush.valid.expect(true.B) + dut.io.robNoflush.bits.transactionId.expect(0x220.U) + dut.clock.step() + dut.io.robNoflush.valid.expect(false.B) + + pokeNfrdy(0, 0x123, 0x456, 1) + dut.io.robNoflush.valid.expect(false.B, + "an accepted member remains suppressed after another STID wins") + + dut.io.residentHeads(0).valid.poke(false.B) + dut.clock.step() + pokeHead(0, 0x124, 0x457, 3) + pokeNfrdy(0, 0x124, 0x457, 3) + dut.io.robNoflush.valid.expect(true.B) + } + } + + test("ROB release preflight does not mutate before common commit apply") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 80, rid = 0, member = 0, + early = true, groupCount = 1) + val id = publish(dut, 1).head + dut.io.commit.ready.poke(true.B) + dut.io.commit.valid.expect(true.B) + dut.clock.step() + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(id) + dut.io.releaseReady.expect(true.B) + dut.clock.step() + dut.io.commit.valid.expect(true.B) + dut.io.releaseReady.expect(true.B) + dut.io.commitApply.poke(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.commitApply.poke(false.B) + dut.io.releaseApply.poke(false.B) + dut.io.commit.valid.expect(false.B) + dut.io.releaseReady.expect(false.B) + } + } + + test("ROB recovery clears retained commit preview over killed suffix") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 100, rid = 0, member = 0, + early = true, groupCount = 2) + lane(dut.io.prepare.bits, 1, id = 101, rid = 1, member = 0, + early = true, groupCount = 2) + val ids = publish(dut, 2) + dut.io.commit.ready.poke(false.B) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(2.U) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.transactionId.poke(0x71.U) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recoveryPrepare.bits.trigger.poke(ids(0)) + dut.io.recoveryPrepare.ready.expect(true.B) + dut.clock.step() + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recoveryApply.valid.poke(true.B) + dut.io.recoveryApply.bits.poke(dut.io.recoveryPrepared.bits.peek()) + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.commit.ready.poke(true.B) + dut.io.commit.valid.expect(true.B) + dut.io.commit.bits.count.expect(1.U) + dut.io.commit.bits.entries(0).commit.rob.ridSlot.expect(0.U) + dut.io.commit.bits.entries(0).commit.rob.memberIndex.expect(0.U) + retirePreview(dut) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(ids(0)) + dut.io.releaseReady.expect(true.B) + } + } + + test("ROB rejects malformed D3 shape and consumes exact BROB bindings") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 50, rid = 1, member = 0, + early = true, groupCount = 1) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.bits.entries(0).uop.decoded.rob.ridSlot.poke(0.U) + dut.io.prepare.bits.entries(0).uop.decoded.rob.memberIndex.poke(1.U) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.bits.entries(0).uop.decoded.rob.memberIndex.poke(0.U) + dut.io.prepare.bits.entries(0).brobBound.poke(true.B) + dut.io.brobPrepared.count.poke(1.U) + dut.io.brobPrepared.entries(0).valid.poke(true.B) + dut.io.brobPrepared.entries(0).stid.poke(0.U) + dut.io.brobPrepared.entries(0).bid.poke(3.U) + dut.io.brobPrepared.entries(0).brobGeneration.poke(2.U) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.bits.entries(0).uop.decoded.rob.bid.poke(3.U) + dut.io.prepare.bits.entries(0).uop.decoded.rob.brobGeneration.poke(2.U) + dut.io.prepare.bits.entries(0).residentBound.poke(true.B) + dut.io.prepare.bits.entries(0).uop.decoded.rob.residentGeneration.poke(1.U) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.bits.entries(0).uop.decoded.rob.residentGeneration.poke(0.U) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).rob.bid.expect(3.U) + dut.io.prepared.entries(0).rob.brobGeneration.expect(2.U) + dut.io.brobPrepared.entries(0).stid.poke(1.U) + dut.io.prepare.ready.expect(false.B) + } + } + + test("ROB release validates the whole prefix before mutation") { + simulate(new ROB(params(4))) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 60, rid = 0, member = 0, + early = true, groupCount = 1) + val id = publish(dut, 1).head + retirePreview(dut) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(false.B) + dut.io.release.bits.lanes(0).rob.poke(id) + dut.io.releaseReady.expect(false.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.ridTailSlot(0).expect(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.releaseReady.expect(true.B) + dut.clock.step() + dut.io.ridHeadSlot(0).expect(1.U) + } + } + + test("BROB accepts partial retirement and frees the block on its final member") { + simulate(new BROB(params(4))) { dut => + clearBrob(dut) + lane(dut.io.prepare.bits, 0, id = 70, rid = 0, member = 0, + blockStart = true, blockStop = false, groupCount = 1) + lane(dut.io.prepare.bits, 1, id = 71, rid = 0, member = 1, + blockStart = false, blockStop = true, groupCount = 1) + dut.io.prepare.valid.poke(true.B) + bindBrobPrepared(dut, 2) + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).stid.poke(0.U) + dut.io.release.bits.entries(0).bid.poke(0.U) + dut.io.release.bits.entries(0).brobGeneration.poke(0.U) + dut.io.release.bits.entries(0).ridSlot.poke(0.U) + dut.io.release.bits.entries(0).memberIndex.poke(0.U) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.debugUsed(0).expect(1.U) + dut.io.release.valid.poke(false.B) + dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recoveryPrepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recoveryPrepare.bits.firstKilledValid.poke(true.B) + dut.io.recoveryPrepare.bits.firstKilled.stid.poke(0.U) + dut.io.recoveryPrepare.bits.firstKilled.bid.poke(0.U) + dut.io.recoveryPrepare.bits.firstKilled.brobGeneration.poke(1.U) + dut.io.recoveryPrepare.ready.expect(false.B) + dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries(0).stid.poke(0.U) + dut.io.release.bits.entries(0).bid.poke(0.U) + dut.io.release.bits.entries(0).brobGeneration.poke(0.U) + dut.io.release.bits.entries(0).ridSlot.poke(0.U) + dut.io.release.bits.entries(0).memberIndex.poke(1.U) + dut.io.release.bits.entries(1).stid.poke(0.U) + dut.io.release.bits.entries(1).bid.poke(0.U) + dut.io.release.bits.entries(1).brobGeneration.poke(0.U) + dut.io.release.bits.entries(1).ridSlot.poke(0.U) + dut.io.release.bits.entries(1).memberIndex.poke(1.U) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.debugUsed(0).expect(0.U) + } + } + + test("BROB closes an open predecessor when a new block starts") { + simulate(new BROB(params(4))) { dut => + clearBrob(dut) + lane(dut.io.prepare.bits, 0, id = 80, rid = 0, member = 0, + blockStart = true, blockStop = false, groupCount = 1) + dut.io.prepare.valid.poke(true.B) + val predecessor = bindBrobPrepared(dut, 1).head + dut.io.prepare.ready.expect(true.B) + dut.io.publishFire.poke(true.B) + dut.clock.step() + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 81, rid = 1, member = 0, + blockStart = true, blockStop = true, groupCount = 1) + val successor = bindBrobPrepared(dut, 1).head + dut.io.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.entries.head.poke(predecessor) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.releaseApply.poke(false.B) + dut.io.release.bits.entries.head.poke(successor) + dut.io.releaseReady.expect(true.B) + } + } + + test("ROB rejects unsupported bank geometry and maps nontrivial bank profiles") { + def exercise(width: Int, banks: Int, sameBankSlot: Int): Unit = { + val base = params(width).copy(ooo = params(width).ooo.copy( + robGroupsPerStid = 8, + robBankCount = banks)) + simulate(new ROB(base)) { dut => + clearRob(dut) + def publishOne(idValue: Int, rid: Int, early: Boolean = false): RobIdentity = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = idValue, rid = rid, member = 0, + early = early, groupCount = 1) + bindBrobPrepared(dut, 1) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(true.B) + val rob = dut.io.prepared.entries(0).rob.peek() + dut.io.publishFire.poke(true.B) + dut.clock.step() + dut.io.prepare.valid.poke(false.B) + dut.io.publishFire.poke(false.B) + rob + } + val first = publishOne(90, 0, early = true) + val middle = (1 until sameBankSlot).map(rid => publishOne(90 + rid, rid)) + val sameBank = publishOne(100 + sameBankSlot, sameBankSlot) + complete(dut, sameBank, accepted = true) + retirePreview(dut) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(first) + dut.io.releaseReady.expect(true.B) + dut.io.releaseApply.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.releaseApply.poke(false.B) + complete(dut, first, accepted = false) + complete(dut, sameBank, accepted = false) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 130, rid = sameBankSlot, + member = 0, groupCount = 1) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(false.B) + dut.io.prepare.valid.poke(false.B) + middle.foreach(_ => ()) + ((sameBankSlot + 1) until 8).foreach { rid => + publishOne(140 + rid, rid) + } + dut.io.ridTailSlot(0).expect(0.U) + dut.io.ridTailGeneration(0).expect(1.U) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + lane(dut.io.prepare.bits, 0, id = 180, rid = 0, member = 0, + groupCount = 1) + dut.io.prepare.bits.entries(0).uop.decoded.rob.ridGeneration.poke(1.U) + bindBrobPrepared(dut, 1) + dut.io.prepare.valid.poke(true.B) + dut.io.prepare.ready.expect(true.B) + dut.io.prepared.entries(0).rob.ridSlot.expect(0.U) + dut.io.prepared.entries(0).rob.ridGeneration.expect(1.U) + dut.io.prepared.entries(0).rob.residentGeneration.expect(1.U) + } + } + exercise(width = 2, banks = 2, sameBankSlot = 2) + exercise(width = 4, banks = 4, sameBankSlot = 4) + val base = params(2).copy(ooo = params(2).ooo.copy( + robGroupsPerStid = 8, + robBankCount = 2)) + simulate(new ROB(base)) { dut => + clearRob(dut) + lane(dut.io.prepare.bits, 0, id = 90, rid = 0, member = 0, + early = true, groupCount = 1) + val id = publish(dut, 1).head + retirePreview(dut) + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(id) + dut.io.releaseReady.expect(true.B) + } + assertThrows[IllegalArgumentException] { + simulate(new ROB(base.copy(ooo = base.ooo.copy( + robGroupsPerStid = 6, + robBankCount = 4)))) { _ => } + } + } + + test("ROB elaborates W2 W4 W6 and W8 without fixed W4 bank assumptions") { + Seq(2, 4, 6, 8).foreach { width => + simulate(new ROB(params(width))) { dut => + clearRob(dut) + dut.io.ridTailSlot(0).expect(0.U) + } + } + } + + test("ROB rejects unsafe recovery age token widths") { + val unsafe = params(2).copy(transactionIdWidth = 4, ooo = params(2).ooo.copy( + stidCount = 2, + robGroupsPerStid = 4, + maxInstructionsPerRobGroup = 2, + robBankCount = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 64, + tPhysRegs = 16, + uPhysRegs = 16, + tuMapQDepthPerStid = 16)) + assertThrows[IllegalArgumentException] { + simulate(new ROB(unsafe)) { _ => } + } + assertThrows[IllegalArgumentException] { + simulate(new RecoveryControl(unsafe, targetCount = 1)) { _ => } + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OooBrobSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooBrobSpec.scala deleted file mode 100644 index eabe7766..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooBrobSpec.scala +++ /dev/null @@ -1,458 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooBrobSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooBrob): Unit = { - dut.io.prepare.valid.poke(false.B) - dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - dut.io.publishFire.poke(false.B) - dut.io.commit.valid.poke(false.B) - dut.io.commit.bits.poke(0.U.asTypeOf(dut.io.commit.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - } - - private def pokePrepare( - dut: OooBrob, - stid: Int, - transactionId: Int, - firstRid: Int, - boundaries: Seq[(Boolean, Boolean)], - peId: Int = 2): Unit = { - dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - val transaction = dut.io.prepare.bits.transaction - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(9.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.groupCount.poke(boundaries.size.U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(9.U) - transaction.groupMask.poke(((1 << boundaries.size) - 1).U) - boundaries.zipWithIndex.foreach { case ((start, stop), index) => - val group = transaction.groups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - val absoluteRid = firstRid + index - group.key.ridSlot.poke((absoluteRid % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((absoluteRid / dut.p.robGroupsPerStid).U) - group.boundaryStart.poke(start.B) - group.boundaryStop.poke(stop.B) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - } - dut.io.prepare.valid.poke(true.B) - } - - private def publish(dut: OooBrob): Unit = { - dut.io.prepareReady.expect(true.B) - dut.io.publishFire.poke(true.B) - dut.clock.step() - dut.io.publishFire.poke(false.B) - dut.io.prepare.valid.poke(false.B) - } - - private def pokeCommit( - dut: OooBrob, - stid: Int, - groups: Seq[(Int, Int, Int, Boolean, Boolean)], - peId: Int = 2): Unit = { - dut.io.commit.bits.poke(0.U.asTypeOf(dut.io.commit.bits)) - dut.io.commit.bits.release.groupCount.poke(groups.size.U) - val firstRid = groups.head._1 - dut.io.commit.bits.release.firstGroup.valid.poke(true.B) - dut.io.commit.bits.release.firstGroup.peId.poke(peId.U) - dut.io.commit.bits.release.firstGroup.stid.poke(stid.U) - dut.io.commit.bits.release.firstGroup.ridSlot.poke( - (firstRid % dut.p.robGroupsPerStid).U) - dut.io.commit.bits.release.firstGroup.ridGeneration.poke( - (firstRid / dut.p.robGroupsPerStid).U) - groups.zipWithIndex.foreach { - case ((ridSlot, bid, brobGeneration, start, stop), index) => - val group = dut.io.commit.bits.groups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((ridSlot % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((ridSlot / dut.p.robGroupsPerStid).U) - group.brob.valid.poke(true.B) - group.brob.bid.valid.poke(true.B) - group.brob.bid.value.poke(bid.U) - group.brob.generation.poke(brobGeneration.U) - group.boundaryStart.poke(start.B) - group.boundaryStop.poke(stop.B) - } - dut.io.commit.valid.poke(true.B) - } - - private def commit(dut: OooBrob): Unit = { - dut.io.commit.ready.expect(true.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) - } - - private def pokeRecoveryPlan( - dut: OooBrob, - stid: Int, - staleGeneration: Boolean = false): Unit = { - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.request.rename.key.member.group.valid.poke(true.B) - plan.request.rename.key.member.group.peId.poke(2.U) - plan.request.rename.key.member.group.stid.poke(stid.U) - plan.request.rename.key.member.bid.valid.poke(true.B) - plan.oldOccupied.poke(5.U) - plan.newOccupied.poke(2.U) - plan.killedGroupCount.poke(3.U) - plan.killedGroupMask.poke(7.U) - plan.survivingTailValid.poke(true.B) - plan.survivingTail.valid.poke(true.B) - plan.survivingTail.key.valid.poke(true.B) - plan.survivingTail.key.peId.poke(2.U) - plan.survivingTail.key.stid.poke(stid.U) - plan.survivingTail.key.ridSlot.poke(1.U) - plan.survivingTail.brob.valid.poke(true.B) - plan.survivingTail.brob.bid.valid.poke(true.B) - plan.survivingTail.brob.bid.value.poke(0.U) - plan.survivingTail.brob.generation.poke(0.U) - - val groups = Seq( - (2, 1, true, true, 0), - (3, 1, false, false, 0), - (4, 2, true, true, 1)) - groups.zipWithIndex.foreach { - case ((rid, bid, allocated, implicitClose, priorBid), index) => - val group = plan.killedGroups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(2.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(rid.U) - group.key.ridGeneration.poke(0.U) - group.boundaryStart.poke(allocated.B) - group.brob.valid.poke(true.B) - group.brob.bid.valid.poke(true.B) - group.brob.bid.value.poke(bid.U) - group.brob.generation.poke( - (if (staleGeneration && index == 1) 1 else 0).U) - group.brobAllocated.poke(allocated.B) - group.brobImplicitCloseValid.poke(implicitClose.B) - group.brobImplicitClose.valid.poke(implicitClose.B) - group.brobImplicitClose.bid.valid.poke(implicitClose.B) - group.brobImplicitClose.bid.value.poke(priorBid.U) - group.brobImplicitClose.generation.poke(0.U) - } - dut.io.recoveryPrepare.valid.poke(true.B) - } - - test("requires an opening boundary before assigning the first native BID") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - boundaries = Seq(false -> false)) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.io.usedBlocks(0).expect(0.U) - dut.clock.step() - dut.io.usedBlocks(0).expect(0.U) - } - } - - test("rolls back exact tail blocks and reopens an implicitly closed survivor") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> false, false -> false, true -> false)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - boundaries = Seq(false -> false, true -> false)) - publish(dut) - dut.io.usedBlocks(1).expect(3.U) - dut.io.tail(1).bid.value.expect(3.U) - dut.io.currentValid(1).expect(true.B) - dut.io.current(1).bid.value.expect(2.U) - - pokeRecoveryPlan(dut, stid = 1) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.recoveryPrepared.freedBlocks.expect(2.U) - dut.io.recoveryPrepared.tailAfter.bid.value.expect(1.U) - dut.io.recoveryPrepared.currentAfterValid.expect(true.B) - dut.io.recoveryPrepared.currentAfter.bid.value.expect(0.U) - dut.clock.step() - dut.io.usedBlocks(1).expect(3.U) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedBlocks(1).expect(1.U) - dut.io.tail(1).bid.value.expect(1.U) - dut.io.currentValid(1).expect(true.B) - dut.io.current(1).bid.value.expect(0.U) - - pokePrepare(dut, stid = 1, transactionId = 2, firstRid = 2, - boundaries = Seq(true -> false)) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.pointers(0).bid.value.expect(1.U) - dut.io.prepared.implicitCloseMask.expect(1.U) - dut.io.prepared.implicitClosePointers(0).bid.value.expect(0.U) - publish(dut) - dut.io.usedBlocks(1).expect(2.U) - dut.io.current(1).bid.value.expect(1.U) - } - } - - test("rejects a stale killed-block generation without BROB mutation") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> false, false -> false, true -> false)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - boundaries = Seq(false -> false, true -> false)) - publish(dut) - - pokeRecoveryPlan(dut, stid = 1, staleGeneration = true) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryRejected.bits.killedRowsExact.expect(false.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedBlocks(1).expect(3.U) - dut.io.tail(1).bid.value.expect(3.U) - dut.io.current(1).bid.value.expect(2.U) - } - } - - test("publishes one BID across grouped rows and frees it only at exact close commit") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> false, false -> true)) - dut.io.prepared.allocatedBlocks.expect(1.U) - dut.io.prepared.pointers(0).bid.value.expect(0.U) - dut.io.prepared.pointers(1).bid.value.expect(0.U) - publish(dut) - dut.io.usedBlocks(1).expect(1.U) - dut.io.currentValid(1).expect(false.B) - - pokeCommit(dut, stid = 1, - groups = Seq((0, 0, 0, true, false), (1, 0, 0, false, true))) - commit(dut) - dut.io.usedBlocks(1).expect(0.U) - dut.io.head(1).valid.expect(false.B) - dut.io.head(1).bid.value.expect(1.U) - dut.io.tail(1).bid.value.expect(1.U) - } - } - - test("holds an empty open block until its in-body BSTART close owner commits") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 2, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> false)) - publish(dut) - dut.io.currentValid(2).expect(true.B) - - pokeCommit(dut, stid = 2, groups = Seq((0, 0, 0, true, false))) - commit(dut) - dut.io.usedBlocks(2).expect(1.U) - dut.io.head(2).bid.value.expect(0.U) - - pokePrepare(dut, stid = 2, transactionId = 1, firstRid = 1, - boundaries = Seq(true -> true)) - dut.io.prepared.implicitCloseMask.expect(1.U) - dut.io.prepared.implicitClosePointers(0).bid.value.expect(0.U) - dut.io.prepared.pointers(0).bid.value.expect(1.U) - publish(dut) - dut.io.usedBlocks(2).expect(2.U) - - pokeCommit(dut, stid = 2, groups = Seq((1, 1, 0, true, true))) - commit(dut) - dut.io.usedBlocks(2).expect(0.U) - dut.io.head(2).bid.value.expect(2.U) - } - } - - test("rejects wrong BROB generation and preserves another STID") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> true)) - publish(dut) - pokePrepare(dut, stid = 3, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> true)) - publish(dut) - - pokeCommit(dut, stid = 0, groups = Seq((0, 0, 1, true, true))) - dut.io.commit.ready.expect(false.B) - dut.io.commitRejected.valid.expect(true.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) - dut.io.usedBlocks(0).expect(1.U) - dut.io.usedBlocks(3).expect(1.U) - - pokeCommit(dut, stid = 0, groups = Seq((0, 0, 0, true, true))) - dut.io.commit.bits.release.firstGroup.valid.poke(true.B) - dut.io.commit.bits.release.firstGroup.peId.poke(2.U) - dut.io.commit.bits.release.firstGroup.stid.poke(0.U) - dut.io.commit.bits.release.firstGroup.ridSlot.poke(0.U) - dut.io.commit.bits.release.firstGroup.ridGeneration.poke(0.U) - commit(dut) - dut.io.usedBlocks(0).expect(0.U) - dut.io.usedBlocks(3).expect(1.U) - } - } - - test("does not let an invalid retained commit starve prepare and rejects a mismatched release header") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> true)) - publish(dut) - - pokeCommit(dut, stid = 0, groups = Seq((0, 0, 0, true, true))) - dut.io.commit.bits.release.firstGroup.valid.poke(true.B) - dut.io.commit.bits.release.firstGroup.peId.poke(2.U) - dut.io.commit.bits.release.firstGroup.stid.poke(0.U) - dut.io.commit.bits.release.firstGroup.ridSlot.poke(7.U) - dut.io.commit.bits.release.firstGroup.ridGeneration.poke(0.U) - dut.io.commit.ready.expect(false.B) - dut.io.commitRejected.valid.expect(true.B) - - pokePrepare(dut, stid = 0, transactionId = 1, firstRid = 1, - boundaries = Seq(true -> true)) - dut.io.prepareReady.expect(true.B) - dut.io.usedBlocks(0).expect(1.U) - dut.clock.step() - dut.io.usedBlocks(0).expect(1.U) - } - } - - test("rejects skipped and duplicate ROB groups within one BID") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - boundaries = Seq(true -> false, false -> true)) - publish(dut) - - pokeCommit(dut, stid = 1, groups = Seq((1, 0, 0, false, true))) - dut.io.commit.ready.expect(false.B) - dut.io.commitRejected.valid.expect(true.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) - dut.io.usedBlocks(1).expect(1.U) - - pokeCommit(dut, stid = 1, groups = Seq((0, 0, 0, true, false))) - commit(dut) - dut.io.usedBlocks(1).expect(1.U) - - pokeCommit(dut, stid = 1, groups = Seq((0, 0, 0, true, false))) - dut.io.commit.ready.expect(false.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) - dut.io.usedBlocks(1).expect(1.U) - - pokeCommit(dut, stid = 1, groups = Seq((1, 0, 0, false, true))) - commit(dut) - dut.io.usedBlocks(1).expect(0.U) - } - } - - test("wraps native BID independently from BROB generation") { - val p = OooParams(instructionDecodeWidth = 2, brobEntriesPerStid = 4) - simulate(new OooBrob(p)) { dut => - clear(dut) - for (block <- 0 until 4) { - pokePrepare(dut, stid = 0, transactionId = block, firstRid = block, - boundaries = Seq(true -> true)) - dut.io.prepared.pointers(0).bid.value.expect(block.U) - dut.io.prepared.pointers(0).generation.expect(0.U) - publish(dut) - pokeCommit(dut, stid = 0, groups = Seq((block, block, 0, true, true))) - commit(dut) - } - dut.io.head(0).bid.value.expect(0.U) - dut.io.head(0).generation.expect(1.U) - dut.io.tail(0).bid.value.expect(0.U) - dut.io.tail(0).generation.expect(1.U) - - pokePrepare(dut, stid = 0, transactionId = 4, firstRid = 4, - boundaries = Seq(true -> true)) - dut.io.prepared.pointers(0).bid.value.expect(0.U) - dut.io.prepared.pointers(0).generation.expect(1.U) - } - } - - test("accepts an exact RID slot wrap only with the next RID generation") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 7, - boundaries = Seq(true -> false, false -> true)) - publish(dut) - pokeCommit(dut, stid = 0, - groups = Seq((7, 0, 0, true, false), (8, 0, 0, false, true))) - commit(dut) - dut.io.usedBlocks(0).expect(0.U) - } - } - - test("aggregates one block across 2 4 and 6-wide publication and 4-wide retire") { - Seq(2, 4, 6).foreach { width => - val p = OooParams( - instructionDecodeWidth = width, - retireGroupWidth = 4, - brobEntriesPerStid = 8) - simulate(new OooBrob(p)) { dut => - clear(dut) - val boundaries = (0 until width).map { index => - (index == 0) -> (index == width - 1) - } - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, boundaries) - dut.io.prepared.allocatedBlocks.expect(1.U) - publish(dut) - - val firstCount = math.min(width, 4) - val firstCommit = (0 until firstCount).map { index => - (index, 0, 0, index == 0, index == width - 1) - } - pokeCommit(dut, stid = 1, groups = firstCommit) - commit(dut) - if (width > 4) { - dut.io.usedBlocks(1).expect(1.U) - val secondCommit = (4 until width).map { index => - (index, 0, 0, false, index == width - 1) - } - pokeCommit(dut, stid = 1, groups = secondCommit) - commit(dut) - } - dut.io.usedBlocks(1).expect(0.U) - } - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooCtuIngressBridgeSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooCtuIngressBridgeSpec.scala deleted file mode 100644 index fd7586e9..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooCtuIngressBridgeSpec.scala +++ /dev/null @@ -1,340 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooCtuIngressBridgeSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams() - - private def clear(dut: OooCtuIngressBridge): Unit = { - dut.io.in.valid.poke(false.B) - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.out.ready.poke(false.B) - dut.io.parentClaim.ready.poke(false.B) - dut.io.expansionPlan.valid.poke(false.B) - dut.io.expansionPlan.bits.poke(0.U.asTypeOf(dut.io.expansionPlan.bits)) - dut.io.child.valid.poke(false.B) - dut.io.child.bits.poke(0.U.asTypeOf(dut.io.child.bits)) - dut.io.fence.foreach(_.poke(false.B)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryApply.poke(false.B) - dut.io.recoveryAbort.poke(false.B) - } - - private def pokeParent( - target: ArchitecturalParentRef, - stid: Int, - instructionId: Int, - epoch: Int = 3): Unit = { - target.poke(0.U.asTypeOf(target)) - target.key.valid.poke(true.B) - target.key.peId.poke(1.U) - target.key.stid.poke(stid.U) - target.key.instructionId.poke(instructionId.U) - target.key.epoch.poke(epoch.U) - target.pc.poke((0x1000 + instructionId * 4).U) - target.lengthBytes.poke(4.U) - target.traceOwner.poke(true.B) - target.prediction.epoch.poke(epoch.U) - } - - private def pokeNormalUop( - target: OooDecodedUop, - stid: Int, - instructionId: Int, - opcode: Int = 7): Unit = { - target.poke(0.U.asTypeOf(target)) - target.valid.poke(true.B) - target.identity.key.primaryParent.valid.poke(true.B) - target.identity.key.primaryParent.peId.poke(1.U) - target.identity.key.primaryParent.stid.poke(stid.U) - target.identity.key.primaryParent.instructionId.poke(instructionId.U) - target.identity.key.primaryParent.epoch.poke(3.U) - target.identity.key.uopCount.poke(1.U) - target.identity.parentCount.poke(1.U) - pokeParent(target.identity.parents(0), stid, instructionId) - target.opcode.poke(opcode.U) - target.recipe.valid.poke(true.B) - target.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - target.recipe.recipeKind.poke(OooOpcodeRecipeKind.Single.U) - target.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - target.recipe.dispatchWrites.poke(1.U) - target.recipe.dispatchDemand(0).poke(1.U) - target.plannedChildCount.poke(1.U) - } - - private def pokeMixedPacket( - dut: OooCtuIngressBridge, - stid: Int, - firstId: Int, - ctuId: Int, - lastId: Int): Unit = { - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.in.bits.peId.poke(1.U) - dut.io.in.bits.stid.poke(stid.U) - dut.io.in.bits.epoch.poke(3.U) - dut.io.in.bits.endOfStream.poke(true.B) - dut.io.in.bits.uopMask.poke(3.U) - pokeNormalUop(dut.io.in.bits.uops(0), stid, firstId) - pokeNormalUop(dut.io.in.bits.uops(1), stid, lastId, opcode = 8) - dut.io.in.bits.ctuParentMask.poke(2.U) - pokeParent(dut.io.in.bits.ctuParents(1).parent, stid, ctuId) - dut.io.in.bits.ctuParents(1).parent.rawInstruction.poke(0x1234.U) - } - - private def pokeCtuOnlyPacket( - dut: OooCtuIngressBridge, - stid: Int, - parentId: Int): Unit = { - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.in.bits.peId.poke(1.U) - dut.io.in.bits.stid.poke(stid.U) - dut.io.in.bits.epoch.poke(3.U) - dut.io.in.bits.endOfStream.poke(true.B) - dut.io.in.bits.ctuParentMask.poke(1.U) - pokeParent(dut.io.in.bits.ctuParents(0).parent, stid, parentId) - dut.io.in.bits.ctuParents(0).parent.rawInstruction.poke(0x5678.U) - } - - private def pokeLease( - target: OooCtuLeaseKey, - stid: Int, - parentId: Int, - groupId: Int = 0, - generation: Int = 0): Unit = { - target.poke(0.U.asTypeOf(target)) - target.valid.poke(true.B) - target.peId.poke(1.U) - target.stid.poke(stid.U) - target.parent.valid.poke(true.B) - target.parent.peId.poke(1.U) - target.parent.stid.poke(stid.U) - target.parent.instructionId.poke(parentId.U) - target.parent.epoch.poke(3.U) - target.templateGroupId.poke(groupId.U) - target.generation.poke(generation.U) - } - - private def pokePlan( - dut: OooCtuIngressBridge, - stid: Int, - parentId: Int, - childCount: Int): Unit = { - dut.io.expansionPlan.bits.poke(0.U.asTypeOf(dut.io.expansionPlan.bits)) - pokeLease(dut.io.expansionPlan.bits.lease, stid, parentId) - dut.io.expansionPlan.bits.childCount.poke(childCount.U) - } - - private def pokeChild( - dut: OooCtuIngressBridge, - stid: Int, - parentId: Int, - ordinal: Int, - childCount: Int): Unit = { - dut.io.child.bits.poke(0.U.asTypeOf(dut.io.child.bits)) - pokeLease(dut.io.child.bits.lease, stid, parentId) - dut.io.child.bits.ordinal.poke(ordinal.U) - dut.io.child.bits.childCount.poke(childCount.U) - dut.io.child.bits.finalChild.poke((ordinal == childCount - 1).B) - pokeNormalUop(dut.io.child.bits.uop, stid, parentId, opcode = 20 + ordinal) - } - - private def claimAndPlan( - dut: OooCtuIngressBridge, - stid: Int, - parentId: Int, - childCount: Int): Unit = { - dut.io.parentClaim.valid.expect(true.B) - dut.io.parentClaim.bits.lease.stid.expect(stid.U) - dut.io.parentClaim.bits.parent.parent.key.instructionId.expect(parentId.U) - dut.io.parentClaim.ready.poke(true.B) - dut.clock.step() - dut.io.parentClaim.ready.poke(false.B) - pokePlan(dut, stid, parentId, childCount) - dut.io.expansionPlan.valid.poke(true.B) - dut.io.expansionPlan.ready.expect(true.B) - dut.clock.step() - dut.io.expansionPlan.valid.poke(false.B) - } - - private def pokeRecovery( - target: OooGlobalRecoveryRequest, - stid: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.rename.key.member.group.valid.poke(true.B) - target.rename.key.member.group.peId.poke(1.U) - target.rename.key.member.group.stid.poke(stid.U) - target.rename.key.member.bid.valid.poke(true.B) - target.rename.key.member.bid.value.poke(4.U) - target.rename.key.epoch.poke(3.U) - target.triggerMemberCount.poke(1.U) - } - - test("preserves mixed parent order and reinserts a multi-RID child stream") { - simulate(new OooCtuIngressBridge(p)) { dut => - clear(dut) - pokeMixedPacket(dut, stid = 1, firstId = 10, ctuId = 11, lastId = 12) - dut.io.in.valid.poke(true.B) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - - dut.io.out.valid.expect(true.B) - dut.io.out.bits.uopMask.expect(1.U) - dut.io.out.bits.uops(0).identity.key.primaryParent.instructionId.expect(10.U) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - - dut.io.parentClaim.ready.poke(false.B) - dut.io.parentClaim.valid.expect(true.B) - dut.clock.step(2) - dut.io.parentClaim.valid.expect(true.B) - claimAndPlan(dut, stid = 1, parentId = 11, childCount = 6) - - for (ordinal <- 0 until 6) { - pokeChild(dut, stid = 1, parentId = 11, ordinal, childCount = 6) - dut.io.child.valid.poke(true.B) - if (ordinal == 0) { - dut.io.out.ready.poke(false.B) - dut.io.child.ready.expect(false.B) - dut.io.out.valid.expect(true.B) - dut.clock.step(2) - } - dut.io.out.ready.poke(true.B) - dut.io.child.ready.expect(true.B) - dut.io.out.bits.uops(0).identity.templateValid.expect(true.B) - dut.io.out.bits.uops(0).identity.key.uopOrdinal.expect(ordinal.U) - dut.io.out.bits.uops(0).identity.key.uopCount.expect(6.U) - dut.io.out.bits.uops(0).identity.parents(0).traceOwner.expect( - (ordinal == 5).B) - dut.io.out.bits.demand.instructionRows.expect( - (if (ordinal == 5) 1 else 0).U) - dut.clock.step() - dut.io.child.valid.poke(false.B) - } - dut.io.out.ready.poke(false.B) - - dut.io.out.valid.expect(true.B) - dut.io.out.bits.uops(0).identity.key.primaryParent.instructionId.expect(12.U) - dut.io.out.bits.endOfStream.expect(true.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.occupied(1).expect(false.B) - dut.io.active(1).expect(false.B) - } - } - - test("keeps unrelated STIDs moving while one CTU waits for children") { - simulate(new OooCtuIngressBridge(p)) { dut => - clear(dut) - pokeCtuOnlyPacket(dut, stid = 0, parentId = 20) - dut.io.in.valid.poke(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - claimAndPlan(dut, stid = 0, parentId = 20, childCount = 2) - dut.io.active(0).expect(true.B) - - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.in.bits.peId.poke(1.U) - dut.io.in.bits.stid.poke(2.U) - dut.io.in.bits.epoch.poke(3.U) - dut.io.in.bits.uopMask.poke(1.U) - pokeNormalUop(dut.io.in.bits.uops(0), stid = 2, instructionId = 30) - dut.io.in.valid.poke(true.B) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.stid.expect(2.U) - dut.io.out.bits.uops(0).identity.key.primaryParent.instructionId.expect(30.U) - } - } - - test("rejects stale plans and out-of-order children without advancing the lease") { - simulate(new OooCtuIngressBridge(p)) { dut => - clear(dut) - pokeCtuOnlyPacket(dut, stid = 1, parentId = 40) - dut.io.in.valid.poke(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.parentClaim.ready.poke(true.B) - dut.clock.step() - dut.io.parentClaim.ready.poke(false.B) - - pokePlan(dut, stid = 1, parentId = 40, childCount = 2) - dut.io.expansionPlan.bits.lease.generation.poke(7.U) - dut.io.expansionPlan.valid.poke(true.B) - dut.io.planRejected.valid.expect(true.B) - dut.io.planRejected.bits.reason.expect(OooCtuPlanRejectReason.StaleLease) - dut.clock.step() - pokePlan(dut, stid = 1, parentId = 40, childCount = 2) - dut.clock.step() - dut.io.expansionPlan.valid.poke(false.B) - - pokeChild(dut, stid = 1, parentId = 40, ordinal = 1, childCount = 2) - dut.io.child.valid.poke(true.B) - dut.io.childRejected.valid.expect(true.B) - dut.io.childRejected.bits.reason.expect(OooCtuChildRejectReason.WrongOrdinal) - dut.io.child.ready.expect(true.B) - dut.clock.step() - pokeChild(dut, stid = 1, parentId = 40, ordinal = 0, childCount = 2) - dut.io.out.ready.poke(true.B) - dut.io.childRejected.valid.expect(false.B) - dut.io.child.ready.expect(true.B) - } - } - - test("recovery prepare freezes an active lease and abort or apply is exact") { - simulate(new OooCtuIngressBridge(p)) { dut => - clear(dut) - pokeCtuOnlyPacket(dut, stid = 1, parentId = 50) - dut.io.in.valid.poke(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - claimAndPlan(dut, stid = 1, parentId = 50, childCount = 2) - - pokeRecovery(dut.io.recoveryPrepare.bits, stid = 1) - dut.io.recoveryPrepare.valid.poke(true.B) - dut.io.recoveryPrepare.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.recoveryPrepared.bits.expansionActive.expect(true.B) - - dut.io.cancel(1).poke(true.B) - dut.clock.step() - dut.io.cancel(1).poke(false.B) - dut.io.active(1).expect(true.B) - - pokeChild(dut, stid = 1, parentId = 50, ordinal = 0, childCount = 2) - dut.io.child.valid.poke(true.B) - dut.io.out.ready.poke(true.B) - dut.io.child.ready.expect(false.B) - dut.io.recoveryAbort.poke(true.B) - dut.clock.step() - dut.io.recoveryAbort.poke(false.B) - dut.io.child.ready.expect(true.B) - dut.clock.step() - dut.io.child.valid.poke(false.B) - - pokeRecovery(dut.io.recoveryPrepare.bits, stid = 1) - dut.io.recoveryPrepare.valid.poke(true.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryApply.poke(true.B) - dut.clock.step() - dut.io.recoveryApply.poke(false.B) - dut.io.active(1).expect(false.B) - dut.io.occupied(1).expect(false.B) - - pokeChild(dut, stid = 1, parentId = 50, ordinal = 1, childCount = 2) - dut.io.child.valid.poke(true.B) - dut.io.childRejected.valid.expect(true.B) - dut.io.childRejected.bits.reason.expect(OooCtuChildRejectReason.StaleLease) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooD1DecodeSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooD1DecodeSpec.scala index 58c43d28..67ce8d9e 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooD1DecodeSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooD1DecodeSpec.scala @@ -252,6 +252,58 @@ class OooD1DecodeSpec extends AnyFunSuite with ChiselSim { } } + test("normalizes compact load and store memory controls exactly once") { + val p = OooParams() + simulate(new OooD1Decode(p)) { dut => + clear(dut) + val cLwi = encoded("OP_C_LWI", (15, 11, 0x1e), (10, 6, 3)) + val cLdi = encoded("OP_C_LDI", (15, 11, 2), (10, 6, 4)) + val cSwi = encoded("OP_C_SWI", (15, 11, 0x1f), (10, 6, 5)) + val cSdi = encoded("OP_C_SDI", (15, 11, 1), (10, 6, 6)) + drive(dut, 0, "OP_C_LWI", cLwi, 40, 0x4000) + drive(dut, 1, "OP_C_LDI", cLdi, 41, 0x4002) + drive(dut, 2, "OP_C_SWI", cSwi, 42, 0x4004) + drive(dut, 3, "OP_C_SDI", cSdi, 43, 0x4006) + dut.io.in.bits.validMask.poke("b1111".U) + dut.io.in.valid.poke(true.B) + + val wordLoad = dut.io.out.bits.uops(0) + wordLoad.recipe.recipeKind.expect(OooOpcodeRecipeKind.ScalarLoad.U) + wordLoad.recipe.sideEffectOwner.expect(OooSideEffectOwner.Lsu.U) + wordLoad.recipe.pDestinationCount.expect(0.U) + wordLoad.recipe.tAllocationCount.expect(1.U) + wordLoad.destinations(0).kind.expect(DestinationKind.T) + wordLoad.memory.valid.expect(true.B) + wordLoad.memory.isLoad.expect(true.B) + wordLoad.memory.accessBytes.expect(4.U) + wordLoad.memory.signExtend.expect(true.B) + wordLoad.memory.offset.expect(BigInt("fffffffffffffff8", 16).U) + wordLoad.memory.addressSourceMask.expect(1.U) + + val doubleLoad = dut.io.out.bits.uops(1) + doubleLoad.destinations(0).kind.expect(DestinationKind.T) + doubleLoad.memory.accessBytes.expect(8.U) + doubleLoad.memory.signExtend.expect(false.B) + doubleLoad.memory.offset.expect(16.U) + + val wordStore = dut.io.out.bits.uops(2) + wordStore.recipe.recipeKind.expect(OooOpcodeRecipeKind.ScalarStore.U) + wordStore.memory.isStore.expect(true.B) + wordStore.memory.accessBytes.expect(4.U) + wordStore.memory.offset.expect(BigInt("fffffffffffffffc", 16).U) + wordStore.memory.addressSourceMask.expect(1.U) + wordStore.memory.dataSourceMask.expect(2.U) + wordStore.sources(0).operandClass.expect(OperandClass.P) + wordStore.sources(1).operandClass.expect(OperandClass.T) + + val doubleStore = dut.io.out.bits.uops(3) + doubleStore.memory.accessBytes.expect(8.U) + doubleStore.memory.offset.expect(8.U) + doubleStore.memory.addressSourceMask.expect(1.U) + doubleStore.memory.dataSourceMask.expect(2.U) + } + } + test("normalizes 32 and 48-bit ADDTPC page displacements to bytes") { val p = OooParams() simulate(new OooD1Decode(p)) { dut => diff --git a/chisel/src/test/scala/linxcore/ooo/OooD2GroupPlannerSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooD2GroupPlannerSpec.scala index 368bc380..2d5466fd 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooD2GroupPlannerSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooD2GroupPlannerSpec.scala @@ -118,8 +118,14 @@ class OooD2GroupPlannerSpec extends AnyFunSuite with ChiselSim { } } - test("splits before physical member overflow and computes member bases") { - val p = OooParams() + test("splits before physical member overflow with unequal identity and physical domains") { + val p = OooParams( + robIdentityMembersPerGroup = 4, + maxOrdinaryUopsPerGroup = 12, + maxRecipeUops = 32, + uopIdentityEntriesPerInstruction = 32) + assert(new RobMemberKey(p).memberIndex.getWidth == 2) + assert(new OooD2GroupedTransaction(p).uopMemberBase.head.getWidth == 4) simulate(new OooD2GroupPlanner(p)) { dut => clear(dut) for (index <- 0 until 4) { diff --git a/chisel/src/test/scala/linxcore/ooo/OooD3ReservationAllocatorSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooD3ReservationAllocatorSpec.scala deleted file mode 100644 index 6adcca1a..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooD3ReservationAllocatorSpec.scala +++ /dev/null @@ -1,490 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooD3ReservationAllocatorSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooD3ReservationAllocator): Unit = { - dut.io.in.valid.poke(false.B) - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.publishEligible.foreach(_.poke(true.B)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.out.ready.poke(false.B) - } - - private def pokePlan( - dut: OooD3ReservationAllocator, - stid: Int, - transactionId: Int, - groupCount: Int, - tailSlot: Int, - tailGeneration: Int, - tailEpoch: Int): Unit = { - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - val plan = dut.io.in.bits.plan - plan.stid.poke(stid.U) - plan.peId.poke(2.U) - plan.epoch.poke(3.U) - plan.transactionId.poke(transactionId.U) - plan.groupCount.poke(groupCount.U) - dut.io.in.bits.groupMask.poke(((1 << groupCount) - 1).U) - plan.virtualTailEpoch.poke(tailEpoch.U) - plan.firstVirtualGroup.valid.poke(true.B) - plan.firstVirtualGroup.peId.poke(2.U) - plan.firstVirtualGroup.stid.poke(stid.U) - plan.firstVirtualGroup.ridSlot.poke(tailSlot.U) - plan.firstVirtualGroup.ridGeneration.poke(tailGeneration.U) - dut.io.in.bits.decoded.peId.poke(2.U) - dut.io.in.bits.decoded.stid.poke(stid.U) - dut.io.in.bits.decoded.epoch.poke(3.U) - for (groupIndex <- 0 until groupCount) { - val absolute = tailSlot + groupIndex - val group = dut.io.in.bits.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(2.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((absolute % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((tailGeneration + absolute / dut.p.robGroupsPerStid).U) - } - dut.io.in.valid.poke(true.B) - } - - private def pokeRecoveryPlan( - dut: OooD3ReservationAllocator, - stid: Int, - oldOccupied: Int, - newOccupied: Int, - oldTailSlot: Int, - oldTailGeneration: Int, - newTailSlot: Int, - newTailGeneration: Int, - headSlot: Int = 0, - headGeneration: Int = 0): Unit = { - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.request.rename.key.member.group.valid.poke(true.B) - plan.request.rename.key.member.group.peId.poke(2.U) - plan.request.rename.key.member.group.stid.poke(stid.U) - plan.request.rename.key.member.bid.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(2.U) - plan.oldHead.stid.poke(stid.U) - plan.oldHead.ridSlot.poke(headSlot.U) - plan.oldHead.ridGeneration.poke(headGeneration.U) - plan.oldOccupied.poke(oldOccupied.U) - plan.pivotOffset.poke(math.max(0, newOccupied - 1).U) - plan.survivingPivotValid.poke((newOccupied > 0).B) - plan.newOccupied.poke(newOccupied.U) - plan.killedGroupCount.poke((oldOccupied - newOccupied).U) - plan.killedGroupMask.poke(((1 << (oldOccupied - newOccupied)) - 1).U) - plan.oldTail.valid.poke(true.B) - plan.oldTail.peId.poke(2.U) - plan.oldTail.stid.poke(stid.U) - plan.oldTail.ridSlot.poke(oldTailSlot.U) - plan.oldTail.ridGeneration.poke(oldTailGeneration.U) - plan.newTail.valid.poke(true.B) - plan.newTail.peId.poke(2.U) - plan.newTail.stid.poke(stid.U) - plan.newTail.ridSlot.poke(newTailSlot.U) - plan.newTail.ridGeneration.poke(newTailGeneration.U) - dut.io.recoveryPrepare.valid.poke(true.B) - } - - test("claims a fresh preview provisionally and publishes only on the S1 handshake") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 1, transactionId = 0, groupCount = 2, 0, 0, 0) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - - dut.io.tailSlot(1).expect(2.U) - dut.io.tailGeneration(1).expect(0.U) - dut.io.tailEpoch(1).expect(1.U) - dut.io.nextTransactionId(1).expect(1.U) - dut.io.usedGroups(1).expect(2.U) - dut.io.provisionalMask.expect("b0010".U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.claimEpoch.expect(0.U) - dut.io.out.bits.transaction.plan.transactionId.expect(0.U) - dut.clock.step(2) - dut.io.out.bits.transaction.plan.groupCount.expect(2.U) - - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.provisionalMask.expect(0.U) - dut.io.usedGroups(1).expect(2.U) - } - } - - test("prepares exact ROB-tail recovery and cancels an unexposed provisional row") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - - pokePlan(dut, 1, transactionId = 0, groupCount = 3, 0, 0, 0) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - dut.io.usedGroups(1).expect(3.U) - dut.io.publishedGroups(1).expect(3.U) - - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, 0) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.stid.expect(0.U) - dut.clock.step() - - pokePlan(dut, 1, transactionId = 1, groupCount = 2, 3, 0, 1) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.usedGroups(1).expect(5.U) - dut.io.publishedGroups(1).expect(3.U) - dut.io.tailSlot(1).expect(5.U) - dut.io.tailEpoch(1).expect(2.U) - - pokeRecoveryPlan(dut, stid = 1, oldOccupied = 3, newOccupied = 1, - oldTailSlot = 3, oldTailGeneration = 0, - newTailSlot = 1, newTailGeneration = 0) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryRejected.valid.expect(false.B) - dut.clock.step() - dut.io.usedGroups(1).expect(5.U) - dut.io.publishedGroups(1).expect(3.U) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedGroups(1).expect(1.U) - dut.io.publishedGroups(1).expect(1.U) - dut.io.tailSlot(1).expect(1.U) - dut.io.tailGeneration(1).expect(0.U) - dut.io.tailEpoch(1).expect(3.U) - dut.io.headSlot(1).expect(0.U) - dut.io.headGeneration(1).expect(0.U) - dut.io.provisionalMask.expect("b0001".U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.stid.expect(0.U) - } - } - - test("restores a wrapped absolute tail without rewinding transaction identity") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - dut.io.out.ready.poke(true.B) - - pokePlan(dut, 0, transactionId = 0, groupCount = 4, - tailSlot = 0, tailGeneration = 0, tailEpoch = 0) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.clock.step() - - dut.io.release.valid.poke(true.B) - dut.io.release.bits.firstGroup.valid.poke(true.B) - dut.io.release.bits.firstGroup.peId.poke(2.U) - dut.io.release.bits.firstGroup.stid.poke(0.U) - dut.io.release.bits.firstGroup.ridSlot.poke(0.U) - dut.io.release.bits.firstGroup.ridGeneration.poke(0.U) - dut.io.release.bits.headEpoch.poke(0.U) - dut.io.release.bits.groupCount.poke(4.U) - dut.io.release.ready.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - - pokePlan(dut, 0, transactionId = 1, groupCount = 4, - tailSlot = 4, tailGeneration = 0, tailEpoch = 2) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.clock.step() - pokePlan(dut, 0, transactionId = 2, groupCount = 2, - tailSlot = 0, tailGeneration = 1, tailEpoch = 3) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.clock.step() - - dut.io.headSlot(0).expect(4.U) - dut.io.headGeneration(0).expect(0.U) - dut.io.tailSlot(0).expect(2.U) - dut.io.tailGeneration(0).expect(1.U) - dut.io.tailEpoch(0).expect(4.U) - dut.io.nextTransactionId(0).expect(3.U) - dut.io.publishedGroups(0).expect(6.U) - - pokeRecoveryPlan(dut, stid = 0, oldOccupied = 6, - newOccupied = 4, oldTailSlot = 2, oldTailGeneration = 1, - newTailSlot = 0, newTailGeneration = 1, - headSlot = 4, headGeneration = 0) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - - dut.io.headSlot(0).expect(4.U) - dut.io.headGeneration(0).expect(0.U) - dut.io.tailSlot(0).expect(0.U) - dut.io.tailGeneration(0).expect(1.U) - dut.io.tailEpoch(0).expect(5.U) - dut.io.nextTransactionId(0).expect(3.U) - dut.io.usedGroups(0).expect(4.U) - dut.io.publishedGroups(0).expect(4.U) - - pokePlan(dut, 0, transactionId = 3, groupCount = 1, - tailSlot = 0, tailGeneration = 1, tailEpoch = 5) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.tailSlot(0).expect(1.U) - dut.io.tailGeneration(0).expect(1.U) - dut.io.nextTransactionId(0).expect(4.U) - } - } - - test("rejects a stale ROB recovery plan without allocator mutation") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 1, transactionId = 0, groupCount = 2, 0, 0, 0) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - - pokeRecoveryPlan(dut, stid = 1, oldOccupied = 2, newOccupied = 1, - oldTailSlot = 3, oldTailGeneration = 0, - newTailSlot = 1, newTailGeneration = 0) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedGroups(1).expect(2.U) - dut.io.publishedGroups(1).expect(2.U) - dut.io.tailSlot(1).expect(2.U) - dut.io.tailEpoch(1).expect(1.U) - } - } - - test("consumes a stale preview with zero allocator mutation") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 0, transactionId = 9, groupCount = 1, 0, 0, tailEpoch = 4) - dut.io.in.ready.expect(true.B) - dut.io.staleRejected.valid.expect(true.B) - dut.io.staleRejected.bits.plannedTailEpoch.expect(4.U) - dut.io.staleRejected.bits.liveTailEpoch.expect(0.U) - dut.clock.step() - dut.io.in.valid.poke(false.B) - - dut.io.tailSlot(0).expect(0.U) - dut.io.tailEpoch(0).expect(0.U) - dut.io.nextTransactionId(0).expect(0.U) - dut.io.usedGroups(0).expect(0.U) - dut.io.provisionalMask.expect(0.U) - - pokePlan(dut, 0, transactionId = 1, groupCount = 1, 0, 0, tailEpoch = 0) - dut.io.in.ready.expect(true.B) - dut.io.staleRejected.valid.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.tailSlot(0).expect(0.U) - dut.io.tailEpoch(0).expect(0.U) - dut.io.nextTransactionId(0).expect(0.U) - dut.io.usedGroups(0).expect(0.U) - - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, tailEpoch = 0) - dut.io.in.bits.groups(0).key.peId.poke(7.U) - dut.io.in.ready.expect(true.B) - dut.io.staleRejected.valid.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.tailSlot(0).expect(0.U) - dut.io.tailEpoch(0).expect(0.U) - dut.io.usedGroups(0).expect(0.U) - - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, tailEpoch = 0) - dut.io.in.bits.plan.groupCount.poke(5.U) - dut.io.in.ready.expect(true.B) - dut.io.staleRejected.valid.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.usedGroups(0).expect(0.U) - - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, tailEpoch = 0) - dut.io.in.bits.groups(1).valid.poke(true.B) - dut.io.in.bits.groups(1).key.valid.poke(true.B) - dut.io.in.ready.expect(true.B) - dut.io.staleRejected.valid.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.usedGroups(0).expect(0.U) - } - } - - test("skips an ineligible STID and publishes another provisional row") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, 0) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.publishEligible(0).poke(false.B) - dut.io.out.valid.expect(false.B) - - pokePlan(dut, 1, transactionId = 0, groupCount = 1, 0, 0, 0) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.provisionalMask.expect("b0011".U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.stid.expect(1.U) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - dut.io.provisionalMask.expect("b0001".U) - - dut.io.publishEligible(0).poke(true.B) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.stid.expect(0.U) - } - } - - test("never withdraws an exposed grant when eligibility changes") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 0, transactionId = 0, groupCount = 1, 0, 0, 0) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.transactionId.expect(0.U) - dut.clock.step() // capture the exposed blocked grant - - dut.io.publishEligible(0).poke(false.B) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.transactionId.expect(0.U) - dut.clock.step(3) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.transaction.plan.transactionId.expect(0.U) - - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.provisionalMask.expect(0.U) - } - } - - test("rolls back only a canceled provisional claim and preserves published usage") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - pokePlan(dut, 2, transactionId = 0, groupCount = 2, 0, 0, 0) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - - pokePlan(dut, 2, transactionId = 1, groupCount = 3, 2, 0, 1) - dut.io.in.ready.expect(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.tailSlot(2).expect(5.U) - dut.io.usedGroups(2).expect(5.U) - - dut.io.cancel(2).poke(true.B) - dut.clock.step() - dut.io.cancel(2).poke(false.B) - dut.io.tailSlot(2).expect(2.U) - dut.io.tailGeneration(2).expect(0.U) - dut.io.tailEpoch(2).expect(3.U) - dut.io.usedGroups(2).expect(2.U) - dut.io.provisionalMask.expect(0.U) - } - } - - test("rejects inexact release and encodes retire width independently of decode width") { - val p = OooParams(instructionDecodeWidth = 2, retireGroupWidth = 4, robGroupsPerStid = 8) - simulate(new OooD3ReservationAllocator(p)) { dut => - clear(dut) - - pokePlan(dut, 0, transactionId = 0, groupCount = 2, 0, 0, 0) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - - pokePlan(dut, 0, transactionId = 1, groupCount = 2, 2, 0, 1) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - pokePlan(dut, 0, transactionId = 2, groupCount = 2, 4, 0, 2) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.ready.poke(false.B) - dut.io.usedGroups(0).expect(6.U) - dut.io.publishedGroups(0).expect(6.U) - - dut.io.release.valid.poke(true.B) - dut.io.release.bits.firstGroup.valid.poke(true.B) - dut.io.release.bits.firstGroup.peId.poke(2.U) - dut.io.release.bits.firstGroup.stid.poke(0.U) - dut.io.release.bits.firstGroup.ridSlot.poke(0.U) - dut.io.release.bits.firstGroup.ridGeneration.poke(1.U) - dut.io.release.bits.headEpoch.poke(0.U) - dut.io.release.bits.groupCount.poke(4.U) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.usedGroups(0).expect(6.U) - dut.io.publishedGroups(0).expect(6.U) - dut.io.headSlot(0).expect(0.U) - - dut.io.release.bits.firstGroup.ridGeneration.poke(0.U) - dut.io.release.bits.groupCount.poke(5.U) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.usedGroups(0).expect(6.U) - dut.io.publishedGroups(0).expect(6.U) - - dut.io.release.bits.groupCount.poke(4.U) - dut.io.release.ready.expect(true.B) - dut.io.releaseRejected.valid.expect(false.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.usedGroups(0).expect(2.U) - dut.io.publishedGroups(0).expect(2.U) - dut.io.headSlot(0).expect(4.U) - dut.io.headGeneration(0).expect(0.U) - dut.io.headEpoch(0).expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooD3S1BrobIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooD3S1BrobIntegrationSpec.scala deleted file mode 100644 index c0c441bf..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooD3S1BrobIntegrationSpec.scala +++ /dev/null @@ -1,150 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.Decoupled -import org.scalatest.funsuite.AnyFunSuite - -private class OooD3S1BrobHarnessIO(val p: OooParams) extends Bundle { - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val commitReady = Input(Bool()) - val d3Used = Output(UInt(p.countWidth(p.robGroupsPerStid).W)) - val d3Published = Output(UInt(p.countWidth(p.robGroupsPerStid).W)) - val s1Occupied = Output(UInt(p.countWidth(p.robGroupsPerStid).W)) - val brobUsed = Output(UInt(p.brobCountWidth.W)) - val commitValid = Output(Bool()) -} - -private class OooD3S1BrobHarness(val p: OooParams) extends Module { - val io = IO(new OooD3S1BrobHarnessIO(p)) - val d3 = Module(new OooD3ReservationAllocator(p)) - val s1 = Module(new OooS1GroupedRob(p)) - val brob = Module(new OooBrob(p)) - - d3.io.in <> io.reserve - d3.io.cancel.foreach(_ := false.B) - d3.io.publishEligible.foreach(_ := true.B) - d3.io.recoveryPrepare.valid := false.B - d3.io.recoveryPrepare.bits := 0.U.asTypeOf(d3.io.recoveryPrepare.bits) - d3.io.recoveryFire := false.B - brob.io.prepare.valid := d3.io.out.valid - brob.io.prepare.bits := d3.io.out.bits - brob.io.recoveryPrepare.valid := false.B - brob.io.recoveryPrepare.bits := - 0.U.asTypeOf(brob.io.recoveryPrepare.bits) - brob.io.recoveryFire := false.B - - s1.io.publish.valid := d3.io.out.valid && brob.io.prepareReady - s1.io.publish.bits := 0.U.asTypeOf(s1.io.publish.bits) - s1.io.publish.bits.reservation := d3.io.out.bits - for (groupIndex <- 0 until p.instructionDecodeWidth) { - val active = d3.io.out.bits.transaction.groups(groupIndex).valid - val binding = s1.io.publish.bits.bindings(groupIndex) - binding.valid := active - binding.brob := brob.io.prepared.pointers(groupIndex) - binding.residentGeneration := - d3.io.out.bits.transaction.groups(groupIndex).key.ridGeneration - binding.initiallyCompletedMembers := Mux(active, 1.U, 0.U) - } - d3.io.out.ready := brob.io.prepareReady && s1.io.publish.ready - val sharedPublishFire = d3.io.out.valid && d3.io.out.ready - brob.io.publishFire := sharedPublishFire - - s1.io.completion.valid := false.B - s1.io.completion.bits := 0.U.asTypeOf(s1.io.completion.bits) - s1.io.nonFlushEvidence.valid := false.B - s1.io.nonFlushEvidence.bits := 0.U.asTypeOf(s1.io.nonFlushEvidence.bits) - s1.io.interruptPending.foreach(_ := false.B) - s1.io.recoveryPrepare.valid := false.B - s1.io.recoveryPrepare.bits := 0.U.asTypeOf(s1.io.recoveryPrepare.bits) - s1.io.recoveryFire := false.B - brob.io.commit.bits := s1.io.commit.bits - d3.io.release.bits := s1.io.commit.bits.release - val allCommitReady = brob.io.commit.ready && d3.io.release.ready - io.commitValid := s1.io.commit.valid && allCommitReady - s1.io.commit.ready := io.commitReady && allCommitReady - val sharedCommitFire = io.commitValid && io.commitReady - brob.io.commit.valid := sharedCommitFire - d3.io.release.valid := sharedCommitFire - - io.d3Used := d3.io.usedGroups(1) - io.d3Published := d3.io.publishedGroups(1) - io.s1Occupied := s1.io.occupiedGroups(1) - io.brobUsed := brob.io.usedBlocks(1) -} - -class OooD3S1BrobIntegrationSpec extends AnyFunSuite with ChiselSim { - test("publishes and retires D3 grouped ROB and BROB state in one shared transaction") { - val p = OooParams( - instructionDecodeWidth = 2, - retireGroupWidth = 4, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooD3S1BrobHarness(p)) { dut => - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.commitReady.poke(false.B) - - val transaction = dut.io.reserve.bits - transaction.plan.peId.poke(4.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(0.U) - transaction.plan.groupCount.poke(2.U) - transaction.plan.virtualTailEpoch.poke(0.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(4.U) - transaction.plan.firstVirtualGroup.stid.poke(1.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(0.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(0.U) - transaction.decoded.peId.poke(4.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.groupMask.poke(3.U) - for (groupIndex <- 0 until 2) { - val group = transaction.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(4.U) - group.key.stid.poke(1.U) - group.key.ridSlot.poke(groupIndex.U) - group.key.ridGeneration.poke(0.U) - group.logicalUopMask.poke((1 << groupIndex).U) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - group.boundaryStart.poke((groupIndex == 0).B) - group.boundaryStop.poke((groupIndex == 1).B) - } - - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.d3Used.expect(2.U) - dut.io.d3Published.expect(0.U) - dut.io.s1Occupied.expect(0.U) - dut.io.brobUsed.expect(0.U) - - dut.clock.step() - dut.io.d3Published.expect(2.U) - dut.io.s1Occupied.expect(2.U) - dut.io.brobUsed.expect(1.U) - - dut.clock.step() - dut.io.commitValid.expect(true.B) - dut.clock.step(2) - dut.io.commitValid.expect(true.B) - dut.io.d3Used.expect(2.U) - dut.io.d3Published.expect(2.U) - dut.io.s1Occupied.expect(2.U) - dut.io.brobUsed.expect(1.U) - dut.io.commitReady.poke(true.B) - dut.clock.step() - dut.io.commitReady.poke(false.B) - dut.io.d3Used.expect(0.U) - dut.io.d3Published.expect(0.U) - dut.io.s1Occupied.expect(0.U) - dut.io.brobUsed.expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooD3S1GroupedRobIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooD3S1GroupedRobIntegrationSpec.scala deleted file mode 100644 index 1d9d1daf..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooD3S1GroupedRobIntegrationSpec.scala +++ /dev/null @@ -1,146 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.Decoupled -import org.scalatest.funsuite.AnyFunSuite - -private class OooD3S1GroupedRobHarnessIO(val p: OooParams) extends Bundle { - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val bindings = Input(Vec(p.instructionDecodeWidth, new OooS1GroupBinding(p))) - val commit = Decoupled(new OooRobCommitBatch(p)) - val cancel = Input(Vec(p.stidCount, Bool())) - val d3Used = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3Published = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val d3HeadEpoch = Output(Vec(p.stidCount, UInt(p.reservationEpochWidth.W))) - val s1Occupied = Output(Vec(p.stidCount, UInt(p.countWidth(p.robGroupsPerStid).W))) - val s1HeadEpoch = Output(Vec(p.stidCount, UInt(p.reservationEpochWidth.W))) -} - -private class OooD3S1GroupedRobHarness(val p: OooParams) extends Module { - val io = IO(new OooD3S1GroupedRobHarnessIO(p)) - - val d3 = Module(new OooD3ReservationAllocator(p)) - val s1 = Module(new OooS1GroupedRob(p)) - d3.io.in <> io.reserve - d3.io.cancel := io.cancel - d3.io.publishEligible.foreach(_ := true.B) - d3.io.recoveryPrepare.valid := false.B - d3.io.recoveryPrepare.bits := 0.U.asTypeOf(d3.io.recoveryPrepare.bits) - d3.io.recoveryFire := false.B - - s1.io.publish.valid := d3.io.out.valid - s1.io.publish.bits.reservation := d3.io.out.bits - s1.io.publish.bits.bindings := io.bindings - d3.io.out.ready := s1.io.publish.ready - - s1.io.completion.valid := false.B - s1.io.completion.bits := 0.U.asTypeOf(s1.io.completion.bits) - s1.io.nonFlushEvidence.valid := false.B - s1.io.nonFlushEvidence.bits := 0.U.asTypeOf(s1.io.nonFlushEvidence.bits) - s1.io.interruptPending.foreach(_ := false.B) - s1.io.recoveryPrepare.valid := false.B - s1.io.recoveryPrepare.bits := 0.U.asTypeOf(s1.io.recoveryPrepare.bits) - s1.io.recoveryFire := false.B - d3.io.release.bits := s1.io.commit.bits.release - io.commit.valid := s1.io.commit.valid && d3.io.release.ready - io.commit.bits := s1.io.commit.bits - s1.io.commit.ready := io.commit.ready && d3.io.release.ready - val sharedCommitFire = io.commit.valid && io.commit.ready - d3.io.release.valid := sharedCommitFire - - io.d3Used := d3.io.usedGroups - io.d3Published := d3.io.publishedGroups - io.d3HeadEpoch := d3.io.headEpoch - io.s1Occupied := s1.io.occupiedGroups - io.s1HeadEpoch := s1.io.headEpoch -} - -class OooD3S1GroupedRobIntegrationSpec extends AnyFunSuite with ChiselSim { - test("publishes and retires one exact grouped transaction across D3 and S1") { - val p = OooParams( - instructionDecodeWidth = 2, - retireGroupWidth = 4, - robGroupsPerStid = 8) - simulate(new OooD3S1GroupedRobHarness(p)) { dut => - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.bindings.foreach(_.poke(0.U.asTypeOf(dut.io.bindings.head))) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.commit.ready.poke(false.B) - - val transaction = dut.io.reserve.bits - transaction.plan.peId.poke(6.U) - transaction.plan.stid.poke(2.U) - transaction.plan.epoch.poke(9.U) - transaction.plan.transactionId.poke(0.U) - transaction.plan.groupCount.poke(2.U) - transaction.plan.virtualTailEpoch.poke(0.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(6.U) - transaction.plan.firstVirtualGroup.stid.poke(2.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(0.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(0.U) - transaction.decoded.peId.poke(6.U) - transaction.decoded.stid.poke(2.U) - transaction.decoded.epoch.poke(9.U) - transaction.groupMask.poke(3.U) - for (groupIndex <- 0 until 2) { - val group = transaction.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(6.U) - group.key.stid.poke(2.U) - group.key.ridSlot.poke(groupIndex.U) - group.key.ridGeneration.poke(0.U) - group.logicalUopMask.poke((1 << groupIndex).U) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - - val binding = dut.io.bindings(groupIndex) - binding.valid.poke(true.B) - binding.brob.valid.poke(true.B) - binding.brob.bid.valid.poke(true.B) - binding.brob.bid.value.poke(12.U) - binding.brob.generation.poke(4.U) - binding.residentGeneration.poke(3.U) - binding.initiallyCompletedMembers.poke(1.U) - } - - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.d3Used(2).expect(2.U) - dut.io.d3Published(2).expect(0.U) - - dut.clock.step() - dut.io.d3Used(2).expect(2.U) - dut.io.d3Published(2).expect(2.U) - dut.io.s1Occupied(2).expect(2.U) - - dut.clock.step() - dut.io.commit.valid.expect(false.B) - dut.clock.step() - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.firstGroup.stid.expect(2.U) - dut.io.commit.bits.release.firstGroup.ridSlot.expect(0.U) - dut.io.commit.bits.release.headEpoch.expect(0.U) - dut.io.commit.bits.release.groupCount.expect(2.U) - dut.clock.step(2) - dut.io.commit.valid.expect(true.B) - dut.io.d3Used(2).expect(2.U) - dut.io.d3Published(2).expect(2.U) - dut.io.s1Occupied(2).expect(2.U) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - - dut.io.d3Used(2).expect(0.U) - dut.io.d3Published(2).expect(0.U) - dut.io.s1Occupied(2).expect(0.U) - dut.io.d3HeadEpoch(2).expect(1.U) - dut.io.s1HeadEpoch(2).expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooDispatchSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooDispatchSpec.scala deleted file mode 100644 index dff4fa17..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooDispatchSpec.scala +++ /dev/null @@ -1,604 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -private object OooDispatchSpec { - final case class Token( - uopClass: Int, - bank: Int, - port: Int, - slot: Int, - epoch: Int, - lane: Int, - uopIndex: Int, - childIndex: Int) -} - -class OooDispatchSpec extends AnyFunSuite with ChiselSim { - import OooDispatchSpec._ - - private def clear(dut: OooDispatch): Unit = { - dut.io.prepare.valid.poke(false.B) - dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - dut.io.reserveFire.poke(false.B) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.publish.valid.poke(false.B) - dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) - dut.io.releases.foreach { release => - release.valid.poke(false.B) - release.bits.poke(0.U.asTypeOf(release.bits)) - } - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - } - - private def pokeTransaction( - dut: OooDispatch, - stid: Int, - transactionId: Int, - demands: Vector[Vector[Int]], - plannedOverride: Option[Vector[Int]] = None, - capabilities: Option[Vector[Vector[Int]]] = None): Unit = { - require(demands.length <= dut.p.decodedUopWidth) - require(demands.forall(_.length == dut.p.iqClassCount)) - val transaction = dut.io.prepare.bits - transaction.poke(0.U.asTypeOf(transaction)) - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(5.U) - val uopMask = (1 << demands.length) - 1 - transaction.plan.uopMask.poke(uopMask.U) - transaction.decoded.uopMask.poke(uopMask.U) - for (uopIndex <- demands.indices) { - val uop = transaction.decoded.uops(uopIndex) - val total = demands(uopIndex).sum - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.recipe.dispatchWrites.poke(total.U) - for (uopClass <- 0 until dut.p.iqClassCount) { - uop.recipe.dispatchDemand(uopClass).poke( - demands(uopIndex)(uopClass).U) - val defaultCapability = uopClass match { - case 0 => BigInt(1) << OooIexDomainCapability.SimpleAlu - case 1 => BigInt(1) << OooIexDomainCapability.Branch - case 2 => BigInt(1) << OooIexDomainCapability.LoadAddress - case 3 => BigInt(1) << OooIexDomainCapability.StoreData - case 4 => BigInt(1) << OooIexDomainCapability.FloatingVector - case 5 => BigInt(1) << OooIexDomainCapability.System - case 6 => BigInt(1) << OooIexDomainCapability.EngineCommand - case _ => BigInt(0) - } - val capability = capabilities - .map(_(uopIndex)(uopClass)) - .getOrElse(if (demands(uopIndex)(uopClass) != 0) - defaultCapability.toInt else 0) - uop.recipe.dispatchCapabilities(uopClass).poke(capability.U) - } - } - val planned = plannedOverride.getOrElse(Vector.tabulate( - dut.p.iqClassCount) { uopClass => - demands.map(_(uopClass)).sum - }) - for (uopClass <- 0 until dut.p.iqClassCount) { - transaction.plan.demand.dispatchWritesByClass(uopClass).poke( - planned(uopClass).U) - } - dut.io.prepare.valid.poke(true.B) - } - - private def capture(dut: OooDispatch): Vector[Token] = - (0 until dut.p.dispatchWidth).flatMap { lane => - val allocation = dut.io.prepared.allocations(lane) - if (allocation.valid.peek().litToBoolean) { - Some(Token( - uopClass = allocation.reservation.uopClass.peek().litValue.toInt, - bank = allocation.reservation.bank.peek().litValue.toInt, - port = allocation.reservation.writePort.peek().litValue.toInt, - slot = allocation.reservation.speculativeSlot.peek().litValue.toInt, - epoch = allocation.reservation.reservationEpoch.peek().litValue.toInt, - lane = lane, - uopIndex = allocation.uopIndex.peek().litValue.toInt, - childIndex = allocation.childIndex.peek().litValue.toInt)) - } else { - None - } - }.toVector - - private def pokeClass(target: OooUopClass.Type, value: Int): Unit = - value match { - case 0 => target.poke(OooUopClass.Alu) - case 1 => target.poke(OooUopClass.Bru) - case 2 => target.poke(OooUopClass.Agu) - case 3 => target.poke(OooUopClass.Std) - case 4 => target.poke(OooUopClass.Fsu) - case 5 => target.poke(OooUopClass.Sys) - case 6 => target.poke(OooUopClass.Cmd) - case 7 => target.poke(OooUopClass.Boundary) - } - - private def release( - dut: OooDispatch, - stid: Int, - transactionId: Int, - token: Token): Unit = { - val request = dut.io.release.bits - request.poke(0.U.asTypeOf(request)) - request.peId.poke(3.U) - request.stid.poke(stid.U) - request.epoch.poke(5.U) - request.transactionId.poke(transactionId.U) - pokeMember(request.member, stid, transactionId, token.lane) - request.reservation.valid.poke(true.B) - pokeClass(request.reservation.uopClass, token.uopClass) - request.reservation.bank.poke(token.bank.U) - request.reservation.writePort.poke(token.port.U) - request.reservation.speculativeSlot.poke(token.slot.U) - request.reservation.reservationEpoch.poke(token.epoch.U) - dut.io.release.valid.poke(true.B) - dut.io.release.ready.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - } - - private def reserve( - dut: OooDispatch, - stid: Int, - transactionId: Int, - demands: Vector[Vector[Int]]): Vector[Token] = { - pokeTransaction(dut, stid, transactionId, demands) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.valid.expect(true.B) - val tokens = capture(dut) - dut.io.reserveFire.poke(true.B) - dut.clock.step() - dut.io.reserveFire.poke(false.B) - dut.io.prepare.valid.poke(false.B) - tokens - } - - private def publish( - dut: OooDispatch, - stid: Int, - transactionId: Int, - tokens: Vector[Token]): Unit = { - dut.io.publish.bits.peId.poke(3.U) - dut.io.publish.bits.stid.poke(stid.U) - dut.io.publish.bits.epoch.poke(5.U) - dut.io.publish.bits.transactionId.poke(transactionId.U) - dut.io.publish.bits.memberMask.poke( - tokens.map(token => 1 << token.lane).sum.U) - tokens.foreach { token => - pokeMember(dut.io.publish.bits.members(token.lane), - stid, transactionId, token.lane) - } - dut.io.publish.valid.poke(true.B) - dut.io.publishRejected.valid.expect(false.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - } - - private def pokeMember( - member: RobMemberKey, - stid: Int, - transactionId: Int, - memberIndex: Int): Unit = { - member.poke(0.U.asTypeOf(member)) - member.group.valid.poke(true.B) - member.group.peId.poke(3.U) - member.group.stid.poke(stid.U) - member.group.ridSlot.poke((transactionId & 7).U) - member.group.ridGeneration.poke(0.U) - member.bid.valid.poke(true.B) - member.bid.value.poke((stid + 1).U) - member.brobGeneration.poke(0.U) - member.memberIndex.poke(memberIndex.U) - member.residentGeneration.poke(1.U) - } - - private def pokeRecoveryPlan( - dut: OooDispatch, - stid: Int, - pivotPhysicalMembers: Int, - survivingPhysicalMembers: Int): Unit = { - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(stid.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(0.U) - plan.oldOccupied.poke(1.U) - plan.newOccupied.poke(1.U) - plan.pivotOffset.poke(0.U) - pokeMember(plan.pivot, stid, transactionId = 0, memberIndex = 0) - plan.pivotPhysicalMemberCount.poke(pivotPhysicalMembers.U) - plan.survivingPivotValid.poke(true.B) - plan.survivingPivotPhysicalMemberCount - .poke(survivingPhysicalMembers.U) - dut.io.recoveryPrepare.valid.poke(true.B) - } - - test("reserves publishes releases and generation-qualifies a split bundle") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 4, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val zero = Vector.fill(p.iqClassCount)(0) - val alu = zero.updated(0, 1) - val aguStd = zero.updated(2, 1).updated(3, 1) - val first = reserve(dut, stid = 1, transactionId = 0, - demands = Vector(alu, aguStd)) - assert(first.map(_.uopClass) == Vector(0, 2, 3)) - assert(first.map(_.uopIndex) == Vector(0, 1, 1)) - assert(first.map(_.childIndex) == Vector(0, 0, 1)) - first.foreach(token => assert(token.epoch == 1)) - dut.io.provisional(1).valid.expect(true.B) - dut.io.provisionalEntries(0)(0).expect(1.U) - dut.io.provisionalEntries(2)(1).expect(1.U) - dut.io.provisionalEntries(3)(0).expect(1.U) - - publish(dut, stid = 1, transactionId = 0, first) - dut.io.provisional(1).valid.expect(false.B) - dut.io.publishedEntries(0)(0).expect(1.U) - dut.io.publishedEntries(2)(1).expect(1.U) - dut.io.publishedEntries(3)(0).expect(1.U) - first.foreach(token => release(dut, 1, 0, token)) - dut.io.publishedEntries(0)(0).expect(0.U) - - val second = reserve(dut, stid = 1, transactionId = 2, - demands = Vector(alu, aguStd)) - assert(second.map(_.bank) == first.map(_.bank)) - assert(second.map(_.slot) == first.map(_.slot)) - second.foreach(token => assert(token.epoch == 2)) - dut.io.publish.bits.peId.poke(3.U) - dut.io.publish.bits.stid.poke(1.U) - dut.io.publish.bits.epoch.poke(4.U) - dut.io.publish.bits.transactionId.poke(2.U) - dut.io.publish.valid.poke(true.B) - dut.io.publishRejected.valid.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.provisional(1).valid.expect(true.B) - - dut.io.publish.bits.epoch.poke(5.U) - dut.io.publish.valid.poke(true.B) - dut.io.cancel(1).poke(true.B) - dut.io.publishRejected.valid.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.cancel(1).poke(false.B) - dut.io.provisional(1).valid.expect(false.B) - second.foreach { token => - dut.io.freeEntries(token.uopClass)(token.bank).expect(4.U) - } - } - } - - test("releases two independent published slots and rejects a duplicate pair") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iexIssueDomainCount = 2, - iexReleaseWidth = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val zero = Vector.fill(p.iqClassCount)(0) - val tokens = reserve(dut, stid = 1, transactionId = 0, - demands = Vector(zero.updated(0, 1), zero.updated(1, 1))) - publish(dut, stid = 1, transactionId = 0, tokens) - - def pokeLane(lane: Int, token: Token): Unit = { - val request = dut.io.releases(lane).bits - request.poke(0.U.asTypeOf(request)) - request.peId.poke(3.U) - request.stid.poke(1.U) - request.epoch.poke(5.U) - request.transactionId.poke(0.U) - pokeMember(request.member, 1, 0, token.lane) - request.reservation.valid.poke(true.B) - pokeClass(request.reservation.uopClass, token.uopClass) - request.reservation.bank.poke(token.bank.U) - request.reservation.writePort.poke(token.port.U) - request.reservation.speculativeSlot.poke(token.slot.U) - request.reservation.reservationEpoch.poke(token.epoch.U) - dut.io.releases(lane).valid.poke(true.B) - } - - pokeLane(0, tokens(0)) - pokeLane(1, tokens(1)) - dut.io.releases.foreach(_.ready.expect(true.B)) - dut.clock.step() - dut.io.releases.foreach(_.valid.poke(false.B)) - dut.io.publishedEntries(0)(tokens(0).bank).expect(0.U) - dut.io.publishedEntries(1)(tokens(1).bank).expect(0.U) - - val duplicate = reserve(dut, stid = 1, transactionId = 2, - demands = Vector(zero.updated(0, 1))).head - publish(dut, stid = 1, transactionId = 2, Vector(duplicate)) - pokeLane(0, duplicate) - pokeLane(1, duplicate) - dut.io.releases.foreach(_.ready.expect(false.B)) - dut.io.releaseRejecteds.foreach(_.valid.expect(true.B)) - dut.clock.step() - dut.io.releases.foreach(_.valid.poke(false.B)) - dut.io.publishedEntries(0)(duplicate.bank).expect(1.U) - } - } - - test("isolates STID leases and rejects demand or port overbooking atomically") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 4, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 1, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val zero = Vector.fill(p.iqClassCount)(0) - val alu = zero.updated(0, 1) - reserve(dut, stid = 0, transactionId = 0, demands = Vector(alu)) - val stid2 = reserve(dut, stid = 2, transactionId = 0, - demands = Vector(alu)) - dut.io.provisional(0).valid.expect(true.B) - dut.io.provisional(2).valid.expect(true.B) - dut.io.cancel(0).poke(true.B) - dut.clock.step() - dut.io.cancel(0).poke(false.B) - dut.io.provisional(0).valid.expect(false.B) - dut.io.provisional(2).valid.expect(true.B) - publish(dut, stid = 2, transactionId = 0, stid2) - - val twoAlu = zero.updated(0, 2) - pokeTransaction(dut, stid = 1, transactionId = 0, - demands = Vector(twoAlu, twoAlu)) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.io.reserveFire.poke(false.B) - dut.clock.step() - dut.io.prepare.valid.poke(false.B) - dut.io.provisional(1).valid.expect(false.B) - - pokeTransaction(dut, stid = 3, transactionId = 0, - demands = Vector(alu), - plannedOverride = Some(zero.updated(1, 1))) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.io.provisional(3).valid.expect(false.B) - } - } - - test("rejects stale published-slot release without freeing it") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val alu = Vector.fill(p.iqClassCount)(0).updated(0, 1) - val token = reserve(dut, stid = 0, transactionId = 0, - demands = Vector(alu)).head - publish(dut, stid = 0, transactionId = 0, Vector(token)) - - val stale = token.copy(epoch = token.epoch + 1) - val request = dut.io.release.bits - request.poke(0.U.asTypeOf(request)) - request.peId.poke(3.U) - request.stid.poke(0.U) - request.epoch.poke(5.U) - request.transactionId.poke(0.U) - pokeMember(request.member, 0, 0, token.lane) - request.reservation.valid.poke(true.B) - pokeClass(request.reservation.uopClass, stale.uopClass) - request.reservation.bank.poke(stale.bank.U) - request.reservation.writePort.poke(stale.port.U) - request.reservation.speculativeSlot.poke(stale.slot.U) - request.reservation.reservationEpoch.poke(stale.epoch.U) - dut.io.release.valid.poke(true.B) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.publishedEntries(token.uopClass)(token.bank).expect(1.U) - - request.reservation.reservationEpoch.poke(token.epoch.U) - request.reservation.writePort.poke((token.port ^ 1).U) - dut.io.release.valid.poke(true.B) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.publishedEntries(token.uopClass)(token.bank).expect(1.U) - release(dut, 0, 0, token) - } - } - - test("recovers provisional state and an exact published member suffix") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 4, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val zero = Vector.fill(p.iqClassCount)(0) - val twoAlu = zero.updated(0, 2) - val oneAlu = zero.updated(0, 1) - val published = reserve(dut, stid = 1, transactionId = 0, - demands = Vector(twoAlu, oneAlu)) - publish(dut, stid = 1, transactionId = 0, published) - val provisional = reserve(dut, stid = 1, transactionId = 2, - demands = Vector(zero.updated(1, 1))) - val unrelated = reserve(dut, stid = 2, transactionId = 4, - demands = Vector(zero.updated(2, 1))) - - pokeRecoveryPlan(dut, stid = 1, pivotPhysicalMembers = 3, - survivingPhysicalMembers = 1) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.recoveryPrepared.provisionalKilled.expect(1.U) - dut.io.recoveryPrepared.publishedKilled.expect(2.U) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - - dut.io.provisional(1).valid.expect(false.B) - dut.io.provisional(2).valid.expect(true.B) - dut.io.publishedByStid(1).expect(1.U) - assert(provisional.nonEmpty && unrelated.nonEmpty) - - release(dut, 1, 0, published.head) - dut.io.publishedByStid(1).expect(0.U) - val killed = published(1) - val request = dut.io.release.bits - request.poke(0.U.asTypeOf(request)) - request.peId.poke(3.U) - request.stid.poke(1.U) - request.epoch.poke(5.U) - request.transactionId.poke(0.U) - pokeMember(request.member, 1, 0, killed.lane) - request.reservation.valid.poke(true.B) - pokeClass(request.reservation.uopClass, killed.uopClass) - request.reservation.bank.poke(killed.bank.U) - request.reservation.writePort.poke(killed.port.U) - request.reservation.speculativeSlot.poke(killed.slot.U) - request.reservation.reservationEpoch.poke(killed.epoch.U) - dut.io.release.valid.poke(true.B) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - } - } - - test("preserves first-free allocation across hierarchical leaf boundaries") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 4, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 8, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooDispatch(p)) { dut => - clear(dut) - val fourAlu = Vector.fill(p.iqClassCount)(0).updated(0, 2) - val demands = Vector(fourAlu, fourAlu) - - val first = reserve(dut, stid = 0, transactionId = 0, demands) - publish(dut, stid = 0, transactionId = 0, first) - val second = reserve(dut, stid = 1, transactionId = 2, demands) - publish(dut, stid = 1, transactionId = 2, second) - val third = reserve(dut, stid = 2, transactionId = 4, demands) - - assert(first.map(_.slot) == Vector(0, 1, 0, 1)) - assert(second.map(_.slot) == Vector(2, 3, 2, 3)) - assert(third.map(_.slot) == Vector(4, 5, 4, 5)) - } - } - - test("admits only banks whose physical domain covers the recipe capability") { - import OooIexDomainCapability._ - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - val permissive = Seq.fill(p.iqClassCount)( - Seq.fill(p.iqBankCount)(ValidMask)) - val topology = OooIexCapabilityTopology(permissive - .updated(OooDispatchClass.Alu - 1, - Seq(mask(SimpleAlu), mask(MultiCycleAlu))) - .updated(OooDispatchClass.Agu - 1, - Seq(mask(LoadAddress, StoreAddress), mask(LoadAddress)))) - - simulate(new OooDispatch(p, topology)) { dut => - clear(dut) - val zero = Vector.fill(p.iqClassCount)(0) - val aluDemand = Vector(zero.updated(OooDispatchClass.Alu - 1, 1)) - val multiCaps = Vector(zero.updated(OooDispatchClass.Alu - 1, - mask(MultiCycleAlu).toInt)) - pokeTransaction(dut, stid = 0, transactionId = 0, - demands = aluDemand, capabilities = Some(multiCaps)) - dut.io.prepareReady.expect(true.B) - assert(capture(dut).head.bank == 1) - - val aguDemand = Vector(zero.updated(OooDispatchClass.Agu - 1, 1)) - val storeCaps = Vector(zero.updated(OooDispatchClass.Agu - 1, - mask(StoreAddress).toInt)) - pokeTransaction(dut, stid = 1, transactionId = 1, - demands = aguDemand, capabilities = Some(storeCaps)) - dut.io.prepareReady.expect(true.B) - assert(capture(dut).head.bank == 0) - - val malformedCaps = Vector(zero) - pokeTransaction(dut, stid = 2, transactionId = 0, - demands = aluDemand, capabilities = Some(malformedCaps)) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - } - } - - test("elaborates dispatch at instruction widths 2 4 and 6") { - Seq(2, 4, 6).foreach { width => - val p = OooParams( - instructionDecodeWidth = width, - iqBankCount = 2, - iqEntriesPerBank = 4, - pMapQDepthPerStid = 4) - circt.stage.ChiselStage.emitSystemVerilog(new OooDispatch(p)) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooFastResultAtomicPublishSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooFastResultAtomicPublishSpec.scala new file mode 100644 index 00000000..29f28d8f --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OooFastResultAtomicPublishSpec.scala @@ -0,0 +1,43 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class OooFastResultAtomicPublishSpec extends AnyFunSuite with ChiselSim { + test("either blocked peer prevents every fast-result side effect") { + simulate(new OooFastResultAtomicPublish(SimulationParamProfiles.W2)) { dut => + dut.io.source.bits.poke(0.U.asTypeOf(dut.io.source.bits)) + dut.io.source.bits.value.poke("h1234".U) + dut.io.source.valid.poke(true.B) + + dut.io.iex.ready.poke(true.B) + dut.io.rob.ready.poke(false.B) + dut.io.source.ready.expect(false.B) + dut.io.iex.valid.expect(false.B) + dut.io.rob.valid.expect(true.B) + dut.io.rob.valid.expect(true.B) + dut.io.rob.ready.expect(false.B) + + dut.io.iex.ready.poke(false.B) + dut.io.rob.ready.poke(true.B) + dut.io.source.ready.expect(false.B) + dut.io.iex.valid.expect(true.B) + dut.io.iex.valid.expect(true.B) + dut.io.iex.ready.expect(false.B) + dut.io.rob.valid.expect(false.B) + + dut.io.iex.ready.poke(true.B) + dut.io.rob.ready.poke(true.B) + dut.io.source.ready.expect(true.B) + dut.io.iex.valid.expect(true.B) + dut.io.iex.ready.expect(true.B) + dut.io.rob.valid.expect(true.B) + dut.io.rob.ready.expect(true.B) + dut.io.iex.bits.writeback.value.expect("h1234".U) + dut.io.rob.bits.value.expect("h1234".U) + dut.clock.step() + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OooFrontendCtuRecoveryIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooFrontendCtuRecoveryIntegrationSpec.scala deleted file mode 100644 index 6d206f8c..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooFrontendCtuRecoveryIntegrationSpec.scala +++ /dev/null @@ -1,216 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, Valid} -import linxcore.common.InterfaceParams -import linxcore.frontend.{IfuInnerFlushReason, IfuPruneScope} -import org.scalatest.funsuite.AnyFunSuite - -class OooFrontendCtuRecoveryIntegrationIO( - val ifuP: InterfaceParams, - val oooP: OooParams) - extends Bundle { - val ctuIn = Flipped(Decoupled(new OooD1DecodedPacket(oooP))) - val ctuParentClaim = Decoupled(new OooCtuParentClaim(oooP)) - val ctuExpansionPlan = Flipped(Decoupled(new OooCtuExpansionPlan(oooP))) - val ctuChild = Flipped(Decoupled(new OooCtuCanonicalChild(oooP))) - - val command = Flipped(Decoupled(new OooFrontendRecoveryCommand(ifuP, oooP))) - val o3Request = Decoupled(new OooGlobalRecoveryRequest(oooP)) - val o3Applied = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Completed = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Aborted = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - - val ctuActive = Output(Vec(oooP.stidCount, Bool())) - val ctuOccupied = Output(Vec(oooP.stidCount, Bool())) - val fence = Output(Vec(oooP.stidCount, Bool())) - val stageCancel = Output(Vec(oooP.stidCount, Bool())) -} - -class OooFrontendCtuRecoveryIntegration( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Module { - val io = IO(new OooFrontendCtuRecoveryIntegrationIO(ifuP, oooP)) - val recovery = Module(new OooFrontendRecoveryBridge(ifuP, oooP)) - val ctu = Module(new OooCtuIngressBridge(oooP)) - - ctu.io.in <> io.ctuIn - io.ctuParentClaim <> ctu.io.parentClaim - ctu.io.expansionPlan <> io.ctuExpansionPlan - ctu.io.child <> io.ctuChild - ctu.io.fence := recovery.io.fence - ctu.io.cancel.foreach(_ := false.B) - - recovery.io.in <> io.command - io.o3Request <> recovery.io.o3Request - recovery.io.o3Applied := io.o3Applied - recovery.io.o3Completed := io.o3Completed - recovery.io.o3Aborted := io.o3Aborted - ctu.io.recoveryPrepare <> recovery.io.ctuPrepare - recovery.io.ctuPrepared := ctu.io.recoveryPrepared - recovery.io.ctuRejected := ctu.io.recoveryRejected - ctu.io.recoveryApply := recovery.io.ctuApply - ctu.io.recoveryAbort := recovery.io.ctuAbort - - recovery.io.ifuRedirect.ready := false.B - recovery.io.canonicalFlush.valid := false.B - recovery.io.canonicalFlush.bits := 0.U.asTypeOf(recovery.io.canonicalFlush.bits) - ctu.io.out.ready := false.B - - io.ctuActive := ctu.io.active - io.ctuOccupied := ctu.io.occupied - io.fence := recovery.io.fence - io.stageCancel := recovery.io.stageCancel -} - -class OooFrontendCtuRecoveryIntegrationSpec extends AnyFunSuite with ChiselSim { - private val ifuP = InterfaceParams() - private val oooP = OooParams() - - private def clear(dut: OooFrontendCtuRecoveryIntegration): Unit = { - dut.io.ctuIn.valid.poke(false.B) - dut.io.ctuIn.bits.poke(0.U.asTypeOf(dut.io.ctuIn.bits)) - dut.io.ctuParentClaim.ready.poke(false.B) - dut.io.ctuExpansionPlan.valid.poke(false.B) - dut.io.ctuExpansionPlan.bits.poke( - 0.U.asTypeOf(dut.io.ctuExpansionPlan.bits)) - dut.io.ctuChild.valid.poke(false.B) - dut.io.ctuChild.bits.poke(0.U.asTypeOf(dut.io.ctuChild.bits)) - dut.io.command.valid.poke(false.B) - dut.io.command.bits.poke(0.U.asTypeOf(dut.io.command.bits)) - dut.io.o3Request.ready.poke(false.B) - dut.io.o3Applied.valid.poke(false.B) - dut.io.o3Applied.bits.poke(0.U.asTypeOf(dut.io.o3Applied.bits)) - dut.io.o3Completed.valid.poke(false.B) - dut.io.o3Completed.bits.poke(0.U.asTypeOf(dut.io.o3Completed.bits)) - dut.io.o3Aborted.valid.poke(false.B) - dut.io.o3Aborted.bits.poke(0.U.asTypeOf(dut.io.o3Aborted.bits)) - } - - private def pokeParent( - target: ArchitecturalParentRef, - stid: Int, - instructionId: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.key.valid.poke(true.B) - target.key.peId.poke(2.U) - target.key.stid.poke(stid.U) - target.key.instructionId.poke(instructionId.U) - target.key.epoch.poke(7.U) - target.pc.poke(0x2000.U) - target.lengthBytes.poke(4.U) - target.traceOwner.poke(true.B) - target.prediction.epoch.poke(7.U) - } - - private def pokeLease( - target: OooCtuLeaseKey, - stid: Int, - instructionId: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.valid.poke(true.B) - target.peId.poke(2.U) - target.stid.poke(stid.U) - target.parent.valid.poke(true.B) - target.parent.peId.poke(2.U) - target.parent.stid.poke(stid.U) - target.parent.instructionId.poke(instructionId.U) - target.parent.epoch.poke(7.U) - } - - private def seedActiveCtu( - dut: OooFrontendCtuRecoveryIntegration, - stid: Int, - instructionId: Int): Unit = { - dut.io.ctuIn.bits.poke(0.U.asTypeOf(dut.io.ctuIn.bits)) - dut.io.ctuIn.bits.peId.poke(2.U) - dut.io.ctuIn.bits.stid.poke(stid.U) - dut.io.ctuIn.bits.epoch.poke(7.U) - dut.io.ctuIn.bits.ctuParentMask.poke(1.U) - pokeParent(dut.io.ctuIn.bits.ctuParents(0).parent, stid, instructionId) - dut.io.ctuIn.valid.poke(true.B) - dut.io.ctuIn.ready.expect(true.B) - dut.clock.step() - dut.io.ctuIn.valid.poke(false.B) - - dut.io.ctuParentClaim.valid.expect(true.B) - dut.io.ctuParentClaim.ready.poke(true.B) - dut.clock.step() - dut.io.ctuParentClaim.ready.poke(false.B) - pokeLease(dut.io.ctuExpansionPlan.bits.lease, stid, instructionId) - dut.io.ctuExpansionPlan.bits.childCount.poke(4.U) - dut.io.ctuExpansionPlan.valid.poke(true.B) - dut.io.ctuExpansionPlan.ready.expect(true.B) - dut.clock.step() - dut.io.ctuExpansionPlan.valid.poke(false.B) - dut.io.ctuActive(stid).expect(true.B) - } - - private def pokeRecovery( - target: OooGlobalRecoveryRequest, - stid: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.rename.key.member.group.valid.poke(true.B) - target.rename.key.member.group.peId.poke(2.U) - target.rename.key.member.group.stid.poke(stid.U) - target.rename.key.member.bid.valid.poke(true.B) - target.rename.key.member.bid.value.poke(3.U) - target.rename.key.cause.poke(OooRecoveryCause.CtuCancel) - target.rename.key.epoch.poke(7.U) - target.rename.killTrigger.poke(true.B) - target.triggerMemberCount.poke(1.U) - } - - private def pokeCommand( - dut: OooFrontendCtuRecoveryIntegration, - stid: Int): Unit = { - dut.io.command.bits.poke(0.U.asTypeOf(dut.io.command.bits)) - pokeRecovery(dut.io.command.bits.ooo, stid) - val redirect = dut.io.command.bits.redirect - redirect.valid.poke(true.B) - redirect.peId.poke(2.U) - redirect.threadId.poke(stid.U) - redirect.oldEpoch.poke(7.U) - redirect.restartPc.poke(0x3000.U) - redirect.reason.poke(IfuInnerFlushReason.OooRecovery) - redirect.scope.poke(IfuPruneScope.KillTriggerAndYounger) - } - - test("CTU prepare gates O3 admission and CTU cancellation shares common apply") { - simulate(new OooFrontendCtuRecoveryIntegration(ifuP, oooP)) { dut => - clear(dut) - seedActiveCtu(dut, stid = 1, instructionId = 60) - - pokeCommand(dut, stid = 1) - dut.io.command.valid.poke(true.B) - dut.io.command.ready.expect(true.B) - dut.io.fence(1).expect(true.B) - dut.clock.step() - dut.io.command.valid.poke(false.B) - - dut.io.o3Request.valid.expect(false.B) - var cycles = 0 - while (!dut.io.o3Request.valid.peek().litToBoolean && cycles < 8) { - dut.io.ctuActive(1).expect(true.B) - dut.clock.step() - cycles += 1 - } - assert(cycles < 8, "CTU prepare did not release exact O3 admission") - dut.io.ctuActive(1).expect(true.B) - - dut.io.o3Request.ready.poke(true.B) - dut.clock.step() - dut.io.o3Request.ready.poke(false.B) - pokeRecovery(dut.io.o3Applied.bits, stid = 1) - dut.io.o3Applied.valid.poke(true.B) - dut.io.stageCancel(1).expect(true.B) - dut.io.ctuActive(1).expect(true.B) - dut.clock.step() - dut.io.o3Applied.valid.poke(false.B) - dut.io.ctuActive(1).expect(false.B) - dut.io.ctuOccupied(1).expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooFrontendIfuRecoveryIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooFrontendIfuRecoveryIntegrationSpec.scala deleted file mode 100644 index 8948cbf8..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooFrontendIfuRecoveryIntegrationSpec.scala +++ /dev/null @@ -1,197 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, RegEnable, Valid} -import linxcore.common.InterfaceParams -import linxcore.frontend.{IfuInnerFlush, IfuInnerFlushReason, IfuPruneScope} -import linxcore.top.LinxCoreComposition -import org.scalatest.funsuite.AnyFunSuite - -class OooFrontendIfuRecoveryIntegrationIO( - val ifuP: InterfaceParams, - val oooP: OooParams) - extends Bundle { - val command = Flipped(Decoupled(new OooFrontendRecoveryCommand(ifuP, oooP))) - val o3Request = Decoupled(new OooGlobalRecoveryRequest(oooP)) - val o3Applied = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Completed = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val o3Aborted = Flipped(Valid(new OooGlobalRecoveryRequest(oooP))) - val fence = Output(Vec(oooP.stidCount, Bool())) - val stageCancel = Output(Vec(oooP.stidCount, Bool())) - val canonicalFlush = Valid(new IfuInnerFlush(ifuP)) - val complete = Valid(new OooFrontendRecoveryCompletion(ifuP, oooP)) - val ifuEpochs = Output(Vec(oooP.stidCount, UInt(ifuP.blockEpochWidth.W))) -} - -/** Test-only integration of the canonical R4 bridge with the real IFU - * redirect arbiter and canonical flush broadcast. - */ -class OooFrontendIfuRecoveryIntegration( - val ifuP: InterfaceParams = InterfaceParams(), - val oooP: OooParams = OooParams()) - extends Module { - val io = IO(new OooFrontendIfuRecoveryIntegrationIO(ifuP, oooP)) - val bridge = Module(new OooFrontendRecoveryBridge(ifuP, oooP)) - val ifu = Module(new LinxCoreComposition( - ifuP, - threadCount = oooP.stidCount, - lineBytes = 64, - pageBytes = 4096, - itlbEntries = 4, - l1iSets = 4, - missEntries = 4, - joinEntries = 4, - maxGroupsPerTransaction = 8, - instructionBufferDepth = 16, - lineBridgeEntries = 4, - feedbackEntries = 2)) - - bridge.io.in <> io.command - io.o3Request <> bridge.io.o3Request - bridge.io.o3Applied := io.o3Applied - bridge.io.o3Completed := io.o3Completed - bridge.io.o3Aborted := io.o3Aborted - bridge.io.ctuPrepare.ready := true.B - val ctuPreparedValid = RegNext(bridge.io.ctuPrepare.fire, false.B) - val ctuPreparedRequest = RegEnable( - bridge.io.ctuPrepare.bits, - 0.U.asTypeOf(bridge.io.ctuPrepare.bits), - bridge.io.ctuPrepare.fire) - bridge.io.ctuPrepared.valid := ctuPreparedValid - bridge.io.ctuPrepared.bits := 0.U.asTypeOf(bridge.io.ctuPrepared.bits) - bridge.io.ctuPrepared.bits.request := ctuPreparedRequest - bridge.io.ctuRejected.valid := false.B - bridge.io.ctuRejected.bits := 0.U.asTypeOf(bridge.io.ctuRejected.bits) - ifu.io.recoveryRedirect <> bridge.io.ifuRedirect - bridge.io.canonicalFlush := ifu.io.canonicalFlush - - ifu.io.start.valid := false.B - ifu.io.start.bits := 0.U.asTypeOf(ifu.io.start.bits) - ifu.io.ptwRequest.ready := true.B - ifu.io.ptwRefill.valid := false.B - ifu.io.ptwRefill.bits := 0.U.asTypeOf(ifu.io.ptwRefill.bits) - ifu.io.memoryRequest.ready := false.B - ifu.io.memoryResponse.valid := false.B - ifu.io.memoryResponse.bits := 0.U.asTypeOf(ifu.io.memoryResponse.bits) - ifu.io.fetchFault.ready := true.B - ifu.io.invalidateItlb := false.B - ifu.io.invalidateL1I := false.B - ifu.io.d1ThreadId := 0.U - ifu.io.decoded.ready := false.B - ifu.io.backendValidation.valid := false.B - ifu.io.backendValidation.bits := 0.U.asTypeOf(ifu.io.backendValidation.bits) - - io.fence := bridge.io.fence - io.stageCancel := bridge.io.stageCancel - io.canonicalFlush := ifu.io.canonicalFlush - io.complete := bridge.io.complete - io.ifuEpochs := ifu.io.epochs -} - -class OooFrontendIfuRecoveryIntegrationSpec extends AnyFunSuite with ChiselSim { - private val ifuP = InterfaceParams() - private val oooP = OooParams() - - private def pokeRequest(target: OooGlobalRecoveryRequest): Unit = { - target.poke(0.U.asTypeOf(target)) - val key = target.rename.key - key.member.group.valid.poke(true.B) - key.member.group.peId.poke(2.U) - key.member.group.stid.poke(1.U) - key.member.group.ridSlot.poke(3.U) - key.member.group.ridGeneration.poke(1.U) - key.member.bid.valid.poke(true.B) - key.member.bid.value.poke(9.U) - key.member.brobGeneration.poke(2.U) - key.member.memberIndex.poke(0.U) - key.member.residentGeneration.poke(5.U) - key.cause.poke(OooRecoveryCause.Branch) - key.transactionId.poke(0x23.U) - key.epoch.poke(0.U) - target.rename.killTrigger.poke(true.B) - target.triggerMemberCount.poke(1.U) - } - - private def pokeCommand(dut: OooFrontendIfuRecoveryIntegration): Unit = { - dut.io.command.bits.poke(0.U.asTypeOf(dut.io.command.bits)) - pokeRequest(dut.io.command.bits.ooo) - val redirect = dut.io.command.bits.redirect - redirect.valid.poke(true.B) - redirect.peId.poke(2.U) - redirect.threadId.poke(1.U) - redirect.transactionId.poke(0x44.U) - redirect.fetchSeq.poke(0x55.U) - redirect.oldEpoch.poke(0.U) - redirect.restartPc.poke(0x12340.U) - redirect.checkpointId.poke(7.U) - redirect.reason.poke(IfuInnerFlushReason.BruRecovery) - redirect.scope.poke(IfuPruneScope.KillTriggerAndYounger) - redirect.historyKeyValid.poke(true.B) - redirect.predictionTag.poke(0x66.U) - redirect.fetchPacketUid.poke(0x77.U) - } - - test("real IFU canonical flush closes R4 only after exact O3 completion") { - simulate(new OooFrontendIfuRecoveryIntegration(ifuP, oooP)) { dut => - dut.io.command.valid.poke(false.B) - dut.io.o3Request.ready.poke(false.B) - dut.io.o3Applied.valid.poke(false.B) - dut.io.o3Applied.bits.poke(0.U.asTypeOf(dut.io.o3Applied.bits)) - dut.io.o3Completed.valid.poke(false.B) - dut.io.o3Completed.bits.poke(0.U.asTypeOf(dut.io.o3Completed.bits)) - dut.io.o3Aborted.valid.poke(false.B) - dut.io.o3Aborted.bits.poke(0.U.asTypeOf(dut.io.o3Aborted.bits)) - - pokeCommand(dut) - dut.io.command.valid.poke(true.B) - dut.io.command.ready.expect(true.B) - dut.io.fence(1).expect(true.B) - dut.clock.step() - dut.io.command.valid.poke(false.B) - - var requestCycles = 0 - while (!dut.io.o3Request.valid.peek().litToBoolean && requestCycles < 8) { - dut.clock.step() - requestCycles += 1 - } - assert(requestCycles < 8, "CTU prepare did not release O3 request") - dut.io.o3Request.ready.poke(true.B) - dut.clock.step() - dut.io.o3Request.ready.poke(false.B) - - pokeRequest(dut.io.o3Applied.bits) - dut.io.o3Applied.valid.poke(true.B) - dut.io.stageCancel(1).expect(true.B) - dut.clock.step() - dut.io.o3Applied.valid.poke(false.B) - - var cycles = 0 - while (!dut.io.canonicalFlush.valid.peek().litToBoolean && cycles < 12) { - dut.clock.step() - cycles += 1 - } - assert(cycles < 12, "real IFU did not canonicalize the OOO redirect") - dut.io.canonicalFlush.bits.threadId.expect(1.U) - dut.io.canonicalFlush.bits.restartPc.expect(0x12340.U) - dut.io.canonicalFlush.bits.reason.expect(IfuInnerFlushReason.BruRecovery) - dut.io.canonicalFlush.bits.oldEpoch.expect(0.U) - dut.io.canonicalFlush.bits.newEpoch.expect(1.U) - dut.io.complete.valid.expect(false.B) - dut.clock.step() - dut.io.ifuEpochs(1).expect(1.U) - dut.io.fence(1).expect(true.B) - - pokeRequest(dut.io.o3Completed.bits) - dut.io.o3Completed.valid.poke(true.B) - dut.io.complete.valid.expect(true.B) - dut.io.complete.bits.acceptedEpoch.expect(1.U) - dut.clock.step() - dut.io.o3Completed.valid.poke(false.B) - dut.io.fence(1).expect(false.B) - dut.io.fence(0).expect(false.B) - dut.io.fence(2).expect(false.B) - dut.io.fence(3).expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooFrontendRecoveryBridgeSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooFrontendRecoveryBridgeSpec.scala deleted file mode 100644 index 218c1831..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooFrontendRecoveryBridgeSpec.scala +++ /dev/null @@ -1,282 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.InterfaceParams -import linxcore.frontend.{IfuInnerFlushReason, IfuPruneScope} -import org.scalatest.funsuite.AnyFunSuite - -class OooFrontendRecoveryBridgeSpec extends AnyFunSuite with ChiselSim { - private val ifuP = InterfaceParams() - private val oooP = OooParams() - - private def clear(dut: OooFrontendRecoveryBridge): Unit = { - dut.io.in.valid.poke(false.B) - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - dut.io.o3Request.ready.poke(false.B) - dut.io.o3Applied.valid.poke(false.B) - dut.io.o3Applied.bits.poke(0.U.asTypeOf(dut.io.o3Applied.bits)) - dut.io.o3Completed.valid.poke(false.B) - dut.io.o3Completed.bits.poke(0.U.asTypeOf(dut.io.o3Completed.bits)) - dut.io.o3Aborted.valid.poke(false.B) - dut.io.o3Aborted.bits.poke(0.U.asTypeOf(dut.io.o3Aborted.bits)) - dut.io.ctuPrepare.ready.poke(false.B) - dut.io.ctuPrepared.valid.poke(false.B) - dut.io.ctuPrepared.bits.poke(0.U.asTypeOf(dut.io.ctuPrepared.bits)) - dut.io.ctuRejected.valid.poke(false.B) - dut.io.ctuRejected.bits.poke(0.U.asTypeOf(dut.io.ctuRejected.bits)) - dut.io.ifuRedirect.ready.poke(false.B) - dut.io.canonicalFlush.valid.poke(false.B) - dut.io.canonicalFlush.bits.poke(0.U.asTypeOf(dut.io.canonicalFlush.bits)) - } - - private def pokeO3Request( - target: OooGlobalRecoveryRequest, - stid: Int = 1, - cause: OooRecoveryCause.Type = OooRecoveryCause.Branch, - killTrigger: Boolean = true, - epoch: Int = 7): Unit = { - target.poke(0.U.asTypeOf(target)) - val key = target.rename.key - key.member.group.valid.poke(true.B) - key.member.group.peId.poke(3.U) - key.member.group.stid.poke(stid.U) - key.member.group.ridSlot.poke(5.U) - key.member.group.ridGeneration.poke(2.U) - key.member.bid.valid.poke(true.B) - key.member.bid.value.poke(11.U) - key.member.brobGeneration.poke(1.U) - key.member.memberIndex.poke(2.U) - key.member.residentGeneration.poke(4.U) - key.cause.poke(cause) - key.transactionId.poke(0x31.U) - key.epoch.poke(epoch.U) - target.rename.killTrigger.poke(killTrigger.B) - target.triggerMemberCount.poke(2.U) - } - - private def pokeCommand( - dut: OooFrontendRecoveryBridge, - stid: Int = 1, - cause: OooRecoveryCause.Type = OooRecoveryCause.Branch, - killTrigger: Boolean = true, - epoch: Int = 7, - restartPc: Int = 0x900): Unit = { - dut.io.in.bits.poke(0.U.asTypeOf(dut.io.in.bits)) - pokeO3Request(dut.io.in.bits.ooo, stid, cause, killTrigger, epoch) - val redirect = dut.io.in.bits.redirect - redirect.valid.poke(true.B) - redirect.peId.poke(3.U) - redirect.threadId.poke(stid.U) - redirect.transactionId.poke(0x51.U) - redirect.fetchSeq.poke(0x61.U) - redirect.oldEpoch.poke(epoch.U) - redirect.restartPc.poke(restartPc.U) - redirect.checkpointId.poke(6.U) - redirect.reason.poke( - if (cause == OooRecoveryCause.Branch) IfuInnerFlushReason.BruRecovery - else IfuInnerFlushReason.OooRecovery) - redirect.scope.poke( - if (killTrigger) IfuPruneScope.KillTriggerAndYounger - else IfuPruneScope.PreserveTriggerKillYounger) - redirect.historyKeyValid.poke(true.B) - redirect.predictionTag.poke(0x71.U) - redirect.fetchPacketUid.poke(0x81.U) - } - - private def copyActiveRequestTo( - dut: OooFrontendRecoveryBridge, - target: OooGlobalRecoveryRequest): Unit = { - pokeO3Request(target) - } - - private def pokeCanonical( - dut: OooFrontendRecoveryBridge, - restartPc: Int = 0x900, - newEpoch: Int = 8): Unit = { - dut.io.canonicalFlush.bits.poke(0.U.asTypeOf(dut.io.canonicalFlush.bits)) - val flush = dut.io.canonicalFlush.bits - flush.valid.poke(true.B) - flush.peId.poke(3.U) - flush.threadId.poke(1.U) - flush.transactionId.poke(0x51.U) - flush.fetchSeq.poke(0x61.U) - flush.oldEpoch.poke(7.U) - flush.restartPc.poke(restartPc.U) - flush.checkpointId.poke(6.U) - flush.newEpoch.poke(newEpoch.U) - flush.reason.poke(IfuInnerFlushReason.BruRecovery) - flush.scope.poke(IfuPruneScope.KillTriggerAndYounger) - flush.historyKeyValid.poke(true.B) - flush.predictionTag.poke(0x71.U) - flush.fetchPacketUid.poke(0x81.U) - dut.io.canonicalFlush.valid.poke(true.B) - } - - private def captureAndSendO3(dut: OooFrontendRecoveryBridge): Unit = { - pokeCommand(dut) - dut.io.in.valid.poke(true.B) - dut.io.in.ready.expect(true.B) - dut.io.fence(1).expect(true.B) - dut.io.stageCancel(1).expect(false.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - - dut.io.ctuPrepare.valid.expect(true.B) - dut.io.ctuPrepare.bits.rename.key.member.group.stid.expect(1.U) - dut.clock.step(2) - dut.io.ctuPrepare.valid.expect(true.B) - dut.io.ctuPrepare.ready.poke(true.B) - dut.clock.step() - dut.io.ctuPrepare.ready.poke(false.B) - - dut.io.ctuPrepared.bits.poke(0.U.asTypeOf(dut.io.ctuPrepared.bits)) - pokeO3Request(dut.io.ctuPrepared.bits.request) - dut.io.ctuPrepared.valid.poke(true.B) - dut.clock.step() - dut.io.ctuPrepared.valid.poke(false.B) - - dut.io.o3Request.valid.expect(true.B) - dut.io.o3Request.bits.rename.key.member.group.stid.expect(1.U) - dut.clock.step(2) - dut.io.o3Request.valid.expect(true.B) - dut.io.o3Request.ready.poke(true.B) - dut.clock.step() - dut.io.o3Request.ready.poke(false.B) - } - - test("fences before apply and completes only after exact O3 rebuild plus IFU echo") { - simulate(new OooFrontendRecoveryBridge(ifuP, oooP)) { dut => - clear(dut) - captureAndSendO3(dut) - - dut.io.fence(1).expect(true.B) - dut.io.stageCancel(1).expect(false.B) - dut.io.ifuRedirect.valid.expect(false.B) - - copyActiveRequestTo(dut, dut.io.o3Applied.bits) - dut.io.o3Applied.valid.poke(true.B) - dut.io.stageCancel(1).expect(true.B) - dut.io.ctuApply.expect(true.B) - dut.clock.step() - dut.io.o3Applied.valid.poke(false.B) - - dut.io.ifuRedirect.valid.expect(true.B) - dut.io.ifuRedirect.bits.restartPc.expect(0x900.U) - dut.clock.step(2) - dut.io.ifuRedirect.valid.expect(true.B) - - copyActiveRequestTo(dut, dut.io.o3Completed.bits) - dut.io.o3Completed.valid.poke(true.B) - dut.io.complete.valid.expect(false.B) - dut.clock.step() - dut.io.o3Completed.valid.poke(false.B) - - dut.io.ifuRedirect.ready.poke(true.B) - dut.clock.step() - dut.io.ifuRedirect.ready.poke(false.B) - - pokeCanonical(dut, restartPc = 0xa00, newEpoch = 8) - dut.io.complete.valid.expect(false.B) - dut.clock.step() - dut.io.canonicalFlush.valid.poke(false.B) - dut.io.fence(1).expect(true.B) - - pokeCanonical(dut, restartPc = 0x900, newEpoch = 9) - dut.io.complete.valid.expect(true.B) - dut.io.complete.bits.acceptedEpoch.expect(9.U) - dut.clock.step() - dut.io.canonicalFlush.valid.poke(false.B) - dut.io.busy.expect(false.B) - dut.io.fence(1).expect(false.B) - } - } - - test("accepts canonical IFU acknowledgement before O3 rebuild completion") { - simulate(new OooFrontendRecoveryBridge(ifuP, oooP)) { dut => - clear(dut) - captureAndSendO3(dut) - copyActiveRequestTo(dut, dut.io.o3Applied.bits) - dut.io.o3Applied.valid.poke(true.B) - dut.clock.step() - dut.io.o3Applied.valid.poke(false.B) - - dut.io.ifuRedirect.ready.poke(true.B) - dut.clock.step() - dut.io.ifuRedirect.ready.poke(false.B) - pokeCanonical(dut, newEpoch = 10) - dut.io.complete.valid.expect(false.B) - dut.clock.step() - dut.io.canonicalFlush.valid.poke(false.B) - - copyActiveRequestTo(dut, dut.io.o3Completed.bits) - dut.io.o3Completed.valid.poke(true.B) - dut.io.complete.valid.expect(true.B) - dut.io.complete.bits.acceptedEpoch.expect(10.U) - } - } - - test("O3 abort releases the fence without cancel or IFU mutation") { - simulate(new OooFrontendRecoveryBridge(ifuP, oooP)) { dut => - clear(dut) - captureAndSendO3(dut) - copyActiveRequestTo(dut, dut.io.o3Aborted.bits) - dut.io.o3Aborted.valid.poke(true.B) - dut.io.rejected.valid.expect(true.B) - dut.io.rejected.bits.reason.expect(OooFrontendRecoveryRejectReason.O3Aborted) - dut.io.stageCancel(1).expect(false.B) - dut.io.ctuAbort.expect(true.B) - dut.io.ifuRedirect.valid.expect(false.B) - dut.clock.step() - dut.io.o3Aborted.valid.poke(false.B) - dut.io.busy.expect(false.B) - dut.io.fence(1).expect(false.B) - } - } - - test("CTU prepare rejection releases the fence before O3 admission") { - simulate(new OooFrontendRecoveryBridge(ifuP, oooP)) { dut => - clear(dut) - pokeCommand(dut) - dut.io.in.valid.poke(true.B) - dut.clock.step() - dut.io.in.valid.poke(false.B) - - dut.io.ctuPrepare.valid.expect(true.B) - dut.io.ctuPrepare.ready.poke(true.B) - dut.io.ctuRejected.bits.poke(0.U.asTypeOf(dut.io.ctuRejected.bits)) - pokeO3Request(dut.io.ctuRejected.bits.request) - dut.io.ctuRejected.valid.poke(true.B) - dut.io.rejected.valid.expect(true.B) - dut.io.rejected.bits.reason.expect( - OooFrontendRecoveryRejectReason.CtuRejected) - dut.io.o3Request.valid.expect(false.B) - dut.io.stageCancel(1).expect(false.B) - dut.io.ctuApply.expect(false.B) - dut.io.ctuAbort.expect(false.B) - dut.clock.step() - dut.io.ctuRejected.valid.poke(false.B) - dut.io.ctuPrepare.ready.poke(false.B) - dut.io.busy.expect(false.B) - dut.io.fence(1).expect(false.B) - } - } - - test("rejects a cross-epoch command before fencing or requesting O3") { - simulate(new OooFrontendRecoveryBridge(ifuP, oooP)) { dut => - clear(dut) - pokeCommand(dut) - dut.io.in.bits.redirect.oldEpoch.poke(6.U) - dut.io.in.valid.poke(true.B) - dut.io.in.ready.expect(true.B) - dut.io.fence(1).expect(false.B) - dut.io.rejected.valid.expect(true.B) - dut.io.rejected.bits.reason.expect( - OooFrontendRecoveryRejectReason.MalformedCommand) - dut.clock.step() - dut.io.in.valid.poke(false.B) - dut.io.o3Request.valid.expect(false.B) - dut.io.busy.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooHierarchicalFreeSlotSelectSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooHierarchicalFreeSlotSelectSpec.scala index f7952022..7bac4258 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooHierarchicalFreeSlotSelectSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooHierarchicalFreeSlotSelectSpec.scala @@ -37,4 +37,13 @@ class OooHierarchicalFreeSlotSelectSpec extends AnyFunSuite with ChiselSim { dut.io.selectedIndex.expect(5.U) } } + + test("supports a non-power-of-two canonical dispatch width") { + simulate(new OooHierarchicalFreeSlotSelect(entries = 6, + groupEntries = 1)) { dut => + dut.io.available.poke("b101000".U) + dut.io.selectedValid.expect(true.B) + dut.io.selectedIndex.expect(3.U) + } + } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexAguPipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexAguPipelineSpec.scala index fee21bff..87d543a6 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexAguPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexAguPipelineSpec.scala @@ -5,6 +5,7 @@ import chisel3.simulator.scalatest.ChiselSim import linxcore.common.{DestinationKind, OperandClass} import linxcore.frontend.FrontendOpcodeDecodeTable import org.scalatest.funsuite.AnyFunSuite +import linxcore.top.interface.RecoveryPhase class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { private val p = OooParams( @@ -19,9 +20,9 @@ class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, @@ -127,6 +128,8 @@ class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { payload.recipe.pcReadRequired.poke(rule.pcReadRequired.B) payload.recipe.pSourceCount.poke(rule.pSourceCount.U) payload.recipe.pDestinationCount.poke(rule.pDestinationCount.U) + payload.recipe.tAllocationCount.poke(rule.tAllocationCount.U) + payload.recipe.uAllocationCount.poke(rule.uAllocationCount.U) payload.immediateValid.poke((sources.length < 2).B) payload.immediate.poke(offset.U) payload.memory.valid.poke(true.B) @@ -149,17 +152,25 @@ class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { private def pokeRecovery( dut: OooIexAguPipeline, - newOccupied: Int): Unit = { + firstKilledSlot: Int): Unit = { val plan = dut.io.recoveryApply.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) + plan.phase.poke(RecoveryPhase.Apply) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(1.U) + if (firstKilledSlot < 4) { + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(1.U) + plan.firstKilled.ridSlot.poke(firstKilledSlot.U) + plan.firstKilled.ridGeneration.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(1.U) + plan.lastKilled.ridSlot.poke(3.U) + plan.lastKilled.ridGeneration.poke(1.U) + plan.killedGroupCount.poke((4 - firstKilledSlot).U) + plan.killedMemberCount.poke((4 - firstKilledSlot).U) + } dut.io.recoveryApply.valid.poke(true.B) } @@ -216,6 +227,34 @@ class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { } } + test("accepts a compact load with one exact T destination") { + simulate(new OooIexAguPipeline(p)) { dut => + clear(dut) + pokeExecute(dut, FrontendOpcodeDecodeTable.OP_C_LWI, ridSlot = 1, + sources = Seq(0x1000), mode = OooMemoryAddressMode.BaseOffset, + offset = 8, accessBytes = 4, signExtend = true) + val destination = dut.io.e1.bits.i2.row.schedule.destinations(0) + destination.kind.poke(DestinationKind.T) + destination.atag.poke(31.U) + destination.relativeIndex.poke(2.U) + destination.localTag.poke(3.U) + destination.localSequence.valid.poke(true.B) + destination.localSequence.index.poke(9.U) + destination.localSequence.generation.poke(4.U) + dut.io.request.ready.poke(true.B) + + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.request.valid.expect(true.B) + dut.io.request.bits.address.expect(0x1008.U) + dut.io.request.bits.accessBytes.expect(4.U) + dut.io.request.bits.signExtend.expect(true.B) + dut.io.request.bits.destination.kind.expect(DestinationKind.T) + dut.io.request.bits.destination.localTag.expect(3.U) + } + } + test("kills exact retained requests and rejects malformed load ownership") { simulate(new OooIexAguPipeline(p)) { dut => clear(dut) @@ -247,7 +286,7 @@ class OooIexAguPipelineSpec extends AnyFunSuite with ChiselSim { dut.io.e1.ready.expect(true.B) dut.clock.step() dut.io.e1.valid.poke(false.B) - pokeRecovery(dut, newOccupied = 3) + pokeRecovery(dut, firstKilledSlot = 3) dut.io.request.valid.expect(false.B) dut.io.killedRequest.valid.expect(true.B) dut.clock.step() diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexAluPipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexAluPipelineSpec.scala index a91a1066..d42a2e87 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexAluPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexAluPipelineSpec.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.simulator.scalatest.ChiselSim import linxcore.common.{DestinationKind, OperandClass} import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.top.interface.RecoveryPhase import org.scalatest.funsuite.AnyFunSuite class OooIexAluPipelineSpec extends AnyFunSuite with ChiselSim { @@ -19,9 +20,9 @@ class OooIexAluPipelineSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, @@ -134,17 +135,25 @@ class OooIexAluPipelineSpec extends AnyFunSuite with ChiselSim { private def pokeRecovery( dut: OooIexAluPipeline, - newOccupied: Int): Unit = { + firstKilledSlot: Int): Unit = { val plan = dut.io.recoveryApply.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) + plan.phase.poke(RecoveryPhase.Apply) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(1.U) + if (firstKilledSlot < 4) { + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(1.U) + plan.firstKilled.ridSlot.poke(firstKilledSlot.U) + plan.firstKilled.ridGeneration.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(1.U) + plan.lastKilled.ridSlot.poke(3.U) + plan.lastKilled.ridGeneration.poke(1.U) + plan.killedGroupCount.poke((4 - firstKilledSlot).U) + plan.killedMemberCount.poke((4 - firstKilledSlot).U) + } dut.io.recoveryApply.valid.poke(true.B) } @@ -218,6 +227,115 @@ class OooIexAluPipelineSpec extends AnyFunSuite with ChiselSim { } } + test("accepts the exact c.sext.w shape emitted by the natural frontend") { + simulate(new OooIexAluPipeline(p)) { dut => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + pokeExecute(dut, FrontendOpcodeDecodeTable.OP_C_SEXT_W, + ridSlot = 3, sources = Seq(BigInt("80000001", 16)), + destinationKind = DestinationKind.T) + + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.w1Bypass.valid.expect(true.B) + dut.io.w1Bypass.bits.writebacks(0).data.expect( + BigInt("ffffffff80000001", 16).U) + dut.io.w1Bypass.bits.writebacks(0).destination.kind.expect( + DestinationKind.T) + } + } + + test("computes-base-scalar-shifts") { + final case class ShiftCase( + opcode: Int, + sources: Seq[BigInt], + immediate: Option[BigInt], + expected: BigInt) + + val cases = Seq( + ShiftCase(FrontendOpcodeDecodeTable.OP_SLL, + Seq(0x11, 4), None, 0x110), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRL, + Seq(BigInt("8000000000000000", 16), 63), None, 1), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRA, + Seq(BigInt("8000000000000000", 16), 63), None, + BigInt("ffffffffffffffff", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SLLI, + Seq(3), Some(5), 0x60), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRLI, + Seq(BigInt("8000000000000000", 16)), Some(4), + BigInt("0800000000000000", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRAI, + Seq(BigInt("f000000000000000", 16)), Some(4), + BigInt("ff00000000000000", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SLLW, + Seq(BigInt("40000001", 16), 1), None, + BigInt("ffffffff80000002", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRLW, + Seq(BigInt("80000000", 16), 31), None, 1), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRAW, + Seq(BigInt("80000000", 16), 31), None, + BigInt("ffffffffffffffff", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SLLIW, + Seq(BigInt("40000001", 16)), Some(1), + BigInt("ffffffff80000002", 16)), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRLIW, + Seq(BigInt("80000000", 16)), Some(31), 1), + ShiftCase(FrontendOpcodeDecodeTable.OP_SRAIW, + Seq(BigInt("80000000", 16)), Some(31), + BigInt("ffffffffffffffff", 16))) + + simulate(new OooIexAluPipeline(p)) { dut => + cases.zipWithIndex.foreach { case (testCase, index) => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + pokeExecute(dut, testCase.opcode, ridSlot = index % 4, + sources = testCase.sources, immediate = testCase.immediate) + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.w1Bypass.valid.expect(true.B) + dut.io.w1Bypass.bits.writebacks(0).data.expect(testCase.expected.U) + } + } + } + + test("computes-normalized-load-immediates") { + val cases = Seq( + (FrontendOpcodeDecodeTable.OP_LUI, + BigInt("ffffffff80000000", 16)), + (FrontendOpcodeDecodeTable.OP_HL_LUI, + BigInt("ffffffff80000000", 16)), + (FrontendOpcodeDecodeTable.OP_HL_LIS, + BigInt("ffffffff80000000", 16)), + (FrontendOpcodeDecodeTable.OP_HL_LIU, + BigInt("0000000080000000", 16))) + + simulate(new OooIexAluPipeline(p)) { dut => + cases.zipWithIndex.foreach { case ((opcode, normalizedImmediate), index) => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + pokeExecute(dut, opcode, ridSlot = index, + sources = Seq.empty, immediate = Some(normalizedImmediate)) + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.w1Bypass.valid.expect(true.B) + dut.io.w1Bypass.bits.writebacks(0).data.expect(normalizedImmediate.U) + } + } + } + test("kills exact retained stages and rejects malformed execution") { simulate(new OooIexAluPipeline(p)) { dut => clear(dut) @@ -233,7 +351,7 @@ class OooIexAluPipelineSpec extends AnyFunSuite with ChiselSim { dut.io.w1Bypass.bits.writebacks(0).data.expect(30.U) dut.io.w1Bypass.bits.writebacks(0).destination.kind.expect( DestinationKind.T) - pokeRecovery(dut, newOccupied = 2) + pokeRecovery(dut, firstKilledSlot = 2) dut.io.w1Bypass.valid.expect(false.B) dut.io.killedW1.valid.expect(true.B) dut.io.killedW1.bits.execute.i2.row.member.group.ridSlot.expect(2.U) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexAtomicReadArbiterSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexAtomicReadArbiterSpec.scala index 021656a1..67607690 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexAtomicReadArbiterSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexAtomicReadArbiterSpec.scala @@ -11,6 +11,7 @@ class OooIexAtomicReadArbiterSpec extends AnyFunSuite with ChiselSim { iexPReadPorts = 3, iexTReadPorts = 2, iexUReadPorts = 2) + private val core = OooRecoveryMembership.coreParams(p) private def clear(dut: OooIexAtomicReadArbiter): Unit = { dut.io.attempts.foreach(_.poke(0.U.asTypeOf(dut.io.attempts.head))) @@ -74,7 +75,7 @@ class OooIexAtomicReadArbiterSpec extends AnyFunSuite with ChiselSim { } test("allocates complete read groups by age and cross-STID fairness") { - simulate(new OooIexAtomicReadArbiter(p)) { dut => + simulate(new OooIexAtomicReadArbiter(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -132,6 +133,10 @@ class OooIexAtomicReadArbiterSpec extends AnyFunSuite with ChiselSim { dut.io.tReadRequests(0).valid.expect(true.B) dut.io.uReadRequests(0).valid.expect(true.B) dut.io.pcReadRequests(0).valid.expect(true.B) + dut.io.pcReadRequests(0).bits.valid.expect(true.B) + dut.io.pcReadRequests(0).bits.stid.expect(0.U) + dut.io.pcReadRequests(0).bits.pcBufferIndex.expect(5.U) + dut.io.pcReadRequests(0).bits.allocationEpoch.expect(3.U) dut.io.sourceDataValid(0).expect("b0111".U) dut.io.sourceData(0)(0).expect(11.U) dut.io.sourceData(0)(1).expect(22.U) @@ -178,7 +183,8 @@ class OooIexAtomicReadArbiterSpec extends AnyFunSuite with ChiselSim { iexPReadPorts = 6, iexTReadPorts = 4, iexUReadPorts = 4)) - simulate(new OooIexAtomicReadArbiter(profileParams)) { dut => + val profileCore = OooRecoveryMembership.coreParams(profileParams) + simulate(new OooIexAtomicReadArbiter(profileCore, profileParams)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexBruPipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexBruPipelineSpec.scala index a0fbe0d7..8c10b509 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexBruPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexBruPipelineSpec.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.simulator.scalatest.ChiselSim import linxcore.common.{DestinationKind, OperandClass} import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.top.interface.RecoveryPhase import org.scalatest.funsuite.AnyFunSuite class OooIexBruPipelineSpec extends AnyFunSuite with ChiselSim { @@ -19,9 +20,9 @@ class OooIexBruPipelineSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, @@ -138,17 +139,25 @@ class OooIexBruPipelineSpec extends AnyFunSuite with ChiselSim { private def pokeRecovery( dut: OooIexBruPipeline, - newOccupied: Int): Unit = { + firstKilledSlot: Int): Unit = { val plan = dut.io.recoveryApply.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) + plan.phase.poke(RecoveryPhase.Apply) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(1.U) + if (firstKilledSlot < 4) { + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(1.U) + plan.firstKilled.ridSlot.poke(firstKilledSlot.U) + plan.firstKilled.ridGeneration.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(1.U) + plan.lastKilled.ridSlot.poke(3.U) + plan.lastKilled.ridGeneration.poke(1.U) + plan.killedGroupCount.poke((4 - firstKilledSlot).U) + plan.killedMemberCount.poke((4 - firstKilledSlot).U) + } dut.io.recoveryApply.valid.poke(true.B) } @@ -218,7 +227,7 @@ class OooIexBruPipelineSpec extends AnyFunSuite with ChiselSim { dut.io.e2.bits.bctrl.valid.expect(true.B) dut.io.e2.bits.bctrl.kind.expect(OooIexBctrlUpdateKind.Condition) dut.io.e2.bits.bctrl.condition.expect(true.B) - pokeRecovery(dut, newOccupied = 2) + pokeRecovery(dut, firstKilledSlot = 2) dut.io.e2.valid.expect(false.B) dut.io.killedE2.valid.expect(true.B) dut.clock.step() @@ -245,17 +254,25 @@ class OooIexBruPipelineSpec extends AnyFunSuite with ChiselSim { dut.clock.step() cancel.valid.poke(false.B) - // J needs redirect ownership and B.Z/B.NZ need explicit EXEC/condition - // state, so both remain outside this first fail-closed BRU subset. + // Direct J owns an exact PC-relative redirect. Conditional branches + // remain fail-closed until their architectural condition state is wired. pokeExecute(dut, FrontendOpcodeDecodeTable.OP_J, ridSlot = 3, sources = Seq.empty, immediate = Some(4), pc = Some(0x1000)) + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.e2.valid.expect(true.B) + dut.io.e2.bits.bctrl.valid.expect(true.B) + dut.io.e2.bits.bctrl.targetValid.expect(true.B) + dut.io.e2.bits.bctrl.target.expect(0x1004.U) + dut.io.e2.ready.poke(true.B) + dut.clock.step() + + pokeExecute(dut, FrontendOpcodeDecodeTable.OP_B_Z, ridSlot = 3, + sources = Seq.empty, immediate = Some(4), pc = Some(0x1000)) dut.io.e1.ready.expect(false.B) dut.io.rejected.valid.expect(true.B) dut.io.rejected.bits.supportedOpcode.expect(false.B) - dut.io.e1.bits.ownerClass.poke(OooUopClass.Alu) - dut.io.rejected.bits.classExact.expect(false.B) - dut.clock.step() - dut.io.occupied.expect(false.B) } } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala new file mode 100644 index 00000000..e6e06fbb --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala @@ -0,0 +1,807 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import circt.stage.ChiselStage +import org.scalatest.funsuite.AnyFunSuite + +import linxcore.common.{CoreParams, DestinationKind, ScalarLsuParams} +import linxcore.lsu.LoadAttemptIdentity +import linxcore.top.interface.{RecoveryPhase, RecoveryPlan} + +class OooIexCanonicalLoadOwnershipSpec extends AnyFunSuite with ChiselSim { + + test("uses two canonical load lanes in the default W4 ownership profile") { + val defaultP = OooParams() + val defaultCore = OooIexCanonicalLoadOwnership.defaultCoreParams(defaultP) + + simulate(new OooIexCanonicalLoadOwnership(defaultP, defaultCore)) { dut => + assert(defaultCore.scalarLsu.loadReturnPipeCount == 2) + assert(dut.io.agu.length == 2) + assert(dut.io.speculativeWakeup.length == 2) + } + } + + private final class ExpectedLease( + val lane: Int, + val slot: Int, + val rowGeneration: Int, + val ridSlot: Int, + val lsid: BigInt, + val returnPipe: Int, + val attemptGeneration: Int, + val transactionValue: BigInt, + val transactionGeneration: BigInt, + val destinationPhysTag: Int, + val destinationOldPhysTag: Int) { + val peId = 3 + val stid = 1 + val nativeBid = ridSlot + 4 + val brobGeneration = 9 + val ridGeneration = 5 + val memberIndex = 1 + val residentGeneration = 11 + } + + private def expectMember( + member: RobMemberKey, + expected: ExpectedLease): Unit = { + member.group.valid.expect(true.B) + member.group.peId.expect(expected.peId.U) + member.group.stid.expect(expected.stid.U) + member.group.ridSlot.expect(expected.ridSlot.U) + member.group.ridGeneration.expect(expected.ridGeneration.U) + member.bid.valid.expect(true.B) + member.bid.value.expect(expected.nativeBid.U) + member.brobGeneration.expect(expected.brobGeneration.U) + member.memberIndex.expect(expected.memberIndex.U) + member.residentGeneration.expect(expected.residentGeneration.U) + } + + private def expectAttempt( + attempt: LoadAttemptIdentity, + expected: ExpectedLease): Unit = { + attempt.valid.expect(true.B) + attempt.producer.valid.expect(true.B) + attempt.producer.peId.expect(expected.peId.U) + attempt.producer.stid.expect(expected.stid.U) + attempt.producer.nativeBidValid.expect(true.B) + attempt.producer.nativeBid.expect(expected.nativeBid.U) + attempt.producer.brobGeneration.expect(expected.brobGeneration.U) + attempt.producer.ridSlot.expect(expected.ridSlot.U) + attempt.producer.ridGeneration.expect(expected.ridGeneration.U) + attempt.producer.memberIndex.expect(expected.memberIndex.U) + attempt.producer.residentGeneration.expect(expected.residentGeneration.U) + assert(attempt.generation.peek().litValue == expected.attemptGeneration, + s"attempt generation for literal RID ${expected.ridSlot}") + } + + private def expectLoad( + load: OooIexLoadGeneration, + expected: ExpectedLease): Unit = { + load.valid.expect(true.B) + expectMember(load.producer, expected) + load.transaction.value.expect(expected.transactionValue.U) + load.transaction.generation.expect(expected.transactionGeneration.U) + load.generation.expect(expected.attemptGeneration.U) + } + + private def expectAlloc( + dut: OooIexCanonicalLoadOwnership, + expected: ExpectedLease): Unit = { + dut.io.liqAlloc.bits.returnPipeIndex.expect(expected.returnPipe.U) + dut.io.liqAlloc.bits.loadLsIdFullValid.expect(true.B) + dut.io.liqAlloc.bits.loadLsIdFull.expect(expected.lsid.U) + expectAttempt(dut.io.liqAlloc.bits.attempt, expected) + } + + private def expectResult( + dut: OooIexCanonicalLoadOwnership, + expected: ExpectedLease): Unit = { + dut.io.result.valid.expect(true.B) + dut.io.resultLane.expect(expected.returnPipe.U) + expectMember(dut.io.result.bits.agu.execute.i2.row.schedule.member, + expected) + expectLoad(dut.io.result.bits.load, expected) + dut.io.result.bits.agu.execute.i2.row.payload.memoryOrder.firstLsid + .expect(expected.lsid.U) + dut.io.result.bits.agu.destination.ptag + .expect(expected.destinationPhysTag.U) + dut.io.result.bits.agu.execute.i2.row.payload.previousPDestinations(0).ptag + .expect(expected.destinationOldPhysTag.U) + } + private val p = OooParams( + stidCount = 4, + instructionDecodeWidth = 2, + decodedUopWidth = 2, + renameWidth = 2, + dispatchWidth = 2, + retireGroupWidth = 2, + robGroupsPerStid = 8, + robBankCount = 2, + robRecoveryScanGroupsPerCycle = 2, + robNonFlushScanGroupsPerCycle = 2, + brobEntriesPerStid = 16, + pcBufferEntries = 16, + pcBankCount = 4, + pcRecoveryScanGroupsPerCycle = 2, + pcWritePorts = 3, + iqBankCount = 2, + iqEntriesPerBank = 4, + iqFreeSelectLeafEntries = 2, + tuRetireSourceDepthPerStid = 16, + lsidWidth = 40) + + private val core = CoreParams( + robEntries = 8, + lsidWidth = 40, + scalarLsu = ScalarLsuParams( + stqEntries = 4, + liqEntries = 4, + loadReturnPipeCount = 3, + stidCount = 4)) + + private def defaults(dut: OooIexCanonicalLoadOwnership): Unit = { + dut.io.agu.foreach { lane => + lane.valid.poke(false.B) + lane.bits.poke(0.U.asTypeOf(lane.bits)) + } + dut.io.liqAlloc.ready.poke(false.B) + dut.io.liqAllocLoadId.poke(0.U.asTypeOf(dut.io.liqAllocLoadId)) + dut.io.completion.valid.poke(false.B) + dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) + dut.io.result.ready.poke(false.B) + dut.io.rebind.valid.poke(false.B) + dut.io.rebind.bits.poke(0.U.asTypeOf(dut.io.rebind.bits)) + dut.io.liqRebind.ready.poke(false.B) + dut.io.attemptLaunch.valid.poke(false.B) + dut.io.attemptLaunch.bits.poke( + 0.U.asTypeOf(dut.io.attemptLaunch.bits)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def pokeRecoveryPlan( + plan: RecoveryPlan, + phase: RecoveryPhase.Type, + transactionId: Int, + stid: Int, + firstRid: Int, + lastRid: Int): Unit = { + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(transactionId.U) + plan.phase.poke(phase) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(stid.U) + plan.trigger.ridSlot.poke(firstRid.U) + plan.trigger.ridGeneration.poke(5.U) + plan.trigger.memberIndex.poke(1.U) + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(stid.U) + plan.firstKilled.ridSlot.poke(firstRid.U) + plan.firstKilled.ridGeneration.poke(5.U) + plan.firstKilled.memberIndex.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(stid.U) + plan.lastKilled.ridSlot.poke(lastRid.U) + plan.lastKilled.ridGeneration.poke(5.U) + plan.lastKilled.memberIndex.poke(1.U) + plan.killedGroupCount.poke((lastRid - firstRid + 1).U) + plan.killedMemberCount.poke((lastRid - firstRid + 1).U) + } + + private def pokeMember( + member: RobMemberKey, + ridSlot: Int, + stid: Int = 1): Unit = { + member.poke(0.U.asTypeOf(member)) + member.group.valid.poke(true.B) + member.group.peId.poke(3.U) + member.group.stid.poke(stid.U) + member.group.ridSlot.poke(ridSlot.U) + member.group.ridGeneration.poke(5.U) + member.bid.valid.poke(true.B) + member.bid.value.poke((ridSlot + 4).U) + member.brobGeneration.poke(9.U) + member.memberIndex.poke(1.U) + member.residentGeneration.poke(11.U) + } + + private def pokeRequest( + dut: OooIexCanonicalLoadOwnership, + lane: Int, + ridSlot: Int, + lsid: BigInt, + transactionValue: BigInt = 0, + transactionGeneration: BigInt = 0, + attemptGeneration: BigInt = 1, + stid: Int = 1): Unit = { + val input = dut.io.agu(lane) + input.bits.poke(0.U.asTypeOf(input.bits)) + input.valid.poke(true.B) + input.bits.pcValid.poke(true.B) + input.bits.pc.poke((0x4000 + ridSlot * 4).U) + input.bits.address.poke((0x8000 + ridSlot * 8).U) + input.bits.accessBytes.poke(8.U) + input.bits.signExtend.poke(true.B) + input.bits.execute.ownerClass.poke(OooUopClass.Agu) + + val row = input.bits.execute.i2.row + row.schedule.valid.poke(true.B) + row.schedule.peId.poke(3.U) + row.schedule.stid.poke(stid.U) + row.schedule.epoch.poke(7.U) + row.schedule.memoryTransactionValid.poke(true.B) + row.schedule.memoryTransaction.value.poke(transactionValue.U) + row.schedule.memoryTransaction.generation.poke(transactionGeneration.U) + row.schedule.initialLoadAttemptValid.poke(true.B) + row.schedule.initialLoadAttemptGeneration.poke(attemptGeneration.U) + pokeMember(row.schedule.member, ridSlot, stid) + row.schedule.reservation.valid.poke(true.B) + row.schedule.reservation.uopClass.poke(OooUopClass.Agu) + row.payload.opcode.poke(101.U) + row.payload.recipe.valid.poke(true.B) + row.payload.recipe.opcode.poke(101.U) + row.payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + row.payload.recipe.recipeKind.poke(OooOpcodeRecipeKind.ScalarLoad.U) + row.payload.recipe.dispatchClass.poke(OooDispatchClass.Agu.U) + row.payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) + row.payload.recipe.memoryRequestCount.poke(1.U) + row.payload.memory.valid.poke(true.B) + row.payload.memory.isLoad.poke(true.B) + row.payload.memoryOrder.valid.poke(true.B) + row.payload.memoryOrder.memoryValid.poke(true.B) + row.payload.memoryOrder.isLoad.poke(true.B) + row.payload.memoryOrder.requestCount.poke(1.U) + row.payload.memoryOrder.firstLsid.poke(lsid.U) + row.payload.memoryOrder.firstTypeId.poke(4.U) + row.payload.memoryOrder.before.lsid.poke(lsid.U) + row.payload.memoryOrder.before.loadId.poke(4.U) + row.payload.memoryOrder.after.lsid.poke((lsid + 1).U) + row.payload.memoryOrder.after.loadId.poke(5.U) + row.schedule.destinations(0).valid.poke(true.B) + row.schedule.destinations(0).kind.poke(DestinationKind.Gpr) + row.schedule.destinations(0).atag.poke(6.U) + row.schedule.destinations(0).ptag.poke((31 + lane).U) + row.schedule.destinations(0).ptagGeneration.poke(4.U) + row.payload.previousPDestinations(0).valid.poke(true.B) + row.payload.previousPDestinations(0).ptag.poke((21 + lane).U) + input.bits.destination.poke(row.schedule.destinations(0).peek()) + } + + private def accept( + dut: OooIexCanonicalLoadOwnership, + lane: Int, + slot: Int, + wrap: Boolean): BigInt = { + dut.io.liqAllocLoadId.valid.poke(true.B) + dut.io.liqAllocLoadId.value.poke(slot.U) + dut.io.liqAllocLoadId.wrap.poke(wrap.B) + dut.io.liqAlloc.ready.poke(true.B) + dut.io.liqAlloc.valid.expect(true.B) + dut.io.agu(lane).ready.expect(true.B) + dut.io.allocAccepted.expect(true.B) + val generation = dut.io.liqAlloc.bits.attempt.generation.peek().litValue + dut.clock.step() + dut.io.agu(lane).valid.poke(false.B) + dut.io.liqAlloc.ready.poke(false.B) + generation + } + + private def pokeCompletion( + dut: OooIexCanonicalLoadOwnership, + slot: Int, + wrap: Boolean, + ridSlot: Int, + attemptGeneration: BigInt, + fault: Boolean = false, + destinationPhysTag: Int = 33, + destinationOldPhysTag: Int = 23, + stid: Int = 1): Unit = { + val completion = dut.io.completion.bits + completion.poke(0.U.asTypeOf(completion)) + completion.peId.poke(3.U) + completion.stid.poke(stid.U) + completion.tid.poke(stid.U) + completion.payload.valid.poke(true.B) + completion.payload.loadId.valid.poke(true.B) + completion.payload.loadId.slot.poke(slot.U) + completion.payload.loadId.generation.poke((if (wrap) 1 else 0).U) + completion.payload.attempt.valid.poke(true.B) + completion.payload.attempt.producer.valid.poke(true.B) + completion.payload.attempt.producer.peId.poke(3.U) + completion.payload.attempt.producer.stid.poke(stid.U) + completion.payload.attempt.producer.nativeBidValid.poke(true.B) + completion.payload.attempt.producer.nativeBid.poke((ridSlot + 4).U) + completion.payload.attempt.producer.brobGeneration.poke(9.U) + completion.payload.attempt.producer.ridSlot.poke(ridSlot.U) + completion.payload.attempt.producer.ridGeneration.poke(5.U) + completion.payload.attempt.producer.memberIndex.poke(1.U) + completion.payload.attempt.producer.residentGeneration.poke(11.U) + completion.payload.attempt.generation.poke(attemptGeneration.U) + completion.payload.dst.valid.poke(true.B) + completion.payload.dst.kind.poke(DestinationKind.Gpr) + completion.payload.dst.archTag.poke(6.U) + completion.payload.dst.physTag.poke(destinationPhysTag.U) + completion.payload.dst.oldPhysTag.poke(destinationOldPhysTag.U) + completion.payload.data.poke( + (if (fault) BigInt(0) else BigInt("1122334455667788", 16)).U) + completion.payload.faultValid.poke(fault.B) + completion.payload.faultCause.poke((if (fault) 0x55 else 0).U) + dut.io.completion.valid.poke(true.B) + } + + private def pokeLoadAttempt( + load: OooIexLoadGeneration, + attempt: linxcore.lsu.LoadAttemptIdentity, + ridSlot: Int, + generation: BigInt, + transactionValue: BigInt = 0, + transactionGeneration: BigInt = 0): Unit = { + load.poke(0.U.asTypeOf(load)) + load.valid.poke(true.B) + pokeMember(load.producer, ridSlot) + load.transaction.value.poke(transactionValue.U) + load.transaction.generation.poke(transactionGeneration.U) + load.generation.poke(generation.U) + attempt.poke(0.U.asTypeOf(attempt)) + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(3.U) + attempt.producer.stid.poke(1.U) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke((ridSlot + 4).U) + attempt.producer.brobGeneration.poke(9.U) + attempt.producer.ridSlot.poke(ridSlot.U) + attempt.producer.ridGeneration.poke(5.U) + attempt.producer.memberIndex.poke(1.U) + attempt.producer.residentGeneration.poke(11.U) + attempt.generation.poke(generation.U) + } + + private def pokeAttempt( + attempt: linxcore.lsu.LoadAttemptIdentity, + ridSlot: Int, + generation: BigInt): Unit = { + attempt.poke(0.U.asTypeOf(attempt)) + attempt.valid.poke(true.B) + attempt.producer.valid.poke(true.B) + attempt.producer.peId.poke(3.U) + attempt.producer.stid.poke(1.U) + attempt.producer.nativeBidValid.poke(true.B) + attempt.producer.nativeBid.poke((ridSlot + 4).U) + attempt.producer.brobGeneration.poke(9.U) + attempt.producer.ridSlot.poke(ridSlot.U) + attempt.producer.ridGeneration.poke(5.U) + attempt.producer.memberIndex.poke(1.U) + attempt.producer.residentGeneration.poke(11.U) + attempt.generation.poke(generation.U) + } + + private def pokeLaunch( + dut: OooIexCanonicalLoadOwnership, + slot: Int, + wrap: Boolean, + ridSlot: Int, + generation: BigInt): Unit = { + dut.io.attemptLaunch.bits.poke( + 0.U.asTypeOf(dut.io.attemptLaunch.bits)) + dut.io.attemptLaunch.bits.loadId.valid.poke(true.B) + dut.io.attemptLaunch.bits.loadId.slot.poke(slot.U) + dut.io.attemptLaunch.bits.loadId.generation + .poke((if (wrap) 1 else 0).U) + pokeAttempt(dut.io.attemptLaunch.bits.attempt, ridSlot, generation) + dut.io.attemptLaunch.valid.poke(true.B) + } + + test("allocates canonical LIQ and terminal metadata on one atomic fire") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = BigInt("100000001", 16)) + dut.io.liqAllocLoadId.valid.poke(true.B) + dut.io.liqAllocLoadId.value.poke(2.U) + // Valid is allowed to advertise the transaction before the canonical + // LIQ is ready; neither producer nor metadata may consume it early. + dut.io.liqAlloc.valid.expect(true.B) + dut.io.agu(2).ready.expect(false.B) + dut.io.allocAccepted.expect(false.B) + + val generation = accept(dut, lane = 2, slot = 2, wrap = true) + dut.io.metadataOccupied.expect(1.U) + dut.io.liqAlloc.bits.returnPipeIndex.expect(2.U) + + // Reusing the same canonical row lease is held off by the still-live + // terminal sidecar even when the LIQ advertises allocation readiness. + pokeRequest(dut, lane = 0, ridSlot = 4, lsid = 9, + transactionValue = 1, attemptGeneration = 2) + dut.io.liqAlloc.ready.poke(true.B) + dut.io.liqAlloc.valid.expect(false.B) + dut.io.agu(0).ready.expect(false.B) + dut.io.metadataOccupied.expect(1.U) + assert(generation == 1) + } + } + + test("retains exact hit or fault completion until one terminal fire") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 7) + val generation = accept(dut, lane = 2, slot = 2, wrap = true) + pokeCompletion(dut, slot = 2, wrap = true, ridSlot = 3, + attemptGeneration = generation) + dut.io.result.valid.expect(true.B) + dut.io.completion.ready.expect(false.B) + dut.io.result.bits.data.expect(BigInt("1122334455667788", 16).U) + dut.io.loadBypass(2).valid.expect(true.B) + dut.io.loadBypass(2).bits.data + .expect(BigInt("1122334455667788", 16).U) + dut.io.loadCancel.foreach(_.valid.expect(false.B)) + dut.clock.step(2) + dut.io.metadataOccupied.expect(1.U) + + dut.io.result.ready.poke(true.B) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.result.ready.poke(false.B) + dut.io.metadataEmpty.expect(true.B) + + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 8, + transactionValue = 1, attemptGeneration = 2) + val faultGeneration = accept(dut, lane = 2, slot = 2, wrap = false) + pokeCompletion(dut, slot = 2, wrap = false, ridSlot = 3, + attemptGeneration = faultGeneration, fault = true) + dut.io.result.valid.expect(true.B) + dut.io.result.bits.faultValid.expect(true.B) + dut.io.result.bits.data.expect(0.U) + dut.io.loadBypass.foreach(_.valid.expect(false.B)) + // Fault cancellation is a one-shot policy event. It must not depend on + // the terminal sink accepting W2, otherwise terminal ready can close a + // combinational loop through the ALU cancel consumers. + dut.io.loadCancel(2).valid.expect(true.B) + dut.io.loadCancel(2).bits.load.generation.expect(faultGeneration.U) + dut.clock.step() + dut.io.result.valid.expect(true.B) + dut.io.loadCancel.foreach(_.valid.expect(false.B)) + + dut.io.result.ready.poke(true.B) + dut.io.completion.ready.expect(true.B) + dut.io.loadCancel.foreach(_.valid.expect(false.B)) + dut.clock.step() + dut.io.metadataEmpty.expect(true.B) + } + } + + test("qualifies speculative wakeup by exact LIQ launch attempt") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 7) + val generation = accept(dut, lane = 2, slot = 2, wrap = true) + + pokeLaunch(dut, slot = 2, wrap = true, ridSlot = 3, + generation = generation) + dut.io.attemptLaunchAccepted.expect(true.B) + dut.io.attemptLaunchRejected.valid.expect(false.B) + dut.io.speculativeWakeup(0).valid.expect(false.B) + dut.io.speculativeWakeup(1).valid.expect(false.B) + dut.io.speculativeWakeup(2).valid.expect(true.B) + dut.io.speculativeWakeup(2).bits.ptag.expect(33.U) + dut.io.speculativeWakeup(2).bits.load.generation.expect(generation.U) + dut.clock.step() + + pokeLaunch(dut, slot = 2, wrap = true, ridSlot = 3, + generation = generation + 1) + dut.io.attemptLaunchAccepted.expect(false.B) + dut.io.attemptLaunchRejected.valid.expect(true.B) + dut.io.attemptLaunchRejected.bits.attemptExact.expect(false.B) + dut.io.speculativeWakeup.foreach(_.valid.expect(false.B)) + } + } + + test("rebinds canonical LIQ and OOO attempt metadata on one fire") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 7) + val current = accept(dut, lane = 2, slot = 2, wrap = true) + + val rebind = dut.io.rebind.bits + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(2.U) + rebind.loadId.generation.poke(1.U) + pokeLoadAttempt(rebind.currentLoad, rebind.currentAttempt, + ridSlot = 3, generation = current) + pokeLoadAttempt(rebind.nextLoad, rebind.nextAttempt, + ridSlot = 3, generation = current + 1) + dut.io.rebind.valid.poke(true.B) + + dut.io.liqRebind.valid.expect(true.B) + dut.io.rebind.ready.expect(false.B) + dut.io.rebindAccepted.expect(false.B) + dut.io.liqRebind.bits.loadId.value.expect(2.U) + dut.io.liqRebind.bits.loadId.wrap.expect(true.B) + dut.clock.step(2) + dut.io.metadataOccupied.expect(1.U) + + dut.io.liqRebind.ready.poke(true.B) + dut.io.rebind.ready.expect(true.B) + dut.io.rebindAccepted.expect(true.B) + dut.io.loadCancel(2).valid.expect(true.B) + dut.io.loadCancel(2).bits.load.generation.expect(current.U) + dut.clock.step() + dut.io.rebind.valid.poke(false.B) + dut.io.liqRebind.ready.poke(false.B) + + pokeCompletion(dut, slot = 2, wrap = true, ridSlot = 3, + attemptGeneration = current) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(false.B) + dut.io.completionRejected.valid.expect(true.B) + pokeCompletion(dut, slot = 2, wrap = true, ridSlot = 3, + attemptGeneration = current + 1) + dut.io.result.valid.expect(true.B) + + dut.io.completion.valid.poke(false.B) + dut.io.result.ready.poke(false.B) + pokeLaunch(dut, slot = 2, wrap = true, ridSlot = 3, + generation = current + 1) + dut.io.attemptLaunchAccepted.expect(true.B) + dut.io.speculativeWakeup(2).valid.expect(true.B) + dut.io.speculativeWakeup(2).bits.load.generation + .expect((current + 1).U) + } + } + + test("fences allocation and terminal publication during common recovery") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 7) + val generation = accept(dut, lane = 2, slot = 2, wrap = true) + pokeCompletion(dut, slot = 2, wrap = true, ridSlot = 3, + attemptGeneration = generation) + dut.io.result.ready.poke(false.B) + + pokeRecoveryPlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare, + transactionId = 31, stid = 1, firstRid = 3, lastRid = 3) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepared.valid.expect(false.B) + dut.io.metadataOccupied.expect(1.U) + + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.io.result.valid.expect(false.B) + dut.io.completion.ready.expect(false.B) + dut.clock.step() + + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.bits.transactionId.expect(31.U) + dut.io.recovery.prepared.bits.phase.expect(RecoveryPhase.Prepare) + dut.io.recovery.prepared.bits.firstKilled.ridSlot.expect(3.U) + + pokeRequest(dut, lane = 0, ridSlot = 4, lsid = 8, + transactionValue = 1, attemptGeneration = 2, stid = 2) + dut.io.liqAllocLoadId.valid.poke(true.B) + dut.io.liqAllocLoadId.value.poke(3.U) + dut.io.liqAllocLoadId.wrap.poke(false.B) + dut.io.liqAlloc.ready.poke(true.B) + dut.io.liqAlloc.valid.expect(true.B) + dut.io.agu(0).ready.expect(true.B) + val peerGeneration = + dut.io.liqAlloc.bits.attempt.generation.peek().litValue + dut.clock.step() + dut.io.agu(0).valid.poke(false.B) + dut.io.liqAlloc.ready.poke(false.B) + dut.io.metadataOccupied.expect(2.U) + + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + dut.io.recovery.prepared.ready.poke(false.B) + + pokeRecoveryPlan(dut.io.recovery.apply.bits, RecoveryPhase.Apply, + transactionId = 31, stid = 1, firstRid = 3, lastRid = 3) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.completion.valid.poke(false.B) + dut.io.metadataOccupied.expect(1.U) + + pokeCompletion(dut, slot = 3, wrap = false, ridSlot = 4, + attemptGeneration = peerGeneration, destinationPhysTag = 31, + destinationOldPhysTag = 21, stid = 2) + dut.io.result.ready.poke(true.B) + dut.io.result.valid.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.metadataEmpty.expect(true.B) + } + } + + test("serializes fault and replay cancels that target one physical lane") { + simulate(new OooIexCanonicalLoadOwnership(p, core)) { dut => + defaults(dut) + pokeRequest(dut, lane = 2, ridSlot = 2, lsid = 6) + val faultGeneration = accept(dut, lane = 2, slot = 1, wrap = false) + pokeRequest(dut, lane = 2, ridSlot = 3, lsid = 7, + transactionValue = 1, attemptGeneration = 2) + val replayGeneration = accept(dut, lane = 2, slot = 2, wrap = false) + + pokeCompletion(dut, slot = 1, wrap = false, ridSlot = 2, + attemptGeneration = faultGeneration, fault = true) + dut.io.result.ready.poke(true.B) + + val rebind = dut.io.rebind.bits + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(2.U) + rebind.loadId.generation.poke(0.U) + pokeLoadAttempt(rebind.currentLoad, rebind.currentAttempt, + ridSlot = 3, generation = replayGeneration, transactionValue = 1) + pokeLoadAttempt(rebind.nextLoad, rebind.nextAttempt, + ridSlot = 3, generation = replayGeneration + 1, + transactionValue = 1) + dut.io.rebind.valid.poke(true.B) + dut.io.liqRebind.ready.poke(true.B) + + dut.io.rebind.ready.expect(false.B) + dut.io.liqRebind.valid.expect(false.B) + dut.io.loadCancel(2).valid.expect(true.B) + dut.io.loadCancel(2).bits.load.generation.expect(faultGeneration.U) + dut.clock.step() + + dut.io.completion.valid.poke(false.B) + dut.io.result.ready.poke(false.B) + dut.io.rebind.ready.expect(true.B) + dut.io.loadCancel(2).valid.expect(true.B) + dut.io.loadCancel(2).bits.load.generation.expect(replayGeneration.U) + } + } + + test("keeps two canonical AGU leases disjoint through retry rebind return and recovery") { + val twoPipeCore = core.copy( + scalarLsu = core.scalarLsu.copy(loadReturnPipeCount = 2)) + simulate(new OooIexCanonicalLoadOwnership( + p, twoPipeCore, laneCount = 2)) { dut => + defaults(dut) + + pokeRequest(dut, lane = 0, ridSlot = 2, + lsid = BigInt("100000002", 16), transactionValue = 1, + attemptGeneration = 2) + pokeRequest(dut, lane = 1, ridSlot = 3, + lsid = BigInt("200000003", 16), transactionValue = 0, + attemptGeneration = 1) + dut.io.agu(0).valid.poke(false.B) + val lane1 = new ExpectedLease(lane = 1, slot = 0, rowGeneration = 0, + ridSlot = 3, lsid = BigInt("200000003", 16), returnPipe = 1, + attemptGeneration = 1, transactionValue = 0, + transactionGeneration = 0, destinationPhysTag = 32, + destinationOldPhysTag = 22) + val lane0Initial = new ExpectedLease(lane = 0, slot = 1, + rowGeneration = 0, ridSlot = 2, lsid = BigInt("100000002", 16), + returnPipe = 0, attemptGeneration = 2, transactionValue = 1, + transactionGeneration = 0, destinationPhysTag = 31, + destinationOldPhysTag = 21) + val lane0Rebound = new ExpectedLease(lane = 0, slot = 1, + rowGeneration = 0, ridSlot = 2, lsid = BigInt("100000002", 16), + returnPipe = 0, attemptGeneration = 3, transactionValue = 1, + transactionGeneration = 0, destinationPhysTag = 31, + destinationOldPhysTag = 21) + dut.io.liqAllocLoadId.valid.poke(true.B) + dut.io.liqAllocLoadId.value.poke(0.U) + dut.io.liqAlloc.ready.poke(true.B) + dut.io.agu(1).ready.expect(true.B) + expectAlloc(dut, lane1) + dut.clock.step() + dut.io.agu(1).valid.poke(false.B) + + dut.io.liqAllocLoadId.value.poke(1.U) + dut.io.agu(0).valid.poke(true.B) + dut.io.agu(0).ready.expect(true.B) + expectAlloc(dut, lane0Initial) + dut.clock.step() + dut.io.agu(0).valid.poke(false.B) + dut.io.liqAlloc.ready.poke(false.B) + dut.io.metadataOccupied.expect(2.U) + + val rebind = dut.io.rebind.bits + rebind.loadId.valid.poke(true.B) + rebind.loadId.slot.poke(1.U) + rebind.loadId.generation.poke(0.U) + pokeLoadAttempt(rebind.currentLoad, rebind.currentAttempt, + ridSlot = 2, generation = lane0Initial.attemptGeneration, + transactionValue = lane0Initial.transactionValue, + transactionGeneration = lane0Initial.transactionGeneration) + pokeLoadAttempt(rebind.nextLoad, rebind.nextAttempt, + ridSlot = 2, generation = lane0Rebound.attemptGeneration, + transactionValue = lane0Rebound.transactionValue, + transactionGeneration = lane0Rebound.transactionGeneration) + dut.io.rebind.valid.poke(true.B) + dut.io.liqRebind.ready.poke(false.B) + for (_ <- 0 until 2) { + dut.io.rebind.ready.expect(false.B) + dut.io.rebindAccepted.expect(false.B) + dut.io.loadCancel.foreach(_.valid.expect(false.B)) + dut.io.metadataOccupied.expect(2.U) + dut.io.liqRebind.valid.expect(true.B) + dut.io.liqRebind.bits.loadId.valid.expect(true.B) + dut.io.liqRebind.bits.loadId.value.expect(lane0Initial.slot.U) + dut.io.liqRebind.bits.loadId.wrap.expect(false.B) + expectAttempt(dut.io.liqRebind.bits.current, lane0Initial) + expectAttempt(dut.io.liqRebind.bits.next, lane0Rebound) + dut.clock.step() + } + dut.io.liqRebind.ready.poke(true.B) + dut.io.rebind.ready.expect(true.B) + dut.io.rebindAccepted.expect(true.B) + dut.io.loadCancel(0).valid.expect(true.B) + dut.io.loadCancel(0).bits.stid.expect(lane0Initial.stid.U) + expectLoad(dut.io.loadCancel(0).bits.load, lane0Initial) + dut.io.loadCancel(1).valid.expect(false.B) + dut.clock.step() + dut.io.rebind.valid.poke(false.B) + dut.io.liqRebind.ready.poke(false.B) + + pokeCompletion(dut, slot = 1, wrap = false, ridSlot = 2, + attemptGeneration = lane0Initial.attemptGeneration, + destinationPhysTag = 31, + destinationOldPhysTag = 21) + dut.io.completionRejected.valid.expect(true.B) + expectMember(dut.io.completionRejected.bits.member, lane0Rebound) + dut.io.result.valid.expect(false.B) + dut.io.completion.valid.poke(false.B) + + pokeCompletion(dut, slot = 0, wrap = false, ridSlot = 3, + attemptGeneration = lane1.attemptGeneration, destinationPhysTag = 32, + destinationOldPhysTag = 22) + expectResult(dut, lane1) + dut.io.result.ready.poke(false.B) + for (_ <- 0 until 3) { + expectResult(dut, lane1) + dut.io.completion.ready.expect(false.B) + dut.clock.step() + } + dut.io.result.ready.poke(true.B) + expectResult(dut, lane1) + dut.io.completion.ready.expect(true.B) + dut.clock.step() + dut.io.completion.valid.poke(false.B) + dut.io.result.ready.poke(false.B) + dut.io.metadataOccupied.expect(1.U) + + pokeRecoveryPlan(dut.io.recovery.prepare.bits, RecoveryPhase.Prepare, + transactionId = 37, stid = 1, firstRid = 2, lastRid = 2) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepared.valid.expect(true.B) + dut.io.recovery.prepared.ready.poke(true.B) + dut.clock.step() + dut.io.recovery.prepared.ready.poke(false.B) + pokeRecoveryPlan(dut.io.recovery.apply.bits, RecoveryPhase.Apply, + transactionId = 37, stid = 1, firstRid = 2, lastRid = 2) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.metadataEmpty.expect(true.B) + } + } + + test("emits the canonical ownership graph without a duplicate load tracker") { + val systemVerilog = ChiselStage.emitSystemVerilog( + new OooIexCanonicalLoadOwnership(p, core)) + + assert(systemVerilog.contains("module OooIexCanonicalLoadOwnership")) + assert(systemVerilog.contains("LoadIexIssuePipeline issuePipeline")) + assert(systemVerilog.contains("OooIexLoadTerminalMetadata metadata")) + assert(!systemVerilog.contains("OooIexLoadUnit")) + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexE1TransferSlotSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexE1TransferSlotSpec.scala index a7755382..78c0cceb 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexE1TransferSlotSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexE1TransferSlotSpec.scala @@ -3,6 +3,7 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim import linxcore.common.OperandClass +import linxcore.top.interface.RecoveryPhase import org.scalatest.funsuite.AnyFunSuite class OooIexE1TransferSlotSpec extends AnyFunSuite with ChiselSim { @@ -118,17 +119,25 @@ class OooIexE1TransferSlotSpec extends AnyFunSuite with ChiselSim { private def pokeRecovery( dut: OooIexE1TransferSlot, - newOccupied: Int): Unit = { + firstKilledSlot: Int): Unit = { val plan = dut.io.recoveryApply.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) + plan.phase.poke(RecoveryPhase.Apply) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(1.U) + if (firstKilledSlot < 4) { + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(1.U) + plan.firstKilled.ridSlot.poke(firstKilledSlot.U) + plan.firstKilled.ridGeneration.poke(1.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(1.U) + plan.lastKilled.ridSlot.poke(3.U) + plan.lastKilled.ridGeneration.poke(1.U) + plan.killedGroupCount.poke((4 - firstKilledSlot).U) + plan.killedMemberCount.poke((4 - firstKilledSlot).U) + } dut.io.recoveryApply.valid.poke(true.B) } @@ -184,10 +193,10 @@ class OooIexE1TransferSlotSpec extends AnyFunSuite with ChiselSim { dut.io.e1.bits.i2.sourceData(0).expect("h8877665544332211".U) // Exact ROB recovery, not an unrelated surviving prefix, owns the kill. - pokeRecovery(dut, newOccupied = 4) + pokeRecovery(dut, firstKilledSlot = 4) dut.io.e1.valid.expect(true.B) dut.io.killed.valid.expect(false.B) - pokeRecovery(dut, newOccupied = 2) + pokeRecovery(dut, firstKilledSlot = 2) dut.io.e1.valid.expect(false.B) dut.io.killed.valid.expect(true.B) dut.io.killed.bits.i2.row.member.group.ridSlot.expect(3.U) @@ -234,7 +243,8 @@ class OooIexE1TransferSlotSpec extends AnyFunSuite with ChiselSim { test("rejects an I2 row whose recipe exceeds the retained domain capability") { import OooIexDomainCapability._ simulate(new OooIexE1TransferSlot(p, - acceptedCapabilities = mask(SimpleAlu))) { dut => + acceptedCapabilities = mask(SimpleAlu), + coreParams = OooRecoveryMembership.coreParams(p))) { dut => clear(dut) pokeI2(dut, ridSlot = 1, data = 0, capability = mask(MultiCycleAlu)) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionClusterSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexExecutionClusterSpec.scala index ec823b13..4c7230be 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionClusterSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexExecutionClusterSpec.scala @@ -2,34 +2,15 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.DestinationKind +import circt.stage.ChiselStage +import linxcore.common.{DestinationKind, OperandClass} import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.ParamProfiles import org.scalatest.funsuite.AnyFunSuite class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { - private val base = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 8, - iqEntriesPerBank = 2, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - private val profile = OooIexLinxPhysicalProfile(base) + private val core = ParamProfiles.W4 + private val profile = OooIexPhysicalProfile.fromCoreParams(core) private val p = profile.params private def clear(dut: OooIexExecutionCluster): Unit = { @@ -37,33 +18,52 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { input.valid.poke(false.B) input.bits.poke(0.U.asTypeOf(input.bits)) } - dut.io.recoveryApply.valid.poke(false.B) - dut.io.recoveryApply.bits.poke( - 0.U.asTypeOf(dut.io.recoveryApply.bits)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) dut.io.storeAddress.foreach(_.ready.poke(true.B)) dut.io.storeData.foreach(_.ready.poke(true.B)) dut.io.multiCycleAlu.foreach(_.ready.poke(true.B)) - dut.io.system.foreach(_.ready.poke(true.B)) dut.io.pointerAuth.foreach(_.ready.poke(true.B)) dut.io.floatingVector.ready.poke(true.B) - dut.io.engineCommand.ready.poke(true.B) - dut.io.memoryRequest.foreach(_.ready.poke(true.B)) - dut.io.memoryResponse.foreach { response => - response.valid.poke(false.B) - response.bits.poke(0.U.asTypeOf(response.bits)) - } + dut.io.robNoflushReady.ready.poke(false.B) + dut.io.robNoflush.valid.poke(false.B) + dut.io.robNoflush.bits.poke(0.U.asTypeOf(dut.io.robNoflush.bits)) + dut.io.systemIssue.foreach(_.ready.poke(true.B)) + dut.io.cmdIssue.ready.poke(true.B) + dut.io.systemCmdResolve.ready.poke(true.B) + dut.io.load.liqAlloc.ready.poke(true.B) + dut.io.load.liqAllocLoadId.poke( + 0.U.asTypeOf(dut.io.load.liqAllocLoadId)) + dut.io.load.rebind.valid.poke(false.B) + dut.io.load.rebind.bits.poke(0.U.asTypeOf(dut.io.load.rebind.bits)) + dut.io.load.liqRebind.ready.poke(true.B) + dut.io.load.attemptLaunch.valid.poke(false.B) + dut.io.load.attemptLaunch.bits.poke( + 0.U.asTypeOf(dut.io.load.attemptLaunch.bits)) + dut.io.load.completion.valid.poke(false.B) + dut.io.load.completion.bits.poke( + 0.U.asTypeOf(dut.io.load.completion.bits)) dut.io.pWrite.foreach(_.ready.poke(true.B)) dut.io.tWrite.foreach(_.ready.poke(true.B)) dut.io.uWrite.foreach(_.ready.poke(true.B)) dut.io.bctrl.foreach(_.ready.poke(true.B)) dut.io.trace.foreach(_.ready.poke(true.B)) - dut.io.completion.foreach(_.ready.poke(true.B)) + dut.io.robResolve.foreach(_.ready.poke(true.B)) + dut.io.recoveryEvent.foreach(_.ready.poke(true.B)) } private def pokeMember(target: RobMemberKey, ridSlot: Int): Unit = { target.group.valid.poke(true.B) target.group.peId.poke(3.U) - target.group.stid.poke(1.U) + target.group.stid.poke(0.U) target.group.ridSlot.poke(ridSlot.U) target.group.ridGeneration.poke(1.U) target.bid.valid.poke(true.B) @@ -88,7 +88,7 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { val row = execute.i2.row.schedule row.valid.poke(true.B) row.peId.poke(3.U) - row.stid.poke(1.U) + row.stid.poke(0.U) row.epoch.poke(7.U) pokeMember(row.member, ridSlot) row.reservation.valid.poke(true.B) @@ -123,7 +123,7 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { payload.immediate.poke(immediate.U) payload.uopKey.primaryParent.valid.poke(true.B) payload.uopKey.primaryParent.peId.poke(3.U) - payload.uopKey.primaryParent.stid.poke(1.U) + payload.uopKey.primaryParent.stid.poke(0.U) payload.uopKey.primaryParent.instructionId.poke((20 + ridSlot).U) payload.uopKey.uopCount.poke(1.U) row.destinations(0).valid.poke(true.B) @@ -133,8 +133,98 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { row.destinations(0).ptagGeneration.poke(3.U) } + private def pokeCanonicalLoad( + dut: OooIexExecutionCluster, + lane: Int, + ridSlot: Int, + ptag: Int): Unit = { + val opcode = FrontendOpcodeDecodeTable.OP_LDI + val rule = OooOpcodeRecipeTable.Rules.find(_.opcode == opcode).get + pokeRoute(dut, lane, OooUopClass.Agu, OooDispatchClass.Agu, + OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress), + ridSlot) + + val execute = dut.io.e1(lane).bits + val i2 = execute.i2 + val row = i2.row.schedule + val payload = i2.row.payload + row.transactionId.poke((200 + ridSlot).U) + row.inFlight.poke(true.B) + row.reservation.bank.poke(0.U) + row.reservation.writePort.poke(0.U) + row.reservation.speculativeSlot.poke((ridSlot % p.iqEntriesPerBank).U) + row.reservation.reservationEpoch.poke(9.U) + row.sources(0).valid.poke(true.B) + row.sources(0).ready.poke(true.B) + row.sources(0).operandClass.poke(OperandClass.P) + row.sources(0).ptag.poke(17.U) + row.sources(0).ptagGeneration.poke(3.U) + i2.sourceMask.poke(1.U) + i2.sourceData(0).poke(0x1000.U) + i2.pcValid.poke(true.B) + i2.pc.poke(0x4000.U) + + payload.opcode.poke(opcode.U) + payload.recipe.opcode.poke(opcode.U) + payload.recipe.disposition.poke(rule.disposition.U) + payload.recipe.recipeKind.poke(rule.recipeKind.U) + payload.recipe.dispatchClass.poke(rule.dispatchClass.U) + payload.recipe.sideEffectOwner.poke(rule.sideEffectOwner.U) + payload.recipe.memoryRequestCount.poke(rule.memoryRequestCount.U) + payload.recipe.pcReadRequired.poke(rule.pcReadRequired.B) + payload.recipe.pSourceCount.poke(rule.pSourceCount.U) + payload.recipe.pDestinationCount.poke(rule.pDestinationCount.U) + payload.immediateValid.poke(true.B) + payload.immediate.poke(8.U) + payload.memory.valid.poke(true.B) + payload.memory.isLoad.poke(true.B) + payload.memory.addressMode.poke(OooMemoryAddressMode.BaseOffset) + payload.memory.accessBytes.poke(8.U) + payload.memory.signExtend.poke(false.B) + payload.memory.offset.poke(8.U) + payload.memory.addressSourceMask.poke(1.U) + + payload.memoryOrder.valid.poke(true.B) + payload.memoryOrder.memoryValid.poke(true.B) + payload.memoryOrder.isLoad.poke(true.B) + payload.memoryOrder.requestCount.poke(1.U) + payload.memoryOrder.firstLsid.poke(7.U) + payload.memoryOrder.firstTypeId.poke(4.U) + payload.memoryOrder.before.lsid.poke(7.U) + payload.memoryOrder.before.loadId.poke(4.U) + payload.memoryOrder.after.lsid.poke(8.U) + payload.memoryOrder.after.loadId.poke(5.U) + + row.destinations(0).valid.poke(true.B) + row.destinations(0).kind.poke(DestinationKind.Gpr) + row.destinations(0).atag.poke(6.U) + row.destinations(0).ptag.poke(ptag.U) + row.destinations(0).ptagGeneration.poke(3.U) + payload.previousPDestinations(0).valid.poke(true.B) + payload.previousPDestinations(0).ptag.poke((ptag - 10).U) + } + + private def pokeAttempt( + target: linxcore.lsu.LoadAttemptIdentity, + ridSlot: Int, + generation: BigInt): Unit = { + target.poke(0.U.asTypeOf(target)) + target.valid.poke(true.B) + target.producer.valid.poke(true.B) + target.producer.peId.poke(3.U) + target.producer.stid.poke(0.U) + target.producer.nativeBidValid.poke(true.B) + target.producer.nativeBid.poke(5.U) + target.producer.brobGeneration.poke(2.U) + target.producer.ridSlot.poke(ridSlot.U) + target.producer.ridGeneration.poke(1.U) + target.producer.memberIndex.poke(0.U) + target.producer.residentGeneration.poke(4.U) + target.generation.poke(generation.U) + } + test("routes every nonlocal execution family through an explicit boundary") { - simulate(new OooIexExecutionCluster(profile)) { dut => + simulate(new OooIexExecutionCluster(core)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -151,15 +241,50 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { dut.io.e1(stdLane).ready.expect(true.B) dut.io.e1(stdLane).valid.poke(false.B) - val fsuLane = profile.pickerIndex("fsu0") - pokeRoute(dut, fsuLane, OooUopClass.Cmd, OooDispatchClass.Cmd, + val cmdLane = profile.pickerIndex("cmd0") + pokeRoute(dut, cmdLane, OooUopClass.Cmd, OooDispatchClass.Cmd, OooIexDomainCapability.mask(OooIexDomainCapability.EngineCommand), 2) - dut.io.engineCommand.valid.expect(true.B) + val cmd = dut.io.e1(cmdLane).bits + cmd.i2.row.transactionId.poke(202.U) + cmd.i2.row.payload.opcode.poke(0x77.U) + cmd.i2.row.payload.recipe.opcode.poke(0x77.U) + cmd.i2.row.payload.recipe.disposition.poke( + OooOpcodeDisposition.Dispatch.U) + cmd.i2.row.payload.recipe.sideEffectOwner.poke( + OooSideEffectOwner.Commit.U) + cmd.i2.row.payload.uopKey.primaryParent.valid.poke(true.B) + cmd.i2.row.payload.uopKey.primaryParent.peId.poke(3.U) + cmd.i2.row.payload.uopKey.primaryParent.stid.poke(0.U) + cmd.i2.row.payload.uopKey.primaryParent.instructionId.poke(22.U) + dut.io.robNoflushReady.valid.expect(true.B) + dut.io.robNoflushReady.bits.transactionId.expect(202.U) + dut.io.cmdIssue.valid.expect(false.B) dut.io.floatingVector.valid.expect(false.B) - dut.io.e1(fsuLane).ready.expect(true.B) - dut.io.e1(fsuLane).valid.poke(false.B) + dut.io.e1(cmdLane).ready.expect(false.B) - val specialLane = profile.pickerIndex("alu2") + val permit = dut.io.robNoflush.bits + permit.transactionId.poke(202.U) + permit.instruction.peId.poke(3.U) + permit.instruction.stid.poke(0.U) + permit.instruction.instructionId.poke(22.U) + permit.instruction.epoch.poke(7.U) + permit.rob.peId.poke(3.U) + permit.rob.stid.poke(0.U) + permit.rob.ridSlot.poke(2.U) + permit.rob.ridGeneration.poke(1.U) + permit.rob.memberIndex.poke(0.U) + permit.rob.residentGeneration.poke(4.U) + permit.rob.bid.poke(5.U) + permit.rob.brobGeneration.poke(2.U) + dut.io.robNoflush.valid.poke(true.B) + dut.io.robNoflushReady.ready.poke(true.B) + dut.io.cmdIssue.valid.expect(true.B) + dut.io.systemCmdResolve.valid.expect(true.B) + dut.io.systemCmdTerminalFire.expect(true.B) + dut.io.e1(cmdLane).ready.expect(true.B) + dut.io.e1(cmdLane).valid.poke(false.B) + + val specialLane = profile.pickerIndex("sys0") pokeRoute(dut, specialLane, OooUopClass.Alu, OooDispatchClass.Alu, OooIexDomainCapability.mask(OooIexDomainCapability.MultiCycleAlu, OooIexDomainCapability.PointerAuth), 3) @@ -170,7 +295,7 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { } test("executes two simple ALUs through W1 and two atomic W2 terminals") { - simulate(new OooIexExecutionCluster(profile)) { dut => + simulate(new OooIexExecutionCluster(core)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -197,10 +322,94 @@ class OooIexExecutionClusterSpec extends AnyFunSuite with ChiselSim { dut.io.pWrite(0).bits.key.ptag.expect(30.U) dut.io.pWrite(2).valid.expect(true.B) dut.io.pWrite(2).bits.key.ptag.expect(31.U) - dut.io.completion(0).bits.key.group.ridSlot.expect(1.U) - dut.io.completion(1).bits.key.group.ridSlot.expect(2.U) + dut.io.robResolve(0).bits.rob.ridSlot.expect(1.U) + dut.io.robResolve(1).bits.rob.ridSlot.expect(2.U) + dut.clock.step() + dut.io.empty.expect(true.B) + } + } + + test("owns one scalar load from E1 through canonical launch and terminal") { + simulate(new OooIexExecutionCluster(core)) { dut => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + val lane = profile.pickerIndex("agu1-lda") + val ridSlot = 3 + val loadSlot = 2 + val ptag = 31 + dut.io.load.liqAllocLoadId.valid.poke(true.B) + dut.io.load.liqAllocLoadId.value.poke(loadSlot.U) + dut.io.load.liqAllocLoadId.wrap.poke(false.B) + pokeCanonicalLoad(dut, lane, ridSlot, ptag) + dut.io.e1(lane).ready.expect(true.B) dut.clock.step() + dut.io.e1(lane).valid.poke(false.B) + + dut.io.load.liqAlloc.valid.expect(true.B) + dut.io.load.liqAlloc.bits.addr.expect(0x1008.U) + dut.io.load.liqAlloc.bits.returnPipeIndex.expect(1.U) + val attemptGeneration = + dut.io.load.liqAlloc.bits.attempt.generation.peek().litValue + dut.clock.step() + dut.io.loadMetadataOccupied.expect(1.U) + + dut.io.load.attemptLaunch.bits.poke( + 0.U.asTypeOf(dut.io.load.attemptLaunch.bits)) + dut.io.load.attemptLaunch.bits.loadId.valid.poke(true.B) + dut.io.load.attemptLaunch.bits.loadId.slot.poke(loadSlot.U) + dut.io.load.attemptLaunch.bits.loadId.generation.poke(0.U) + pokeAttempt(dut.io.load.attemptLaunch.bits.attempt, + ridSlot, attemptGeneration) + dut.io.load.attemptLaunch.valid.poke(true.B) + val speculativePort = p.iexTerminalWidth * p.maxDestinationOperands + 1 + dut.io.wakeup(speculativePort).valid.expect(true.B) + dut.io.wakeup(speculativePort).bits.ptag.expect(ptag.U) + dut.clock.step() + dut.io.load.attemptLaunch.valid.poke(false.B) + + val completion = dut.io.load.completion.bits + completion.poke(0.U.asTypeOf(completion)) + completion.peId.poke(3.U) + completion.stid.poke(0.U) + completion.tid.poke(0.U) + completion.payload.valid.poke(true.B) + completion.payload.loadId.valid.poke(true.B) + completion.payload.loadId.slot.poke(loadSlot.U) + completion.payload.loadId.generation.poke(0.U) + pokeAttempt(completion.payload.attempt, ridSlot, attemptGeneration) + completion.payload.dst.valid.poke(true.B) + completion.payload.dst.kind.poke(DestinationKind.Gpr) + completion.payload.dst.archTag.poke(6.U) + completion.payload.dst.physTag.poke(ptag.U) + completion.payload.dst.oldPhysTag.poke((ptag - 10).U) + completion.payload.data.poke(BigInt("1122334455667788", 16).U) + dut.io.load.completion.valid.poke(true.B) + + dut.io.load.completion.ready.expect(true.B) + dut.io.bypass(3).valid.expect(true.B) + dut.io.bypass(3).bits.ptag.expect(ptag.U) + dut.io.pWrite(2).valid.expect(true.B) + dut.io.pWrite(2).bits.key.ptag.expect(ptag.U) + dut.io.pWrite(2).bits.data.expect( + BigInt("1122334455667788", 16).U) + dut.io.robResolve(1).valid.expect(true.B) + dut.io.robResolve(1).bits.rob.ridSlot.expect(ridSlot.U) + dut.io.terminalFireMask.expect(2.U) + dut.clock.step() + dut.io.load.completion.valid.poke(false.B) + dut.io.loadMetadataOccupied.expect(0.U) dut.io.empty.expect(true.B) } } + + test("elaborates with one canonical load owner and no migration tracker") { + val systemVerilog = ChiselStage.emitSystemVerilog( + new OooIexExecutionCluster(core)) + + assert(systemVerilog.contains("OooIexCanonicalLoadOwnership load")) + assert(!systemVerilog.contains("OooIexLoadUnit")) + } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala index c788650c..8825eba4 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala @@ -1,50 +1,30 @@ package linxcore.ooo import circt.stage.ChiselStage +import linxcore.params.ParamProfiles import org.scalatest.funsuite.AnyFunSuite -/** Production-top structural integration. Dynamic stage behavior remains - * covered by the focused S1-to-E1, execution-cluster, terminal, and operand +/** Canonical private-cluster structural integration. Dynamic stage behavior is + * covered by the focused dispatch-to-E1, execution-cluster, terminal, and operand * file suites so this gate does not rebuild the monolithic formal IQ in * Verilator. */ class OooIexExecutionPipelineSpec extends AnyFunSuite { - private val base = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 8, - iqEntriesPerBank = 1, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 1, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) + private val core = ParamProfiles.W4 - test("elaborates the formal fourteen-lane S1-to-W2 plus canonical STQ composition") { - val profile = OooIexLinxPhysicalProfile(base) + test("installs canonical issue and execution owners without legacy ingress") { + val profile = OooIexPhysicalProfile.fromCoreParams(core) val systemVerilog = ChiselStage.emitSystemVerilog( - new OooIexExecutionStorePipeline(profile, stqEntries = 4)) + new OooIexExecutionPipeline(core)) - assert(profile.pickerFunctions.length == 14) - assert(profile.params.iexReleaseWidth == 14) + assert(profile.pickerFunctions.length == profile.params.iexReleaseWidth) assert(profile.params.iexTerminalWidth == 2) - assert(systemVerilog.contains("module OooIexExecutionStorePipeline")) - assert(systemVerilog.contains("OooIexExecutionPipeline execution")) - assert(systemVerilog.contains("OooIexStoreStqFabric store")) - assert(systemVerilog.contains("STQSCBCommitBackend storeCommit")) + assert(systemVerilog.contains("module OooIexExecutionPipeline")) assert(systemVerilog.contains("OooIexPipeline issue")) assert(systemVerilog.contains("OooIexExecutionCluster execute")) + assert("OooIexCanonicalLoadOwnership load".r + .findAllMatchIn(systemVerilog).length == 1) + assert(!systemVerilog.contains("OooIexS1Transaction")) + assert(!systemVerilog.contains("OooDispatchRelease")) } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionStoreIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexExecutionStoreIntegrationSpec.scala deleted file mode 100644 index 7a7ead18..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexExecutionStoreIntegrationSpec.scala +++ /dev/null @@ -1,554 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, Valid} -import linxcore.lsu.{STQEntryBankRow, STQEntryStatus, STQMemoryClass, - STQMemoryClassifyToken, STQRobCommitToken, STQSCBCommitBackend} -import org.scalatest.funsuite.AnyFunSuite - -class OooIexExecutionStoreHarnessIO( - val p: OooParams, - val stqEntries: Int) extends Bundle { - val reserve = Flipped(Decoupled(new OooIexIssueRow(p))) - val e1 = Flipped(Vec(OooIexLinxPhysicalProfile.ExecutionLaneCount, - Decoupled(new OooIexExecuteTransaction(p)))) - val recoveryPrepare = Flipped(Valid(new OooResidencyRecoveryPlan(p))) - val recoveryPrepareReady = Output(Bool()) - val recoveryFire = Input(Bool()) - val robStoreCommit = Flipped(Decoupled(new STQRobCommitToken( - p.robGroupsPerStid, p.lsidWidth, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth))) - val memoryClassify = Flipped(Decoupled(new STQMemoryClassifyToken( - stqEntries, p.robGroupsPerStid, p.peIdWidth, p.stidWidth, - p.nativeBidWidth, p.ridGenerationWidth, p.brobGenerationWidth, - p.robMemberIndexWidth, p.residentGenerationWidth, - p.executeSlotGenerationWidth))) - val storeCommitIssueEnable = Input(Bool()) - val serializedStoreRequestReady = Input(Bool()) - val serializedStoreRequestValid = Output(Bool()) - val serializedStoreRequestTxnId = Output(UInt(8.W)) - val serializedStoreResponseValid = Input(Bool()) - val serializedStoreResponseTxnId = Input(UInt(8.W)) - val serializedStoreResponseError = Input(Bool()) - val serializedStoreResponseReady = Output(Bool()) - val robStoreCommitAccepted = Output(Bool()) - val memoryClassifyAccepted = Output(Bool()) - val storeCommitQueueCount = Output(UInt(3.W)) - val scbAcceptedMask = Output(UInt(4.W)) - val logicalCompletionCount = Output(UInt(2.W)) - val rows = Output(Vec(stqEntries, new STQEntryBankRow( - p.robGroupsPerStid, - peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, - tidWidth = p.stidWidth, - mapQDepth = p.tuMapQDepthPerStid, - lsidWidth = p.lsidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth))) - val addressReadyMask = Output(UInt(stqEntries.W)) - val dataReadyMask = Output(UInt(stqEntries.W)) - val routeRejected = Output(Vec( - OooIexLinxPhysicalProfile.ExecutionLaneCount, Bool())) -} - -class OooIexExecutionStoreHarness( - val profile: OooIexPhysicalProfile, - val stqEntries: Int) extends Module { - val p = profile.params - val io = IO(new OooIexExecutionStoreHarnessIO(p, stqEntries)) - - val execute = Module(new OooIexExecutionCluster(profile)) - val store = Module(new OooIexStoreStqFabric(p, stqEntries)) - val storeCommit = Module(new STQSCBCommitBackend( - entries = stqEntries, - queueEntries = 4, - issueWidth = 2, - scbEntries = 4, - scbResponseBufferDepth = 2, - mapQDepth = p.tuMapQDepthPerStid, - robEntries = p.robGroupsPerStid, - lsidWidth = p.lsidWidth, - peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, - tidWidth = p.stidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth)) - - for (lane <- 0 until OooIexLinxPhysicalProfile.ExecutionLaneCount) { - execute.io.e1(lane).valid := io.e1(lane).valid - execute.io.e1(lane).bits := io.e1(lane).bits - io.e1(lane).ready := execute.io.e1(lane).ready - io.routeRejected(lane) := execute.io.routeRejected(lane).valid - } - store.io.reserve <> io.reserve - store.io.storeAddress <> execute.io.storeAddress - store.io.storeData <> execute.io.storeData - store.io.loadCancel := execute.io.loadCancel - store.io.loadForwardQuery.foreach { query => - query.valid := false.B - query.bits := 0.U.asTypeOf(query.bits) - } - store.io.loadForwardResponse.foreach(_.ready := true.B) - - store.io.recoveryPrepare := io.recoveryPrepare - io.recoveryPrepareReady := store.io.recoveryPrepareReady - val recoveryApply = io.recoveryFire && store.io.recoveryPrepareReady - store.io.recoveryFire := recoveryApply - execute.io.recoveryApply.valid := recoveryApply - execute.io.recoveryApply.bits := io.recoveryPrepare.bits - - execute.io.multiCycleAlu.foreach(_.ready := true.B) - execute.io.system.foreach(_.ready := true.B) - execute.io.pointerAuth.foreach(_.ready := true.B) - execute.io.floatingVector.ready := true.B - execute.io.engineCommand.ready := true.B - execute.io.memoryRequest.foreach(_.ready := true.B) - execute.io.memoryResponse.foreach { response => - response.valid := false.B - response.bits := 0.U.asTypeOf(response.bits) - } - execute.io.pWrite.foreach(_.ready := true.B) - execute.io.tWrite.foreach(_.ready := true.B) - execute.io.uWrite.foreach(_.ready := true.B) - execute.io.bctrl.foreach(_.ready := true.B) - execute.io.trace.foreach(_.ready := true.B) - execute.io.completion.foreach(_.ready := true.B) - - storeCommit.io.rows := store.io.rows - storeCommit.io.recoveryActive := io.recoveryPrepare.valid - storeCommit.io.robStoreCommit <> io.robStoreCommit - storeCommit.io.memoryClassify <> io.memoryClassify - store.io.markCommitValid := storeCommit.io.markCommitValid - store.io.markCommitIndex := storeCommit.io.markCommitIndex - storeCommit.io.markCommitAccepted := store.io.markCommitAccepted - store.io.commitFreeMaskValid := storeCommit.io.commitFreeMaskValid - store.io.commitFreeMask := storeCommit.io.commitFreeMask - storeCommit.io.commitFreeAcceptedMask := store.io.commitFreeAcceptedMask - storeCommit.io.issueEnable := io.storeCommitIssueEnable - storeCommit.io.evictEnable := false.B - storeCommit.io.dcacheReady := true.B - storeCommit.io.dcacheWriteHit := false.B - storeCommit.io.dcacheTagHit := false.B - storeCommit.io.l2RequestReady := true.B - storeCommit.io.rawRespValid := false.B - storeCommit.io.rawRespTxnId := 0.U - storeCommit.io.rawRespWrite := false.B - storeCommit.io.rawRespUpgrade := false.B - storeCommit.io.serializedRequest.ready := - io.serializedStoreRequestReady - io.serializedStoreRequestValid := storeCommit.io.serializedRequest.valid - io.serializedStoreRequestTxnId := - storeCommit.io.serializedRequest.bits.transactionId - storeCommit.io.serializedResponse.valid := - io.serializedStoreResponseValid - storeCommit.io.serializedResponse.bits.transactionId := - io.serializedStoreResponseTxnId - storeCommit.io.serializedResponse.bits.error := - io.serializedStoreResponseError - io.serializedStoreResponseReady := - storeCommit.io.serializedResponse.ready - - io.robStoreCommitAccepted := storeCommit.io.robStoreCommitAccepted - io.memoryClassifyAccepted := storeCommit.io.memoryClassifyAccepted - io.storeCommitQueueCount := storeCommit.io.drainQueueCount - io.scbAcceptedMask := storeCommit.io.scbAcceptedMask - io.logicalCompletionCount := storeCommit.io.logicalCompletionCount - io.rows := store.io.rows - io.addressReadyMask := store.io.addrReadyMask - io.dataReadyMask := store.io.dataReadyMask -} - -class OooIexExecutionStoreIntegrationSpec - extends AnyFunSuite with ChiselSim { - private val base = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 8, - iqEntriesPerBank = 2, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 1, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16, - lsidWidth = 40) - private val profile = OooIexLinxPhysicalProfile(base) - private val p = profile.params - - private def pokeMember( - member: RobMemberKey, - memberIndex: Int, - ridSlot: Int): Unit = { - member.group.valid.poke(true.B) - member.group.peId.poke(1.U) - member.group.stid.poke(1.U) - member.group.ridSlot.poke(ridSlot.U) - member.group.ridGeneration.poke(3.U) - member.bid.valid.poke(true.B) - member.bid.value.poke(0x81.U) - member.brobGeneration.poke(4.U) - member.memberIndex.poke(memberIndex.U) - member.residentGeneration.poke(5.U) - } - - private def pokeStoreRow( - row: OooIexIssueRow, - memberIndex: Int, - ridSlot: Int, - firstLsid: BigInt, - firstStoreId: BigInt): Unit = { - row.poke(0.U.asTypeOf(row)) - row.schedule.valid.poke(true.B) - row.schedule.peId.poke(1.U) - row.schedule.stid.poke(1.U) - pokeMember(row.schedule.member, memberIndex, ridSlot) - row.schedule.reservation.valid.poke(true.B) - row.schedule.reservation.uopClass.poke(OooUopClass.Agu) - row.payload.recipe.valid.poke(true.B) - row.payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - row.payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - row.payload.recipe.recipeKind.poke(OooOpcodeRecipeKind.ScalarStore.U) - row.payload.recipe.lateSplitKind.poke( - OooLateSplitKind.StoreAddressData.U) - row.payload.memory.valid.poke(true.B) - row.payload.memory.isStore.poke(true.B) - row.payload.memory.addressMode.poke(OooMemoryAddressMode.BaseOffset) - row.payload.memory.accessBytes.poke(8.U) - row.payload.memory.offset.poke(16.U) - row.payload.memory.addressSourceMask.poke(1.U) - row.payload.memory.dataSourceMask.poke(4.U) - row.payload.memoryOrder.valid.poke(true.B) - row.payload.memoryOrder.memoryValid.poke(true.B) - row.payload.memoryOrder.isStore.poke(true.B) - row.payload.memoryOrder.requestCount.poke(1.U) - row.payload.memoryOrder.firstLsid.poke(firstLsid.U) - row.payload.memoryOrder.firstTypeId.poke(firstStoreId.U) - } - - private def pokeStoreExecute( - execute: OooIexExecuteTransaction, - lane: Int, - addressHalf: Boolean, - ridSlot: Int, - firstLsid: BigInt, - firstStoreId: BigInt): Unit = { - execute.poke(0.U.asTypeOf(execute)) - val ownerClass = if (addressHalf) OooUopClass.Agu else OooUopClass.Std - val dispatchClass = if (addressHalf) OooDispatchClass.Agu - else OooDispatchClass.Std - val capability = if (addressHalf) OooIexDomainCapability.StoreAddress - else OooIexDomainCapability.StoreData - execute.ownerClass.poke(ownerClass) - execute.ownerLane.poke(lane.U) - execute.slotGeneration.poke(2.U) - pokeStoreRow(execute.i2.row, - memberIndex = if (addressHalf) 0 else 1, - ridSlot = ridSlot, - firstLsid = firstLsid, - firstStoreId = firstStoreId) - execute.i2.row.schedule.childIndex.poke( - (if (addressHalf) 0 else 1).U) - execute.i2.row.schedule.reservation.uopClass.poke(ownerClass) - execute.i2.row.payload.recipe.dispatchClass.poke(dispatchClass.U) - execute.i2.row.payload.recipe.dispatchCapabilities(dispatchClass - 1) - .poke(OooIexDomainCapability.mask(capability).U) - execute.i2.sourceMask.poke((if (addressHalf) 1 else 4).U) - execute.i2.sourceData(0).poke(0x1000.U) - execute.i2.sourceData(2).poke( - BigInt("1122334455667788", 16).U) - } - - private def initializeHarness(dut: OooIexExecutionStoreHarness): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.e1.foreach { lane => - lane.valid.poke(false.B) - lane.bits.poke(0.U.asTypeOf(lane.bits)) - } - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.robStoreCommit.valid.poke(false.B) - dut.io.robStoreCommit.bits.poke( - 0.U.asTypeOf(dut.io.robStoreCommit.bits)) - dut.io.memoryClassify.valid.poke(false.B) - dut.io.memoryClassify.bits.poke( - 0.U.asTypeOf(dut.io.memoryClassify.bits)) - dut.io.storeCommitIssueEnable.poke(false.B) - dut.io.serializedStoreRequestReady.poke(false.B) - dut.io.serializedStoreResponseValid.poke(false.B) - dut.io.serializedStoreResponseTxnId.poke(0.U) - dut.io.serializedStoreResponseError.poke(false.B) - } - - private def pokeExactOwner(owner: linxcore.lsu.STQExactOwner): Unit = { - owner.valid.poke(true.B) - owner.peId.poke(1.U) - owner.stid.poke(1.U) - owner.nativeBidValid.poke(true.B) - owner.nativeBid.poke(0x81.U) - owner.brobGeneration.poke(4.U) - owner.ridSlot.poke(2.U) - owner.ridGeneration.poke(3.U) - owner.memberIndex.poke(0.U) - owner.residentGeneration.poke(5.U) - } - - test("recovery join requires both owners and emits one common fire") { - simulate(new OooIexExecutionStoreRecoveryJoin(p)) { dut => - dut.io.requested.poke(0.U.asTypeOf(dut.io.requested)) - dut.io.executionReady.poke(false.B) - dut.io.executionPrepared.poke( - 0.U.asTypeOf(dut.io.executionPrepared)) - dut.io.executionRejected.poke( - 0.U.asTypeOf(dut.io.executionRejected)) - dut.io.storeReady.poke(false.B) - dut.io.storeRejected.poke(false.B) - dut.io.fire.poke(false.B) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - dut.io.requested.valid.poke(true.B) - dut.io.requested.bits.valid.poke(true.B) - dut.io.requested.bits.oldHead.stid.poke(1.U) - dut.io.executionReady.poke(true.B) - dut.io.executionPrepared.valid.poke(true.B) - dut.io.executionPrepared.stid.poke(1.U) - dut.io.prepareReady.expect(false.B) - dut.io.commonFire.expect(false.B) - - dut.io.storeReady.poke(true.B) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.valid.expect(true.B) - dut.io.prepared.stid.expect(1.U) - dut.io.fire.poke(true.B) - dut.io.commonFire.expect(true.B) - - dut.io.storeReady.poke(false.B) - dut.io.storeRejected.poke(true.B) - dut.io.prepareReady.expect(false.B) - dut.io.commonFire.expect(false.B) - dut.io.rejected.valid.expect(true.B) - dut.io.rejected.bits.residentRowsExact.expect(false.B) - dut.io.rejected.bits.s1RowsExact.expect(true.B) - - dut.io.executionRejected.valid.poke(true.B) - dut.io.executionRejected.bits.residentRowsExact.poke(true.B) - dut.io.executionRejected.bits.s1RowsExact.poke(false.B) - dut.io.rejected.bits.residentRowsExact.expect(true.B) - dut.io.rejected.bits.s1RowsExact.expect(false.B) - } - } - - test("formal STA and STD lanes fill one pre-reserved canonical STQ row") { - simulate(new OooIexExecutionStoreHarness(profile, stqEntries = 4)) { - dut => - initializeHarness(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - val firstLsid = BigInt("100000001", 16) - val firstStoreId = BigInt("200000001", 16) - pokeStoreRow(dut.io.reserve.bits, 0, 2, firstLsid, firstStoreId) - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - val staLane = profile.pickerIndex("agu0-sta") - val stdLane = profile.pickerIndex("alu0") - pokeStoreExecute(dut.io.e1(staLane).bits, staLane, - addressHalf = true, 2, firstLsid, firstStoreId) - pokeStoreExecute(dut.io.e1(stdLane).bits, stdLane, - addressHalf = false, 2, firstLsid, firstStoreId) - dut.io.e1(staLane).valid.poke(true.B) - dut.io.e1(stdLane).valid.poke(true.B) - dut.io.e1(staLane).ready.expect(true.B) - dut.io.e1(stdLane).ready.expect(true.B) - dut.io.routeRejected(staLane).expect(false.B) - dut.io.routeRejected(stdLane).expect(false.B) - dut.clock.step() - dut.io.e1(staLane).valid.poke(false.B) - dut.io.e1(stdLane).valid.poke(false.B) - - // E1 capture, STD admission, mask phase, then data/completion phase. - dut.clock.step(4) - dut.io.addressReadyMask.expect(1.U) - dut.io.dataReadyMask.expect(1.U) - dut.io.rows(0).addr.expect(0x1010.U) - dut.io.rows(0).data.expect( - BigInt("1122334455667788", 16).U) - } - } - - test("formal store reaches CommitQ and SCB through the single canonical STQ") { - simulate(new OooIexExecutionStoreHarness(profile, stqEntries = 4)) { - dut => - initializeHarness(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - val firstLsid = BigInt("100000001", 16) - val firstStoreId = BigInt("200000001", 16) - pokeStoreRow(dut.io.reserve.bits, 0, 2, firstLsid, firstStoreId) - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - val staLane = profile.pickerIndex("agu0-sta") - val stdLane = profile.pickerIndex("alu0") - pokeStoreExecute(dut.io.e1(staLane).bits, staLane, - addressHalf = true, 2, firstLsid, firstStoreId) - pokeStoreExecute(dut.io.e1(stdLane).bits, stdLane, - addressHalf = false, 2, firstLsid, firstStoreId) - dut.io.e1(staLane).valid.poke(true.B) - dut.io.e1(stdLane).valid.poke(true.B) - dut.clock.step() - dut.io.e1(staLane).valid.poke(false.B) - dut.io.e1(stdLane).valid.poke(false.B) - dut.clock.step(3) - dut.io.rows(0).status.expect(STQEntryStatus.Wait) - - val classify = dut.io.memoryClassify.bits - classify.poke(0.U.asTypeOf(classify)) - classify.lease.valid.poke(true.B) - classify.lease.index.poke(0.U) - classify.lease.generation.poke( - dut.io.rows(0).leaseGeneration.peek()) - pokeExactOwner(classify.exactOwner) - classify.logicalBeat.poke(0.U) - classify.memoryClass.poke(STQMemoryClass.NormalCacheable) - dut.io.memoryClassify.valid.poke(true.B) - dut.io.memoryClassify.ready.expect(true.B) - dut.io.memoryClassifyAccepted.expect(true.B) - dut.clock.step() - dut.io.memoryClassify.valid.poke(false.B) - - val commit = dut.io.robStoreCommit.bits - commit.poke(0.U.asTypeOf(commit)) - commit.logicalFirstLsid.poke(firstLsid.U) - commit.logicalFirstStoreId.poke(firstStoreId.U) - commit.logicalRequestCount.poke(1.U) - commit.logicalBeat.poke(0.U) - pokeExactOwner(commit.exactOwner) - dut.io.robStoreCommit.valid.poke(true.B) - dut.io.robStoreCommit.ready.expect(true.B) - dut.io.robStoreCommitAccepted.expect(true.B) - dut.clock.step() - dut.io.robStoreCommit.valid.poke(false.B) - dut.io.rows(0).status.expect(STQEntryStatus.Commit) - dut.io.storeCommitQueueCount.expect(1.U) - - dut.io.storeCommitIssueEnable.poke(true.B) - dut.clock.step() - dut.io.scbAcceptedMask.expect(1.U) - dut.io.logicalCompletionCount.expect(1.U) - dut.clock.step() - dut.io.rows(0).valid.expect(false.B) - } - } - - test("serialized terminal free is retained across recovery prepare") { - simulate(new OooIexExecutionStoreHarness(profile, stqEntries = 4)) { - dut => - initializeHarness(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - val firstLsid = BigInt("100000011", 16) - val firstStoreId = BigInt("200000011", 16) - pokeStoreRow(dut.io.reserve.bits, 0, 2, firstLsid, firstStoreId) - dut.io.reserve.valid.poke(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - val staLane = profile.pickerIndex("agu0-sta") - val stdLane = profile.pickerIndex("alu0") - pokeStoreExecute(dut.io.e1(staLane).bits, staLane, - addressHalf = true, 2, firstLsid, firstStoreId) - pokeStoreExecute(dut.io.e1(stdLane).bits, stdLane, - addressHalf = false, 2, firstLsid, firstStoreId) - dut.io.e1(staLane).valid.poke(true.B) - dut.io.e1(stdLane).valid.poke(true.B) - dut.clock.step() - dut.io.e1(staLane).valid.poke(false.B) - dut.io.e1(stdLane).valid.poke(false.B) - dut.clock.step(3) - - val classify = dut.io.memoryClassify.bits - classify.poke(0.U.asTypeOf(classify)) - classify.lease.valid.poke(true.B) - classify.lease.index.poke(0.U) - classify.lease.generation.poke( - dut.io.rows(0).leaseGeneration.peek()) - pokeExactOwner(classify.exactOwner) - classify.logicalBeat.poke(0.U) - classify.memoryClass.poke(STQMemoryClass.DeviceMmio) - dut.io.memoryClassify.valid.poke(true.B) - dut.io.memoryClassify.ready.expect(true.B) - dut.clock.step() - dut.io.memoryClassify.valid.poke(false.B) - - val commit = dut.io.robStoreCommit.bits - commit.poke(0.U.asTypeOf(commit)) - commit.logicalFirstLsid.poke(firstLsid.U) - commit.logicalFirstStoreId.poke(firstStoreId.U) - commit.logicalRequestCount.poke(1.U) - commit.logicalBeat.poke(0.U) - pokeExactOwner(commit.exactOwner) - dut.io.robStoreCommit.valid.poke(true.B) - dut.io.robStoreCommit.ready.expect(true.B) - dut.clock.step() - dut.io.robStoreCommit.valid.poke(false.B) - - dut.io.storeCommitIssueEnable.poke(true.B) - dut.clock.step(2) - dut.io.serializedStoreRequestValid.expect(true.B) - val transactionId = - dut.io.serializedStoreRequestTxnId.peek().litValue - dut.io.serializedStoreRequestReady.poke(true.B) - dut.clock.step() - dut.io.serializedStoreRequestReady.poke(false.B) - - dut.io.recoveryPrepare.valid.poke(true.B) - dut.io.serializedStoreResponseValid.poke(true.B) - dut.io.serializedStoreResponseTxnId.poke(transactionId.U) - dut.io.serializedStoreResponseReady.expect(true.B) - dut.clock.step() - dut.io.serializedStoreResponseValid.poke(false.B) - dut.io.rows(0).valid.expect(true.B) - dut.io.rows(0).status.expect(STQEntryStatus.Commit) - - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - dut.io.rows(0).valid.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueBlockMatrixSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueBlockMatrixSpec.scala index 8e123089..51e2d04b 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueBlockMatrixSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexIssueBlockMatrixSpec.scala @@ -3,6 +3,7 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim import circt.stage.ChiselStage +import linxcore.params.ParamProfiles import org.scalatest.funsuite.AnyFunSuite class OooIexIssueBlockMatrixSpec extends AnyFunSuite with ChiselSim { @@ -91,7 +92,7 @@ class OooIexIssueBlockMatrixSpec extends AnyFunSuite with ChiselSim { test("canonical operand-read composition exposes policy and diagnostics") { val sv = ChiselStage.emitSystemVerilog(new OooIexIssueReadFabric( - p.copy(iexIssueDomainCount = 1))) + ParamProfiles.W2)) assert(sv.contains("module OooIexIssueReadFabric")) assert(sv.contains("io_issuePolicy_globalQuiesce")) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueE1IntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueE1IntegrationSpec.scala deleted file mode 100644 index aead2fd6..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueE1IntegrationSpec.scala +++ /dev/null @@ -1,271 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.Decoupled -import org.scalatest.funsuite.AnyFunSuite - -class OooIexIssueE1IntegrationHarnessIO(val p: OooParams) extends Bundle { - val s1 = Flipped(Decoupled(new OooIexS1Transaction(p))) - val e1 = Vec(p.iexIssueDomainCount, - Decoupled(new OooIexExecuteTransaction(p))) - val dispatchReleases = Vec(p.iexReleaseWidth, - Decoupled(new OooDispatchRelease(p))) - def dispatchRelease = dispatchReleases(0) - val transferFire = Output(Bool()) - val transferFireMask = Output(UInt(p.iexReleaseWidth.W)) - val residentEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val inFlightEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val empty = Output(Bool()) -} - -class OooIexIssueE1IntegrationHarness( - val profile: OooIexPhysicalProfile) extends Module { - val p = profile.params - val io = IO(new OooIexIssueE1IntegrationHarnessIO(p)) - - val pipeline = Module(new OooIexPipeline(profile)) - - pipeline.io.s1 <> io.s1 - pipeline.io.wakeup.foreach(_ := 0.U.asTypeOf(pipeline.io.wakeup.head)) - pipeline.io.loadCancel.foreach( - _ := 0.U.asTypeOf(pipeline.io.loadCancel.head)) - pipeline.io.ptagRecycle.valid := false.B - pipeline.io.ptagRecycle.bits := - 0.U.asTypeOf(pipeline.io.ptagRecycle.bits) - pipeline.io.recoveryPrepare.valid := false.B - pipeline.io.recoveryPrepare.bits := - 0.U.asTypeOf(pipeline.io.recoveryPrepare.bits) - pipeline.io.recoveryFire := false.B - pipeline.io.issuePolicy := 0.U.asTypeOf(pipeline.io.issuePolicy) - pipeline.io.stageCancels.flatten.foreach { cancel => - cancel.valid := false.B - cancel.bits := 0.U.asTypeOf(cancel.bits) - } - for (port <- 0 until p.pcReadPorts) { - pipeline.io.pcReadResponses(port).valid := - pipeline.io.pcReadRequests(port).valid - pipeline.io.pcReadResponses(port).bits := ("h80000100".U + port.U) - } - pipeline.io.bypass.foreach(_ := 0.U.asTypeOf(pipeline.io.bypass.head)) - pipeline.io.pInit := 0.U.asTypeOf(pipeline.io.pInit) - pipeline.io.pClear.foreach(_ := 0.U.asTypeOf(pipeline.io.pClear.head)) - pipeline.io.pWrite.foreach(_ := 0.U.asTypeOf(pipeline.io.pWrite.head)) - pipeline.io.tClear.foreach(_ := 0.U.asTypeOf(pipeline.io.tClear.head)) - pipeline.io.uClear.foreach(_ := 0.U.asTypeOf(pipeline.io.uClear.head)) - pipeline.io.tWrite.foreach(_ := 0.U.asTypeOf(pipeline.io.tWrite.head)) - pipeline.io.uWrite.foreach(_ := 0.U.asTypeOf(pipeline.io.uWrite.head)) - - for (domain <- 0 until p.iexIssueDomainCount) { - io.e1(domain) <> pipeline.io.e1(domain) - } - io.dispatchReleases <> pipeline.io.dispatchReleases - - io.transferFire := pipeline.io.transferFireMask.orR - io.transferFireMask := pipeline.io.transferFireMask - io.residentEntries := pipeline.io.residentEntries - io.inFlightEntries := pipeline.io.inFlightEntries - io.empty := pipeline.io.empty -} - -class OooIexIssueE1IntegrationSpec extends AnyFunSuite with ChiselSim { - private val baseP = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 8, - iqEntriesPerBank = 2, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - private val profile = OooIexLinxPhysicalProfile(baseP) - private val p = profile.params - - private def pokeMember(target: RobMemberKey, memberIndex: Int): Unit = { - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(2.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(4.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(memberIndex.U) - target.residentGeneration.poke(5.U) - } - - private def pokeSourceFreeAluBru( - dut: OooIexIssueE1IntegrationHarness): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(31.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(3.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(1.U) - request.pRename.epoch.poke(7.U) - request.pRename.transactionId.poke(31.U) - request.pRename.uopMask.poke(3.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(1.U) - request.tuRename.epoch.poke(7.U) - request.tuRename.transactionId.poke(31.U) - request.tuRename.uopMask.poke(3.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(1.U) - request.dispatch.epoch.poke(7.U) - request.dispatch.transactionId.poke(31.U) - request.dispatch.allocationMask.poke(3.U) - - def pokeUop( - index: Int, - opcode: Int, - dispatchClass: Int, - uopClass: OooUopClass.Type, - pcRead: Boolean): Unit = { - val decoded = transaction.decoded.uops(index) - val renamed = request.pRename.uops(index) - val local = request.tuRename.uops(index) - decoded.valid.poke(true.B) - renamed.valid.poke(true.B) - renamed.decoded.valid.poke(true.B) - local.valid.poke(true.B) - Seq(decoded, renamed.decoded).foreach { uop => - uop.opcode.poke(opcode.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(opcode.U) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.dispatchClass.poke(dispatchClass.U) - uop.recipe.dispatchWrites.poke(1.U) - uop.recipe.dispatchDemand(dispatchClass - 1).poke(1.U) - val capability = dispatchClass match { - case OooDispatchClass.Alu => OooIexDomainCapability.mask( - OooIexDomainCapability.SimpleAlu) - case OooDispatchClass.Bru => OooIexDomainCapability.mask( - OooIexDomainCapability.Branch) - case _ => OooIexDomainCapability.ValidMask - } - uop.recipe.dispatchCapabilities(dispatchClass - 1) - .poke(capability.U) - uop.recipe.pcReadRequired.poke(pcRead.B) - uop.recipe.pcReadClass.poke(dispatchClass.U) - uop.plannedChildCount.poke(1.U) - uop.identity.key.primaryParent.valid.poke(true.B) - uop.identity.key.primaryParent.peId.poke(3.U) - uop.identity.key.primaryParent.stid.poke(1.U) - uop.identity.key.primaryParent.instructionId.poke((101 + index).U) - uop.identity.key.primaryParent.epoch.poke(7.U) - uop.identity.parentCount.poke(1.U) - val parent = uop.identity.parents(0) - parent.key.valid.poke(true.B) - parent.key.peId.poke(3.U) - parent.key.stid.poke(1.U) - parent.key.instructionId.poke((101 + index).U) - parent.key.epoch.poke(7.U) - } - pokeMember(renamed.member, index) - pokeMember(local.member, index) - if (pcRead) { - val pcToken = request.o3.parentPcTokens(index)(0) - pcToken.valid.poke(true.B) - pcToken.index.poke((5 + index).U) - pcToken.byteOffset.poke((6 + index).U) - pcToken.allocationEpoch.poke(3.U) - } - val allocation = request.dispatch.allocations(index) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(index.U) - allocation.childIndex.poke(0.U) - allocation.reservation.valid.poke(true.B) - allocation.reservation.uopClass.poke(uopClass) - allocation.reservation.bank.poke(0.U) - allocation.reservation.writePort.poke(index.U) - allocation.reservation.speculativeSlot.poke(index.U) - allocation.reservation.reservationEpoch.poke((9 + index).U) - } - - pokeUop(0, opcode = 1, OooDispatchClass.Alu, - OooUopClass.Alu, pcRead = false) - pokeUop(1, opcode = 73, OooDispatchClass.Bru, - OooUopClass.Bru, pcRead = true) - dut.io.s1.valid.poke(true.B) - } - - test("canonical IQ release and dispatch return share the E1 transfer") { - simulate(new OooIexIssueE1IntegrationHarness(profile)) { dut => - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.e1.foreach(_.ready.poke(false.B)) - dut.io.dispatchReleases.foreach(_.ready.poke(true.B)) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeSourceFreeAluBru(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - - var cycles = 0 - val aluRelease = profile.picker("alu0").releasePort - val bruRelease = profile.picker("bru0").releasePort - val aluLane = profile.pickerIndex("alu0") - val bruLane = profile.pickerIndex("bru0") - val expectedFireMask = (BigInt(1) << aluRelease) | - (BigInt(1) << bruRelease) - while (dut.io.transferFireMask.peek().litValue != expectedFireMask && - cycles < 12) { - dut.clock.step() - cycles += 1 - } - dut.io.transferFireMask.expect(expectedFireMask.U) - dut.io.dispatchReleases(aluRelease).valid.expect(true.B) - dut.io.dispatchReleases(bruRelease).valid.expect(true.B) - dut.io.dispatchReleases(aluRelease).bits.member.memberIndex.expect(0.U) - dut.io.dispatchReleases(bruRelease).bits.member.memberIndex.expect(1.U) - dut.clock.step() - - dut.io.e1(aluLane).valid.expect(true.B) - dut.io.e1(bruLane).valid.expect(true.B) - dut.io.e1(aluLane).bits.ownerClass.expect(OooUopClass.Alu) - dut.io.e1(bruLane).bits.ownerClass.expect(OooUopClass.Bru) - dut.io.e1(aluLane).bits.i2.row.member.group.ridSlot.expect(2.U) - dut.io.e1(bruLane).bits.i2.row.member.memberIndex.expect(1.U) - dut.io.residentEntries(OooDispatchClass.Alu - 1)(0).expect(0.U) - dut.io.residentEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(0).expect(0.U) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - dut.io.empty.expect(false.B) - - dut.io.e1(aluLane).ready.poke(true.B) - dut.io.e1(bruLane).ready.poke(true.B) - dut.clock.step() - dut.io.empty.expect(true.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1FabricSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1FabricSpec.scala deleted file mode 100644 index d494c68c..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1FabricSpec.scala +++ /dev/null @@ -1,435 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooIexIssueP1FabricSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - iexIssueDomainCount = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - - private def clear(dut: OooIexIssueP1Fabric): Unit = { - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.wakeup.foreach(_.poke(0.U.asTypeOf(dut.io.wakeup.head))) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.dispatchRelease.ready.poke(true.B) - dut.io.ptagRecycle.valid.poke(false.B) - dut.io.ptagRecycle.bits.poke(0.U.asTypeOf(dut.io.ptagRecycle.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Bru - 1).poke(1.U) - dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) - for (domain <- 0 until p.iexIssueDomainCount) { - dut.io.readDecisionValid(domain).poke(false.B) - dut.io.readGrant(domain).poke(false.B) - dut.io.sourceDataValid(domain).poke(0.U) - dut.io.sourceData(domain).foreach(_.poke(0.U)) - dut.io.pcDataValid(domain).poke(false.B) - dut.io.pcData(domain).poke(0.U) - dut.io.i2(domain).ready.poke(false.B) - } - dut.io.bypass.foreach( - _.poke(0.U.asTypeOf(dut.io.bypass.head))) - dut.io.loadCancel.foreach( - _.poke(0.U.asTypeOf(dut.io.loadCancel.head))) - dut.io.stageCancels.flatten.foreach { cancel => - cancel.valid.poke(false.B) - cancel.bits.poke(0.U.asTypeOf(cancel.bits)) - } - } - - private def pokeMember(target: RobMemberKey, memberIndex: Int): Unit = { - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(2.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(4.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(memberIndex.U) - target.residentGeneration.poke(5.U) - } - - private def pokeUop( - dut: OooIexIssueP1Fabric, - index: Int, - opcode: Int, - dispatchClass: Int, - uopClass: OooUopClass.Type, - pcRead: Boolean): Unit = { - val request = dut.io.s1.bits - val decoded = request.o3.request.reservation.transaction.decoded.uops(index) - val renamed = request.pRename.uops(index) - val local = request.tuRename.uops(index) - decoded.valid.poke(true.B) - renamed.valid.poke(true.B) - renamed.decoded.valid.poke(true.B) - local.valid.poke(true.B) - Seq(decoded, renamed.decoded).foreach { uop => - uop.opcode.poke(opcode.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(opcode.U) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.dispatchClass.poke(dispatchClass.U) - uop.recipe.dispatchWrites.poke(1.U) - uop.recipe.dispatchDemand(dispatchClass - 1).poke(1.U) - val capability = dispatchClass match { - case OooDispatchClass.Alu => OooIexDomainCapability.mask( - OooIexDomainCapability.SimpleAlu) - case OooDispatchClass.Bru => OooIexDomainCapability.mask( - OooIexDomainCapability.Branch) - case _ => OooIexDomainCapability.ValidMask - } - uop.recipe.dispatchCapabilities(dispatchClass - 1) - .poke(capability.U) - uop.recipe.pcReadRequired.poke(pcRead.B) - uop.recipe.pcReadClass.poke(dispatchClass.U) - uop.plannedChildCount.poke(1.U) - uop.identity.key.primaryParent.valid.poke(true.B) - uop.identity.key.primaryParent.peId.poke(3.U) - uop.identity.key.primaryParent.stid.poke(1.U) - uop.identity.key.primaryParent.instructionId.poke((101 + index).U) - uop.identity.key.primaryParent.epoch.poke(7.U) - uop.identity.parentCount.poke(1.U) - val parent = uop.identity.parents(0) - parent.key.valid.poke(true.B) - parent.key.peId.poke(3.U) - parent.key.stid.poke(1.U) - parent.key.instructionId.poke((101 + index).U) - parent.key.epoch.poke(7.U) - } - pokeMember(renamed.member, index) - pokeMember(local.member, index) - - if (pcRead) { - val pcToken = request.o3.parentPcTokens(index)(0) - pcToken.valid.poke(true.B) - pcToken.index.poke((5 + index).U) - pcToken.byteOffset.poke((6 + index).U) - pcToken.allocationEpoch.poke(3.U) - } - - val allocation = request.dispatch.allocations(index) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(index.U) - allocation.childIndex.poke(0.U) - allocation.reservation.valid.poke(true.B) - allocation.reservation.uopClass.poke(uopClass) - allocation.reservation.bank.poke(0.U) - allocation.reservation.writePort.poke(index.U) - allocation.reservation.speculativeSlot.poke((index + 1).U) - allocation.reservation.reservationEpoch.poke((9 + index).U) - } - - private def pokeTwoDomainTransaction(dut: OooIexIssueP1Fabric): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(31.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(3.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(1.U) - request.pRename.epoch.poke(7.U) - request.pRename.transactionId.poke(31.U) - request.pRename.uopMask.poke(3.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(1.U) - request.tuRename.epoch.poke(7.U) - request.tuRename.transactionId.poke(31.U) - request.tuRename.uopMask.poke(3.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(1.U) - request.dispatch.epoch.poke(7.U) - request.dispatch.transactionId.poke(31.U) - request.dispatch.allocationMask.poke(3.U) - - pokeUop(dut, 0, opcode = 1, OooDispatchClass.Alu, - OooUopClass.Alu, pcRead = false) - pokeUop(dut, 1, opcode = 73, OooDispatchClass.Bru, - OooUopClass.Bru, pcRead = true) - dut.io.s1.valid.poke(true.B) - } - - private def pokeTwoAluBankTransaction(dut: OooIexIssueP1Fabric): Unit = { - pokeTwoDomainTransaction(dut) - val request = dut.io.s1.bits - val decoded = request.o3.request.reservation.transaction.decoded.uops(1) - val renamed = request.pRename.uops(1).decoded - Seq(decoded, renamed).foreach { uop => - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.recipe.dispatchDemand.poke(0.U.asTypeOf(uop.recipe.dispatchDemand)) - uop.recipe.dispatchDemand(OooDispatchClass.Alu - 1).poke(1.U) - uop.recipe.dispatchCapabilities.poke( - 0.U.asTypeOf(uop.recipe.dispatchCapabilities)) - uop.recipe.dispatchCapabilities(OooDispatchClass.Alu - 1).poke( - OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) - uop.recipe.pcReadRequired.poke(false.B) - uop.recipe.pcReadClass.poke(OooDispatchClass.Alu.U) - } - request.dispatch.allocations(1).reservation.uopClass.poke( - OooUopClass.Alu) - request.dispatch.allocations(1).reservation.bank.poke(1.U) - } - - private def pokeTwoAguCapabilityTransaction( - dut: OooIexIssueP1Fabric): Unit = { - import OooIexDomainCapability._ - pokeTwoDomainTransaction(dut) - val request = dut.io.s1.bits - for (index <- 0 until 2) { - val capability = if (index == 0) mask(LoadAddress) - else mask(StoreAddress) - Seq( - request.o3.request.reservation.transaction.decoded.uops(index), - request.pRename.uops(index).decoded).foreach { uop => - uop.recipe.dispatchClass.poke(OooDispatchClass.Agu.U) - uop.recipe.dispatchDemand.poke( - 0.U.asTypeOf(uop.recipe.dispatchDemand)) - uop.recipe.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) - uop.recipe.dispatchCapabilities.poke( - 0.U.asTypeOf(uop.recipe.dispatchCapabilities)) - uop.recipe.dispatchCapabilities(OooDispatchClass.Agu - 1) - .poke(capability.U) - uop.recipe.pcReadRequired.poke(false.B) - uop.recipe.pcReadClass.poke(OooDispatchClass.Agu.U) - } - request.dispatch.allocations(index).reservation.uopClass.poke( - OooUopClass.Agu) - request.dispatch.allocations(index).reservation.bank.poke(0.U) - } - } - - private def pokeRelease( - dut: OooIexIssueP1Fabric, - memberIndex: Int, - uopClass: OooUopClass.Type, - bank: Int = 0): Unit = { - val release = dut.io.release.bits - release.poke(0.U.asTypeOf(release)) - pokeMember(release.member, memberIndex) - release.dispatch.peId.poke(3.U) - release.dispatch.stid.poke(1.U) - release.dispatch.epoch.poke(7.U) - release.dispatch.transactionId.poke(31.U) - pokeMember(release.dispatch.member, memberIndex) - release.dispatch.reservation.valid.poke(true.B) - release.dispatch.reservation.uopClass.poke(uopClass) - release.dispatch.reservation.bank.poke(bank.U) - release.dispatch.reservation.writePort.poke(memberIndex.U) - release.dispatch.reservation.speculativeSlot.poke((memberIndex + 1).U) - release.dispatch.reservation.reservationEpoch.poke((9 + memberIndex).U) - dut.io.release.valid.poke(true.B) - } - - test("parallel domains claim independently and one denial does not cancel its peer") { - simulate(new OooIexIssueP1Fabric(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - dut.io.empty.expect(true.B) - - pokeTwoDomainTransaction(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step(4) - - dut.io.readAttempts(0).valid.expect(true.B) - dut.io.readAttempts(0).bits.pcRequired.expect(false.B) - dut.io.readAttempts(1).valid.expect(true.B) - dut.io.readAttempts(1).bits.pcRequired.expect(true.B) - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(0).expect(1.U) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(1.U) - - dut.io.readDecisionValid(0).poke(true.B) - dut.io.readGrant(0).poke(true.B) - dut.io.readDecisionValid(1).poke(true.B) - dut.io.readGrant(1).poke(false.B) - dut.io.retryFeedback(1).valid.expect(true.B) - dut.clock.step() - dut.io.readDecisionValid(0).poke(false.B) - dut.io.readGrant(0).poke(false.B) - dut.io.readDecisionValid(1).poke(false.B) - - dut.io.i2(0).valid.expect(true.B) - dut.io.i2(0).bits.row.reservation.uopClass.expect(OooUopClass.Alu) - dut.io.i1Occupied(1).expect(false.B) - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(0).expect(1.U) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - - dut.io.i2(0).ready.poke(true.B) - dut.clock.step() - dut.io.i2(0).ready.poke(false.B) - dut.clock.step(2) - dut.io.readAttempts(1).valid.expect(true.B) - - dut.io.readDecisionValid(1).poke(true.B) - dut.io.readGrant(1).poke(true.B) - dut.io.pcDataValid(1).poke(true.B) - dut.io.pcData(1).poke("h80000127".U) - dut.clock.step() - dut.io.readDecisionValid(1).poke(false.B) - dut.io.readGrant(1).poke(false.B) - dut.io.i2(1).valid.expect(true.B) - dut.io.i2(1).bits.pc.expect("h80000127".U) - dut.io.i2(1).ready.poke(true.B) - dut.clock.step() - dut.io.i2(1).ready.poke(false.B) - - pokeRelease(dut, 0, OooUopClass.Alu) - dut.io.release.ready.expect(true.B) - dut.clock.step() - pokeRelease(dut, 1, OooUopClass.Bru) - dut.io.release.ready.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - - dut.io.lanesEmpty.expect(true.B) - dut.io.empty.expect(true.B) - dut.io.residentEntries(OooDispatchClass.Alu - 1)(0).expect(0.U) - dut.io.residentEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - - // Reuse the quiescent fabric with two ALU domains split by bank. This - // covers the other legal topology relation without another elaboration. - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Alu - 1).poke(2.U) - pokeTwoAluBankTransaction(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step(4) - dut.io.readAttempts(0).valid.expect(true.B) - dut.io.readAttempts(0).bits.reservation.bank.expect(0.U) - dut.io.readAttempts(1).valid.expect(true.B) - dut.io.readAttempts(1).bits.reservation.bank.expect(1.U) - for (domain <- 0 until p.iexIssueDomainCount) { - dut.io.readDecisionValid(domain).poke(true.B) - dut.io.readGrant(domain).poke(true.B) - } - dut.clock.step() - for (domain <- 0 until p.iexIssueDomainCount) { - dut.io.readDecisionValid(domain).poke(false.B) - dut.io.readGrant(domain).poke(false.B) - dut.io.i2(domain).valid.expect(true.B) - dut.io.i2(domain).ready.poke(true.B) - } - dut.clock.step() - dut.io.i2.foreach(_.ready.poke(false.B)) - pokeRelease(dut, 0, OooUopClass.Alu, bank = 0) - dut.clock.step() - pokeRelease(dut, 1, OooUopClass.Alu, bank = 1) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.empty.expect(true.B) - } - } - - test("rejects overlapping class and bank projections") { - intercept[Exception] { - simulate(new OooIexIssueP1Fabric(p)) { dut => - clear(dut) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Alu - 1).poke(1.U) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - dut.clock.step() - } - } - } - - test("capability-disjoint LDA and STA pickers issue from one AGU owner") { - import OooIexDomainCapability._ - simulate(new OooIexIssueP1Fabric(p, - Seq(mask(LoadAddress), mask(StoreAddress)))) { dut => - clear(dut) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Agu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Agu - 1).poke(1.U) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeTwoAguCapabilityTransaction(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step(4) - - dut.io.readAttempts(0).valid.expect(true.B) - dut.io.readAttempts(0).bits.reservation.speculativeSlot.expect(1.U) - dut.io.readAttempts(1).valid.expect(true.B) - dut.io.readAttempts(1).bits.reservation.speculativeSlot.expect(2.U) - dut.io.inFlightEntries(OooDispatchClass.Agu - 1)(0).expect(2.U) - } - } - - test("keeps an unsupported multi-cycle ALU row resident and unclaimed") { - import OooIexDomainCapability._ - simulate(new OooIexIssueP1Fabric(p, - Seq(mask(SimpleAlu), mask(SimpleAlu)))) { dut => - clear(dut) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Alu - 1).poke(2.U) - pokeTwoAluBankTransaction(dut) - val request = dut.io.s1.bits - Seq( - request.o3.request.reservation.transaction.decoded.uops(1), - request.pRename.uops(1).decoded).foreach { uop => - uop.recipe.dispatchCapabilities(OooDispatchClass.Alu - 1) - .poke(mask(MultiCycleAlu).U) - } - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step(4) - - dut.io.readAttempts(0).valid.expect(true.B) - dut.io.readAttempts(1).valid.expect(false.B) - dut.io.residentEntries(OooDispatchClass.Alu - 1)(1).expect(1.U) - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(1).expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1LaneSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1LaneSpec.scala deleted file mode 100644 index 5df0546b..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueP1LaneSpec.scala +++ /dev/null @@ -1,403 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.OperandClass -import org.scalatest.funsuite.AnyFunSuite - -class OooIexIssueP1LaneSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - - private def clear(dut: OooIexIssueP1Lane): Unit = { - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.wakeup.foreach(_.poke(0.U.asTypeOf(dut.io.wakeup.head))) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.dispatchRelease.ready.poke(false.B) - dut.io.ptagRecycle.valid.poke(false.B) - dut.io.ptagRecycle.bits.poke(0.U.asTypeOf(dut.io.ptagRecycle.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.pickBankEnables.foreach(_.poke(0.U)) - dut.io.pickBankEnables(OooDispatchClass.Bru - 1).poke(1.U) - dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - dut.io.sourceDataValid.poke(0.U) - dut.io.sourceData.foreach(_.poke(0.U)) - dut.io.pcDataValid.poke(false.B) - dut.io.pcData.poke(0.U) - dut.io.bypass.foreach( - _.poke(0.U.asTypeOf(dut.io.bypass.head))) - dut.io.loadCancel.foreach( - _.poke(0.U.asTypeOf(dut.io.loadCancel.head))) - dut.io.stageCancel.foreach { cancel => - cancel.valid.poke(false.B) - cancel.bits.poke(0.U.asTypeOf(cancel.bits)) - } - dut.io.i2.ready.poke(false.B) - } - - private def pokeMember(target: RobMemberKey): Unit = { - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(2.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(4.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(0.U) - target.residentGeneration.poke(5.U) - } - - private def pokeLoadProducer(target: RobMemberKey): Unit = { - target.poke(0.U.asTypeOf(target)) - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(1.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(3.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(0.U) - target.residentGeneration.poke(4.U) - } - - private def pokeLoadToken( - target: OooIexLoadGeneration, - generation: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.valid.poke(true.B) - pokeLoadProducer(target.producer) - target.generation.poke(generation.U) - } - - private def pokeI2StageCancel(dut: OooIexIssueP1Lane): Unit = { - val cancel = dut.io.stageCancel(1).bits - cancel.poke(0.U.asTypeOf(cancel)) - cancel.stage.poke(OooIexStageCancelPoint.I2) - pokeMember(cancel.member) - cancel.reservation.valid.poke(true.B) - cancel.reservation.uopClass.poke(OooUopClass.Bru) - cancel.reservation.bank.poke(0.U) - cancel.reservation.writePort.poke(0.U) - cancel.reservation.speculativeSlot.poke(1.U) - cancel.reservation.reservationEpoch.poke(9.U) - cancel.reasonMask.poke( - (BigInt(1) << OooIexIssueBlockReason.SideDoorConflict).U) - dut.io.stageCancel(1).valid.poke(true.B) - } - - private def pokeOnePcBru(dut: OooIexIssueP1Lane): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(31.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(1.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(1.U) - request.pRename.epoch.poke(7.U) - request.pRename.transactionId.poke(31.U) - request.pRename.uopMask.poke(1.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(1.U) - request.tuRename.epoch.poke(7.U) - request.tuRename.transactionId.poke(31.U) - request.tuRename.uopMask.poke(1.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(1.U) - request.dispatch.epoch.poke(7.U) - request.dispatch.transactionId.poke(31.U) - request.dispatch.allocationMask.poke(1.U) - - val decoded = transaction.decoded.uops(0) - val renamed = request.pRename.uops(0) - val local = request.tuRename.uops(0) - decoded.valid.poke(true.B) - renamed.valid.poke(true.B) - renamed.decoded.valid.poke(true.B) - local.valid.poke(true.B) - Seq(decoded, renamed.decoded).foreach { uop => - uop.opcode.poke(73.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(73.U) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Bru.U) - uop.recipe.dispatchWrites.poke(1.U) - uop.recipe.dispatchDemand(OooDispatchClass.Bru - 1).poke(1.U) - uop.recipe.dispatchCapabilities(OooDispatchClass.Bru - 1).poke(1.U) - uop.recipe.pcReadRequired.poke(true.B) - uop.recipe.pcReadClass.poke(OooDispatchClass.Bru.U) - uop.plannedChildCount.poke(1.U) - uop.identity.key.primaryParent.valid.poke(true.B) - uop.identity.key.primaryParent.peId.poke(3.U) - uop.identity.key.primaryParent.stid.poke(1.U) - uop.identity.key.primaryParent.instructionId.poke(101.U) - uop.identity.key.primaryParent.epoch.poke(7.U) - uop.identity.parentCount.poke(1.U) - val parent = uop.identity.parents(0) - parent.key.valid.poke(true.B) - parent.key.peId.poke(3.U) - parent.key.stid.poke(1.U) - parent.key.instructionId.poke(101.U) - parent.key.epoch.poke(7.U) - } - pokeMember(renamed.member) - pokeMember(local.member) - - val pcToken = request.o3.parentPcTokens(0)(0) - pcToken.valid.poke(true.B) - pcToken.index.poke(5.U) - pcToken.byteOffset.poke(6.U) - pcToken.allocationEpoch.poke(3.U) - - val allocation = request.dispatch.allocations(0) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(0.U) - allocation.childIndex.poke(0.U) - allocation.reservation.valid.poke(true.B) - allocation.reservation.uopClass.poke(OooUopClass.Bru) - allocation.reservation.bank.poke(0.U) - allocation.reservation.writePort.poke(0.U) - allocation.reservation.speculativeSlot.poke(1.U) - allocation.reservation.reservationEpoch.poke(9.U) - dut.io.s1.valid.poke(true.B) - } - - test("denied PC read retries the exact IQ member and repicks it") { - simulate(new OooIexIssueP1Lane(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOnePcBru(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() // S2 bind - dut.clock.step() // S3 resident - dut.clock.step() // picker retains the exact scheduling token - dut.clock.step() // exact token joins payload and enters I1 - - dut.io.i1Occupied.expect(true.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(1.U) - dut.io.readAttempt.valid.expect(true.B) - dut.io.readAttempt.bits.pcRequired.expect(true.B) - dut.io.readAttempt.bits.pcToken.index.expect(5.U) - dut.io.readAttempt.bits.pcToken.byteOffset.expect(6.U) - - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(false.B) - dut.io.retryFeedback.valid.expect(true.B) - dut.io.retryFeedback.bits.member.group.ridSlot.expect(2.U) - dut.io.retryFeedback.bits.reservation.speculativeSlot.expect(1.U) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - dut.io.i1Occupied.expect(false.B) - - dut.clock.step() // retry makes the row selectable; picker retains it - dut.clock.step() // repicked row enters I1 again - dut.io.i1Occupied.expect(true.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(1.U) - dut.io.readAttempt.valid.expect(true.B) - - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(true.B) - dut.io.pcDataValid.poke(true.B) - dut.io.pcData.poke("h80000126".U) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - dut.io.i2.valid.expect(true.B) - dut.io.i2.bits.pcValid.expect(true.B) - dut.io.i2.bits.pc.expect("h80000126".U) - dut.io.i2.bits.row.opcode.expect(73.U) - } - } - - test("cancels an exact speculative load copy and reissues a new generation") { - simulate(new OooIexIssueP1Lane(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOnePcBru(dut) - val request = dut.io.s1.bits - val decoded = request.o3.request.reservation.transaction.decoded.uops(0) - val renamed = request.pRename.uops(0) - Seq(decoded.sources(0), renamed.decoded.sources(0)).foreach { source => - source.valid.poke(true.B) - source.operandClass.poke(OperandClass.P) - source.atag.poke(2.U) - } - renamed.sources(0).decoded.valid.poke(true.B) - renamed.sources(0).decoded.operandClass.poke(OperandClass.P) - renamed.sources(0).decoded.atag.poke(2.U) - renamed.sources(0).pMapping.valid.poke(true.B) - renamed.sources(0).pMapping.ptag.poke(17.U) - renamed.sources(0).pMapping.ptagGeneration.poke(3.U) - renamed.sources(0).pMapping.ready.poke(false.B) - renamed.sources(0).pMapping.stid.poke(1.U) - renamed.sources(0).pMapping.epoch.poke(7.U) - - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() // S2 bind - dut.clock.step() // S3 resident, still not ready - - val wakeup = dut.io.wakeup(0) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.kind.poke(OooIexWakeupKind.SpeculativeLoad) - wakeup.bits.stid.poke(1.U) - wakeup.bits.epoch.poke(7.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - pokeLoadToken(wakeup.bits.load, generation = 7) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.clock.step() // picker retains the now-ready row - dut.clock.step() // bridge joins and enters I1 - dut.io.i1Occupied.expect(true.B) - dut.io.readAttempt.valid.expect(false.B) - - val bypass = dut.io.bypass(0) - bypass.bits.poke(0.U.asTypeOf(bypass.bits)) - bypass.bits.stid.poke(1.U) - bypass.bits.epoch.poke(7.U) - pokeLoadToken(bypass.bits.load, generation = 7) - pokeLoadProducer(bypass.bits.producer) - bypass.bits.operandClass.poke(OperandClass.P) - bypass.bits.ptag.poke(17.U) - bypass.bits.ptagGeneration.poke(3.U) - bypass.bits.stage.poke(OooIexBypassStage.W1) - bypass.bits.data.poke("h1111222233334444".U) - bypass.valid.poke(true.B) - dut.io.readAttempt.valid.expect(true.B) - dut.io.readAttempt.bits.sourceMask.expect(0.U) - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(true.B) - dut.io.pcDataValid.poke(true.B) - dut.io.pcData.poke("h80000126".U) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - bypass.valid.poke(false.B) - dut.io.i2.valid.expect(true.B) - dut.io.i2.bits.sourceData(0).expect("h1111222233334444".U) - - val cancel = dut.io.loadCancel(0) - cancel.bits.poke(0.U.asTypeOf(cancel.bits)) - cancel.bits.stid.poke(1.U) - cancel.bits.epoch.poke(7.U) - pokeLoadToken(cancel.bits.load, generation = 7) - cancel.valid.poke(true.B) - dut.io.i2.valid.expect(false.B) - dut.io.loadCanceled(2).valid.expect(true.B) - dut.clock.step() - cancel.valid.poke(false.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - dut.io.i2.valid.expect(false.B) - - wakeup.bits.load.generation.poke(8.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.clock.step() - dut.clock.step() - dut.io.i1Occupied.expect(true.B) - bypass.bits.load.generation.poke(8.U) - bypass.valid.poke(true.B) - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(true.B) - dut.io.pcDataValid.poke(true.B) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - bypass.valid.poke(false.B) - dut.io.i2.valid.expect(true.B) - dut.io.i2.bits.bypass(0).load.generation.expect(8.U) - } - } - - test("returns an exact I2 resource cancel to the canonical IQ") { - simulate(new OooIexIssueP1Lane(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOnePcBru(dut) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step(4) - dut.io.i1Occupied.expect(true.B) - - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(true.B) - dut.io.pcDataValid.poke(true.B) - dut.io.pcData.poke("h80000126".U) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - dut.io.i2.valid.expect(true.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(1.U) - - pokeI2StageCancel(dut) - dut.io.stageCancel(1).ready.expect(true.B) - dut.io.stageCanceled(1).valid.expect(true.B) - dut.io.i2.valid.expect(false.B) - dut.io.retryFeedback.valid.expect(true.B) - dut.io.retryFeedback.bits.member.group.ridSlot.expect(2.U) - dut.clock.step() - dut.io.stageCancel(1).valid.poke(false.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(0.U) - dut.io.i2Occupied.expect(false.B) - - dut.clock.step() - dut.clock.step() - dut.io.i1Occupied.expect(true.B) - dut.io.inFlightEntries(OooDispatchClass.Bru - 1)(0).expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueReadFabricSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueReadFabricSpec.scala deleted file mode 100644 index 3a7638b3..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueReadFabricSpec.scala +++ /dev/null @@ -1,342 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.OperandClass -import org.scalatest.funsuite.AnyFunSuite - -class OooIexIssueReadFabricSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - iexIssueDomainCount = 1, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - - private val staticTopology = Seq( - OooIexIssueDomainConfig.singleClass(p, - OooUopClass.Alu.asUInt.litValue.toInt, 1, - name = "alu0").copy(capabilities = OooIexDomainCapability.mask( - OooIexDomainCapability.SimpleAlu))) - - private def clear(dut: OooIexIssueReadFabric): Unit = { - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.wakeup.foreach(_.poke(0.U.asTypeOf(dut.io.wakeup.head))) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.dispatchRelease.ready.poke(true.B) - dut.io.ptagRecycle.valid.poke(false.B) - dut.io.ptagRecycle.bits.poke(0.U.asTypeOf(dut.io.ptagRecycle.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) - dut.io.pcReadResponses.foreach( - _.poke(0.U.asTypeOf(dut.io.pcReadResponses.head))) - dut.io.bypass.foreach( - _.poke(0.U.asTypeOf(dut.io.bypass.head))) - dut.io.loadCancel.foreach( - _.poke(0.U.asTypeOf(dut.io.loadCancel.head))) - dut.io.stageCancels.flatten.foreach { cancel => - cancel.valid.poke(false.B) - cancel.bits.poke(0.U.asTypeOf(cancel.bits)) - } - dut.io.pInit.poke(0.U.asTypeOf(dut.io.pInit)) - dut.io.pClear.foreach(_.poke(0.U.asTypeOf(dut.io.pClear.head))) - dut.io.pWrite.foreach(_.poke(0.U.asTypeOf(dut.io.pWrite.head))) - dut.io.tClear.foreach(_.poke(0.U.asTypeOf(dut.io.tClear.head))) - dut.io.uClear.foreach(_.poke(0.U.asTypeOf(dut.io.uClear.head))) - dut.io.tWrite.foreach(_.poke(0.U.asTypeOf(dut.io.tWrite.head))) - dut.io.uWrite.foreach(_.poke(0.U.asTypeOf(dut.io.uWrite.head))) - dut.io.i2(0).ready.poke(false.B) - } - - private def pokeMember(target: RobMemberKey): Unit = { - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(2.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(4.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(0.U) - target.residentGeneration.poke(5.U) - } - - private def pokeOnePSourceAlu(dut: OooIexIssueReadFabric): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(31.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(1.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(1.U) - request.pRename.epoch.poke(7.U) - request.pRename.transactionId.poke(31.U) - request.pRename.uopMask.poke(1.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(1.U) - request.tuRename.epoch.poke(7.U) - request.tuRename.transactionId.poke(31.U) - request.tuRename.uopMask.poke(1.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(1.U) - request.dispatch.epoch.poke(7.U) - request.dispatch.transactionId.poke(31.U) - request.dispatch.allocationMask.poke(1.U) - - val decoded = transaction.decoded.uops(0) - val renamed = request.pRename.uops(0) - val local = request.tuRename.uops(0) - decoded.valid.poke(true.B) - renamed.valid.poke(true.B) - renamed.decoded.valid.poke(true.B) - local.valid.poke(true.B) - Seq(decoded, renamed.decoded).foreach { uop => - uop.opcode.poke(1.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(1.U) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.recipe.dispatchWrites.poke(1.U) - uop.recipe.dispatchDemand(OooDispatchClass.Alu - 1).poke(1.U) - uop.recipe.dispatchCapabilities(OooDispatchClass.Alu - 1).poke( - OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) - uop.recipe.pcReadRequired.poke(false.B) - uop.recipe.pcReadClass.poke(OooDispatchClass.Alu.U) - uop.plannedChildCount.poke(1.U) - uop.identity.key.primaryParent.valid.poke(true.B) - uop.identity.key.primaryParent.peId.poke(3.U) - uop.identity.key.primaryParent.stid.poke(1.U) - uop.identity.key.primaryParent.instructionId.poke(101.U) - uop.identity.key.primaryParent.epoch.poke(7.U) - uop.identity.parentCount.poke(1.U) - val parent = uop.identity.parents(0) - parent.key.valid.poke(true.B) - parent.key.peId.poke(3.U) - parent.key.stid.poke(1.U) - parent.key.instructionId.poke(101.U) - parent.key.epoch.poke(7.U) - uop.sources(0).valid.poke(true.B) - uop.sources(0).operandClass.poke(OperandClass.P) - uop.sources(0).atag.poke(2.U) - } - renamed.sources(0).decoded.valid.poke(true.B) - renamed.sources(0).decoded.operandClass.poke(OperandClass.P) - renamed.sources(0).decoded.atag.poke(2.U) - renamed.sources(0).pMapping.valid.poke(true.B) - renamed.sources(0).pMapping.ptag.poke(40.U) - renamed.sources(0).pMapping.ptagGeneration.poke(3.U) - renamed.sources(0).pMapping.ready.poke(true.B) - renamed.sources(0).pMapping.stid.poke(1.U) - renamed.sources(0).pMapping.epoch.poke(7.U) - pokeMember(renamed.member) - pokeMember(local.member) - - val allocation = request.dispatch.allocations(0) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(0.U) - allocation.childIndex.poke(0.U) - allocation.reservation.valid.poke(true.B) - allocation.reservation.uopClass.poke(OooUopClass.Alu) - allocation.reservation.bank.poke(0.U) - allocation.reservation.writePort.poke(0.U) - allocation.reservation.speculativeSlot.poke(1.U) - allocation.reservation.reservationEpoch.poke(9.U) - dut.io.s1.valid.poke(true.B) - } - - private def pokeRelease(dut: OooIexIssueReadFabric): Unit = { - val release = dut.io.release.bits - release.poke(0.U.asTypeOf(release)) - pokeMember(release.member) - release.dispatch.peId.poke(3.U) - release.dispatch.stid.poke(1.U) - release.dispatch.epoch.poke(7.U) - release.dispatch.transactionId.poke(31.U) - pokeMember(release.dispatch.member) - release.dispatch.reservation.valid.poke(true.B) - release.dispatch.reservation.uopClass.poke(OooUopClass.Alu) - release.dispatch.reservation.bank.poke(0.U) - release.dispatch.reservation.writePort.poke(0.U) - release.dispatch.reservation.speculativeSlot.poke(1.U) - release.dispatch.reservation.reservationEpoch.poke(9.U) - dut.io.release.valid.poke(true.B) - } - - test("missing canonical P data rejects and exact-repicks before I2") { - simulate(new OooIexIssueReadFabric(p, - staticDomains = staticTopology)) { dut => - clear(dut) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOnePSourceAlu(dut) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - - var cycles = 0 - while (!dut.io.readAttempts(0).valid.peek().litToBoolean && cycles < 8) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.readAttempts(0).valid.peek().litToBoolean, - "the exact ALU row never reached the canonical I1 read attempt") - dut.io.readSelectedMask.expect(1.U) - dut.io.readDeniedMask.expect(0.U) - dut.io.readAttempts(0).bits.sourceMask.expect(1.U) - dut.io.readAttempts(0).bits.sources(0).ptag.expect(40.U) - dut.io.readCapabilities(0).expect(OooIexDomainCapability.mask( - OooIexDomainCapability.SimpleAlu).U) - dut.io.sharedEligibleMask.expect(1.U) - dut.io.sharedConflictMask.expect(0.U) - dut.io.sharedMalformedMask.expect(0.U) - dut.io.readRejected(0).valid.expect(true.B) - dut.io.retryFeedback(0).valid.expect(true.B) - dut.io.retryFeedback(0).bits.member.group.ridSlot.expect(2.U) - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(0).expect(1.U) - dut.clock.step() - dut.io.inFlightEntries(OooDispatchClass.Alu - 1)(0).expect(0.U) - - dut.io.pInit.valid.poke(true.B) - dut.io.pInit.bits.key.stid.poke(1.U) - dut.io.pInit.bits.key.epoch.poke(7.U) - dut.io.pInit.bits.key.ptag.poke(40.U) - dut.io.pInit.bits.key.generation.poke(3.U) - dut.io.pInit.bits.data.poke("h0123456789abcdef".U) - dut.clock.step() - dut.io.pInit.valid.poke(false.B) - - cycles = 0 - while (!dut.io.readAttempts(0).valid.peek().litToBoolean && cycles < 8) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.readAttempts(0).valid.peek().litToBoolean, - "the rejected row did not become eligible for an exact repick") - dut.io.readSelectedMask.expect(1.U) - dut.io.readRejected(0).valid.expect(false.B) - dut.clock.step() - - dut.io.i2(0).valid.expect(true.B) - dut.io.i2(0).bits.sourceData(0).expect("h0123456789abcdef".U) - dut.io.i2(0).bits.row.schedule.sources(0).ptag.expect(40.U) - dut.io.i2(0).ready.poke(true.B) - dut.clock.step() - dut.io.i2(0).ready.poke(false.B) - - pokeRelease(dut) - dut.io.release.ready.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.empty.expect(true.B) - dut.io.pProtocolError.expect(false.B) - dut.io.localProtocolError.expect(false.B) - } - } - - test("arbitrates independent shared resources fairly before RF read") { - import OooIexDomainCapability._ - val sharedP = p.copy(iexIssueDomainCount = 2) - val resources = Seq( - OooIexSharedResourceConfig("divide", MultiCycleAlu, Seq(0, 1)), - OooIexSharedResourceConfig("pointer-auth", PointerAuth, Seq(0, 1)), - OooIexSharedResourceConfig("system", System, Seq(0, 1))) - - simulate(new OooIexSharedResourceArbiter(sharedP, resources)) { dut => - dut.io.requestValid.poke(0.U) - dut.io.capabilities.foreach(_.poke(0.U)) - dut.io.accepted.poke(0.U) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - dut.io.requestValid.poke("b11".U) - dut.io.capabilities(0).poke(mask(MultiCycleAlu).U) - dut.io.capabilities(1).poke(mask(MultiCycleAlu).U) - dut.io.eligible.expect("b01".U) - dut.io.conflicted.expect("b10".U) - dut.io.winners.expect("b01".U) - - dut.io.accepted.poke("b01".U) - dut.clock.step() - dut.io.accepted.poke(0.U) - dut.io.roundRobin(0).expect(1.U) - dut.io.eligible.expect("b10".U) - dut.io.conflicted.expect("b01".U) - - dut.io.capabilities(0).poke(mask(MultiCycleAlu).U) - dut.io.capabilities(1).poke(mask(PointerAuth).U) - dut.io.eligible.expect("b11".U) - dut.io.conflicted.expect(0.U) - dut.io.winners.expect("b11".U) - - dut.io.capabilities(0).poke(mask(SimpleAlu).U) - dut.io.capabilities(1).poke(mask(SimpleAlu).U) - dut.io.eligible.expect("b11".U) - dut.io.conflicted.expect(0.U) - dut.io.winners.expect(0.U) - - dut.io.capabilities(0).poke(mask(SimpleAlu, MultiCycleAlu).U) - dut.io.capabilities(1).poke(mask(SimpleAlu).U) - dut.io.malformed.expect("b01".U) - dut.io.eligible.expect("b10".U) - } - - assertThrows[IllegalArgumentException] { - new OooIexSharedResourceArbiter(sharedP, Seq( - OooIexSharedResourceConfig("divide-a", MultiCycleAlu, Seq(0, 1)), - OooIexSharedResourceConfig("divide-b", MultiCycleAlu, Seq(0, 1)))) - } - } - - test("rejects inconsistent static capabilities and shared participants") { - assertThrows[IllegalArgumentException] { - new OooIexIssueReadFabric(p, - domainCapabilities = Seq(OooIexDomainCapability.mask( - OooIexDomainCapability.Branch)), - staticDomains = staticTopology) - } - assertThrows[IllegalArgumentException] { - new OooIexIssueReadFabric(p, - sharedResources = Seq(OooIexSharedResourceConfig( - "divide", OooIexDomainCapability.MultiCycleAlu, Seq(0, 0))), - staticDomains = staticTopology) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala index 78151a03..c4645e47 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala @@ -1,1400 +1,26 @@ package linxcore.ooo -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import circt.stage.ChiselStage -import linxcore.common.{DestinationKind, OperandClass} +import linxcore.params.ParamProfiles +import linxcore.top.interface.{DispatchTxn, StoreDispatchTxn} import org.scalatest.funsuite.AnyFunSuite -private object OooIexIssueSpec { - final case class Allocation( - uopIndex: Int, - childIndex: Int, - uopClass: Int, - bank: Int, - port: Int, - entry: Int, - reservationEpoch: Int = 1) -} - -class OooIexIssueSpec extends AnyFunSuite with ChiselSim { - import OooIexIssueSpec._ - - private def pokeClass(target: OooUopClass.Type, value: Int): Unit = - value match { - case 0 => target.poke(OooUopClass.Alu) - case 1 => target.poke(OooUopClass.Bru) - case 2 => target.poke(OooUopClass.Agu) - case 3 => target.poke(OooUopClass.Std) - case 4 => target.poke(OooUopClass.Fsu) - case 5 => target.poke(OooUopClass.Sys) - case 6 => target.poke(OooUopClass.Cmd) - case 7 => target.poke(OooUopClass.Boundary) - } - - private def clear(dut: OooIexIssue): Unit = { - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.wakeup.foreach { wakeup => - wakeup.valid.poke(false.B) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - } - dut.io.loadCancel.foreach( - _.poke(0.U.asTypeOf(dut.io.loadCancel.head))) - dut.io.releases.foreach { release => - release.valid.poke(false.B) - release.bits.poke(0.U.asTypeOf(release.bits)) - } - dut.io.dispatchReleases.foreach(_.ready.poke(false.B)) - dut.io.query.poke(0.U.asTypeOf(dut.io.query)) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - val allBanks = (BigInt(1) << dut.p.iqBankCount) - 1 - dut.io.pickBankEnables(0).foreach(_.poke(allBanks.U)) - dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) - dut.io.pick.ready.poke(false.B) - dut.io.pickRetry.valid.poke(false.B) - dut.io.pickRetry.bits.poke(0.U.asTypeOf(dut.io.pickRetry.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.ptagRecycle.valid.poke(false.B) - dut.io.ptagRecycle.bits.poke(0.U.asTypeOf(dut.io.ptagRecycle.bits)) - } - - private def pokeMember( - target: RobMemberKey, - stid: Int, - memberIndex: Int, - residentGeneration: Int = 7, - ridSlot: Int = 1): Unit = { - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(stid.U) - target.group.ridSlot.poke(ridSlot.U) - target.group.ridGeneration.poke(2.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(4.U) - target.brobGeneration.poke(5.U) - target.memberIndex.poke(memberIndex.U) - target.residentGeneration.poke(residentGeneration.U) - } - - private def pokeTransaction( - dut: OooIexIssue, - stid: Int, - transactionId: Int, - allocations: Vector[Allocation], - pSourceReady: Option[Boolean] = None, - pSourceGeneration: Int = 3, - ridSlot: Int = 1, - memberBase: Int = 0): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(6.U) - transaction.plan.transactionId.poke(transactionId.U) - - val activeUops = allocations.map(_.uopIndex).distinct.sorted - val uopMask = activeUops.map(index => 1 << index).sum - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(6.U) - transaction.decoded.uopMask.poke(uopMask.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(stid.U) - request.pRename.epoch.poke(6.U) - request.pRename.transactionId.poke(transactionId.U) - request.pRename.uopMask.poke(uopMask.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(stid.U) - request.tuRename.epoch.poke(6.U) - request.tuRename.transactionId.poke(transactionId.U) - request.tuRename.uopMask.poke(uopMask.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(stid.U) - request.dispatch.epoch.poke(6.U) - request.dispatch.transactionId.poke(transactionId.U) - request.dispatch.allocationMask.poke( - ((BigInt(1) << allocations.length) - 1).U) - - activeUops.foreach { uopIndex => - val uopAllocations = allocations.filter(_.uopIndex == uopIndex) - val childCount = uopAllocations - .map(_.childIndex).max + 1 - val requiredClasses = uopAllocations.map(_.uopClass).distinct - val decoded = transaction.decoded.uops(uopIndex) - val pUop = request.pRename.uops(uopIndex) - val tuUop = request.tuRename.uops(uopIndex) - decoded.valid.poke(true.B) - decoded.opcode.poke((40 + uopIndex).U) - decoded.plannedChildCount.poke(childCount.U) - pUop.valid.poke(true.B) - pUop.decoded.valid.poke(true.B) - pUop.decoded.opcode.poke((40 + uopIndex).U) - pUop.decoded.plannedChildCount.poke(childCount.U) - tuUop.valid.poke(true.B) - pokeMember(pUop.member, stid, - memberIndex = memberBase + uopIndex * 2, ridSlot = ridSlot) - pokeMember(tuUop.member, stid, - memberIndex = memberBase + uopIndex * 2, ridSlot = ridSlot) - - Seq(decoded, pUop.decoded).foreach { logical => - logical.identity.key.primaryParent.valid.poke(true.B) - logical.identity.key.primaryParent.peId.poke(3.U) - logical.identity.key.primaryParent.stid.poke(stid.U) - logical.identity.key.primaryParent.instructionId - .poke((100 + uopIndex).U) - logical.identity.key.primaryParent.epoch.poke(6.U) - logical.identity.parentCount.poke(1.U) - logical.recipe.valid.poke(true.B) - logical.recipe.opcode.poke((40 + uopIndex).U) - logical.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - logical.recipe.pcReadRequired.poke(false.B) - requiredClasses.foreach { uopClass => - logical.recipe.dispatchDemand(uopClass).poke(1.U) - logical.recipe.dispatchCapabilities(uopClass).poke(1.U) - } - val parent = logical.identity.parents(0) - parent.key.valid.poke(true.B) - parent.key.peId.poke(3.U) - parent.key.stid.poke(stid.U) - parent.key.instructionId.poke((100 + uopIndex).U) - parent.key.epoch.poke(6.U) - parent.prediction.valid.poke(true.B) - parent.prediction.predictionTag.poke((20 + uopIndex).U) - } - val pcToken = request.o3.parentPcTokens(uopIndex)(0) - pcToken.valid.poke(true.B) - pcToken.index.poke((uopIndex + stid * 4).U) - pcToken.byteOffset.poke((uopIndex * 4).U) - pcToken.allocationEpoch.poke(2.U) - - Seq(decoded.destinations(0), pUop.decoded.destinations(0)) - .foreach { destination => - destination.valid.poke(true.B) - destination.kind.poke(DestinationKind.Gpr) - destination.atag.poke(3.U) - } - pUop.destinations(0).currentPMapping.valid.poke(true.B) - pUop.destinations(0).currentPMapping.ptag.poke((30 + uopIndex).U) - pUop.destinations(0).currentPMapping.ptagGeneration.poke(4.U) - pUop.destinations(0).previousPMapping.valid.poke(true.B) - pUop.destinations(0).previousPMapping.ptag.poke((20 + uopIndex).U) - pUop.destinations(0).previousPMapping.ptagGeneration.poke(3.U) - - pSourceReady.foreach { ready => - decoded.sources(0).valid.poke(true.B) - decoded.sources(0).operandClass.poke(OperandClass.P) - decoded.sources(0).atag.poke(2.U) - pUop.decoded.sources(0).valid.poke(true.B) - pUop.decoded.sources(0).operandClass.poke(OperandClass.P) - pUop.decoded.sources(0).atag.poke(2.U) - pUop.sources(0).decoded.valid.poke(true.B) - pUop.sources(0).decoded.operandClass.poke(OperandClass.P) - pUop.sources(0).decoded.atag.poke(2.U) - pUop.sources(0).pMapping.valid.poke(true.B) - pUop.sources(0).pMapping.ptag.poke(17.U) - pUop.sources(0).pMapping.ptagGeneration.poke(pSourceGeneration.U) - pUop.sources(0).pMapping.ready.poke(ready.B) - pUop.sources(0).pMapping.stid.poke(stid.U) - pUop.sources(0).pMapping.epoch.poke(6.U) - } - } - - allocations.zipWithIndex.foreach { case (value, lane) => - val allocation = request.dispatch.allocations(lane) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(value.uopIndex.U) - allocation.childIndex.poke(value.childIndex.U) - allocation.reservation.valid.poke(true.B) - pokeClass(allocation.reservation.uopClass, value.uopClass) - allocation.reservation.bank.poke(value.bank.U) - allocation.reservation.writePort.poke(value.port.U) - allocation.reservation.speculativeSlot.poke(value.entry.U) - allocation.reservation.reservationEpoch.poke(value.reservationEpoch.U) - } - dut.io.s1.valid.poke(true.B) - } - - private def pokeStoreTransaction( - dut: OooIexIssue, - stid: Int, - transactionId: Int, - ridSlot: Int, - memberBase: Int, - firstLsid: BigInt, - firstStoreId: BigInt, - allocations: Vector[Allocation]): Unit = { - pokeTransaction(dut, stid, transactionId, allocations, - ridSlot = ridSlot, memberBase = memberBase) - val request = dut.io.s1.bits - val transaction = request.o3.request.reservation.transaction - val decoded = transaction.decoded.uops(0) - val pUop = request.pRename.uops(0) - Seq(decoded, pUop.decoded).foreach { logical => - logical.recipe.recipeKind.poke(OooOpcodeRecipeKind.ScalarStore.U) - logical.recipe.lateSplitKind.poke(OooLateSplitKind.StoreAddressData.U) - logical.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - logical.recipe.memoryRequestCount.poke(1.U) - logical.recipe.dispatchDemand(OooDispatchClass.Agu - 1).poke(1.U) - logical.recipe.dispatchCapabilities(OooDispatchClass.Agu - 1) - .poke(1.U) - logical.recipe.dispatchDemand(OooDispatchClass.Std - 1).poke(1.U) - logical.recipe.dispatchCapabilities(OooDispatchClass.Std - 1) - .poke(2.U) - logical.memory.valid.poke(true.B) - logical.memory.isLoad.poke(false.B) - logical.memory.isStore.poke(true.B) - logical.memory.accessBytes.poke(8.U) - logical.memory.addressSourceMask.poke(1.U) - logical.memory.dataSourceMask.poke(2.U) - logical.destinations(0).valid.poke(false.B) - } - pUop.destinations(0).currentPMapping.valid.poke(false.B) - pUop.destinations(0).previousPMapping.valid.poke(false.B) - transaction.plan.demand.storeIds.poke(1.U) - transaction.decoded.demand.storeIds.poke(1.U) - - val memoryOrder = request.memoryOrder - memoryOrder.valid.poke(true.B) - memoryOrder.peId.poke(3.U) - memoryOrder.stid.poke(stid.U) - memoryOrder.epoch.poke(6.U) - memoryOrder.transactionId.poke(transactionId.U) - memoryOrder.uopMask.poke(1.U) - memoryOrder.before.lsid.poke(firstLsid.U) - memoryOrder.before.storeId.poke(firstStoreId.U) - memoryOrder.after.lsid.poke((firstLsid + 1).U) - memoryOrder.after.storeId.poke((firstStoreId + 1).U) - - val active = memoryOrder.uops(0) - active.valid.poke(true.B) - active.memoryValid.poke(true.B) - active.isLoad.poke(false.B) - active.isStore.poke(true.B) - active.requestCount.poke(1.U) - active.firstLsid.poke(firstLsid.U) - active.firstTypeId.poke(firstStoreId.U) - active.before.lsid.poke(firstLsid.U) - active.before.storeId.poke(firstStoreId.U) - active.after.lsid.poke((firstLsid + 1).U) - active.after.storeId.poke((firstStoreId + 1).U) - - for (uopIndex <- 1 until memoryOrder.uops.length) { - val inactive = memoryOrder.uops(uopIndex) - inactive.valid.poke(false.B) - inactive.memoryValid.poke(false.B) - inactive.isLoad.poke(false.B) - inactive.isStore.poke(false.B) - inactive.requestCount.poke(0.U) - inactive.firstLsid.poke((firstLsid + 1).U) - inactive.firstTypeId.poke((firstStoreId + 1).U) - inactive.before.lsid.poke((firstLsid + 1).U) - inactive.before.storeId.poke((firstStoreId + 1).U) - inactive.after.lsid.poke((firstLsid + 1).U) - inactive.after.storeId.poke((firstStoreId + 1).U) - } - } - - private def query( - dut: OooIexIssue, - uopClass: Int, - bank: Int, - entry: Int, - domain: Int = 0): Unit = { - pokeClass(dut.io.queries(domain).uopClass, uopClass) - dut.io.queries(domain).bank.poke(bank.U) - dut.io.queries(domain).entry.poke(entry.U) - } - - private def advanceToS3(dut: OooIexIssue): Unit = { - dut.io.s1.ready.expect(true.B) - dut.clock.step() // retained S1 - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.clock.step() // exact S2 bind - dut.io.s3Enable.valid.expect(true.B) - dut.clock.step() // S3 resident/pick-enable - } - - test("keeps S1 S2 and S3 as independent retained stages") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val allocation = Allocation(0, 0, 0, 0, 0, 1) - pokeTransaction(dut, 1, 9, Vector(allocation)) - query(dut, 0, 0, 1) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s1Occupied(1).expect(true.B) - dut.io.s2Bind.valid.expect(true.B) - dut.io.s2Bind.bits.transactionId.expect(9.U) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - dut.clock.step() - dut.io.s1Occupied(1).expect(false.B) - dut.io.s3Enable.valid.expect(true.B) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - dut.io.queryPickable.expect(false.B) - dut.clock.step() - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(true.B) - dut.io.queryRow.member.memberIndex.expect(0.U) - dut.io.queryRow.transactionId.expect(9.U) - dut.io.queryRow.opcode.expect(40.U) - dut.io.queryRow.primaryPrediction.valid.expect(true.B) - dut.io.queryRow.primaryPrediction.predictionTag.expect(20.U) - dut.io.queryRow.parentPcTokens(0).valid.expect(true.B) - dut.io.queryRow.pcParentIndexValid.expect(true.B) - dut.io.queryRow.pcParentIndex.expect(0.U) - dut.io.queryRow.recipe.pcReadRequired.expect(false.B) - dut.io.queryRow.destinations(0).valid.expect(true.B) - dut.io.queryRow.destinations(0).ptag.expect(30.U) - dut.io.queryRow.payload.previousPDestinations(0).valid.expect(true.B) - dut.io.queryRow.payload.previousPDestinations(0).ptag.expect(20.U) - dut.io.queryRow.payload.previousPDestinations(0).ptagGeneration - .expect(3.U) - } - } - - test("projects split stores into disjoint AGU and STD operand rows") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val allocations = Vector( - Allocation(0, 0, 2, 0, 0, 1), - Allocation(0, 1, 3, 0, 1, 2)) - pokeTransaction(dut, 1, 10, allocations) - val decoded = dut.io.s1.bits.o3.request.reservation.transaction.decoded.uops(0) - val transaction = - dut.io.s1.bits.o3.request.reservation.transaction - val pUop = dut.io.s1.bits.pRename.uops(0) - Seq(decoded, pUop.decoded).foreach { logical => - logical.recipe.lateSplitKind.poke(OooLateSplitKind.StoreAddressData.U) - logical.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - logical.recipe.memoryRequestCount.poke(1.U) - logical.memory.valid.poke(true.B) - logical.memory.isStore.poke(true.B) - logical.memory.addressMode.poke(OooMemoryAddressMode.BaseIndex) - logical.memory.accessBytes.poke(8.U) - logical.memory.addressSourceMask.poke("b0110".U) - logical.memory.dataSourceMask.poke("b0001".U) - logical.destinations(0).valid.poke(false.B) - for (sourceIndex <- 0 until 3) { - logical.sources(sourceIndex).valid.poke(true.B) - logical.sources(sourceIndex).operandClass.poke(OperandClass.P) - logical.sources(sourceIndex).atag.poke((8 + sourceIndex).U) - } - } - transaction.plan.demand.storeIds.poke(1.U) - transaction.decoded.demand.storeIds.poke(1.U) - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - dut.io.s1Rejected.bits.shapeExact.expect(false.B) - val memoryOrder = dut.io.s1.bits.memoryOrder - memoryOrder.valid.poke(true.B) - memoryOrder.peId.poke(3.U) - memoryOrder.stid.poke(1.U) - memoryOrder.epoch.poke(6.U) - memoryOrder.transactionId.poke(10.U) - memoryOrder.uopMask.poke(1.U) - memoryOrder.after.lsid.poke(1.U) - memoryOrder.after.storeId.poke(1.U) - memoryOrder.uops(0).valid.poke(true.B) - memoryOrder.uops(0).memoryValid.poke(true.B) - memoryOrder.uops(0).isStore.poke(true.B) - memoryOrder.uops(0).requestCount.poke(1.U) - memoryOrder.uops(0).after.lsid.poke(1.U) - memoryOrder.uops(0).after.storeId.poke(1.U) - memoryOrder.uops(1).before.lsid.poke(1.U) - memoryOrder.uops(1).before.storeId.poke(1.U) - memoryOrder.uops(1).firstLsid.poke(1.U) - memoryOrder.uops(1).after.lsid.poke(1.U) - memoryOrder.uops(1).after.storeId.poke(1.U) - for (sourceIndex <- 0 until 3) { - val renamed = pUop.sources(sourceIndex) - renamed.decoded.valid.poke(true.B) - renamed.decoded.operandClass.poke(OperandClass.P) - renamed.decoded.atag.poke((8 + sourceIndex).U) - renamed.pMapping.valid.poke(true.B) - renamed.pMapping.ptag.poke((40 + sourceIndex).U) - renamed.pMapping.ptagGeneration.poke(3.U) - renamed.pMapping.ready.poke(true.B) - renamed.pMapping.stid.poke(1.U) - renamed.pMapping.epoch.poke(6.U) - } - - advanceToS3(dut) - query(dut, 2, 0, 1) - dut.io.queryRow.sources(0).valid.expect(false.B) - dut.io.queryRow.sources(1).valid.expect(true.B) - dut.io.queryRow.sources(2).valid.expect(true.B) - dut.io.queryRow.destinations(0).valid.expect(false.B) - dut.io.queryRow.memoryOrder.memoryValid.expect(true.B) - dut.io.queryRow.memoryOrder.firstLsid.expect(0.U) - dut.io.queryRow.memoryOrder.firstTypeId.expect(0.U) - query(dut, 3, 0, 2) - dut.io.queryRow.sources(0).valid.expect(true.B) - dut.io.queryRow.sources(1).valid.expect(false.B) - dut.io.queryRow.sources(2).valid.expect(false.B) - dut.io.queryRow.destinations(0).valid.expect(false.B) - dut.io.queryRow.memoryOrder.memoryValid.expect(true.B) - dut.io.queryRow.memoryOrder.firstLsid.expect(0.U) - dut.io.queryRow.memoryOrder.firstTypeId.expect(0.U) - } - } - - test("rejects a split store whose child classes are swapped") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - pokeTransaction(dut, 1, 11, Vector( - Allocation(0, 0, 3, 0, 0, 1), - Allocation(0, 1, 2, 0, 1, 2))) - val decoded = dut.io.s1.bits.o3.request.reservation.transaction.decoded.uops(0) - val pDecoded = dut.io.s1.bits.pRename.uops(0).decoded - Seq(decoded, pDecoded).foreach { logical => - logical.recipe.lateSplitKind.poke(OooLateSplitKind.StoreAddressData.U) - } - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - dut.io.s1Rejected.bits.shapeExact.expect(false.B) - } - } - - test("registers wakeup before it becomes visible to S3 eligibility") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - pokeTransaction(dut, 0, 2, - Vector(Allocation(0, 0, 0, 0, 0, 0)), - pSourceReady = Some(false)) - query(dut, 0, 0, 0) - advanceToS3(dut) - dut.io.queryPickable.expect(false.B) - - val wakeup = dut.io.wakeup(0) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - wakeup.valid.poke(true.B) - dut.io.queryPickable.expect(false.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.io.queryPickable.expect(true.B) - - // A later consumer must observe the generation-qualified ready table - // even though it never overlapped the original one-cycle wakeup pulse. - pokeTransaction(dut, 0, 3, - Vector(Allocation(0, 0, 0, 0, 0, 1)), - pSourceReady = Some(false), pSourceGeneration = 4) - query(dut, 0, 0, 1) - advanceToS3(dut) - dut.io.queryPickable.expect(false.B) - - pokeTransaction(dut, 0, 4, - Vector(Allocation(0, 0, 0, 0, 0, 2)), - pSourceReady = Some(false), pSourceGeneration = 3) - query(dut, 0, 0, 2) - advanceToS3(dut) - dut.io.queryPickable.expect(true.B) - - // Recycling the exact generation must clear the retained ready record - // before that physical tag can be issued again. - dut.io.ptagRecycle.bits.poke( - 0.U.asTypeOf(dut.io.ptagRecycle.bits)) - dut.io.ptagRecycle.bits.count.poke(1.U) - dut.io.ptagRecycle.bits.tokens(0).valid.poke(true.B) - dut.io.ptagRecycle.bits.tokens(0).ptag.poke(17.U) - dut.io.ptagRecycle.bits.tokens(0).generation.poke(3.U) - dut.io.ptagRecycle.valid.poke(true.B) - dut.io.ptagRecycle.ready.expect(true.B) - dut.clock.step() - dut.io.ptagRecycle.valid.poke(false.B) - - pokeTransaction(dut, 0, 7, - Vector(Allocation(0, 0, 0, 0, 0, 3)), - pSourceReady = Some(false), pSourceGeneration = 3) - query(dut, 0, 0, 3) - advanceToS3(dut) - dut.io.queryPickable.expect(false.B) - - // T/U readiness uses the same retained principle but exact local - // sequence identity rather than PTag allocation generation. - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.T) - wakeup.bits.localTag.poke(5.U) - wakeup.bits.localSequence.valid.poke(true.B) - wakeup.bits.localSequence.index.poke(1.U) - wakeup.bits.localSequence.generation.poke(2.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - - pokeTransaction(dut, 0, 5, - Vector(Allocation(0, 0, 0, 1, 0, 0))) - val tRequest = dut.io.s1.bits - val tDecoded = tRequest.o3.request.reservation.transaction.decoded.uops(0) - val tPUop = tRequest.pRename.uops(0) - val tLocalSource = tRequest.tuRename.uops(0).sources(0) - Seq(tDecoded.sources(0), tPUop.decoded.sources(0)).foreach { source => - source.valid.poke(true.B) - source.operandClass.poke(OperandClass.T) - source.relativeIndex.poke(0.U) - } - tLocalSource.valid.poke(true.B) - tLocalSource.kind.poke(DestinationKind.T) - tLocalSource.relativeIndex.poke(0.U) - tLocalSource.physicalTag.poke(5.U) - tLocalSource.stid.poke(0.U) - tLocalSource.epoch.poke(6.U) - tLocalSource.sequence.valid.poke(true.B) - tLocalSource.sequence.index.poke(1.U) - tLocalSource.sequence.generation.poke(2.U) - query(dut, 0, 1, 0) - advanceToS3(dut) - dut.io.queryPickable.expect(true.B) - - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.U) - wakeup.bits.localTag.poke(6.U) - wakeup.bits.localSequence.valid.poke(true.B) - wakeup.bits.localSequence.index.poke(2.U) - wakeup.bits.localSequence.generation.poke(3.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - - pokeTransaction(dut, 0, 6, - Vector(Allocation(0, 0, 0, 1, 0, 1))) - val uRequest = dut.io.s1.bits - val uDecoded = uRequest.o3.request.reservation.transaction.decoded.uops(0) - val uPUop = uRequest.pRename.uops(0) - val uLocalSource = uRequest.tuRename.uops(0).sources(0) - Seq(uDecoded.sources(0), uPUop.decoded.sources(0)).foreach { source => - source.valid.poke(true.B) - source.operandClass.poke(OperandClass.U) - source.relativeIndex.poke(0.U) - } - uLocalSource.valid.poke(true.B) - uLocalSource.kind.poke(DestinationKind.U) - uLocalSource.relativeIndex.poke(0.U) - uLocalSource.physicalTag.poke(6.U) - uLocalSource.stid.poke(0.U) - uLocalSource.epoch.poke(6.U) - uLocalSource.sequence.valid.poke(true.B) - uLocalSource.sequence.index.poke(2.U) - uLocalSource.sequence.generation.poke(3.U) - query(dut, 0, 1, 1) - advanceToS3(dut) - dut.io.queryPickable.expect(true.B) - } - } - - test("captures a producer wakeup on the same edge as consumer S2 bind") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - pokeTransaction(dut, 0, 7, - Vector(Allocation(0, 0, 0, 0, 0, 3)), - pSourceReady = Some(false)) - query(dut, 0, 0, 3) - dut.io.s1.ready.expect(true.B) - dut.clock.step() // retain S1 - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - - val wakeup = dut.io.wakeup(0) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - wakeup.valid.poke(true.B) - dut.clock.step() // bind S2 and capture the same-cycle wakeup - wakeup.valid.poke(false.B) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - dut.io.queryPickable.expect(false.B) - - dut.clock.step() // registered S3 enable - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(true.B) - } - } - - test("keeps speculative load readiness IQ-local and generation-qualified") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - pokeTransaction(dut, 0, 20, - Vector(Allocation(0, 0, 0, 0, 0, 0)), - pSourceReady = Some(false)) - query(dut, 0, 0, 0) - advanceToS3(dut) - dut.io.queryPickable.expect(false.B) - - val wakeup = dut.io.wakeup(0) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.kind.poke(OooIexWakeupKind.SpeculativeLoad) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - wakeup.bits.load.valid.poke(true.B) - pokeMember(wakeup.bits.load.producer, 0, memberIndex = 5, - residentGeneration = 9) - wakeup.bits.load.generation.poke(7.U) - wakeup.valid.poke(true.B) - dut.io.queryPickable.expect(false.B) - dut.clock.step() - wakeup.valid.poke(false.B) - - dut.io.queryRow.sources(0).ready.expect(false.B) - dut.io.queryRow.sources(0).specReady.expect(true.B) - dut.io.queryRow.sources(0).load.valid.expect(true.B) - dut.io.queryRow.sources(0).load.generation.expect(7.U) - dut.io.queryRow.sources(0).load.producer.memberIndex.expect(5.U) - dut.io.queryPickable.expect(true.B) - - val cancel = dut.io.loadCancel(0) - cancel.bits.poke(0.U.asTypeOf(cancel.bits)) - cancel.bits.stid.poke(0.U) - cancel.bits.epoch.poke(6.U) - cancel.bits.load.valid.poke(true.B) - pokeMember(cancel.bits.load.producer, 0, memberIndex = 5, - residentGeneration = 9) - cancel.bits.load.generation.poke(6.U) - cancel.valid.poke(true.B) - dut.clock.step() - cancel.valid.poke(false.B) - dut.io.queryRow.sources(0).specReady.expect(true.B) - dut.io.queryRow.sources(0).load.generation.expect(7.U) - - cancel.bits.load.generation.poke(7.U) - cancel.valid.poke(true.B) - dut.io.queryPickable.expect(false.B) - dut.clock.step() - cancel.valid.poke(false.B) - dut.io.queryRow.sources(0).ready.expect(false.B) - dut.io.queryRow.sources(0).specReady.expect(false.B) - dut.io.queryRow.sources(0).load.valid.expect(false.B) - dut.io.queryPickable.expect(false.B) - - wakeup.bits.load.generation.poke(8.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.io.queryRow.sources(0).specReady.expect(true.B) - dut.io.queryRow.sources(0).load.generation.expect(8.U) - dut.io.queryPickable.expect(true.B) - - // A consumer installed after the pulse must not inherit speculative - // readiness from the non-speculative P ready table. - pokeTransaction(dut, 0, 21, - Vector(Allocation(0, 0, 0, 0, 0, 1)), - pSourceReady = Some(false)) - query(dut, 0, 0, 1) - advanceToS3(dut) - dut.io.queryRow.sources(0).ready.expect(false.B) - dut.io.queryRow.sources(0).specReady.expect(false.B) - dut.io.queryPickable.expect(false.B) - - // A stable wakeup promotes both resident consumers and is the only - // event allowed to populate the global ready table. - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.kind.poke(OooIexWakeupKind.Committed) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.io.queryRow.sources(0).ready.expect(true.B) - dut.io.queryRow.sources(0).specReady.expect(false.B) - dut.io.queryPickable.expect(true.B) - query(dut, 0, 0, 0) - dut.io.queryRow.sources(0).ready.expect(true.B) - dut.io.queryRow.sources(0).specReady.expect(false.B) - dut.io.queryRow.sources(0).load.valid.expect(false.B) - - // The S2 bind edge has an explicit capture path because the ordinary - // resident-row wakeup loop still sees the slot as free on that edge. - pokeTransaction(dut, 0, 22, - Vector(Allocation(0, 0, 0, 0, 0, 2)), - pSourceReady = Some(false), pSourceGeneration = 4) - query(dut, 0, 0, 2) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.kind.poke(OooIexWakeupKind.SpeculativeLoad) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(4.U) - wakeup.bits.load.valid.poke(true.B) - pokeMember(wakeup.bits.load.producer, 0, memberIndex = 6, - residentGeneration = 10) - wakeup.bits.load.generation.poke(8.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - dut.clock.step() - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryRow.sources(0).ready.expect(false.B) - dut.io.queryRow.sources(0).specReady.expect(true.B) - dut.io.queryRow.sources(0).load.generation.expect(8.U) - dut.io.queryPickable.expect(true.B) - } - } - - test("retains independent STID S1 rows and binds them fairly") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - pokeTransaction(dut, 0, 1, - Vector(Allocation(0, 0, 0, 0, 0, 0))) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - - // The first row has not reached S2 yet, but its pending S1 claim must - // already exclude the same physical target for every other STID. - pokeTransaction(dut, 2, 2, - Vector(Allocation(0, 0, 0, 0, 0, 0))) - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - - pokeTransaction(dut, 2, 2, - Vector(Allocation(0, 0, 0, 1, 0, 0))) - dut.io.s1.ready.expect(true.B) - dut.io.s2Bind.valid.expect(true.B) - dut.io.s2Bind.bits.stid.expect(0.U) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.io.s2Bind.bits.stid.expect(2.U) - dut.clock.step() - dut.io.s1Occupied(0).expect(false.B) - dut.io.s1Occupied(2).expect(false.B) - } - } - - test("releases resident state and dispatch ownership on one exact fire") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val allocation = Allocation(0, 0, 0, 1, 1, 2, reservationEpoch = 3) - pokeTransaction(dut, 3, 11, Vector(allocation)) - query(dut, 0, 1, 2) - advanceToS3(dut) - - dut.io.pickBankEnable(OooDispatchClass.Alu - 1).poke("b10".U) - dut.clock.step() - dut.io.pick.valid.expect(true.B) - dut.io.pick.bits.query.bank.expect(1.U) - dut.io.pick.bits.query.entry.expect(2.U) - - val retry = dut.io.pickRetry.bits - retry.poke(0.U.asTypeOf(retry)) - pokeMember(retry.member, 3, memberIndex = 0) - retry.reservation.valid.poke(true.B) - retry.reservation.uopClass.poke(OooUopClass.Alu) - retry.reservation.bank.poke(1.U) - retry.reservation.writePort.poke(1.U) - retry.reservation.speculativeSlot.poke(2.U) - retry.reservation.reservationEpoch.poke(3.U) - - // A bridge/P1 shape failure returns the exact token on the claim edge. - // The claim and retry must collapse to a resident, pickable row. - dut.io.pick.ready.poke(true.B) - dut.io.pickRetry.valid.poke(true.B) - dut.io.pickRetryRejected.valid.expect(false.B) - dut.clock.step() - dut.io.pick.ready.poke(false.B) - dut.io.pickRetry.valid.poke(false.B) - dut.io.inFlightEntries(0)(1).expect(0.U) - dut.io.queryPickable.expect(true.B) - - dut.clock.step() - dut.io.pick.valid.expect(true.B) - dut.io.pick.ready.poke(true.B) - dut.clock.step() - dut.io.pick.ready.poke(false.B) - dut.io.inFlightEntries(0)(1).expect(1.U) - dut.io.queryPickable.expect(false.B) - - dut.io.pickRetry.valid.poke(true.B) - dut.io.pickRetryRejected.valid.expect(false.B) - dut.clock.step() - dut.io.pickRetry.valid.poke(false.B) - dut.io.inFlightEntries(0)(1).expect(0.U) - dut.io.queryPickable.expect(true.B) - - dut.clock.step() - dut.io.pick.valid.expect(true.B) - dut.io.pick.ready.poke(true.B) - dut.clock.step() - dut.io.pick.ready.poke(false.B) - dut.io.inFlightEntries(0)(1).expect(1.U) - - val release = dut.io.release.bits - release.poke(0.U.asTypeOf(release)) - pokeMember(release.member, 3, memberIndex = 0) - pokeMember(release.dispatch.member, 3, memberIndex = 0) - release.dispatch.peId.poke(3.U) - release.dispatch.stid.poke(3.U) - release.dispatch.epoch.poke(6.U) - release.dispatch.transactionId.poke(11.U) - release.dispatch.reservation.valid.poke(true.B) - release.dispatch.reservation.uopClass.poke(OooUopClass.Alu) - release.dispatch.reservation.bank.poke(1.U) - release.dispatch.reservation.writePort.poke(1.U) - release.dispatch.reservation.speculativeSlot.poke(2.U) - release.dispatch.reservation.reservationEpoch.poke(4.U) - dut.io.release.valid.poke(true.B) - dut.io.release.ready.expect(false.B) - dut.io.releaseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - - release.dispatch.reservation.reservationEpoch.poke(3.U) - dut.io.dispatchRelease.ready.poke(false.B) - dut.io.releaseRejected.valid.expect(false.B) - dut.io.release.ready.expect(false.B) - dut.io.dispatchRelease.valid.expect(true.B) - dut.clock.step() - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - - dut.io.dispatchRelease.ready.poke(true.B) - dut.io.release.ready.expect(true.B) - dut.clock.step() - dut.io.release.valid.poke(false.B) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - } - } - - test("policy blocks a resident row and invalidates a newly held pick token") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val allocation = Allocation(0, 0, 0, 0, 0, 1) - pokeTransaction(dut, 1, 17, Vector(allocation)) - query(dut, 0, 0, 1) - advanceToS3(dut) - - dut.io.pickBankEnable(OooDispatchClass.Alu - 1).poke(1.U) - dut.clock.step() - dut.io.pick.valid.expect(true.B) - - dut.io.issuePolicy.classPressure(0).poke("b0010".U) - val classPressure = 1 << OooIexIssueBlockReason.ClassPressure - dut.io.pick.valid.expect(false.B) - dut.io.pickPolicyBlocked.valid.expect(true.B) - dut.io.pickPolicyBlocked.bits.reasonMask.expect(classPressure.U) - dut.io.pickPolicyBlocked.bits.token.candidate.stid.expect(1.U) - dut.io.queryPolicyReason.expect(classPressure.U) - dut.io.queryPickable.expect(false.B) - dut.io.policyBlockedCount(0).expect(1.U) - dut.clock.step() - - // The policy event consumes only the stale held picker token. The IQ - // row never became in-flight and is selected again after unblock. - dut.io.pickPolicyBlocked.valid.expect(false.B) - dut.io.inFlightEntries(0)(0).expect(0.U) - dut.io.issuePolicy.classPressure(0).poke(0.U) - dut.io.queryPickable.expect(true.B) - dut.clock.step() - dut.io.pick.valid.expect(true.B) - dut.io.pick.ready.poke(true.B) - dut.clock.step() - dut.io.pick.ready.poke(false.B) - dut.io.inFlightEntries(0)(0).expect(1.U) - } - } - - test("multi-release frees independent rows and blocks duplicate targets") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iexIssueDomainCount = 2, - iexReleaseWidth = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val allocations = Vector( - Allocation(0, 0, 0, 0, 0, 1, reservationEpoch = 3), - Allocation(1, 0, 1, 0, 1, 2, reservationEpoch = 4)) - pokeTransaction(dut, 1, 21, allocations) - advanceToS3(dut) - - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Bru - 1).poke(1.U) - dut.clock.step() - dut.io.picks.foreach(_.valid.expect(true.B)) - dut.io.picks.foreach(_.ready.poke(true.B)) - dut.clock.step() - dut.io.picks.foreach(_.ready.poke(false.B)) - - def pokeRelease( - lane: Int, - allocation: Allocation, - memberIndex: Int): Unit = { - val release = dut.io.releases(lane).bits - release.poke(0.U.asTypeOf(release)) - pokeMember(release.member, 1, memberIndex) - pokeMember(release.dispatch.member, 1, memberIndex) - release.dispatch.peId.poke(3.U) - release.dispatch.stid.poke(1.U) - release.dispatch.epoch.poke(6.U) - release.dispatch.transactionId.poke(21.U) - release.dispatch.reservation.valid.poke(true.B) - pokeClass(release.dispatch.reservation.uopClass, - allocation.uopClass) - release.dispatch.reservation.bank.poke(allocation.bank.U) - release.dispatch.reservation.writePort.poke(allocation.port.U) - release.dispatch.reservation.speculativeSlot.poke(allocation.entry.U) - release.dispatch.reservation.reservationEpoch.poke( - allocation.reservationEpoch.U) - dut.io.releases(lane).valid.poke(true.B) - } - - pokeRelease(0, allocations(0), memberIndex = 0) - pokeRelease(1, allocations(1), memberIndex = 2) - dut.io.dispatchReleases.foreach(_.ready.poke(true.B)) - dut.io.releases.foreach(_.ready.expect(true.B)) - dut.clock.step() - dut.io.releases.foreach(_.valid.poke(false.B)) - dut.io.residentEntries(0)(0).expect(0.U) - dut.io.residentEntries(1)(0).expect(0.U) - - val duplicate = Allocation(0, 0, 0, 0, 0, 3, - reservationEpoch = 5) - pokeTransaction(dut, 1, 22, Vector(duplicate)) - advanceToS3(dut) - dut.io.pickBankEnables(0)(OooDispatchClass.Alu - 1).poke(1.U) - dut.clock.step() - dut.io.picks(0).valid.expect(true.B) - dut.io.picks(0).ready.poke(true.B) - dut.clock.step() - dut.io.picks(0).ready.poke(false.B) - - pokeRelease(0, duplicate, memberIndex = 0) - pokeRelease(1, duplicate, memberIndex = 0) - dut.io.releases.foreach(_.bits.dispatch.transactionId.poke(22.U)) - dut.io.releases.foreach(_.ready.expect(false.B)) - dut.io.releaseRejecteds.foreach(_.valid.expect(true.B)) - dut.clock.step() - dut.io.releases.foreach(_.valid.poke(false.B)) - dut.io.residentEntries(0)(0).expect(1.U) - dut.io.inFlightEntries(0)(0).expect(1.U) - } - } - - test("rejects duplicate physical targets and binds a split bundle atomically") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 4, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val first = Allocation(0, 0, 2, 0, 0, 1) - pokeTransaction(dut, 1, 4, - Vector(first, first.copy(childIndex = 1, port = 1))) - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.residentEntries(2)(0).expect(0.U) - - pokeTransaction(dut, 1, 5, - Vector(first, first.copy(childIndex = 1, port = 1, entry = 2))) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.io.s2Bind.bits.allocationMask.expect("b0011".U) - dut.clock.step(2) - dut.io.residentEntries(2)(0).expect(2.U) - query(dut, 2, 0, 1) - dut.io.queryRow.member.memberIndex.expect(0.U) - query(dut, 2, 0, 2) - dut.io.queryRow.member.memberIndex.expect(1.U) - } - } - - test("keeps younger same-STID stores behind the cross-bank logical frontier") { - val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 2, - iexIssueDomainCount = 2, - iexReleaseWidth = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16, - lsidWidth = 40) - simulate(new OooIexIssue(p)) { dut => - clear(dut) - val older = Vector( - Allocation(0, 0, 2, 0, 0, 0, reservationEpoch = 3), - Allocation(0, 1, 3, 0, 1, 0, reservationEpoch = 4)) - val younger = Vector( - Allocation(0, 0, 2, 0, 0, 1, reservationEpoch = 5), - Allocation(0, 1, 3, 0, 1, 1, reservationEpoch = 6)) - - pokeStoreTransaction(dut, stid = 0, transactionId = 30, - ridSlot = 1, memberBase = 0, firstLsid = 20, - firstStoreId = 10, allocations = older) - advanceToS3(dut) - pokeStoreTransaction(dut, stid = 0, transactionId = 31, - ridSlot = 2, memberBase = 0, firstLsid = 23, - firstStoreId = 11, allocations = younger) - advanceToS3(dut) - - query(dut, uopClass = 2, bank = 0, entry = 0) - dut.io.queryPickable.expect(true.B) - dut.io.queryRow.storeOrder.firstStoreId.expect(10.U) - query(dut, uopClass = 3, bank = 0, entry = 0) - dut.io.queryPickable.expect(true.B) - query(dut, uopClass = 2, bank = 0, entry = 1) - dut.io.queryPickable.expect(false.B) - query(dut, uopClass = 3, bank = 0, entry = 1) - dut.io.queryPickable.expect(false.B) - dut.io.storeFrontierBlocked(0).expect(2.U) - dut.io.storeFrontierBlocked(1).expect(0.U) - - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooDispatchClass.Agu - 1).poke(1.U) - dut.io.pickBankEnables(1)(OooDispatchClass.Std - 1).poke(1.U) - dut.clock.step() - dut.io.picks(0).valid.expect(true.B) - dut.io.picks(0).bits.query.entry.expect(0.U) - dut.io.picks(1).valid.expect(true.B) - dut.io.picks(1).bits.query.entry.expect(0.U) - dut.io.picks.foreach(_.ready.poke(true.B)) - dut.clock.step() - dut.io.picks.foreach(_.ready.poke(false.B)) - - def pokeRelease( - lane: Int, - allocation: Allocation, - childIndex: Int): Unit = { - val release = dut.io.releases(lane).bits - release.poke(0.U.asTypeOf(release)) - pokeMember(release.member, stid = 0, memberIndex = childIndex, - ridSlot = 1) - pokeMember(release.dispatch.member, stid = 0, - memberIndex = childIndex, ridSlot = 1) - release.dispatch.peId.poke(3.U) - release.dispatch.stid.poke(0.U) - release.dispatch.epoch.poke(6.U) - release.dispatch.transactionId.poke(30.U) - release.dispatch.reservation.valid.poke(true.B) - pokeClass(release.dispatch.reservation.uopClass, - allocation.uopClass) - release.dispatch.reservation.bank.poke(allocation.bank.U) - release.dispatch.reservation.writePort.poke(allocation.port.U) - release.dispatch.reservation.speculativeSlot.poke(allocation.entry.U) - release.dispatch.reservation.reservationEpoch.poke( - allocation.reservationEpoch.U) - dut.io.releases(lane).valid.poke(true.B) - dut.io.dispatchReleases(lane).ready.poke(true.B) - } - - // Releasing only STA is insufficient: the resident STD child still - // represents the older logical store across both physical IQ classes. - pokeRelease(0, older(0), childIndex = 0) - dut.io.releases(0).ready.expect(true.B) - dut.clock.step() - dut.io.releases(0).valid.poke(false.B) - query(dut, uopClass = 2, bank = 0, entry = 1) - dut.io.queryPickable.expect(false.B) - dut.io.storeFrontierBlocked(0).expect(2.U) - - pokeRelease(0, older(1), childIndex = 1) - dut.io.releases(0).ready.expect(true.B) - dut.clock.step() - dut.io.releases(0).valid.poke(false.B) - query(dut, uopClass = 2, bank = 0, entry = 1) - dut.io.queryPickable.expect(true.B) - query(dut, uopClass = 3, bank = 0, entry = 1, domain = 1) - dut.io.queryPickables(1).expect(true.B) - dut.io.storeFrontierBlocked(0).expect(0.U) - } - } - - test("elaborates the IEX residency boundary at instruction widths 2 4 and 6") { - Seq(2, 4, 6).foreach { width => - val p = OooParams( - instructionDecodeWidth = width, - decodedUopWidth = width, - dispatchWidth = width * 2, - robGroupsPerStid = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pTagStagingDepthPerBank = 8, - pMapQDepthPerStid = 16, - tuMapQDepthPerStid = 16, - tuRetireSourceDepthPerStid = 64) - val sv = ChiselStage.emitSystemVerilog(new OooIexIssue(p)) - assert(sv.contains("module OooIexIssue")) - } - } - - test("holds a store in retained S1 until canonical STQ reservation fires") { - val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16, - lsidWidth = 40) - simulate(new OooIexIssue(p, requireStoreReservation = true)) { dut => - clear(dut) - dut.io.storeReserve.ready.poke(false.B) - val allocations = Vector( - Allocation(0, 0, 2, 0, 0, 0), - Allocation(0, 1, 3, 0, 1, 0)) - pokeStoreTransaction(dut, stid = 1, transactionId = 91, - ridSlot = 5, memberBase = 0, - firstLsid = BigInt("100000001", 16), - firstStoreId = BigInt("200000001", 16), - allocations = allocations) - val decoded = dut.io.s1.bits.o3.request.reservation.transaction - .decoded.uops(0) - val pDecoded = dut.io.s1.bits.pRename.uops(0).decoded - Seq(decoded, pDecoded).foreach(_.recipe.sideEffectOwner - .poke(OooSideEffectOwner.None.U)) - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - dut.io.s1Rejected.bits.shapeExact.expect(false.B) - Seq(decoded, pDecoded).foreach(_.recipe.sideEffectOwner - .poke(OooSideEffectOwner.Lsu.U)) - Seq(decoded, pDecoded).foreach(_.recipe.recipeKind - .poke(OooOpcodeRecipeKind.PairStore.U)) - dut.io.s1.ready.expect(false.B) - dut.io.s1Rejected.valid.expect(true.B) - Seq(decoded, pDecoded).foreach(_.recipe.recipeKind - .poke(OooOpcodeRecipeKind.ScalarStore.U)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - - def pokePartialStoreRecovery(): Unit = { - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(5.U) - plan.oldHead.ridGeneration.poke(2.U) - plan.oldOccupied.poke(1.U) - plan.newOccupied.poke(1.U) - plan.pivotOffset.poke(0.U) - pokeMember(plan.pivot, stid = 1, memberIndex = 0, ridSlot = 5) - plan.pivotPhysicalMemberCount.poke(2.U) - plan.survivingPivotValid.poke(true.B) - plan.survivingPivotPhysicalMemberCount.poke(1.U) - dut.io.recoveryPrepare.valid.poke(true.B) - } - - pokePartialStoreRecovery() - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryRejected.bits.s1RowsExact.expect(false.B) - dut.io.storeReserve.valid.expect(false.B) - dut.io.s2Bind.valid.expect(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - - dut.io.storeReserve.valid.expect(true.B) - dut.io.storeReserve.bits.schedule.childIndex.expect(0.U) - dut.io.storeReserve.bits.schedule.member.memberIndex.expect(0.U) - dut.io.storeReserve.bits.payload.memoryOrder.firstLsid.expect( - BigInt("100000001", 16).U) - dut.io.s2Bind.valid.expect(false.B) - dut.clock.step(2) - dut.io.storeReserve.valid.expect(true.B) - dut.io.s2Bind.valid.expect(false.B) - - dut.io.storeReserve.ready.poke(true.B) - dut.clock.step() - dut.io.storeReserve.valid.expect(false.B) - pokePartialStoreRecovery() - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryRejected.bits.s1RowsExact.expect(false.B) - dut.io.s2Bind.valid.expect(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.clock.step() - dut.io.s3Enable.valid.expect(true.B) - dut.clock.step() - - pokePartialStoreRecovery() - var recoveryCycles = 0 - while (!dut.io.recoveryRejected.valid.peek().litToBoolean && - recoveryCycles < p.iexRecoveryScanCycles + 2) { - dut.clock.step() - recoveryCycles += 1 - } - assert(dut.io.recoveryRejected.valid.peek().litToBoolean, - "resident split-store partial recovery was not rejected") - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - } +/** Structural contract retained beside the behavior-focused private ingress + * suite. Picker/retry/release behavior remains covered through the composed + * IEX mechanism suites. + */ +class OooIexIssueSpec extends AnyFunSuite { + test("canonical IQ ingress exposes only classed dispatch and recovery") { + val io = new OooIexIssueIO(ParamProfiles.W4) + assert(io.dispatch.aluDispatch.length == 2) + assert(io.dispatch.bruDispatch.length == 1) + assert(io.dispatch.aguDispatch.length == 2) + assert(io.dispatch.storeDispatch.length == 2) + assert(io.dispatch.systemDispatch.length == 1) + assert(io.dispatch.cmdDispatch.length == 1) + assert(io.dispatch.aluDispatch.head.bits.isInstanceOf[DispatchTxn]) + assert(io.dispatch.storeDispatch.head.bits.isInstanceOf[StoreDispatchTxn]) + assert(!io.elements.contains("s1")) + assert(!io.elements.contains("dispatchReleases")) + assert(!io.elements.contains("ptagRecycle")) } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexLoadLiqAllocAdapterSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexLoadLiqAllocAdapterSpec.scala deleted file mode 100644 index f3c24f9f..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexLoadLiqAllocAdapterSpec.scala +++ /dev/null @@ -1,291 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -import linxcore.common.{CoreParams, DestinationKind, ScalarLsuParams} - -class OooIexLoadLiqAllocAdapterSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 4, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - brobEntriesPerStid = 16, - pcBufferEntries = 16, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - tuRetireSourceDepthPerStid = 16, - lsidWidth = 40) - - private val core = CoreParams( - robEntries = 8, - lsidWidth = 40, - scalarLsu = ScalarLsuParams( - stqEntries = 4, - liqEntries = 4, - loadReturnPipeCount = 3, - stidCount = 4)) - - private def clear(dut: OooIexLoadLiqAllocAdapter): Unit = { - dut.io.agu.foreach { lane => - lane.valid.poke(false.B) - lane.bits.poke(0.U.asTypeOf(lane.bits)) - } - dut.io.alloc.ready.poke(false.B) - dut.io.recoveryApply.valid.poke(false.B) - dut.io.recoveryApply.bits.poke( - 0.U.asTypeOf(dut.io.recoveryApply.bits)) - dut.io.flush.poke(false.B) - } - - private def pokeRequest( - dut: OooIexLoadLiqAllocAdapter, - lane: Int, - ridSlot: Int, - nativeBid: Int, - firstLsid: BigInt, - firstLoadId: BigInt, - storeTail: BigInt, - pcValid: Boolean = true): Unit = { - val input = dut.io.agu(lane) - val youngestStoreLsid = if (storeTail != 0) firstLsid - 3 else BigInt(0) - input.bits.poke(0.U.asTypeOf(input.bits)) - input.valid.poke(true.B) - input.bits.pcValid.poke(pcValid.B) - input.bits.pc.poke((0x4000 + ridSlot * 4).U) - input.bits.address.poke((0x8000 + ridSlot * 8).U) - input.bits.accessBytes.poke(8.U) - input.bits.signExtend.poke(true.B) - - val execute = input.bits.execute - execute.ownerClass.poke(OooUopClass.Agu) - val row = execute.i2.row - row.schedule.valid.poke(true.B) - row.schedule.peId.poke(3.U) - row.schedule.stid.poke((lane + 1).U) - row.schedule.epoch.poke(7.U) - row.schedule.member.group.valid.poke(true.B) - row.schedule.member.group.peId.poke(3.U) - row.schedule.member.group.stid.poke((lane + 1).U) - row.schedule.member.group.ridSlot.poke(ridSlot.U) - row.schedule.member.group.ridGeneration.poke(5.U) - row.schedule.member.bid.valid.poke(true.B) - row.schedule.member.bid.value.poke(nativeBid.U) - row.schedule.member.brobGeneration.poke(9.U) - row.schedule.member.memberIndex.poke(1.U) - row.schedule.member.residentGeneration.poke(11.U) - row.schedule.reservation.valid.poke(true.B) - row.schedule.reservation.uopClass.poke(OooUopClass.Agu) - - row.payload.opcode.poke(101.U) - row.payload.recipe.valid.poke(true.B) - row.payload.recipe.opcode.poke(101.U) - row.payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - row.payload.recipe.recipeKind.poke(OooOpcodeRecipeKind.ScalarLoad.U) - row.payload.recipe.dispatchClass.poke(OooDispatchClass.Agu.U) - row.payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - row.payload.recipe.memoryRequestCount.poke(1.U) - row.payload.memory.valid.poke(true.B) - row.payload.memory.isLoad.poke(true.B) - row.payload.memory.isStore.poke(false.B) - row.payload.memoryOrder.valid.poke(true.B) - row.payload.memoryOrder.memoryValid.poke(true.B) - row.payload.memoryOrder.isLoad.poke(true.B) - row.payload.memoryOrder.isStore.poke(false.B) - row.payload.memoryOrder.requestCount.poke(1.U) - row.payload.memoryOrder.firstLsid.poke(firstLsid.U) - row.payload.memoryOrder.firstTypeId.poke(firstLoadId.U) - row.payload.memoryOrder.before.lsid.poke(firstLsid.U) - row.payload.memoryOrder.before.loadId.poke(firstLoadId.U) - row.payload.memoryOrder.before.storeId.poke(storeTail.U) - row.payload.memoryOrder.before.youngestStoreLsidValid - .poke((storeTail != 0).B) - row.payload.memoryOrder.before.youngestStoreLsid - .poke(youngestStoreLsid.U) - row.payload.memoryOrder.after.lsid.poke((firstLsid + 1).U) - row.payload.memoryOrder.after.loadId.poke((firstLoadId + 1).U) - row.payload.memoryOrder.after.storeId.poke(storeTail.U) - row.payload.memoryOrder.after.youngestStoreLsidValid - .poke((storeTail != 0).B) - row.payload.memoryOrder.after.youngestStoreLsid - .poke(youngestStoreLsid.U) - - row.schedule.destinations(0).valid.poke(true.B) - row.schedule.destinations(0).kind.poke(DestinationKind.Gpr) - row.schedule.destinations(0).atag.poke(6.U) - row.schedule.destinations(0).ptag.poke((31 + lane).U) - row.schedule.destinations(0).ptagGeneration.poke(4.U) - row.payload.previousPDestinations(0).valid.poke(true.B) - row.payload.previousPDestinations(0).ptag.poke((21 + lane).U) - row.payload.previousPDestinations(0).ptagGeneration.poke(3.U) - input.bits.destination.valid.poke(true.B) - input.bits.destination.kind.poke(DestinationKind.Gpr) - input.bits.destination.atag.poke(6.U) - input.bits.destination.ptag.poke((31 + lane).U) - input.bits.destination.ptagGeneration.poke(4.U) - } - - test("maps the exact OOO producer and 40-bit memory order into one LIQ alloc") { - simulate(new OooIexLoadLiqAllocAdapter(p, core)) { dut => - clear(dut) - val lsid = BigInt("100000001", 16) - pokeRequest(dut, lane = 2, ridSlot = 6, nativeBid = 13, - firstLsid = lsid, firstLoadId = 9, storeTail = 4) - - dut.io.alloc.valid.expect(true.B) - dut.io.agu(2).ready.expect(false.B) - dut.io.accepted.valid.expect(false.B) - dut.io.alloc.bits.attempt.producer.nativeBid.expect(13.U) - dut.io.alloc.bits.attempt.producer.ridSlot.expect(6.U) - dut.io.alloc.bits.attempt.producer.ridGeneration.expect(5.U) - dut.io.alloc.bits.attempt.producer.memberIndex.expect(1.U) - dut.io.alloc.bits.attempt.producer.residentGeneration.expect(11.U) - dut.io.alloc.bits.attempt.generation.expect(1.U) - dut.io.alloc.bits.bid.valid.expect(true.B) - dut.io.alloc.bits.bid.value.expect(5.U) - dut.io.alloc.bits.bid.wrap.expect(true.B) - dut.io.alloc.bits.gid.valid.expect(true.B) - dut.io.alloc.bits.gid.value.expect(6.U) - dut.io.alloc.bits.gid.wrap.expect(true.B) - dut.io.alloc.bits.rid.valid.expect(true.B) - dut.io.alloc.bits.rid.value.expect(6.U) - dut.io.alloc.bits.rid.wrap.expect(true.B) - dut.io.alloc.bits.loadLsId.valid.expect(true.B) - dut.io.alloc.bits.loadLsId.value.expect(1.U) - dut.io.alloc.bits.loadLsId.wrap.expect(false.B) - dut.io.alloc.bits.loadLsIdFull.expect(lsid.U) - dut.io.alloc.bits.loadLsIdFullValid.expect(true.B) - dut.io.alloc.bits.youngestStoreId.valid.expect(true.B) - dut.io.alloc.bits.youngestStoreId.value.expect(3.U) - dut.io.alloc.bits.youngestStoreId.wrap.expect(false.B) - dut.io.alloc.bits.youngestStoreLsId.valid.expect(true.B) - dut.io.alloc.bits.youngestStoreLsId.value.expect(6.U) - dut.io.alloc.bits.youngestStoreLsId.wrap.expect(true.B) - dut.io.alloc.bits.youngestStoreLsIdFull.expect((lsid - 3).U) - dut.io.alloc.bits.youngestStoreLsIdFullValid.expect(true.B) - dut.io.alloc.bits.pc.expect((0x4000 + 6 * 4).U) - dut.io.alloc.bits.addr.expect((0x8000 + 6 * 8).U) - dut.io.alloc.bits.returnPipeIndex.expect(2.U) - dut.io.alloc.bits.dst.physTag.expect(33.U) - dut.io.alloc.bits.dst.oldPhysTag.expect(23.U) - dut.io.alloc.bits.specWakeup.expect(false.B) - - dut.io.alloc.ready.poke(true.B) - dut.io.agu(2).ready.expect(true.B) - dut.io.accepted.valid.expect(true.B) - dut.io.accepted.bits.lane.expect(2.U) - dut.io.accepted.bits.load.generation.expect(1.U) - dut.clock.step() - - dut.io.agu(2).valid.poke(false.B) - pokeRequest(dut, lane = 2, ridSlot = 7, nativeBid = 14, - firstLsid = lsid + 1, firstLoadId = 10, storeTail = 4) - dut.io.alloc.bits.attempt.generation.expect(2.U) - } - } - - test("arbitrates three retained AGUs fairly without adding residency") { - simulate(new OooIexLoadLiqAllocAdapter(p, core)) { dut => - clear(dut) - for (lane <- 0 until 3) { - pokeRequest(dut, lane, ridSlot = lane + 1, nativeBid = lane + 3, - firstLsid = 20 + lane, firstLoadId = 10 + lane, storeTail = 0) - } - dut.io.alloc.ready.poke(true.B) - - for (expected <- 0 until 3) { - dut.io.accepted.valid.expect(true.B) - dut.io.accepted.bits.lane.expect(expected.U) - dut.io.alloc.bits.returnPipeIndex.expect(expected.U) - dut.clock.step() - dut.io.agu(expected).valid.poke(false.B) - } - dut.io.alloc.valid.expect(false.B) - } - } - - test("fails closed for missing PC and destructively drains recovery kills") { - simulate(new OooIexLoadLiqAllocAdapter(p, core)) { dut => - clear(dut) - pokeRequest(dut, lane = 0, ridSlot = 1, nativeBid = 2, - firstLsid = 1, firstLoadId = 1, storeTail = 0, pcValid = false) - dut.io.alloc.ready.poke(true.B) - dut.io.alloc.valid.expect(false.B) - dut.io.agu(0).ready.expect(false.B) - dut.io.rejected(0).valid.expect(true.B) - dut.io.rejected(0).bits.pcExact.expect(false.B) - - dut.io.agu(0).bits.pcValid.poke(true.B) - dut.io.flush.poke(true.B) - dut.io.alloc.valid.expect(false.B) - dut.io.agu(0).ready.expect(true.B) - dut.io.rejected(0).bits.flushed.expect(true.B) - dut.clock.step() - - // The producer observed ready during flush, so the old request is gone. - dut.io.agu(0).valid.poke(false.B) - dut.io.flush.poke(false.B) - dut.io.alloc.valid.expect(false.B) - - // A fresh request receives the first generation; the dropped request did - // not consume allocation identity. - pokeRequest(dut, lane = 0, ridSlot = 1, nativeBid = 2, - firstLsid = 1, firstLoadId = 1, storeTail = 0) - dut.io.alloc.valid.expect(true.B) - dut.io.alloc.bits.attempt.generation.expect(1.U) - dut.clock.step() - - dut.io.agu(0).valid.poke(false.B) - pokeRequest(dut, lane = 0, ridSlot = 2, nativeBid = 3, - firstLsid = 2, firstLoadId = 2, storeTail = 0) - dut.io.alloc.bits.attempt.generation.expect(2.U) - } - } - - test("destructively drains an exact killed member without allocating it") { - simulate(new OooIexLoadLiqAllocAdapter(p, core)) { dut => - clear(dut) - pokeRequest(dut, lane = 1, ridSlot = 2, nativeBid = 4, - firstLsid = 9, firstLoadId = 3, storeTail = 0) - dut.io.alloc.ready.poke(true.B) - - val plan = dut.io.recoveryApply.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(2.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(5.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(2.U) - dut.io.recoveryApply.valid.poke(true.B) - - dut.io.alloc.valid.expect(false.B) - dut.io.agu(1).ready.expect(true.B) - dut.io.rejected(1).valid.expect(true.B) - dut.io.rejected(1).bits.killed.expect(true.B) - dut.clock.step() - - dut.io.agu(1).valid.poke(false.B) - dut.io.recoveryApply.valid.poke(false.B) - dut.io.alloc.valid.expect(false.B) - - pokeRequest(dut, lane = 1, ridSlot = 3, nativeBid = 5, - firstLsid = 10, firstLoadId = 4, storeTail = 0) - dut.io.alloc.bits.attempt.generation.expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexLoadTerminalMetadataSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexLoadTerminalMetadataSpec.scala deleted file mode 100644 index 0ef08fb5..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexLoadTerminalMetadataSpec.scala +++ /dev/null @@ -1,307 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -import linxcore.common.{CoreParams, DestinationKind, ScalarLsuParams} - -class OooIexLoadTerminalMetadataSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 4, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - brobEntriesPerStid = 16, - pcBufferEntries = 16, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - tuRetireSourceDepthPerStid = 16, - lsidWidth = 40) - - private val core = CoreParams( - robEntries = 8, - lsidWidth = 40, - scalarLsu = ScalarLsuParams( - stqEntries = 4, - liqEntries = 4, - loadReturnPipeCount = 3, - stidCount = 4)) - - private def defaults(dut: OooIexLoadTerminalMetadata): Unit = { - dut.io.flush.poke(false.B) - dut.io.alloc.valid.poke(false.B) - dut.io.alloc.bits.poke(0.U.asTypeOf(dut.io.alloc.bits)) - dut.io.rebind.valid.poke(false.B) - dut.io.rebind.bits.poke(0.U.asTypeOf(dut.io.rebind.bits)) - dut.io.completion.valid.poke(false.B) - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - dut.io.result.ready.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - } - - private def pokeMember( - member: RobMemberKey, - ridSlot: Int, - memberIndex: Int = 1, - stid: Int = 1): Unit = { - member.poke(0.U.asTypeOf(member)) - member.group.valid.poke(true.B) - member.group.peId.poke(3.U) - member.group.stid.poke(stid.U) - member.group.ridSlot.poke(ridSlot.U) - member.group.ridGeneration.poke(5.U) - member.bid.valid.poke(true.B) - member.bid.value.poke((ridSlot + 4).U) - member.brobGeneration.poke(9.U) - member.memberIndex.poke(memberIndex.U) - member.residentGeneration.poke(11.U) - } - - private def pokeAttemptFromLoad( - attempt: linxcore.lsu.LoadAttemptIdentity, - load: OooIexLoadGeneration): Unit = { - attempt.poke(0.U.asTypeOf(attempt)) - attempt.valid.poke(true.B) - attempt.producer.valid.poke(true.B) - attempt.producer.peId.poke(load.producer.group.peId.peek()) - attempt.producer.stid.poke(load.producer.group.stid.peek()) - attempt.producer.nativeBidValid.poke(true.B) - attempt.producer.nativeBid.poke(load.producer.bid.value.peek()) - attempt.producer.brobGeneration.poke( - load.producer.brobGeneration.peek()) - attempt.producer.ridSlot.poke(load.producer.group.ridSlot.peek()) - attempt.producer.ridGeneration.poke( - load.producer.group.ridGeneration.peek()) - attempt.producer.memberIndex.poke(load.producer.memberIndex.peek()) - attempt.producer.residentGeneration.poke( - load.producer.residentGeneration.peek()) - attempt.generation.poke(load.generation.peek()) - } - - private def pokeAlloc( - dut: OooIexLoadTerminalMetadata, - slot: Int, - rowGeneration: Int, - ridSlot: Int, - attemptGeneration: Int, - stid: Int = 1): Unit = { - val alloc = dut.io.alloc.bits - alloc.poke(0.U.asTypeOf(alloc)) - alloc.loadId.valid.poke(true.B) - alloc.loadId.slot.poke(slot.U) - alloc.loadId.generation.poke(rowGeneration.U) - alloc.load.valid.poke(true.B) - pokeMember(alloc.load.producer, ridSlot, stid = stid) - alloc.load.generation.poke(attemptGeneration.U) - - val row = alloc.request.execute.i2.row - row.schedule.valid.poke(true.B) - row.schedule.peId.poke(3.U) - row.schedule.stid.poke(stid.U) - row.schedule.epoch.poke(7.U) - pokeMember(row.schedule.member, ridSlot, stid = stid) - row.schedule.destinations(0).valid.poke(true.B) - row.schedule.destinations(0).kind.poke(DestinationKind.Gpr) - row.schedule.destinations(0).atag.poke(6.U) - row.schedule.destinations(0).ptag.poke((31 + slot).U) - row.schedule.destinations(0).ptagGeneration.poke(4.U) - row.payload.previousPDestinations(0).valid.poke(true.B) - row.payload.previousPDestinations(0).ptag.poke((21 + slot).U) - row.payload.previousPDestinations(0).ptagGeneration.poke(3.U) - alloc.request.destination.poke(row.schedule.destinations(0).peek()) - alloc.request.address.poke((0x8000 + slot * 8).U) - alloc.request.accessBytes.poke(8.U) - pokeAttemptFromLoad(alloc.attempt, alloc.load) - dut.io.alloc.valid.poke(true.B) - } - - private def acceptAlloc(dut: OooIexLoadTerminalMetadata): Unit = { - dut.io.alloc.ready.expect(true.B) - dut.clock.step() - dut.io.alloc.valid.poke(false.B) - } - - private def pokeCompletion( - dut: OooIexLoadTerminalMetadata, - slot: Int, - rowGeneration: Int, - ridSlot: Int, - attemptGeneration: Int, - fault: Boolean = false, - stid: Int = 1): Unit = { - val completion = dut.io.completion.bits - completion.poke(0.U.asTypeOf(completion)) - completion.peId.poke(3.U) - completion.stid.poke(stid.U) - completion.tid.poke(stid.U) - completion.payload.valid.poke(true.B) - completion.payload.loadId.valid.poke(true.B) - completion.payload.loadId.slot.poke(slot.U) - completion.payload.loadId.generation.poke(rowGeneration.U) - completion.payload.attempt.valid.poke(true.B) - completion.payload.attempt.producer.valid.poke(true.B) - completion.payload.attempt.producer.peId.poke(3.U) - completion.payload.attempt.producer.stid.poke(stid.U) - completion.payload.attempt.producer.nativeBidValid.poke(true.B) - completion.payload.attempt.producer.nativeBid.poke((ridSlot + 4).U) - completion.payload.attempt.producer.brobGeneration.poke(9.U) - completion.payload.attempt.producer.ridSlot.poke(ridSlot.U) - completion.payload.attempt.producer.ridGeneration.poke(5.U) - completion.payload.attempt.producer.memberIndex.poke(1.U) - completion.payload.attempt.producer.residentGeneration.poke(11.U) - completion.payload.attempt.generation.poke(attemptGeneration.U) - completion.payload.dst.valid.poke(true.B) - completion.payload.dst.kind.poke(DestinationKind.Gpr) - completion.payload.dst.archTag.poke(6.U) - completion.payload.dst.physTag.poke((31 + slot).U) - completion.payload.dst.oldPhysTag.poke((21 + slot).U) - completion.payload.data.poke( - (if (fault) BigInt(0) else BigInt("1122334455667788", 16)).U) - completion.payload.faultValid.poke(fault.B) - completion.payload.faultCause.poke((if (fault) 0x55 else 0).U) - dut.io.completion.valid.poke(true.B) - } - - test("retains exact terminal metadata under backpressure and clears only on atomic fire") { - simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => - defaults(dut) - pokeAlloc(dut, slot = 2, rowGeneration = 1, ridSlot = 3, - attemptGeneration = 7) - acceptAlloc(dut) - dut.io.occupied.expect(1.U) - - pokeCompletion(dut, slot = 2, rowGeneration = 1, ridSlot = 3, - attemptGeneration = 7) - dut.io.result.valid.expect(true.B) - dut.io.completion.ready.expect(false.B) - dut.io.result.bits.agu.destination.ptag.expect(33.U) - dut.io.result.bits.agu.destination.ptagGeneration.expect(4.U) - dut.io.result.bits.data.expect(BigInt("1122334455667788", 16).U) - dut.clock.step(3) - dut.io.occupied.expect(1.U) - dut.io.result.valid.expect(true.B) - - // The canonical LIQ slot cannot be reused while its terminal metadata - // still owns the older physical row lease. - pokeAlloc(dut, slot = 2, rowGeneration = 0, ridSlot = 4, - attemptGeneration = 8) - dut.io.alloc.ready.expect(false.B) - dut.io.allocRejected.valid.expect(true.B) - dut.io.allocRejected.bits.resident.expect(true.B) - dut.io.alloc.valid.poke(false.B) - - dut.io.result.ready.poke(true.B) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - dut.io.result.ready.poke(false.B) - dut.io.empty.expect(true.B) - } - } - - test("requires exact rebind generation and rejects the stale attempt after replay") { - simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => - defaults(dut) - pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 2, - attemptGeneration = 5) - acceptAlloc(dut) - - val rebind = dut.io.rebind.bits - rebind.poke(0.U.asTypeOf(rebind)) - rebind.loadId.valid.poke(true.B) - rebind.loadId.slot.poke(1.U) - rebind.currentLoad.valid.poke(true.B) - pokeMember(rebind.currentLoad.producer, ridSlot = 2) - rebind.currentLoad.generation.poke(5.U) - pokeAttemptFromLoad(rebind.currentAttempt, rebind.currentLoad) - rebind.nextLoad.valid.poke(true.B) - pokeMember(rebind.nextLoad.producer, ridSlot = 2) - rebind.nextLoad.generation.poke(6.U) - pokeAttemptFromLoad(rebind.nextAttempt, rebind.nextLoad) - dut.io.rebind.valid.poke(true.B) - dut.io.rebind.ready.expect(true.B) - dut.clock.step() - dut.io.rebind.valid.poke(false.B) - - pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, - attemptGeneration = 5) - dut.io.result.ready.poke(true.B) - dut.io.result.valid.expect(false.B) - dut.io.completion.ready.expect(false.B) - dut.io.completionRejected.valid.expect(true.B) - dut.io.completionRejected.bits.attemptExact.expect(false.B) - - pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 2, - attemptGeneration = 6) - dut.io.result.valid.expect(true.B) - dut.io.result.bits.load.generation.expect(6.U) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - dut.io.empty.expect(true.B) - } - } - - test("recovery fences terminal publication and prunes only the exact killed member") { - simulate(new OooIexLoadTerminalMetadata(p, core)) { dut => - defaults(dut) - pokeAlloc(dut, slot = 0, rowGeneration = 0, ridSlot = 1, - attemptGeneration = 1) - acceptAlloc(dut) - pokeAlloc(dut, slot = 1, rowGeneration = 0, ridSlot = 3, - attemptGeneration = 2) - acceptAlloc(dut) - dut.io.occupied.expect(2.U) - - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(1.U) - plan.oldHead.ridGeneration.poke(5.U) - plan.oldOccupied.poke(3.U) - plan.newOccupied.poke(2.U) - dut.io.recoveryPrepare.valid.poke(true.B) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryKilledMask.expect(2.U) - - pokeCompletion(dut, slot = 1, rowGeneration = 0, ridSlot = 3, - attemptGeneration = 2, fault = true) - dut.io.result.ready.poke(true.B) - dut.io.result.valid.expect(false.B) - dut.io.completion.ready.expect(false.B) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.completion.valid.poke(false.B) - dut.io.occupied.expect(1.U) - - pokeCompletion(dut, slot = 0, rowGeneration = 0, ridSlot = 1, - attemptGeneration = 1, fault = true) - dut.io.result.valid.expect(true.B) - dut.io.result.bits.faultValid.expect(true.B) - dut.io.result.bits.faultCause.expect(0x55.U) - dut.io.result.bits.data.expect(0.U) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - dut.io.empty.expect(true.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexLoadUnitSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexLoadUnitSpec.scala deleted file mode 100644 index 77247071..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexLoadUnitSpec.scala +++ /dev/null @@ -1,293 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.DestinationKind -import org.scalatest.funsuite.AnyFunSuite - -class OooIexLoadUnitSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - iexLoadTrackEntries = 4, - tuRetireSourceDepthPerStid = 16) - - private def clear(dut: OooIexLoadUnit): Unit = { - dut.io.agu.valid.poke(false.B) - dut.io.agu.bits.poke(0.U.asTypeOf(dut.io.agu.bits)) - dut.io.memoryRequest.ready.poke(false.B) - dut.io.memoryResponse.valid.poke(false.B) - dut.io.memoryResponse.bits.poke( - 0.U.asTypeOf(dut.io.memoryResponse.bits)) - dut.io.result.ready.poke(false.B) - dut.io.recoveryApply.valid.poke(false.B) - dut.io.recoveryApply.bits.poke( - 0.U.asTypeOf(dut.io.recoveryApply.bits)) - } - - private def pokeMember(target: RobMemberKey, ridSlot: Int): Unit = { - target.poke(0.U.asTypeOf(target)) - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(ridSlot.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(5.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(0.U) - target.residentGeneration.poke(4.U) - } - - private def pokeAgu( - dut: OooIexLoadUnit, - ridSlot: Int, - address: BigInt, - accessBytes: Int, - signExtend: Boolean, - ptag: Int = 31): Unit = { - val request = dut.io.agu.bits - request.poke(0.U.asTypeOf(request)) - val row = request.execute.i2.row.schedule - row.valid.poke(true.B) - row.peId.poke(3.U) - row.stid.poke(1.U) - row.epoch.poke(7.U) - pokeMember(row.member, ridSlot) - request.address.poke(address.U) - request.accessBytes.poke(accessBytes.U) - request.signExtend.poke(signExtend.B) - request.destination.valid.poke(true.B) - request.destination.kind.poke(DestinationKind.Gpr) - request.destination.atag.poke(6.U) - request.destination.ptag.poke(ptag.U) - request.destination.ptagGeneration.poke(2.U) - dut.io.agu.valid.poke(true.B) - } - - private def pokeLoad( - target: OooIexLoadGeneration, - ridSlot: Int, - generation: BigInt): Unit = { - target.poke(0.U.asTypeOf(target)) - target.valid.poke(true.B) - pokeMember(target.producer, ridSlot) - target.generation.poke(generation.U) - } - - private def pokeResponse( - dut: OooIexLoadUnit, - ridSlot: Int, - generation: BigInt, - kind: OooIexLoadResponseKind.Type, - data: BigInt = 0, - cause: BigInt = 0): Unit = { - dut.io.memoryResponse.bits.poke( - 0.U.asTypeOf(dut.io.memoryResponse.bits)) - pokeLoad(dut.io.memoryResponse.bits.load, ridSlot, generation) - dut.io.memoryResponse.bits.kind.poke(kind) - dut.io.memoryResponse.bits.data.poke(data.U) - dut.io.memoryResponse.bits.faultCause.poke(cause.U) - dut.io.memoryResponse.valid.poke(true.B) - } - - private def pokeRecovery( - dut: OooIexLoadUnit, - newOccupied: Int): Unit = { - val plan = dut.io.recoveryApply.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) - dut.io.recoveryApply.valid.poke(true.B) - } - - test("allocates a generation and retains an extended hit result") { - simulate(new OooIexLoadUnit(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeAgu(dut, ridSlot = 1, address = 0x4000, - accessBytes = 1, signExtend = true) - dut.io.agu.ready.expect(true.B) - dut.clock.step() - dut.io.agu.valid.poke(false.B) - dut.io.occupied.expect(1.U) - dut.io.memoryRequest.valid.expect(true.B) - dut.io.memoryRequest.bits.address.expect(0x4000.U) - val generation = dut.io.memoryRequest.bits.load.generation.peek().litValue - assert(generation != 0) - dut.clock.step(2) - dut.io.memoryRequest.bits.load.generation.expect(generation.U) - - dut.io.memoryRequest.ready.poke(true.B) - dut.io.speculativeWakeup.valid.expect(true.B) - dut.io.speculativeWakeup.bits.load.generation.expect(generation.U) - dut.io.speculativeWakeup.bits.ptag.expect(31.U) - dut.clock.step() - dut.io.memoryRequest.ready.poke(false.B) - - pokeResponse(dut, ridSlot = 1, generation = generation, - kind = OooIexLoadResponseKind.Hit, data = 0x80) - dut.io.memoryResponse.ready.expect(true.B) - dut.io.cancel.valid.expect(false.B) - dut.clock.step() - dut.io.memoryResponse.valid.poke(false.B) - dut.io.result.valid.expect(true.B) - dut.io.result.bits.data.expect(BigInt("ffffffffffffff80", 16).U) - dut.io.bypass.valid.expect(true.B) - dut.io.bypass.bits.load.generation.expect(generation.U) - dut.clock.step(2) - dut.io.result.bits.data.expect(BigInt("ffffffffffffff80", 16).U) - - dut.io.result.ready.poke(true.B) - dut.clock.step() - dut.io.occupied.expect(0.U) - dut.io.bypass.valid.expect(false.B) - } - } - - test("cancels a missed generation and retries with a new generation") { - simulate(new OooIexLoadUnit(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeAgu(dut, ridSlot = 2, address = 0x5000, - accessBytes = 4, signExtend = false) - dut.clock.step() - dut.io.agu.valid.poke(false.B) - val first = dut.io.memoryRequest.bits.load.generation.peek().litValue - dut.io.memoryRequest.ready.poke(true.B) - dut.clock.step() - dut.io.memoryRequest.ready.poke(false.B) - - pokeResponse(dut, ridSlot = 2, generation = first, - kind = OooIexLoadResponseKind.Miss) - dut.io.cancel.valid.expect(true.B) - dut.io.cancel.bits.load.generation.expect(first.U) - dut.clock.step() - dut.io.memoryResponse.valid.poke(false.B) - dut.io.memoryRequest.valid.expect(true.B) - val second = dut.io.memoryRequest.bits.load.generation.peek().litValue - assert(second != first) - dut.io.speculativeWakeup.valid.expect(false.B) - - pokeResponse(dut, ridSlot = 2, generation = first, - kind = OooIexLoadResponseKind.Hit, data = 0x1234) - dut.io.responseRejected.valid.expect(true.B) - dut.clock.step() - dut.io.memoryResponse.valid.poke(false.B) - - dut.io.memoryRequest.ready.poke(true.B) - dut.io.speculativeWakeup.valid.expect(true.B) - dut.io.speculativeWakeup.bits.load.generation.expect(second.U) - dut.clock.step() - dut.io.memoryRequest.ready.poke(false.B) - pokeResponse(dut, ridSlot = 2, generation = second, - kind = OooIexLoadResponseKind.Hit, - data = BigInt("deadbeef", 16)) - dut.clock.step() - dut.io.memoryResponse.valid.poke(false.B) - dut.io.result.valid.expect(true.B) - dut.io.result.bits.data.expect(BigInt("deadbeef", 16).U) - } - } - - test("retains precise faults and drops recovered outstanding loads") { - simulate(new OooIexLoadUnit(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeAgu(dut, ridSlot = 1, address = 0x6000, - accessBytes = 8, signExtend = false) - dut.clock.step() - dut.io.agu.valid.poke(false.B) - val faultGeneration = - dut.io.memoryRequest.bits.load.generation.peek().litValue - dut.io.memoryRequest.ready.poke(true.B) - dut.clock.step() - dut.io.memoryRequest.ready.poke(false.B) - pokeResponse(dut, ridSlot = 1, generation = faultGeneration, - kind = OooIexLoadResponseKind.Fault, cause = 13) - dut.io.cancel.valid.expect(true.B) - dut.clock.step() - dut.io.memoryResponse.valid.poke(false.B) - dut.io.result.valid.expect(true.B) - dut.io.result.bits.faultValid.expect(true.B) - dut.io.result.bits.faultCause.expect(13.U) - dut.io.bypass.valid.expect(false.B) - dut.io.result.ready.poke(true.B) - dut.clock.step() - - dut.io.result.ready.poke(false.B) - pokeAgu(dut, ridSlot = 3, address = 0x7000, - accessBytes = 8, signExtend = false) - dut.clock.step() - dut.io.agu.valid.poke(false.B) - val killedGeneration = - dut.io.memoryRequest.bits.load.generation.peek().litValue - dut.io.memoryRequest.ready.poke(true.B) - dut.clock.step() - dut.io.memoryRequest.ready.poke(false.B) - pokeRecovery(dut, newOccupied = 3) - dut.io.occupied.expect(1.U) - dut.clock.step() - dut.io.recoveryApply.valid.poke(false.B) - dut.io.occupied.expect(0.U) - pokeResponse(dut, ridSlot = 3, generation = killedGeneration, - kind = OooIexLoadResponseKind.Hit, data = 9) - dut.io.responseRejected.valid.expect(true.B) - } - } - - test("rejects malformed requests and duplicate live producers") { - simulate(new OooIexLoadUnit(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeAgu(dut, ridSlot = 1, address = 0x8000, - accessBytes = 3, signExtend = false) - dut.io.agu.ready.expect(false.B) - dut.io.acceptRejected.valid.expect(true.B) - dut.io.acceptRejected.bits.accessExact.expect(false.B) - dut.io.agu.bits.accessBytes.poke(8.U) - dut.io.agu.ready.expect(true.B) - dut.clock.step() - - pokeAgu(dut, ridSlot = 1, address = 0x8008, - accessBytes = 8, signExtend = false) - dut.io.agu.ready.expect(false.B) - dut.io.acceptRejected.bits.duplicateProducer.expect(true.B) - dut.io.agu.bits.execute.i2.row.schedule.peId.poke(2.U) - dut.io.acceptRejected.bits.identityExact.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexOldestReadyPickerSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexOldestReadyPickerSpec.scala index f1b0caca..54a6163f 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexOldestReadyPickerSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexOldestReadyPickerSpec.scala @@ -34,9 +34,6 @@ class OooIexOldestReadyPickerSpec extends AnyFunSuite with ChiselSim { dut.io.candidates.foreach(_.foreach(_.foreach( _.poke(0.U.asTypeOf(dut.io.candidates.head.head.head))))) dut.io.pick.ready.poke(false.B) - dut.io.recoveryApply.valid.poke(false.B) - dut.io.recoveryApply.bits.poke( - 0.U.asTypeOf(dut.io.recoveryApply.bits)) } private def pokeCandidate( @@ -73,23 +70,6 @@ class OooIexOldestReadyPickerSpec extends AnyFunSuite with ChiselSim { candidate.reservation.reservationEpoch.poke(9.U) } - private def pokeRecovery( - dut: OooIexOldestReadyPicker, - stid: Int, - newOccupied: Int): Unit = { - val plan = dut.io.recoveryApply.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(stid.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) - dut.io.recoveryApply.valid.poke(true.B) - } - test("selects wrap-safe oldest members and rotates fairly across STIDs") { simulate(new OooIexOldestReadyPicker(p)) { dut => clear(dut) @@ -162,29 +142,6 @@ class OooIexOldestReadyPickerSpec extends AnyFunSuite with ChiselSim { } } - test("suppresses and clears a retained result killed by recovery") { - simulate(new OooIexOldestReadyPicker(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeCandidate(dut, bank = 0, entry = 1, stid = 1, - generation = 1, ridSlot = 2) - dut.clock.step() - dut.io.pick.valid.expect(true.B) - - pokeRecovery(dut, stid = 1, newOccupied = 1) - dut.io.pick.valid.expect(false.B) - dut.io.recoveryCanceled.valid.expect(true.B) - dut.io.recoveryCanceled.bits.query.entry.expect(1.U) - dut.clock.step() - dut.io.recoveryApply.valid.poke(false.B) - dut.io.pick.valid.expect(false.B) - dut.io.held.expect(false.B) - } - } - test("drops a blocked target token and continues with a peer STID") { simulate(new OooIexOldestReadyPicker(p)) { dut => clear(dut) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala index f6b21bd9..41374b79 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala @@ -7,6 +7,26 @@ import linxcore.common.OperandClass import org.scalatest.funsuite.AnyFunSuite class OooIexOperandFilesSpec extends AnyFunSuite with ChiselSim { + test("exports exact generation-qualified PTag Ready Bits") { + val p = OooParams() + simulate(new OooIexOperandFiles(p)) { dut => + clear(dut) + dut.io.pInit.valid.poke(true.B) + dut.io.pInit.bits.key.stid.poke(1.U) + dut.io.pInit.bits.key.epoch.poke(7.U) + dut.io.pInit.bits.key.ptag.poke(31.U) + dut.io.pInit.bits.key.generation.poke(9.U) + dut.io.pInit.bits.data.poke(0x55.U) + dut.clock.step() + dut.io.pInit.valid.poke(false.B) + + dut.io.readyBits.ptag(31).valid.expect(true.B) + dut.io.readyBits.ptag(31).ready.expect(true.B) + dut.io.readyBits.ptag(31).stid.expect(1.U) + dut.io.readyBits.ptag(31).epoch.expect(7.U) + dut.io.readyBits.ptag(31).generation.expect(9.U) + } + } private val p = OooParams( stidCount = 2, pPhysRegs = 128, @@ -95,7 +115,7 @@ class OooIexOperandFilesSpec extends AnyFunSuite with ChiselSim { dut.clock.step() dut.reset.poke(false.B) - // P data/ready is the existing canonical ScalarGPRFile state. + // P data/ready belongs to the canonical OOO-IEX operand owner. dut.io.pInit.valid.poke(true.B) pokePKey(dut.io.pInit.bits.key, stid = 0, ptag = 40, generation = 3) @@ -107,6 +127,13 @@ class OooIexOperandFilesSpec extends AnyFunSuite with ChiselSim { dut.io.pReadResponses(0).valid.expect(true.B) dut.io.pReadResponses(0).bits.expect(11.U) + // A physical GPR mapping may outlive the frontend epoch that created + // it. The PTag generation, not the consumer instruction epoch, is the + // exact reuse discriminator. + dut.io.pReadRequests(0).bits.epoch.poke(8.U) + dut.io.pReadResponses(0).valid.expect(true.B) + dut.io.pReadResponses(0).bits.expect(11.U) + dut.io.pClear(0).valid.poke(true.B) pokePKey(dut.io.pClear(0).bits, stid = 0, ptag = 40, generation = 4) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexP1I2LaneSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexP1I2LaneSpec.scala index 6fc8e8cc..1f7b05e1 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexP1I2LaneSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexP1I2LaneSpec.scala @@ -18,19 +18,21 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, tuRetireSourceDepthPerStid = 16) + private val core = OooRecoveryMembership.coreParams(p) private def clear(dut: OooIexP1I2Lane): Unit = { dut.io.p1.valid.poke(false.B) dut.io.p1.bits.poke(0.U.asTypeOf(dut.io.p1.bits)) dut.io.readDecisionValid.poke(false.B) dut.io.readGrant.poke(false.B) + dut.io.operandReadyBits.poke(0.U.asTypeOf(dut.io.operandReadyBits)) dut.io.sourceDataValid.poke(0.U) dut.io.sourceData.foreach(_.poke(0.U)) dut.io.pcDataValid.poke(false.B) @@ -183,19 +185,27 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { newOccupied: Int): Unit = { val plan = dut.io.recoveryApply.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(stid.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(1.U) - plan.oldOccupied.poke(4.U) - plan.newOccupied.poke(newOccupied.U) + plan.phase.poke(linxcore.top.interface.RecoveryPhase.Apply) + plan.trigger.peId.poke(3.U) + plan.trigger.stid.poke(stid.U) + plan.trigger.ridSlot.poke(0.U) + plan.trigger.ridGeneration.poke(1.U) + plan.firstKilledValid.poke(true.B) + plan.firstKilled.peId.poke(3.U) + plan.firstKilled.stid.poke(stid.U) + plan.firstKilled.ridSlot.poke(newOccupied.U) + plan.firstKilled.ridGeneration.poke(1.U) + plan.firstKilled.memberIndex.poke(0.U) + plan.lastKilled.peId.poke(3.U) + plan.lastKilled.stid.poke(stid.U) + plan.lastKilled.ridSlot.poke(3.U) + plan.lastKilled.ridGeneration.poke(1.U) + plan.lastKilled.memberIndex.poke((p.maxOrdinaryUopsPerGroup - 1).U) dut.io.recoveryApply.valid.poke(true.B) } test("stages exact P T and PC reads from P1 through retained I2") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -223,13 +233,13 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { dut.io.i2.bits.sourceData(0).expect("h1122334455667788".U) dut.io.i2.bits.sourceData(1).expect("h8877665544332211".U) dut.io.i2.bits.pcValid.expect(true.B) - dut.io.i2.bits.pc.expect("h80000126".U) + dut.io.i2.bits.pc.expect("h8000012c".U) dut.io.sourceData.foreach(_.poke("hdeadbeef".U)) dut.io.pcData.poke("h55".U) dut.clock.step(2) dut.io.i2.bits.sourceData(0).expect("h1122334455667788".U) - dut.io.i2.bits.pc.expect("h80000126".U) + dut.io.i2.bits.pc.expect("h8000012c".U) dut.io.i2.ready.poke(true.B) dut.clock.step() @@ -239,7 +249,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("turns an I1 read-port denial into an exact repick") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -262,7 +272,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("serializes simultaneous exact I2 and I1 cancels without losing retries") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -328,7 +338,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("rejects a stale stage-cancel identity without disturbing I1") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -379,7 +389,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("uses exact load bypass data without requesting its RF source") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -480,8 +490,49 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } } + test("resamples-expired-speculative-p-source-from-the-physical-file") { + simulate(new OooIexP1I2Lane(core, p)) { dut => + clear(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + + pokeRequest(dut, stid = 0, ridSlot = 5, pcRequired = false) + val source = dut.io.p1.bits.row.schedule.sources(0) + source.ready.poke(false.B) + source.specReady.poke(true.B) + pokeLoadToken(source.load, stid = 0, generation = 7) + dut.clock.step() + dut.io.p1.valid.poke(false.B) + + dut.io.i1Occupied.expect(true.B) + dut.io.readAttempt.valid.expect(false.B) + + val ptag = dut.io.operandReadyBits.ptag(17) + ptag.valid.poke(true.B) + ptag.ready.poke(true.B) + ptag.stid.poke(0.U) + ptag.generation.poke(3.U) + dut.io.readAttempt.valid.expect(true.B) + dut.io.readAttempt.bits.sourceMask.expect("b0011".U) + + dut.io.readDecisionValid.poke(true.B) + dut.io.readGrant.poke(true.B) + dut.io.sourceDataValid.poke("b0011".U) + dut.io.sourceData(0).poke("h0123456789abcdef".U) + dut.io.sourceData(1).poke("h8877665544332211".U) + dut.clock.step() + dut.io.readDecisionValid.poke(false.B) + dut.io.readGrant.poke(false.B) + + dut.io.i2.valid.expect(true.B) + dut.io.i2.bits.bypassMask.expect(0.U) + dut.io.i2.bits.sourceData(0).expect("h0123456789abcdef".U) + } + } + test("consumes a malformed P1 row as a typed reject") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -499,7 +550,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("rejects a partial readyless response without publishing I2") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() @@ -527,7 +578,7 @@ class OooIexP1I2LaneSpec extends AnyFunSuite with ChiselSim { } test("applies recovery only to a matching retained I1 or I2 member") { - simulate(new OooIexP1I2Lane(p)) { dut => + simulate(new OooIexP1I2Lane(core, p)) { dut => clear(dut) dut.reset.poke(true.B) dut.clock.step() diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexP1I2PcIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexP1I2PcIntegrationSpec.scala deleted file mode 100644 index b4e40692..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexP1I2PcIntegrationSpec.scala +++ /dev/null @@ -1,233 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, Valid} -import linxcore.common.OperandClass -import org.scalatest.funsuite.AnyFunSuite - -private class OooIexP1I2PcIntegrationHarnessIO(val p: OooParams) - extends Bundle { - val pcPrepare = Flipped(Valid(new OooD3GroupedReservation(p))) - val pcPrepared = Output(new OooPcPreparedBindings(p)) - val pcPrepareReady = Output(Bool()) - val pcPublishFire = Input(Bool()) - - val p1 = Flipped(Decoupled(new OooIexP1Request(p))) - val readAttempt = Output(Valid(new OooIexI1ReadAttempt(p))) - val readDecisionValid = Input(Bool()) - val readGrant = Input(Bool()) - val sourceDataValid = Input(UInt(p.maxSourceOperands.W)) - val sourceData = Input(Vec(p.maxSourceOperands, UInt(p.pcWidth.W))) - val i2 = Decoupled(new OooIexI2Transaction(p)) -} - -private class OooIexP1I2PcIntegrationHarness(val p: OooParams) - extends Module { - val io = IO(new OooIexP1I2PcIntegrationHarnessIO(p)) - - val pc = Module(new OooPcBuffer(p)) - val lane = Module(new OooIexP1I2Lane(p)) - - pc.io.prepare := io.pcPrepare - io.pcPrepared := pc.io.prepared - io.pcPrepareReady := pc.io.prepareReady - pc.io.publishFire := io.pcPublishFire - pc.io.commit.valid := false.B - pc.io.commit.bits := 0.U.asTypeOf(pc.io.commit.bits) - pc.io.recoveryPrepare.valid := false.B - pc.io.recoveryPrepare.bits := - 0.U.asTypeOf(pc.io.recoveryPrepare.bits) - pc.io.recoveryFire := false.B - pc.io.readTokens.foreach(_ := 0.U.asTypeOf(pc.io.readTokens.head)) - when(lane.io.readAttempt.valid && lane.io.readAttempt.bits.pcRequired) { - pc.io.readTokens(0) := lane.io.readAttempt.bits.pcToken - } - - lane.io.p1 <> io.p1 - io.readAttempt := lane.io.readAttempt - lane.io.readDecisionValid := io.readDecisionValid - lane.io.readGrant := io.readGrant - lane.io.sourceDataValid := io.sourceDataValid - lane.io.sourceData := io.sourceData - lane.io.pcDataValid := pc.io.readValid(0) - lane.io.pcData := pc.io.readPc(0) - lane.io.recoveryApply.valid := false.B - lane.io.recoveryApply.bits := - 0.U.asTypeOf(lane.io.recoveryApply.bits) - lane.io.bypass.foreach(_ := 0.U.asTypeOf(lane.io.bypass.head)) - lane.io.loadCancel.foreach(_ := 0.U.asTypeOf(lane.io.loadCancel.head)) - lane.io.stageCancel.foreach { cancel => - cancel.valid := false.B - cancel.bits := 0.U.asTypeOf(cancel.bits) - } - lane.io.repick.ready := true.B - io.i2.valid := lane.io.i2.valid - io.i2.bits := lane.io.i2.bits - lane.io.i2.ready := io.i2.ready -} - -class OooIexP1I2PcIntegrationSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - tuRetireSourceDepthPerStid = 16) - - private def clear(dut: OooIexP1I2PcIntegrationHarness): Unit = { - dut.io.pcPrepare.valid.poke(false.B) - dut.io.pcPrepare.bits.poke(0.U.asTypeOf(dut.io.pcPrepare.bits)) - dut.io.pcPublishFire.poke(false.B) - dut.io.p1.valid.poke(false.B) - dut.io.p1.bits.poke(0.U.asTypeOf(dut.io.p1.bits)) - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - dut.io.sourceDataValid.poke(0.U) - dut.io.sourceData.foreach(_.poke(0.U)) - dut.io.i2.ready.poke(false.B) - } - - private def pokePcPrepare( - dut: OooIexP1I2PcIntegrationHarness, - basePc: Long): Unit = { - val prepare = dut.io.pcPrepare.bits - prepare.poke(0.U.asTypeOf(prepare)) - val transaction = prepare.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(102.U) - transaction.plan.groupCount.poke(2.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(3.U) - transaction.groupMask.poke(3.U) - Seq(basePc, basePc + 6).zipWithIndex.foreach { case (pc, index) => - transaction.uopGroupIndex(index).poke(index.U) - val group = transaction.groups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(1.U) - group.key.ridSlot.poke((2 + index).U) - group.key.ridGeneration.poke(1.U) - group.logicalUopMask.poke((1 << index).U) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - - val uop = transaction.decoded.uops(index) - uop.valid.poke(true.B) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(1.U) - uop.identity.parents(0).key.instructionId.poke((202 + index).U) - uop.identity.parents(0).key.epoch.poke(7.U) - uop.identity.parents(0).pc.poke(pc.U) - } - dut.io.pcPrepare.valid.poke(true.B) - } - - private def pokeP1( - dut: OooIexP1I2PcIntegrationHarness, - tokenIndex: BigInt, - tokenOffset: BigInt, - tokenEpoch: BigInt): Unit = { - val request = dut.io.p1.bits - request.poke(0.U.asTypeOf(request)) - val row = request.row - row.schedule.valid.poke(true.B) - row.schedule.peId.poke(3.U) - row.schedule.stid.poke(1.U) - row.schedule.epoch.poke(7.U) - row.schedule.transactionId.poke(102.U) - row.schedule.member.group.valid.poke(true.B) - row.schedule.member.group.peId.poke(3.U) - row.schedule.member.group.stid.poke(1.U) - row.schedule.member.group.ridSlot.poke(3.U) - row.schedule.member.group.ridGeneration.poke(1.U) - row.schedule.member.bid.valid.poke(true.B) - row.schedule.member.bid.value.poke(5.U) - row.schedule.member.brobGeneration.poke(2.U) - row.schedule.member.residentGeneration.poke(4.U) - row.schedule.reservation.valid.poke(true.B) - row.schedule.reservation.uopClass.poke(OooUopClass.Alu) - row.schedule.reservation.bank.poke(0.U) - row.schedule.reservation.speculativeSlot.poke(1.U) - row.payload.uopKey.primaryParent.valid.poke(true.B) - row.payload.uopKey.primaryParent.peId.poke(3.U) - row.payload.uopKey.primaryParent.stid.poke(1.U) - row.payload.uopKey.primaryParent.instructionId.poke(203.U) - row.payload.uopKey.primaryParent.epoch.poke(7.U) - row.schedule.sources(0).valid.poke(true.B) - row.schedule.sources(0).ready.poke(true.B) - row.schedule.sources(0).operandClass.poke(OperandClass.P) - row.schedule.sources(0).ptag.poke(17.U) - row.schedule.sources(0).ptagGeneration.poke(3.U) - row.payload.parentCount.poke(1.U) - row.payload.parentPcTokens(0).valid.poke(true.B) - row.payload.parentPcTokens(0).index.poke(tokenIndex.U) - row.payload.parentPcTokens(0).byteOffset.poke(tokenOffset.U) - row.payload.parentPcTokens(0).allocationEpoch.poke(tokenEpoch.U) - request.pcReadRequired.poke(true.B) - request.pcParentIndex.poke(0.U) - dut.io.p1.valid.poke(true.B) - } - - test("reads an allocated PC token into retained I2") { - simulate(new OooIexP1I2PcIntegrationHarness(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokePcPrepare(dut, basePc = 0x80000120L) - dut.io.pcPrepareReady.expect(true.B) - val token = dut.io.pcPrepared.parentTokens(1)(0) - val tokenIndex = token.index.peek().litValue - val tokenOffset = token.byteOffset.peek().litValue - val tokenEpoch = token.allocationEpoch.peek().litValue - token.valid.expect(true.B) - token.byteOffset.expect(6.U) - dut.io.pcPublishFire.poke(true.B) - dut.clock.step() - dut.io.pcPublishFire.poke(false.B) - dut.io.pcPrepare.valid.poke(false.B) - - pokeP1(dut, tokenIndex, tokenOffset, tokenEpoch) - dut.io.p1.ready.expect(true.B) - dut.clock.step() - dut.io.p1.valid.poke(false.B) - dut.io.readAttempt.valid.expect(true.B) - dut.io.readAttempt.bits.pcToken.index.expect(tokenIndex.U) - - dut.io.readDecisionValid.poke(true.B) - dut.io.readGrant.poke(true.B) - dut.io.sourceDataValid.poke(1.U) - dut.io.sourceData(0).poke("h1122334455667788".U) - dut.clock.step() - dut.io.readDecisionValid.poke(false.B) - dut.io.readGrant.poke(false.B) - - dut.io.i2.valid.expect(true.B) - dut.io.i2.bits.pcValid.expect(true.B) - dut.io.i2.bits.pc.expect("h80000126".U) - dut.io.i2.bits.sourceData(0).expect("h1122334455667788".U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala index 30175f09..3bef615c 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala @@ -1,6 +1,7 @@ package linxcore.ooo import circt.stage.ChiselStage +import linxcore.params.ParamProfiles import org.scalatest.funsuite.AnyFunSuite class OooIexPhysicalProfileSpec extends AnyFunSuite { @@ -136,4 +137,20 @@ class OooIexPhysicalProfileSpec extends AnyFunSuite { assert(sharedSystemVerilog.contains("module OooIexSharedResourceArbiter")) assert(sharedSystemVerilog.contains("io_conflicted")) } + + test("canonical profile permits only capability-disjoint logical owner overlap") { + val profile = OooIexPhysicalProfile.fromCoreParams(ParamProfiles.W4) + val aluClass = OooDispatchClass.Alu - 1 + val simpleOwners = profile.ownersOf(aluClass).filter( + _.hasCapability(SimpleAlu)) + val systemOwner = profile.ownersOf(aluClass).find( + _.hasCapability(MultiCycleAlu)).get + + assert(simpleOwners.size == 2) + assert(simpleOwners.forall(owner => + (owner.classBankEnables(aluClass) & + systemOwner.classBankEnables(aluClass)) != 0)) + assert(simpleOwners.forall(owner => + (owner.capabilities & systemOwner.capabilities) == 0)) + } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexRecoverySpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexRecoverySpec.scala deleted file mode 100644 index 192cd434..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexRecoverySpec.scala +++ /dev/null @@ -1,507 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -/** Focused O7 recovery proof with the smallest physical IQ that can retain an - * older member and a killed suffix simultaneously. The owner is - * instantiated directly; this is not a behavioral mock. - */ -class OooIexRecoverySpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - robGroupsPerStid = 4, - iqBankCount = 2, - iqEntriesPerBank = 2, - iqWritePortsPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 8) - - private def clear(dut: OooIexIssue): Unit = { - dut.io.s1.valid.poke(false.B) - dut.io.s1.bits.poke(0.U.asTypeOf(dut.io.s1.bits)) - dut.io.wakeup.foreach { wakeup => - wakeup.valid.poke(false.B) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - } - dut.io.loadCancel.foreach( - _.poke(0.U.asTypeOf(dut.io.loadCancel.head))) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.dispatchRelease.ready.poke(true.B) - dut.io.query.poke(0.U.asTypeOf(dut.io.query)) - dut.io.pickBankEnables.flatten.foreach(_.poke(0.U)) - dut.io.pickBankEnables(0)(OooUopClass.Alu.asUInt.litValue.toInt) - .poke(((BigInt(1) << p.iqBankCount) - 1).U) - dut.io.issuePolicy.poke(0.U.asTypeOf(dut.io.issuePolicy)) - dut.io.pick.ready.poke(false.B) - dut.io.pickRetry.valid.poke(false.B) - dut.io.pickRetry.bits.poke(0.U.asTypeOf(dut.io.pickRetry.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.ptagRecycle.valid.poke(false.B) - dut.io.ptagRecycle.bits.poke(0.U.asTypeOf(dut.io.ptagRecycle.bits)) - } - - private def pokeMember( - member: RobMemberKey, - stid: Int, - ridSlot: Int, - memberIndex: Int): Unit = { - member.poke(0.U.asTypeOf(member)) - member.group.valid.poke(true.B) - member.group.peId.poke(3.U) - member.group.stid.poke(stid.U) - member.group.ridSlot.poke(ridSlot.U) - member.group.ridGeneration.poke(0.U) - member.bid.valid.poke(true.B) - member.bid.value.poke((stid + 1).U) - member.brobGeneration.poke(2.U) - member.memberIndex.poke(memberIndex.U) - member.residentGeneration.poke(3.U) - } - - private def pokeTransaction( - dut: OooIexIssue, - stid: Int, - ridSlot: Int, - transactionId: Int, - entries: Vector[Int], - pDestination: Option[(Int, Int)] = None, - pSource: Option[(Int, Int)] = None): Unit = { - val request = dut.io.s1.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.o3.request.reservation.transaction - val uopMask = (1 << entries.length) - 1 - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(6.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(6.U) - transaction.decoded.uopMask.poke(uopMask.U) - - request.pRename.valid.poke(true.B) - request.pRename.peId.poke(3.U) - request.pRename.stid.poke(stid.U) - request.pRename.epoch.poke(6.U) - request.pRename.transactionId.poke(transactionId.U) - request.pRename.uopMask.poke(uopMask.U) - request.tuRename.valid.poke(true.B) - request.tuRename.peId.poke(3.U) - request.tuRename.stid.poke(stid.U) - request.tuRename.epoch.poke(6.U) - request.tuRename.transactionId.poke(transactionId.U) - request.tuRename.uopMask.poke(uopMask.U) - request.dispatch.valid.poke(true.B) - request.dispatch.peId.poke(3.U) - request.dispatch.stid.poke(stid.U) - request.dispatch.epoch.poke(6.U) - request.dispatch.transactionId.poke(transactionId.U) - request.dispatch.allocationMask.poke(uopMask.U) - - entries.indices.foreach { lane => - val decoded = transaction.decoded.uops(lane) - val pUop = request.pRename.uops(lane) - val tuUop = request.tuRename.uops(lane) - decoded.valid.poke(true.B) - decoded.opcode.poke((40 + lane).U) - decoded.plannedChildCount.poke(1.U) - decoded.recipe.valid.poke(true.B) - decoded.recipe.opcode.poke((40 + lane).U) - decoded.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - pUop.valid.poke(true.B) - pUop.decoded.valid.poke(true.B) - pUop.decoded.opcode.poke((40 + lane).U) - pUop.decoded.plannedChildCount.poke(1.U) - pUop.decoded.recipe.valid.poke(true.B) - pUop.decoded.recipe.opcode.poke((40 + lane).U) - pUop.decoded.recipe.disposition - .poke(OooOpcodeDisposition.Dispatch.U) - tuUop.valid.poke(true.B) - pokeMember(pUop.member, stid, ridSlot, lane) - pokeMember(tuUop.member, stid, ridSlot, lane) - - pDestination.foreach { case (ptag, generation) => - Seq(decoded.destinations(0), pUop.decoded.destinations(0)) - .foreach { destination => - destination.valid.poke(true.B) - destination.kind.poke(DestinationKind.Gpr) - destination.atag.poke(3.U) - } - pUop.destinations(0).currentPMapping.valid.poke(true.B) - pUop.destinations(0).currentPMapping.ptag.poke(ptag.U) - pUop.destinations(0).currentPMapping.ptagGeneration - .poke(generation.U) - } - - pSource.foreach { case (ptag, generation) => - Seq(decoded.sources(0), pUop.decoded.sources(0)).foreach { source => - source.valid.poke(true.B) - source.operandClass.poke(OperandClass.P) - source.atag.poke(2.U) - } - pUop.sources(0).decoded.valid.poke(true.B) - pUop.sources(0).decoded.operandClass.poke(OperandClass.P) - pUop.sources(0).decoded.atag.poke(2.U) - pUop.sources(0).pMapping.valid.poke(true.B) - pUop.sources(0).pMapping.ptag.poke(ptag.U) - pUop.sources(0).pMapping.ptagGeneration.poke(generation.U) - pUop.sources(0).pMapping.ready.poke(false.B) - pUop.sources(0).pMapping.stid.poke(stid.U) - pUop.sources(0).pMapping.epoch.poke(6.U) - } - - val allocation = request.dispatch.allocations(lane) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(lane.U) - allocation.childIndex.poke(0.U) - allocation.reservation.valid.poke(true.B) - allocation.reservation.uopClass.poke(OooUopClass.Alu) - allocation.reservation.bank.poke(0.U) - allocation.reservation.writePort.poke(lane.U) - allocation.reservation.speculativeSlot.poke(entries(lane).U) - allocation.reservation.reservationEpoch.poke(1.U) - } - dut.io.s1.valid.poke(true.B) - } - - private def pokeRecovery( - dut: OooIexIssue, - stid: Int, - ridSlot: Int, - oldMembers: Int, - survivingMembers: Int): Unit = { - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(3.U) - plan.oldHead.stid.poke(stid.U) - plan.oldHead.ridSlot.poke(ridSlot.U) - plan.oldHead.ridGeneration.poke(0.U) - plan.oldOccupied.poke(1.U) - plan.newOccupied.poke((if (survivingMembers == 0) 0 else 1).U) - plan.pivotOffset.poke(0.U) - pokeMember(plan.pivot, stid, ridSlot, 0) - plan.pivotPhysicalMemberCount.poke(oldMembers.U) - plan.survivingPivotValid.poke((survivingMembers != 0).B) - plan.survivingPivotPhysicalMemberCount.poke(survivingMembers.U) - dut.io.recoveryPrepare.valid.poke(true.B) - } - - private def query(dut: OooIexIssue, entry: Int): Unit = { - dut.io.query.uopClass.poke(OooUopClass.Alu) - dut.io.query.bank.poke(0.U) - dut.io.query.entry.poke(entry.U) - } - - private def waitForPrepared( - dut: OooIexIssue, - whileScanning: => Unit, - scanParams: OooParams = p): Int = { - var cycles = 0 - while (!dut.io.recoveryPrepareReady.peek().litToBoolean && - cycles < scanParams.iexRecoveryScanCycles + 2) { - whileScanning - dut.clock.step() - cycles += 1 - } - assert(dut.io.recoveryPrepareReady.peek().litToBoolean, - "retained IEX recovery scan did not prepare") - assert(cycles == scanParams.iexRecoveryScanCycles + 1, - s"expected one capture plus ${scanParams.iexRecoveryScanCycles} scan cycles, got $cycles") - cycles - } - - private def waitForRejected(dut: OooIexIssue): Unit = { - var cycles = 0 - while (!dut.io.recoveryRejected.valid.peek().litToBoolean && - cycles < p.iexRecoveryScanCycles + 2) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.recoveryRejected.valid.peek().litToBoolean, - "malformed resident window was not rejected by the timed scan") - } - - test("prunes exact BoundS2 and ResidentS3 suffixes without stopping peers") { - simulate(new OooIexIssue(p)) { dut => - clear(dut) - - pokeTransaction(dut, stid = 0, ridSlot = 0, transactionId = 1, - entries = Vector(0, 1)) - dut.io.s1Rejected.bits.shapeExact.expect(true.B) - dut.io.s1Rejected.bits.targetsExact.expect(true.B) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 2, - survivingMembers = 1) - dut.io.recoveryPrepareReady.expect(false.B) - - // Capture and then abort one partially completed scan. Target rows are - // frozen but remain physically resident because prepare is read-only. - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 2, - survivingMembers = 1) - waitForPrepared(dut, { - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - }) - dut.io.recoveryPrepared.boundKilled.expect(1.U) - dut.io.recoveryPrepared.residentKilled.expect(0.U) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.s3Enable.valid.expect(true.B) - dut.io.s3Enable.bits.bind.allocationMask.expect(1.U) - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(true.B) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - - pokeTransaction(dut, stid = 1, ridSlot = 1, transactionId = 2, - entries = Vector(1)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.io.s2Bind.valid.expect(true.B) - dut.clock.step() - dut.io.s3Enable.valid.expect(true.B) - dut.clock.step() - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - - pokeRecovery(dut, stid = 1, ridSlot = 1, oldMembers = 1, - survivingMembers = 0) - dut.io.recoveryPrepareReady.expect(false.B) - waitForPrepared(dut, { - query(dut, 0) - dut.io.queryPickable.expect(true.B) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(false.B) - }) - dut.io.recoveryPrepared.boundKilled.expect(0.U) - dut.io.recoveryPrepared.residentKilled.expect(1.U) - query(dut, 0) - dut.io.queryPickable.expect(true.B) - query(dut, 1) - dut.io.queryPickable.expect(false.B) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - - // A plan whose old window does not contain a live target-STID row must - // reject after scanning that row and must not prune it. - pokeRecovery(dut, stid = 0, ridSlot = 1, oldMembers = 1, - survivingMembers = 0) - waitForRejected(dut) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.bits.residentRowsExact.expect(false.B) - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - query(dut, 0) - dut.io.queryPickable.expect(true.B) - } - } - - test("rejects plan drift and identity-qualifies P-ready cleanup across reuse") { - simulate(new OooIexIssue(p)) { dut => - clear(dut) - - pokeTransaction(dut, stid = 0, ridSlot = 0, transactionId = 10, - entries = Vector(0), pDestination = Some(17 -> 3)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - - val wakeup = dut.io.wakeup(0) - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(3.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 1, - survivingMembers = 0) - dut.clock.step() - dut.io.recoveryPrepare.bits.survivingPivotPhysicalMemberCount.poke(1.U) - dut.io.recoveryRejected.valid.expect(true.B) - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - - // Capture a fresh exact plan and its old target P-ready identity. - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 1, - survivingMembers = 0) - dut.clock.step() - - // Recycle that exact old generation while the target row is scanned. - dut.io.ptagRecycle.bits.poke( - 0.U.asTypeOf(dut.io.ptagRecycle.bits)) - dut.io.ptagRecycle.bits.count.poke(1.U) - dut.io.ptagRecycle.bits.tokens(0).valid.poke(true.B) - dut.io.ptagRecycle.bits.tokens(0).ptag.poke(17.U) - dut.io.ptagRecycle.bits.tokens(0).generation.poke(3.U) - dut.io.ptagRecycle.valid.poke(true.B) - dut.io.ptagRecycle.ready.expect(true.B) - dut.clock.step() - dut.io.ptagRecycle.valid.poke(false.B) - - // A peer then owns the same numerical PTag with a new generation. The - // retained target mask must not clear this identity at common apply. - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.stid.poke(1.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(17.U) - wakeup.bits.ptagGeneration.poke(4.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - dut.io.recoveryPrepareReady.expect(true.B) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - - pokeTransaction(dut, stid = 1, ridSlot = 1, transactionId = 11, - entries = Vector(1), pSource = Some(17 -> 4)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() - dut.clock.step() - query(dut, 1) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(true.B) - - // The complementary positive case: when the killed producer still owns - // the exact captured identity at apply, its retained ready bit clears. - pokeTransaction(dut, stid = 0, ridSlot = 0, transactionId = 12, - entries = Vector(0), pDestination = Some(18 -> 2)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() - dut.clock.step() - - wakeup.bits.poke(0.U.asTypeOf(wakeup.bits)) - wakeup.bits.stid.poke(0.U) - wakeup.bits.epoch.poke(6.U) - wakeup.bits.operandClass.poke(OperandClass.P) - wakeup.bits.ptag.poke(18.U) - wakeup.bits.ptagGeneration.poke(2.U) - wakeup.valid.poke(true.B) - dut.clock.step() - wakeup.valid.poke(false.B) - - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 1, - survivingMembers = 0) - waitForPrepared(dut, { - query(dut, 1) - dut.io.queryPickable.expect(true.B) - }) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - - pokeTransaction(dut, stid = 1, ridSlot = 1, transactionId = 13, - entries = Vector(0), pSource = Some(18 -> 2)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() - dut.clock.step() - query(dut, 0) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(false.B) - } - } - - test("scans a non-default two-entry bank slice with exact latency") { - val wideScan = p.copy( - iqEntriesPerBank = 4, - iexRecoveryScanEntriesPerBankPerCycle = 2) - simulate(new OooIexIssue(wideScan)) { dut => - clear(dut) - pokeTransaction(dut, stid = 0, ridSlot = 0, transactionId = 20, - entries = Vector(2)) - dut.io.s1.ready.expect(true.B) - dut.clock.step() - dut.io.s1.valid.poke(false.B) - dut.clock.step() - query(dut, 2) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - - pokeRecovery(dut, stid = 0, ridSlot = 0, oldMembers = 1, - survivingMembers = 0) - waitForPrepared(dut, { - query(dut, 2) - dut.io.queryState.expect(OooIexIssueSlotState.BoundS2) - }, wideScan) - dut.io.recoveryPrepared.boundKilled.expect(1.U) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - query(dut, 2) - dut.io.queryState.expect(OooIexIssueSlotState.Free) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexStorePipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexStorePipelineSpec.scala index 5105cbfa..50a9be1c 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexStorePipelineSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexStorePipelineSpec.scala @@ -2,14 +2,17 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.log2Ceil +import chisel3.util.{Valid, log2Ceil} import linxcore.lsu.STQEntryBank +import linxcore.params.CoreParams +import linxcore.top.interface.{RecoveryCause, RecoveryPhase, RecoveryPlan} import org.scalatest.funsuite.AnyFunSuite class OooIexStoreStqHarnessIO( - val p: OooParams, + val core: CoreParams, val stqEntries: Int) extends Bundle { + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params val reserveValid = Input(Bool()) val reserveRow = Input(new OooIexIssueRow(p)) val reserveAccepted = Output(Bool()) @@ -22,8 +25,7 @@ class OooIexStoreStqHarnessIO( val stdReady = Output(Bool()) val stdRejected = Output(Bool()) val fillPermit = Input(Bool()) - val recoveryValid = Input(Bool()) - val recovery = Input(new OooResidencyRecoveryPlan(p)) + val recoveryApply = Input(Valid(new RecoveryPlan(core))) val addrReady = Output(UInt(stqEntries.W)) val dataReady = Output(UInt(stqEntries.W)) val addresses = Output(Vec(stqEntries, UInt(p.pcWidth.W))) @@ -37,13 +39,13 @@ class OooIexStoreStqHarnessIO( } class OooIexStoreStqHarness( - val p: OooParams, + val core: CoreParams, val stqEntries: Int = 4) extends Module { - val io = IO(new OooIexStoreStqHarnessIO(p, stqEntries)) + val p: OooParams = OooIexPhysicalProfile.fromCoreParams(core).params + val io = IO(new OooIexStoreStqHarnessIO(core, stqEntries)) val projection = Module(new OooStqReservationProjection(p, stqEntries)) - val recoveryProjection = Module(new OooStqRecoveryProjection(p, stqEntries)) - val pipeline = Module(new OooIexStorePipeline(p, stqEntries)) + val pipeline = Module(new OooIexStorePipeline(core, stqEntries)) val stq = Module(new STQEntryBank( entries = stqEntries, peIdWidth = p.peIdWidth, @@ -63,12 +65,8 @@ class OooIexStoreStqHarness( projection.io.inputValid := io.reserveValid projection.io.input := io.reserveRow stq.io.flush := 0.U.asTypeOf(stq.io.flush) - recoveryProjection.io.recoveryValid := io.recoveryValid - recoveryProjection.io.recovery := io.recovery - recoveryProjection.io.rows := stq.io.rows - stq.io.exactRecoveryValid := - io.recoveryValid && io.recovery.valid && !recoveryProjection.io.rejected - stq.io.exactRecoveryFreeMask := recoveryProjection.io.freeMask + stq.io.exactRecoveryValid := false.B + stq.io.exactRecoveryFreeMask := 0.U stq.io.insertValid := false.B stq.io.insert := 0.U.asTypeOf(stq.io.insert) stq.io.reserveValid := false.B @@ -93,8 +91,6 @@ class OooIexStoreStqHarness( leaseValid := true.B lease.valid := true.B lease.logicalMember := io.reserveRow.member - lease.logicalMember.memberIndex := - io.reserveRow.member.memberIndex - io.reserveRow.childIndex lease.requestCount := io.reserveRow.memoryOrder.requestCount lease.firstLsid := io.reserveRow.memoryOrder.firstLsid lease.firstStoreId := io.reserveRow.memoryOrder.firstTypeId @@ -107,8 +103,7 @@ class OooIexStoreStqHarness( pipeline.io.std.valid := io.stdValid && leaseValid pipeline.io.std.bits.execute := io.std pipeline.io.std.bits.lease := lease - pipeline.io.recoveryApply.valid := io.recoveryValid - pipeline.io.recoveryApply.bits := io.recovery + pipeline.io.recoveryApply := io.recoveryApply pipeline.io.loadCancel.foreach(cancel => cancel := 0.U.asTypeOf(cancel)) @@ -144,14 +139,15 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, tuRetireSourceDepthPerStid = 16, lsidWidth = 40) + private val core = OooRecoveryMembership.coreParams(p) private def pokeMember(member: RobMemberKey, memberIndex: Int): Unit = { member.poke(0.U.asTypeOf(member)) @@ -210,7 +206,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { pokeCommonRow( execute.i2.row, childIndex = if (addressHalf) 0 else 1, - memberIndex = if (addressHalf) 3 else 4, + memberIndex = 3, uopClass = if (addressHalf) OooUopClass.Agu else OooUopClass.Std) execute.i2.sourceMask.poke((if (addressHalf) 1 else 12).U) execute.i2.sourceData(0).poke(0x1000.U) @@ -219,7 +215,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { } test("retained STA and STD converge pair beats only through canonical STQ") { - simulate(new OooIexStoreStqHarness(p)) { dut => + simulate(new OooIexStoreStqHarness(core)) { dut => dut.io.reserveValid.poke(true.B) pokeCommonRow(dut.io.reserveRow, childIndex = 0, memberIndex = 3, uopClass = OooUopClass.Agu) @@ -228,8 +224,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.stdValid.poke(false.B) dut.io.std.poke(0.U.asTypeOf(dut.io.std)) dut.io.fillPermit.poke(true.B) - dut.io.recoveryValid.poke(false.B) - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) + dut.io.recoveryApply.poke(0.U.asTypeOf(dut.io.recoveryApply)) dut.io.reserveAccepted.expect(true.B) dut.clock.step() dut.io.reserveValid.poke(false.B) @@ -265,7 +260,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { } test("STD may finish before STA and retained fill survives STQ backpressure") { - simulate(new OooIexStoreStqHarness(p)) { dut => + simulate(new OooIexStoreStqHarness(core)) { dut => dut.io.reserveValid.poke(true.B) pokeCommonRow(dut.io.reserveRow, childIndex = 0, memberIndex = 3, uopClass = OooUopClass.Agu) @@ -274,8 +269,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.stdValid.poke(false.B) dut.io.std.poke(0.U.asTypeOf(dut.io.std)) dut.io.fillPermit.poke(false.B) - dut.io.recoveryValid.poke(false.B) - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) + dut.io.recoveryApply.poke(0.U.asTypeOf(dut.io.recoveryApply)) dut.io.reserveAccepted.expect(true.B) dut.clock.step() dut.io.reserveValid.poke(false.B) @@ -291,8 +285,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.dataReady.expect(0.U) dut.io.fillPermit.poke(true.B) - dut.io.recoveryValid.poke(false.B) - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) + dut.io.recoveryApply.poke(0.U.asTypeOf(dut.io.recoveryApply)) dut.clock.step(2) dut.io.occupied.expect(false.B) dut.io.addrReady.expect(0.U) @@ -310,7 +303,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { } test("wrong physical child member cannot mutate a reserved logical store") { - simulate(new OooIexStoreStqHarness(p)) { dut => + simulate(new OooIexStoreStqHarness(core)) { dut => dut.io.reserveValid.poke(true.B) pokeCommonRow(dut.io.reserveRow, childIndex = 0, memberIndex = 3, uopClass = OooUopClass.Agu) @@ -319,8 +312,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.stdValid.poke(false.B) dut.io.std.poke(0.U.asTypeOf(dut.io.std)) dut.io.fillPermit.poke(true.B) - dut.io.recoveryValid.poke(false.B) - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) + dut.io.recoveryApply.poke(0.U.asTypeOf(dut.io.recoveryApply)) dut.clock.step() dut.io.reserveValid.poke(false.B) @@ -338,8 +330,8 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { } } - test("exact recovery kills retained STD before any canonical fill") { - simulate(new OooIexStoreStqHarness(p)) { dut => + test("an accepted canonical Apply kills retained STD before any fill") { + simulate(new OooIexStoreStqHarness(core)) { dut => dut.io.reserveValid.poke(true.B) pokeCommonRow(dut.io.reserveRow, childIndex = 0, memberIndex = 3, uopClass = OooUopClass.Agu) @@ -348,8 +340,7 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.stdValid.poke(false.B) dut.io.std.poke(0.U.asTypeOf(dut.io.std)) dut.io.fillPermit.poke(false.B) - dut.io.recoveryValid.poke(false.B) - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) + dut.io.recoveryApply.poke(0.U.asTypeOf(dut.io.recoveryApply)) dut.clock.step() dut.io.reserveValid.poke(false.B) @@ -359,21 +350,30 @@ class OooIexStorePipelineSpec extends AnyFunSuite with ChiselSim { dut.io.stdValid.poke(false.B) dut.io.occupied.expect(true.B) - val recovery = dut.io.recovery + val recovery = dut.io.recoveryApply.bits recovery.poke(0.U.asTypeOf(recovery)) - recovery.valid.poke(true.B) - recovery.oldHead.valid.poke(true.B) - recovery.oldHead.peId.poke(1.U) - recovery.oldHead.stid.poke(1.U) - recovery.oldHead.ridSlot.poke(0.U) - recovery.oldHead.ridGeneration.poke(7.U) - recovery.oldOccupied.poke(8.U) - recovery.newOccupied.poke(2.U) - dut.io.recoveryValid.poke(true.B) + recovery.transactionId.poke(77.U) + recovery.phase.poke(RecoveryPhase.Apply) + recovery.cause.poke(RecoveryCause.Branch) + for (identity <- Seq(recovery.trigger, recovery.firstKilled, + recovery.lastKilled)) { + identity.peId.poke(1.U) + identity.stid.poke(1.U) + identity.ridSlot.poke(6.U) + identity.ridGeneration.poke(7.U) + identity.memberIndex.poke(3.U) + identity.residentGeneration.poke(9.U) + identity.bid.poke(0x93.U) + identity.brobGeneration.poke(8.U) + } + recovery.firstKilledValid.poke(true.B) + recovery.killedGroupCount.poke(1.U) + recovery.killedMemberCount.poke(1.U) + dut.io.recoveryApply.valid.poke(true.B) dut.io.occupied.expect(false.B) dut.clock.step() - dut.io.residentCount.expect(0.U) - dut.io.recoveryValid.poke(false.B) + dut.io.residentCount.expect(2.U) + dut.io.recoveryApply.valid.poke(false.B) dut.io.fillPermit.poke(true.B) dut.clock.step(2) dut.io.occupied.expect(false.B) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala index 4549a39f..95e519db 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala @@ -2,6 +2,8 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim +import linxcore.top.interface.{RecoveryCause, RecoveryPhase, RecoveryPlan, + RobIdentity} import org.scalatest.funsuite.AnyFunSuite class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { @@ -13,27 +15,29 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dispatchWidth = 4, retireGroupWidth = 2, robGroupsPerStid = 8, - robBankCount = 2, + robBankCount = 4, robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, tuRetireSourceDepthPerStid = 32, lsidWidth = 40) + private val core = OooRecoveryMembership.coreParams(p) private def pokeMember( member: RobMemberKey, memberIndex: Int, - ridSlot: Int): Unit = { + ridSlot: Int, + stid: Int = 1): Unit = { member.poke(0.U.asTypeOf(member)) member.group.valid.poke(true.B) member.group.peId.poke(1.U) - member.group.stid.poke(1.U) + member.group.stid.poke(stid.U) member.group.ridSlot.poke(ridSlot.U) member.group.ridGeneration.poke(7.U) member.bid.valid.poke(true.B) @@ -49,13 +53,14 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { ridSlot: Int, firstLsid: BigInt, firstStoreId: BigInt, - requestCount: Int = 1): Unit = { + requestCount: Int = 1, + stid: Int = 1): Unit = { row.poke(0.U.asTypeOf(row)) row.schedule.valid.poke(true.B) row.schedule.peId.poke(1.U) - row.schedule.stid.poke(1.U) + row.schedule.stid.poke(stid.U) row.schedule.childIndex.poke(0.U) - pokeMember(row.schedule.member, memberIndex, ridSlot) + pokeMember(row.schedule.member, memberIndex, ridSlot, stid) row.schedule.reservation.valid.poke(true.B) row.schedule.reservation.uopClass.poke(OooUopClass.Agu) row.payload.recipe.valid.poke(true.B) @@ -95,7 +100,7 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { execute.ownerClass.poke( (if (addressHalf) OooUopClass.Agu else OooUopClass.Std)) pokeStoreRow(execute.i2.row, - memberIndex = memberIndex + (if (addressHalf) 0 else 1), + memberIndex = memberIndex, ridSlot = ridSlot, firstLsid = firstLsid, firstStoreId = firstStoreId, @@ -114,8 +119,10 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { } private def defaults(dut: OooIexStoreStqFabric): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) + dut.io.reserve.foreach { reserve => + reserve.valid.poke(false.B) + reserve.bits.poke(0.U.asTypeOf(reserve.bits)) + } for (lane <- 0 until 2) { dut.io.storeAddress(lane).valid.poke(false.B) dut.io.storeAddress(lane).bits.poke( @@ -124,10 +131,16 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dut.io.storeData(lane).bits.poke( 0.U.asTypeOf(dut.io.storeData(lane).bits)) } - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) dut.io.loadCancel.foreach(_.poke(0.U.asTypeOf( dut.io.loadCancel.head))) dut.io.loadForwardQuery.foreach { query => @@ -135,10 +148,73 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { query.bits.poke(0.U.asTypeOf(query.bits)) } dut.io.loadForwardResponse.foreach(_.ready.poke(true.B)) + dut.io.lateStaPermit.poke(true.B) dut.io.markCommitValid.poke(false.B) dut.io.markCommitIndex.poke(0.U) dut.io.commitFreeMaskValid.poke(false.B) dut.io.commitFreeMask.poke(0.U) + dut.io.completion.ready.poke(false.B) + } + + test("W4 atomically reserves both active store lanes in the canonical STQ") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 8)) { dut => + defaults(dut) + pokeStoreRow(dut.io.reserve(0).bits, memberIndex = 0, ridSlot = 0, + firstLsid = 20, firstStoreId = 30, requestCount = 1, stid = 1) + pokeStoreRow(dut.io.reserve(1).bits, memberIndex = 0, ridSlot = 1, + firstLsid = 21, firstStoreId = 31, requestCount = 1, stid = 1) + dut.io.reserve.foreach(_.valid.poke(true.B)) + dut.io.reserve.foreach(_.ready.expect(true.B)) + dut.io.reserveAccepted.expect(true.B) + dut.clock.step() + dut.io.reserve.foreach(_.valid.poke(false.B)) + dut.io.residentCount.expect(2.U) + dut.io.rows(0).exactOwner.ridSlot.expect(0.U) + dut.io.rows(1).exactOwner.ridSlot.expect(1.U) + } + } + + test("retains an address fill until its late STA side effect is permitted") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => + defaults(dut) + reserve(dut, 2, 2, BigInt("100000041", 16), + BigInt("200000041", 16)) + + dut.io.lateStaPermit.poke(false.B) + pokeExecute(dut.io.storeAddress(0).bits, addressHalf = true, + 2, 2, BigInt("100000041", 16), BigInt("200000041", 16)) + dut.io.storeAddress(0).valid.poke(true.B) + dut.io.storeAddress(0).ready.expect(true.B) + dut.clock.step() + dut.io.storeAddress(0).valid.poke(false.B) + + dut.io.lateStaCandidate.valid.expect(true.B) + dut.io.lateStaCandidate.bits.addr.expect(0x1210.U) + dut.io.lateStaProbe.valid.expect(false.B) + dut.clock.step(2) + dut.io.lateStaCandidate.valid.expect(true.B) + dut.io.addrReadyMask.expect(0.U) + + dut.io.lateStaPermit.poke(true.B) + dut.io.lateStaProbe.valid.expect(true.B) + dut.clock.step() + dut.io.addrReadyMask.expect(1.U) + } + } + + private def pokeLoadIdentity( + query: linxcore.lsu.STQLoadForwardQuery, + token: Int, + pipeIndex: Int): Unit = { + query.loadId.valid.poke(true.B) + query.loadId.slot.poke((token & 3).U) + query.loadId.generation.poke((token & 1).U) + query.attempt.valid.poke(true.B) + query.attempt.producer.valid.poke(true.B) + query.attempt.producer.nativeBidValid.poke(true.B) + query.attempt.producer.stid.poke(1.U) + query.attempt.generation.poke(token.U) + query.returnPipeIndex.poke(pipeIndex.U) } private def reserve( @@ -147,22 +223,60 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { ridSlot: Int, firstLsid: BigInt, firstStoreId: BigInt, - requestCount: Int = 1): Unit = { - pokeStoreRow(dut.io.reserve.bits, memberIndex, ridSlot, - firstLsid, firstStoreId, requestCount) - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(true.B) + requestCount: Int = 1, + stid: Int = 1): Unit = { + pokeStoreRow(dut.io.reserve.head.bits, memberIndex, ridSlot, + firstLsid, firstStoreId, requestCount, stid) + dut.io.reserve.head.valid.poke(true.B) + dut.io.reserve.head.ready.expect(true.B) dut.io.reserveAccepted.expect(true.B) dut.clock.step() - dut.io.reserve.valid.poke(false.B) + dut.io.reserve.head.valid.poke(false.B) + } + + private def pokeIdentity( + identity: RobIdentity, + memberIndex: Int, + ridSlot: Int, + stid: Int = 1): Unit = { + identity.poke(0.U.asTypeOf(identity)) + identity.peId.poke(1.U) + identity.stid.poke(stid.U) + identity.ridSlot.poke(ridSlot.U) + identity.ridGeneration.poke(7.U) + identity.memberIndex.poke(memberIndex.U) + identity.residentGeneration.poke(9.U) + identity.bid.poke(0x93.U) + identity.brobGeneration.poke(8.U) + } + + private def pokeRecoveryPlan( + plan: RecoveryPlan, + phase: RecoveryPhase.Type, + transactionId: Int, + memberIndex: Int, + ridSlot: Int, + stid: Int = 1, + lastMemberIndex: Int = -1): Unit = { + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(transactionId.U) + plan.phase.poke(phase) + plan.cause.poke(RecoveryCause.Branch) + pokeIdentity(plan.trigger, memberIndex, ridSlot, stid) + plan.firstKilledValid.poke(true.B) + pokeIdentity(plan.firstKilled, memberIndex, ridSlot, stid) + val finalMember = if (lastMemberIndex < 0) memberIndex else lastMemberIndex + pokeIdentity(plan.lastKilled, finalMember, ridSlot, stid) + plan.killedGroupCount.poke(1.U) + plan.killedMemberCount.poke((finalMember - memberIndex + 1).U) } test("two logical stores keep independent leases across crossed STA STD lanes") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) reserve(dut, 2, 2, BigInt("100000001", 16), BigInt("200000001", 16)) - reserve(dut, 4, 3, BigInt("100000002", 16), + reserve(dut, 1, 3, BigInt("100000002", 16), BigInt("200000002", 16)) dut.io.residentCount.expect(2.U) @@ -185,7 +299,7 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dut.io.lateStaProbe.bits.stid.expect(1.U) dut.io.lateStaProbe.bits.tid.expect(1.U) dut.io.lateStaProbe.bits.bid.valid.expect(true.B) - dut.io.lateStaProbe.bits.bid.value.expect(3.U) + dut.io.lateStaProbe.bits.bid.value.expect(0x13.U) dut.io.lateStaProbe.bits.bid.wrap.expect(false.B) dut.io.lateStaProbe.bits.gid.valid.expect(true.B) dut.io.lateStaProbe.bits.gid.value.expect(2.U) @@ -212,10 +326,11 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { val loadQuery = dut.io.loadForwardQuery(0) loadQuery.bits.poke(0.U.asTypeOf(loadQuery.bits)) loadQuery.bits.token.poke(0x55.U) + pokeLoadIdentity(loadQuery.bits, 0x55, pipeIndex = 0) loadQuery.bits.stid.poke(1.U) loadQuery.bits.loadBid.valid.poke(true.B) loadQuery.bits.loadBid.wrap.poke(false.B) - loadQuery.bits.loadBid.value.poke(3.U) + loadQuery.bits.loadBid.value.poke(0x13.U) loadQuery.bits.loadLsIdFullValid.poke(true.B) loadQuery.bits.loadLsIdFull.poke(BigInt("100000002", 16).U) loadQuery.bits.address.poke(0x1210.U) @@ -234,9 +349,9 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dut.io.loadForwardResponse(0).bits.blocked.expect(false.B) pokeExecute(dut.io.storeData(0).bits, addressHalf = false, - 4, 3, BigInt("100000002", 16), BigInt("200000002", 16)) + 1, 3, BigInt("100000002", 16), BigInt("200000002", 16)) pokeExecute(dut.io.storeAddress(1).bits, addressHalf = true, - 4, 3, BigInt("100000002", 16), BigInt("200000002", 16)) + 1, 3, BigInt("100000002", 16), BigInt("200000002", 16)) dut.io.storeData(0).valid.poke(true.B) dut.io.storeAddress(1).valid.poke(true.B) dut.io.storeData(0).ready.expect(true.B) @@ -251,18 +366,62 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { } } + test("joined STA and STD publish one retained exact ROB completion") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => + defaults(dut) + reserve(dut, memberIndex = 2, ridSlot = 3, + firstLsid = 41, firstStoreId = 51) + + pokeExecute(dut.io.storeAddress(0).bits, addressHalf = true, + memberIndex = 2, ridSlot = 3, firstLsid = 41, firstStoreId = 51) + pokeExecute(dut.io.storeData(1).bits, addressHalf = false, + memberIndex = 2, ridSlot = 3, firstLsid = 41, firstStoreId = 51) + dut.io.storeAddress(0).valid.poke(true.B) + dut.io.storeData(1).valid.poke(true.B) + dut.io.storeAddress(0).ready.expect(true.B) + dut.io.storeData(1).ready.expect(true.B) + dut.clock.step() + dut.io.storeAddress(0).valid.poke(false.B) + dut.io.storeData(1).valid.poke(false.B) + + var cycles = 0 + while (!dut.io.completion.valid.peek().litToBoolean && cycles < 12) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 12, + "canonical STQ join must retain completion after both halves arrive") + dut.io.completion.bits.rob.peId.expect(1.U) + dut.io.completion.bits.rob.stid.expect(1.U) + dut.io.completion.bits.rob.ridSlot.expect(3.U) + dut.io.completion.bits.rob.ridGeneration.expect(7.U) + dut.io.completion.bits.rob.memberIndex.expect(2.U) + dut.io.completion.bits.rob.residentGeneration.expect(9.U) + dut.io.completion.bits.rob.bid.expect(0x93.U) + dut.io.completion.bits.rob.brobGeneration.expect(8.U) + dut.clock.step(2) + dut.io.completion.valid.expect(true.B) + + dut.io.completion.ready.poke(true.B) + dut.clock.step() + dut.io.completion.ready.poke(false.B) + dut.clock.step(2) + dut.io.completion.valid.expect(false.B) + } + } + test("both STD lanes write independent physical data-bank ports in one cycle") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) reserve(dut, 2, 2, BigInt("100000011", 16), BigInt("200000011", 16)) - reserve(dut, 4, 3, BigInt("100000012", 16), + reserve(dut, 1, 3, BigInt("100000012", 16), BigInt("200000012", 16)) pokeExecute(dut.io.storeData(0).bits, addressHalf = false, 2, 2, BigInt("100000011", 16), BigInt("200000011", 16)) pokeExecute(dut.io.storeData(1).bits, addressHalf = false, - 4, 3, BigInt("100000012", 16), BigInt("200000012", 16)) + 1, 3, BigInt("100000012", 16), BigInt("200000012", 16)) dut.io.storeData(0).valid.poke(true.B) dut.io.storeData(1).valid.poke(true.B) dut.io.storeData(0).ready.expect(true.B) @@ -281,10 +440,10 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { } test("unreserved execution is retained upstream and cannot allocate by CAM") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) pokeExecute(dut.io.storeAddress(0).bits, addressHalf = true, - 6, 4, BigInt("100000003", 16), BigInt("200000003", 16)) + 2, 4, BigInt("100000003", 16), BigInt("200000003", 16)) dut.io.storeAddress(0).valid.poke(true.B) dut.io.storeAddress(0).ready.expect(false.B) dut.io.leaseLookupRejected(0).expect(true.B) @@ -296,8 +455,40 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { } } + test("STD child one may share ROB member zero but mismatched child or member is rejected") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => + defaults(dut) + val firstLsid = BigInt("100000020", 16) + val firstStoreId = BigInt("200000020", 16) + reserve(dut, memberIndex = 0, ridSlot = 5, + firstLsid = firstLsid, firstStoreId = firstStoreId) + + val data = dut.io.storeData(0) + pokeExecute(data.bits, addressHalf = false, + memberIndex = 0, ridSlot = 5, + firstLsid = firstLsid, firstStoreId = firstStoreId) + data.bits.i2.row.schedule.childIndex.poke(0.U) + data.valid.poke(true.B) + data.ready.expect(false.B) + dut.io.leaseLookupRejected(2).expect(true.B) + + data.bits.i2.row.schedule.childIndex.poke(1.U) + data.bits.i2.row.schedule.member.memberIndex.poke(1.U) + data.ready.expect(false.B) + dut.io.leaseLookupRejected(2).expect(true.B) + + data.bits.i2.row.schedule.member.memberIndex.poke(0.U) + data.ready.expect(true.B) + dut.io.leaseLookupRejected(2).expect(false.B) + dut.clock.step() + data.valid.poke(false.B) + dut.clock.step(4) + dut.io.dataReadyMask.expect(1.U) + } + } + test("one recovery plan cancels retained STD and frees its exact STQ lease") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) reserve(dut, 3, 6, BigInt("100000010", 16), BigInt("200000010", 16), requestCount = 2) @@ -310,29 +501,27 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dut.io.storeData(0).valid.poke(false.B) dut.io.storePipelinesOccupied.expect(1.U) - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(1.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(7.U) - plan.oldOccupied.poke(8.U) - plan.newOccupied.poke(2.U) - dut.io.recoveryPrepare.valid.poke(true.B) - dut.io.recoveryPrepareReady.expect(true.B) + pokeRecoveryPlan(dut.io.recovery.prepare.bits, + RecoveryPhase.Prepare, transactionId = 91, + memberIndex = 3, ridSlot = 6) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) dut.io.lateStaProbe.valid.expect(false.B) dut.io.recoveryFreeMask.expect(3.U) dut.io.recoveryApplied.expect(false.B) dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) dut.io.residentCount.expect(2.U) dut.io.storePipelinesOccupied.expect(1.U) - dut.io.recoveryFire.poke(true.B) + dut.io.recovery.prepared.valid.expect(true.B) + dut.clock.step() + pokeRecoveryPlan(dut.io.recovery.apply.bits, + RecoveryPhase.Apply, transactionId = 91, + memberIndex = 3, ridSlot = 6) + dut.io.recovery.apply.valid.poke(true.B) dut.io.recoveryApplied.expect(true.B) dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) dut.io.residentCount.expect(0.U) dut.io.storePipelinesOccupied.expect(0.U) dut.clock.step(2) @@ -340,57 +529,86 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { } } - test("recovery prepare fences mutation and rejects a split-store partial cut") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + test("recovery Prepare fences its STID and matching Abort preserves rows") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) reserve(dut, 0, 5, BigInt("100000020", 16), BigInt("200000020", 16)) - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.oldHead.valid.poke(true.B) - plan.oldHead.peId.poke(1.U) - plan.oldHead.stid.poke(1.U) - plan.oldHead.ridSlot.poke(0.U) - plan.oldHead.ridGeneration.poke(7.U) - plan.oldOccupied.poke(8.U) - plan.newOccupied.poke(1.U) - plan.pivotOffset.poke(0.U) - pokeMember(plan.pivot, memberIndex = 0, ridSlot = 5) - plan.pivotPhysicalMemberCount.poke(2.U) - plan.survivingPivotValid.poke(true.B) - plan.survivingPivotPhysicalMemberCount.poke(1.U) - dut.io.recoveryPrepare.valid.poke(true.B) - - dut.io.recoveryPrepareReady.expect(false.B) + pokeRecoveryPlan(dut.io.recovery.prepare.bits, + RecoveryPhase.Prepare, transactionId = 92, + memberIndex = 0, ridSlot = 5) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) dut.io.lateStaProbe.valid.expect(false.B) - dut.io.recoveryPartialStoreCut.expect(true.B) - dut.io.recoveryRejected.expect(true.B) - dut.io.recoveryFreeMask.expect(0.U) + dut.io.recoveryRejected.expect(false.B) + dut.io.recoveryFreeMask.expect(1.U) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) - pokeStoreRow(dut.io.reserve.bits, 2, 6, + pokeStoreRow(dut.io.reserve.head.bits, 2, 6, BigInt("100000021", 16), BigInt("200000021", 16)) - dut.io.reserve.valid.poke(true.B) - dut.io.reserve.ready.expect(false.B) + dut.io.reserve.head.valid.poke(true.B) + dut.io.reserve.head.ready.expect(false.B) dut.io.markCommitValid.poke(true.B) dut.io.markCommitIndex.poke(0.U) dut.io.markCommitAccepted.expect(false.B) dut.io.commitFreeMaskValid.poke(true.B) dut.io.commitFreeMask.poke(1.U) dut.io.commitFreeAcceptedMask.expect(0.U) - dut.clock.step(2) + dut.clock.step() dut.io.residentCount.expect(1.U) - dut.io.reserve.valid.poke(false.B) + dut.io.reserve.head.valid.poke(false.B) dut.io.markCommitValid.poke(false.B) dut.io.commitFreeMaskValid.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) + pokeRecoveryPlan(dut.io.recovery.abort.bits, + RecoveryPhase.Abort, transactionId = 92, + memberIndex = 0, ridSlot = 5) + dut.io.recovery.abort.valid.poke(true.B) + dut.clock.step() + dut.io.recovery.abort.valid.poke(false.B) + dut.io.residentCount.expect(1.U) + pokeStoreRow(dut.io.reserve.head.bits, 2, 6, + BigInt("100000021", 16), BigInt("200000021", 16)) + dut.io.reserve.head.valid.poke(true.B) + dut.io.reserve.head.ready.expect(true.B) + } + } + + test("peer STID reservation survives and progresses across target Apply") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => + defaults(dut) + reserve(dut, 0, 5, BigInt("100000050", 16), + BigInt("200000050", 16), stid = 1) + + pokeRecoveryPlan(dut.io.recovery.prepare.bits, + RecoveryPhase.Prepare, transactionId = 93, + memberIndex = 0, ridSlot = 5, stid = 1) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + reserve(dut, 1, 2, BigInt("100000051", 16), + BigInt("200000051", 16), stid = 0) + dut.io.residentCount.expect(2.U) + + pokeRecoveryPlan(dut.io.recovery.apply.bits, + RecoveryPhase.Apply, transactionId = 93, + memberIndex = 0, ridSlot = 5, stid = 1) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.recoveryApplied.expect(true.B) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + dut.io.residentCount.expect(1.U) + dut.io.rows(1).valid.expect(true.B) + dut.io.rows(1).stid.expect(0.U) } } - test("cross-line stores block only overlapping production load queries") { - simulate(new OooIexStoreStqFabric(p, stqEntries = 4)) { dut => + test("cross-line stores block only overlapping load queries") { + simulate(new OooIexStoreStqFabric(core, stqEntries = 4)) { dut => defaults(dut) val storeLsid = BigInt("100000030", 16) reserve(dut, 2, 2, storeLsid, BigInt("200000030", 16)) @@ -410,9 +628,10 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { val query = dut.io.loadForwardQuery(0) query.bits.poke(0.U.asTypeOf(query.bits)) query.bits.token.poke(0x61.U) + pokeLoadIdentity(query.bits, 0x61, pipeIndex = 0) query.bits.stid.poke(1.U) query.bits.loadBid.valid.poke(true.B) - query.bits.loadBid.value.poke(4.U) + query.bits.loadBid.value.poke(0x14.U) query.bits.loadLsIdFullValid.poke(true.B) query.bits.loadLsIdFull.poke((storeLsid + 1).U) query.bits.address.poke(0x123e.U) @@ -427,6 +646,7 @@ class OooIexStoreStqFabricSpec extends AnyFunSuite with ChiselSim { dut.io.loadForwardResponse(0).bits.blocked.expect(true.B) query.bits.token.poke(0x62.U) + pokeLoadIdentity(query.bits, 0x62, pipeIndex = 0) query.bits.address.poke(0x1200.U) query.bits.size.poke(8.U) query.valid.poke(true.B) diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala index 52d90401..c20f2eb0 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala @@ -1,32 +1,89 @@ package linxcore.ooo import chisel3._ +import chisel3.util.{Decoupled, DecoupledIO, Valid} import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.DestinationKind +import linxcore.common.{DestinationKind, OperandClass} +import linxcore.frontend.FrontendOpcodeDecodeTable +import linxcore.params.{CoreParams, SimulationParamProfiles} +import linxcore.top.interface.{RecoveryCause, RobResolveTxn} import org.scalatest.funsuite.AnyFunSuite +private class OooIexAluTerminalHarnessIO(val core: CoreParams) extends Bundle { + val p = OooIexPhysicalProfile.fromCoreParams(core).params + private val publicationPorts = p.iexTerminalWidth * p.maxDestinationOperands + val e1 = Flipped(Decoupled(new OooIexExecuteTransaction(p))) + val pWrite = Vec(publicationPorts, Decoupled(new OooIexPFileWrite(p))) + val tWrite = Vec(publicationPorts, Decoupled(new OooIexLocalFileWrite(p))) + val uWrite = Vec(publicationPorts, Decoupled(new OooIexLocalFileWrite(p))) + val wakeup = Vec(publicationPorts, Decoupled(new OooIexWakeup(p))) + val bctrl = Vec(p.iexTerminalWidth, + Decoupled(new OooIexTerminalBctrl(p))) + val trace = Vec(p.iexTerminalWidth, + Decoupled(new OooIexTerminalTrace(p))) + val robResolve = Vec(p.iexTerminalWidth, + Decoupled(new RobResolveTxn(core))) + val terminalFireMask = Output(UInt(p.iexTerminalWidth.W)) + val retainedW2 = Valid(new OooIexAluTerminalTransaction(p)) + val w1Occupied = Output(Bool()) + val w2Occupied = Output(Bool()) +} + +private class OooIexAluTerminalHarness(val core: CoreParams) extends Module { + val p = OooIexPhysicalProfile.fromCoreParams(core).params + val io = IO(new OooIexAluTerminalHarnessIO(core)) + + val alu = Module(new OooIexAluPipeline(p, core)) + val terminal = Module(new OooIexTerminalFabric( + core, aluSourceCount = 1, bruSourceCount = 1, loadSourceCount = 1)) + terminal.io.recoveryEvent.foreach(_.ready := true.B) + terminal.io.recovery.prepare.valid := false.B + terminal.io.recovery.prepare.bits := + 0.U.asTypeOf(terminal.io.recovery.prepare.bits) + terminal.io.recovery.prepared.ready := true.B + terminal.io.recovery.apply.valid := false.B + terminal.io.recovery.apply.bits := + 0.U.asTypeOf(terminal.io.recovery.apply.bits) + terminal.io.recovery.abort.valid := false.B + terminal.io.recovery.abort.bits := + 0.U.asTypeOf(terminal.io.recovery.abort.bits) + + alu.io.e1.valid := io.e1.valid + alu.io.e1.bits := io.e1.bits + io.e1.ready := alu.io.e1.ready + alu.io.recoveryApply.valid := false.B + alu.io.recoveryApply.bits := 0.U.asTypeOf(alu.io.recoveryApply.bits) + alu.io.loadCancel.foreach(_ := 0.U.asTypeOf(alu.io.loadCancel.head)) + terminal.io.alu(0) <> alu.io.w2 + terminal.io.bru(0).valid := false.B + terminal.io.bru(0).bits := 0.U.asTypeOf(terminal.io.bru(0).bits) + terminal.io.load(0).valid := false.B + terminal.io.load(0).bits := 0.U.asTypeOf(terminal.io.load(0).bits) + + def forward[T <: Data](outer: DecoupledIO[T], inner: DecoupledIO[T]): Unit = { + outer.valid := inner.valid + outer.bits := inner.bits + inner.ready := outer.ready + } + io.pWrite.zip(terminal.io.pWrite).foreach { case (o, i) => forward(o, i) } + io.tWrite.zip(terminal.io.tWrite).foreach { case (o, i) => forward(o, i) } + io.uWrite.zip(terminal.io.uWrite).foreach { case (o, i) => forward(o, i) } + io.wakeup.zip(terminal.io.wakeup).foreach { case (o, i) => forward(o, i) } + io.bctrl.zip(terminal.io.bctrl).foreach { case (o, i) => forward(o, i) } + io.trace.zip(terminal.io.trace).foreach { case (o, i) => forward(o, i) } + io.robResolve.zip(terminal.io.robResolve).foreach { + case (o, i) => forward(o, i) + } + io.terminalFireMask := terminal.io.terminalFireMask + io.retainedW2.valid := alu.io.w2.valid + io.retainedW2.bits := alu.io.w2.bits + io.w1Occupied := alu.io.w1Occupied + io.w2Occupied := alu.io.w2Occupied +} + class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - iexIssueDomainCount = 6, - iexReleaseWidth = 6, - tuRetireSourceDepthPerStid = 16) + private val core = SimulationParamProfiles.W4 + private val p = OooIexPhysicalProfile.fromCoreParams(core).params private def clear(dut: OooIexTerminalFabric): Unit = { dut.io.alu.foreach { source => @@ -47,23 +104,82 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { dut.io.wakeup.foreach(_.ready.poke(true.B)) dut.io.bctrl.foreach(_.ready.poke(true.B)) dut.io.trace.foreach(_.ready.poke(true.B)) - dut.io.completion.foreach(_.ready.poke(true.B)) + dut.io.robResolve.foreach(_.ready.poke(true.B)) + dut.io.recoveryEvent.foreach(_.ready.poke(true.B)) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) } private def pokeMember(target: RobMemberKey, ridSlot: Int): Unit = { target.poke(0.U.asTypeOf(target)) target.group.valid.poke(true.B) target.group.peId.poke(3.U) - target.group.stid.poke(1.U) + target.group.stid.poke(0.U) target.group.ridSlot.poke(ridSlot.U) target.group.ridGeneration.poke(1.U) target.bid.valid.poke(true.B) - target.bid.value.poke(5.U) + target.bid.value.poke(2.U) target.brobGeneration.poke(2.U) target.memberIndex.poke(0.U) target.residentGeneration.poke(4.U) } + private def expectRetainedMember(target: RobMemberKey): Unit = { + target.group.valid.expect(true.B) + target.group.peId.expect(3.U) + target.group.stid.expect(0.U) + target.group.ridSlot.expect(3.U) + target.group.ridGeneration.expect(1.U) + target.bid.valid.expect(true.B) + target.bid.value.expect(2.U) + target.brobGeneration.expect(2.U) + target.memberIndex.expect(0.U) + target.residentGeneration.expect(4.U) + } + + private def expectRetainedDestination( + destination: OooIexDestinationState): Unit = { + destination.valid.expect(true.B) + destination.kind.expect(DestinationKind.Gpr) + destination.atag.expect(6.U) + destination.ptag.expect(27.U) + destination.ptagGeneration.expect(3.U) + destination.localTag.expect(0.U) + destination.localSequence.valid.expect(false.B) + destination.localSequence.index.expect(0.U) + destination.localSequence.generation.expect(0.U) + } + + private def expectEmptyMember(target: RobMemberKey): Unit = { + target.group.valid.expect(false.B) + target.group.peId.expect(0.U) + target.group.stid.expect(0.U) + target.group.ridSlot.expect(0.U) + target.group.ridGeneration.expect(0.U) + target.bid.valid.expect(false.B) + target.bid.value.expect(0.U) + target.brobGeneration.expect(0.U) + target.memberIndex.expect(0.U) + target.residentGeneration.expect(0.U) + } + + private def expectEmptyLoad(load: OooIexLoadGeneration): Unit = { + load.valid.expect(false.B) + expectEmptyMember(load.producer) + load.transaction.value.expect(0.U) + load.transaction.generation.expect(0.U) + load.generation.expect(0.U) + } + private def pokeAlu( dut: OooIexTerminalFabric, source: Int, @@ -78,7 +194,7 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { val row = execute.i2.row.schedule row.valid.poke(true.B) row.peId.poke(3.U) - row.stid.poke(1.U) + row.stid.poke(0.U) row.epoch.poke(9.U) pokeMember(row.member, ridSlot) row.reservation.valid.poke(true.B) @@ -92,7 +208,7 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) payload.uopKey.primaryParent.valid.poke(true.B) payload.uopKey.primaryParent.peId.poke(3.U) - payload.uopKey.primaryParent.stid.poke(1.U) + payload.uopKey.primaryParent.stid.poke(0.U) payload.uopKey.primaryParent.instructionId.poke((40 + ridSlot).U) payload.uopKey.uopCount.poke(1.U) @@ -110,8 +226,111 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { dut.io.alu(source).valid.poke(true.B) } + private def pokeDirectJump( + dut: OooIexTerminalFabric, + source: Int, + ridSlot: Int, + target: BigInt): Unit = { + val terminal = dut.io.bru(source).bits + terminal.poke(0.U.asTypeOf(terminal)) + val execute = terminal.execute + execute.ownerClass.poke(OooUopClass.Bru) + val row = execute.i2.row.schedule + row.valid.poke(true.B) + row.peId.poke(3.U) + row.stid.poke(0.U) + row.epoch.poke(9.U) + row.transactionId.poke(71.U) + pokeMember(row.member, ridSlot) + row.reservation.valid.poke(true.B) + row.reservation.uopClass.poke(OooUopClass.Bru) + val payload = execute.i2.row.payload + payload.opcode.poke(FrontendOpcodeDecodeTable.OP_J.U) + payload.recipe.valid.poke(true.B) + payload.recipe.opcode.poke(FrontendOpcodeDecodeTable.OP_J.U) + payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + payload.recipe.dispatchClass.poke(OooDispatchClass.Bru.U) + payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Bctrl.U) + payload.uopKey.primaryParent.valid.poke(true.B) + payload.uopKey.primaryParent.peId.poke(3.U) + payload.uopKey.primaryParent.stid.poke(0.U) + payload.uopKey.primaryParent.instructionId.poke(71.U) + payload.uopKey.primaryParent.epoch.poke(9.U) + payload.uopKey.uopCount.poke(1.U) + terminal.bctrl.valid.poke(true.B) + terminal.bctrl.kind.poke(OooIexBctrlUpdateKind.Target) + terminal.bctrl.targetValid.poke(true.B) + terminal.bctrl.target.poke(target.U) + dut.io.bru(source).valid.poke(true.B) + } + + private def clearHarness(dut: OooIexAluTerminalHarness): Unit = { + dut.io.e1.valid.poke(false.B) + dut.io.e1.bits.poke(0.U.asTypeOf(dut.io.e1.bits)) + dut.io.pWrite.foreach(_.ready.poke(true.B)) + dut.io.tWrite.foreach(_.ready.poke(true.B)) + dut.io.uWrite.foreach(_.ready.poke(true.B)) + dut.io.wakeup.foreach(_.ready.poke(true.B)) + dut.io.bctrl.foreach(_.ready.poke(true.B)) + dut.io.trace.foreach(_.ready.poke(true.B)) + dut.io.robResolve.foreach(_.ready.poke(true.B)) + } + + private def pokeHarnessExecute(dut: OooIexAluTerminalHarness): Unit = { + val execute = dut.io.e1.bits + execute.poke(0.U.asTypeOf(execute)) + execute.ownerClass.poke(OooUopClass.Alu) + execute.ownerLane.poke(0.U) + execute.slotGeneration.poke(7.U) + val i2 = execute.i2 + val row = i2.row.schedule + row.valid.poke(true.B) + row.peId.poke(3.U) + row.stid.poke(0.U) + row.epoch.poke(9.U) + row.transactionId.poke(43.U) + pokeMember(row.member, ridSlot = 3) + row.reservation.valid.poke(true.B) + row.reservation.uopClass.poke(OooUopClass.Alu) + row.reservation.bank.poke(0.U) + row.reservation.writePort.poke(0.U) + row.reservation.speculativeSlot.poke(1.U) + row.reservation.reservationEpoch.poke(9.U) + row.inFlight.poke(true.B) + row.sources(0).valid.poke(true.B) + row.sources(0).ready.poke(true.B) + row.sources(0).operandClass.poke(OperandClass.P) + row.sources(0).ptag.poke(17.U) + row.sources(0).ptagGeneration.poke(3.U) + i2.sourceMask.poke(1.U) + i2.sourceData(0).poke(41.U) + val payload = i2.row.payload + payload.opcode.poke(FrontendOpcodeDecodeTable.OP_ADDI.U) + payload.recipe.valid.poke(true.B) + payload.recipe.opcode.poke(FrontendOpcodeDecodeTable.OP_ADDI.U) + payload.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) + payload.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) + payload.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) + payload.recipe.pSourceCount.poke(1.U) + payload.recipe.pDestinationCount.poke(1.U) + payload.immediateValid.poke(true.B) + payload.immediate.poke(1.U) + payload.uopKey.primaryParent.valid.poke(true.B) + payload.uopKey.primaryParent.peId.poke(3.U) + payload.uopKey.primaryParent.stid.poke(0.U) + payload.uopKey.primaryParent.instructionId.poke(43.U) + payload.uopKey.uopCount.poke(1.U) + row.destinations(0).valid.poke(true.B) + row.destinations(0).kind.poke(DestinationKind.Gpr) + row.destinations(0).atag.poke(6.U) + row.destinations(0).ptag.poke(27.U) + row.destinations(0).ptagGeneration.poke(3.U) + dut.io.e1.valid.poke(true.B) + } + test("publishes two independent terminal lanes in the same cycle") { - simulate(new OooIexTerminalFabric(p)) { dut => + simulate(new OooIexTerminalFabric( + core, aluSourceCount = 3, bruSourceCount = 1, loadSourceCount = 1)) { dut => clear(dut) pokeAlu(dut, source = 0, ridSlot = 1, ptag = 30) pokeAlu(dut, source = 1, ridSlot = 2, ptag = 31) @@ -123,17 +342,18 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { dut.io.pWrite(0).bits.key.ptag.expect(30.U) dut.io.pWrite(2).valid.expect(true.B) dut.io.pWrite(2).bits.key.ptag.expect(31.U) - dut.io.completion(0).bits.key.group.ridSlot.expect(1.U) - dut.io.completion(1).bits.key.group.ridSlot.expect(2.U) + dut.io.robResolve(0).bits.rob.ridSlot.expect(1.U) + dut.io.robResolve(1).bits.rob.ridSlot.expect(2.U) } } test("keeps terminal clusters independently backpressured") { - simulate(new OooIexTerminalFabric(p)) { dut => + simulate(new OooIexTerminalFabric( + core, aluSourceCount = 3, bruSourceCount = 1, loadSourceCount = 1)) { dut => clear(dut) pokeAlu(dut, source = 0, ridSlot = 1, ptag = 30) pokeAlu(dut, source = 1, ridSlot = 2, ptag = 31) - dut.io.completion(0).ready.poke(false.B) + dut.io.robResolve(0).ready.poke(false.B) dut.io.terminalFireMask.expect(2.U) dut.io.alu(0).ready.expect(false.B) @@ -141,28 +361,195 @@ class OooIexTerminalFabricSpec extends AnyFunSuite with ChiselSim { dut.io.pWrite(0).valid.expect(false.B) dut.io.pWrite(2).valid.expect(true.B) - dut.io.completion(0).ready.poke(true.B) + dut.io.robResolve(0).ready.poke(true.B) dut.io.terminalFireMask.expect(3.U) } } + test("direct J waits for recovery and publishes redirect atomically once") { + simulate(new OooIexTerminalFabric( + core, aluSourceCount = 1, bruSourceCount = 1, loadSourceCount = 1)) { dut => + clear(dut) + pokeDirectJump(dut, source = 0, ridSlot = 3, target = 0x3008) + dut.io.recoveryEvent.head.ready.poke(false.B) + + dut.io.bru.head.ready.expect(false.B) + dut.io.terminalFireMask.expect(0.U) + dut.io.robResolve.head.valid.expect(false.B) + dut.io.trace.head.valid.expect(false.B) + dut.io.recoveryEvent.head.valid.expect(true.B) + dut.io.bctrl.head.valid.expect(false.B) + + dut.io.recoveryEvent.head.ready.poke(true.B) + dut.io.bru.head.ready.expect(true.B) + dut.io.terminalFireMask.expect(1.U) + dut.io.robResolve.head.valid.expect(true.B) + dut.io.trace.head.valid.expect(true.B) + dut.io.recoveryEvent.head.valid.expect(true.B) + dut.io.recoveryEvent.head.bits.cause.expect(RecoveryCause.Branch) + dut.io.recoveryEvent.head.bits.redirectPc.expect(0x3008.U) + dut.clock.step() + dut.io.bru.head.valid.poke(false.B) + dut.io.recoveryEvent.head.valid.expect(false.B) + dut.io.robResolve.head.valid.expect(false.B) + dut.io.trace.head.valid.expect(false.B) + } + } + + test("backpressured direct J does not block a peer terminal lane") { + simulate(new OooIexTerminalFabric( + core, aluSourceCount = 2, bruSourceCount = 1, loadSourceCount = 1)) { dut => + clear(dut) + pokeDirectJump(dut, source = 0, ridSlot = 3, target = 0x3008) + pokeAlu(dut, source = 1, ridSlot = 4, ptag = 31) + dut.io.recoveryEvent.head.ready.poke(false.B) + + dut.io.bru.head.ready.expect(false.B) + dut.io.alu(1).ready.expect(true.B) + dut.io.terminalFireMask.expect(2.U) + dut.io.robResolve(0).valid.expect(false.B) + dut.io.robResolve(1).valid.expect(true.B) + dut.io.pWrite(2).valid.expect(true.B) + } + } + test("round robins same-cluster ALU owners only on terminal fire") { - simulate(new OooIexTerminalFabric(p)) { dut => + simulate(new OooIexTerminalFabric( + core, aluSourceCount = 3, bruSourceCount = 1, loadSourceCount = 1)) { dut => clear(dut) pokeAlu(dut, source = 0, ridSlot = 1, ptag = 30) - pokeAlu(dut, source = 2, ridSlot = 3, ptag = 32) - dut.io.completion(0).ready.poke(false.B) + pokeAlu(dut, source = 2, ridSlot = 3, ptag = 29) + dut.io.robResolve(0).ready.poke(false.B) dut.io.alu(0).ready.expect(false.B) dut.io.alu(2).ready.expect(false.B) + dut.io.robResolve(0).bits.rob.ridSlot.expect(3.U) dut.clock.step(2) - dut.io.completion(0).ready.poke(true.B) + dut.io.robResolve(0).bits.rob.ridSlot.expect(3.U) + dut.io.robResolve(0).ready.poke(true.B) + dut.io.alu(0).ready.expect(false.B) + dut.io.alu(2).ready.expect(true.B) + dut.clock.step() + + dut.io.alu(2).valid.poke(false.B) dut.io.alu(0).ready.expect(true.B) - dut.io.alu(2).ready.expect(false.B) + dut.io.robResolve(0).bits.rob.ridSlot.expect(1.U) + } + } + + test("retains a real ALU W1 W2 transaction until one atomic terminal fire") { + simulate(new OooIexAluTerminalHarness(core)) { dut => + clearHarness(dut) + dut.reset.poke(true.B) + dut.clock.step() + dut.reset.poke(false.B) + pokeHarnessExecute(dut) + dut.io.e1.ready.expect(true.B) + dut.clock.step() + dut.io.e1.valid.poke(false.B) + dut.io.w1Occupied.expect(true.B) + dut.io.w2Occupied.expect(false.B) dut.clock.step() + dut.io.w1Occupied.expect(false.B) + dut.io.w2Occupied.expect(true.B) + dut.io.robResolve(0).ready.poke(false.B) - dut.io.alu(0).valid.poke(false.B) - dut.io.alu(2).ready.expect(true.B) - dut.io.completion(0).bits.key.group.ridSlot.expect(3.U) + for (_ <- 0 until 3) { + dut.io.terminalFireMask.expect(0.U) + dut.io.robResolve(0).valid.expect(true.B) + dut.io.robResolve(0).ready.expect(false.B) + dut.io.robResolve(0).bits.rob.ridSlot.expect(3.U) + dut.io.robResolve.drop(1).foreach(_.valid.expect(false.B)) + dut.io.retainedW2.valid.expect(true.B) + expectRetainedMember(dut.io.retainedW2.bits.execute.i2.row + .schedule.member) + expectRetainedDestination(dut.io.retainedW2.bits.execute.i2.row + .schedule.destinations(0)) + dut.io.retainedW2.bits.writebacks(0).valid.expect(true.B) + expectRetainedDestination( + dut.io.retainedW2.bits.writebacks(0).destination) + dut.io.retainedW2.bits.writebacks(0).data.expect(42.U) + dut.io.pWrite.foreach(_.valid.expect(false.B)) + dut.io.tWrite.foreach(_.valid.expect(false.B)) + dut.io.uWrite.foreach(_.valid.expect(false.B)) + dut.io.wakeup.foreach(_.valid.expect(false.B)) + dut.io.trace.foreach(_.valid.expect(false.B)) + dut.io.bctrl.foreach(_.valid.expect(false.B)) + dut.io.w2Occupied.expect(true.B) + dut.clock.step() + } + + dut.io.robResolve(0).ready.poke(true.B) + dut.io.terminalFireMask.expect(1.U) + dut.io.robResolve(0).valid.expect(true.B) + dut.io.robResolve(0).bits.rob.ridSlot.expect(3.U) + dut.io.robResolve(0).bits.trap.valid.expect(false.B) + dut.io.robResolve(0).bits.trap.cause.expect(0.U) + dut.io.robResolve.drop(1).foreach(_.valid.expect(false.B)) + dut.io.pWrite(0).valid.expect(true.B) + dut.io.pWrite(0).bits.commit.expect(true.B) + dut.io.pWrite(0).bits.key.stid.expect(0.U) + dut.io.pWrite(0).bits.key.epoch.expect(9.U) + dut.io.pWrite(0).bits.key.ptag.expect(27.U) + dut.io.pWrite(0).bits.key.generation.expect(3.U) + dut.io.pWrite(0).bits.data.expect(42.U) + dut.io.pWrite.drop(1).foreach(_.valid.expect(false.B)) + dut.io.wakeup(0).valid.expect(true.B) + dut.io.wakeup(0).bits.kind.expect(OooIexWakeupKind.Committed) + dut.io.wakeup(0).bits.stid.expect(0.U) + dut.io.wakeup(0).bits.epoch.expect(9.U) + dut.io.wakeup(0).bits.operandClass.expect(OperandClass.P) + dut.io.wakeup(0).bits.ptag.expect(27.U) + dut.io.wakeup(0).bits.ptagGeneration.expect(3.U) + dut.io.wakeup(0).bits.localTag.expect(0.U) + dut.io.wakeup(0).bits.localSequence.valid.expect(false.B) + dut.io.wakeup(0).bits.localSequence.index.expect(0.U) + dut.io.wakeup(0).bits.localSequence.generation.expect(0.U) + expectEmptyLoad(dut.io.wakeup(0).bits.load) + dut.io.wakeup.drop(1).foreach(_.valid.expect(false.B)) + dut.io.trace(0).valid.expect(true.B) + val trace = dut.io.trace(0).bits + trace.source.expect(OooIexTerminalSource.Alu) + expectRetainedMember(trace.member) + trace.uopKey.primaryParent.valid.expect(true.B) + trace.uopKey.primaryParent.peId.expect(3.U) + trace.uopKey.primaryParent.stid.expect(0.U) + trace.uopKey.primaryParent.instructionId.expect(43.U) + trace.uopKey.primaryParent.epoch.expect(0.U) + trace.uopKey.uopOrdinal.expect(0.U) + trace.uopKey.uopCount.expect(1.U) + trace.opcode.expect(62.U) + trace.writebacks(0).valid.expect(true.B) + expectRetainedDestination(trace.writebacks(0).destination) + trace.writebacks(0).data.expect(42.U) + trace.writebacks.drop(1).foreach(_.valid.expect(false.B)) + expectEmptyLoad(trace.load) + trace.trapValid.expect(false.B) + trace.trapCause.expect(0.U) + dut.io.trace.drop(1).foreach(_.valid.expect(false.B)) + dut.io.tWrite.foreach(_.valid.expect(false.B)) + dut.io.uWrite.foreach(_.valid.expect(false.B)) + dut.io.bctrl.foreach(_.valid.expect(false.B)) + dut.io.retainedW2.valid.expect(true.B) + expectRetainedMember(dut.io.retainedW2.bits.execute.i2.row + .schedule.member) + expectRetainedDestination( + dut.io.retainedW2.bits.writebacks(0).destination) + dut.io.retainedW2.bits.writebacks(0).data.expect(42.U) + dut.clock.step() + + for (_ <- 0 until 2) { + dut.io.w2Occupied.expect(false.B) + dut.io.retainedW2.valid.expect(false.B) + dut.io.terminalFireMask.expect(0.U) + dut.io.robResolve.foreach(_.valid.expect(false.B)) + dut.io.pWrite.foreach(_.valid.expect(false.B)) + dut.io.wakeup.foreach(_.valid.expect(false.B)) + dut.io.trace.foreach(_.valid.expect(false.B)) + dut.io.tWrite.foreach(_.valid.expect(false.B)) + dut.io.uWrite.foreach(_.valid.expect(false.B)) + dut.io.bctrl.foreach(_.valid.expect(false.B)) + dut.clock.step() + } } } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooIexTerminalPublishSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIexTerminalPublishSpec.scala deleted file mode 100644 index bf67579f..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIexTerminalPublishSpec.scala +++ /dev/null @@ -1,454 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, Valid} -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -class OooIexTerminalOperandHarnessIO(val p: OooParams) extends Bundle { - val alu = Flipped(Decoupled(new OooIexAluTerminalTransaction(p))) - val pInit = Flipped(Valid(new OooIexPFileInit(p))) - val tClear = Flipped(Valid(new OooIexLocalFileKey(p))) - val uClear = Flipped(Valid(new OooIexLocalFileKey(p))) - val pRead = Flipped(Valid(new OooIexOperandReadPortRequest(p))) - val tRead = Flipped(Valid(new OooIexOperandReadPortRequest(p))) - val uRead = Flipped(Valid(new OooIexOperandReadPortRequest(p))) - val pResponse = Valid(UInt(p.pcWidth.W)) - val tResponse = Valid(UInt(p.pcWidth.W)) - val uResponse = Valid(UInt(p.pcWidth.W)) - val wakeup = Vec(p.maxDestinationOperands, - Decoupled(new OooIexWakeup(p))) - val trace = Decoupled(new OooIexTerminalTrace(p)) - val completion = Decoupled(new OooRobMemberCompletion(p)) - val terminalFire = Output(Bool()) -} - -/** Composition shell proving the publication pulse mutates the canonical RF. */ -class OooIexTerminalOperandHarness(val p: OooParams) extends Module { - val io = IO(new OooIexTerminalOperandHarnessIO(p)) - val publish = Module(new OooIexTerminalPublish(p)) - val files = Module(new OooIexOperandFiles(p)) - - publish.io.alu <> io.alu - publish.io.bru.valid := false.B - publish.io.bru.bits := 0.U.asTypeOf(publish.io.bru.bits) - publish.io.load.valid := false.B - publish.io.load.bits := 0.U.asTypeOf(publish.io.load.bits) - - files.io.pInit := io.pInit - for (index <- 0 until 2) { - files.io.pClear(index).valid := false.B - files.io.pClear(index).bits := 0.U.asTypeOf(files.io.pClear(index).bits) - } - for (index <- 0 until p.tuAllocationWidth) { - files.io.tClear(index).valid := index.U === 0.U && io.tClear.valid - files.io.tClear(index).bits := io.tClear.bits - files.io.uClear(index).valid := index.U === 0.U && io.uClear.valid - files.io.uClear(index).bits := io.uClear.bits - } - - for (index <- 0 until p.iexPReadPorts) { - files.io.pReadRequests(index).valid := index.U === 0.U && io.pRead.valid - files.io.pReadRequests(index).bits := io.pRead.bits - } - for (index <- 0 until p.iexTReadPorts) { - files.io.tReadRequests(index).valid := index.U === 0.U && io.tRead.valid - files.io.tReadRequests(index).bits := io.tRead.bits - } - for (index <- 0 until p.iexUReadPorts) { - files.io.uReadRequests(index).valid := index.U === 0.U && io.uRead.valid - files.io.uReadRequests(index).bits := io.uRead.bits - } - io.pResponse := files.io.pReadResponses(0) - io.tResponse := files.io.tReadResponses(0) - io.uResponse := files.io.uReadResponses(0) - - for (index <- 0 until p.iexPWritePorts) { - if (index < p.maxDestinationOperands) { - files.io.pWrite(index).valid := publish.io.pWrite(index).valid - files.io.pWrite(index).bits := publish.io.pWrite(index).bits - publish.io.pWrite(index).ready := files.io.pWriteReady(index) - } else { - files.io.pWrite(index).valid := false.B - files.io.pWrite(index).bits := - 0.U.asTypeOf(files.io.pWrite(index).bits) - } - } - for (index <- 0 until p.iexTWritePorts) { - if (index < p.maxDestinationOperands) { - files.io.tWrite(index).valid := publish.io.tWrite(index).valid - files.io.tWrite(index).bits := publish.io.tWrite(index).bits - publish.io.tWrite(index).ready := files.io.tWriteReady(index) - } else { - files.io.tWrite(index).valid := false.B - files.io.tWrite(index).bits := - 0.U.asTypeOf(files.io.tWrite(index).bits) - } - } - for (index <- 0 until p.iexUWritePorts) { - if (index < p.maxDestinationOperands) { - files.io.uWrite(index).valid := publish.io.uWrite(index).valid - files.io.uWrite(index).bits := publish.io.uWrite(index).bits - publish.io.uWrite(index).ready := files.io.uWriteReady(index) - } else { - files.io.uWrite(index).valid := false.B - files.io.uWrite(index).bits := - 0.U.asTypeOf(files.io.uWrite(index).bits) - } - } - - publish.io.wakeup <> io.wakeup - publish.io.trace <> io.trace - publish.io.completion <> io.completion - publish.io.bctrl.ready := true.B - io.terminalFire := publish.io.terminalFire -} - -class OooIexTerminalPublishSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - tuRetireSourceDepthPerStid = 16) - - private def pokeMember(target: RobMemberKey, ridSlot: Int = 2): Unit = { - target.poke(0.U.asTypeOf(target)) - target.group.valid.poke(true.B) - target.group.peId.poke(3.U) - target.group.stid.poke(1.U) - target.group.ridSlot.poke(ridSlot.U) - target.group.ridGeneration.poke(1.U) - target.bid.valid.poke(true.B) - target.bid.value.poke(5.U) - target.brobGeneration.poke(2.U) - target.memberIndex.poke(0.U) - target.residentGeneration.poke(4.U) - } - - private def pokeDestination( - destination: OooIexDestinationState, - kind: DestinationKind.Type, - ordinal: Int): Unit = { - destination.poke(0.U.asTypeOf(destination)) - destination.valid.poke(true.B) - destination.kind.poke(kind) - destination.atag.poke((4 + ordinal).U) - destination.ptag.poke((30 + ordinal).U) - destination.ptagGeneration.poke(3.U) - destination.localTag.poke((6 + ordinal).U) - destination.localSequence.valid.poke(true.B) - destination.localSequence.index.poke((10 + ordinal).U) - destination.localSequence.generation.poke(2.U) - } - - private def pokeExecute( - execute: OooIexExecuteTransaction, - destinations: Seq[DestinationKind.Type], - ridSlot: Int = 2): Unit = { - execute.poke(0.U.asTypeOf(execute)) - val row = execute.i2.row.schedule - row.valid.poke(true.B) - row.peId.poke(3.U) - row.stid.poke(1.U) - row.epoch.poke(7.U) - pokeMember(row.member, ridSlot) - row.reservation.valid.poke(true.B) - row.reservation.uopClass.poke(OooUopClass.Alu) - execute.ownerClass.poke(OooUopClass.Alu) - execute.i2.row.payload.opcode.poke(0x51.U) - execute.i2.row.payload.recipe.valid.poke(true.B) - execute.i2.row.payload.recipe.opcode.poke(0x51.U) - execute.i2.row.payload.recipe.disposition.poke( - OooOpcodeDisposition.Dispatch.U) - execute.i2.row.payload.recipe.dispatchClass.poke( - OooDispatchClass.Alu.U) - execute.i2.row.payload.recipe.sideEffectOwner.poke( - OooSideEffectOwner.Iex.U) - execute.i2.row.payload.uopKey.primaryParent.valid.poke(true.B) - execute.i2.row.payload.uopKey.primaryParent.peId.poke(3.U) - execute.i2.row.payload.uopKey.primaryParent.stid.poke(1.U) - execute.i2.row.payload.uopKey.primaryParent.instructionId.poke(9.U) - execute.i2.row.payload.uopKey.uopCount.poke(1.U) - destinations.zipWithIndex.foreach { case (kind, index) => - pokeDestination(row.destinations(index), kind, index) - } - } - - private def clear(dut: OooIexTerminalPublish): Unit = { - dut.io.alu.valid.poke(false.B) - dut.io.alu.bits.poke(0.U.asTypeOf(dut.io.alu.bits)) - dut.io.bru.valid.poke(false.B) - dut.io.bru.bits.poke(0.U.asTypeOf(dut.io.bru.bits)) - dut.io.load.valid.poke(false.B) - dut.io.load.bits.poke(0.U.asTypeOf(dut.io.load.bits)) - dut.io.pWrite.foreach(_.ready.poke(true.B)) - dut.io.tWrite.foreach(_.ready.poke(true.B)) - dut.io.uWrite.foreach(_.ready.poke(true.B)) - dut.io.wakeup.foreach(_.ready.poke(true.B)) - dut.io.bctrl.ready.poke(true.B) - dut.io.trace.ready.poke(true.B) - dut.io.completion.ready.poke(true.B) - } - - private def pokeAlu( - dut: OooIexTerminalPublish, - destinations: Seq[DestinationKind.Type]): Unit = { - val terminal = dut.io.alu.bits - terminal.poke(0.U.asTypeOf(terminal)) - pokeExecute(terminal.execute, destinations) - destinations.zipWithIndex.foreach { case (kind, index) => - terminal.writebacks(index).valid.poke(true.B) - pokeDestination(terminal.writebacks(index).destination, kind, index) - terminal.writebacks(index).data.poke((0x100 + index).U) - } - dut.io.alu.valid.poke(true.B) - } - - test("holds every peer until P write and committed wakeup can fire together") { - simulate(new OooIexTerminalPublish(p)) { dut => - clear(dut) - pokeAlu(dut, Seq(DestinationKind.Gpr)) - dut.io.pWrite(0).ready.poke(false.B) - dut.io.alu.ready.expect(false.B) - dut.io.pWrite(0).valid.expect(true.B) - dut.io.wakeup(0).valid.expect(false.B) - dut.io.completion.valid.expect(false.B) - dut.io.trace.valid.expect(false.B) - - dut.io.pWrite(0).ready.poke(true.B) - dut.io.wakeup(0).ready.poke(false.B) - dut.io.pWrite(0).valid.expect(false.B) - dut.io.wakeup(0).valid.expect(true.B) - dut.io.alu.ready.expect(false.B) - - dut.io.wakeup(0).ready.poke(true.B) - dut.io.alu.ready.expect(true.B) - dut.io.terminalFire.expect(true.B) - dut.io.pWrite(0).valid.expect(true.B) - dut.io.wakeup(0).valid.expect(true.B) - dut.io.wakeup(0).bits.kind.expect(OooIexWakeupKind.Committed) - dut.io.wakeup(0).bits.operandClass.expect(OperandClass.P) - dut.io.completion.valid.expect(true.B) - dut.io.trace.valid.expect(true.B) - dut.io.trace.bits.writebacks(0).data.expect(0x100.U) - } - } - - test("publishes T and U destinations as one multi-write transaction") { - simulate(new OooIexTerminalPublish(p)) { dut => - clear(dut) - pokeAlu(dut, Seq(DestinationKind.T, DestinationKind.U)) - dut.io.uWrite(1).ready.poke(false.B) - dut.io.alu.ready.expect(false.B) - dut.io.tWrite(0).valid.expect(false.B) - dut.io.uWrite(1).valid.expect(true.B) - dut.io.wakeup(1).valid.expect(false.B) - dut.io.terminalFire.expect(false.B) - - dut.io.uWrite(1).ready.poke(true.B) - dut.io.alu.ready.expect(true.B) - dut.io.tWrite(0).valid.expect(true.B) - dut.io.uWrite(1).valid.expect(true.B) - dut.io.wakeup(0).bits.operandClass.expect(OperandClass.T) - dut.io.wakeup(1).bits.operandClass.expect(OperandClass.U) - dut.io.terminalFire.expect(true.B) - } - } - - test("keeps BRU BCTRL and load fault publication under the same terminal fire") { - simulate(new OooIexTerminalPublish(p)) { dut => - clear(dut) - pokeExecute(dut.io.bru.bits.execute, Seq.empty) - dut.io.bru.bits.execute.ownerClass.poke(OooUopClass.Bru) - dut.io.bru.bits.execute.i2.row.schedule.reservation.uopClass.poke( - OooUopClass.Bru) - dut.io.bru.bits.execute.i2.row.payload.recipe.dispatchClass.poke( - OooDispatchClass.Bru.U) - dut.io.bru.bits.execute.i2.row.payload.recipe.sideEffectOwner.poke( - OooSideEffectOwner.Bctrl.U) - dut.io.bru.bits.bctrl.valid.poke(true.B) - dut.io.bru.bits.bctrl.kind.poke(OooIexBctrlUpdateKind.Condition) - dut.io.bru.bits.bctrl.condition.poke(true.B) - dut.io.bru.valid.poke(true.B) - dut.io.bctrl.ready.poke(false.B) - dut.io.bctrl.valid.expect(true.B) - dut.io.completion.valid.expect(false.B) - dut.io.bru.ready.expect(false.B) - dut.io.bctrl.ready.poke(true.B) - dut.io.bru.ready.expect(true.B) - dut.io.bctrl.valid.expect(true.B) - dut.io.completion.valid.expect(true.B) - dut.io.trace.valid.expect(true.B) - dut.clock.step() - - dut.io.bru.valid.poke(false.B) - val load = dut.io.load.bits - load.poke(0.U.asTypeOf(load)) - pokeExecute(load.agu.execute, Seq(DestinationKind.Gpr), ridSlot = 3) - load.agu.execute.ownerClass.poke(OooUopClass.Agu) - load.agu.execute.i2.row.schedule.reservation.uopClass.poke( - OooUopClass.Agu) - load.agu.execute.i2.row.payload.recipe.dispatchClass.poke( - OooDispatchClass.Agu.U) - load.agu.execute.i2.row.payload.recipe.sideEffectOwner.poke( - OooSideEffectOwner.Lsu.U) - pokeDestination(load.agu.destination, DestinationKind.Gpr, 0) - load.faultValid.poke(true.B) - load.faultCause.poke(13.U) - load.load.valid.poke(true.B) - pokeMember(load.load.producer, ridSlot = 3) - load.load.generation.poke(6.U) - dut.io.load.valid.poke(true.B) - dut.io.load.ready.expect(true.B) - dut.io.pWrite.foreach(_.valid.expect(false.B)) - dut.io.wakeup.foreach(_.valid.expect(false.B)) - dut.io.trace.bits.trapValid.expect(true.B) - dut.io.trace.bits.trapCause.expect(13.U) - dut.io.completion.valid.expect(true.B) - dut.io.completion.bits.faultValid.expect(true.B) - dut.io.completion.bits.faultCause.expect(13.U) - } - } - - test("rejects duplicated destinations without consuming the owner") { - simulate(new OooIexTerminalPublish(p)) { dut => - clear(dut) - pokeAlu(dut, Seq(DestinationKind.Gpr, DestinationKind.Gpr)) - pokeDestination( - dut.io.alu.bits.execute.i2.row.schedule.destinations(1), - DestinationKind.Gpr, 0) - pokeDestination(dut.io.alu.bits.writebacks(1).destination, - DestinationKind.Gpr, 0) - dut.io.alu.ready.expect(false.B) - dut.io.rejected(0).valid.expect(true.B) - dut.io.rejected(0).bits.duplicateDestination.expect(true.B) - dut.io.terminalFire.expect(false.B) - } - } - - test("writes P T and U data into the canonical operand files") { - simulate(new OooIexTerminalOperandHarness(p)) { dut => - dut.io.alu.valid.poke(false.B) - dut.io.alu.bits.poke(0.U.asTypeOf(dut.io.alu.bits)) - dut.io.pInit.valid.poke(false.B) - dut.io.pInit.bits.poke(0.U.asTypeOf(dut.io.pInit.bits)) - dut.io.tClear.valid.poke(false.B) - dut.io.tClear.bits.poke(0.U.asTypeOf(dut.io.tClear.bits)) - dut.io.uClear.valid.poke(false.B) - dut.io.uClear.bits.poke(0.U.asTypeOf(dut.io.uClear.bits)) - dut.io.pRead.valid.poke(false.B) - dut.io.pRead.bits.poke(0.U.asTypeOf(dut.io.pRead.bits)) - dut.io.tRead.valid.poke(false.B) - dut.io.tRead.bits.poke(0.U.asTypeOf(dut.io.tRead.bits)) - dut.io.uRead.valid.poke(false.B) - dut.io.uRead.bits.poke(0.U.asTypeOf(dut.io.uRead.bits)) - dut.io.wakeup.foreach(_.ready.poke(true.B)) - dut.io.trace.ready.poke(true.B) - dut.io.completion.ready.poke(true.B) - dut.clock.step() - - dut.io.pInit.bits.key.stid.poke(1.U) - dut.io.pInit.bits.key.epoch.poke(7.U) - dut.io.pInit.bits.key.ptag.poke(30.U) - dut.io.pInit.bits.key.generation.poke(3.U) - dut.io.pInit.bits.data.poke(0.U) - dut.io.pInit.valid.poke(true.B) - dut.io.tClear.bits.stid.poke(1.U) - dut.io.tClear.bits.epoch.poke(7.U) - dut.io.tClear.bits.tag.poke(7.U) - dut.io.tClear.bits.sequence.valid.poke(true.B) - dut.io.tClear.bits.sequence.index.poke(11.U) - dut.io.tClear.bits.sequence.generation.poke(2.U) - dut.io.tClear.valid.poke(true.B) - dut.io.uClear.bits.stid.poke(1.U) - dut.io.uClear.bits.epoch.poke(7.U) - dut.io.uClear.bits.tag.poke(6.U) - dut.io.uClear.bits.sequence.valid.poke(true.B) - dut.io.uClear.bits.sequence.index.poke(10.U) - dut.io.uClear.bits.sequence.generation.poke(2.U) - dut.io.uClear.valid.poke(true.B) - dut.clock.step() - dut.io.pInit.valid.poke(false.B) - dut.io.tClear.valid.poke(false.B) - dut.io.uClear.valid.poke(false.B) - - val terminal = dut.io.alu.bits - terminal.poke(0.U.asTypeOf(terminal)) - pokeExecute(terminal.execute, - Seq(DestinationKind.Gpr, DestinationKind.T)) - terminal.writebacks(0).valid.poke(true.B) - pokeDestination(terminal.writebacks(0).destination, - DestinationKind.Gpr, 0) - terminal.writebacks(0).data.poke(0x1111.U) - terminal.writebacks(1).valid.poke(true.B) - pokeDestination(terminal.writebacks(1).destination, - DestinationKind.T, 1) - terminal.writebacks(1).data.poke(0x2222.U) - dut.io.alu.valid.poke(true.B) - dut.io.alu.ready.expect(true.B) - dut.io.terminalFire.expect(true.B) - dut.clock.step() - dut.io.alu.valid.poke(false.B) - - dut.io.pRead.bits.stid.poke(1.U) - dut.io.pRead.bits.epoch.poke(7.U) - dut.io.pRead.bits.source.operandClass.poke(OperandClass.P) - dut.io.pRead.bits.source.ptag.poke(30.U) - dut.io.pRead.bits.source.ptagGeneration.poke(3.U) - dut.io.pRead.valid.poke(true.B) - dut.io.pResponse.valid.expect(true.B) - dut.io.pResponse.bits.expect(0x1111.U) - - dut.io.tRead.bits.stid.poke(1.U) - dut.io.tRead.bits.epoch.poke(7.U) - dut.io.tRead.bits.source.operandClass.poke(OperandClass.T) - dut.io.tRead.bits.source.localTag.poke(7.U) - dut.io.tRead.bits.source.localSequence.valid.poke(true.B) - dut.io.tRead.bits.source.localSequence.index.poke(11.U) - dut.io.tRead.bits.source.localSequence.generation.poke(2.U) - dut.io.tRead.valid.poke(true.B) - dut.io.tResponse.valid.expect(true.B) - dut.io.tResponse.bits.expect(0x2222.U) - - dut.io.pRead.valid.poke(false.B) - dut.io.tRead.valid.poke(false.B) - terminal.poke(0.U.asTypeOf(terminal)) - pokeExecute(terminal.execute, Seq(DestinationKind.U), ridSlot = 3) - terminal.writebacks(0).valid.poke(true.B) - pokeDestination(terminal.writebacks(0).destination, - DestinationKind.U, 0) - terminal.writebacks(0).data.poke(0x3333.U) - dut.io.alu.valid.poke(true.B) - dut.io.alu.ready.expect(true.B) - dut.io.terminalFire.expect(true.B) - dut.clock.step() - dut.io.alu.valid.poke(false.B) - - dut.io.uRead.bits.stid.poke(1.U) - dut.io.uRead.bits.epoch.poke(7.U) - dut.io.uRead.bits.source.operandClass.poke(OperandClass.U) - dut.io.uRead.bits.source.localTag.poke(6.U) - dut.io.uRead.bits.source.localSequence.valid.poke(true.B) - dut.io.uRead.bits.source.localSequence.index.poke(10.U) - dut.io.uRead.bits.source.localSequence.generation.poke(2.U) - dut.io.uRead.valid.poke(true.B) - dut.io.uResponse.valid.expect(true.B) - dut.io.uResponse.bits.expect(0x3333.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIfuD1IngressSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIfuD1IngressSpec.scala deleted file mode 100644 index 3014d7d2..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIfuD1IngressSpec.scala +++ /dev/null @@ -1,129 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.InterfaceParams -import org.scalatest.funsuite.AnyFunSuite - -class OooIfuD1IngressSpec extends AnyFunSuite with ChiselSim { - private val ifuP = InterfaceParams() - private val oooP = OooParams(instructionDecodeWidth = 4) - - private def rule(symbol: String): OooOpcodeRecipeTable.Rule = - OooOpcodeRecipeTable.Rules.find(_.symbol == symbol).getOrElse( - fail(s"missing generated recipe for $symbol")) - - private def clear(dut: OooIfuD1Ingress): Unit = { - dut.io.ifuD1.valid.poke(false.B) - dut.io.ifuD1.bits.poke(0.U.asTypeOf(dut.io.ifuD1.bits)) - dut.io.selectStid.poke(0.U) - dut.io.flush.poke(0.U.asTypeOf(dut.io.flush)) - dut.io.fence.foreach(_.poke(false.B)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.ctuParentClaim.ready.poke(false.B) - dut.io.ctuExpansionPlan.valid.poke(false.B) - dut.io.ctuExpansionPlan.bits.poke( - 0.U.asTypeOf(dut.io.ctuExpansionPlan.bits)) - dut.io.ctuChild.valid.poke(false.B) - dut.io.ctuChild.bits.poke(0.U.asTypeOf(dut.io.ctuChild.bits)) - dut.io.ctuRecoveryPrepare.valid.poke(false.B) - dut.io.ctuRecoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.ctuRecoveryPrepare.bits)) - dut.io.ctuRecoveryApply.poke(false.B) - dut.io.ctuRecoveryAbort.poke(false.B) - dut.io.out.ready.poke(true.B) - } - - private def pokeEntry( - dut: OooIfuD1Ingress, - lane: Int, - symbol: String, - instructionId: Int, - stid: Int = 0, - epoch: Int = 3): Unit = { - val entry = dut.io.ifuD1.bits.entries(lane) - val recipe = rule(symbol) - val pc = 0x8000 + instructionId * 8 - entry.pc.poke(pc.U) - entry.instructionUid.poke(instructionId.U) - entry.transactionId.poke((0x1000 + instructionId).U) - entry.insn.poke(recipe.value.U) - entry.lenBytes.poke(recipe.lenBytes.U) - entry.identity.peId.poke(4.U) - entry.identity.threadId.poke(stid.U) - entry.identity.fetchPacketUid.poke((0x2000 + instructionId).U) - entry.identity.fetchSeq.poke((0x3000 + instructionId).U) - entry.identity.fetchSlot.poke(lane.U) - entry.identity.checkpointId.poke(2.U) - entry.identity.epoch.poke(epoch.U) - entry.prediction.valid.poke(true.B) - entry.prediction.predictionTag.poke((0x4000 + instructionId).U) - entry.prediction.requestPc.poke(pc.U) - entry.prediction.branchPc.poke(pc.U) - entry.prediction.target.poke((pc + 0x100).U) - entry.prediction.fallthroughPc.poke((pc + recipe.lenBytes).U) - entry.prediction.checkpointId.poke(2.U) - entry.prediction.epoch.poke(epoch.U) - } - - private def enqueue( - dut: OooIfuD1Ingress, - symbols: Seq[String], - firstId: Int): Unit = { - dut.io.ifuD1.bits.poke(0.U.asTypeOf(dut.io.ifuD1.bits)) - symbols.zipWithIndex.foreach { case (symbol, lane) => - pokeEntry(dut, lane, symbol, firstId + lane) - } - dut.io.ifuD1.bits.validMask.poke(((1 << symbols.size) - 1).U) - dut.io.ifuD1.valid.poke(true.B) - dut.io.ifuD1.ready.expect(true.B) - dut.clock.step() - dut.io.ifuD1.valid.poke(false.B) - } - - test("connects IFU raw rows through canonical decode and boundary fusion") { - simulate(new OooIfuD1Ingress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, Seq("OP_ADD", "OP_BSTOP"), firstId = 10) - dut.io.out.ready.poke(false.B) - dut.clock.step() - - dut.io.out.valid.expect(true.B) - dut.io.out.bits.uopMask.expect(1.U) - dut.io.out.bits.uops(0).opcode.expect(rule("OP_ADD").opcode.U) - dut.io.out.bits.uops(0).identity.parentCount.expect(2.U) - dut.io.out.bits.uops(0).identity.parents(0).key.instructionId.expect(10.U) - dut.io.out.bits.uops(0).identity.parents(1).key.instructionId.expect(11.U) - dut.io.out.bits.uops(0).identity.boundary.stop.expect(true.B) - dut.io.out.bits.uops(0).identity.parents(0).prediction.transactionId - .expect((0x1000 + 10).U) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.rawCounts(0).expect(0.U) - } - } - - test("claims an exact CTU parent instead of forwarding a diversion mask to D2") { - simulate(new OooIfuD1Ingress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, Seq("OP_FENTRY"), firstId = 20) - dut.clock.step() - - dut.io.out.valid.expect(false.B) - dut.io.ctuParentClaim.valid.expect(true.B) - val parent = dut.io.ctuParentClaim.bits.parent.parent - parent.key.valid.expect(true.B) - parent.key.peId.expect(4.U) - parent.key.stid.expect(0.U) - parent.key.instructionId.expect(20.U) - parent.rawInstruction.expect(rule("OP_FENTRY").value.U) - parent.prediction.transactionId.expect((0x1000 + 20).U) - parent.prediction.fetchPacketUid.expect((0x2000 + 20).U) - parent.prediction.fetchSeq.expect((0x3000 + 20).U) - parent.prediction.predictionTag.expect((0x4000 + 20).U) - dut.io.ctuParentClaim.bits.lease.parent.instructionId.expect(20.U) - dut.io.ctuParentClaim.bits.lease.templateGroupId.expect(0.U) - dut.io.ctuParentClaim.bits.lease.generation.expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooIfuRawIngressSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooIfuRawIngressSpec.scala deleted file mode 100644 index 396ca234..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooIfuRawIngressSpec.scala +++ /dev/null @@ -1,257 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{BoundaryKind, InterfaceParams} -import linxcore.frontend.{ - BSideStage, - IfuPruneScope, - PredictionProvider -} -import org.scalatest.funsuite.AnyFunSuite - -class OooIfuRawIngressSpec extends AnyFunSuite with ChiselSim { - private val ifuP = InterfaceParams() - - private def clear(dut: OooIfuRawIngress): Unit = { - dut.io.ifuD1.valid.poke(false.B) - dut.io.ifuD1.bits.poke(0.U.asTypeOf(dut.io.ifuD1.bits)) - dut.io.selectStid.poke(0.U) - dut.io.fence.foreach(_.poke(false.B)) - dut.io.out.ready.poke(false.B) - dut.io.flush.poke(0.U.asTypeOf(dut.io.flush)) - } - - private def pokeGroup( - dut: OooIfuRawIngress, - stid: Int, - firstId: Int, - lanes: Int = 4, - epoch: Int = 7, - peId: Int = 2): Unit = { - require(lanes >= 1 && lanes <= ifuP.decodeWidth) - dut.io.ifuD1.bits.poke(0.U.asTypeOf(dut.io.ifuD1.bits)) - dut.io.ifuD1.bits.validMask.poke(((1 << lanes) - 1).U) - for (lane <- 0 until lanes) { - val entry = dut.io.ifuD1.bits.entries(lane) - val instructionId = firstId + lane - val pc = 0x1000 + instructionId * 4 - entry.pc.poke(pc.U) - entry.instructionUid.poke(instructionId.U) - entry.transactionId.poke((0x2000 + instructionId).U) - entry.insn.poke((BigInt("10000000", 16) + instructionId).U) - entry.lenBytes.poke(((lane % 4 + 1) * 2).U) - entry.identity.peId.poke(peId.U) - entry.identity.threadId.poke(stid.U) - entry.identity.fetchPacketUid.poke((0x3000 + instructionId).U) - entry.identity.fetchSeq.poke((0x4000 + instructionId).U) - entry.identity.fetchSlot.poke(lane.U) - entry.identity.checkpointId.poke(5.U) - entry.identity.epoch.poke(epoch.U) - entry.prediction.valid.poke(true.B) - entry.prediction.predictionTag.poke((0x5000 + instructionId).U) - entry.prediction.requestPc.poke(pc.U) - entry.prediction.taken.poke((lane == lanes - 1).B) - entry.prediction.branchPc.poke(pc.U) - entry.prediction.target.poke((pc + 0x100).U) - entry.prediction.fallthroughPc.poke((pc + 4).U) - entry.prediction.kind.poke(BoundaryKind.Cond) - entry.prediction.provider.poke(PredictionProvider.LongTage) - entry.prediction.stage.poke(BSideStage.BF4) - entry.prediction.confidence.poke((lane & 3).U) - entry.prediction.checkpointId.poke(5.U) - entry.prediction.epoch.poke(epoch.U) - } - dut.io.ifuD1.valid.poke(true.B) - } - - private def enqueue( - dut: OooIfuRawIngress, - stid: Int, - firstId: Int, - lanes: Int = 4, - epoch: Int = 7): Unit = { - pokeGroup(dut, stid, firstId, lanes, epoch) - dut.io.ifuD1.ready.expect(true.B) - dut.clock.step() - dut.io.ifuD1.valid.poke(false.B) - } - - test("adapts a four-wide IFU group into two-wide exact production prefixes") { - val oooP = OooParams(instructionDecodeWidth = 2) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, stid = 1, firstId = 10) - - dut.io.counts(1).expect(4.U) - dut.io.eligibleMask.expect("b0010".U) - dut.io.selectStid.poke(1.U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.validMask.expect("b11".U) - dut.io.out.bits.peId.expect(2.U) - dut.io.out.bits.stid.expect(1.U) - dut.io.out.bits.epoch.expect(7.U) - - val first = dut.io.out.bits.entries(0) - first.parent.key.valid.expect(true.B) - first.parent.key.instructionId.expect(10.U) - first.parent.pc.expect((0x1000 + 10 * 4).U) - first.parent.rawInstruction.expect((BigInt("10000000", 16) + 10).U) - first.parent.prediction.transactionId.expect((0x2000 + 10).U) - first.parent.prediction.fetchPacketUid.expect((0x3000 + 10).U) - first.parent.prediction.fetchSeq.expect((0x4000 + 10).U) - first.parent.prediction.predictionTag.expect((0x5000 + 10).U) - first.parent.prediction.provider.expect(PredictionProvider.LongTage.asUInt) - first.parent.prediction.stage.expect(BSideStage.BF4.asUInt) - first.parent.traceOwner.expect(true.B) - first.parent.preciseExceptionOwner.expect(true.B) - - dut.clock.step(2) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(10.U) - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.out.bits.entries(0).parent.key.instructionId.expect(12.U) - dut.io.counts(1).expect(2.U) - dut.clock.step() - dut.io.counts(1).expect(0.U) - } - } - - test("gathers queued IFU groups into a six-wide prefix without reordering") { - val oooP = OooParams(instructionDecodeWidth = 6) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 16)) { dut => - clear(dut) - dut.io.selectStid.poke(2.U) - enqueue(dut, stid = 2, firstId = 20) - enqueue(dut, stid = 2, firstId = 24) - - dut.io.counts(2).expect(8.U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.validMask.expect("b111111".U) - for (lane <- 0 until 6) { - dut.io.out.bits.entries(lane).parent.key.instructionId.expect((20 + lane).U) - } - - dut.io.out.ready.poke(true.B) - dut.clock.step() - dut.io.counts(2).expect(2.U) - dut.io.out.bits.validMask.expect("b000011".U) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(26.U) - dut.io.out.bits.entries(1).parent.key.instructionId.expect(27.U) - } - } - - test("uses same-bank dequeue credit to replace a full four-row reservoir") { - val oooP = OooParams(instructionDecodeWidth = 4) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 4)) { dut => - clear(dut) - dut.io.selectStid.poke(2.U) - enqueue(dut, stid = 2, firstId = 70) - dut.io.counts(2).expect(4.U) - - pokeGroup(dut, stid = 2, firstId = 74) - dut.io.out.ready.poke(true.B) - dut.io.out.valid.expect(true.B) - dut.io.ifuD1.ready.expect(true.B) - dut.clock.step() - dut.io.ifuD1.valid.poke(false.B) - - dut.io.counts(2).expect(4.U) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(74.U) - dut.io.out.bits.entries(3).parent.key.instructionId.expect(77.U) - } - } - - test("keeps four STID banks isolated across a targeted hard flush") { - val oooP = OooParams(instructionDecodeWidth = 4) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, stid = 0, firstId = 30, epoch = 3) - enqueue(dut, stid = 3, firstId = 40, epoch = 9) - - dut.io.selectStid.poke(3.U) - dut.io.out.ready.poke(true.B) - dut.io.flush.valid.poke(true.B) - dut.io.flush.threadId.poke(0.U) - dut.io.flush.scope.poke(IfuPruneScope.KillAllThreadState) - dut.io.flush.newEpoch.poke(4.U) - dut.io.out.valid.expect(false.B) - dut.clock.step() - dut.io.flush.valid.poke(false.B) - - dut.io.counts(0).expect(0.U) - dut.io.counts(3).expect(4.U) - dut.io.eligibleMask.expect("b1000".U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.epoch.expect(9.U) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(40.U) - } - } - - test("prunes the trigger and younger raw rows without disturbing the older prefix") { - val oooP = OooParams(instructionDecodeWidth = 4) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, stid = 1, firstId = 60, epoch = 5) - - dut.io.flush.valid.poke(true.B) - dut.io.flush.threadId.poke(1.U) - dut.io.flush.scope.poke(IfuPruneScope.KillTriggerAndYounger) - dut.io.flush.oldEpoch.poke(5.U) - dut.io.flush.fetchSeq.poke((0x4000 + 61).U) - dut.io.flush.transactionId.poke((0x2000 + 61).U) - dut.io.flush.newEpoch.poke(6.U) - dut.clock.step() - dut.io.flush.valid.poke(false.B) - - dut.io.counts(1).expect(1.U) - dut.io.selectStid.poke(1.U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.validMask.expect(1.U) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(60.U) - dut.io.out.bits.entries(0).parent.key.epoch.expect(5.U) - } - } - - test("fences one STID without mutating its raw rows while another STID advances") { - val oooP = OooParams(instructionDecodeWidth = 4) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, stid = 1, firstId = 80, epoch = 4) - enqueue(dut, stid = 2, firstId = 90, epoch = 6) - - dut.io.fence(1).poke(true.B) - dut.io.selectStid.poke(1.U) - dut.io.out.valid.expect(false.B) - dut.io.eligibleMask.expect("b0100".U) - pokeGroup(dut, stid = 1, firstId = 84, epoch = 4) - dut.io.ifuD1.ready.expect(false.B) - dut.io.ifuD1.valid.poke(false.B) - - dut.io.selectStid.poke(2.U) - dut.io.out.ready.poke(true.B) - dut.io.out.valid.expect(true.B) - dut.clock.step() - dut.io.counts(2).expect(0.U) - dut.io.counts(1).expect(4.U) - - dut.io.fence(1).poke(false.B) - dut.io.selectStid.poke(1.U) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(80.U) - } - } - - test("elaborates and transfers a partial prefix at every production decode width") { - Seq(2, 4, 6).foreach { width => - val oooP = OooParams(instructionDecodeWidth = width) - simulate(new OooIfuRawIngress(ifuP, oooP, depthPerStid = 8)) { dut => - clear(dut) - enqueue(dut, stid = 0, firstId = 50, lanes = 1) - dut.io.out.valid.expect(true.B) - dut.io.out.bits.validMask.expect(1.U) - dut.io.out.bits.entries(0).parent.key.instructionId.expect(50.U) - } - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala index e132dbee..13c38d37 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala @@ -2,90 +2,60 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.ParamProfiles import org.scalatest.funsuite.AnyFunSuite -private object OooMemoryOrderAllocatorSpec { - final case class MemoryUop(load: Boolean, store: Boolean, requests: Int) -} - class OooMemoryOrderAllocatorSpec extends AnyFunSuite with ChiselSim { - import OooMemoryOrderAllocatorSpec.MemoryUop + private val base = ParamProfiles.W2 + private val p = base.copy(lsidWidth = 40, + ooo = base.ooo.copy(stidCount = 2)) private def clear(dut: OooMemoryOrderAllocator): Unit = { dut.io.prepare.valid.poke(false.B) dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) dut.io.reserveFire.poke(false.B) dut.io.publishPrepare.valid.poke(false.B) - dut.io.publishPrepare.bits.poke( - 0.U.asTypeOf(dut.io.publishPrepare.bits)) + dut.io.publishPrepare.bits.poke(0.U.asTypeOf(dut.io.publishPrepare.bits)) dut.io.publishFire.poke(false.B) dut.io.cancel.foreach(_.poke(false.B)) dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) + dut.io.recoveryPrepare.bits.poke(0.U.asTypeOf(dut.io.recoveryPrepare.bits)) dut.io.recoveryFire.poke(false.B) } - private def pokeTransaction( - dut: OooMemoryOrderAllocator, - stid: Int, - transactionId: Int, - uops: Seq[MemoryUop], - peId: Int = 3, - epoch: Int = 7): Unit = { - val transaction = dut.io.prepare.bits - transaction.poke(0.U.asTypeOf(transaction)) - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(epoch.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.uopMask.poke(((BigInt(1) << uops.size) - 1).U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(epoch.U) - transaction.decoded.uopMask.poke(((BigInt(1) << uops.size) - 1).U) - val loadIds = uops.filter(_.load).map(_.requests).sum - val storeIds = uops.filter(_.store).map(_.requests).sum - transaction.plan.demand.loadIds.poke(loadIds.U) - transaction.plan.demand.storeIds.poke(storeIds.U) - transaction.decoded.demand.loadIds.poke(loadIds.U) - transaction.decoded.demand.storeIds.poke(storeIds.U) - - uops.zipWithIndex.foreach { case (shape, index) => - val uop = transaction.decoded.uops(index) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.recipe.memoryRequestCount.poke(shape.requests.U) - uop.memory.valid.poke((shape.load || shape.store).B) - uop.memory.isLoad.poke(shape.load.B) - uop.memory.isStore.poke(shape.store.B) + private def prepare(dut: OooMemoryOrderAllocator, stid: Int, + lanes: Seq[(Boolean, Boolean, Int)]): Unit = { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(lanes.size.U) + lanes.zipWithIndex.foreach { case ((load, store, count), lane) => + val row = dut.io.prepare.bits.entries(lane).uop + row.valid.poke(true.B) + row.rob.stid.poke(stid.U) + row.memory.valid.poke((load || store).B) + row.memory.isLoad.poke(load.B) + row.memory.isStore.poke(store.B) + row.memory.requestCount.poke(count.U) } dut.io.prepare.valid.poke(true.B) } private def reserve(dut: OooMemoryOrderAllocator): Unit = { dut.io.prepareReady.expect(true.B) - dut.io.prepared.valid.expect(true.B) dut.io.reserveFire.poke(true.B) dut.clock.step() dut.io.reserveFire.poke(false.B) dut.io.prepare.valid.poke(false.B) } - private def publish( - dut: OooMemoryOrderAllocator, - stid: Int, - transactionId: Int, - peId: Int = 3, - epoch: Int = 7): Unit = { - val reservation = dut.io.publishPrepare.bits - reservation.poke(0.U.asTypeOf(reservation)) - reservation.transaction.plan.peId.poke(peId.U) - reservation.transaction.plan.stid.poke(stid.U) - reservation.transaction.plan.epoch.poke(epoch.U) - reservation.transaction.plan.transactionId.poke(transactionId.U) - reservation.transaction.plan.uopMask.poke( - dut.io.provisional(stid).uopMask.peek()) + private def publish(dut: OooMemoryOrderAllocator, stid: Int): Unit = { + dut.io.publishPrepare.bits.poke(0.U.asTypeOf(dut.io.publishPrepare.bits)) + dut.io.publishPrepare.bits.count.poke(dut.io.provisional(stid).count.peek()) + dut.io.publishPrepare.bits.entries(0).uop.decoded.rob.stid.poke(stid.U) + dut.io.publishPrepare.bits.memoryOrder.poke(dut.io.provisional(stid).peek()) + for (lane <- 0 until p.ooo.d3PrefixWidth) { + dut.io.publishPrepare.bits.entries(lane).memoryOrder.poke( + dut.io.provisionalLanes(stid)(lane).peek()) + } dut.io.publishPrepare.valid.poke(true.B) dut.io.publishReady.expect(true.B) dut.io.publishFire.poke(true.B) @@ -94,257 +64,132 @@ class OooMemoryOrderAllocatorSpec extends AnyFunSuite with ChiselSim { dut.io.publishPrepare.valid.poke(false.B) } - test("assigns unified and type-local full serial ranges atomically") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 4, - decodedUopWidth = 4, renameWidth = 4, dispatchWidth = 4, - retireGroupWidth = 2, lsidWidth = 40) - simulate(new OooMemoryOrderAllocator(p)) { dut => - clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 1, transactionId = 0, Seq( - MemoryUop(load = true, store = false, requests = 1), - MemoryUop(load = false, store = false, requests = 0), - MemoryUop(load = false, store = true, requests = 1), - MemoryUop(load = false, store = true, requests = 2))) - - dut.io.prepared.before.lsid.expect(0.U) - dut.io.prepared.after.lsid.expect(4.U) - dut.io.prepared.after.loadId.expect(1.U) - dut.io.prepared.after.storeId.expect(3.U) - dut.io.prepared.uops(0).firstLsid.expect(0.U) - dut.io.prepared.uops(0).firstTypeId.expect(0.U) - dut.io.prepared.uops(1).memoryValid.expect(false.B) - dut.io.prepared.uops(1).before.lsid.expect(1.U) - dut.io.prepared.uops(1).after.lsid.expect(1.U) - dut.io.prepared.uops(2).firstLsid.expect(1.U) - dut.io.prepared.uops(2).firstTypeId.expect(0.U) - dut.io.prepared.uops(2).before.youngestStoreLsidValid.expect(false.B) - dut.io.prepared.uops(2).after.youngestStoreLsidValid.expect(true.B) - dut.io.prepared.uops(2).after.youngestStoreLsid.expect(1.U) - dut.io.prepared.uops(3).firstLsid.expect(2.U) - dut.io.prepared.uops(3).firstTypeId.expect(1.U) - dut.io.prepared.uops(3).before.youngestStoreLsid.expect(1.U) - dut.io.prepared.uops(3).after.youngestStoreLsid.expect(3.U) - - reserve(dut) - dut.io.provisional(1).valid.expect(true.B) - dut.io.next(1).lsid.expect(4.U) - dut.io.next(1).loadId.expect(1.U) - dut.io.next(1).storeId.expect(3.U) - dut.io.next(1).youngestStoreLsidValid.expect(true.B) - dut.io.next(1).youngestStoreLsid.expect(3.U) - dut.io.next(0).lsid.expect(0.U) - - publish(dut, stid = 1, transactionId = 0) - dut.io.provisional(1).valid.expect(false.B) - dut.io.next(1).lsid.expect(4.U) - } - } - - test("cancel rolls back only the exact provisional STID suffix") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 2, - decodedUopWidth = 2, renameWidth = 2, dispatchWidth = 2, - retireGroupWidth = 2) + test("allocates one mixed prefix from DEC-normalized requestCount") { simulate(new OooMemoryOrderAllocator(p)) { dut => clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 0, transactionId = 0, - Seq(MemoryUop(load = true, store = false, requests = 1))) + prepare(dut, 0, Seq((true, false, 1), (false, true, 2))) + dut.io.preparedLanes(0).requestCount.expect(1.U) + dut.io.preparedLanes(0).firstLsid.expect(0.U) + dut.io.preparedLanes(0).firstLid.expect(0.U) + dut.io.preparedLanes(0).firstSid.expect(0.U) + dut.io.preparedLanes(0).yostValid.expect(false.B) + dut.io.preparedLanes(0).yoldValid.expect(false.B) + dut.io.preparedLanes(1).requestCount.expect(2.U) + dut.io.preparedLanes(1).firstLsid.expect(1.U) + dut.io.preparedLanes(1).firstLid.expect(1.U) + dut.io.preparedLanes(1).firstSid.expect(0.U) + dut.io.preparedLanes(1).yostValid.expect(false.B) + dut.io.preparedLanes(1).yoldValid.expect(true.B) + dut.io.preparedLanes(1).yoldLsid.expect(0.U) + dut.io.preparedLanes(1).yoldLid.expect(0.U) reserve(dut) - dut.io.next(0).lsid.expect(1.U) - dut.io.cancel(0).poke(true.B) - dut.clock.step() - dut.io.cancel(0).poke(false.B) - dut.io.next(0).lsid.expect(0.U) - dut.io.provisional(0).valid.expect(false.B) - dut.io.next(1).lsid.expect(0.U) + dut.io.next(0).lsid.expect(3.U) + dut.io.next(0).lid.expect(1.U) + dut.io.next(0).sid.expect(2.U) + dut.io.next(0).yostValid.expect(true.B) + dut.io.next(0).yostLsid.expect(2.U) + dut.io.next(0).yostSid.expect(1.U) + dut.io.next(0).yoldValid.expect(true.B) + dut.io.next(0).yoldLsid.expect(0.U) + dut.io.next(0).yoldLid.expect(0.U) } } - test("same-cycle publication replaces the exact STID lease without a bubble") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 2, - decodedUopWidth = 2, renameWidth = 2, dispatchWidth = 2, - retireGroupWidth = 2) + test("publishes one provisional prefix and retains the exact serial suffix") { simulate(new OooMemoryOrderAllocator(p)) { dut => clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 0, transactionId = 0, - Seq(MemoryUop(load = true, store = false, requests = 1))) + prepare(dut, 0, Seq((true, false, 1), (false, true, 2))) reserve(dut) - pokeTransaction(dut, stid = 0, transactionId = 1, - Seq(MemoryUop(load = false, store = true, requests = 1))) - val outgoing = dut.io.publishPrepare.bits - outgoing.poke(0.U.asTypeOf(outgoing)) - outgoing.transaction.plan.peId.poke(3.U) - outgoing.transaction.plan.stid.poke(0.U) - outgoing.transaction.plan.epoch.poke(7.U) - outgoing.transaction.plan.transactionId.poke(0.U) - outgoing.transaction.plan.uopMask.poke(1.U) + val publication = dut.io.publishPrepare.bits + publication.poke(0.U.asTypeOf(publication)) + publication.count.poke(1.U) + publication.groupCount.poke(1.U) + publication.entries(0).uop.decoded.rob.stid.poke(0.U) + publication.entries(0).memoryOrder.poke( + dut.io.provisionalLanes(0)(0).peek()) + publication.memoryOrder.valid.poke(true.B) + publication.memoryOrder.stid.poke(0.U) + publication.memoryOrder.count.poke(1.U) + publication.memoryOrder.before.poke(dut.io.provisional(0).before.peek()) + publication.memoryOrder.after.lsid.poke(1.U) + publication.memoryOrder.after.lid.poke(1.U) + publication.memoryOrder.after.sid.poke(0.U) + publication.memoryOrder.after.yoldValid.poke(true.B) + publication.memoryOrder.after.yoldLsid.poke(0.U) + publication.memoryOrder.after.yoldLid.poke(0.U) dut.io.publishPrepare.valid.poke(true.B) dut.io.publishReady.expect(true.B) dut.io.publishFire.poke(true.B) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.before.lsid.expect(1.U) - dut.io.prepared.after.lsid.expect(2.U) - dut.io.reserveFire.poke(true.B) dut.clock.step() - dut.io.reserveFire.poke(false.B) dut.io.publishFire.poke(false.B) dut.io.publishPrepare.valid.poke(false.B) - dut.io.prepare.valid.poke(false.B) dut.io.provisional(0).valid.expect(true.B) - dut.io.provisional(0).transactionId.expect(1.U) + dut.io.provisional(0).count.expect(1.U) dut.io.provisional(0).before.lsid.expect(1.U) - dut.io.provisional(0).after.lsid.expect(2.U) - dut.io.next(0).lsid.expect(2.U) - dut.io.next(0).loadId.expect(1.U) - dut.io.next(0).storeId.expect(1.U) + dut.io.provisional(0).before.lid.expect(1.U) + dut.io.provisional(0).after.lsid.expect(3.U) + dut.io.provisional(0).after.lid.expect(1.U) + dut.io.provisional(0).after.sid.expect(2.U) + dut.io.provisionalLanes(0)(0).requestCount.expect(2.U) + dut.io.provisionalLanes(0)(0).firstLsid.expect(1.U) + dut.io.provisionalLanes(0)(1).requestCount.expect(0.U) + dut.io.next(0).lsid.expect(3.U) + + publish(dut, 0) + dut.io.provisional(0).valid.expect(false.B) + dut.io.next(0).lsid.expect(3.U) } } - test("rejects demand or typed-memory mismatch without claiming serials") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 2, - decodedUopWidth = 2, renameWidth = 2, dispatchWidth = 2, - retireGroupWidth = 2) + test("rejects inconsistent normalized memory shape") { simulate(new OooMemoryOrderAllocator(p)) { dut => clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 0, transactionId = 0, - Seq(MemoryUop(load = true, store = false, requests = 1))) - dut.io.prepare.bits.plan.demand.loadIds.poke(2.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.io.reserveFire.poke(false.B) - dut.clock.step() - dut.io.next(0).lsid.expect(0.U) - dut.io.provisional(0).valid.expect(false.B) - - dut.io.prepare.bits.plan.demand.loadIds.poke(1.U) - dut.io.prepare.bits.decoded.uops(0).memory.isLoad.poke(false.B) + prepare(dut, 0, Seq((false, false, 1))) dut.io.prepareReady.expect(false.B) dut.io.next(0).lsid.expect(0.U) } } - test("global recovery restores the surviving ROB memory tail and kills a provisional suffix") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 2, - decodedUopWidth = 2, renameWidth = 2, dispatchWidth = 2, - retireGroupWidth = 2) + test("cancel rewinds only an unpublished suffix and permits replacement") { simulate(new OooMemoryOrderAllocator(p)) { dut => clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 0, transactionId = 0, Seq( - MemoryUop(load = true, store = false, requests = 1), - MemoryUop(load = false, store = true, requests = 2))) + prepare(dut, 0, Seq((true, false, 1))) reserve(dut) - publish(dut, stid = 0, transactionId = 0) - dut.io.next(0).lsid.expect(3.U) - - pokeTransaction(dut, stid = 0, transactionId = 1, - Seq(MemoryUop(load = true, store = false, requests = 1))) - reserve(dut) - dut.io.next(0).lsid.expect(4.U) - - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.request.rename.key.member.group.valid.poke(true.B) - plan.request.rename.key.member.group.stid.poke(0.U) - plan.oldOccupied.poke(2.U) - plan.newOccupied.poke(1.U) - plan.killedGroupCount.poke(1.U) - plan.pivot.valid.poke(true.B) - plan.pivot.memoryOrderValid.poke(true.B) - plan.pivot.memoryBefore.lsid.poke(0.U) - plan.pivot.memoryAfter.lsid.poke(1.U) - plan.pivot.memoryAfter.loadId.poke(1.U) - plan.survivingTailValid.poke(true.B) - plan.survivingTail.valid.poke(true.B) - plan.survivingTail.memoryOrderValid.poke(true.B) - plan.survivingTail.memoryBefore.lsid.poke(0.U) - plan.survivingTail.memoryAfter.lsid.poke(1.U) - plan.survivingTail.memoryAfter.loadId.poke(1.U) - plan.killedGroups(0).valid.poke(true.B) - plan.killedGroups(0).memoryOrderValid.poke(true.B) - plan.killedGroups(0).memoryBefore.lsid.poke(1.U) - plan.killedGroups(0).memoryBefore.loadId.poke(1.U) - plan.killedGroups(0).memoryAfter.lsid.poke(3.U) - plan.killedGroups(0).memoryAfter.loadId.poke(1.U) - plan.killedGroups(0).memoryAfter.storeId.poke(2.U) - plan.killedGroups(0).memoryAfter.youngestStoreLsidValid.poke(true.B) - plan.killedGroups(0).memoryAfter.youngestStoreLsid.poke(2.U) - dut.io.recoveryPrepare.valid.poke(true.B) - - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.provisionalKilled.expect(true.B) - dut.io.recoveryPrepared.oldPublishedTail.lsid.expect(3.U) - dut.io.recoveryPrepared.newTail.lsid.expect(1.U) - dut.io.recoveryFire.poke(true.B) + dut.io.cancel(0).poke(true.B) dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.next(0).lsid.expect(1.U) - dut.io.next(0).loadId.expect(1.U) - dut.io.next(0).storeId.expect(0.U) - dut.io.provisional(0).valid.expect(false.B) + dut.io.cancel(0).poke(false.B) + dut.io.next(0).lsid.expect(0.U) + prepare(dut, 0, Seq((false, true, 2))) + reserve(dut) + publish(dut, 0) + dut.io.next(0).lsid.expect(2.U) } } - test("partial pivot recovery distinguishes the old published tail from the trimmed tail") { - val p = OooParams(stidCount = 2, instructionDecodeWidth = 2, - decodedUopWidth = 2, renameWidth = 2, dispatchWidth = 2, - retireGroupWidth = 2) + test("recovery preview and abort do not mutate while apply restores target only") { simulate(new OooMemoryOrderAllocator(p)) { dut => clear(dut) - dut.clock.step() - - pokeTransaction(dut, stid = 0, transactionId = 0, Seq( - MemoryUop(load = true, store = false, requests = 1), - MemoryUop(load = false, store = true, requests = 1))) - reserve(dut) - publish(dut, stid = 0, transactionId = 0) - dut.io.next(0).lsid.expect(2.U) - - val plan = dut.io.recoveryPrepare.bits - plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.request.rename.key.member.group.valid.poke(true.B) - plan.request.rename.key.member.group.stid.poke(0.U) - plan.oldOccupied.poke(1.U) - plan.newOccupied.poke(1.U) - plan.killedGroupCount.poke(0.U) - plan.pivot.valid.poke(true.B) - plan.pivot.memoryOrderValid.poke(true.B) - plan.pivot.memoryAfter.lsid.poke(2.U) - plan.pivot.memoryAfter.loadId.poke(1.U) - plan.pivot.memoryAfter.storeId.poke(1.U) - plan.pivot.memoryAfter.youngestStoreLsidValid.poke(true.B) - plan.pivot.memoryAfter.youngestStoreLsid.poke(1.U) - plan.survivingPivotValid.poke(true.B) - plan.survivingTailValid.poke(true.B) - plan.survivingTail.valid.poke(true.B) - plan.survivingTail.memoryOrderValid.poke(true.B) - plan.survivingTail.memoryAfter.lsid.poke(1.U) - plan.survivingTail.memoryAfter.loadId.poke(1.U) + for (stid <- 0 to 1) { + prepare(dut, stid, Seq((true, false, 1))) + reserve(dut); publish(dut, stid) + } + dut.io.recoveryPrepare.bits.valid.poke(true.B) + dut.io.recoveryPrepare.bits.stid.poke(0.U) + dut.io.recoveryPrepare.bits.oldTail.poke(dut.io.next(0).peek()) + dut.io.recoveryPrepare.bits.newTail.poke( + 0.U.asTypeOf(dut.io.recoveryPrepare.bits.newTail)) dut.io.recoveryPrepare.valid.poke(true.B) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.oldPublishedTail.lsid.expect(2.U) - dut.io.recoveryPrepared.newTail.lsid.expect(1.U) + dut.clock.step(2) // Prepare then Abort/no terminal fire: no mutation. + dut.io.next(0).lsid.expect(1.U) + dut.io.next(1).lsid.expect(1.U) dut.io.recoveryFire.poke(true.B) dut.clock.step() dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.next(0).lsid.expect(1.U) - dut.io.next(0).loadId.expect(1.U) - dut.io.next(0).storeId.expect(0.U) + dut.io.next(0).lsid.expect(0.U) + dut.io.next(1).lsid.expect(1.U) } } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooO3FastResolveIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooO3FastResolveIntegrationSpec.scala deleted file mode 100644 index 47d55f9b..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooO3FastResolveIntegrationSpec.scala +++ /dev/null @@ -1,229 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.DestinationKind -import org.scalatest.funsuite.AnyFunSuite - -class OooO3FastResolveIntegrationSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooO3RenameCoordinator): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.iexS1.ready.poke(false.B) - dut.io.fastBoundary.ready.poke(true.B) - dut.io.fastWriteback.ready.poke(true.B) - dut.io.fastWakeup.ready.poke(true.B) - dut.io.fastTrace.ready.poke(true.B) - dut.io.completions.foreach { completion => - completion.valid.poke(false.B) - completion.bits.poke(0.U.asTypeOf(completion.bits)) - } - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.commit.ready.poke(false.B) - dut.io.storeCommit.ready.poke(true.B) - dut.io.ptagRecycle.ready.poke(true.B) - dut.io.dispatchRelease.valid.poke(false.B) - dut.io.dispatchRelease.bits.poke( - 0.U.asTypeOf(dut.io.dispatchRelease.bits)) - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.iexRecoveryPrepareReady.poke(true.B) - dut.io.iexRecoveryPrepared.poke( - 0.U.asTypeOf(dut.io.iexRecoveryPrepared)) - dut.io.iexRecoveryRejected.valid.poke(false.B) - dut.io.iexRecoveryRejected.bits.poke( - 0.U.asTypeOf(dut.io.iexRecoveryRejected.bits)) - dut.io.queryStid.poke(0.U) - dut.io.queryAtag.poke(10.U) - dut.io.pcReadTokens.foreach(_.poke( - 0.U.asTypeOf(dut.io.pcReadTokens.head))) - } - - private def pokeSetret(dut: OooO3RenameCoordinator): Unit = { - val transaction = dut.io.reserve.bits - transaction.poke(0.U.asTypeOf(transaction)) - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(0.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(0.U) - transaction.plan.uopMask.poke(1.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.virtualTailEpoch.poke(0.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(3.U) - transaction.plan.firstVirtualGroup.stid.poke(0.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(0.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(0.U) - transaction.plan.demand.pDestinations.poke(1.U) - transaction.plan.demand.mapQRows.poke(1.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(0.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(1.U) - transaction.groupMask.poke(1.U) - transaction.uopGroupIndex(0).poke(0.U) - transaction.uopMemberBase(0).poke(0.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(0.U) - group.key.ridSlot.poke(0.U) - group.key.ridGeneration.poke(0.U) - group.logicalUopMask.poke(1.U) - group.physicalMemberCount.poke(1.U) - group.pMapQRows.poke(1.U) - group.architecturalParentCount.poke(1.U) - group.boundaryStart.poke(true.B) - group.boundaryStop.poke(true.B) - group.releasePcBase.poke(true.B) - - val uop = transaction.decoded.uops(0) - uop.valid.poke(true.B) - uop.opcode.poke(343.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(343.U) - uop.recipe.disposition.poke(OooOpcodeDisposition.FastResolve.U) - uop.recipe.recipeKind.poke(OooOpcodeRecipeKind.Setret.U) - uop.recipe.uopCountMin.poke(1.U) - uop.recipe.uopCountMax.poke(1.U) - uop.recipe.fastResolveClass.poke( - OooFastResolveClass.ImmediateProducer.U) - uop.recipe.pDestinationCount.poke(1.U) - uop.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) - uop.plannedChildCount.poke(1.U) - uop.immediateValid.poke(true.B) - uop.immediate.poke(0x28.U) - uop.identity.key.primaryParent.valid.poke(true.B) - uop.identity.key.primaryParent.peId.poke(3.U) - uop.identity.key.primaryParent.stid.poke(0.U) - uop.identity.key.primaryParent.instructionId.poke(190.U) - uop.identity.key.primaryParent.epoch.poke(5.U) - uop.identity.key.uopOrdinal.poke(0.U) - uop.identity.key.uopCount.poke(1.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(0.U) - uop.identity.parents(0).key.instructionId.poke(190.U) - uop.identity.parents(0).key.epoch.poke(5.U) - uop.identity.parents(0).pc.poke(0x400.U) - uop.identity.parents(0).lengthBytes.poke(4.U) - uop.destinations(0).valid.poke(true.B) - uop.destinations(0).kind.poke(DestinationKind.Gpr) - uop.destinations(0).atag.poke(10.U) - dut.io.reserve.valid.poke(true.B) - } - - private def waitForCommit( - dut: OooO3RenameCoordinator, - limit: Int = 32): Unit = { - var cycles = 0 - while (!dut.io.commit.valid.peek().litToBoolean && cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(cycles < limit, "timed out waiting for fast-resolved commit") - } - - test("publishes SETRET without IQ residency and completes the exact ROB member") { - val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 16, - tPhysRegs = 8, - uPhysRegs = 8, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - pokeSetret(dut) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - var prepareCycles = 0 - while (!dut.io.preparedValid.peek().litToBoolean && prepareCycles < 8) { - dut.clock.step() - prepareCycles += 1 - } - assert(prepareCycles < 8, - s"SETRET prepare missing: p=${dut.io.prepared.valid.peek().litValue} " + - s"tu=${dut.io.tuPrepared.valid.peek().litValue} " + - s"dispatch=${dut.io.dispatchPrepared.valid.peek().litValue} " + - s"ptagProv=${dut.io.ptagProvisionalCount.peek().litValue}") - - dut.io.fastWriteback.ready.poke(false.B) - dut.io.iexS1.ready.poke(true.B) - dut.io.fastS1Rejected.valid.expect(false.B) - dut.io.iexS1.valid.expect(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - - dut.io.fastPendingByStid(0).expect(1.U) - dut.io.fastWriteback.valid.expect(true.B) - dut.io.fastWriteback.bits.data.expect(0x428.U) - dut.io.fastTerminalFire.expect(false.B) - for (clazz <- 0 until p.iqClassCount; bank <- 0 until p.iqBankCount) { - dut.io.dispatchPublishedEntries(clazz)(bank).expect(0.U) - } - dut.clock.step(2) - dut.io.robOccupiedGroups(0).expect(1.U) - dut.io.fastPendingByStid(0).expect(1.U) - - // A malformed global request is accepted into the retained coordinator, - // then rejected without applying any fast-owner mutation. - dut.io.recoveryRequest.valid.poke(true.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.recoveryRequest.bits.rename.key.member.group.stid.poke(0.U) - dut.io.recoveryRequest.ready.expect(true.B) - dut.io.recoveryBusy.expect(false.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - var recoveryCycles = 0 - while (dut.io.recoveryBusy.peek().litToBoolean && recoveryCycles < 8) { - dut.clock.step() - recoveryCycles += 1 - } - assert(recoveryCycles < 8, "malformed global recovery did not abort") - dut.io.fastPendingByStid(0).expect(1.U) - dut.io.fastWriteback.valid.expect(true.B) - dut.io.fastTerminalFire.expect(false.B) - - dut.io.fastWriteback.ready.poke(true.B) - dut.io.fastTerminalFire.expect(true.B) - dut.io.fastWakeup.valid.expect(true.B) - dut.io.fastTrace.valid.expect(true.B) - dut.clock.step() - dut.io.fastPendingByStid(0).expect(0.U) - - waitForCommit(dut) - dut.io.commit.bits.release.firstGroup.stid.expect(0.U) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.mapQUsed(0).expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala deleted file mode 100644 index e9c1ae85..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala +++ /dev/null @@ -1,311 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.HasSimulator -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.{Decoupled, Valid} -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite -import svsim.verilator.Backend - -class OooO3IexIntegrationHarnessIO(val p: OooParams) extends Bundle { - val reserve = Flipped(Decoupled(new OooD2GroupedTransaction(p))) - val release = Flipped(Decoupled(new OooIexIssueRelease(p))) - val recoveryRequest = Flipped(Decoupled(new OooGlobalRecoveryRequest(p))) - val query = Input(new OooIexSlotQuery(p)) - - val publishFire = Output(Bool()) - val recoveryBusy = Output(Bool()) - val recoveryComplete = Output(Bool()) - val recoveryApplied = Valid(new OooGlobalRecoveryRequest(p)) - val s2Bind = Valid(new OooIexS2BindAck(p)) - val s3Enable = Valid(new OooIexS3Enable(p)) - val queryState = Output(OooIexIssueSlotState()) - val queryPickable = Output(Bool()) - val queryMember = Output(new RobMemberKey(p)) - val queryReservation = Output(new DispatchReservation(p)) - val queryMemoryOrder = Output(new OooMemoryOrderUopAllocation(p)) - val memoryOrderNext = Output(Vec(p.stidCount, new OooMemoryIdState(p))) - val dispatchPublishedEntries = Output(Vec(p.iqClassCount, - Vec(p.iqBankCount, UInt(p.iqBankEntryCountWidth.W)))) - val robOccupiedGroups = Output(Vec(p.stidCount, - UInt(p.countWidth(p.robGroupsPerStid).W))) - val mapQUsed = Output(Vec(p.stidCount, UInt(p.pMapQCountWidth.W))) -} - -/** Minimal integration shell for the real O3/RENU/dispatch-to-IEX seam. */ -class OooO3IexIntegrationHarness(val p: OooParams) extends Module { - val io = IO(new OooO3IexIntegrationHarnessIO(p)) - - val coordinator = Module(new OooO3RenameCoordinator(p)) - coordinator.io.storeCommit.ready := true.B - val issue = Module(new OooIexIssue(p)) - - coordinator.io.reserve.valid := io.reserve.valid - coordinator.io.reserve.bits := io.reserve.bits - io.reserve.ready := coordinator.io.reserve.ready - coordinator.io.cancel.foreach(_ := false.B) - coordinator.io.completions.foreach { completion => - completion.valid := false.B - completion.bits := 0.U.asTypeOf(completion.bits) - } - coordinator.io.nonFlushEvidence.valid := false.B - coordinator.io.nonFlushEvidence.bits := - 0.U.asTypeOf(coordinator.io.nonFlushEvidence.bits) - coordinator.io.interruptPending.foreach(_ := false.B) - coordinator.io.commit.ready := false.B - coordinator.io.fastBoundary.ready := true.B - coordinator.io.fastWriteback.ready := true.B - coordinator.io.fastWakeup.ready := true.B - coordinator.io.fastTrace.ready := true.B - coordinator.io.recoveryRequest <> io.recoveryRequest - coordinator.io.queryStid := 0.U - coordinator.io.queryAtag := 0.U - coordinator.io.pcReadTokens.foreach { token => - token := 0.U.asTypeOf(token) - } - - issue.io.s1 <> coordinator.io.iexS1 - issue.io.storeReserve.ready := true.B - coordinator.io.dispatchRelease <> issue.io.dispatchRelease - issue.io.ptagRecycle <> coordinator.io.ptagRecycle - issue.io.wakeup.foreach { wakeup => - wakeup.valid := false.B - wakeup.bits := 0.U.asTypeOf(wakeup.bits) - } - issue.io.loadCancel.foreach { cancel => - cancel.valid := false.B - cancel.bits := 0.U.asTypeOf(cancel.bits) - } - issue.io.release.valid := io.release.valid - issue.io.release.bits := io.release.bits - io.release.ready := issue.io.release.ready - issue.io.query := io.query - issue.io.pickBankEnable.foreach(_ := 0.U) - issue.io.pickBankEnable(OooUopClass.Agu.asUInt.litValue.toInt) := - ((BigInt(1) << p.iqBankCount) - 1).U - issue.io.issuePolicy := 0.U.asTypeOf(issue.io.issuePolicy) - issue.io.pick.ready := false.B - issue.io.pickRetry.valid := false.B - issue.io.pickRetry.bits := 0.U.asTypeOf(issue.io.pickRetry.bits) - issue.io.recoveryPrepare := coordinator.io.iexRecoveryPrepare - coordinator.io.iexRecoveryPrepareReady := issue.io.recoveryPrepareReady - coordinator.io.iexRecoveryPrepared := issue.io.recoveryPrepared - coordinator.io.iexRecoveryRejected := issue.io.recoveryRejected - issue.io.recoveryFire := coordinator.io.iexRecoveryFire - - io.publishFire := coordinator.io.publishFire - io.recoveryBusy := coordinator.io.recoveryBusy - io.recoveryComplete := coordinator.io.recoveryComplete - io.recoveryApplied := coordinator.io.recoveryApplied - io.s2Bind := issue.io.s2Bind - io.s3Enable := issue.io.s3Enable - io.queryState := issue.io.queryState - io.queryPickable := issue.io.queryPickable - io.queryMember := issue.io.queryRow.member - io.queryReservation := issue.io.queryRow.reservation - io.queryMemoryOrder := issue.io.queryRow.memoryOrder - io.memoryOrderNext := coordinator.io.memoryOrderNext - io.dispatchPublishedEntries := coordinator.io.dispatchPublishedEntries - io.robOccupiedGroups := coordinator.io.robOccupiedGroups - io.mapQUsed := coordinator.io.mapQUsed -} - -class OooO3IexIntegrationSpec extends AnyFunSuite with ChiselSim { - private implicit val boundedVerilator: HasSimulator = - HasSimulator.simulators.verilator(verilatorSettings = - Backend.CompilationSettings.default - .withOutputSplit(Some(2000)) - .withOutputSplitCFuncs(Some(100)) - .withParallelism(Some( - Backend.CompilationSettings.Parallelism.Different.default - .withBuild(Some(1)).withVerilate(Some(1))))) - - private def clear(dut: OooO3IexIntegrationHarness): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.release.valid.poke(false.B) - dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.query.poke(0.U.asTypeOf(dut.io.query)) - } - - private def pokeTransaction(dut: OooO3IexIntegrationHarness): Unit = { - val transaction = dut.io.reserve.bits - transaction.poke(0.U.asTypeOf(transaction)) - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(0.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(0.U) - transaction.plan.uopMask.poke(1.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(3.U) - transaction.plan.firstVirtualGroup.stid.poke(0.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(0.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(0.U) - transaction.plan.demand.pDestinations.poke(1.U) - transaction.plan.demand.mapQRows.poke(1.U) - transaction.plan.demand.dispatchWritesByClass(2).poke(1.U) - transaction.plan.demand.loadIds.poke(1.U) - - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(0.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(1.U) - transaction.decoded.demand.loadIds.poke(1.U) - transaction.groupMask.poke(1.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(0.U) - group.key.ridSlot.poke(0.U) - group.key.ridGeneration.poke(0.U) - group.logicalUopMask.poke(1.U) - group.physicalMemberCount.poke(1.U) - group.pMapQRows.poke(1.U) - group.architecturalParentCount.poke(1.U) - group.boundaryStart.poke(true.B) - group.boundaryStop.poke(true.B) - group.releasePcBase.poke(true.B) - - transaction.uopGroupIndex(0).poke(0.U) - transaction.uopMemberBase(0).poke(0.U) - val uop = transaction.decoded.uops(0) - uop.valid.poke(true.B) - uop.opcode.poke(42.U) - uop.recipe.valid.poke(true.B) - uop.recipe.opcode.poke(42.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Agu.U) - uop.recipe.dispatchWrites.poke(1.U) - uop.recipe.dispatchDemand(2).poke(1.U) - uop.recipe.dispatchCapabilities(2).poke( - OooIexDomainCapability.mask(OooIexDomainCapability.LoadAddress).U) - uop.recipe.memoryRequestCount.poke(1.U) - uop.memory.valid.poke(true.B) - uop.memory.isLoad.poke(true.B) - uop.plannedChildCount.poke(1.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(0.U) - uop.identity.parents(0).key.instructionId.poke(100.U) - uop.identity.parents(0).key.epoch.poke(5.U) - uop.identity.parents(0).pc.poke(256.U) - uop.sources(0).valid.poke(true.B) - uop.sources(0).operandClass.poke(OperandClass.P) - uop.sources(0).atag.poke(1.U) - uop.destinations(0).valid.poke(true.B) - uop.destinations(0).kind.poke(DestinationKind.Gpr) - uop.destinations(0).atag.poke(1.U) - dut.io.reserve.valid.poke(true.B) - } - - private def pokeGlobalRecovery(dut: OooO3IexIntegrationHarness): Unit = { - val global = dut.io.recoveryRequest.bits - global.poke(0.U.asTypeOf(global)) - val request = global.rename - request.key.member.group.valid.poke(true.B) - request.key.member.group.peId.poke(3.U) - request.key.member.group.stid.poke(0.U) - request.key.member.group.ridSlot.poke(0.U) - request.key.member.group.ridGeneration.poke(0.U) - request.key.member.bid.valid.poke(true.B) - request.key.member.bid.value.poke(0.U) - request.key.member.brobGeneration.poke(0.U) - request.key.member.memberIndex.poke(0.U) - request.key.member.residentGeneration.poke(1.U) - request.key.cause.poke(OooRecoveryCause.Branch) - request.key.transactionId.poke(0.U) - request.key.epoch.poke(5.U) - request.killTrigger.poke(true.B) - global.triggerMemberCount.poke(1.U) - dut.io.recoveryRequest.valid.poke(true.B) - } - - test("publishes one exact O3 row then globally recovers ROB rename dispatch and IEX") { - val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - dispatchWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 2, - iqWritePortsPerBank = 2, - robGroupsPerStid = 4, - brobEntriesPerStid = 4, - pTagStagingDepthPerBank = 2, - pMapQDepthPerStid = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 8) - simulate(new OooO3IexIntegrationHarness(p)) { dut => - clear(dut) - dut.clock.step() // fill PTag staging - pokeTransaction(dut) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - dut.io.publishFire.expect(true.B) - dut.clock.step() // exact O3/RENU/dispatch/IEX-S1 common fire - dut.io.dispatchPublishedEntries(2)(0).expect(1.U) - dut.io.s2Bind.valid.expect(true.B) - dut.clock.step() // S2 physical row bind - dut.io.s3Enable.valid.expect(true.B) - dut.clock.step() // S3 pick enable - - dut.io.query.uopClass.poke(OooUopClass.Agu) - dut.io.query.bank.poke(0.U) - dut.io.query.entry.poke(0.U) - dut.io.queryState.expect(OooIexIssueSlotState.ResidentS3) - dut.io.queryPickable.expect(true.B) - dut.io.queryMember.memberIndex.expect(0.U) - dut.io.queryMember.residentGeneration.expect(1.U) - dut.io.queryReservation.valid.expect(true.B) - dut.io.queryReservation.writePort.expect(0.U) - dut.io.queryReservation.reservationEpoch.expect(1.U) - dut.io.queryMemoryOrder.valid.expect(true.B) - dut.io.queryMemoryOrder.memoryValid.expect(true.B) - dut.io.queryMemoryOrder.isLoad.expect(true.B) - dut.io.queryMemoryOrder.requestCount.expect(1.U) - dut.io.queryMemoryOrder.firstLsid.expect(0.U) - dut.io.queryMemoryOrder.firstTypeId.expect(0.U) - dut.io.queryMemoryOrder.after.lsid.expect(1.U) - dut.io.queryMemoryOrder.after.loadId.expect(1.U) - dut.io.memoryOrderNext(0).lsid.expect(1.U) - dut.io.memoryOrderNext(0).loadId.expect(1.U) - - dut.io.dispatchPublishedEntries(2)(0).expect(1.U) - dut.io.robOccupiedGroups(0).expect(1.U) - dut.io.mapQUsed(0).expect(1.U) - - pokeGlobalRecovery(dut) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - - var cycles = 0 - var sawApplied = false - var sawComplete = false - while (dut.io.recoveryBusy.peek().litToBoolean && cycles < 64) { - sawApplied ||= dut.io.recoveryApplied.valid.peek().litToBoolean - sawComplete ||= dut.io.recoveryComplete.peek().litToBoolean - dut.clock.step() - cycles += 1 - } - assert(cycles < 64, "global O3/IEX recovery did not complete") - assert(sawApplied, "global recovery never produced one common apply") - assert(sawComplete, "global recovery never reached R4 completion") - dut.io.queryState.expect(OooIexIssueSlotState.Free) - dut.io.dispatchPublishedEntries(0)(0).expect(0.U) - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.memoryOrderNext(0).lsid.expect(0.U) - dut.io.memoryOrderNext(0).loadId.expect(0.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooO3IexStorePipelineSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooO3IexStorePipelineSpec.scala deleted file mode 100644 index 72b86d57..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooO3IexStorePipelineSpec.scala +++ /dev/null @@ -1,56 +0,0 @@ -package linxcore.ooo - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -class OooO3IexStorePipelineSpec extends AnyFunSuite { - test("elaborates the closed O3 to IEX to canonical store-retirement path") { - val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robCompletionBufferEntries = 4, - storeCommitBufferEntries = 8, - maxInstPerRobGroup = 2, - maxOrdinaryUopsPerGroup = 2, - maxRecipeUops = 2, - robGroupsPerStid = 4, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - brobEntriesPerStid = 4, - pPhysRegs = 64, - pTagStagingDepthPerBank = 2, - pMapQDepthPerStid = 4, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4, - tuRetireSourceDepthPerStid = 8, - tuRelationDepthPerStid = 4, - tuRelationReleaseThreshold = 2, - pcBufferEntries = 4, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqEntriesPerBank = 1, - iqWritePortsPerBank = 2, - iqFreeSelectLeafEntries = 1, - iexLoadTrackEntries = 4) - // The complete O3+IEX hierarchy intentionally exceeds the 4 GiB local - // FIRRTL-to-SystemVerilog test budget. CHIRRTL still elaborates every - // Chisel owner and connection while the child SV gates cover lowering. - val chirrtl = ChiselStage.emitCHIRRTL( - new OooO3IexStorePipeline( - OooIexLinxPhysicalProfile(p), stqEntries = 4)) - - assert(chirrtl.contains("circuit OooO3IexStorePipeline")) - assert(chirrtl.contains("inst o3 of OooO3RenameCoordinator")) - assert(chirrtl.contains("inst completionBuffer of OooRobCompletionBuffer")) - assert(chirrtl.contains("inst iex of OooIexExecutionStorePipeline")) - assert(chirrtl.contains("inst fastResult of OooIexFastResultPort")) - assert(chirrtl.contains("inst storeCommit of STQSCBCommitBackend")) - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooO3RenameCoordinatorSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooO3RenameCoordinatorSpec.scala deleted file mode 100644 index 30fda710..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooO3RenameCoordinatorSpec.scala +++ /dev/null @@ -1,871 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -class OooO3RenameCoordinatorSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooO3RenameCoordinator): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.iexS1.ready.poke(false.B) - dut.io.fastBoundary.ready.poke(true.B) - dut.io.fastWriteback.ready.poke(true.B) - dut.io.fastWakeup.ready.poke(true.B) - dut.io.fastTrace.ready.poke(true.B) - dut.io.completions.foreach { completion => - completion.valid.poke(false.B) - completion.bits.poke(0.U.asTypeOf(completion.bits)) - } - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.commit.ready.poke(false.B) - dut.io.storeCommit.ready.poke(true.B) - dut.io.ptagRecycle.ready.poke(true.B) - dut.io.dispatchRelease.valid.poke(false.B) - dut.io.dispatchRelease.bits.poke( - 0.U.asTypeOf(dut.io.dispatchRelease.bits)) - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.iexRecoveryPrepareReady.poke(true.B) - dut.io.iexRecoveryPrepared.poke( - 0.U.asTypeOf(dut.io.iexRecoveryPrepared)) - dut.io.iexRecoveryRejected.valid.poke(false.B) - dut.io.iexRecoveryRejected.bits.poke( - 0.U.asTypeOf(dut.io.iexRecoveryRejected.bits)) - dut.io.queryStid.poke(0.U) - dut.io.queryAtag.poke(0.U) - dut.io.pcReadTokens.foreach(_.poke(0.U.asTypeOf(dut.io.pcReadTokens.head))) - } - - private def pokeOneDestination( - dut: OooO3RenameCoordinator, - tailEpoch: Int = 0, - uopCount: Int = 1, - stid: Int = 0, - transactionId: Int = 0, - firstRid: Int = 0, - atag: Int = 1, - basePc: Int = 256): Unit = { - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - val transaction = dut.io.reserve.bits - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(transactionId.U) - val uopMask = (1 << uopCount) - 1 - transaction.plan.uopMask.poke(uopMask.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.virtualTailEpoch.poke(tailEpoch.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(3.U) - transaction.plan.firstVirtualGroup.stid.poke(stid.U) - transaction.plan.firstVirtualGroup.ridSlot.poke( - (firstRid % dut.p.robGroupsPerStid).U) - transaction.plan.firstVirtualGroup.ridGeneration.poke( - (firstRid / dut.p.robGroupsPerStid).U) - transaction.plan.demand.pDestinations.poke(uopCount.U) - transaction.plan.demand.mapQRows.poke(uopCount.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(uopMask.U) - transaction.groupMask.poke(1.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((firstRid % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((firstRid / dut.p.robGroupsPerStid).U) - group.logicalUopMask.poke(uopMask.U) - group.physicalMemberCount.poke(uopCount.U) - group.pMapQRows.poke(uopCount.U) - group.architecturalParentCount.poke(uopCount.U) - group.boundaryStart.poke(true.B) - group.boundaryStop.poke(true.B) - group.releasePcBase.poke(true.B) - - for (uopIndex <- 0 until uopCount) { - transaction.uopGroupIndex(uopIndex).poke(0.U) - transaction.uopMemberBase(uopIndex).poke(uopIndex.U) - val uop = transaction.decoded.uops(uopIndex) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.plannedChildCount.poke(1.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke( - (100 + 10 * transactionId + uopIndex).U) - uop.identity.parents(0).key.epoch.poke(5.U) - uop.identity.parents(0).pc.poke((basePc + 4 * uopIndex).U) - uop.sources(0).valid.poke(true.B) - uop.sources(0).operandClass.poke(OperandClass.P) - uop.sources(0).atag.poke(atag.U) - uop.destinations(0).valid.poke(true.B) - uop.destinations(0).kind.poke(DestinationKind.Gpr) - uop.destinations(0).atag.poke(atag.U) - } - dut.io.reserve.valid.poke(true.B) - } - - private def completeMembers( - dut: OooO3RenameCoordinator, - stid: Int, - rid: Int, - memberCount: Int, - bid: Int = 0, - brobGeneration: Int = 0, - residentGeneration: Int = 1): Unit = { - for (memberIndex <- 0 until memberCount) { - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - val key = dut.io.completion.bits.key - key.group.valid.poke(true.B) - key.group.peId.poke(3.U) - key.group.stid.poke(stid.U) - key.group.ridSlot.poke((rid % dut.p.robGroupsPerStid).U) - key.group.ridGeneration.poke((rid / dut.p.robGroupsPerStid).U) - key.bid.valid.poke(true.B) - key.bid.value.poke(bid.U) - key.brobGeneration.poke(brobGeneration.U) - key.memberIndex.poke(memberIndex.U) - key.residentGeneration.poke(residentGeneration.U) - dut.io.completion.valid.poke(true.B) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - } - } - - private def waitForCommit( - dut: OooO3RenameCoordinator, - limit: Int = 32): Unit = { - var cycles = 0 - while (!dut.io.commit.valid.peek().litToBoolean && cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(cycles < limit, - "timed out waiting for the shared P/T/U commit owners") - } - - private def waitForPCommitBusy( - dut: OooO3RenameCoordinator, - limit: Int = 32): Unit = { - var cycles = 0 - while (!dut.io.pCommitBusy.peek().litToBoolean && cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(cycles < limit, - "timed out waiting for the retained P commit walk") - } - - private def acceptPtagRecycle( - dut: OooO3RenameCoordinator, - expectedPtag: Int, - limit: Int = 16): Unit = { - var cycles = 0 - while (!dut.io.ptagRecycle.valid.peek().litToBoolean && cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(cycles < limit, "timed out waiting for retained PTag recycle") - dut.io.ptagRecycle.bits.count.expect(1.U) - dut.io.ptagRecycle.bits.tokens(0).ptag.expect(expectedPtag.U) - dut.clock.step() - } - - private def pokeLocalRenameChain( - dut: OooO3RenameCoordinator, - tailEpoch: Int = 0, - stid: Int = 0, - transactionId: Int = 0, - firstRid: Int = 0): Unit = { - pokeOneDestination(dut, tailEpoch = tailEpoch, uopCount = 2, - stid = stid, transactionId = transactionId, firstRid = firstRid) - val transaction = dut.io.reserve.bits - transaction.plan.demand.pDestinations.poke(0.U) - transaction.plan.demand.mapQRows.poke(0.U) - transaction.plan.demand.tAllocations.poke(1.U) - transaction.plan.demand.uAllocations.poke(1.U) - transaction.groups(0).pMapQRows.poke(0.U) - - val producer = transaction.decoded.uops(0) - producer.sources(0).valid.poke(false.B) - producer.destinations(0).kind.poke(DestinationKind.T) - producer.destinations(0).relativeIndex.poke(0.U) - - val consumer = transaction.decoded.uops(1) - consumer.sources(0).operandClass.poke(OperandClass.T) - consumer.sources(0).relativeIndex.poke(0.U) - consumer.destinations(0).kind.poke(DestinationKind.U) - consumer.destinations(0).relativeIndex.poke(0.U) - } - - private def pokeMixedRenameTransaction( - dut: OooO3RenameCoordinator, - tailEpoch: Int, - stid: Int, - transactionId: Int, - firstRid: Int, - atag: Int = 1, - basePc: Int = 512): Unit = { - pokeOneDestination(dut, tailEpoch = tailEpoch, uopCount = 2, - stid = stid, transactionId = transactionId, firstRid = firstRid, - atag = atag, basePc = basePc) - val transaction = dut.io.reserve.bits - transaction.plan.demand.pDestinations.poke(1.U) - transaction.plan.demand.mapQRows.poke(1.U) - transaction.plan.demand.tAllocations.poke(1.U) - transaction.plan.demand.uAllocations.poke(1.U) - transaction.groups(0).pMapQRows.poke(1.U) - - val first = transaction.decoded.uops(0) - first.destinations(1).valid.poke(true.B) - first.destinations(1).kind.poke(DestinationKind.T) - first.destinations(1).relativeIndex.poke(0.U) - - val second = transaction.decoded.uops(1) - second.destinations(0).kind.poke(DestinationKind.U) - second.destinations(0).relativeIndex.poke(0.U) - } - - private def pokeRecoveryRequest( - dut: OooO3RenameCoordinator, - stid: Int, - transactionId: Int, - rid: Int, - bid: BigInt, - brobGeneration: BigInt, - memberIndex: BigInt, - residentGeneration: BigInt, - killTrigger: Boolean, - epoch: Int = 5): Unit = { - val global = dut.io.recoveryRequest.bits - val request = global.rename - request.poke(0.U.asTypeOf(request)) - request.key.member.group.valid.poke(true.B) - request.key.member.group.peId.poke(3.U) - request.key.member.group.stid.poke(stid.U) - request.key.member.group.ridSlot.poke( - (rid % dut.p.robGroupsPerStid).U) - request.key.member.group.ridGeneration.poke( - (rid / dut.p.robGroupsPerStid).U) - request.key.member.bid.valid.poke(true.B) - request.key.member.bid.value.poke(bid.U) - request.key.member.brobGeneration.poke(brobGeneration.U) - request.key.member.memberIndex.poke(memberIndex.U) - request.key.member.residentGeneration.poke(residentGeneration.U) - request.key.cause.poke(OooRecoveryCause.Branch) - request.key.transactionId.poke(transactionId.U) - request.key.epoch.poke(epoch.U) - request.killTrigger.poke(killTrigger.B) - global.triggerMemberCount.poke(1.U) - dut.io.iexRecoveryPrepared.valid.poke(true.B) - dut.io.iexRecoveryPrepared.stid.poke(stid.U) - } - - test("joins D3 PTag ROB BROB PC SMAP and MapQ publication on one fire") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() // refill the PTag staging rows - pokeOneDestination(dut) - dut.io.reserve.bits.decoded.uops(0).recipe.valid.poke(true.B) - dut.io.reserve.bits.decoded.uops(0).recipe.dispatchWrites.poke(1.U) - dut.io.reserve.bits.decoded.uops(0).recipe.dispatchDemand(0).poke(1.U) - dut.io.reserve.bits.decoded.uops(0).recipe.dispatchCapabilities(0).poke( - OooIexDomainCapability.mask(OooIexDomainCapability.SimpleAlu).U) - dut.io.reserve.bits.plan.demand.dispatchWritesByClass(0).poke(1.U) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - dut.io.tuPublicationRejected.valid.expect(false.B) - dut.io.tuPrepared.valid.expect(true.B) - dut.io.prepared.valid.expect(true.B) - dut.io.preparedValid.expect(true.B) - dut.io.prepared.uops(0).sources(0).pMapping.ptag.expect(1.U) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.expect(96.U) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.producerBindingValid.expect(true.B) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.producerIqClass.expect(OooUopClass.Alu) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.producerIqBank.expect(0.U) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.producerIqEntry.expect(0.U) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.producerIqEpoch.expect(1.U) - dut.io.dispatchPrepared.valid.expect(true.B) - dut.io.dispatchPrepared.allocations(0).reservation - .uopClass.expect(OooUopClass.Alu) - dut.io.ptagProvisionalCount.expect(1.U) - dut.io.ptagPublishedCount.expect(0.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.iexS1.valid.expect(true.B) - dut.io.iexS1.bits.o3.request.reservation.transaction.plan - .transactionId.expect(0.U) - dut.io.iexS1.bits.pRename.uops(0).destinations(0) - .currentPMapping.ptag.expect(96.U) - dut.io.iexS1.bits.dispatch.allocations(0).reservation - .reservationEpoch.expect(1.U) - dut.clock.step(2) - dut.io.ptagProvisionalCount.expect(1.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.iexS1.valid.expect(true.B) - dut.io.iexS1.bits.o3.request.reservation.transaction.plan - .transactionId.expect(0.U) - dut.io.iexS1.bits.pRename.uops(0).destinations(0) - .currentPMapping.ptag.expect(96.U) - dut.io.iexS1.bits.dispatch.allocations(0).reservation - .reservationEpoch.expect(1.U) - - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.ptagProvisionalCount.expect(0.U) - dut.io.ptagPublishedCount.expect(1.U) - dut.io.mapQUsed(0).expect(1.U) - dut.io.robOccupiedGroups(0).expect(1.U) - dut.io.dispatchPublishedEntries(0)(0).expect(1.U) - dut.io.queryAtag.poke(1.U) - dut.io.speculativeMapping.ptag.expect(96.U) - dut.io.committedMapping.ptag.expect(1.U) - - val dispatchRelease = dut.io.dispatchRelease.bits - dispatchRelease.poke(0.U.asTypeOf(dispatchRelease)) - dispatchRelease.peId.poke(3.U) - dispatchRelease.stid.poke(0.U) - dispatchRelease.epoch.poke(5.U) - dispatchRelease.transactionId.poke(0.U) - dispatchRelease.member.group.valid.poke(true.B) - dispatchRelease.member.group.peId.poke(3.U) - dispatchRelease.member.group.stid.poke(0.U) - dispatchRelease.member.group.ridSlot.poke(0.U) - dispatchRelease.member.group.ridGeneration.poke(0.U) - dispatchRelease.member.bid.valid.poke(true.B) - dispatchRelease.member.bid.value.poke(0.U) - dispatchRelease.member.brobGeneration.poke(0.U) - dispatchRelease.member.memberIndex.poke(0.U) - dispatchRelease.member.residentGeneration.poke(1.U) - dispatchRelease.reservation.valid.poke(true.B) - dispatchRelease.reservation.uopClass.poke(OooUopClass.Alu) - dispatchRelease.reservation.bank.poke(0.U) - dispatchRelease.reservation.writePort.poke(0.U) - dispatchRelease.reservation.speculativeSlot.poke(0.U) - dispatchRelease.reservation.reservationEpoch.poke(1.U) - dut.io.dispatchRelease.valid.poke(true.B) - dut.io.dispatchRelease.ready.expect(true.B) - dut.clock.step() - dut.io.dispatchRelease.valid.poke(false.B) - dut.io.dispatchPublishedEntries(0)(0).expect(0.U) - - val completion = dut.io.completion.bits.key - completion.group.valid.poke(true.B) - completion.group.peId.poke(3.U) - completion.group.stid.poke(0.U) - completion.group.ridSlot.poke(0.U) - completion.group.ridGeneration.poke(0.U) - completion.bid.valid.poke(true.B) - completion.bid.value.poke(0.U) - completion.brobGeneration.poke(0.U) - completion.memberIndex.poke(0.U) - completion.residentGeneration.poke(1.U) - dut.io.completion.valid.poke(true.B) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - waitForPCommitBusy(dut) - dut.io.pCommitRejected.valid.expect(false.B) - dut.io.pCommitBusy.expect(true.B) - dut.io.commit.valid.expect(false.B) - dut.clock.step() // return the replaced reset mapping and advance CMAP - waitForCommit(dut) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.committedMapping.ptag.expect(96.U) - dut.io.ptagPublishedCount.expect(1.U) - } - } - - test("publishes T and U sequential rename on the same O3 terminal fire") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4, - tPhysRegs = 8, - uPhysRegs = 8, - tuMapQDepthPerStid = 8) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - pokeLocalRenameChain(dut, stid = 1, transactionId = 0) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - - dut.io.tuPublicationRejected.valid.expect(false.B) - dut.io.tuPrepared.valid.expect(true.B) - dut.io.prepared.valid.expect(true.B) - dut.io.preparedValid.expect(true.B) - dut.io.tuPrepared.uops(1).sources(0).valid.expect(true.B) - dut.io.tuPrepared.uops(1).sources(0).physicalTag.expect(0.U) - dut.io.tuPrepared.uops(0).destinations(0).physicalTag.expect(0.U) - dut.io.tuPrepared.uops(1).destinations(0).physicalTag.expect(0.U) - dut.io.tuPrepared.rows(0).member.memberIndex.expect(0.U) - dut.io.tuPrepared.rows(2).member.memberIndex.expect(1.U) - dut.io.tMapQUsed(1).expect(0.U) - dut.io.uMapQUsed(1).expect(0.U) - - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.tMapQUsed(1).expect(1.U) - dut.io.uMapQUsed(1).expect(1.U) - dut.io.tMapQUsed(0).expect(0.U) - dut.io.robOccupiedGroups(1).expect(1.U) - - completeMembers(dut, stid = 1, rid = 0, memberCount = 2) - waitForCommit(dut) - dut.io.tuCommitBusy.expect(true.B) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.tMapQUsed(1).expect(0.U) - dut.io.uMapQUsed(1).expect(0.U) - dut.io.tuRetireSourceUsed(1).expect(0.U) - dut.io.tRelationUsed(1).expect(0.U) - dut.io.uRelationUsed(1).expect(0.U) - dut.io.robOccupiedGroups(1).expect(0.U) - } - } - - test("consumes stale T/U-underflow plans without orphaning rename leases") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - pokeOneDestination(dut, tailEpoch = 1) - dut.io.reserve.bits.decoded.uops(0).sources(0) - .operandClass.poke(OperandClass.T) - dut.io.reserve.bits.decoded.uops(0).sources(0) - .relativeIndex.poke(0.U) - dut.io.tuReserveRejected.valid.expect(true.B) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(false.B) - dut.io.ptagProvisionalCount.expect(0.U) - dut.io.ptagPublishedCount.expect(0.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.tMapQUsed(0).expect(0.U) - dut.io.uMapQUsed(0).expect(0.U) - dut.io.robOccupiedGroups(0).expect(0.U) - - // Stale consumption changes no D3 transaction/tail or rename lease. - pokeOneDestination(dut, tailEpoch = 0, transactionId = 0) - dut.io.reserve.ready.expect(true.B) - } - } - - test("serializes WAW CMAP commit and returns the exact old PTag before ROB deallocation") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - pokeOneDestination(dut, uopCount = 2) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(true.B) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.expect(96.U) - dut.io.prepared.uops(1).destinations(0) - .currentPMapping.ptag.expect(97.U) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.ptagPublishedCount.expect(2.U) - dut.io.mapQUsed(0).expect(2.U) - - for (memberIndex <- 0 until 2) { - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - val key = dut.io.completion.bits.key - key.group.valid.poke(true.B) - key.group.peId.poke(3.U) - key.group.stid.poke(0.U) - key.group.ridSlot.poke(0.U) - key.group.ridGeneration.poke(0.U) - key.bid.valid.poke(true.B) - key.bid.value.poke(0.U) - key.brobGeneration.poke(0.U) - key.memberIndex.poke(memberIndex.U) - key.residentGeneration.poke(1.U) - dut.io.completion.valid.poke(true.B) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - } - - waitForPCommitBusy(dut) - dut.io.ptagRecycle.valid.expect(false.B) - acceptPtagRecycle(dut, expectedPtag = 1) - dut.io.queryAtag.poke(1.U) - dut.io.committedMapping.ptag.expect(96.U) - dut.io.mapQUsed(0).expect(1.U) - dut.io.ptagPublishedCount.expect(2.U) - dut.io.ptagRecycle.valid.expect(false.B) - acceptPtagRecycle(dut, expectedPtag = 96) - dut.io.committedMapping.ptag.expect(97.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.ptagPublishedCount.expect(1.U) - waitForCommit(dut) - dut.io.robOccupiedGroups(0).expect(1.U) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.ptagPublishedCount.expect(1.U) - } - } - - test("lets an older commit drain a full MapQ ahead of a younger provisional row") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 2, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - - pokeOneDestination(dut, uopCount = 2) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.mapQUsed(0).expect(2.U) - - pokeOneDestination(dut, tailEpoch = 1, uopCount = 2, - transactionId = 1, firstRid = 1, atag = 2, basePc = 512) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(false.B) // MapQ is full; row stays provisional. - - completeMembers(dut, stid = 0, rid = 0, memberCount = 2) - waitForPCommitBusy(dut) - dut.io.preparedValid.expect(false.B) - dut.clock.step(2) // width-one return of identity PTag 1, then PTag 96 - waitForCommit(dut) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.pCommitBusy.expect(false.B) - dut.io.mapQUsed(0).expect(0.U) - - dut.io.preparedValid.expect(true.B) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.mapQUsed(0).expect(2.U) - dut.io.robOccupiedGroups(0).expect(1.U) - } - } - - test("retains an exposed younger prepare before starting same-STID commit") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - - pokeOneDestination(dut) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - - pokeOneDestination(dut, tailEpoch = 1, transactionId = 1, - firstRid = 1, atag = 2, basePc = 512) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(true.B) - dut.io.prepared.transactionId.expect(1.U) - val retainedPtag = dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.peek().litValue - - completeMembers(dut, stid = 0, rid = 0, memberCount = 1) - dut.clock.step(3) - dut.io.pCommitBusy.expect(false.B) - dut.io.preparedValid.expect(true.B) - dut.io.prepared.transactionId.expect(1.U) - dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.expect(retainedPtag.U) - - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.mapQUsed(0).expect(2.U) - - dut.clock.step() // now the older retained ROB batch may lock - dut.io.pCommitBusy.expect(true.B) - dut.clock.step() // return reset PTag 1 and commit the first MapQ row - waitForCommit(dut) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.pCommitBusy.expect(false.B) - dut.io.mapQUsed(0).expect(1.U) - dut.io.robOccupiedGroups(0).expect(1.U) - } - } - - test("recovers P T and U atomically while unrelated STIDs keep publishing") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 8, - tuRetireSourceDepthPerStid = 16, - brobEntriesPerStid = 8, - pMapQDepthPerStid = 8, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1, - tPhysRegs = 8, - uPhysRegs = 8, - tuMapQDepthPerStid = 8) - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - - // Publish the exact survivor anchor on STID 1, transaction zero. - pokeOneDestination(dut, stid = 1, transactionId = 0, firstRid = 0, - atag = 1, basePc = 256) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(true.B) - val survivorPtag = dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.peek().litValue - val anchor = dut.io.tuPrepared.uops(0).member - val anchorBid = anchor.bid.value.peek().litValue - val anchorBrobGeneration = anchor.brobGeneration.peek().litValue - val anchorMemberIndex = anchor.memberIndex.peek().litValue - val anchorResidentGeneration = anchor.residentGeneration.peek().litValue - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - - // Publish a younger transaction whose suffix owns P, T, and U state. - pokeMixedRenameTransaction(dut, tailEpoch = 1, stid = 1, - transactionId = 1, firstRid = 1) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(true.B) - val killedPtag = dut.io.prepared.uops(0).destinations(0) - .currentPMapping.ptag.peek().litValue - assert(killedPtag != survivorPtag) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.mapQUsed(1).expect(2.U) - dut.io.tMapQUsed(1).expect(1.U) - dut.io.uMapQUsed(1).expect(1.U) - dut.io.tuRetireSourceUsed(1).expect(3.U) - dut.io.ptagPublishedCount.expect(2.U) - - pokeRecoveryRequest(dut, stid = 1, transactionId = 0, rid = 0, - bid = anchorBid, brobGeneration = anchorBrobGeneration, - memberIndex = anchorMemberIndex, - residentGeneration = anchorResidentGeneration, - killTrigger = false) - dut.io.recoveryRequest.valid.poke(true.B) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryBusy.expect(true.B) - dut.io.recoveryStid.expect(1.U) - - // The target STID is fenced from D3 as soon as scan authority is live. - pokeOneDestination(dut, tailEpoch = 2, stid = 1, - transactionId = 2, firstRid = 2, atag = 2, basePc = 768) - dut.io.reserve.ready.expect(false.B) - dut.clock.step() - - // STID 2 remains independent and can reserve and publish during recovery. - pokeOneDestination(dut, stid = 2, transactionId = 0, firstRid = 0, - atag = 2, basePc = 1024) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - dut.io.preparedValid.expect(true.B) - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - dut.io.mapQUsed(2).expect(1.U) - - var cycles = 0 - var sawCommonComplete = false - var sawTypedComplete = false - while (dut.io.recoveryBusy.peek().litToBoolean && cycles < 64) { - sawCommonComplete ||= dut.io.recoveryComplete.peek().litToBoolean - if (dut.io.recoveryCompleted.valid.peek().litToBoolean) { - sawTypedComplete = true - dut.io.recoveryCompleted.bits.rename.key.member.group.stid.expect(1.U) - dut.io.recoveryCompleted.bits.rename.key.transactionId.expect(0.U) - } - dut.clock.step() - cycles += 1 - } - assert(cycles < 64, "timed out waiting for atomic rename recovery") - assert(sawCommonComplete, - "coordinator never joined scanner, P, and T/U completion") - assert(sawTypedComplete, - "coordinator never published the exact completed recovery request") - - dut.io.mapQUsed(1).expect(1.U) - dut.io.tMapQUsed(1).expect(0.U) - dut.io.uMapQUsed(1).expect(0.U) - dut.io.tuRetireSourceUsed(1).expect(1.U) - dut.io.ptagPublishedCount.expect(2.U) - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(1.U) - dut.io.speculativeMapping.ptag.expect(survivorPtag.U) - dut.io.mapQUsed(0).expect(0.U) - dut.io.mapQUsed(2).expect(1.U) - dut.io.mapQUsed(3).expect(0.U) - dut.io.tMapQUsed(2).expect(0.U) - dut.io.uMapQUsed(2).expect(0.U) - - // A stale exact key is diagnosed by the scanner and mutates no owner. - pokeRecoveryRequest(dut, stid = 1, transactionId = 0, rid = 0, - bid = anchorBid, brobGeneration = anchorBrobGeneration, - memberIndex = anchorMemberIndex, - residentGeneration = anchorResidentGeneration + 1, - killTrigger = false) - dut.io.recoveryRequest.valid.poke(true.B) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - var rejectCycles = 0 - while (!dut.io.recoveryRejected.valid.peek().litToBoolean && - rejectCycles < 16) { - dut.clock.step() - rejectCycles += 1 - } - assert(rejectCycles < 16, "timed out waiting for stale-key diagnostic") - dut.io.pRecoveryRejected.valid.expect(false.B) - dut.io.tuRecoveryRejected.valid.expect(false.B) - dut.io.mapQUsed(1).expect(1.U) - dut.io.tuRetireSourceUsed(1).expect(1.U) - dut.io.ptagPublishedCount.expect(2.U) - - var abortCycles = 0 - var sawTypedAbort = false - while (dut.io.recoveryBusy.peek().litToBoolean && abortCycles < 32) { - if (dut.io.recoveryAborted.valid.peek().litToBoolean) { - sawTypedAbort = true - dut.io.recoveryAborted.bits.rename.key.member.group.stid.expect(1.U) - dut.io.recoveryAborted.bits.rename.key.member.residentGeneration - .expect((anchorResidentGeneration + 1).U) - } - dut.clock.step() - abortCycles += 1 - } - assert(abortCycles < 32, "timed out draining rejected global recovery") - assert(sawTypedAbort, - "coordinator never published the exact aborted recovery request") - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooO3RenameRandomizedSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooO3RenameRandomizedSpec.scala deleted file mode 100644 index 59ddc6ef..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooO3RenameRandomizedSpec.scala +++ /dev/null @@ -1,508 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -import scala.collection.mutable.ArrayBuffer -import scala.util.Random - -private object OooO3RenameRandomizedSpec { - final case class Shape(p: Boolean, t: Boolean, u: Boolean) - - final case class Mapping( - valid: Boolean, - ptag: BigInt, - generation: BigInt, - producerToken: BigInt, - producerIqEpoch: BigInt, - ready: Boolean, - stid: Int, - epoch: Int) - - final case class Member( - ridSlot: BigInt, - ridGeneration: BigInt, - bid: BigInt, - brobGeneration: BigInt, - memberIndex: BigInt, - residentGeneration: BigInt) - - final case class PDestination(atag: Int, mapping: Mapping) - - final case class Source( - transactionId: BigInt, - epoch: Int, - member: Member, - pDestinations: Vector[PDestination], - tDestinations: Int, - uDestinations: Int) - - final case class ThreadModel( - sources: ArrayBuffer[Source], - initialMappings: Vector[Mapping], - var instructionSerial: Int, - var nextTransactionId: BigInt, - var headSlot: Int, - var headGeneration: BigInt, - var tailSlot: Int, - var tailGeneration: BigInt, - var tailEpoch: BigInt, - var recoveries: Int) -} - -class OooO3RenameRandomizedSpec extends AnyFunSuite with ChiselSim { - import OooO3RenameRandomizedSpec._ - - private def identityMapping(p: OooParams, stid: Int, atag: Int): Mapping = - Mapping(valid = true, ptag = stid * p.pArchRegs + atag, - generation = 0, producerToken = 0, producerIqEpoch = 0, - ready = true, stid = stid, - epoch = 0) - - private def incrementWrapped(value: BigInt, width: Int): BigInt = - (value + 1) & ((BigInt(1) << width) - 1) - - private def advanceRobPointer( - p: OooParams, - slot: Int, - generation: BigInt, - count: Int): (Int, BigInt) = { - val absolute = slot + count - val nextSlot = absolute % p.robGroupsPerStid - val nextGeneration = generation + absolute / p.robGroupsPerStid - (nextSlot, nextGeneration & - ((BigInt(1) << p.ridGenerationWidth) - 1)) - } - - private def clear(dut: OooO3RenameCoordinator): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.iexS1.ready.poke(false.B) - dut.io.fastBoundary.ready.poke(true.B) - dut.io.fastWriteback.ready.poke(true.B) - dut.io.fastWakeup.ready.poke(true.B) - dut.io.fastTrace.ready.poke(true.B) - dut.io.completions.foreach { completion => - completion.valid.poke(false.B) - completion.bits.poke(0.U.asTypeOf(completion.bits)) - } - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.commit.ready.poke(false.B) - dut.io.storeCommit.ready.poke(true.B) - dut.io.ptagRecycle.ready.poke(true.B) - dut.io.dispatchRelease.valid.poke(false.B) - dut.io.dispatchRelease.bits.poke( - 0.U.asTypeOf(dut.io.dispatchRelease.bits)) - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.iexRecoveryPrepareReady.poke(true.B) - dut.io.iexRecoveryPrepared.poke( - 0.U.asTypeOf(dut.io.iexRecoveryPrepared)) - dut.io.iexRecoveryRejected.valid.poke(false.B) - dut.io.iexRecoveryRejected.bits.poke( - 0.U.asTypeOf(dut.io.iexRecoveryRejected.bits)) - dut.io.queryStid.poke(0.U) - dut.io.queryAtag.poke(0.U) - dut.io.pcReadTokens.foreach(_.poke( - 0.U.asTypeOf(dut.io.pcReadTokens.head))) - } - - private def pokeTransaction( - dut: OooO3RenameCoordinator, - stid: Int, - instructionSerial: Int, - transactionId: BigInt, - tailSlot: Int, - tailGeneration: BigInt, - tailEpoch: BigInt, - sourceAtag: Int, - destinationAtag: Int, - shape: Shape): Unit = { - val transaction = dut.io.reserve.bits - transaction.poke(0.U.asTypeOf(transaction)) - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.uopMask.poke(1.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.virtualTailEpoch.poke(tailEpoch.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(3.U) - transaction.plan.firstVirtualGroup.stid.poke(stid.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(tailSlot.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(tailGeneration.U) - transaction.plan.demand.pDestinations.poke((if (shape.p) 1 else 0).U) - transaction.plan.demand.mapQRows.poke((if (shape.p) 1 else 0).U) - transaction.plan.demand.tAllocations.poke((if (shape.t) 1 else 0).U) - transaction.plan.demand.uAllocations.poke((if (shape.u) 1 else 0).U) - - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(1.U) - transaction.groupMask.poke(1.U) - transaction.uopGroupIndex(0).poke(0.U) - transaction.uopMemberBase(0).poke(0.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(tailSlot.U) - group.key.ridGeneration.poke(tailGeneration.U) - group.logicalUopMask.poke(1.U) - group.physicalMemberCount.poke(1.U) - group.pMapQRows.poke((if (shape.p) 1 else 0).U) - group.architecturalParentCount.poke(1.U) - group.boundaryStart.poke(true.B) - group.boundaryStop.poke(true.B) - group.releasePcBase.poke(true.B) - - val uop = transaction.decoded.uops(0) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.plannedChildCount.poke(1.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke( - (1000 + stid * 100 + instructionSerial).U) - uop.identity.parents(0).key.epoch.poke(5.U) - uop.identity.parents(0).pc.poke( - (0x1000 + stid * 0x400 + instructionSerial * 8).U) - uop.sources(0).valid.poke(true.B) - uop.sources(0).operandClass.poke(OperandClass.P) - uop.sources(0).atag.poke(sourceAtag.U) - - var destinationIndex = 0 - if (shape.p) { - val destination = uop.destinations(destinationIndex) - destination.valid.poke(true.B) - destination.kind.poke(DestinationKind.Gpr) - destination.atag.poke(destinationAtag.U) - destinationIndex += 1 - } - if (shape.t) { - val destination = uop.destinations(destinationIndex) - destination.valid.poke(true.B) - destination.kind.poke(DestinationKind.T) - destination.relativeIndex.poke(0.U) - destinationIndex += 1 - } - if (shape.u) { - val destination = uop.destinations(destinationIndex) - destination.valid.poke(true.B) - destination.kind.poke(DestinationKind.U) - destination.relativeIndex.poke(0.U) - } - dut.io.reserve.valid.poke(true.B) - } - - private def captureMapping( - dut: OooO3RenameCoordinator, - destinationIndex: Int): Mapping = { - val mapping = dut.io.prepared.uops(0).destinations(destinationIndex) - .currentPMapping - Mapping( - valid = mapping.valid.peek().litToBoolean, - ptag = mapping.ptag.peek().litValue, - generation = mapping.ptagGeneration.peek().litValue, - producerToken = mapping.producerToken.peek().litValue, - producerIqEpoch = mapping.producerIqEpoch.peek().litValue, - ready = mapping.ready.peek().litToBoolean, - stid = mapping.stid.peek().litValue.toInt, - epoch = mapping.epoch.peek().litValue.toInt) - } - - private def captureMember(dut: OooO3RenameCoordinator): Member = { - val member = dut.io.tuPrepared.uops(0).member - Member( - ridSlot = member.group.ridSlot.peek().litValue, - ridGeneration = member.group.ridGeneration.peek().litValue, - bid = member.bid.value.peek().litValue, - brobGeneration = member.brobGeneration.peek().litValue, - memberIndex = member.memberIndex.peek().litValue, - residentGeneration = member.residentGeneration.peek().litValue) - } - - private def publish( - dut: OooO3RenameCoordinator, - models: Vector[ThreadModel], - stid: Int, - sourceAtag: Int, - destinationAtag: Int, - shape: Shape): Unit = { - val model = models(stid) - val transactionId = model.nextTransactionId - pokeTransaction(dut, stid, model.instructionSerial, transactionId, - model.tailSlot, model.tailGeneration, model.tailEpoch, sourceAtag, - destinationAtag, shape) - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - assert(dut.io.preparedValid.peek().litToBoolean, - s"STID $stid serial ${model.instructionSerial} shape $shape did not prepare; " + - s"P provisional=${dut.io.ptagProvisionalCount.peek().litValue} " + - s"T/U reserve reject=${dut.io.tuReserveRejected.valid.peek().litToBoolean} " + - s"T/U publish reject=${dut.io.tuPublicationRejected.valid.peek().litToBoolean}") - dut.io.tuPrepared.valid.expect(true.B) - - val pDestinations = if (shape.p) { - Vector(PDestination(destinationAtag, captureMapping(dut, 0))) - } else { - Vector.empty - } - val source = Source(transactionId = transactionId, epoch = 5, - member = captureMember(dut), pDestinations = pDestinations, - tDestinations = if (shape.t) 1 else 0, - uDestinations = if (shape.u) 1 else 0) - - dut.io.iexS1.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.iexS1.ready.poke(false.B) - model.sources += source - val (nextTailSlot, nextTailGeneration) = advanceRobPointer( - dut.p, model.tailSlot, model.tailGeneration, count = 1) - model.tailSlot = nextTailSlot - model.tailGeneration = nextTailGeneration - model.tailEpoch = incrementWrapped( - model.tailEpoch, dut.p.reservationEpochWidth) - model.nextTransactionId = incrementWrapped( - model.nextTransactionId, dut.p.transactionIdWidth) - model.instructionSerial += 1 - } - - private def pokeRecovery( - dut: OooO3RenameCoordinator, - stid: Int, - source: Source, - killTrigger: Boolean): Unit = { - val global = dut.io.recoveryRequest.bits - val request = global.rename - request.poke(0.U.asTypeOf(request)) - request.key.member.group.valid.poke(true.B) - request.key.member.group.peId.poke(3.U) - request.key.member.group.stid.poke(stid.U) - request.key.member.group.ridSlot.poke(source.member.ridSlot.U) - request.key.member.group.ridGeneration.poke( - source.member.ridGeneration.U) - request.key.member.bid.valid.poke(true.B) - request.key.member.bid.value.poke(source.member.bid.U) - request.key.member.brobGeneration.poke(source.member.brobGeneration.U) - request.key.member.memberIndex.poke(source.member.memberIndex.U) - request.key.member.residentGeneration.poke( - source.member.residentGeneration.U) - request.key.cause.poke(OooRecoveryCause.Branch) - request.key.transactionId.poke(source.transactionId.U) - request.key.epoch.poke(source.epoch.U) - request.killTrigger.poke(killTrigger.B) - global.triggerMemberCount.poke(1.U) - dut.io.iexRecoveryPrepared.valid.poke(true.B) - dut.io.iexRecoveryPrepared.stid.poke(stid.U) - dut.io.recoveryRequest.valid.poke(true.B) - } - - private def recover( - dut: OooO3RenameCoordinator, - model: ThreadModel, - stid: Int, - anchorIndex: Int, - killTrigger: Boolean): Unit = { - val anchor = model.sources(anchorIndex) - pokeRecovery(dut, stid, anchor, killTrigger) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryBusy.expect(true.B) - - var cycles = 0 - var sawComplete = false - var sawReject = false - while (dut.io.recoveryBusy.peek().litToBoolean && cycles < 96) { - sawComplete ||= dut.io.recoveryComplete.peek().litToBoolean - sawReject ||= dut.io.recoveryRejected.valid.peek().litToBoolean - sawReject ||= dut.io.pRecoveryRejected.valid.peek().litToBoolean - sawReject ||= dut.io.tuRecoveryRejected.valid.peek().litToBoolean - dut.clock.step() - cycles += 1 - } - assert(cycles < 96, s"STID $stid recovery timed out") - assert(sawComplete, s"STID $stid recovery did not join all owners") - assert(!sawReject, s"STID $stid exact recovery was rejected") - - val survivorCount = anchorIndex + (if (killTrigger) 0 else 1) - model.sources.remove(survivorCount, - model.sources.length - survivorCount) - val (nextTailSlot, nextTailGeneration) = advanceRobPointer( - dut.p, model.headSlot, model.headGeneration, survivorCount) - model.tailSlot = nextTailSlot - model.tailGeneration = nextTailGeneration - model.tailEpoch = incrementWrapped( - model.tailEpoch, dut.p.reservationEpochWidth) - model.recoveries += 1 - } - - private def expectedMappings(model: ThreadModel): Vector[Mapping] = { - val mappings = model.initialMappings.toArray - model.sources.foreach { source => - source.pDestinations.foreach { destination => - mappings(destination.atag) = destination.mapping - } - } - mappings.toVector - } - - private def assertMapping( - actual: PMapPayload, - expected: Mapping): Unit = { - actual.valid.expect(expected.valid.B) - actual.ptag.expect(expected.ptag.U) - actual.ptagGeneration.expect(expected.generation.U) - actual.producerToken.expect(expected.producerToken.U) - actual.producerIqEpoch.expect(expected.producerIqEpoch.U) - actual.ready.expect(expected.ready.B) - actual.stid.expect(expected.stid.U) - actual.epoch.expect(expected.epoch.U) - } - - private def assertModel( - dut: OooO3RenameCoordinator, - models: Vector[ThreadModel]): Unit = { - var expectedPublishedPtags = 0 - for (stid <- models.indices) { - val model = models(stid) - val pCount = model.sources.map(_.pDestinations.size).sum - val tCount = model.sources.map(_.tDestinations).sum - val uCount = model.sources.map(_.uDestinations).sum - expectedPublishedPtags += pCount - dut.io.mapQUsed(stid).expect(pCount.U) - dut.io.tMapQUsed(stid).expect(tCount.U) - dut.io.uMapQUsed(stid).expect(uCount.U) - dut.io.tuRetireSourceUsed(stid).expect(model.sources.size.U) - dut.io.robOccupiedGroups(stid).expect(model.sources.size.U) - dut.io.d3UsedGroups(stid).expect(model.sources.size.U) - dut.io.d3PublishedGroups(stid).expect(model.sources.size.U) - dut.io.d3TailSlot(stid).expect(model.tailSlot.U) - dut.io.d3TailGeneration(stid).expect(model.tailGeneration.U) - dut.io.d3TailEpoch(stid).expect(model.tailEpoch.U) - dut.io.d3NextTransactionId(stid).expect( - model.nextTransactionId.U) - dut.io.tRelationUsed(stid).expect(0.U) - dut.io.uRelationUsed(stid).expect(0.U) - - val speculative = expectedMappings(model) - for (atag <- 0 until dut.p.pArchRegs) { - dut.io.queryStid.poke(stid.U) - dut.io.queryAtag.poke(atag.U) - assertMapping(dut.io.speculativeMapping, speculative(atag)) - assertMapping(dut.io.committedMapping, - model.initialMappings(atag)) - } - } - dut.io.ptagProvisionalCount.expect(0.U) - dut.io.ptagPublishedCount.expect(expectedPublishedPtags.U) - } - - test("matches a four-STID sequential reference across randomized publish and recovery") { - val seed = 0x4f344dL - val random = new Random(seed) - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqWritePortsPerBank = 2, - robGroupsPerStid = 16, - tuRetireSourceDepthPerStid = 32, - brobEntriesPerStid = 16, - pMapQDepthPerStid = 32, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 2, - tPhysRegs = 16, - uPhysRegs = 16, - tuMapQDepthPerStid = 32) - val shapes = Vector( - Shape(p = true, t = false, u = false), - Shape(p = false, t = true, u = false), - Shape(p = false, t = false, u = true), - Shape(p = true, t = true, u = false), - Shape(p = true, t = false, u = true), - Shape(p = false, t = true, u = true), - Shape(p = false, t = false, u = false)) - - simulate(new OooO3RenameCoordinator(p)) { dut => - clear(dut) - dut.clock.step() - val models = Vector.tabulate(p.stidCount) { stid => - ThreadModel(ArrayBuffer.empty, - Vector.tabulate(p.pArchRegs)(atag => - identityMapping(p, stid, atag)), instructionSerial = 0, - nextTransactionId = 0, headSlot = 0, headGeneration = 0, - tailSlot = 0, tailGeneration = 0, tailEpoch = 0, - recoveries = 0) - } - - // Seed every namespace and every STID before randomized selection. - for (stid <- 0 until p.stidCount) { - publish(dut, models, stid, sourceAtag = stid, - destinationAtag = (stid + 1) % p.pArchRegs, - shape = shapes(stid)) - publish(dut, models, stid, sourceAtag = stid + 1, - destinationAtag = (stid + 5) % p.pArchRegs, - shape = shapes(3 + (stid % 3))) - } - publish(dut, models, stid = 0, sourceAtag = 7, - destinationAtag = 7, shape = shapes(6)) - recover(dut, models(0), stid = 0, - anchorIndex = models(0).sources.length - 1, killTrigger = false) - recover(dut, models(3), stid = 3, - anchorIndex = models(3).sources.length - 1, killTrigger = true) - assertModel(dut, models) - - for (_ <- 0 until 36) { - val stid = random.nextInt(p.stidCount) - val model = models(stid) - val livePtags = models.map(_.sources.map(_.pDestinations.size).sum).sum - val mayPublish = model.instructionSerial < 7 && livePtags < 20 - val choosePublish = model.sources.isEmpty || - (mayPublish && random.nextInt(100) < 62) - if (choosePublish) { - publish(dut, models, stid, - sourceAtag = random.nextInt(p.pArchRegs), - destinationAtag = random.nextInt(p.pArchRegs), - shape = shapes(random.nextInt(shapes.length))) - } else { - val anchorIndex = random.nextInt(model.sources.length) - recover(dut, model, stid, anchorIndex, - killTrigger = random.nextBoolean()) - } - assertModel(dut, models) - } - - // Close coverage deterministically if random choice missed one STID. - for (stid <- 0 until p.stidCount) { - val model = models(stid) - if (model.sources.isEmpty) { - publish(dut, models, stid, sourceAtag = stid, - destinationAtag = stid, shape = shapes(stid)) - } - if (model.recoveries == 0) { - recover(dut, model, stid, anchorIndex = model.sources.length - 1, - killTrigger = false) - } - assertModel(dut, models) - } - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooOpcodeRecipeTableSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooOpcodeRecipeTableSpec.scala index d84feefe..e85e0b77 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooOpcodeRecipeTableSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooOpcodeRecipeTableSpec.scala @@ -69,6 +69,15 @@ class OooOpcodeRecipeTableSpec extends AnyFunSuite with ChiselSim { assert(rule("OP_EBREAK").fastResolveClass == OooFastResolveClass.PreciseTrapRecord) assert(rule("OP_ACRC").dispatchClass == OooDispatchClass.Sys) assert(rule("OP_BSTART_TMA").recipeKind == OooOpcodeRecipeKind.EngineCmd) + val cmdRules = OooOpcodeRecipeTable.Rules.filter( + _.dispatchClass == OooDispatchClass.Cmd) + assert(cmdRules.nonEmpty) + assert(cmdRules.forall { entry => + entry.sideEffectOwner == OooSideEffectOwner.Commit && + entry.nonspeculative && + entry.dispatchCapabilities(OooDispatchClass.Cmd - 1) == + OooIexDomainCapability.mask(OooIexDomainCapability.EngineCommand) + }) assert(rule("OP_ADD").pcReadRequired == false) assert(rule("OP_B_Z").pcReadRequired) assert(rule("OP_JR").pcReadRequired) @@ -119,6 +128,8 @@ class OooOpcodeRecipeTableSpec extends AnyFunSuite with ChiselSim { dut.io.meta.opcode.expect(entry.opcode.U) dut.io.meta.disposition.expect(entry.disposition.U) dut.io.meta.recipeKind.expect(entry.recipeKind.U) + dut.io.meta.sideEffectOwner.expect(entry.sideEffectOwner.U) + dut.io.meta.nonspeculative.expect(entry.nonspeculative.B) dut.io.meta.pcReadRequired.expect(entry.pcReadRequired.B) for (classIndex <- 0 until p.iqClassCount) { dut.io.meta.dispatchCapabilities(classIndex) diff --git a/chisel/src/test/scala/linxcore/ooo/OooPRenameSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooPRenameSpec.scala deleted file mode 100644 index 2372f162..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooPRenameSpec.scala +++ /dev/null @@ -1,896 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -class OooPRenameSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooPRename): Unit = { - dut.io.prepare.valid.poke(false.B) - dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - dut.io.ptagLease.poke(0.U.asTypeOf(dut.io.ptagLease)) - dut.io.dispatchLease.poke(0.U.asTypeOf(dut.io.dispatchLease)) - dut.io.publishFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitPrepare.bits.poke(0.U.asTypeOf(dut.io.commitPrepare.bits)) - dut.io.commitFire.poke(false.B) - dut.io.ptagReturn.ready.poke(false.B) - dut.io.queryStid.poke(0.U) - dut.io.queryAtag.poke(0.U) - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryAuthorize.bits.poke( - 0.U.asTypeOf(dut.io.recoveryAuthorize.bits)) - dut.io.recoverySource.valid.poke(false.B) - dut.io.recoverySource.bits.poke( - 0.U.asTypeOf(dut.io.recoverySource.bits)) - dut.io.recoverySourcesDone.poke(false.B) - dut.io.recoveryFinish.poke(false.B) - } - - private def pokeTwoUopChain( - dut: OooPRename, - stid: Int, - transactionId: Int, - atag: Int, - firstPtag: Int, - secondPtag: Int, - splitAcrossGroups: Boolean = false, - firstRidSlot: Int = 4, - firstRidGeneration: Int = 2): Unit = { - dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - dut.io.ptagLease.poke(0.U.asTypeOf(dut.io.ptagLease)) - - val request = dut.io.prepare.bits.request - val reservation = request.reservation - val transaction = reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.uopMask.poke(3.U) - val groupCount = if (splitAcrossGroups) 2 else 1 - transaction.plan.groupCount.poke(groupCount.U) - transaction.plan.demand.pDestinations.poke(2.U) - transaction.plan.demand.mapQRows.poke(2.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(3.U) - transaction.groupMask.poke(((1 << groupCount) - 1).U) - for (groupIndex <- 0 until groupCount) { - val group = transaction.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(stid.U) - val absoluteSlot = firstRidSlot + groupIndex - group.key.ridSlot.poke((absoluteSlot % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke( - (firstRidGeneration + absoluteSlot / dut.p.robGroupsPerStid).U) - group.logicalUopMask.poke( - (if (splitAcrossGroups) 1 << groupIndex else 3).U) - group.physicalMemberCount.poke( - (if (splitAcrossGroups) 1 else 2).U) - group.pMapQRows.poke((if (splitAcrossGroups) 1 else 2).U) - request.bindings(groupIndex).valid.poke(true.B) - request.bindings(groupIndex).brob.valid.poke(true.B) - request.bindings(groupIndex).brob.bid.valid.poke(true.B) - request.bindings(groupIndex).brob.bid.value.poke(7.U) - request.bindings(groupIndex).brob.generation.poke(3.U) - request.bindings(groupIndex).pcBase.valid.poke(true.B) - request.bindings(groupIndex).residentGeneration.poke(9.U) - } - - for (uopIndex <- 0 until 2) { - val uop = transaction.decoded.uops(uopIndex) - uop.valid.poke(true.B) - uop.plannedChildCount.poke(1.U) - uop.sources(0).valid.poke(true.B) - uop.sources(0).operandClass.poke(OperandClass.P) - uop.sources(0).atag.poke(atag.U) - uop.destinations(0).valid.poke(true.B) - uop.destinations(0).kind.poke(DestinationKind.Gpr) - uop.destinations(0).atag.poke(atag.U) - transaction.uopGroupIndex(uopIndex).poke( - (if (splitAcrossGroups) uopIndex else 0).U) - transaction.uopMemberBase(uopIndex).poke( - (if (splitAcrossGroups) 0 else uopIndex).U) - } - - dut.io.ptagLease.valid.poke(true.B) - dut.io.ptagLease.peId.poke(3.U) - dut.io.ptagLease.stid.poke(stid.U) - dut.io.ptagLease.epoch.poke(5.U) - dut.io.ptagLease.transactionId.poke(transactionId.U) - dut.io.ptagLease.allocationMask.poke(5.U) // flat rows 0 and 2 - Seq(firstPtag, secondPtag).zipWithIndex.foreach { case (ptag, uopIndex) => - val flatIndex = uopIndex * dut.p.maxDestinationOperands - val allocation = dut.io.ptagLease.allocations(flatIndex) - allocation.valid.poke(true.B) - allocation.uopIndex.poke(uopIndex.U) - allocation.destinationIndex.poke(0.U) - allocation.atag.poke(atag.U) - allocation.token.valid.poke(true.B) - allocation.token.ptag.poke(ptag.U) - allocation.token.bank.poke((ptag % dut.p.pTagBanks).U) - allocation.token.generation.poke(1.U) - } - dut.io.prepare.valid.poke(true.B) - } - - private def publish(dut: OooPRename): Unit = { - dut.io.prepareReady.expect(true.B) - dut.io.publishFire.poke(true.B) - dut.clock.step() - dut.io.publishFire.poke(false.B) - dut.io.prepare.valid.poke(false.B) - } - - private def captureCommitSlice(dut: OooPRename): Unit = { - dut.clock.step() // retain the ROB batch and enter the MapQ read stage - dut.io.commitBusy.expect(true.B) - dut.io.ptagReturn.valid.expect(false.B) - dut.clock.step() // register the selected physical-subbank rows - dut.io.ptagReturn.valid.expect(true.B) - } - - private def captureNextCommitSlice(dut: OooPRename): Unit = { - dut.io.ptagReturn.valid.expect(false.B) - dut.clock.step() - dut.io.ptagReturn.valid.expect(true.B) - } - - private def pokeOneUopMapping( - dut: OooPRename, - stid: Int, - transactionId: Int, - atag: Int, - ptag: Int): Unit = { - pokeTwoUopChain(dut, stid, transactionId, atag, ptag, ptag + 1) - val transaction = dut.io.prepare.bits.request.reservation.transaction - transaction.plan.uopMask.poke(1.U) - transaction.plan.demand.pDestinations.poke(1.U) - transaction.plan.demand.mapQRows.poke(1.U) - transaction.decoded.uopMask.poke(1.U) - transaction.groups(0).logicalUopMask.poke(1.U) - transaction.groups(0).physicalMemberCount.poke(1.U) - transaction.groups(0).pMapQRows.poke(1.U) - transaction.decoded.uops(1).valid.poke(false.B) - transaction.decoded.uops(1).plannedChildCount.poke(0.U) - transaction.decoded.uops(1).sources(0).valid.poke(false.B) - transaction.decoded.uops(1).destinations(0).valid.poke(false.B) - dut.io.ptagLease.allocationMask.poke(1.U) - dut.io.ptagLease.allocations(2).poke( - 0.U.asTypeOf(dut.io.ptagLease.allocations(2))) - } - - private def pokeOneGroupCommit( - dut: OooPRename, - stid: Int, - transactionId: Int, - pRows: Int, - firstRidSlot: Int = 4, - firstRidGeneration: Int = 2, - logicalMask: Int = 3, - physicalMemberCount: Int = 2): Unit = { - dut.io.commitPrepare.bits.poke(0.U.asTypeOf(dut.io.commitPrepare.bits)) - val batch = dut.io.commitPrepare.bits - batch.release.firstGroup.valid.poke(true.B) - batch.release.firstGroup.peId.poke(3.U) - batch.release.firstGroup.stid.poke(stid.U) - batch.release.firstGroup.ridSlot.poke(firstRidSlot.U) - batch.release.firstGroup.ridGeneration.poke(firstRidGeneration.U) - batch.release.groupCount.poke(1.U) - val group = batch.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(firstRidSlot.U) - group.key.ridGeneration.poke(firstRidGeneration.U) - group.transactionId.poke(transactionId.U) - group.brob.valid.poke(true.B) - group.brob.bid.valid.poke(true.B) - group.brob.bid.value.poke(7.U) - group.brob.generation.poke(3.U) - group.pcBase.valid.poke(true.B) - group.residentGeneration.poke(9.U) - group.logicalUopMask.poke(logicalMask.U) - group.physicalMemberCount.poke(physicalMemberCount.U) - group.completedMembers.poke(((1 << physicalMemberCount) - 1).U) - group.pMapQRows.poke(pRows.U) - dut.io.commitPrepare.valid.poke(true.B) - } - - private def pokeTwoGroupCommit( - dut: OooPRename, - stid: Int, - transactionId: Int, - firstRidSlot: Int = 4, - firstRidGeneration: Int = 2): Unit = { - pokeOneGroupCommit(dut, stid, transactionId, pRows = 1, - firstRidSlot = firstRidSlot, firstRidGeneration = firstRidGeneration) - val batch = dut.io.commitPrepare.bits - batch.release.groupCount.poke(2.U) - val second = batch.groups(1) - second.valid.poke(true.B) - second.key.valid.poke(true.B) - second.key.peId.poke(3.U) - second.key.stid.poke(stid.U) - val secondAbsoluteSlot = firstRidSlot + 1 - second.key.ridSlot.poke( - (secondAbsoluteSlot % dut.p.robGroupsPerStid).U) - second.key.ridGeneration.poke( - (firstRidGeneration + secondAbsoluteSlot / dut.p.robGroupsPerStid).U) - second.transactionId.poke(transactionId.U) - second.brob.valid.poke(true.B) - second.brob.bid.valid.poke(true.B) - second.brob.bid.value.poke(7.U) - second.brob.generation.poke(3.U) - second.pcBase.valid.poke(true.B) - second.residentGeneration.poke(9.U) - second.logicalUopMask.poke(2.U) - second.physicalMemberCount.poke(1.U) - second.completedMembers.poke(1.U) - second.pMapQRows.poke(1.U) - val first = batch.groups(0) - first.logicalUopMask.poke(1.U) - first.physicalMemberCount.poke(1.U) - first.completedMembers.poke(1.U) - } - - private def pokeRecoveryRequest( - request: OooRenameRecoveryRequest, - dut: OooPRename, - stid: Int, - transactionId: Int, - uopIndex: Int, - killTrigger: Boolean, - epoch: Int = 5): Unit = { - request.poke(0.U.asTypeOf(request)) - request.key.member.group.valid.poke(true.B) - request.key.member.group.peId.poke(3.U) - request.key.member.group.stid.poke(stid.U) - request.key.member.group.ridSlot.poke(4.U) - request.key.member.group.ridGeneration.poke(2.U) - request.key.member.bid.valid.poke(true.B) - request.key.member.bid.value.poke(7.U) - request.key.member.brobGeneration.poke(3.U) - request.key.member.memberIndex.poke(uopIndex.U) - request.key.member.residentGeneration.poke(9.U) - request.key.cause.poke(OooRecoveryCause.Branch) - request.key.transactionId.poke(transactionId.U) - request.key.epoch.poke(epoch.U) - request.killTrigger.poke(killTrigger.B) - } - - private def startRecovery( - dut: OooPRename, - stid: Int, - transactionId: Int, - uopIndex: Int, - killTrigger: Boolean): Unit = { - pokeRecoveryRequest(dut.io.recoveryAuthorize.bits, dut, stid, - transactionId, uopIndex, killTrigger) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.recoveryAuthorize.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryBusy.expect(true.B) - } - - private def sendKilledSource( - dut: OooPRename, - triggerStid: Int, - triggerTransactionId: Int, - triggerUopIndex: Int, - killedTransactionId: Int, - killedUopIndex: Int, - last: Boolean): Unit = { - val transfer = dut.io.recoverySource.bits - transfer.poke(0.U.asTypeOf(transfer)) - pokeRecoveryRequest(transfer.request, dut, triggerStid, - triggerTransactionId, triggerUopIndex, killTrigger = false) - val source = transfer.source - source.valid.poke(true.B) - source.transactionId.poke(killedTransactionId.U) - source.epoch.poke(5.U) - source.uopIndex.poke(killedUopIndex.U) - source.member.group.valid.poke(true.B) - source.member.group.peId.poke(3.U) - source.member.group.stid.poke(triggerStid.U) - source.member.group.ridSlot.poke(4.U) - source.member.group.ridGeneration.poke(2.U) - source.member.bid.valid.poke(true.B) - source.member.bid.value.poke(7.U) - source.member.brobGeneration.poke(3.U) - source.member.memberIndex.poke(killedUopIndex.U) - source.member.residentGeneration.poke(9.U) - source.pDestinationCount.poke(1.U) - transfer.last.poke(last.B) - dut.io.recoverySource.valid.poke(true.B) - dut.io.recoverySource.ready.expect(true.B) - dut.clock.step() - dut.io.recoverySource.valid.poke(false.B) - } - - private def returnKilledTag( - dut: OooPRename, - expectedPtag: Int): Unit = { - dut.io.ptagReturn.valid.expect(false.B) - dut.clock.step() // register the killed tail row before returning its PTag - dut.io.ptagReturn.valid.expect(true.B) - dut.io.ptagReturn.bits.count.expect(1.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(expectedPtag.U) - dut.io.ptagReturn.bits.tokens(0).generation.expect(1.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - } - - private def finishRecovery(dut: OooPRename): Unit = { - var cycles = 0 - while (!dut.io.recoveryComplete.peek().litToBoolean && cycles < 64) { - dut.clock.step() - cycles += 1 - } - assert(cycles < 64, "timed out waiting for P recovery replay") - dut.io.recoveryFinish.poke(true.B) - dut.clock.step() - dut.io.recoveryFinish.poke(false.B) - dut.io.recoveryBusy.expect(false.B) - } - - test("forwards same-transaction P RAW and WAW while publishing exact MapQ rows") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4) - simulate(new OooPRename(p)) { dut => - clear(dut) - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(3.U) - dut.io.speculativeMapping.valid.expect(true.B) - dut.io.speculativeMapping.ptag.expect(27.U) - dut.io.committedMapping.ptag.expect(27.U) - - pokeTwoUopChain(dut, stid = 1, transactionId = 10, atag = 3, - firstPtag = 96, secondPtag = 97) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.uops(0).sources(0).pMapping.ptag.expect(27.U) - dut.io.prepared.uops(1).sources(0).pMapping.ptag.expect(96.U) - dut.io.prepared.uops(0).destinations(0) - .previousPMapping.ptag.expect(27.U) - dut.io.prepared.uops(1).destinations(0) - .previousPMapping.ptag.expect(96.U) - dut.io.prepared.uops(1).destinations(0) - .currentPMapping.ptag.expect(97.U) - dut.io.prepared.uops(1).destinations(0) - .currentPMapping.producerBindingValid.expect(false.B) - dut.io.prepared.mapQRowMask.expect(5.U) - dut.io.prepared.mapQRows(0).mapQIndex.expect(0.U) - dut.io.prepared.mapQRows(2).mapQIndex.expect(1.U) - dut.io.prepared.mapQRows(2).member.memberIndex.expect(1.U) - dut.clock.step(2) - dut.io.mapQUsed(1).expect(0.U) - dut.io.speculativeMapping.ptag.expect(27.U) - - publish(dut) - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(3.U) - dut.io.mapQUsed(1).expect(2.U) - dut.io.speculativeMapping.ptag.expect(97.U) - dut.io.committedMapping.ptag.expect(27.U) - dut.io.mapQUsed(0).expect(0.U) - - pokeOneGroupCommit(dut, stid = 1, transactionId = 10, pRows = 2) - dut.io.commitReady.expect(false.B) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(2.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(27.U) - dut.io.ptagReturn.bits.tokens(0).generation.expect(0.U) - dut.io.ptagReturn.bits.tokens(1).ptag.expect(96.U) - dut.io.ptagReturn.bits.tokens(1).generation.expect(1.U) - dut.clock.step(2) - dut.io.mapQUsed(1).expect(2.U) - dut.io.committedMapping.ptag.expect(27.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitPrepared.mapQRowCount.expect(2.U) - dut.io.mapQUsed(1).expect(0.U) - dut.io.committedMapping.ptag.expect(97.U) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitBusy.expect(false.B) - } - } - - test("rejects a malformed lease without mutating speculative state") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 2, transactionId = 12, atag = 4, - firstPtag = 96, secondPtag = 97) - dut.io.ptagLease.allocations(2).atag.poke(5.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.mapQUsed(2).expect(0.U) - dut.io.queryStid.poke(2.U) - dut.io.queryAtag.poke(4.U) - dut.io.speculativeMapping.ptag.expect(52.U) - - pokeTwoUopChain(dut, stid = 2, transactionId = 12, atag = 4, - firstPtag = 96, secondPtag = 97) - dut.io.prepare.bits.request.reservation.transaction.decoded - .uops(1).plannedChildCount.poke(2.U) - dut.io.prepareReady.expect(false.B) - dut.clock.step() - dut.io.mapQUsed(2).expect(0.U) - - pokeTwoUopChain(dut, stid = 2, transactionId = 12, atag = 4, - firstPtag = 96, secondPtag = 97) - dut.io.prepare.bits.request.reservation.transaction - .uopMemberBase(1).poke(0.U) - dut.io.prepareReady.expect(false.B) - dut.clock.step() - dut.io.mapQUsed(2).expect(0.U) - - pokeTwoUopChain(dut, stid = 2, transactionId = 12, atag = 4, - firstPtag = 96, secondPtag = 97) - val transaction = dut.io.prepare.bits.request.reservation.transaction - for (uopIndex <- 0 until 2) { - transaction.decoded.uops(uopIndex).recipe.dispatchWrites.poke(1.U) - transaction.decoded.uops(uopIndex).recipe.dispatchDemand(0).poke(1.U) - } - transaction.plan.demand.dispatchWritesByClass(0).poke(2.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.clock.step() - dut.io.mapQUsed(2).expect(0.U) - } - } - - test("registers MapQ reads before pointer updates at return width one") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 0, atag = 1, - firstPtag = 96, secondPtag = 97) - publish(dut) - dut.io.queryAtag.poke(1.U) - pokeOneGroupCommit(dut, stid = 0, transactionId = 0, pRows = 2) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(1.U) - dut.io.ptagReturn.bits.tokens(0).generation.expect(0.U) - dut.clock.step(2) - dut.io.mapQUsed(0).expect(2.U) - dut.io.committedMapping.ptag.expect(1.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(1.U) - - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() // return reset mapping and commit first row - dut.io.ptagReturn.ready.poke(false.B) - dut.io.mapQUsed(0).expect(1.U) - dut.io.committedMapping.ptag.expect(96.U) - captureNextCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(1.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(96.U) - dut.io.ptagReturn.bits.tokens(0).generation.expect(1.U) - dut.clock.step(2) - dut.io.mapQUsed(0).expect(1.U) - dut.io.committedMapping.ptag.expect(96.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(96.U) - - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.mapQUsed(0).expect(0.U) - dut.io.committedMapping.ptag.expect(97.U) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitBusy.expect(false.B) - } - } - - test("rejects underreported or stale commit identity with zero mutation") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 1, transactionId = 10, atag = 3, - firstPtag = 96, secondPtag = 97) - publish(dut) - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(3.U) - - pokeOneGroupCommit(dut, stid = 1, transactionId = 10, pRows = 1) - dut.io.commitRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.commitBusy.expect(false.B) - dut.io.mapQUsed(1).expect(2.U) - dut.io.committedMapping.ptag.expect(27.U) - - pokeOneGroupCommit(dut, stid = 1, transactionId = 11, pRows = 2) - dut.io.commitRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.commitBusy.expect(false.B) - dut.io.mapQUsed(1).expect(2.U) - dut.io.committedMapping.ptag.expect(27.U) - dut.io.ptagReturn.valid.expect(false.B) - } - } - - test("validates a wrapped two-group commit before draining either group") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 4, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 2) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 2, transactionId = 12, atag = 4, - firstPtag = 96, secondPtag = 97, splitAcrossGroups = true, - firstRidSlot = 3, firstRidGeneration = 2) - dut.io.prepared.mapQRows(0).member.group.ridSlot.expect(3.U) - dut.io.prepared.mapQRows(2).member.group.ridSlot.expect(0.U) - dut.io.prepared.mapQRows(2).member.group.ridGeneration.expect(3.U) - publish(dut) - dut.io.queryStid.poke(2.U) - dut.io.queryAtag.poke(4.U) - - pokeTwoGroupCommit(dut, stid = 2, transactionId = 12, - firstRidSlot = 3, firstRidGeneration = 2) - dut.io.commitPrepare.bits.groups(1).residentGeneration.poke(10.U) - dut.io.commitRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.commitBusy.expect(false.B) - dut.io.mapQUsed(2).expect(2.U) - dut.io.committedMapping.ptag.expect(52.U) - - pokeTwoGroupCommit(dut, stid = 2, transactionId = 12, - firstRidSlot = 3, firstRidGeneration = 2) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(2.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.mapQUsed(2).expect(0.U) - dut.io.committedMapping.ptag.expect(97.U) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitBusy.expect(false.B) - } - } - - test("applies per-STID MapQ capacity atomically") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 4) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 20, atag = 1, - firstPtag = 96, secondPtag = 97) - publish(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 22, atag = 2, - firstPtag = 98, secondPtag = 99) - dut.io.prepared.mapQRows(0).mapQIndex.expect(2.U) - dut.io.prepared.mapQRows(2).mapQIndex.expect(3.U) - publish(dut) - dut.io.mapQUsed(0).expect(4.U) - - pokeTwoUopChain(dut, stid = 0, transactionId = 24, atag = 3, - firstPtag = 100, secondPtag = 101) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.bits.freeRows.expect(0.U) - dut.clock.step() - dut.io.mapQUsed(0).expect(4.U) - dut.io.queryAtag.poke(3.U) - dut.io.speculativeMapping.ptag.expect(3.U) - } - } - - test("preserves exact commit and recovery across a subbanked MapQ wrap") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pMapQSubbankCount = 2, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 2) - simulate(new OooPRename(p)) { dut => - clear(dut) - - // Advance the logical head/tail by one row, then by two rows, so the - // next two-row publication occupies logical indices 3 and 0. - pokeOneUopMapping(dut, stid = 0, transactionId = 20, atag = 1, - ptag = 96) - dut.io.prepared.mapQRows(0).mapQIndex.expect(0.U) - publish(dut) - pokeOneGroupCommit(dut, stid = 0, transactionId = 20, pRows = 1, - logicalMask = 1, physicalMemberCount = 1) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(1.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - - pokeTwoUopChain(dut, stid = 0, transactionId = 22, atag = 2, - firstPtag = 97, secondPtag = 98) - dut.io.prepared.mapQRows(0).mapQIndex.expect(1.U) - dut.io.prepared.mapQRows(2).mapQIndex.expect(2.U) - publish(dut) - pokeOneGroupCommit(dut, stid = 0, transactionId = 22, pRows = 2) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(2.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - - pokeTwoUopChain(dut, stid = 0, transactionId = 24, atag = 3, - firstPtag = 99, secondPtag = 100) - dut.io.prepared.mapQRows(0).mapQIndex.expect(3.U) - dut.io.prepared.mapQRows(2).mapQIndex.expect(0.U) - publish(dut) - dut.io.mapQUsed(0).expect(2.U) - - // Kill the youngest wrapped row. Recovery must drain index 0 and replay - // the surviving index-3 prefix without changing logical queue order. - startRecovery(dut, stid = 0, transactionId = 24, uopIndex = 0, - killTrigger = false) - sendKilledSource(dut, triggerStid = 0, triggerTransactionId = 24, - triggerUopIndex = 0, killedTransactionId = 24, - killedUopIndex = 1, last = true) - returnKilledTag(dut, expectedPtag = 100) - dut.io.recoverySourcesDone.poke(true.B) - dut.clock.step() - dut.io.recoverySourcesDone.poke(false.B) - finishRecovery(dut) - dut.io.mapQUsed(0).expect(1.U) - dut.io.queryAtag.poke(3.U) - dut.io.speculativeMapping.ptag.expect(99.U) - - pokeOneGroupCommit(dut, stid = 0, transactionId = 24, pRows = 1, - logicalMask = 1, physicalMemberCount = 1) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(1.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(3.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.mapQUsed(0).expect(0.U) - dut.io.committedMapping.ptag.expect(99.U) - } - } - - test("rejects an out-of-range six-wide uop group index without mutation") { - val p = OooParams( - instructionDecodeWidth = 6, - decodedUopWidth = 6, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 6, - pTagReturnWidth = 4) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 0, atag = 1, - firstPtag = 96, secondPtag = 97) - dut.io.prepare.bits.request.reservation.transaction - .uopGroupIndex(1).poke(7.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.clock.step() - dut.io.mapQUsed(0).expect(0.U) - dut.io.queryAtag.poke(1.U) - dut.io.speculativeMapping.ptag.expect(1.U) - } - } - - test("returns killed current PTags and rebuilds SMAP from surviving MapQ rows") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 8, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 2) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 1, transactionId = 10, atag = 3, - firstPtag = 96, secondPtag = 97) - publish(dut) - pokeTwoUopChain(dut, stid = 1, transactionId = 11, atag = 3, - firstPtag = 98, secondPtag = 99) - publish(dut) - dut.io.mapQUsed(1).expect(4.U) - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(3.U) - dut.io.speculativeMapping.ptag.expect(99.U) - dut.io.committedMapping.ptag.expect(27.U) - - startRecovery(dut, stid = 1, transactionId = 10, uopIndex = 1, - killTrigger = false) - - // The affected STID is frozen, while an unrelated STID may still rename. - pokeTwoUopChain(dut, stid = 1, transactionId = 12, atag = 4, - firstPtag = 100, secondPtag = 101) - dut.io.prepareReady.expect(false.B) - pokeTwoUopChain(dut, stid = 2, transactionId = 13, atag = 4, - firstPtag = 100, secondPtag = 101) - dut.io.prepareReady.expect(true.B) - publish(dut) - dut.io.mapQUsed(2).expect(2.U) - - // Scanner order is youngest logical uop first. Current, not previous, - // mappings are returned because these rows never became architectural. - sendKilledSource(dut, triggerStid = 1, triggerTransactionId = 10, - triggerUopIndex = 1, killedTransactionId = 11, - killedUopIndex = 1, last = false) - returnKilledTag(dut, expectedPtag = 99) - sendKilledSource(dut, triggerStid = 1, triggerTransactionId = 10, - triggerUopIndex = 1, killedTransactionId = 11, - killedUopIndex = 0, last = true) - returnKilledTag(dut, expectedPtag = 98) - dut.io.mapQUsed(1).expect(2.U) - - dut.io.recoverySourcesDone.poke(true.B) - dut.clock.step() - dut.io.recoverySourcesDone.poke(false.B) - finishRecovery(dut) - - dut.io.queryStid.poke(1.U) - dut.io.queryAtag.poke(3.U) - dut.io.speculativeMapping.ptag.expect(97.U) - dut.io.committedMapping.ptag.expect(27.U) - dut.io.mapQUsed(1).expect(2.U) - - // The surviving prefix remains an exact, committable MapQ chain. - pokeOneGroupCommit(dut, stid = 1, transactionId = 10, pRows = 2) - captureCommitSlice(dut) - dut.io.ptagReturn.bits.count.expect(2.U) - dut.io.ptagReturn.bits.tokens(0).ptag.expect(27.U) - dut.io.ptagReturn.bits.tokens(1).ptag.expect(96.U) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.committedMapping.ptag.expect(97.U) - } - } - - test("replays a transaction-zero survivor without fabricating killed rows") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 1) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 0, atag = 1, - firstPtag = 96, secondPtag = 97) - publish(dut) - startRecovery(dut, stid = 0, transactionId = 0, uopIndex = 1, - killTrigger = false) - dut.io.ptagReturn.valid.expect(false.B) - dut.io.recoverySourcesDone.poke(true.B) - dut.clock.step() - dut.io.recoverySourcesDone.poke(false.B) - finishRecovery(dut) - dut.io.queryStid.poke(0.U) - dut.io.queryAtag.poke(1.U) - dut.io.speculativeMapping.ptag.expect(97.U) - dut.io.committedMapping.ptag.expect(1.U) - dut.io.mapQUsed(0).expect(2.U) - } - } - - test("rejects malformed authority and gives an exact commit capture priority") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - pMapQDepthPerStid = 4, - pTagStagingDepthPerBank = 2, - pTagReturnWidth = 2) - simulate(new OooPRename(p)) { dut => - clear(dut) - pokeTwoUopChain(dut, stid = 0, transactionId = 20, atag = 1, - firstPtag = 96, secondPtag = 97) - publish(dut) - - dut.io.recoveryAuthorize.bits.poke( - 0.U.asTypeOf(dut.io.recoveryAuthorize.bits)) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.recoveryAuthorize.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryRejected.bits.mapQCount.expect(2.U) - dut.io.recoveryBusy.expect(false.B) - dut.io.mapQUsed(0).expect(2.U) - - pokeOneGroupCommit(dut, stid = 0, transactionId = 20, pRows = 2) - pokeRecoveryRequest(dut.io.recoveryAuthorize.bits, dut, stid = 0, - transactionId = 20, uopIndex = 1, killTrigger = true) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.commitStartReady.expect(true.B) - dut.io.recoveryAuthorize.ready.expect(false.B) - dut.clock.step() - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.commitBusy.expect(true.B) - dut.io.ptagReturn.valid.expect(false.B) - dut.clock.step() - dut.io.ptagReturn.valid.expect(true.B) - dut.io.ptagReturn.ready.poke(true.B) - dut.clock.step() - dut.io.ptagReturn.ready.poke(false.B) - dut.io.commitReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitBusy.expect(false.B) - dut.io.recoveryBusy.expect(false.B) - } - } - - test("elaborates P rename at widths 2 4 6 and subbanks 1 2 4") { - Seq((2, 1), (4, 2), (6, 4)).foreach { case (width, subbanks) => - val p = OooParams( - instructionDecodeWidth = width, - pMapQDepthPerStid = 4, - pMapQSubbankCount = subbanks) - circt.stage.ChiselStage.emitSystemVerilog(new OooPRename(p)) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooParamIdentityDomainSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooParamIdentityDomainSpec.scala new file mode 100644 index 00000000..cf4f1623 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OooParamIdentityDomainSpec.scala @@ -0,0 +1,23 @@ +package linxcore.ooo + +import org.scalatest.funsuite.AnyFunSuite + +class OooParamIdentityDomainSpec extends AnyFunSuite { + test("ROB member and recipe uop identities retain unequal namespaces") { + val p = OooParams( + robIdentityMembersPerGroup = 4, + maxOrdinaryUopsPerGroup = 4, + maxRecipeUops = 32, + uopIdentityEntriesPerInstruction = 32) + val member = new RobMemberKey(p) + val uop = new CanonicalUopKey(p) + + assert(p.robMemberIndexWidth == 2) + assert(p.robMemberCountWidth == 3) + assert(p.recipeUopIndexWidth == 5) + assert(p.recipeUopCountWidth == 6) + assert(member.memberIndex.getWidth == 2) + assert(uop.uopOrdinal.getWidth == 5) + assert(uop.uopCount.getWidth == 6) + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OooParamsSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooParamsSpec.scala index 31c5f071..171d2216 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooParamsSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooParamsSpec.scala @@ -3,6 +3,24 @@ package linxcore.ooo import org.scalatest.funsuite.AnyFunSuite class OooParamsSpec extends AnyFunSuite { + test("central adapters preserve private identity widths exactly") { + val base = linxcore.params.ParamProfiles.W4 + val mainline = base.copy( + ooo = base.ooo.copy( + gprTagGenerationWidth = 13, + localSeqGenerationWidth = 11), + memoryTransactionIdWidth = 41, + memoryTransactionGenerationWidth = 11) + val adapted = OooParams.fromCoreParams(mainline) + + assert(adapted.pTagGenerationWidth == 13) + assert(adapted.localSeqGenerationWidth == 11) + assert(adapted.memoryTransactionIdWidth == 41) + assert(adapted.memoryTransactionGenerationWidth == 11) + assert(adapted.toMainline.gprTagGenerationWidth == 13) + assert(adapted.toMainline.localSeqGenerationWidth == 11) + } + test("defaults keep fetch-independent OOO widths and native identity domains") { val p = OooParams() @@ -71,13 +89,14 @@ class OooParamsSpec extends AnyFunSuite { assert(p.iexBypassPorts == 12) assert(p.iexLoadCancelPorts == 4) assert(p.iexTerminalWidth == 2) - assert(p.iexLoadTrackEntries == 16) assert(p.loadGenerationWidth == 8) + assert(p.memoryTransactionIdWidth == 64) + assert(p.memoryTransactionGenerationWidth == 16) assert(p.executeSlotGenerationWidth == 8) } - test("instruction decode widths 2 4 and 6 are independent elaboration points") { - Seq(2, 4, 6).foreach { width => + test("instruction decode widths 2 4 6 and 8 are independent elaboration points") { + Seq(2, 4, 6, 8).foreach { width => val p = OooParams(instructionDecodeWidth = width) assert(p.instructionDecodeWidth == width) assert(p.decodedUopWidth >= width) @@ -120,8 +139,11 @@ class OooParamsSpec extends AnyFunSuite { assertThrows[IllegalArgumentException](OooParams(iexBypassPorts = 0)) assertThrows[IllegalArgumentException](OooParams(iexLoadCancelPorts = 0)) assertThrows[IllegalArgumentException](OooParams(iexTerminalWidth = 0)) - assertThrows[IllegalArgumentException](OooParams(iexLoadTrackEntries = 3)) assertThrows[IllegalArgumentException](OooParams(loadGenerationWidth = 0)) + assertThrows[IllegalArgumentException]( + OooParams(memoryTransactionIdWidth = 0)) + assertThrows[IllegalArgumentException]( + OooParams(memoryTransactionGenerationWidth = 0)) assertThrows[IllegalArgumentException](OooParams( executeSlotGenerationWidth = 0)) assertThrows[IllegalArgumentException](OooParams(iexIssueDomainCount = 0)) diff --git a/chisel/src/test/scala/linxcore/ooo/OooPcBufferSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooPcBufferSpec.scala index 95a2cc04..03933f40 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooPcBufferSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooPcBufferSpec.scala @@ -2,615 +2,482 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ import org.scalatest.funsuite.AnyFunSuite class OooPcBufferSpec extends AnyFunSuite with ChiselSim { private def clear(dut: OooPcBuffer): Unit = { dut.io.prepare.valid.poke(false.B) dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.selectedLimit.valid.poke(false.B) + dut.io.selectedLimit.bits.poke( + 0.U.asTypeOf(dut.io.selectedLimit.bits)) + dut.io.publicationIdentity.valid.poke(false.B) + dut.io.publicationIdentity.bits.poke( + 0.U.asTypeOf(dut.io.publicationIdentity.bits)) dut.io.publishFire.poke(false.B) - dut.io.commit.valid.poke(false.B) - dut.io.commit.bits.poke(0.U.asTypeOf(dut.io.commit.bits)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.readTokens.foreach(_.poke(0.U.asTypeOf(dut.io.readTokens.head))) + dut.io.commitPreview.valid.poke(false.B) + dut.io.commitPreview.bits.poke(0.U.asTypeOf(dut.io.commitPreview.bits)) + dut.io.commitApply.poke(false.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.io.readAddress.foreach(_.poke(0.U.asTypeOf(dut.io.readAddress.head))) } - private def pokePrepare( - dut: OooPcBuffer, + private def pokeRob( + rob: RobIdentity, + p: CoreParams, stid: Int, - transactionId: Int, - firstRid: Int, - pcs: Seq[Long], - releases: Set[Int] = Set.empty, - traps: Set[Int] = Set.empty, + rid: Int, + member: Int = 0, peId: Int = 3): Unit = { + rob.peId.poke(peId.U) + rob.stid.poke(stid.U) + rob.ridSlot.poke((rid % p.ooo.robGroupsPerStid).U) + rob.ridGeneration.poke((rid / p.ooo.robGroupsPerStid).U) + rob.memberIndex.poke(member.U) + rob.residentGeneration.poke((0x20 + rid * 4 + member).U) + rob.bid.poke((7 + rid).U) + rob.brobGeneration.poke((0x30 + rid).U) + } + + private def pokePrepare( + dut: OooPcBuffer, + lanes: Seq[(Int, Int, Long)], + stid: Int = 0, + blockStops: Set[Int] = Set.empty, + traps: Set[Int] = Set.empty): Unit = { + val p = dut.p + val groups = lanes.map(_._1).distinct + dut.io.selectedLimit.valid.poke(false.B) + dut.io.selectedLimit.bits.poke( + 0.U.asTypeOf(dut.io.selectedLimit.bits)) dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) - val transaction = dut.io.prepare.bits.transaction - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(5.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.groupCount.poke(pcs.size.U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(5.U) - transaction.decoded.uopMask.poke(((1 << pcs.size) - 1).U) - transaction.groupMask.poke(((1 << pcs.size) - 1).U) - pcs.zipWithIndex.foreach { case (pc, index) => - val absoluteRid = firstRid + index - val group = transaction.groups(index) + dut.io.prepare.bits.count.poke(lanes.size.U) + dut.io.prepare.bits.groupCount.poke(groups.size.U) + groups.zipWithIndex.foreach { case (rid, groupIndex) => + val group = dut.io.prepare.bits.groups(groupIndex) group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((absoluteRid % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((absoluteRid / dut.p.robGroupsPerStid).U) - group.logicalUopMask.poke((1 << index).U) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - group.releasePcBase.poke(releases(index).B) - group.preciseTrap.poke(traps(index).B) - transaction.uopGroupIndex(index).poke(index.U) - - val uop = transaction.decoded.uops(index) - uop.valid.poke(true.B) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(peId.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke((100 + index).U) - uop.identity.parents(0).key.epoch.poke(5.U) - uop.identity.parents(0).pc.poke(pc.U) + group.peId.poke(3.U) + group.stid.poke(stid.U) + group.ridSlot.poke((rid % p.ooo.robGroupsPerStid).U) + group.ridGeneration.poke((rid / p.ooo.robGroupsPerStid).U) + } + lanes.zipWithIndex.foreach { case ((rid, member, pc), laneIndex) => + val lane = dut.io.prepare.bits.entries(laneIndex) + lane.uop.decoded.valid.poke(true.B) + pokeRob(lane.uop.decoded.rob, p, stid, rid, member) + lane.uop.decoded.instruction.parent.pc.poke(pc.U) + lane.uop.decoded.instruction.parent.lengthBytes.poke(2.U) + lane.uop.decoded.instruction.parent.identity.peId.poke(3.U) + lane.uop.decoded.instruction.parent.identity.stid.poke(stid.U) + lane.uop.decoded.instruction.parent.identity.instructionId.poke( + (0x100 + laneIndex).U) + lane.uop.decoded.instruction.parent.identity.epoch.poke(5.U) + lane.uop.decoded.blockStop.poke(blockStops(laneIndex).B) + lane.blockStop.poke(blockStops(laneIndex).B) + lane.trap.valid.poke(traps(laneIndex).B) + lane.trap.cause.poke((if (traps(laneIndex)) 9 else 0).U) } dut.io.prepare.valid.poke(true.B) } - private def publish(dut: OooPcBuffer): Unit = { + private def selectPrefix( + dut: OooPcBuffer, + expectedCount: Int, + expectedGroupCount: Int): Unit = { + dut.io.prefixOffer.valid.expect(true.B) + dut.io.prefixOffer.bits.count.expect(expectedCount.U) + dut.io.prefixOffer.bits.groupCount.expect(expectedGroupCount.U) + dut.io.selectedLimit.bits.poke( + 0.U.asTypeOf(dut.io.selectedLimit.bits)) + dut.io.selectedLimit.bits.count.poke(expectedCount.U) + dut.io.selectedLimit.bits.groupCount.poke(expectedGroupCount.U) + dut.io.selectedLimit.valid.poke(true.B) + } + + private def publish( + dut: OooPcBuffer, + residentGenerationDelta: Int = 0, + bidDelta: Int = 0, + brobGenerationDelta: Int = 0): Unit = { dut.io.prepareReady.expect(true.B) + val count = dut.io.prepared.count.peek().litValue.toInt + dut.io.publicationIdentity.bits.poke( + 0.U.asTypeOf(dut.io.publicationIdentity.bits)) + dut.io.publicationIdentity.bits.count.poke(count.U) + for (lane <- 0 until count) { + val source = dut.io.prepare.bits.entries(lane).uop.decoded.rob + val bound = dut.io.publicationIdentity.bits.entries(lane) + bound.valid.poke(true.B) + bound.rob.poke(source.peek()) + bound.rob.residentGeneration.poke( + (source.residentGeneration.peek().litValue + residentGenerationDelta).U) + bound.rob.bid.poke((source.bid.peek().litValue + bidDelta).U) + bound.rob.brobGeneration.poke( + (source.brobGeneration.peek().litValue + brobGenerationDelta).U) + } + dut.io.publicationIdentity.valid.poke(true.B) dut.io.publishFire.poke(true.B) dut.clock.step() dut.io.publishFire.poke(false.B) + dut.io.publicationIdentity.valid.poke(false.B) dut.io.prepare.valid.poke(false.B) + dut.io.selectedLimit.valid.poke(false.B) } - private def pokeCommit( + private def readBase( dut: OooPcBuffer, + port: Int, stid: Int, - groups: Seq[(Int, Int, Int)], - peId: Int = 3): Unit = { - dut.io.commit.bits.poke(0.U.asTypeOf(dut.io.commit.bits)) - dut.io.commit.bits.release.groupCount.poke(groups.size.U) - val firstRid = groups.head._1 - dut.io.commit.bits.release.firstGroup.valid.poke(true.B) - dut.io.commit.bits.release.firstGroup.peId.poke(peId.U) - dut.io.commit.bits.release.firstGroup.stid.poke(stid.U) - dut.io.commit.bits.release.firstGroup.ridSlot.poke( - (firstRid % dut.p.robGroupsPerStid).U) - dut.io.commit.bits.release.firstGroup.ridGeneration.poke( - (firstRid / dut.p.robGroupsPerStid).U) - groups.zipWithIndex.foreach { case ((absoluteRid, pcIndex, pcEpoch), index) => - val group = dut.io.commit.bits.groups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((absoluteRid % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((absoluteRid / dut.p.robGroupsPerStid).U) - group.pcBase.valid.poke(true.B) - group.pcBase.index.poke(pcIndex.U) - group.pcBase.allocationEpoch.poke(pcEpoch.U) - } - dut.io.commit.valid.poke(true.B) + index: Int, + epoch: Int, + valid: Boolean, + base: Long = 0): Unit = { + val address = dut.io.readAddress(port) + address.valid.poke(true.B) + address.stid.poke(stid.U) + address.pcBufferIndex.poke(index.U) + address.allocationEpoch.poke(epoch.U) + dut.io.readPcBase(port).valid.expect(valid.B) + if (valid) dut.io.readPcBase(port).bits.expect(base.U) } - private def commit(dut: OooPcBuffer): Unit = { - dut.io.commit.ready.expect(true.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) + private def pokeCommit( + dut: OooPcBuffer, + rows: Seq[(Int, Int, Int, Boolean)], + stid: Int = 0): Unit = { + dut.io.commitPreview.bits.poke( + 0.U.asTypeOf(dut.io.commitPreview.bits)) + dut.io.commitPreview.bits.count.poke(rows.size.U) + rows.zipWithIndex.foreach { case ((rid, index, epoch, groupLast), lane) => + val entry = dut.io.commitPreview.bits.entries(lane) + pokeRob(entry.rob, dut.p, stid, rid) + entry.pcBufferIndexOffset.valid.poke(true.B) + entry.pcBufferIndexOffset.pcBufferIndex.poke(index.U) + entry.pcBufferIndexOffset.pcOffset.poke(0.U) + entry.pcBufferIndexOffset.allocationEpoch.poke(epoch.U) + entry.robGroupLast.poke(groupLast.B) + } + dut.io.commitPreview.valid.poke(true.B) } - private def pokeRecoveryPlan( + private def pokeRecoveryPrepare( dut: OooPcBuffer, - stid: Int, - staleEpoch: Boolean = false): Unit = { - val partitionBase = stid * dut.p.pcEntriesPerStid - val plan = dut.io.recoveryPrepare.bits + firstRid: Int, + lastRid: Int, + survivingRid: Option[Int], + stid: Int = 0, + transactionId: Int = 0x55, + residentGenerationDelta: Int = 0, + bidDelta: Int = 0, + brobGenerationDelta: Int = 0): Unit = { + def bindIdentity(rob: RobIdentity, rid: Int): Unit = { + rob.residentGeneration.poke((0x20 + rid * 4 + + residentGenerationDelta).U) + rob.bid.poke((7 + rid + bidDelta).U) + rob.brobGeneration.poke((0x30 + rid + + brobGenerationDelta).U) + } + val plan = dut.io.recovery.prepare.bits plan.poke(0.U.asTypeOf(plan)) - plan.valid.poke(true.B) - plan.request.rename.key.member.group.valid.poke(true.B) - plan.request.rename.key.member.group.peId.poke(3.U) - plan.request.rename.key.member.group.stid.poke(stid.U) - plan.request.rename.key.member.bid.valid.poke(true.B) - plan.oldOccupied.poke(5.U) - plan.newOccupied.poke(2.U) - plan.killedGroupCount.poke(3.U) - plan.killedGroupMask.poke(7.U) - plan.survivingTailValid.poke(true.B) - plan.survivingTail.valid.poke(true.B) - plan.survivingTail.key.valid.poke(true.B) - plan.survivingTail.key.peId.poke(3.U) - plan.survivingTail.key.stid.poke(stid.U) - plan.survivingTail.key.ridSlot.poke(1.U) - plan.survivingTail.pcBase.valid.poke(true.B) - plan.survivingTail.pcBase.index.poke(partitionBase.U) - plan.survivingTail.pcBase.allocationEpoch.poke(0.U) - - val groups = Seq( - (2, 1, true, true, 0), - (3, 1, false, false, 0), - (4, 2, true, true, 1)) - groups.zipWithIndex.foreach { - case ((rid, local, allocated, implicitClose, priorLocal), index) => - val group = plan.killedGroups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(rid.U) - group.key.ridGeneration.poke(0.U) - group.pcBase.valid.poke(true.B) - group.pcBase.index.poke((partitionBase + local).U) - group.pcBase.allocationEpoch.poke( - (if (staleEpoch && index == 1) 1 else 0).U) - group.pcBaseAllocated.poke(allocated.B) - group.pcImplicitCloseValid.poke(implicitClose.B) - group.pcImplicitClose.valid.poke(implicitClose.B) - group.pcImplicitClose.index.poke((partitionBase + priorLocal).U) - group.pcImplicitClose.allocationEpoch.poke(0.U) + plan.transactionId.poke(transactionId.U) + plan.phase.poke(RecoveryPhase.Prepare) + plan.cause.poke(RecoveryCause.Branch) + pokeRob(plan.trigger, dut.p, stid, firstRid) + bindIdentity(plan.trigger, firstRid) + plan.firstKilledValid.poke(true.B) + pokeRob(plan.firstKilled, dut.p, stid, firstRid) + bindIdentity(plan.firstKilled, firstRid) + pokeRob(plan.lastKilled, dut.p, stid, lastRid) + bindIdentity(plan.lastKilled, lastRid) + plan.killedGroupCount.poke((lastRid - firstRid + 1).U) + plan.killedMemberCount.poke((lastRid - firstRid + 1).U) + plan.survivingTailValid.poke(survivingRid.nonEmpty.B) + survivingRid.foreach { rid => + pokeRob(plan.survivingTail, dut.p, stid, rid) + bindIdentity(plan.survivingTail, rid) } - dut.io.recoveryPrepare.valid.poke(true.B) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) } - private def waitForRecoveryReady( - dut: OooPcBuffer, - maxCycles: Int = 32): Int = { + private def waitPrepared(dut: OooPcBuffer, maxCycles: Int = 64): Unit = { var cycles = 0 - while (!dut.io.recoveryPrepareReady.peek().litToBoolean && - !dut.io.recoveryRejected.valid.peek().litToBoolean && + while (!dut.io.recovery.prepared.valid.peek().litToBoolean && cycles < maxCycles) { dut.clock.step() cycles += 1 } - assert(cycles < maxCycles, "PC recovery preparation did not terminate") - dut.io.recoveryRejected.valid.expect(false.B) - dut.io.recoveryPrepareReady.expect(true.B) - cycles + assert(cycles < maxCycles, "PC-buffer recovery preparation did not finish") + dut.io.recovery.prepared.bits.phase.expect(RecoveryPhase.Prepare) } - private def waitForRecoveryReject( - dut: OooPcBuffer, - maxCycles: Int = 32): Int = { - var cycles = 0 - while (!dut.io.recoveryRejected.valid.peek().litToBoolean && - !dut.io.recoveryPrepareReady.peek().litToBoolean && - cycles < maxCycles) { - dut.clock.step() - cycles += 1 - } - assert(cycles < maxCycles, "PC recovery rejection did not terminate") - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - cycles + private def terminateRecovery(dut: OooPcBuffer, apply: Boolean): Unit = { + val terminal = if (apply) dut.io.recovery.apply else dut.io.recovery.abort + terminal.bits.poke(dut.io.recovery.prepared.bits.peek()) + terminal.bits.phase.poke( + if (apply) RecoveryPhase.Apply else RecoveryPhase.Abort) + terminal.valid.poke(true.B) + dut.clock.step() + terminal.valid.poke(false.B) } - test("reuses one base with byte offsets for 2 4 6 and 8-byte instruction PCs") { - val p = OooParams(instructionDecodeWidth = 4, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("groups exact ROB members onto one base and returns six stale-safe base reads") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 106, 112), releases = Set(3)) - dut.io.prepared.allocatedBases.expect(1.U) - for (index <- 0 until 4) { - dut.io.prepared.groupTokens(index).index.expect(16.U) - } - Seq(0, 2, 6, 12).zipWithIndex.foreach { case (offset, index) => - dut.io.prepared.parentTokens(index)(0).byteOffset.expect(offset.U) + pokePrepare(dut, Seq((0, 0, 100L), (0, 1, 102L), (1, 0, 106L), + (2, 0, 112L)), blockStops = Set(3)) + selectPrefix(dut, expectedCount = 4, expectedGroupCount = 3) + dut.io.prepared.count.expect(4.U) + Seq(0, 2, 6, 12).zipWithIndex.foreach { case (offset, lane) => + dut.io.prepared.lanes(lane).valid.expect(true.B) + dut.io.prepared.lanes(lane).pcBufferIndex.expect(0.U) + dut.io.prepared.lanes(lane).pcOffset.expect(offset.U) } + readBase(dut, 0, stid = 0, index = 0, epoch = 0, valid = false) publish(dut) - dut.io.usedBases(1).expect(1.U) - dut.io.currentValid(1).expect(false.B) - dut.io.readTokens(0).valid.poke(true.B) - dut.io.readTokens(0).index.poke(16.U) - dut.io.readTokens(0).byteOffset.poke(12.U) - dut.io.readTokens(0).allocationEpoch.poke(0.U) - dut.io.readValid(0).expect(true.B) - dut.io.readPc(0).expect(112.U) - dut.io.readTokens(1).valid.poke(true.B) - dut.io.readTokens(1).index.poke(16.U) - dut.io.readTokens(1).byteOffset.poke(2.U) - dut.io.readTokens(1).allocationEpoch.poke(1.U) - dut.io.readValid(1).expect(false.B) - - pokeCommit(dut, stid = 1, - groups = (0 until 4).map(index => (index, 16, 0))) - commit(dut) - dut.io.usedBases(1).expect(0.U) + for (port <- 0 until dut.p.ooo.pcReadPorts) { + readBase(dut, port, stid = 0, index = 0, epoch = 0, + valid = true, base = 100) + } + readBase(dut, 1, stid = 0, index = 0, epoch = 1, valid = false) } } - test("rolls back exact PC-base tail and reopens the surviving base") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("admits the oldest three-base prefix and retries the younger suffix") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 1000)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - pcs = Seq(1002, 2000)) - publish(dut) - dut.io.usedBases(1).expect(3.U) - dut.io.currentValid(1).expect(true.B) - dut.io.current(1).index.expect(18.U) - - pokeRecoveryPlan(dut, stid = 1) - assert(waitForRecoveryReady(dut) == 3) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.recoveryPrepared.freedBases.expect(2.U) - dut.io.recoveryPrepared.tailAfter.index.expect(17.U) - dut.io.recoveryPrepared.currentAfterValid.expect(true.B) - dut.io.recoveryPrepared.currentAfter.index.expect(16.U) - dut.io.recoveryPrepared.currentBaseAfter.expect(100.U) - dut.clock.step() - dut.io.usedBases(1).expect(3.U) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedBases(1).expect(1.U) - dut.io.currentValid(1).expect(true.B) - dut.io.current(1).index.expect(16.U) - for (port <- 0 until p.pcReadPorts) { - dut.io.readTokens(port).valid.poke(true.B) - dut.io.readTokens(port).index.poke(17.U) - dut.io.readTokens(port).allocationEpoch.poke(0.U) - dut.io.readValid(port).expect(false.B) - dut.io.readTokens(port).index.poke(16.U) - dut.io.readValid(port).expect(true.B) - dut.io.readPc(port).expect(100.U) - } - - pokePrepare(dut, stid = 1, transactionId = 2, firstRid = 2, - pcs = Seq(1000)) + pokePrepare(dut, + Seq((0, 0, 0L), (1, 0, 1000L), (2, 0, 2000L), (3, 0, 3000L))) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) dut.io.prepareReady.expect(true.B) - dut.io.prepared.groupTokens(0).index.expect(17.U) - dut.io.prepared.implicitCloseMask.expect(1.U) - dut.io.prepared.implicitCloseTokens(0).index.expect(16.U) + dut.io.prepared.count.expect(3.U) + dut.io.prepared.groupCount.expect(3.U) + dut.io.prepared.lanes(0).valid.expect(true.B) + dut.io.prepared.lanes(1).valid.expect(true.B) + dut.io.prepared.lanes(2).valid.expect(true.B) + dut.io.prepared.lanes(3).valid.expect(false.B) publish(dut) - dut.io.usedBases(1).expect(2.U) - dut.io.current(1).index.expect(17.U) - } - } - - test("rejects a stale killed PC epoch without buffer mutation") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 1000)) + readBase(dut, 0, 0, 0, 0, valid = true, base = 0) + readBase(dut, 1, 0, 1, 0, valid = true, base = 1000) + readBase(dut, 2, 0, 2, 0, valid = true, base = 2000) + + pokePrepare(dut, Seq((3, 0, 3000L))) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) + dut.io.prepared.count.expect(1.U) + dut.io.prepared.lanes(0).pcBufferIndex.expect(3.U) publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - pcs = Seq(1002, 2000)) + readBase(dut, 0, 0, 3, 0, valid = true, base = 3000) + + pokePrepare(dut, + Seq((4, 0, 4000L), (5, 0, 5000L), (6, 0, 6000L)), + traps = Set(2)) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) + dut.io.prepared.lanes(0).pcBufferIndex.expect(4.U) + dut.io.prepared.lanes(1).pcBufferIndex.expect(5.U) + dut.io.prepared.lanes(2).pcBufferIndex.expect(6.U) publish(dut) - - pokeRecoveryPlan(dut, stid = 1, staleEpoch = true) - // A reject is observable while the final slice is being evaluated; - // unlike prepared success it does not need one more retention edge. - assert(waitForRecoveryReject(dut) == 2) - dut.io.recoveryRejected.bits.killedRowsExact.expect(false.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedBases(1).expect(3.U) - dut.io.current(1).index.expect(18.U) + readBase(dut, 0, 0, 6, 0, valid = true, base = 6000) } } - test("aborts a private scan while another STID publishes then retries exactly") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("never splits a ROB group at the three-write boundary") { + simulate(new OooPcBuffer(ParamProfiles.W8)) { dut => clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 1000)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - pcs = Seq(1002, 2000)) - publish(dut) - - pokeRecoveryPlan(dut, stid = 1) - dut.clock.step() - dut.io.recoveryPrepareReady.expect(false.B) - - pokePrepare(dut, stid = 2, transactionId = 2, firstRid = 0, - pcs = Seq(400), releases = Set(0)) + pokePrepare(dut, Seq( + (0, 0, 0L), + (0, 1, 2L), + (1, 0, 1000L), + (2, 0, 2000L), + (3, 0, 3000L), + (3, 1, 3002L), + (3, 2, 3004L), + (3, 3, 3006L), + )) + + selectPrefix(dut, expectedCount = 4, expectedGroupCount = 3) dut.io.prepareReady.expect(true.B) + dut.io.prepared.count.expect(4.U) + dut.io.prepared.groupCount.expect(3.U) + (0 until 4).foreach(lane => + dut.io.prepared.lanes(lane).valid.expect(true.B)) + (4 until 8).foreach(lane => + dut.io.prepared.lanes(lane).valid.expect(false.B)) publish(dut) - dut.io.usedBases(2).expect(1.U) - pokePrepare(dut, stid = 1, transactionId = 3, firstRid = 5, - pcs = Seq(2002)) - dut.io.prepareReady.expect(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - dut.io.prepareReady.expect(true.B) - dut.io.usedBases(1).expect(3.U) - dut.io.current(1).index.expect(18.U) - dut.io.prepare.valid.poke(false.B) - - pokeRecoveryPlan(dut, stid = 1) - assert(waitForRecoveryReady(dut) == 3) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.usedBases(1).expect(1.U) - dut.io.usedBases(2).expect(1.U) + readBase(dut, 0, 0, 0, 0, valid = true, base = 0) + readBase(dut, 1, 0, 1, 0, valid = true, base = 1000) + readBase(dut, 2, 0, 2, 0, valid = true, base = 2000) + readBase(dut, 3, 0, 3, 0, valid = false) } } - test("rejects a drifting retained recovery plan without row mutation") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("applies an ordered common commit only on commitApply and rejects stale epochs") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 1000)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - pcs = Seq(1002, 2000)) + pokePrepare(dut, Seq((0, 0, 100L), (1, 0, 102L)), + blockStops = Set(1)) + selectPrefix(dut, expectedCount = 2, expectedGroupCount = 2) publish(dut) - pokeRecoveryPlan(dut, stid = 1) + pokeCommit(dut, Seq((0, 0, 1, true), (1, 0, 0, true))) + dut.io.commitReady.expect(false.B) + pokeCommit(dut, Seq((0, 0, 0, true), (1, 0, 0, true))) + dut.io.commitReady.expect(true.B) dut.clock.step() - dut.io.recoveryPrepare.bits.killedGroups(0).key.ridSlot.poke(7.U) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.bits.requested.killedGroups(0).key.ridSlot - .expect(2.U) - dut.io.recoveryRejected.bits.usedBases.expect(3.U) + readBase(dut, 0, 0, 0, 0, valid = true, base = 100) + dut.io.commitApply.poke(true.B) dut.clock.step() - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.usedBases(1).expect(3.U) - dut.io.current(1).index.expect(18.U) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - - pokeRecoveryPlan(dut, stid = 1) - assert(waitForRecoveryReady(dut) == 3) + dut.io.commitApply.poke(false.B) + dut.io.commitPreview.valid.poke(false.B) + readBase(dut, 0, 0, 0, 0, valid = false) } } - test("honors a two-group PC recovery scan slice") { - val p = OooParams(instructionDecodeWidth = 4, - robGroupsPerStid = 8, pcBufferEntries = 64, - pcRecoveryScanGroupsPerCycle = 2) - simulate(new OooPcBuffer(p)) { dut => + test("held same-STID commit preview does not block an open block admission") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(100, 102, 1000)) - publish(dut) - pokePrepare(dut, stid = 1, transactionId = 1, firstRid = 3, - pcs = Seq(1002, 2000)) + pokePrepare(dut, Seq((0, 0, 100L))) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) publish(dut) - pokeRecoveryPlan(dut, stid = 1) - assert(waitForRecoveryReady(dut) == 5) - dut.io.recoveryPrepared.freedBases.expect(2.U) - dut.io.recoveryPrepared.tailAfter.index.expect(17.U) + pokeCommit(dut, Seq((0, 0, 0, true))) + dut.io.commitReady.expect(true.B) + dut.io.commitApply.expect(false.B) + + pokePrepare(dut, Seq((1, 0, 102L))) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) + dut.io.prepareReady.expect(true.B) + dut.io.prepared.lanes.head.pcBufferIndex.expect(0.U) + dut.io.prepared.lanes.head.pcOffset.expect(2.U) } } - test("allocates a new base on offset overflow and retains the old close owner") { - val p = OooParams(instructionDecodeWidth = 2, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("aborts without mutation then applies an exact suffix and reopens its survivor") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 2, transactionId = 0, firstRid = 0, - pcs = Seq(100, 300), releases = Set(1)) - dut.io.prepared.allocatedBases.expect(2.U) - dut.io.prepared.groupTokens(0).index.expect(32.U) - dut.io.prepared.groupTokens(1).index.expect(33.U) - dut.io.prepared.implicitCloseMask.expect("b10".U) + pokePrepare(dut, + Seq((0, 0, 100L), (1, 0, 1000L), (2, 0, 2000L))) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) publish(dut) - dut.io.usedBases(2).expect(2.U) - pokeCommit(dut, stid = 2, groups = Seq((0, 32, 0), (1, 33, 0))) - commit(dut) - dut.io.usedBases(2).expect(0.U) + pokeRecoveryPrepare(dut, firstRid = 1, lastRid = 2, + survivingRid = Some(0)) + waitPrepared(dut) + terminateRecovery(dut, apply = false) + readBase(dut, 0, 0, 1, 0, valid = true, base = 1000) + readBase(dut, 1, 0, 2, 0, valid = true, base = 2000) + + pokeRecoveryPrepare(dut, firstRid = 1, lastRid = 2, + survivingRid = Some(0), transactionId = 0x56) + waitPrepared(dut) + terminateRecovery(dut, apply = true) + readBase(dut, 0, 0, 0, 0, valid = true, base = 100) + readBase(dut, 1, 0, 1, 0, valid = false) + readBase(dut, 2, 0, 2, 0, valid = false) + + pokePrepare(dut, Seq((1, 0, 1000L))) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) + dut.io.prepared.lanes(0).pcBufferIndex.expect(1.U) + publish(dut) } } - test("closes a predicted-taken base and allocates the following discontinuity") { - val p = OooParams(instructionDecodeWidth = 2, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => + test("redirected stop closes and frees an open-current recovery survivor") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - pcs = Seq(40, 1000), releases = Set(0, 1)) - dut.io.prepared.allocatedBases.expect(2.U) - dut.io.prepared.groupTokens(0).index.expect(0.U) - dut.io.prepared.groupTokens(1).index.expect(1.U) + pokePrepare(dut, + Seq((0, 0, 0x7000L), (1, 0, 0x7004L), (2, 0, 0x7008L)), + blockStops = Set(2)) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) publish(dut) - pokeCommit(dut, stid = 0, groups = Seq((0, 0, 0), (1, 1, 0))) - commit(dut) - dut.io.usedBases(0).expect(0.U) - } - } + readBase(dut, 0, 0, 0, 0, valid = true, base = 0x7000L) - test("rejects more than three base writes without partial publication") { - val p = OooParams(instructionDecodeWidth = 4, pcBufferEntries = 64, pcWritePorts = 3) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 3, transactionId = 0, firstRid = 0, - pcs = Seq(0, 256, 512, 768), releases = Set(0, 1, 2, 3)) - dut.io.prepared.allocatedBases.expect(4.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) - dut.io.publishFire.poke(false.B) - dut.clock.step() - dut.io.usedBases(3).expect(0.U) - } - } + pokeRecoveryPrepare(dut, firstRid = 1, lastRid = 2, + survivingRid = Some(0)) + waitPrepared(dut) + terminateRecovery(dut, apply = true) - test("rejects an inconsistent uop group index and logical mask") { - val p = OooParams(instructionDecodeWidth = 2, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 1, transactionId = 0, firstRid = 0, - pcs = Seq(80, 88), releases = Set(1)) - dut.io.prepare.bits.transaction.uopGroupIndex(1).poke(0.U) - dut.io.prepareReady.expect(false.B) - dut.io.prepareRejected.valid.expect(true.B) + pokeCommit(dut, Seq((0, 0, 0, true))) + dut.io.commitReady.expect(true.B) + dut.io.commitApply.poke(true.B) dut.clock.step() - dut.io.usedBases(1).expect(0.U) - } - } - - test("rejects skipped and duplicate ROB groups for one PC base") { - val p = OooParams(instructionDecodeWidth = 2, pcBufferEntries = 64) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 7, - pcs = Seq(120, 126), releases = Set(1)) + dut.io.commitApply.poke(false.B) + dut.io.commitPreview.valid.poke(false.B) + readBase(dut, 0, 0, 0, 0, valid = true, base = 0x7000L) + + pokePrepare(dut, Seq((1, 0, 0x7008L)), blockStops = Set(0)) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) + dut.io.prepared.lanes.head.pcBufferIndex.expect(0.U) + dut.io.prepared.lanes.head.allocationEpoch.expect(0.U) publish(dut) - pokeCommit(dut, stid = 0, groups = Seq((8, 0, 0))) - dut.io.commit.ready.expect(false.B) + pokeCommit(dut, Seq((1, 0, 0, true))) + dut.io.commitReady.expect(true.B) + dut.io.commitApply.poke(true.B) dut.clock.step() - dut.io.commit.valid.poke(false.B) - - pokeCommit(dut, stid = 0, groups = Seq((7, 0, 0))) - commit(dut) - pokeCommit(dut, stid = 0, groups = Seq((7, 0, 0))) - dut.io.commit.ready.expect(false.B) - dut.clock.step() - dut.io.commit.valid.poke(false.B) - - pokeCommit(dut, stid = 0, groups = Seq((8, 0, 0))) - commit(dut) - dut.io.usedBases(0).expect(0.U) + dut.io.commitApply.poke(false.B) + dut.io.commitPreview.valid.poke(false.B) + readBase(dut, 0, 0, 0, 0, valid = false) } } - test("keeps fixed STID partitions and wraps allocation epoch independently") { - val p = OooParams( - instructionDecodeWidth = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcWritePorts = 2, - retireGroupWidth = 2, - stidCount = 4) - simulate(new OooPcBuffer(p)) { dut => + test("retains ROB-bound endpoint identities across PC-buffer publication") { + simulate(new OooPcBuffer(ParamProfiles.W4)) { dut => clear(dut) - for (iteration <- 0 until 2) { - pokePrepare(dut, stid = 3, transactionId = iteration, firstRid = iteration, - pcs = Seq(1000 + iteration * 256), releases = Set(0)) - dut.io.prepared.groupTokens(0).index.expect((6 + iteration).U) - dut.io.prepared.groupTokens(0).allocationEpoch.expect(0.U) - publish(dut) - pokeCommit(dut, stid = 3, groups = Seq((iteration, 6 + iteration, 0))) - commit(dut) - dut.io.usedBases(0).expect(0.U) - } - pokePrepare(dut, stid = 3, transactionId = 2, firstRid = 2, - pcs = Seq(2000), releases = Set(0)) - dut.io.prepared.groupTokens(0).index.expect(6.U) - dut.io.prepared.groupTokens(0).allocationEpoch.expect(1.U) + pokePrepare(dut, + Seq((0, 0, 100L), (1, 0, 1000L), (2, 0, 2000L))) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) + publish(dut, residentGenerationDelta = 9, bidDelta = 1, + brobGenerationDelta = 7) + + pokeRecoveryPrepare(dut, firstRid = 1, lastRid = 2, + survivingRid = Some(0), residentGenerationDelta = 9, bidDelta = 1, + brobGenerationDelta = 7) + waitPrepared(dut) + terminateRecovery(dut, apply = true) + readBase(dut, 0, 0, 0, 0, valid = true, base = 100) + readBase(dut, 1, 0, 1, 0, valid = false) + readBase(dut, 2, 0, 2, 0, valid = false) } } - test("maps consecutive bases across banks and rows while preserving all six reads") { - val p = OooParams(instructionDecodeWidth = 4, pcBufferEntries = 64, - pcBankCount = 4) + test("fences only the recovery target STID while a peer publishes") { + val p = ParamProfiles.W4.copy( + ooo = ParamProfiles.W4.ooo.copy(stidCount = 2)) simulate(new OooPcBuffer(p)) { dut => clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - pcs = Seq(0, 256, 512), releases = Set(0, 1, 2)) - (0 until 3).foreach { index => - dut.io.prepared.groupTokens(index).index.expect(index.U) - } + pokePrepare(dut, + Seq((0, 0, 100L), (1, 0, 1000L), (2, 0, 2000L)), stid = 0) + selectPrefix(dut, expectedCount = 3, expectedGroupCount = 3) publish(dut) + pokeRecoveryPrepare(dut, firstRid = 1, lastRid = 2, + survivingRid = Some(0), stid = 0) - pokePrepare(dut, stid = 0, transactionId = 1, firstRid = 3, - pcs = Seq(768), releases = Set(0)) - dut.io.prepared.groupTokens(0).index.expect(3.U) - publish(dut) - pokePrepare(dut, stid = 0, transactionId = 2, firstRid = 4, - pcs = Seq(1024), releases = Set(0)) - dut.io.prepared.groupTokens(0).index.expect(4.U) - publish(dut) - dut.io.usedBases(0).expect(5.U) - - Seq(0, 1, 2, 3, 4, 0).zipWithIndex.foreach { - case (tokenIndex, port) => - dut.io.readTokens(port).valid.poke(true.B) - dut.io.readTokens(port).index.poke(tokenIndex.U) - dut.io.readTokens(port).allocationEpoch.poke(0.U) - dut.io.readValid(port).expect(true.B) - dut.io.readPc(port).expect((tokenIndex * 256).U) - } - - pokeCommit(dut, stid = 0, - groups = (0 until 4).map(index => (index, index, 0))) - commit(dut) - dut.io.usedBases(0).expect(1.U) - dut.io.readValid(0).expect(false.B) - dut.io.readValid(4).expect(true.B) - dut.io.readPc(4).expect(1024.U) - - pokeCommit(dut, stid = 0, groups = Seq((4, 4, 0))) - commit(dut) - dut.io.usedBases(0).expect(0.U) - } - } - - test("broadcasts base allocation and release across three fixed two-read replicas") { - val p = OooParams(instructionDecodeWidth = 4, pcBufferEntries = 64, - pcBankCount = 4, pcReadPorts = 6, pcReadReplicaCount = 3) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 2, transactionId = 0, firstRid = 0, - pcs = Seq(4096), releases = Set(0)) + pokePrepare(dut, Seq((0, 0, 500L)), stid = 1) + selectPrefix(dut, expectedCount = 1, expectedGroupCount = 1) + dut.io.prepareReady.expect(true.B) publish(dut) + readBase(dut, 0, 1, 32, 0, valid = true, base = 500) - for (port <- 0 until p.pcReadPorts) { - dut.io.readTokens(port).valid.poke(true.B) - dut.io.readTokens(port).index.poke(32.U) - dut.io.readTokens(port).byteOffset.poke((port * 2).U) - dut.io.readTokens(port).allocationEpoch.poke(0.U) - dut.io.readValid(port).expect(true.B) - dut.io.readPc(port).expect((4096 + port * 2).U) - } - - pokeCommit(dut, stid = 2, groups = Seq((0, 32, 0))) - commit(dut) - for (port <- 0 until p.pcReadPorts) { - dut.io.readValid(port).expect(false.B) - dut.io.readPc(port).expect(0.U) - } - } - } - - test("elaborates 1 2 and 4 PC banks with 2 4 and 6 decode width") { - Seq((2, 1, 1, 1), (4, 2, 2, 2), (6, 4, 3, 4)).foreach { - case (width, bankCount, writePorts, retireWidth) => - val p = OooParams( - instructionDecodeWidth = width, - pcBufferEntries = 64, - pcBankCount = bankCount, - pcWritePorts = writePorts, - retireGroupWidth = retireWidth) - simulate(new OooPcBuffer(p)) { dut => - clear(dut) - pokePrepare(dut, stid = 0, transactionId = 0, firstRid = 0, - pcs = (0 until width).map(index => 64L + index * 8), - releases = Set(width - 1)) - dut.io.prepareReady.expect(true.B) - dut.io.prepared.allocatedBases.expect(1.U) - } + pokePrepare(dut, Seq((3, 0, 3000L)), stid = 0) + dut.io.prefixOffer.valid.expect(false.B) + dut.io.prepareReady.expect(false.B) + dut.io.prepare.valid.poke(false.B) + waitPrepared(dut) + terminateRecovery(dut, apply = true) } } } diff --git a/chisel/src/test/scala/linxcore/ooo/OooRobBrobPcCoordinatorSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooRobBrobPcCoordinatorSpec.scala deleted file mode 100644 index aa899a1d..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooRobBrobPcCoordinatorSpec.scala +++ /dev/null @@ -1,707 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooRobBrobPcCoordinatorSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooRobBrobPcCoordinator): Unit = { - dut.io.reserve.valid.poke(false.B) - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.publishEligible.foreach(_.poke(true.B)) - dut.io.memoryOrder.poke(0.U.asTypeOf(dut.io.memoryOrder)) - dut.io.publishPermit.poke(false.B) - dut.io.completion.valid.poke(false.B) - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.commit.ready.poke(false.B) - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryRequest.bits.poke( - 0.U.asTypeOf(dut.io.recoveryRequest.bits)) - dut.io.recoveryApply.poke(false.B) - dut.io.recoveryAbort.poke(false.B) - dut.io.pcReadTokens.foreach(_.poke(0.U.asTypeOf(dut.io.pcReadTokens.head))) - } - - private def pokeTransaction( - dut: OooRobBrobPcCoordinator, - stid: Int, - transactionId: Int, - firstRid: Int, - tailEpoch: Int, - pcs: Seq[Long], - starts: Set[Int], - stops: Set[Int], - releases: Set[Int], - peId: Int = 3, - epoch: Int = 5): Unit = { - dut.io.reserve.bits.poke(0.U.asTypeOf(dut.io.reserve.bits)) - val transaction = dut.io.reserve.bits - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(epoch.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.groupCount.poke(pcs.size.U) - transaction.plan.virtualTailEpoch.poke(tailEpoch.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(peId.U) - transaction.plan.firstVirtualGroup.stid.poke(stid.U) - transaction.plan.firstVirtualGroup.ridSlot.poke( - (firstRid % dut.p.robGroupsPerStid).U) - transaction.plan.firstVirtualGroup.ridGeneration.poke( - (firstRid / dut.p.robGroupsPerStid).U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(epoch.U) - transaction.decoded.uopMask.poke(((1 << pcs.size) - 1).U) - transaction.groupMask.poke(((1 << pcs.size) - 1).U) - - pcs.zipWithIndex.foreach { case (pc, index) => - val absoluteRid = firstRid + index - val group = transaction.groups(index) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((absoluteRid % dut.p.robGroupsPerStid).U) - group.key.ridGeneration.poke((absoluteRid / dut.p.robGroupsPerStid).U) - group.logicalUopMask.poke((1 << index).U) - group.physicalMemberCount.poke(1.U) - group.architecturalParentCount.poke(1.U) - group.boundaryStart.poke(starts(index).B) - group.boundaryStop.poke(stops(index).B) - group.releasePcBase.poke(releases(index).B) - transaction.uopGroupIndex(index).poke(index.U) - transaction.uopMemberBase(index).poke(0.U) - - val uop = transaction.decoded.uops(index) - uop.valid.poke(true.B) - uop.plannedChildCount.poke(1.U) - uop.recipe.valid.poke(true.B) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(peId.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke((100 + absoluteRid).U) - uop.identity.parents(0).key.epoch.poke(epoch.U) - uop.identity.parents(0).pc.poke(pc.U) - } - dut.io.reserve.valid.poke(true.B) - } - - private def reserve(dut: OooRobBrobPcCoordinator): Unit = { - dut.io.reserve.ready.expect(true.B) - dut.clock.step() - dut.io.reserve.valid.poke(false.B) - } - - private def complete( - dut: OooRobBrobPcCoordinator, - stid: Int, - absoluteRid: Int, - bid: Int, - brobGeneration: Int, - residentGeneration: Int, - peId: Int = 3): Unit = { - val key = dut.io.completion.bits.key - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - key.group.valid.poke(true.B) - key.group.peId.poke(peId.U) - key.group.stid.poke(stid.U) - key.group.ridSlot.poke((absoluteRid % dut.p.robGroupsPerStid).U) - key.group.ridGeneration.poke((absoluteRid / dut.p.robGroupsPerStid).U) - key.bid.valid.poke(true.B) - key.bid.value.poke(bid.U) - key.brobGeneration.poke(brobGeneration.U) - key.memberIndex.poke(0.U) - key.residentGeneration.poke(residentGeneration.U) - dut.io.completion.valid.poke(true.B) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - } - - private def pokeRecovery( - dut: OooRobBrobPcCoordinator, - stid: Int, - absoluteRid: Int, - bid: Int, - brobGeneration: Int, - residentGeneration: Int, - transactionId: Int, - epoch: Int, - killTrigger: Boolean = false, - triggerMemberCount: Int = 1, - peId: Int = 3): Unit = { - val request = dut.io.recoveryRequest.bits - request.poke(0.U.asTypeOf(request)) - request.rename.key.member.group.valid.poke(true.B) - request.rename.key.member.group.peId.poke(peId.U) - request.rename.key.member.group.stid.poke(stid.U) - request.rename.key.member.group.ridSlot.poke( - (absoluteRid % dut.p.robGroupsPerStid).U) - request.rename.key.member.group.ridGeneration.poke( - (absoluteRid / dut.p.robGroupsPerStid).U) - request.rename.key.member.bid.valid.poke(true.B) - request.rename.key.member.bid.value.poke(bid.U) - request.rename.key.member.brobGeneration.poke(brobGeneration.U) - request.rename.key.member.memberIndex.poke(0.U) - request.rename.key.member.residentGeneration.poke( - residentGeneration.U) - request.rename.key.transactionId.poke(transactionId.U) - request.rename.key.epoch.poke(epoch.U) - request.rename.killTrigger.poke(killTrigger.B) - request.triggerMemberCount.poke(triggerMemberCount.U) - dut.io.recoveryRequest.valid.poke(true.B) - } - - private def waitRecoveryPrepared( - dut: OooRobBrobPcCoordinator, - maxCycles: Int = 64): Unit = { - var cycles = 0 - while (!dut.io.recoveryPreparedValid.peek().litToBoolean && - cycles < maxCycles) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.recoveryPreparedValid.peek().litToBoolean, - s"physical recovery did not prepare within $maxCycles cycles") - } - - private def waitRobRecoveryRejected( - dut: OooRobBrobPcCoordinator, - maxCycles: Int = 64): Unit = { - var cycles = 0 - while (!dut.io.robRecoveryRejected.valid.peek().litToBoolean && - cycles < maxCycles) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.robRecoveryRejected.valid.peek().litToBoolean, - s"ROB recovery did not reject within $maxCycles cycles") - } - - private def waitForCommit( - dut: OooRobBrobPcCoordinator, - maxCycles: Int = 32): Unit = { - var cycles = 0 - while (!dut.io.commit.valid.peek().litToBoolean && cycles < maxCycles) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.commit.valid.peek().litToBoolean, - s"coordinated commit did not become valid within $maxCycles cycles") - } - - private def waitForNonFlushPrefix( - dut: OooRobBrobPcCoordinator, - stid: Int, - expected: Int, - maxCycles: Int = 64): Unit = { - var cycles = 0 - while (dut.io.nonFlushWindows(stid).prefixCount.peek().litValue != expected && - cycles < maxCycles) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.nonFlushWindows(stid).prefixCount.peek().litValue == expected, - s"STID $stid non-flush prefix did not reach $expected within $maxCycles cycles") - } - - test("publishes and retires D3 ROB BROB and PC state on common terminal fires") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8, - pcBufferEntries = 64) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - pokeTransaction(dut, stid = 1, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(100, 106), starts = Set(0), stops = Set(1), - releases = Set(1)) - reserve(dut) - - dut.io.preparedValid.expect(true.B) - dut.io.prepared.request.bindings(0).brob.bid.value.expect(0.U) - dut.io.prepared.request.bindings(1).brob.bid.value.expect(0.U) - dut.io.prepared.request.bindings(0).residentGeneration.expect(1.U) - dut.io.prepared.request.bindings(1).residentGeneration.expect(1.U) - dut.io.prepared.parentPcTokens(0)(0).index.expect(16.U) - dut.io.prepared.parentPcTokens(0)(0).byteOffset.expect(0.U) - dut.io.prepared.parentPcTokens(1)(0).byteOffset.expect(6.U) - dut.clock.step(3) - dut.io.d3UsedGroups(1).expect(2.U) - dut.io.d3PublishedGroups(1).expect(0.U) - dut.io.robOccupiedGroups(1).expect(0.U) - dut.io.brobUsedBlocks(1).expect(0.U) - dut.io.pcUsedBases(1).expect(0.U) - - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - dut.io.d3PublishedGroups(1).expect(2.U) - dut.io.robOccupiedGroups(1).expect(2.U) - dut.io.brobUsedBlocks(1).expect(1.U) - dut.io.pcUsedBases(1).expect(1.U) - - dut.io.pcReadTokens(0).valid.poke(true.B) - dut.io.pcReadTokens(0).index.poke(16.U) - dut.io.pcReadTokens(0).byteOffset.poke(6.U) - dut.io.pcReadTokens(0).allocationEpoch.poke(0.U) - dut.io.pcReadValid(0).expect(true.B) - dut.io.pcRead(0).expect(106.U) - - complete(dut, stid = 1, absoluteRid = 1, bid = 0, - brobGeneration = 0, residentGeneration = 1) - complete(dut, stid = 1, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - val retainedRid = dut.io.commit.bits.release.firstGroup.ridSlot.peek().litValue - val retainedEpoch = dut.io.commit.bits.release.headEpoch.peek().litValue - val retainedCount = dut.io.commit.bits.release.groupCount.peek().litValue - dut.clock.step(2) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.firstGroup.ridSlot.expect(retainedRid.U) - dut.io.commit.bits.release.headEpoch.expect(retainedEpoch.U) - dut.io.commit.bits.release.groupCount.expect(retainedCount.U) - - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.d3UsedGroups(1).expect(0.U) - dut.io.d3PublishedGroups(1).expect(0.U) - dut.io.robOccupiedGroups(1).expect(0.U) - dut.io.brobUsedBlocks(1).expect(0.U) - dut.io.pcUsedBases(1).expect(0.U) - dut.io.pcReadValid(0).expect(false.B) - } - } - - test("rejects malformed PC parent mapping without partial owner publication") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - pokeTransaction(dut, stid = 2, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(40, 48), starts = Set(0), stops = Set(1), - releases = Set(1)) - reserve(dut) - // Corrupt the retained D3 packet before reservation is not possible; this - // negative case instead enters D3 with a malformed inverse mapping that - // only the PC owner is responsible for validating. - // Re-create it through a fresh provisional transaction after cancellation. - dut.io.cancel(2).poke(true.B) - dut.clock.step() - dut.io.cancel(2).poke(false.B) - - pokeTransaction(dut, stid = 2, transactionId = 1, firstRid = 0, - tailEpoch = 2, pcs = Seq(40, 48), starts = Set(0), stops = Set(1), - releases = Set(1)) - dut.io.reserve.bits.uopGroupIndex(1).poke(0.U) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.preparedValid.expect(false.B) - dut.io.publishFire.expect(false.B) - dut.io.pcPrepareRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.d3UsedGroups(2).expect(2.U) - dut.io.d3PublishedGroups(2).expect(0.U) - dut.io.robOccupiedGroups(2).expect(0.U) - dut.io.brobUsedBlocks(2).expect(0.U) - dut.io.pcUsedBases(2).expect(0.U) - - dut.io.cancel(2).poke(true.B) - dut.clock.step() - dut.io.cancel(2).poke(false.B) - dut.io.d3UsedGroups(2).expect(0.U) - } - } - - test("commits one STID while publishing another STID in the same cycle") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - pokeTransaction(dut, stid = 0, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(64), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - complete(dut, stid = 0, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - - pokeTransaction(dut, stid = 1, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(128), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.commit.ready.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.io.commit.valid.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - dut.io.commit.ready.poke(false.B) - - dut.io.robOccupiedGroups(0).expect(0.U) - dut.io.brobUsedBlocks(0).expect(0.U) - dut.io.pcUsedBases(0).expect(0.U) - dut.io.robOccupiedGroups(1).expect(1.U) - dut.io.brobUsedBlocks(1).expect(1.U) - dut.io.pcUsedBases(1).expect(1.U) - } - } - - test("elaborates coordinated publication at decode widths 2 4 and 6") { - Seq(2, 4, 6).foreach { width => - val p = OooParams( - instructionDecodeWidth = width, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - pokeTransaction(dut, stid = 3, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(256), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.preparedValid.expect(true.B) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.robOccupiedGroups(3).expect(1.U) - } - } - } - - test("bridges exact typed non-flush evidence without mutating commit owners") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - pokeTransaction(dut, stid = 2, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(512), starts = Set(0), - stops = Set(0), releases = Set(0)) - val recipe = dut.io.reserve.bits.decoded.uops(0).recipe - recipe.mayTrap.poke(true.B) - recipe.mayTrapLate.poke(true.B) - recipe.memoryRequestCount.poke(1.U) - recipe.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - recipe.dispatchClass.poke(OooDispatchClass.Agu.U) - reserve(dut) - - dut.io.preparedValid.expect(true.B) - val bid = dut.io.prepared.request.bindings(0).brob.bid.value.peek().litValue - val brobGeneration = - dut.io.prepared.request.bindings(0).brob.generation.peek().litValue - val residentGeneration = - dut.io.prepared.request.bindings(0).residentGeneration.peek().litValue - dut.io.publishPermit.poke(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - dut.clock.step() - dut.io.nonFlushWindows(2).valid.expect(true.B) - dut.io.nonFlushWindows(2).prefixCount.expect(0.U) - - val evidence = dut.io.nonFlushEvidence.bits - evidence.poke(0.U.asTypeOf(evidence)) - evidence.key.group.valid.poke(true.B) - evidence.key.group.peId.poke(3.U) - evidence.key.group.stid.poke(2.U) - evidence.key.group.ridSlot.poke(0.U) - evidence.key.group.ridGeneration.poke(0.U) - evidence.key.bid.valid.poke(true.B) - evidence.key.bid.value.poke(bid.U) - evidence.key.brobGeneration.poke(brobGeneration.U) - evidence.key.memberIndex.poke(0.U) - evidence.key.residentGeneration.poke(residentGeneration.U) - evidence.proofs.poke((OooNonFlushProof.ExceptionSafeMask | - OooNonFlushProof.MemorySafeMask | - OooNonFlushProof.ControlSafeMask).U) - dut.io.nonFlushEvidence.valid.poke(true.B) - dut.io.nonFlushEvidence.ready.expect(true.B) - dut.io.nonFlushEvidenceRejected.valid.expect(false.B) - dut.clock.step() - dut.io.nonFlushEvidence.valid.poke(false.B) - waitForNonFlushPrefix(dut, stid = 2, expected = 1) - - dut.io.nonFlushWindows(2).head.ridSlot.expect(0.U) - dut.io.nonFlushWindows(2).prefixCount.expect(1.U) - dut.io.robOccupiedGroups(2).expect(1.U) - dut.io.commit.valid.expect(false.B) - } - } - - test("retains one exact ROB D3 BROB PC recovery plan until common apply") { - val p = OooParams( - instructionDecodeWidth = 2, - robGroupsPerStid = 8, - brobEntriesPerStid = 8, - pcBufferEntries = 32) - simulate(new OooRobBrobPcCoordinator(p)) { dut => - clear(dut) - - // Two independently closed groups force two native blocks and two PC - // bases, so the common recovery must mutate every physical owner. - pokeTransaction(dut, stid = 1, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(100, 300), starts = Set(0, 1), - stops = Set(0, 1), releases = Set(0, 1)) - reserve(dut) - dut.io.preparedValid.expect(true.B) - val killedPcIndex = dut.io.prepared.request.bindings(1).pcBase.index - .peek().litValue - val killedPcEpoch = dut.io.prepared.request.bindings(1).pcBase - .allocationEpoch.peek().litValue - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - - // An unrelated STID remains live through both prepare and apply. - pokeTransaction(dut, stid = 2, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(700), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - - dut.io.robOccupiedGroups(1).expect(2.U) - dut.io.d3PublishedGroups(1).expect(2.U) - dut.io.brobUsedBlocks(1).expect(2.U) - dut.io.pcUsedBases(1).expect(2.U) - dut.io.robOccupiedGroups(2).expect(1.U) - - pokeRecovery(dut, stid = 1, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1, - transactionId = 0, epoch = 5) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - dut.io.recoveryBusy.expect(true.B) - waitRecoveryPrepared(dut) - - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.recoveryPrepared.oldOccupied.expect(2.U) - dut.io.recoveryPrepared.newOccupied.expect(1.U) - dut.io.recoveryPrepared.killedGroupCount.expect(1.U) - dut.io.recoveryPrepared.survivingPivotValid.expect(true.B) - - dut.io.pcReadTokens(0).valid.poke(true.B) - dut.io.pcReadTokens(0).index.poke(killedPcIndex.U) - dut.io.pcReadTokens(0).byteOffset.poke(0.U) - dut.io.pcReadTokens(0).allocationEpoch.poke(killedPcEpoch.U) - dut.io.pcReadValid(0).expect(true.B) - - // Arbitrary global-owner backpressure cannot let any lower owner apply. - dut.clock.step(3) - dut.io.recoveryPreparedValid.expect(true.B) - dut.io.robOccupiedGroups(1).expect(2.U) - dut.io.d3PublishedGroups(1).expect(2.U) - dut.io.brobUsedBlocks(1).expect(2.U) - dut.io.pcUsedBases(1).expect(2.U) - - // A composed-owner reject can abort this side-effect-free lower plan. - dut.io.recoveryAbort.poke(true.B) - dut.clock.step() - dut.io.recoveryAbort.poke(false.B) - dut.io.recoveryBusy.expect(false.B) - dut.io.robOccupiedGroups(1).expect(2.U) - dut.io.d3PublishedGroups(1).expect(2.U) - dut.io.brobUsedBlocks(1).expect(2.U) - dut.io.pcUsedBases(1).expect(2.U) - - pokeRecovery(dut, stid = 1, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1, - transactionId = 0, epoch = 5) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - waitRecoveryPrepared(dut) - - dut.io.recoveryApply.poke(true.B) - dut.io.recoveryApplied.valid.expect(true.B) - dut.io.recoveryApplied.bits.rename.key.member.group.stid.expect(1.U) - dut.clock.step() - dut.io.recoveryApply.poke(false.B) - dut.io.recoveryBusy.expect(false.B) - dut.io.robOccupiedGroups(1).expect(1.U) - dut.io.d3PublishedGroups(1).expect(1.U) - dut.io.brobUsedBlocks(1).expect(1.U) - dut.io.pcUsedBases(1).expect(1.U) - dut.io.pcReadValid(0).expect(false.B) - dut.io.robOccupiedGroups(2).expect(1.U) - dut.io.d3PublishedGroups(2).expect(1.U) - dut.io.brobUsedBlocks(2).expect(1.U) - dut.io.pcUsedBases(2).expect(1.U) - - // A younger D3 row that has already exposed valid must publish before - // recovery capture; the request remains stable and then kills that row. - pokeTransaction(dut, stid = 1, transactionId = 1, firstRid = 1, - tailEpoch = 2, pcs = Seq(500), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.preparedValid.expect(true.B) - pokeRecovery(dut, stid = 1, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1, - transactionId = 0, epoch = 5) - dut.io.recoveryRequest.ready.expect(false.B) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - waitRecoveryPrepared(dut) - dut.io.recoveryPrepared.newOccupied.expect(1.U) - dut.io.recoveryApply.poke(true.B) - dut.io.recoveryApplied.valid.expect(true.B) - dut.clock.step() - dut.io.recoveryApply.poke(false.B) - dut.io.robOccupiedGroups(1).expect(1.U) - dut.io.d3PublishedGroups(1).expect(1.U) - - // A stale exact key is consumed by the ROB authority and cannot create a - // partial D3/BROB/PC mutation. - pokeRecovery(dut, stid = 1, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 0, - transactionId = 0, epoch = 5) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - waitRobRecoveryRejected(dut) - dut.io.d3RecoveryRejected.valid.expect(false.B) - dut.io.brobRecoveryRejected.valid.expect(false.B) - dut.io.pcRecoveryRejected.valid.expect(false.B) - dut.clock.step() - dut.io.recoveryBusy.expect(false.B) - dut.io.robOccupiedGroups(1).expect(1.U) - dut.io.d3PublishedGroups(1).expect(1.U) - dut.io.brobUsedBlocks(1).expect(1.U) - dut.io.pcUsedBases(1).expect(1.U) - - // A retained same-STID commit is another non-retractable Decoupled - // obligation. Recovery capture waits for it to fire, then the now-missing - // exact key is rejected by the ROB without reaching lower owners. - pokeTransaction(dut, stid = 0, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(900), starts = Set(0), stops = Set(0), - releases = Set(0)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - complete(dut, stid = 0, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.firstGroup.stid.expect(0.U) - pokeRecovery(dut, stid = 0, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1, - transactionId = 0, epoch = 5) - dut.io.recoveryRequest.ready.expect(false.B) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - waitRobRecoveryRejected(dut) - dut.io.d3RecoveryRejected.valid.expect(false.B) - dut.io.brobRecoveryRejected.valid.expect(false.B) - dut.io.pcRecoveryRejected.valid.expect(false.B) - dut.clock.step() - dut.io.recoveryBusy.expect(false.B) - dut.io.robOccupiedGroups(0).expect(0.U) - - // Move every physical head forward, fill a complete eight-row window, - // then remove the two rows after RID/BID/PC wrap. The coordinator must - // retain the wrap-qualified old/new tails rather than compare slots. - pokeTransaction(dut, stid = 3, transactionId = 0, firstRid = 0, - tailEpoch = 0, pcs = Seq(1000, 1200), starts = Set(0, 1), - stops = Set(0, 1), releases = Set(0, 1)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - complete(dut, stid = 3, absoluteRid = 1, bid = 1, - brobGeneration = 0, residentGeneration = 1) - complete(dut, stid = 3, absoluteRid = 0, bid = 0, - brobGeneration = 0, residentGeneration = 1) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.robOccupiedGroups(3).expect(0.U) - - Seq( - (1, 2, 2, Seq(1400L, 1600L)), - (2, 4, 3, Seq(1800L, 2000L)), - (3, 6, 4, Seq(2200L, 2400L)), - (4, 8, 5, Seq(2600L, 2800L))).foreach { - case (transactionId, firstRid, tailEpoch, pcs) => - pokeTransaction(dut, stid = 3, transactionId = transactionId, - firstRid = firstRid, tailEpoch = tailEpoch, pcs = pcs, - starts = Set(0, 1), stops = Set(0, 1), releases = Set(0, 1)) - reserve(dut) - dut.io.publishPermit.poke(true.B) - dut.io.publishFire.expect(true.B) - dut.clock.step() - dut.io.publishPermit.poke(false.B) - } - dut.io.robOccupiedGroups(3).expect(8.U) - dut.io.d3PublishedGroups(3).expect(8.U) - dut.io.brobUsedBlocks(3).expect(8.U) - dut.io.pcUsedBases(3).expect(8.U) - - pokeRecovery(dut, stid = 3, absoluteRid = 7, bid = 7, - brobGeneration = 0, residentGeneration = 1, - transactionId = 3, epoch = 5) - dut.io.recoveryRequest.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryRequest.valid.poke(false.B) - waitRecoveryPrepared(dut) - dut.io.recoveryPrepared.oldHead.ridSlot.expect(2.U) - dut.io.recoveryPrepared.oldHead.ridGeneration.expect(0.U) - dut.io.recoveryPrepared.oldOccupied.expect(8.U) - dut.io.recoveryPrepared.newOccupied.expect(6.U) - dut.io.recoveryPrepared.killedGroupCount.expect(2.U) - dut.io.recoveryPrepared.firstKilledGroup.ridSlot.expect(0.U) - dut.io.recoveryPrepared.firstKilledGroup.ridGeneration.expect(1.U) - dut.io.recoveryPrepared.newTail.ridSlot.expect(0.U) - dut.io.recoveryPrepared.newTail.ridGeneration.expect(1.U) - dut.io.recoveryApply.poke(true.B) - dut.io.recoveryApplied.valid.expect(true.B) - dut.clock.step() - dut.io.recoveryApply.poke(false.B) - dut.io.robOccupiedGroups(3).expect(6.U) - dut.io.d3PublishedGroups(3).expect(6.U) - dut.io.brobUsedBlocks(3).expect(6.U) - dut.io.pcUsedBases(3).expect(6.U) - dut.io.robOccupiedGroups(1).expect(1.U) - dut.io.robOccupiedGroups(2).expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitOwnerSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitOwnerSpec.scala deleted file mode 100644 index ef87cf41..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitOwnerSpec.scala +++ /dev/null @@ -1,200 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooRobStoreCommitOwnerSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - storeCommitBufferEntries = 8, - robGroupsPerStid = 8, - brobEntriesPerStid = 8, - pcBufferEntries = 16, - pcBankCount = 4, - pcReadPorts = 4, - pcReadReplicaCount = 2, - pMapQDepthPerStid = 32, - tuRetireSourceDepthPerStid = 32) - - private def clear(dut: OooRobStoreCommitOwner): Unit = { - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitPrepare.bits.poke( - 0.U.asTypeOf(dut.io.commitPrepare.bits)) - dut.io.commitFire.poke(false.B) - dut.io.storeCommit.ready.poke(false.B) - } - - private def pokeState( - state: OooMemoryIdState, - lsid: BigInt, - loadId: BigInt, - storeId: BigInt): Unit = { - state.lsid.poke(lsid.U) - state.loadId.poke(loadId.U) - state.storeId.poke(storeId.U) - } - - private def pokeGroup( - dut: OooRobStoreCommitOwner, - groupIndex: Int, - ridSlot: Int, - ridGeneration: Int, - bid: Int, - brobGeneration: Int, - residentGeneration: Int, - memberCount: Int, - before: (BigInt, BigInt, BigInt), - after: (BigInt, BigInt, BigInt)): Unit = { - val group = dut.io.commitPrepare.bits.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(1.U) - group.key.ridSlot.poke(ridSlot.U) - group.key.ridGeneration.poke(ridGeneration.U) - group.brob.valid.poke(true.B) - group.brob.bid.valid.poke(true.B) - group.brob.bid.value.poke(bid.U) - group.brob.generation.poke(brobGeneration.U) - group.residentGeneration.poke(residentGeneration.U) - group.physicalMemberCount.poke(memberCount.U) - group.completedMembers.poke(((BigInt(1) << memberCount) - 1).U) - group.logicalUopMask.poke(1.U) - group.logicalMemberBase(0).poke(0.U) - group.logicalMemberCount(0).poke(memberCount.U) - group.memoryOrderValid.poke(true.B) - pokeState(group.memoryBefore, before._1, before._2, before._3) - pokeState(group.memoryAfter, after._1, after._2, after._3) - pokeState(group.logicalMemoryAfter(0), after._1, after._2, after._3) - } - - private def pokeScalarPairBatch(dut: OooRobStoreCommitOwner): Unit = { - val batch = dut.io.commitPrepare.bits - batch.poke(0.U.asTypeOf(batch)) - batch.release.firstGroup.valid.poke(true.B) - batch.release.firstGroup.peId.poke(3.U) - batch.release.firstGroup.stid.poke(1.U) - batch.release.firstGroup.ridSlot.poke(6.U) - batch.release.firstGroup.ridGeneration.poke(4.U) - batch.release.groupCount.poke(2.U) - pokeGroup(dut, groupIndex = 0, ridSlot = 6, ridGeneration = 4, - bid = 5, brobGeneration = 2, residentGeneration = 9, - memberCount = 1, - before = (10, 4, 7), after = (11, 4, 8)) - pokeGroup(dut, groupIndex = 1, ridSlot = 7, ridGeneration = 4, - bid = 6, brobGeneration = 2, residentGeneration = 10, - memberCount = 2, - before = (11, 4, 8), after = (13, 4, 10)) - dut.io.commitPrepare.valid.poke(true.B) - } - - test("atomically captures scalar and pair stores then preserves exact beat order") { - simulate(new OooRobStoreCommitOwner(p)) { dut => - clear(dut) - dut.clock.step() - - pokeScalarPairBatch(dut) - dut.io.commitStartReady.expect(true.B) - dut.io.preparedTokenCount.expect(3.U) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - - dut.io.used.expect(3.U) - dut.io.storeCommit.valid.expect(true.B) - dut.io.storeCommit.bits.logicalFirstLsid.expect(10.U) - dut.io.storeCommit.bits.logicalFirstStoreId.expect(7.U) - dut.io.storeCommit.bits.logicalRequestCount.expect(1.U) - dut.io.storeCommit.bits.logicalBeat.expect(0.U) - dut.io.storeCommit.bits.exactOwner.ridSlot.expect(6.U) - - val heldFirstLsid = - dut.io.storeCommit.bits.logicalFirstLsid.peek().litValue - val heldFirstStoreId = - dut.io.storeCommit.bits.logicalFirstStoreId.peek().litValue - val heldOwner = - dut.io.storeCommit.bits.exactOwner.nativeBid.peek().litValue - dut.clock.step(2) - assert(dut.io.storeCommit.bits.logicalFirstLsid.peek().litValue == - heldFirstLsid) - assert(dut.io.storeCommit.bits.logicalFirstStoreId.peek().litValue == - heldFirstStoreId) - assert(dut.io.storeCommit.bits.exactOwner.nativeBid.peek().litValue == - heldOwner) - - dut.io.storeCommit.ready.poke(true.B) - dut.clock.step() - dut.io.storeCommit.bits.logicalFirstLsid.expect(11.U) - dut.io.storeCommit.bits.logicalFirstStoreId.expect(8.U) - dut.io.storeCommit.bits.logicalRequestCount.expect(2.U) - dut.io.storeCommit.bits.logicalBeat.expect(0.U) - dut.io.storeCommit.bits.exactOwner.ridSlot.expect(7.U) - dut.clock.step() - dut.io.storeCommit.bits.logicalBeat.expect(1.U) - dut.io.storeCommit.bits.logicalFirstLsid.expect(11.U) - dut.clock.step() - dut.io.storeCommit.valid.expect(false.B) - dut.io.used.expect(0.U) - } - } - - test("rejects a broken cross-group memory chain without mutating the token buffer") { - simulate(new OooRobStoreCommitOwner(p)) { dut => - clear(dut) - dut.clock.step() - pokeScalarPairBatch(dut) - pokeState(dut.io.commitPrepare.bits.groups(1).memoryBefore, - lsid = 12, loadId = 4, storeId = 8) - - dut.io.commitStartReady.expect(false.B) - dut.io.commitRejected.valid.expect(true.B) - dut.io.used.expect(0.U) - dut.clock.step(2) - dut.io.storeCommit.valid.expect(false.B) - } - } - - test("reconstructs a two-beat store across full-serial wrap") { - val wrapP = p.copy(lsidWidth = 32) - simulate(new OooRobStoreCommitOwner(wrapP)) { dut => - clear(dut) - dut.clock.step() - val batch = dut.io.commitPrepare.bits - batch.poke(0.U.asTypeOf(batch)) - batch.release.firstGroup.valid.poke(true.B) - batch.release.firstGroup.peId.poke(3.U) - batch.release.firstGroup.stid.poke(1.U) - batch.release.firstGroup.ridSlot.poke(0.U) - batch.release.firstGroup.ridGeneration.poke(5.U) - batch.release.groupCount.poke(1.U) - val maxMinusOne = (BigInt(1) << 32) - 1 - pokeGroup(dut, groupIndex = 0, ridSlot = 0, ridGeneration = 5, - bid = 7, brobGeneration = 3, residentGeneration = 11, - memberCount = 2, - before = (maxMinusOne, 2, maxMinusOne), - after = (1, 2, 1)) - dut.io.commitPrepare.valid.poke(true.B) - dut.io.commitStartReady.expect(true.B) - dut.io.preparedTokenCount.expect(2.U) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.storeCommit.ready.poke(true.B) - dut.io.storeCommit.bits.logicalFirstLsid.expect(maxMinusOne.U) - dut.io.storeCommit.bits.logicalRequestCount.expect(2.U) - dut.io.storeCommit.bits.logicalBeat.expect(0.U) - dut.clock.step() - dut.io.storeCommit.bits.logicalBeat.expect(1.U) - dut.clock.step() - dut.io.storeCommit.valid.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitStqIntegrationSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitStqIntegrationSpec.scala deleted file mode 100644 index a5902e34..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooRobStoreCommitStqIntegrationSpec.scala +++ /dev/null @@ -1,272 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import chisel3.util.Valid -import linxcore.lsu._ -import org.scalatest.funsuite.AnyFunSuite - -private class OooRobStoreCommitStqHarnessIO(val p: OooParams) - extends Bundle { - val commitPrepare = Flipped(Valid(new OooRobCommitBatch(p))) - val commitStartReady = Output(Bool()) - val commitFire = Input(Bool()) - val insertValid = Input(Bool()) - val insert = Input(new STQStoreRequest( - p.robGroupsPerStid, lsidWidth = p.lsidWidth, - peIdWidth = p.peIdWidth, stidWidth = p.stidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - physicalStqEntries = 4)) - val insertReady = Output(Bool()) - val insertIndex = Output(UInt(2.W)) - val issueEnable = Input(Bool()) - val storeTokenAccepted = Output(Bool()) - val storeTokenUsed = Output(UInt(p.storeCommitBufferCountWidth.W)) - val commitQueueCount = Output(UInt(3.W)) - val stqCommitMask = Output(UInt(4.W)) - val scbAcceptedMask = Output(UInt(4.W)) - val logicalCompletionCount = Output(UInt(2.W)) -} - -private class OooRobStoreCommitStqHarness(val p: OooParams) extends Module { - val io = IO(new OooRobStoreCommitStqHarnessIO(p)) - - val owner = Module(new OooRobStoreCommitOwner(p)) - val path = Module(new STQSCBCommitPath( - entries = 4, - queueEntries = 4, - issueWidth = 2, - scbEntries = 4, - scbResponseBufferDepth = 2, - robEntries = p.robGroupsPerStid, - peIdWidth = p.peIdWidth, - stidWidth = p.stidWidth, - lsidWidth = p.lsidWidth, - nativeBidWidth = p.nativeBidWidth, - ridGenerationWidth = p.ridGenerationWidth, - brobGenerationWidth = p.brobGenerationWidth, - memberIndexWidth = p.robMemberIndexWidth, - residentGenerationWidth = p.residentGenerationWidth, - leaseGenerationWidth = p.executeSlotGenerationWidth)) - - owner.io.commitPrepare <> io.commitPrepare - owner.io.commitFire := io.commitFire - path.io.robStoreCommit <> owner.io.storeCommit - - path.io.flush := 0.U.asTypeOf(path.io.flush) - path.io.insertValid := io.insertValid - path.io.insert := io.insert - path.io.markCommitValid := false.B - path.io.markCommitIndex := 0.U - path.io.issueEnable := io.issueEnable - path.io.evictEnable := false.B - path.io.dcacheReady := true.B - path.io.dcacheWriteHit := false.B - path.io.dcacheTagHit := false.B - path.io.l2RequestReady := true.B - path.io.rawRespValid := false.B - path.io.rawRespTxnId := 0.U - path.io.rawRespWrite := false.B - path.io.rawRespUpgrade := false.B - path.io.serializedRequest.ready := false.B - path.io.serializedResponse.valid := false.B - path.io.serializedResponse.bits := 0.U.asTypeOf( - path.io.serializedResponse.bits) - - // This harness models the translation/PMA result as a one-entry retained - // adapter. Classification follows physical allocation and carries the - // exact lease generation plus semantic owner; commit never guesses a memory - // class from the opcode or address. - val classifyPending = RegInit(false.B) - val classifyIndex = Reg(UInt(2.W)) - val classifyGeneration = Reg(UInt(p.executeSlotGenerationWidth.W)) - val classifyOwner = Reg(chiselTypeOf(io.insert.exactOwner)) - val classifyBeat = Reg(UInt(1.W)) - path.io.memoryClassify.valid := classifyPending - path.io.memoryClassify.bits := 0.U.asTypeOf( - path.io.memoryClassify.bits) - path.io.memoryClassify.bits.lease.valid := classifyPending - path.io.memoryClassify.bits.lease.index := classifyIndex - path.io.memoryClassify.bits.lease.generation := classifyGeneration - path.io.memoryClassify.bits.exactOwner := classifyOwner - path.io.memoryClassify.bits.logicalBeat := classifyBeat - path.io.memoryClassify.bits.memoryClass := STQMemoryClass.NormalCacheable - - when(path.io.memoryClassify.fire) { - classifyPending := false.B - } - when(path.io.insertAccepted) { - assert(!classifyPending || path.io.memoryClassify.fire, - "the test PMA adapter must not overwrite an unaccepted classification") - classifyPending := true.B - classifyIndex := path.io.insertIndex - classifyGeneration := - path.io.stqRows(path.io.insertIndex).leaseGeneration + 1.U - classifyOwner := io.insert.exactOwner - classifyBeat := io.insert.logicalBeat - } - - io.commitStartReady := owner.io.commitStartReady - io.insertReady := path.io.insertReady - io.insertIndex := path.io.insertIndex - io.storeTokenAccepted := path.io.robStoreCommitAccepted - io.storeTokenUsed := owner.io.used - io.commitQueueCount := path.io.drainQueueCount - io.stqCommitMask := path.io.stqCommitMask - io.scbAcceptedMask := path.io.scbAcceptedMask - io.logicalCompletionCount := path.io.drainLogicalCompletionCount -} - -class OooRobStoreCommitStqIntegrationSpec - extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - storeCommitBufferEntries = 8, - robGroupsPerStid = 8, - brobEntriesPerStid = 8, - pcBufferEntries = 16, - pcBankCount = 4, - pcReadPorts = 4, - pcReadReplicaCount = 2, - pMapQDepthPerStid = 32, - tuRetireSourceDepthPerStid = 32, - lsidWidth = 40) - - private def pokeOwner( - owner: STQExactOwner, - beatOwner: Boolean = true): Unit = { - owner.valid.poke(beatOwner.B) - owner.peId.poke(3.U) - owner.stid.poke(1.U) - owner.nativeBidValid.poke(true.B) - owner.nativeBid.poke(5.U) - owner.brobGeneration.poke(2.U) - owner.ridSlot.poke(6.U) - owner.ridGeneration.poke(4.U) - owner.memberIndex.poke(0.U) - owner.residentGeneration.poke(9.U) - } - - private def pokeStoreBeat( - dut: OooRobStoreCommitStqHarness, - beat: Int, - addr: BigInt, - data: BigInt): Unit = { - val request = dut.io.insert - request.poke(0.U.asTypeOf(request)) - request.storeType.poke(STQStoreType.All) - request.peId.poke(3.U) - request.stid.poke(1.U) - request.bid.valid.poke(true.B) - request.bid.value.poke(5.U) - request.gid.valid.poke(true.B) - request.gid.value.poke(6.U) - request.rid.valid.poke(true.B) - request.rid.value.poke(6.U) - request.lsId.valid.poke(true.B) - request.lsId.value.poke(((10 + beat) & 7).U) - request.lsIdFull.poke((10 + beat).U) - request.storeIdFullValid.poke(true.B) - request.storeIdFull.poke((20 + beat).U) - request.logicalStoreValid.poke(true.B) - request.logicalFirstLsid.poke(10.U) - request.logicalFirstStoreId.poke(20.U) - request.logicalRequestCount.poke(2.U) - request.logicalBeat.poke(beat.U) - pokeOwner(request.exactOwner) - request.addr.poke(addr.U) - request.data.poke(data.U) - request.size.poke(8.U) - dut.io.insertValid.poke(true.B) - dut.io.insertReady.expect(true.B) - dut.clock.step() - dut.io.insertValid.poke(false.B) - } - - private def pokeCommitBatch(dut: OooRobStoreCommitStqHarness): Unit = { - val batch = dut.io.commitPrepare.bits - batch.poke(0.U.asTypeOf(batch)) - batch.release.firstGroup.valid.poke(true.B) - batch.release.firstGroup.peId.poke(3.U) - batch.release.firstGroup.stid.poke(1.U) - batch.release.firstGroup.ridSlot.poke(6.U) - batch.release.firstGroup.ridGeneration.poke(4.U) - batch.release.groupCount.poke(1.U) - val group = batch.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(1.U) - group.key.ridSlot.poke(6.U) - group.key.ridGeneration.poke(4.U) - group.brob.valid.poke(true.B) - group.brob.bid.valid.poke(true.B) - group.brob.bid.value.poke(5.U) - group.brob.generation.poke(2.U) - group.residentGeneration.poke(9.U) - group.physicalMemberCount.poke(2.U) - group.completedMembers.poke(3.U) - group.logicalUopMask.poke(1.U) - group.logicalMemberBase(0).poke(0.U) - group.logicalMemberCount(0).poke(2.U) - group.memoryOrderValid.poke(true.B) - group.memoryBefore.lsid.poke(10.U) - group.memoryBefore.loadId.poke(0.U) - group.memoryBefore.storeId.poke(20.U) - group.memoryAfter.lsid.poke(12.U) - group.memoryAfter.loadId.poke(0.U) - group.memoryAfter.storeId.poke(22.U) - group.logicalMemoryAfter(0).lsid.poke(12.U) - group.logicalMemoryAfter(0).loadId.poke(0.U) - group.logicalMemoryAfter(0).storeId.poke(22.U) - dut.io.commitPrepare.valid.poke(true.B) - } - - test("ROB pair commit reaches CommitQ and SCB without a physical-index sideband") { - simulate(new OooRobStoreCommitStqHarness(p)) { dut => - dut.io.commitPrepare.valid.poke(false.B) - dut.io.commitPrepare.bits.poke( - 0.U.asTypeOf(dut.io.commitPrepare.bits)) - dut.io.commitFire.poke(false.B) - dut.io.insertValid.poke(false.B) - dut.io.insert.poke(0.U.asTypeOf(dut.io.insert)) - dut.io.issueEnable.poke(false.B) - dut.clock.step() - - pokeStoreBeat(dut, beat = 0, addr = 0x103e, - data = BigInt("1122334455667788", 16)) - pokeStoreBeat(dut, beat = 1, addr = 0x107e, - data = BigInt("99aabbccddeeff00", 16)) - - pokeCommitBatch(dut) - dut.io.commitStartReady.expect(true.B) - dut.io.commitFire.poke(true.B) - dut.clock.step() - dut.io.commitFire.poke(false.B) - dut.io.commitPrepare.valid.poke(false.B) - dut.io.storeTokenUsed.expect(2.U) - - dut.io.storeTokenAccepted.expect(true.B) - dut.clock.step() - dut.io.storeTokenAccepted.expect(true.B) - dut.clock.step() - dut.io.storeTokenUsed.expect(0.U) - dut.io.stqCommitMask.expect("b0011".U) - dut.io.commitQueueCount.expect(2.U) - - dut.io.issueEnable.poke(true.B) - dut.clock.step() - dut.io.scbAcceptedMask.expect("b1111".U) - dut.io.logicalCompletionCount.expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobFaultSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobFaultSpec.scala deleted file mode 100644 index a9848968..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobFaultSpec.scala +++ /dev/null @@ -1,205 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class OooS1GroupedRobFaultSpec extends AnyFunSuite with ChiselSim { - private val p = OooParams( - stidCount = 2, - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - retireGroupWidth = 2, - robGroupsPerStid = 8, - robBankCount = 2, - robRecoveryScanGroupsPerCycle = 2, - robNonFlushScanGroupsPerCycle = 2, - pcBufferEntries = 8, - pcBankCount = 2, - pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, - iqBankCount = 2, - iqEntriesPerBank = 4, - iqFreeSelectLeafEntries = 2, - tuRetireSourceDepthPerStid = 16) - - private def clear(dut: OooS1GroupedRob): Unit = { - dut.io.publish.valid.poke(false.B) - dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) - dut.io.completion.valid.poke(false.B) - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.commit.ready.poke(false.B) - } - - private def pokeOneMemberPublication( - dut: OooS1GroupedRob, - memberCount: Int = 1): Unit = { - val request = dut.io.publish.bits - request.poke(0.U.asTypeOf(request)) - val transaction = request.reservation.transaction - transaction.plan.peId.poke(3.U) - transaction.plan.stid.poke(1.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.transactionId.poke(70.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.uopMask.poke(((1 << memberCount) - 1).U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(3.U) - transaction.plan.firstVirtualGroup.stid.poke(1.U) - transaction.decoded.peId.poke(3.U) - transaction.decoded.stid.poke(1.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(((1 << memberCount) - 1).U) - transaction.groupMask.poke(1.U) - request.reservation.tailAfter.valid.poke(true.B) - request.reservation.tailAfter.peId.poke(3.U) - request.reservation.tailAfter.stid.poke(1.U) - request.reservation.tailAfter.ridSlot.poke(1.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(3.U) - group.key.stid.poke(1.U) - group.logicalUopMask.poke(((1 << memberCount) - 1).U) - group.physicalMemberCount.poke(memberCount.U) - group.architecturalParentCount.poke(memberCount.U) - - for (uopIndex <- 0 until memberCount) { - transaction.uopGroupIndex(uopIndex).poke(0.U) - transaction.uopMemberBase(uopIndex).poke(uopIndex.U) - val uop = transaction.decoded.uops(uopIndex) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) - uop.plannedChildCount.poke(1.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(3.U) - uop.identity.parents(0).key.stid.poke(1.U) - uop.identity.parents(0).key.instructionId.poke((9 + uopIndex).U) - uop.identity.parents(0).key.epoch.poke(7.U) - uop.identity.parents(0).traceOwner.poke(true.B) - } - - val binding = request.bindings(0) - binding.valid.poke(true.B) - binding.brob.valid.poke(true.B) - binding.brob.bid.valid.poke(true.B) - binding.brob.bid.value.poke(5.U) - binding.brob.generation.poke(2.U) - binding.residentGeneration.poke(4.U) - dut.io.publish.valid.poke(true.B) - } - - private def pokeFaultCompletion( - dut: OooS1GroupedRob, - memberIndex: Int = 0): Unit = { - val completion = dut.io.completion.bits - completion.poke(0.U.asTypeOf(completion)) - completion.key.group.valid.poke(true.B) - completion.key.group.peId.poke(3.U) - completion.key.group.stid.poke(1.U) - completion.key.bid.valid.poke(true.B) - completion.key.bid.value.poke(5.U) - completion.key.brobGeneration.poke(2.U) - completion.key.memberIndex.poke(memberIndex.U) - completion.key.residentGeneration.poke(4.U) - completion.faultValid.poke(true.B) - completion.faultCause.poke(13.U) - dut.io.completion.valid.poke(true.B) - } - - test("retains a precise runtime fault on the exact completed member") { - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOneMemberPublication(dut) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - pokeFaultCompletion(dut) - dut.io.completion.ready.expect(true.B) - dut.io.completionRejected.valid.expect(false.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - var cycles = 0 - while (!dut.io.commit.valid.peek().litToBoolean && cycles < 32) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.commit.valid.peek().litToBoolean, - "faulted grouped-ROB row did not become committable") - dut.io.commit.bits.groups(0).completedMembers.expect(1.U) - dut.io.commit.bits.groups(0).faultedMembers.expect(1.U) - dut.io.commit.bits.groups(0).memberFaultCauses(0).expect(13.U) - dut.io.commit.bits.groups(0).preciseTrap.expect(true.B) - } - } - - test("prunes killed runtime fault state from a surviving pivot") { - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - pokeOneMemberPublication(dut, memberCount = 2) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - pokeFaultCompletion(dut, memberIndex = 1) - dut.io.completion.ready.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - val recovery = dut.io.recoveryPrepare.bits - recovery.poke(0.U.asTypeOf(recovery)) - recovery.rename.key.member.group.valid.poke(true.B) - recovery.rename.key.member.group.peId.poke(3.U) - recovery.rename.key.member.group.stid.poke(1.U) - recovery.rename.key.member.bid.valid.poke(true.B) - recovery.rename.key.member.bid.value.poke(5.U) - recovery.rename.key.member.brobGeneration.poke(2.U) - recovery.rename.key.member.residentGeneration.poke(4.U) - recovery.rename.key.transactionId.poke(70.U) - recovery.rename.key.epoch.poke(7.U) - recovery.rename.killTrigger.poke(false.B) - recovery.triggerMemberCount.poke(1.U) - dut.io.recoveryPrepare.valid.poke(true.B) - - var cycles = 0 - while (!dut.io.recoveryPrepareReady.peek().litToBoolean && - !dut.io.recoveryRejected.valid.peek().litToBoolean && cycles < 64) { - dut.clock.step() - cycles += 1 - } - assert(!dut.io.recoveryRejected.valid.peek().litToBoolean, - s"fault-pruning recovery rejected: occupied=${dut.io.recoveryRejected.bits.occupied.peek().litValue} exact=${dut.io.recoveryRejected.bits.exactMatchCount.peek().litValue} shape=${dut.io.recoveryRejected.bits.triggerShapeMatch.peek().litToBoolean}") - assert(dut.io.recoveryPrepareReady.peek().litToBoolean, - "fault-pruning recovery did not prepare") - dut.io.recoveryPrepared.survivingPivotValid.expect(true.B) - dut.io.recoveryPrepared.survivingPivot.physicalMemberCount.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.faultedMembers.expect(0.U) - dut.io.recoveryPrepared.survivingPivot.memberFaultCauses(1).expect(0.U) - dut.io.recoveryPrepared.survivingPivot.preciseTrap.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobSpec.scala deleted file mode 100644 index ad2314ee..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooS1GroupedRobSpec.scala +++ /dev/null @@ -1,1172 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.DestinationKind -import org.scalatest.funsuite.AnyFunSuite - -class OooS1GroupedRobSpec extends AnyFunSuite with ChiselSim { - private def clear(dut: OooS1GroupedRob): Unit = { - dut.io.publish.valid.poke(false.B) - dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) - dut.io.completion.valid.poke(false.B) - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushEvidence.bits.poke(0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - dut.io.interruptPending.foreach(_.poke(false.B)) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.recoveryPrepare.bits.poke( - 0.U.asTypeOf(dut.io.recoveryPrepare.bits)) - dut.io.recoveryFire.poke(false.B) - dut.io.commit.ready.poke(false.B) - } - - private def pokePublication( - dut: OooS1GroupedRob, - stid: Int, - transactionId: Int, - firstSlot: Int, - firstGeneration: Int, - groupMembers: Seq[Int], - groupPMapRows: Seq[Int] = Seq.empty, - initiallyComplete: Set[Int] = Set.empty, - peId: Int = 2, - claimEpoch: Int = 0, - brobBid: Int = 7, - brobGeneration: Int = 3, - residentGeneration: Int = 5): Unit = { - val p = dut.p - dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) - val reservation = dut.io.publish.bits.reservation - val transaction = reservation.transaction - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(11.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.groupCount.poke(groupMembers.size.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(peId.U) - transaction.plan.firstVirtualGroup.stid.poke(stid.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(firstSlot.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(firstGeneration.U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(11.U) - transaction.decoded.uopMask.poke(((1 << groupMembers.size) - 1).U) - transaction.groupMask.poke(((1 << groupMembers.size) - 1).U) - reservation.claimEpoch.poke(claimEpoch.U) - val absoluteTail = firstSlot + groupMembers.size - reservation.tailAfter.valid.poke(true.B) - reservation.tailAfter.peId.poke(peId.U) - reservation.tailAfter.stid.poke(stid.U) - reservation.tailAfter.ridSlot.poke((absoluteTail % p.robGroupsPerStid).U) - reservation.tailAfter.ridGeneration.poke( - (firstGeneration + absoluteTail / p.robGroupsPerStid).U) - - groupMembers.zipWithIndex.foreach { case (memberCount, groupIndex) => - val absoluteSlot = firstSlot + groupIndex - val slot = absoluteSlot % p.robGroupsPerStid - val generation = firstGeneration + absoluteSlot / p.robGroupsPerStid - val group = transaction.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(slot.U) - group.key.ridGeneration.poke(generation.U) - group.logicalUopMask.poke((1 << groupIndex).U) - group.physicalMemberCount.poke(memberCount.U) - group.pMapQRows.poke(groupPMapRows.lift(groupIndex).getOrElse(0).U) - group.architecturalParentCount.poke(1.U) - - val uop = transaction.decoded.uops(groupIndex) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.plannedChildCount.poke(memberCount.U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(peId.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke( - (100 + transactionId * 10 + groupIndex).U) - uop.identity.parents(0).key.epoch.poke(11.U) - uop.identity.parents(0).traceOwner.poke(true.B) - - val binding = dut.io.publish.bits.bindings(groupIndex) - binding.valid.poke(true.B) - binding.brob.valid.poke(true.B) - binding.brob.bid.valid.poke(true.B) - binding.brob.bid.value.poke(brobBid.U) - binding.brob.generation.poke(brobGeneration.U) - binding.residentGeneration.poke(residentGeneration.U) - val initialMask = if (initiallyComplete(groupIndex)) (1 << memberCount) - 1 else 0 - binding.initiallyCompletedMembers.poke(initialMask.U) - } - dut.io.publish.valid.poke(true.B) - } - - private def pokeCompletion( - dut: OooS1GroupedRob, - stid: Int, - slot: Int, - ridGeneration: Int, - member: Int, - peId: Int = 2, - brobBid: Int = 7, - brobGeneration: Int = 3, - residentGeneration: Int = 5): Unit = { - dut.io.completion.bits.poke(0.U.asTypeOf(dut.io.completion.bits)) - val key = dut.io.completion.bits.key - key.group.valid.poke(true.B) - key.group.peId.poke(peId.U) - key.group.stid.poke(stid.U) - key.group.ridSlot.poke(slot.U) - key.group.ridGeneration.poke(ridGeneration.U) - key.bid.valid.poke(true.B) - key.bid.value.poke(brobBid.U) - key.brobGeneration.poke(brobGeneration.U) - key.memberIndex.poke(member.U) - key.residentGeneration.poke(residentGeneration.U) - dut.io.completion.valid.poke(true.B) - } - - private def pokeIntraGroupPublication( - dut: OooS1GroupedRob, - stid: Int = 1, - transactionId: Int = 0, - firstSlot: Int = 0, - firstGeneration: Int = 0, - peId: Int = 2): Unit = { - val p = dut.p - val memberCounts = Seq(1, 2, 1, 1) - val groupIndexes = Seq(0, 0, 1, 2) - val memberBases = Seq(0, 1, 0, 0) - dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) - val reservation = dut.io.publish.bits.reservation - val transaction = reservation.transaction - transaction.plan.peId.poke(peId.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(11.U) - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.groupCount.poke(3.U) - transaction.plan.firstVirtualGroup.valid.poke(true.B) - transaction.plan.firstVirtualGroup.peId.poke(peId.U) - transaction.plan.firstVirtualGroup.stid.poke(stid.U) - transaction.plan.firstVirtualGroup.ridSlot.poke(firstSlot.U) - transaction.plan.firstVirtualGroup.ridGeneration.poke(firstGeneration.U) - transaction.decoded.peId.poke(peId.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(11.U) - transaction.decoded.uopMask.poke(15.U) - transaction.groupMask.poke(7.U) - reservation.tailAfter.valid.poke(true.B) - reservation.tailAfter.peId.poke(peId.U) - reservation.tailAfter.stid.poke(stid.U) - reservation.tailAfter.ridSlot.poke(((firstSlot + 3) % p.robGroupsPerStid).U) - reservation.tailAfter.ridGeneration.poke( - (firstGeneration + (firstSlot + 3) / p.robGroupsPerStid).U) - - val groupMasks = Seq(3, 4, 8) - val physicalCounts = Seq(3, 1, 1) - val pMapRows = Seq(2, 0, 0) - val parentCounts = Seq(2, 1, 1) - val memoryBefore = Seq(0, 2, 3) - val memoryAfter = Seq(2, 3, 4) - for (groupIndex <- 0 until 3) { - val absoluteSlot = firstSlot + groupIndex - val group = transaction.groups(groupIndex) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(peId.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke((absoluteSlot % p.robGroupsPerStid).U) - group.key.ridGeneration.poke( - (firstGeneration + absoluteSlot / p.robGroupsPerStid).U) - group.logicalUopMask.poke(groupMasks(groupIndex).U) - group.physicalMemberCount.poke(physicalCounts(groupIndex).U) - group.pMapQRows.poke(pMapRows(groupIndex).U) - group.architecturalParentCount.poke(parentCounts(groupIndex).U) - - val binding = dut.io.publish.bits.bindings(groupIndex) - binding.valid.poke(true.B) - binding.brob.valid.poke(true.B) - binding.brob.bid.valid.poke(true.B) - binding.brob.bid.value.poke(7.U) - binding.brob.generation.poke(3.U) - binding.residentGeneration.poke(5.U) - binding.memoryOrderValid.poke(true.B) - binding.memoryBefore.lsid.poke(memoryBefore(groupIndex).U) - binding.memoryBefore.storeId.poke(memoryBefore(groupIndex).U) - binding.memoryBefore.youngestStoreLsidValid - .poke((memoryBefore(groupIndex) > 0).B) - binding.memoryBefore.youngestStoreLsid - .poke(math.max(0, memoryBefore(groupIndex) - 1).U) - binding.memoryAfter.lsid.poke(memoryAfter(groupIndex).U) - binding.memoryAfter.storeId.poke(memoryAfter(groupIndex).U) - binding.memoryAfter.youngestStoreLsidValid.poke(true.B) - binding.memoryAfter.youngestStoreLsid - .poke((memoryAfter(groupIndex) - 1).U) - } - - for (uopIndex <- 0 until 4) { - transaction.uopGroupIndex(uopIndex).poke(groupIndexes(uopIndex).U) - transaction.uopMemberBase(uopIndex).poke(memberBases(uopIndex).U) - val uop = transaction.decoded.uops(uopIndex) - uop.valid.poke(true.B) - uop.recipe.valid.poke(true.B) - uop.recipe.disposition.poke(OooOpcodeDisposition.Dispatch.U) - uop.recipe.sideEffectOwner.poke(OooSideEffectOwner.Iex.U) - uop.recipe.dispatchClass.poke(OooDispatchClass.Alu.U) - uop.plannedChildCount.poke(memberCounts(uopIndex).U) - uop.identity.parentCount.poke(1.U) - uop.identity.parents(0).key.valid.poke(true.B) - uop.identity.parents(0).key.peId.poke(peId.U) - uop.identity.parents(0).key.stid.poke(stid.U) - uop.identity.parents(0).key.instructionId.poke((200 + uopIndex).U) - uop.identity.parents(0).key.epoch.poke(11.U) - uop.identity.parents(0).traceOwner.poke(true.B) - if (uopIndex < 2) { - uop.destinations(0).valid.poke(true.B) - uop.destinations(0).kind.poke(DestinationKind.Gpr) - uop.destinations(0).atag.poke((uopIndex + 1).U) - } - val binding = dut.io.publish.bits.bindings(groupIndexes(uopIndex)) - binding.logicalMemoryAfter(uopIndex).lsid.poke((uopIndex + 1).U) - binding.logicalMemoryAfter(uopIndex).storeId.poke((uopIndex + 1).U) - binding.logicalMemoryAfter(uopIndex).youngestStoreLsidValid.poke(true.B) - binding.logicalMemoryAfter(uopIndex).youngestStoreLsid.poke(uopIndex.U) - } - dut.io.publish.valid.poke(true.B) - } - - private def pokeRecovery( - dut: OooS1GroupedRob, - stid: Int, - slot: Int, - ridGeneration: Int, - member: Int, - memberCount: Int, - killTrigger: Boolean, - transactionId: Int = 0, - epoch: Int = 11, - peId: Int = 2): Unit = { - val request = dut.io.recoveryPrepare.bits - request.poke(0.U.asTypeOf(request)) - request.rename.key.member.group.valid.poke(true.B) - request.rename.key.member.group.peId.poke(peId.U) - request.rename.key.member.group.stid.poke(stid.U) - request.rename.key.member.group.ridSlot.poke(slot.U) - request.rename.key.member.group.ridGeneration.poke(ridGeneration.U) - request.rename.key.member.bid.valid.poke(true.B) - request.rename.key.member.bid.value.poke(7.U) - request.rename.key.member.brobGeneration.poke(3.U) - request.rename.key.member.memberIndex.poke(member.U) - request.rename.key.member.residentGeneration.poke(5.U) - request.rename.key.transactionId.poke(transactionId.U) - request.rename.key.epoch.poke(epoch.U) - request.rename.killTrigger.poke(killTrigger.B) - request.triggerMemberCount.poke(memberCount.U) - dut.io.recoveryPrepare.valid.poke(true.B) - } - - private def waitForRecoveryPrepared( - dut: OooS1GroupedRob, - limit: Int = 64): Int = { - var cycles = 0 - while (!dut.io.recoveryPrepareReady.peek().litToBoolean && - !dut.io.recoveryRejected.valid.peek().litToBoolean && - cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(!dut.io.recoveryRejected.valid.peek().litToBoolean, - s"ROB recovery rejected after $cycles scan cycles") - assert(dut.io.recoveryPrepareReady.peek().litToBoolean, - s"ROB recovery did not prepare within $limit cycles") - dut.io.recoveryPrepared.valid.expect(true.B) - cycles - } - - private def waitForRecoveryRejected( - dut: OooS1GroupedRob, - limit: Int = 64): Int = { - var cycles = 0 - while (!dut.io.recoveryRejected.valid.peek().litToBoolean && - cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.recoveryRejected.valid.peek().litToBoolean, - s"ROB recovery did not reject within $limit cycles") - cycles - } - - private def waitForCommit( - dut: OooS1GroupedRob, - limit: Int = 32): Int = { - var cycles = 0 - while (!dut.io.commit.valid.peek().litToBoolean && cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.commit.valid.peek().litToBoolean, - s"grouped-ROB commit did not become valid within $limit cycles") - cycles - } - - private def waitForNonFlushPrefix( - dut: OooS1GroupedRob, - stid: Int, - expected: Int, - limit: Int = 64): Int = { - var cycles = 0 - while (dut.io.nonFlushWindows(stid).prefixCount.peek().litValue != expected && - cycles < limit) { - dut.clock.step() - cycles += 1 - } - assert(dut.io.nonFlushWindows(stid).prefixCount.peek().litValue == expected, - s"STID $stid non-flush prefix did not reach $expected within $limit cycles") - cycles - } - - private def acceptCommit(dut: OooS1GroupedRob): Unit = { - waitForCommit(dut) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - } - - private def acceptCompletion(dut: OooS1GroupedRob): Unit = { - dut.io.completion.ready.expect(true.B) - dut.io.completionRejected.valid.expect(false.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - } - - private def pokeNonFlushEvidence( - dut: OooS1GroupedRob, - stid: Int, - slot: Int, - ridGeneration: Int, - proofs: Int, - member: Int = 0, - peId: Int = 2, - brobBid: Int = 7, - brobGeneration: Int = 3, - residentGeneration: Int = 5): Unit = { - dut.io.nonFlushEvidence.bits.poke( - 0.U.asTypeOf(dut.io.nonFlushEvidence.bits)) - val evidence = dut.io.nonFlushEvidence.bits - evidence.key.group.valid.poke(true.B) - evidence.key.group.peId.poke(peId.U) - evidence.key.group.stid.poke(stid.U) - evidence.key.group.ridSlot.poke(slot.U) - evidence.key.group.ridGeneration.poke(ridGeneration.U) - evidence.key.bid.valid.poke(true.B) - evidence.key.bid.value.poke(brobBid.U) - evidence.key.brobGeneration.poke(brobGeneration.U) - evidence.key.memberIndex.poke(member.U) - evidence.key.residentGeneration.poke(residentGeneration.U) - evidence.proofs.poke(proofs.U) - dut.io.nonFlushEvidence.valid.poke(true.B) - } - - private def acceptNonFlushEvidence(dut: OooS1GroupedRob): Unit = { - dut.io.nonFlushEvidence.ready.expect(true.B) - dut.io.nonFlushEvidenceRejected.valid.expect(false.B) - dut.clock.step() - dut.io.nonFlushEvidence.valid.poke(false.B) - } - - test("admits parentless template continuations but requires the final parent") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication( - dut, - stid = 1, - transactionId = 90, - firstSlot = 0, - firstGeneration = 0, - groupMembers = Seq(1), - initiallyComplete = Set(0)) - val transaction = dut.io.publish.bits.reservation.transaction - val group = transaction.groups(0) - val uop = transaction.decoded.uops(0) - group.architecturalParentCount.poke(0.U) - uop.identity.parents(0).traceOwner.poke(false.B) - uop.identity.templateValid.poke(true.B) - uop.identity.key.uopOrdinal.poke(0.U) - uop.identity.key.uopCount.poke(4.U) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.groups(0).architecturalParentCount.expect(0.U) - - pokePublication( - dut, - stid = 2, - transactionId = 91, - firstSlot = 0, - firstGeneration = 0, - groupMembers = Seq(1)) - val finalTransaction = dut.io.publish.bits.reservation.transaction - val finalGroup = finalTransaction.groups(0) - val finalUop = finalTransaction.decoded.uops(0) - finalGroup.architecturalParentCount.poke(0.U) - finalUop.identity.parents(0).traceOwner.poke(false.B) - finalUop.identity.templateValid.poke(true.B) - finalUop.identity.key.uopOrdinal.poke(3.U) - finalUop.identity.key.uopCount.poke(4.U) - dut.io.publish.ready.expect(false.B) - } - } - - test("publishes every group atomically and retains an older-first commit batch") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(2, 1), - groupPMapRows = Seq(2, 1)) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(2.U) - - pokeCompletion(dut, stid = 1, slot = 1, ridGeneration = 0, member = 0) - acceptCompletion(dut) - dut.clock.step() - dut.io.commit.valid.expect(false.B) - - pokeCompletion(dut, stid = 1, slot = 0, ridGeneration = 0, member = 0) - acceptCompletion(dut) - pokeCompletion(dut, stid = 1, slot = 0, ridGeneration = 0, member = 1) - acceptCompletion(dut) - dut.io.commit.valid.expect(false.B) - dut.clock.step() // retain the selected STID, head token, and group count - dut.io.commit.valid.expect(false.B) - dut.clock.step() // read the banked payload into the retained commit row - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.firstGroup.stid.expect(1.U) - dut.io.commit.bits.release.firstGroup.ridSlot.expect(0.U) - dut.io.commit.bits.groups(0).pMapQRows.expect(2.U) - dut.io.commit.bits.groups(1).pMapQRows.expect(1.U) - dut.io.commit.bits.release.groupCount.expect(2.U) - dut.io.commit.bits.groups(0).physicalMemberCount.expect(2.U) - dut.io.commit.bits.groups(1).physicalMemberCount.expect(1.U) - val heldTransaction = dut.io.commit.bits.groups(0).transactionId.peek().litValue - val heldCount = dut.io.commit.bits.release.groupCount.peek().litValue - dut.clock.step(2) - dut.io.commit.bits.groups(0).transactionId.expect(heldTransaction.U) - dut.io.commit.bits.release.groupCount.expect(heldCount.U) - - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.commit.valid.expect(false.B) - dut.io.occupiedGroups(1).expect(0.U) - dut.io.headSlot(1).expect(2.U) - dut.io.headEpoch(1).expect(1.U) - } - } - - test("fences same-STID recovery while the retained head token reads its payload") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1), - initiallyComplete = Set(0)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - dut.clock.step() // retain the selected STID/head token - dut.io.commit.valid.expect(false.B) - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = false) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(false.B) - - dut.clock.step() // read the selected bank payload - dut.io.commit.valid.expect(true.B) - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.recoveryRejected.valid.expect(false.B) - val heldTransaction = - dut.io.commit.bits.groups(0).transactionId.peek().litValue - val heldRid = - dut.io.commit.bits.groups(0).key.ridSlot.peek().litValue - val heldMembers = - dut.io.commit.bits.groups(0).physicalMemberCount.peek().litValue - dut.clock.step() - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.groups(0).transactionId.expect(heldTransaction.U) - dut.io.commit.bits.groups(0).key.ridSlot.expect(heldRid.U) - dut.io.commit.bits.groups(0).physicalMemberCount.expect(heldMembers.U) - dut.io.recoveryPrepareReady.expect(false.B) - - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.occupiedGroups(1).expect(0.U) - waitForRecoveryRejected(dut) - dut.io.recoveryPrepared.valid.expect(false.B) - } - } - - test("consumes stale and duplicate completions without mutating the live row") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 0, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(2)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 1, member = 0) - dut.io.completionRejected.valid.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 0, - brobGeneration = 4) - dut.io.completionRejected.valid.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 2) - dut.io.completionRejected.valid.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 0) - acceptCompletion(dut) - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 0) - dut.io.completionRejected.valid.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - dut.clock.step() - dut.io.commit.valid.expect(false.B) - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 1) - acceptCompletion(dut) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.groupCount.expect(1.U) - } - } - - test("rejects a colliding multi-group publication without partial slot writes") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 2, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.clock.step() - - pokePublication(dut, stid = 2, transactionId = 1, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1, 1)) - dut.io.publish.ready.expect(false.B) - dut.io.publicationRejected.valid.expect(true.B) - dut.clock.step() - dut.io.occupiedGroups(2).expect(1.U) - - pokePublication(dut, stid = 2, transactionId = 1, firstSlot = 1, - firstGeneration = 0, groupMembers = Seq(1)) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(2).expect(2.U) - } - } - - test("rejects a publication ahead of the live tail and an invalid BROB binding") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 2, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.clock.step() - - pokePublication(dut, stid = 2, transactionId = 1, firstSlot = 2, - firstGeneration = 0, groupMembers = Seq(1)) - dut.io.publish.ready.expect(false.B) - dut.io.publicationRejected.valid.expect(true.B) - dut.clock.step() - dut.io.occupiedGroups(2).expect(1.U) - - pokePublication(dut, stid = 2, transactionId = 1, firstSlot = 1, - firstGeneration = 0, groupMembers = Seq(1)) - dut.io.publish.bits.bindings(0).brob.valid.poke(false.B) - dut.io.publish.ready.expect(false.B) - dut.clock.step() - dut.io.occupiedGroups(2).expect(1.U) - - pokePublication(dut, stid = 2, transactionId = 1, firstSlot = 1, - firstGeneration = 0, groupMembers = Seq(1)) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(2).expect(2.U) - } - } - - test("keeps STIDs isolated and advances an exact wrapped head generation") { - val p = OooParams(robGroupsPerStid = 8, retireGroupWidth = 4) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(4)(1), - initiallyComplete = Set(0, 1, 2, 3)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - acceptCommit(dut) - - pokePublication(dut, stid = 1, transactionId = 1, firstSlot = 4, - firstGeneration = 0, groupMembers = Seq.fill(3)(1), - initiallyComplete = Set(0, 1, 2)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - acceptCommit(dut) - dut.io.headSlot(1).expect(7.U) - dut.io.headGeneration(1).expect(0.U) - - pokePublication(dut, stid = 1, transactionId = 2, firstSlot = 7, - firstGeneration = 0, groupMembers = Seq(1, 1), initiallyComplete = Set(0, 1)) - dut.clock.step() - pokePublication(dut, stid = 3, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.firstGroup.stid.expect(1.U) - dut.io.commit.bits.release.firstGroup.ridSlot.expect(7.U) - dut.io.commit.bits.release.firstGroup.ridGeneration.expect(0.U) - dut.io.commit.bits.release.groupCount.expect(2.U) - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.headSlot(1).expect(1.U) - dut.io.headGeneration(1).expect(1.U) - dut.io.occupiedGroups(1).expect(0.U) - dut.io.occupiedGroups(3).expect(1.U) - dut.clock.step(2) - dut.io.commit.valid.expect(false.B) - } - } - - test("elaborates publication and retirement independently at 2 4 and 6 decode width") { - Seq(2, 4, 6).foreach { width => - val p = OooParams( - instructionDecodeWidth = width, - retireGroupWidth = 4, - robGroupsPerStid = 16, - robBankCount = 8, - robSubbankCount = 2) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 0, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(width)(1), - initiallyComplete = (0 until width).toSet) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.groupCount.expect(math.min(width, 4).U) - } - } - } - - test("maps sequential groups across ROB bank and even odd subbank boundaries") { - val p = OooParams( - instructionDecodeWidth = 4, - robGroupsPerStid = 16, - robBankCount = 8, - robSubbankCount = 2) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - Seq(0, 4, 8).zipWithIndex.foreach { case (firstSlot, transactionId) => - pokePublication(dut, stid = 0, transactionId = transactionId, - firstSlot = firstSlot, firstGeneration = 0, - groupMembers = Seq.fill(4)(1)) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - } - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(0).expect(12.U) - - pokeCompletion(dut, stid = 0, slot = 0, ridGeneration = 0, member = 0) - dut.io.completion.ready.expect(true.B) - dut.io.completionRejected.valid.expect(false.B) - dut.clock.step() - pokeCompletion(dut, stid = 0, slot = 8, ridGeneration = 0, member = 0) - dut.io.completion.ready.expect(true.B) - dut.io.completionRejected.valid.expect(false.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - dut.io.occupiedGroups(0).expect(12.U) - } - } - - test("publishes a bounded non-flush scan atomically after all retained slices") { - val p = OooParams( - instructionDecodeWidth = 4, - robGroupsPerStid = 8, - robNonFlushScanGroupsPerCycle = 2) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 0, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(4)(1)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - dut.clock.step() - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - dut.clock.step() - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - dut.clock.step() - dut.io.nonFlushWindows(0).prefixCount.expect(4.U) - dut.io.nonFlushWindows(0).epoch.expect(1.U) - dut.io.occupiedGroups(0).expect(4.U) - } - } - - test("restarts a retained non-flush scan after exact evidence changes its row") { - val p = OooParams( - instructionDecodeWidth = 4, - robGroupsPerStid = 8, - robNonFlushScanGroupsPerCycle = 1) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 0, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(4)(1)) - val memory = dut.io.publish.bits.reservation.transaction.decoded.uops(3).recipe - memory.mayTrap.poke(true.B) - memory.mayTrapLate.poke(true.B) - memory.memoryRequestCount.poke(1.U) - memory.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - memory.dispatchClass.poke(OooDispatchClass.Agu.U) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - dut.clock.step(2) - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - pokeNonFlushEvidence(dut, stid = 0, slot = 3, ridGeneration = 0, - proofs = OooNonFlushProof.ExceptionSafeMask | - OooNonFlushProof.MemorySafeMask) - acceptNonFlushEvidence(dut) - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - - assert(waitForNonFlushPrefix(dut, stid = 0, expected = 4) >= 5) - dut.io.nonFlushWindows(0).epoch.expect(1.U) - } - } - - test("advances only an exact typed safe prefix and never treats evidence as commit") { - val p = OooParams( - instructionDecodeWidth = 4, - robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1, 1, 1)) - - val memory = dut.io.publish.bits.reservation.transaction.decoded.uops(1).recipe - memory.mayTrap.poke(true.B) - memory.mayTrapLate.poke(true.B) - memory.memoryRequestCount.poke(1.U) - memory.sideEffectOwner.poke(OooSideEffectOwner.Lsu.U) - memory.dispatchClass.poke(OooDispatchClass.Agu.U) - - val control = dut.io.publish.bits.reservation.transaction.decoded.uops(2).recipe - control.mayTrap.poke(true.B) - control.mayRedirect.poke(true.B) - control.requiresTargetValidation.poke(true.B) - control.nonspeculative.poke(true.B) - control.sideEffectOwner.poke(OooSideEffectOwner.Bctrl.U) - control.dispatchClass.poke(OooDispatchClass.Bru.U) - - dut.clock.step() - dut.io.publish.valid.poke(false.B) - waitForNonFlushPrefix(dut, stid = 1, expected = 1) - dut.io.nonFlushWindows(1).valid.expect(true.B) - dut.io.nonFlushWindows(1).head.ridSlot.expect(0.U) - dut.io.nonFlushWindows(1).prefixCount.expect(1.U) - dut.io.occupiedGroups(1).expect(3.U) - dut.io.commit.valid.expect(false.B) - - pokeNonFlushEvidence(dut, stid = 1, slot = 1, ridGeneration = 0, - proofs = OooNonFlushProof.ExceptionSafeMask | - OooNonFlushProof.MemorySafeMask) - acceptNonFlushEvidence(dut) - waitForNonFlushPrefix(dut, stid = 1, expected = 2) - dut.io.nonFlushWindows(1).prefixCount.expect(2.U) - dut.io.occupiedGroups(1).expect(3.U) - - pokeNonFlushEvidence(dut, stid = 1, slot = 2, ridGeneration = 1, - proofs = OooNonFlushProof.ExceptionSafeMask | - OooNonFlushProof.ControlSafeMask) - dut.io.nonFlushEvidenceRejected.valid.expect(true.B) - dut.clock.step() - dut.io.nonFlushEvidence.valid.poke(false.B) - dut.io.nonFlushWindows(1).prefixCount.expect(2.U) - - pokeNonFlushEvidence(dut, stid = 1, slot = 2, ridGeneration = 0, - proofs = OooNonFlushProof.ExceptionSafeMask | - OooNonFlushProof.ControlSafeMask) - acceptNonFlushEvidence(dut) - dut.clock.step() - dut.io.nonFlushWindows(1).prefixCount.expect(2.U) - - pokeNonFlushEvidence(dut, stid = 1, slot = 2, ridGeneration = 0, - proofs = OooNonFlushProof.SerializationSafeMask) - acceptNonFlushEvidence(dut) - waitForNonFlushPrefix(dut, stid = 1, expected = 3) - dut.io.nonFlushWindows(1).prefixCount.expect(3.U) - dut.io.occupiedGroups(1).expect(3.U) - dut.io.commit.valid.expect(false.B) - - pokeNonFlushEvidence(dut, stid = 1, slot = 2, ridGeneration = 0, - proofs = OooNonFlushProof.ControlSafeMask) - dut.io.nonFlushEvidenceRejected.valid.expect(true.B) - } - } - - test("freezes only the interrupted STID and keeps precise traps outside the window") { - val p = OooParams(instructionDecodeWidth = 2, robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - dut.io.interruptPending(0).poke(true.B) - pokePublication(dut, stid = 0, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.clock.step() - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - waitForNonFlushPrefix(dut, stid = 1, expected = 1) - dut.io.nonFlushWindows(0).prefixCount.expect(0.U) - dut.io.nonFlushWindows(1).prefixCount.expect(1.U) - - dut.io.interruptPending(0).poke(false.B) - waitForNonFlushPrefix(dut, stid = 0, expected = 1) - dut.io.nonFlushWindows(0).prefixCount.expect(1.U) - - pokePublication(dut, stid = 2, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - val trapGroup = dut.io.publish.bits.reservation.transaction.groups(0) - trapGroup.preciseTrap.poke(true.B) - val trapUop = dut.io.publish.bits.reservation.transaction.decoded.uops(0) - trapUop.preciseTrap.poke(true.B) - trapUop.recipe.mayTrap.poke(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.clock.step() - dut.io.nonFlushWindows(2).valid.expect(true.B) - dut.io.nonFlushWindows(2).prefixCount.expect(0.U) - - pokeNonFlushEvidence(dut, stid = 2, slot = 0, ridGeneration = 0, - proofs = OooNonFlushProof.ExceptionSafeMask) - dut.io.nonFlushEvidenceRejected.valid.expect(true.B) - } - } - - test("moves the exact window head without using non-flush as deallocation authority") { - val p = OooParams( - instructionDecodeWidth = 2, - retireGroupWidth = 1, - robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 3, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1, 1), - initiallyComplete = Set(0, 1)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - waitForNonFlushPrefix(dut, stid = 3, expected = 2) - dut.io.nonFlushWindows(3).head.ridSlot.expect(0.U) - dut.io.nonFlushWindows(3).prefixCount.expect(2.U) - dut.io.occupiedGroups(3).expect(2.U) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - - dut.io.commit.ready.poke(true.B) - dut.clock.step() - dut.io.commit.ready.poke(false.B) - dut.io.nonFlushWindows(3).head.ridSlot.expect(1.U) - dut.io.nonFlushWindows(3).prefixCount.expect(1.U) - dut.io.occupiedGroups(3).expect(1.U) - } - } - - test("prepares and applies an exact intra-group survivor suffix recovery") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokeIntraGroupPublication(dut) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(3.U) - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = false) - dut.io.recoveryPrepareReady.expect(false.B) - assert(waitForRecoveryPrepared(dut) >= 3) - dut.io.recoveryPrepared.pivotOffset.expect(0.U) - dut.io.recoveryPrepared.pivot.physicalMemberCount.expect(3.U) - dut.io.recoveryPrepared.pivot.logicalUopMask.expect(3.U) - dut.io.recoveryPrepared.pivot.memoryAfter.lsid.expect(2.U) - dut.io.recoveryPrepared.pivot.memoryAfter.youngestStoreLsid.expect(1.U) - dut.io.recoveryPrepared.survivingPivotValid.expect(true.B) - dut.io.recoveryPrepared.survivingPivot.physicalMemberCount.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.logicalUopMask.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.memoryAfter.lsid.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.memoryAfter - .youngestStoreLsid.expect(0.U) - dut.io.recoveryPrepared.survivingTailValid.expect(true.B) - dut.io.recoveryPrepared.survivingTail.key.ridSlot.expect(0.U) - dut.io.recoveryPrepared.survivingPivot.pMapQRows.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.architecturalParentCount.expect(1.U) - dut.io.recoveryPrepared.killedGroupCount.expect(2.U) - dut.io.recoveryPrepared.killedGroupMask.expect(3.U) - dut.io.recoveryPrepared.firstKilledGroup.valid.expect(true.B) - dut.io.recoveryPrepared.firstKilledGroup.ridSlot.expect(1.U) - dut.io.recoveryPrepared.killedGroups(0).key.ridSlot.expect(1.U) - dut.io.recoveryPrepared.killedGroups(0).memoryBefore.lsid.expect(2.U) - dut.io.recoveryPrepared.killedGroups(1).key.ridSlot.expect(2.U) - dut.io.recoveryPrepared.killedGroups(1).memoryAfter.lsid.expect(4.U) - dut.io.recoveryPrepared.oldTail.ridSlot.expect(3.U) - dut.io.recoveryPrepared.newTail.ridSlot.expect(1.U) - - pokeCompletion(dut, stid = 1, slot = 0, ridGeneration = 0, member = 0) - dut.io.completion.ready.expect(false.B) - dut.io.commit.valid.expect(false.B) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.completion.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(1.U) - dut.io.nonFlushWindows(1).prefixCount.expect(0.U) - - pokeCompletion(dut, stid = 1, slot = 0, ridGeneration = 0, member = 1) - dut.io.completion.ready.expect(true.B) - dut.io.completionRejected.valid.expect(true.B) - dut.clock.step() - dut.io.completion.valid.poke(false.B) - - pokeCompletion(dut, stid = 1, slot = 0, ridGeneration = 0, member = 0) - acceptCompletion(dut) - waitForCommit(dut) - dut.io.commit.valid.expect(true.B) - dut.io.commit.bits.release.groupCount.expect(1.U) - dut.io.commit.bits.groups(0).physicalMemberCount.expect(1.U) - dut.io.commit.bits.groups(0).pMapQRows.expect(1.U) - dut.io.commit.bits.groups(0).memoryAfter.lsid.expect(1.U) - } - } - - test("kills an exact logical trigger and can remove the complete ROB window") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokeIntraGroupPublication(dut) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 0, - member = 1, memberCount = 2, killTrigger = true) - waitForRecoveryPrepared(dut) - dut.io.recoveryPrepared.survivingPivotValid.expect(true.B) - dut.io.recoveryPrepared.survivingPivot.physicalMemberCount.expect(1.U) - dut.io.recoveryPrepared.survivingPivot.logicalUopMask.expect(1.U) - dut.io.recoveryPrepared.killedGroupCount.expect(2.U) - dut.io.recoveryPrepared.killedGroupMask.expect(3.U) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(1.U) - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = true) - waitForRecoveryPrepared(dut) - dut.io.recoveryPrepared.survivingPivotValid.expect(false.B) - dut.io.recoveryPrepared.survivingTailValid.expect(false.B) - dut.io.recoveryPrepared.killedGroupCount.expect(1.U) - dut.io.recoveryPrepared.killedGroupMask.expect(1.U) - dut.io.recoveryPrepared.firstKilledGroup.ridSlot.expect(0.U) - dut.io.recoveryPrepared.killedGroups(0).key.ridSlot.expect(0.U) - dut.io.recoveryPrepared.newTail.ridSlot.expect(0.U) - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(0.U) - dut.io.commit.valid.expect(false.B) - } - } - - test("preserves the trigger group and truncates only younger groups across wrap") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(4)(1), - initiallyComplete = Set(0, 1, 2, 3)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - acceptCommit(dut) - - pokePublication(dut, stid = 1, transactionId = 1, firstSlot = 4, - firstGeneration = 0, groupMembers = Seq.fill(3)(1), - initiallyComplete = Set(0, 1, 2)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - acceptCommit(dut) - dut.io.headSlot(1).expect(7.U) - dut.io.headGeneration(1).expect(0.U) - - pokeIntraGroupPublication(dut, transactionId = 2, firstSlot = 7) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 1, - member = 0, memberCount = 1, killTrigger = false, - transactionId = 2) - waitForRecoveryPrepared(dut) - dut.io.recoveryPrepared.pivotOffset.expect(1.U) - dut.io.recoveryPrepared.survivingPivotValid.expect(true.B) - dut.io.recoveryPrepared.survivingTailValid.expect(true.B) - dut.io.recoveryPrepared.survivingTail.key.ridSlot.expect(0.U) - dut.io.recoveryPrepared.survivingTail.key.ridGeneration.expect(1.U) - dut.io.recoveryPrepared.killedGroupCount.expect(1.U) - dut.io.recoveryPrepared.killedGroupMask.expect(1.U) - dut.io.recoveryPrepared.firstKilledGroup.ridSlot.expect(1.U) - dut.io.recoveryPrepared.firstKilledGroup.ridGeneration.expect(1.U) - dut.io.recoveryPrepared.killedGroups(0).key.ridSlot.expect(1.U) - dut.io.recoveryPrepared.killedGroups(0).key.ridGeneration.expect(1.U) - dut.io.recoveryPrepared.oldTail.ridSlot.expect(2.U) - dut.io.recoveryPrepared.oldTail.ridGeneration.expect(1.U) - dut.io.recoveryPrepared.newTail.ridSlot.expect(1.U) - dut.io.recoveryPrepared.newTail.ridGeneration.expect(1.U) - dut.io.commit.valid.expect(false.B) - dut.clock.step() - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.io.commit.valid.expect(false.B) - dut.io.recoveryFire.poke(true.B) - dut.io.recoveryPrepareReady.expect(true.B) - dut.io.recoveryPrepared.valid.expect(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(2.U) - dut.io.headSlot(1).expect(7.U) - dut.io.headGeneration(1).expect(0.U) - } - } - - test("retains a bounded recovery scan, aborts privately, and lets a peer publish") { - val p = OooParams( - robGroupsPerStid = 8, - robRecoveryScanGroupsPerCycle = 2) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokePublication(dut, stid = 1, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq.fill(4)(1)) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(4.U) - - pokeRecovery(dut, stid = 1, slot = 2, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = false) - dut.clock.step() - dut.clock.step() - dut.io.recoveryPrepareReady.expect(false.B) - dut.io.occupiedGroups(1).expect(4.U) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - dut.io.occupiedGroups(1).expect(4.U) - - pokeRecovery(dut, stid = 1, slot = 2, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = false) - dut.clock.step() - dut.io.recoveryPrepare.bits.rename.key.transactionId.poke(99.U) - dut.io.recoveryRejected.valid.expect(true.B) - dut.clock.step() - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - dut.io.occupiedGroups(1).expect(4.U) - - pokeRecovery(dut, stid = 1, slot = 2, ridGeneration = 0, - member = 0, memberCount = 1, killTrigger = false) - dut.clock.step() - pokePublication(dut, stid = 2, transactionId = 0, firstSlot = 0, - firstGeneration = 0, groupMembers = Seq(1)) - dut.io.publish.ready.expect(true.B) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - dut.io.occupiedGroups(2).expect(1.U) - assert(waitForRecoveryPrepared(dut) >= 7) - dut.io.recoveryPrepared.pivotOffset.expect(2.U) - dut.io.recoveryPrepared.newOccupied.expect(3.U) - dut.io.recoveryPrepared.killedGroupCount.expect(1.U) - dut.io.recoveryPrepared.killedGroups(0).key.ridSlot.expect(3.U) - dut.io.occupiedGroups(1).expect(4.U) - - dut.io.recoveryFire.poke(true.B) - dut.clock.step() - dut.io.recoveryFire.poke(false.B) - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(3.U) - dut.io.occupiedGroups(2).expect(1.U) - } - } - - test("rejects stale identity and non-logical trigger shapes with zero mutation") { - val p = OooParams(robGroupsPerStid = 8) - simulate(new OooS1GroupedRob(p)) { dut => - clear(dut) - pokeIntraGroupPublication(dut) - dut.clock.step() - dut.io.publish.valid.poke(false.B) - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 1, - member = 0, memberCount = 1, killTrigger = false) - dut.io.recoveryPrepareReady.expect(false.B) - waitForRecoveryRejected(dut) - dut.io.recoveryPrepared.valid.expect(false.B) - dut.io.recoveryRejected.bits.exactMatchCount.expect(0.U) - dut.clock.step() - - dut.io.recoveryPrepare.valid.poke(false.B) - dut.clock.step() - - pokeRecovery(dut, stid = 1, slot = 0, ridGeneration = 0, - member = 1, memberCount = 1, killTrigger = true) - dut.io.recoveryPrepareReady.expect(false.B) - waitForRecoveryRejected(dut) - dut.io.recoveryRejected.bits.exactMatchCount.expect(1.U) - dut.io.recoveryRejected.bits.triggerShapeMatch.expect(false.B) - dut.clock.step() - - dut.io.recoveryPrepare.valid.poke(false.B) - dut.io.occupiedGroups(1).expect(3.U) - dut.io.recoveryFire.poke(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/OooStoreCommitAuthorizationOwnerSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooStoreCommitAuthorizationOwnerSpec.scala new file mode 100644 index 00000000..1df39ffb --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/OooStoreCommitAuthorizationOwnerSpec.scala @@ -0,0 +1,68 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class OooStoreCommitAuthorizationOwnerSpec extends AnyFunSuite with ChiselSim { + test("store batch is invisible before common commit fire then drains exactly once") { + simulate(new OooStoreCommitAuthorizationOwner( + SimulationParamProfiles.W2)) { dut => + dut.io.commit.bits.poke(0.U.asTypeOf(dut.io.commit.bits)) + dut.io.commit.valid.poke(true.B) + dut.io.commit.bits.count.poke(2.U) + val pair = dut.io.commit.bits.entries(0) + pair.memoryValid.poke(true.B) + pair.memoryStore.poke(true.B) + pair.memory.transaction.value.poke(9.U) + pair.memory.transaction.generation.poke(3.U) + pair.memoryOrder.firstLsid.poke(21.U) + pair.memoryOrder.firstSid.poke(31.U) + pair.memoryOrder.requestCount.poke(2.U) + val scalar = dut.io.commit.bits.entries(1) + scalar.memoryValid.poke(true.B) + scalar.memoryStore.poke(true.B) + scalar.memory.transaction.value.poke(10.U) + scalar.memory.transaction.generation.poke(4.U) + scalar.memoryOrder.firstLsid.poke(23.U) + scalar.memoryOrder.firstSid.poke(33.U) + scalar.memoryOrder.requestCount.poke(1.U) + dut.io.applied.poke(false.B) + dut.io.storeCommit.ready.poke(false.B) + + dut.io.canAccept.expect(true.B) + dut.io.drained.expect(true.B) + dut.io.storeCommit.valid.expect(false.B, + "prepared store tokens must not become visible before common commit fire") + dut.clock.step(2) + dut.io.storeCommit.valid.expect(false.B) + + dut.io.applied.poke(true.B) + dut.clock.step() + dut.io.applied.poke(false.B) + dut.io.commit.valid.poke(false.B) + dut.io.drained.expect(false.B) + dut.io.storeCommit.valid.expect(true.B) + dut.io.storeCommit.bits.beat.expect(0.U) + dut.io.storeCommit.bits.transaction.value.expect(9.U) + dut.io.storeCommit.bits.transaction.generation.expect(3.U) + val held = dut.io.storeCommit.bits.peek() + dut.clock.step(2) + dut.io.storeCommit.bits.expect(held) + + dut.io.storeCommit.ready.poke(true.B) + dut.clock.step() + dut.io.storeCommit.valid.expect(true.B) + dut.io.storeCommit.bits.beat.expect(1.U) + dut.clock.step() + dut.io.storeCommit.valid.expect(true.B) + dut.io.storeCommit.bits.beat.expect(0.U) + dut.io.storeCommit.bits.transaction.value.expect(10.U) + dut.io.storeCommit.bits.transaction.generation.expect(4.U) + dut.clock.step() + dut.io.storeCommit.valid.expect(false.B) + dut.io.drained.expect(true.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/OooStqRecoveryProjectionSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooStqRecoveryProjectionSpec.scala index ef781127..eb5241d7 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooStqRecoveryProjectionSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooStqRecoveryProjectionSpec.scala @@ -3,6 +3,8 @@ package linxcore.ooo import chisel3._ import chisel3.simulator.scalatest.ChiselSim import linxcore.lsu.{STQEntryBankRow, STQEntryStatus} +import linxcore.top.interface.{RecoveryCause, RecoveryPhase, RecoveryPlan, + RobIdentity} import org.scalatest.funsuite.AnyFunSuite class OooStqRecoveryProjectionSpec extends AnyFunSuite with ChiselSim { @@ -18,26 +20,45 @@ class OooStqRecoveryProjectionSpec extends AnyFunSuite with ChiselSim { robRecoveryScanGroupsPerCycle = 2, robNonFlushScanGroupsPerCycle = 2, pcBufferEntries = 8, - pcBankCount = 2, + pcBankCount = 4, pcRecoveryScanGroupsPerCycle = 2, - pcWritePorts = 2, + pcWritePorts = 3, iqBankCount = 2, iqEntriesPerBank = 4, iqFreeSelectLeafEntries = 2, tuRetireSourceDepthPerStid = 16, lsidWidth = 40) + private val core = OooRecoveryMembership.coreParams(p) - private def pokeRecovery(dut: OooStqRecoveryProjection): Unit = { - dut.io.recovery.poke(0.U.asTypeOf(dut.io.recovery)) - dut.io.recovery.valid.poke(true.B) - dut.io.recovery.oldHead.valid.poke(true.B) - dut.io.recovery.oldHead.peId.poke(1.U) - dut.io.recovery.oldHead.stid.poke(1.U) - dut.io.recovery.oldHead.ridSlot.poke(0.U) - dut.io.recovery.oldHead.ridGeneration.poke(7.U) - dut.io.recovery.oldOccupied.poke(8.U) - dut.io.recovery.newOccupied.poke(2.U) - dut.io.recoveryValid.poke(true.B) + private def pokeIdentity( + identity: RobIdentity, + ridSlot: Int, + memberIndex: Int = 3): Unit = { + identity.poke(0.U.asTypeOf(identity)) + identity.peId.poke(1.U) + identity.stid.poke(1.U) + identity.ridSlot.poke(ridSlot.U) + identity.ridGeneration.poke(7.U) + identity.memberIndex.poke(memberIndex.U) + identity.residentGeneration.poke(9.U) + identity.bid.poke(0x93.U) + identity.brobGeneration.poke(8.U) + } + + private def pokeRecovery( + plan: RecoveryPlan, + firstRidSlot: Int, + lastRidSlot: Int): Unit = { + plan.poke(0.U.asTypeOf(plan)) + plan.transactionId.poke(71.U) + plan.phase.poke(RecoveryPhase.Prepare) + plan.cause.poke(RecoveryCause.Branch) + pokeIdentity(plan.trigger, firstRidSlot) + plan.firstKilledValid.poke(true.B) + pokeIdentity(plan.firstKilled, firstRidSlot) + pokeIdentity(plan.lastKilled, lastRidSlot) + plan.killedGroupCount.poke(1.U) + plan.killedMemberCount.poke(1.U) } private def pokeRow( @@ -64,9 +85,10 @@ class OooStqRecoveryProjectionSpec extends AnyFunSuite with ChiselSim { } test("projects only the killed speculative suffix and reports committed rows") { - simulate(new OooStqRecoveryProjection(p, stqEntries = 4)) { dut => + simulate(new OooStqRecoveryProjection(core, stqEntries = 4)) { dut => dut.io.rows.poke(0.U.asTypeOf(dut.io.rows)) - pokeRecovery(dut) + pokeRecovery(dut.io.prepare, firstRidSlot = 6, lastRidSlot = 7) + dut.io.prepareValid.poke(true.B) pokeRow(dut.io.rows(0), ridSlot = 6) pokeRow(dut.io.rows(1), ridSlot = 1) pokeRow(dut.io.rows(3), ridSlot = 7, status = STQEntryStatus.Commit) @@ -78,9 +100,10 @@ class OooStqRecoveryProjectionSpec extends AnyFunSuite with ChiselSim { } test("malformed target owner rejects the entire exact recovery projection") { - simulate(new OooStqRecoveryProjection(p, stqEntries = 4)) { dut => + simulate(new OooStqRecoveryProjection(core, stqEntries = 4)) { dut => dut.io.rows.poke(0.U.asTypeOf(dut.io.rows)) - pokeRecovery(dut) + pokeRecovery(dut.io.prepare, firstRidSlot = 5, lastRidSlot = 6) + dut.io.prepareValid.poke(true.B) pokeRow(dut.io.rows(0), ridSlot = 6) pokeRow(dut.io.rows(2), ridSlot = 5, malformedPe = true) dut.io.rejected.expect(true.B) diff --git a/chisel/src/test/scala/linxcore/ooo/OooStqReservationProjectionSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooStqReservationProjectionSpec.scala index dac415e6..4166ca12 100644 --- a/chisel/src/test/scala/linxcore/ooo/OooStqReservationProjectionSpec.scala +++ b/chisel/src/test/scala/linxcore/ooo/OooStqReservationProjectionSpec.scala @@ -201,7 +201,7 @@ class OooStqReservationProjectionSpec extends AnyFunSuite with ChiselSim { test("STD child and malformed pair range cannot allocate STQ rows") { simulate(new OooStqReservationHarness(p, stqEntries = 4)) { dut => dut.io.inputValid.poke(true.B) - pokeStore(dut.io.input, pair = true, childIndex = 1, memberIndex = 4) + pokeStore(dut.io.input, pair = true, childIndex = 1, memberIndex = 3) dut.io.rejected.expect(true.B) dut.io.accepted.expect(false.B) dut.clock.step() diff --git a/chisel/src/test/scala/linxcore/ooo/OooTURenameSpec.scala b/chisel/src/test/scala/linxcore/ooo/OooTURenameSpec.scala deleted file mode 100644 index 1ecdb4c8..00000000 --- a/chisel/src/test/scala/linxcore/ooo/OooTURenameSpec.scala +++ /dev/null @@ -1,872 +0,0 @@ -package linxcore.ooo - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import linxcore.common.{DestinationKind, OperandClass} -import org.scalatest.funsuite.AnyFunSuite - -object OooTURenameSpec { - final case class UopShape( - sources: Seq[(OperandClass.Type, Int)] = Seq.empty, - destinations: Seq[(DestinationKind.Type, Int)] = Seq.empty) -} - -class OooTURenameSpec extends AnyFunSuite with ChiselSim { - import OooTURenameSpec.UopShape - - private def clear(dut: OooTURename): Unit = { - dut.io.reservePrepare.valid.poke(false.B) - dut.io.reservePrepare.bits.poke(0.U.asTypeOf(dut.io.reservePrepare.bits)) - dut.io.reserveFire.poke(false.B) - dut.io.cancel.foreach(_.poke(false.B)) - dut.io.publicationPrepare.valid.poke(false.B) - dut.io.publicationPrepare.bits.poke( - 0.U.asTypeOf(dut.io.publicationPrepare.bits)) - dut.io.publishFire.poke(false.B) - dut.io.retireCommand.valid.poke(false.B) - dut.io.retireCommand.bits.poke( - 0.U.asTypeOf(dut.io.retireCommand.bits)) - dut.io.blockCommit.valid.poke(false.B) - dut.io.blockCommit.bits.poke( - 0.U.asTypeOf(dut.io.blockCommit.bits)) - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryAuthorize.bits.poke( - 0.U.asTypeOf(dut.io.recoveryAuthorize.bits)) - dut.io.recoverySource.valid.poke(false.B) - dut.io.recoverySource.bits.poke( - 0.U.asTypeOf(dut.io.recoverySource.bits)) - dut.io.recoverySourcesDone.poke(false.B) - dut.io.recoveryFinish.poke(false.B) - } - - private def pokeTransaction( - transaction: OooD2GroupedTransaction, - p: OooParams, - stid: Int, - transactionId: Int, - shapes: Seq[UopShape]): Unit = { - transaction.poke(0.U.asTypeOf(transaction)) - val mask = (BigInt(1) << shapes.size) - 1 - val tCount = shapes.flatMap(_.destinations).count(_._1 == DestinationKind.T) - val uCount = shapes.flatMap(_.destinations).count(_._1 == DestinationKind.U) - - transaction.plan.transactionId.poke(transactionId.U) - transaction.plan.peId.poke(2.U) - transaction.plan.stid.poke(stid.U) - transaction.plan.epoch.poke(7.U) - transaction.plan.uopMask.poke(mask.U) - transaction.plan.groupCount.poke(1.U) - transaction.plan.demand.tAllocations.poke(tCount.U) - transaction.plan.demand.uAllocations.poke(uCount.U) - transaction.decoded.peId.poke(2.U) - transaction.decoded.stid.poke(stid.U) - transaction.decoded.epoch.poke(7.U) - transaction.decoded.uopMask.poke(mask.U) - transaction.groupMask.poke(1.U) - - val group = transaction.groups(0) - group.valid.poke(true.B) - group.key.valid.poke(true.B) - group.key.peId.poke(2.U) - group.key.stid.poke(stid.U) - group.key.ridSlot.poke(5.U) - group.key.ridGeneration.poke(3.U) - group.logicalUopMask.poke(mask.U) - group.logicalUopCount.poke(shapes.size.U) - group.physicalMemberCount.poke(shapes.size.U) - - shapes.zipWithIndex.foreach { case (shape, uopIndex) => - val uop = transaction.decoded.uops(uopIndex) - uop.valid.poke(true.B) - uop.plannedChildCount.poke(1.U) - transaction.uopGroupIndex(uopIndex).poke(0.U) - transaction.uopMemberBase(uopIndex).poke(uopIndex.U) - shape.sources.zipWithIndex.foreach { case ((operandClass, relative), sourceIndex) => - uop.sources(sourceIndex).valid.poke(true.B) - uop.sources(sourceIndex).operandClass.poke(operandClass) - uop.sources(sourceIndex).relativeIndex.poke(relative.U) - } - shape.destinations.zipWithIndex.foreach { - case ((kind, relative), destinationIndex) => - uop.destinations(destinationIndex).valid.poke(true.B) - uop.destinations(destinationIndex).kind.poke(kind) - uop.destinations(destinationIndex).relativeIndex.poke(relative.U) - } - } - } - - private def pokeReserve( - dut: OooTURename, - stid: Int, - transactionId: Int, - shapes: Seq[UopShape]): Unit = { - pokeTransaction(dut.io.reservePrepare.bits, dut.p, stid, transactionId, - shapes) - dut.io.reservePrepare.valid.poke(true.B) - } - - private def pokePublication( - dut: OooTURename, - stid: Int, - transactionId: Int, - shapes: Seq[UopShape]): Unit = { - dut.io.publicationPrepare.bits.poke( - 0.U.asTypeOf(dut.io.publicationPrepare.bits)) - val request = dut.io.publicationPrepare.bits - val mask = (BigInt(1) << shapes.size) - 1 - request.peId.poke(2.U) - request.stid.poke(stid.U) - request.epoch.poke(7.U) - request.transactionId.poke(transactionId.U) - request.uopMask.poke(mask.U) - shapes.zipWithIndex.foreach { case (shape, uopIndex) => - val uop = request.uops(uopIndex) - uop.valid.poke(true.B) - uop.member.group.valid.poke(true.B) - uop.member.group.peId.poke(2.U) - uop.member.group.stid.poke(stid.U) - uop.member.group.ridSlot.poke(5.U) - uop.member.group.ridGeneration.poke(3.U) - uop.member.bid.valid.poke(true.B) - uop.member.bid.value.poke(9.U) - uop.member.brobGeneration.poke(4.U) - uop.member.memberIndex.poke(uopIndex.U) - uop.member.residentGeneration.poke(11.U) - shape.sources.zipWithIndex.foreach { - case ((operandClass, relative), sourceIndex) => - val source = uop.sources(sourceIndex) - source.valid.poke( - (operandClass == OperandClass.T || operandClass == OperandClass.U).B) - source.kind.poke(if (operandClass == OperandClass.T) - DestinationKind.T else DestinationKind.U) - source.relativeIndex.poke(relative.U) - } - shape.destinations.zipWithIndex.foreach { - case ((kind, relative), destinationIndex) => - val destination = uop.destinations(destinationIndex) - destination.valid.poke( - (kind == DestinationKind.T || kind == DestinationKind.U).B) - destination.kind.poke(kind) - destination.relativeIndex.poke(relative.U) - } - } - dut.io.publicationPrepare.valid.poke(true.B) - } - - private def reserve(dut: OooTURename): Unit = { - dut.io.reserveReady.expect(true.B) - dut.io.reserveFire.poke(true.B) - dut.clock.step() - dut.io.reserveFire.poke(false.B) - dut.io.reservePrepare.valid.poke(false.B) - } - - private def publish(dut: OooTURename): Unit = { - dut.io.publicationReady.expect(true.B) - dut.io.publishFire.poke(true.B) - dut.clock.step() - dut.io.publishFire.poke(false.B) - dut.io.publicationPrepare.valid.poke(false.B) - } - - private def retireLocal( - dut: OooTURename, - kind: DestinationKind.Type, - sequenceIndex: Int, - sequenceGeneration: Int, - memberIndex: Int = 0, - dealloc: Boolean): Unit = { - val command = dut.io.retireCommand.bits - command.poke(0.U.asTypeOf(command)) - command.valid.poke(true.B) - command.member.group.valid.poke(true.B) - command.member.group.peId.poke(2.U) - command.member.group.stid.poke(0.U) - command.member.group.ridSlot.poke(5.U) - command.member.group.ridGeneration.poke(3.U) - command.member.bid.valid.poke(true.B) - command.member.bid.value.poke(9.U) - command.member.brobGeneration.poke(4.U) - command.member.memberIndex.poke(memberIndex.U) - command.member.residentGeneration.poke(11.U) - command.kind.poke(kind) - command.sequence.valid.poke(true.B) - command.sequence.index.poke(sequenceIndex.U) - command.sequence.generation.poke(sequenceGeneration.U) - command.dealloc.poke(dealloc.B) - dut.io.retireCommand.valid.poke(true.B) - dut.io.retireCommand.ready.expect(true.B) - dut.clock.step() - dut.io.retireCommand.valid.poke(false.B) - } - - private def pokeRecoveryRequest( - request: OooRenameRecoveryRequest, - stid: Int, - transactionId: Int, - uopIndex: Int, - killTrigger: Boolean): Unit = { - request.poke(0.U.asTypeOf(request)) - request.key.member.group.valid.poke(true.B) - request.key.member.group.peId.poke(2.U) - request.key.member.group.stid.poke(stid.U) - request.key.member.group.ridSlot.poke(5.U) - request.key.member.group.ridGeneration.poke(3.U) - request.key.member.bid.valid.poke(true.B) - request.key.member.bid.value.poke(9.U) - request.key.member.brobGeneration.poke(4.U) - request.key.member.memberIndex.poke(uopIndex.U) - request.key.member.residentGeneration.poke(11.U) - request.key.cause.poke(OooRecoveryCause.Branch) - request.key.transactionId.poke(transactionId.U) - request.key.epoch.poke(7.U) - request.killTrigger.poke(killTrigger.B) - } - - private def startRecovery( - dut: OooTURename, - stid: Int, - transactionId: Int, - uopIndex: Int = 0, - killTrigger: Boolean = false): Unit = { - pokeRecoveryRequest(dut.io.recoveryAuthorize.bits, stid, - transactionId, uopIndex, killTrigger) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.recoveryAuthorize.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryBusy.expect(true.B) - dut.io.recoveryStid.expect(stid.U) - } - - private def sendRecoverySource( - dut: OooTURename, - triggerTransactionId: Int, - killedTransactionId: Int, - killedUopIndex: Int, - tBeforeIndex: Int, - tBeforeGeneration: Int, - uBeforeIndex: Int, - uBeforeGeneration: Int, - destinations: Seq[(DestinationKind.Type, Int, Int, Int)], - last: Boolean, - stid: Int = 0): Unit = { - val transfer = dut.io.recoverySource.bits - transfer.poke(0.U.asTypeOf(transfer)) - pokeRecoveryRequest(transfer.request, stid, triggerTransactionId, - uopIndex = 0, killTrigger = false) - val source = transfer.source - source.valid.poke(true.B) - source.transactionId.poke(killedTransactionId.U) - source.epoch.poke(7.U) - source.uopIndex.poke(killedUopIndex.U) - source.member.group.valid.poke(true.B) - source.member.group.peId.poke(2.U) - source.member.group.stid.poke(stid.U) - source.member.group.ridSlot.poke(5.U) - source.member.group.ridGeneration.poke(3.U) - source.member.bid.valid.poke(true.B) - source.member.bid.value.poke(9.U) - source.member.brobGeneration.poke(4.U) - source.member.memberIndex.poke(killedUopIndex.U) - source.member.residentGeneration.poke(11.U) - source.tSeqBefore.valid.poke(true.B) - source.tSeqBefore.index.poke(tBeforeIndex.U) - source.tSeqBefore.generation.poke(tBeforeGeneration.U) - source.uSeqBefore.valid.poke(true.B) - source.uSeqBefore.index.poke(uBeforeIndex.U) - source.uSeqBefore.generation.poke(uBeforeGeneration.U) - destinations.zipWithIndex.foreach { - case ((kind, sequenceIndex, sequenceGeneration, physicalTag), index) => - val destination = source.destinations(index) - destination.valid.poke(true.B) - destination.kind.poke(kind) - destination.relativeIndex.poke(0.U) - destination.sequence.valid.poke(true.B) - destination.sequence.index.poke(sequenceIndex.U) - destination.sequence.generation.poke(sequenceGeneration.U) - destination.physicalTag.poke(physicalTag.U) - destination.stid.poke(stid.U) - destination.epoch.poke(7.U) - } - transfer.last.poke(last.B) - dut.io.recoverySource.valid.poke(true.B) - dut.io.recoverySource.ready.expect(true.B) - dut.clock.step() - dut.io.recoverySource.valid.poke(false.B) - } - - private def finishRecovery(dut: OooTURename): Unit = { - dut.io.recoverySourcesDone.poke(true.B) - dut.clock.step() - dut.io.recoverySourcesDone.poke(false.B) - dut.io.recoveryComplete.expect(true.B) - dut.io.recoveryFinish.poke(true.B) - dut.clock.step() - dut.io.recoveryFinish.poke(false.B) - dut.io.recoveryBusy.expect(false.B) - } - - test("resolves T and U relative sources across one retained bundle") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 4, - renameWidth = 4, - dispatchWidth = 4, - tPhysRegs = 8, - uPhysRegs = 8, - tuMapQDepthPerStid = 8) - simulate(new OooTURename(p)) { dut => - clear(dut) - val shapes = Seq( - UopShape(destinations = Seq(DestinationKind.T -> 0)), - UopShape( - sources = Seq(OperandClass.T -> 0), - destinations = Seq(DestinationKind.U -> 0)), - UopShape( - sources = Seq(OperandClass.U -> 0), - destinations = Seq(DestinationKind.T -> 0))) - - pokeReserve(dut, stid = 1, transactionId = 20, shapes) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.tAllocationCount.expect(2.U) - dut.io.reservation.uAllocationCount.expect(1.U) - dut.io.reservation.tSeqBefore(0).index.expect(0.U) - dut.io.reservation.tSeqBefore(1).index.expect(1.U) - dut.io.reservation.uSeqBefore(1).index.expect(0.U) - dut.io.reservation.tSeqBefore(2).index.expect(1.U) - dut.io.reservation.uSeqBefore(2).index.expect(1.U) - dut.io.reservation.sourceMappings(1)(0).valid.expect(true.B) - dut.io.reservation.sourceMappings(1)(0).physicalTag.expect(0.U) - dut.io.reservation.sourceMappings(2)(0).valid.expect(true.B) - dut.io.reservation.sourceMappings(2)(0).physicalTag.expect(0.U) - dut.io.reservation.allocations(0).mapping.sequence.index.expect(0.U) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(0.U) - dut.io.reservation.allocations(2).mapping.sequence.index.expect(0.U) - dut.io.reservation.allocations(2).mapping.physicalTag.expect(0.U) - dut.io.reservation.allocations(4).mapping.sequence.index.expect(1.U) - dut.io.reservation.allocations(4).mapping.physicalTag.expect(1.U) - dut.clock.step(3) - dut.io.tMapQUsed(1).expect(0.U) - dut.io.uMapQUsed(1).expect(0.U) - - reserve(dut) - dut.io.provisional(1).valid.expect(true.B) - pokePublication(dut, stid = 1, transactionId = 20, shapes) - dut.io.publicationReady.expect(true.B) - dut.io.prepared.uops(1).sources(0).physicalTag.expect(0.U) - dut.io.prepared.uops(2).destinations(0).physicalTag.expect(1.U) - dut.io.prepared.rows(4).member.memberIndex.expect(2.U) - publish(dut) - dut.io.provisional(1).valid.expect(false.B) - dut.io.tMapQUsed(1).expect(2.U) - dut.io.uMapQUsed(1).expect(1.U) - dut.io.tPhysicalUsed(1).expect(2.U) - dut.io.uPhysicalUsed(1).expect(1.U) - dut.io.tMapQUsed(0).expect(0.U) - - val lookup = Seq(UopShape(sources = Seq( - OperandClass.T -> 0, - OperandClass.T -> 1, - OperandClass.U -> 0))) - pokeReserve(dut, stid = 1, transactionId = 21, lookup) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.sourceMappings(0)(0).physicalTag.expect(1.U) - dut.io.reservation.sourceMappings(0)(0).sequence.index.expect(1.U) - dut.io.reservation.sourceMappings(0)(1).physicalTag.expect(0.U) - dut.io.reservation.sourceMappings(0)(1).sequence.index.expect(0.U) - dut.io.reservation.sourceMappings(0)(2).physicalTag.expect(0.U) - dut.io.reservation.sourceMappings(0)(2).sequence.index.expect(0.U) - } - } - - test("rejects relative-source underflow without reserving state") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - pokeReserve(dut, stid = 0, transactionId = 30, - Seq(UopShape(sources = Seq(OperandClass.T -> 0)))) - dut.io.reserveReady.expect(false.B) - dut.io.reserveRejected.valid.expect(true.B) - dut.io.reserveRejected.bits.sourceUnderflowMask.expect(1.U) - dut.clock.step(3) - dut.io.tMapQUsed(0).expect(0.U) - dut.io.provisional(0).valid.expect(false.B) - } - } - - test("keeps one provisional lease per STID and cancels it exactly") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 40, oneT) - val heldTag = dut.io.reservation.allocations(0).mapping.physicalTag.peek().litValue - dut.clock.step(3) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(heldTag.U) - reserve(dut) - dut.io.provisional(0).valid.expect(true.B) - dut.io.tMapQUsed(0).expect(0.U) - - pokeReserve(dut, stid = 0, transactionId = 41, oneT) - dut.io.reserveReady.expect(false.B) - pokeReserve(dut, stid = 1, transactionId = 42, oneT) - dut.io.reserveReady.expect(true.B) - dut.io.cancel(0).poke(true.B) - dut.clock.step() - dut.io.cancel(0).poke(false.B) - dut.io.provisional(0).valid.expect(false.B) - dut.io.tMapQUsed(0).expect(0.U) - pokeReserve(dut, stid = 0, transactionId = 43, oneT) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(0.U) - } - } - - test("rejects a mismatched publication and publishes only the exact lease") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneU = Seq(UopShape(destinations = Seq(DestinationKind.U -> 0))) - pokeReserve(dut, stid = 1, transactionId = 50, oneU) - reserve(dut) - - pokePublication(dut, stid = 1, transactionId = 51, oneU) - dut.io.publicationReady.expect(false.B) - dut.io.publicationRejected.valid.expect(true.B) - dut.clock.step(2) - dut.io.uMapQUsed(1).expect(0.U) - dut.io.provisional(1).valid.expect(true.B) - - pokePublication(dut, stid = 1, transactionId = 50, oneU) - dut.io.publicationPrepare.bits.uops(0).member.memberIndex.poke(1.U) - dut.io.publicationReady.expect(false.B) - dut.io.publicationPrepare.bits.uops(0).member.memberIndex.poke(0.U) - dut.io.publicationPrepare.bits.uopMask.poke(0.U) - dut.io.publicationReady.expect(false.B) - dut.io.publicationPrepare.bits.uopMask.poke(1.U) - dut.io.publicationReady.expect(true.B) - publish(dut) - dut.io.uMapQUsed(1).expect(1.U) - dut.io.uPhysicalUsed(1).expect(1.U) - dut.io.provisional(1).valid.expect(false.B) - } - } - - test("replaces a publishing lease and bypasses its local destination") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val producer = Seq(UopShape( - destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 60, producer) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 60, producer) - - val consumer = Seq(UopShape( - sources = Seq(OperandClass.T -> 0), - destinations = Seq(DestinationKind.U -> 0))) - pokeReserve(dut, stid = 0, transactionId = 61, consumer) - dut.io.publicationReady.expect(true.B) - dut.io.publishFire.poke(true.B) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.tSeqBefore(0).index.expect(1.U) - dut.io.reservation.sourceMappings(0)(0).valid.expect(true.B) - dut.io.reservation.sourceMappings(0)(0).physicalTag.expect(0.U) - - dut.io.reserveFire.poke(true.B) - dut.clock.step() - dut.io.publishFire.poke(false.B) - dut.io.reserveFire.poke(false.B) - dut.io.reservePrepare.valid.poke(false.B) - dut.io.publicationPrepare.valid.poke(false.B) - dut.io.tMapQUsed(0).expect(1.U) - dut.io.uMapQUsed(0).expect(0.U) - dut.io.provisional(0).valid.expect(true.B) - dut.io.provisional(0).transactionId.expect(61.U) - dut.io.provisional(0).sourceMappings(0)(0).physicalTag.expect(0.U) - - pokePublication(dut, stid = 0, transactionId = 61, consumer) - publish(dut) - dut.io.tMapQUsed(0).expect(1.U) - dut.io.uMapQUsed(0).expect(1.U) - } - } - - test("keeps four STID local namespaces independent") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - stidCount = 4, - tPhysRegs = 8, - uPhysRegs = 8, - tuMapQDepthPerStid = 8) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - for (stid <- 0 until 4) { - pokeReserve(dut, stid = stid, transactionId = 70 + stid, oneT) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(0.U) - reserve(dut) - pokePublication(dut, stid = stid, transactionId = 70 + stid, oneT) - publish(dut) - } - dut.io.tMapQUsed.foreach(_.expect(1.U)) - - pokeReserve(dut, stid = 2, transactionId = 80, oneT) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(1.U) - reserve(dut) - pokePublication(dut, stid = 2, transactionId = 80, oneT) - publish(dut) - dut.io.tMapQUsed(2).expect(2.U) - dut.io.tMapQUsed(0).expect(1.U) - dut.io.tMapQUsed(1).expect(1.U) - dut.io.tMapQUsed(3).expect(1.U) - - val lookup = Seq(UopShape(sources = Seq(OperandClass.T -> 0))) - pokeReserve(dut, stid = 2, transactionId = 81, lookup) - dut.io.reservation.sourceMappings(0)(0).physicalTag.expect(1.U) - pokeReserve(dut, stid = 1, transactionId = 82, lookup) - dut.io.reservation.sourceMappings(0)(0).physicalTag.expect(0.U) - } - } - - test("requires exact wrap-qualified retire commands and reclaims physical tags") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - - for (transactionId <- 90 until 94) { - val sequenceIndex = transactionId - 90 - pokeReserve(dut, stid = 0, transactionId, oneT) - dut.io.reservation.allocations(0).mapping.sequence.index.expect( - sequenceIndex.U) - dut.io.reservation.allocations(0).mapping.sequence.generation.expect(0.U) - reserve(dut) - pokePublication(dut, stid = 0, transactionId, oneT) - publish(dut) - retireLocal(dut, DestinationKind.T, sequenceIndex, - sequenceGeneration = 0, dealloc = false) - retireLocal(dut, DestinationKind.T, sequenceIndex, - sequenceGeneration = 0, dealloc = true) - } - dut.io.tMapQUsed(0).expect(0.U) - dut.io.tPhysicalUsed(0).expect(0.U) - - pokeReserve(dut, stid = 0, transactionId = 94, oneT) - dut.io.reservation.allocations(0).mapping.sequence.index.expect(0.U) - dut.io.reservation.allocations(0).mapping.sequence.generation.expect(1.U) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 94, oneT) - publish(dut) - - val stale = dut.io.retireCommand.bits - stale.poke(0.U.asTypeOf(stale)) - stale.valid.poke(true.B) - stale.member.group.valid.poke(true.B) - stale.member.group.peId.poke(2.U) - stale.member.group.stid.poke(0.U) - stale.member.group.ridSlot.poke(5.U) - stale.member.group.ridGeneration.poke(3.U) - stale.member.bid.valid.poke(true.B) - stale.member.bid.value.poke(9.U) - stale.member.brobGeneration.poke(4.U) - stale.member.residentGeneration.poke(11.U) - stale.kind.poke(DestinationKind.T) - stale.sequence.valid.poke(true.B) - stale.sequence.index.poke(0.U) - stale.sequence.generation.poke(0.U) - dut.io.retireCommand.valid.poke(true.B) - dut.io.retireCommand.ready.expect(false.B) - dut.clock.step() - dut.io.retireCommand.valid.poke(false.B) - dut.io.tMapQUsed(0).expect(1.U) - - retireLocal(dut, DestinationKind.T, sequenceIndex = 0, - sequenceGeneration = 1, dealloc = false) - retireLocal(dut, DestinationKind.T, sequenceIndex = 0, - sequenceGeneration = 1, dealloc = true) - dut.io.tMapQUsed(0).expect(0.U) - dut.io.tPhysicalUsed(0).expect(0.U) - } - } - - test("releases the exact retired block prefix after relation cleanup") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val twoT = Seq( - UopShape(destinations = Seq(DestinationKind.T -> 0)), - UopShape(destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 100, twoT) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 100, twoT) - publish(dut) - retireLocal(dut, DestinationKind.T, sequenceIndex = 0, - sequenceGeneration = 0, memberIndex = 0, dealloc = false) - retireLocal(dut, DestinationKind.T, sequenceIndex = 1, - sequenceGeneration = 0, memberIndex = 1, dealloc = false) - dut.io.tMapQUsed(0).expect(2.U) - - val commit = dut.io.blockCommit.bits - commit.poke(0.U.asTypeOf(commit)) - commit.valid.poke(true.B) - commit.peId.poke(2.U) - commit.stid.poke(0.U) - commit.block.valid.poke(true.B) - commit.block.bid.valid.poke(true.B) - commit.block.bid.value.poke(9.U) - commit.block.generation.poke(4.U) - dut.io.blockCommit.valid.poke(true.B) - dut.io.blockCommit.ready.expect(true.B) - dut.clock.step() - dut.io.blockCommit.valid.poke(false.B) - dut.io.tMapQUsed(0).expect(0.U) - dut.io.tPhysicalUsed(0).expect(0.U) - } - } - - test("rolls back an exact mixed T/U suffix and restores both cursors") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - stidCount = 4, - tPhysRegs = 8, - uPhysRegs = 8, - tuMapQDepthPerStid = 8) - simulate(new OooTURename(p)) { dut => - clear(dut) - val both = Seq(UopShape(destinations = Seq( - DestinationKind.T -> 0, DestinationKind.U -> 0))) - pokeReserve(dut, stid = 0, transactionId = 200, both) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 200, both) - publish(dut) - - val killed = Seq( - UopShape(destinations = Seq( - DestinationKind.T -> 0, DestinationKind.U -> 0)), - UopShape(destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 201, killed) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 201, killed) - publish(dut) - dut.io.tMapQUsed(0).expect(3.U) - dut.io.uMapQUsed(0).expect(2.U) - - startRecovery(dut, stid = 0, transactionId = 200) - - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 202, oneT) - dut.io.reserveReady.expect(false.B) - pokeReserve(dut, stid = 1, transactionId = 203, oneT) - dut.io.reserveReady.expect(true.B) - reserve(dut) - pokePublication(dut, stid = 1, transactionId = 203, oneT) - publish(dut) - dut.io.tMapQUsed(1).expect(1.U) - - sendRecoverySource(dut, triggerTransactionId = 200, - killedTransactionId = 201, killedUopIndex = 1, - tBeforeIndex = 2, tBeforeGeneration = 0, - uBeforeIndex = 2, uBeforeGeneration = 0, - destinations = Seq((DestinationKind.T, 2, 0, 2)), last = false) - dut.io.tMapQUsed(0).expect(2.U) - dut.io.uMapQUsed(0).expect(2.U) - sendRecoverySource(dut, triggerTransactionId = 200, - killedTransactionId = 201, killedUopIndex = 0, - tBeforeIndex = 1, tBeforeGeneration = 0, - uBeforeIndex = 1, uBeforeGeneration = 0, - destinations = Seq( - (DestinationKind.T, 1, 0, 1), - (DestinationKind.U, 1, 0, 1)), last = true) - dut.io.tMapQUsed(0).expect(1.U) - dut.io.uMapQUsed(0).expect(1.U) - dut.io.tPhysicalUsed(0).expect(1.U) - dut.io.uPhysicalUsed(0).expect(1.U) - finishRecovery(dut) - - val lookup = Seq(UopShape(sources = Seq( - OperandClass.T -> 0, OperandClass.U -> 0))) - pokeReserve(dut, stid = 0, transactionId = 204, lookup) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.sourceMappings(0)(0).physicalTag.expect(0.U) - dut.io.reservation.sourceMappings(0)(1).physicalTag.expect(0.U) - - pokeReserve(dut, stid = 0, transactionId = 205, both) - dut.io.reserveReady.expect(true.B) - dut.io.reservation.allocations(0).mapping.sequence.index.expect(1.U) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(1.U) - dut.io.reservation.allocations(1).mapping.sequence.index.expect(1.U) - dut.io.reservation.allocations(1).mapping.physicalTag.expect(1.U) - } - } - - test("preserves wrapped survivor state across a zero-destination suffix row") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - for (transactionId <- 300 until 304) { - pokeReserve(dut, stid = 0, transactionId, oneT) - reserve(dut) - pokePublication(dut, stid = 0, transactionId, oneT) - publish(dut) - retireLocal(dut, DestinationKind.T, - sequenceIndex = transactionId - 300, - sequenceGeneration = 0, dealloc = false) - retireLocal(dut, DestinationKind.T, - sequenceIndex = transactionId - 300, - sequenceGeneration = 0, dealloc = true) - } - - pokeReserve(dut, stid = 0, transactionId = 304, oneT) - dut.io.reservation.allocations(0).mapping.sequence.index.expect(0.U) - dut.io.reservation.allocations(0).mapping.sequence.generation.expect(1.U) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 304, oneT) - publish(dut) - pokeReserve(dut, stid = 0, transactionId = 305, oneT) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 305, oneT) - publish(dut) - - val noDestination = Seq(UopShape()) - pokeReserve(dut, stid = 0, transactionId = 0, noDestination) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 0, noDestination) - publish(dut) - - startRecovery(dut, stid = 0, transactionId = 304) - sendRecoverySource(dut, triggerTransactionId = 304, - killedTransactionId = 0, killedUopIndex = 0, - tBeforeIndex = 2, tBeforeGeneration = 1, - uBeforeIndex = 0, uBeforeGeneration = 0, - destinations = Seq.empty, last = false) - sendRecoverySource(dut, triggerTransactionId = 304, - killedTransactionId = 305, killedUopIndex = 0, - tBeforeIndex = 1, tBeforeGeneration = 1, - uBeforeIndex = 0, uBeforeGeneration = 0, - destinations = Seq((DestinationKind.T, 1, 1, 1)), last = true) - finishRecovery(dut) - - dut.io.tMapQUsed(0).expect(1.U) - pokeReserve(dut, stid = 0, transactionId = 306, oneT) - dut.io.reservation.allocations(0).mapping.sequence.index.expect(1.U) - dut.io.reservation.allocations(0).mapping.sequence.generation.expect(1.U) - dut.io.reservation.allocations(0).mapping.physicalTag.expect(1.U) - } - } - - test("rejects malformed recovery authority and gives retire exact priority") { - val p = OooParams( - instructionDecodeWidth = 2, - decodedUopWidth = 2, - renameWidth = 2, - dispatchWidth = 2, - tPhysRegs = 4, - uPhysRegs = 4, - tuMapQDepthPerStid = 4) - simulate(new OooTURename(p)) { dut => - clear(dut) - val oneT = Seq(UopShape(destinations = Seq(DestinationKind.T -> 0))) - pokeReserve(dut, stid = 0, transactionId = 400, oneT) - reserve(dut) - pokePublication(dut, stid = 0, transactionId = 400, oneT) - publish(dut) - - dut.io.recoveryAuthorize.bits.poke( - 0.U.asTypeOf(dut.io.recoveryAuthorize.bits)) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.recoveryAuthorize.ready.expect(true.B) - dut.clock.step() - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryRejected.valid.expect(true.B) - dut.io.recoveryRejected.bits.tMapQCount.expect(1.U) - dut.io.recoveryBusy.expect(false.B) - - val command = dut.io.retireCommand.bits - command.poke(0.U.asTypeOf(command)) - command.valid.poke(true.B) - command.member.group.valid.poke(true.B) - command.member.group.peId.poke(2.U) - command.member.group.stid.poke(0.U) - command.member.group.ridSlot.poke(5.U) - command.member.group.ridGeneration.poke(3.U) - command.member.bid.valid.poke(true.B) - command.member.bid.value.poke(9.U) - command.member.brobGeneration.poke(4.U) - command.member.residentGeneration.poke(11.U) - command.kind.poke(DestinationKind.T) - command.sequence.valid.poke(true.B) - command.sequence.index.poke(0.U) - command.sequence.generation.poke(0.U) - command.dealloc.poke(false.B) - dut.io.retireCommand.valid.poke(true.B) - pokeRecoveryRequest(dut.io.recoveryAuthorize.bits, stid = 0, - transactionId = 400, uopIndex = 0, killTrigger = true) - dut.io.recoveryAuthorize.valid.poke(true.B) - dut.io.retireCommand.ready.expect(true.B) - dut.io.recoveryAuthorize.ready.expect(false.B) - dut.clock.step() - dut.io.retireCommand.valid.poke(false.B) - dut.io.recoveryAuthorize.valid.poke(false.B) - dut.io.recoveryBusy.expect(false.B) - dut.io.tMapQUsed(0).expect(1.U) - } - } -} diff --git a/chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala b/chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala new file mode 100644 index 00000000..b0361071 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala @@ -0,0 +1,583 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface.{D2AdmissionGroup, D3RenameGroup, OperandKind, + RecoveryPhase, UopClass} +import org.scalatest.funsuite.AnyFunSuite + +class RENUAtomicSpec extends AnyFunSuite with ChiselSim { + private def base(width: Int, stids: Int = 1): CoreParams = + ParamProfiles.forWidth(width).copy( + ooo = ParamProfiles.forWidth(width).ooo.copy( + stidCount = stids, + stidIdentityEntries = math.max(2, stids), + robGroupsPerStid = 8, + gprPhysRegs = if (stids == 1) 32 else 64, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 8)) + + private def clear(dut: RENU): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.toD3.ready.poke(true.B) + dut.io.prefixLimit.valid.poke(true.B) + dut.io.prefixLimit.bits.count.poke(1.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + dut.io.publicationIdentity.valid.poke(false.B) + dut.io.publicationIdentity.bits.poke( + 0.U.asTypeOf(dut.io.publicationIdentity.bits)) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + private def pokeGpr( + group: D2AdmissionGroup, + lane: Int, + id: Int, + dst: Int, + stid: Int = 0, + rid: Int = -1, + member: Int = -1): Unit = { + val ridSlot = if (rid >= 0) rid else lane + val memberIndex = if (member >= 0) member else lane + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(stid.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.stid.poke(stid.U) + row.uop.rob.ridSlot.poke(ridSlot.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke(memberIndex.U) + row.uop.uopClass.poke(UopClass.Alu) + row.uop.destinations(0).valid.poke(true.B) + row.uop.destinations(0).kind.poke(OperandKind.Gpr) + row.uop.destinations(0).atag.poke(dst.U) + row.uop.sources(0).valid.poke(true.B) + row.uop.sources(0).kind.poke(OperandKind.Gpr) + row.uop.sources(0).atag.poke(2.U) + if (group.groupCount.peek().litValue == 1) { + val intent = group.groups(0) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(stid.U) + intent.ridSlot.poke(ridSlot.U) + intent.ridGeneration.poke(5.U) + } + } + + private def pokeBoundary( + group: D2AdmissionGroup, + lane: Int, + id: Int, + stid: Int, + rid: Int): Unit = { + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(stid.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.stid.poke(stid.U) + row.uop.rob.ridSlot.poke(rid.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke(0.U) + row.uop.uopClass.poke(UopClass.Boundary) + row.uop.blockBoundary.poke(true.B) + if (group.groupCount.peek().litValue == 1) { + val intent = group.groups(0) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(stid.U) + intent.ridSlot.poke(rid.U) + intent.ridGeneration.poke(5.U) + } + } + + private def pokeLocalDest( + group: D2AdmissionGroup, + lane: Int, + id: Int, + rid: Int, + kinds: Seq[OperandKind.Type]): Unit = { + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(0.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.stid.poke(0.U) + row.uop.rob.ridSlot.poke(rid.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke(0.U) + row.uop.uopClass.poke(UopClass.Alu) + kinds.zipWithIndex.foreach { case (kind, dest) => + row.uop.destinations(dest).valid.poke(true.B) + row.uop.destinations(dest).kind.poke(kind) + row.uop.destinations(dest).atag.poke((dest + 1).U) + } + if (group.groupCount.peek().litValue == 1) { + val intent = group.groups(0) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(rid.U) + intent.ridGeneration.poke(5.U) + } + } + + private def driveOne( + dut: RENU, + id: Int, + dst: Int, + stid: Int = 0, + rid: Int = 0): Unit = { + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.prefixLimit.bits.count.poke(1.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + pokeGpr(dut.io.fromD2.bits, 0, id = id, dst = dst, stid = stid, rid = rid) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + } + + private def acceptHeld(dut: RENU): D3RenameGroup = { + dut.io.toD3.valid.expect(true.B) + val held = dut.io.toD3.bits.peek() + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.toD3.ready.poke(false.B) + held + } + + private def releaseRows(dut: RENU, rows: Seq[D3RenameGroup]): Unit = { + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(rows.length.U) + rows.zipWithIndex.foreach { case (row, lane) => + dut.io.release.bits.lanes(lane).valid.poke(true.B) + dut.io.release.bits.lanes(lane).rob.poke( + row.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(lane).history(0).poke(row.entries(0).history(0)) + } + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + } + + private def applyRecovery( + dut: RENU, + transactionId: Int, + triggerRid: Int, + survivingRid: Option[Int]): Unit = { + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(transactionId.U) + dut.io.recovery.prepare.bits.trigger.peId.poke(1.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.bits.trigger.ridSlot.poke(triggerRid.U) + dut.io.recovery.prepare.bits.trigger.ridGeneration.poke(5.U) + dut.io.recovery.prepare.bits.survivingTailValid.poke( + survivingRid.isDefined.B) + dut.io.recovery.prepare.bits.survivingTail.peId.poke(1.U) + dut.io.recovery.prepare.bits.survivingTail.stid.poke(0.U) + dut.io.recovery.prepare.bits.survivingTail.ridSlot.poke( + survivingRid.getOrElse(0).U) + dut.io.recovery.prepare.bits.survivingTail.ridGeneration.poke(5.U) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.recovery.apply.bits.poke(dut.io.recovery.prepare.bits.peek()) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + } + + test("held D3 arbitration does not switch when lower STID arrives") { + simulate(new RENU(base(2, stids = 2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + driveOne(dut, id = 10, dst = 1, stid = 1, rid = 1) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(1.U) + val stid1P = dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + + driveOne(dut, id = 11, dst = 1, stid = 0, rid = 1) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(1.U) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(stid1P.U) + + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(0x11.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(1.U) + dut.io.recovery.prepare.bits.trigger.ridSlot.poke(1.U) + dut.io.recovery.prepare.bits.trigger.ridGeneration.poke(5.U) + dut.io.recovery.prepare.valid.poke(true.B) + + // A recovery request targeting the currently presented D3 row cannot + // revoke or replace that Decoupled payload while it is stalled. + dut.io.recovery.prepare.ready.expect(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(1.U) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(stid1P.U) + + // Let the irrevocable target row fire first. The still-valid recovery + // request can then be accepted while the unrelated retained row fires. + dut.io.toD3.ready.poke(true.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(1.U) + dut.clock.step() + dut.io.recovery.prepare.ready.expect(true.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(0.U) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + // Prepare fences only the target STID; new unrelated work remains + // admissible while the recovery transaction is pending. + dut.io.toD3.ready.poke(false.B) + driveOne(dut, id = 12, dst = 2, stid = 0, rid = 2) + } + } + + test("two STID provisional P leases allocate unique physical tags") { + simulate(new RENU(base(2, stids = 2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + driveOne(dut, id = 20, dst = 1, stid = 1, rid = 1) + val stid1P = dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + + driveOne(dut, id = 21, dst = 1, stid = 0, rid = 1) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(0.U) + val stid0P = dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + assert(stid0P != stid1P) + } + } + + test("P release is all-or-none and a bad head row blocks later head plus one") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + driveOne(dut, id = 30, dst = 1, rid = 1) + val first = acceptHeld(dut) + val firstP = first.entries(0).history(0).ptag.litValue + + driveOne(dut, id = 31, dst = 1, rid = 2) + val second = acceptHeld(dut) + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(first.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).rob.ridSlot.poke(7.U) + dut.io.release.bits.lanes(0).history(0).poke(first.entries(0).history(0)) + dut.io.release.bits.lanes(1).valid.poke(true.B) + dut.io.release.bits.lanes(1).rob.poke(second.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(1).history(0).poke(second.entries(0).history(0)) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + + driveOne(dut, id = 32, dst = 2, rid = 3) + dut.io.toD3.bits.entries(0).history(0).ptag.expect((firstP + 2).U) + } + } + + test("P MapQ index and generation advance exactly across circular wrap") { + val params = base(2).copy(ooo = base(2).ooo.copy( + gprMapQDepthPerStid = 4)) + simulate(new RENU(params)) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + (0 until 3).foreach { i => + driveOne(dut, id = 40 + i, dst = 1 + i, rid = 1 + i) + val row = acceptHeld(dut) + releaseRows(dut, Seq(row)) + } + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(2.U) + dut.io.prefixLimit.bits.count.poke(2.U) + dut.io.prefixLimit.bits.groupCount.poke(2.U) + pokeGpr(dut.io.fromD2.bits, 0, id = 41, dst = 2, rid = 2, member = 0) + pokeGpr(dut.io.fromD2.bits, 1, id = 42, dst = 3, rid = 3, member = 0) + for ((rid, group) <- Seq(2, 3).zipWithIndex) { + val intent = dut.io.fromD2.bits.groups(group) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(rid.U) + intent.ridGeneration.poke(5.U) + } + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).history(0).pMapQIndex.expect(3.U) + dut.io.toD3.bits.entries(0).history(0).pMapQGeneration.expect(0.U) + dut.io.toD3.bits.entries(1).history(0).pMapQIndex.expect(0.U) + dut.io.toD3.bits.entries(1).history(0).pMapQGeneration.expect(1.U) + } + } + + test("zero-destination survivor preserves older P rows during recovery") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + driveOne(dut, id = 50, dst = 1, rid = 1) + val oldest = acceptHeld(dut) + val oldestP = oldest.entries(0).history(0).ptag.litValue + + driveOne(dut, id = 51, dst = 2, rid = 2) + val older = acceptHeld(dut) + val olderP = older.entries(0).history(0).ptag.litValue + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeBoundary(dut.io.fromD2.bits, 0, id = 52, stid = 0, rid = 3) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + acceptHeld(dut) + + driveOne(dut, id = 53, dst = 3, rid = 4) + val younger = acceptHeld(dut) + val youngerP = younger.entries(0).history(0).ptag.litValue + + applyRecovery(dut, transactionId = 0x52, triggerRid = 4, + survivingRid = Some(3)) + dut.io.debugPMap(0)(1).expect(oldestP.U) + dut.io.debugPMap(0)(2).expect(olderP.U) + + driveOne(dut, id = 54, dst = 4, rid = 5) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(youngerP.U) + } + } + + test("previous P generation is preserved when a recycled tag is overwritten") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + + driveOne(dut, id = 60, dst = 1, rid = 1) + val first = acceptHeld(dut) + releaseRows(dut, Seq(first)) + + driveOne(dut, id = 61, dst = 1, rid = 2) + val second = acceptHeld(dut) + releaseRows(dut, Seq(second)) + + driveOne(dut, id = 62, dst = 1, rid = 3) + val third = acceptHeld(dut) + assert(third.entries(0).history(0).pGeneration.litValue == 1) + assert(third.entries(0).history(0).previousPGeneration.litValue == 0) + releaseRows(dut, Seq(third)) + + driveOne(dut, id = 63, dst = 1, rid = 4) + dut.io.toD3.bits.entries(0).history(0).pGeneration.expect(1.U) + dut.io.toD3.bits.entries(0).history(0).previousPGeneration.expect(1.U) + dut.io.toD3.bits.entries(0).uop.destinations(0) + .previousPGeneration.expect(1.U) + } + } + + test("release is atomic across P T and U owners") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocalDest(dut.io.fromD2.bits, lane = 0, id = 70, rid = 1, + kinds = Seq(OperandKind.Gpr, OperandKind.T)) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val mixedPAndT = acceptHeld(dut) + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke( + mixedPAndT.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).history(0).poke( + mixedPAndT.entries(0).history(0)) + dut.io.release.bits.lanes(0).history(1).poke( + mixedPAndT.entries(0).history(1)) + dut.io.release.bits.lanes(0).history(1).tMapQGeneration.poke(7.U) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + + applyRecovery(dut, transactionId = 0x70, triggerRid = 1, + survivingRid = None) + dut.io.debugPMap(0)(1).expect(1.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocalDest(dut.io.fromD2.bits, lane = 0, id = 71, rid = 2, + kinds = Seq(OperandKind.T, OperandKind.U)) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val mixedTAndU = acceptHeld(dut) + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke( + mixedTAndU.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).history(0).poke( + mixedTAndU.entries(0).history(0)) + dut.io.release.bits.lanes(0).history(1).poke( + mixedTAndU.entries(0).history(1)) + dut.io.release.bits.lanes(0).history(1).uMapQGeneration.poke(7.U) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + + applyRecovery(dut, transactionId = 0x71, triggerRid = 2, + survivingRid = None) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocalDest(dut.io.fromD2.bits, lane = 0, id = 72, rid = 3, + kinds = Seq(OperandKind.T, OperandKind.U)) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.bits.entries(0).history(0).ttag.expect(0.U) + dut.io.toD3.bits.entries(0).history(1).utag.expect(0.U) + acceptHeld(dut) + applyRecovery(dut, transactionId = 0x72, triggerRid = 3, + survivingRid = None) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(2.U) + dut.io.prefixLimit.bits.count.poke(2.U) + dut.io.prefixLimit.bits.groupCount.poke(2.U) + pokeGpr(dut.io.fromD2.bits, 0, id = 73, dst = 1, rid = 4, member = 0) + pokeGpr(dut.io.fromD2.bits, 1, id = 74, dst = 2, rid = 5, member = 0) + for ((rid, group) <- Seq(4, 5).zipWithIndex) { + val intent = dut.io.fromD2.bits.groups(group) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(rid.U) + intent.ridGeneration.poke(5.U) + } + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val twoP = acceptHeld(dut) + + // A count prefix with a validity hole is malformed. It must not let the + // later lane commit the current head row. + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.lanes(1).valid.poke(true.B) + dut.io.release.bits.lanes(1).rob.poke(twoP.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(1).history(0).poke(twoP.entries(0).history(0)) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + applyRecovery(dut, transactionId = 0x73, triggerRid = 5, + survivingRid = None) + dut.io.debugPMap(0)(1).expect(1.U) + dut.io.debugPMap(0)(2).expect(2.U) + + driveOne(dut, id = 75, dst = 3, rid = 6) + val releaseDuringRecovery = acceptHeld(dut) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(0x74.U) + dut.io.recovery.prepare.bits.trigger.peId.poke(1.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepare.bits.trigger.ridSlot.poke(6.U) + dut.io.recovery.prepare.bits.trigger.ridGeneration.poke(5.U) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke( + releaseDuringRecovery.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).history(0).poke( + releaseDuringRecovery.entries(0).history(0)) + dut.io.release.valid.poke(true.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.apply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recovery.apply.bits.transactionId.poke(0x74.U) + dut.io.recovery.apply.bits.trigger.peId.poke(1.U) + dut.io.recovery.apply.bits.trigger.stid.poke(0.U) + dut.io.recovery.apply.bits.trigger.ridSlot.poke(6.U) + dut.io.recovery.apply.bits.trigger.ridGeneration.poke(5.U) + dut.io.recovery.apply.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) + + applyRecovery(dut, transactionId = 0x75, triggerRid = 6, + survivingRid = None) + dut.io.debugPMap(0)(3).expect(3.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGpr(dut.io.fromD2.bits, 1, id = 76, dst = 4, rid = 7) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(false.B) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/RENUSpec.scala b/chisel/src/test/scala/linxcore/ooo/RENUSpec.scala new file mode 100644 index 00000000..fd4f8e04 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/RENUSpec.scala @@ -0,0 +1,903 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface.{D2AdmissionGroup, D3RenameGroup, OperandKind, + UopClass} +import org.scalatest.funsuite.AnyFunSuite + +class RENUSpec extends AnyFunSuite with ChiselSim { + private def base(width: Int, stids: Int = 1): CoreParams = + ParamProfiles.forWidth(width).copy( + ooo = ParamProfiles.forWidth(width).ooo.copy( + stidCount = stids, + stidIdentityEntries = math.max(2, stids), + robGroupsPerStid = 8, + gprPhysRegs = if (stids == 1 && width <= 4) 32 else 64, + gprMapQDepthPerStid = if (width <= 4) 8 else 16, + tPhysRegs = if (width <= 4) 8 else 16, + uPhysRegs = if (width <= 4) 8 else 16, + tuMapQDepthPerStid = if (width <= 4) 8 else 16)) + + private def clear(dut: RENU): Unit = { + dut.io.fromD2.valid.poke(false.B) + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.toD3.ready.poke(true.B) + dut.io.prefixLimit.valid.poke(true.B) + dut.io.prefixLimit.bits.count.poke(1.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + dut.io.publicationIdentity.valid.poke(false.B) + dut.io.publicationIdentity.bits.poke( + 0.U.asTypeOf(dut.io.publicationIdentity.bits)) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(true.B) + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.prepare.bits.poke( + 0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepared.ready.poke(true.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke( + 0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke( + 0.U.asTypeOf(dut.io.recovery.abort.bits)) + } + + test("publishes an accepted prefix and retains exact P T U identities in the suffix") { + simulate(new RENU(base(4))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.bits.count.poke(4.U) + dut.io.fromD2.bits.groupCount.poke(4.U) + for (lane <- 0 until 4) { + val group = dut.io.fromD2.bits.groups(lane) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(lane.U) + group.ridGeneration.poke(5.U) + pokeGprAdd(dut.io.fromD2.bits, lane, id = 500 + lane, + dst = lane + 1, src0 = 0, src1 = 0, rid = lane) + } + dut.io.fromD2.bits.entries(2).uop.destinations(1).valid.poke(true.B) + dut.io.fromD2.bits.entries(2).uop.destinations(1).kind.poke(OperandKind.T) + dut.io.fromD2.bits.entries(3).uop.destinations(1).valid.poke(true.B) + dut.io.fromD2.bits.entries(3).uop.destinations(1).kind.poke(OperandKind.U) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + dut.io.candidate.valid.expect(true.B) + dut.io.candidate.bits.count.expect(4.U) + val suffixP2 = dut.io.candidate.bits.entries(2).history(0).ptag.peek().litValue + val suffixP3 = dut.io.candidate.bits.entries(3).history(0).ptag.peek().litValue + val suffixT = dut.io.candidate.bits.entries(2).history(1).ttag.peek().litValue + val suffixU = dut.io.candidate.bits.entries(3).history(1).utag.peek().litValue + + dut.io.prefixLimit.bits.count.poke(2.U) + dut.io.prefixLimit.bits.groupCount.poke(2.U) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.count.expect(2.U) + dut.io.toD3.bits.groupCount.expect(2.U) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + + dut.io.candidate.valid.expect(true.B) + dut.io.candidate.bits.count.expect(2.U) + dut.io.candidate.bits.groupCount.expect(2.U) + dut.io.candidate.bits.entries(0).history(0).ptag.expect(suffixP2.U) + dut.io.candidate.bits.entries(1).history(0).ptag.expect(suffixP3.U) + dut.io.candidate.bits.entries(0).history(1).ttag.expect(suffixT.U) + dut.io.candidate.bits.entries(1).history(1).utag.expect(suffixU.U) + dut.io.toD3.bits.count.expect(2.U) + dut.clock.step() + dut.io.toD3.valid.expect(false.B) + } + } + + private def pokeGprAdd( + group: D2AdmissionGroup, + lane: Int, + id: Int, + dst: Int, + src0: Int, + src1: Int, + stid: Int = 0, + rid: Int = -1): Unit = { + val ridSlot = if (rid >= 0) rid else 0 + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(stid.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.stid.poke(stid.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.ridSlot.poke(ridSlot.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke((lane % 4).U) + row.uop.uopClass.poke(UopClass.Alu) + row.uop.destinations(0).valid.poke(true.B) + row.uop.destinations(0).kind.poke(OperandKind.Gpr) + row.uop.destinations(0).atag.poke(dst.U) + row.uop.sources(0).valid.poke(true.B) + row.uop.sources(0).kind.poke(OperandKind.Gpr) + row.uop.sources(0).atag.poke(src0.U) + row.uop.sources(1).valid.poke(true.B) + row.uop.sources(1).kind.poke(OperandKind.Gpr) + row.uop.sources(1).atag.poke(src1.U) + if (group.groupCount.peek().litValue == 1) { + val intent = group.groups(0) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(stid.U) + intent.ridSlot.poke(ridSlot.U) + intent.ridGeneration.poke(5.U) + } + } + + private def pokeLocal( + group: D2AdmissionGroup, + lane: Int, + id: Int, + kind: OperandKind.Type, + relSrc: Option[Int], + stid: Int = 0, + rid: Int = -1): Unit = { + val ridSlot = if (rid >= 0) rid else 0 + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(stid.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.stid.poke(stid.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.ridSlot.poke(ridSlot.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke((lane % 4).U) + row.uop.uopClass.poke(UopClass.Alu) + row.uop.destinations(0).valid.poke(true.B) + row.uop.destinations(0).kind.poke(kind) + row.uop.destinations(0).relativeIndex.poke(0.U) + relSrc.foreach { rel => + row.uop.sources(0).valid.poke(true.B) + row.uop.sources(0).kind.poke(kind) + row.uop.sources(0).relativeIndex.poke(rel.U) + } + if (group.groupCount.peek().litValue == 1) { + val intent = group.groups(0) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(stid.U) + intent.ridSlot.poke(ridSlot.U) + intent.ridGeneration.poke(5.U) + } + } + + private def publishOne(dut: RENU): Unit = { + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.toD3.ready.poke(true.B) + } + + private def acceptHeld(dut: RENU): D3RenameGroup = { + dut.io.toD3.valid.expect(true.B) + val held = dut.io.toD3.bits.peek() + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + held + } + + private def releaseHeld(dut: RENU, held: D3RenameGroup, laneCount: Int): Unit = { + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(laneCount.U) + (0 until laneCount).foreach { lane => + dut.io.release.bits.lanes(lane).valid.poke(true.B) + dut.io.release.bits.lanes(lane).rob.poke( + held.entries(lane).uop.decoded.rob) + dut.io.release.bits.lanes(lane).epoch.poke( + held.entries(lane).uop.decoded.instruction.parent.identity.epoch) + dut.io.release.bits.lanes(lane).blockLast.poke( + held.entries(lane).uop.decoded.blockBoundary) + (0 until 2).foreach { dest => + dut.io.release.bits.lanes(lane).history(dest).poke( + held.entries(lane).history(dest)) + } + } + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + } + + test("renu-preserves-local-producer-epoch-across-consumer-epoch") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocal(dut.io.fromD2.bits, 0, id = 58, OperandKind.T, None, rid = 0) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + acceptHeld(dut) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocal(dut.io.fromD2.bits, 0, id = 59, OperandKind.T, Some(0), rid = 1) + dut.io.fromD2.bits.entries(0).uop.destinations(0).valid.poke(false.B) + dut.io.fromD2.bits.entries(0).uop.instruction.parent.identity.epoch + .poke(11.U) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.sources(0).localEpoch.expect(3.U) + } + } + + private def applyRecovery( + dut: RENU, + transactionId: Int, + triggerRid: Int, + surviving: Option[Int], + stid: Int = 0): Unit = { + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.bits.phase.poke( + linxcore.top.interface.RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(transactionId.U) + dut.io.recovery.prepare.bits.trigger.peId.poke(1.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(stid.U) + dut.io.recovery.prepare.bits.trigger.ridSlot.poke(triggerRid.U) + dut.io.recovery.prepare.bits.trigger.ridGeneration.poke(5.U) + surviving.foreach { rid => + dut.io.recovery.prepare.bits.survivingTailValid.poke(true.B) + dut.io.recovery.prepare.bits.survivingTail.peId.poke(1.U) + dut.io.recovery.prepare.bits.survivingTail.stid.poke(stid.U) + dut.io.recovery.prepare.bits.survivingTail.ridSlot.poke(rid.U) + dut.io.recovery.prepare.bits.survivingTail.ridGeneration.poke(5.U) + } + dut.io.recovery.prepare.ready.expect(true.B) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.recovery.apply.bits.phase.poke( + linxcore.top.interface.RecoveryPhase.Apply) + dut.io.recovery.apply.bits.transactionId.poke(transactionId.U) + dut.io.recovery.apply.bits.trigger.peId.poke(1.U) + dut.io.recovery.apply.bits.trigger.stid.poke(stid.U) + dut.io.recovery.apply.bits.trigger.ridSlot.poke(triggerRid.U) + dut.io.recovery.apply.bits.trigger.ridGeneration.poke(5.U) + surviving.foreach { rid => + dut.io.recovery.apply.bits.survivingTailValid.poke(true.B) + dut.io.recovery.apply.bits.survivingTail.peId.poke(1.U) + dut.io.recovery.apply.bits.survivingTail.stid.poke(stid.U) + dut.io.recovery.apply.bits.survivingTail.ridSlot.poke(rid.U) + dut.io.recovery.apply.bits.survivingTail.ridGeneration.poke(5.U) + } + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + } + + test("publishes P SMAP and same-prefix forwarding only on common D3 fire") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.prefixLimit.bits.count.poke(2.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 10, dst = 1, src0 = 2, src1 = 3) + pokeGprAdd(dut.io.fromD2.bits, 1, id = 11, dst = 4, src0 = 1, src1 = 5) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.count.expect(2.U) + dut.io.toD3.bits.entries(0).uop.destinations(0).ptagValid.expect(true.B) + val firstPTag = + dut.io.toD3.bits.entries(0).uop.destinations(0).ptag.peek().litValue + dut.io.toD3.bits.entries(1).uop.sources(0).ptag.expect(firstPTag.U) + dut.io.toD3.bits.entries(1).uop.sources(0).ready.expect(false.B) + + // The D2 fire retained only a provisional lease; the public SMAP has not + // changed until the common D3 publication fires. + dut.io.debugPMap(0)(1).expect(1.U) + dut.clock.step(2) + dut.io.debugPMap(0)(1).expect(1.U) + + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.debugPMap(0)(1).expect(firstPTag.U) + } + } + + test("allocates T and U as ordered relative namespaces independent from P") { + simulate(new RENU(base(4))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(3.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.prefixLimit.bits.count.poke(3.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + pokeLocal(dut.io.fromD2.bits, 0, id = 20, OperandKind.T, None) + pokeLocal(dut.io.fromD2.bits, 1, id = 21, OperandKind.T, Some(0)) + pokeLocal(dut.io.fromD2.bits, 2, id = 22, OperandKind.U, None) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.destinations(0).ttagValid.expect(true.B) + val firstT = + dut.io.toD3.bits.entries(0).uop.destinations(0).ttag.peek().litValue + dut.io.toD3.bits.entries(1).uop.sources(0).ttag.expect(firstT.U) + dut.io.toD3.bits.entries(2).uop.destinations(0).utagValid.expect(true.B) + dut.io.toD3.bits.entries(2).uop.destinations(0).ttagValid.expect(false.B) + dut.clock.step() + dut.io.debugTCount(0).expect(2.U) + dut.io.debugUCount(0).expect(1.U) + } + } + + test("rejects a whole prefix on T or U source underflow without mutation") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocal(dut.io.fromD2.bits, 0, id = 30, OperandKind.T, Some(0)) + dut.io.fromD2.valid.poke(true.B) + + dut.io.fromD2.ready.expect(false.B) + dut.clock.step() + dut.io.debugTCount(0).expect(0.U) + dut.io.toD3.valid.expect(false.B) + } + } + + test("same-lane dual GPR destinations carry WAW history in order") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 40, dst = 1, src0 = 2, src1 = 3) + val second = dut.io.fromD2.bits.entries(0).uop.destinations(1) + second.valid.poke(true.B) + second.kind.poke(OperandKind.Gpr) + second.atag.poke(1.U) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + val firstP = + dut.io.toD3.bits.entries(0).uop.destinations(0).ptag.peek().litValue + val finalP = + dut.io.toD3.bits.entries(0).uop.destinations(1).ptag.peek().litValue + dut.io.toD3.bits.entries(0).history(0).previousPtag.expect(1.U) + dut.io.toD3.bits.entries(0).history(1).previousPtag.expect(firstP.U) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.debugPMap(0)(1).expect(finalP.U) + } + } + + test("recovery apply is STID scoped and preserves non-target state") { + simulate(new RENU(base(2, stids = 2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.prefixLimit.bits.count.poke(1.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 50, dst = 1, src0 = 2, src1 = 3, + stid = 0, rid = 1) + publishOne(dut) + val survivingStid0P = dut.io.debugPMap(0)(1).peek().litValue + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 51, dst = 1, src0 = 2, src1 = 3, + stid = 0, rid = 2) + publishOne(dut) + val killedStid0P = dut.io.debugPMap(0)(1).peek().litValue + assert(killedStid0P != survivingStid0P) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 52, dst = 1, src0 = 2, src1 = 3, + stid = 1, rid = 1) + publishOne(dut) + val stid1P = dut.io.debugPMap(1)(1).peek().litValue + + applyRecovery(dut, transactionId = 0x55, triggerRid = 2, + surviving = Some(1), stid = 0) + + dut.io.debugPMap(0)(1).expect(survivingStid0P.U) + dut.io.debugPMap(1)(1).expect(stid1P.U) + } + } + + test("stale or non-head P release does not free the live tag") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 60, dst = 1, src0 = 2, src1 = 3) + publishOne(dut) + val live = dut.io.debugPMap(0)(1).peek().litValue + + dut.io.release.valid.poke(true.B) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.stid.poke(0.U) + dut.io.release.bits.lanes(0).rob.ridSlot.poke(7.U) + dut.io.release.bits.lanes(0).history(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).history(0).kind.poke(OperandKind.Gpr) + dut.io.release.bits.lanes(0).history(0).atag.poke(1.U) + dut.io.release.bits.lanes(0).history(0).ptag.poke(live.U) + dut.io.release.bits.lanes(0).history(0).previousPtag.poke(1.U) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.debugPMap(0)(1).expect(live.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 61, dst = 2, src0 = 1, src1 = 3) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.bits.entries(0).uop.destinations(0).ptag.expect((live + 1).U) + } + } + + test("out-of-range identity PTag release cannot alias a physical rename entry") { + val p = base(2) + simulate(new RENU(p)) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 62, dst = 1, + src0 = 2, src1 = 3, rid = 1) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val held = acceptHeld(dut) + val live = dut.io.debugPMap(0)(1).peek().litValue + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke( + held.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).history(0).poke( + held.entries(0).history(0)) + dut.io.release.bits.lanes(0).history(0).ptag.poke( + p.ooo.gprPhysRegs.U) + dut.io.release.valid.poke(true.B) + dut.io.releaseReady.expect(false.B, + "an out-of-range identity tag must not truncate onto physical tag zero") + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.debugPMap(0)(1).expect(live.U) + } + } + + test("recovery cancels an unpublished target-STID provisional row") { + simulate(new RENU(base(2, stids = 2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + val initialStid1P = dut.io.debugPMap(1)(1).peek().litValue + + // Hold an unrelated STID 0 row at D3 so the target STID 1 lease remains + // provisional but is not the irrevocable output transaction. + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 70, dst = 1, src0 = 2, src1 = 3, + stid = 0, rid = 1) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(0.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 71, dst = 1, src0 = 2, src1 = 3, + stid = 1, rid = 1) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.bits.phase.poke( + linxcore.top.interface.RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.transactionId.poke(0x70.U) + dut.io.recovery.prepare.bits.trigger.stid.poke(1.U) + dut.io.recovery.prepare.bits.trigger.ridSlot.poke(1.U) + dut.io.recovery.prepare.bits.trigger.ridGeneration.poke(5.U) + dut.io.recovery.prepare.ready.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(0.U) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + dut.io.recovery.apply.valid.poke(true.B) + dut.io.recovery.apply.bits.poke(dut.io.recovery.prepare.bits.peek()) + dut.io.recovery.apply.bits.phase.poke( + linxcore.top.interface.RecoveryPhase.Apply) + dut.clock.step() + dut.io.recovery.apply.valid.poke(false.B) + + // Only the unrelated STID 0 row remains. Publishing it must not reveal + // the cancelled target row afterward. + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity.stid + .expect(0.U) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.toD3.valid.expect(false.B) + dut.io.debugPMap(1)(1).expect(initialStid1P.U) + } + } + + test("dual-destination commit frees an older same-uop P tag in exact order") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 80, dst = 1, src0 = 2, src1 = 3, + rid = 1) + dut.io.fromD2.bits.entries(0).uop.destinations(1).valid.poke(true.B) + dut.io.fromD2.bits.entries(0).uop.destinations(1).kind.poke(OperandKind.Gpr) + dut.io.fromD2.bits.entries(0).uop.destinations(1).atag.poke(1.U) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val firstP = + dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + val secondP = + dut.io.toD3.bits.entries(0).history(1).ptag.peek().litValue + assert(firstP != secondP) + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke( + dut.io.toD3.bits.entries(0).uop.decoded.rob.peek()) + dut.io.release.bits.lanes(0).history(0).poke( + dut.io.toD3.bits.entries(0).history(0).peek()) + dut.io.release.bits.lanes(0).history(1).poke( + dut.io.toD3.bits.entries(0).history(1).peek()) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 81, dst = 2, src0 = 1, src1 = 3, + rid = 2) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(firstP.U) + } + } + + test("survivor recovery prunes suffix frees P tags and rewinds T and U") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.bits.count.poke(2.U) + dut.io.fromD2.bits.groupCount.poke(2.U) + dut.io.prefixLimit.bits.count.poke(2.U) + dut.io.prefixLimit.bits.groupCount.poke(2.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 90, dst = 1, src0 = 2, src1 = 3, + rid = 1) + pokeLocal(dut.io.fromD2.bits, 1, id = 91, OperandKind.T, None, rid = 2) + for ((rid, group) <- Seq(1, 2).zipWithIndex) { + val intent = dut.io.fromD2.bits.groups(group) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(rid.U) + intent.ridGeneration.poke(5.U) + } + dut.io.fromD2.bits.entries(1).uop.destinations(1).valid.poke(true.B) + dut.io.fromD2.bits.entries(1).uop.destinations(1).kind.poke(OperandKind.U) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val first = acceptHeld(dut) + val survivorP = first.entries(0).history(0).ptag.litValue + val killedPFreeCandidate = first.entries(1).history(0).ptag.litValue + assert(killedPFreeCandidate != survivorP) + dut.io.debugPMap(0)(1).expect(survivorP.U) + dut.io.debugTCount(0).expect(1.U) + dut.io.debugUCount(0).expect(1.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + dut.io.prefixLimit.bits.count.poke(1.U) + dut.io.prefixLimit.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 92, dst = 4, src0 = 1, src1 = 3, + rid = 3) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val suffixP = dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + acceptHeld(dut) + + applyRecovery(dut, transactionId = 0x90, triggerRid = 3, + surviving = Some(1)) + dut.io.debugPMap(0)(1).expect(survivorP.U) + dut.io.debugTCount(0).expect(0.U) + dut.io.debugUCount(0).expect(0.U) + + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 93, dst = 5, src0 = 1, src1 = 3, + rid = 4) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(suffixP.U) + } + } + + test("stale T and U releases after wrap do not advance exact heads") { + simulate(new RENU(base(2).copy(ooo = base(2).ooo.copy( + tPhysRegs = 4, + uPhysRegs = 4, + tuMapQDepthPerStid = 4)))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + (0 until 4).foreach { i => + dut.io.fromD2.bits.poke(0.U.asTypeOf(dut.io.fromD2.bits)) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeLocal(dut.io.fromD2.bits, 0, id = 100 + i, OperandKind.T, None, + rid = i) + dut.io.fromD2.bits.entries(0).uop.destinations(1).valid.poke(true.B) + dut.io.fromD2.bits.entries(0).uop.destinations(1).kind.poke(OperandKind.U) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + acceptHeld(dut) + } + dut.io.debugTCount(0).expect(4.U) + dut.io.debugUCount(0).expect(4.U) + + dut.io.release.bits.count.poke(1.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.stid.poke(0.U) + dut.io.release.bits.lanes(0).rob.ridSlot.poke(3.U) + dut.io.release.bits.lanes(0).rob.ridGeneration.poke(5.U) + dut.io.release.bits.lanes(0).history(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).history(0).kind.poke(OperandKind.T) + dut.io.release.bits.lanes(0).history(0).ttag.poke(0.U) + dut.io.release.bits.lanes(0).history(0).tGeneration.poke(0.U) + dut.io.release.bits.lanes(0).history(1).valid.poke(true.B) + dut.io.release.bits.lanes(0).history(1).kind.poke(OperandKind.U) + dut.io.release.bits.lanes(0).history(1).utag.poke(0.U) + dut.io.release.bits.lanes(0).history(1).uGeneration.poke(0.U) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.debugTCount(0).expect(4.U) + dut.io.debugUCount(0).expect(4.U) + } + } + + test("D3 backpressure keeps payload stable and prevents duplicate mutation") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.toD3.ready.poke(false.B) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + pokeGprAdd(dut.io.fromD2.bits, 0, id = 110, dst = 1, src0 = 2, src1 = 3) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + val ptag = dut.io.toD3.bits.entries(0).history(0).ptag.peek().litValue + val instructionId = + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity + .instructionId.peek().litValue + val ridSlot = + dut.io.toD3.bits.entries(0).uop.decoded.rob.ridSlot.peek().litValue + dut.clock.step(3) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).history(0).ptag.expect(ptag.U) + dut.io.toD3.bits.entries(0).uop.decoded.instruction.parent.identity + .instructionId.expect(instructionId.U) + dut.io.toD3.bits.entries(0).uop.decoded.rob.ridSlot.expect(ridSlot.U) + dut.io.debugPMap(0)(1).expect(1.U) + dut.io.toD3.ready.poke(true.B) + dut.clock.step() + dut.io.debugPMap(0)(1).expect(ptag.U) + dut.clock.step(2) + dut.io.debugPMap(0)(1).expect(ptag.U) + } + } + + test("true early-complete boundary retains a sidecar without allocating maps") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + val row = dut.io.fromD2.bits.entries(0) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(0.U) + row.uop.instruction.parent.identity.instructionId.poke(120.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.stid.poke(0.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.ridSlot.poke(1.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.uopClass.poke(UopClass.Boundary) + row.uop.blockBoundary.poke(true.B) + row.uop.earlyComplete.poke(true.B) + val group = dut.io.fromD2.bits.groups(0) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(1.U) + group.ridGeneration.poke(5.U) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.count.expect(1.U) + dut.io.toD3.bits.entries(0).earlyRobComplete.expect(true.B) + dut.io.toD3.bits.entries(0).history(0).valid.expect(false.B) + dut.io.toD3.bits.entries(0).history(1).valid.expect(false.B) + dut.io.debugPMap(0)(1).expect(1.U) + dut.io.debugTCount(0).expect(0.U) + dut.io.debugUCount(0).expect(0.U) + } + } + + test("fused executable block boundary remains dispatchable") { + simulate(new RENU(base(2))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(1.U) + dut.io.fromD2.bits.groupCount.poke(1.U) + val row = dut.io.fromD2.bits.entries(0) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(0.U) + row.uop.instruction.parent.identity.instructionId.poke(121.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.stid.poke(0.U) + row.uop.rob.peId.poke(1.U) + row.uop.rob.ridSlot.poke(1.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.uopClass.poke(UopClass.Alu) + row.uop.blockStart.poke(true.B) + row.uop.blockStop.poke(true.B) + row.uop.blockBoundary.poke(true.B) + row.uop.earlyComplete.poke(false.B) + val group = dut.io.fromD2.bits.groups(0) + group.valid.poke(true.B) + group.peId.poke(1.U) + group.stid.poke(0.U) + group.ridSlot.poke(1.U) + group.ridGeneration.poke(5.U) + dut.io.fromD2.valid.poke(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.entries(0).earlyRobComplete.expect(false.B) + } + } + + test("unequal P T U and ROB capacities accept one legal prefix") { + val p = base(6).copy(ooo = base(6).ooo.copy( + robGroupsPerStid = 16, + gprPhysRegs = 64, + gprMapQDepthPerStid = 16, + tPhysRegs = 16, + uPhysRegs = 32, + tuMapQDepthPerStid = 32)) + simulate(new RENU(p)) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(6.U) + dut.io.fromD2.bits.groupCount.poke(2.U) + dut.io.prefixLimit.bits.count.poke(6.U) + dut.io.prefixLimit.bits.groupCount.poke(2.U) + (0 until 6).foreach { lane => + pokeGprAdd(dut.io.fromD2.bits, lane, id = 130 + lane, + dst = lane % 6, src0 = 1, src1 = 2, rid = lane / 3) + dut.io.fromD2.bits.entries(lane).uop.rob.memberIndex.poke((lane % 3).U) + } + for (group <- 0 until 2) { + val intent = dut.io.fromD2.bits.groups(group) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(group.U) + intent.ridGeneration.poke(5.U) + } + dut.io.fromD2.bits.entries(4).uop.destinations(0).kind.poke(OperandKind.T) + dut.io.fromD2.bits.entries(5).uop.destinations(0).kind.poke(OperandKind.U) + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.count.expect(6.U) + dut.io.toD3.bits.entries(4).history(0).kind.expect(OperandKind.T) + dut.io.toD3.bits.entries(5).history(0).kind.expect(OperandKind.U) + } + } + + test("behavioral W2 W4 W6 and W8 each accept an atomic prefix") { + Seq(2, 4, 6, 8).foreach { width => + simulate(new RENU(base(width))) { dut => + clear(dut) + dut.io.fromD2.bits.count.poke(width.U) + val groupCount = (width + 3) / 4 + dut.io.fromD2.bits.groupCount.poke(groupCount.U) + dut.io.prefixLimit.bits.count.poke(width.U) + dut.io.prefixLimit.bits.groupCount.poke(groupCount.U) + (0 until width).foreach { lane => + pokeGprAdd(dut.io.fromD2.bits, lane, id = 140 + lane, + dst = (lane % 6) + 1, src0 = 2, src1 = 3, rid = lane / 4) + } + for (group <- 0 until groupCount) { + val intent = dut.io.fromD2.bits.groups(group) + intent.valid.poke(true.B) + intent.peId.poke(1.U) + intent.stid.poke(0.U) + intent.ridSlot.poke(group.U) + intent.ridGeneration.poke(5.U) + } + dut.io.fromD2.valid.poke(true.B) + dut.io.fromD2.ready.expect(true.B) + dut.clock.step() + dut.io.fromD2.valid.poke(false.B) + dut.io.toD3.valid.expect(true.B) + dut.io.toD3.bits.count.expect(width.U) + } + } + } + + test("elaborates W2 W4 W6 and W8 with central generation widths") { + Seq(2, 4, 6, 8).foreach { width => + val p = base(width) + val d3 = new linxcore.top.interface.D3RenameGroup(p) + + assert(d3.entries.head.history.head.pGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(d3.entries.head.history.head.pMapQGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(d3.entries.head.history.head.tGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(d3.entries.head.tSeqBefore.generation.getWidth == + p.ooo.localSeqGenerationWidth) + assert(d3.entries.head.history.head.uGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(d3.entries.length == width) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/RecoveryControlBarrierSpec.scala b/chisel/src/test/scala/linxcore/ooo/RecoveryControlBarrierSpec.scala new file mode 100644 index 00000000..86479858 --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/RecoveryControlBarrierSpec.scala @@ -0,0 +1,84 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class RecoveryControlBarrierSpec extends AnyFunSuite with ChiselSim { + private val p: CoreParams = { + val base = ParamProfiles.W4 + base.copy(ooo = base.ooo.copy( + stidCount = 2, + stidIdentityEntries = 2, + robGroupsPerStid = 4, + robBankCount = 4, + brobEntriesPerStid = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 64)) + } + + private def clear(dut: RecoveryControl): Unit = { + dut.io.events.foreach { event => + event.valid.poke(false.B) + event.bits.poke(0.U.asTypeOf(event.bits)) + } + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.abort.poke(false.B) + dut.io.robCandidateStatus.foreach { status => + status.valid.poke(false.B) + status.bits.poke(0.U.asTypeOf(status.bits)) + } + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepared.bits.poke(0.U.asTypeOf(dut.io.robPrepared.bits)) + dut.io.targets.foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + } + + test("prepare fans out once and common apply waits for every acknowledgement") { + simulate(new RecoveryControl(p, targetCount = 3)) { dut => + clear(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0x80.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.robCandidateStatus(0).valid.poke(true.B) + dut.io.robCandidateStatus(0).bits.transactionId.poke(0x80.U) + dut.io.robCandidateStatus(0).bits.trigger.stid.poke(0.U) + dut.io.robCandidateStatus(0).bits.eligible.poke(true.B) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robCandidateStatus(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + + dut.io.targets.foreach(_.prepare.valid.expect(true.B)) + dut.clock.step() + dut.io.targets.foreach(_.prepare.valid.expect(false.B)) + for (target <- 0 until 2) { + dut.io.targets(target).prepared.valid.poke(true.B) + dut.io.targets(target).prepared.bits.poke( + dut.io.targets(target).prepare.bits.peek()) + } + dut.clock.step() + dut.io.targets.foreach(_.apply.valid.expect(false.B)) + + dut.io.targets(0).prepared.valid.poke(false.B) + dut.io.targets(1).prepared.valid.poke(false.B) + dut.io.targets(2).prepared.valid.poke(true.B) + dut.io.targets(2).prepared.bits.poke( + dut.io.targets(2).prepare.bits.peek()) + dut.clock.step() + dut.io.targets.foreach(_.apply.valid.expect(true.B)) + } + } +} diff --git a/chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala b/chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala new file mode 100644 index 00000000..a3bda60f --- /dev/null +++ b/chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala @@ -0,0 +1,234 @@ +package linxcore.ooo + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface.{D2AdmissionGroup, D3RenameGroup, OperandKind, + RecoveryPhase, UopClass} +import org.scalatest.funsuite.AnyFunSuite + +class TURenameSequenceSpec extends AnyFunSuite with ChiselSim { + private def params(width: Int): CoreParams = + ParamProfiles.forWidth(width).copy( + ooo = ParamProfiles.forWidth(width).ooo.copy( + stidCount = 1, + robGroupsPerStid = 8, + gprPhysRegs = 32, + gprMapQDepthPerStid = 8, + tPhysRegs = 8, + uPhysRegs = 8, + tuMapQDepthPerStid = 16)) + + private def clear(dut: TURename): Unit = { + dut.io.prepare.valid.poke(false.B) + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.publish.valid.poke(false.B) + dut.io.publish.bits.poke(0.U.asTypeOf(dut.io.publish.bits)) + dut.io.release.valid.poke(false.B) + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.releaseApply.poke(true.B) + dut.io.recoveryApply.valid.poke(false.B) + dut.io.recoveryApply.bits.poke(0.U.asTypeOf(dut.io.recoveryApply.bits)) + } + + private def pokeLocal( + group: D2AdmissionGroup, + lane: Int, + id: Int, + kind: OperandKind.Type, + relSrc: Option[Int] = None, + destValid: Boolean = true, + rid: Int = -1): Unit = { + val ridSlot = if (rid >= 0) rid else lane + val row = group.entries(lane) + row.uop.valid.poke(true.B) + row.uop.instruction.parent.identity.peId.poke(1.U) + row.uop.instruction.parent.identity.stid.poke(0.U) + row.uop.instruction.parent.identity.instructionId.poke(id.U) + row.uop.instruction.parent.identity.epoch.poke(3.U) + row.uop.rob.stid.poke(0.U) + row.uop.rob.ridSlot.poke(ridSlot.U) + row.uop.rob.ridGeneration.poke(5.U) + row.uop.rob.memberIndex.poke((lane % 4).U) + row.uop.uopClass.poke(UopClass.Alu) + row.uop.destinations(0).valid.poke(destValid.B) + row.uop.destinations(0).kind.poke(kind) + relSrc.foreach { rel => + row.uop.sources(0).valid.poke(true.B) + row.uop.sources(0).kind.poke(kind) + row.uop.sources(0).relativeIndex.poke(rel.U) + } + } + + private def publishPrepared(dut: TURename, prepared: D3RenameGroup): Unit = { + dut.io.publish.bits.poke(prepared) + dut.io.publish.valid.poke(true.B) + dut.clock.step() + dut.io.publish.valid.poke(false.B) + } + + test("tu-mapq-sequence-snapshots-use-mapq-depth") { + val p = params(2) + val d3 = new D3RenameGroup(p) + + assert(d3.entries.head.tSeqBefore.tag.getWidth == + chisel3.util.log2Ceil(p.ooo.tuMapQDepthPerStid)) + assert(d3.entries.head.uSeqBefore.tag.getWidth == + chisel3.util.log2Ceil(p.ooo.tuMapQDepthPerStid)) + } + + test("tu-prefix-sequence-and-physical-capacity-are-independent") { + val p = params(4) + simulate(new TURename(p)) { dut => + clear(dut) + dut.io.prepare.bits.count.poke(3.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 10, OperandKind.T) + pokeLocal(dut.io.prepare.bits, 1, id = 11, OperandKind.T) + pokeLocal(dut.io.prepare.bits, 2, id = 12, OperandKind.T, relSrc = Some(0)) + dut.io.prepare.valid.poke(true.B) + + dut.io.prepareReady.expect(true.B) + dut.io.prepared.entries(0).tSeqBefore.tag.expect(0.U) + dut.io.prepared.entries(1).tSeqBefore.tag.expect(1.U) + dut.io.prepared.entries(2).tSeqBefore.tag.expect(2.U) + dut.io.prepared.entries(2).uop.sources(0).ttag.expect(1.U) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(4.U) + dut.io.prepare.bits.groupCount.poke(1.U) + (0 until 4).foreach { lane => + pokeLocal(dut.io.prepare.bits, lane, id = 20 + lane, OperandKind.U) + } + dut.io.prepareReady.expect(true.B) + } + } + + test("tu-release-requires-all-exact-prefix-and-zero-dest-survivor") { + val p = params(2) + simulate(new TURename(p)) { dut => + clear(dut) + dut.io.prepare.bits.count.poke(2.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 40, OperandKind.T, destValid = false, + rid = 1) + pokeLocal(dut.io.prepare.bits, 1, id = 41, OperandKind.T, rid = 2) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + val prepared = dut.io.prepared.peek() + publishPrepared(dut, prepared) + dut.io.debugTCount(0).expect(1.U) + + dut.io.recoveryApply.bits.phase.poke(RecoveryPhase.Apply) + dut.io.recoveryApply.bits.transactionId.poke(0x40.U) + dut.io.recoveryApply.bits.trigger.stid.poke(0.U) + dut.io.recoveryApply.bits.trigger.ridSlot.poke(2.U) + dut.io.recoveryApply.bits.trigger.ridGeneration.poke(5.U) + dut.io.recoveryApply.bits.survivingTailValid.poke(true.B) + dut.io.recoveryApply.bits.survivingTail.stid.poke(0.U) + dut.io.recoveryApply.bits.survivingTail.ridSlot.poke(1.U) + dut.io.recoveryApply.bits.survivingTail.ridGeneration.poke(5.U) + dut.io.recoveryApply.valid.poke(true.B) + dut.clock.step() + dut.io.recoveryApply.valid.poke(false.B) + dut.io.debugTCount(0).expect(0.U) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(2.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 50, OperandKind.T, rid = 3) + pokeLocal(dut.io.prepare.bits, 1, id = 51, OperandKind.T, rid = 4) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + val twoRows = dut.io.prepared.peek() + publishPrepared(dut, twoRows) + dut.io.debugTCount(0).expect(2.U) + + dut.io.release.bits.count.poke(2.U) + dut.io.release.bits.lanes(0).valid.poke(true.B) + dut.io.release.bits.lanes(0).rob.poke(twoRows.entries(0).uop.decoded.rob) + dut.io.release.bits.lanes(0).history(0).poke(twoRows.entries(0).history(0)) + dut.io.release.bits.lanes(1).valid.poke(true.B) + dut.io.release.bits.lanes(1).rob.poke(twoRows.entries(1).uop.decoded.rob) + dut.io.release.bits.lanes(1).history(0).poke(twoRows.entries(1).history(0)) + dut.io.release.bits.lanes(1).history(0).tGeneration.poke(7.U) + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + dut.io.debugTCount(0).expect(2.U) + } + } + + test("relative-source-preserves-producer-epoch-across-consumer-epoch") { + simulate(new TURename(params(2))) { dut => + clear(dut) + dut.io.prepare.bits.count.poke(1.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 70, OperandKind.T, rid = 0) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + val producer = dut.io.prepared.peek() + publishPrepared(dut, producer) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(1.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 71, OperandKind.T, + relSrc = Some(0), destValid = false, rid = 1) + dut.io.prepare.bits.entries(0).uop.instruction.parent.identity.epoch + .poke(11.U) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + dut.io.prepared.entries(0).uop.sources(0).localEpoch.expect(3.U) + } + } + + test("physical T tags wrap at eight entries inside a 32-entry identity namespace") { + val p = params(4) + assert(p.ooo.tPhysRegs == 8) + assert(p.ooo.tTagIdentityEntries == 32) + assert(p.ooo.tTagWidth == 5) + simulate(new TURename(p)) { dut => + clear(dut) + val published = scala.collection.mutable.ArrayBuffer.empty[D3RenameGroup] + for (prefix <- 0 until 2) { + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(4.U) + dut.io.prepare.bits.groupCount.poke(1.U) + for (lane <- 0 until 4) { + pokeLocal(dut.io.prepare.bits, lane, id = 80 + prefix * 4 + lane, + OperandKind.T, rid = prefix * 4 + lane) + } + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + val row = dut.io.prepared.peek() + published += row + publishPrepared(dut, row) + } + + dut.io.release.bits.poke(0.U.asTypeOf(dut.io.release.bits)) + dut.io.release.bits.count.poke(4.U) + for (lane <- 0 until 4) { + dut.io.release.bits.lanes(lane).valid.poke(true.B) + dut.io.release.bits.lanes(lane).rob.poke( + published.head.entries(lane).uop.decoded.rob) + dut.io.release.bits.lanes(lane).history(0).poke( + published.head.entries(lane).history(0)) + } + dut.io.release.valid.poke(true.B) + dut.clock.step() + dut.io.release.valid.poke(false.B) + + dut.io.prepare.bits.poke(0.U.asTypeOf(dut.io.prepare.bits)) + dut.io.prepare.bits.count.poke(1.U) + dut.io.prepare.bits.groupCount.poke(1.U) + pokeLocal(dut.io.prepare.bits, 0, id = 88, OperandKind.T, rid = 0) + dut.io.prepare.valid.poke(true.B) + dut.io.prepareReady.expect(true.B) + dut.io.prepared.entries(0).history(0).ttag.expect(0.U) + dut.io.prepared.entries(0).history(0).tGeneration.expect(1.U) + dut.io.prepared.entries(0).history(0).tMapQIndex.expect(8.U) + dut.io.prepared.entries(0).history(0).tMapQGeneration.expect(0.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/params/CoreConfigurationSpec.scala b/chisel/src/test/scala/linxcore/params/CoreConfigurationSpec.scala new file mode 100644 index 00000000..e618ab93 --- /dev/null +++ b/chisel/src/test/scala/linxcore/params/CoreConfigurationSpec.scala @@ -0,0 +1,270 @@ +package linxcore.params + +import org.scalatest.funsuite.AnyFunSuite + +class CoreConfigurationSpec extends AnyFunSuite { + private val supportedWidths = Seq(2, 4, 6, 8) + + test("W2 W4 W6 and W8 profiles keep every principal box width coherent") { + supportedWidths.foreach { width => + val p = ParamProfiles.forWidth(width) + + ParamChecks.validate(p) + assert(p.widths == WidthParams.uniform(width)) + assert(p.ifu.fetchWidth == width) + assert(p.ifu.ctuTransferWidth == width) + assert(p.ctu.inputWidth == width) + assert(p.ctu.outputWidth == width) + assert(p.ooo.decodeWidth == width) + assert(p.ooo.renameWidth == width) + assert(p.ooo.dispatchWidth == width) + assert(p.ooo.d3PrefixWidth == width) + assert(p.iex.issueWidth == width) + } + } + + test("W4 is the default profile and preserves the requested physical topology") { + val p = ParamProfiles.Default + + assert(p == ParamProfiles.W4) + assert(CoreParams() == ParamProfiles.W4) + assert(p.iex.aluPipes == 2) + assert(p.iex.bruPipes == 1) + assert(p.iex.aguPipes == 2) + assert(p.iex.stdPipes == 2) + assert(p.iex.systemMulticycleQueues == 1) + assert(p.iex.cmdIssueQueues == 1) + assert(p.lsu.loadPipes == 2) + assert(p.lsu.storePipes == 2) + assert(p.ooo.gprTagGenerationWidth == 16) + assert(p.ooo.localSeqGenerationWidth == 16) + } + + test("unsupported profile width fails before a configuration is published") { + val error = intercept[IllegalArgumentException] { + ParamProfiles.forWidth(3) + } + + assert(error.getMessage.contains("supported widths are 2, 4, 6, and 8")) + } + + test("CTU cannot publish a wider prefix than IFU can transfer") { + val base = ParamProfiles.W4 + val error = intercept[IllegalArgumentException] { + base.copy( + widths = base.widths.copy(fetchWidth = 2, ctuOutputWidth = 4), + ifu = base.ifu.copy(fetchWidth = 2, ctuTransferWidth = 4)) + } + + assert(error.getMessage.contains("IFU fetch width must cover CTU output")) + } + + test("OOO dispatch covers the complete accepted D3 prefix") { + val base = ParamProfiles.W4 + val error = intercept[IllegalArgumentException] { + base.copy( + widths = base.widths.copy(dispatchWidth = 2), + ooo = base.ooo.copy(dispatchWidth = 2, d3PrefixWidth = 4)) + } + + assert(error.getMessage.contains("dispatch width must cover the D3 prefix")) + } + + test("LSU requires at least one load pipe and one store pipe") { + val base = ParamProfiles.W4 + + val loadError = intercept[IllegalArgumentException] { + base.copy(lsu = base.lsu.copy(loadPipes = 0)) + } + val storeError = intercept[IllegalArgumentException] { + base.copy(lsu = base.lsu.copy(storePipes = 0)) + } + + assert(loadError.getMessage.contains("load pipe count must be positive")) + assert(storeError.getMessage.contains("store pipe count must be positive")) + } + + test("STQ covers one atomic STD reservation batch and pipe counts match") { + val base = ParamProfiles.W4 + + val capacityError = intercept[IllegalArgumentException] { + base.copy(lsu = base.lsu.copy(storeQueueEntries = 2)) + } + assert(capacityError.getMessage.contains( + "store queue must cover one atomic STD reservation batch")) + + val couplingError = intercept[IllegalArgumentException] { + base.copy(iex = base.iex.copy(stdPipes = 1)) + } + assert(couplingError.getMessage.contains( + "STD pipe count must match the LSU store pipe count")) + } + + test("lower-memory ledgers cover retained store and SCB capacities") { + val base = ParamProfiles.W4 + + val storeError = intercept[IllegalArgumentException] { + ParamChecks.validate(base.copy(lsu = base.lsu.copy( + lowerMemoryTransactionsPerLane = 4, + storeCommitQueueEntries = 5, + scbEntries = 4, + loadMissQueueEntries = 4))) + } + assert(storeError.getMessage.contains("store commit queue")) + + val scbError = intercept[IllegalArgumentException] { + ParamChecks.validate(base.copy(lsu = base.lsu.copy( + lowerMemoryTransactionsPerLane = 4, + storeCommitQueueEntries = 4, + scbEntries = 5, + loadMissQueueEntries = 4))) + } + assert(scbError.getMessage.contains("SCB")) + } + + test("BROB entries per STID must preserve a nonzero BID width") { + val base = ParamProfiles.W4 + + val singletonError = intercept[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy(brobEntriesPerStid = 1)) + } + + assert(singletonError.getMessage.contains( + "BROB entries per STID must be a power of two and at least 2")) + assert(base.copy(ooo = base.ooo.copy(brobEntriesPerStid = 4)).nativeBidWidth == + base.nativeBidWidth) + assert(base.nativeBidWidth == 8) + } + + test("module-local widths cannot drift from the central width contract") { + val base = ParamProfiles.W6 + val error = intercept[IllegalArgumentException] { + base.copy(iex = base.iex.copy(issueWidth = 4)) + } + + assert(error.getMessage.contains("IEX issue width must match WidthParams")) + } + + test("rename generation widths are centrally configured and fail closed") { + val base = ParamProfiles.W4 + val custom = base.copy(ooo = base.ooo.copy( + gprTagGenerationWidth = 12, + localSeqGenerationWidth = 10, + gprPhysRegs = 128, + gprMapQDepthPerStid = 16)) + + assert(custom.ooo.gprTagGenerationWidth == 12) + assert(custom.ooo.localSeqGenerationWidth == 10) + assert(custom.ooo.gprPhysRegs == 128) + assert(custom.ooo.gprMapQDepthPerStid == 16) + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy(gprTagGenerationWidth = 0)) + } + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy(localSeqGenerationWidth = 0)) + } + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy(gprMapQDepthPerStid = 4)) + } + } + + test("rename physical and MapQ capacities independently cover one prefix") { + val wide = ParamProfiles.W8 + + assertThrows[IllegalArgumentException] { + wide.copy(ooo = wide.ooo.copy(stidCount = 1, gprPhysRegs = 32)) + } + assertThrows[IllegalArgumentException] { + wide.copy(ooo = wide.ooo.copy(tPhysRegs = 8)) + } + assertThrows[IllegalArgumentException] { + wide.copy(ooo = wide.ooo.copy(uPhysRegs = 8)) + } + assertThrows[IllegalArgumentException] { + wide.copy(ooo = wide.ooo.copy(tuMapQDepthPerStid = 8)) + } + } + + test("identity namespaces fail closed when they do not cover physical storage") { + val base = ParamProfiles.W4 + + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy( + robIdentityGroupsPerStid = 4, + robGroupsPerStid = 8)) + } + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy( + robIdentityMembersPerGroup = 2, + maxInstructionsPerRobGroup = 4)) + } + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy( + uopIdentityEntriesPerInstruction = 8, + maxUopsPerInstruction = 12)) + } + assertThrows[IllegalArgumentException] { + base.copy(ooo = base.ooo.copy( + gprTagIdentityEntries = 32, + gprPhysRegs = 64)) + } + } + + test("DTU trace packets cover a complete IFU transfer prefix") { + val base = ParamProfiles.W8 + val error = intercept[IllegalArgumentException] { + base.copy(dtu = base.dtu.copy(traceWidth = 4)) + } + + assert(error.getMessage.contains("DTU trace width must cover the IFU transfer")) + } + + test("legacy parameter records convert to the central profile without state") { + val legacyCore = linxcore.common.CoreParams( + robEntries = 64, + commitWidth = 2, + lsidWidth = 40) + val convertedCore = legacyCore.toMainline(profileWidth = 2) + val legacyOoo = linxcore.ooo.OooParams( + stidCount = 2, + instructionDecodeWidth = 2, + decodedUopWidth = 4, + renameWidth = 4, + dispatchWidth = 4, + pTagGenerationWidth = 13, + localSeqGenerationWidth = 11) + val convertedOoo = legacyOoo.toMainline + + assert(convertedCore.widths.decodeWidth == 2) + assert(convertedCore.ooo.robCapacityPerStid == 64) + assert(convertedCore.widths.retireWidth == 2) + assert(convertedCore.lsidWidth == 40) + assert(convertedOoo.stidCount == 2) + assert(convertedOoo.decodeWidth == 2) + assert(convertedOoo.renameWidth == 4) + assert(convertedOoo.dispatchWidth == 4) + assert(convertedOoo.gprTagGenerationWidth == 13) + assert(convertedOoo.localSeqGenerationWidth == 11) + } + + test("central parameters construct value-only legacy adapters") { + val mainline = ParamProfiles.W2 + val legacyCore = linxcore.common.CoreParams.fromMainline(mainline) + val legacyOoo = linxcore.ooo.OooParams.fromMainline(mainline.ooo) + val legacyWideOoo = + linxcore.ooo.OooParams.fromMainline(ParamProfiles.W8.ooo) + + assert(legacyCore.robEntries == mainline.ooo.robCapacityPerStid) + assert(legacyCore.commitWidth == mainline.widths.retireWidth) + assert(legacyCore.scalarLsu.liqEntries == mainline.lsu.loadQueueEntries) + assert(legacyCore.scalarLsu.stqEntries == mainline.lsu.storeQueueEntries) + assert(legacyOoo.instructionDecodeWidth == mainline.ooo.decodeWidth) + assert(legacyOoo.renameWidth == mainline.ooo.renameWidth) + assert(legacyOoo.dispatchWidth == mainline.ooo.dispatchWidth) + assert(legacyOoo.pTagGenerationWidth == + mainline.ooo.gprTagGenerationWidth) + assert(legacyOoo.localSeqGenerationWidth == + mainline.ooo.localSeqGenerationWidth) + assert(legacyWideOoo.instructionDecodeWidth == 8) + } +} diff --git a/chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala b/chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala new file mode 100644 index 00000000..4e1e376f --- /dev/null +++ b/chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala @@ -0,0 +1,380 @@ +package linxcore.params + +import linxcore.common.TemplateD3Constants +import linxcore.iex.OOOIEXLSUActivationParams +import linxcore.ooo.{OooParams => MechanismOooParams} +import org.scalatest.funsuite.AnyFunSuite + +class SimulationParamProfilesSpec extends AnyFunSuite { + private val widths = Seq(2, 4, 6, 8) + + test("simulation profiles preserve the main MDB failed-wait timeout") { + widths.foreach { width => + val main = ParamProfiles.forWidth(width) + val simulation = SimulationParamProfiles.forWidth(width) + + assert(main.lsu.mdbFailedWaitTimeoutCycles == 300) + assert(simulation.lsu.mdbFailedWaitTimeoutCycles == + main.lsu.mdbFailedWaitTimeoutCycles) + } + } + + test("generic LSU and width profiles do not assume platform MMIO regions") { + assert(LSUParams().physicalMemoryRegions.isEmpty) + widths.foreach { width => + assert(ParamProfiles.forWidth(width).lsu.physicalMemoryRegions.isEmpty) + assert(SimulationParamProfiles.forWidth(width).lsu.physicalMemoryRegions.isEmpty) + } + } + + test("natural_platform_normal_ram_noncacheable_devices_mmio") { + val natural = NaturalPlatformParams(SimulationParamProfiles.W4) + val regions = natural.lsu.physicalMemoryRegions + + assert(natural.lsu.defaultMemoryAttributes == MemoryAccessAttributes( + readable = true, writable = true, cacheable = false, device = false)) + + assert(regions.map(_.base) == Seq( + BigInt("10000000", 16), BigInt("10009000", 16))) + assert(regions.forall(_.mask == BigInt("fffffffffffff000", 16))) + assert(regions.forall(region => region.attributes.readable && + region.attributes.writable && !region.attributes.cacheable && + region.attributes.device)) + } + + test("simulation profiles use the literal bounded IFU and DTU capacity table") { + val expected = Map( + 2 -> (4, 4, 4, 4, 4), + 4 -> (4, 4, 4, 4, 4), + 6 -> (4, 4, 4, 4, 4), + 8 -> (4, 4, 4, 4, 4)) + + widths.foreach { width => + val main = ParamProfiles.forWidth(width) + val sim = SimulationParamProfiles.forWidth(width) + val mainMechanism = MechanismOooParams.fromCoreParams(main) + val simMechanism = MechanismOooParams.fromCoreParams(sim) + val physicalCapacities = ( + sim.ifu.itlbEntries, + sim.ifu.l1iSets, + sim.ifu.missEntries, + sim.ifu.joinEntries, + sim.dtu.traceBufferEntries) + + ParamChecks.validate(sim) + assert(physicalCapacities == expected(width)) + assert(sim.ifu.maxGroupsPerTransaction == + main.ifu.maxGroupsPerTransaction) + assert(sim.dtu.performanceCounterCount == + main.dtu.performanceCounterCount) + assert(sim.ctu.maxTemplateUops == main.ctu.maxTemplateUops) + assert((sim.iex.aluPipes, sim.iex.bruPipes, sim.iex.aguPipes, + sim.iex.stdPipes, sim.lsu.loadPipes, sim.lsu.storePipes) == + (main.iex.aluPipes, main.iex.bruPipes, main.iex.aguPipes, + main.iex.stdPipes, main.lsu.loadPipes, main.lsu.storePipes)) + assert((simMechanism.stidWidth, simMechanism.ridSlotWidth, + simMechanism.robMemberIndexWidth, simMechanism.nativeBidWidth, + simMechanism.pTagWidth, simMechanism.tTagWidth, + simMechanism.uTagWidth) == + (mainMechanism.stidWidth, mainMechanism.ridSlotWidth, + mainMechanism.robMemberIndexWidth, mainMechanism.nativeBidWidth, + mainMechanism.pTagWidth, mainMechanism.tTagWidth, + mainMechanism.uTagWidth)) + assert((sim.lsidWidth, sim.transactionIdWidth, + sim.memoryTransactionIdWidth, sim.memoryTransactionGenerationWidth, + sim.memoryAttemptGenerationWidth) == + (main.lsidWidth, main.transactionIdWidth, + main.memoryTransactionIdWidth, + main.memoryTransactionGenerationWidth, + main.memoryAttemptGenerationWidth)) + } + } + + test("simulation profiles preserve principal widths and fixed identity domains") { + widths.foreach { width => + val main = ParamProfiles.forWidth(width) + val sim = SimulationParamProfiles.forWidth(width) + val prefixCapacity = if (width <= 2) 2 else if (width <= 4) 4 else 8 + val robGroupCapacity = 16 + val issueCapacity = prefixCapacity + + ParamChecks.validate(sim) + assert(sim.widths == WidthParams.uniform(width)) + assert(sim.ifu.fetchWidth == width) + assert(sim.ifu.ctuTransferWidth == width) + assert(sim.ctu.inputWidth == width) + assert(sim.ctu.outputWidth == width) + assert(sim.ctu.maxTemplateUops >= TemplateD3Constants.MaxRows) + assert(sim.ooo.decodeWidth == width) + assert(sim.ooo.renameWidth == width) + assert(sim.ooo.d3PrefixWidth == width) + assert(sim.ooo.dispatchWidth == width) + assert(sim.ooo.retireWidth == width) + assert(sim.ooo.storeCommitBufferEntries == + Integer.highestOneBit( + width * sim.maxMemoryRequestsPerInstruction - 1) * 2) + assert(sim.iex.issueWidth == width) + assert(sim.ooo.robGroupsPerStid == robGroupCapacity) + assert(sim.ooo.maxInstructionsPerRobGroup == + main.ooo.maxInstructionsPerRobGroup) + assert(sim.ooo.maxUopsPerInstruction == 12) + assert(sim.ooo.robBankCount == prefixCapacity) + assert(sim.ooo.pcRecoveryScanGroupsPerCycle == math.min(4, + robGroupCapacity)) + assert(sim.ooo.robGroupsPerStid % + sim.ooo.pcRecoveryScanGroupsPerCycle == 0) + assert(sim.ooo.gprPhysRegs <= main.ooo.gprPhysRegs) + assert(sim.ooo.gprMapQDepthPerStid == math.max(16, + Integer.highestOneBit(width * sim.maxDestinationOperands - 1) * 2)) + assert(sim.ooo.tPhysRegs == sim.ooo.gprMapQDepthPerStid) + assert(sim.ooo.uPhysRegs == sim.ooo.gprMapQDepthPerStid) + assert(sim.ooo.tuMapQDepthPerStid == sim.ooo.gprMapQDepthPerStid) + assert(sim.iex.scalarIssueEntries == issueCapacity) + assert(sim.iex.scalarIssueEntries / sim.iex.scalarIssueBanks >= 1) + assert(sim.iex.stdPipes == sim.lsu.storePipes) + assert(sim.lsu.storeQueueEntries == + Integer.highestOneBit( + sim.iex.stdPipes * sim.maxMemoryRequestsPerInstruction - 1) * 2) + assert(sim.pcWidth == main.pcWidth) + assert(sim.instructionWidth == main.instructionWidth) + assert(sim.instructionIdWidth == main.instructionIdWidth) + assert(sim.transactionIdWidth == main.transactionIdWidth) + assert(sim.lsidWidth == main.lsidWidth) + assert(sim.memoryTransactionIdWidth == main.memoryTransactionIdWidth) + assert(sim.memoryTransactionGenerationWidth == + main.memoryTransactionGenerationWidth) + assert(sim.memoryAttemptGenerationWidth == + main.memoryAttemptGenerationWidth) + assert(sim.epochWidth == main.epochWidth) + assert(sim.ridGenerationWidth == main.ridGenerationWidth) + assert(sim.brobGenerationWidth == main.brobGenerationWidth) + } + } + + test("bounded simulation ROB covers an open block plus one canonical template window") { + widths.foreach { width => + val sim = SimulationParamProfiles.forWidth(width) + + assert(sim.ooo.robGroupsPerStid == 16) + assert(sim.ooo.robCapacityPerStid >= 2 * sim.ctu.maxTemplateUops) + } + } + + test("bounded simulation rename retains block-closing forward progress") { + widths.foreach { width => + val sim = SimulationParamProfiles.forWidth(width) + + assert(sim.ooo.gprMapQDepthPerStid >= 16) + assert(sim.ooo.tuMapQDepthPerStid >= 16) + assert(sim.ooo.gprPhysRegs >= sim.ooo.gprArchRegs + 16) + assert(sim.ooo.tPhysRegs >= 16) + assert(sim.ooo.uPhysRegs >= 16) + } + } + + test("W4 simulation topology remains two one two two and two load two store") { + val p = SimulationParamProfiles.W4 + + assert((p.iex.aluPipes, p.iex.bruPipes, p.iex.aguPipes, p.iex.stdPipes) == + (2, 1, 2, 2)) + assert(p.iex.systemMulticycleQueues == 1) + assert(p.iex.cmdIssueQueues == 1) + assert((p.lsu.loadPipes, p.lsu.storePipes) == (2, 2)) + assert((p.ooo.pcWritePorts, p.ooo.pcReadPorts) == (3, 6)) + } + + test("W8 directed profile uses minimum retained capacities for the proof") { + val p = SimulationParamProfiles.W8 + + assert(p.ifu.fetchBufferEntries == 8) + assert(p.ifu.predictionCheckpointEntries == 8) + assert(p.ctu.instructionBufferEntries == 8) + assert(p.ctu.maxTemplateUops >= TemplateD3Constants.MaxRows) + assert(p.ooo.robGroupsPerStid == 16) + assert(p.ooo.maxInstructionsPerRobGroup == 4) + assert(p.ooo.maxUopsPerInstruction == 12) + assert(p.ooo.robBankCount == 8) + assert(p.ooo.brobEntriesPerStid == 8) + assert(p.ooo.pcBufferEntries == 8) + assert(p.ooo.pcBankCount == 8) + assert(p.ooo.pcRecoveryScanGroupsPerCycle == 4) + assert(p.ooo.gprPhysRegs == 64) + assert(p.ooo.gprMapQDepthPerStid == 16) + assert(p.ooo.tPhysRegs == 16) + assert(p.ooo.uPhysRegs == 16) + assert(p.ooo.tuMapQDepthPerStid == 16) + assert(p.iex.scalarIssueEntries == 8) + assert((p.lsu.loadQueueEntries, p.lsu.storeQueueEntries) == (2, 4)) + assert(p.lsu.loadReturnQueueEntries == 2) + assert(p.lsu.storeCommitQueueEntries == 2) + assert(p.lsu.scbEntries == 4) + } + + test("identity-derived domains never narrow in simulation profiles") { + val main = ParamProfiles.W8 + val sim = SimulationParamProfiles.W8 + + assert(sim.nativeBidWidth == main.nativeBidWidth) + assert(sim.ooo.stidIdentityEntries == main.ooo.stidIdentityEntries) + assert(sim.ooo.robIdentityGroupsPerStid == + main.ooo.robIdentityGroupsPerStid) + assert(sim.ooo.robIdentityMembersPerGroup == + main.ooo.robIdentityMembersPerGroup) + assert(sim.ooo.uopIdentityEntriesPerInstruction == + main.ooo.uopIdentityEntriesPerInstruction) + assert(sim.ooo.brobIdentityEntriesPerStid == + main.ooo.brobIdentityEntriesPerStid) + assert(sim.ooo.gprTagIdentityEntries == main.ooo.gprTagIdentityEntries) + assert(sim.ooo.tTagIdentityEntries == main.ooo.tTagIdentityEntries) + assert(sim.ooo.uTagIdentityEntries == main.ooo.uTagIdentityEntries) + assert(sim.ooo.robGroupsPerStid < main.ooo.robGroupsPerStid) + assert(sim.ooo.gprMapQDepthPerStid < main.ooo.gprMapQDepthPerStid) + assert(sim.ooo.pcBufferEntries < main.ooo.pcBufferEntries) + } + + test("W4 activation preserves public identity widths while bounding retained storage") { + val main = ParamProfiles.W4 + val activation = OOOIEXLSUActivationParams.W4 + val mainMechanism = MechanismOooParams.fromCoreParams(main) + val activationMechanism = MechanismOooParams.fromCoreParams(activation) + + assert(activation.ooo.stidIdentityEntries == main.ooo.stidIdentityEntries) + assert(activation.ooo.robIdentityGroupsPerStid == + main.ooo.robIdentityGroupsPerStid) + assert(activation.ooo.robIdentityMembersPerGroup == + main.ooo.robIdentityMembersPerGroup) + assert(activation.ooo.uopIdentityEntriesPerInstruction == + main.ooo.uopIdentityEntriesPerInstruction) + assert(activation.ooo.brobIdentityEntriesPerStid == + main.ooo.brobIdentityEntriesPerStid) + assert(activation.ooo.gprTagIdentityEntries == + main.ooo.gprTagIdentityEntries) + assert(activation.ooo.tTagIdentityEntries == main.ooo.tTagIdentityEntries) + assert(activation.ooo.uTagIdentityEntries == main.ooo.uTagIdentityEntries) + assert(activationMechanism.stidWidth == mainMechanism.stidWidth) + assert(activationMechanism.ridSlotWidth == mainMechanism.ridSlotWidth) + assert(activationMechanism.robMemberIndexWidth == + mainMechanism.robMemberIndexWidth) + assert(activationMechanism.recipeUopCountWidth == + mainMechanism.recipeUopCountWidth) + assert(activationMechanism.nativeBidWidth == mainMechanism.nativeBidWidth) + assert(activationMechanism.pTagWidth == mainMechanism.pTagWidth) + assert(activationMechanism.tTagWidth == mainMechanism.tTagWidth) + assert(activationMechanism.uTagWidth == mainMechanism.uTagWidth) + assert(activation.nativeBidWidth == main.nativeBidWidth) + assert(activation.ridGenerationWidth == main.ridGenerationWidth) + assert(activation.brobGenerationWidth == main.brobGenerationWidth) + assert(activation.lsidWidth == main.lsidWidth) + assert(activation.transactionIdWidth == main.transactionIdWidth) + assert(activation.memoryTransactionIdWidth == + main.memoryTransactionIdWidth) + assert(activation.memoryTransactionGenerationWidth == + main.memoryTransactionGenerationWidth) + assert(activation.memoryAttemptGenerationWidth == + main.memoryAttemptGenerationWidth) + + assert(activation.ooo.stidCount == 2) + assert(activation.ooo.robGroupsPerStid == 8) + assert(activation.ooo.maxInstructionsPerRobGroup == 1) + assert(activation.ooo.maxUopsPerInstruction == 12) + assert(activation.ooo.brobEntriesPerStid == 8) + assert(activation.ooo.gprPhysRegs == 64) + assert(activation.ooo.tPhysRegs == 8) + assert(activation.ooo.uPhysRegs == 8) + assert(activation.ooo.gprMapQDepthPerStid < main.ooo.gprMapQDepthPerStid) + assert(activation.ooo.tuMapQDepthPerStid < main.ooo.tuMapQDepthPerStid) + assert(activation.iex.scalarIssueEntries < main.iex.scalarIssueEntries) + assert(activation.lsu.loadQueueEntries < main.lsu.loadQueueEntries) + assert(activation.lsu.storeQueueEntries < main.lsu.storeQueueEntries) + } + + test("W2 activation minimizes retained state without narrowing identities") { + val main = ParamProfiles.W2 + val activation = OOOIEXLSUActivationParams.W2 + + assert(activation.widths == main.widths) + assert(activation.ooo.stidIdentityEntries == main.ooo.stidIdentityEntries) + assert(activation.ooo.robIdentityGroupsPerStid == + main.ooo.robIdentityGroupsPerStid) + assert(activation.ooo.robIdentityMembersPerGroup == + main.ooo.robIdentityMembersPerGroup) + assert(activation.ooo.brobIdentityEntriesPerStid == + main.ooo.brobIdentityEntriesPerStid) + assert(activation.ooo.gprTagIdentityEntries == + main.ooo.gprTagIdentityEntries) + assert(activation.ooo.tTagIdentityEntries == main.ooo.tTagIdentityEntries) + assert(activation.ooo.uTagIdentityEntries == main.ooo.uTagIdentityEntries) + assert(activation.lsidWidth == main.lsidWidth) + assert(activation.memoryTransactionIdWidth == + main.memoryTransactionIdWidth) + assert(activation.memoryAttemptGenerationWidth == + main.memoryAttemptGenerationWidth) + + assert(activation.ooo.stidCount == 1) + assert(activation.ooo.robGroupsPerStid == 8) + assert(activation.ooo.maxInstructionsPerRobGroup == 1) + assert(activation.ooo.robBankCount == 2) + assert(activation.ooo.brobEntriesPerStid == 8) + assert(activation.ooo.pcBufferEntries == 4) + assert(activation.ooo.gprPhysRegs == 32) + assert(activation.ooo.gprMapQDepthPerStid == 4) + assert(activation.ooo.tPhysRegs == 4) + assert(activation.ooo.uPhysRegs == 4) + assert(activation.ooo.tuMapQDepthPerStid == 4) + assert(activation.iex.scalarIssueEntries == 4) + assert(activation.lsu.loadQueueEntries == 2) + assert(activation.lsu.storeQueueEntries == 4) + } + + test("physical STQ ROB and full LSID capacities remain independent") { + val unequal = OOOIEXLSUActivationParams.W4.copy( + ooo = OOOIEXLSUActivationParams.W4.ooo.copy(robGroupsPerStid = 8), + lsu = OOOIEXLSUActivationParams.W4.lsu.copy(storeQueueEntries = 16), + lsidWidth = 40) + val mechanism = MechanismOooParams.fromCoreParams(unequal) + + ParamChecks.validate(unequal) + assert(unequal.lsu.storeQueueEntries == 16) + assert(unequal.ooo.robGroupsPerStid == 8) + assert(unequal.ooo.robIdentityGroupsPerStid == 64) + assert(unequal.lsidWidth == 40) + assert(mechanism.ridSlotWidth == 6) + } + + test("public and private ROB member widths ignore the larger recipe uop domain") { + val core = ParamProfiles.W4.copy( + ooo = ParamProfiles.W4.ooo.copy( + robIdentityMembersPerGroup = 4, + maxInstructionsPerRobGroup = 4, + maxUopsPerInstruction = 32, + uopIdentityEntriesPerInstruction = 32)) + val mechanism = MechanismOooParams.fromCoreParams(core) + + assert(core.ooo.robMemberIndexWidth == 2) + assert(core.ooo.recipeUopIndexWidth == 5) + assert(core.ooo.recipeUopCountWidth == 6) + assert(mechanism.robMemberIndexWidth == 2) + assert(mechanism.recipeUopIndexWidth == 5) + assert(mechanism.recipeUopCountWidth == 6) + } + + test("simulation capacity changes never mutate main profiles") { + assert(ParamProfiles.W8.ooo.robGroupsPerStid == 64) + assert(ParamProfiles.W8.ooo.maxInstructionsPerRobGroup == 4) + assert(ParamProfiles.W8.ooo.brobEntriesPerStid == 256) + assert(ParamProfiles.W8.ooo.pcBufferEntries == 64) + assert(ParamProfiles.W8.ooo.gprPhysRegs == 128) + assert(ParamProfiles.W8.ooo.gprMapQDepthPerStid == 256) + assert(ParamProfiles.W8.iex.scalarIssueEntries == 64) + assert(ParamProfiles.W8.lsu.loadQueueEntries == 16) + assert(ParamProfiles.W8.lsu.storeQueueEntries == 16) + } + + test("unsupported simulation width fails before publishing a profile") { + val error = intercept[IllegalArgumentException] { + SimulationParamProfiles.forWidth(3) + } + + assert(error.getMessage.contains("supported widths are 2, 4, 6, and 8")) + } +} diff --git a/chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala b/chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala new file mode 100644 index 00000000..31474210 --- /dev/null +++ b/chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala @@ -0,0 +1,47 @@ +package linxcore.testutil + +final case class SimulationProgressEvent(kind: String, identity: String) + +/** Tracks typed architectural progress in simulated cycles. + * + * This is intentionally independent from build-process liveness: a busy + * simulator can still be architecturally deadlocked. + */ +final class SimulationProgress( + maxIdleCycles: Long, + occupancy: () => String) { + require(maxIdleCycles > 0, "maxIdleCycles must be positive") + + private var lastObservedCycle = 0L + private var lastProgressCycle = 0L + private var lastProgress = Option.empty[SimulationProgressEvent] + + def observe( + cycle: Long, + events: Iterable[SimulationProgressEvent]): Unit = { + require(cycle >= lastObservedCycle, + "cycle must not move backwards") + lastObservedCycle = cycle + + events.lastOption.foreach { event => + lastProgressCycle = cycle + lastProgress = Some(event) + } + } + + def requireAlive(cycle: Long): Unit = { + require(cycle >= lastObservedCycle, + "cycle must not move backwards") + lastObservedCycle = cycle + + if (cycle - lastProgressCycle > maxIdleCycles) { + val event = lastProgress + .map(value => s"${value.kind}:${value.identity}") + .getOrElse("none") + throw new IllegalStateException( + s"simulation made no architectural progress: cycle=$cycle " + + s"lastCycle=$lastProgressCycle lastEvent=$event " + + s"occupancy=${occupancy()}") + } + } +} diff --git a/chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala b/chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala new file mode 100644 index 00000000..5e6f4851 --- /dev/null +++ b/chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala @@ -0,0 +1,60 @@ +package linxcore.testutil + +import org.scalatest.funsuite.AnyFunSuite + +class SimulationProgressSpec extends AnyFunSuite { + test("a typed progress event resets the idle-cycle window") { + val progress = new SimulationProgress(8, () => "rob=1,liq=0") + + progress.observe( + 7, + Seq(SimulationProgressEvent("dispatch", "rid=3"))) + progress.requireAlive(15) + } + + test("the first cycle beyond the limit reports identity and occupancy") { + val progress = new SimulationProgress(8, () => "rob=1,liq=1") + progress.observe( + 4, + Seq(SimulationProgressEvent("memory-rebind", "attempt=2"))) + + val error = intercept[IllegalStateException] { + progress.requireAlive(13) + } + + assert(error.getMessage.contains("cycle=13")) + assert(error.getMessage.contains("lastCycle=4")) + assert(error.getMessage.contains("memory-rebind")) + assert(error.getMessage.contains("attempt=2")) + assert(error.getMessage.contains("rob=1,liq=1")) + } + + test("empty observations do not create synthetic progress") { + val progress = new SimulationProgress(2, () => "iq=1") + + progress.observe(0, Seq.empty) + + assertThrows[IllegalStateException] { + progress.requireAlive(3) + } + } + + test("decreasing cycle observations fail closed") { + val progress = new SimulationProgress(8, () => "rob=0") + progress.observe(5, Seq(SimulationProgressEvent("commit", "rid=1"))) + + val error = intercept[IllegalArgumentException] { + progress.observe(4, Seq(SimulationProgressEvent("dispatch", "rid=2"))) + } + + assert(error.getMessage.contains("cycle must not move backwards")) + } + + test("the idle limit must be positive") { + val error = intercept[IllegalArgumentException] { + new SimulationProgress(0, () => "") + } + + assert(error.getMessage.contains("maxIdleCycles must be positive")) + } +} diff --git a/chisel/src/test/scala/linxcore/top/FullBidBlockConditionOwnerSpec.scala b/chisel/src/test/scala/linxcore/top/FullBidBlockConditionOwnerSpec.scala deleted file mode 100644 index c7597ae9..00000000 --- a/chisel/src/test/scala/linxcore/top/FullBidBlockConditionOwnerSpec.scala +++ /dev/null @@ -1,63 +0,0 @@ -package linxcore.top - -import chisel3._ -import chisel3.simulator.scalatest.ChiselSim -import org.scalatest.funsuite.AnyFunSuite - -class FullBidBlockConditionOwnerSpec extends AnyFunSuite with ChiselSim { - private def clearInputs(dut: FullBidBlockConditionOwner): Unit = { - dut.io.captureValid.poke(false.B) - dut.io.captureTaken.poke(false.B) - dut.io.captureBlockBidValid.poke(false.B) - dut.io.captureBlockBid.poke(0.U) - dut.io.activeBlockValid.poke(false.B) - dut.io.activeBlockBid.poke(0.U) - dut.io.fretValid.poke(false.B) - dut.io.fretBlockBidValid.poke(false.B) - dut.io.fretBlockBid.poke(0.U) - dut.io.fretConsume.poke(false.B) - } - - test("SETC condition survives unrelated markers and is consumed only by matching full BID FRET") { - simulate(new FullBidBlockConditionOwner(16)) { dut => - clearInputs(dut) - dut.reset.poke(true.B) - dut.clock.step() - dut.reset.poke(false.B) - - dut.io.captureValid.poke(true.B) - dut.io.captureTaken.poke(true.B) - dut.io.captureBlockBidValid.poke(true.B) - dut.io.captureBlockBid.poke(0x1234.U) - dut.io.activeBlockValid.poke(true.B) - dut.io.activeBlockBid.poke(0x1234.U) - dut.io.activeConditionValid.expect(true.B) - dut.io.activeConditionTaken.expect(true.B) - dut.clock.step() - - clearInputs(dut) - dut.io.activeBlockValid.poke(true.B) - dut.io.activeBlockBid.poke(0x5678.U) - dut.io.activeConditionValid.expect(false.B) - dut.clock.step() - - clearInputs(dut) - dut.io.fretValid.poke(true.B) - dut.io.fretBlockBidValid.poke(true.B) - dut.io.fretBlockBid.poke(0x5678.U) - dut.io.fretConditionValid.expect(false.B) - - dut.io.fretBlockBid.poke(0x1234.U) - dut.io.fretConditionValid.expect(true.B) - dut.io.fretConditionTaken.expect(true.B) - dut.io.fretConsume.poke(true.B) - dut.clock.step() - - clearInputs(dut) - dut.io.fretValid.poke(true.B) - dut.io.fretBlockBidValid.poke(true.B) - dut.io.fretBlockBid.poke(0x1234.U) - dut.io.fretConditionValid.expect(false.B) - } - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreBenchmarkAutonomousTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreBenchmarkAutonomousTopSpec.scala deleted file mode 100644 index a3f0312b..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreBenchmarkAutonomousTopSpec.scala +++ /dev/null @@ -1,546 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -import java.nio.charset.StandardCharsets -import java.nio.file.{Files, Paths} - -object LinxCoreBenchmarkAutonomousTopReference { - def blockFitsRob(robEntries: Int, bodyUopsBeforeClosingMarker: Int): Boolean = - robEntries > bodyUopsBeforeClosingMarker - - def localIncomingBlocked(usesLocal: Boolean, pendingT: Int, pendingU: Int): Boolean = - usesLocal && (pendingT != 0 || pendingU != 0) - - final case class Inputs( - rowValid: Boolean = true, - memValid: Boolean = true, - isStore: Boolean = true, - addr: BigInt = 0, - data: BigInt = 0, - size: Int = 1, - trapValid: Boolean = false, - commitContractError: Boolean = false, - startValid: Boolean = false, - restartValid: Boolean = false, - flushValid: Boolean = false, - sourceBlocked: Boolean = false, - resetSp: BigInt = 0, - restartSp: BigInt = 0) - - final case class RowInput( - valid: Boolean = true, - ready: Boolean = true, - memValid: Boolean = false, - isStore: Boolean = false, - addr: BigInt = 0, - data: BigInt = 0, - size: Int = 1, - trapValid: Boolean = false, - commitContractError: Boolean = false, - blockLast: Boolean = false) - - final case class Decision( - commitAccepted: Boolean, - committedSideEffectAccepted: Boolean, - storeObserveValid: Boolean, - storeObserveMask: Int, - uartWriteValid: Boolean, - uartWriteByte: Int, - finisherWriteValid: Boolean, - finisherPass: Boolean, - bootSp: BigInt, - halted: Boolean, - trapValid: Boolean, - unsupportedInstruction: Boolean, - status: Int) - - final case class WindowDecision( - retiredRows: Int, - sideEffectAddrs: Seq[BigInt], - halted: Boolean, - trapValid: Boolean, - unsupportedInstruction: Boolean) - - def storeFitsObservationLane(addr: BigInt, size: Int): Boolean = { - val lowAddr = (addr & 0x7).toInt - size > 0 && size <= 8 && lowAddr + size <= 8 - } - - def storeMask(addr: BigInt, size: Int): Option[Int] = - if (storeFitsObservationLane(addr, size)) { - val lowAddr = (addr & 0x7).toInt - Some(((1 << size) - 1) << lowAddr) - } else { - None - } - - def storeLaneData(addr: BigInt, data: BigInt): BigInt = - (data << (((addr & 0x7).toInt) * 8)) & ((BigInt(1) << 64) - 1) - - def decide(in: Inputs): Decision = { - val startOrRestart = in.startValid || in.restartValid - val selectedSp = if (in.restartValid) in.restartSp else in.resetSp - val commitAccepted = in.rowValid && !startOrRestart && !in.flushValid && !in.sourceBlocked - val mask = storeMask(in.addr, in.size) - val exceptionalCommit = in.trapValid || in.commitContractError - val committedSideEffectAccepted = commitAccepted && !exceptionalCommit && in.memValid && in.isStore && mask.nonEmpty - val uartWrite = - committedSideEffectAccepted && in.addr == LinxCoreBenchmarkAutonomousTop.UartDataAddr - val finisherWrite = - committedSideEffectAccepted && in.addr == LinxCoreBenchmarkAutonomousTop.TestFinisherAddr - val finisherPass = (in.data & 0xffff) == LinxCoreBenchmarkAutonomousTop.FinisherPass - val invalidStoreSideEffect = commitAccepted && !exceptionalCommit && in.memValid && in.isStore && mask.isEmpty - val unsupported = commitAccepted && in.commitContractError - val trapCommit = commitAccepted && in.trapValid - - val (halted, trap, unsupportedInstruction, status) = - if (startOrRestart) { - (false, false, false, LinxCoreBenchmarkAutonomousTop.StatusFetch) - } else if (in.flushValid) { - (true, false, false, LinxCoreBenchmarkAutonomousTop.StatusIdle) - } else if (finisherWrite) { - ( - true, - !finisherPass, - false, - if (finisherPass) LinxCoreBenchmarkAutonomousTop.StatusFinisherPass - else LinxCoreBenchmarkAutonomousTop.StatusFinisherFail) - } else if (trapCommit || unsupported || invalidStoreSideEffect) { - (true, true, unsupported || invalidStoreSideEffect, LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - } else { - (false, false, false, LinxCoreBenchmarkAutonomousTop.StatusFetch) - } - - Decision( - commitAccepted = commitAccepted, - committedSideEffectAccepted = committedSideEffectAccepted, - storeObserveValid = committedSideEffectAccepted, - storeObserveMask = mask.getOrElse(0), - uartWriteValid = uartWrite, - uartWriteByte = (in.data & 0xff).toInt, - finisherWriteValid = finisherWrite, - finisherPass = finisherWrite && finisherPass, - bootSp = selectedSp, - halted = halted, - trapValid = trap, - unsupportedInstruction = unsupportedInstruction, - status = status) - } - - def decideWindow(rows: Seq[RowInput]): WindowDecision = { - var retired = 0 - var stop = false - var halted = false - var trap = false - var unsupported = false - val sideEffects = scala.collection.mutable.ArrayBuffer.empty[BigInt] - - rows.foreach { row => - if (!stop && row.valid && row.ready) { - retired += 1 - val mask = storeMask(row.addr, row.size) - val exceptional = row.trapValid || row.commitContractError - val invalidStore = row.memValid && row.isStore && !exceptional && mask.isEmpty - - if (exceptional || invalidStore) { - halted = true - trap = true - unsupported = row.commitContractError || invalidStore - stop = true - } else if (row.memValid && row.isStore) { - sideEffects += row.addr - stop = true - } - - if (row.blockLast) { - stop = true - } - } else { - stop = true - } - } - - WindowDecision(retired, sideEffects.toSeq, halted, trap, unsupported) - } - - def drainOneSideEffectPerCycle(retiredWindows: Seq[Seq[BigInt]]): Seq[BigInt] = { - val pending = scala.collection.mutable.Queue.empty[BigInt] - val observed = scala.collection.mutable.ArrayBuffer.empty[BigInt] - - retiredWindows.foreach { window => - if (pending.nonEmpty) { - observed += pending.dequeue() - pending.enqueueAll(window) - } else if (window.nonEmpty) { - observed += window.head - pending.enqueueAll(window.tail) - } - } - - while (pending.nonEmpty) { - observed += pending.dequeue() - } - - observed.toSeq - } -} - -object LinxCoreBenchmarkAutonomousTopSpecFixtures { - lazy val defaultTopSystemVerilog: String = - ChiselStage.emitSystemVerilog(new LinxCoreBenchmarkAutonomousTop()) - - def sourceText(path: String): String = - new String(Files.readAllBytes(Paths.get(path)), StandardCharsets.UTF_8) -} - -class LinxCoreBenchmarkAutonomousTopSpec extends AnyFunSuite { - test("natural _start_c block capacity and local ordering have explicit guards") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val startCBodyUopsBeforeClosingMarker = 16 - assert(!blockFitsRob(8, startCBodyUopsBeforeClosingMarker)) - assert(blockFitsRob( - LinxCoreBenchmarkAutonomousTop.BenchmarkRobEntries, - startCBodyUopsBeforeClosingMarker)) - - assert(localIncomingBlocked(usesLocal = true, pendingT = 1, pendingU = 0)) - assert(localIncomingBlocked(usesLocal = true, pendingT = 0, pendingU = 1)) - assert(localIncomingBlocked(usesLocal = true, pendingT = 1, pendingU = 1)) - assert(!localIncomingBlocked(usesLocal = true, pendingT = 0, pendingU = 0)) - assert(!localIncomingBlocked(usesLocal = false, pendingT = 3, pendingU = 3)) - } - - test("Phase 1 autonomous top exposes live pipeline memory and commit boundaries") { - val p = LinxCoreBenchmarkAutonomousTop.interfaceParamsFor(CoreParams(robEntries = 8, commitWidth = 2)) - val traceParams = LinxCoreBenchmarkAutonomousTop.traceParamsFor(p) - val io = new LinxCoreBenchmarkAutonomousTopIO(p, traceParams) - - assert(io.p.commitWidth == 2) - assert(io.traceParams.commitWidth == 2) - assert(io.fetchReqPc.getWidth == 64) - assert(io.fetchRespWindow.getWidth == io.p.windowWidth) - assert(io.loadLookupData.getWidth == 64) - assert(io.loadLookupAddr.getWidth == 64) - assert(io.loadLookupPc.getWidth == 64) - assert(io.loadLookupDstPhysTag.getWidth == io.p.physRegWidth) - assert(!io.elements.contains("loadLookupReady")) - assert(!io.elements.contains("loadRespValid")) - assert(!io.elements.contains("loadRespReady")) - assert(io.commit.rows.length == 2) - assert(io.storeObserveAddr.getWidth == 64) - assert(io.storeObserveData.getWidth == 64) - assert(io.storeObserveSize.getWidth == io.p.memSizeWidth) - assert(io.storeObserveMask.getWidth == 8) - assert(io.storeObservePairValid.getWidth == 1) - assert(io.storeObservePairAddr.getWidth == 64) - assert(io.storeObservePairData.getWidth == 64) - assert(io.storeObservePairSize.getWidth == io.p.memSizeWidth) - assert(io.storeObservePairMask.getWidth == 8) - assert(io.storeObserveRobValue.getWidth == io.p.robIndexWidth) - assert(io.storeObserveBlockBid.getWidth == io.p.blockBidWidth) - assert(io.uartWriteByte.getWidth == 8) - assert(io.finisherCode.getWidth == 16) - assert(io.finisherPayload.getWidth == 32) - assert(io.debugLocalPendingCounts.getWidth == 6) - assert(io.debugLocalReadyMasks.getWidth == 8) - assert(io.debugLocalHeadPc.getWidth == 64) - assert(io.debugLocalExecuteCompleteValid.getWidth == 1) - assert(io.debugLocalCompletePc.getWidth == 64) - assert(io.debugLocalCompleteWbReg.getWidth == traceParams.regWidth) - assert(io.debugDecodeBlockBits.getWidth == 4) - assert(io.debugDecodeReadyBits.getWidth == 5) - } - - test("reference suppresses committed side effects during start restart flush and halted state") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val ordinary = decide(Inputs(addr = 0x40, data = 0x1234, size = 4)) - assert(ordinary.commitAccepted) - assert(ordinary.committedSideEffectAccepted) - assert(ordinary.storeObserveValid) - - for (blocked <- Seq( - Inputs(startValid = true, resetSp = 0x1000), - Inputs(restartValid = true, restartSp = 0x2000), - Inputs(flushValid = true), - Inputs(sourceBlocked = true))) { - val decision = decide(blocked.copy(addr = LinxCoreBenchmarkAutonomousTop.UartDataAddr, data = 0x41)) - assert(!decision.commitAccepted) - assert(!decision.committedSideEffectAccepted) - assert(!decision.storeObserveValid) - assert(!decision.uartWriteValid) - assert(!decision.finisherWriteValid) - } - } - - test("reference covers boot SP and Phase 1 single-cycle load boundary") { - import LinxCoreBenchmarkAutonomousTopReference._ - - assert(decide(Inputs(startValid = true, resetSp = 0x801000)).bootSp == 0x801000) - assert(decide(Inputs(restartValid = true, resetSp = 0x801000, restartSp = 0x802000)).bootSp == 0x802000) - - val p = LinxCoreBenchmarkAutonomousTop.interfaceParamsFor(CoreParams(robEntries = 8, commitWidth = 2)) - val io = new LinxCoreBenchmarkAutonomousTopIO(p, LinxCoreBenchmarkAutonomousTop.traceParamsFor(p)) - assert(io.loadLookupData.getWidth == p.immWidth) - assert(io.loadLookupValid.getWidth == 1) - assert(io.loadLookupAddr.getWidth == p.immWidth) - assert(io.loadLookupPc.getWidth == p.pcWidth) - assert(!io.elements.contains("loadLookupReady")) - assert(!io.elements.contains("loadRespData")) - } - - test("reference derives committed store UART and finisher only from accepted store payloads") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val store = decide(Inputs(addr = 0x48, data = BigInt("feedfacecafebeef", 16), size = 8)) - assert(store.storeObserveValid) - assert(store.storeObserveMask == 0xff) - assert(!store.uartWriteValid) - assert(!store.finisherWriteValid) - - assert(storeMask(0x1003, 1).contains(0x08)) - assert(storeLaneData(0x1003, 0x52) == BigInt("52000000", 16)) - assert(storeLaneData(0x1006, BigInt("bbaa", 16)) == BigInt("bbaa000000000000", 16)) - - val uart = decide(Inputs(addr = LinxCoreBenchmarkAutonomousTop.UartDataAddr, data = 0x41, size = 1)) - assert(uart.storeObserveValid) - assert(uart.uartWriteValid) - assert(uart.uartWriteByte == 0x41) - assert(!uart.finisherWriteValid) - - val finisher = decide(Inputs( - addr = LinxCoreBenchmarkAutonomousTop.TestFinisherAddr, - data = LinxCoreBenchmarkAutonomousTop.FinisherPass, - size = 8)) - assert(finisher.storeObserveValid) - assert(finisher.finisherWriteValid) - assert(finisher.finisherPass) - assert(finisher.halted) - assert(!finisher.trapValid) - assert(finisher.status == LinxCoreBenchmarkAutonomousTop.StatusFinisherPass) - } - - test("reference gives flush priority over trap and committed side effects") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val flushedTrapAndStore = decide(Inputs( - flushValid = true, - trapValid = true, - addr = LinxCoreBenchmarkAutonomousTop.TestFinisherAddr, - data = 1, - size = 8)) - - assert(flushedTrapAndStore.halted) - assert(!flushedTrapAndStore.trapValid) - assert(!flushedTrapAndStore.storeObserveValid) - assert(!flushedTrapAndStore.finisherWriteValid) - assert(flushedTrapAndStore.status == LinxCoreBenchmarkAutonomousTop.StatusIdle) - - val trap = decide(Inputs(rowValid = true, memValid = false, isStore = false, trapValid = true)) - assert(trap.halted) - assert(trap.trapValid) - assert(!trap.storeObserveValid) - assert(trap.status == LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - } - - test("reference suppresses exceptional row stores UART and finisher pulses") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val trapUart = decide(Inputs( - trapValid = true, - addr = LinxCoreBenchmarkAutonomousTop.UartDataAddr, - data = 0x41, - size = 1)) - assert(trapUart.commitAccepted) - assert(!trapUart.committedSideEffectAccepted) - assert(!trapUart.storeObserveValid) - assert(!trapUart.uartWriteValid) - assert(!trapUart.finisherWriteValid) - assert(trapUart.halted) - assert(trapUart.trapValid) - assert(!trapUart.unsupportedInstruction) - assert(trapUart.status == LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - - val trapFinisher = decide(Inputs( - trapValid = true, - addr = LinxCoreBenchmarkAutonomousTop.TestFinisherAddr, - data = LinxCoreBenchmarkAutonomousTop.FinisherPass, - size = 8)) - assert(trapFinisher.commitAccepted) - assert(!trapFinisher.committedSideEffectAccepted) - assert(!trapFinisher.storeObserveValid) - assert(!trapFinisher.uartWriteValid) - assert(!trapFinisher.finisherWriteValid) - assert(!trapFinisher.finisherPass) - assert(trapFinisher.halted) - assert(trapFinisher.trapValid) - assert(!trapFinisher.unsupportedInstruction) - assert(trapFinisher.status == LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - - val contractErrorStore = decide(Inputs( - commitContractError = true, - addr = 0x40, - data = 0x1234, - size = 4)) - assert(contractErrorStore.commitAccepted) - assert(!contractErrorStore.committedSideEffectAccepted) - assert(!contractErrorStore.storeObserveValid) - assert(!contractErrorStore.uartWriteValid) - assert(!contractErrorStore.finisherWriteValid) - assert(contractErrorStore.halted) - assert(contractErrorStore.trapValid) - assert(contractErrorStore.unsupportedInstruction) - assert(contractErrorStore.status == LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - } - - test("reference masks aligned in-lane stores and rejects cross-lane stores") { - import LinxCoreBenchmarkAutonomousTopReference._ - - assert(storeMask(0x1000, 1).contains(0x01)) - assert(storeMask(0x1002, 2).contains(0x0c)) - assert(storeMask(0x1004, 4).contains(0xf0)) - assert(storeMask(0x1000, 8).contains(0xff)) - - for ((addr, size) <- Seq(0x1001 -> 8, 0x1006 -> 4, 0x1007 -> 2, 0x1000 -> 0, 0x1000 -> 9)) { - val rejected = decide(Inputs(addr = addr, size = size)) - assert(storeMask(addr, size).isEmpty) - assert(!rejected.storeObserveValid) - assert(rejected.halted) - assert(rejected.trapValid) - assert(rejected.unsupportedInstruction) - assert(rejected.status == LinxCoreBenchmarkAutonomousTop.StatusUnsupported) - } - } - - test("reference retires two consecutive register rows and serializes store side effects") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val registers = decideWindow(Seq(RowInput(), RowInput())) - assert(registers.retiredRows == 2) - assert(registers.sideEffectAddrs.isEmpty) - - val stores = decideWindow(Seq( - RowInput(memValid = true, isStore = true, addr = 0x1000, data = 0x11), - RowInput(memValid = true, isStore = true, addr = 0x1008, data = 0x22))) - - assert(stores.retiredRows == 1) - assert(stores.sideEffectAddrs == Seq(0x1000)) - } - - test("reference stops width two retirement on unready exception invalid store and block last boundaries") { - import LinxCoreBenchmarkAutonomousTopReference._ - - assert(decideWindow(Seq(RowInput(), RowInput(ready = false))).retiredRows == 1) - - val trapFirst = decideWindow(Seq( - RowInput(trapValid = true), - RowInput(memValid = true, isStore = true, addr = 0x2000))) - assert(trapFirst.retiredRows == 1) - assert(trapFirst.sideEffectAddrs.isEmpty) - assert(trapFirst.halted) - assert(trapFirst.trapValid) - - val invalidStoreFirst = decideWindow(Seq( - RowInput(memValid = true, isStore = true, addr = 0x1007, size = 2), - RowInput(memValid = true, isStore = true, addr = 0x2000))) - assert(invalidStoreFirst.retiredRows == 1) - assert(invalidStoreFirst.sideEffectAddrs.isEmpty) - assert(invalidStoreFirst.unsupportedInstruction) - - val blockLastFirst = decideWindow(Seq( - RowInput(blockLast = true), - RowInput(memValid = true, isStore = true, addr = 0x2000))) - assert(blockLastFirst.retiredRows == 1) - assert(blockLastFirst.sideEffectAddrs.isEmpty) - } - - test("reference observes already serialized committed stores without queueing") { - import LinxCoreBenchmarkAutonomousTopReference._ - - val observed = Seq( - Seq(0x1000), - Seq(0x1010), - Seq.empty, - Seq(0x1018)).flatten - - assert(observed == Seq(0x1000, 0x1010, 0x1018)) - assert(observed.distinct == observed) - } - - test("Chisel top elaborates the production IFU and live backend without oracle inputs") { - val sv = LinxCoreBenchmarkAutonomousTopSpecFixtures.defaultTopSystemVerilog - - assert(sv.contains("module LinxCoreBenchmarkAutonomousTop")) - assert(sv.contains("module LinxCoreFrontendFetchRfAluTraceTop")) - assert(sv.contains("module LinxCoreIfu")) - assert(sv.contains("module BSidePredictionPipeline")) - assert(sv.contains("module D1InstructionDecodeStage")) - assert(sv.contains("module D1DecodedLaneQueue")) - assert(sv.contains("module IfuWindowLineFillAdapter")) - assert(!sv.contains("module FrontendFetchPacketSource")) - assert(!sv.contains("module F4DecodeWindow")) - assert(!sv.contains("module F4DenseSlotQueue")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("module StoreDispatchSTQPath")) - assert(sv.contains("module ReducedStoreStaAddressExecBridge")) - assert(sv.contains("module ScalarScTopHandshake")) - assert(sv.contains("io_resetPc")) - assert(sv.contains("io_resetSp")) - assert(sv.contains("io_fetchReqValid")) - assert(sv.contains("io_fetchReqReady")) - assert(sv.contains("io_fetchRespWindow")) - assert(sv.contains("io_loadLookupValid")) - assert(sv.contains("io_loadLookupData")) - assert(sv.contains("io_commit_rows_0_valid")) - assert(sv.contains("io_storeObserveValid")) - assert(sv.contains("io_storeObserveMask")) - assert(sv.contains("io_storeObservePairValid")) - assert(sv.contains("io_storeObservePairMask")) - assert(sv.contains("io_uartWriteValid")) - assert(sv.contains("io_finisherWriteValid")) - assert(sv.contains("io_finisherPass")) - assert(!sv.contains("loadRespValid")) - assert(!sv.contains("loadRespReady")) - assert(!sv.contains("loadLookupReady")) - assert(!sv.contains("expectedPc")) - assert(!sv.contains("io_expected")) - assert(!sv.contains("qemu")) - } - - test("default autonomous top exposes two commit lanes") { - val sv = LinxCoreBenchmarkAutonomousTopSpecFixtures.defaultTopSystemVerilog - - assert(sv.contains("module LinxCoreBenchmarkAutonomousTop")) - assert(sv.contains("io_commit_rows_0_valid")) - assert(sv.contains("io_commit_rows_1_valid")) - assert(sv.contains("autonomous benchmark top observed multiple committed stores in one cycle")) - assert(!sv.contains("sideEffectQueue")) - } - - test("autonomous benchmark top enables reduced SC store issue knobs") { - val source = LinxCoreBenchmarkAutonomousTopSpecFixtures.sourceText( - "src/main/scala/linxcore/top/LinxCoreBenchmarkAutonomousTop.scala") - - assert(source.contains("useReducedStoreDispatchStq = true")) - assert(source.contains("useReducedStoreStaAddressExecBridge = true")) - assert(source.contains("useProductionD1Ingress = true")) - } - - test("autonomous benchmark top keeps reduced SC store issue path live") { - val sv = LinxCoreBenchmarkAutonomousTopSpecFixtures.defaultTopSystemVerilog - val frontendSource = LinxCoreBenchmarkAutonomousTopSpecFixtures.sourceText( - "src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala") - - assert(frontendSource.contains("Module(new ScalarScTopHandshake")) - assert(frontendSource.contains("scalarScHandshake.io.ownerScReqReady")) - assert(frontendSource.contains("path.io.storeScResultValid := scalarScHandshake.io.storeScResultValid")) - assert(frontendSource.contains("issue.io.issueReady :=")) - assert(sv.contains("module ScalarScTopHandshake")) - assert(!sv.contains("assign scalarScHandshake_io_scReqValid = 1'h0")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFentryFretNaturalObservationSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFentryFretNaturalObservationSpec.scala deleted file mode 100644 index e9f2e701..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFentryFretNaturalObservationSpec.scala +++ /dev/null @@ -1,126 +0,0 @@ -package linxcore.top - -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -object LinxCoreFentryFretNaturalObservationReference { - val FentryPc: BigInt = BigInt("11370", 16) - val FentryRaw: BigInt = BigInt("29350041", 16) - val FretPc: BigInt = BigInt("11dba", 16) - val FretRaw: BigInt = BigInt("29353041", 16) - val OuterCallPc: BigInt = BigInt("11eb4", 16) - val OuterCallFirstRaw: BigInt = BigInt("fd2f4001", 16) - val OuterCallSetretRaw: BigInt = BigInt("5516", 16) - val OuterCallBytes: Seq[Int] = Seq(0x01, 0x40, 0x2f, 0xfd, 0x16, 0x55) - val OuterReturnPc: BigInt = BigInt("11ee0", 16) - val NewSp: BigInt = BigInt(231248) - val OldSp: BigInt = BigInt(231408) - val Uimm: Int = 160 - val RaSlot: BigInt = BigInt(231400) - val LastSlot: BigInt = BigInt(231328) - val ArchitecturalA0: Int = 2 - val ArchitecturalX3: Int = 23 - - def decodeDstBegin(raw: BigInt): Int = ((raw >> 15) & 0x1f).toInt - - def decodeDstEnd(raw: BigInt): Int = ((raw >> 20) & 0x1f).toInt - - def decodeImmediate(raw: BigInt): Int = - ((((raw >> 7) & 0x1f) << 10) | (((raw >> 25) & 0x7f) << 3)).toInt - - def decodeOuterCallTargetPc(pc: BigInt, raw32: BigInt): BigInt = { - require((raw32 & BigInt("7fff", 16)) == BigInt("4001", 16)) - val imm17 = ((raw32 >> 15) & BigInt("1ffff", 16)).toInt - val signed = if ((imm17 & 0x10000) != 0) imm17 - 0x20000 else imm17 - pc + signed * 2 - } - - def decodeOuterCallReturnPc(pc: BigInt, setretRaw: BigInt): BigInt = { - require((setretRaw & BigInt("f83f", 16)) == BigInt("5016", 16)) - pc + 4 + (((setretRaw >> 6) & 0x1f).toInt * 2) - } - - def templateRegisters(begin: Int, end: Int): Seq[Int] = { - require(begin >= ArchitecturalA0 && begin <= ArchitecturalX3) - require(end >= ArchitecturalA0 && end <= ArchitecturalX3) - Iterator - .iterate(begin)(reg => if (reg == ArchitecturalX3) ArchitecturalA0 else reg + 1) - .take(ArchitecturalX3 - ArchitecturalA0 + 1) - .takeWhile(_ != end) - .toSeq :+ end - } - - def saveSlots(newSp: BigInt, uimm: Int, registerCount: Int): Seq[BigInt] = - (0 until registerCount).map(index => newSp + uimm - 8 - index * 8) -} - -class LinxCoreFentryFretNaturalObservationSpec extends AnyFunSuite { - test("public autonomous top exposes every verifier-owned observation") { - val core = CoreParams( - robEntries = LinxCoreBenchmarkAutonomousTop.BenchmarkRobEntries, - commitWidth = 1 - ) - val p = LinxCoreBenchmarkAutonomousTop.interfaceParamsFor(core) - val traceParams = LinxCoreBenchmarkAutonomousTop.traceParamsFor(p) - val io = new LinxCoreBenchmarkAutonomousTopIO(p, traceParams) - - assert(io.commit.rows.length == 1) - assert(io.commit.rows.head.identity.bid.getWidth == 32) - assert(io.commit.rows.head.identity.gid.getWidth == 32) - assert(io.commit.rows.head.identity.rid.getWidth == 32) - assert(io.commit.rows.head.rob.value.getWidth == p.robIndexWidth) - assert(io.commit.rows.head.blockBid.getWidth == p.blockBidWidth) - assert(io.commit.rows.head.wb.reg.getWidth == traceParams.regWidth) - assert(io.storeObserveValid.getWidth == 1) - assert(io.storeObserveBid.getWidth == 32) - assert(io.storeObserveGid.getWidth == 32) - assert(io.storeObserveRid.getWidth == 32) - assert(io.storeObserveRobValue.getWidth == p.robIndexWidth) - assert(io.storeObserveBlockBid.getWidth == p.blockBidWidth) - assert(io.loadLookupValid.getWidth == 1) - assert(io.loadLookupAddr.getWidth == 64) - assert(io.loadLookupPc.getWidth == 64) - assert(io.loadLookupData.getWidth == 64) - assert(io.debugExecuteAcceptedIdentityValid.getWidth == 1) - assert(io.debugExecuteAcceptedBidValue.getWidth == p.robIndexWidth) - assert(io.debugExecuteAcceptedRidValue.getWidth == p.robIndexWidth) - assert(io.debugExecuteAcceptedStid.getWidth == p.threadIdWidth) - assert(io.debugLocalExecuteCompleteValid.getWidth == 1) - assert(io.debugExecuteCompleteRobValue.getWidth == p.robIndexWidth) - assert(io.debugMarkerRedirectFire.getWidth == 1) - assert(io.debugMarkerRedirectPc.getWidth == 64) - assert(io.sourceRestartValid.getWidth == 1) - assert(io.sourceRestartPc.getWidth == 64) - } - - test("independent decode and CTGen register ring establish same-frame shape") { - import LinxCoreFentryFretNaturalObservationReference._ - - val raw32 = OuterCallBytes.take(4).zipWithIndex - .map { case (byte, index) => BigInt(byte) << (8 * index) }.sum - val setret = OuterCallBytes.drop(4).zipWithIndex - .map { case (byte, index) => BigInt(byte) << (8 * index) }.sum - - assert(raw32 == OuterCallFirstRaw) - assert(setret == OuterCallSetretRaw) - assert(decodeOuterCallTargetPc(OuterCallPc, raw32) == FentryPc) - assert(decodeOuterCallReturnPc(OuterCallPc, setret) == OuterReturnPc) - assert(decodeDstBegin(FentryRaw) == 10) - assert(decodeDstEnd(FentryRaw) == 19) - assert(decodeImmediate(FentryRaw) == Uimm) - assert(decodeDstBegin(FretRaw) == 10) - assert(decodeDstEnd(FretRaw) == 19) - assert(decodeImmediate(FretRaw) == Uimm) - - val normal = templateRegisters(10, 19) - assert(normal == 10.to(19)) - val slots = saveSlots(NewSp, Uimm, normal.length) - assert(OldSp - NewSp == Uimm) - assert(slots.head == RaSlot) - assert(slots.last == LastSlot) - - assert(templateRegisters(22, 3) == Seq(22, 23, 2, 3)) - assertThrows[IllegalArgumentException](templateRegisters(1, 3)) - assertThrows[IllegalArgumentException](templateRegisters(22, 24)) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendAluTraceTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFrontendAluTraceTopSpec.scala deleted file mode 100644 index 3344bd37..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendAluTraceTopSpec.scala +++ /dev/null @@ -1,39 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreFrontendAluTraceTopSpec extends AnyFunSuite { - test("interface and trace parameters follow the reduced ALU trace top configuration") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendAluTraceTopIO(p, trace) - - assert(p.robEntries == 8) - assert(p.commitWidth == 2) - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - assert(io.in.window.getWidth == 64) - assert(io.operandData.length == 3) - assert(io.operandData.head.getWidth == 64) - assert(io.executeCompleteRobValue.getWidth == 3) - assert(io.commit.rows.length == 2) - } - - test("LinxCoreFrontendAluTraceTop elaborates frontend, rename, ROB, and ALU execute") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendAluTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendAluTraceTop")) - assert(sv.contains("module F4DecodeWindow")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("module DispatchROBAllocator")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("io_executeCompleteValid")) - assert(sv.contains("io_commitContractError")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTopSpec.scala deleted file mode 100644 index a442dcc9..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTopSpec.scala +++ /dev/null @@ -1,2267 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import java.nio.file.{Files, Paths} -import linxcore.common.{CoreParams, ScalarLsuParams} -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreFrontendFetchRfAluTraceTopSpec extends AnyFunSuite { - private def topSourceText: String = { - val candidates = Seq( - Paths.get("src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala"), - Paths.get("chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala")) - val path = candidates.find(Files.exists(_)).getOrElse(candidates.head) - Files.readString(path) - } - - private def executeSourceText: String = { - val candidates = Seq( - Paths.get("src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala"), - Paths.get("chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala")) - val path = candidates.find(Files.exists(_)).getOrElse(candidates.head) - Files.readString(path) - } - - test("interface combines live fetch source with RF-backed issue and ALU diagnostics") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(p.robEntries == 8) - assert(p.commitWidth == 2) - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - assert(io.startPc.getWidth == 64) - assert(io.bfuBodyValid.getWidth == 1) - assert(io.bfuHeaderPc.getWidth == 64) - assert(io.bfuHSizeBytes.getWidth == 64) - assert(io.bfuBSizeBytes.getWidth == 64) - assert(io.bfuStaticGeometryValid.getWidth == 1) - assert(io.bfuStaticHeaderActive.getWidth == 1) - assert(io.bfuStaticLearnedFire.getWidth == 1) - assert(io.bfuStaticResolvedLearnedFire.getWidth == 1) - assert(io.bfuResolvedBodyEndAccepted.getWidth == 1) - assert(io.bfuResolvedBodyEndHeaderMismatch.getWidth == 1) - assert(io.bfuResolvedBodyEndInactiveDrop.getWidth == 1) - assert(io.bfuResolvedBodyEndFlushDrop.getWidth == 1) - assert(io.bfuResolvedBodyEndUnderflow.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimeSelected.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceReplaySelected.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimeReplayComparable.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimeReplayMatch.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimeReplayMismatch.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimeFeedbackFire.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePending.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePendingConsumeFire.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePendingDropMismatch.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePendingCandidateComparable.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePendingCandidateMatch.getWidth == 1) - assert(io.bfuResolvedBodyEndSourceRuntimePendingCandidateMismatch.getWidth == 1) - assert(io.bfuPendingRuntimeCandidateValid.getWidth == 1) - assert(io.bfuPendingRuntimeCandidatePendingWithoutActiveHeader.getWidth == 1) - assert(io.bfuPendingRuntimeCandidateActiveHeaderMismatch.getWidth == 1) - assert(io.bfuPendingRuntimeCandidateReplayComparable.getWidth == 1) - assert(io.bfuPendingRuntimeCandidateReplayMatch.getWidth == 1) - assert(io.bfuPendingRuntimeCandidateReplayMismatch.getWidth == 1) - assert(io.bfuRuntimeBodyEndOraclePending.getWidth == 1) - assert(io.bfuRuntimeBodyEndOracleCaptureFire.getWidth == 1) - assert(io.bfuRuntimeBodyEndOracleReplayComparable.getWidth == 1) - assert(io.bfuRuntimeBodyEndOracleReplayMatch.getWidth == 1) - assert(io.bfuRuntimeBodyEndOracleReplayMismatch.getWidth == 1) - assert(io.bfuRuntimeBodyEndOracleOverwritePending.getWidth == 1) - assert(io.bfuStaticExternalComparable.getWidth == 1) - assert(io.bfuStaticExternalMatch.getWidth == 1) - assert(io.bfuStaticExternalMismatch.getWidth == 1) - assert(io.bfuStaticExternalHeaderMismatch.getWidth == 1) - assert(io.bfuStaticExternalHSizeMismatch.getWidth == 1) - assert(io.bfuStaticExternalBSizeMismatch.getWidth == 1) - assert(io.bfuBodyCutArmComparable.getWidth == 1) - assert(io.bfuBodyCutArmAccepted.getWidth == 1) - assert(io.bfuBodyCutArmMismatch.getWidth == 1) - assert(io.bfuBodyCutArmHeaderMismatch.getWidth == 1) - assert(io.bfuBodyCutArmHSizeMismatch.getWidth == 1) - assert(io.bfuBodyCutArmBSizeMismatch.getWidth == 1) - assert(io.fetchReqPc.getWidth == 64) - assert(io.fetchRespWindow.getWidth == 64) - assert(io.sourceAdvanceBytes.getWidth == 4) - assert(io.reducedBodyCutActive.getWidth == 1) - assert(io.reducedBodyCutFire.getWidth == 1) - assert(io.reducedBodyCutAdvanceBytes.getWidth == 4) - assert(io.denseSlotQueueInFire.getWidth == 1) - assert(io.denseSlotQueueOutFire.getWidth == 1) - assert(io.denseSlotQueueInSlotCount.getWidth == 3) - assert(io.denseSlotQueueCount.getWidth == 4) - assert(io.denseSlotQueueHeadSlot.getWidth == 2) - assert(io.admittedMarkerDrainBarrier.getWidth == 1) - assert(io.blockMarkerSkipFire.getWidth == 1) - assert(io.blockMarkerMixedPacket.getWidth == 1) - assert(io.blockMarkerPc.getWidth == 64) - assert(io.blockMarkerInsn.getWidth == 64) - assert(io.blockMarkerLen.getWidth == 4) - assert(io.blockMarkerTarget.getWidth == 64) - assert(io.blockMarkerAllocReady.getWidth == 1) - assert(io.blockMarkerLifecycleConflict.getWidth == 1) - assert(io.blockMarkerAllocFire.getWidth == 1) - assert(io.blockMarkerAllocBid.getWidth == 64) - assert(io.blockMarkerActiveValid.getWidth == 1) - assert(io.blockMarkerActiveBid.getWidth == 64) - assert(io.blockMarkerActiveTarget.getWidth == 64) - assert(io.blockMarkerStopRedirectValid.getWidth == 1) - assert(io.blockMarkerStopRedirectPc.getWidth == 64) - assert(io.rfInitArchTag.getWidth == 6) - assert(io.rfInitData.getWidth == 64) - assert(io.rfReadyMask.getWidth == 64) - assert(io.issueQueueCount.getWidth == 3) - assert(io.issueQueueHeadPc.getWidth == 64) - assert(io.issueQueueHeadOpcode.getWidth == 12) - assert(io.issueQueueHeadSrcValidMask.getWidth == 3) - assert(io.issueQueueHeadSrcClass.length == 3) - assert(io.issueQueueHeadSrcPhysTag.head.getWidth == 6) - assert(io.issueQueueHeadSrcRelTag.head.getWidth == 6) - assert(io.issueQueueSelectedIndex.getWidth == 2) - assert(io.decRenValid.getWidth == 1) - assert(io.decRenHeadPc.getWidth == 64) - assert(io.decRenHeadRidValid.getWidth == 1) - assert(io.decRenHeadRidValue.getWidth == 3) - assert(io.robRenameUpdateAttemptValid.getWidth == 1) - assert(io.robRenameUpdateReady.getWidth == 1) - assert(io.robRenameUpdateIgnored.getWidth == 1) - assert(io.localTReadyMask.getWidth == 4) - assert(io.localUReadyMask.getWidth == 4) - assert(io.localTPendingCount.getWidth == 3) - assert(io.localUPendingCount.getWidth == 3) - assert(io.localIncomingUsesLocal.getWidth == 1) - assert(io.localIncomingBlocked.getWidth == 1) - assert(io.decodeBlockedByRob.getWidth == 1) - assert(io.decodeBlockedByOutput.getWidth == 1) - assert(io.tuRenameSourceUnderflowMask.getWidth == 3) - assert(io.executeCompleteRobValue.getWidth == 3) - assert(io.executeLoadWaitHold.getWidth == 1) - assert(io.loadLookupPc.getWidth == 64) - assert(io.loadLookupDstValid.getWidth == 1) - assert(io.loadLookupDstKind.getWidth == 2) - assert(io.loadLookupDstArchTag.getWidth == 6) - assert(io.loadLookupDstRelTag.getWidth == 6) - assert(io.loadLookupDstPhysTag.getWidth == 6) - assert(io.loadLookupDstOldPhysTag.getWidth == 6) - assert(io.loadLookupExecuteGranted.getWidth == 1) - assert(io.loadLookupReplayGranted.getWidth == 1) - assert(io.reducedStoreDispatchEnabled.getWidth == 1) - assert(io.reducedStoreExecCompleteStoreValid.getWidth == 1) - assert(io.reducedStoreExecCaptureFire.getWidth == 1) - assert(io.reducedStoreExecCaptureBlocked.getWidth == 1) - assert(io.reducedStoreExecCaptureDuplicate.getWidth == 1) - assert(io.reducedStoreExecStaMatch.getWidth == 1) - assert(io.reducedStoreExecStdMatch.getWidth == 1) - assert(io.reducedStoreExecValidMask.getWidth == 4) - assert(io.reducedStoreExecBufferCount.getWidth == 3) - assert(io.reducedStoreStaExecValid.getWidth == 1) - assert(io.reducedStoreStdExecValid.getWidth == 1) - assert(io.reducedStoreCommitStoreSeen.getWidth == 1) - assert(io.reducedStoreCommitStoreMatched.getWidth == 1) - assert(io.reducedStoreCommitStoreUnmatched.getWidth == 1) - assert(io.reducedStoreCommitMatchMask.getWidth == 8) - assert(io.reducedStoreCommitPendingMarkMask.getWidth == 8) - assert(io.reducedStoreCommitPendingFreeMask.getWidth == 8) - assert(io.reducedStoreCommitPendingMarkCount.getWidth == 4) - assert(io.reducedStoreCommitPendingFreeCount.getWidth == 4) - assert(io.reducedStoreCommitMarkValid.getWidth == 1) - assert(io.reducedStoreCommitMarkIndex.getWidth == 3) - assert(io.reducedStoreCommitMarkAccepted.getWidth == 1) - assert(io.reducedStoreCommitMarkIgnored.getWidth == 1) - assert(io.reducedStoreCommitFreeValid.getWidth == 1) - assert(io.reducedStoreCommitFreeIndex.getWidth == 3) - assert(io.reducedStoreCommitFreeAccepted.getWidth == 1) - assert(io.reducedStoreCommitFreeAcceptedMask.getWidth == 8) - assert(io.reducedStoreCommitFreeCount.getWidth == 4) - assert(io.reducedStoreDrainEnqueueAccepted.getWidth == 1) - assert(io.reducedStoreDrainEnqueueDuplicate.getWidth == 1) - assert(io.reducedStoreDrainIssueValidMask.getWidth == 2) - assert(io.reducedStoreDrainIssueCount.getWidth == 2) - assert(io.reducedStoreDrainEarlyFreeMask.getWidth == 8) - assert(io.reducedStoreDrainQueueCount.getWidth == 4) - assert(io.reducedStoreDrainEmpty.getWidth == 1) - assert(io.reducedStoreDrainOrderError.getWidth == 1) - assert(io.reducedStoreScbReadyForDrain.getWidth == 1) - assert(io.reducedStoreScbAcceptedMask.getWidth == 4) - assert(io.reducedStoreScbStalledMask.getWidth == 4) - assert(io.reducedStoreScbCommitFreeMaskValid.getWidth == 1) - assert(io.reducedStoreScbCommitFreeMask.getWidth == 8) - assert(io.reducedStoreScbCommitFreeCount.getWidth == 3) - assert(io.reducedStoreScbValidMask.getWidth == 8) - assert(io.reducedStoreScbEntryCount.getWidth == 4) - assert(io.reducedStoreMemoryValidMask.getWidth == 64) - assert(io.reducedStoreMemoryLineCount.getWidth == 7) - assert(io.reducedStoreMemoryLoadForwardMask.getWidth == 8) - assert(io.reducedStoreMemoryStoreDroppedMask.getWidth == 8) - assert(io.reducedStoreCommitBypassValidMask.getWidth == 2) - assert(io.reducedStoreCommitBypassBid.length == 2) - assert(io.reducedStoreCommitBypassLsId.length == 2) - assert(io.reducedStoreCommitBypassLsId.head.getWidth == 32) - assert(io.reducedStoreResidentForwardMask.getWidth == 8) - assert(io.reducedStoreResidentWaitMask.getWidth == 8) - assert(io.reducedStoreResidentEligibleMask.getWidth == 8) - assert(io.reducedStoreResidentReadyForward.getWidth == 1) - assert(io.reducedStoreResidentWaitBlocked.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreValid.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreIndex.getWidth == 3) - assert(io.reducedStoreResidentWaitStoreBidValid.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreBidWrap.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreBidValue.getWidth == 3) - assert(io.reducedStoreResidentWaitStoreLsIdValid.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreLsIdWrap.getWidth == 1) - assert(io.reducedStoreResidentWaitStoreLsIdValue.getWidth == 3) - assert(io.reducedStoreResidentWaitStorePc.getWidth == 64) - assert(io.reducedStoreResidentLoadCrossesLine.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeValid.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeSelected.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeIdentityMatch.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeReady.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeCrossesLine.getWidth == 1) - assert(io.reducedStoreResidentReplayWakeLineAddr.getWidth == 64) - assert(io.reducedStoreResidentReplayWakeByteMask.getWidth == 64) - assert(io.reducedLoadWaitReplayActive.getWidth == 1) - assert(io.reducedLoadWaitReplayCaptureAccepted.getWidth == 1) - assert(io.reducedLoadWaitReplayClearValid.getWidth == 1) - assert(io.reducedLoadWaitReplayStoredWaitValid.getWidth == 1) - assert(io.reducedLoadWaitReplayStoredWaitPc.getWidth == 64) - assert(io.reducedLoadWaitReplayRelaunchValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchPc.getWidth == 64) - assert(io.reducedLoadWaitReplayRelaunchAddr.getWidth == 64) - assert(io.reducedLoadWaitReplayRelaunchSize.getWidth == 7) - assert(io.reducedLoadWaitReplayRelaunchDstValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchDstKind.getWidth == 2) - assert(io.reducedLoadWaitReplayRelaunchDstArchTag.getWidth == 6) - assert(io.reducedLoadWaitReplayRelaunchDstRelTag.getWidth == 6) - assert(io.reducedLoadWaitReplayRelaunchDstPhysTag.getWidth == 6) - assert(io.reducedLoadWaitReplayRelaunchDstOldPhysTag.getWidth == 6) - assert(io.reducedLoadWaitReplayRelaunchBidValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchBidWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchBidValue.getWidth == 3) - assert(io.reducedLoadWaitReplayRelaunchGidValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchGidWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchGidValue.getWidth == 3) - assert(io.reducedLoadWaitReplayRelaunchRidValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchRidWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchRidValue.getWidth == 3) - assert(io.reducedLoadWaitReplayRelaunchLsIdValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchLsIdWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchLsIdValue.getWidth == 3) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreIdValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreIdWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreIdValue.getWidth == 3) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdValid.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdWrap.getWidth == 1) - assert(io.reducedLoadWaitReplayRelaunchYoungestStoreLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayQueueOutYoungestStoreIdValid.getWidth == 1) - assert(io.reducedLoadReplayQueueOutYoungestStoreIdWrap.getWidth == 1) - assert(io.reducedLoadReplayQueueOutYoungestStoreIdValue.getWidth == 3) - assert(io.reducedLoadReplayQueueOutDstValid.getWidth == 1) - assert(io.reducedLoadReplayQueueOutDstKind.getWidth == 2) - assert(io.reducedLoadReplayQueueOutDstArchTag.getWidth == 6) - assert(io.reducedLoadReplayQueueOutDstRelTag.getWidth == 6) - assert(io.reducedLoadReplayQueueOutDstPhysTag.getWidth == 6) - assert(io.reducedLoadReplayQueueOutDstOldPhysTag.getWidth == 6) - assert(io.reducedLoadReplayQueueOutYoungestStoreLsIdValid.getWidth == 1) - assert(io.reducedLoadReplayQueueOutYoungestStoreLsIdWrap.getWidth == 1) - assert(io.reducedLoadReplayQueueOutYoungestStoreLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayLiqAllocEnabled.getWidth == 1) - assert(io.reducedLoadReplayLiqAllocConsumeReady.getWidth == 1) - assert(io.reducedLoadReplayLiqAllocCandidateUsable.getWidth == 1) - assert(io.reducedLoadReplayLiqAllocBlockedByAlloc.getWidth == 1) - assert(io.reducedLoadReplayLiqAllocAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqAllocIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqAllocLoadIdValue.getWidth == 3) - assert(io.reducedLoadReplayLiqOccupiedMask.getWidth == 8) - assert(io.reducedLoadReplayLiqWaitMask.getWidth == 8) - assert(io.reducedLoadReplayLiqWaitStoreMask.getWidth == 8) - assert(io.reducedLoadReplayLiqReplayWakeWaitStoreClearMask.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchWaitMask.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchRequestCompleteMask.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchDataHitMask.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchCandidateMask.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchDriveValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchCandidateCount.getWidth == 4) - assert(io.reducedLoadReplayLiqLaunchSelectedLoadIdValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchSelectedBidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchSelectedGidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchSelectedRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchSelectedLoadLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLaunchSelectedPc.getWidth == 64) - assert(io.reducedLoadReplayLiqLaunchSelectedAddr.getWidth == 64) - assert(io.reducedLoadReplayLiqLaunchSelectedSize.getWidth == 7) - assert(io.reducedLoadReplayLiqLaunchSelectedDstValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchSelectedDstKind.getWidth == 2) - assert(io.reducedLoadReplayLiqLaunchSelectedDstArchTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLaunchSelectedDstRelTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLaunchSelectedDstPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLaunchSelectedDstOldPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLaunchSelectedRequestByteMask.getWidth == 64) - assert(io.reducedLoadReplayLiqBaseLookupValid.getWidth == 1) - assert(io.reducedLoadReplayLiqBaseLookupCrossesLine.getWidth == 1) - assert(io.reducedLoadReplayLiqBaseLookupPc.getWidth == 64) - assert(io.reducedLoadReplayLiqBaseLookupAddr.getWidth == 64) - assert(io.reducedLoadReplayLiqBaseLookupSize.getWidth == 7) - assert(io.reducedLoadReplayLiqBaseLookupRequestByteMask.getWidth == 64) - assert(io.reducedLoadReplayLiqBaseLineValidMask.getWidth == 64) - assert(io.reducedLoadReplayLiqBaseDataReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqBaseLookupGranted.getWidth == 1) - assert(io.reducedLoadReplayLiqBaseLookupBlockedByExecute.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBaseDataReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessSourcesReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByBaseData.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByScb.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchReadinessBlockedByReturn.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSourceReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbSourceReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnSourceReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnBlockedByBaseData.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnBlockedByScb.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetConsumerReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetAvailable.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetBlockedBySources.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetBlockedByBudgetDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBudgetBlockedByConsumer.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitPipeBudgetAvailable.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitMask.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitBlockedBySources.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipePermitBlockedByPipeBudget.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeAvailableMask.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeAvailable.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeSelectedPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBlockedBySources.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPipeBlockedByNoPipe.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessSelectedPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessBlockedBySources.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnReadinessBlockedByReturnPipe.getWidth == 1) - } - - test("interface exposes load-return, store, and retirement diagnostics") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqReturnDataCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataRequestByteMask.getWidth == 64) - assert(io.reducedLoadReplayLiqReturnDataBytesComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataCrossLine.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataSizeSupported.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataRawData.getWidth == 64) - assert(io.reducedLoadReplayLiqReturnData.getWidth == 64) - assert(io.reducedLoadReplayLiqReturnDataValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByZeroSize.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByUnsupportedSize.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByCrossLine.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnDataBlockedByIncompleteBytes.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishDataReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishBlockedByData.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnPublishBlockedByConsumer.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPayloadGidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadGidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadGidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPayloadRidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadRidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPayloadLoadLsIdValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadLoadLsIdWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadLoadLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPayloadPc.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPayloadAddr.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPayloadSize.getWidth == 7) - assert(io.reducedLoadReplayLiqLretPayloadDstValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadDstKind.getWidth == 2) - assert(io.reducedLoadReplayLiqLretPayloadDstArchTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPayloadDstRelTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPayloadDstPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPayloadDstOldPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPayloadData.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPayloadPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadSpecWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadStackValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadWakeupRequired.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadBlockedByData.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPayloadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadFireValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsAgu.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadTargetIsLda.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidFireWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidPayloadWithoutFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPayloadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadFireValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsAgu.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadTargetIsLda.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadDstPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadData.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidFireWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidPayloadWithoutFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPayloadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadFireValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsAgu.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadTargetIsLda.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidWrap.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstKind.getWidth == 2) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstPhysTag.getWidth == 6) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadReducedGprWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadNonGprWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidFireWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidPayloadWithoutFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireMask.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadFireMask.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteMissingPayloadFireMask.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteUnexpectedPayloadFireMask.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadMatchesFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFutureClearEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidFireWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidPayloadWithoutFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentPreClearEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentPermitEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentPostFireEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentLiveClear.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedPermit.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentMismatchedFireComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearIntentInvalidEvidenceWithoutSlot.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadyEmpty.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadySameCycleEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadySameCycleReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadyFutureAdvance.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadyMatchesCurrent.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadyBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RefillReadyInvalidLiveClearWithoutIntent.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkEnqueueReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkEnqueueAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkEnqueueDropped.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkDrainValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkDrainFire.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkPending.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkFull.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkEmpty.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkCount.getWidth == 2) - assert(io.reducedLoadReplayLiqLretSinkBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkBlockedByNoPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkBlockedByFull.getWidth == 1) - assert(io.reducedLoadReplayLiqLretSinkBlockedByDrain.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitPipeOccupiedMask.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitPipeFreeMask.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitAnyPipeFree.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitSelectedPipeIndex.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitBlockedByNoEntry.getWidth == 1) - assert(io.reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataRobRowValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataRobRowNeedFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataWouldDrain.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataSetMemDataValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByNoEntry.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByInvalidEntry.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByDrain.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByRobMissing.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataBlockedByNeedFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackValid.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackTag.getWidth == 6) - assert(io.reducedLoadReplayLiqWritebackData.getWidth == 64) - assert(io.reducedLoadReplayLiqWritebackIgnoredNoDestination.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackIgnoredNonGprDestination.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackArbiterReplayEnabled.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackArbiterSelectedExecute.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackArbiterSelectedReplay.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackArbiterReplayBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqWritebackArbiterReplayBlockedByExecute.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectLretReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectWritebackReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectWakeupReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectBlockedByNoPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectBlockedByLret.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectBlockedByWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqSideEffectBlockedByWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlLiveEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlArmed.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlFire.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlBlockedByNoPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlBlockedByPublish.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlBlockedBySideEffects.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishControlBlockedByLiveDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestValid.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestLret.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestMask.getWidth == 3) - assert(io.reducedLoadReplayLiqPublishRequestBlockedByNoFire.getWidth == 1) - assert(io.reducedLoadReplayLiqPublishRequestInvalidFireWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupRequired.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupValid.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupKind.getWidth == 2) - assert(io.reducedLoadReplayLiqWakeupTag.getWidth == 6) - assert(io.reducedLoadReplayLiqWakeupReducedGprValid.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupNonGpr.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupSuppressedNotRequired.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupIgnoredNoDestination.getWidth == 1) - assert(io.reducedLoadReplayLiqWakeupBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqRepickMask.getWidth == 8) - assert(io.reducedLoadReplayLiqMissMask.getWidth == 8) - assert(io.reducedLoadReplayLiqResolvedMask.getWidth == 8) - assert(io.reducedLoadReplayLiqE4UpdateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqE4UpdateIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqE4MissKind.getWidth == 3) - assert(io.reducedLoadReplayLiqE4WakeupValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLhqRecordValid.getWidth == 1) - assert(io.reducedLoadReplayLiqResidentCount.getWidth == 4) - assert(io.reducedLoadReplayResolveQueuePushReady.getWidth == 1) - assert(io.reducedLoadReplayResolveQueuePushAccepted.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueClearPending.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueClearAccepted.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueClearIndex.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueRetireValid.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueRetireIsLoadStore.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueRetireIsLoad.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueRetireIsStore.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueRetireBidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueRetireRidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueRetireLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueuePreciseFlushValid.getWidth == 1) - assert(io.reducedLoadReplayResolveQueuePreciseFlushBidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueuePreciseFlushRidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueuePreciseFlushLsIdValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueFlushPruneMask.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueFlushPruneCount.getWidth == 4) - assert(io.reducedLoadReplayResolveQueueRetireMask.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueRetireCount.getWidth == 4) - assert(io.reducedLoadReplayResolveQueueValidMask.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueCount.getWidth == 4) - assert(io.reducedLoadReplayResolveQueueEmpty.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueFull.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueHeadValid.getWidth == 1) - assert(io.reducedLoadReplayResolveQueueHeadPeId.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueHeadStid.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueHeadTid.getWidth == 8) - assert(io.reducedLoadReplayResolveQueueHeadPc.getWidth == 64) - assert(io.reducedLoadReplayResolveQueueHeadAddr.getWidth == 64) - assert(io.reducedLoadReplayResolveQueueHeadSize.getWidth == 7) - assert(io.reducedLoadReplayResolveQueueHeadBidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueHeadGidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueHeadRidValue.getWidth == 3) - assert(io.reducedLoadReplayResolveQueueHeadLsIdValue.getWidth == 3) - assert(io.reducedMdbConflictStoreValid.getWidth == 1) - assert(io.reducedMdbConflictActiveCandidateMask.getWidth == 8) - assert(io.reducedMdbConflictResolveCandidateMask.getWidth == 8) - assert(io.reducedMdbConflictWaitStoreMask.getWidth == 8) - assert(io.reducedMdbConflictWaitStoreCount.getWidth == 4) - assert(io.reducedMdbConflictValid.getWidth == 1) - assert(io.reducedMdbConflictActiveIndex.getWidth == 3) - assert(io.reducedMdbConflictResolveIndex.getWidth == 3) - assert(io.reducedMdbConflictOrdinal.getWidth == 4) - assert(io.reducedMdbConflictInnerFlush.getWidth == 1) - assert(io.reducedMdbConflictNukeFlush.getWidth == 1) - assert(io.reducedMdbConflictLoadBidValue.getWidth == 3) - assert(io.reducedMdbConflictLoadLsIdValue.getWidth == 3) - assert(io.reducedMdbConflictStoreBidValue.getWidth == 3) - assert(io.reducedMdbConflictStoreLsIdValue.getWidth == 3) - assert(io.reducedMdbFanoutLookupValid.getWidth == 1) - assert(io.reducedMdbFanoutLookupReady.getWidth == 1) - assert(io.reducedMdbFanoutLookupAccepted.getWidth == 1) - assert(io.reducedMdbFanoutLookupProcessed.getWidth == 1) - assert(io.reducedMdbFanoutDeleteValid.getWidth == 1) - assert(io.reducedMdbFanoutDeleteReady.getWidth == 1) - assert(io.reducedMdbFanoutDeleteAccepted.getWidth == 1) - assert(io.reducedMdbFanoutDeleteProcessed.getWidth == 1) - assert(io.reducedMdbFanoutPhaseStalledByFanout.getWidth == 1) - assert(io.reducedMdbFanoutLuOutValid.getWidth == 1) - assert(io.reducedMdbFanoutLuOutHit.getWidth == 1) - assert(io.reducedMdbFanoutLuOutStoreBidValue.getWidth == 3) - assert(io.reducedMdbFanoutSuOutValid.getWidth == 1) - assert(io.reducedMdbFanoutSuOutHit.getWidth == 1) - assert(io.reducedMdbFanoutSuOutStoreBidValue.getWidth == 3) - assert(io.reducedMdbFanoutRecordValid.getWidth == 1) - assert(io.reducedMdbFanoutRecordReady.getWidth == 1) - assert(io.reducedMdbFanoutRecordAccepted.getWidth == 1) - assert(io.reducedMdbFanoutRecordProcessed.getWidth == 1) - assert(io.reducedMdbFanoutBmdbReportValid.getWidth == 1) - assert(io.reducedMdbFanoutBmdbLoadBidValue.getWidth == 3) - assert(io.reducedMdbFanoutBmdbStoreBidValue.getWidth == 3) - assert(io.reducedMdbFanoutBmdbStoreStid.getWidth == 8) - assert(io.reducedMdbFanoutDeleteMatched.getWidth == 1) - assert(io.reducedMdbFanoutDeleteReleased.getWidth == 1) - assert(io.reducedMdbFanoutDeleteDroppedBelowStall.getWidth == 1) - assert(io.reducedMdbFanoutRecordOverflow.getWidth == 1) - assert(io.reducedMdbFanoutRecordOrderIllegal.getWidth == 1) - assert(io.reducedMdbFanoutSsitValidMask.getWidth == 8) - assert(io.reducedMdbFanoutSuMatchedStore.getWidth == 1) - assert(io.reducedMdbFanoutSuStorePending.getWidth == 1) - assert(io.reducedMdbFanoutSuWakeupValid.getWidth == 1) - assert(io.reducedMdbFanoutSuWakeupIndex.getWidth == 3) - assert(io.reducedLoadWaitReplaySlotPc.getWidth == 64) - assert(io.reducedLoadWaitReplaySlotAddr.getWidth == 64) - assert(io.storeDispatchReady.getWidth == 1) - assert(io.storeDispatchFire.getWidth == 1) - assert(io.storeDispatchSplit.getWidth == 1) - assert(io.storeStaQueueValid.getWidth == 1) - assert(io.storeStdQueueValid.getWidth == 1) - assert(io.storeStaQueueCount.getWidth == 3) - assert(io.storeStdQueueCount.getWidth == 3) - assert(io.storeStqInsertIndex.getWidth == 3) - assert(io.storeStqOccupiedMask.getWidth == 8) - assert(io.storeStqAddrReadyMask.getWidth == 8) - assert(io.storeStqDataReadyMask.getWidth == 8) - assert(io.storeStqResidentCount.getWidth == 4) - assert(io.commit.rows.length == 2) - assert(io.robDeallocBlockLastValid.getWidth == 1) - assert(io.robDeallocBlockLastBlockBid.getWidth == 64) - assert(io.blockScalarDoneFire.getWidth == 1) - assert(io.blockScalarDoneBid.getWidth == 64) - assert(io.blockRetireFire.getWidth == 1) - assert(io.blockRetireBid.getWidth == 64) - assert(io.gprCommitAccepted.getWidth == 1) - assert(io.gprCommitBlockBid.getWidth == 64) - assert(io.gprCommittedMapQCount.getWidth == 6) - assert(io.gprReleasedPhysCount.getWidth == 7) - assert(io.blockAllocatedMask.getWidth == 8) - assert(io.blockCompleteMask.getWidth == 8) - assert(io.blockPendingMask.getWidth == 8) - } - - test("interface sizes scalar store structures independently from ROB identities") { - val core = CoreParams(robEntries = 8, commitWidth = 2, lsidWidth = 40) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val scalarLsu = ScalarLsuParams( - stqEntries = 16, - commitQueueEntries = 32, - commitIssueWidth = 4, - scbEntries = 64) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO( - p, - trace, - issueQueueDepth = 4, - scalarLsuParams = Some(scalarLsu), - physRegs = 64) - - assert(io.storeStqInsertIndex.getWidth == 4) - assert(io.storeStqOccupiedMask.getWidth == 16) - assert(io.reducedStoreCommitMarkIndex.getWidth == 4) - assert(io.reducedStoreCommitFreeIndex.getWidth == 4) - assert(io.reducedStoreResidentWaitStoreIndex.getWidth == 4) - assert(io.reducedMdbFanoutSuWakeupIndex.getWidth == 4) - assert(io.reducedStoreDrainIssueValidMask.getWidth == 4) - assert(io.reducedStoreDrainQueueCount.getWidth == 6) - assert(io.reducedStoreScbValidMask.getWidth == 64) - assert(io.reducedStoreScbEntryCount.getWidth == 7) - assert(io.reducedStoreCommitBypassBid.head.value.getWidth == 3) - assert(io.reducedStoreCommitBypassLsId.head.getWidth == 40) - } - - test("R667 scalar issue-bank diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.issueQueueBankOccupancy.length == 2) - assert(io.issueQueueBankOccupancy.head.getWidth == 2) - assert(io.issueQueueBankPickMask.getWidth == 2) - assert(io.issueQueueBankReadAttemptMask.getWidth == 2) - assert(io.issueQueueBankReadGrantMask.getWidth == 2) - assert(io.issueQueueBankIssueValidMask.getWidth == 2) - assert(io.issueQueueBankIssueGrantMask.getWidth == 2) - assert(io.issueQueueSimultaneousPick.getWidth == 1) - assert(io.issueQueueReadContention.getWidth == 1) - assert(io.issueQueueReadArbitrationLoss.getWidth == 1) - assert(io.issueQueueIssueContention.getWidth == 1) - assert(io.issueQueueProtocolError.getWidth == 1) - } - - test("R465 replay-LIQ MDB wait-plan diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedMdbLookupWaitPlanLookupHit.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanCandidateMask.getWidth == 8) - assert(io.reducedMdbLookupWaitPlanTargetIndex.getWidth == 3) - assert(io.reducedMdbLookupWaitPlanWaitIntentValid.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanRequestValid.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBlockedByNoTarget.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBlockedByMissingStoreIndex.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBlockedByMissingStoreLsId.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.active.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.valid.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.sourceStoreIndexFits.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.blockedByDisabled.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.blockedByFlush.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.blockedByNoRequest.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.invalidStoreIndexOutOfRange.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.invalidConflictingStatusWrite.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.invalidWaitStoreWithoutWaitStatus.getWidth == 1) - assert(io.reducedMdbLookupWaitPlanBridge.invalidReturnWithoutSplitSources.getWidth == 1) - } - - test("R389 replay-LIQ source-return SCB live-control diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnScbLiveActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveRequestActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveEvidenceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLivePending.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByNoPending.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnScbLiveBlockedByScbReturn.getWidth == 1) - } - - test("R390 replay-LIQ source-return store snapshot diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveRequestActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveEvidenceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLegacyReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByLegacySnapshot.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedBySnapshot.getWidth == 1) - } - - test("R439 replay-LIQ source-return store snapshot live-arm policy diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponsePortBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyBlockedByPolicyDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByNoLaunch.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRowMutationDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRequestQueue.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByAcceptedToken.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByNoRequest.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRowMutationDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRawSink.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByQueueFull.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByRawResponse.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestQueueCanAccept.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveSinkReady.getWidth == 1) - } - - test("R426 replay-LIQ source-return store snapshot precise-flush diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneMask.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePrecisePruneCount.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByPreciseFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneMask.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePrecisePruneCount.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByPreciseFlush.getWidth == 1) - } - - test("R485 replay-LIQ source-return store snapshot flow diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestControlBlockedByToken.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCanAccept.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenResidentValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenBlockedByOutstanding.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoIssue.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByStaleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadConsumed.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePending.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueFull.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueEmpty.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueCount.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByFull.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkResponseValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByNoRequest.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByRawSink.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByResponse.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEnqueueAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadConsumed.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePending.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueFull.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEmpty.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueCount.getWidth == 2) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByFull.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainDequeueReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainOrderedConsumed.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainStaleDropped.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoHead.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoAction.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupQueryValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupWaitStoreValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupRawDataValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupResponseDataValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotLookupStoreBypassComplete.getWidth == 1) - } - - test("R428 replay-LIQ row-mutation visibility diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateTargetMask.getWidth == 8) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationTargetReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetMask.getWidth == 8) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestTargetIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByNoTarget.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByLiveDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationInvalidMultiTarget.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationBridgeValid.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationSelectedSourceReturn.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationSourceConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationSourceStoreIndexFits.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationInvalidStoreIndexOutOfRange.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationInvalidConflictingStatusWrite.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationInvalidWaitStoreWithoutWaitStatus.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationInvalidReturnWithoutSplitSources.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationWriteEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationApplyValid.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationTargetEvidenceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationWriteConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationBlockedByBridge.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationBlockedByControl.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByInvalidRow.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByNotRepick.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByScbNotReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByE4UpdateConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByClearResolvedConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByReplayWakeConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByRefillConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByLaunchConflict.getWidth == 1) - assert(io.reducedLoadReplayLiqRowMutationControlBlockedByAllocationConflict.getWidth == 1) - } - - test("R440 replay-LIQ source-return response apply and row-state plan diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyTargetMask.getWidth == 8) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyWaitStore.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataMerge.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyDataNoMerge.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyMergedRequestComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoOrderedResponse.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNotRepick.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByWaitStore.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoData.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidOrderedWithoutPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataWithWaitStore.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidDataValidWithoutRawData.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyInvalidSuppressedDataWithoutWait.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanRewait.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataMerge.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanDataNoMerge.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanSetWaitStatus.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanKeepRepickStatus.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanClearReturnState.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanLineWrite.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanWaitStoreWrite.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextDataComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextScbReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStqReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStoreSourceReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanBlockedByNoApply.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidApplyWithoutStqReturned.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqReturnedWithoutApply.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqApplyWithoutScb.getWidth == 1) - } - - test("R391 replay-LIQ source-return store snapshot evidence diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceRequestValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceQueryActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceResponseAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotRequired.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceWaitStoreReplay.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoQuery.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoResponse.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByWaitStore.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidResponseWithoutQuery.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceInvalidDataWithWaitStore.getWidth == 1) - } - - test("R392 replay-LIQ source-return store snapshot query issue diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueRequestActive.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueValid.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByNoLaunch.getWidth == 1) - assert(io.reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedBySink.getWidth == 1) - } - - test("R364 replay W2 ROB completion diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputResolveValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ResolveArbiterInputRidValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceSinkReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteRobValue.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2RobCompleteSourceBlockedByExecute.getWidth == 1) - assert(io.robCompleteArbiterSelectedExecute.getWidth == 1) - assert(io.robCompleteArbiterSelectedReplay.getWidth == 1) - assert(io.robCompleteArbiterReplayBlockedByExecute.getWidth == 1) - assert(io.scalarLrReservationSetCandidate.getWidth == 1) - assert(io.scalarLrReservationSetAccepted.getWidth == 1) - assert(io.scalarLrReservationSetLineAddr.getWidth == 64) - assert(io.scalarLrReservationSetRidValue.getWidth == 3) - assert(io.scalarLrReservationValidStid0.getWidth == 1) - assert(io.scalarLrReservationLineStid0.getWidth == 64) - assert(io.scalarLrReservationCount.getWidth == 1) - assert(io.scalarLrReservationCommittedStoreInvalidate.getWidth == 1) - } - - test("R365 replay W2 clear commit guard diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardCommitClearReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardLiveClearReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardResolveMatchesSlot.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesSlot.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardRobMatchesResolve.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByNoRobComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByResolveSlotMismatch.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobSlotMismatch.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ClearCommitGuardBlockedByRobResolveMismatch.getWidth == 1) - } - - test("R366 replay W2 commit row candidate diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateRowFillValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateCompleteRowValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoMetadata.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoSourceTrace.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByInvalidSize.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNonGprDestination.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByRowFillDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateRowFillValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateCompleteRowValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoRecord.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoMetadata.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoSourceTrace.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByInvalidSize.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNonGprDestination.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByRowFillDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceInstructionReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceSourceReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoMetadata.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoSourceTrace.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupRowValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupInstructionValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByNeedFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByMissingInstruction.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceBeforeCompletion.getWidth == 1) - } - - test("R375 replay-LIQ launch source trace diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLaunchSelectedSourceTraceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchSelectedSource0Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchSelectedSource0Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchSelectedSource0Data.getWidth == 64) - assert(io.reducedLoadReplayLiqLaunchSelectedSource1Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLaunchSelectedSource1Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLaunchSelectedSource1Data.getWidth == 64) - } - - test("R376 replay-LIQ LRET and W2 source trace diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPayloadSourceTraceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadSource0Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadSource0Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLretPayloadSource0Data.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPayloadSource1Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPayloadSource1Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLretPayloadSource1Data.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSourceTraceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource0Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource0Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource0Data.getWidth == 64) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource1Valid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource1Reg.getWidth == 8) - assert(io.reducedLoadReplayLiqLretPipeW2SlotSource1Data.getWidth == 64) - } - - test("R545 replay-LIQ LRET ROB row-status blocker diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretIexDataRobRowBlockedByInvalidRid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataRobRowBlockedByFree.getWidth == 1) - assert(io.reducedLoadReplayLiqLretIexDataRobRowBlockedByStaleRid.getWidth == 1) - } - - test("R379 replay-LIQ return wakeup sink diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqReturnWakeupSinkCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkArmed.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkBlockedByNoWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkBlockedBySink.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWakeupSinkBlockedByLiveDisabled.getWidth == 1) - } - - test("R380 replay-LIQ return writeback sink diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqReturnWritebackSinkCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkArmed.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkReady.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkBlockedByNoWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkBlockedBySink.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnWritebackSinkBlockedByLiveDisabled.getWidth == 1) - } - - test("R381 replay-LIQ return side-effect live-control diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqReturnSideEffectLiveCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveRequiredMask.getWidth == 3) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveEnableMask.getWidth == 3) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByNoPayload.getWidth == 1) - assert(io.reducedLoadReplayLiqReturnSideEffectLiveBlockedByLiveDisabled.getWidth == 1) - } - - test("R549 replay W2 atomic request policy blockers have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByModeDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByPolicy.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoSideEffectSink.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoClearCommit.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRowFillCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoLifecycleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRequiredSideEffect.getWidth == 1) - } - - test("R367 replay W2 row-fill enable diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlPrerequisitesReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlRowFillEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoSideEffectCommit.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoClearCommit.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByLiveClearDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoReplayRowLifecycle.getWidth == 1) - } - - test("R368 replay W2 replay-row lifecycle diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCandidateValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleSlotIdentityValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleResolvedRowMatch.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleMatchCount.getWidth == 4) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByNoResolvedRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByMultipleResolvedRows.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByLifecycleClearDisabled.getWidth == 1) - } - - test("R370 replay W2 replay-row lifecycle request diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlRequestCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlLifecycleClearRequestEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByRequestInactive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoRowFillCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlBlockedByNoLifecycleRow.getWidth == 1) - } - - test("R581 retire-record lifecycle request probe diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeLivePromotionCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoLifecycleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoAtomicRequest.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillEnable.getWidth == 1) - } - - test("R582 retire-record atomic request probe diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeEvidenceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillCandidateAligned.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillEnableAligned.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoLifecycleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillEnable.getWidth == 1) - } - - test("R586 retire-record row-fill enable diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableRequestEvidenceValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableCandidateAligned.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoLifecycleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoRowFillCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureIntent.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureFromLifecycle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureBlockedByNoLifecycle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceClearAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValidWithoutRecord.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceRecordValidWithoutProvider.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCapturePhysicalComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackDuplicatePhysicalComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCompleteValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCapturePhysicalWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackDuplicatePhysicalWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackWritebackValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCapturePhysicalWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackDuplicatePhysicalWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackWakeupValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCapturePhysicalClear.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackDuplicatePhysicalClear.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackClearValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyAllCandidatesReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByPhysicalDuplicate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyNoPhysicalProbeActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackEmitProbeActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackLiveProbeActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyRetainedSoleOwnerEligible.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByGlobalFallbackDisabled - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicySideEffectEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackLiveCompleteSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackLiveWritebackSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackLiveWakeupSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackLiveClearSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRecordCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnSideEffectsReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRetireClearEvidenceReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnThenRetireReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderFallbackOwnerEligible.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingReturnSideEffect.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingRetireClearEvidence.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByOwnerDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionRecordCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionPreArmModelOrderReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionAnyPhysicalDuplicate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByNoRecord.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingFallbackCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingLifecycleEvidence.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByPhysicalDuplicate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByProbeActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorReturnSideEffectBundle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorModelOrderBundle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorPartial.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorSingle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorMulti.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorCount.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorNextRequiresBundleTransfer.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoRecord.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByPreArmNotReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoDuplicate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanPreArmReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanModelOrderBundle.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultTransferCandidate.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanRequiresPhysicalBundleSuppression - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultPromotionAlreadyReady - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoRecord.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPreArmNotReady.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoDuplicateVector.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPartialDuplicate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByProbeActive.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanTransferCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressionRequired.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanPhysicalBundleComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAtomicSuppressCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRobComplete.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRfWriteback.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressWakeup.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressLifecycleClear.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressMask.getWidth == 4) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAllOrNoneSuppress.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoTransferCandidate - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoSuppressionRequirement - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByIncompletePhysicalBundle - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeEnabledCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelectedMask.getWidth == 4) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeAllOrNoneInputMask.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByProbeDisabled - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByNoAtomicCandidate - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByPartialMask - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryCapture.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredMask.getWidth == 4) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredFullMask - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByNoSelection - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByPartialMask - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryClearedByFlush.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCaptureIdentity.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCapturedIdentityValid - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRegisteredCandidate - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRetainedRecordAligned - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifecycleRowAligned - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifetimeAligned.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityEligibleRegisteredMask - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNoCapturedIdentity - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingRecord - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByRidMismatch - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLoadLsIdMismatch - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingLifecycleEvidence - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLifecycleRowMismatch - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNotFullMask - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCaptureOwnership.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCapturedOwnershipValid - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredCandidate - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredRidValid - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLoadLsIdValid - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLifecycleRowReady - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredBundleReady - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipEligibleRegisteredMask - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNoCapturedOwnership - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingRid - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLoadLsId - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLifecycleRow - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNotFullMask - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskCandidate.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskEnabledCandidate - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRobComplete - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRfWriteback - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressWakeup.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressLifecycleClear - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressMask.getWidth == 4) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskAllOrNone.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByLiveMaskDisabled - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByNoEligibleOwnership - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFullMask.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFireCompleteAligned - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofClearIntentAligned - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLiveClearAligned - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofRowFillAligned.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLifecycleClearSuppressed - .getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofAllClearAligned.getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByPartialMask - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoFireComplete - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoClearIntent - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoLiveClear - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoRowFill - .getWidth == 1) - assert(io - .reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByLifecycleClearStillEnabled - .getWidth == 1) - } - - test("R371 replay W2 replay-row lifecycle commit permit diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitRowFillPermit.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitLifecycleClearCommitEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoSelection.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitBlockedByNoRowFillEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitInvalidRowFillWithoutSelection.getWidth == 1) - } - - test("R369 replay W2 replay-row clear-request diagnostics have stable widths") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleCandidate.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleClearEnable.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleSelected.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedValid.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedIndex.getWidth == 3) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestExistingAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestLifecycleAccepted.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlocked.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByExistingClear.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleRequestDisabled.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByNoLifecycleRow.getWidth == 1) - assert(io.reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestBlockedByLifecycleCommitDisabled.getWidth == 1) - } - - test("LinxCoreFrontendFetchRfAluTraceTop elaborates source, frontend, rename, RF, issue, ROB, and ALU execute") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchRfAluTraceTop")) - assert(sv.contains("module FrontendFetchPacketSource")) - assert(sv.contains("module F4DecodeWindow")) - assert(sv.contains("module F4DenseSlotQueue")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(!sv.contains("module BlockMarkerDecodeContext")) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("module ScalarIssueFabric")) - assert(sv.contains("module ScalarIssueCandidateArbiter")) - assert(!sv.contains("module ReducedScalarRegisterFile")) - assert(sv.contains("module ReducedScalarIssueQueue")) - assert(sv.contains("module ReducedScalarIssuePick")) - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("io_releaseValid")) - assert(sv.contains("io_secondaryReleaseValid")) - assert(sv.contains("io_tertiaryReleaseValid")) - assert(sv.contains("io_earlyReleaseValid")) - assert(sv.contains("io_earlyReleaseBid")) - assert(sv.contains("io_earlyReleaseRid")) - assert(sv.contains("io_earlyReleaseStid")) - assert(sv.contains("fretStkContextValid")) - assert(sv.contains("fretStkConditionTaken")) - assert(sv.contains("fretStkFallbackTarget")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ClearCommitGuardCommitClearReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceSourceReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoSourceTrace")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupInstructionValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceBeforeCompletion")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateCompleteRowValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateRowFillValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnable")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackDuplicatePhysicalComplete")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackDuplicatePhysicalWriteback")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicySideEffectEnable")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyRetainedSoleOwnerEligible")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackEmitProbeActive")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderFallbackOwnerEligible")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorModelOrderBundle")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultTransferCandidate")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAtomicSuppressCandidate")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelected")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifetimeAligned")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipEligibleRegisteredMask")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlLifecycleClearRequestEnable")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitLifecycleClearCommitEnable")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ReplayRowClearRequestClearResolvedValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlRowFillEnable")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("module BfuBodyCutPredictor")) - assert(sv.contains("module BfuBodyCutArm")) - assert(sv.contains("module BfuResolvedBodyEndOwner")) - assert(sv.contains("module BfuResolvedBodyEndPending")) - assert(sv.contains("module BfuPendingRuntimeBodyEndCandidate")) - assert(sv.contains("module BfuRuntimeBodyEndOracle")) - assert(sv.contains("module BfuResolvedBodyEndSource")) - assert(sv.contains("module BfuStaticGeometryProducer")) - assert(sv.contains("io_fetchReqValid")) - assert(sv.contains("io_sourceOutFire")) - assert(sv.contains("io_reducedBodyCutFire")) - assert(sv.contains("io_bfuStaticResolvedLearnedFire")) - assert(sv.contains("io_bfuResolvedBodyEndAccepted")) - assert(sv.contains("io_bfuResolvedBodyEndUnderflow")) - assert(sv.contains("io_bfuResolvedBodyEndSourceRuntimeSelected")) - assert(sv.contains("io_bfuResolvedBodyEndSourceRuntimeFeedbackFire")) - assert(sv.contains("io_bfuResolvedBodyEndSourceRuntimePending")) - assert(sv.contains("io_bfuResolvedBodyEndSourceRuntimePendingCandidateMatch")) - assert(sv.contains("io_bfuPendingRuntimeCandidateReplayMatch")) - assert(sv.contains("io_bfuPendingRuntimeCandidateActiveHeaderMismatch")) - assert(sv.contains("io_bfuRuntimeBodyEndOracleReplayMatch")) - assert(sv.contains("io_bfuRuntimeBodyEndOracleOverwritePending")) - assert(sv.contains("io_bfuStaticExternalMatch")) - assert(sv.contains("io_bfuStaticExternalBSizeMismatch")) - assert(sv.contains("io_bfuBodyCutArmAccepted")) - assert(sv.contains("io_bfuBodyCutArmBSizeMismatch")) - assert(sv.contains("io_denseSlotQueueOutFire")) - assert(sv.contains("io_admittedMarkerDrainBarrier")) - assert(sv.contains("io_blockMarkerSkipFire")) - assert(sv.contains("io_blockMarkerMixedPacket")) - assert(sv.contains("io_blockMarkerAllocReady")) - assert(sv.contains("io_blockMarkerLifecycleConflict")) - assert(sv.contains("io_blockMarkerAllocFire")) - assert(sv.contains("io_blockMarkerActiveBid")) - assert(sv.contains("io_blockMarkerStopRedirectValid")) - assert(sv.contains("io_rfWriteValid")) - assert(sv.contains("io_issueQueuePickFire")) - assert(sv.contains("io_issueQueueHeadPc")) - assert(sv.contains("io_issueQueueHeadSrcValidMask")) - assert(sv.contains("io_issueQueueHeadSrcPhysTag")) - assert(sv.contains("io_decRenValid")) - assert(sv.contains("io_decRenHeadPc")) - assert(sv.contains("io_robRenameUpdateReady")) - assert(sv.contains("io_localTReadyMask")) - assert(sv.contains("io_localIncomingUsesLocal")) - assert(sv.contains("io_localIncomingBlocked")) - assert(sv.contains("io_decodeBlockedByTURename")) - assert(sv.contains("io_executeCompleteValid")) - assert(sv.contains("io_executeLoadWaitHold")) - assert(sv.contains("io_reducedStoreExecCaptureFire")) - assert(sv.contains("io_reducedStoreCommitPendingMarkMask")) - assert(sv.contains("io_reducedStoreScbCommitFreeMask")) - assert(sv.contains("io_storeStqResidentCount")) - assert(sv.contains("io_blockScalarDoneFire")) - assert(sv.contains("io_blockRetireFire")) - assert(sv.contains("io_blockAllocatedMask")) - assert(sv.contains("io_commitContractError")) - } - - test("optional reduced STQ dispatch mode elaborates store exec and commit/free owners") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 8, - useReducedStoreDispatchStq = true) - ) - - assert(sv.contains("module ReducedStoreExecResultBridge")) - assert(sv.contains("module ReducedStoreCommitFreeOwner")) - assert(sv.contains("module STQCommitDrain")) - assert(sv.contains("module SCBRowBank")) - assert(sv.contains("module ReducedStoreMemoryOverlay")) - assert(sv.contains("module ReducedStoreResidentForward")) - assert(sv.contains("module ResidentStoreForwardStoreSnapshot")) - assert(sv.contains("module ReducedLoadWaitReplaySlot")) - assert(sv.contains("module ReducedLoadReplayRelaunchQueue")) - assert(sv.contains("module ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("module LoadResolveQueue")) - assert(sv.contains("io_reducedMdbConflictStoreValid")) - assert(sv.contains("io_reducedMdbFanoutRecordValid")) - assert(sv.contains("io_reducedMdbLookupWaitPlanRequestValid")) - assert(sv.contains("module ReducedLoadReplayCompletionDrain")) - assert(sv.contains("io_loadLookupDstPhysTag")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchDstPhysTag")) - assert(sv.contains("io_reducedLoadReplayQueueOutDstPhysTag")) - assert(sv.contains("io_reducedStoreDispatchEnabled")) - assert(sv.contains("io_reducedStoreExecCaptureFire")) - assert(sv.contains("io_reducedStoreCommitMarkValid")) - assert(sv.contains("io_reducedStoreCommitFreeValid")) - assert(sv.contains("io_reducedStoreDrainIssueValidMask")) - assert(sv.contains("io_reducedStoreScbCommitFreeMask")) - assert(sv.contains("io_reducedStoreMemoryLineCount")) - assert(sv.contains("io_reducedStoreMemoryLoadForwardMask")) - assert(sv.contains("io_reducedStoreResidentForwardMask")) - assert(sv.contains("io_reducedStoreResidentWaitMask")) - assert(sv.contains("io_reducedStoreResidentWaitStorePc")) - assert(sv.contains("io_reducedStoreResidentReplayWakeValid")) - assert(sv.contains("io_reducedLoadWaitReplayClearValid")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchValid")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchGidValue")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchRidValue")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchYoungestStoreIdValue")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchYoungestStoreLsIdValue")) - assert(sv.contains("io_reducedLoadReplayQueueEnqueueAccepted")) - assert(sv.contains("io_reducedLoadReplayQueueOutBidValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutGidValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutRidValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutYoungestStoreIdValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutYoungestStoreLsIdValue")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedSourceTraceValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedSource0Data")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedSource1Data")) - assert(sv.contains("io_reducedLoadReplayDrainMatchValid")) - assert(sv.contains("io_reducedLoadReplayDrainGidMismatch")) - assert(sv.contains("io_reducedLoadReplayDrainLsIdMismatch")) - assert(sv.contains("io_reducedLoadReplayLiqAllocEnabled")) - assert(sv.contains("io_reducedLoadReplayLiqAllocAccepted")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchCandidateMask")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchDriveValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchAccepted")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedPc")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedRequestByteMask")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupValid")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupGranted")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupBlockedByExecute")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessCandidateValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessEnable")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBlockedByScb")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBlockedByReturn")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestCandidate")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRowMutationDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestEnable")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanInvalidStqApplyWithoutScb")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanNextStoreSourceReturned")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByLiveDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationInvalidMultiTarget")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnSourceReturned")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnScbLiveActive")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnScbLiveBlockedByScbReturn")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetAvailable")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetBlockedByBudgetDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetBlockedByConsumer")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipePermitPipeBudgetAvailable")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipePermitBlockedByPipeBudget")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeAvailableMask")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBlockedByNoPipe")) - assert(sv.contains("io_reducedLoadReplayLiqReturnReadinessReady")) - assert(sv.contains("io_reducedLoadReplayLiqReturnReadinessBlockedByReturnPipe")) - assert(sv.contains("io_reducedLoadReplayLiqE4UpdateValid")) - assert(sv.contains("io_reducedLoadReplayLiqLhqRecordValid")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupRequestByteMask")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLineValidMask")) - assert(sv.contains("io_reducedLoadReplayLiqResidentCount")) - assert(sv.contains("io_reducedLoadReplayResolveQueuePushAccepted")) - assert(sv.contains("io_reducedLoadReplayResolveQueueClearAccepted")) - assert(sv.contains("io_reducedLoadReplayResolveQueuePreciseFlushValid")) - assert(sv.contains("io_reducedLoadReplayResolveQueueFlushPruneCount")) - assert(sv.contains("io_reducedMdbConflictActiveCandidateMask")) - assert(sv.contains("io_reducedMdbConflictResolveCandidateMask")) - assert(sv.contains("io_reducedMdbConflictInnerFlush")) - assert(sv.contains("io_reducedMdbFanoutLookupAccepted")) - assert(sv.contains("io_reducedMdbFanoutLookupProcessed")) - assert(sv.contains("io_reducedMdbFanoutDeleteReady")) - assert(sv.contains("io_reducedMdbFanoutPhaseStalledByFanout")) - assert(sv.contains("io_reducedMdbFanoutLuOutHit")) - assert(sv.contains("io_reducedMdbFanoutSuOutHit")) - assert(sv.contains("io_reducedMdbFanoutRecordAccepted")) - assert(sv.contains("io_reducedMdbFanoutBmdbReportValid")) - assert(sv.contains("io_reducedMdbFanoutSsitValidMask")) - assert(sv.contains("io_reducedLoadReplayResolveQueueValidMask")) - assert(sv.contains("io_reducedLoadReplayResolveQueueHeadPc")) - assert(sv.contains("io_executeLoadWaitHold")) - assert(sv.contains("io_storeStqInsertValid")) - assert(sv.contains("io_storeStqAddrReadyMask")) - assert(sv.contains("io_storeStqDataReadyMask")) - } - - test("reduced-store harness wrapper elaborates the opt-in STQ path") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluReducedStoreTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchRfAluReducedStoreTraceTop")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module ReducedStoreExecResultBridge")) - assert(sv.contains("module ReducedStoreCommitFreeOwner")) - assert(sv.contains("module STQCommitDrain")) - assert(sv.contains("module SCBRowBank")) - assert(sv.contains("module ReducedStoreMemoryOverlay")) - assert(sv.contains("module ReducedStoreResidentForward")) - assert(sv.contains("module ResidentStoreForwardStoreSnapshot")) - assert(sv.contains("module ReducedLoadWaitReplaySlot")) - assert(sv.contains("module ReducedLoadReplayRelaunchQueue")) - assert(sv.contains("module ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("module LoadResolveQueue")) - assert(sv.contains("module ReducedLoadReplayCompletionDrain")) - assert(sv.contains("io_reducedStoreDispatchEnabled")) - assert(sv.contains("io_reducedStoreScbCommitFreeMask")) - assert(sv.contains("io_reducedStoreMemoryStoreDroppedMask")) - assert(sv.contains("io_reducedStoreResidentEligibleMask")) - assert(sv.contains("io_reducedStoreResidentWaitStoreBidValue")) - assert(sv.contains("io_reducedStoreResidentReplayWakeByteMask")) - assert(sv.contains("io_reducedLoadWaitReplayStoredWaitPc")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchPc")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchGidValue")) - assert(sv.contains("io_reducedLoadWaitReplayRelaunchYoungestStoreIdValue")) - assert(sv.contains("io_reducedLoadReplayQueuePending")) - assert(sv.contains("io_reducedLoadReplayQueueOutLsIdValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutRidValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutYoungestStoreLsIdValue")) - assert(sv.contains("io_reducedLoadReplayDrainConsumeReady")) - assert(sv.contains("io_reducedLoadReplayDrainAddrMismatch")) - assert(sv.contains("io_reducedLoadReplayDrainRidMismatch")) - assert(sv.contains("io_reducedLoadReplayLiqAllocEnabled")) - assert(sv.contains("io_reducedLoadReplayLiqAllocConsumeReady")) - assert(sv.contains("io_reducedLoadReplayLiqOccupiedMask")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchDataHitMask")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchIndex")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReady")) - assert(sv.contains("io_reducedLoadReplayLiqRepickMask")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedLoadLsIdValue")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupAddr")) - assert(sv.contains("io_reducedLoadReplayLiqBaseDataReturned")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupGranted")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupBlockedByExecute")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBaseDataReady")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup")) - assert(sv.contains("io_reducedLoadReplayResolveQueueCount")) - assert(sv.contains("io_reducedLoadReplayResolveQueueClearIndex")) - assert(sv.contains("io_reducedLoadReplayResolveQueueFlushPruneMask")) - assert(sv.contains("io_reducedLoadReplayResolveQueueHeadAddr")) - assert(sv.contains("io_executeLoadWaitHold")) - assert(sv.contains("io_storeStqInsertValid")) - } - - test("reduced-store live-load-LIQ wrapper elaborates E1 admission and LIQ ownership") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop( - CoreParams(robEntries = 8, commitWidth = 2), - mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop")) - assert(sv.contains("module ReducedLiveLoadLiqCapture")) - assert(sv.contains("io_captureAccepted")) - assert(sv.contains("io_candidateValid")) - assert(sv.contains("module ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("module LoadInflightQueue")) - } - - test("reduced-store replay-LIQ wrapper elaborates allocation consumer diagnostics") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop( - CoreParams(robEntries = 8, commitWidth = 2, lsidWidth = 40), - mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop")) - assert(sv.contains("module ReducedLoadReplayLiqAllocPath")) - assert(sv.contains("module ReducedLoadReplayLiqAllocAdapter")) - assert(sv.contains("module ResidentStoreForwardStoreSnapshot")) - assert(sv.contains("module LoadLookupArbiter")) - assert(sv.contains("module LoadReplayLaunchReadiness")) - assert(sv.contains("module LoadReplayReturnConsumerReady")) - assert(sv.contains("module LoadReplayReturnPipeBudget")) - assert(sv.contains("module LoadReplayReturnPipePermit")) - assert(sv.contains("module LoadReplayReturnDataExtract")) - assert(sv.contains("module LoadReplayReturnPublishReady")) - assert(sv.contains("module LoadReplayReturnLretPayload")) - assert(sv.contains("module LoadReplayReturnWritebackCandidate")) - assert(sv.contains("module LoadReplayReturnWakeupCandidate")) - assert(sv.contains("module ReducedScalarWritebackArbiter")) - assert(sv.contains("module LoadReplayReturnSideEffectReady")) - assert(sv.contains("module LoadReplayReturnPublishControl")) - assert(sv.contains("module LoadReplayReturnPublishRequest")) - assert(sv.contains("module LoadInflightQueue")) - assert(sv.contains("module LoadInflightLaunchSelect")) - assert(sv.contains("module LoadReplayBaseDataAlign")) - assert(sv.contains("module LoadResolveQueue")) - assert(sv.contains("module MDBStoreProbeReplay")) - assert(sv.contains("module ScalarLSUMDBPath")) - assert(sv.contains("module ScalarLSURecoveryBoundary")) - assert(sv.contains("module MDBConflictDetect")) - assert(sv.contains("module MDBQueueFanout")) - assert(!sv.contains("module MDBRecoveryDeliveryPath")) - assert("module MDBConflictDetect".r.findAllMatchIn(sv).length == 1) - assert("module MDBQueueFanout".r.findAllMatchIn(sv).length == 1) - assert(sv.contains("io_reducedLoadReplayLiqAllocEnabled")) - assert(sv.contains("io_reducedLoadReplayLiqAllocConsumeReady")) - assert(sv.contains("io_reducedLoadReplayLiqAllocAccepted")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchCandidateMask")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchDriveValid")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchAccepted")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedAddr")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedDstPhysTag")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedSpecWakeup")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchSelectedStackValid")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupValid")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupCrossesLine")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupGranted")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLookupBlockedByExecute")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessReady")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseData")) - assert(sv.contains("io_reducedLoadReplayLiqLaunchReadinessBlockedByReturn")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnScbSourceReturned")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnBlockedByScb")) - assert(sv.contains("io_reducedLoadReplayLiqSourceReturnScbLivePending")) - assert(sv.contains("io_reducedLoadReplayLiqReturnConsumerReady")) - assert(sv.contains("io_reducedLoadReplayLiqReturnConsumerBlockedByLretSink")) - assert(sv.contains("io_reducedLoadReplayLiqReturnConsumerBlockedByWakeupSink")) - assert(sv.contains("io_reducedLoadReplayLiqReturnWritebackSinkCandidateValid")) - assert(sv.contains("io_reducedLoadReplayLiqReturnWritebackSinkBlockedByLiveDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqReturnSideEffectLiveRequiredMask")) - assert(sv.contains("io_reducedLoadReplayLiqReturnSideEffectLiveBlockedByLiveDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqReturnWakeupSinkCandidateValid")) - assert(sv.contains("io_reducedLoadReplayLiqReturnWakeupSinkBlockedByLiveDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetEnable")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetConsumerReady")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPipeBudgetBlockedBySources")) - assert(sv.contains("io_reducedLoadReplayLiqReturnDataValid")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPublishReady")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPublishBlockedByData")) - assert(sv.contains("io_reducedLoadReplayLiqReturnPublishBlockedByConsumer")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadDstPhysTag")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadSourceTraceValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadSource0Data")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadData")) - assert(sv.contains("io_reducedLoadReplayLiqLretPayloadWakeupRequired")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2SlotSourceTraceValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2SlotSource1Data")) - assert(sv.contains("module LoadReplayReturnPipeW2ResolveFirePayload")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ResolveFirePayloadFireValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ResolveFirePayloadBidValue")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ResolveFirePayloadInvalidPayloadWithoutFire")) - assert(sv.contains("module LoadReplayReturnPipeW2RobCompleteSource")) - assert(sv.contains("module ExecuteCompletionRetainer")) - assert(sv.contains("module ReducedRobCompletionArbiter")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RobCompleteSourceCompleteValid")) - assert(sv.contains("io_robCompleteArbiterSelectedExecute")) - assert(sv.contains("io_robCompleteArbiterSelectedReplay")) - assert(sv.contains("module LoadReplayReturnPipeW2WritebackFirePayload")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WritebackFirePayloadFireValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WritebackFirePayloadDstPhysTag")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WritebackFirePayloadInvalidPayloadWithoutFire")) - assert(sv.contains("module LoadReplayReturnPipeW2WakeupFirePayload")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WakeupFirePayloadFireValid")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WakeupFirePayloadDstPhysTag")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2WakeupFirePayloadInvalidPayloadWithoutFire")) - assert(sv.contains("module LoadReplayReturnPipeW2SideEffectFireComplete")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2SideEffectFireCompletePayloadFireMask")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteInvalidFireWithoutPayload")) - assert(sv.contains("module LoadReplayReturnPipeW2ClearIntent")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ClearIntentLiveClear")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2ClearIntentInvalidEvidenceWithoutSlot")) - assert(sv.contains("module LoadReplayReturnPipeW2RefillReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RefillReadyFutureAdvance")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RefillReadySameCycleEligible")) - assert(sv.contains("io_reducedLoadReplayLiqLretPipeW2RefillReadyInvalidLiveClearWithoutIntent")) - assert(sv.contains("module ScalarLSULoadReturnQueue")) - assert(sv.contains("module ScalarLSULoadReturnQueueBank")) - assert(sv.contains("io_reducedLoadReplayLiqLretSinkEnqueueAccepted")) - assert(sv.contains("io_reducedLoadReplayLiqLretSinkDrainStid")) - assert(sv.contains("io_reducedLoadReplayLiqLretSinkPrecisePruneCount")) - assert(sv.contains("io_reducedLoadReplayLiqLretSinkBlockedByDrain")) - assert(sv.contains("module LoadReplayReturnIexDrainPermit")) - assert(sv.contains("io_reducedLoadReplayLiqLretDrainPermitReady")) - assert(sv.contains("io_reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull")) - assert(sv.contains("io_reducedLoadReplayLiqWritebackValid")) - assert(sv.contains("io_reducedLoadReplayLiqWritebackIgnoredNonGprDestination")) - assert(sv.contains("io_reducedLoadReplayLiqWritebackArbiterSelectedExecute")) - assert(sv.contains("io_reducedLoadReplayLiqWritebackArbiterReplayBlockedByDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqSideEffectReady")) - assert(sv.contains("io_reducedLoadReplayLiqSideEffectBlockedByWriteback")) - assert(sv.contains("io_reducedLoadReplayLiqSideEffectBlockedByWakeup")) - assert(sv.contains("io_reducedLoadReplayLiqPublishControlArmed")) - assert(sv.contains("io_reducedLoadReplayLiqPublishControlFire")) - assert(sv.contains("io_reducedLoadReplayLiqPublishControlBlockedByLiveDisabled")) - assert(sv.contains("io_reducedLoadReplayLiqPublishRequestValid")) - assert(sv.contains("io_reducedLoadReplayLiqPublishRequestMask")) - assert(sv.contains("io_reducedLoadReplayLiqPublishRequestInvalidFireWithoutPayload")) - assert(sv.contains("io_reducedLoadReplayLiqWakeupValid")) - assert(sv.contains("io_reducedLoadReplayLiqWakeupReducedGprValid")) - assert(sv.contains("io_reducedLoadReplayLiqWakeupSuppressedNotRequired")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationBridgeValid")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationWriteEnable")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationBlockedByControl")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationControlBlockedByScbNotReturned")) - assert(sv.contains("io_reducedLoadReplayLiqRowMutationControlBlockedByAllocationConflict")) - assert(sv.contains("io_reducedLoadReplayLiqMissMask")) - assert(sv.contains("io_reducedLoadReplayLiqResolvedMask")) - assert(sv.contains("io_reducedLoadReplayLiqE4MissKind")) - assert(sv.contains("io_reducedLoadReplayLiqBaseLineValidMask")) - assert(sv.contains("io_reducedLoadReplayLiqResidentCount")) - assert(sv.contains("io_reducedLoadReplayResolveQueuePushAccepted")) - assert(sv.contains("io_reducedLoadReplayResolveQueueClearPending")) - assert(sv.contains("io_reducedLoadReplayResolveQueueRetireValid")) - assert(sv.contains("io_reducedLoadReplayResolveQueueRetireLsIdValue")) - assert(sv.contains("io_reducedLoadReplayResolveQueuePreciseFlushLsIdValue")) - assert(sv.contains("io_reducedLoadReplayResolveQueueFlushPruneCount")) - assert(sv.contains("io_reducedMdbConflictStoreValid")) - assert(sv.contains("io_reducedMdbConflictLoadLsIdValue")) - assert(sv.contains("io_reducedMdbConflictStoreLsIdValue")) - assert(sv.contains("io_reducedMdbFanoutLookupReady")) - assert(sv.contains("io_reducedMdbFanoutLuOutStoreBidValue")) - assert(sv.contains("io_reducedMdbFanoutSuOutStoreBidValue")) - assert(sv.contains("io_reducedMdbFanoutRecordProcessed")) - assert(sv.contains("io_reducedMdbFanoutBmdbLoadBidValue")) - assert(sv.contains("io_reducedMdbFanoutDeleteDroppedBelowStall")) - assert(sv.contains("io_reducedMdbFanoutSuWakeupValid")) - assert(sv.contains("io_reducedLoadReplayResolveQueueHeadLsIdValue")) - assert(sv.contains("io_reducedLoadReplayQueueOutFire")) - } - - test("marker-row harness elaborates admitted markers with decode-time BID context") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchRfAluMarkerRowsTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchRfAluMarkerRowsTraceTop")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module BlockMarkerDecodeContext")) - assert(sv.contains("io_decodeValid")) - assert(sv.contains("io_decodeFire")) - assert(sv.contains("io_decodeBlockBid")) - assert(sv.contains("io_decodeUsesExistingBlock")) - assert(sv.contains("io_robRenameUpdateReady")) - assert(sv.contains("io_executeCompleteValid")) - assert(sv.contains("io_blockMarkerSkipValid")) - assert(sv.contains("io_admittedMarkerDrainBarrier")) - } - - test("ACRC service enqueue uses one accepted ready-valid contract") { - val source = topSourceText - - assert(source.contains("execute.io.completeReady := retainer.io.laneReady(0)")) - assert(source.contains("retainer.io.lanes(0).valid := execute.io.completeValid")) - assert(source.contains("retainer.io.lanes(0).rowValid := execute.io.completeValid")) - assert(source.contains("retainer.io.outputReady := arbiter.io.selectedExecute && (path.io.completeAccepted || path.io.completeIgnored)")) - assert(source.contains("arbiter.io.executeCompleteValid := retainer.io.completeValid")) - assert(source.contains("retainer.io.lanes(1) := 0.U.asTypeOf(retainer.io.lanes(1))")) - assert(source.contains("stale retained rows after recovery drain via")) - assert(source.contains("val incomingServiceRow = path.io.decRenValid && path.io.decRenHeadOpcode === serviceOpcode")) - assert(source.contains("val serviceQueueAccepts = !incomingServiceRow || servicePath.io.enqueueReady")) - assert(source.contains("!servicePath.io.renameFence && serviceQueueAccepts")) - assert(source.contains("issue.io.inValid := path.io.renamedOutValid && path.io.renamedOutReady")) - assert(source.contains("val serviceEnqueueFire = issue.io.inputAcceptFire && issue.io.inputAcceptUop.opcode === serviceOpcode")) - assert(source.contains("rf.io.clearValid := issue.io.inputAcceptDstValid")) - assert(source.contains("val localDstAllocT =\n issue.io.inputAcceptFire && issue.io.inputAcceptUop.dst(0).valid")) - assert(source.contains("val conditionalFretIssueFire = issue.io.issueFire && issueFretStkFallbackValid")) - assert(source.contains("path.io.samePacketNextSlotValid :=\n denseSlots.io.outNextSamePacketSlotValid && !admittedMarkerDrainBarrier")) - assert(source.contains("path.io.samePacketNextSlot := denseSlots.io.outNextSamePacketSlot")) - assert(source.contains("!productionHeadIsService || productionD1.io.nextValid")) - assert(source.contains("path.io.predecodedNextValid :=\n productionD1.io.nextValid && !admittedMarkerDrainBarrier")) - } - - test("issue release wiring keeps terminal, LIQ-service-SC, and early-release identities on separate ports") { - val source = topSourceText - val executeSource = executeSourceText - - assert(source.contains("issue.io.releaseValid := execute.io.releaseValid")) - assert(source.contains("issue.io.releaseBid := execute.io.releaseBid")) - assert(source.contains("issue.io.releaseRid := execute.io.releaseRid")) - assert(source.contains("issue.io.releaseStid := execute.io.releaseStid")) - assert(source.contains("val serviceOrScReleaseValid = servicePath.io.releaseValid || scalarScReleaseValid")) - assert(source.contains("issue.io.secondaryReleaseValid := execute.io.liqReleaseValid || serviceOrScReleaseValid")) - assert(source.contains("execute.io.liqReleaseValid,\n execute.io.liqReleaseBid")) - assert(source.contains("Mux(servicePath.io.releaseValid, servicePath.io.releaseBid, scalarScReleaseBid)")) - assert(source.contains("execute.io.liqReleaseValid,\n execute.io.liqReleaseRid")) - assert(source.contains("Mux(servicePath.io.releaseValid, servicePath.io.releaseRid, scalarScReleaseRid)")) - assert(source.contains("execute.io.liqReleaseValid,\n execute.io.liqReleaseStid")) - assert(source.contains("Mux(servicePath.io.releaseValid, servicePath.io.releaseStid, scalarScReleaseStid)")) - assert(source.contains("issue.io.tertiaryReleaseValid := execute.io.earlyReleaseValid")) - assert(source.contains("issue.io.tertiaryReleaseBid := execute.io.earlyReleaseBid")) - assert(source.contains("issue.io.tertiaryReleaseRid := execute.io.earlyReleaseRid")) - assert(source.contains("issue.io.tertiaryReleaseStid := execute.io.earlyReleaseStid")) - assert(source.contains("val redirectCleanupCutsIssue = LinxCoreFrontendFetchRfAluTraceTopRedirectIssueCutWiring.cutsIssue(")) - assert(source.contains("execute.io.inReady && !conditionalFretStkWaiting && !templateContextBlocksIssue && !redirectCleanupCutsIssue")) - assert(source.contains("issue.io.issueValid && !serviceIssueCandidate && !scalarScIssueGate.candidate &&\n !conditionalFretStkWaiting && !templateContextBlocksIssue && !redirectCleanupCutsIssue")) - assert(source.contains("execute.io.flushValid := backendPipeFlush")) - assert(!source.contains("execute.io.earlyReleaseKill")) - assert(!source.contains("issue.io.releaseValid := execute.io.earlyReleaseValid")) - assert(!source.contains("issue.io.secondaryReleaseValid := execute.io.earlyReleaseValid")) - - assert(executeSource.contains("val earlyReleasePendingValid = RegInit(false.B)")) - assert(executeSource.contains("val earlyReleasePendingBid = RegInit(ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("val earlyReleasePendingGid = RegInit(ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("val earlyReleasePendingRid = RegInit(ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("val earlyReleasePendingStid = RegInit(0.U(p.threadIdWidth.W))")) - assert(executeSource.contains("val earlyReleaseCapture = accept && ScalarPipeSafety.fixedScalarAlu(io.in)")) - assert(executeSource.contains("when(io.flushValid)")) - assert(executeSource.contains("earlyReleasePendingValid := earlyReleaseCapture")) - assert(executeSource.contains("earlyReleasePendingBid := io.in.bid")) - assert(executeSource.contains("earlyReleasePendingGid := io.in.gid")) - assert(executeSource.contains("earlyReleasePendingRid := io.in.rid")) - assert(executeSource.contains("earlyReleasePendingStid := io.in.threadId")) - assert(executeSource.contains("io.earlyReleaseValid := !io.flushValid && earlyReleasePendingValid")) - assert(!executeSource.contains("earlyReleaseKill")) - assert(executeSource.contains("io.releaseValid := (io.completeFire && !w2EarlyReleased) || w2UnsupportedDrain")) - assert(executeSource.contains("io.earlyReleaseBid := Mux(io.earlyReleaseValid, earlyReleasePendingBid, ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("io.earlyReleaseGid := Mux(io.earlyReleaseValid, earlyReleasePendingGid, ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("io.earlyReleaseRid := Mux(io.earlyReleaseValid, earlyReleasePendingRid, ROBID.disabled(p.robEntries))")) - assert(executeSource.contains("io.earlyReleaseStid := Mux(io.earlyReleaseValid, earlyReleasePendingStid, 0.U)")) - assert(!executeSource.contains("io.earlyReleaseBid := Mux(io.earlyReleaseValid, io.in.bid")) - assert(!executeSource.contains("io.earlyReleaseRid := Mux(io.earlyReleaseValid, io.in.rid")) - assert(!executeSource.contains("io.earlyReleaseStid := Mux(io.earlyReleaseValid, io.in.threadId")) - } - - test("execute W2 side effects fire only after retained completion backpressure accepts") { - val source = topSourceText - - assert(source.contains( - "reducedLoadReplayCompletionDrain.io.completeValid :=\n" + - " useReducedStoreDispatchStq.B && !reducedLoadReplayLiqAllocEnabled && execute.io.completeFire")) - assert(source.contains("execute.io.completeFire && execute.io.completeRow.wb.valid && (execute.io.completeRow.wb.reg === 31.U)")) - assert(source.contains("execute.io.completeFire && execute.io.completeRow.wb.valid && (execute.io.completeRow.wb.reg === 30.U)")) - assert(source.contains( - "val scalarLrSetCandidate =\n" + - " execute.io.completeFire &&")) - assert(source.contains("storeExecBridge.io.completeValid := execute.io.completeFire && useReducedStoreDispatchStq")) - assert(source.contains( - "val executeCompleteIsFentry =\n" + - " execute.io.completeFire &&")) - assert(!source.contains("storeExecBridge.io.completeValid := execute.io.completeValid")) - assert(!source.contains("reducedLoadReplayCompletionDrain.io.completeValid :=\n useReducedStoreDispatchStq.B && !reducedLoadReplayLiqAllocEnabled && execute.io.completeValid")) - } - - test("ACRC service issue uses full commit-head identity") { - val source = topSourceText - - assert(source.contains("path.io.commitHeadStid === issue.io.issueUop.threadId")) - assert(source.contains("path.io.commitHeadBid.valid && path.io.commitHeadGid.valid && path.io.commitHeadRid.valid")) - assert(source.contains("ROBID.equal(path.io.commitHeadBid, issue.io.issueUop.bid)")) - assert(source.contains("ROBID.equal(path.io.commitHeadGid, issue.io.issueUop.gid)")) - assert(source.contains("ROBID.equal(path.io.commitHeadRid, issue.io.issueUop.rid)")) - } - - test("ACRC service marker adjacency only latches accepted same-context stops") { - val source = topSourceText - - assert(source.contains("val acceptedServiceStopMarkerFire =")) - assert(source.contains("acceptedMarkerDrainFire && path.io.blockMarkerStop")) - assert(source.contains("}.elsewhen(acceptedServiceStopMarkerFire)")) - assert(source.contains("latestStopStid === issue.io.issueUop.threadId")) - assert(source.contains("latestStopBlockBidValid && issue.io.issueUop.blockBidValid")) - assert(source.contains("latestStopBlockBid === issue.io.issueUop.blockBid")) - assert(!source.contains("}.elsewhen(path.io.blockMarkerStop)")) - } - - test("ACRC service issue prefers decode-captured same-packet C.BSTOP metadata") { - val source = topSourceText - - assert(source.contains("val enqueueAdjacentStop =")) - assert(source.contains("val serviceDecodeStopPendingValid = RegInit(false.B)")) - assert(source.contains("when(!serviceMetadataFlush && path.io.serviceAdjacentStop.valid)")) - assert(source.contains("val pendingMatches =")) - assert(source.contains("val enqueueAdjacentStop = serviceEnqueueFire && (liveMatches || pendingMatches)")) - assert(source.contains("ROBID.equal(serviceDecodeStopPendingBid, issue.io.inputAcceptUop.bid)")) - assert(source.contains("ROBID.equal(serviceDecodeStopPendingGid, issue.io.inputAcceptUop.gid)")) - assert(source.contains("ROBID.equal(serviceDecodeStopPendingRid, issue.io.inputAcceptUop.rid)")) - assert(source.contains("serviceQueuedStopBid.valid && serviceQueuedStopGid.valid && serviceQueuedStopRid.valid")) - assert(source.contains("ROBID.equal(serviceQueuedStopBid, issue.io.issueUop.bid)")) - assert(source.contains("ROBID.equal(serviceQueuedStopGid, issue.io.issueUop.gid)")) - assert(source.contains("ROBID.equal(serviceQueuedStopRid, issue.io.issueUop.rid)")) - assert(source.contains("queuedMatches || acceptedMarkerMatches")) - assert(source.contains("Mux(queuedMatches, serviceQueuedStopInsn, latestStopInsn)")) - assert(source.contains("Mux(queuedMatches, serviceQueuedStopLen, latestStopLen)")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchTraceTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchTraceTopSpec.scala deleted file mode 100644 index 95c46981..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchTraceTopSpec.scala +++ /dev/null @@ -1,49 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreFrontendFetchTraceTopSpec extends AnyFunSuite { - test("interface exposes live fetch source and reduced commit trace parameters") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendFetchTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendFetchTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendFetchTraceTopIO(p, trace) - - assert(p.robEntries == 8) - assert(p.commitWidth == 2) - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - assert(io.startPc.getWidth == 64) - assert(io.fetchReqPc.getWidth == 64) - assert(io.fetchRespWindow.getWidth == 64) - assert(io.sourceCurrentPc.getWidth == 64) - assert(io.sourceNextPktUid.getWidth == 64) - assert(io.sourceAdvanceBytes.getWidth == 4) - assert(io.f4ValidMask.getWidth == 4) - assert(io.selectedRobValue.getWidth == 3) - assert(io.commit.rows.length == 2) - assert(io.commitHeadRobValue.getWidth == 3) - } - - test("LinxCoreFrontendFetchTraceTop elaborates source through F4 and DecodeRenameROBPath") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendFetchTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendFetchTraceTop")) - assert(sv.contains("module FrontendFetchPacketSource")) - assert(sv.contains("module F4DecodeWindow")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module FrontendDecodeStage")) - assert(sv.contains("module DecodeRenameQueue")) - assert(sv.contains("module ScalarTURenameBridge")) - assert(sv.contains("module DispatchROBAllocator")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("io_fetchReqValid")) - assert(sv.contains("io_fetchRespReady")) - assert(sv.contains("io_sourceOutFire")) - assert(sv.contains("io_commitContractError")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendRfAluTraceTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFrontendRfAluTraceTopSpec.scala deleted file mode 100644 index cd61512f..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendRfAluTraceTopSpec.scala +++ /dev/null @@ -1,82 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreFrontendRfAluTraceTopSpec extends AnyFunSuite { - test("interface removes operand fixtures and exposes RF plus issue debug") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendRfAluTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendRfAluTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendRfAluTraceTopIO(p, trace, issueQueueDepth = 4, physRegs = 64) - - assert(p.robEntries == 8) - assert(p.commitWidth == 2) - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - assert(io.in.window.getWidth == 64) - assert(io.rfInitArchTag.getWidth == 6) - assert(io.rfInitData.getWidth == 64) - assert(io.rfReadyMask.getWidth == 64) - assert(io.rfWriteTag.getWidth == 6) - assert(io.issueQueueCount.getWidth == 3) - assert(io.issueQueueIssuedCount.getWidth == 3) - assert(io.issueQueueNotIssuedCount.getWidth == 3) - assert(io.issueQueueSourceReadyMask.getWidth == 3) - assert(io.issueQueueSelectedIndex.getWidth == 2) - assert(io.issueQueueSelectedReadReady.getWidth == 1) - assert(io.issueQueuePickFire.getWidth == 1) - assert(io.issueQueueCancelFire.getWidth == 1) - assert(io.issueQueueI1Valid.getWidth == 1) - assert(io.issueQueueI2Valid.getWidth == 1) - assert(io.issueQueueStageBusy.getWidth == 1) - assert(io.issueQueueBankOccupancy.length == 2) - assert(io.issueQueueBankPickMask.getWidth == 2) - assert(io.issueQueueBankReadAttemptMask.getWidth == 2) - assert(io.issueQueueBankIssueValidMask.getWidth == 2) - assert(io.issueQueueReadArbitrationLoss.getWidth == 1) - assert(io.executeCompleteRobValue.getWidth == 3) - assert(io.commit.rows.length == 2) - } - - test("LinxCoreFrontendRfAluTraceTop elaborates frontend, rename, RF, issue, ROB, and ALU execute") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendRfAluTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendRfAluTraceTop")) - assert(sv.contains("module F4DecodeWindow")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("module ScalarIssueFabric")) - assert(sv.contains("module ScalarIssueCandidateArbiter")) - assert(!sv.contains("module ReducedScalarRegisterFile")) - assert(sv.contains("module ReducedScalarIssueQueue")) - assert(sv.contains("module ReducedScalarIssuePick")) - assert(sv.contains("module ReducedScalarAluExecute")) - assert(sv.contains("module DispatchROBAllocator")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("io_rfInitValid")) - assert(sv.contains("io_rfWriteValid")) - assert(sv.contains("io_issueQueueEnqueueFire")) - assert(sv.contains("io_issueQueuePickFire")) - assert(sv.contains("io_issueQueueCancelFire")) - assert(sv.contains("io_issueQueueReleaseFire")) - assert(sv.contains("io_issueQueueHeadIssued")) - assert(sv.contains("io_issueQueueSourceReadyMask")) - assert(sv.contains("io_issueQueueSelectedValid")) - assert(sv.contains("io_issueQueueSelectedIndex")) - assert(sv.contains("io_issueQueueSelectedReadReady")) - assert(sv.contains("io_issueQueueI1Valid")) - assert(sv.contains("io_issueQueueI2Valid")) - assert(sv.contains("io_issueQueueStageBusy")) - assert(sv.contains("io_issueQueueBlockedBySource")) - assert(sv.contains("io_issueQueueBlockedByRead")) - assert(sv.contains("io_issueQueueBlockedByIssued")) - assert(sv.contains("io_issueQueueBankOccupancy_0")) - assert(sv.contains("io_issueQueueReadArbitrationLoss")) - assert(sv.contains("io_executeCompleteValid")) - assert(sv.contains("io_commitContractError")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendTraceTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreFrontendTraceTopSpec.scala deleted file mode 100644 index 12bedc87..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreFrontendTraceTopSpec.scala +++ /dev/null @@ -1,41 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.CoreParams -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreFrontendTraceTopSpec extends AnyFunSuite { - test("interface and trace parameters follow the reduced top configuration") { - val core = CoreParams(robEntries = 8, commitWidth = 2) - val p = LinxCoreFrontendTraceTop.interfaceParamsFor(core) - val trace = LinxCoreFrontendTraceTop.traceParamsFor(p) - val io = new LinxCoreFrontendTraceTopIO(p, trace) - - assert(p.robEntries == 8) - assert(p.commitWidth == 2) - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - assert(io.in.window.getWidth == 64) - assert(io.f4ValidMask.getWidth == 4) - assert(io.selectedRobValue.getWidth == 3) - assert(io.commit.rows.length == 2) - assert(io.commitHeadRobValue.getWidth == 3) - } - - test("LinxCoreFrontendTraceTop elaborates F4 decode through DecodeRenameROBPath") { - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreFrontendTraceTop(CoreParams(robEntries = 8, commitWidth = 2), mapQDepth = 8) - ) - - assert(sv.contains("module LinxCoreFrontendTraceTop")) - assert(sv.contains("module F4DecodeWindow")) - assert(sv.contains("module DecodeRenameROBPath")) - assert(sv.contains("module FrontendDecodeStage")) - assert(sv.contains("module DecodeRenameQueue")) - assert(sv.contains("module ScalarTURenameBridge")) - assert(sv.contains("module DispatchROBAllocator")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("io_commitContractError")) - assert(sv.contains("io_commitHeadRobValue")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/LinxCoreTopSpec.scala b/chisel/src/test/scala/linxcore/top/LinxCoreTopSpec.scala deleted file mode 100644 index 264ca2e3..00000000 --- a/chisel/src/test/scala/linxcore/top/LinxCoreTopSpec.scala +++ /dev/null @@ -1,72 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.{CoreParams, ScalarLsuParams} -import org.scalatest.funsuite.AnyFunSuite - -class LinxCoreTopSpec extends AnyFunSuite { - test("public load-return allow cannot bypass resident owner readiness") { - def combinedReady(publicAllow: Boolean, ownerReady: Boolean): Boolean = - publicAllow && ownerReady - - assert(combinedReady(publicAllow = true, ownerReady = true)) - assert(!combinedReady(publicAllow = false, ownerReady = true)) - assert(!combinedReady(publicAllow = true, ownerReady = false)) - } - - test("trace parameters follow the top-level ROB and commit configuration") { - val params = CoreParams(robEntries = 8, commitWidth = 2) - val trace = LinxCoreTop.traceParamsFor(params) - - assert(trace.commitWidth == 2) - assert(trace.robValueWidth == 3) - } - - test("Chisel LinxCoreTop elaborates with commit and scalar LSU owners") { - val lsu = ScalarLsuParams( - stqEntries = 8, - commitQueueEntries = 4, - commitIssueWidth = 1, - scbEntries = 4, - scbResponseBufferDepth = 2, - liqEntries = 4, - resolveQueueEntries = 8, - mapQDepth = 8 - ) - val sv = ChiselStage.emitSystemVerilog( - new LinxCoreTop(CoreParams(robEntries = 8, commitWidth = 2, scalarLsu = lsu)) - ) - - assert(sv.contains("module LinxCoreTop")) - assert(sv.contains("module ReducedCommitROB")) - assert(sv.contains("module CommitTraceMonitor")) - assert(sv.contains("module ScalarLSU")) - assert(sv.contains("module ScalarLoadCompletionROBBridge")) - assert(sv.contains("module ScalarLoadGPRCompletionSink")) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("module STQSCBCommitPath")) - assert(sv.contains("module ScalarLSULoadPath")) - assert(sv.contains("module ScalarLSURecoveryBoundary")) - assert(sv.contains("module ScalarLSURecoverySource")) - assert(sv.contains("module RecoveryEligibilityControl")) - assert(!sv.contains("module RecoveryCleanupControl")) - assert(sv.contains("io_scalarLsu_store_flush_req_valid")) - assert(sv.contains("io_scalarLsu_load_preciseFlush_req_valid")) - assert(sv.contains("io_scalarLsu_load_loadReturn_robLookupRid_value")) - assert(sv.contains("io_scalarLsu_load_loadReturn_completion_payload_rid_value")) - assert(sv.contains("io_scalarLoadCompleteSelected")) - assert(sv.contains("io_completeCollision")) - assert(sv.contains("io_scalarGprReadyMask")) - assert(sv.contains("io_scalarLoadWritebackSelected")) - assert(sv.contains("io_scalarLoadWakeupPublished")) - assert(sv.contains("io_scalarBackendContractError")) - assert(sv.contains("io_scalarLsu_recovery_oldestBid_0_value")) - assert(sv.contains("io_scalarLsu_recovery_fullBidLookupRequest_rid_value")) - assert(sv.contains("io_scalarLsu_recovery_fullBidLookup_blockBid")) - assert(sv.contains("io_scalarLsu_recovery_source_blockBid")) - assert(sv.contains("io_scalarLsu_recovery_sourceReady")) - assert(sv.contains("io_scalarLsu_recovery_sourceStidInRange")) - assert(sv.contains("commitContractError")) - assert(sv.contains("io_idle")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala b/chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala new file mode 100644 index 00000000..6b54d471 --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala @@ -0,0 +1,243 @@ +package linxcore.top + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.ctu.CTU +import linxcore.ooo.{CommitControl, RecoveryControl} +import linxcore.params.{CoreParams, ParamProfiles} +import linxcore.top.interface._ +import org.scalatest.funsuite.AnyFunSuite + +class RecoveryIntegrationSpec extends AnyFunSuite with ChiselSim { + private val p: CoreParams = { + val base = ParamProfiles.W4 + base.copy(ooo = base.ooo.copy( + stidCount = 2, + stidIdentityEntries = 2, + robGroupsPerStid = 4, + robBankCount = 4, + brobEntriesPerStid = 4, + gprPhysRegs = 64, + gprMapQDepthPerStid = 64)) + } + + private def clearCommit(dut: CommitControl): Unit = { + dut.io.rob.valid.poke(false.B) + dut.io.rob.bits.poke(0.U.asTypeOf(dut.io.rob.bits)) + dut.io.residentHeads.foreach(_.poke(0.U.asTypeOf(dut.io.residentHeads.head))) + dut.io.recoveryFence.foreach(_.poke(false.B)) + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.robReleaseReady.poke(true.B) + dut.io.renameReleaseReady.poke(true.B) + dut.io.brobReleaseReady.poke(true.B) + dut.io.pcBufferCommitReady.poke(true.B) + dut.io.out.ready.poke(false.B) + dut.io.debugRequest.valid.poke(false.B) + dut.io.debugRequest.bits.poke(0.U.asTypeOf(dut.io.debugRequest.bits)) + dut.io.debugResponse.ready.poke(false.B) + dut.io.robNoflushReady.valid.poke(false.B) + dut.io.robNoflushReady.bits.poke(0.U.asTypeOf(dut.io.robNoflushReady.bits)) + dut.io.robNoflush.ready.poke(false.B) + } + + private def clearRecovery(dut: RecoveryControl): Unit = { + dut.io.events.foreach { event => + event.valid.poke(false.B) + event.bits.poke(0.U.asTypeOf(event.bits)) + } + dut.io.interrupts.foreach(_.poke(0.U.asTypeOf(dut.io.interrupts.head))) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.interruptBoundary.poke(0.U.asTypeOf(dut.io.interruptBoundary)) + dut.io.abort.poke(false.B) + dut.io.robCandidateStatus.foreach { status => + status.valid.poke(false.B) + status.bits.poke(0.U.asTypeOf(status.bits)) + } + dut.io.robPrepare.ready.poke(true.B) + dut.io.robPrepared.valid.poke(false.B) + dut.io.robPrepared.bits.poke(0.U.asTypeOf(dut.io.robPrepared.bits)) + dut.io.targets.foreach { target => + target.prepare.ready.poke(true.B) + target.prepared.valid.poke(false.B) + target.prepared.bits.poke(0.U.asTypeOf(target.prepared.bits)) + } + } + + test("OOO selects only the highest-priority interrupt for the precise STID boundary") { + simulate(new CommitControl(p)) { dut => + clearCommit(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.headValid.poke(true.B) + dut.io.rob.bits.head.stid.poke(0.U) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).stid.poke(0.U) + dut.io.interrupts(0).cause.poke(7.U) + dut.io.interrupts(0).priority.poke(3.U) + dut.io.interrupts(1).valid.poke(true.B) + dut.io.interrupts(1).stid.poke(1.U) + dut.io.interrupts(1).cause.poke(9.U) + dut.io.interrupts(1).priority.poke(15.U) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Interrupt) + dut.io.out.bits.trap.cause.expect(7.U) + dut.io.out.bits.trap.rob.stid.expect(0.U) + } + } + + test("a synchronous head fault has priority over an interrupt") { + simulate(new CommitControl(p)) { dut => + clearCommit(dut) + dut.io.rob.valid.poke(true.B) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.entries(0).valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.valid.poke(true.B) + dut.io.rob.bits.entries(0).commit.trap.kind.poke(TrapKind.Exception) + dut.io.rob.bits.entries(0).commit.trap.cause.poke(0x21.U) + dut.io.interruptBoundaryValid.poke(true.B) + dut.io.interrupts(0).valid.poke(true.B) + dut.io.interrupts(0).stid.poke(0.U) + dut.io.interrupts(0).cause.poke(0x12.U) + dut.io.interrupts(0).priority.poke(15.U) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Exception) + dut.io.out.bits.trap.cause.expect(0x21.U) + } + } + + test("OOO accepts halt only at a commit boundary and resume releases it") { + simulate(new CommitControl(p)) { dut => + clearCommit(dut) + dut.io.rob.bits.count.poke(1.U) + dut.io.rob.bits.headValid.poke(true.B) + dut.io.rob.bits.head.stid.poke(0.U) + dut.io.interruptBoundary.stid.poke(0.U) + dut.io.debugRequest.valid.poke(true.B) + dut.io.debugRequest.bits.transactionId.poke(0x44.U) + dut.io.debugRequest.bits.command.poke(DebugCommand.Halt) + dut.io.debugRequest.bits.stid.poke(0.U) + dut.io.debugRequest.ready.expect(true.B) + dut.clock.step() + dut.io.debugRequest.valid.poke(false.B) + dut.io.rob.valid.poke(true.B) + dut.io.interruptBoundaryValid.poke(true.B) + + dut.io.out.valid.expect(true.B) + dut.io.out.bits.trap.valid.expect(true.B) + dut.io.out.bits.trap.kind.expect(TrapKind.Debug) + dut.io.out.bits.trap.rob.stid.expect(0.U) + dut.io.out.ready.poke(true.B) + dut.clock.step() + dut.io.out.ready.poke(false.B) + dut.io.rob.valid.poke(false.B) + dut.io.interruptBoundaryValid.poke(false.B) + dut.io.halted.expect(true.B) + dut.io.debugResponse.valid.expect(true.B) + dut.io.debugResponse.bits.transactionId.expect(0x44.U) + dut.io.debugResponse.bits.accepted.expect(true.B) + dut.io.debugResponse.ready.poke(true.B) + dut.clock.step() + dut.io.debugResponse.ready.poke(false.B) + + dut.io.debugRequest.valid.poke(true.B) + dut.io.debugRequest.bits.transactionId.poke(0x45.U) + dut.io.debugRequest.bits.command.poke(DebugCommand.Resume) + dut.io.debugRequest.bits.stid.poke(0.U) + dut.io.debugRequest.ready.expect(true.B) + dut.clock.step() + dut.io.debugRequest.valid.poke(false.B) + dut.io.halted.expect(false.B) + dut.io.debugResponse.valid.expect(true.B) + dut.io.debugResponse.bits.transactionId.expect(0x45.U) + dut.io.debugResponse.bits.accepted.expect(true.B) + } + } + + test("prepare fans out once and one missing acknowledgement stalls common apply") { + simulate(new RecoveryControl(p, targetCount = 3)) { dut => + clearRecovery(dut) + dut.io.events(0).valid.poke(true.B) + dut.io.events(0).bits.transactionId.poke(0x80.U) + dut.io.events(0).bits.cause.poke(RecoveryCause.MemoryOrder) + dut.io.events(0).bits.trigger.stid.poke(0.U) + dut.io.robCandidateStatus(0).valid.poke(true.B) + dut.io.robCandidateStatus(0).bits.transactionId.poke(0x80.U) + dut.io.robCandidateStatus(0).bits.trigger.stid.poke(0.U) + dut.io.robCandidateStatus(0).bits.eligible.poke(true.B) + dut.clock.step() + dut.io.events(0).valid.poke(false.B) + dut.io.robCandidateStatus(0).valid.poke(false.B) + dut.io.robPrepared.valid.poke(true.B) + dut.io.robPrepared.bits.poke(dut.io.robPrepare.bits.peek()) + dut.clock.step() + dut.io.robPrepared.valid.poke(false.B) + + dut.io.targets.foreach(_.prepare.valid.expect(true.B)) + dut.clock.step() + dut.io.targets.foreach(_.prepare.valid.expect(false.B)) + for (target <- 0 until 2) { + dut.io.targets(target).prepared.valid.poke(true.B) + dut.io.targets(target).prepared.bits.poke( + dut.io.targets(target).prepare.bits.peek()) + } + dut.clock.step() + dut.io.targets.foreach(_.apply.valid.expect(false.B)) + + dut.io.targets(0).prepared.valid.poke(false.B) + dut.io.targets(1).prepared.valid.poke(false.B) + dut.io.targets(2).prepared.valid.poke(true.B) + dut.io.targets(2).prepared.bits.poke( + dut.io.targets(2).prepare.bits.peek()) + dut.clock.step() + dut.io.targets.foreach(_.apply.valid.expect(true.B)) + } + } + + test("a target-STID prepare does not block unrelated CTU admission") { + simulate(new CTU(p)) { dut => + dut.io.fromIfu.valid.poke(false.B) + dut.io.fromIfu.bits.poke(0.U.asTypeOf(dut.io.fromIfu.bits)) + dut.io.toOoo.ready.poke(true.B) + dut.io.trace.ready.poke(true.B) + dut.io.recovery.prepare.valid.poke(true.B) + dut.io.recovery.prepare.bits.poke(0.U.asTypeOf(dut.io.recovery.prepare.bits)) + dut.io.recovery.prepare.bits.transactionId.poke(0x91.U) + dut.io.recovery.prepare.bits.phase.poke(RecoveryPhase.Prepare) + dut.io.recovery.prepare.bits.cause.poke(RecoveryCause.Branch) + dut.io.recovery.prepare.bits.trigger.stid.poke(0.U) + dut.io.recovery.prepared.ready.poke(false.B) + dut.io.recovery.apply.valid.poke(false.B) + dut.io.recovery.apply.bits.poke(0.U.asTypeOf(dut.io.recovery.apply.bits)) + dut.io.recovery.abort.valid.poke(false.B) + dut.io.recovery.abort.bits.poke(0.U.asTypeOf(dut.io.recovery.abort.bits)) + dut.clock.step() + dut.io.recovery.prepare.valid.poke(false.B) + + dut.io.fromIfu.bits.count.poke(1.U) + dut.io.fromIfu.bits.entries(0).identity.stid.poke(1.U) + dut.io.fromIfu.bits.entries(0).identity.instructionId.poke(0x55.U) + dut.io.fromIfu.bits.entries(0).identity.epoch.poke(1.U) + dut.io.fromIfu.bits.entries(0).instruction.poke(5.U) + dut.io.fromIfu.bits.entries(0).lengthBytes.poke(2.U) + dut.io.fromIfu.valid.poke(true.B) + dut.io.fromIfu.ready.expect(true.B) + dut.clock.step() + dut.io.fromIfu.valid.poke(false.B) + var cycles = 0 + while (!dut.io.toOoo.valid.peek().litToBoolean && cycles < 8) { + dut.clock.step() + cycles += 1 + } + assert(cycles < 8, "unrelated STID did not make forward progress") + dut.io.toOoo.valid.expect(true.B) + dut.io.toOoo.bits.entries(0).parent.identity.stid.expect(1.U) + dut.io.toOoo.bits.entries(0).parent.identity.instructionId.expect(0x55.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/top/ScalarLoadCompletionROBBridgeSpec.scala b/chisel/src/test/scala/linxcore/top/ScalarLoadCompletionROBBridgeSpec.scala deleted file mode 100644 index 1f5e24fc..00000000 --- a/chisel/src/test/scala/linxcore/top/ScalarLoadCompletionROBBridgeSpec.scala +++ /dev/null @@ -1,81 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import org.scalatest.funsuite.AnyFunSuite - -object ScalarLoadCompletionROBBridgeReference { - final case class Result( - loadReady: Boolean, - robComplete: Option[Int], - loadSelected: Boolean, - collision: Boolean, - sameRowCollision: Boolean) - - def arbitrate( - external: Option[Int], - loadCandidate: Option[Int], - loadResolveEnable: Boolean, - exactCompleteReady: Boolean): Result = { - val loadReady = loadResolveEnable && external.isEmpty && exactCompleteReady - val selected = loadCandidate.nonEmpty && loadReady - Result( - loadReady = loadReady, - robComplete = external.orElse(if (selected) loadCandidate else None), - loadSelected = selected, - collision = external.nonEmpty && loadCandidate.nonEmpty, - sameRowCollision = external.nonEmpty && external == loadCandidate - ) - } -} - -class ScalarLoadCompletionROBBridgeSpec extends AnyFunSuite { - import ScalarLoadCompletionROBBridgeReference._ - - test("external completion has priority and holds a colliding scalar load") { - val collision = arbitrate(Some(1), Some(2), loadResolveEnable = true, exactCompleteReady = true) - assert(!collision.loadReady) - assert(!collision.loadSelected) - assert(collision.robComplete.contains(1)) - assert(collision.collision) - assert(!collision.sameRowCollision) - - val retry = arbitrate(None, Some(2), loadResolveEnable = true, exactCompleteReady = true) - assert(retry.loadReady && retry.loadSelected) - assert(retry.robComplete.contains(2)) - } - - test("same-row external and scalar completion is a duplicate-owner violation") { - val result = arbitrate(Some(3), Some(3), loadResolveEnable = true, exactCompleteReady = true) - assert(!result.loadReady) - assert(!result.loadSelected) - assert(result.robComplete.contains(3)) - assert(result.collision && result.sameRowCollision) - } - - test("disabled resolve ownership prevents scalar load completion") { - val result = arbitrate(None, Some(3), loadResolveEnable = false, exactCompleteReady = true) - assert(!result.loadReady) - assert(!result.loadSelected) - assert(result.robComplete.isEmpty) - } - - test("stale or free exact RID holds scalar W2 completion") { - val result = arbitrate(None, Some(3), loadResolveEnable = true, exactCompleteReady = false) - assert(!result.loadReady) - assert(!result.loadSelected) - assert(result.robComplete.isEmpty) - } - - test("bridge elaborates exact lookup and one shared completion sink") { - val sv = ChiselStage.emitSystemVerilog(new ScalarLoadCompletionROBBridge(entries = 8)) - assert(sv.contains("module ScalarLoadCompletionROBBridge")) - assert(sv.contains("io_loadLookupRid_wrap")) - assert(sv.contains("io_robLookupRowValid")) - assert(sv.contains("io_loadResolveReady")) - assert(sv.contains("io_robExactCompleteReady")) - assert(sv.contains("io_robExactCompleteRid_wrap")) - assert(sv.contains("io_robCompleteRobValue")) - assert(sv.contains("io_sameRowCollision")) - assert(sv.contains("io_protocolError")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/ScalarLoadGPRCompletionSinkSpec.scala b/chisel/src/test/scala/linxcore/top/ScalarLoadGPRCompletionSinkSpec.scala deleted file mode 100644 index 7abd7404..00000000 --- a/chisel/src/test/scala/linxcore/top/ScalarLoadGPRCompletionSinkSpec.scala +++ /dev/null @@ -1,95 +0,0 @@ -package linxcore.top - -import circt.stage.ChiselStage -import linxcore.common.{ScalarBackendParams, ScalarLsuParams} -import org.scalatest.funsuite.AnyFunSuite - -object ScalarLoadGPRCompletionSinkReference { - final case class Result( - ready: Boolean, - writebackFire: Boolean, - wakeupFire: Boolean, - blockedByExternal: Boolean, - unsupportedDestination: Boolean) - - def arbitrate( - loadValid: Boolean, - loadTag: Int, - externalTag: Option[Int], - writePorts: Int, - resolveReady: Boolean, - destinationSupported: Boolean = true): Result = { - val unsupported = loadValid && !destinationSupported - val hasPort = externalTag.isEmpty || (writePorts > 1 && !externalTag.contains(loadTag)) - val ready = !loadValid || (destinationSupported && hasPort) - val resolveFire = loadValid && resolveReady && ready - Result( - ready = ready, - writebackFire = resolveFire, - wakeupFire = resolveFire, - blockedByExternal = loadValid && destinationSupported && !hasPort, - unsupportedDestination = unsupported) - } -} - -class ScalarLoadGPRCompletionSinkSpec extends AnyFunSuite { - import ScalarLoadGPRCompletionSinkReference._ - - test("same-tag external write holds scalar W2") { - val result = arbitrate( - loadValid = true, - loadTag = 40, - externalTag = Some(40), - writePorts = 2, - resolveReady = true) - assert(!result.ready && !result.writebackFire && !result.wakeupFire) - assert(result.blockedByExternal) - } - - test("independent tags use parameterized write ports in one cycle") { - val result = arbitrate( - loadValid = true, - loadTag = 40, - externalTag = Some(41), - writePorts = 2, - resolveReady = true) - assert(result.ready && result.writebackFire && result.wakeupFire) - assert(!result.blockedByExternal) - } - - test("one physical port serializes every external write") { - val result = arbitrate( - loadValid = true, - loadTag = 40, - externalTag = Some(41), - writePorts = 1, - resolveReady = true) - assert(!result.ready && result.blockedByExternal) - } - - test("unsupported T/U destination is an explicit non-mutating contract error") { - val result = arbitrate( - loadValid = true, - loadTag = 40, - externalTag = None, - writePorts = 2, - resolveReady = true, - destinationSupported = false) - assert(!result.ready) - assert(!result.writebackFire && !result.wakeupFire) - assert(result.unsupportedDestination) - } - - test("sink elaborates canonical GPR writeback and ready-table wakeup ownership") { - val sv = ChiselStage.emitSystemVerilog(new ScalarLoadGPRCompletionSink( - ScalarBackendParams(gprWritePorts = 2), - ScalarLsuParams() - )) - assert(sv.contains("module ScalarLoadGPRCompletionSink")) - assert(sv.contains("module ScalarGPRFile")) - assert(sv.contains("io_loadWritebackReady")) - assert(sv.contains("io_loadWakeupReady")) - assert(sv.contains("io_loadBlockedByExternalWrite")) - assert(sv.contains("io_readyMask")) - } -} diff --git a/chisel/src/test/scala/linxcore/top/TOPSpec.scala b/chisel/src/test/scala/linxcore/top/TOPSpec.scala new file mode 100644 index 00000000..3f9a8a9c --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/TOPSpec.scala @@ -0,0 +1,36 @@ +package linxcore.top + +import _root_.circt.stage.ChiselStage +import java.nio.file.{Files, Paths} +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class TOPSpec extends AnyFunSuite { + private val repoRoot = Paths.get("..").toAbsolutePath.normalize + + test("W4 TOP instantiates each public box exactly once and owns no state") { + val sv = ChiselStage.emitSystemVerilog(new TOP(SimulationParamProfiles.W4)) + + Seq("IFU", "CTU", "OOO", "IEX", "LSU", "DTU").foreach { box => + assert((s"(?m)^ ${box} ${box.toLowerCase} \\(".r findAllIn sv).size == 1, box) + } + assert(!sv.contains("iex_to_ifu")) + assert(!sv.contains("lsu_to_ifu")) + + val source = Files.readString( + repoRoot.resolve("chisel/src/main/scala/linxcore/top/TOP.scala")) + val stateTokens = Seq("Reg(", "RegInit(", "RegNext(", "Mem(", + "SyncReadMem(", "new Queue(") + stateTokens.foreach(token => assert(!source.contains(token), token)) + } + + test("CMD remains externally backpressured and trace observation is lossy") { + val source = Files.readString( + repoRoot.resolve("chisel/src/main/scala/linxcore/top/TOP.scala")) + + assert(source.contains("io.cmdIssue <> iex.io.cmdIssue")) + assert(!source.contains("iex.io.cmdIssue.ready := true.B")) + assert(source.contains("new TracePrefixPacker")) + assert(!source.contains("dtu.io.traceIn.ready")) + } +} diff --git a/chisel/src/test/scala/linxcore/top/TOPWidthProfilesSpec.scala b/chisel/src/test/scala/linxcore/top/TOPWidthProfilesSpec.scala new file mode 100644 index 00000000..6308cf6c --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/TOPWidthProfilesSpec.scala @@ -0,0 +1,20 @@ +package linxcore.top + +import _root_.circt.stage.ChiselStage +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class TOPWidthProfilesSpec extends AnyFunSuite { + Seq(2, 4, 6, 8).foreach { width => + test(s"W$width TOP elaborates the selected public widths") { + val p = SimulationParamProfiles.forWidth(width) + val chirrtl = ChiselStage.emitCHIRRTL(new TOP(p)) + + assert(chirrtl.contains("module TOP")) + assert(p.widths.fetchWidth == width) + assert(p.widths.decodeWidth == width) + assert(p.widths.issueWidth == width) + assert(p.widths.retireWidth == width) + } + } +} diff --git a/chisel/src/test/scala/linxcore/top/TracePrefixPackerSpec.scala b/chisel/src/test/scala/linxcore/top/TracePrefixPackerSpec.scala new file mode 100644 index 00000000..043bb89a --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/TracePrefixPackerSpec.scala @@ -0,0 +1,30 @@ +package linxcore.top + +import chisel3._ +import chisel3.simulator.scalatest.ChiselSim +import linxcore.params.SimulationParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class TracePrefixPackerSpec extends AnyFunSuite with ChiselSim { + test("simultaneous sources pack a deterministic prefix and count overflow") { + simulate(new TracePrefixPacker(SimulationParamProfiles.W4, 3)) { dut => + dut.io.out.ready.poke(false.B) + dut.io.in.foreach { source => + source.bits.poke(0.U.asTypeOf(source.bits)) + source.valid.poke(true.B) + source.bits.count.poke(2.U) + } + for (source <- 0 until 3; lane <- 0 until 2) { + dut.io.in(source).bits.entries(lane).payload + .poke((source * 10 + lane).U) + } + dut.io.in.foreach(_.ready.expect(true.B)) + dut.io.out.valid.expect(true.B) + dut.io.out.bits.count.expect(4.U) + Seq(0, 1, 10, 11).zipWithIndex.foreach { case (value, lane) => + dut.io.out.bits.entries(lane).payload.expect(value.U) + } + dut.io.dropped.expect(2.U) + } + } +} diff --git a/chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala b/chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala new file mode 100644 index 00000000..427fbee8 --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala @@ -0,0 +1,252 @@ +package linxcore.top.interface + +import java.nio.charset.StandardCharsets +import java.nio.file.{Files, Paths} +import chisel3.util.log2Ceil +import linxcore.params.ParamProfiles +import org.scalatest.funsuite.AnyFunSuite + +class InterfaceManifestSpec extends AnyFunSuite { + private val repoRoot = Paths.get("..").toAbsolutePath.normalize + private val generatedRoot = repoRoot.resolve("docs/chisel/generated") + + test("generated JSON and Markdown are exact projections of canonical Bundles") { + val expectedJson = InterfaceManifest.renderJson + val expectedMarkdown = InterfaceManifest.renderMarkdown + val actualJson = Files.readString( + generatedRoot.resolve("top-interface-manifest.json"), + StandardCharsets.UTF_8) + val actualMarkdown = Files.readString( + generatedRoot.resolve("top-interface-manifest.md"), + StandardCharsets.UTF_8) + + assert(actualJson == expectedJson) + assert(actualMarkdown == expectedMarkdown) + } + + test("every endpoint has one contract home and every profile is represented") { + val manifest = InterfaceManifest.model + + assert(manifest.profiles.map(_.name) == Seq("W2", "W4", "W6", "W8")) + assert(manifest.profiles.forall(_.endpoints.nonEmpty)) + assert(manifest.profiles.flatMap(_.endpoints).forall(_.contractId.startsWith("IFC-"))) + assert(manifest.profiles.flatMap(_.endpoints).forall(_.ports.nonEmpty)) + assert(manifest.profiles.flatMap(_.endpoints).flatMap(_.ports) + .exists(port => port.name.endsWith("_instruction") && port.width == 64)) + assert(!manifest.profiles.flatMap(_.endpoints).exists { endpoint => + endpoint.name.contains("iex_to_ifu") || endpoint.name.contains("lsu_to_ifu") + }) + val recoveryEndpoints = manifest.profiles.head.endpoints + .filter(_.contractId == "IFC-RECOVERY-001") + .map(_.name) + .toSet + assert(recoveryEndpoints == Set( + "owner_to_ooo_recovery_event", + "ooo_recovery_prepare", + "target_to_ooo_recovery_prepared", + "ooo_recovery_apply", + "ooo_recovery_abort")) + + val external = manifest.profiles.head.endpoints + .filter(_.contractId.startsWith("IFC-TOP-EXT-")) + assert(external.exists(_.name == "top_io")) + assert(external.flatMap(_.ports).exists(port => + port.name == "instructionMemoryRequest_bits_size" && + port.width == MemorySize.getWidth)) + assert(external.flatMap(_.ports).exists(port => + port.name.startsWith("dataMemoryRequest_3_bits_"))) + } + + test("backend profiles freeze lane multiplicity canonical payload names and identities") { + InterfaceManifest.model.profiles.foreach { profile => + val endpoints = profile.endpoints.map(endpoint => endpoint.name -> endpoint).toMap + val width = profile.width + + val expected = Map( + "ooo_to_iex_alu" -> ("OOO", "IEX", 2, "DispatchTxn"), + "ooo_to_iex_bru" -> ("OOO", "IEX", 1, "DispatchTxn"), + "ooo_to_iex_agu" -> ("OOO", "IEX", 2, "DispatchTxn"), + "ooo_to_iex_std" -> ("OOO", "IEX", 2, "StoreDispatchTxn"), + "ooo_to_iex_system" -> ("OOO", "IEX", 1, "DispatchTxn"), + "ooo_to_iex_cmd" -> ("OOO", "IEX", 1, "DispatchTxn"), + "ooo_to_iex_rob_noflush" -> ("OOO", "IEX", 1, "RobNoflushTxn"), + "iex_to_ooo_rob_noflush_ready" -> + ("IEX", "OOO", 1, "RobNoflushReadyTxn"), + "iex_to_ooo_rob_resolve" -> ("IEX", "OOO", width, "RobResolveTxn"), + "iex_to_ooo_system_issue" -> ("IEX", "OOO", 1, "SystemIssueTxn"), + "iex_to_ooo_pc_buffer_read_address" -> + ("IEX", "OOO", profile.endpoints + .find(_.name == "iex_to_ooo_pc_buffer_read_address").get.lanes, + "PcBufferReadAddress"), + "ooo_to_iex_pc_buffer_read_pc_base" -> + ("OOO", "IEX", profile.endpoints + .find(_.name == "ooo_to_iex_pc_buffer_read_pc_base").get.lanes, + "UInt"), + "iex_to_lsu_load_issue" -> ("IEX", "LSU", 2, "LoadIssueTxn"), + "lsu_to_iex_load_allocation_preview" -> + ("LSU", "IEX", 2, "LoadAllocationPreview"), + "lsu_to_iex_load_launch" -> ("LSU", "IEX", 2, "LoadLaunchTxn"), + "iex_to_lsu_store_reservation" -> + ("IEX", "LSU", 2, "StoreReservationTxn"), + "iex_to_lsu_store_address" -> ("IEX", "LSU", 2, "StoreAddressTxn"), + "iex_to_lsu_store_data" -> ("IEX", "LSU", 2, "StoreDataTxn"), + "lsu_to_iex_load_result" -> ("LSU", "IEX", 2, "LoadResultTxn"), + "lsu_to_iex_load_reissue" -> ("LSU", "IEX", 2, "LoadReissueTxn"), + "lsu_to_iex_load_repick" -> ("LSU", "IEX", 2, "LoadRepickTxn"), + "lsu_to_iex_load_cancel" -> ("LSU", "IEX", 2, "LoadCancelTxn"), + "ooo_to_lsu_store_commit" -> + ("OOO", "LSU", 1, "StoreCommitAuthorizationTxn"), + "lsu_internal_store_classify" -> + ("LSU Translation", "LSU Commit Backend", 1, + "StoreMemoryClassifyTxn"), + "external_cmd_issue" -> ("IEX", "External CMD", 1, "CmdIssueTxn")) + + expected.foreach { case (name, (producer, consumer, lanes, payload)) => + val endpoint = endpoints(name) + assert(endpoint.producer == producer, name) + assert(endpoint.consumer == consumer, name) + assert(endpoint.lanes == lanes, name) + assert(endpoint.payload == payload, name) + } + + val orderPorts = endpoints("ooo_to_iex_alu").ports + .filter(_.name.startsWith("memoryOrder_")) + .map(_.name) + .toSet + assert(orderPorts == Set( + "memoryOrder_requestCount", "memoryOrder_firstLsid", + "memoryOrder_firstLid", "memoryOrder_firstSid", + "memoryOrder_yostValid", "memoryOrder_yostLsid", + "memoryOrder_yostSid", "memoryOrder_yoldValid", + "memoryOrder_yoldLsid", "memoryOrder_yoldLid")) + assert(!orderPorts.exists(name => + name.toLowerCase.contains("transaction") || + name.toLowerCase.contains("attempt") || + name.toLowerCase.contains("pipe") || + name.toLowerCase.contains("slot") || + name.toLowerCase.contains("lane"))) + + val trapPorts = endpoints("ooo_to_iex_alu").ports + .filter(_.name.startsWith("trap_")) + .map(port => port.name -> port.width) + .toMap + assert(trapPorts == Map( + "trap_valid" -> 1, + "trap_cause" -> ParamProfiles.W4.trapCauseWidth)) + + val storeTrapPorts = endpoints("ooo_to_iex_std").ports + .filter(port => port.name.startsWith("sta_trap_") || + port.name.startsWith("std_trap_")) + .map(port => port.name -> port.width) + .toMap + assert(storeTrapPorts == Map( + "sta_trap_valid" -> 1, + "sta_trap_cause" -> ParamProfiles.W4.trapCauseWidth, + "std_trap_valid" -> 1, + "std_trap_cause" -> ParamProfiles.W4.trapCauseWidth)) + + val pcIndexOffsetPorts = endpoints("ooo_to_iex_alu").ports + .filter(_.name.startsWith("pcBufferIndexOffset_")) + .map(port => port.name -> port.width) + .toMap + val p = ParamProfiles.forWidth(width) + assert(pcIndexOffsetPorts == Map( + "pcBufferIndexOffset_valid" -> 1, + "pcBufferIndexOffset_pcBufferIndex" -> log2Ceil(p.ooo.pcBufferEntries), + "pcBufferIndexOffset_pcOffset" -> p.ooo.pcOffsetWidth, + "pcBufferIndexOffset_allocationEpoch" -> + p.ooo.pcAllocationEpochWidth)) + + val readAddressPorts = endpoints("iex_to_ooo_pc_buffer_read_address").ports + .map(port => port.name -> port.width) + .toMap + assert(readAddressPorts == Map( + "valid" -> 1, + "stid" -> math.max(1, log2Ceil(p.ooo.stidCount)), + "pcBufferIndex" -> log2Ceil(p.ooo.pcBufferEntries), + "allocationEpoch" -> p.ooo.pcAllocationEpochWidth)) + assert(endpoints("ooo_to_iex_pc_buffer_read_pc_base").ports == + Seq(ManifestPort("", p.pcWidth))) + + val issueIdentityPorts = endpoints("iex_to_lsu_load_issue").ports + .filter(_.name.startsWith("identity_")) + .map(_.name) + .toSet + assert(issueIdentityPorts.contains("identity_transaction_value")) + assert(issueIdentityPorts.contains("identity_transaction_generation")) + assert(issueIdentityPorts.contains("identity_lsid")) + assert(issueIdentityPorts.contains("identity_attemptGeneration")) + assert(issueIdentityPorts.contains("identity_pipeId")) + } + + val w4 = InterfaceManifest.model.profiles.find(_.name == "W4").get + val endpoints = w4.endpoints.map(endpoint => endpoint.name -> endpoint).toMap + assert(endpoints("ooo_to_iex_alu").lanes == 2) + assert(endpoints("ooo_to_iex_bru").lanes == 1) + assert(endpoints("ooo_to_iex_agu").lanes == 2) + assert(endpoints("ooo_to_iex_std").lanes == 2) + assert(endpoints("ooo_to_iex_system").lanes == 1) + assert(endpoints("ooo_to_iex_cmd").lanes == 1) + assert(endpoints("iex_to_lsu_load_issue").lanes == 2) + assert(endpoints("iex_to_lsu_store_address").lanes == 2) + assert(endpoints("iex_to_lsu_store_data").lanes == 2) + } + + test("internal CMD queue multiplicity is independent of the singleton external endpoint") { + val base = ParamProfiles.W4 + val p = base.copy(iex = base.iex.copy(cmdIssueQueues = 2)) + val profile = InterfaceManifest.profileFor("CUSTOM", p) + val endpoints = profile.endpoints.map(endpoint => endpoint.name -> endpoint).toMap + + assert(new OOOIEXIO(p).cmdDispatch.length == 2) + assert(endpoints("ooo_to_iex_cmd").lanes == 2) + assert(endpoints("external_cmd_issue").lanes == 1) + } + + test("memory lifecycle manifest leaves preserve independent identity widths") { + val base = ParamProfiles.W4 + val p = base.copy( + ooo = base.ooo.copy(robGroupsPerStid = 32), + lsu = base.lsu.copy( + loadPipes = 8, + loadQueueEntries = 16, + loadReturnQueueEntries = 8), + lsidWidth = 37, + ridGenerationWidth = 7, + residentGenerationWidth = 9, + memoryTransactionIdWidth = 41, + memoryTransactionGenerationWidth = 11, + memoryAttemptGenerationWidth = 13) + val profile = InterfaceManifest.profileFor("IDENTITY", p) + val endpoints = profile.endpoints.map(endpoint => endpoint.name -> endpoint).toMap + val expectedSuffixWidths = Map( + "rob_peId" -> p.peIdWidth, + "rob_stid" -> 1, + "rob_ridSlot" -> 6, + "rob_ridGeneration" -> 7, + "rob_memberIndex" -> 2, + "rob_residentGeneration" -> 9, + "rob_bid" -> p.nativeBidWidth, + "rob_brobGeneration" -> p.brobGenerationWidth, + "transaction_value" -> 41, + "transaction_generation" -> 11, + "lsid" -> 37, + "attemptGeneration" -> 13, + "pipeId" -> 3) + + def assertIdentity(endpointName: String, prefix: String): Unit = { + val actual = endpoints(endpointName).ports.collect { + case port if port.name.startsWith(prefix) => + port.name.stripPrefix(prefix) -> port.width + }.toMap + assert(actual == expectedSuffixWidths, s"$endpointName:$prefix") + } + + assertIdentity("iex_to_lsu_load_issue", "identity_") + assertIdentity("lsu_to_iex_load_reissue", "currentIdentity_") + assertIdentity("lsu_to_iex_load_reissue", "nextIdentity_") + assertIdentity("lsu_to_iex_load_repick", "currentIdentity_") + assertIdentity("lsu_to_iex_load_repick", "nextIdentity_") + assertIdentity("lsu_to_iex_load_cancel", "currentIdentity_") + } +} diff --git a/chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala b/chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala new file mode 100644 index 00000000..b6266ff3 --- /dev/null +++ b/chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala @@ -0,0 +1,550 @@ +package linxcore.top.interface + +import chisel3._ +import chisel3.reflect.DataMirror +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import java.nio.file.{Files, Paths} +import linxcore.params.{CoreParams, ParamProfiles} +import org.scalatest.funsuite.AnyFunSuite +import scala.jdk.CollectionConverters._ + +class InterfaceHoldProbeIO(val p: CoreParams) extends Bundle { + val in = Flipped(Decoupled(new FetchedPacket(p))) + val out = Decoupled(new FetchedPacket(p)) +} + +class InterfaceHoldProbe(val p: CoreParams) extends Module { + val io = IO(new InterfaceHoldProbeIO(p)) + + val occupied = RegInit(false.B) + val payload = Reg(new FetchedPacket(p)) + + io.in.ready := !occupied || io.out.ready + io.out.valid := occupied + io.out.bits := payload + + val stalled = io.out.valid && !io.out.ready + val previousStalled = RegNext(stalled, false.B) + val previousPayload = RegEnable(io.out.bits.asUInt, stalled) + when(previousStalled) { + assert(io.out.valid) + assert(io.out.bits.asUInt === previousPayload) + } + + when(io.in.fire) { + payload := io.in.bits + occupied := true.B + }.elsewhen(io.out.fire) { + occupied := false.B + } +} + +class BoxIOElaborationProbeIO(val p: CoreParams) extends Bundle { + val ifu = new IFUIO(p) + val ctu = new CTUIO(p) + val ooo = new OOOIO(p) + val iex = new IEXIO(p) + val lsu = new LSUIO(p) + val dtu = new DTUIO(p) + val top = new TOPIO(p) +} + +class BoxIOElaborationProbe(val p: CoreParams) extends Module { + val io = IO(new BoxIOElaborationProbeIO(p)) + io := DontCare +} + +class InterfaceDirectionProbe(val p: CoreParams) extends RawModule { + val iex = IO(new IEXIO(p)) + val top = IO(new TOPIO(p)) + + require(DataMirror.directionOf(iex.ooo.aluDispatch.head.valid) == + ActualDirection.Input) + require(DataMirror.directionOf(iex.ooo.aluDispatch.head.bits.trap.valid) == + ActualDirection.Input) + require(DataMirror.directionOf(iex.ooo.aluDispatch.head.bits.trap.cause) == + ActualDirection.Input) + require(DataMirror.directionOf( + iex.ooo.storeDispatch.head.bits.sta.trap.valid) == ActualDirection.Input) + require(DataMirror.directionOf( + iex.ooo.storeDispatch.head.bits.std.trap.valid) == ActualDirection.Input) + require(DataMirror.directionOf(iex.ooo.aluDispatch.head.ready) == + ActualDirection.Output) + require(DataMirror.directionOf(iex.ooo.robResolve.head.valid) == + ActualDirection.Output) + require(DataMirror.directionOf(iex.ooo.robResolve.head.ready) == + ActualDirection.Input) + require(DataMirror.directionOf(iex.ooo.pcBufferReadAddress.head.valid) == + ActualDirection.Output) + require(DataMirror.directionOf( + iex.ooo.pcBufferReadAddress.head.stid) == ActualDirection.Output) + require(DataMirror.directionOf( + iex.ooo.pcBufferReadPcBase.head.valid) == ActualDirection.Input) + require(DataMirror.directionOf( + iex.ooo.pcBufferReadPcBase.head.bits) == ActualDirection.Input) + require(DataMirror.directionOf(iex.lsu.loadAddress.head.valid) == + ActualDirection.Output) + require(DataMirror.directionOf(iex.lsu.loadAddress.head.ready) == + ActualDirection.Input) + require(DataMirror.directionOf(iex.lsu.loadReissue.head.valid) == + ActualDirection.Input) + require(DataMirror.directionOf(iex.lsu.loadReissue.head.ready) == + ActualDirection.Output) + require(DataMirror.directionOf(iex.cmdIssue.valid) == ActualDirection.Output) + require(DataMirror.directionOf(iex.cmdIssue.ready) == ActualDirection.Input) + require(DataMirror.directionOf(iex.branchResolve.valid) == + ActualDirection.Output) + require(DataMirror.directionOf(iex.branchResolve.ready) == + ActualDirection.Input) + require(DataMirror.directionOf(top.cmdIssue.valid) == ActualDirection.Output) + require(DataMirror.directionOf(top.cmdIssue.ready) == ActualDirection.Input) +} + +class TopInterfaceSpec extends AnyFunSuite { + private val repoRoot = Paths.get("..").toAbsolutePath.normalize + private val profiles = Seq( + 2 -> ParamProfiles.W2, + 4 -> ParamProfiles.W4, + 6 -> ParamProfiles.W6, + 8 -> ParamProfiles.W8) + + test("all principal profiles elaborate continuous-prefix front-end packets") { + profiles.foreach { case (width, p) => + val fetched = new FetchedPacket(p) + val d1 = new D1Packet(p) + val commit = new CommitTxn(p) + + assert(fetched.count.getWidth == log2Ceil(width + 1)) + assert(fetched.entries.length == width) + assert(fetched.entries.head.instruction.getWidth == 64) + assert(fetched.entries.head.lengthBytes.getWidth == 4) + assert(!fetched.elements.contains("validMask")) + + assert(d1.count.getWidth == log2Ceil(width + 1)) + assert(d1.entries.length == width) + assert(!d1.elements.contains("validMask")) + + assert(commit.count.getWidth == log2Ceil(p.widths.retireWidth + 1)) + assert(commit.entries.length == p.widths.retireWidth) + assert(!commit.elements.contains("validMask")) + } + } + + test("instruction ROB and memory identities keep every generation domain separate") { + val p = ParamProfiles.W4 + val instruction = new InstructionIdentity(p) + val rob = new RobIdentity(p) + val memory = new MemoryIdentity(p) + + assert(instruction.instructionId.getWidth == p.instructionIdWidth) + assert(instruction.epoch.getWidth == p.epochWidth) + assert(rob.ridSlot.getWidth == log2Ceil(p.ooo.robGroupsPerStid)) + assert(rob.ridGeneration.getWidth == p.ridGenerationWidth) + assert(rob.residentGeneration.getWidth == p.residentGenerationWidth) + assert(rob.bid.getWidth == p.nativeBidWidth) + assert(rob.brobGeneration.getWidth == p.brobGenerationWidth) + assert(memory.transaction.value.getWidth == p.memoryTransactionIdWidth) + assert(memory.transaction.generation.getWidth == p.memoryTransactionGenerationWidth) + assert(memory.lsid.getWidth == p.lsidWidth) + assert(memory.attemptGeneration.getWidth == p.memoryAttemptGenerationWidth) + } + + test("native BID width follows the configured per-STID BROB identity count") { + val base = ParamProfiles.W4 + val p64 = base.copy(ooo = base.ooo.copy( + brobEntriesPerStid = 64, + brobIdentityEntriesPerStid = 64)) + val p512 = base.copy(ooo = base.ooo.copy( + brobEntriesPerStid = 512, + brobIdentityEntriesPerStid = 512)) + + assert(new RobIdentity(p64).bid.getWidth == 6) + assert(new RobIdentity(p512).bid.getWidth == 9) + assert(new RobIdentity(p64).brobGeneration.getWidth == + base.brobGenerationWidth) + assert(new RobIdentity(p512).brobGeneration.getWidth == + base.brobGenerationWidth) + } + + test("decoded and renamed uops preserve architectural and physical tag domains") { + val p = ParamProfiles.W4 + val decoded = new DecodedUop(p) + val renamed = new RenamedUop(p) + + assert(decoded.instruction.parent.instruction.getWidth == 64) + assert(decoded.opcode.getWidth == p.opcodeWidth) + assert(decoded.sources.length == p.maxSourceOperands) + assert(decoded.destinations.length == p.maxDestinationOperands) + assert(decoded.sources.head.atag.getWidth == p.archRegWidth) + assert(renamed.sources.head.atag.getWidth == p.archRegWidth) + assert(renamed.sources.head.ptag.getWidth == log2Ceil(p.ooo.gprPhysRegs)) + assert(renamed.sources.head.ttag.getWidth == log2Ceil(p.ooo.tPhysRegs)) + assert(renamed.sources.head.utag.getWidth == log2Ceil(p.ooo.uPhysRegs)) + assert(renamed.sources.head.tSeqIndex.getWidth == + log2Ceil(p.ooo.tuMapQDepthPerStid)) + assert(renamed.sources.head.tSeqGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(renamed.sources.head.uSeqGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(renamed.destinations.head.previousPtag.getWidth == + log2Ceil(p.ooo.gprPhysRegs)) + } + + test("decoded memory controls and dispatch order metadata are canonical logical payloads") { + val p = ParamProfiles.W4 + val decoded = new DecodedUop(p) + val memory = decoded.memory + val dispatch = new DispatchTxn(p) + val order = dispatch.memoryOrder + + assert(dispatch.elements.keySet == Set( + "transactionId", "uop", "memoryOrder", "pcBufferIndexOffset", "trap")) + assert(dispatch.trap.elements.keySet == Set("valid", "cause")) + assert(dispatch.trap.cause.getWidth == p.trapCauseWidth) + + assert(memory.elements.keySet == Set( + "valid", "isLoad", "isStore", "addressMode", "accessBytes", + "signExtend", "offset", "indexMode", "indexShift", + "addressSourceMask", "dataSourceMask", "writebackValid", + "writebackPreIndex", "requestCount")) + assert(memory.addressMode.getWidth == MemoryAddressMode.getWidth) + assert(memory.accessBytes.getWidth == 4) + assert(memory.offset.getWidth == p.pcWidth) + assert(memory.indexMode.getWidth == MemoryIndexMode.getWidth) + assert(memory.indexShift.getWidth == 5) + assert(memory.addressSourceMask.getWidth == p.maxSourceOperands) + assert(memory.dataSourceMask.getWidth == p.maxSourceOperands) + assert(memory.requestCount.getWidth == order.requestCount.getWidth) + + assert(order.elements.keySet == Set( + "requestCount", "firstLsid", "firstLid", "firstSid", + "yostValid", "yostLsid", "yostSid", + "yoldValid", "yoldLsid", "yoldLid")) + assert(order.requestCount.getWidth == + log2Ceil(p.maxMemoryRequestsPerInstruction + 1)) + assert(order.firstLsid.getWidth == p.lsidWidth) + assert(order.firstLid.getWidth == p.lsidWidth) + assert(order.firstSid.getWidth == p.lsidWidth) + assert(order.yostLsid.getWidth == p.lsidWidth) + assert(order.yostSid.getWidth == p.lsidWidth) + assert(order.yoldLsid.getWidth == p.lsidWidth) + assert(order.yoldLid.getWidth == p.lsidWidth) + assert(!order.elements.keySet.exists(name => + name.toLowerCase.contains("transaction") || + name.toLowerCase.contains("attempt") || + name.toLowerCase.contains("pipe") || + name.toLowerCase.contains("slot") || + name.toLowerCase.contains("lane"))) + + val wider = p.copy(maxMemoryRequestsPerInstruction = 7) + assert(new MemoryOrderMeta(wider).requestCount.getWidth == log2Ceil(7 + 1)) + assert(new DecodedMemoryControl(wider).requestCount.getWidth == + new MemoryOrderMeta(wider).requestCount.getWidth) + } + + test("PC buffer index and offset metadata stays generation qualified across OOO") { + val p = ParamProfiles.W4 + val indexOffset = new PcBufferIndexOffset(p) + val readAddress = new PcBufferReadAddress(p) + val prepared = new PcBufferD3Prepared(p) + val d3 = new D3RenameLane(p) + val dispatch = new DispatchTxn(p) + val commit = new CommitEntry(p) + + assert(indexOffset.elements.keySet == Set( + "valid", "pcBufferIndex", "pcOffset", "allocationEpoch")) + assert(indexOffset.pcBufferIndex.getWidth == + log2Ceil(p.ooo.pcBufferEntries)) + assert(indexOffset.pcOffset.getWidth == p.ooo.pcOffsetWidth) + assert(indexOffset.allocationEpoch.getWidth == + p.ooo.pcAllocationEpochWidth) + + assert(readAddress.elements.keySet == Set( + "valid", "stid", "pcBufferIndex", "allocationEpoch")) + assert(readAddress.stid.getWidth == math.max(1, log2Ceil(p.ooo.stidCount))) + assert(readAddress.pcBufferIndex.getWidth == + indexOffset.pcBufferIndex.getWidth) + assert(readAddress.allocationEpoch.getWidth == + indexOffset.allocationEpoch.getWidth) + + assert(prepared.count.getWidth == + log2Ceil(p.ooo.d3PrefixWidth + 1)) + assert(prepared.lanes.length == p.ooo.d3PrefixWidth) + assert(prepared.lanes.head.getClass == indexOffset.getClass) + assert(d3.pcBufferIndexOffset.getClass == indexOffset.getClass) + assert(dispatch.pcBufferIndexOffset.getClass == indexOffset.getClass) + assert(commit.pcBufferIndexOffset.getClass == indexOffset.getClass) + assert(commit.robGroupLast.getWidth == 1) + } + + test("resolve load lifecycle system and CMD transactions use exact canonical identities") { + val base = ParamProfiles.W4 + val p = base.copy( + ooo = base.ooo.copy(robGroupsPerStid = 32), + lsu = base.lsu.copy( + loadPipes = 8, + loadQueueEntries = 16, + loadReturnQueueEntries = 8), + lsidWidth = 37, + transactionIdWidth = 29, + ridGenerationWidth = 7, + residentGenerationWidth = 9, + memoryTransactionIdWidth = 41, + memoryTransactionGenerationWidth = 11, + memoryAttemptGenerationWidth = 13) + val resolve = new RobResolveTxn(p) + val issue = new LoadIssueTxn(p) + val reissue = new LoadReissueTxn(p) + val repick = new LoadRepickTxn(p) + val cancel = new LoadCancelTxn(p) + val noflush = new RobNoflushTxn(p) + val noflushReady = new RobNoflushReadyTxn(p) + val system = new SystemIssueTxn(p) + val cmd = new CmdIssueTxn(p) + + val expectedRobFields = Set( + "peId", "stid", "ridSlot", "ridGeneration", "memberIndex", + "residentGeneration", "bid", "brobGeneration") + val expectedMemoryFields = Set( + "rob", "transaction", "lsid", "attemptGeneration", "pipeId") + + assert(resolve.elements.keySet == Set( + "transactionId", "rob", "destinationValid", "destinationIndex", + "value", "trap")) + assert(resolve.rob.elements.keySet == expectedRobFields) + assert(resolve.destinationIndex.getWidth == + InterfaceWidth.index(p.maxDestinationOperands)) + assert(resolve.value.getWidth == p.dataWidth) + + def checkTransition(current: MemoryIdentity, next: MemoryIdentity): Unit = { + Seq(current, next).foreach { identity => + assert(identity.elements.keySet == expectedMemoryFields) + assert(identity.rob.elements.keySet == expectedRobFields) + assert(identity.transaction.elements.keySet == Set("value", "generation")) + assert(identity.rob.ridSlot.getWidth == p.ooo.ridSlotWidth) + assert(identity.rob.ridGeneration.getWidth == 7) + assert(identity.rob.residentGeneration.getWidth == 9) + assert(identity.transaction.value.getWidth == 41) + assert(identity.transaction.generation.getWidth == 11) + assert(identity.lsid.getWidth == 37) + assert(identity.attemptGeneration.getWidth == 13) + assert(identity.pipeId.getWidth == 3) + } + } + assert(issue.elements.keySet == Set( + "identity", "pc", "address", "sizeBytes", "signed", "destination", + "destinationRelativeIndex", "youngestStoreValid", "youngestStoreLsid", + "youngestStoreId")) + checkTransition(issue.identity, issue.identity) + checkTransition(reissue.currentIdentity, reissue.nextIdentity) + checkTransition(repick.currentIdentity, repick.nextIdentity) + val expectedStructuralWaitFields = Set( + "valid", "storeIndex", "storeIdValid", "storeIdValue", "storeIdWrap", + "storeLsidValid", "storeLsidValue", "storeLsidWrap", + "storeLsidFullValid", "storeLsidFull", "pc") + assert(reissue.elements.keySet == Set( + "allocationId", "currentIdentity", "nextIdentity", "address", + "structural", "waitStore")) + assert(repick.elements.keySet == Set( + "allocationId", "currentIdentity", "nextIdentity", "structural", + "waitStore")) + assert(reissue.waitStore.elements.keySet == expectedStructuralWaitFields) + assert(repick.waitStore.elements.keySet == expectedStructuralWaitFields) + Seq(reissue.waitStore, repick.waitStore).foreach { waitStore => + assert(waitStore.storeIndex.getWidth == + InterfaceWidth.index(p.lsu.storeQueueEntries)) + assert(waitStore.storeIdValue.getWidth == p.ooo.ridSlotWidth) + assert(waitStore.storeLsidValue.getWidth == p.ooo.ridSlotWidth) + assert(waitStore.storeLsidFull.getWidth == p.lsidWidth) + assert(waitStore.pc.getWidth == p.pcWidth) + } + assert(repick.allocationId.value.getWidth == 41) + assert(repick.allocationId.generation.getWidth == 11) + assert(reissue.address.getWidth == p.physicalAddressWidth) + assert(cancel.elements.keySet == Set("currentIdentity")) + assert(cancel.currentIdentity.elements.keySet == expectedMemoryFields) + checkTransition(cancel.currentIdentity, cancel.currentIdentity) + + Seq(noflush, noflushReady, system, cmd).foreach { transaction => + assert(transaction.elements.contains("instruction")) + assert(transaction.elements.contains("rob")) + } + assert(noflush.elements.keySet == Set("transactionId", "instruction", "rob")) + assert(noflushReady.elements.keySet == + Set("transactionId", "instruction", "rob")) + assert(system.opcode.getWidth == p.opcodeWidth) + assert(system.immediate.getWidth == p.dataWidth) + assert(cmd.opcode.getWidth == p.opcodeWidth) + assert(cmd.sourceValid.getWidth == p.maxSourceOperands) + assert(cmd.sourceValues.length == p.maxSourceOperands) + assert(cmd.sourceValues.forall(_.getWidth == p.dataWidth)) + } + + test("the public OOO D1 D2 slice contract lives with the TOP interfaces") { + profiles.foreach { case (width, p) => + val slice = new OOOD1D2IO(p) + val rename = new RENUD2D3IO(p) + assert(slice.fromCtu.bits.getClass == new D1Packet(p).getClass) + assert(slice.d2.bits.entries.length == width) + assert(slice.d2.bits.groups.length == width) + assert(rename.toD3.bits.entries.length == width) + assert(rename.toD3.bits.groups.length == width) + assert(slice.d2.bits.count.getWidth == log2Ceil(width + 1)) + assert(rename.toD3.bits.count.getWidth == log2Ceil(width + 1)) + assert(slice.d2.bits.entries.head.uop.rob.ridGeneration.getWidth == + p.ridGenerationWidth) + assert(rename.toD3.bits.entries.head.history.head.pGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(rename.toD3.bits.entries.head.history.head.previousPGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(rename.toD3.bits.entries.head.history.head.pMapQIndex.getWidth == + log2Ceil(p.ooo.gprMapQDepthPerStid)) + assert(rename.toD3.bits.entries.head.history.head.pMapQGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(rename.toD3.bits.entries.head.history.head.tMapQIndex.getWidth == + log2Ceil(p.ooo.tuMapQDepthPerStid)) + assert(rename.toD3.bits.entries.head.history.head.tMapQGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(rename.toD3.bits.entries.head.history.head.tGeneration.getWidth == + p.ooo.localSeqGenerationWidth) + assert(rename.toD3.bits.entries.head.uop.destinations.head.previousPGeneration.getWidth == + p.ooo.gprTagGenerationWidth) + assert(rename.toD3.bits.entries.head.tSeqBefore.generation.getWidth == + p.ooo.localSeqGenerationWidth) + assert(rename.toD3.bits.entries.head.tSeqBefore.tag.getWidth == + log2Ceil(p.ooo.tuMapQDepthPerStid)) + assert(slice.ridTailGeneration.head.getWidth == p.ridGenerationWidth) + assert(!slice.d2.bits.elements.contains("validMask")) + assert(!rename.toD3.bits.elements.contains("validMask")) + } + } + + test("OOO IEX and LSU boundaries preserve independent resource channels") { + val p = ParamProfiles.W4 + val oooIex = new OOOIEXIO(p) + val iexLsu = new IEXLSUIO(p) + + assert(oooIex.aluDispatch.length == p.iex.aluPipes) + assert(oooIex.bruDispatch.length == p.iex.bruPipes) + assert(oooIex.aguDispatch.length == p.iex.aguPipes) + assert(oooIex.storeDispatch.length == p.iex.stdPipes) + assert(oooIex.storeDispatch.head.bits.sta.getClass == + oooIex.storeDispatch.head.bits.std.getClass) + assert(oooIex.systemDispatch.length == p.iex.systemMulticycleQueues) + assert(oooIex.cmdDispatch.length == p.iex.cmdIssueQueues) + assert(oooIex.cmdDispatch.head.bits.getClass != + oooIex.systemDispatch.head.bits.getClass || + (oooIex.cmdDispatch ne oooIex.systemDispatch)) + + assert(oooIex.robNoflush.bits.getClass == new RobNoflushTxn(p).getClass) + assert(oooIex.robNoflushReady.bits.getClass == + new RobNoflushReadyTxn(p).getClass) + assert(oooIex.robResolve.length == p.widths.issueWidth) + assert(oooIex.robResolve.head.bits.getClass == new RobResolveTxn(p).getClass) + assert(oooIex.systemIssue.length == p.iex.systemMulticycleQueues) + assert(oooIex.systemIssue.head.bits.getClass == new SystemIssueTxn(p).getClass) + assert(oooIex.pcBufferReadAddress.length == p.ooo.pcReadPorts) + assert(oooIex.pcBufferReadAddress.head.getClass == + new PcBufferReadAddress(p).getClass) + assert(oooIex.pcBufferReadPcBase.length == p.ooo.pcReadPorts) + assert(oooIex.pcBufferReadPcBase.head.bits.getWidth == p.pcWidth) + + assert(iexLsu.loadAddress.length == 2) + assert(iexLsu.storeAddress.length == 2) + assert(iexLsu.storeData.length == 2) + assert(iexLsu.loadResult.length == 2) + assert(iexLsu.loadAddress.head.bits.getClass == new LoadIssueTxn(p).getClass) + assert(iexLsu.loadReissue.length == 2) + assert(iexLsu.loadRepick.length == 2) + assert(iexLsu.loadCancel.length == 2) + assert(iexLsu.loadReissue.head.bits.getClass == new LoadReissueTxn(p).getClass) + assert(iexLsu.loadRepick.head.bits.getClass == new LoadRepickTxn(p).getClass) + assert(iexLsu.loadCancel.head.bits.getClass == new LoadCancelTxn(p).getClass) + } + + test("box IOs share typed payloads and expose prepare then apply recovery") { + val p = ParamProfiles.W4 + val ifu = new IFUIO(p) + val ctu = new CTUIO(p) + val ooo = new OOOIO(p) + val iex = new IEXIO(p) + val lsu = new LSUIO(p) + val dtu = new DTUIO(p) + val top = new TOPIO(p) + + assert(ifu.toCtu.bits.getClass == ctu.fromIfu.bits.getClass) + assert(ctu.toOoo.bits.getClass == ooo.fromCtu.bits.getClass) + assert(ooo.iex.aluDispatch.head.bits.getClass == + iex.ooo.aluDispatch.head.bits.getClass) + assert(iex.lsu.loadAddress.head.bits.getClass == + lsu.iex.loadAddress.head.bits.getClass) + assert(iex.cmdIssue.bits.getClass == top.cmdIssue.bits.getClass) + assert(ooo.storeCommit.bits.getClass == lsu.storeCommit.bits.getClass) + assert(!top.elements.contains("storeCommit")) + assert(!top.elements.contains("storeClassify")) + + Seq( + ifu.recovery, + ctu.recovery, + iex.ooo.recovery, + lsu.recovery).foreach { recovery => + assert(recovery.prepare.bits.phase.getWidth > 0) + assert(recovery.prepared.bits.transactionId.getWidth == p.transactionIdWidth) + assert(recovery.apply.bits.transactionId.getWidth == p.transactionIdWidth) + assert(recovery.abort.bits.transactionId.getWidth == p.transactionIdWidth) + } + + assert(dtu.traceIn.bits.entries.length == p.dtu.traceWidth) + assert(top.instructionMemoryRequest.bits.identity.generation.getWidth == + p.memoryTransactionGenerationWidth) + assert(top.dataMemoryResponse.head.bits.identity.generation.getWidth == + p.memoryTransactionGenerationWidth) + assert(top.dataMemoryRequest.length == + p.lsu.loadPipes + p.lsu.storePipes) + assert(top.dataMemoryResponse.length == top.dataMemoryRequest.length) + assert(top.instructionMemoryRequest.bits.size.getWidth == MemorySize.getWidth) + assert(MemorySize.Bytes64.litValue == 6) + } + + test("a retained decoupled interface payload remains stable under backpressure") { + val p = ParamProfiles.W4 + val sv = ChiselStage.emitSystemVerilog(new InterfaceHoldProbe(p)) + + assert(sv.contains("module InterfaceHoldProbe")) + assert(sv.contains("previousPayload")) + assert(sv.contains("Assertion failed")) + } + + test("all box IO aggregates elaborate with their declared directions") { + profiles.foreach { case (width, p) => + val chirrtl = ChiselStage.emitCHIRRTL(new BoxIOElaborationProbe(p)) + val directionChirrtl = ChiselStage.emitCHIRRTL(new InterfaceDirectionProbe(p)) + assert(chirrtl.contains("module BoxIOElaborationProbe")) + assert(directionChirrtl.contains("module InterfaceDirectionProbe")) + assert(chirrtl.contains(s"UInt<${p.instructionWidth}>")) + assert(width == p.widths.decodeWidth) + } + } + + test("canonical public transaction names displace old transaction names") { + val scalaRoots = Seq( + repoRoot.resolve("chisel/src/main"), + repoRoot.resolve("chisel/src/test")) + val sources = scalaRoots.flatMap { root => + val paths = Files.walk(root) + try { + paths.iterator.asScala + .filter(path => Files.isRegularFile(path) && path.toString.endsWith(".scala")) + .map(path => Files.readString(path)) + .toSeq + } finally { + paths.close() + } + } + .mkString("\n") + + assert(!sources.contains("Completion" + "Txn")) + assert(!sources.contains("Load" + "RequestTxn")) + } +} diff --git a/docs/architecture/code_template_unit.md b/docs/architecture/code_template_unit.md index d2138964..0f124963 100644 --- a/docs/architecture/code_template_unit.md +++ b/docs/architecture/code_template_unit.md @@ -8,9 +8,9 @@ Canonical contract summary: `CodeTemplateUnit` expands template blocks (`FENTRY`, `FEXIT`, `FRET_RA`, `FRET_STK`) into an ordered canonical-child stream for the owning STID. It is -external to IFU and OOO. `OooCtuIngressBridge` claims one D1-classified raw -parent exactly once, retains an expansion lease, and inserts CTU children into -the OOO ingress before D2; CTU is not a post-D3 allocator or +external to IFU and OOO. The canonical `CTU` owner claims one I-F4 packet, +retains an expansion lease, and inserts CTU children through +`OOOD1D2Stage` before D2; CTU is not a post-D3 allocator or architectural-effect owner. Source: @@ -121,8 +121,8 @@ Canonical target integration is: 1. OOO D1 decodes only far enough to classify the fixed-64-bit template parent and retains the complete raw parent/prediction sideband. The production - `OooCtuIngressBridge` claims it after D1 and before D2. I-F4 predecode - remains limited to BSTART/BSTOP. + canonical `CTU` claims it before `OOOD1D2Stage`. I-F4 predecode remains + limited to BSTART/BSTOP. 2. CTU computes the exact ordered child recipe and resource envelope. The bridge assigns a retained `{PE,STID,parent,templateGroupId,generation}` ingress lease before the first @@ -141,12 +141,14 @@ Canonical target integration is: directly. 7. CTU backpressure is per STID; it must not stall unrelated STIDs. -The production OOO-side claim/lease/reinsertion and recovery boundary is now -implemented in `chisel/src/main/scala/linxcore/ooo/OooCtuIngressBridge.scala` -and composed by `OooIfuD1Ingress`. `OooS1GroupedRob` permits a zero-parent row -only for an exact nonfinal template continuation and requires the final child -to own the single parent. Focused UT/IT cover six-child multi-RID expansion, -stale/order rejects, STID isolation, and common recovery apply. +The production OOO-side claim/lease/reinsertion boundary is implemented by +`chisel/src/main/scala/linxcore/ctu/CTU.scala` and composed with +`OOOD1D2Stage`; its typed recovery target joins the canonical +`RecoveryControl` apply. Canonical `ROB` permits a zero-parent row only for an +exact nonfinal template continuation and requires the final child to own the +single parent. `CTUSpec`, `OOODecodeSpec`, and `CTUOOOIntegrationSpec` cover +six-child multi-RID expansion, stale/order rejects, STID isolation, and common +recovery apply. The external recipe engine and its production-top connection remain O9 work. Until that promotion, the legacy `LinxCoreBackend` integration uses CTU outputs @@ -160,7 +162,7 @@ to: Those direct-write/global-block paths and the current Template-D3 reservation modules are migration oracles only. They are forbidden from the production -composition once the external producer is connected to `OooCtuIngressBridge`. +composition once the external recipe producer is connected to `CTU`. Integration point: diff --git a/docs/architecture/diagrams/linxcore-core-architecture.drawio b/docs/architecture/diagrams/linxcore-core-architecture.drawio new file mode 100644 index 00000000..8a92d443 --- /dev/null +++ b/docs/architecture/diagrams/linxcore-core-architecture.drawio @@ -0,0 +1,427 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/architecture/diagrams/linxcore-core-architecture.graph.json b/docs/architecture/diagrams/linxcore-core-architecture.graph.json new file mode 100644 index 00000000..e22141d1 --- /dev/null +++ b/docs/architecture/diagrams/linxcore-core-architecture.graph.json @@ -0,0 +1,148 @@ +{ + "direction": "LR", + "nodes": [ + {"id": "imem", "label": "Instruction Memory / L2", "group": "Canonical full pyCircuit core/Memory", "groupLabel": "Memory interfaces", "style": "shape=cylinder3;whiteSpace=wrap;html=1;dashed=1;fillColor=#f5f5f5;strokeColor=#666666;", "width": 150, "height": 70}, + {"id": "dmem", "label": "Data Memory / L2", "group": "Canonical full pyCircuit core/Memory", "style": "shape=cylinder3;whiteSpace=wrap;html=1;dashed=1;fillColor=#f5f5f5;strokeColor=#666666;", "width": 150, "height": 70}, + + {"id": "if0", "label": "I-F0\nPC + request", "group": "Canonical full pyCircuit core/Frontend", "groupLabel": "Frontend: decoupled I-SIDE and B-SIDE", "width": 130}, + {"id": "if1", "label": "I-F1\nITLB + L1I launch", "group": "Canonical full pyCircuit core/Frontend", "width": 150}, + {"id": "if2", "label": "I-F2\ntranslate/cache join", "group": "Canonical full pyCircuit core/Frontend", "width": 160}, + {"id": "if3", "label": "I-F3\nline align + carry", "group": "Canonical full pyCircuit core/Frontend", "width": 150}, + {"id": "if4", "label": "I-F4\nassemble + predecode", "group": "Canonical full pyCircuit core/Frontend", "width": 160}, + {"id": "ib", "label": "Instruction Buffer\nper STID", "group": "Canonical full pyCircuit core/Frontend", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;", "width": 150}, + {"id": "bf0", "label": "B-F0\nNLP + history", "group": "Canonical full pyCircuit core/Frontend", "width": 130}, + {"id": "bf1", "label": "B-F1\nuBTB + RAS", "group": "Canonical full pyCircuit core/Frontend", "width": 130}, + {"id": "bf2", "label": "B-F2\nBTB + BIM", "group": "Canonical full pyCircuit core/Frontend", "width": 130}, + {"id": "bf3", "label": "B-F3\nTAGE + IBTB", "group": "Canonical full pyCircuit core/Frontend", "width": 130}, + {"id": "bf4", "label": "B-F4\nfinal prediction", "group": "Canonical full pyCircuit core/Frontend", "width": 140}, + + {"id": "d1", "label": "D1\n4-wide full decode", "group": "Canonical full pyCircuit core/Decode and OOO", "groupLabel": "Decode, rename, dispatch, issue and execute", "width": 150}, + {"id": "d2", "label": "D2\nboundaries + demand", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 150}, + {"id": "d3", "label": "D3 / Rename\natomic admission", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 150}, + {"id": "s1", "label": "S1\nspeculative buffer", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 145}, + {"id": "iq", "label": "S2 / S3-IQ\nallocate + resident", "group": "Canonical full pyCircuit core/Decode and OOO", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;", "width": 160}, + {"id": "pick", "label": "P0 / P1\npreselect + pick", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 145}, + {"id": "issue", "label": "I1 / I2\nRF read + confirm", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 150}, + {"id": "iex", "label": "IEX\nALU / BRU / AGU", "group": "Canonical full pyCircuit core/Decode and OOO", "width": 150}, + + {"id": "rob", "label": "ROB\nordered uop state", "group": "Canonical full pyCircuit core/Commit and Recovery", "groupLabel": "Commit, block retirement and recovery", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;", "width": 150}, + {"id": "retire", "label": "R0..R4\nresolve + retire", "group": "Canonical full pyCircuit core/Commit and Recovery", "width": 145}, + {"id": "commit", "label": "Commit / CMT", "group": "Canonical full pyCircuit core/Commit and Recovery", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;", "width": 140}, + {"id": "flush", "label": "Flush / FLS\nrestart + prune", "group": "Canonical full pyCircuit core/Commit and Recovery", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;", "width": 145}, + {"id": "pcrenu", "label": "PC Buffer + RENU\ncheckpoint repair", "group": "Canonical full pyCircuit core/Commit and Recovery", "width": 160}, + + {"id": "liq", "label": "LIQ\nload inflight / replay", "group": "Canonical full pyCircuit core/LSU", "groupLabel": "LSU and memory ordering (current integration)", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#e1d5e7;strokeColor=#9673a6;", "width": 160}, + {"id": "lhq", "label": "LHQ\nresolved-load conflicts", "group": "Canonical full pyCircuit core/LSU", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#e1d5e7;strokeColor=#9673a6;", "width": 165}, + {"id": "mdb", "label": "MDB\nstore-set predictor", "group": "Canonical full pyCircuit core/LSU", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#e1d5e7;strokeColor=#9673a6;", "width": 155}, + {"id": "stq", "label": "STQ\nspeculative stores", "group": "Canonical full pyCircuit core/LSU", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#e1d5e7;strokeColor=#9673a6;", "width": 150}, + {"id": "l1d", "label": "L1D\ncache boundary", "group": "Canonical full pyCircuit core/LSU", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;", "width": 140}, + {"id": "scb", "label": "SCB + Store Drain\ncommitted stores", "group": "Canonical full pyCircuit core/LSU", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#e1d5e7;strokeColor=#9673a6;", "width": 165}, + + {"id": "bisq", "label": "BISQ\nblock issue queue", "group": "Canonical full pyCircuit core/Block Fabric", "groupLabel": "Block fabric, BID ownership and heterogeneous engines", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;", "width": 150}, + {"id": "brenu", "label": "BRENU\nblock rename metadata", "group": "Canonical full pyCircuit core/Block Fabric", "width": 160}, + {"id": "bctrl", "label": "BCTRL\ncommand routing", "group": "Canonical full pyCircuit core/Block Fabric", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#ffe6cc;strokeColor=#d79b00;", "width": 150}, + {"id": "brob", "label": "BROB\nBID allocation + retire", "group": "Canonical full pyCircuit core/Block Fabric", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;", "width": 165}, + {"id": "tmu", "label": "TMU\nNoC + tile RF", "group": "Canonical full pyCircuit core/Block Fabric", "width": 140}, + {"id": "vec", "label": "VEC", "group": "Canonical full pyCircuit core/Engines", "groupLabel": "Block engines", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#e1d5e7;strokeColor=#9673a6;"}, + {"id": "cube", "label": "CUBE", "group": "Canonical full pyCircuit core/Engines", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#e1d5e7;strokeColor=#9673a6;"}, + {"id": "tma", "label": "TMA", "group": "Canonical full pyCircuit core/Engines", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#e1d5e7;strokeColor=#9673a6;"}, + {"id": "tau", "label": "TAU", "group": "Canonical full pyCircuit core/Engines", "style": "rounded=1;whiteSpace=wrap;html=1;fillColor=#e1d5e7;strokeColor=#9673a6;"}, + + {"id": "probes", "label": "Commit / Block / Pipeview Probes", "group": "Canonical full pyCircuit core/Observability", "groupLabel": "Observability only (not architectural owners)", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#f5f5f5;strokeColor=#666666;", "width": 190}, + {"id": "trace", "label": "LinxTrace / Debug", "group": "Canonical full pyCircuit core/Observability", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#f5f5f5;strokeColor=#666666;", "width": 150}, + + {"id": "cifu", "label": "IFU", "group": "Reduced typed composition lane (not the full core)", "groupLabel": "Reduced typed composition lane (not the full core)"}, + {"id": "cctu", "label": "CTU", "group": "Reduced typed composition lane (not the full core)"}, + {"id": "cooo", "label": "OOO", "group": "Reduced typed composition lane (not the full core)"}, + {"id": "ciex", "label": "IEX", "group": "Reduced typed composition lane (not the full core)"}, + {"id": "clsu", "label": "LSU", "group": "Reduced typed composition lane (not the full core)"}, + {"id": "cdtu", "label": "DTU / Trace", "group": "Reduced typed composition lane (not the full core)", "style": "rounded=1;whiteSpace=wrap;html=1;dashed=1;fillColor=#f5f5f5;strokeColor=#666666;", "width": 140} + ], + "edges": [ + {"source": "imem", "target": "if1", "label": "fetch response"}, + {"source": "if0", "target": "if1"}, + {"source": "if1", "target": "if2"}, + {"source": "if2", "target": "if3"}, + {"source": "if3", "target": "if4"}, + {"source": "if4", "target": "ib", "label": "fixed 64-bit entries"}, + {"source": "ib", "target": "d1", "label": "up to 4 lanes"}, + {"source": "if0", "target": "bf0", "label": "request + history"}, + {"source": "bf0", "target": "bf1"}, + {"source": "bf1", "target": "bf2"}, + {"source": "bf2", "target": "bf3"}, + {"source": "bf3", "target": "bf4"}, + {"source": "bf4", "target": "d1", "label": "sealed prediction record"}, + {"source": "bf4", "target": "if0", "label": "RECOVERY: predictor correction"}, + + {"source": "d1", "target": "d2"}, + {"source": "d2", "target": "d3"}, + {"source": "d3", "target": "s1", "label": "renamed uops"}, + {"source": "s1", "target": "iq"}, + {"source": "iq", "target": "pick"}, + {"source": "pick", "target": "issue"}, + {"source": "issue", "target": "iex"}, + {"source": "d3", "target": "rob", "label": "allocate + identity"}, + {"source": "iex", "target": "rob", "label": "resolve / writeback"}, + {"source": "rob", "target": "retire"}, + {"source": "retire", "target": "commit", "label": "R2 publish"}, + {"source": "retire", "target": "flush", "label": "RECOVERY: R2 flush"}, + {"source": "commit", "target": "pcrenu", "label": "architectural maps"}, + {"source": "flush", "target": "pcrenu", "label": "RECOVERY: rollback"}, + {"source": "pcrenu", "target": "if0", "label": "RECOVERY: restart PC"}, + {"source": "pcrenu", "target": "d3", "label": "RECOVERY: rename restore"}, + {"source": "flush", "target": "iq", "label": "RECOVERY: prune"}, + + {"source": "iex", "target": "liq", "label": "loads"}, + {"source": "iex", "target": "stq", "label": "stores"}, + {"source": "liq", "target": "l1d", "label": "load request"}, + {"source": "l1d", "target": "liq", "label": "data / miss"}, + {"source": "liq", "target": "lhq", "label": "resolved load"}, + {"source": "lhq", "target": "mdb", "label": "conflict"}, + {"source": "mdb", "target": "liq", "label": "RECOVERY: replay / wait"}, + {"source": "liq", "target": "rob", "label": "load completion"}, + {"source": "commit", "target": "stq", "label": "store commit"}, + {"source": "stq", "target": "scb", "label": "committed fragments"}, + {"source": "scb", "target": "l1d", "label": "coalesced write"}, + {"source": "l1d", "target": "dmem", "label": "load / store traffic"}, + {"source": "flush", "target": "liq", "label": "RECOVERY: LSU prune"}, + {"source": "flush", "target": "stq", "label": "RECOVERY: store prune"}, + + {"source": "d3", "target": "bisq", "label": "block command"}, + {"source": "d3", "target": "brenu", "label": "STID / BID metadata"}, + {"source": "brenu", "target": "bisq", "label": "renamed command"}, + {"source": "bisq", "target": "bctrl", "label": "head command"}, + {"source": "brob", "target": "d3", "label": "BID allocation"}, + {"source": "bctrl", "target": "vec", "label": "issue"}, + {"source": "bctrl", "target": "cube", "label": "issue"}, + {"source": "bctrl", "target": "tma", "label": "issue"}, + {"source": "bctrl", "target": "tau", "label": "issue"}, + {"source": "bctrl", "target": "tmu", "label": "tile / NoC command"}, + {"source": "tmu", "target": "tma", "label": "tile operands"}, + {"source": "tmu", "target": "cube", "label": "tile operands"}, + {"source": "vec", "target": "brob", "label": "done / exception"}, + {"source": "cube", "target": "brob", "label": "done / exception"}, + {"source": "tma", "target": "brob", "label": "done / exception"}, + {"source": "tau", "target": "brob", "label": "done / exception"}, + {"source": "brob", "target": "rob", "label": "block completion"}, + {"source": "flush", "target": "brob", "label": "RECOVERY: STID-qualified kill set"}, + {"source": "flush", "target": "bctrl", "label": "RECOVERY: cancel / redirect"}, + + {"source": "rob", "target": "probes", "label": "commit state"}, + {"source": "brob", "target": "probes", "label": "block state"}, + {"source": "iex", "target": "probes", "label": "pipeview"}, + {"source": "probes", "target": "trace", "label": "observability"}, + + {"source": "cifu", "target": "cctu"}, + {"source": "cctu", "target": "cooo"}, + {"source": "cooo", "target": "ciex"}, + {"source": "ciex", "target": "clsu"}, + {"source": "cooo", "target": "cifu", "label": "RECOVERY: typed recovery"}, + {"source": "cooo", "target": "cctu", "label": "RECOVERY: typed recovery"}, + {"source": "cooo", "target": "clsu", "label": "RECOVERY: typed recovery"}, + {"source": "cifu", "target": "cdtu", "label": "trace"}, + {"source": "cctu", "target": "cdtu", "label": "trace"}, + {"source": "cooo", "target": "cdtu", "label": "commit + trace"}, + {"source": "ciex", "target": "cdtu", "label": "trace"}, + {"source": "clsu", "target": "cdtu", "label": "trace"} + ] +} diff --git a/docs/architecture/diagrams/linxcore-core-architecture.png b/docs/architecture/diagrams/linxcore-core-architecture.png new file mode 100644 index 00000000..bf471d61 Binary files /dev/null and b/docs/architecture/diagrams/linxcore-core-architecture.png differ diff --git a/docs/archive/v0.3/README.md b/docs/archive/v0.3/README.md index e8b71e9a..197daab5 100644 --- a/docs/archive/v0.3/README.md +++ b/docs/archive/v0.3/README.md @@ -3,6 +3,6 @@ This directory preserves the retired v0.3 LinxCore uop-classification snapshot. It is non-normative and intentionally contains historical instruction names. -The active v0.56.5 classification is owned by the LinxISA superproject at -`isa/v0.56/uop_classification_v0.56/`. Do not copy identities or encodings from -this archive into current decoders, generators, or documentation. +The active classification is owned by the LinxISA superproject at +`isa/v0.57/uop_classification_v0.57/`. Do not copy identities or encodings from +this archive into current decoders, generators, or documentation. \ No newline at end of file diff --git a/docs/chisel/README.md b/docs/chisel/README.md index 3abb5e25..5a418d00 100644 --- a/docs/chisel/README.md +++ b/docs/chisel/README.md @@ -33,22 +33,32 @@ Current phase: - Phase 0A: model notes - Phase 0B: ROB and cross-check infrastructure first - Phase 1: interface schema and type-system monitors in progress -- OOO O0/O1: the normative D2-virtual/D3-reserve/S1-publish - contract, independent `OooParams`, exact grouped/member identity bundles, - and four-thread retained stage shell are implemented. Decode expansion, - fusion, grouped ROB/BROB, RENU, dispatch, recovery, CTU, and benchmark - promotion remain subsequent packets. +- OOO O0-O7: parameterized raw ingress and decode/fusion, grouped ROB/BROB/PC, + P/T/U RENU, dispatch/IEX residency, fast resolve/non-flush, exact global + recovery, and the OOO-side CTU lease/reinsertion contract are implemented + with focused UT/IT evidence. O8 physical banking/timing closure remains + active. O9 external CTU recipe-engine/top wiring, legacy reduced-owner + removal, and production workload promotion remain open. The authoritative + packet handoff is [integrated-development-flow.md](integrated-development-flow.md). - IFU implementation: `LinxCoreIfu` composes independent I-SIDE and B-SIDE owners, the final prediction join, fixed-width Instruction Buffer, and four-wide D1. A generated-RTL hot-cache gate proves sustained four-wide - output; natural CoreMark/Dhrystone run through the promoted owner graph. + output; recorded natural CoreMark/Dhrystone evidence ran through the promoted + owner graph. The 2026-07-30 replay-LIQ LRET integration repair restores the + current-head `LinxCoreBenchmarkAutonomousTopSpec` gate to 15/15 and the live + trace-top gate to 44/44 by carrying the canonical LIQ row lease, exact load + attempt, and terminal data-or-fault result through the compatibility top. + This is elaboration/no-regression evidence for the hybrid workload graph; + it does not promote that graph to the final production owner. Four-row atomic D2/D3 admission, complete predictor policy, SoC PTW/L1I binding, and lower-memory error termination remain open. - Phase 5 preparation: integrated ROB/CMT status vocabulary, entry-bank skeleton, flush-prune selector, entry-bank flush application, and native row BID/RID sidecars started -- Backend/recovery integration: dispatch/BROB-to-ROB allocation bridge, - full-BID recovery handoff, and registered cleanup intent started +- Backend/recovery integration: O7 joins ROB/D3/BROB/PC, P/T/U rename, + dispatch/IEX/fast residency, frontend acknowledgement, and CTU leases under + one retained prepare/apply/rebuild transaction. Production-top promotion + remains gated on O8/O9 closure. - LSU recovery and drain integration: first STQ flush-prune consumer, state bank, store-commit queue, and memory-side commit drain boundary started - Phase 1 top shell: `LinxCoreTop` wraps the monitored reduced ROB so top @@ -328,7 +338,7 @@ bash tools/chisel/run_chisel_tests.sh --only CommitTraceMonitor bash tools/chisel/run_chisel_tests.sh --only BROB bash tools/chisel/run_chisel_tests.sh --only FlushControl bash tools/chisel/run_chisel_reduced_rob_xcheck.sh -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh SBT_OPTS='-Xms512m -Xmx4g -XX:+UseG1GC' bash tools/chisel/run_chisel_tests.sh --all bash tools/chisel/emit_verilog.sh bash tools/chisel/run_chisel_verilator_lint.sh diff --git a/docs/chisel/agent-loop.md b/docs/chisel/agent-loop.md index bb869e5c..37f97963 100644 --- a/docs/chisel/agent-loop.md +++ b/docs/chisel/agent-loop.md @@ -2074,6 +2074,21 @@ next STA/STD arbitration packet. | R758 | I0.15b exact OOO load-attempt / canonical LIQ binding | Starting from static-top closure commit `50dc00c3`, `LoadAttemptIdentity` defines a producer-qualified, OOO-compatible semantic token without making LSU depend on `OooParams`: PE/STID, native BID/BROB generation, RID slot/generation, member index/resident generation, and attempt generation are retained explicitly. `LoadAttemptIdentity.requireBridgeFits` proves at elaboration that every native field fits before zero-extension and rejects truncating adapters. `LoadInflightQueue` co-allocates the token with one slot-plus-wrap row and accepts a rebind only for the exact resident lease, exact current producer/generation, and consecutive next generation while the row is nonterminal and not launching. Hard/precise flush, stale or reused rows, producer mismatch, skipped generation, and lifecycle races reject without mutation. The token is a sidecar, never an LSU ordering key, and now survives LIQ, LHQ/ResolveQ, LRET formatting/queueing, W1/W2 backpressure, `robLookupAttempt`, and terminal completion. Dynamic unequal-capacity tests use `LIQ=4`, `ROB=8`, `STQ=4`, `LSID=40` and cover production width-fit/rejection, co-allocation, exact rebind including generation wrap, stale/skipped/race/flush rejection, natural same-slot/opposite-wrap reuse rejection, formatter invalidation, and W1/W2 retention. Focused load-attempt 7/7, LIQ 16/16, return-pipeline, load-path, ScalarLSU, and final build gates pass. The live OOO adapter, removal of duplicate `OooIexLoadUnit` request/retry/result residency, attempt-qualified asynchronous E3/E4/refill returns, common OOO/LIQ/LRET recovery, physical memory system, timing, and workloads remain I0.15c/d gaps. Closeout: `skill-evolve: no-update` because producer-qualified attempts, single-owner replay/return state, no truncation, unequal capacities, and exact recovery precedence are already normative in the installed skill. | | R759 | I0.15c-a three-AGU typed LIQ allocation seam | Starting from exact-attempt commit `6d3131ca`, `OooIexLoadLiqAllocAdapter` defines the first concrete production-width OOO-to-LSU bridge. Three retained AGU inputs are fairly serialized into the current single canonical LIQ allocation port without adding request residency. Every fire maps the complete `RobMemberKey`, non-rewinding allocation-serial attempt generation, full LSID, exact youngest-older-store full LSID, exact parent PC, address/size/sign, new and displaced generation-qualified PTags, GPR destination, and physical return-pipe lane; elaboration proves native fields, RID/BID projections, tags, scope, PC, and LSID fit before assignment. Hard flush or an exact recovery kill performs a destructive producer handshake while allocation is masked, so an AGU-retained pre-recovery request cannot allocate after the pulse; malformed non-killed traffic stays backpressured and fail-closed. All scalar loads now request parent PC even for base/index addressing because MDB/store-set/replay state cannot use a placeholder PC. `OooMemoryIdState` also retains the exact youngest-store unified LSID because a type-local store counter cannot reconstruct it after interleaved loads; allocator, ROB snapshots, and recovery carry that tail automatically. Same-BID replay wake ordering now compares full LSIDs and reports missing or half-range-ambiguous authority instead of accepting a projected alias. Speculative wakeup remains disabled at allocation until I0.15c-b composes exact wake/cancel generations. Unequal-capacity adapter UT (`LIQ=4`, `ROB=8`, `STQ=4`, `LSID=40`) passes 4/4; replay-wakeup passes 12/12; memory-order allocation passes 6/6; P1 bridge 5/5; AGU 3/3; P1 lane 3/3; LIQ 16/16; focused IEX retained-stage/old-PTag propagation 1/1; exact grouped-ROB survivor-tail recovery 1/1; load-forward pipeline 9/9; store forwarding 8/8; composed scalar load path 5/5; ScalarLSU 4/4; and the Chisel build plus diff check pass. The grouped-ROB fault suite also passes 2/2; the broad wildcard run was intentionally bounded after it moved into unrelated bank-boundary cases. Live `ScalarLSULoadPath` allocation/launch/return composition, STQ result connection, common recovery, terminal metadata, exact speculative wake/cancel composition, and deletion of duplicate `OooIexLoadUnit` residency remain I0.15c-b. Closeout: `skill-evolve: no-update` because exact cross-domain identity, full serial order, parent-PC ownership, no truncation, recovery fencing, and single canonical residency are already normative in the installed skill. | +| R760 | I0.15c-b1 atomic canonical load ownership boundary | Starting from three-AGU seam commit `419b2b66` and exact-terminal commit `e96cea5b`, `OooIexCanonicalLoadOwnership` composes the non-resident three-lane adapter with the metadata-only terminal sidecar. Canonical LIQ allocation and sidecar installation share one ready/valid fire and exact slot-plus-wrap lease; replay rebind likewise requires simultaneous canonical LIQ and OOO metadata acceptance. Exact canonical completion retains data or fault under terminal backpressure and releases the sidecar only on the same W2 fire. Recovery prepare now independently fences the adapter without acknowledging any producer, the sidecar validates and reports its exact kill mask, and only an externally authorized common fire destructively drains killed AGUs and applies metadata removal. The ownership graph carries no address/miss/refill/retry/data residency and emitted SystemVerilog contains no `OooIexLoadUnit`. Unequal-capacity IT uses `LIQ=4`, `ROB=8`, `STQ=4`, `LSID=40`; ownership passes 5/5, allocation adapter 5/5, and terminal metadata 3/3. Production execution-cluster cutover, real LIQ launch-qualified speculative wakeup/cancel, direct three-pipe STQ result connection, deletion of the migration tracker, physical memory system, timing, and workloads remain c-b2/d gaps. Closeout: `skill-evolve: no-update` because atomic cross-owner allocation/rebind, mutation-free prepare, common-fire-only apply, exact terminal release, and no duplicate lifecycle state are already normative in the installed `linx-core` skill. | + +| R761 | I0.15c-b2a launch-qualified load speculation policy | Starting from canonical ownership commit `6f63cd91`, the existing metadata sidecar now retains the accepted physical AGU lane beside each exact LIQ lease and attempt. A canonical `{loadId,attempt}` launch emits speculative wakeup only for the exact resident generation; allocation never wakes a dependent. Exact rebind emits old-generation cancel on that lane and a later exact launch wakes the new generation. Ordinary terminal data exposes lane-qualified W1 bypass while precise fault exposes no bypass and emits cancel only on terminal fire. If fault completion and an unrelated rebind target the same physical lane, fault cancel wins and rebind is backpressured one cycle, so neither cancellation is lost. No address, miss, refill, replay, or data residency is added. Unequal-capacity ownership IT passes 7/7 including stale launch rejection, rebind cancel, fault cancel, bypass, terminal backpressure, same-lane collision serialization, common recovery, and generated graph proof; terminal metadata remains 3/3. Production cluster cutover and deletion of `OooIexLoadUnit`, direct three-pipe STQ result composition, asynchronous-return attempt qualification, physical memory system, timing, and workloads remain c-b2b/d. Closeout: `skill-evolve: no-update` because launch-qualified speculative readiness, cancel symmetry, lane collision serialization, exact bypass identity, and single lifecycle ownership are already normative in the installed skill. | + +| R762 | I0.15c-b2b canonical execution-cluster load cutover | Starting from launch-policy commit `808990b8`, `OooIexExecutionCluster` replaces its three independent migration trackers with one `OooIexCanonicalLoadOwnership` shared by all three AGUs. The typed canonical allocation/load-ID, exact rebind, attempt-launch, LIQ-rebind, and terminal-completion boundary propagates through `OooIexExecutionPipeline`, `OooIexExecutionStorePipeline`, and the closed `OooO3IexStorePipeline`; the load metadata owner joins the execution common recovery prepare/fire and cluster quiescence. Canonical completion demultiplexes by the retained accepted AGU lane into the existing atomic terminal fabric, while speculative wakeup, W1 bypass, and cancel retain lane-qualified exact identity. A fault cancel is now a one-shot policy event independent of W2 ready and is remembered in the sidecar until terminal fire, removing a terminal-ready/cancel combinational loop without duplicating result residency. Dynamic cluster IT proves a real `agu2-lda` E1 transaction through address generation, canonical LIQ allocation, exact launch wakeup, W1 bypass, P-file write, and ROB completion; generated SystemVerilog proves exactly one canonical owner and no migration module. The obsolete tracker source, UT, module page, abstract memory request/response types, track state, and `iexLoadTrackEntries` parameter are deleted after replacement gates turn green. Focused cluster passes 4/4 and canonical ownership passes 7/7. Direct live `ScalarLSULoadPath` plus three STQ-result composition, scalar-LSU common recovery, asynchronous-return attempt qualification, physical memory system, timing, and workloads remain I0.15c-b3/d. Closeout: `skill-evolve: no-update` because the installed `linx-core` skill already requires sole canonical load residency, exact launch/cancel symmetry, common recovery, and deletion of duplicate lifecycle owners. | +| R763 | I0.15c-b3a attempt-qualified STQ asynchronous result identity | Starting from canonical cluster cutover commit `d4b71a31`, every `STQLoadForwardQuery` now carries the exact canonical LIQ slot-plus-wrap lease, complete producer-qualified load-attempt generation, and physical return-pipe index beside its ordering and source-data fields. Each replicated STQ pipe rejects an invalid/non-representable row lease, malformed attempt, attempt/STID mismatch, or request/pipe mismatch before it can look like a normal E3 result. `STQLoadForwardResultPipeline` registers only the minimal `{loadId, attempt, returnPipeIndex}` sidecar in lockstep with the common E3/E4 data/result stages, avoiding a duplicate 64-byte baseline register while preserving exact identity through bubbles and back-to-back responses and clearing stage validity on recovery flush. The STQ still does not own LIQ capacity or mutate load lifecycle state; the canonical LIQ owner must revalidate `{loadId, attempt}` when applying E4. Directed result tests pass 6/6, STQ query tests pass 13/13 including the new fail-closed cases, and canonical store-fabric IT passes 6/6. Direct launch-to-query wiring, E4-to-LIQ mutation, scalar-LSU two-phase recovery, physical translation/cache/coherence, timing, and workloads remain I0.15c-b3b/c/d gaps. Closeout: `skill-evolve: no-update` because exact asynchronous-return identity, physical pipe qualification, recovery-aligned retention, and fail-closed cross-owner validation are already normative in the installed `linx-core` skill. | +| R764 | I0.15c-b3b exact canonical LIQ forwarding-result apply seam | Starting from attempt-qualified STQ commit `9eda1980`, `LoadInflightQueue` now has one common E4 row-mutation path for both compatibility and production forwarding results. Production `useExternalForwardResult` mode accepts a complete classified result only when the canonical slot-plus-wrap lease, producer-qualified attempt, physical return pipe, resident row, and one accepted-launch `forwardPending` lifecycle all match with no recovery or competing row mutation. The first exact result clears `forwardPending`; stale row reuse, stale attempts, cross-pipe returns, pick-only rows, duplicate returns, and conflicts reject without mutation. Compatibility mode captures the same identity at launch and feeds the old local pipeline through this common apply path. Compile-time production mode elaborates without `LoadForwardPipeline` or `LoadStoreForwarding`, proving that the abstract duplicate STQ CAM is not resident behind the new seam. Dynamic attempt/LIQ UT passes 9/9, including exact apply, stale/wrap/attempt/pipe rejection, duplicate rejection, and generated-graph proof; LIQ reference/elaboration passes 16/16, ScalarLSULoadPath 5/5, and ScalarLSU 4/4. Direct three-pipe launch/query/response composition, retained producer retry across apply backpressure, scalar-LSU two-phase recovery, physical memory, timing, and workloads remain I0.15c-b3c/d gaps. Closeout: `skill-evolve: no-update` because the installed `linx-core` skill already requires sole canonical lifecycle ownership, exact asynchronous-return matching, duplicate rejection, and deletion of compatibility residency from production graphs. | +| R765 | I0.15c-b3c1 lossless forwarding-result sink policy | Starting from exact LIQ apply commit `60cba6ed`, `LoadInflightQueue` now separates permanent stale results from retryable owner conflicts. Malformed/stale row leases, attempts, pipe identities, absent pending launches, and duplicates are terminal permanent rejections; hard/typed recovery and competing exact-row clear/MDB/replay/refill writers request retry without mutation. `LoadForwardResultRetainer` is a bounded complete-payload FIFO whose head remains stable across retry and drains only on exact LIQ acceptance or permanent stale rejection. Hard flush clears transport; typed precise recovery preserves the head until post-recovery identity decides it. Superpowers TDD first produced the expected missing-interface/module compile failure, then the new retainer suite passed 1/1 and attempt/LIQ passed 10/10. Three-pipe query/response wiring, E3/E4 ingress credit, structural hard-block ownership, common scalar-LSU recovery, physical memory, timing, and workloads remain I0.15c-b3c2/d gaps. Closeout: `skill-evolve: no-update` because typed transient-versus-permanent producer decisions and retained asynchronous result ownership are already required by the installed `linx-core` contracts. | +| R766 | I0.15c-b3c2 live three-pipe scalar-load forwarding composition | Starting from retained-result commit `e55dfbea`, production `ScalarLSULoadPath(useExternalStqForwarding=true)` replaces its compatibility E2 CAM with exactly three retained one-entry STQ query queues, three retained response lanes, direct `STQLoadForwardResultPipeline`, bounded normal-result reservations, and `LoadForwardResultRetainer`. Canonical LIQ launch and selected query enqueue are one atomic local transaction; the external Decoupled query then holds valid and its full load/attempt/pipe/source payload across backpressure. Normal responses accept only with reserved E3/E4/FIFO capacity, while structural uncertainty remains independently retained on `hardBlock`. Exact E4 results preserve split SCB/STQ-return evidence and drain only on LIQ acceptance or permanent stale rejection. Hard flush clears transport; typed precise recovery fences external query/response fire, preserves owned queries and E3/E4/results, and recomputes return/miss reservations from exact surviving LIQ rows. A native BID that does not fit the migration STQ ordering projection blocks launch and raises `protocolError` instead of aliasing. Owned query/result transport participates in load-path quiescence. Production elaboration proves no `LoadForwardPipeline` or `LoadStoreForwarding` instance. Superpowers v6.2.0 TDD first made the backpressure IT fail against the ready-dependent producer, then passed after query retention. Focused gates pass: integration 5/5 including hard clear, precise query/E4 survival, and BID fail-closed behavior; load path 6/6, result pipeline 7/7, attempt binding 10/10, LIQ 16/16, STQ pipeline 13/13, store fabric 6/6, execution/store IT 4/4, ScalarLSU aggregate 32/32, and the Chisel build. The closed OOO/store-fabric/scalar-LSU wrapper, common recovery apply/readiness, hard-block policy, final BID/BROB ordering adapter, physical SCB/DTLB/PMP/PMA/coherence, timing, and workloads remain open. Closeout: `skill-evolve: no-update` because retained Decoupled producers, capacity-before-acceptance, exact asynchronous identity, split recovery semantics, and honest migration boundaries are already normative in the installed skill. | +| R767 | I0.15c-b3c3a focused canonical OOO/LSU load-store closure | Starting from live-forwarding commit `6421670c`, `OooIexScalarLoadStorePath` composes exactly one canonical OOO load metadata owner, one production `ScalarLSULoadPath`, and one canonical `OooIexStoreStqFabric`. Three private query/response lanes now carry an accepted AGU load through LIQ, live STQ forwarding, E3/E4, LRET/W1/W2, and one atomic OOO result; the complete ROB lookup identity is exported before return validation. `lateStaCandidate/lateStaPermit` expose the prospective MDB side effect before canonical STQ address mutation, retain the store-pipeline fill while MDB is unavailable, and commit both effects together. MDB protocol diagnostics now distinguish an uncommitted waiting candidate from an illegal commit without readiness. Recovery presents both grouped-member and LSU-native views, proves identical per-resident-LIQ kill masks, fences wrapper ingress, requires two consecutive empty snapshots for every non-LIQ recovery consumer, retains prepared authorization and bit-stable inputs, and applies only on common fire; live post-LIQ state rejects until the final all-owner projection exists. Superpowers TDD observed expected missing-module/ROB-interface/late-STA-interface failures, a same-scope kill mismatch, MDB false-positive protocol error, live post-LIQ recovery acceptance, and a combinational recovery cycle before each minimal repair. Focused gates pass new closure 5/5, store fabric 7/7, MDB 8/8, execution/store IT 4/4, forwarding 5/5, canonical ownership 7/7, load path 6/6, execution structure 1/1, O3 structure 1/1, Chisel build, and diff check. The full execution/O3 installation, hard-block consumer, final BID/BROB/all-LSU recovery adapter, physical SCB/DTLB/PMP/PMA/device/coherence, timing, and workloads remain open. Closeout: `skill-evolve: no-update` because single canonical residency, capacity-before-side-effect, retained prepare/fire, exact dual-view recovery, and fail-closed unsupported state are already normative in `linx-core`. | +| R768 | I0.15c-b3c3b production execution/O3 scalar-load installation | Starting from focused closure commit `71c6dc19`, `OooIexExecutionStorePipeline` installs one `OooIexScalarLoadStorePath` against the execution cluster's existing `OooIexCanonicalLoadOwnership` and the wrapper's existing `OooIexStoreStqFabric`. The attachment now owns only LIQ/L1D/MDB/LRET; three forwarding lanes, STQ snapshots, and prospective late-STA MDB admission are private, while the O3 boundary exposes only physical memory/control obligations. Recovery requires execution/metadata, STQ/store, and scalar-load owners to prepare before one common fire, and quiescence includes the live load path. Superpowers TDD first observed the missing production instance, then two real launch/rebind/completion ready cycles. The minimal repair separates raw same-row launch intent from downstream-credit-qualified acceptance, preserving conservative rebind exclusion and atomic W2 without adding a result buffer. Small O3 configurations also size default LIQ capacity no larger than the canonical ROB identity domain, retaining the no-truncation check. Focused gates pass production structure 1/1, scalar closure 5/5, execution/store integration 4/4, O3 structure 1/1, attempt binding 10/10, canonical ownership 7/7, scalar load path 6/6, Chisel build, and diff check. Remaining gaps are structural-hard-block consumption, shared BID/BROB ordering, all-LSU recovery projection, physical SCB/DTLB/PMP/PMA/device/coherence, cross-line policy, timing, and workloads. Closeout: `skill-evolve: no-update` because sole-owner installation, raw-intent versus accepted-work separation, atomic cross-owner handshakes, and exact recovery rendezvous are already normative in `linx-core`. | +| R769 | I0.15c-b3c3c retained structural-load retry ownership | Starting from production-installation commit `58b8093d`, one `LoadStructuralBlockPolicy` privately consumes the live forwarding fabric's raw hard-block channel. It retains exact identity under backpressure, maps an unknown older exact store to `WaitStore`, maps a stale snapshot to `RetrySnapshot`, advances the producer-qualified attempt generation, and joins old-attempt cancel, OOO metadata rebind, and exact LIQ mutation on one fire. `LoadInflightQueue` independently accepts only the same lease, old attempt, consecutive new attempt, pipe, `Repick + forwardPending` state, and optional exact store wait key. Missing or ambiguous full-LSID authority, invalid shape/query, and cross-line overlap remain retained `Unsupported` state with protocol error and no approximate mutation. The public O3 boundary exports diagnostics only; emitted CHIRRTL proves one policy owner and no external raw hard-block port. Superpowers TDD first observed the missing policy and retry interfaces, then found and repaired a full-execution combinational cycle by arbitrating raw mutation intent instead of downstream acceptance. Directed integration proves a real address-not-ready older store causes exactly one cancel and exact wait-store retry, while a real cross-line overlap remains fail closed. The latter also proves the current recovery limit: exact dual-view kill of the policy is insufficient while MDB transient evidence remains live, so full typed recovery still requires an all-LSU projection and hard flush is the current escape. Final gates pass policy 4/4, structural retry 4/4, LIQ 16/16, STQ result pipeline 7/7, forwarding integration 5/5, scalar closure 8/8, canonical ownership 7/7, store fabric 7/7, O3 structure 1/1, execution structure 1/1, and the Chisel build. The structure gates emit 17 pre-existing size-one-`Vec` dynamic-index warnings in `OooIexIssue.scala`; no warning is introduced by this packet. Remaining gaps are shared native BID/BROB age authority, exact recovery projection for every LSU queue, cross-line forwarding/execution, physical SCB/DTLB/PMP/PMA/device/coherence, sustained pressure, timing, and workloads. Closeout: `skill-evolve: no-update` because retained producer ownership, exact generation rebind, common-fire mutation, and fail-closed unsupported recovery are already normative in `linx-core`. | + +| R770 | LSU two-pipe mechanism preparation and bounded forwarding IT | Starting from Task-13 prerequisite commit `2d769a1b`, `ScalarLSULoadPath` removes the external-forwarding-only three-pipe requirement while retaining a parameterized positive load-return-pipe count. W2/W4/W6/W8 keep two load and two store pipes through the centralized value-only `ScalarLsuParams.fromMainline` projection. Each profile elaborates focused unequal-capacity `16 STQ / 8 ROB / 40-bit LSID` geometry with two forwarding lanes and the existing single LIQ、MDB、MissQ、refill、LRET and L1D owners. The representative forwarding IT now uses the W4 two-pipe shape and minimum legal test-only MDB/refill/L1D capacities. Its five result、hard-recovery、typed-recovery and BID fail-closed scenarios share one reset-separated simulation, and captured query identity is reset-qualified before response injection. This reduces that generated directory from 243 MiB to 47 MiB (80.7%) without dropping a scenario. TDD first failed on the obsolete exact-three requirement. Final focused gates pass the new four-profile mechanism test 1/1, forwarding IT 1/1, related ScalarLSU/L1D selectors 37/37, attempt/structural/STQ/SCB/LIQ/MDB/miss/refill/return tests 71/71, store non-flush and BROB store-range Verilator probes, and the owner checker. The public LSU boundary, final native BID/BROB authority, all-queue recovery equality, translation/protection/coherence, timing and workloads remain Task-15-or-later work. Closeout: `skill-evolve: no-update` because independent queue/identity sizing, bounded directed profiles, parameterized pipe topology and retained exact recovery are already normative in `linx-core`. | + ## Done Criteria A packet is complete only when: diff --git a/docs/chisel/development-loop.md b/docs/chisel/development-loop.md index 2440f62a..68d009e6 100644 --- a/docs/chisel/development-loop.md +++ b/docs/chisel/development-loop.md @@ -1,6 +1,6 @@ # LinxCore Chisel Development Loop -Date: 2026-07-28 +Date: 2026-07-31 ## Purpose @@ -10,6 +10,39 @@ compiler/QEMU/Chisel/LinxCoreModel/superproject loop, then use this file with `docs/chisel/agent-loop.md`, which remains the detailed packet ledger and gate history. +The active LSU priority is I0.15c-b3 live scalar-LSU composition. The b3c3c +packet installs one private retained structural-block policy. Exact +unknown-older dependencies rebind the OOO metadata and LIQ owners under a new +attempt and exact store wait key; stale snapshots retry without a wait key. +Ambiguous authority, malformed/cross-line cases remain fail closed, and the raw +hard-block channel no longer escapes the production wrapper. Typed recovery of +the policy is exact-dual-kill only and still obeys the all-other-LSU-owner-empty +fence. The b3c3b production wrapper installs the b3c3a scalar-load attachment +against the existing execution-cluster metadata owner and existing STQ owner. +It keeps all three forwarding lanes and prospective MDB admission private, proves exactly +one metadata/LIQ/STQ owner graph, and joins execution, store, and scalar-load +recovery on one common fire. Raw launch intent is separate from downstream +credit-qualified acceptance so same-row rebind exclusion does not form a +terminal-ready loop. +The b3c2 +packet now atomically queues every canonical LIQ launch onto one of three +physical STQ lanes, retains queries under backpressure, reserves normal-result +E3/E4/FIFO capacity, routes structural uncertainty separately, and applies the +retained exact result without a production compatibility CAM. Hard flush +clears transport; typed precise recovery fences external fire and preserves +survivor reservations for post-recovery exact apply. The b3c1 result +owner separates permanent stale rejection from retryable recovery or exact-row +mutation conflicts. The c-b1 ownership bridge makes LIQ allocation, exact replay rebind, terminal metadata, and +two-phase recovery atomic without introducing load lifecycle residency. c-b2a +now derives speculative wakeup only from exact LIQ launch, derives cancel from +exact rebind/fault, and restores lane-qualified W1 bypass. c-b2b replaces the +three migration trackers with one canonical bridge in the execution cluster, +propagates its typed LSU port through the closed wrappers, joins load metadata +recovery readiness, and deletes the old tracker after replacement cluster IT +passes. The next packet must replace the migration BID projection with shared +BID/BROB ordering authority, extend recovery projection equality to the +remaining LSU owners, and implement cross-line forwarding/execution. + The active backend priority is OOO packet O8.3 physical closure. O7 global recovery and CTU reinsertion are packet-complete. O8.3e replaces the grouped ROB's full-window combinational recovery view with retained bounded find/build @@ -39,9 +72,9 @@ O7.2c dispatch/IEX/fast direct owners are now complete: exact published member identity, target-STID provisional cancellation, S1/S2/S3 pruning, local generation-qualified ready cleanup, and retained-fast cancellation all consume one compact ROB-authorized recovery window. O7.2d1 retains the lower physical -subtransaction in `OooRobBrobPcCoordinator`. O7.2d2 now composes it in -`OooO3RenameCoordinator` with the exact P/T/U suffix authority, dispatch, fast -resolve, and an external typed IEX prepare/fire interface. All physical owners +subtransaction in `OOOD3S1Graph`. The live composition is public +`OOO` through `OOOD3S1Graph`, where `RecoveryControl` prepares RENU, BROB, +Dispatch, and typed external recovery targets. All participating owners apply on one cycle; R4 waits for rename-source drain and P/T/U rebuild. A retained abort state prevents a late owner acceptance from surviving another owner's rejection. PTag return and external IEX ready-generation invalidation @@ -58,7 +91,7 @@ metadata, canonical 2/4/6-wide D1 decode, exact P/T/U and pair operand normalization, precise-trap conversion, same/cross-cycle boundary fusion, and the fixed-four-wide IFU to per-STID 2/4/6 raw ingress. CTU and complex rows carry exact diverted parents rather than mask-only identity; CTU child -reinsertion now uses the O7 `OooCtuIngressBridge` before D2. O3 now has virtual grouping, +reinsertion now uses the O7 `CTU` before D2. O3 now has virtual grouping, retained D2/D3 allocation, atomic grouped ROB publication/completion, native BID/generation BROB ownership, a fixed-partition 64-entry byte-offset PC buffer, and the shared ROB/BROB/PC reserve/publish/commit coordinator. O4 owns @@ -567,9 +600,9 @@ comparator. The Verilator harness now derives initial RF preloads from the first expected source reads instead of hardcoding the synthetic fixture's `r4=10, r5=32`; this lets QEMU's zero-valued initial sources and the older synthetic rows share one expected-row contract. Evidence: -`build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r100-live-qemu-fixture` +historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r100-live-qemu-fixture` Provenance: source commit 77001f0ec3b463950c1a275fcb5e3dc1638d73cd. and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 3 --capture-rows 3 --pc-lo 0x10002 --pc-hi 0x1000b --max-seconds 5` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 3 --capture-rows 3 --pc-lo 0x10002 --pc-hi 0x1000b --max-seconds 5` Provenance: source commit 77001f0ec3b463950c1a275fcb5e3dc1638d73cd. passed with `compared_rows: 3` and `mismatch_count: 0`. This is still a reduced scalar prefix gate; block headers, dense packets, memory/trap rows, LSU, recovery, and CoreMark live-DUT equivalence remain future packets. @@ -588,9 +621,9 @@ block-marker consume path for the live fetch RF/ALU gate: legal `C.BSTART` and `C.BSTOP` rows from QEMU are preserved as `skip` entries, fetched and decoded by the DUT, and asserted not to allocate ROB rows or enter issue. The architectural comparator still receives only the three scalar rows. Evidence: -`build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r101-live-qemu-fixture` +historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r101-live-qemu-fixture` Provenance: source commit 7eecd8e2770658c633bd52e65654a92d61f7b4e0. and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r101-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --elf generated/r101-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` Provenance: source commit 7eecd8e2770658c633bd52e65654a92d61f7b4e0. captured five raw QEMU rows, preserved skip markers at `0x10000` and `0x1000c`, and passed with `compared_rows: 3` and `mismatch_count: 0`. This is not full block execution: dense mixed marker/scalar packets, scalar_done/BROB @@ -610,10 +643,10 @@ serialized `DecodeRenameROBPath`: it captures every valid slot from one cycle. This aligns the reduced live fetch RF/ALU gate with the model IFU `DecodeBundle` path (`mask`, `entry[]`, `isize[]`, and `tpcArr[]`) while deferring width-wide ROB allocation. Evidence: -`build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r102-live-qemu-fixture`, -`BUILD_DIR=generated/r102-default-fetch-rf-alu-trace-top-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh`, +historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r102-live-qemu-fixture` Provenance: source commit d56ea4f505b0e4db9dcd81604e8fdd19bf1ce965. , +historical evidence only (no current runnable equivalent): `BUILD_DIR=generated/r102-default-fetch-rf-alu-trace-top-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit d56ea4f505b0e4db9dcd81604e8fdd19bf1ce965. , and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r102-dense-qemu-elf-xcheck --elf generated/r102-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r102-dense-qemu-elf-xcheck --elf generated/r102-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` Provenance: source commit d56ea4f505b0e4db9dcd81604e8fdd19bf1ce965. passed with `compared_rows: 3` and `mismatch_count: 0`. The R102 marker contract is marker-owned: a marker slot must not select a scalar row, push dec/ren, or allocate ROB, but it may drain in the same cycle that an older @@ -632,9 +665,9 @@ and commit sideband, and consumed `BSTOP` rows pulse scalar done for the active BID before the normal one-cycle-later BROB retire pulse. This remains reduced marker-consume timing, not full marker ROB retirement or recovery-exact block control. Evidence: -`build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r104-live-qemu-fixture` +historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r104-live-qemu-fixture` Provenance: source commit b487843427125df2aca2284bd17e0578f31e32e0. and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r104-marker-lifecycle-qemu-elf-xcheck --elf generated/r104-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r104-marker-lifecycle-qemu-elf-xcheck --elf generated/r104-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` Provenance: source commit b487843427125df2aca2284bd17e0578f31e32e0. passed with `compared_rows: 3` and `mismatch_count: 0`. R105 started from `linx-isa` commit `39d975bdf589923354ddbb300b49a40cb5e36313`, `rtl/LinxCore` commit @@ -645,9 +678,9 @@ R105 started from `linx-isa` commit `--long-body` mode to the live-QEMU legal-entry fixture so the current reduced scalar ALU subset runs seven scalar commits under one marker-owned active block instead of only the three-row smoke. Evidence: -`build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r105-long-body-fixture --long-body` +historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r105-long-body-fixture --long-body` Provenance: source commit 96bf4fc077ec9df6759a723c3caf5ffc13154d98. and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r105-long-body-qemu-elf-xcheck --elf generated/r105-long-body-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 9 --allow-block-markers --max-seconds 5` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r105-long-body-qemu-elf-xcheck --elf generated/r105-long-body-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 9 --allow-block-markers --max-seconds 5` Provenance: source commit 96bf4fc077ec9df6759a723c3caf5ffc13154d98. passed with `compared_rows: 7` and `mismatch_count: 0`. R106 started from `linx-isa` commit `a5f99f55dd76542de6178dcb144e4ae35da68c2c`, `rtl/LinxCore` commit @@ -662,7 +695,7 @@ RF/ALU live-QEMU envelope with `ADDTPC`, the first unsupported CoreMark The QEMU probe before the patch failed at `pc=0x400054f8 insn=0x9187`, and the R106 gate compares the first four CoreMark rows before the next unsupported HL call marker. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r106-coremark-addtpc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 4 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r106-coremark-addtpc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 4 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 59a64a0746b07346e88e0c9ea1e3319e11f85603. passed with `status: "pass"`, `summary.compared_rows: 3`, and `summary.mismatch_count: 0`. R107 started from `linx-isa` commit @@ -678,7 +711,7 @@ to the active `BSTART` target instead of executing filler markers. The model/QEMU contract is `PC::CalcInstSetret` for PC-relative return setup, `BCtrl`/IFU target-bearing `BSTART` semantics, and QEMU's duplicate zero-advance HL marker artifact followed by the advancing marker row. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r107-coremark-hl-call-setret-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 8 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r107-coremark-hl-call-setret-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 8 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 9ba736f4851417da7b06d5b8813e344ddca5c3a8. passed with `status: "pass"`, `summary.compared_rows: 4`, and `summary.mismatch_count: 0`. R108 started from `linx-isa` commit @@ -692,7 +725,7 @@ decoder reads the saved GPR and SP internally, writes the decremented SP, and emits the QEMU-shaped 8-byte store sideband while suppressing internal source fields in the commit row. This is only the current CoreMark single-save prologue shape, not full stack-template or LSU execution. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r108-coremark-fentry-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 11 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r108-coremark-fentry-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 11 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 795e78fb6dc68863e0fcf108f7b2d9f2375249e0. passed with `status: "pass"`, `summary.compared_rows: 6`, and `summary.mismatch_count: 0`. A 12-row probe stops at the next unsupported row: `ADDI` writing architectural tag `30`. @@ -708,7 +741,7 @@ owns the T/U destination overlay from the model `OPD_ULINK` path; the reduced issue and execute owners now gate scalar RF clear/write side effects to `DestinationKind.Gpr`, while the commit row still carries the QEMU-shaped `dst_reg=30` and `wb_rd=30` architectural fields. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r109-coremark-u-dst-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 12 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r109-coremark-u-dst-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 12 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 0849e42300025d20f92535b070f4e61889315e3c. passed with `status: "pass"`, `summary.compared_rows: 7`, and `summary.mismatch_count: 0`. A 13-row probe stops at the next unsupported row: `OP_HL_LUI` at `pc=0x4000551a`, `insn=0x1f97000e`, `len=6`. @@ -723,7 +756,7 @@ extracts `IMM32=1` from `Cat(pfx16[15:4], main32[31:12])`, classifies destination architectural tag `31` as `DestinationKind.T`, and the reduced ALU emits the immediate as the QEMU-shaped destination/writeback data while keeping scalar RF writeback gated to `DestinationKind.Gpr`. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r110-coremark-hl-lui-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 13 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r110-coremark-hl-lui-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 13 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 2d5cbcaf234d32fc773792b5a36279d1063f5287. passed with `status: "pass"`, `summary.compared_rows: 8`, and `summary.mismatch_count: 0`. A 14-row probe stops at the next unsupported row: `OP_SLL` at `pc=0x40005520`, `insn=0x01cc7f05`, `len=4`; that row uses T/U @@ -744,7 +777,7 @@ same packet fixes the first reduced ROB wrap case: the `SLL` row is the ninth scalar allocation in an 8-entry generated top, so `DecodeRenameROBPath` must stamp queued `rid.wrap` from `DispatchROBAllocator.allocRobWrap` instead of using a false-wrap RID. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r111-coremark-sll-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 14 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r111-coremark-sll-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 14 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit e4d8f6bae895a562afb4f254660ffe6be8174b9d. passed with `status: "pass"`, `summary.compared_rows: 9`, and `summary.mismatch_count: 0`. R112 started from `linx-isa` commit @@ -760,7 +793,7 @@ live RF/ALU path compare the next CoreMark local shift pair. `SLL` at `pc=0x4000552e` reads local T/U sources and writes T tag `31`; both rows keep scalar source fields suppressed and avoid scalar RF writeback side effects. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r112-coremark-sll-srl-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 17 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r112-coremark-sll-srl-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 17 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit c0b9ca12224408e964e729661a07e21dc04aa04b. passed with `status: "pass"`, `summary.compared_rows: 12`, and `summary.mismatch_count: 0`. An 18-row probe stops at `OP_OR` (`pc=0x40005532`, `insn=0x078e3f05`, `len=4`), which reads local U0/T0 and @@ -778,7 +811,7 @@ live RF/ALU path compare `OP_OR` at `pc=0x40005532` and the following and writes U0; the narrow `C.LDI` row reads scalar x4, emits an 8-byte load sideband with zero data, writes T0, and remains a prefix bridge rather than a general data-memory implementation. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r113-coremark-or-c-ldi-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 19 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r113-coremark-or-c-ldi-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 19 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 00bf5f15f11355b86a07b7a95d333811db5430d0. passed with `status: "pass"`, `summary.compared_rows: 14`, and `summary.mismatch_count: 0`. A 21-row extraction probe identifies the next unsupported row as `OP_C_ADD` (`pc=0x4000553c`, `insn=0xe608`, `len=2`) after a @@ -798,7 +831,7 @@ and implicit `dst0=31`; for `insn=0xe608` those fields read T0/U0 and write T0. Current QEMU commit JSONL omits the C.ADD local destination/writeback fields, so the expected-row reducer synthesizes only that implicit T writeback from QEMU PC/instruction order plus the local-value queue. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r114-coremark-c-add-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 21 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r114-coremark-c-add-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 21 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 088d80f20b9a9c3a6dc40acc5ceab9855056b40d. passed with `status: "pass"`, `summary.compared_rows: 16`, and `summary.mismatch_count: 0`. A 22-row extraction probe identifies the next unsupported row as `OP_SRA` (`pc=0x4000553e`, `insn=0x01ec6f85`, `len=4`); @@ -818,7 +851,7 @@ RF/ALU path compare `OP_SRA` at `pc=0x4000553e` and the paired `OP_SLLI` at `SrcR & 0x3f`, while `SLLI` uses `shamt_20_25`. Because the live frontend emits `SRA` and `SLLI` in the same dense packet, the reduced top now stalls younger rename output while a local T/U producer is pending. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r115-coremark-sra-slli-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 23 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r115-coremark-sra-slli-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 23 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit b332ab2427df2c63ff18e3b1c422bd232ec1315b. passed with `status: "pass"`, `summary.compared_rows: 18`, and `summary.mismatch_count: 0`. A 24-row extraction probe identifies the next frontier as mixed local/scalar `C.ADD` (`pc=0x40005546`, `insn=0x2608`, @@ -847,7 +880,7 @@ encoded source fields by checking whether each encoded register is a local T/U alias or scalar GPR, instead of hard-coding opcode-wide source-valid patterns. A 24-row gate is intentionally too short because it cuts through the three-slot dense packet; use the 26-row gate for this packet. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r116-coremark-c-add-mixed-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 26 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r116-coremark-c-add-mixed-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 26 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 198c8641c105ad4674ebe4ee48bbecce311ff666. passed with `status: "pass"`, `summary.compared_rows: 21`, and `summary.mismatch_count: 0`. A 27-row probe still passes and shows the next raw row as a zero-advance `C.BSTART` artifact at `pc=0x4000554e`, `insn=0x0004`; @@ -884,7 +917,7 @@ T/U retire serializer now drains terminal rename responses `accepted`; this prevents a stale relation command from holding the retire path forever while preserving the miss/mismatch diagnostics that exposed the issue. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r117-coremark-c-movr-c-ldi-setc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 34 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r117-coremark-c-movr-c-ldi-setc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 34 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit c6121aabdb9a7a3962045123d366f380c983bc8b. passed with `status: "pass"`, `expected rows: 31`, `summary.compared_rows: 25`, and `summary.mismatch_count: 0`. The next frontier is the dense packet beginning at `pc=0x4000555c`, @@ -911,7 +944,7 @@ data and suppressed local T0 as the address base. A 41-row capture cuts inside the two-slot dense packet containing `SDI`, and a 43-row capture cuts inside the following three-slot packet, so the promoted gate uses `--capture-rows 42`. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r118-coremark-sdi-42-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 42 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r118-coremark-sdi-42-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 42 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit b1a2039c4dc02704974f36d122625d822bf75e0b. passed with `status: "pass"`, `summary.compared_rows: 31`, and `summary.mismatch_count: 0`. The next frontier is the dense packet beginning at `pc=0x40005572`, including the `0x3a36` no-writeback compare and the @@ -936,7 +969,7 @@ allocates the fallthrough marker block or redirects to the active conditional target without allocating a new marker block. A 48-row raw capture cuts inside the post-redirect dense F4 window, so the promoted gate uses `--capture-rows 50`. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r119-coremark-cond-bstart-50-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 50 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r119-coremark-cond-bstart-50-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 50 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 4fdfdc4d431f4d660d0bfab605842c67b073b35d. passed with `status: "pass"`, `summary.compared_rows: 36`, and `summary.mismatch_count: 0`. @@ -959,7 +992,7 @@ block-last sideband closes it; second, this reduced top compares stores from the ALU-produced sideband but does not drive STA/STD execution or STQ commit/free feedback, so it must bypass store-dispatch residency instead of letting the reduced STQ shell fill on repeated `SDI` rows. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r120-coremark-scalar-block-store-bypass-128-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 128 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r120-coremark-scalar-block-store-bypass-128-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 128 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit d1386dcab31ca6495c1bac84ed04d7c65bd43e34. passed with `status: "pass"`, `summary.compared_rows: 88`, and `summary.mismatch_count: 0`. The 256-row probe stops before RTL comparison at the next unsupported reduced selector row: `pc=0x40005576`, @@ -984,7 +1017,7 @@ capture ended at `pc=0x400055ba` inside an 8-byte F4 window, while the DUT decoded the remaining slots from the real fetch bytes. The harness now treats only the final captured expected row as a verified prefix and still requires exact row comparison for every committed row in the captured prefix. Evidence: -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r121-coremark-ldi-setceq-tail-256-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 256 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r121-coremark-ldi-setceq-tail-256-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 256 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 61a2bd17fc7b974a4f72b795c60b40daf9460c2d. passed with `status: "pass"`, `summary.compared_rows: 173`, and `summary.mismatch_count: 0`. @@ -1007,7 +1040,7 @@ admits the next QEMU row shapes discovered by the larger probe: `frontend_fetch_rf_alu_qemu_rows.py --self-test`, `run_chisel_tests.sh --only ReducedScalarAluExecute`, `run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop`, and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r122-coremark-prefix-before-redirect-marker-470-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 470 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r122-coremark-prefix-before-redirect-marker-470-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 470 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 25367127b0674d74a6c35d19adaee3d645b2c737. passed with `frontend-fetch-rf-alu-qemu-elf-status=pass`, `compared=315`, and `mismatches=0`. A 512-row probe advances to `OP_SD` at `pc=0x400055f2`, and a 486-row pre-store probe first exposes a redirecting `C.BSTART` marker @@ -1034,7 +1067,7 @@ directly. It also updates the live RF/ALU Verilator harness to collect legal two-slot commit windows in slot order. Evidence: `run_chisel_tests.sh --only DecodeRenameROBPath`, `run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop`, and -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r123-coremark-redirect-marker-486-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 486 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r123-coremark-redirect-marker-486-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 486 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 8bfd505604f3fb035897356556aece8f0ab3debf. passed with `frontend-fetch-rf-alu-qemu-elf-status=pass`, `compared=323`, and `mismatches=0`. The next frontier remains the following indexed `OP_SD` at `pc=0x400055f2`, which needs explicit store memory mutation or real LSU/STQ @@ -1062,7 +1095,7 @@ Evidence: `python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test`, `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute`, `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop`, and -`bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r124-coremark-op-sd-544-probe-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 544 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r124-coremark-op-sd-544-probe-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 544 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 06e3855d713aa03a63d6dea70988f3b3a24bbcf5. passed with `frontend-fetch-rf-alu-qemu-elf-status=pass`, `compared=357`, and `mismatches=0`. @@ -1087,9 +1120,9 @@ plus signed bits `[15:11] << 3`, fixed T0 store payload, no writeback, and one `python3 tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test`, `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute`, `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop`, -`bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r125-coremark-subi-cand-add-csdi-768-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 768 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf`, +historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r125-coremark-subi-cand-add-csdi-768-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 768 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit a4881845b415bbc01ee9a1b9899399e8ec4b76da. , and -`bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r125-coremark-1024-frontier-probe-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r125-coremark-1024-frontier-probe-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit a4881845b415bbc01ee9a1b9899399e8ec4b76da. passed. The promoted 1024-row probe extracted 953 expected rows and compared 665 normalized QEMU/DUT rows with zero mismatches. @@ -1118,7 +1151,7 @@ side-effect-free macro rows in the compare stream. Evidence: `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath`, `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop`, and -`bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r126-coremark-fret-scalar-redirect-1415-qemu-elf-xcheck-pass --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1415 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r126-coremark-fret-scalar-redirect-1415-qemu-elf-xcheck-pass --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1415 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit a26fdb916fce0fe4ad5201055082f5279dbfb63d. passed. The promoted gate extracted 1303 expected rows and compared 927 normalized QEMU/DUT rows with zero mismatches. @@ -1194,7 +1227,8 @@ LinxCore adaptation: - Use `tools/chisel/build_chisel.sh`, `emit_verilog.sh`, `run_chisel_verilator_lint.sh`, `run_chisel_reduced_rob_xcheck.sh`, - `run_chisel_top_xcheck.sh`, and `run_chisel_qemu_crosscheck.sh`. + `run_chisel_frontend_trace_top_xcheck.sh`, and + `run_chisel_qemu_crosscheck.sh`. - Use `tools/chisel/trace_schema_adapter.py` as the typed boundary into `tools/trace/crosscheck_qemu_linxcore.py`. - Define Linx-native `LC-IF-CHISEL-XCHK-*` payloads. Do not import @@ -1228,7 +1262,7 @@ The ROB/cross-check substrate remains the required base: |---|---|---|---| | 1 | R76 implemented baseline: enqueue-time ROB reservation plus post-rename sidecar update | `DecodeRenameROBPath.scala`, `DispatchROBAllocator.scala`, `ROBEntryBank.scala`, module docs | `DecodeRenameROBPath`, `DispatchROBAllocator`, `ROBEntryBank`, `DecodeRenameQueue`, `run_chisel_rob_bookkeeping.sh --reduced-rob` | | 2 | R77 gate broadening and top trace prep | `commit/`, `top/`, `tools/chisel/trace_schema_adapter.py`, wrapper docs | top xcheck, Verilator lint, `build_chisel.sh`, trace self-test, QEMU dry-run | -| 3 | R78 trace replay xcheck harness | `tools/chisel/reduced_rob_trace_tb.cpp`, `tools/chisel/run_chisel_trace_replay_xcheck.sh`, wrapper docs | `run_chisel_trace_replay_xcheck.sh`, top xcheck, trace self-test, QEMU dry-run | +| 3 | R78 trace replay xcheck harness | `tools/chisel/reduced_rob_trace_tb.cpp`, historical evidence only (no current runnable equivalent): `tools/chisel/run_chisel_trace_replay_xcheck.sh` Provenance: source commit ed70d74d700d5c4bcd20dc3ce768b23329d8deea. , wrapper docs | historical evidence only (no current runnable equivalent): `run_chisel_trace_replay_xcheck.sh` Provenance: source commit ed70d74d700d5c4bcd20dc3ce768b23329d8deea. , top xcheck, trace self-test, QEMU dry-run | | 4 | R79 frontend-window trace top | `top/LinxCoreFrontendTraceTop.scala`, `F4DecodeWindow.scala`, `DecodeRenameROBPath.scala`, top docs | `LinxCoreFrontendTraceTop`, frontend trace top Verilator lint, `DecodeRenameROBPath`, trace self-test, QEMU dry-run | | 5 | R80 frontend-window Verilator xcheck | `tools/chisel/frontend_trace_top_tb.cpp`, `tools/chisel/run_chisel_frontend_trace_top_xcheck.sh`, top/cross-check docs | `run_chisel_frontend_trace_top_xcheck.sh`, frontend trace top lint, trace self-test, QEMU dry-run | | 6 | R81 scalar ALU completion row xcheck | `execute/ReducedScalarAluExecute.scala`, `top/LinxCoreFrontendAluTraceTop.scala`, frontend ALU xcheck driver/script, module docs | `ReducedScalarAluExecute`, `LinxCoreFrontendAluTraceTop`, `run_chisel_frontend_alu_trace_top_xcheck.sh`, old frontend trace-top regression | @@ -1241,22 +1275,22 @@ The ROB/cross-check substrate remains the required base: | 13 | R88 reduced P1/I1/I2 issue timing | `execute/ReducedScalarIssuePick.scala`, `execute/ReducedScalarIssueQueue.scala`, `top/LinxCoreFrontendRfAluTraceTop.scala`, issue/top module docs | `ReducedScalarIssuePick`, `ReducedScalarIssueQueue`, `LinxCoreFrontendRfAluTraceTop`, `run_chisel_frontend_rf_alu_trace_top_xcheck.sh`, R81/R82 trace regressions | | 14 | Live commit trace schema | `commit/`, `top/`, `tools/chisel/trace_schema_adapter.py` | `trace_schema_adapter.py --self-test`, reduced/top/replay/frontend-top gates | | 15 | R89 QEMU cross-check manifest evidence | `tools/chisel/run_chisel_qemu_crosscheck.sh`, cross-check docs | dry-run, RF/ALU xcheck, ALU xcheck, trace self-test, diff check | -| 16 | R90 QEMU trace replay harness | `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh`, trace replay wrapper docs | dry-run, archived/fresh QEMU JSONL replay with metadata-aware raw prefix, manifest inspection | -| 17 | R91 bounded CoreMark ELF replay prefix | `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh`, trace replay wrapper docs | default-memory fail-fast check, CoreMark `--elf` replay with explicit `-m 1280M`, manifest inspection | +| 16 | R90 QEMU trace replay harness | historical evidence only (no current runnable equivalent): `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh` Provenance: source commit 1c40d4eeae136370003d1e257669972e2f90e433. , trace replay wrapper docs | dry-run, archived/fresh QEMU JSONL replay with metadata-aware raw prefix, manifest inspection | +| 17 | R91 bounded CoreMark ELF replay prefix | historical evidence only (no current runnable equivalent): `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh` Provenance: source commit 9cd2e09af329ff08d0370c9bb334ae72298b1281. , trace replay wrapper docs | default-memory fail-fast check, CoreMark `--elf` replay with explicit `-m 1280M`, manifest inspection | | 18 | R92 shared commit JSONL writer | `tools/chisel/commit_trace_jsonl.h`, generated-RTL Verilator harnesses, cross-check docs | reduced/top/replay/frontend generated-RTL xchecks, trace self-test, QEMU dry-run, diff check | | 19 | R93 frontend fetch packet source | `frontend/FrontendFetchPacketSource.scala`, module docs/tests | `FrontendFetchPacketSource`, `F4DecodeWindow`, `FrontendDecodeIngress`, trace self-test, QEMU dry-run | | 20 | R94 live frontend fetch trace top | `top/LinxCoreFrontendFetchTraceTop.scala`, `frontend/FrontendFetchPacketSource.scala`, live Chisel trace writer | `LinxCoreFrontendFetchTraceTop`, `run_chisel_frontend_fetch_trace_top_xcheck.sh`, manifest inspection | -| 21 | R95 live frontend fetch RF-backed ALU trace top | `top/LinxCoreFrontendFetchRfAluTraceTop.scala`, `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, top/cross-check docs | `FrontendFetchPacketSource`, `LinxCoreFrontendFetchRfAluTraceTop`, `run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh`, manifest inspection | +| 21 | R95 live frontend fetch RF-backed ALU trace top | `top/LinxCoreFrontendFetchRfAluTraceTop.scala`, `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, top/cross-check docs | `FrontendFetchPacketSource`, `LinxCoreFrontendFetchRfAluTraceTop`, historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 1775df73eefaa1eadac5a0ff0499ad133466113b. , manifest inspection | | 22 | R96 file-backed frontend fetch memory feeder | `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, `tools/chisel/frontend_fetch_rf_alu_fixture_memory.py`, top/cross-check docs | live fetch RF/ALU xcheck, manifest inspection, trace self-test, QEMU dry-run | -| 23 | R97 sparse ELF fetch-memory extractor | `tools/chisel/frontend_fetch_elf_memory.py`, `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, `tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh`, top/cross-check docs | ELF extractor self-test, live fetch RF/ALU xcheck through sparse memory, manifest inspection | +| 23 | R97 sparse ELF fetch-memory extractor | `tools/chisel/frontend_fetch_elf_memory.py`, `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, historical evidence only (no current runnable equivalent): `tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 0f74eb380193f9a56132905fc782d533e457c1b0. , top/cross-check docs | ELF extractor self-test, live fetch RF/ALU xcheck through sparse memory, manifest inspection | | 24 | R98 external expected-row source binding | `tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp`, `tools/chisel/frontend_fetch_rf_alu_fixture_rows.py`, live fetch RF/ALU wrapper/docs | fixture row self-test, live fetch RF/ALU xcheck through `FETCH_EXPECTED_ROWS`, manifest inspection | | 25 | R99 strict QEMU trace expected-row extraction | `tools/chisel/frontend_fetch_rf_alu_qemu_rows.py`, live fetch RF/ALU wrapper/docs | QEMU-row helper self-test, live fetch RF/ALU xcheck through `FETCH_QEMU_TRACE`, default fixture regression, manifest inspection | -| 26 | R100 live QEMU capture plus reduced-row selection | `tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh`, `tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh`, live fetch RF/ALU harness/docs | bounded QEMU trace capture, `FETCH_QEMU_TRACE` plus `FETCH_ELF`, row-derived RF preload regression, manifest inspection, explicit unsupported-row report | +| 26 | R100 live QEMU capture plus reduced-row selection | historical evidence only (no current runnable equivalent): `tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` Provenance: source commit 77001f0ec3b463950c1a275fcb5e3dc1638d73cd. , historical evidence only (no current runnable equivalent): `tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh` Provenance: source commit 77001f0ec3b463950c1a275fcb5e3dc1638d73cd. , live fetch RF/ALU harness/docs | bounded QEMU trace capture, `FETCH_QEMU_TRACE` plus `FETCH_ELF`, row-derived RF preload regression, manifest inspection, explicit unsupported-row report | | 27 | R101 reduced block-marker skip path | `DecodeRenameROBPath.scala`, `LinxCoreFrontendFetchRfAluTraceTop.scala`, QEMU-row extractor, live harness/docs | live fetch xchecks with BSTART/BSTOP skip rows, no PC filter, manifest inspection | | 28 | R102 reduced dense multi-slot frontend packet path | `F4DenseSlotQueue.scala`, `LinxCoreFrontendFetchRfAluTraceTop.scala`, live fetch RF/ALU harness/docs | `F4DenseSlotQueue`, adjacent frontend/path tests, default live fetch RF/ALU xcheck, live QEMU fixture with mixed BSTART/scalar/BSTOP 8-byte windows, manifest inspection | | 29 | R103 ROB block-last to BROB lifecycle sideband | `BROB.scala`, `ROBEntryBank.scala`, `DispatchROBAllocator.scala`, `DecodeRenameROBPath.scala`, `LinxCoreFrontendFetchRfAluTraceTop.scala`, module docs | BROB stale-BID reference, full block-BID block-last deallocation sideband, reduced scalar-done and next-cycle retire diagnostics, focused ROB/BROB/top gates, manifest inspection | | 30 | R104 marker-owned active block lifecycle | `DispatchROBAllocator.scala`, `DecodeRenameROBPath.scala`, `LinxCoreFrontendFetchRfAluTraceTop.scala`, live harness/docs | marker-only BROB allocation, scalar active-BID reuse, marker-driven scalar-done/retire, default RF/ALU xcheck, live QEMU fixture with `BSTART`/scalar/`BSTOP`, manifest inspection | -| 31 | R105 longer live-QEMU reduced scalar body | `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh`, `LinxCoreFrontendFetchRfAluTraceTop.md`, runbook docs | `--long-body` fixture build, live QEMU marker gate with `--capture-rows 9`, seven scalar commits compared, manifest inspection | +| 31 | R105 longer live-QEMU reduced scalar body | historical evidence only (no current runnable equivalent): `build_frontend_fetch_rf_alu_qemu_fixture_elf.sh` Provenance: source commit 96bf4fc077ec9df6759a723c3caf5ffc13154d98. , `LinxCoreFrontendFetchRfAluTraceTop.md`, runbook docs | `--long-body` fixture build, live QEMU marker gate with `--capture-rows 9`, seven scalar commits compared, manifest inspection | | 32 | R106 CoreMark ADDTPC reduced scalar prefix | `ReducedScalarAluExecute.scala`, `frontend_fetch_rf_alu_qemu_rows.py`, execute/top docs | reduced ALU unit, extractor self-test, CoreMark live-QEMU gate with `--capture-rows 4`, first three scalar commits compared, manifest inspection | | 33 | R107 CoreMark HL call marker and compact SETRET prefix | `FrontendDecodeStage.scala`, `FrontendOperandDecode.scala`, `F4DecodeWindow.scala`, `DecodeRenameROBPath.scala`, `LinxCoreFrontendFetchRfAluTraceTop.scala`, `ReducedScalarAluExecute.scala`, `frontend_fetch_rf_alu_qemu_rows.py`, module docs | extractor self-test, focused Chisel gates, CoreMark live-QEMU gate with `--capture-rows 8`, first four scalar commits compared, manifest inspection | | 34 | R108 CoreMark single-save FENTRY reduced macro row | `FrontendOperandDecode.scala`, `ReducedScalarAluExecute.scala`, `frontend_fetch_rf_alu_qemu_rows.py`, `frontend_fetch_rf_alu_trace_top_tb.cpp`, module docs | extractor self-test, focused Chisel gates, CoreMark live-QEMU gate with `--capture-rows 11`, first six scalar/macro commits compared, manifest inspection | @@ -1299,71 +1333,22 @@ Use this ladder for every promoted packet: commit, allocation, or recovery changes. 4. `python3 tools/chisel/trace_schema_adapter.py --self-test` for trace schema changes. -5. `bash tools/chisel/run_chisel_top_xcheck.sh` for top-level IO or commit - monitor changes. -6. `bash tools/chisel/run_chisel_trace_replay_xcheck.sh` for any top-level - commit export, adapter, or cross-check harness changes. -7. `bash tools/chisel/run_chisel_frontend_trace_top_lint.sh` for any +5. `bash tools/chisel/run_chisel_frontend_trace_top_lint.sh` for any frontend-window-to-commit top boundary changes. -8. `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` after changes +6. `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh --dry-run` for + emitter, top-name, harness, wrapper, or comparator-argument changes. +7. `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` after changes to the frontend trace-top driver, completion surrogate, or commit export. -9. `bash tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh` after - changes to the live frontend fetch source top, bounded memory-window - fixture, source-to-legacy-window handshake, completion surrogate, or commit - export. -10. `bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` after - changes to scalar ALU execute completion, completion-row payload wiring, or - the frontend ALU trace-top driver. -11. `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` after - changes to scalar RF operand sourcing, registered issue-queue source - readiness, oldest-ready issue selection, issue-pick read-confirm gating, - physical writeback metadata, or the shared frontend ALU trace-top driver. -12. `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` - after changes to the live fetch source to RF-backed issue/ALU top, bounded - memory-window fixture, source PC advance, dense F4 slot capture/drain, - issue enqueue, RF writeback, ALU completion, or commit export. -13. `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` - after changes to live QEMU capture, strict QEMU row selection, sparse ELF - fetch-memory binding, or the row-derived RF preload contract for the - reduced fetch RF/ALU gate. - Use `--allow-block-markers --expected-rows 0 --capture-rows 5` for the - legal-entry fixture when marker rows are intentionally part of the DUT input - stream but not part of the comparator stream. Use - `--allow-block-loop-reentry` only with `--allow-block-markers` for dynamic - FALL-header re-entry streams. For R143 and later reduced-top promotion, feed - those loop-aware rows through the live fetch RF/ALU top and require a - zero-mismatch generated-RTL replay. R144 moves the temporary contract to - `reducedBfu*` geometry consumed by `ReducedBfuBodyCutPredictor`; do not claim - full BFU closure until a real static-predictor geometry producer replaces - that harness source. R145 adds only diagnostic static-geometry learning from - explicit block-boundary or `BSTOP` events, R146 adds resolved body-end - learning for the same `SetBsize` contract, and R147 carries resolved - `hsize` payload on that diagnostic row. R148 compares the diagnostic row - against the external replay geometry, R149 factors resolved body-end - normalization into `ReducedBfuResolvedBodyEndOwner`, and R150 lets - `ReducedBfuBodyCutPredictor` consume latched static geometry payload through - `ReducedBfuGeometryPredictionLatch`. The latch prevents same-cycle learning - from clipping the sequential packet that discovered a body end. R152 factors - external cut-arm acceptance into `ReducedBfuBodyCutArm`; the generated-RTL - harness reports comparable, accepted, and mismatched arm rows while only - accepted rows can enable body-cut control. The external replay row remains - only the temporary cut-arm, resolved-event source, and comparison oracle - until real branch-resolution/body-end ownership is replay-proven. -14. `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` for wrapper or +8. `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` for comparator or QEMU-selection changes. -15. `bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh --dry-run` for - QEMU-row replay wrapper changes, then replay a bounded archived or fresh - QEMU JSONL with `--qemu-trace` or `--elf`. Use `--replay-rows` only to cap - the raw search window; `--max-commits` remains the architectural compare - window. -16. Inspect `/crosscheck_manifest.json` after any non-dry-run +9. Inspect `/crosscheck_manifest.json` after any non-dry-run generated-RTL or QEMU comparison that routes through the common wrapper. - R151 and later manifests must include `git.linxcore`, `git.linxcore_model`, + Manifests must include `git.linxcore`, `git.linxcore_model`, `git.qemu`, and `git.superproject` before the run is cited as provenance for a promoted RTL packet. -17. Full QEMU-vs-DUT comparison only after the Chisel top emits real +10. Full QEMU-vs-DUT comparison only after the Chisel top emits real architectural commit rows. -18. `gfsim -f ` only after the same ELF passed QEMU in the same run packet. +11. `gfsim -f ` only after the same ELF passed QEMU in the same run packet. ## Project Maintenance diff --git a/docs/chisel/generated/simulation-artifact-baseline.json b/docs/chisel/generated/simulation-artifact-baseline.json new file mode 100644 index 00000000..2e898fb5 --- /dev/null +++ b/docs/chisel/generated/simulation-artifact-baseline.json @@ -0,0 +1,65 @@ +{ + "schema": "linxcore.chisel.simulation_artifact_baseline.v1", + "suite": "OOOD3ContinuousPrefixSpec", + "case": "W8 publishes one retained D3 transaction as three three two", + "captured_date": "2026-08-03", + "main_profile": { + "git_sha": "356cf3c30a994bc0f5e6831c970ccce3a67886e5", + "profile_blob_sha": "938dae98ebe8ddf0de3f6872892b8558fb4949b3", + "elapsed_seconds": 30081.0, + "peak_rss_bytes": 13421772800, + "peak_rss_sampled": true, + "generated_bytes": 4190280746, + "generated_line_count": 28410225, + "largest_files": [ + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec//workdir-verilator/verilated-sources/VsvsimTestbench___024root__*.cpp", + "bytes": 957777535 + }, + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec//primary-sources/PRename.sv", + "bytes": 781469347 + } + ] + }, + "simulation_profile": { + "git_sha": "356cf3c30a994bc0f5e6831c970ccce3a67886e5", + "profile_blob_sha": "d562144316a1d4fd6201226d18d20a1a62f181de", + "elapsed_seconds": 207.461, + "peak_rss_bytes": 9084649472, + "generated_bytes": 802543964, + "generated_line_count": 5264397, + "largest_files": [ + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec/W8-publishes-one-retained-D3-transaction-as-three-three-two/workdir-verilator/verilated-sources/VsvsimTestbench___024root__15.cpp", + "bytes": 128722490 + }, + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec/W8-publishes-one-retained-D3-transaction-as-three-three-two/primary-sources/TURename.sv", + "bytes": 81569666 + }, + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec/W8-publishes-one-retained-D3-transaction-as-three-three-two/primary-sources/PRename.sv", + "bytes": 66728978 + }, + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec/W8-publishes-one-retained-D3-transaction-as-three-three-two/workdir-verilator/verilated-sources/VsvsimTestbench___024root__17.cpp", + "bytes": 59829883 + }, + { + "path": "chisel/build/chiselsim/OOOD3ContinuousPrefixSpec/W8-publishes-one-retained-D3-transaction-as-three-three-two/workdir-verilator/verilated-sources/VsvsimTestbench__pch.h.slow.gch", + "bytes": 48744744 + } + ] + }, + "reduction": { + "elapsed_percent": 99.310325, + "generated_bytes_percent": 80.847489, + "generated_line_count_percent": 81.470062 + }, + "result_parity": { + "passed": true, + "tail_transitions": [3, 6, 8], + "published_lanes": 8 + } +} diff --git a/docs/chisel/generated/top-interface-manifest.json b/docs/chisel/generated/top-interface-manifest.json new file mode 100644 index 00000000..04f31e22 --- /dev/null +++ b/docs/chisel/generated/top-interface-manifest.json @@ -0,0 +1 @@ +{"schema":1,"profiles":[{"name":"W2","width":2,"endpoints":[{"name":"top_io","contract_id":"IFC-TOP-EXT-002","producer":"Platform","consumer":"TOP","lanes":1,"payload":"TOPIO","ports":[{"name":"bootstrapComplete","width":1},{"name":"bootstrapReady","width":1},{"name":"cmdIssue_bits_instruction_epoch","width":16},{"name":"cmdIssue_bits_instruction_instructionId","width":64},{"name":"cmdIssue_bits_instruction_peId","width":8},{"name":"cmdIssue_bits_instruction_stid","width":1},{"name":"cmdIssue_bits_opcode","width":12},{"name":"cmdIssue_bits_rob_bid","width":8},{"name":"cmdIssue_bits_rob_brobGeneration","width":16},{"name":"cmdIssue_bits_rob_memberIndex","width":2},{"name":"cmdIssue_bits_rob_peId","width":8},{"name":"cmdIssue_bits_rob_residentGeneration","width":16},{"name":"cmdIssue_bits_rob_ridGeneration","width":16},{"name":"cmdIssue_bits_rob_ridSlot","width":6},{"name":"cmdIssue_bits_rob_stid","width":1},{"name":"cmdIssue_bits_sourceValid","width":4},{"name":"cmdIssue_bits_sourceValues_0","width":64},{"name":"cmdIssue_bits_sourceValues_1","width":64},{"name":"cmdIssue_bits_sourceValues_2","width":64},{"name":"cmdIssue_bits_sourceValues_3","width":64},{"name":"cmdIssue_bits_transactionId","width":64},{"name":"cmdIssue_ready","width":1},{"name":"cmdIssue_valid","width":1},{"name":"commit_bits_count","width":2},{"name":"commit_bits_entries_0_destination_atag","width":6},{"name":"commit_bits_entries_0_destination_kind","width":3},{"name":"commit_bits_entries_0_destination_pGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPtag","width":7},{"name":"commit_bits_entries_0_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousTtag","width":5},{"name":"commit_bits_entries_0_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousUtag","width":5},{"name":"commit_bits_entries_0_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_0_destination_ptag","width":7},{"name":"commit_bits_entries_0_destination_ptagValid","width":1},{"name":"commit_bits_entries_0_destination_tGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_ttag","width":5},{"name":"commit_bits_entries_0_destination_ttagValid","width":1},{"name":"commit_bits_entries_0_destination_uGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_utag","width":5},{"name":"commit_bits_entries_0_destination_utagValid","width":1},{"name":"commit_bits_entries_0_destination_valid","width":1},{"name":"commit_bits_entries_0_instruction_epoch","width":16},{"name":"commit_bits_entries_0_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_instruction_peId","width":8},{"name":"commit_bits_entries_0_instruction_stid","width":1},{"name":"commit_bits_entries_0_instructionBits","width":64},{"name":"commit_bits_entries_0_instructionLengthBytes","width":4},{"name":"commit_bits_entries_0_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_0_memory_lsid","width":32},{"name":"commit_bits_entries_0_memory_pipeId","width":1},{"name":"commit_bits_entries_0_memory_rob_bid","width":8},{"name":"commit_bits_entries_0_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_memory_rob_peId","width":8},{"name":"commit_bits_entries_0_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_memory_rob_stid","width":1},{"name":"commit_bits_entries_0_memory_transaction_generation","width":16},{"name":"commit_bits_entries_0_memory_transaction_value","width":64},{"name":"commit_bits_entries_0_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_0_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_0_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_0_memoryStore","width":1},{"name":"commit_bits_entries_0_memoryValid","width":1},{"name":"commit_bits_entries_0_opcode","width":12},{"name":"commit_bits_entries_0_pc","width":64},{"name":"commit_bits_entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_0_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_0_result","width":64},{"name":"commit_bits_entries_0_resultValid","width":1},{"name":"commit_bits_entries_0_rob_bid","width":8},{"name":"commit_bits_entries_0_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_rob_peId","width":8},{"name":"commit_bits_entries_0_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_rob_stid","width":1},{"name":"commit_bits_entries_0_robGroupLast","width":1},{"name":"commit_bits_entries_0_storeData","width":64},{"name":"commit_bits_entries_0_storeMask","width":8},{"name":"commit_bits_entries_0_trap_cause","width":32},{"name":"commit_bits_entries_0_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_0_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_trap_instruction_peId","width":8},{"name":"commit_bits_entries_0_trap_instruction_stid","width":1},{"name":"commit_bits_entries_0_trap_kind","width":2},{"name":"commit_bits_entries_0_trap_rob_bid","width":8},{"name":"commit_bits_entries_0_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_trap_rob_peId","width":8},{"name":"commit_bits_entries_0_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_trap_rob_stid","width":1},{"name":"commit_bits_entries_0_trap_targetPc","width":64},{"name":"commit_bits_entries_0_trap_tval","width":64},{"name":"commit_bits_entries_0_trap_valid","width":1},{"name":"commit_bits_entries_1_destination_atag","width":6},{"name":"commit_bits_entries_1_destination_kind","width":3},{"name":"commit_bits_entries_1_destination_pGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPtag","width":7},{"name":"commit_bits_entries_1_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousTtag","width":5},{"name":"commit_bits_entries_1_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousUtag","width":5},{"name":"commit_bits_entries_1_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_1_destination_ptag","width":7},{"name":"commit_bits_entries_1_destination_ptagValid","width":1},{"name":"commit_bits_entries_1_destination_tGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_ttag","width":5},{"name":"commit_bits_entries_1_destination_ttagValid","width":1},{"name":"commit_bits_entries_1_destination_uGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_utag","width":5},{"name":"commit_bits_entries_1_destination_utagValid","width":1},{"name":"commit_bits_entries_1_destination_valid","width":1},{"name":"commit_bits_entries_1_instruction_epoch","width":16},{"name":"commit_bits_entries_1_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_instruction_peId","width":8},{"name":"commit_bits_entries_1_instruction_stid","width":1},{"name":"commit_bits_entries_1_instructionBits","width":64},{"name":"commit_bits_entries_1_instructionLengthBytes","width":4},{"name":"commit_bits_entries_1_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_1_memory_lsid","width":32},{"name":"commit_bits_entries_1_memory_pipeId","width":1},{"name":"commit_bits_entries_1_memory_rob_bid","width":8},{"name":"commit_bits_entries_1_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_memory_rob_peId","width":8},{"name":"commit_bits_entries_1_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_memory_rob_stid","width":1},{"name":"commit_bits_entries_1_memory_transaction_generation","width":16},{"name":"commit_bits_entries_1_memory_transaction_value","width":64},{"name":"commit_bits_entries_1_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_1_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_1_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_1_memoryStore","width":1},{"name":"commit_bits_entries_1_memoryValid","width":1},{"name":"commit_bits_entries_1_opcode","width":12},{"name":"commit_bits_entries_1_pc","width":64},{"name":"commit_bits_entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_1_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_1_result","width":64},{"name":"commit_bits_entries_1_resultValid","width":1},{"name":"commit_bits_entries_1_rob_bid","width":8},{"name":"commit_bits_entries_1_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_rob_peId","width":8},{"name":"commit_bits_entries_1_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_rob_stid","width":1},{"name":"commit_bits_entries_1_robGroupLast","width":1},{"name":"commit_bits_entries_1_storeData","width":64},{"name":"commit_bits_entries_1_storeMask","width":8},{"name":"commit_bits_entries_1_trap_cause","width":32},{"name":"commit_bits_entries_1_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_1_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_trap_instruction_peId","width":8},{"name":"commit_bits_entries_1_trap_instruction_stid","width":1},{"name":"commit_bits_entries_1_trap_kind","width":2},{"name":"commit_bits_entries_1_trap_rob_bid","width":8},{"name":"commit_bits_entries_1_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_trap_rob_peId","width":8},{"name":"commit_bits_entries_1_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_trap_rob_stid","width":1},{"name":"commit_bits_entries_1_trap_targetPc","width":64},{"name":"commit_bits_entries_1_trap_tval","width":64},{"name":"commit_bits_entries_1_trap_valid","width":1},{"name":"commit_ready","width":1},{"name":"commit_valid","width":1},{"name":"dataMemoryRequest_0_bits_accessKind","width":2},{"name":"dataMemoryRequest_0_bits_address","width":64},{"name":"dataMemoryRequest_0_bits_byteMask","width":8},{"name":"dataMemoryRequest_0_bits_command","width":3},{"name":"dataMemoryRequest_0_bits_data","width":64},{"name":"dataMemoryRequest_0_bits_identity_generation","width":16},{"name":"dataMemoryRequest_0_bits_identity_value","width":64},{"name":"dataMemoryRequest_0_bits_instructionSide","width":1},{"name":"dataMemoryRequest_0_bits_size","width":3},{"name":"dataMemoryRequest_0_ready","width":1},{"name":"dataMemoryRequest_0_valid","width":1},{"name":"dataMemoryRequest_1_bits_accessKind","width":2},{"name":"dataMemoryRequest_1_bits_address","width":64},{"name":"dataMemoryRequest_1_bits_byteMask","width":8},{"name":"dataMemoryRequest_1_bits_command","width":3},{"name":"dataMemoryRequest_1_bits_data","width":64},{"name":"dataMemoryRequest_1_bits_identity_generation","width":16},{"name":"dataMemoryRequest_1_bits_identity_value","width":64},{"name":"dataMemoryRequest_1_bits_instructionSide","width":1},{"name":"dataMemoryRequest_1_bits_size","width":3},{"name":"dataMemoryRequest_1_ready","width":1},{"name":"dataMemoryRequest_1_valid","width":1},{"name":"dataMemoryRequest_2_bits_accessKind","width":2},{"name":"dataMemoryRequest_2_bits_address","width":64},{"name":"dataMemoryRequest_2_bits_byteMask","width":8},{"name":"dataMemoryRequest_2_bits_command","width":3},{"name":"dataMemoryRequest_2_bits_data","width":64},{"name":"dataMemoryRequest_2_bits_identity_generation","width":16},{"name":"dataMemoryRequest_2_bits_identity_value","width":64},{"name":"dataMemoryRequest_2_bits_instructionSide","width":1},{"name":"dataMemoryRequest_2_bits_size","width":3},{"name":"dataMemoryRequest_2_ready","width":1},{"name":"dataMemoryRequest_2_valid","width":1},{"name":"dataMemoryRequest_3_bits_accessKind","width":2},{"name":"dataMemoryRequest_3_bits_address","width":64},{"name":"dataMemoryRequest_3_bits_byteMask","width":8},{"name":"dataMemoryRequest_3_bits_command","width":3},{"name":"dataMemoryRequest_3_bits_data","width":64},{"name":"dataMemoryRequest_3_bits_identity_generation","width":16},{"name":"dataMemoryRequest_3_bits_identity_value","width":64},{"name":"dataMemoryRequest_3_bits_instructionSide","width":1},{"name":"dataMemoryRequest_3_bits_size","width":3},{"name":"dataMemoryRequest_3_ready","width":1},{"name":"dataMemoryRequest_3_valid","width":1},{"name":"dataMemoryResponse_0_bits_address","width":64},{"name":"dataMemoryResponse_0_bits_attributesValid","width":1},{"name":"dataMemoryResponse_0_bits_cacheable","width":1},{"name":"dataMemoryResponse_0_bits_corrupt","width":1},{"name":"dataMemoryResponse_0_bits_data","width":64},{"name":"dataMemoryResponse_0_bits_denied","width":1},{"name":"dataMemoryResponse_0_bits_device","width":1},{"name":"dataMemoryResponse_0_bits_errorCause","width":32},{"name":"dataMemoryResponse_0_bits_identity_generation","width":16},{"name":"dataMemoryResponse_0_bits_identity_value","width":64},{"name":"dataMemoryResponse_0_bits_lineData","width":512},{"name":"dataMemoryResponse_0_bits_readable","width":1},{"name":"dataMemoryResponse_0_bits_writable","width":1},{"name":"dataMemoryResponse_0_ready","width":1},{"name":"dataMemoryResponse_0_valid","width":1},{"name":"dataMemoryResponse_1_bits_address","width":64},{"name":"dataMemoryResponse_1_bits_attributesValid","width":1},{"name":"dataMemoryResponse_1_bits_cacheable","width":1},{"name":"dataMemoryResponse_1_bits_corrupt","width":1},{"name":"dataMemoryResponse_1_bits_data","width":64},{"name":"dataMemoryResponse_1_bits_denied","width":1},{"name":"dataMemoryResponse_1_bits_device","width":1},{"name":"dataMemoryResponse_1_bits_errorCause","width":32},{"name":"dataMemoryResponse_1_bits_identity_generation","width":16},{"name":"dataMemoryResponse_1_bits_identity_value","width":64},{"name":"dataMemoryResponse_1_bits_lineData","width":512},{"name":"dataMemoryResponse_1_bits_readable","width":1},{"name":"dataMemoryResponse_1_bits_writable","width":1},{"name":"dataMemoryResponse_1_ready","width":1},{"name":"dataMemoryResponse_1_valid","width":1},{"name":"dataMemoryResponse_2_bits_address","width":64},{"name":"dataMemoryResponse_2_bits_attributesValid","width":1},{"name":"dataMemoryResponse_2_bits_cacheable","width":1},{"name":"dataMemoryResponse_2_bits_corrupt","width":1},{"name":"dataMemoryResponse_2_bits_data","width":64},{"name":"dataMemoryResponse_2_bits_denied","width":1},{"name":"dataMemoryResponse_2_bits_device","width":1},{"name":"dataMemoryResponse_2_bits_errorCause","width":32},{"name":"dataMemoryResponse_2_bits_identity_generation","width":16},{"name":"dataMemoryResponse_2_bits_identity_value","width":64},{"name":"dataMemoryResponse_2_bits_lineData","width":512},{"name":"dataMemoryResponse_2_bits_readable","width":1},{"name":"dataMemoryResponse_2_bits_writable","width":1},{"name":"dataMemoryResponse_2_ready","width":1},{"name":"dataMemoryResponse_2_valid","width":1},{"name":"dataMemoryResponse_3_bits_address","width":64},{"name":"dataMemoryResponse_3_bits_attributesValid","width":1},{"name":"dataMemoryResponse_3_bits_cacheable","width":1},{"name":"dataMemoryResponse_3_bits_corrupt","width":1},{"name":"dataMemoryResponse_3_bits_data","width":64},{"name":"dataMemoryResponse_3_bits_denied","width":1},{"name":"dataMemoryResponse_3_bits_device","width":1},{"name":"dataMemoryResponse_3_bits_errorCause","width":32},{"name":"dataMemoryResponse_3_bits_identity_generation","width":16},{"name":"dataMemoryResponse_3_bits_identity_value","width":64},{"name":"dataMemoryResponse_3_bits_lineData","width":512},{"name":"dataMemoryResponse_3_bits_readable","width":1},{"name":"dataMemoryResponse_3_bits_writable","width":1},{"name":"dataMemoryResponse_3_ready","width":1},{"name":"dataMemoryResponse_3_valid","width":1},{"name":"debugRequest_bits_address","width":64},{"name":"debugRequest_bits_command","width":3},{"name":"debugRequest_bits_data","width":64},{"name":"debugRequest_bits_stid","width":1},{"name":"debugRequest_bits_transactionId","width":64},{"name":"debugRequest_ready","width":1},{"name":"debugRequest_valid","width":1},{"name":"debugResponse_bits_accepted","width":1},{"name":"debugResponse_bits_data","width":64},{"name":"debugResponse_bits_error","width":1},{"name":"debugResponse_bits_transactionId","width":64},{"name":"debugResponse_ready","width":1},{"name":"debugResponse_valid","width":1},{"name":"instructionMemoryRequest_bits_accessKind","width":2},{"name":"instructionMemoryRequest_bits_address","width":64},{"name":"instructionMemoryRequest_bits_byteMask","width":8},{"name":"instructionMemoryRequest_bits_command","width":3},{"name":"instructionMemoryRequest_bits_data","width":64},{"name":"instructionMemoryRequest_bits_identity_generation","width":16},{"name":"instructionMemoryRequest_bits_identity_value","width":64},{"name":"instructionMemoryRequest_bits_instructionSide","width":1},{"name":"instructionMemoryRequest_bits_size","width":3},{"name":"instructionMemoryRequest_ready","width":1},{"name":"instructionMemoryRequest_valid","width":1},{"name":"instructionMemoryResponse_bits_address","width":64},{"name":"instructionMemoryResponse_bits_attributesValid","width":1},{"name":"instructionMemoryResponse_bits_cacheable","width":1},{"name":"instructionMemoryResponse_bits_corrupt","width":1},{"name":"instructionMemoryResponse_bits_data","width":64},{"name":"instructionMemoryResponse_bits_denied","width":1},{"name":"instructionMemoryResponse_bits_device","width":1},{"name":"instructionMemoryResponse_bits_errorCause","width":32},{"name":"instructionMemoryResponse_bits_identity_generation","width":16},{"name":"instructionMemoryResponse_bits_identity_value","width":64},{"name":"instructionMemoryResponse_bits_lineData","width":512},{"name":"instructionMemoryResponse_bits_readable","width":1},{"name":"instructionMemoryResponse_bits_writable","width":1},{"name":"instructionMemoryResponse_ready","width":1},{"name":"instructionMemoryResponse_valid","width":1},{"name":"interrupt_bits_cause","width":32},{"name":"interrupt_bits_priority","width":8},{"name":"interrupt_bits_stid","width":1},{"name":"interrupt_bits_valid","width":1},{"name":"interrupt_valid","width":1},{"name":"loadReissueRequest_bits_address","width":64},{"name":"loadReissueRequest_bits_allocationId_generation","width":16},{"name":"loadReissueRequest_bits_allocationId_value","width":64},{"name":"loadReissueRequest_bits_currentIdentity_attemptGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_lsid","width":32},{"name":"loadReissueRequest_bits_currentIdentity_pipeId","width":1},{"name":"loadReissueRequest_bits_currentIdentity_rob_bid","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_brobGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_memberIndex","width":2},{"name":"loadReissueRequest_bits_currentIdentity_rob_peId","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_residentGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridSlot","width":6},{"name":"loadReissueRequest_bits_currentIdentity_rob_stid","width":1},{"name":"loadReissueRequest_bits_currentIdentity_transaction_generation","width":16},{"name":"loadReissueRequest_bits_currentIdentity_transaction_value","width":64},{"name":"loadReissueRequest_ready","width":1},{"name":"loadReissueRequest_valid","width":1},{"name":"lsuProtocolError","width":1},{"name":"lsuQuiescent","width":1},{"name":"maintenance_bits_address","width":64},{"name":"maintenance_bits_command","width":2},{"name":"maintenance_ready","width":1},{"name":"maintenance_valid","width":1},{"name":"maintenanceResult_bits_address","width":64},{"name":"maintenanceResult_bits_command","width":2},{"name":"maintenanceResult_bits_success","width":1},{"name":"maintenanceResult_ready","width":1},{"name":"maintenanceResult_valid","width":1},{"name":"memoryFault_bits_address","width":64},{"name":"memoryFault_bits_cause","width":1},{"name":"memoryFault_bits_identity_attemptGeneration","width":16},{"name":"memoryFault_bits_identity_lsid","width":32},{"name":"memoryFault_bits_identity_pipeId","width":1},{"name":"memoryFault_bits_identity_rob_bid","width":8},{"name":"memoryFault_bits_identity_rob_brobGeneration","width":16},{"name":"memoryFault_bits_identity_rob_memberIndex","width":2},{"name":"memoryFault_bits_identity_rob_peId","width":8},{"name":"memoryFault_bits_identity_rob_residentGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridSlot","width":6},{"name":"memoryFault_bits_identity_rob_stid","width":1},{"name":"memoryFault_bits_identity_transaction_generation","width":16},{"name":"memoryFault_bits_identity_transaction_value","width":64},{"name":"memoryFault_bits_write","width":1},{"name":"memoryFault_ready","width":1},{"name":"memoryFault_valid","width":1},{"name":"pInit_bits_atag","width":5},{"name":"pInit_bits_epoch","width":16},{"name":"pInit_bits_generation","width":16},{"name":"pInit_bits_ptag","width":7},{"name":"pInit_bits_stid","width":1},{"name":"pInit_bits_value","width":64},{"name":"pInit_ready","width":1},{"name":"pInit_valid","width":1},{"name":"performanceCounters_0","width":64},{"name":"performanceCounters_1","width":64},{"name":"performanceCounters_2","width":64},{"name":"performanceCounters_3","width":64},{"name":"performanceCounters_4","width":64},{"name":"performanceCounters_5","width":64},{"name":"performanceCounters_6","width":64},{"name":"performanceCounters_7","width":64},{"name":"performanceCounters_8","width":64},{"name":"performanceCounters_9","width":64},{"name":"performanceCounters_10","width":64},{"name":"performanceCounters_11","width":64},{"name":"performanceCounters_12","width":64},{"name":"performanceCounters_13","width":64},{"name":"performanceCounters_14","width":64},{"name":"performanceCounters_15","width":64},{"name":"performanceCounters_16","width":64},{"name":"performanceCounters_17","width":64},{"name":"performanceCounters_18","width":64},{"name":"performanceCounters_19","width":64},{"name":"performanceCounters_20","width":64},{"name":"performanceCounters_21","width":64},{"name":"performanceCounters_22","width":64},{"name":"performanceCounters_23","width":64},{"name":"performanceCounters_24","width":64},{"name":"performanceCounters_25","width":64},{"name":"performanceCounters_26","width":64},{"name":"performanceCounters_27","width":64},{"name":"performanceCounters_28","width":64},{"name":"performanceCounters_29","width":64},{"name":"performanceCounters_30","width":64},{"name":"performanceCounters_31","width":64},{"name":"systemIssue_0_bits_immediate","width":64},{"name":"systemIssue_0_bits_instruction_epoch","width":16},{"name":"systemIssue_0_bits_instruction_instructionId","width":64},{"name":"systemIssue_0_bits_instruction_peId","width":8},{"name":"systemIssue_0_bits_instruction_stid","width":1},{"name":"systemIssue_0_bits_opcode","width":12},{"name":"systemIssue_0_bits_rob_bid","width":8},{"name":"systemIssue_0_bits_rob_brobGeneration","width":16},{"name":"systemIssue_0_bits_rob_memberIndex","width":2},{"name":"systemIssue_0_bits_rob_peId","width":8},{"name":"systemIssue_0_bits_rob_residentGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridSlot","width":6},{"name":"systemIssue_0_bits_rob_stid","width":1},{"name":"systemIssue_0_bits_transactionId","width":64},{"name":"systemIssue_0_ready","width":1},{"name":"systemIssue_0_valid","width":1},{"name":"trace_bits_count","width":2},{"name":"trace_bits_entries_0_cycle","width":64},{"name":"trace_bits_entries_0_instruction_epoch","width":16},{"name":"trace_bits_entries_0_instruction_instructionId","width":64},{"name":"trace_bits_entries_0_instruction_peId","width":8},{"name":"trace_bits_entries_0_instruction_stid","width":1},{"name":"trace_bits_entries_0_instructionValid","width":1},{"name":"trace_bits_entries_0_kind","width":3},{"name":"trace_bits_entries_0_opcode","width":12},{"name":"trace_bits_entries_0_payload","width":64},{"name":"trace_bits_entries_0_pc","width":64},{"name":"trace_bits_entries_0_rob_bid","width":8},{"name":"trace_bits_entries_0_rob_brobGeneration","width":16},{"name":"trace_bits_entries_0_rob_memberIndex","width":2},{"name":"trace_bits_entries_0_rob_peId","width":8},{"name":"trace_bits_entries_0_rob_residentGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridSlot","width":6},{"name":"trace_bits_entries_0_rob_stid","width":1},{"name":"trace_bits_entries_0_robValid","width":1},{"name":"trace_bits_entries_0_source","width":3},{"name":"trace_bits_entries_1_cycle","width":64},{"name":"trace_bits_entries_1_instruction_epoch","width":16},{"name":"trace_bits_entries_1_instruction_instructionId","width":64},{"name":"trace_bits_entries_1_instruction_peId","width":8},{"name":"trace_bits_entries_1_instruction_stid","width":1},{"name":"trace_bits_entries_1_instructionValid","width":1},{"name":"trace_bits_entries_1_kind","width":3},{"name":"trace_bits_entries_1_opcode","width":12},{"name":"trace_bits_entries_1_payload","width":64},{"name":"trace_bits_entries_1_pc","width":64},{"name":"trace_bits_entries_1_rob_bid","width":8},{"name":"trace_bits_entries_1_rob_brobGeneration","width":16},{"name":"trace_bits_entries_1_rob_memberIndex","width":2},{"name":"trace_bits_entries_1_rob_peId","width":8},{"name":"trace_bits_entries_1_rob_residentGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridSlot","width":6},{"name":"trace_bits_entries_1_rob_stid","width":1},{"name":"trace_bits_entries_1_robValid","width":1},{"name":"trace_bits_entries_1_source","width":3},{"name":"trace_ready","width":1},{"name":"trace_valid","width":1},{"name":"trap_bits_cause","width":32},{"name":"trap_bits_instruction_epoch","width":16},{"name":"trap_bits_instruction_instructionId","width":64},{"name":"trap_bits_instruction_peId","width":8},{"name":"trap_bits_instruction_stid","width":1},{"name":"trap_bits_kind","width":2},{"name":"trap_bits_rob_bid","width":8},{"name":"trap_bits_rob_brobGeneration","width":16},{"name":"trap_bits_rob_memberIndex","width":2},{"name":"trap_bits_rob_peId","width":8},{"name":"trap_bits_rob_residentGeneration","width":16},{"name":"trap_bits_rob_ridGeneration","width":16},{"name":"trap_bits_rob_ridSlot","width":6},{"name":"trap_bits_rob_stid","width":1},{"name":"trap_bits_targetPc","width":64},{"name":"trap_bits_tval","width":64},{"name":"trap_bits_valid","width":1},{"name":"trap_ready","width":1},{"name":"trap_valid","width":1}]},{"name":"ifu_to_ctu","contract_id":"IFC-IFU-CTU-001","producer":"IFU","consumer":"CTU","lanes":2,"payload":"FetchedPacket","ports":[{"name":"count","width":2},{"name":"entries_0_fetchFault","width":1},{"name":"entries_0_fetchFaultCause","width":32},{"name":"entries_0_identity_epoch","width":16},{"name":"entries_0_identity_instructionId","width":64},{"name":"entries_0_identity_peId","width":8},{"name":"entries_0_identity_stid","width":1},{"name":"entries_0_instruction","width":64},{"name":"entries_0_lengthBytes","width":4},{"name":"entries_0_pc","width":64},{"name":"entries_0_prediction_checkpointId","width":5},{"name":"entries_0_prediction_confidence","width":2},{"name":"entries_0_prediction_epoch","width":16},{"name":"entries_0_prediction_fallthroughPc","width":64},{"name":"entries_0_prediction_kind","width":3},{"name":"entries_0_prediction_predictionTag","width":64},{"name":"entries_0_prediction_provider","width":4},{"name":"entries_0_prediction_requestPc","width":64},{"name":"entries_0_prediction_taken","width":1},{"name":"entries_0_prediction_target","width":64},{"name":"entries_0_prediction_transactionId","width":64},{"name":"entries_0_prediction_valid","width":1},{"name":"entries_1_fetchFault","width":1},{"name":"entries_1_fetchFaultCause","width":32},{"name":"entries_1_identity_epoch","width":16},{"name":"entries_1_identity_instructionId","width":64},{"name":"entries_1_identity_peId","width":8},{"name":"entries_1_identity_stid","width":1},{"name":"entries_1_instruction","width":64},{"name":"entries_1_lengthBytes","width":4},{"name":"entries_1_pc","width":64},{"name":"entries_1_prediction_checkpointId","width":5},{"name":"entries_1_prediction_confidence","width":2},{"name":"entries_1_prediction_epoch","width":16},{"name":"entries_1_prediction_fallthroughPc","width":64},{"name":"entries_1_prediction_kind","width":3},{"name":"entries_1_prediction_predictionTag","width":64},{"name":"entries_1_prediction_provider","width":4},{"name":"entries_1_prediction_requestPc","width":64},{"name":"entries_1_prediction_taken","width":1},{"name":"entries_1_prediction_target","width":64},{"name":"entries_1_prediction_transactionId","width":64},{"name":"entries_1_prediction_valid","width":1}]},{"name":"ctu_to_ooo","contract_id":"IFC-CTU-OOO-001","producer":"CTU","consumer":"OOO","lanes":2,"payload":"D1Packet","ports":[{"name":"count","width":2},{"name":"entries_0_kind","width":1},{"name":"entries_0_parent_fetchFault","width":1},{"name":"entries_0_parent_fetchFaultCause","width":32},{"name":"entries_0_parent_identity_epoch","width":16},{"name":"entries_0_parent_identity_instructionId","width":64},{"name":"entries_0_parent_identity_peId","width":8},{"name":"entries_0_parent_identity_stid","width":1},{"name":"entries_0_parent_instruction","width":64},{"name":"entries_0_parent_lengthBytes","width":4},{"name":"entries_0_parent_pc","width":64},{"name":"entries_0_parent_prediction_checkpointId","width":5},{"name":"entries_0_parent_prediction_confidence","width":2},{"name":"entries_0_parent_prediction_epoch","width":16},{"name":"entries_0_parent_prediction_fallthroughPc","width":64},{"name":"entries_0_parent_prediction_kind","width":3},{"name":"entries_0_parent_prediction_predictionTag","width":64},{"name":"entries_0_parent_prediction_provider","width":4},{"name":"entries_0_parent_prediction_requestPc","width":64},{"name":"entries_0_parent_prediction_taken","width":1},{"name":"entries_0_parent_prediction_target","width":64},{"name":"entries_0_parent_prediction_transactionId","width":64},{"name":"entries_0_parent_prediction_valid","width":1},{"name":"entries_0_templateCount","width":8},{"name":"entries_0_templateImmediate","width":64},{"name":"entries_0_templateOpcode","width":12},{"name":"entries_0_templateOrdinal","width":8},{"name":"entries_1_kind","width":1},{"name":"entries_1_parent_fetchFault","width":1},{"name":"entries_1_parent_fetchFaultCause","width":32},{"name":"entries_1_parent_identity_epoch","width":16},{"name":"entries_1_parent_identity_instructionId","width":64},{"name":"entries_1_parent_identity_peId","width":8},{"name":"entries_1_parent_identity_stid","width":1},{"name":"entries_1_parent_instruction","width":64},{"name":"entries_1_parent_lengthBytes","width":4},{"name":"entries_1_parent_pc","width":64},{"name":"entries_1_parent_prediction_checkpointId","width":5},{"name":"entries_1_parent_prediction_confidence","width":2},{"name":"entries_1_parent_prediction_epoch","width":16},{"name":"entries_1_parent_prediction_fallthroughPc","width":64},{"name":"entries_1_parent_prediction_kind","width":3},{"name":"entries_1_parent_prediction_predictionTag","width":64},{"name":"entries_1_parent_prediction_provider","width":4},{"name":"entries_1_parent_prediction_requestPc","width":64},{"name":"entries_1_parent_prediction_taken","width":1},{"name":"entries_1_parent_prediction_target","width":64},{"name":"entries_1_parent_prediction_transactionId","width":64},{"name":"entries_1_parent_prediction_valid","width":1},{"name":"entries_1_templateCount","width":8},{"name":"entries_1_templateImmediate","width":64},{"name":"entries_1_templateOpcode","width":12},{"name":"entries_1_templateOrdinal","width":8}]},{"name":"ooo_to_iex_alu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":2},{"name":"uop_decoded_classification_dispatchDemand_1","width":2},{"name":"uop_decoded_classification_dispatchDemand_2","width":2},{"name":"uop_decoded_classification_dispatchDemand_3","width":2},{"name":"uop_decoded_classification_dispatchDemand_4","width":2},{"name":"uop_decoded_classification_dispatchDemand_5","width":2},{"name":"uop_decoded_classification_dispatchDemand_6","width":2},{"name":"uop_decoded_classification_dispatchDemand_7","width":2},{"name":"uop_decoded_classification_dispatchWrites","width":2},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_bru","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":2},{"name":"uop_decoded_classification_dispatchDemand_1","width":2},{"name":"uop_decoded_classification_dispatchDemand_2","width":2},{"name":"uop_decoded_classification_dispatchDemand_3","width":2},{"name":"uop_decoded_classification_dispatchDemand_4","width":2},{"name":"uop_decoded_classification_dispatchDemand_5","width":2},{"name":"uop_decoded_classification_dispatchDemand_6","width":2},{"name":"uop_decoded_classification_dispatchDemand_7","width":2},{"name":"uop_decoded_classification_dispatchWrites","width":2},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_agu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":2},{"name":"uop_decoded_classification_dispatchDemand_1","width":2},{"name":"uop_decoded_classification_dispatchDemand_2","width":2},{"name":"uop_decoded_classification_dispatchDemand_3","width":2},{"name":"uop_decoded_classification_dispatchDemand_4","width":2},{"name":"uop_decoded_classification_dispatchDemand_5","width":2},{"name":"uop_decoded_classification_dispatchDemand_6","width":2},{"name":"uop_decoded_classification_dispatchDemand_7","width":2},{"name":"uop_decoded_classification_dispatchWrites","width":2},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_std","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"StoreDispatchTxn","ports":[{"name":"aguPipe","width":1},{"name":"sta_memoryOrder_firstLid","width":32},{"name":"sta_memoryOrder_firstLsid","width":32},{"name":"sta_memoryOrder_firstSid","width":32},{"name":"sta_memoryOrder_requestCount","width":2},{"name":"sta_memoryOrder_yoldLid","width":32},{"name":"sta_memoryOrder_yoldLsid","width":32},{"name":"sta_memoryOrder_yoldValid","width":1},{"name":"sta_memoryOrder_yostLsid","width":32},{"name":"sta_memoryOrder_yostSid","width":32},{"name":"sta_memoryOrder_yostValid","width":1},{"name":"sta_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"sta_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"sta_pcBufferIndexOffset_pcOffset","width":7},{"name":"sta_pcBufferIndexOffset_valid","width":1},{"name":"sta_transactionId","width":64},{"name":"sta_trap_cause","width":32},{"name":"sta_trap_valid","width":1},{"name":"sta_uop_decoded_blockBoundary","width":1},{"name":"sta_uop_decoded_blockStart","width":1},{"name":"sta_uop_decoded_blockStop","width":1},{"name":"sta_uop_decoded_classification_complexBreak","width":1},{"name":"sta_uop_decoded_classification_dispatchClass","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_0","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_1","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_2","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_3","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_4","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_5","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_6","width":2},{"name":"sta_uop_decoded_classification_dispatchDemand_7","width":2},{"name":"sta_uop_decoded_classification_dispatchWrites","width":2},{"name":"sta_uop_decoded_classification_disposition","width":2},{"name":"sta_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"sta_uop_decoded_classification_fastResolveClass","width":3},{"name":"sta_uop_decoded_classification_fusionHeadClass","width":2},{"name":"sta_uop_decoded_classification_fusionTailClass","width":2},{"name":"sta_uop_decoded_classification_implicitDestination","width":2},{"name":"sta_uop_decoded_classification_implicitSourceMask","width":4},{"name":"sta_uop_decoded_classification_kind","width":4},{"name":"sta_uop_decoded_classification_mayRedirect","width":1},{"name":"sta_uop_decoded_classification_mayTrap","width":1},{"name":"sta_uop_decoded_classification_mayTrapLate","width":1},{"name":"sta_uop_decoded_classification_memoryRequestCount","width":2},{"name":"sta_uop_decoded_classification_nonspeculative","width":1},{"name":"sta_uop_decoded_classification_pDestinationCount","width":2},{"name":"sta_uop_decoded_classification_pSourceCount","width":3},{"name":"sta_uop_decoded_classification_pcReadClass","width":4},{"name":"sta_uop_decoded_classification_pcReadRequired","width":1},{"name":"sta_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"sta_uop_decoded_classification_sideEffectOwner","width":3},{"name":"sta_uop_decoded_classification_splitKind","width":2},{"name":"sta_uop_decoded_classification_tAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uopCountMax","width":6},{"name":"sta_uop_decoded_classification_uopCountMin","width":6},{"name":"sta_uop_decoded_classification_valid","width":1},{"name":"sta_uop_decoded_destinations_0_atag","width":6},{"name":"sta_uop_decoded_destinations_0_kind","width":3},{"name":"sta_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_0_valid","width":1},{"name":"sta_uop_decoded_destinations_1_atag","width":6},{"name":"sta_uop_decoded_destinations_1_kind","width":3},{"name":"sta_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_1_valid","width":1},{"name":"sta_uop_decoded_earlyComplete","width":1},{"name":"sta_uop_decoded_immediate","width":64},{"name":"sta_uop_decoded_immediateValid","width":1},{"name":"sta_uop_decoded_instruction_kind","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"sta_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"sta_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"sta_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"sta_uop_decoded_instruction_parent_instruction","width":64},{"name":"sta_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"sta_uop_decoded_instruction_parent_pc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"sta_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"sta_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"sta_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"sta_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"sta_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"sta_uop_decoded_instruction_templateCount","width":8},{"name":"sta_uop_decoded_instruction_templateImmediate","width":64},{"name":"sta_uop_decoded_instruction_templateOpcode","width":12},{"name":"sta_uop_decoded_instruction_templateOrdinal","width":8},{"name":"sta_uop_decoded_memory_accessBytes","width":4},{"name":"sta_uop_decoded_memory_addressMode","width":2},{"name":"sta_uop_decoded_memory_addressSourceMask","width":4},{"name":"sta_uop_decoded_memory_dataSourceMask","width":4},{"name":"sta_uop_decoded_memory_indexMode","width":2},{"name":"sta_uop_decoded_memory_indexShift","width":5},{"name":"sta_uop_decoded_memory_isLoad","width":1},{"name":"sta_uop_decoded_memory_isStore","width":1},{"name":"sta_uop_decoded_memory_offset","width":64},{"name":"sta_uop_decoded_memory_requestCount","width":2},{"name":"sta_uop_decoded_memory_signExtend","width":1},{"name":"sta_uop_decoded_memory_valid","width":1},{"name":"sta_uop_decoded_memory_writebackPreIndex","width":1},{"name":"sta_uop_decoded_memory_writebackValid","width":1},{"name":"sta_uop_decoded_opcode","width":12},{"name":"sta_uop_decoded_rob_bid","width":8},{"name":"sta_uop_decoded_rob_brobGeneration","width":16},{"name":"sta_uop_decoded_rob_memberIndex","width":2},{"name":"sta_uop_decoded_rob_peId","width":8},{"name":"sta_uop_decoded_rob_residentGeneration","width":16},{"name":"sta_uop_decoded_rob_ridGeneration","width":16},{"name":"sta_uop_decoded_rob_ridSlot","width":6},{"name":"sta_uop_decoded_rob_stid","width":1},{"name":"sta_uop_decoded_sources_0_atag","width":6},{"name":"sta_uop_decoded_sources_0_kind","width":3},{"name":"sta_uop_decoded_sources_0_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_0_valid","width":1},{"name":"sta_uop_decoded_sources_1_atag","width":6},{"name":"sta_uop_decoded_sources_1_kind","width":3},{"name":"sta_uop_decoded_sources_1_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_1_valid","width":1},{"name":"sta_uop_decoded_sources_2_atag","width":6},{"name":"sta_uop_decoded_sources_2_kind","width":3},{"name":"sta_uop_decoded_sources_2_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_2_valid","width":1},{"name":"sta_uop_decoded_sources_3_atag","width":6},{"name":"sta_uop_decoded_sources_3_kind","width":3},{"name":"sta_uop_decoded_sources_3_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_3_valid","width":1},{"name":"sta_uop_decoded_uopClass","width":3},{"name":"sta_uop_decoded_valid","width":1},{"name":"sta_uop_destinations_0_atag","width":6},{"name":"sta_uop_destinations_0_kind","width":3},{"name":"sta_uop_destinations_0_pGeneration","width":16},{"name":"sta_uop_destinations_0_previousPGeneration","width":16},{"name":"sta_uop_destinations_0_previousPtag","width":7},{"name":"sta_uop_destinations_0_previousPtagValid","width":1},{"name":"sta_uop_destinations_0_previousTtag","width":5},{"name":"sta_uop_destinations_0_previousTtagValid","width":1},{"name":"sta_uop_destinations_0_previousUtag","width":5},{"name":"sta_uop_destinations_0_previousUtagValid","width":1},{"name":"sta_uop_destinations_0_ptag","width":7},{"name":"sta_uop_destinations_0_ptagValid","width":1},{"name":"sta_uop_destinations_0_tGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqIndex","width":5},{"name":"sta_uop_destinations_0_ttag","width":5},{"name":"sta_uop_destinations_0_ttagValid","width":1},{"name":"sta_uop_destinations_0_uGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqIndex","width":5},{"name":"sta_uop_destinations_0_utag","width":5},{"name":"sta_uop_destinations_0_utagValid","width":1},{"name":"sta_uop_destinations_0_valid","width":1},{"name":"sta_uop_destinations_1_atag","width":6},{"name":"sta_uop_destinations_1_kind","width":3},{"name":"sta_uop_destinations_1_pGeneration","width":16},{"name":"sta_uop_destinations_1_previousPGeneration","width":16},{"name":"sta_uop_destinations_1_previousPtag","width":7},{"name":"sta_uop_destinations_1_previousPtagValid","width":1},{"name":"sta_uop_destinations_1_previousTtag","width":5},{"name":"sta_uop_destinations_1_previousTtagValid","width":1},{"name":"sta_uop_destinations_1_previousUtag","width":5},{"name":"sta_uop_destinations_1_previousUtagValid","width":1},{"name":"sta_uop_destinations_1_ptag","width":7},{"name":"sta_uop_destinations_1_ptagValid","width":1},{"name":"sta_uop_destinations_1_tGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqIndex","width":5},{"name":"sta_uop_destinations_1_ttag","width":5},{"name":"sta_uop_destinations_1_ttagValid","width":1},{"name":"sta_uop_destinations_1_uGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqIndex","width":5},{"name":"sta_uop_destinations_1_utag","width":5},{"name":"sta_uop_destinations_1_utagValid","width":1},{"name":"sta_uop_destinations_1_valid","width":1},{"name":"sta_uop_sources_0_atag","width":6},{"name":"sta_uop_sources_0_kind","width":3},{"name":"sta_uop_sources_0_pGeneration","width":16},{"name":"sta_uop_sources_0_ptag","width":7},{"name":"sta_uop_sources_0_ptagValid","width":1},{"name":"sta_uop_sources_0_ready","width":1},{"name":"sta_uop_sources_0_tGeneration","width":16},{"name":"sta_uop_sources_0_tSeqGeneration","width":16},{"name":"sta_uop_sources_0_tSeqIndex","width":5},{"name":"sta_uop_sources_0_ttag","width":5},{"name":"sta_uop_sources_0_ttagValid","width":1},{"name":"sta_uop_sources_0_uGeneration","width":16},{"name":"sta_uop_sources_0_uSeqGeneration","width":16},{"name":"sta_uop_sources_0_uSeqIndex","width":5},{"name":"sta_uop_sources_0_utag","width":5},{"name":"sta_uop_sources_0_utagValid","width":1},{"name":"sta_uop_sources_0_valid","width":1},{"name":"sta_uop_sources_1_atag","width":6},{"name":"sta_uop_sources_1_kind","width":3},{"name":"sta_uop_sources_1_pGeneration","width":16},{"name":"sta_uop_sources_1_ptag","width":7},{"name":"sta_uop_sources_1_ptagValid","width":1},{"name":"sta_uop_sources_1_ready","width":1},{"name":"sta_uop_sources_1_tGeneration","width":16},{"name":"sta_uop_sources_1_tSeqGeneration","width":16},{"name":"sta_uop_sources_1_tSeqIndex","width":5},{"name":"sta_uop_sources_1_ttag","width":5},{"name":"sta_uop_sources_1_ttagValid","width":1},{"name":"sta_uop_sources_1_uGeneration","width":16},{"name":"sta_uop_sources_1_uSeqGeneration","width":16},{"name":"sta_uop_sources_1_uSeqIndex","width":5},{"name":"sta_uop_sources_1_utag","width":5},{"name":"sta_uop_sources_1_utagValid","width":1},{"name":"sta_uop_sources_1_valid","width":1},{"name":"sta_uop_sources_2_atag","width":6},{"name":"sta_uop_sources_2_kind","width":3},{"name":"sta_uop_sources_2_pGeneration","width":16},{"name":"sta_uop_sources_2_ptag","width":7},{"name":"sta_uop_sources_2_ptagValid","width":1},{"name":"sta_uop_sources_2_ready","width":1},{"name":"sta_uop_sources_2_tGeneration","width":16},{"name":"sta_uop_sources_2_tSeqGeneration","width":16},{"name":"sta_uop_sources_2_tSeqIndex","width":5},{"name":"sta_uop_sources_2_ttag","width":5},{"name":"sta_uop_sources_2_ttagValid","width":1},{"name":"sta_uop_sources_2_uGeneration","width":16},{"name":"sta_uop_sources_2_uSeqGeneration","width":16},{"name":"sta_uop_sources_2_uSeqIndex","width":5},{"name":"sta_uop_sources_2_utag","width":5},{"name":"sta_uop_sources_2_utagValid","width":1},{"name":"sta_uop_sources_2_valid","width":1},{"name":"sta_uop_sources_3_atag","width":6},{"name":"sta_uop_sources_3_kind","width":3},{"name":"sta_uop_sources_3_pGeneration","width":16},{"name":"sta_uop_sources_3_ptag","width":7},{"name":"sta_uop_sources_3_ptagValid","width":1},{"name":"sta_uop_sources_3_ready","width":1},{"name":"sta_uop_sources_3_tGeneration","width":16},{"name":"sta_uop_sources_3_tSeqGeneration","width":16},{"name":"sta_uop_sources_3_tSeqIndex","width":5},{"name":"sta_uop_sources_3_ttag","width":5},{"name":"sta_uop_sources_3_ttagValid","width":1},{"name":"sta_uop_sources_3_uGeneration","width":16},{"name":"sta_uop_sources_3_uSeqGeneration","width":16},{"name":"sta_uop_sources_3_uSeqIndex","width":5},{"name":"sta_uop_sources_3_utag","width":5},{"name":"sta_uop_sources_3_utagValid","width":1},{"name":"sta_uop_sources_3_valid","width":1},{"name":"std_memoryOrder_firstLid","width":32},{"name":"std_memoryOrder_firstLsid","width":32},{"name":"std_memoryOrder_firstSid","width":32},{"name":"std_memoryOrder_requestCount","width":2},{"name":"std_memoryOrder_yoldLid","width":32},{"name":"std_memoryOrder_yoldLsid","width":32},{"name":"std_memoryOrder_yoldValid","width":1},{"name":"std_memoryOrder_yostLsid","width":32},{"name":"std_memoryOrder_yostSid","width":32},{"name":"std_memoryOrder_yostValid","width":1},{"name":"std_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"std_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"std_pcBufferIndexOffset_pcOffset","width":7},{"name":"std_pcBufferIndexOffset_valid","width":1},{"name":"std_transactionId","width":64},{"name":"std_trap_cause","width":32},{"name":"std_trap_valid","width":1},{"name":"std_uop_decoded_blockBoundary","width":1},{"name":"std_uop_decoded_blockStart","width":1},{"name":"std_uop_decoded_blockStop","width":1},{"name":"std_uop_decoded_classification_complexBreak","width":1},{"name":"std_uop_decoded_classification_dispatchClass","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_0","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_1","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_2","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_3","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_4","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_5","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_6","width":2},{"name":"std_uop_decoded_classification_dispatchDemand_7","width":2},{"name":"std_uop_decoded_classification_dispatchWrites","width":2},{"name":"std_uop_decoded_classification_disposition","width":2},{"name":"std_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"std_uop_decoded_classification_fastResolveClass","width":3},{"name":"std_uop_decoded_classification_fusionHeadClass","width":2},{"name":"std_uop_decoded_classification_fusionTailClass","width":2},{"name":"std_uop_decoded_classification_implicitDestination","width":2},{"name":"std_uop_decoded_classification_implicitSourceMask","width":4},{"name":"std_uop_decoded_classification_kind","width":4},{"name":"std_uop_decoded_classification_mayRedirect","width":1},{"name":"std_uop_decoded_classification_mayTrap","width":1},{"name":"std_uop_decoded_classification_mayTrapLate","width":1},{"name":"std_uop_decoded_classification_memoryRequestCount","width":2},{"name":"std_uop_decoded_classification_nonspeculative","width":1},{"name":"std_uop_decoded_classification_pDestinationCount","width":2},{"name":"std_uop_decoded_classification_pSourceCount","width":3},{"name":"std_uop_decoded_classification_pcReadClass","width":4},{"name":"std_uop_decoded_classification_pcReadRequired","width":1},{"name":"std_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"std_uop_decoded_classification_sideEffectOwner","width":3},{"name":"std_uop_decoded_classification_splitKind","width":2},{"name":"std_uop_decoded_classification_tAllocationCount","width":2},{"name":"std_uop_decoded_classification_uAllocationCount","width":2},{"name":"std_uop_decoded_classification_uopCountMax","width":6},{"name":"std_uop_decoded_classification_uopCountMin","width":6},{"name":"std_uop_decoded_classification_valid","width":1},{"name":"std_uop_decoded_destinations_0_atag","width":6},{"name":"std_uop_decoded_destinations_0_kind","width":3},{"name":"std_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_0_valid","width":1},{"name":"std_uop_decoded_destinations_1_atag","width":6},{"name":"std_uop_decoded_destinations_1_kind","width":3},{"name":"std_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_1_valid","width":1},{"name":"std_uop_decoded_earlyComplete","width":1},{"name":"std_uop_decoded_immediate","width":64},{"name":"std_uop_decoded_immediateValid","width":1},{"name":"std_uop_decoded_instruction_kind","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"std_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"std_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"std_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"std_uop_decoded_instruction_parent_instruction","width":64},{"name":"std_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"std_uop_decoded_instruction_parent_pc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"std_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"std_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"std_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"std_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"std_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"std_uop_decoded_instruction_templateCount","width":8},{"name":"std_uop_decoded_instruction_templateImmediate","width":64},{"name":"std_uop_decoded_instruction_templateOpcode","width":12},{"name":"std_uop_decoded_instruction_templateOrdinal","width":8},{"name":"std_uop_decoded_memory_accessBytes","width":4},{"name":"std_uop_decoded_memory_addressMode","width":2},{"name":"std_uop_decoded_memory_addressSourceMask","width":4},{"name":"std_uop_decoded_memory_dataSourceMask","width":4},{"name":"std_uop_decoded_memory_indexMode","width":2},{"name":"std_uop_decoded_memory_indexShift","width":5},{"name":"std_uop_decoded_memory_isLoad","width":1},{"name":"std_uop_decoded_memory_isStore","width":1},{"name":"std_uop_decoded_memory_offset","width":64},{"name":"std_uop_decoded_memory_requestCount","width":2},{"name":"std_uop_decoded_memory_signExtend","width":1},{"name":"std_uop_decoded_memory_valid","width":1},{"name":"std_uop_decoded_memory_writebackPreIndex","width":1},{"name":"std_uop_decoded_memory_writebackValid","width":1},{"name":"std_uop_decoded_opcode","width":12},{"name":"std_uop_decoded_rob_bid","width":8},{"name":"std_uop_decoded_rob_brobGeneration","width":16},{"name":"std_uop_decoded_rob_memberIndex","width":2},{"name":"std_uop_decoded_rob_peId","width":8},{"name":"std_uop_decoded_rob_residentGeneration","width":16},{"name":"std_uop_decoded_rob_ridGeneration","width":16},{"name":"std_uop_decoded_rob_ridSlot","width":6},{"name":"std_uop_decoded_rob_stid","width":1},{"name":"std_uop_decoded_sources_0_atag","width":6},{"name":"std_uop_decoded_sources_0_kind","width":3},{"name":"std_uop_decoded_sources_0_relativeIndex","width":6},{"name":"std_uop_decoded_sources_0_valid","width":1},{"name":"std_uop_decoded_sources_1_atag","width":6},{"name":"std_uop_decoded_sources_1_kind","width":3},{"name":"std_uop_decoded_sources_1_relativeIndex","width":6},{"name":"std_uop_decoded_sources_1_valid","width":1},{"name":"std_uop_decoded_sources_2_atag","width":6},{"name":"std_uop_decoded_sources_2_kind","width":3},{"name":"std_uop_decoded_sources_2_relativeIndex","width":6},{"name":"std_uop_decoded_sources_2_valid","width":1},{"name":"std_uop_decoded_sources_3_atag","width":6},{"name":"std_uop_decoded_sources_3_kind","width":3},{"name":"std_uop_decoded_sources_3_relativeIndex","width":6},{"name":"std_uop_decoded_sources_3_valid","width":1},{"name":"std_uop_decoded_uopClass","width":3},{"name":"std_uop_decoded_valid","width":1},{"name":"std_uop_destinations_0_atag","width":6},{"name":"std_uop_destinations_0_kind","width":3},{"name":"std_uop_destinations_0_pGeneration","width":16},{"name":"std_uop_destinations_0_previousPGeneration","width":16},{"name":"std_uop_destinations_0_previousPtag","width":7},{"name":"std_uop_destinations_0_previousPtagValid","width":1},{"name":"std_uop_destinations_0_previousTtag","width":5},{"name":"std_uop_destinations_0_previousTtagValid","width":1},{"name":"std_uop_destinations_0_previousUtag","width":5},{"name":"std_uop_destinations_0_previousUtagValid","width":1},{"name":"std_uop_destinations_0_ptag","width":7},{"name":"std_uop_destinations_0_ptagValid","width":1},{"name":"std_uop_destinations_0_tGeneration","width":16},{"name":"std_uop_destinations_0_tSeqGeneration","width":16},{"name":"std_uop_destinations_0_tSeqIndex","width":5},{"name":"std_uop_destinations_0_ttag","width":5},{"name":"std_uop_destinations_0_ttagValid","width":1},{"name":"std_uop_destinations_0_uGeneration","width":16},{"name":"std_uop_destinations_0_uSeqGeneration","width":16},{"name":"std_uop_destinations_0_uSeqIndex","width":5},{"name":"std_uop_destinations_0_utag","width":5},{"name":"std_uop_destinations_0_utagValid","width":1},{"name":"std_uop_destinations_0_valid","width":1},{"name":"std_uop_destinations_1_atag","width":6},{"name":"std_uop_destinations_1_kind","width":3},{"name":"std_uop_destinations_1_pGeneration","width":16},{"name":"std_uop_destinations_1_previousPGeneration","width":16},{"name":"std_uop_destinations_1_previousPtag","width":7},{"name":"std_uop_destinations_1_previousPtagValid","width":1},{"name":"std_uop_destinations_1_previousTtag","width":5},{"name":"std_uop_destinations_1_previousTtagValid","width":1},{"name":"std_uop_destinations_1_previousUtag","width":5},{"name":"std_uop_destinations_1_previousUtagValid","width":1},{"name":"std_uop_destinations_1_ptag","width":7},{"name":"std_uop_destinations_1_ptagValid","width":1},{"name":"std_uop_destinations_1_tGeneration","width":16},{"name":"std_uop_destinations_1_tSeqGeneration","width":16},{"name":"std_uop_destinations_1_tSeqIndex","width":5},{"name":"std_uop_destinations_1_ttag","width":5},{"name":"std_uop_destinations_1_ttagValid","width":1},{"name":"std_uop_destinations_1_uGeneration","width":16},{"name":"std_uop_destinations_1_uSeqGeneration","width":16},{"name":"std_uop_destinations_1_uSeqIndex","width":5},{"name":"std_uop_destinations_1_utag","width":5},{"name":"std_uop_destinations_1_utagValid","width":1},{"name":"std_uop_destinations_1_valid","width":1},{"name":"std_uop_sources_0_atag","width":6},{"name":"std_uop_sources_0_kind","width":3},{"name":"std_uop_sources_0_pGeneration","width":16},{"name":"std_uop_sources_0_ptag","width":7},{"name":"std_uop_sources_0_ptagValid","width":1},{"name":"std_uop_sources_0_ready","width":1},{"name":"std_uop_sources_0_tGeneration","width":16},{"name":"std_uop_sources_0_tSeqGeneration","width":16},{"name":"std_uop_sources_0_tSeqIndex","width":5},{"name":"std_uop_sources_0_ttag","width":5},{"name":"std_uop_sources_0_ttagValid","width":1},{"name":"std_uop_sources_0_uGeneration","width":16},{"name":"std_uop_sources_0_uSeqGeneration","width":16},{"name":"std_uop_sources_0_uSeqIndex","width":5},{"name":"std_uop_sources_0_utag","width":5},{"name":"std_uop_sources_0_utagValid","width":1},{"name":"std_uop_sources_0_valid","width":1},{"name":"std_uop_sources_1_atag","width":6},{"name":"std_uop_sources_1_kind","width":3},{"name":"std_uop_sources_1_pGeneration","width":16},{"name":"std_uop_sources_1_ptag","width":7},{"name":"std_uop_sources_1_ptagValid","width":1},{"name":"std_uop_sources_1_ready","width":1},{"name":"std_uop_sources_1_tGeneration","width":16},{"name":"std_uop_sources_1_tSeqGeneration","width":16},{"name":"std_uop_sources_1_tSeqIndex","width":5},{"name":"std_uop_sources_1_ttag","width":5},{"name":"std_uop_sources_1_ttagValid","width":1},{"name":"std_uop_sources_1_uGeneration","width":16},{"name":"std_uop_sources_1_uSeqGeneration","width":16},{"name":"std_uop_sources_1_uSeqIndex","width":5},{"name":"std_uop_sources_1_utag","width":5},{"name":"std_uop_sources_1_utagValid","width":1},{"name":"std_uop_sources_1_valid","width":1},{"name":"std_uop_sources_2_atag","width":6},{"name":"std_uop_sources_2_kind","width":3},{"name":"std_uop_sources_2_pGeneration","width":16},{"name":"std_uop_sources_2_ptag","width":7},{"name":"std_uop_sources_2_ptagValid","width":1},{"name":"std_uop_sources_2_ready","width":1},{"name":"std_uop_sources_2_tGeneration","width":16},{"name":"std_uop_sources_2_tSeqGeneration","width":16},{"name":"std_uop_sources_2_tSeqIndex","width":5},{"name":"std_uop_sources_2_ttag","width":5},{"name":"std_uop_sources_2_ttagValid","width":1},{"name":"std_uop_sources_2_uGeneration","width":16},{"name":"std_uop_sources_2_uSeqGeneration","width":16},{"name":"std_uop_sources_2_uSeqIndex","width":5},{"name":"std_uop_sources_2_utag","width":5},{"name":"std_uop_sources_2_utagValid","width":1},{"name":"std_uop_sources_2_valid","width":1},{"name":"std_uop_sources_3_atag","width":6},{"name":"std_uop_sources_3_kind","width":3},{"name":"std_uop_sources_3_pGeneration","width":16},{"name":"std_uop_sources_3_ptag","width":7},{"name":"std_uop_sources_3_ptagValid","width":1},{"name":"std_uop_sources_3_ready","width":1},{"name":"std_uop_sources_3_tGeneration","width":16},{"name":"std_uop_sources_3_tSeqGeneration","width":16},{"name":"std_uop_sources_3_tSeqIndex","width":5},{"name":"std_uop_sources_3_ttag","width":5},{"name":"std_uop_sources_3_ttagValid","width":1},{"name":"std_uop_sources_3_uGeneration","width":16},{"name":"std_uop_sources_3_uSeqGeneration","width":16},{"name":"std_uop_sources_3_uSeqIndex","width":5},{"name":"std_uop_sources_3_utag","width":5},{"name":"std_uop_sources_3_utagValid","width":1},{"name":"std_uop_sources_3_valid","width":1},{"name":"stdPipe","width":1}]},{"name":"ooo_to_iex_system","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":2},{"name":"uop_decoded_classification_dispatchDemand_1","width":2},{"name":"uop_decoded_classification_dispatchDemand_2","width":2},{"name":"uop_decoded_classification_dispatchDemand_3","width":2},{"name":"uop_decoded_classification_dispatchDemand_4","width":2},{"name":"uop_decoded_classification_dispatchDemand_5","width":2},{"name":"uop_decoded_classification_dispatchDemand_6","width":2},{"name":"uop_decoded_classification_dispatchDemand_7","width":2},{"name":"uop_decoded_classification_dispatchWrites","width":2},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_cmd","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":2},{"name":"uop_decoded_classification_dispatchDemand_1","width":2},{"name":"uop_decoded_classification_dispatchDemand_2","width":2},{"name":"uop_decoded_classification_dispatchDemand_3","width":2},{"name":"uop_decoded_classification_dispatchDemand_4","width":2},{"name":"uop_decoded_classification_dispatchDemand_5","width":2},{"name":"uop_decoded_classification_dispatchDemand_6","width":2},{"name":"uop_decoded_classification_dispatchDemand_7","width":2},{"name":"uop_decoded_classification_dispatchWrites","width":2},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_rob_noflush","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"RobNoflushTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_noflush_ready","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"RobNoflushReadyTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_resolve","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":2,"payload":"RobResolveTxn","ports":[{"name":"destinationIndex","width":1},{"name":"destinationValid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"value","width":64}]},{"name":"iex_to_ooo_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_top_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"TOP","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_pc_buffer_read_address","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":6,"payload":"PcBufferReadAddress","ports":[{"name":"allocationEpoch","width":16},{"name":"pcBufferIndex","width":6},{"name":"stid","width":1},{"name":"valid","width":1}]},{"name":"ooo_to_iex_pc_buffer_read_pc_base","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":6,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"iex_to_lsu_load_issue","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"LoadIssueTxn","ports":[{"name":"address","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"pc","width":64},{"name":"signed","width":1},{"name":"sizeBytes","width":4},{"name":"youngestStoreId","width":32},{"name":"youngestStoreLsid","width":32},{"name":"youngestStoreValid","width":1}]},{"name":"lsu_to_iex_load_allocation_preview","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadAllocationPreview","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_launch","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadLaunchTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"iex_to_lsu_store_reservation","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreReservationTxn","ports":[{"name":"aguPipe","width":1},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sizeBytes","width":4},{"name":"stdPipe","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64},{"name":"transactionId","width":64}]},{"name":"iex_to_lsu_store_address","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreAddressTxn","ports":[{"name":"address","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"iex_to_lsu_store_data","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreDataTxn","ports":[{"name":"byteMask_0","width":8},{"name":"byteMask_1","width":8},{"name":"data_0","width":64},{"name":"data_1","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"lsu_to_iex_load_result","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadResultTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"data","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1}]},{"name":"lsu_to_iex_load_reissue","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadReissueTxn","ports":[{"name":"address","width":64},{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_repick","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadRepickTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_cancel","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadCancelTxn","ports":[{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64}]},{"name":"ooo_to_lsu_store_commit","contract_id":"IFC-IEX-LSU-001","producer":"OOO","consumer":"LSU","lanes":1,"payload":"StoreCommitAuthorizationTxn","ports":[{"name":"beat","width":1},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"lsu_internal_store_classify","contract_id":"IFC-IEX-LSU-001","producer":"LSU Translation","consumer":"LSU Commit Backend","lanes":1,"payload":"StoreMemoryClassifyTxn","ports":[{"name":"beat","width":1},{"name":"faultCause","width":32},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"memoryClass","width":2},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"external_cmd_issue","contract_id":"IFC-TOP-EXT-001","producer":"IEX","consumer":"External CMD","lanes":1,"payload":"CmdIssueTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sourceValid","width":4},{"name":"sourceValues_0","width":64},{"name":"sourceValues_1","width":64},{"name":"sourceValues_2","width":64},{"name":"sourceValues_3","width":64},{"name":"transactionId","width":64}]},{"name":"owner_to_ooo_recovery_event","contract_id":"IFC-RECOVERY-001","producer":"IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryEvent","ports":[{"name":"cause","width":3},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"redirectPc","width":64},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_prepare","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"target_to_ooo_recovery_prepared","contract_id":"IFC-RECOVERY-001","producer":"IFU/CTU/IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_apply","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_abort","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_commit","contract_id":"IFC-COMMIT-001","producer":"OOO","consumer":"TOP/DTU","lanes":2,"payload":"CommitTxn","ports":[{"name":"count","width":2},{"name":"entries_0_destination_atag","width":6},{"name":"entries_0_destination_kind","width":3},{"name":"entries_0_destination_pGeneration","width":16},{"name":"entries_0_destination_previousPGeneration","width":16},{"name":"entries_0_destination_previousPtag","width":7},{"name":"entries_0_destination_previousPtagValid","width":1},{"name":"entries_0_destination_previousTtag","width":5},{"name":"entries_0_destination_previousTtagValid","width":1},{"name":"entries_0_destination_previousUtag","width":5},{"name":"entries_0_destination_previousUtagValid","width":1},{"name":"entries_0_destination_ptag","width":7},{"name":"entries_0_destination_ptagValid","width":1},{"name":"entries_0_destination_tGeneration","width":16},{"name":"entries_0_destination_tSeqGeneration","width":16},{"name":"entries_0_destination_tSeqIndex","width":5},{"name":"entries_0_destination_ttag","width":5},{"name":"entries_0_destination_ttagValid","width":1},{"name":"entries_0_destination_uGeneration","width":16},{"name":"entries_0_destination_uSeqGeneration","width":16},{"name":"entries_0_destination_uSeqIndex","width":5},{"name":"entries_0_destination_utag","width":5},{"name":"entries_0_destination_utagValid","width":1},{"name":"entries_0_destination_valid","width":1},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionBits","width":64},{"name":"entries_0_instructionLengthBytes","width":4},{"name":"entries_0_memory_attemptGeneration","width":16},{"name":"entries_0_memory_lsid","width":32},{"name":"entries_0_memory_pipeId","width":1},{"name":"entries_0_memory_rob_bid","width":8},{"name":"entries_0_memory_rob_brobGeneration","width":16},{"name":"entries_0_memory_rob_memberIndex","width":2},{"name":"entries_0_memory_rob_peId","width":8},{"name":"entries_0_memory_rob_residentGeneration","width":16},{"name":"entries_0_memory_rob_ridGeneration","width":16},{"name":"entries_0_memory_rob_ridSlot","width":6},{"name":"entries_0_memory_rob_stid","width":1},{"name":"entries_0_memory_transaction_generation","width":16},{"name":"entries_0_memory_transaction_value","width":64},{"name":"entries_0_memoryOrder_firstLid","width":32},{"name":"entries_0_memoryOrder_firstLsid","width":32},{"name":"entries_0_memoryOrder_firstSid","width":32},{"name":"entries_0_memoryOrder_requestCount","width":2},{"name":"entries_0_memoryOrder_yoldLid","width":32},{"name":"entries_0_memoryOrder_yoldLsid","width":32},{"name":"entries_0_memoryOrder_yoldValid","width":1},{"name":"entries_0_memoryOrder_yostLsid","width":32},{"name":"entries_0_memoryOrder_yostSid","width":32},{"name":"entries_0_memoryOrder_yostValid","width":1},{"name":"entries_0_memoryStore","width":1},{"name":"entries_0_memoryValid","width":1},{"name":"entries_0_opcode","width":12},{"name":"entries_0_pc","width":64},{"name":"entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_0_pcBufferIndexOffset_valid","width":1},{"name":"entries_0_result","width":64},{"name":"entries_0_resultValid","width":1},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robGroupLast","width":1},{"name":"entries_0_storeData","width":64},{"name":"entries_0_storeMask","width":8},{"name":"entries_0_trap_cause","width":32},{"name":"entries_0_trap_instruction_epoch","width":16},{"name":"entries_0_trap_instruction_instructionId","width":64},{"name":"entries_0_trap_instruction_peId","width":8},{"name":"entries_0_trap_instruction_stid","width":1},{"name":"entries_0_trap_kind","width":2},{"name":"entries_0_trap_rob_bid","width":8},{"name":"entries_0_trap_rob_brobGeneration","width":16},{"name":"entries_0_trap_rob_memberIndex","width":2},{"name":"entries_0_trap_rob_peId","width":8},{"name":"entries_0_trap_rob_residentGeneration","width":16},{"name":"entries_0_trap_rob_ridGeneration","width":16},{"name":"entries_0_trap_rob_ridSlot","width":6},{"name":"entries_0_trap_rob_stid","width":1},{"name":"entries_0_trap_targetPc","width":64},{"name":"entries_0_trap_tval","width":64},{"name":"entries_0_trap_valid","width":1},{"name":"entries_1_destination_atag","width":6},{"name":"entries_1_destination_kind","width":3},{"name":"entries_1_destination_pGeneration","width":16},{"name":"entries_1_destination_previousPGeneration","width":16},{"name":"entries_1_destination_previousPtag","width":7},{"name":"entries_1_destination_previousPtagValid","width":1},{"name":"entries_1_destination_previousTtag","width":5},{"name":"entries_1_destination_previousTtagValid","width":1},{"name":"entries_1_destination_previousUtag","width":5},{"name":"entries_1_destination_previousUtagValid","width":1},{"name":"entries_1_destination_ptag","width":7},{"name":"entries_1_destination_ptagValid","width":1},{"name":"entries_1_destination_tGeneration","width":16},{"name":"entries_1_destination_tSeqGeneration","width":16},{"name":"entries_1_destination_tSeqIndex","width":5},{"name":"entries_1_destination_ttag","width":5},{"name":"entries_1_destination_ttagValid","width":1},{"name":"entries_1_destination_uGeneration","width":16},{"name":"entries_1_destination_uSeqGeneration","width":16},{"name":"entries_1_destination_uSeqIndex","width":5},{"name":"entries_1_destination_utag","width":5},{"name":"entries_1_destination_utagValid","width":1},{"name":"entries_1_destination_valid","width":1},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionBits","width":64},{"name":"entries_1_instructionLengthBytes","width":4},{"name":"entries_1_memory_attemptGeneration","width":16},{"name":"entries_1_memory_lsid","width":32},{"name":"entries_1_memory_pipeId","width":1},{"name":"entries_1_memory_rob_bid","width":8},{"name":"entries_1_memory_rob_brobGeneration","width":16},{"name":"entries_1_memory_rob_memberIndex","width":2},{"name":"entries_1_memory_rob_peId","width":8},{"name":"entries_1_memory_rob_residentGeneration","width":16},{"name":"entries_1_memory_rob_ridGeneration","width":16},{"name":"entries_1_memory_rob_ridSlot","width":6},{"name":"entries_1_memory_rob_stid","width":1},{"name":"entries_1_memory_transaction_generation","width":16},{"name":"entries_1_memory_transaction_value","width":64},{"name":"entries_1_memoryOrder_firstLid","width":32},{"name":"entries_1_memoryOrder_firstLsid","width":32},{"name":"entries_1_memoryOrder_firstSid","width":32},{"name":"entries_1_memoryOrder_requestCount","width":2},{"name":"entries_1_memoryOrder_yoldLid","width":32},{"name":"entries_1_memoryOrder_yoldLsid","width":32},{"name":"entries_1_memoryOrder_yoldValid","width":1},{"name":"entries_1_memoryOrder_yostLsid","width":32},{"name":"entries_1_memoryOrder_yostSid","width":32},{"name":"entries_1_memoryOrder_yostValid","width":1},{"name":"entries_1_memoryStore","width":1},{"name":"entries_1_memoryValid","width":1},{"name":"entries_1_opcode","width":12},{"name":"entries_1_pc","width":64},{"name":"entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_1_pcBufferIndexOffset_valid","width":1},{"name":"entries_1_result","width":64},{"name":"entries_1_resultValid","width":1},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robGroupLast","width":1},{"name":"entries_1_storeData","width":64},{"name":"entries_1_storeMask","width":8},{"name":"entries_1_trap_cause","width":32},{"name":"entries_1_trap_instruction_epoch","width":16},{"name":"entries_1_trap_instruction_instructionId","width":64},{"name":"entries_1_trap_instruction_peId","width":8},{"name":"entries_1_trap_instruction_stid","width":1},{"name":"entries_1_trap_kind","width":2},{"name":"entries_1_trap_rob_bid","width":8},{"name":"entries_1_trap_rob_brobGeneration","width":16},{"name":"entries_1_trap_rob_memberIndex","width":2},{"name":"entries_1_trap_rob_peId","width":8},{"name":"entries_1_trap_rob_residentGeneration","width":16},{"name":"entries_1_trap_rob_ridGeneration","width":16},{"name":"entries_1_trap_rob_ridSlot","width":6},{"name":"entries_1_trap_rob_stid","width":1},{"name":"entries_1_trap_targetPc","width":64},{"name":"entries_1_trap_tval","width":64},{"name":"entries_1_trap_valid","width":1}]},{"name":"box_to_dtu_trace","contract_id":"IFC-DTU-001","producer":"TOP/IFU/CTU/OOO/IEX/LSU","consumer":"DTU","lanes":2,"payload":"TracePacket","ports":[{"name":"count","width":2},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3}]},{"name":"external_to_dtu_debug_request","contract_id":"IFC-DTU-001","producer":"External Debug","consumer":"DTU","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_ooo_debug_request","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"OOO","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_dtu_debug_response","contract_id":"IFC-DTU-001","producer":"OOO","consumer":"DTU","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_external_debug_response","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Debug","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_trace_export","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Trace","lanes":2,"payload":"TracePacket","ports":[{"name":"count","width":2},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3}]},{"name":"dtu_performance_counter","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Counter","lanes":32,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"instruction_memory_request","contract_id":"IFC-MEMORY-001","producer":"IFU","consumer":"Memory","lanes":1,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"instruction_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"IFU","lanes":1,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]},{"name":"data_memory_request","contract_id":"IFC-MEMORY-001","producer":"LSU","consumer":"Memory","lanes":4,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"data_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"LSU","lanes":4,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]}]},{"name":"W4","width":4,"endpoints":[{"name":"top_io","contract_id":"IFC-TOP-EXT-002","producer":"Platform","consumer":"TOP","lanes":1,"payload":"TOPIO","ports":[{"name":"bootstrapComplete","width":1},{"name":"bootstrapReady","width":1},{"name":"cmdIssue_bits_instruction_epoch","width":16},{"name":"cmdIssue_bits_instruction_instructionId","width":64},{"name":"cmdIssue_bits_instruction_peId","width":8},{"name":"cmdIssue_bits_instruction_stid","width":1},{"name":"cmdIssue_bits_opcode","width":12},{"name":"cmdIssue_bits_rob_bid","width":8},{"name":"cmdIssue_bits_rob_brobGeneration","width":16},{"name":"cmdIssue_bits_rob_memberIndex","width":2},{"name":"cmdIssue_bits_rob_peId","width":8},{"name":"cmdIssue_bits_rob_residentGeneration","width":16},{"name":"cmdIssue_bits_rob_ridGeneration","width":16},{"name":"cmdIssue_bits_rob_ridSlot","width":6},{"name":"cmdIssue_bits_rob_stid","width":1},{"name":"cmdIssue_bits_sourceValid","width":4},{"name":"cmdIssue_bits_sourceValues_0","width":64},{"name":"cmdIssue_bits_sourceValues_1","width":64},{"name":"cmdIssue_bits_sourceValues_2","width":64},{"name":"cmdIssue_bits_sourceValues_3","width":64},{"name":"cmdIssue_bits_transactionId","width":64},{"name":"cmdIssue_ready","width":1},{"name":"cmdIssue_valid","width":1},{"name":"commit_bits_count","width":3},{"name":"commit_bits_entries_0_destination_atag","width":6},{"name":"commit_bits_entries_0_destination_kind","width":3},{"name":"commit_bits_entries_0_destination_pGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPtag","width":7},{"name":"commit_bits_entries_0_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousTtag","width":5},{"name":"commit_bits_entries_0_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousUtag","width":5},{"name":"commit_bits_entries_0_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_0_destination_ptag","width":7},{"name":"commit_bits_entries_0_destination_ptagValid","width":1},{"name":"commit_bits_entries_0_destination_tGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_ttag","width":5},{"name":"commit_bits_entries_0_destination_ttagValid","width":1},{"name":"commit_bits_entries_0_destination_uGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_utag","width":5},{"name":"commit_bits_entries_0_destination_utagValid","width":1},{"name":"commit_bits_entries_0_destination_valid","width":1},{"name":"commit_bits_entries_0_instruction_epoch","width":16},{"name":"commit_bits_entries_0_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_instruction_peId","width":8},{"name":"commit_bits_entries_0_instruction_stid","width":1},{"name":"commit_bits_entries_0_instructionBits","width":64},{"name":"commit_bits_entries_0_instructionLengthBytes","width":4},{"name":"commit_bits_entries_0_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_0_memory_lsid","width":32},{"name":"commit_bits_entries_0_memory_pipeId","width":1},{"name":"commit_bits_entries_0_memory_rob_bid","width":8},{"name":"commit_bits_entries_0_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_memory_rob_peId","width":8},{"name":"commit_bits_entries_0_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_memory_rob_stid","width":1},{"name":"commit_bits_entries_0_memory_transaction_generation","width":16},{"name":"commit_bits_entries_0_memory_transaction_value","width":64},{"name":"commit_bits_entries_0_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_0_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_0_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_0_memoryStore","width":1},{"name":"commit_bits_entries_0_memoryValid","width":1},{"name":"commit_bits_entries_0_opcode","width":12},{"name":"commit_bits_entries_0_pc","width":64},{"name":"commit_bits_entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_0_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_0_result","width":64},{"name":"commit_bits_entries_0_resultValid","width":1},{"name":"commit_bits_entries_0_rob_bid","width":8},{"name":"commit_bits_entries_0_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_rob_peId","width":8},{"name":"commit_bits_entries_0_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_rob_stid","width":1},{"name":"commit_bits_entries_0_robGroupLast","width":1},{"name":"commit_bits_entries_0_storeData","width":64},{"name":"commit_bits_entries_0_storeMask","width":8},{"name":"commit_bits_entries_0_trap_cause","width":32},{"name":"commit_bits_entries_0_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_0_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_trap_instruction_peId","width":8},{"name":"commit_bits_entries_0_trap_instruction_stid","width":1},{"name":"commit_bits_entries_0_trap_kind","width":2},{"name":"commit_bits_entries_0_trap_rob_bid","width":8},{"name":"commit_bits_entries_0_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_trap_rob_peId","width":8},{"name":"commit_bits_entries_0_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_trap_rob_stid","width":1},{"name":"commit_bits_entries_0_trap_targetPc","width":64},{"name":"commit_bits_entries_0_trap_tval","width":64},{"name":"commit_bits_entries_0_trap_valid","width":1},{"name":"commit_bits_entries_1_destination_atag","width":6},{"name":"commit_bits_entries_1_destination_kind","width":3},{"name":"commit_bits_entries_1_destination_pGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPtag","width":7},{"name":"commit_bits_entries_1_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousTtag","width":5},{"name":"commit_bits_entries_1_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousUtag","width":5},{"name":"commit_bits_entries_1_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_1_destination_ptag","width":7},{"name":"commit_bits_entries_1_destination_ptagValid","width":1},{"name":"commit_bits_entries_1_destination_tGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_ttag","width":5},{"name":"commit_bits_entries_1_destination_ttagValid","width":1},{"name":"commit_bits_entries_1_destination_uGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_utag","width":5},{"name":"commit_bits_entries_1_destination_utagValid","width":1},{"name":"commit_bits_entries_1_destination_valid","width":1},{"name":"commit_bits_entries_1_instruction_epoch","width":16},{"name":"commit_bits_entries_1_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_instruction_peId","width":8},{"name":"commit_bits_entries_1_instruction_stid","width":1},{"name":"commit_bits_entries_1_instructionBits","width":64},{"name":"commit_bits_entries_1_instructionLengthBytes","width":4},{"name":"commit_bits_entries_1_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_1_memory_lsid","width":32},{"name":"commit_bits_entries_1_memory_pipeId","width":1},{"name":"commit_bits_entries_1_memory_rob_bid","width":8},{"name":"commit_bits_entries_1_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_memory_rob_peId","width":8},{"name":"commit_bits_entries_1_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_memory_rob_stid","width":1},{"name":"commit_bits_entries_1_memory_transaction_generation","width":16},{"name":"commit_bits_entries_1_memory_transaction_value","width":64},{"name":"commit_bits_entries_1_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_1_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_1_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_1_memoryStore","width":1},{"name":"commit_bits_entries_1_memoryValid","width":1},{"name":"commit_bits_entries_1_opcode","width":12},{"name":"commit_bits_entries_1_pc","width":64},{"name":"commit_bits_entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_1_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_1_result","width":64},{"name":"commit_bits_entries_1_resultValid","width":1},{"name":"commit_bits_entries_1_rob_bid","width":8},{"name":"commit_bits_entries_1_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_rob_peId","width":8},{"name":"commit_bits_entries_1_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_rob_stid","width":1},{"name":"commit_bits_entries_1_robGroupLast","width":1},{"name":"commit_bits_entries_1_storeData","width":64},{"name":"commit_bits_entries_1_storeMask","width":8},{"name":"commit_bits_entries_1_trap_cause","width":32},{"name":"commit_bits_entries_1_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_1_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_trap_instruction_peId","width":8},{"name":"commit_bits_entries_1_trap_instruction_stid","width":1},{"name":"commit_bits_entries_1_trap_kind","width":2},{"name":"commit_bits_entries_1_trap_rob_bid","width":8},{"name":"commit_bits_entries_1_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_trap_rob_peId","width":8},{"name":"commit_bits_entries_1_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_trap_rob_stid","width":1},{"name":"commit_bits_entries_1_trap_targetPc","width":64},{"name":"commit_bits_entries_1_trap_tval","width":64},{"name":"commit_bits_entries_1_trap_valid","width":1},{"name":"commit_bits_entries_2_destination_atag","width":6},{"name":"commit_bits_entries_2_destination_kind","width":3},{"name":"commit_bits_entries_2_destination_pGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPtag","width":7},{"name":"commit_bits_entries_2_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousTtag","width":5},{"name":"commit_bits_entries_2_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousUtag","width":5},{"name":"commit_bits_entries_2_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_2_destination_ptag","width":7},{"name":"commit_bits_entries_2_destination_ptagValid","width":1},{"name":"commit_bits_entries_2_destination_tGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_ttag","width":5},{"name":"commit_bits_entries_2_destination_ttagValid","width":1},{"name":"commit_bits_entries_2_destination_uGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_utag","width":5},{"name":"commit_bits_entries_2_destination_utagValid","width":1},{"name":"commit_bits_entries_2_destination_valid","width":1},{"name":"commit_bits_entries_2_instruction_epoch","width":16},{"name":"commit_bits_entries_2_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_instruction_peId","width":8},{"name":"commit_bits_entries_2_instruction_stid","width":1},{"name":"commit_bits_entries_2_instructionBits","width":64},{"name":"commit_bits_entries_2_instructionLengthBytes","width":4},{"name":"commit_bits_entries_2_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_2_memory_lsid","width":32},{"name":"commit_bits_entries_2_memory_pipeId","width":1},{"name":"commit_bits_entries_2_memory_rob_bid","width":8},{"name":"commit_bits_entries_2_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_memory_rob_peId","width":8},{"name":"commit_bits_entries_2_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_memory_rob_stid","width":1},{"name":"commit_bits_entries_2_memory_transaction_generation","width":16},{"name":"commit_bits_entries_2_memory_transaction_value","width":64},{"name":"commit_bits_entries_2_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_2_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_2_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_2_memoryStore","width":1},{"name":"commit_bits_entries_2_memoryValid","width":1},{"name":"commit_bits_entries_2_opcode","width":12},{"name":"commit_bits_entries_2_pc","width":64},{"name":"commit_bits_entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_2_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_2_result","width":64},{"name":"commit_bits_entries_2_resultValid","width":1},{"name":"commit_bits_entries_2_rob_bid","width":8},{"name":"commit_bits_entries_2_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_rob_peId","width":8},{"name":"commit_bits_entries_2_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_rob_stid","width":1},{"name":"commit_bits_entries_2_robGroupLast","width":1},{"name":"commit_bits_entries_2_storeData","width":64},{"name":"commit_bits_entries_2_storeMask","width":8},{"name":"commit_bits_entries_2_trap_cause","width":32},{"name":"commit_bits_entries_2_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_2_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_trap_instruction_peId","width":8},{"name":"commit_bits_entries_2_trap_instruction_stid","width":1},{"name":"commit_bits_entries_2_trap_kind","width":2},{"name":"commit_bits_entries_2_trap_rob_bid","width":8},{"name":"commit_bits_entries_2_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_trap_rob_peId","width":8},{"name":"commit_bits_entries_2_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_trap_rob_stid","width":1},{"name":"commit_bits_entries_2_trap_targetPc","width":64},{"name":"commit_bits_entries_2_trap_tval","width":64},{"name":"commit_bits_entries_2_trap_valid","width":1},{"name":"commit_bits_entries_3_destination_atag","width":6},{"name":"commit_bits_entries_3_destination_kind","width":3},{"name":"commit_bits_entries_3_destination_pGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPtag","width":7},{"name":"commit_bits_entries_3_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousTtag","width":5},{"name":"commit_bits_entries_3_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousUtag","width":5},{"name":"commit_bits_entries_3_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_3_destination_ptag","width":7},{"name":"commit_bits_entries_3_destination_ptagValid","width":1},{"name":"commit_bits_entries_3_destination_tGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_ttag","width":5},{"name":"commit_bits_entries_3_destination_ttagValid","width":1},{"name":"commit_bits_entries_3_destination_uGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_utag","width":5},{"name":"commit_bits_entries_3_destination_utagValid","width":1},{"name":"commit_bits_entries_3_destination_valid","width":1},{"name":"commit_bits_entries_3_instruction_epoch","width":16},{"name":"commit_bits_entries_3_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_instruction_peId","width":8},{"name":"commit_bits_entries_3_instruction_stid","width":1},{"name":"commit_bits_entries_3_instructionBits","width":64},{"name":"commit_bits_entries_3_instructionLengthBytes","width":4},{"name":"commit_bits_entries_3_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_3_memory_lsid","width":32},{"name":"commit_bits_entries_3_memory_pipeId","width":1},{"name":"commit_bits_entries_3_memory_rob_bid","width":8},{"name":"commit_bits_entries_3_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_memory_rob_peId","width":8},{"name":"commit_bits_entries_3_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_memory_rob_stid","width":1},{"name":"commit_bits_entries_3_memory_transaction_generation","width":16},{"name":"commit_bits_entries_3_memory_transaction_value","width":64},{"name":"commit_bits_entries_3_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_3_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_3_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_3_memoryStore","width":1},{"name":"commit_bits_entries_3_memoryValid","width":1},{"name":"commit_bits_entries_3_opcode","width":12},{"name":"commit_bits_entries_3_pc","width":64},{"name":"commit_bits_entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_3_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_3_result","width":64},{"name":"commit_bits_entries_3_resultValid","width":1},{"name":"commit_bits_entries_3_rob_bid","width":8},{"name":"commit_bits_entries_3_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_rob_peId","width":8},{"name":"commit_bits_entries_3_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_rob_stid","width":1},{"name":"commit_bits_entries_3_robGroupLast","width":1},{"name":"commit_bits_entries_3_storeData","width":64},{"name":"commit_bits_entries_3_storeMask","width":8},{"name":"commit_bits_entries_3_trap_cause","width":32},{"name":"commit_bits_entries_3_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_3_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_trap_instruction_peId","width":8},{"name":"commit_bits_entries_3_trap_instruction_stid","width":1},{"name":"commit_bits_entries_3_trap_kind","width":2},{"name":"commit_bits_entries_3_trap_rob_bid","width":8},{"name":"commit_bits_entries_3_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_trap_rob_peId","width":8},{"name":"commit_bits_entries_3_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_trap_rob_stid","width":1},{"name":"commit_bits_entries_3_trap_targetPc","width":64},{"name":"commit_bits_entries_3_trap_tval","width":64},{"name":"commit_bits_entries_3_trap_valid","width":1},{"name":"commit_ready","width":1},{"name":"commit_valid","width":1},{"name":"dataMemoryRequest_0_bits_accessKind","width":2},{"name":"dataMemoryRequest_0_bits_address","width":64},{"name":"dataMemoryRequest_0_bits_byteMask","width":8},{"name":"dataMemoryRequest_0_bits_command","width":3},{"name":"dataMemoryRequest_0_bits_data","width":64},{"name":"dataMemoryRequest_0_bits_identity_generation","width":16},{"name":"dataMemoryRequest_0_bits_identity_value","width":64},{"name":"dataMemoryRequest_0_bits_instructionSide","width":1},{"name":"dataMemoryRequest_0_bits_size","width":3},{"name":"dataMemoryRequest_0_ready","width":1},{"name":"dataMemoryRequest_0_valid","width":1},{"name":"dataMemoryRequest_1_bits_accessKind","width":2},{"name":"dataMemoryRequest_1_bits_address","width":64},{"name":"dataMemoryRequest_1_bits_byteMask","width":8},{"name":"dataMemoryRequest_1_bits_command","width":3},{"name":"dataMemoryRequest_1_bits_data","width":64},{"name":"dataMemoryRequest_1_bits_identity_generation","width":16},{"name":"dataMemoryRequest_1_bits_identity_value","width":64},{"name":"dataMemoryRequest_1_bits_instructionSide","width":1},{"name":"dataMemoryRequest_1_bits_size","width":3},{"name":"dataMemoryRequest_1_ready","width":1},{"name":"dataMemoryRequest_1_valid","width":1},{"name":"dataMemoryRequest_2_bits_accessKind","width":2},{"name":"dataMemoryRequest_2_bits_address","width":64},{"name":"dataMemoryRequest_2_bits_byteMask","width":8},{"name":"dataMemoryRequest_2_bits_command","width":3},{"name":"dataMemoryRequest_2_bits_data","width":64},{"name":"dataMemoryRequest_2_bits_identity_generation","width":16},{"name":"dataMemoryRequest_2_bits_identity_value","width":64},{"name":"dataMemoryRequest_2_bits_instructionSide","width":1},{"name":"dataMemoryRequest_2_bits_size","width":3},{"name":"dataMemoryRequest_2_ready","width":1},{"name":"dataMemoryRequest_2_valid","width":1},{"name":"dataMemoryRequest_3_bits_accessKind","width":2},{"name":"dataMemoryRequest_3_bits_address","width":64},{"name":"dataMemoryRequest_3_bits_byteMask","width":8},{"name":"dataMemoryRequest_3_bits_command","width":3},{"name":"dataMemoryRequest_3_bits_data","width":64},{"name":"dataMemoryRequest_3_bits_identity_generation","width":16},{"name":"dataMemoryRequest_3_bits_identity_value","width":64},{"name":"dataMemoryRequest_3_bits_instructionSide","width":1},{"name":"dataMemoryRequest_3_bits_size","width":3},{"name":"dataMemoryRequest_3_ready","width":1},{"name":"dataMemoryRequest_3_valid","width":1},{"name":"dataMemoryResponse_0_bits_address","width":64},{"name":"dataMemoryResponse_0_bits_attributesValid","width":1},{"name":"dataMemoryResponse_0_bits_cacheable","width":1},{"name":"dataMemoryResponse_0_bits_corrupt","width":1},{"name":"dataMemoryResponse_0_bits_data","width":64},{"name":"dataMemoryResponse_0_bits_denied","width":1},{"name":"dataMemoryResponse_0_bits_device","width":1},{"name":"dataMemoryResponse_0_bits_errorCause","width":32},{"name":"dataMemoryResponse_0_bits_identity_generation","width":16},{"name":"dataMemoryResponse_0_bits_identity_value","width":64},{"name":"dataMemoryResponse_0_bits_lineData","width":512},{"name":"dataMemoryResponse_0_bits_readable","width":1},{"name":"dataMemoryResponse_0_bits_writable","width":1},{"name":"dataMemoryResponse_0_ready","width":1},{"name":"dataMemoryResponse_0_valid","width":1},{"name":"dataMemoryResponse_1_bits_address","width":64},{"name":"dataMemoryResponse_1_bits_attributesValid","width":1},{"name":"dataMemoryResponse_1_bits_cacheable","width":1},{"name":"dataMemoryResponse_1_bits_corrupt","width":1},{"name":"dataMemoryResponse_1_bits_data","width":64},{"name":"dataMemoryResponse_1_bits_denied","width":1},{"name":"dataMemoryResponse_1_bits_device","width":1},{"name":"dataMemoryResponse_1_bits_errorCause","width":32},{"name":"dataMemoryResponse_1_bits_identity_generation","width":16},{"name":"dataMemoryResponse_1_bits_identity_value","width":64},{"name":"dataMemoryResponse_1_bits_lineData","width":512},{"name":"dataMemoryResponse_1_bits_readable","width":1},{"name":"dataMemoryResponse_1_bits_writable","width":1},{"name":"dataMemoryResponse_1_ready","width":1},{"name":"dataMemoryResponse_1_valid","width":1},{"name":"dataMemoryResponse_2_bits_address","width":64},{"name":"dataMemoryResponse_2_bits_attributesValid","width":1},{"name":"dataMemoryResponse_2_bits_cacheable","width":1},{"name":"dataMemoryResponse_2_bits_corrupt","width":1},{"name":"dataMemoryResponse_2_bits_data","width":64},{"name":"dataMemoryResponse_2_bits_denied","width":1},{"name":"dataMemoryResponse_2_bits_device","width":1},{"name":"dataMemoryResponse_2_bits_errorCause","width":32},{"name":"dataMemoryResponse_2_bits_identity_generation","width":16},{"name":"dataMemoryResponse_2_bits_identity_value","width":64},{"name":"dataMemoryResponse_2_bits_lineData","width":512},{"name":"dataMemoryResponse_2_bits_readable","width":1},{"name":"dataMemoryResponse_2_bits_writable","width":1},{"name":"dataMemoryResponse_2_ready","width":1},{"name":"dataMemoryResponse_2_valid","width":1},{"name":"dataMemoryResponse_3_bits_address","width":64},{"name":"dataMemoryResponse_3_bits_attributesValid","width":1},{"name":"dataMemoryResponse_3_bits_cacheable","width":1},{"name":"dataMemoryResponse_3_bits_corrupt","width":1},{"name":"dataMemoryResponse_3_bits_data","width":64},{"name":"dataMemoryResponse_3_bits_denied","width":1},{"name":"dataMemoryResponse_3_bits_device","width":1},{"name":"dataMemoryResponse_3_bits_errorCause","width":32},{"name":"dataMemoryResponse_3_bits_identity_generation","width":16},{"name":"dataMemoryResponse_3_bits_identity_value","width":64},{"name":"dataMemoryResponse_3_bits_lineData","width":512},{"name":"dataMemoryResponse_3_bits_readable","width":1},{"name":"dataMemoryResponse_3_bits_writable","width":1},{"name":"dataMemoryResponse_3_ready","width":1},{"name":"dataMemoryResponse_3_valid","width":1},{"name":"debugRequest_bits_address","width":64},{"name":"debugRequest_bits_command","width":3},{"name":"debugRequest_bits_data","width":64},{"name":"debugRequest_bits_stid","width":1},{"name":"debugRequest_bits_transactionId","width":64},{"name":"debugRequest_ready","width":1},{"name":"debugRequest_valid","width":1},{"name":"debugResponse_bits_accepted","width":1},{"name":"debugResponse_bits_data","width":64},{"name":"debugResponse_bits_error","width":1},{"name":"debugResponse_bits_transactionId","width":64},{"name":"debugResponse_ready","width":1},{"name":"debugResponse_valid","width":1},{"name":"instructionMemoryRequest_bits_accessKind","width":2},{"name":"instructionMemoryRequest_bits_address","width":64},{"name":"instructionMemoryRequest_bits_byteMask","width":8},{"name":"instructionMemoryRequest_bits_command","width":3},{"name":"instructionMemoryRequest_bits_data","width":64},{"name":"instructionMemoryRequest_bits_identity_generation","width":16},{"name":"instructionMemoryRequest_bits_identity_value","width":64},{"name":"instructionMemoryRequest_bits_instructionSide","width":1},{"name":"instructionMemoryRequest_bits_size","width":3},{"name":"instructionMemoryRequest_ready","width":1},{"name":"instructionMemoryRequest_valid","width":1},{"name":"instructionMemoryResponse_bits_address","width":64},{"name":"instructionMemoryResponse_bits_attributesValid","width":1},{"name":"instructionMemoryResponse_bits_cacheable","width":1},{"name":"instructionMemoryResponse_bits_corrupt","width":1},{"name":"instructionMemoryResponse_bits_data","width":64},{"name":"instructionMemoryResponse_bits_denied","width":1},{"name":"instructionMemoryResponse_bits_device","width":1},{"name":"instructionMemoryResponse_bits_errorCause","width":32},{"name":"instructionMemoryResponse_bits_identity_generation","width":16},{"name":"instructionMemoryResponse_bits_identity_value","width":64},{"name":"instructionMemoryResponse_bits_lineData","width":512},{"name":"instructionMemoryResponse_bits_readable","width":1},{"name":"instructionMemoryResponse_bits_writable","width":1},{"name":"instructionMemoryResponse_ready","width":1},{"name":"instructionMemoryResponse_valid","width":1},{"name":"interrupt_bits_cause","width":32},{"name":"interrupt_bits_priority","width":8},{"name":"interrupt_bits_stid","width":1},{"name":"interrupt_bits_valid","width":1},{"name":"interrupt_valid","width":1},{"name":"loadReissueRequest_bits_address","width":64},{"name":"loadReissueRequest_bits_allocationId_generation","width":16},{"name":"loadReissueRequest_bits_allocationId_value","width":64},{"name":"loadReissueRequest_bits_currentIdentity_attemptGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_lsid","width":32},{"name":"loadReissueRequest_bits_currentIdentity_pipeId","width":1},{"name":"loadReissueRequest_bits_currentIdentity_rob_bid","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_brobGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_memberIndex","width":2},{"name":"loadReissueRequest_bits_currentIdentity_rob_peId","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_residentGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridSlot","width":6},{"name":"loadReissueRequest_bits_currentIdentity_rob_stid","width":1},{"name":"loadReissueRequest_bits_currentIdentity_transaction_generation","width":16},{"name":"loadReissueRequest_bits_currentIdentity_transaction_value","width":64},{"name":"loadReissueRequest_ready","width":1},{"name":"loadReissueRequest_valid","width":1},{"name":"lsuProtocolError","width":1},{"name":"lsuQuiescent","width":1},{"name":"maintenance_bits_address","width":64},{"name":"maintenance_bits_command","width":2},{"name":"maintenance_ready","width":1},{"name":"maintenance_valid","width":1},{"name":"maintenanceResult_bits_address","width":64},{"name":"maintenanceResult_bits_command","width":2},{"name":"maintenanceResult_bits_success","width":1},{"name":"maintenanceResult_ready","width":1},{"name":"maintenanceResult_valid","width":1},{"name":"memoryFault_bits_address","width":64},{"name":"memoryFault_bits_cause","width":1},{"name":"memoryFault_bits_identity_attemptGeneration","width":16},{"name":"memoryFault_bits_identity_lsid","width":32},{"name":"memoryFault_bits_identity_pipeId","width":1},{"name":"memoryFault_bits_identity_rob_bid","width":8},{"name":"memoryFault_bits_identity_rob_brobGeneration","width":16},{"name":"memoryFault_bits_identity_rob_memberIndex","width":2},{"name":"memoryFault_bits_identity_rob_peId","width":8},{"name":"memoryFault_bits_identity_rob_residentGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridSlot","width":6},{"name":"memoryFault_bits_identity_rob_stid","width":1},{"name":"memoryFault_bits_identity_transaction_generation","width":16},{"name":"memoryFault_bits_identity_transaction_value","width":64},{"name":"memoryFault_bits_write","width":1},{"name":"memoryFault_ready","width":1},{"name":"memoryFault_valid","width":1},{"name":"pInit_bits_atag","width":5},{"name":"pInit_bits_epoch","width":16},{"name":"pInit_bits_generation","width":16},{"name":"pInit_bits_ptag","width":7},{"name":"pInit_bits_stid","width":1},{"name":"pInit_bits_value","width":64},{"name":"pInit_ready","width":1},{"name":"pInit_valid","width":1},{"name":"performanceCounters_0","width":64},{"name":"performanceCounters_1","width":64},{"name":"performanceCounters_2","width":64},{"name":"performanceCounters_3","width":64},{"name":"performanceCounters_4","width":64},{"name":"performanceCounters_5","width":64},{"name":"performanceCounters_6","width":64},{"name":"performanceCounters_7","width":64},{"name":"performanceCounters_8","width":64},{"name":"performanceCounters_9","width":64},{"name":"performanceCounters_10","width":64},{"name":"performanceCounters_11","width":64},{"name":"performanceCounters_12","width":64},{"name":"performanceCounters_13","width":64},{"name":"performanceCounters_14","width":64},{"name":"performanceCounters_15","width":64},{"name":"performanceCounters_16","width":64},{"name":"performanceCounters_17","width":64},{"name":"performanceCounters_18","width":64},{"name":"performanceCounters_19","width":64},{"name":"performanceCounters_20","width":64},{"name":"performanceCounters_21","width":64},{"name":"performanceCounters_22","width":64},{"name":"performanceCounters_23","width":64},{"name":"performanceCounters_24","width":64},{"name":"performanceCounters_25","width":64},{"name":"performanceCounters_26","width":64},{"name":"performanceCounters_27","width":64},{"name":"performanceCounters_28","width":64},{"name":"performanceCounters_29","width":64},{"name":"performanceCounters_30","width":64},{"name":"performanceCounters_31","width":64},{"name":"systemIssue_0_bits_immediate","width":64},{"name":"systemIssue_0_bits_instruction_epoch","width":16},{"name":"systemIssue_0_bits_instruction_instructionId","width":64},{"name":"systemIssue_0_bits_instruction_peId","width":8},{"name":"systemIssue_0_bits_instruction_stid","width":1},{"name":"systemIssue_0_bits_opcode","width":12},{"name":"systemIssue_0_bits_rob_bid","width":8},{"name":"systemIssue_0_bits_rob_brobGeneration","width":16},{"name":"systemIssue_0_bits_rob_memberIndex","width":2},{"name":"systemIssue_0_bits_rob_peId","width":8},{"name":"systemIssue_0_bits_rob_residentGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridSlot","width":6},{"name":"systemIssue_0_bits_rob_stid","width":1},{"name":"systemIssue_0_bits_transactionId","width":64},{"name":"systemIssue_0_ready","width":1},{"name":"systemIssue_0_valid","width":1},{"name":"trace_bits_count","width":3},{"name":"trace_bits_entries_0_cycle","width":64},{"name":"trace_bits_entries_0_instruction_epoch","width":16},{"name":"trace_bits_entries_0_instruction_instructionId","width":64},{"name":"trace_bits_entries_0_instruction_peId","width":8},{"name":"trace_bits_entries_0_instruction_stid","width":1},{"name":"trace_bits_entries_0_instructionValid","width":1},{"name":"trace_bits_entries_0_kind","width":3},{"name":"trace_bits_entries_0_opcode","width":12},{"name":"trace_bits_entries_0_payload","width":64},{"name":"trace_bits_entries_0_pc","width":64},{"name":"trace_bits_entries_0_rob_bid","width":8},{"name":"trace_bits_entries_0_rob_brobGeneration","width":16},{"name":"trace_bits_entries_0_rob_memberIndex","width":2},{"name":"trace_bits_entries_0_rob_peId","width":8},{"name":"trace_bits_entries_0_rob_residentGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridSlot","width":6},{"name":"trace_bits_entries_0_rob_stid","width":1},{"name":"trace_bits_entries_0_robValid","width":1},{"name":"trace_bits_entries_0_source","width":3},{"name":"trace_bits_entries_1_cycle","width":64},{"name":"trace_bits_entries_1_instruction_epoch","width":16},{"name":"trace_bits_entries_1_instruction_instructionId","width":64},{"name":"trace_bits_entries_1_instruction_peId","width":8},{"name":"trace_bits_entries_1_instruction_stid","width":1},{"name":"trace_bits_entries_1_instructionValid","width":1},{"name":"trace_bits_entries_1_kind","width":3},{"name":"trace_bits_entries_1_opcode","width":12},{"name":"trace_bits_entries_1_payload","width":64},{"name":"trace_bits_entries_1_pc","width":64},{"name":"trace_bits_entries_1_rob_bid","width":8},{"name":"trace_bits_entries_1_rob_brobGeneration","width":16},{"name":"trace_bits_entries_1_rob_memberIndex","width":2},{"name":"trace_bits_entries_1_rob_peId","width":8},{"name":"trace_bits_entries_1_rob_residentGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridSlot","width":6},{"name":"trace_bits_entries_1_rob_stid","width":1},{"name":"trace_bits_entries_1_robValid","width":1},{"name":"trace_bits_entries_1_source","width":3},{"name":"trace_bits_entries_2_cycle","width":64},{"name":"trace_bits_entries_2_instruction_epoch","width":16},{"name":"trace_bits_entries_2_instruction_instructionId","width":64},{"name":"trace_bits_entries_2_instruction_peId","width":8},{"name":"trace_bits_entries_2_instruction_stid","width":1},{"name":"trace_bits_entries_2_instructionValid","width":1},{"name":"trace_bits_entries_2_kind","width":3},{"name":"trace_bits_entries_2_opcode","width":12},{"name":"trace_bits_entries_2_payload","width":64},{"name":"trace_bits_entries_2_pc","width":64},{"name":"trace_bits_entries_2_rob_bid","width":8},{"name":"trace_bits_entries_2_rob_brobGeneration","width":16},{"name":"trace_bits_entries_2_rob_memberIndex","width":2},{"name":"trace_bits_entries_2_rob_peId","width":8},{"name":"trace_bits_entries_2_rob_residentGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridSlot","width":6},{"name":"trace_bits_entries_2_rob_stid","width":1},{"name":"trace_bits_entries_2_robValid","width":1},{"name":"trace_bits_entries_2_source","width":3},{"name":"trace_bits_entries_3_cycle","width":64},{"name":"trace_bits_entries_3_instruction_epoch","width":16},{"name":"trace_bits_entries_3_instruction_instructionId","width":64},{"name":"trace_bits_entries_3_instruction_peId","width":8},{"name":"trace_bits_entries_3_instruction_stid","width":1},{"name":"trace_bits_entries_3_instructionValid","width":1},{"name":"trace_bits_entries_3_kind","width":3},{"name":"trace_bits_entries_3_opcode","width":12},{"name":"trace_bits_entries_3_payload","width":64},{"name":"trace_bits_entries_3_pc","width":64},{"name":"trace_bits_entries_3_rob_bid","width":8},{"name":"trace_bits_entries_3_rob_brobGeneration","width":16},{"name":"trace_bits_entries_3_rob_memberIndex","width":2},{"name":"trace_bits_entries_3_rob_peId","width":8},{"name":"trace_bits_entries_3_rob_residentGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridSlot","width":6},{"name":"trace_bits_entries_3_rob_stid","width":1},{"name":"trace_bits_entries_3_robValid","width":1},{"name":"trace_bits_entries_3_source","width":3},{"name":"trace_ready","width":1},{"name":"trace_valid","width":1},{"name":"trap_bits_cause","width":32},{"name":"trap_bits_instruction_epoch","width":16},{"name":"trap_bits_instruction_instructionId","width":64},{"name":"trap_bits_instruction_peId","width":8},{"name":"trap_bits_instruction_stid","width":1},{"name":"trap_bits_kind","width":2},{"name":"trap_bits_rob_bid","width":8},{"name":"trap_bits_rob_brobGeneration","width":16},{"name":"trap_bits_rob_memberIndex","width":2},{"name":"trap_bits_rob_peId","width":8},{"name":"trap_bits_rob_residentGeneration","width":16},{"name":"trap_bits_rob_ridGeneration","width":16},{"name":"trap_bits_rob_ridSlot","width":6},{"name":"trap_bits_rob_stid","width":1},{"name":"trap_bits_targetPc","width":64},{"name":"trap_bits_tval","width":64},{"name":"trap_bits_valid","width":1},{"name":"trap_ready","width":1},{"name":"trap_valid","width":1}]},{"name":"ifu_to_ctu","contract_id":"IFC-IFU-CTU-001","producer":"IFU","consumer":"CTU","lanes":4,"payload":"FetchedPacket","ports":[{"name":"count","width":3},{"name":"entries_0_fetchFault","width":1},{"name":"entries_0_fetchFaultCause","width":32},{"name":"entries_0_identity_epoch","width":16},{"name":"entries_0_identity_instructionId","width":64},{"name":"entries_0_identity_peId","width":8},{"name":"entries_0_identity_stid","width":1},{"name":"entries_0_instruction","width":64},{"name":"entries_0_lengthBytes","width":4},{"name":"entries_0_pc","width":64},{"name":"entries_0_prediction_checkpointId","width":5},{"name":"entries_0_prediction_confidence","width":2},{"name":"entries_0_prediction_epoch","width":16},{"name":"entries_0_prediction_fallthroughPc","width":64},{"name":"entries_0_prediction_kind","width":3},{"name":"entries_0_prediction_predictionTag","width":64},{"name":"entries_0_prediction_provider","width":4},{"name":"entries_0_prediction_requestPc","width":64},{"name":"entries_0_prediction_taken","width":1},{"name":"entries_0_prediction_target","width":64},{"name":"entries_0_prediction_transactionId","width":64},{"name":"entries_0_prediction_valid","width":1},{"name":"entries_1_fetchFault","width":1},{"name":"entries_1_fetchFaultCause","width":32},{"name":"entries_1_identity_epoch","width":16},{"name":"entries_1_identity_instructionId","width":64},{"name":"entries_1_identity_peId","width":8},{"name":"entries_1_identity_stid","width":1},{"name":"entries_1_instruction","width":64},{"name":"entries_1_lengthBytes","width":4},{"name":"entries_1_pc","width":64},{"name":"entries_1_prediction_checkpointId","width":5},{"name":"entries_1_prediction_confidence","width":2},{"name":"entries_1_prediction_epoch","width":16},{"name":"entries_1_prediction_fallthroughPc","width":64},{"name":"entries_1_prediction_kind","width":3},{"name":"entries_1_prediction_predictionTag","width":64},{"name":"entries_1_prediction_provider","width":4},{"name":"entries_1_prediction_requestPc","width":64},{"name":"entries_1_prediction_taken","width":1},{"name":"entries_1_prediction_target","width":64},{"name":"entries_1_prediction_transactionId","width":64},{"name":"entries_1_prediction_valid","width":1},{"name":"entries_2_fetchFault","width":1},{"name":"entries_2_fetchFaultCause","width":32},{"name":"entries_2_identity_epoch","width":16},{"name":"entries_2_identity_instructionId","width":64},{"name":"entries_2_identity_peId","width":8},{"name":"entries_2_identity_stid","width":1},{"name":"entries_2_instruction","width":64},{"name":"entries_2_lengthBytes","width":4},{"name":"entries_2_pc","width":64},{"name":"entries_2_prediction_checkpointId","width":5},{"name":"entries_2_prediction_confidence","width":2},{"name":"entries_2_prediction_epoch","width":16},{"name":"entries_2_prediction_fallthroughPc","width":64},{"name":"entries_2_prediction_kind","width":3},{"name":"entries_2_prediction_predictionTag","width":64},{"name":"entries_2_prediction_provider","width":4},{"name":"entries_2_prediction_requestPc","width":64},{"name":"entries_2_prediction_taken","width":1},{"name":"entries_2_prediction_target","width":64},{"name":"entries_2_prediction_transactionId","width":64},{"name":"entries_2_prediction_valid","width":1},{"name":"entries_3_fetchFault","width":1},{"name":"entries_3_fetchFaultCause","width":32},{"name":"entries_3_identity_epoch","width":16},{"name":"entries_3_identity_instructionId","width":64},{"name":"entries_3_identity_peId","width":8},{"name":"entries_3_identity_stid","width":1},{"name":"entries_3_instruction","width":64},{"name":"entries_3_lengthBytes","width":4},{"name":"entries_3_pc","width":64},{"name":"entries_3_prediction_checkpointId","width":5},{"name":"entries_3_prediction_confidence","width":2},{"name":"entries_3_prediction_epoch","width":16},{"name":"entries_3_prediction_fallthroughPc","width":64},{"name":"entries_3_prediction_kind","width":3},{"name":"entries_3_prediction_predictionTag","width":64},{"name":"entries_3_prediction_provider","width":4},{"name":"entries_3_prediction_requestPc","width":64},{"name":"entries_3_prediction_taken","width":1},{"name":"entries_3_prediction_target","width":64},{"name":"entries_3_prediction_transactionId","width":64},{"name":"entries_3_prediction_valid","width":1}]},{"name":"ctu_to_ooo","contract_id":"IFC-CTU-OOO-001","producer":"CTU","consumer":"OOO","lanes":4,"payload":"D1Packet","ports":[{"name":"count","width":3},{"name":"entries_0_kind","width":1},{"name":"entries_0_parent_fetchFault","width":1},{"name":"entries_0_parent_fetchFaultCause","width":32},{"name":"entries_0_parent_identity_epoch","width":16},{"name":"entries_0_parent_identity_instructionId","width":64},{"name":"entries_0_parent_identity_peId","width":8},{"name":"entries_0_parent_identity_stid","width":1},{"name":"entries_0_parent_instruction","width":64},{"name":"entries_0_parent_lengthBytes","width":4},{"name":"entries_0_parent_pc","width":64},{"name":"entries_0_parent_prediction_checkpointId","width":5},{"name":"entries_0_parent_prediction_confidence","width":2},{"name":"entries_0_parent_prediction_epoch","width":16},{"name":"entries_0_parent_prediction_fallthroughPc","width":64},{"name":"entries_0_parent_prediction_kind","width":3},{"name":"entries_0_parent_prediction_predictionTag","width":64},{"name":"entries_0_parent_prediction_provider","width":4},{"name":"entries_0_parent_prediction_requestPc","width":64},{"name":"entries_0_parent_prediction_taken","width":1},{"name":"entries_0_parent_prediction_target","width":64},{"name":"entries_0_parent_prediction_transactionId","width":64},{"name":"entries_0_parent_prediction_valid","width":1},{"name":"entries_0_templateCount","width":8},{"name":"entries_0_templateImmediate","width":64},{"name":"entries_0_templateOpcode","width":12},{"name":"entries_0_templateOrdinal","width":8},{"name":"entries_1_kind","width":1},{"name":"entries_1_parent_fetchFault","width":1},{"name":"entries_1_parent_fetchFaultCause","width":32},{"name":"entries_1_parent_identity_epoch","width":16},{"name":"entries_1_parent_identity_instructionId","width":64},{"name":"entries_1_parent_identity_peId","width":8},{"name":"entries_1_parent_identity_stid","width":1},{"name":"entries_1_parent_instruction","width":64},{"name":"entries_1_parent_lengthBytes","width":4},{"name":"entries_1_parent_pc","width":64},{"name":"entries_1_parent_prediction_checkpointId","width":5},{"name":"entries_1_parent_prediction_confidence","width":2},{"name":"entries_1_parent_prediction_epoch","width":16},{"name":"entries_1_parent_prediction_fallthroughPc","width":64},{"name":"entries_1_parent_prediction_kind","width":3},{"name":"entries_1_parent_prediction_predictionTag","width":64},{"name":"entries_1_parent_prediction_provider","width":4},{"name":"entries_1_parent_prediction_requestPc","width":64},{"name":"entries_1_parent_prediction_taken","width":1},{"name":"entries_1_parent_prediction_target","width":64},{"name":"entries_1_parent_prediction_transactionId","width":64},{"name":"entries_1_parent_prediction_valid","width":1},{"name":"entries_1_templateCount","width":8},{"name":"entries_1_templateImmediate","width":64},{"name":"entries_1_templateOpcode","width":12},{"name":"entries_1_templateOrdinal","width":8},{"name":"entries_2_kind","width":1},{"name":"entries_2_parent_fetchFault","width":1},{"name":"entries_2_parent_fetchFaultCause","width":32},{"name":"entries_2_parent_identity_epoch","width":16},{"name":"entries_2_parent_identity_instructionId","width":64},{"name":"entries_2_parent_identity_peId","width":8},{"name":"entries_2_parent_identity_stid","width":1},{"name":"entries_2_parent_instruction","width":64},{"name":"entries_2_parent_lengthBytes","width":4},{"name":"entries_2_parent_pc","width":64},{"name":"entries_2_parent_prediction_checkpointId","width":5},{"name":"entries_2_parent_prediction_confidence","width":2},{"name":"entries_2_parent_prediction_epoch","width":16},{"name":"entries_2_parent_prediction_fallthroughPc","width":64},{"name":"entries_2_parent_prediction_kind","width":3},{"name":"entries_2_parent_prediction_predictionTag","width":64},{"name":"entries_2_parent_prediction_provider","width":4},{"name":"entries_2_parent_prediction_requestPc","width":64},{"name":"entries_2_parent_prediction_taken","width":1},{"name":"entries_2_parent_prediction_target","width":64},{"name":"entries_2_parent_prediction_transactionId","width":64},{"name":"entries_2_parent_prediction_valid","width":1},{"name":"entries_2_templateCount","width":8},{"name":"entries_2_templateImmediate","width":64},{"name":"entries_2_templateOpcode","width":12},{"name":"entries_2_templateOrdinal","width":8},{"name":"entries_3_kind","width":1},{"name":"entries_3_parent_fetchFault","width":1},{"name":"entries_3_parent_fetchFaultCause","width":32},{"name":"entries_3_parent_identity_epoch","width":16},{"name":"entries_3_parent_identity_instructionId","width":64},{"name":"entries_3_parent_identity_peId","width":8},{"name":"entries_3_parent_identity_stid","width":1},{"name":"entries_3_parent_instruction","width":64},{"name":"entries_3_parent_lengthBytes","width":4},{"name":"entries_3_parent_pc","width":64},{"name":"entries_3_parent_prediction_checkpointId","width":5},{"name":"entries_3_parent_prediction_confidence","width":2},{"name":"entries_3_parent_prediction_epoch","width":16},{"name":"entries_3_parent_prediction_fallthroughPc","width":64},{"name":"entries_3_parent_prediction_kind","width":3},{"name":"entries_3_parent_prediction_predictionTag","width":64},{"name":"entries_3_parent_prediction_provider","width":4},{"name":"entries_3_parent_prediction_requestPc","width":64},{"name":"entries_3_parent_prediction_taken","width":1},{"name":"entries_3_parent_prediction_target","width":64},{"name":"entries_3_parent_prediction_transactionId","width":64},{"name":"entries_3_parent_prediction_valid","width":1},{"name":"entries_3_templateCount","width":8},{"name":"entries_3_templateImmediate","width":64},{"name":"entries_3_templateOpcode","width":12},{"name":"entries_3_templateOrdinal","width":8}]},{"name":"ooo_to_iex_alu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_bru","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_agu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_std","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"StoreDispatchTxn","ports":[{"name":"aguPipe","width":1},{"name":"sta_memoryOrder_firstLid","width":32},{"name":"sta_memoryOrder_firstLsid","width":32},{"name":"sta_memoryOrder_firstSid","width":32},{"name":"sta_memoryOrder_requestCount","width":2},{"name":"sta_memoryOrder_yoldLid","width":32},{"name":"sta_memoryOrder_yoldLsid","width":32},{"name":"sta_memoryOrder_yoldValid","width":1},{"name":"sta_memoryOrder_yostLsid","width":32},{"name":"sta_memoryOrder_yostSid","width":32},{"name":"sta_memoryOrder_yostValid","width":1},{"name":"sta_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"sta_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"sta_pcBufferIndexOffset_pcOffset","width":7},{"name":"sta_pcBufferIndexOffset_valid","width":1},{"name":"sta_transactionId","width":64},{"name":"sta_trap_cause","width":32},{"name":"sta_trap_valid","width":1},{"name":"sta_uop_decoded_blockBoundary","width":1},{"name":"sta_uop_decoded_blockStart","width":1},{"name":"sta_uop_decoded_blockStop","width":1},{"name":"sta_uop_decoded_classification_complexBreak","width":1},{"name":"sta_uop_decoded_classification_dispatchClass","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_0","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_1","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_2","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_3","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_4","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_5","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_6","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_7","width":3},{"name":"sta_uop_decoded_classification_dispatchWrites","width":3},{"name":"sta_uop_decoded_classification_disposition","width":2},{"name":"sta_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"sta_uop_decoded_classification_fastResolveClass","width":3},{"name":"sta_uop_decoded_classification_fusionHeadClass","width":2},{"name":"sta_uop_decoded_classification_fusionTailClass","width":2},{"name":"sta_uop_decoded_classification_implicitDestination","width":2},{"name":"sta_uop_decoded_classification_implicitSourceMask","width":4},{"name":"sta_uop_decoded_classification_kind","width":4},{"name":"sta_uop_decoded_classification_mayRedirect","width":1},{"name":"sta_uop_decoded_classification_mayTrap","width":1},{"name":"sta_uop_decoded_classification_mayTrapLate","width":1},{"name":"sta_uop_decoded_classification_memoryRequestCount","width":2},{"name":"sta_uop_decoded_classification_nonspeculative","width":1},{"name":"sta_uop_decoded_classification_pDestinationCount","width":2},{"name":"sta_uop_decoded_classification_pSourceCount","width":3},{"name":"sta_uop_decoded_classification_pcReadClass","width":4},{"name":"sta_uop_decoded_classification_pcReadRequired","width":1},{"name":"sta_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"sta_uop_decoded_classification_sideEffectOwner","width":3},{"name":"sta_uop_decoded_classification_splitKind","width":2},{"name":"sta_uop_decoded_classification_tAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uopCountMax","width":6},{"name":"sta_uop_decoded_classification_uopCountMin","width":6},{"name":"sta_uop_decoded_classification_valid","width":1},{"name":"sta_uop_decoded_destinations_0_atag","width":6},{"name":"sta_uop_decoded_destinations_0_kind","width":3},{"name":"sta_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_0_valid","width":1},{"name":"sta_uop_decoded_destinations_1_atag","width":6},{"name":"sta_uop_decoded_destinations_1_kind","width":3},{"name":"sta_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_1_valid","width":1},{"name":"sta_uop_decoded_earlyComplete","width":1},{"name":"sta_uop_decoded_immediate","width":64},{"name":"sta_uop_decoded_immediateValid","width":1},{"name":"sta_uop_decoded_instruction_kind","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"sta_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"sta_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"sta_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"sta_uop_decoded_instruction_parent_instruction","width":64},{"name":"sta_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"sta_uop_decoded_instruction_parent_pc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"sta_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"sta_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"sta_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"sta_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"sta_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"sta_uop_decoded_instruction_templateCount","width":8},{"name":"sta_uop_decoded_instruction_templateImmediate","width":64},{"name":"sta_uop_decoded_instruction_templateOpcode","width":12},{"name":"sta_uop_decoded_instruction_templateOrdinal","width":8},{"name":"sta_uop_decoded_memory_accessBytes","width":4},{"name":"sta_uop_decoded_memory_addressMode","width":2},{"name":"sta_uop_decoded_memory_addressSourceMask","width":4},{"name":"sta_uop_decoded_memory_dataSourceMask","width":4},{"name":"sta_uop_decoded_memory_indexMode","width":2},{"name":"sta_uop_decoded_memory_indexShift","width":5},{"name":"sta_uop_decoded_memory_isLoad","width":1},{"name":"sta_uop_decoded_memory_isStore","width":1},{"name":"sta_uop_decoded_memory_offset","width":64},{"name":"sta_uop_decoded_memory_requestCount","width":2},{"name":"sta_uop_decoded_memory_signExtend","width":1},{"name":"sta_uop_decoded_memory_valid","width":1},{"name":"sta_uop_decoded_memory_writebackPreIndex","width":1},{"name":"sta_uop_decoded_memory_writebackValid","width":1},{"name":"sta_uop_decoded_opcode","width":12},{"name":"sta_uop_decoded_rob_bid","width":8},{"name":"sta_uop_decoded_rob_brobGeneration","width":16},{"name":"sta_uop_decoded_rob_memberIndex","width":2},{"name":"sta_uop_decoded_rob_peId","width":8},{"name":"sta_uop_decoded_rob_residentGeneration","width":16},{"name":"sta_uop_decoded_rob_ridGeneration","width":16},{"name":"sta_uop_decoded_rob_ridSlot","width":6},{"name":"sta_uop_decoded_rob_stid","width":1},{"name":"sta_uop_decoded_sources_0_atag","width":6},{"name":"sta_uop_decoded_sources_0_kind","width":3},{"name":"sta_uop_decoded_sources_0_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_0_valid","width":1},{"name":"sta_uop_decoded_sources_1_atag","width":6},{"name":"sta_uop_decoded_sources_1_kind","width":3},{"name":"sta_uop_decoded_sources_1_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_1_valid","width":1},{"name":"sta_uop_decoded_sources_2_atag","width":6},{"name":"sta_uop_decoded_sources_2_kind","width":3},{"name":"sta_uop_decoded_sources_2_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_2_valid","width":1},{"name":"sta_uop_decoded_sources_3_atag","width":6},{"name":"sta_uop_decoded_sources_3_kind","width":3},{"name":"sta_uop_decoded_sources_3_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_3_valid","width":1},{"name":"sta_uop_decoded_uopClass","width":3},{"name":"sta_uop_decoded_valid","width":1},{"name":"sta_uop_destinations_0_atag","width":6},{"name":"sta_uop_destinations_0_kind","width":3},{"name":"sta_uop_destinations_0_pGeneration","width":16},{"name":"sta_uop_destinations_0_previousPGeneration","width":16},{"name":"sta_uop_destinations_0_previousPtag","width":7},{"name":"sta_uop_destinations_0_previousPtagValid","width":1},{"name":"sta_uop_destinations_0_previousTtag","width":5},{"name":"sta_uop_destinations_0_previousTtagValid","width":1},{"name":"sta_uop_destinations_0_previousUtag","width":5},{"name":"sta_uop_destinations_0_previousUtagValid","width":1},{"name":"sta_uop_destinations_0_ptag","width":7},{"name":"sta_uop_destinations_0_ptagValid","width":1},{"name":"sta_uop_destinations_0_tGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqIndex","width":5},{"name":"sta_uop_destinations_0_ttag","width":5},{"name":"sta_uop_destinations_0_ttagValid","width":1},{"name":"sta_uop_destinations_0_uGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqIndex","width":5},{"name":"sta_uop_destinations_0_utag","width":5},{"name":"sta_uop_destinations_0_utagValid","width":1},{"name":"sta_uop_destinations_0_valid","width":1},{"name":"sta_uop_destinations_1_atag","width":6},{"name":"sta_uop_destinations_1_kind","width":3},{"name":"sta_uop_destinations_1_pGeneration","width":16},{"name":"sta_uop_destinations_1_previousPGeneration","width":16},{"name":"sta_uop_destinations_1_previousPtag","width":7},{"name":"sta_uop_destinations_1_previousPtagValid","width":1},{"name":"sta_uop_destinations_1_previousTtag","width":5},{"name":"sta_uop_destinations_1_previousTtagValid","width":1},{"name":"sta_uop_destinations_1_previousUtag","width":5},{"name":"sta_uop_destinations_1_previousUtagValid","width":1},{"name":"sta_uop_destinations_1_ptag","width":7},{"name":"sta_uop_destinations_1_ptagValid","width":1},{"name":"sta_uop_destinations_1_tGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqIndex","width":5},{"name":"sta_uop_destinations_1_ttag","width":5},{"name":"sta_uop_destinations_1_ttagValid","width":1},{"name":"sta_uop_destinations_1_uGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqIndex","width":5},{"name":"sta_uop_destinations_1_utag","width":5},{"name":"sta_uop_destinations_1_utagValid","width":1},{"name":"sta_uop_destinations_1_valid","width":1},{"name":"sta_uop_sources_0_atag","width":6},{"name":"sta_uop_sources_0_kind","width":3},{"name":"sta_uop_sources_0_pGeneration","width":16},{"name":"sta_uop_sources_0_ptag","width":7},{"name":"sta_uop_sources_0_ptagValid","width":1},{"name":"sta_uop_sources_0_ready","width":1},{"name":"sta_uop_sources_0_tGeneration","width":16},{"name":"sta_uop_sources_0_tSeqGeneration","width":16},{"name":"sta_uop_sources_0_tSeqIndex","width":5},{"name":"sta_uop_sources_0_ttag","width":5},{"name":"sta_uop_sources_0_ttagValid","width":1},{"name":"sta_uop_sources_0_uGeneration","width":16},{"name":"sta_uop_sources_0_uSeqGeneration","width":16},{"name":"sta_uop_sources_0_uSeqIndex","width":5},{"name":"sta_uop_sources_0_utag","width":5},{"name":"sta_uop_sources_0_utagValid","width":1},{"name":"sta_uop_sources_0_valid","width":1},{"name":"sta_uop_sources_1_atag","width":6},{"name":"sta_uop_sources_1_kind","width":3},{"name":"sta_uop_sources_1_pGeneration","width":16},{"name":"sta_uop_sources_1_ptag","width":7},{"name":"sta_uop_sources_1_ptagValid","width":1},{"name":"sta_uop_sources_1_ready","width":1},{"name":"sta_uop_sources_1_tGeneration","width":16},{"name":"sta_uop_sources_1_tSeqGeneration","width":16},{"name":"sta_uop_sources_1_tSeqIndex","width":5},{"name":"sta_uop_sources_1_ttag","width":5},{"name":"sta_uop_sources_1_ttagValid","width":1},{"name":"sta_uop_sources_1_uGeneration","width":16},{"name":"sta_uop_sources_1_uSeqGeneration","width":16},{"name":"sta_uop_sources_1_uSeqIndex","width":5},{"name":"sta_uop_sources_1_utag","width":5},{"name":"sta_uop_sources_1_utagValid","width":1},{"name":"sta_uop_sources_1_valid","width":1},{"name":"sta_uop_sources_2_atag","width":6},{"name":"sta_uop_sources_2_kind","width":3},{"name":"sta_uop_sources_2_pGeneration","width":16},{"name":"sta_uop_sources_2_ptag","width":7},{"name":"sta_uop_sources_2_ptagValid","width":1},{"name":"sta_uop_sources_2_ready","width":1},{"name":"sta_uop_sources_2_tGeneration","width":16},{"name":"sta_uop_sources_2_tSeqGeneration","width":16},{"name":"sta_uop_sources_2_tSeqIndex","width":5},{"name":"sta_uop_sources_2_ttag","width":5},{"name":"sta_uop_sources_2_ttagValid","width":1},{"name":"sta_uop_sources_2_uGeneration","width":16},{"name":"sta_uop_sources_2_uSeqGeneration","width":16},{"name":"sta_uop_sources_2_uSeqIndex","width":5},{"name":"sta_uop_sources_2_utag","width":5},{"name":"sta_uop_sources_2_utagValid","width":1},{"name":"sta_uop_sources_2_valid","width":1},{"name":"sta_uop_sources_3_atag","width":6},{"name":"sta_uop_sources_3_kind","width":3},{"name":"sta_uop_sources_3_pGeneration","width":16},{"name":"sta_uop_sources_3_ptag","width":7},{"name":"sta_uop_sources_3_ptagValid","width":1},{"name":"sta_uop_sources_3_ready","width":1},{"name":"sta_uop_sources_3_tGeneration","width":16},{"name":"sta_uop_sources_3_tSeqGeneration","width":16},{"name":"sta_uop_sources_3_tSeqIndex","width":5},{"name":"sta_uop_sources_3_ttag","width":5},{"name":"sta_uop_sources_3_ttagValid","width":1},{"name":"sta_uop_sources_3_uGeneration","width":16},{"name":"sta_uop_sources_3_uSeqGeneration","width":16},{"name":"sta_uop_sources_3_uSeqIndex","width":5},{"name":"sta_uop_sources_3_utag","width":5},{"name":"sta_uop_sources_3_utagValid","width":1},{"name":"sta_uop_sources_3_valid","width":1},{"name":"std_memoryOrder_firstLid","width":32},{"name":"std_memoryOrder_firstLsid","width":32},{"name":"std_memoryOrder_firstSid","width":32},{"name":"std_memoryOrder_requestCount","width":2},{"name":"std_memoryOrder_yoldLid","width":32},{"name":"std_memoryOrder_yoldLsid","width":32},{"name":"std_memoryOrder_yoldValid","width":1},{"name":"std_memoryOrder_yostLsid","width":32},{"name":"std_memoryOrder_yostSid","width":32},{"name":"std_memoryOrder_yostValid","width":1},{"name":"std_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"std_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"std_pcBufferIndexOffset_pcOffset","width":7},{"name":"std_pcBufferIndexOffset_valid","width":1},{"name":"std_transactionId","width":64},{"name":"std_trap_cause","width":32},{"name":"std_trap_valid","width":1},{"name":"std_uop_decoded_blockBoundary","width":1},{"name":"std_uop_decoded_blockStart","width":1},{"name":"std_uop_decoded_blockStop","width":1},{"name":"std_uop_decoded_classification_complexBreak","width":1},{"name":"std_uop_decoded_classification_dispatchClass","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_0","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_1","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_2","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_3","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_4","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_5","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_6","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_7","width":3},{"name":"std_uop_decoded_classification_dispatchWrites","width":3},{"name":"std_uop_decoded_classification_disposition","width":2},{"name":"std_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"std_uop_decoded_classification_fastResolveClass","width":3},{"name":"std_uop_decoded_classification_fusionHeadClass","width":2},{"name":"std_uop_decoded_classification_fusionTailClass","width":2},{"name":"std_uop_decoded_classification_implicitDestination","width":2},{"name":"std_uop_decoded_classification_implicitSourceMask","width":4},{"name":"std_uop_decoded_classification_kind","width":4},{"name":"std_uop_decoded_classification_mayRedirect","width":1},{"name":"std_uop_decoded_classification_mayTrap","width":1},{"name":"std_uop_decoded_classification_mayTrapLate","width":1},{"name":"std_uop_decoded_classification_memoryRequestCount","width":2},{"name":"std_uop_decoded_classification_nonspeculative","width":1},{"name":"std_uop_decoded_classification_pDestinationCount","width":2},{"name":"std_uop_decoded_classification_pSourceCount","width":3},{"name":"std_uop_decoded_classification_pcReadClass","width":4},{"name":"std_uop_decoded_classification_pcReadRequired","width":1},{"name":"std_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"std_uop_decoded_classification_sideEffectOwner","width":3},{"name":"std_uop_decoded_classification_splitKind","width":2},{"name":"std_uop_decoded_classification_tAllocationCount","width":2},{"name":"std_uop_decoded_classification_uAllocationCount","width":2},{"name":"std_uop_decoded_classification_uopCountMax","width":6},{"name":"std_uop_decoded_classification_uopCountMin","width":6},{"name":"std_uop_decoded_classification_valid","width":1},{"name":"std_uop_decoded_destinations_0_atag","width":6},{"name":"std_uop_decoded_destinations_0_kind","width":3},{"name":"std_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_0_valid","width":1},{"name":"std_uop_decoded_destinations_1_atag","width":6},{"name":"std_uop_decoded_destinations_1_kind","width":3},{"name":"std_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_1_valid","width":1},{"name":"std_uop_decoded_earlyComplete","width":1},{"name":"std_uop_decoded_immediate","width":64},{"name":"std_uop_decoded_immediateValid","width":1},{"name":"std_uop_decoded_instruction_kind","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"std_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"std_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"std_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"std_uop_decoded_instruction_parent_instruction","width":64},{"name":"std_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"std_uop_decoded_instruction_parent_pc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"std_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"std_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"std_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"std_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"std_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"std_uop_decoded_instruction_templateCount","width":8},{"name":"std_uop_decoded_instruction_templateImmediate","width":64},{"name":"std_uop_decoded_instruction_templateOpcode","width":12},{"name":"std_uop_decoded_instruction_templateOrdinal","width":8},{"name":"std_uop_decoded_memory_accessBytes","width":4},{"name":"std_uop_decoded_memory_addressMode","width":2},{"name":"std_uop_decoded_memory_addressSourceMask","width":4},{"name":"std_uop_decoded_memory_dataSourceMask","width":4},{"name":"std_uop_decoded_memory_indexMode","width":2},{"name":"std_uop_decoded_memory_indexShift","width":5},{"name":"std_uop_decoded_memory_isLoad","width":1},{"name":"std_uop_decoded_memory_isStore","width":1},{"name":"std_uop_decoded_memory_offset","width":64},{"name":"std_uop_decoded_memory_requestCount","width":2},{"name":"std_uop_decoded_memory_signExtend","width":1},{"name":"std_uop_decoded_memory_valid","width":1},{"name":"std_uop_decoded_memory_writebackPreIndex","width":1},{"name":"std_uop_decoded_memory_writebackValid","width":1},{"name":"std_uop_decoded_opcode","width":12},{"name":"std_uop_decoded_rob_bid","width":8},{"name":"std_uop_decoded_rob_brobGeneration","width":16},{"name":"std_uop_decoded_rob_memberIndex","width":2},{"name":"std_uop_decoded_rob_peId","width":8},{"name":"std_uop_decoded_rob_residentGeneration","width":16},{"name":"std_uop_decoded_rob_ridGeneration","width":16},{"name":"std_uop_decoded_rob_ridSlot","width":6},{"name":"std_uop_decoded_rob_stid","width":1},{"name":"std_uop_decoded_sources_0_atag","width":6},{"name":"std_uop_decoded_sources_0_kind","width":3},{"name":"std_uop_decoded_sources_0_relativeIndex","width":6},{"name":"std_uop_decoded_sources_0_valid","width":1},{"name":"std_uop_decoded_sources_1_atag","width":6},{"name":"std_uop_decoded_sources_1_kind","width":3},{"name":"std_uop_decoded_sources_1_relativeIndex","width":6},{"name":"std_uop_decoded_sources_1_valid","width":1},{"name":"std_uop_decoded_sources_2_atag","width":6},{"name":"std_uop_decoded_sources_2_kind","width":3},{"name":"std_uop_decoded_sources_2_relativeIndex","width":6},{"name":"std_uop_decoded_sources_2_valid","width":1},{"name":"std_uop_decoded_sources_3_atag","width":6},{"name":"std_uop_decoded_sources_3_kind","width":3},{"name":"std_uop_decoded_sources_3_relativeIndex","width":6},{"name":"std_uop_decoded_sources_3_valid","width":1},{"name":"std_uop_decoded_uopClass","width":3},{"name":"std_uop_decoded_valid","width":1},{"name":"std_uop_destinations_0_atag","width":6},{"name":"std_uop_destinations_0_kind","width":3},{"name":"std_uop_destinations_0_pGeneration","width":16},{"name":"std_uop_destinations_0_previousPGeneration","width":16},{"name":"std_uop_destinations_0_previousPtag","width":7},{"name":"std_uop_destinations_0_previousPtagValid","width":1},{"name":"std_uop_destinations_0_previousTtag","width":5},{"name":"std_uop_destinations_0_previousTtagValid","width":1},{"name":"std_uop_destinations_0_previousUtag","width":5},{"name":"std_uop_destinations_0_previousUtagValid","width":1},{"name":"std_uop_destinations_0_ptag","width":7},{"name":"std_uop_destinations_0_ptagValid","width":1},{"name":"std_uop_destinations_0_tGeneration","width":16},{"name":"std_uop_destinations_0_tSeqGeneration","width":16},{"name":"std_uop_destinations_0_tSeqIndex","width":5},{"name":"std_uop_destinations_0_ttag","width":5},{"name":"std_uop_destinations_0_ttagValid","width":1},{"name":"std_uop_destinations_0_uGeneration","width":16},{"name":"std_uop_destinations_0_uSeqGeneration","width":16},{"name":"std_uop_destinations_0_uSeqIndex","width":5},{"name":"std_uop_destinations_0_utag","width":5},{"name":"std_uop_destinations_0_utagValid","width":1},{"name":"std_uop_destinations_0_valid","width":1},{"name":"std_uop_destinations_1_atag","width":6},{"name":"std_uop_destinations_1_kind","width":3},{"name":"std_uop_destinations_1_pGeneration","width":16},{"name":"std_uop_destinations_1_previousPGeneration","width":16},{"name":"std_uop_destinations_1_previousPtag","width":7},{"name":"std_uop_destinations_1_previousPtagValid","width":1},{"name":"std_uop_destinations_1_previousTtag","width":5},{"name":"std_uop_destinations_1_previousTtagValid","width":1},{"name":"std_uop_destinations_1_previousUtag","width":5},{"name":"std_uop_destinations_1_previousUtagValid","width":1},{"name":"std_uop_destinations_1_ptag","width":7},{"name":"std_uop_destinations_1_ptagValid","width":1},{"name":"std_uop_destinations_1_tGeneration","width":16},{"name":"std_uop_destinations_1_tSeqGeneration","width":16},{"name":"std_uop_destinations_1_tSeqIndex","width":5},{"name":"std_uop_destinations_1_ttag","width":5},{"name":"std_uop_destinations_1_ttagValid","width":1},{"name":"std_uop_destinations_1_uGeneration","width":16},{"name":"std_uop_destinations_1_uSeqGeneration","width":16},{"name":"std_uop_destinations_1_uSeqIndex","width":5},{"name":"std_uop_destinations_1_utag","width":5},{"name":"std_uop_destinations_1_utagValid","width":1},{"name":"std_uop_destinations_1_valid","width":1},{"name":"std_uop_sources_0_atag","width":6},{"name":"std_uop_sources_0_kind","width":3},{"name":"std_uop_sources_0_pGeneration","width":16},{"name":"std_uop_sources_0_ptag","width":7},{"name":"std_uop_sources_0_ptagValid","width":1},{"name":"std_uop_sources_0_ready","width":1},{"name":"std_uop_sources_0_tGeneration","width":16},{"name":"std_uop_sources_0_tSeqGeneration","width":16},{"name":"std_uop_sources_0_tSeqIndex","width":5},{"name":"std_uop_sources_0_ttag","width":5},{"name":"std_uop_sources_0_ttagValid","width":1},{"name":"std_uop_sources_0_uGeneration","width":16},{"name":"std_uop_sources_0_uSeqGeneration","width":16},{"name":"std_uop_sources_0_uSeqIndex","width":5},{"name":"std_uop_sources_0_utag","width":5},{"name":"std_uop_sources_0_utagValid","width":1},{"name":"std_uop_sources_0_valid","width":1},{"name":"std_uop_sources_1_atag","width":6},{"name":"std_uop_sources_1_kind","width":3},{"name":"std_uop_sources_1_pGeneration","width":16},{"name":"std_uop_sources_1_ptag","width":7},{"name":"std_uop_sources_1_ptagValid","width":1},{"name":"std_uop_sources_1_ready","width":1},{"name":"std_uop_sources_1_tGeneration","width":16},{"name":"std_uop_sources_1_tSeqGeneration","width":16},{"name":"std_uop_sources_1_tSeqIndex","width":5},{"name":"std_uop_sources_1_ttag","width":5},{"name":"std_uop_sources_1_ttagValid","width":1},{"name":"std_uop_sources_1_uGeneration","width":16},{"name":"std_uop_sources_1_uSeqGeneration","width":16},{"name":"std_uop_sources_1_uSeqIndex","width":5},{"name":"std_uop_sources_1_utag","width":5},{"name":"std_uop_sources_1_utagValid","width":1},{"name":"std_uop_sources_1_valid","width":1},{"name":"std_uop_sources_2_atag","width":6},{"name":"std_uop_sources_2_kind","width":3},{"name":"std_uop_sources_2_pGeneration","width":16},{"name":"std_uop_sources_2_ptag","width":7},{"name":"std_uop_sources_2_ptagValid","width":1},{"name":"std_uop_sources_2_ready","width":1},{"name":"std_uop_sources_2_tGeneration","width":16},{"name":"std_uop_sources_2_tSeqGeneration","width":16},{"name":"std_uop_sources_2_tSeqIndex","width":5},{"name":"std_uop_sources_2_ttag","width":5},{"name":"std_uop_sources_2_ttagValid","width":1},{"name":"std_uop_sources_2_uGeneration","width":16},{"name":"std_uop_sources_2_uSeqGeneration","width":16},{"name":"std_uop_sources_2_uSeqIndex","width":5},{"name":"std_uop_sources_2_utag","width":5},{"name":"std_uop_sources_2_utagValid","width":1},{"name":"std_uop_sources_2_valid","width":1},{"name":"std_uop_sources_3_atag","width":6},{"name":"std_uop_sources_3_kind","width":3},{"name":"std_uop_sources_3_pGeneration","width":16},{"name":"std_uop_sources_3_ptag","width":7},{"name":"std_uop_sources_3_ptagValid","width":1},{"name":"std_uop_sources_3_ready","width":1},{"name":"std_uop_sources_3_tGeneration","width":16},{"name":"std_uop_sources_3_tSeqGeneration","width":16},{"name":"std_uop_sources_3_tSeqIndex","width":5},{"name":"std_uop_sources_3_ttag","width":5},{"name":"std_uop_sources_3_ttagValid","width":1},{"name":"std_uop_sources_3_uGeneration","width":16},{"name":"std_uop_sources_3_uSeqGeneration","width":16},{"name":"std_uop_sources_3_uSeqIndex","width":5},{"name":"std_uop_sources_3_utag","width":5},{"name":"std_uop_sources_3_utagValid","width":1},{"name":"std_uop_sources_3_valid","width":1},{"name":"stdPipe","width":1}]},{"name":"ooo_to_iex_system","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_cmd","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_rob_noflush","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"RobNoflushTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_noflush_ready","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"RobNoflushReadyTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_resolve","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":4,"payload":"RobResolveTxn","ports":[{"name":"destinationIndex","width":1},{"name":"destinationValid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"value","width":64}]},{"name":"iex_to_ooo_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_top_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"TOP","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_pc_buffer_read_address","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":6,"payload":"PcBufferReadAddress","ports":[{"name":"allocationEpoch","width":16},{"name":"pcBufferIndex","width":6},{"name":"stid","width":1},{"name":"valid","width":1}]},{"name":"ooo_to_iex_pc_buffer_read_pc_base","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":6,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"iex_to_lsu_load_issue","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"LoadIssueTxn","ports":[{"name":"address","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"pc","width":64},{"name":"signed","width":1},{"name":"sizeBytes","width":4},{"name":"youngestStoreId","width":32},{"name":"youngestStoreLsid","width":32},{"name":"youngestStoreValid","width":1}]},{"name":"lsu_to_iex_load_allocation_preview","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadAllocationPreview","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_launch","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadLaunchTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"iex_to_lsu_store_reservation","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreReservationTxn","ports":[{"name":"aguPipe","width":1},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sizeBytes","width":4},{"name":"stdPipe","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64},{"name":"transactionId","width":64}]},{"name":"iex_to_lsu_store_address","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreAddressTxn","ports":[{"name":"address","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"iex_to_lsu_store_data","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreDataTxn","ports":[{"name":"byteMask_0","width":8},{"name":"byteMask_1","width":8},{"name":"data_0","width":64},{"name":"data_1","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"lsu_to_iex_load_result","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadResultTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"data","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1}]},{"name":"lsu_to_iex_load_reissue","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadReissueTxn","ports":[{"name":"address","width":64},{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_repick","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadRepickTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_cancel","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadCancelTxn","ports":[{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64}]},{"name":"ooo_to_lsu_store_commit","contract_id":"IFC-IEX-LSU-001","producer":"OOO","consumer":"LSU","lanes":1,"payload":"StoreCommitAuthorizationTxn","ports":[{"name":"beat","width":1},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"lsu_internal_store_classify","contract_id":"IFC-IEX-LSU-001","producer":"LSU Translation","consumer":"LSU Commit Backend","lanes":1,"payload":"StoreMemoryClassifyTxn","ports":[{"name":"beat","width":1},{"name":"faultCause","width":32},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"memoryClass","width":2},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"external_cmd_issue","contract_id":"IFC-TOP-EXT-001","producer":"IEX","consumer":"External CMD","lanes":1,"payload":"CmdIssueTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sourceValid","width":4},{"name":"sourceValues_0","width":64},{"name":"sourceValues_1","width":64},{"name":"sourceValues_2","width":64},{"name":"sourceValues_3","width":64},{"name":"transactionId","width":64}]},{"name":"owner_to_ooo_recovery_event","contract_id":"IFC-RECOVERY-001","producer":"IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryEvent","ports":[{"name":"cause","width":3},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"redirectPc","width":64},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_prepare","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"target_to_ooo_recovery_prepared","contract_id":"IFC-RECOVERY-001","producer":"IFU/CTU/IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_apply","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_abort","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_commit","contract_id":"IFC-COMMIT-001","producer":"OOO","consumer":"TOP/DTU","lanes":4,"payload":"CommitTxn","ports":[{"name":"count","width":3},{"name":"entries_0_destination_atag","width":6},{"name":"entries_0_destination_kind","width":3},{"name":"entries_0_destination_pGeneration","width":16},{"name":"entries_0_destination_previousPGeneration","width":16},{"name":"entries_0_destination_previousPtag","width":7},{"name":"entries_0_destination_previousPtagValid","width":1},{"name":"entries_0_destination_previousTtag","width":5},{"name":"entries_0_destination_previousTtagValid","width":1},{"name":"entries_0_destination_previousUtag","width":5},{"name":"entries_0_destination_previousUtagValid","width":1},{"name":"entries_0_destination_ptag","width":7},{"name":"entries_0_destination_ptagValid","width":1},{"name":"entries_0_destination_tGeneration","width":16},{"name":"entries_0_destination_tSeqGeneration","width":16},{"name":"entries_0_destination_tSeqIndex","width":5},{"name":"entries_0_destination_ttag","width":5},{"name":"entries_0_destination_ttagValid","width":1},{"name":"entries_0_destination_uGeneration","width":16},{"name":"entries_0_destination_uSeqGeneration","width":16},{"name":"entries_0_destination_uSeqIndex","width":5},{"name":"entries_0_destination_utag","width":5},{"name":"entries_0_destination_utagValid","width":1},{"name":"entries_0_destination_valid","width":1},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionBits","width":64},{"name":"entries_0_instructionLengthBytes","width":4},{"name":"entries_0_memory_attemptGeneration","width":16},{"name":"entries_0_memory_lsid","width":32},{"name":"entries_0_memory_pipeId","width":1},{"name":"entries_0_memory_rob_bid","width":8},{"name":"entries_0_memory_rob_brobGeneration","width":16},{"name":"entries_0_memory_rob_memberIndex","width":2},{"name":"entries_0_memory_rob_peId","width":8},{"name":"entries_0_memory_rob_residentGeneration","width":16},{"name":"entries_0_memory_rob_ridGeneration","width":16},{"name":"entries_0_memory_rob_ridSlot","width":6},{"name":"entries_0_memory_rob_stid","width":1},{"name":"entries_0_memory_transaction_generation","width":16},{"name":"entries_0_memory_transaction_value","width":64},{"name":"entries_0_memoryOrder_firstLid","width":32},{"name":"entries_0_memoryOrder_firstLsid","width":32},{"name":"entries_0_memoryOrder_firstSid","width":32},{"name":"entries_0_memoryOrder_requestCount","width":2},{"name":"entries_0_memoryOrder_yoldLid","width":32},{"name":"entries_0_memoryOrder_yoldLsid","width":32},{"name":"entries_0_memoryOrder_yoldValid","width":1},{"name":"entries_0_memoryOrder_yostLsid","width":32},{"name":"entries_0_memoryOrder_yostSid","width":32},{"name":"entries_0_memoryOrder_yostValid","width":1},{"name":"entries_0_memoryStore","width":1},{"name":"entries_0_memoryValid","width":1},{"name":"entries_0_opcode","width":12},{"name":"entries_0_pc","width":64},{"name":"entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_0_pcBufferIndexOffset_valid","width":1},{"name":"entries_0_result","width":64},{"name":"entries_0_resultValid","width":1},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robGroupLast","width":1},{"name":"entries_0_storeData","width":64},{"name":"entries_0_storeMask","width":8},{"name":"entries_0_trap_cause","width":32},{"name":"entries_0_trap_instruction_epoch","width":16},{"name":"entries_0_trap_instruction_instructionId","width":64},{"name":"entries_0_trap_instruction_peId","width":8},{"name":"entries_0_trap_instruction_stid","width":1},{"name":"entries_0_trap_kind","width":2},{"name":"entries_0_trap_rob_bid","width":8},{"name":"entries_0_trap_rob_brobGeneration","width":16},{"name":"entries_0_trap_rob_memberIndex","width":2},{"name":"entries_0_trap_rob_peId","width":8},{"name":"entries_0_trap_rob_residentGeneration","width":16},{"name":"entries_0_trap_rob_ridGeneration","width":16},{"name":"entries_0_trap_rob_ridSlot","width":6},{"name":"entries_0_trap_rob_stid","width":1},{"name":"entries_0_trap_targetPc","width":64},{"name":"entries_0_trap_tval","width":64},{"name":"entries_0_trap_valid","width":1},{"name":"entries_1_destination_atag","width":6},{"name":"entries_1_destination_kind","width":3},{"name":"entries_1_destination_pGeneration","width":16},{"name":"entries_1_destination_previousPGeneration","width":16},{"name":"entries_1_destination_previousPtag","width":7},{"name":"entries_1_destination_previousPtagValid","width":1},{"name":"entries_1_destination_previousTtag","width":5},{"name":"entries_1_destination_previousTtagValid","width":1},{"name":"entries_1_destination_previousUtag","width":5},{"name":"entries_1_destination_previousUtagValid","width":1},{"name":"entries_1_destination_ptag","width":7},{"name":"entries_1_destination_ptagValid","width":1},{"name":"entries_1_destination_tGeneration","width":16},{"name":"entries_1_destination_tSeqGeneration","width":16},{"name":"entries_1_destination_tSeqIndex","width":5},{"name":"entries_1_destination_ttag","width":5},{"name":"entries_1_destination_ttagValid","width":1},{"name":"entries_1_destination_uGeneration","width":16},{"name":"entries_1_destination_uSeqGeneration","width":16},{"name":"entries_1_destination_uSeqIndex","width":5},{"name":"entries_1_destination_utag","width":5},{"name":"entries_1_destination_utagValid","width":1},{"name":"entries_1_destination_valid","width":1},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionBits","width":64},{"name":"entries_1_instructionLengthBytes","width":4},{"name":"entries_1_memory_attemptGeneration","width":16},{"name":"entries_1_memory_lsid","width":32},{"name":"entries_1_memory_pipeId","width":1},{"name":"entries_1_memory_rob_bid","width":8},{"name":"entries_1_memory_rob_brobGeneration","width":16},{"name":"entries_1_memory_rob_memberIndex","width":2},{"name":"entries_1_memory_rob_peId","width":8},{"name":"entries_1_memory_rob_residentGeneration","width":16},{"name":"entries_1_memory_rob_ridGeneration","width":16},{"name":"entries_1_memory_rob_ridSlot","width":6},{"name":"entries_1_memory_rob_stid","width":1},{"name":"entries_1_memory_transaction_generation","width":16},{"name":"entries_1_memory_transaction_value","width":64},{"name":"entries_1_memoryOrder_firstLid","width":32},{"name":"entries_1_memoryOrder_firstLsid","width":32},{"name":"entries_1_memoryOrder_firstSid","width":32},{"name":"entries_1_memoryOrder_requestCount","width":2},{"name":"entries_1_memoryOrder_yoldLid","width":32},{"name":"entries_1_memoryOrder_yoldLsid","width":32},{"name":"entries_1_memoryOrder_yoldValid","width":1},{"name":"entries_1_memoryOrder_yostLsid","width":32},{"name":"entries_1_memoryOrder_yostSid","width":32},{"name":"entries_1_memoryOrder_yostValid","width":1},{"name":"entries_1_memoryStore","width":1},{"name":"entries_1_memoryValid","width":1},{"name":"entries_1_opcode","width":12},{"name":"entries_1_pc","width":64},{"name":"entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_1_pcBufferIndexOffset_valid","width":1},{"name":"entries_1_result","width":64},{"name":"entries_1_resultValid","width":1},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robGroupLast","width":1},{"name":"entries_1_storeData","width":64},{"name":"entries_1_storeMask","width":8},{"name":"entries_1_trap_cause","width":32},{"name":"entries_1_trap_instruction_epoch","width":16},{"name":"entries_1_trap_instruction_instructionId","width":64},{"name":"entries_1_trap_instruction_peId","width":8},{"name":"entries_1_trap_instruction_stid","width":1},{"name":"entries_1_trap_kind","width":2},{"name":"entries_1_trap_rob_bid","width":8},{"name":"entries_1_trap_rob_brobGeneration","width":16},{"name":"entries_1_trap_rob_memberIndex","width":2},{"name":"entries_1_trap_rob_peId","width":8},{"name":"entries_1_trap_rob_residentGeneration","width":16},{"name":"entries_1_trap_rob_ridGeneration","width":16},{"name":"entries_1_trap_rob_ridSlot","width":6},{"name":"entries_1_trap_rob_stid","width":1},{"name":"entries_1_trap_targetPc","width":64},{"name":"entries_1_trap_tval","width":64},{"name":"entries_1_trap_valid","width":1},{"name":"entries_2_destination_atag","width":6},{"name":"entries_2_destination_kind","width":3},{"name":"entries_2_destination_pGeneration","width":16},{"name":"entries_2_destination_previousPGeneration","width":16},{"name":"entries_2_destination_previousPtag","width":7},{"name":"entries_2_destination_previousPtagValid","width":1},{"name":"entries_2_destination_previousTtag","width":5},{"name":"entries_2_destination_previousTtagValid","width":1},{"name":"entries_2_destination_previousUtag","width":5},{"name":"entries_2_destination_previousUtagValid","width":1},{"name":"entries_2_destination_ptag","width":7},{"name":"entries_2_destination_ptagValid","width":1},{"name":"entries_2_destination_tGeneration","width":16},{"name":"entries_2_destination_tSeqGeneration","width":16},{"name":"entries_2_destination_tSeqIndex","width":5},{"name":"entries_2_destination_ttag","width":5},{"name":"entries_2_destination_ttagValid","width":1},{"name":"entries_2_destination_uGeneration","width":16},{"name":"entries_2_destination_uSeqGeneration","width":16},{"name":"entries_2_destination_uSeqIndex","width":5},{"name":"entries_2_destination_utag","width":5},{"name":"entries_2_destination_utagValid","width":1},{"name":"entries_2_destination_valid","width":1},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionBits","width":64},{"name":"entries_2_instructionLengthBytes","width":4},{"name":"entries_2_memory_attemptGeneration","width":16},{"name":"entries_2_memory_lsid","width":32},{"name":"entries_2_memory_pipeId","width":1},{"name":"entries_2_memory_rob_bid","width":8},{"name":"entries_2_memory_rob_brobGeneration","width":16},{"name":"entries_2_memory_rob_memberIndex","width":2},{"name":"entries_2_memory_rob_peId","width":8},{"name":"entries_2_memory_rob_residentGeneration","width":16},{"name":"entries_2_memory_rob_ridGeneration","width":16},{"name":"entries_2_memory_rob_ridSlot","width":6},{"name":"entries_2_memory_rob_stid","width":1},{"name":"entries_2_memory_transaction_generation","width":16},{"name":"entries_2_memory_transaction_value","width":64},{"name":"entries_2_memoryOrder_firstLid","width":32},{"name":"entries_2_memoryOrder_firstLsid","width":32},{"name":"entries_2_memoryOrder_firstSid","width":32},{"name":"entries_2_memoryOrder_requestCount","width":2},{"name":"entries_2_memoryOrder_yoldLid","width":32},{"name":"entries_2_memoryOrder_yoldLsid","width":32},{"name":"entries_2_memoryOrder_yoldValid","width":1},{"name":"entries_2_memoryOrder_yostLsid","width":32},{"name":"entries_2_memoryOrder_yostSid","width":32},{"name":"entries_2_memoryOrder_yostValid","width":1},{"name":"entries_2_memoryStore","width":1},{"name":"entries_2_memoryValid","width":1},{"name":"entries_2_opcode","width":12},{"name":"entries_2_pc","width":64},{"name":"entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_2_pcBufferIndexOffset_valid","width":1},{"name":"entries_2_result","width":64},{"name":"entries_2_resultValid","width":1},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robGroupLast","width":1},{"name":"entries_2_storeData","width":64},{"name":"entries_2_storeMask","width":8},{"name":"entries_2_trap_cause","width":32},{"name":"entries_2_trap_instruction_epoch","width":16},{"name":"entries_2_trap_instruction_instructionId","width":64},{"name":"entries_2_trap_instruction_peId","width":8},{"name":"entries_2_trap_instruction_stid","width":1},{"name":"entries_2_trap_kind","width":2},{"name":"entries_2_trap_rob_bid","width":8},{"name":"entries_2_trap_rob_brobGeneration","width":16},{"name":"entries_2_trap_rob_memberIndex","width":2},{"name":"entries_2_trap_rob_peId","width":8},{"name":"entries_2_trap_rob_residentGeneration","width":16},{"name":"entries_2_trap_rob_ridGeneration","width":16},{"name":"entries_2_trap_rob_ridSlot","width":6},{"name":"entries_2_trap_rob_stid","width":1},{"name":"entries_2_trap_targetPc","width":64},{"name":"entries_2_trap_tval","width":64},{"name":"entries_2_trap_valid","width":1},{"name":"entries_3_destination_atag","width":6},{"name":"entries_3_destination_kind","width":3},{"name":"entries_3_destination_pGeneration","width":16},{"name":"entries_3_destination_previousPGeneration","width":16},{"name":"entries_3_destination_previousPtag","width":7},{"name":"entries_3_destination_previousPtagValid","width":1},{"name":"entries_3_destination_previousTtag","width":5},{"name":"entries_3_destination_previousTtagValid","width":1},{"name":"entries_3_destination_previousUtag","width":5},{"name":"entries_3_destination_previousUtagValid","width":1},{"name":"entries_3_destination_ptag","width":7},{"name":"entries_3_destination_ptagValid","width":1},{"name":"entries_3_destination_tGeneration","width":16},{"name":"entries_3_destination_tSeqGeneration","width":16},{"name":"entries_3_destination_tSeqIndex","width":5},{"name":"entries_3_destination_ttag","width":5},{"name":"entries_3_destination_ttagValid","width":1},{"name":"entries_3_destination_uGeneration","width":16},{"name":"entries_3_destination_uSeqGeneration","width":16},{"name":"entries_3_destination_uSeqIndex","width":5},{"name":"entries_3_destination_utag","width":5},{"name":"entries_3_destination_utagValid","width":1},{"name":"entries_3_destination_valid","width":1},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionBits","width":64},{"name":"entries_3_instructionLengthBytes","width":4},{"name":"entries_3_memory_attemptGeneration","width":16},{"name":"entries_3_memory_lsid","width":32},{"name":"entries_3_memory_pipeId","width":1},{"name":"entries_3_memory_rob_bid","width":8},{"name":"entries_3_memory_rob_brobGeneration","width":16},{"name":"entries_3_memory_rob_memberIndex","width":2},{"name":"entries_3_memory_rob_peId","width":8},{"name":"entries_3_memory_rob_residentGeneration","width":16},{"name":"entries_3_memory_rob_ridGeneration","width":16},{"name":"entries_3_memory_rob_ridSlot","width":6},{"name":"entries_3_memory_rob_stid","width":1},{"name":"entries_3_memory_transaction_generation","width":16},{"name":"entries_3_memory_transaction_value","width":64},{"name":"entries_3_memoryOrder_firstLid","width":32},{"name":"entries_3_memoryOrder_firstLsid","width":32},{"name":"entries_3_memoryOrder_firstSid","width":32},{"name":"entries_3_memoryOrder_requestCount","width":2},{"name":"entries_3_memoryOrder_yoldLid","width":32},{"name":"entries_3_memoryOrder_yoldLsid","width":32},{"name":"entries_3_memoryOrder_yoldValid","width":1},{"name":"entries_3_memoryOrder_yostLsid","width":32},{"name":"entries_3_memoryOrder_yostSid","width":32},{"name":"entries_3_memoryOrder_yostValid","width":1},{"name":"entries_3_memoryStore","width":1},{"name":"entries_3_memoryValid","width":1},{"name":"entries_3_opcode","width":12},{"name":"entries_3_pc","width":64},{"name":"entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_3_pcBufferIndexOffset_valid","width":1},{"name":"entries_3_result","width":64},{"name":"entries_3_resultValid","width":1},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robGroupLast","width":1},{"name":"entries_3_storeData","width":64},{"name":"entries_3_storeMask","width":8},{"name":"entries_3_trap_cause","width":32},{"name":"entries_3_trap_instruction_epoch","width":16},{"name":"entries_3_trap_instruction_instructionId","width":64},{"name":"entries_3_trap_instruction_peId","width":8},{"name":"entries_3_trap_instruction_stid","width":1},{"name":"entries_3_trap_kind","width":2},{"name":"entries_3_trap_rob_bid","width":8},{"name":"entries_3_trap_rob_brobGeneration","width":16},{"name":"entries_3_trap_rob_memberIndex","width":2},{"name":"entries_3_trap_rob_peId","width":8},{"name":"entries_3_trap_rob_residentGeneration","width":16},{"name":"entries_3_trap_rob_ridGeneration","width":16},{"name":"entries_3_trap_rob_ridSlot","width":6},{"name":"entries_3_trap_rob_stid","width":1},{"name":"entries_3_trap_targetPc","width":64},{"name":"entries_3_trap_tval","width":64},{"name":"entries_3_trap_valid","width":1}]},{"name":"box_to_dtu_trace","contract_id":"IFC-DTU-001","producer":"TOP/IFU/CTU/OOO/IEX/LSU","consumer":"DTU","lanes":4,"payload":"TracePacket","ports":[{"name":"count","width":3},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3}]},{"name":"external_to_dtu_debug_request","contract_id":"IFC-DTU-001","producer":"External Debug","consumer":"DTU","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_ooo_debug_request","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"OOO","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_dtu_debug_response","contract_id":"IFC-DTU-001","producer":"OOO","consumer":"DTU","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_external_debug_response","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Debug","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_trace_export","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Trace","lanes":4,"payload":"TracePacket","ports":[{"name":"count","width":3},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3}]},{"name":"dtu_performance_counter","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Counter","lanes":32,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"instruction_memory_request","contract_id":"IFC-MEMORY-001","producer":"IFU","consumer":"Memory","lanes":1,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"instruction_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"IFU","lanes":1,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]},{"name":"data_memory_request","contract_id":"IFC-MEMORY-001","producer":"LSU","consumer":"Memory","lanes":4,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"data_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"LSU","lanes":4,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]}]},{"name":"W6","width":6,"endpoints":[{"name":"top_io","contract_id":"IFC-TOP-EXT-002","producer":"Platform","consumer":"TOP","lanes":1,"payload":"TOPIO","ports":[{"name":"bootstrapComplete","width":1},{"name":"bootstrapReady","width":1},{"name":"cmdIssue_bits_instruction_epoch","width":16},{"name":"cmdIssue_bits_instruction_instructionId","width":64},{"name":"cmdIssue_bits_instruction_peId","width":8},{"name":"cmdIssue_bits_instruction_stid","width":1},{"name":"cmdIssue_bits_opcode","width":12},{"name":"cmdIssue_bits_rob_bid","width":8},{"name":"cmdIssue_bits_rob_brobGeneration","width":16},{"name":"cmdIssue_bits_rob_memberIndex","width":2},{"name":"cmdIssue_bits_rob_peId","width":8},{"name":"cmdIssue_bits_rob_residentGeneration","width":16},{"name":"cmdIssue_bits_rob_ridGeneration","width":16},{"name":"cmdIssue_bits_rob_ridSlot","width":6},{"name":"cmdIssue_bits_rob_stid","width":1},{"name":"cmdIssue_bits_sourceValid","width":4},{"name":"cmdIssue_bits_sourceValues_0","width":64},{"name":"cmdIssue_bits_sourceValues_1","width":64},{"name":"cmdIssue_bits_sourceValues_2","width":64},{"name":"cmdIssue_bits_sourceValues_3","width":64},{"name":"cmdIssue_bits_transactionId","width":64},{"name":"cmdIssue_ready","width":1},{"name":"cmdIssue_valid","width":1},{"name":"commit_bits_count","width":3},{"name":"commit_bits_entries_0_destination_atag","width":6},{"name":"commit_bits_entries_0_destination_kind","width":3},{"name":"commit_bits_entries_0_destination_pGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPtag","width":7},{"name":"commit_bits_entries_0_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousTtag","width":5},{"name":"commit_bits_entries_0_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousUtag","width":5},{"name":"commit_bits_entries_0_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_0_destination_ptag","width":7},{"name":"commit_bits_entries_0_destination_ptagValid","width":1},{"name":"commit_bits_entries_0_destination_tGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_ttag","width":5},{"name":"commit_bits_entries_0_destination_ttagValid","width":1},{"name":"commit_bits_entries_0_destination_uGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_utag","width":5},{"name":"commit_bits_entries_0_destination_utagValid","width":1},{"name":"commit_bits_entries_0_destination_valid","width":1},{"name":"commit_bits_entries_0_instruction_epoch","width":16},{"name":"commit_bits_entries_0_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_instruction_peId","width":8},{"name":"commit_bits_entries_0_instruction_stid","width":1},{"name":"commit_bits_entries_0_instructionBits","width":64},{"name":"commit_bits_entries_0_instructionLengthBytes","width":4},{"name":"commit_bits_entries_0_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_0_memory_lsid","width":32},{"name":"commit_bits_entries_0_memory_pipeId","width":1},{"name":"commit_bits_entries_0_memory_rob_bid","width":8},{"name":"commit_bits_entries_0_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_memory_rob_peId","width":8},{"name":"commit_bits_entries_0_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_memory_rob_stid","width":1},{"name":"commit_bits_entries_0_memory_transaction_generation","width":16},{"name":"commit_bits_entries_0_memory_transaction_value","width":64},{"name":"commit_bits_entries_0_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_0_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_0_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_0_memoryStore","width":1},{"name":"commit_bits_entries_0_memoryValid","width":1},{"name":"commit_bits_entries_0_opcode","width":12},{"name":"commit_bits_entries_0_pc","width":64},{"name":"commit_bits_entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_0_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_0_result","width":64},{"name":"commit_bits_entries_0_resultValid","width":1},{"name":"commit_bits_entries_0_rob_bid","width":8},{"name":"commit_bits_entries_0_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_rob_peId","width":8},{"name":"commit_bits_entries_0_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_rob_stid","width":1},{"name":"commit_bits_entries_0_robGroupLast","width":1},{"name":"commit_bits_entries_0_storeData","width":64},{"name":"commit_bits_entries_0_storeMask","width":8},{"name":"commit_bits_entries_0_trap_cause","width":32},{"name":"commit_bits_entries_0_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_0_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_trap_instruction_peId","width":8},{"name":"commit_bits_entries_0_trap_instruction_stid","width":1},{"name":"commit_bits_entries_0_trap_kind","width":2},{"name":"commit_bits_entries_0_trap_rob_bid","width":8},{"name":"commit_bits_entries_0_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_trap_rob_peId","width":8},{"name":"commit_bits_entries_0_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_trap_rob_stid","width":1},{"name":"commit_bits_entries_0_trap_targetPc","width":64},{"name":"commit_bits_entries_0_trap_tval","width":64},{"name":"commit_bits_entries_0_trap_valid","width":1},{"name":"commit_bits_entries_1_destination_atag","width":6},{"name":"commit_bits_entries_1_destination_kind","width":3},{"name":"commit_bits_entries_1_destination_pGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPtag","width":7},{"name":"commit_bits_entries_1_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousTtag","width":5},{"name":"commit_bits_entries_1_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousUtag","width":5},{"name":"commit_bits_entries_1_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_1_destination_ptag","width":7},{"name":"commit_bits_entries_1_destination_ptagValid","width":1},{"name":"commit_bits_entries_1_destination_tGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_ttag","width":5},{"name":"commit_bits_entries_1_destination_ttagValid","width":1},{"name":"commit_bits_entries_1_destination_uGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_utag","width":5},{"name":"commit_bits_entries_1_destination_utagValid","width":1},{"name":"commit_bits_entries_1_destination_valid","width":1},{"name":"commit_bits_entries_1_instruction_epoch","width":16},{"name":"commit_bits_entries_1_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_instruction_peId","width":8},{"name":"commit_bits_entries_1_instruction_stid","width":1},{"name":"commit_bits_entries_1_instructionBits","width":64},{"name":"commit_bits_entries_1_instructionLengthBytes","width":4},{"name":"commit_bits_entries_1_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_1_memory_lsid","width":32},{"name":"commit_bits_entries_1_memory_pipeId","width":1},{"name":"commit_bits_entries_1_memory_rob_bid","width":8},{"name":"commit_bits_entries_1_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_memory_rob_peId","width":8},{"name":"commit_bits_entries_1_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_memory_rob_stid","width":1},{"name":"commit_bits_entries_1_memory_transaction_generation","width":16},{"name":"commit_bits_entries_1_memory_transaction_value","width":64},{"name":"commit_bits_entries_1_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_1_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_1_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_1_memoryStore","width":1},{"name":"commit_bits_entries_1_memoryValid","width":1},{"name":"commit_bits_entries_1_opcode","width":12},{"name":"commit_bits_entries_1_pc","width":64},{"name":"commit_bits_entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_1_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_1_result","width":64},{"name":"commit_bits_entries_1_resultValid","width":1},{"name":"commit_bits_entries_1_rob_bid","width":8},{"name":"commit_bits_entries_1_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_rob_peId","width":8},{"name":"commit_bits_entries_1_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_rob_stid","width":1},{"name":"commit_bits_entries_1_robGroupLast","width":1},{"name":"commit_bits_entries_1_storeData","width":64},{"name":"commit_bits_entries_1_storeMask","width":8},{"name":"commit_bits_entries_1_trap_cause","width":32},{"name":"commit_bits_entries_1_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_1_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_trap_instruction_peId","width":8},{"name":"commit_bits_entries_1_trap_instruction_stid","width":1},{"name":"commit_bits_entries_1_trap_kind","width":2},{"name":"commit_bits_entries_1_trap_rob_bid","width":8},{"name":"commit_bits_entries_1_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_trap_rob_peId","width":8},{"name":"commit_bits_entries_1_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_trap_rob_stid","width":1},{"name":"commit_bits_entries_1_trap_targetPc","width":64},{"name":"commit_bits_entries_1_trap_tval","width":64},{"name":"commit_bits_entries_1_trap_valid","width":1},{"name":"commit_bits_entries_2_destination_atag","width":6},{"name":"commit_bits_entries_2_destination_kind","width":3},{"name":"commit_bits_entries_2_destination_pGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPtag","width":7},{"name":"commit_bits_entries_2_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousTtag","width":5},{"name":"commit_bits_entries_2_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousUtag","width":5},{"name":"commit_bits_entries_2_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_2_destination_ptag","width":7},{"name":"commit_bits_entries_2_destination_ptagValid","width":1},{"name":"commit_bits_entries_2_destination_tGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_ttag","width":5},{"name":"commit_bits_entries_2_destination_ttagValid","width":1},{"name":"commit_bits_entries_2_destination_uGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_utag","width":5},{"name":"commit_bits_entries_2_destination_utagValid","width":1},{"name":"commit_bits_entries_2_destination_valid","width":1},{"name":"commit_bits_entries_2_instruction_epoch","width":16},{"name":"commit_bits_entries_2_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_instruction_peId","width":8},{"name":"commit_bits_entries_2_instruction_stid","width":1},{"name":"commit_bits_entries_2_instructionBits","width":64},{"name":"commit_bits_entries_2_instructionLengthBytes","width":4},{"name":"commit_bits_entries_2_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_2_memory_lsid","width":32},{"name":"commit_bits_entries_2_memory_pipeId","width":1},{"name":"commit_bits_entries_2_memory_rob_bid","width":8},{"name":"commit_bits_entries_2_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_memory_rob_peId","width":8},{"name":"commit_bits_entries_2_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_memory_rob_stid","width":1},{"name":"commit_bits_entries_2_memory_transaction_generation","width":16},{"name":"commit_bits_entries_2_memory_transaction_value","width":64},{"name":"commit_bits_entries_2_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_2_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_2_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_2_memoryStore","width":1},{"name":"commit_bits_entries_2_memoryValid","width":1},{"name":"commit_bits_entries_2_opcode","width":12},{"name":"commit_bits_entries_2_pc","width":64},{"name":"commit_bits_entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_2_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_2_result","width":64},{"name":"commit_bits_entries_2_resultValid","width":1},{"name":"commit_bits_entries_2_rob_bid","width":8},{"name":"commit_bits_entries_2_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_rob_peId","width":8},{"name":"commit_bits_entries_2_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_rob_stid","width":1},{"name":"commit_bits_entries_2_robGroupLast","width":1},{"name":"commit_bits_entries_2_storeData","width":64},{"name":"commit_bits_entries_2_storeMask","width":8},{"name":"commit_bits_entries_2_trap_cause","width":32},{"name":"commit_bits_entries_2_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_2_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_trap_instruction_peId","width":8},{"name":"commit_bits_entries_2_trap_instruction_stid","width":1},{"name":"commit_bits_entries_2_trap_kind","width":2},{"name":"commit_bits_entries_2_trap_rob_bid","width":8},{"name":"commit_bits_entries_2_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_trap_rob_peId","width":8},{"name":"commit_bits_entries_2_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_trap_rob_stid","width":1},{"name":"commit_bits_entries_2_trap_targetPc","width":64},{"name":"commit_bits_entries_2_trap_tval","width":64},{"name":"commit_bits_entries_2_trap_valid","width":1},{"name":"commit_bits_entries_3_destination_atag","width":6},{"name":"commit_bits_entries_3_destination_kind","width":3},{"name":"commit_bits_entries_3_destination_pGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPtag","width":7},{"name":"commit_bits_entries_3_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousTtag","width":5},{"name":"commit_bits_entries_3_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousUtag","width":5},{"name":"commit_bits_entries_3_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_3_destination_ptag","width":7},{"name":"commit_bits_entries_3_destination_ptagValid","width":1},{"name":"commit_bits_entries_3_destination_tGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_ttag","width":5},{"name":"commit_bits_entries_3_destination_ttagValid","width":1},{"name":"commit_bits_entries_3_destination_uGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_utag","width":5},{"name":"commit_bits_entries_3_destination_utagValid","width":1},{"name":"commit_bits_entries_3_destination_valid","width":1},{"name":"commit_bits_entries_3_instruction_epoch","width":16},{"name":"commit_bits_entries_3_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_instruction_peId","width":8},{"name":"commit_bits_entries_3_instruction_stid","width":1},{"name":"commit_bits_entries_3_instructionBits","width":64},{"name":"commit_bits_entries_3_instructionLengthBytes","width":4},{"name":"commit_bits_entries_3_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_3_memory_lsid","width":32},{"name":"commit_bits_entries_3_memory_pipeId","width":1},{"name":"commit_bits_entries_3_memory_rob_bid","width":8},{"name":"commit_bits_entries_3_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_memory_rob_peId","width":8},{"name":"commit_bits_entries_3_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_memory_rob_stid","width":1},{"name":"commit_bits_entries_3_memory_transaction_generation","width":16},{"name":"commit_bits_entries_3_memory_transaction_value","width":64},{"name":"commit_bits_entries_3_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_3_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_3_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_3_memoryStore","width":1},{"name":"commit_bits_entries_3_memoryValid","width":1},{"name":"commit_bits_entries_3_opcode","width":12},{"name":"commit_bits_entries_3_pc","width":64},{"name":"commit_bits_entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_3_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_3_result","width":64},{"name":"commit_bits_entries_3_resultValid","width":1},{"name":"commit_bits_entries_3_rob_bid","width":8},{"name":"commit_bits_entries_3_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_rob_peId","width":8},{"name":"commit_bits_entries_3_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_rob_stid","width":1},{"name":"commit_bits_entries_3_robGroupLast","width":1},{"name":"commit_bits_entries_3_storeData","width":64},{"name":"commit_bits_entries_3_storeMask","width":8},{"name":"commit_bits_entries_3_trap_cause","width":32},{"name":"commit_bits_entries_3_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_3_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_trap_instruction_peId","width":8},{"name":"commit_bits_entries_3_trap_instruction_stid","width":1},{"name":"commit_bits_entries_3_trap_kind","width":2},{"name":"commit_bits_entries_3_trap_rob_bid","width":8},{"name":"commit_bits_entries_3_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_trap_rob_peId","width":8},{"name":"commit_bits_entries_3_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_trap_rob_stid","width":1},{"name":"commit_bits_entries_3_trap_targetPc","width":64},{"name":"commit_bits_entries_3_trap_tval","width":64},{"name":"commit_bits_entries_3_trap_valid","width":1},{"name":"commit_bits_entries_4_destination_atag","width":6},{"name":"commit_bits_entries_4_destination_kind","width":3},{"name":"commit_bits_entries_4_destination_pGeneration","width":16},{"name":"commit_bits_entries_4_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_4_destination_previousPtag","width":7},{"name":"commit_bits_entries_4_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_4_destination_previousTtag","width":5},{"name":"commit_bits_entries_4_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_4_destination_previousUtag","width":5},{"name":"commit_bits_entries_4_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_4_destination_ptag","width":7},{"name":"commit_bits_entries_4_destination_ptagValid","width":1},{"name":"commit_bits_entries_4_destination_tGeneration","width":16},{"name":"commit_bits_entries_4_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_4_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_4_destination_ttag","width":5},{"name":"commit_bits_entries_4_destination_ttagValid","width":1},{"name":"commit_bits_entries_4_destination_uGeneration","width":16},{"name":"commit_bits_entries_4_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_4_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_4_destination_utag","width":5},{"name":"commit_bits_entries_4_destination_utagValid","width":1},{"name":"commit_bits_entries_4_destination_valid","width":1},{"name":"commit_bits_entries_4_instruction_epoch","width":16},{"name":"commit_bits_entries_4_instruction_instructionId","width":64},{"name":"commit_bits_entries_4_instruction_peId","width":8},{"name":"commit_bits_entries_4_instruction_stid","width":1},{"name":"commit_bits_entries_4_instructionBits","width":64},{"name":"commit_bits_entries_4_instructionLengthBytes","width":4},{"name":"commit_bits_entries_4_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_4_memory_lsid","width":32},{"name":"commit_bits_entries_4_memory_pipeId","width":1},{"name":"commit_bits_entries_4_memory_rob_bid","width":8},{"name":"commit_bits_entries_4_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_memory_rob_peId","width":8},{"name":"commit_bits_entries_4_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_memory_rob_stid","width":1},{"name":"commit_bits_entries_4_memory_transaction_generation","width":16},{"name":"commit_bits_entries_4_memory_transaction_value","width":64},{"name":"commit_bits_entries_4_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_4_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_4_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_4_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_4_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_4_memoryStore","width":1},{"name":"commit_bits_entries_4_memoryValid","width":1},{"name":"commit_bits_entries_4_opcode","width":12},{"name":"commit_bits_entries_4_pc","width":64},{"name":"commit_bits_entries_4_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_4_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_4_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_4_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_4_result","width":64},{"name":"commit_bits_entries_4_resultValid","width":1},{"name":"commit_bits_entries_4_rob_bid","width":8},{"name":"commit_bits_entries_4_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_rob_peId","width":8},{"name":"commit_bits_entries_4_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_rob_stid","width":1},{"name":"commit_bits_entries_4_robGroupLast","width":1},{"name":"commit_bits_entries_4_storeData","width":64},{"name":"commit_bits_entries_4_storeMask","width":8},{"name":"commit_bits_entries_4_trap_cause","width":32},{"name":"commit_bits_entries_4_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_4_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_4_trap_instruction_peId","width":8},{"name":"commit_bits_entries_4_trap_instruction_stid","width":1},{"name":"commit_bits_entries_4_trap_kind","width":2},{"name":"commit_bits_entries_4_trap_rob_bid","width":8},{"name":"commit_bits_entries_4_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_trap_rob_peId","width":8},{"name":"commit_bits_entries_4_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_trap_rob_stid","width":1},{"name":"commit_bits_entries_4_trap_targetPc","width":64},{"name":"commit_bits_entries_4_trap_tval","width":64},{"name":"commit_bits_entries_4_trap_valid","width":1},{"name":"commit_bits_entries_5_destination_atag","width":6},{"name":"commit_bits_entries_5_destination_kind","width":3},{"name":"commit_bits_entries_5_destination_pGeneration","width":16},{"name":"commit_bits_entries_5_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_5_destination_previousPtag","width":7},{"name":"commit_bits_entries_5_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_5_destination_previousTtag","width":5},{"name":"commit_bits_entries_5_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_5_destination_previousUtag","width":5},{"name":"commit_bits_entries_5_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_5_destination_ptag","width":7},{"name":"commit_bits_entries_5_destination_ptagValid","width":1},{"name":"commit_bits_entries_5_destination_tGeneration","width":16},{"name":"commit_bits_entries_5_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_5_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_5_destination_ttag","width":5},{"name":"commit_bits_entries_5_destination_ttagValid","width":1},{"name":"commit_bits_entries_5_destination_uGeneration","width":16},{"name":"commit_bits_entries_5_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_5_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_5_destination_utag","width":5},{"name":"commit_bits_entries_5_destination_utagValid","width":1},{"name":"commit_bits_entries_5_destination_valid","width":1},{"name":"commit_bits_entries_5_instruction_epoch","width":16},{"name":"commit_bits_entries_5_instruction_instructionId","width":64},{"name":"commit_bits_entries_5_instruction_peId","width":8},{"name":"commit_bits_entries_5_instruction_stid","width":1},{"name":"commit_bits_entries_5_instructionBits","width":64},{"name":"commit_bits_entries_5_instructionLengthBytes","width":4},{"name":"commit_bits_entries_5_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_5_memory_lsid","width":32},{"name":"commit_bits_entries_5_memory_pipeId","width":1},{"name":"commit_bits_entries_5_memory_rob_bid","width":8},{"name":"commit_bits_entries_5_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_memory_rob_peId","width":8},{"name":"commit_bits_entries_5_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_memory_rob_stid","width":1},{"name":"commit_bits_entries_5_memory_transaction_generation","width":16},{"name":"commit_bits_entries_5_memory_transaction_value","width":64},{"name":"commit_bits_entries_5_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_5_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_5_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_5_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_5_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_5_memoryStore","width":1},{"name":"commit_bits_entries_5_memoryValid","width":1},{"name":"commit_bits_entries_5_opcode","width":12},{"name":"commit_bits_entries_5_pc","width":64},{"name":"commit_bits_entries_5_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_5_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_5_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_5_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_5_result","width":64},{"name":"commit_bits_entries_5_resultValid","width":1},{"name":"commit_bits_entries_5_rob_bid","width":8},{"name":"commit_bits_entries_5_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_rob_peId","width":8},{"name":"commit_bits_entries_5_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_rob_stid","width":1},{"name":"commit_bits_entries_5_robGroupLast","width":1},{"name":"commit_bits_entries_5_storeData","width":64},{"name":"commit_bits_entries_5_storeMask","width":8},{"name":"commit_bits_entries_5_trap_cause","width":32},{"name":"commit_bits_entries_5_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_5_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_5_trap_instruction_peId","width":8},{"name":"commit_bits_entries_5_trap_instruction_stid","width":1},{"name":"commit_bits_entries_5_trap_kind","width":2},{"name":"commit_bits_entries_5_trap_rob_bid","width":8},{"name":"commit_bits_entries_5_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_trap_rob_peId","width":8},{"name":"commit_bits_entries_5_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_trap_rob_stid","width":1},{"name":"commit_bits_entries_5_trap_targetPc","width":64},{"name":"commit_bits_entries_5_trap_tval","width":64},{"name":"commit_bits_entries_5_trap_valid","width":1},{"name":"commit_ready","width":1},{"name":"commit_valid","width":1},{"name":"dataMemoryRequest_0_bits_accessKind","width":2},{"name":"dataMemoryRequest_0_bits_address","width":64},{"name":"dataMemoryRequest_0_bits_byteMask","width":8},{"name":"dataMemoryRequest_0_bits_command","width":3},{"name":"dataMemoryRequest_0_bits_data","width":64},{"name":"dataMemoryRequest_0_bits_identity_generation","width":16},{"name":"dataMemoryRequest_0_bits_identity_value","width":64},{"name":"dataMemoryRequest_0_bits_instructionSide","width":1},{"name":"dataMemoryRequest_0_bits_size","width":3},{"name":"dataMemoryRequest_0_ready","width":1},{"name":"dataMemoryRequest_0_valid","width":1},{"name":"dataMemoryRequest_1_bits_accessKind","width":2},{"name":"dataMemoryRequest_1_bits_address","width":64},{"name":"dataMemoryRequest_1_bits_byteMask","width":8},{"name":"dataMemoryRequest_1_bits_command","width":3},{"name":"dataMemoryRequest_1_bits_data","width":64},{"name":"dataMemoryRequest_1_bits_identity_generation","width":16},{"name":"dataMemoryRequest_1_bits_identity_value","width":64},{"name":"dataMemoryRequest_1_bits_instructionSide","width":1},{"name":"dataMemoryRequest_1_bits_size","width":3},{"name":"dataMemoryRequest_1_ready","width":1},{"name":"dataMemoryRequest_1_valid","width":1},{"name":"dataMemoryRequest_2_bits_accessKind","width":2},{"name":"dataMemoryRequest_2_bits_address","width":64},{"name":"dataMemoryRequest_2_bits_byteMask","width":8},{"name":"dataMemoryRequest_2_bits_command","width":3},{"name":"dataMemoryRequest_2_bits_data","width":64},{"name":"dataMemoryRequest_2_bits_identity_generation","width":16},{"name":"dataMemoryRequest_2_bits_identity_value","width":64},{"name":"dataMemoryRequest_2_bits_instructionSide","width":1},{"name":"dataMemoryRequest_2_bits_size","width":3},{"name":"dataMemoryRequest_2_ready","width":1},{"name":"dataMemoryRequest_2_valid","width":1},{"name":"dataMemoryRequest_3_bits_accessKind","width":2},{"name":"dataMemoryRequest_3_bits_address","width":64},{"name":"dataMemoryRequest_3_bits_byteMask","width":8},{"name":"dataMemoryRequest_3_bits_command","width":3},{"name":"dataMemoryRequest_3_bits_data","width":64},{"name":"dataMemoryRequest_3_bits_identity_generation","width":16},{"name":"dataMemoryRequest_3_bits_identity_value","width":64},{"name":"dataMemoryRequest_3_bits_instructionSide","width":1},{"name":"dataMemoryRequest_3_bits_size","width":3},{"name":"dataMemoryRequest_3_ready","width":1},{"name":"dataMemoryRequest_3_valid","width":1},{"name":"dataMemoryResponse_0_bits_address","width":64},{"name":"dataMemoryResponse_0_bits_attributesValid","width":1},{"name":"dataMemoryResponse_0_bits_cacheable","width":1},{"name":"dataMemoryResponse_0_bits_corrupt","width":1},{"name":"dataMemoryResponse_0_bits_data","width":64},{"name":"dataMemoryResponse_0_bits_denied","width":1},{"name":"dataMemoryResponse_0_bits_device","width":1},{"name":"dataMemoryResponse_0_bits_errorCause","width":32},{"name":"dataMemoryResponse_0_bits_identity_generation","width":16},{"name":"dataMemoryResponse_0_bits_identity_value","width":64},{"name":"dataMemoryResponse_0_bits_lineData","width":512},{"name":"dataMemoryResponse_0_bits_readable","width":1},{"name":"dataMemoryResponse_0_bits_writable","width":1},{"name":"dataMemoryResponse_0_ready","width":1},{"name":"dataMemoryResponse_0_valid","width":1},{"name":"dataMemoryResponse_1_bits_address","width":64},{"name":"dataMemoryResponse_1_bits_attributesValid","width":1},{"name":"dataMemoryResponse_1_bits_cacheable","width":1},{"name":"dataMemoryResponse_1_bits_corrupt","width":1},{"name":"dataMemoryResponse_1_bits_data","width":64},{"name":"dataMemoryResponse_1_bits_denied","width":1},{"name":"dataMemoryResponse_1_bits_device","width":1},{"name":"dataMemoryResponse_1_bits_errorCause","width":32},{"name":"dataMemoryResponse_1_bits_identity_generation","width":16},{"name":"dataMemoryResponse_1_bits_identity_value","width":64},{"name":"dataMemoryResponse_1_bits_lineData","width":512},{"name":"dataMemoryResponse_1_bits_readable","width":1},{"name":"dataMemoryResponse_1_bits_writable","width":1},{"name":"dataMemoryResponse_1_ready","width":1},{"name":"dataMemoryResponse_1_valid","width":1},{"name":"dataMemoryResponse_2_bits_address","width":64},{"name":"dataMemoryResponse_2_bits_attributesValid","width":1},{"name":"dataMemoryResponse_2_bits_cacheable","width":1},{"name":"dataMemoryResponse_2_bits_corrupt","width":1},{"name":"dataMemoryResponse_2_bits_data","width":64},{"name":"dataMemoryResponse_2_bits_denied","width":1},{"name":"dataMemoryResponse_2_bits_device","width":1},{"name":"dataMemoryResponse_2_bits_errorCause","width":32},{"name":"dataMemoryResponse_2_bits_identity_generation","width":16},{"name":"dataMemoryResponse_2_bits_identity_value","width":64},{"name":"dataMemoryResponse_2_bits_lineData","width":512},{"name":"dataMemoryResponse_2_bits_readable","width":1},{"name":"dataMemoryResponse_2_bits_writable","width":1},{"name":"dataMemoryResponse_2_ready","width":1},{"name":"dataMemoryResponse_2_valid","width":1},{"name":"dataMemoryResponse_3_bits_address","width":64},{"name":"dataMemoryResponse_3_bits_attributesValid","width":1},{"name":"dataMemoryResponse_3_bits_cacheable","width":1},{"name":"dataMemoryResponse_3_bits_corrupt","width":1},{"name":"dataMemoryResponse_3_bits_data","width":64},{"name":"dataMemoryResponse_3_bits_denied","width":1},{"name":"dataMemoryResponse_3_bits_device","width":1},{"name":"dataMemoryResponse_3_bits_errorCause","width":32},{"name":"dataMemoryResponse_3_bits_identity_generation","width":16},{"name":"dataMemoryResponse_3_bits_identity_value","width":64},{"name":"dataMemoryResponse_3_bits_lineData","width":512},{"name":"dataMemoryResponse_3_bits_readable","width":1},{"name":"dataMemoryResponse_3_bits_writable","width":1},{"name":"dataMemoryResponse_3_ready","width":1},{"name":"dataMemoryResponse_3_valid","width":1},{"name":"debugRequest_bits_address","width":64},{"name":"debugRequest_bits_command","width":3},{"name":"debugRequest_bits_data","width":64},{"name":"debugRequest_bits_stid","width":1},{"name":"debugRequest_bits_transactionId","width":64},{"name":"debugRequest_ready","width":1},{"name":"debugRequest_valid","width":1},{"name":"debugResponse_bits_accepted","width":1},{"name":"debugResponse_bits_data","width":64},{"name":"debugResponse_bits_error","width":1},{"name":"debugResponse_bits_transactionId","width":64},{"name":"debugResponse_ready","width":1},{"name":"debugResponse_valid","width":1},{"name":"instructionMemoryRequest_bits_accessKind","width":2},{"name":"instructionMemoryRequest_bits_address","width":64},{"name":"instructionMemoryRequest_bits_byteMask","width":8},{"name":"instructionMemoryRequest_bits_command","width":3},{"name":"instructionMemoryRequest_bits_data","width":64},{"name":"instructionMemoryRequest_bits_identity_generation","width":16},{"name":"instructionMemoryRequest_bits_identity_value","width":64},{"name":"instructionMemoryRequest_bits_instructionSide","width":1},{"name":"instructionMemoryRequest_bits_size","width":3},{"name":"instructionMemoryRequest_ready","width":1},{"name":"instructionMemoryRequest_valid","width":1},{"name":"instructionMemoryResponse_bits_address","width":64},{"name":"instructionMemoryResponse_bits_attributesValid","width":1},{"name":"instructionMemoryResponse_bits_cacheable","width":1},{"name":"instructionMemoryResponse_bits_corrupt","width":1},{"name":"instructionMemoryResponse_bits_data","width":64},{"name":"instructionMemoryResponse_bits_denied","width":1},{"name":"instructionMemoryResponse_bits_device","width":1},{"name":"instructionMemoryResponse_bits_errorCause","width":32},{"name":"instructionMemoryResponse_bits_identity_generation","width":16},{"name":"instructionMemoryResponse_bits_identity_value","width":64},{"name":"instructionMemoryResponse_bits_lineData","width":512},{"name":"instructionMemoryResponse_bits_readable","width":1},{"name":"instructionMemoryResponse_bits_writable","width":1},{"name":"instructionMemoryResponse_ready","width":1},{"name":"instructionMemoryResponse_valid","width":1},{"name":"interrupt_bits_cause","width":32},{"name":"interrupt_bits_priority","width":8},{"name":"interrupt_bits_stid","width":1},{"name":"interrupt_bits_valid","width":1},{"name":"interrupt_valid","width":1},{"name":"loadReissueRequest_bits_address","width":64},{"name":"loadReissueRequest_bits_allocationId_generation","width":16},{"name":"loadReissueRequest_bits_allocationId_value","width":64},{"name":"loadReissueRequest_bits_currentIdentity_attemptGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_lsid","width":32},{"name":"loadReissueRequest_bits_currentIdentity_pipeId","width":1},{"name":"loadReissueRequest_bits_currentIdentity_rob_bid","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_brobGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_memberIndex","width":2},{"name":"loadReissueRequest_bits_currentIdentity_rob_peId","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_residentGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridSlot","width":6},{"name":"loadReissueRequest_bits_currentIdentity_rob_stid","width":1},{"name":"loadReissueRequest_bits_currentIdentity_transaction_generation","width":16},{"name":"loadReissueRequest_bits_currentIdentity_transaction_value","width":64},{"name":"loadReissueRequest_ready","width":1},{"name":"loadReissueRequest_valid","width":1},{"name":"lsuProtocolError","width":1},{"name":"lsuQuiescent","width":1},{"name":"maintenance_bits_address","width":64},{"name":"maintenance_bits_command","width":2},{"name":"maintenance_ready","width":1},{"name":"maintenance_valid","width":1},{"name":"maintenanceResult_bits_address","width":64},{"name":"maintenanceResult_bits_command","width":2},{"name":"maintenanceResult_bits_success","width":1},{"name":"maintenanceResult_ready","width":1},{"name":"maintenanceResult_valid","width":1},{"name":"memoryFault_bits_address","width":64},{"name":"memoryFault_bits_cause","width":1},{"name":"memoryFault_bits_identity_attemptGeneration","width":16},{"name":"memoryFault_bits_identity_lsid","width":32},{"name":"memoryFault_bits_identity_pipeId","width":1},{"name":"memoryFault_bits_identity_rob_bid","width":8},{"name":"memoryFault_bits_identity_rob_brobGeneration","width":16},{"name":"memoryFault_bits_identity_rob_memberIndex","width":2},{"name":"memoryFault_bits_identity_rob_peId","width":8},{"name":"memoryFault_bits_identity_rob_residentGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridSlot","width":6},{"name":"memoryFault_bits_identity_rob_stid","width":1},{"name":"memoryFault_bits_identity_transaction_generation","width":16},{"name":"memoryFault_bits_identity_transaction_value","width":64},{"name":"memoryFault_bits_write","width":1},{"name":"memoryFault_ready","width":1},{"name":"memoryFault_valid","width":1},{"name":"pInit_bits_atag","width":5},{"name":"pInit_bits_epoch","width":16},{"name":"pInit_bits_generation","width":16},{"name":"pInit_bits_ptag","width":7},{"name":"pInit_bits_stid","width":1},{"name":"pInit_bits_value","width":64},{"name":"pInit_ready","width":1},{"name":"pInit_valid","width":1},{"name":"performanceCounters_0","width":64},{"name":"performanceCounters_1","width":64},{"name":"performanceCounters_2","width":64},{"name":"performanceCounters_3","width":64},{"name":"performanceCounters_4","width":64},{"name":"performanceCounters_5","width":64},{"name":"performanceCounters_6","width":64},{"name":"performanceCounters_7","width":64},{"name":"performanceCounters_8","width":64},{"name":"performanceCounters_9","width":64},{"name":"performanceCounters_10","width":64},{"name":"performanceCounters_11","width":64},{"name":"performanceCounters_12","width":64},{"name":"performanceCounters_13","width":64},{"name":"performanceCounters_14","width":64},{"name":"performanceCounters_15","width":64},{"name":"performanceCounters_16","width":64},{"name":"performanceCounters_17","width":64},{"name":"performanceCounters_18","width":64},{"name":"performanceCounters_19","width":64},{"name":"performanceCounters_20","width":64},{"name":"performanceCounters_21","width":64},{"name":"performanceCounters_22","width":64},{"name":"performanceCounters_23","width":64},{"name":"performanceCounters_24","width":64},{"name":"performanceCounters_25","width":64},{"name":"performanceCounters_26","width":64},{"name":"performanceCounters_27","width":64},{"name":"performanceCounters_28","width":64},{"name":"performanceCounters_29","width":64},{"name":"performanceCounters_30","width":64},{"name":"performanceCounters_31","width":64},{"name":"systemIssue_0_bits_immediate","width":64},{"name":"systemIssue_0_bits_instruction_epoch","width":16},{"name":"systemIssue_0_bits_instruction_instructionId","width":64},{"name":"systemIssue_0_bits_instruction_peId","width":8},{"name":"systemIssue_0_bits_instruction_stid","width":1},{"name":"systemIssue_0_bits_opcode","width":12},{"name":"systemIssue_0_bits_rob_bid","width":8},{"name":"systemIssue_0_bits_rob_brobGeneration","width":16},{"name":"systemIssue_0_bits_rob_memberIndex","width":2},{"name":"systemIssue_0_bits_rob_peId","width":8},{"name":"systemIssue_0_bits_rob_residentGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridSlot","width":6},{"name":"systemIssue_0_bits_rob_stid","width":1},{"name":"systemIssue_0_bits_transactionId","width":64},{"name":"systemIssue_0_ready","width":1},{"name":"systemIssue_0_valid","width":1},{"name":"trace_bits_count","width":3},{"name":"trace_bits_entries_0_cycle","width":64},{"name":"trace_bits_entries_0_instruction_epoch","width":16},{"name":"trace_bits_entries_0_instruction_instructionId","width":64},{"name":"trace_bits_entries_0_instruction_peId","width":8},{"name":"trace_bits_entries_0_instruction_stid","width":1},{"name":"trace_bits_entries_0_instructionValid","width":1},{"name":"trace_bits_entries_0_kind","width":3},{"name":"trace_bits_entries_0_opcode","width":12},{"name":"trace_bits_entries_0_payload","width":64},{"name":"trace_bits_entries_0_pc","width":64},{"name":"trace_bits_entries_0_rob_bid","width":8},{"name":"trace_bits_entries_0_rob_brobGeneration","width":16},{"name":"trace_bits_entries_0_rob_memberIndex","width":2},{"name":"trace_bits_entries_0_rob_peId","width":8},{"name":"trace_bits_entries_0_rob_residentGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridSlot","width":6},{"name":"trace_bits_entries_0_rob_stid","width":1},{"name":"trace_bits_entries_0_robValid","width":1},{"name":"trace_bits_entries_0_source","width":3},{"name":"trace_bits_entries_1_cycle","width":64},{"name":"trace_bits_entries_1_instruction_epoch","width":16},{"name":"trace_bits_entries_1_instruction_instructionId","width":64},{"name":"trace_bits_entries_1_instruction_peId","width":8},{"name":"trace_bits_entries_1_instruction_stid","width":1},{"name":"trace_bits_entries_1_instructionValid","width":1},{"name":"trace_bits_entries_1_kind","width":3},{"name":"trace_bits_entries_1_opcode","width":12},{"name":"trace_bits_entries_1_payload","width":64},{"name":"trace_bits_entries_1_pc","width":64},{"name":"trace_bits_entries_1_rob_bid","width":8},{"name":"trace_bits_entries_1_rob_brobGeneration","width":16},{"name":"trace_bits_entries_1_rob_memberIndex","width":2},{"name":"trace_bits_entries_1_rob_peId","width":8},{"name":"trace_bits_entries_1_rob_residentGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridSlot","width":6},{"name":"trace_bits_entries_1_rob_stid","width":1},{"name":"trace_bits_entries_1_robValid","width":1},{"name":"trace_bits_entries_1_source","width":3},{"name":"trace_bits_entries_2_cycle","width":64},{"name":"trace_bits_entries_2_instruction_epoch","width":16},{"name":"trace_bits_entries_2_instruction_instructionId","width":64},{"name":"trace_bits_entries_2_instruction_peId","width":8},{"name":"trace_bits_entries_2_instruction_stid","width":1},{"name":"trace_bits_entries_2_instructionValid","width":1},{"name":"trace_bits_entries_2_kind","width":3},{"name":"trace_bits_entries_2_opcode","width":12},{"name":"trace_bits_entries_2_payload","width":64},{"name":"trace_bits_entries_2_pc","width":64},{"name":"trace_bits_entries_2_rob_bid","width":8},{"name":"trace_bits_entries_2_rob_brobGeneration","width":16},{"name":"trace_bits_entries_2_rob_memberIndex","width":2},{"name":"trace_bits_entries_2_rob_peId","width":8},{"name":"trace_bits_entries_2_rob_residentGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridSlot","width":6},{"name":"trace_bits_entries_2_rob_stid","width":1},{"name":"trace_bits_entries_2_robValid","width":1},{"name":"trace_bits_entries_2_source","width":3},{"name":"trace_bits_entries_3_cycle","width":64},{"name":"trace_bits_entries_3_instruction_epoch","width":16},{"name":"trace_bits_entries_3_instruction_instructionId","width":64},{"name":"trace_bits_entries_3_instruction_peId","width":8},{"name":"trace_bits_entries_3_instruction_stid","width":1},{"name":"trace_bits_entries_3_instructionValid","width":1},{"name":"trace_bits_entries_3_kind","width":3},{"name":"trace_bits_entries_3_opcode","width":12},{"name":"trace_bits_entries_3_payload","width":64},{"name":"trace_bits_entries_3_pc","width":64},{"name":"trace_bits_entries_3_rob_bid","width":8},{"name":"trace_bits_entries_3_rob_brobGeneration","width":16},{"name":"trace_bits_entries_3_rob_memberIndex","width":2},{"name":"trace_bits_entries_3_rob_peId","width":8},{"name":"trace_bits_entries_3_rob_residentGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridSlot","width":6},{"name":"trace_bits_entries_3_rob_stid","width":1},{"name":"trace_bits_entries_3_robValid","width":1},{"name":"trace_bits_entries_3_source","width":3},{"name":"trace_bits_entries_4_cycle","width":64},{"name":"trace_bits_entries_4_instruction_epoch","width":16},{"name":"trace_bits_entries_4_instruction_instructionId","width":64},{"name":"trace_bits_entries_4_instruction_peId","width":8},{"name":"trace_bits_entries_4_instruction_stid","width":1},{"name":"trace_bits_entries_4_instructionValid","width":1},{"name":"trace_bits_entries_4_kind","width":3},{"name":"trace_bits_entries_4_opcode","width":12},{"name":"trace_bits_entries_4_payload","width":64},{"name":"trace_bits_entries_4_pc","width":64},{"name":"trace_bits_entries_4_rob_bid","width":8},{"name":"trace_bits_entries_4_rob_brobGeneration","width":16},{"name":"trace_bits_entries_4_rob_memberIndex","width":2},{"name":"trace_bits_entries_4_rob_peId","width":8},{"name":"trace_bits_entries_4_rob_residentGeneration","width":16},{"name":"trace_bits_entries_4_rob_ridGeneration","width":16},{"name":"trace_bits_entries_4_rob_ridSlot","width":6},{"name":"trace_bits_entries_4_rob_stid","width":1},{"name":"trace_bits_entries_4_robValid","width":1},{"name":"trace_bits_entries_4_source","width":3},{"name":"trace_bits_entries_5_cycle","width":64},{"name":"trace_bits_entries_5_instruction_epoch","width":16},{"name":"trace_bits_entries_5_instruction_instructionId","width":64},{"name":"trace_bits_entries_5_instruction_peId","width":8},{"name":"trace_bits_entries_5_instruction_stid","width":1},{"name":"trace_bits_entries_5_instructionValid","width":1},{"name":"trace_bits_entries_5_kind","width":3},{"name":"trace_bits_entries_5_opcode","width":12},{"name":"trace_bits_entries_5_payload","width":64},{"name":"trace_bits_entries_5_pc","width":64},{"name":"trace_bits_entries_5_rob_bid","width":8},{"name":"trace_bits_entries_5_rob_brobGeneration","width":16},{"name":"trace_bits_entries_5_rob_memberIndex","width":2},{"name":"trace_bits_entries_5_rob_peId","width":8},{"name":"trace_bits_entries_5_rob_residentGeneration","width":16},{"name":"trace_bits_entries_5_rob_ridGeneration","width":16},{"name":"trace_bits_entries_5_rob_ridSlot","width":6},{"name":"trace_bits_entries_5_rob_stid","width":1},{"name":"trace_bits_entries_5_robValid","width":1},{"name":"trace_bits_entries_5_source","width":3},{"name":"trace_ready","width":1},{"name":"trace_valid","width":1},{"name":"trap_bits_cause","width":32},{"name":"trap_bits_instruction_epoch","width":16},{"name":"trap_bits_instruction_instructionId","width":64},{"name":"trap_bits_instruction_peId","width":8},{"name":"trap_bits_instruction_stid","width":1},{"name":"trap_bits_kind","width":2},{"name":"trap_bits_rob_bid","width":8},{"name":"trap_bits_rob_brobGeneration","width":16},{"name":"trap_bits_rob_memberIndex","width":2},{"name":"trap_bits_rob_peId","width":8},{"name":"trap_bits_rob_residentGeneration","width":16},{"name":"trap_bits_rob_ridGeneration","width":16},{"name":"trap_bits_rob_ridSlot","width":6},{"name":"trap_bits_rob_stid","width":1},{"name":"trap_bits_targetPc","width":64},{"name":"trap_bits_tval","width":64},{"name":"trap_bits_valid","width":1},{"name":"trap_ready","width":1},{"name":"trap_valid","width":1}]},{"name":"ifu_to_ctu","contract_id":"IFC-IFU-CTU-001","producer":"IFU","consumer":"CTU","lanes":6,"payload":"FetchedPacket","ports":[{"name":"count","width":3},{"name":"entries_0_fetchFault","width":1},{"name":"entries_0_fetchFaultCause","width":32},{"name":"entries_0_identity_epoch","width":16},{"name":"entries_0_identity_instructionId","width":64},{"name":"entries_0_identity_peId","width":8},{"name":"entries_0_identity_stid","width":1},{"name":"entries_0_instruction","width":64},{"name":"entries_0_lengthBytes","width":4},{"name":"entries_0_pc","width":64},{"name":"entries_0_prediction_checkpointId","width":5},{"name":"entries_0_prediction_confidence","width":2},{"name":"entries_0_prediction_epoch","width":16},{"name":"entries_0_prediction_fallthroughPc","width":64},{"name":"entries_0_prediction_kind","width":3},{"name":"entries_0_prediction_predictionTag","width":64},{"name":"entries_0_prediction_provider","width":4},{"name":"entries_0_prediction_requestPc","width":64},{"name":"entries_0_prediction_taken","width":1},{"name":"entries_0_prediction_target","width":64},{"name":"entries_0_prediction_transactionId","width":64},{"name":"entries_0_prediction_valid","width":1},{"name":"entries_1_fetchFault","width":1},{"name":"entries_1_fetchFaultCause","width":32},{"name":"entries_1_identity_epoch","width":16},{"name":"entries_1_identity_instructionId","width":64},{"name":"entries_1_identity_peId","width":8},{"name":"entries_1_identity_stid","width":1},{"name":"entries_1_instruction","width":64},{"name":"entries_1_lengthBytes","width":4},{"name":"entries_1_pc","width":64},{"name":"entries_1_prediction_checkpointId","width":5},{"name":"entries_1_prediction_confidence","width":2},{"name":"entries_1_prediction_epoch","width":16},{"name":"entries_1_prediction_fallthroughPc","width":64},{"name":"entries_1_prediction_kind","width":3},{"name":"entries_1_prediction_predictionTag","width":64},{"name":"entries_1_prediction_provider","width":4},{"name":"entries_1_prediction_requestPc","width":64},{"name":"entries_1_prediction_taken","width":1},{"name":"entries_1_prediction_target","width":64},{"name":"entries_1_prediction_transactionId","width":64},{"name":"entries_1_prediction_valid","width":1},{"name":"entries_2_fetchFault","width":1},{"name":"entries_2_fetchFaultCause","width":32},{"name":"entries_2_identity_epoch","width":16},{"name":"entries_2_identity_instructionId","width":64},{"name":"entries_2_identity_peId","width":8},{"name":"entries_2_identity_stid","width":1},{"name":"entries_2_instruction","width":64},{"name":"entries_2_lengthBytes","width":4},{"name":"entries_2_pc","width":64},{"name":"entries_2_prediction_checkpointId","width":5},{"name":"entries_2_prediction_confidence","width":2},{"name":"entries_2_prediction_epoch","width":16},{"name":"entries_2_prediction_fallthroughPc","width":64},{"name":"entries_2_prediction_kind","width":3},{"name":"entries_2_prediction_predictionTag","width":64},{"name":"entries_2_prediction_provider","width":4},{"name":"entries_2_prediction_requestPc","width":64},{"name":"entries_2_prediction_taken","width":1},{"name":"entries_2_prediction_target","width":64},{"name":"entries_2_prediction_transactionId","width":64},{"name":"entries_2_prediction_valid","width":1},{"name":"entries_3_fetchFault","width":1},{"name":"entries_3_fetchFaultCause","width":32},{"name":"entries_3_identity_epoch","width":16},{"name":"entries_3_identity_instructionId","width":64},{"name":"entries_3_identity_peId","width":8},{"name":"entries_3_identity_stid","width":1},{"name":"entries_3_instruction","width":64},{"name":"entries_3_lengthBytes","width":4},{"name":"entries_3_pc","width":64},{"name":"entries_3_prediction_checkpointId","width":5},{"name":"entries_3_prediction_confidence","width":2},{"name":"entries_3_prediction_epoch","width":16},{"name":"entries_3_prediction_fallthroughPc","width":64},{"name":"entries_3_prediction_kind","width":3},{"name":"entries_3_prediction_predictionTag","width":64},{"name":"entries_3_prediction_provider","width":4},{"name":"entries_3_prediction_requestPc","width":64},{"name":"entries_3_prediction_taken","width":1},{"name":"entries_3_prediction_target","width":64},{"name":"entries_3_prediction_transactionId","width":64},{"name":"entries_3_prediction_valid","width":1},{"name":"entries_4_fetchFault","width":1},{"name":"entries_4_fetchFaultCause","width":32},{"name":"entries_4_identity_epoch","width":16},{"name":"entries_4_identity_instructionId","width":64},{"name":"entries_4_identity_peId","width":8},{"name":"entries_4_identity_stid","width":1},{"name":"entries_4_instruction","width":64},{"name":"entries_4_lengthBytes","width":4},{"name":"entries_4_pc","width":64},{"name":"entries_4_prediction_checkpointId","width":5},{"name":"entries_4_prediction_confidence","width":2},{"name":"entries_4_prediction_epoch","width":16},{"name":"entries_4_prediction_fallthroughPc","width":64},{"name":"entries_4_prediction_kind","width":3},{"name":"entries_4_prediction_predictionTag","width":64},{"name":"entries_4_prediction_provider","width":4},{"name":"entries_4_prediction_requestPc","width":64},{"name":"entries_4_prediction_taken","width":1},{"name":"entries_4_prediction_target","width":64},{"name":"entries_4_prediction_transactionId","width":64},{"name":"entries_4_prediction_valid","width":1},{"name":"entries_5_fetchFault","width":1},{"name":"entries_5_fetchFaultCause","width":32},{"name":"entries_5_identity_epoch","width":16},{"name":"entries_5_identity_instructionId","width":64},{"name":"entries_5_identity_peId","width":8},{"name":"entries_5_identity_stid","width":1},{"name":"entries_5_instruction","width":64},{"name":"entries_5_lengthBytes","width":4},{"name":"entries_5_pc","width":64},{"name":"entries_5_prediction_checkpointId","width":5},{"name":"entries_5_prediction_confidence","width":2},{"name":"entries_5_prediction_epoch","width":16},{"name":"entries_5_prediction_fallthroughPc","width":64},{"name":"entries_5_prediction_kind","width":3},{"name":"entries_5_prediction_predictionTag","width":64},{"name":"entries_5_prediction_provider","width":4},{"name":"entries_5_prediction_requestPc","width":64},{"name":"entries_5_prediction_taken","width":1},{"name":"entries_5_prediction_target","width":64},{"name":"entries_5_prediction_transactionId","width":64},{"name":"entries_5_prediction_valid","width":1}]},{"name":"ctu_to_ooo","contract_id":"IFC-CTU-OOO-001","producer":"CTU","consumer":"OOO","lanes":6,"payload":"D1Packet","ports":[{"name":"count","width":3},{"name":"entries_0_kind","width":1},{"name":"entries_0_parent_fetchFault","width":1},{"name":"entries_0_parent_fetchFaultCause","width":32},{"name":"entries_0_parent_identity_epoch","width":16},{"name":"entries_0_parent_identity_instructionId","width":64},{"name":"entries_0_parent_identity_peId","width":8},{"name":"entries_0_parent_identity_stid","width":1},{"name":"entries_0_parent_instruction","width":64},{"name":"entries_0_parent_lengthBytes","width":4},{"name":"entries_0_parent_pc","width":64},{"name":"entries_0_parent_prediction_checkpointId","width":5},{"name":"entries_0_parent_prediction_confidence","width":2},{"name":"entries_0_parent_prediction_epoch","width":16},{"name":"entries_0_parent_prediction_fallthroughPc","width":64},{"name":"entries_0_parent_prediction_kind","width":3},{"name":"entries_0_parent_prediction_predictionTag","width":64},{"name":"entries_0_parent_prediction_provider","width":4},{"name":"entries_0_parent_prediction_requestPc","width":64},{"name":"entries_0_parent_prediction_taken","width":1},{"name":"entries_0_parent_prediction_target","width":64},{"name":"entries_0_parent_prediction_transactionId","width":64},{"name":"entries_0_parent_prediction_valid","width":1},{"name":"entries_0_templateCount","width":8},{"name":"entries_0_templateImmediate","width":64},{"name":"entries_0_templateOpcode","width":12},{"name":"entries_0_templateOrdinal","width":8},{"name":"entries_1_kind","width":1},{"name":"entries_1_parent_fetchFault","width":1},{"name":"entries_1_parent_fetchFaultCause","width":32},{"name":"entries_1_parent_identity_epoch","width":16},{"name":"entries_1_parent_identity_instructionId","width":64},{"name":"entries_1_parent_identity_peId","width":8},{"name":"entries_1_parent_identity_stid","width":1},{"name":"entries_1_parent_instruction","width":64},{"name":"entries_1_parent_lengthBytes","width":4},{"name":"entries_1_parent_pc","width":64},{"name":"entries_1_parent_prediction_checkpointId","width":5},{"name":"entries_1_parent_prediction_confidence","width":2},{"name":"entries_1_parent_prediction_epoch","width":16},{"name":"entries_1_parent_prediction_fallthroughPc","width":64},{"name":"entries_1_parent_prediction_kind","width":3},{"name":"entries_1_parent_prediction_predictionTag","width":64},{"name":"entries_1_parent_prediction_provider","width":4},{"name":"entries_1_parent_prediction_requestPc","width":64},{"name":"entries_1_parent_prediction_taken","width":1},{"name":"entries_1_parent_prediction_target","width":64},{"name":"entries_1_parent_prediction_transactionId","width":64},{"name":"entries_1_parent_prediction_valid","width":1},{"name":"entries_1_templateCount","width":8},{"name":"entries_1_templateImmediate","width":64},{"name":"entries_1_templateOpcode","width":12},{"name":"entries_1_templateOrdinal","width":8},{"name":"entries_2_kind","width":1},{"name":"entries_2_parent_fetchFault","width":1},{"name":"entries_2_parent_fetchFaultCause","width":32},{"name":"entries_2_parent_identity_epoch","width":16},{"name":"entries_2_parent_identity_instructionId","width":64},{"name":"entries_2_parent_identity_peId","width":8},{"name":"entries_2_parent_identity_stid","width":1},{"name":"entries_2_parent_instruction","width":64},{"name":"entries_2_parent_lengthBytes","width":4},{"name":"entries_2_parent_pc","width":64},{"name":"entries_2_parent_prediction_checkpointId","width":5},{"name":"entries_2_parent_prediction_confidence","width":2},{"name":"entries_2_parent_prediction_epoch","width":16},{"name":"entries_2_parent_prediction_fallthroughPc","width":64},{"name":"entries_2_parent_prediction_kind","width":3},{"name":"entries_2_parent_prediction_predictionTag","width":64},{"name":"entries_2_parent_prediction_provider","width":4},{"name":"entries_2_parent_prediction_requestPc","width":64},{"name":"entries_2_parent_prediction_taken","width":1},{"name":"entries_2_parent_prediction_target","width":64},{"name":"entries_2_parent_prediction_transactionId","width":64},{"name":"entries_2_parent_prediction_valid","width":1},{"name":"entries_2_templateCount","width":8},{"name":"entries_2_templateImmediate","width":64},{"name":"entries_2_templateOpcode","width":12},{"name":"entries_2_templateOrdinal","width":8},{"name":"entries_3_kind","width":1},{"name":"entries_3_parent_fetchFault","width":1},{"name":"entries_3_parent_fetchFaultCause","width":32},{"name":"entries_3_parent_identity_epoch","width":16},{"name":"entries_3_parent_identity_instructionId","width":64},{"name":"entries_3_parent_identity_peId","width":8},{"name":"entries_3_parent_identity_stid","width":1},{"name":"entries_3_parent_instruction","width":64},{"name":"entries_3_parent_lengthBytes","width":4},{"name":"entries_3_parent_pc","width":64},{"name":"entries_3_parent_prediction_checkpointId","width":5},{"name":"entries_3_parent_prediction_confidence","width":2},{"name":"entries_3_parent_prediction_epoch","width":16},{"name":"entries_3_parent_prediction_fallthroughPc","width":64},{"name":"entries_3_parent_prediction_kind","width":3},{"name":"entries_3_parent_prediction_predictionTag","width":64},{"name":"entries_3_parent_prediction_provider","width":4},{"name":"entries_3_parent_prediction_requestPc","width":64},{"name":"entries_3_parent_prediction_taken","width":1},{"name":"entries_3_parent_prediction_target","width":64},{"name":"entries_3_parent_prediction_transactionId","width":64},{"name":"entries_3_parent_prediction_valid","width":1},{"name":"entries_3_templateCount","width":8},{"name":"entries_3_templateImmediate","width":64},{"name":"entries_3_templateOpcode","width":12},{"name":"entries_3_templateOrdinal","width":8},{"name":"entries_4_kind","width":1},{"name":"entries_4_parent_fetchFault","width":1},{"name":"entries_4_parent_fetchFaultCause","width":32},{"name":"entries_4_parent_identity_epoch","width":16},{"name":"entries_4_parent_identity_instructionId","width":64},{"name":"entries_4_parent_identity_peId","width":8},{"name":"entries_4_parent_identity_stid","width":1},{"name":"entries_4_parent_instruction","width":64},{"name":"entries_4_parent_lengthBytes","width":4},{"name":"entries_4_parent_pc","width":64},{"name":"entries_4_parent_prediction_checkpointId","width":5},{"name":"entries_4_parent_prediction_confidence","width":2},{"name":"entries_4_parent_prediction_epoch","width":16},{"name":"entries_4_parent_prediction_fallthroughPc","width":64},{"name":"entries_4_parent_prediction_kind","width":3},{"name":"entries_4_parent_prediction_predictionTag","width":64},{"name":"entries_4_parent_prediction_provider","width":4},{"name":"entries_4_parent_prediction_requestPc","width":64},{"name":"entries_4_parent_prediction_taken","width":1},{"name":"entries_4_parent_prediction_target","width":64},{"name":"entries_4_parent_prediction_transactionId","width":64},{"name":"entries_4_parent_prediction_valid","width":1},{"name":"entries_4_templateCount","width":8},{"name":"entries_4_templateImmediate","width":64},{"name":"entries_4_templateOpcode","width":12},{"name":"entries_4_templateOrdinal","width":8},{"name":"entries_5_kind","width":1},{"name":"entries_5_parent_fetchFault","width":1},{"name":"entries_5_parent_fetchFaultCause","width":32},{"name":"entries_5_parent_identity_epoch","width":16},{"name":"entries_5_parent_identity_instructionId","width":64},{"name":"entries_5_parent_identity_peId","width":8},{"name":"entries_5_parent_identity_stid","width":1},{"name":"entries_5_parent_instruction","width":64},{"name":"entries_5_parent_lengthBytes","width":4},{"name":"entries_5_parent_pc","width":64},{"name":"entries_5_parent_prediction_checkpointId","width":5},{"name":"entries_5_parent_prediction_confidence","width":2},{"name":"entries_5_parent_prediction_epoch","width":16},{"name":"entries_5_parent_prediction_fallthroughPc","width":64},{"name":"entries_5_parent_prediction_kind","width":3},{"name":"entries_5_parent_prediction_predictionTag","width":64},{"name":"entries_5_parent_prediction_provider","width":4},{"name":"entries_5_parent_prediction_requestPc","width":64},{"name":"entries_5_parent_prediction_taken","width":1},{"name":"entries_5_parent_prediction_target","width":64},{"name":"entries_5_parent_prediction_transactionId","width":64},{"name":"entries_5_parent_prediction_valid","width":1},{"name":"entries_5_templateCount","width":8},{"name":"entries_5_templateImmediate","width":64},{"name":"entries_5_templateOpcode","width":12},{"name":"entries_5_templateOrdinal","width":8}]},{"name":"ooo_to_iex_alu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_bru","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_agu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_std","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"StoreDispatchTxn","ports":[{"name":"aguPipe","width":1},{"name":"sta_memoryOrder_firstLid","width":32},{"name":"sta_memoryOrder_firstLsid","width":32},{"name":"sta_memoryOrder_firstSid","width":32},{"name":"sta_memoryOrder_requestCount","width":2},{"name":"sta_memoryOrder_yoldLid","width":32},{"name":"sta_memoryOrder_yoldLsid","width":32},{"name":"sta_memoryOrder_yoldValid","width":1},{"name":"sta_memoryOrder_yostLsid","width":32},{"name":"sta_memoryOrder_yostSid","width":32},{"name":"sta_memoryOrder_yostValid","width":1},{"name":"sta_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"sta_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"sta_pcBufferIndexOffset_pcOffset","width":7},{"name":"sta_pcBufferIndexOffset_valid","width":1},{"name":"sta_transactionId","width":64},{"name":"sta_trap_cause","width":32},{"name":"sta_trap_valid","width":1},{"name":"sta_uop_decoded_blockBoundary","width":1},{"name":"sta_uop_decoded_blockStart","width":1},{"name":"sta_uop_decoded_blockStop","width":1},{"name":"sta_uop_decoded_classification_complexBreak","width":1},{"name":"sta_uop_decoded_classification_dispatchClass","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_0","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_1","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_2","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_3","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_4","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_5","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_6","width":3},{"name":"sta_uop_decoded_classification_dispatchDemand_7","width":3},{"name":"sta_uop_decoded_classification_dispatchWrites","width":3},{"name":"sta_uop_decoded_classification_disposition","width":2},{"name":"sta_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"sta_uop_decoded_classification_fastResolveClass","width":3},{"name":"sta_uop_decoded_classification_fusionHeadClass","width":2},{"name":"sta_uop_decoded_classification_fusionTailClass","width":2},{"name":"sta_uop_decoded_classification_implicitDestination","width":2},{"name":"sta_uop_decoded_classification_implicitSourceMask","width":4},{"name":"sta_uop_decoded_classification_kind","width":4},{"name":"sta_uop_decoded_classification_mayRedirect","width":1},{"name":"sta_uop_decoded_classification_mayTrap","width":1},{"name":"sta_uop_decoded_classification_mayTrapLate","width":1},{"name":"sta_uop_decoded_classification_memoryRequestCount","width":2},{"name":"sta_uop_decoded_classification_nonspeculative","width":1},{"name":"sta_uop_decoded_classification_pDestinationCount","width":2},{"name":"sta_uop_decoded_classification_pSourceCount","width":3},{"name":"sta_uop_decoded_classification_pcReadClass","width":4},{"name":"sta_uop_decoded_classification_pcReadRequired","width":1},{"name":"sta_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"sta_uop_decoded_classification_sideEffectOwner","width":3},{"name":"sta_uop_decoded_classification_splitKind","width":2},{"name":"sta_uop_decoded_classification_tAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uopCountMax","width":6},{"name":"sta_uop_decoded_classification_uopCountMin","width":6},{"name":"sta_uop_decoded_classification_valid","width":1},{"name":"sta_uop_decoded_destinations_0_atag","width":6},{"name":"sta_uop_decoded_destinations_0_kind","width":3},{"name":"sta_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_0_valid","width":1},{"name":"sta_uop_decoded_destinations_1_atag","width":6},{"name":"sta_uop_decoded_destinations_1_kind","width":3},{"name":"sta_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_1_valid","width":1},{"name":"sta_uop_decoded_earlyComplete","width":1},{"name":"sta_uop_decoded_immediate","width":64},{"name":"sta_uop_decoded_immediateValid","width":1},{"name":"sta_uop_decoded_instruction_kind","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"sta_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"sta_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"sta_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"sta_uop_decoded_instruction_parent_instruction","width":64},{"name":"sta_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"sta_uop_decoded_instruction_parent_pc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"sta_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"sta_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"sta_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"sta_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"sta_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"sta_uop_decoded_instruction_templateCount","width":8},{"name":"sta_uop_decoded_instruction_templateImmediate","width":64},{"name":"sta_uop_decoded_instruction_templateOpcode","width":12},{"name":"sta_uop_decoded_instruction_templateOrdinal","width":8},{"name":"sta_uop_decoded_memory_accessBytes","width":4},{"name":"sta_uop_decoded_memory_addressMode","width":2},{"name":"sta_uop_decoded_memory_addressSourceMask","width":4},{"name":"sta_uop_decoded_memory_dataSourceMask","width":4},{"name":"sta_uop_decoded_memory_indexMode","width":2},{"name":"sta_uop_decoded_memory_indexShift","width":5},{"name":"sta_uop_decoded_memory_isLoad","width":1},{"name":"sta_uop_decoded_memory_isStore","width":1},{"name":"sta_uop_decoded_memory_offset","width":64},{"name":"sta_uop_decoded_memory_requestCount","width":2},{"name":"sta_uop_decoded_memory_signExtend","width":1},{"name":"sta_uop_decoded_memory_valid","width":1},{"name":"sta_uop_decoded_memory_writebackPreIndex","width":1},{"name":"sta_uop_decoded_memory_writebackValid","width":1},{"name":"sta_uop_decoded_opcode","width":12},{"name":"sta_uop_decoded_rob_bid","width":8},{"name":"sta_uop_decoded_rob_brobGeneration","width":16},{"name":"sta_uop_decoded_rob_memberIndex","width":2},{"name":"sta_uop_decoded_rob_peId","width":8},{"name":"sta_uop_decoded_rob_residentGeneration","width":16},{"name":"sta_uop_decoded_rob_ridGeneration","width":16},{"name":"sta_uop_decoded_rob_ridSlot","width":6},{"name":"sta_uop_decoded_rob_stid","width":1},{"name":"sta_uop_decoded_sources_0_atag","width":6},{"name":"sta_uop_decoded_sources_0_kind","width":3},{"name":"sta_uop_decoded_sources_0_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_0_valid","width":1},{"name":"sta_uop_decoded_sources_1_atag","width":6},{"name":"sta_uop_decoded_sources_1_kind","width":3},{"name":"sta_uop_decoded_sources_1_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_1_valid","width":1},{"name":"sta_uop_decoded_sources_2_atag","width":6},{"name":"sta_uop_decoded_sources_2_kind","width":3},{"name":"sta_uop_decoded_sources_2_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_2_valid","width":1},{"name":"sta_uop_decoded_sources_3_atag","width":6},{"name":"sta_uop_decoded_sources_3_kind","width":3},{"name":"sta_uop_decoded_sources_3_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_3_valid","width":1},{"name":"sta_uop_decoded_uopClass","width":3},{"name":"sta_uop_decoded_valid","width":1},{"name":"sta_uop_destinations_0_atag","width":6},{"name":"sta_uop_destinations_0_kind","width":3},{"name":"sta_uop_destinations_0_pGeneration","width":16},{"name":"sta_uop_destinations_0_previousPGeneration","width":16},{"name":"sta_uop_destinations_0_previousPtag","width":7},{"name":"sta_uop_destinations_0_previousPtagValid","width":1},{"name":"sta_uop_destinations_0_previousTtag","width":5},{"name":"sta_uop_destinations_0_previousTtagValid","width":1},{"name":"sta_uop_destinations_0_previousUtag","width":5},{"name":"sta_uop_destinations_0_previousUtagValid","width":1},{"name":"sta_uop_destinations_0_ptag","width":7},{"name":"sta_uop_destinations_0_ptagValid","width":1},{"name":"sta_uop_destinations_0_tGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqIndex","width":5},{"name":"sta_uop_destinations_0_ttag","width":5},{"name":"sta_uop_destinations_0_ttagValid","width":1},{"name":"sta_uop_destinations_0_uGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqIndex","width":5},{"name":"sta_uop_destinations_0_utag","width":5},{"name":"sta_uop_destinations_0_utagValid","width":1},{"name":"sta_uop_destinations_0_valid","width":1},{"name":"sta_uop_destinations_1_atag","width":6},{"name":"sta_uop_destinations_1_kind","width":3},{"name":"sta_uop_destinations_1_pGeneration","width":16},{"name":"sta_uop_destinations_1_previousPGeneration","width":16},{"name":"sta_uop_destinations_1_previousPtag","width":7},{"name":"sta_uop_destinations_1_previousPtagValid","width":1},{"name":"sta_uop_destinations_1_previousTtag","width":5},{"name":"sta_uop_destinations_1_previousTtagValid","width":1},{"name":"sta_uop_destinations_1_previousUtag","width":5},{"name":"sta_uop_destinations_1_previousUtagValid","width":1},{"name":"sta_uop_destinations_1_ptag","width":7},{"name":"sta_uop_destinations_1_ptagValid","width":1},{"name":"sta_uop_destinations_1_tGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqIndex","width":5},{"name":"sta_uop_destinations_1_ttag","width":5},{"name":"sta_uop_destinations_1_ttagValid","width":1},{"name":"sta_uop_destinations_1_uGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqIndex","width":5},{"name":"sta_uop_destinations_1_utag","width":5},{"name":"sta_uop_destinations_1_utagValid","width":1},{"name":"sta_uop_destinations_1_valid","width":1},{"name":"sta_uop_sources_0_atag","width":6},{"name":"sta_uop_sources_0_kind","width":3},{"name":"sta_uop_sources_0_pGeneration","width":16},{"name":"sta_uop_sources_0_ptag","width":7},{"name":"sta_uop_sources_0_ptagValid","width":1},{"name":"sta_uop_sources_0_ready","width":1},{"name":"sta_uop_sources_0_tGeneration","width":16},{"name":"sta_uop_sources_0_tSeqGeneration","width":16},{"name":"sta_uop_sources_0_tSeqIndex","width":5},{"name":"sta_uop_sources_0_ttag","width":5},{"name":"sta_uop_sources_0_ttagValid","width":1},{"name":"sta_uop_sources_0_uGeneration","width":16},{"name":"sta_uop_sources_0_uSeqGeneration","width":16},{"name":"sta_uop_sources_0_uSeqIndex","width":5},{"name":"sta_uop_sources_0_utag","width":5},{"name":"sta_uop_sources_0_utagValid","width":1},{"name":"sta_uop_sources_0_valid","width":1},{"name":"sta_uop_sources_1_atag","width":6},{"name":"sta_uop_sources_1_kind","width":3},{"name":"sta_uop_sources_1_pGeneration","width":16},{"name":"sta_uop_sources_1_ptag","width":7},{"name":"sta_uop_sources_1_ptagValid","width":1},{"name":"sta_uop_sources_1_ready","width":1},{"name":"sta_uop_sources_1_tGeneration","width":16},{"name":"sta_uop_sources_1_tSeqGeneration","width":16},{"name":"sta_uop_sources_1_tSeqIndex","width":5},{"name":"sta_uop_sources_1_ttag","width":5},{"name":"sta_uop_sources_1_ttagValid","width":1},{"name":"sta_uop_sources_1_uGeneration","width":16},{"name":"sta_uop_sources_1_uSeqGeneration","width":16},{"name":"sta_uop_sources_1_uSeqIndex","width":5},{"name":"sta_uop_sources_1_utag","width":5},{"name":"sta_uop_sources_1_utagValid","width":1},{"name":"sta_uop_sources_1_valid","width":1},{"name":"sta_uop_sources_2_atag","width":6},{"name":"sta_uop_sources_2_kind","width":3},{"name":"sta_uop_sources_2_pGeneration","width":16},{"name":"sta_uop_sources_2_ptag","width":7},{"name":"sta_uop_sources_2_ptagValid","width":1},{"name":"sta_uop_sources_2_ready","width":1},{"name":"sta_uop_sources_2_tGeneration","width":16},{"name":"sta_uop_sources_2_tSeqGeneration","width":16},{"name":"sta_uop_sources_2_tSeqIndex","width":5},{"name":"sta_uop_sources_2_ttag","width":5},{"name":"sta_uop_sources_2_ttagValid","width":1},{"name":"sta_uop_sources_2_uGeneration","width":16},{"name":"sta_uop_sources_2_uSeqGeneration","width":16},{"name":"sta_uop_sources_2_uSeqIndex","width":5},{"name":"sta_uop_sources_2_utag","width":5},{"name":"sta_uop_sources_2_utagValid","width":1},{"name":"sta_uop_sources_2_valid","width":1},{"name":"sta_uop_sources_3_atag","width":6},{"name":"sta_uop_sources_3_kind","width":3},{"name":"sta_uop_sources_3_pGeneration","width":16},{"name":"sta_uop_sources_3_ptag","width":7},{"name":"sta_uop_sources_3_ptagValid","width":1},{"name":"sta_uop_sources_3_ready","width":1},{"name":"sta_uop_sources_3_tGeneration","width":16},{"name":"sta_uop_sources_3_tSeqGeneration","width":16},{"name":"sta_uop_sources_3_tSeqIndex","width":5},{"name":"sta_uop_sources_3_ttag","width":5},{"name":"sta_uop_sources_3_ttagValid","width":1},{"name":"sta_uop_sources_3_uGeneration","width":16},{"name":"sta_uop_sources_3_uSeqGeneration","width":16},{"name":"sta_uop_sources_3_uSeqIndex","width":5},{"name":"sta_uop_sources_3_utag","width":5},{"name":"sta_uop_sources_3_utagValid","width":1},{"name":"sta_uop_sources_3_valid","width":1},{"name":"std_memoryOrder_firstLid","width":32},{"name":"std_memoryOrder_firstLsid","width":32},{"name":"std_memoryOrder_firstSid","width":32},{"name":"std_memoryOrder_requestCount","width":2},{"name":"std_memoryOrder_yoldLid","width":32},{"name":"std_memoryOrder_yoldLsid","width":32},{"name":"std_memoryOrder_yoldValid","width":1},{"name":"std_memoryOrder_yostLsid","width":32},{"name":"std_memoryOrder_yostSid","width":32},{"name":"std_memoryOrder_yostValid","width":1},{"name":"std_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"std_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"std_pcBufferIndexOffset_pcOffset","width":7},{"name":"std_pcBufferIndexOffset_valid","width":1},{"name":"std_transactionId","width":64},{"name":"std_trap_cause","width":32},{"name":"std_trap_valid","width":1},{"name":"std_uop_decoded_blockBoundary","width":1},{"name":"std_uop_decoded_blockStart","width":1},{"name":"std_uop_decoded_blockStop","width":1},{"name":"std_uop_decoded_classification_complexBreak","width":1},{"name":"std_uop_decoded_classification_dispatchClass","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_0","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_1","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_2","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_3","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_4","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_5","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_6","width":3},{"name":"std_uop_decoded_classification_dispatchDemand_7","width":3},{"name":"std_uop_decoded_classification_dispatchWrites","width":3},{"name":"std_uop_decoded_classification_disposition","width":2},{"name":"std_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"std_uop_decoded_classification_fastResolveClass","width":3},{"name":"std_uop_decoded_classification_fusionHeadClass","width":2},{"name":"std_uop_decoded_classification_fusionTailClass","width":2},{"name":"std_uop_decoded_classification_implicitDestination","width":2},{"name":"std_uop_decoded_classification_implicitSourceMask","width":4},{"name":"std_uop_decoded_classification_kind","width":4},{"name":"std_uop_decoded_classification_mayRedirect","width":1},{"name":"std_uop_decoded_classification_mayTrap","width":1},{"name":"std_uop_decoded_classification_mayTrapLate","width":1},{"name":"std_uop_decoded_classification_memoryRequestCount","width":2},{"name":"std_uop_decoded_classification_nonspeculative","width":1},{"name":"std_uop_decoded_classification_pDestinationCount","width":2},{"name":"std_uop_decoded_classification_pSourceCount","width":3},{"name":"std_uop_decoded_classification_pcReadClass","width":4},{"name":"std_uop_decoded_classification_pcReadRequired","width":1},{"name":"std_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"std_uop_decoded_classification_sideEffectOwner","width":3},{"name":"std_uop_decoded_classification_splitKind","width":2},{"name":"std_uop_decoded_classification_tAllocationCount","width":2},{"name":"std_uop_decoded_classification_uAllocationCount","width":2},{"name":"std_uop_decoded_classification_uopCountMax","width":6},{"name":"std_uop_decoded_classification_uopCountMin","width":6},{"name":"std_uop_decoded_classification_valid","width":1},{"name":"std_uop_decoded_destinations_0_atag","width":6},{"name":"std_uop_decoded_destinations_0_kind","width":3},{"name":"std_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_0_valid","width":1},{"name":"std_uop_decoded_destinations_1_atag","width":6},{"name":"std_uop_decoded_destinations_1_kind","width":3},{"name":"std_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_1_valid","width":1},{"name":"std_uop_decoded_earlyComplete","width":1},{"name":"std_uop_decoded_immediate","width":64},{"name":"std_uop_decoded_immediateValid","width":1},{"name":"std_uop_decoded_instruction_kind","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"std_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"std_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"std_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"std_uop_decoded_instruction_parent_instruction","width":64},{"name":"std_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"std_uop_decoded_instruction_parent_pc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"std_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"std_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"std_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"std_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"std_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"std_uop_decoded_instruction_templateCount","width":8},{"name":"std_uop_decoded_instruction_templateImmediate","width":64},{"name":"std_uop_decoded_instruction_templateOpcode","width":12},{"name":"std_uop_decoded_instruction_templateOrdinal","width":8},{"name":"std_uop_decoded_memory_accessBytes","width":4},{"name":"std_uop_decoded_memory_addressMode","width":2},{"name":"std_uop_decoded_memory_addressSourceMask","width":4},{"name":"std_uop_decoded_memory_dataSourceMask","width":4},{"name":"std_uop_decoded_memory_indexMode","width":2},{"name":"std_uop_decoded_memory_indexShift","width":5},{"name":"std_uop_decoded_memory_isLoad","width":1},{"name":"std_uop_decoded_memory_isStore","width":1},{"name":"std_uop_decoded_memory_offset","width":64},{"name":"std_uop_decoded_memory_requestCount","width":2},{"name":"std_uop_decoded_memory_signExtend","width":1},{"name":"std_uop_decoded_memory_valid","width":1},{"name":"std_uop_decoded_memory_writebackPreIndex","width":1},{"name":"std_uop_decoded_memory_writebackValid","width":1},{"name":"std_uop_decoded_opcode","width":12},{"name":"std_uop_decoded_rob_bid","width":8},{"name":"std_uop_decoded_rob_brobGeneration","width":16},{"name":"std_uop_decoded_rob_memberIndex","width":2},{"name":"std_uop_decoded_rob_peId","width":8},{"name":"std_uop_decoded_rob_residentGeneration","width":16},{"name":"std_uop_decoded_rob_ridGeneration","width":16},{"name":"std_uop_decoded_rob_ridSlot","width":6},{"name":"std_uop_decoded_rob_stid","width":1},{"name":"std_uop_decoded_sources_0_atag","width":6},{"name":"std_uop_decoded_sources_0_kind","width":3},{"name":"std_uop_decoded_sources_0_relativeIndex","width":6},{"name":"std_uop_decoded_sources_0_valid","width":1},{"name":"std_uop_decoded_sources_1_atag","width":6},{"name":"std_uop_decoded_sources_1_kind","width":3},{"name":"std_uop_decoded_sources_1_relativeIndex","width":6},{"name":"std_uop_decoded_sources_1_valid","width":1},{"name":"std_uop_decoded_sources_2_atag","width":6},{"name":"std_uop_decoded_sources_2_kind","width":3},{"name":"std_uop_decoded_sources_2_relativeIndex","width":6},{"name":"std_uop_decoded_sources_2_valid","width":1},{"name":"std_uop_decoded_sources_3_atag","width":6},{"name":"std_uop_decoded_sources_3_kind","width":3},{"name":"std_uop_decoded_sources_3_relativeIndex","width":6},{"name":"std_uop_decoded_sources_3_valid","width":1},{"name":"std_uop_decoded_uopClass","width":3},{"name":"std_uop_decoded_valid","width":1},{"name":"std_uop_destinations_0_atag","width":6},{"name":"std_uop_destinations_0_kind","width":3},{"name":"std_uop_destinations_0_pGeneration","width":16},{"name":"std_uop_destinations_0_previousPGeneration","width":16},{"name":"std_uop_destinations_0_previousPtag","width":7},{"name":"std_uop_destinations_0_previousPtagValid","width":1},{"name":"std_uop_destinations_0_previousTtag","width":5},{"name":"std_uop_destinations_0_previousTtagValid","width":1},{"name":"std_uop_destinations_0_previousUtag","width":5},{"name":"std_uop_destinations_0_previousUtagValid","width":1},{"name":"std_uop_destinations_0_ptag","width":7},{"name":"std_uop_destinations_0_ptagValid","width":1},{"name":"std_uop_destinations_0_tGeneration","width":16},{"name":"std_uop_destinations_0_tSeqGeneration","width":16},{"name":"std_uop_destinations_0_tSeqIndex","width":5},{"name":"std_uop_destinations_0_ttag","width":5},{"name":"std_uop_destinations_0_ttagValid","width":1},{"name":"std_uop_destinations_0_uGeneration","width":16},{"name":"std_uop_destinations_0_uSeqGeneration","width":16},{"name":"std_uop_destinations_0_uSeqIndex","width":5},{"name":"std_uop_destinations_0_utag","width":5},{"name":"std_uop_destinations_0_utagValid","width":1},{"name":"std_uop_destinations_0_valid","width":1},{"name":"std_uop_destinations_1_atag","width":6},{"name":"std_uop_destinations_1_kind","width":3},{"name":"std_uop_destinations_1_pGeneration","width":16},{"name":"std_uop_destinations_1_previousPGeneration","width":16},{"name":"std_uop_destinations_1_previousPtag","width":7},{"name":"std_uop_destinations_1_previousPtagValid","width":1},{"name":"std_uop_destinations_1_previousTtag","width":5},{"name":"std_uop_destinations_1_previousTtagValid","width":1},{"name":"std_uop_destinations_1_previousUtag","width":5},{"name":"std_uop_destinations_1_previousUtagValid","width":1},{"name":"std_uop_destinations_1_ptag","width":7},{"name":"std_uop_destinations_1_ptagValid","width":1},{"name":"std_uop_destinations_1_tGeneration","width":16},{"name":"std_uop_destinations_1_tSeqGeneration","width":16},{"name":"std_uop_destinations_1_tSeqIndex","width":5},{"name":"std_uop_destinations_1_ttag","width":5},{"name":"std_uop_destinations_1_ttagValid","width":1},{"name":"std_uop_destinations_1_uGeneration","width":16},{"name":"std_uop_destinations_1_uSeqGeneration","width":16},{"name":"std_uop_destinations_1_uSeqIndex","width":5},{"name":"std_uop_destinations_1_utag","width":5},{"name":"std_uop_destinations_1_utagValid","width":1},{"name":"std_uop_destinations_1_valid","width":1},{"name":"std_uop_sources_0_atag","width":6},{"name":"std_uop_sources_0_kind","width":3},{"name":"std_uop_sources_0_pGeneration","width":16},{"name":"std_uop_sources_0_ptag","width":7},{"name":"std_uop_sources_0_ptagValid","width":1},{"name":"std_uop_sources_0_ready","width":1},{"name":"std_uop_sources_0_tGeneration","width":16},{"name":"std_uop_sources_0_tSeqGeneration","width":16},{"name":"std_uop_sources_0_tSeqIndex","width":5},{"name":"std_uop_sources_0_ttag","width":5},{"name":"std_uop_sources_0_ttagValid","width":1},{"name":"std_uop_sources_0_uGeneration","width":16},{"name":"std_uop_sources_0_uSeqGeneration","width":16},{"name":"std_uop_sources_0_uSeqIndex","width":5},{"name":"std_uop_sources_0_utag","width":5},{"name":"std_uop_sources_0_utagValid","width":1},{"name":"std_uop_sources_0_valid","width":1},{"name":"std_uop_sources_1_atag","width":6},{"name":"std_uop_sources_1_kind","width":3},{"name":"std_uop_sources_1_pGeneration","width":16},{"name":"std_uop_sources_1_ptag","width":7},{"name":"std_uop_sources_1_ptagValid","width":1},{"name":"std_uop_sources_1_ready","width":1},{"name":"std_uop_sources_1_tGeneration","width":16},{"name":"std_uop_sources_1_tSeqGeneration","width":16},{"name":"std_uop_sources_1_tSeqIndex","width":5},{"name":"std_uop_sources_1_ttag","width":5},{"name":"std_uop_sources_1_ttagValid","width":1},{"name":"std_uop_sources_1_uGeneration","width":16},{"name":"std_uop_sources_1_uSeqGeneration","width":16},{"name":"std_uop_sources_1_uSeqIndex","width":5},{"name":"std_uop_sources_1_utag","width":5},{"name":"std_uop_sources_1_utagValid","width":1},{"name":"std_uop_sources_1_valid","width":1},{"name":"std_uop_sources_2_atag","width":6},{"name":"std_uop_sources_2_kind","width":3},{"name":"std_uop_sources_2_pGeneration","width":16},{"name":"std_uop_sources_2_ptag","width":7},{"name":"std_uop_sources_2_ptagValid","width":1},{"name":"std_uop_sources_2_ready","width":1},{"name":"std_uop_sources_2_tGeneration","width":16},{"name":"std_uop_sources_2_tSeqGeneration","width":16},{"name":"std_uop_sources_2_tSeqIndex","width":5},{"name":"std_uop_sources_2_ttag","width":5},{"name":"std_uop_sources_2_ttagValid","width":1},{"name":"std_uop_sources_2_uGeneration","width":16},{"name":"std_uop_sources_2_uSeqGeneration","width":16},{"name":"std_uop_sources_2_uSeqIndex","width":5},{"name":"std_uop_sources_2_utag","width":5},{"name":"std_uop_sources_2_utagValid","width":1},{"name":"std_uop_sources_2_valid","width":1},{"name":"std_uop_sources_3_atag","width":6},{"name":"std_uop_sources_3_kind","width":3},{"name":"std_uop_sources_3_pGeneration","width":16},{"name":"std_uop_sources_3_ptag","width":7},{"name":"std_uop_sources_3_ptagValid","width":1},{"name":"std_uop_sources_3_ready","width":1},{"name":"std_uop_sources_3_tGeneration","width":16},{"name":"std_uop_sources_3_tSeqGeneration","width":16},{"name":"std_uop_sources_3_tSeqIndex","width":5},{"name":"std_uop_sources_3_ttag","width":5},{"name":"std_uop_sources_3_ttagValid","width":1},{"name":"std_uop_sources_3_uGeneration","width":16},{"name":"std_uop_sources_3_uSeqGeneration","width":16},{"name":"std_uop_sources_3_uSeqIndex","width":5},{"name":"std_uop_sources_3_utag","width":5},{"name":"std_uop_sources_3_utagValid","width":1},{"name":"std_uop_sources_3_valid","width":1},{"name":"stdPipe","width":1}]},{"name":"ooo_to_iex_system","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_cmd","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":3},{"name":"uop_decoded_classification_dispatchDemand_1","width":3},{"name":"uop_decoded_classification_dispatchDemand_2","width":3},{"name":"uop_decoded_classification_dispatchDemand_3","width":3},{"name":"uop_decoded_classification_dispatchDemand_4","width":3},{"name":"uop_decoded_classification_dispatchDemand_5","width":3},{"name":"uop_decoded_classification_dispatchDemand_6","width":3},{"name":"uop_decoded_classification_dispatchDemand_7","width":3},{"name":"uop_decoded_classification_dispatchWrites","width":3},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_rob_noflush","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"RobNoflushTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_noflush_ready","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"RobNoflushReadyTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_resolve","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":6,"payload":"RobResolveTxn","ports":[{"name":"destinationIndex","width":1},{"name":"destinationValid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"value","width":64}]},{"name":"iex_to_ooo_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_top_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"TOP","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_pc_buffer_read_address","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":6,"payload":"PcBufferReadAddress","ports":[{"name":"allocationEpoch","width":16},{"name":"pcBufferIndex","width":6},{"name":"stid","width":1},{"name":"valid","width":1}]},{"name":"ooo_to_iex_pc_buffer_read_pc_base","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":6,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"iex_to_lsu_load_issue","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"LoadIssueTxn","ports":[{"name":"address","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"pc","width":64},{"name":"signed","width":1},{"name":"sizeBytes","width":4},{"name":"youngestStoreId","width":32},{"name":"youngestStoreLsid","width":32},{"name":"youngestStoreValid","width":1}]},{"name":"lsu_to_iex_load_allocation_preview","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadAllocationPreview","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_launch","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadLaunchTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"iex_to_lsu_store_reservation","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreReservationTxn","ports":[{"name":"aguPipe","width":1},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sizeBytes","width":4},{"name":"stdPipe","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64},{"name":"transactionId","width":64}]},{"name":"iex_to_lsu_store_address","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreAddressTxn","ports":[{"name":"address","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"iex_to_lsu_store_data","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreDataTxn","ports":[{"name":"byteMask_0","width":8},{"name":"byteMask_1","width":8},{"name":"data_0","width":64},{"name":"data_1","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"lsu_to_iex_load_result","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadResultTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"data","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1}]},{"name":"lsu_to_iex_load_reissue","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadReissueTxn","ports":[{"name":"address","width":64},{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_repick","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadRepickTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_cancel","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadCancelTxn","ports":[{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64}]},{"name":"ooo_to_lsu_store_commit","contract_id":"IFC-IEX-LSU-001","producer":"OOO","consumer":"LSU","lanes":1,"payload":"StoreCommitAuthorizationTxn","ports":[{"name":"beat","width":1},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"lsu_internal_store_classify","contract_id":"IFC-IEX-LSU-001","producer":"LSU Translation","consumer":"LSU Commit Backend","lanes":1,"payload":"StoreMemoryClassifyTxn","ports":[{"name":"beat","width":1},{"name":"faultCause","width":32},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"memoryClass","width":2},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"external_cmd_issue","contract_id":"IFC-TOP-EXT-001","producer":"IEX","consumer":"External CMD","lanes":1,"payload":"CmdIssueTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sourceValid","width":4},{"name":"sourceValues_0","width":64},{"name":"sourceValues_1","width":64},{"name":"sourceValues_2","width":64},{"name":"sourceValues_3","width":64},{"name":"transactionId","width":64}]},{"name":"owner_to_ooo_recovery_event","contract_id":"IFC-RECOVERY-001","producer":"IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryEvent","ports":[{"name":"cause","width":3},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"redirectPc","width":64},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_prepare","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"target_to_ooo_recovery_prepared","contract_id":"IFC-RECOVERY-001","producer":"IFU/CTU/IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_apply","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_abort","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_commit","contract_id":"IFC-COMMIT-001","producer":"OOO","consumer":"TOP/DTU","lanes":6,"payload":"CommitTxn","ports":[{"name":"count","width":3},{"name":"entries_0_destination_atag","width":6},{"name":"entries_0_destination_kind","width":3},{"name":"entries_0_destination_pGeneration","width":16},{"name":"entries_0_destination_previousPGeneration","width":16},{"name":"entries_0_destination_previousPtag","width":7},{"name":"entries_0_destination_previousPtagValid","width":1},{"name":"entries_0_destination_previousTtag","width":5},{"name":"entries_0_destination_previousTtagValid","width":1},{"name":"entries_0_destination_previousUtag","width":5},{"name":"entries_0_destination_previousUtagValid","width":1},{"name":"entries_0_destination_ptag","width":7},{"name":"entries_0_destination_ptagValid","width":1},{"name":"entries_0_destination_tGeneration","width":16},{"name":"entries_0_destination_tSeqGeneration","width":16},{"name":"entries_0_destination_tSeqIndex","width":5},{"name":"entries_0_destination_ttag","width":5},{"name":"entries_0_destination_ttagValid","width":1},{"name":"entries_0_destination_uGeneration","width":16},{"name":"entries_0_destination_uSeqGeneration","width":16},{"name":"entries_0_destination_uSeqIndex","width":5},{"name":"entries_0_destination_utag","width":5},{"name":"entries_0_destination_utagValid","width":1},{"name":"entries_0_destination_valid","width":1},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionBits","width":64},{"name":"entries_0_instructionLengthBytes","width":4},{"name":"entries_0_memory_attemptGeneration","width":16},{"name":"entries_0_memory_lsid","width":32},{"name":"entries_0_memory_pipeId","width":1},{"name":"entries_0_memory_rob_bid","width":8},{"name":"entries_0_memory_rob_brobGeneration","width":16},{"name":"entries_0_memory_rob_memberIndex","width":2},{"name":"entries_0_memory_rob_peId","width":8},{"name":"entries_0_memory_rob_residentGeneration","width":16},{"name":"entries_0_memory_rob_ridGeneration","width":16},{"name":"entries_0_memory_rob_ridSlot","width":6},{"name":"entries_0_memory_rob_stid","width":1},{"name":"entries_0_memory_transaction_generation","width":16},{"name":"entries_0_memory_transaction_value","width":64},{"name":"entries_0_memoryOrder_firstLid","width":32},{"name":"entries_0_memoryOrder_firstLsid","width":32},{"name":"entries_0_memoryOrder_firstSid","width":32},{"name":"entries_0_memoryOrder_requestCount","width":2},{"name":"entries_0_memoryOrder_yoldLid","width":32},{"name":"entries_0_memoryOrder_yoldLsid","width":32},{"name":"entries_0_memoryOrder_yoldValid","width":1},{"name":"entries_0_memoryOrder_yostLsid","width":32},{"name":"entries_0_memoryOrder_yostSid","width":32},{"name":"entries_0_memoryOrder_yostValid","width":1},{"name":"entries_0_memoryStore","width":1},{"name":"entries_0_memoryValid","width":1},{"name":"entries_0_opcode","width":12},{"name":"entries_0_pc","width":64},{"name":"entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_0_pcBufferIndexOffset_valid","width":1},{"name":"entries_0_result","width":64},{"name":"entries_0_resultValid","width":1},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robGroupLast","width":1},{"name":"entries_0_storeData","width":64},{"name":"entries_0_storeMask","width":8},{"name":"entries_0_trap_cause","width":32},{"name":"entries_0_trap_instruction_epoch","width":16},{"name":"entries_0_trap_instruction_instructionId","width":64},{"name":"entries_0_trap_instruction_peId","width":8},{"name":"entries_0_trap_instruction_stid","width":1},{"name":"entries_0_trap_kind","width":2},{"name":"entries_0_trap_rob_bid","width":8},{"name":"entries_0_trap_rob_brobGeneration","width":16},{"name":"entries_0_trap_rob_memberIndex","width":2},{"name":"entries_0_trap_rob_peId","width":8},{"name":"entries_0_trap_rob_residentGeneration","width":16},{"name":"entries_0_trap_rob_ridGeneration","width":16},{"name":"entries_0_trap_rob_ridSlot","width":6},{"name":"entries_0_trap_rob_stid","width":1},{"name":"entries_0_trap_targetPc","width":64},{"name":"entries_0_trap_tval","width":64},{"name":"entries_0_trap_valid","width":1},{"name":"entries_1_destination_atag","width":6},{"name":"entries_1_destination_kind","width":3},{"name":"entries_1_destination_pGeneration","width":16},{"name":"entries_1_destination_previousPGeneration","width":16},{"name":"entries_1_destination_previousPtag","width":7},{"name":"entries_1_destination_previousPtagValid","width":1},{"name":"entries_1_destination_previousTtag","width":5},{"name":"entries_1_destination_previousTtagValid","width":1},{"name":"entries_1_destination_previousUtag","width":5},{"name":"entries_1_destination_previousUtagValid","width":1},{"name":"entries_1_destination_ptag","width":7},{"name":"entries_1_destination_ptagValid","width":1},{"name":"entries_1_destination_tGeneration","width":16},{"name":"entries_1_destination_tSeqGeneration","width":16},{"name":"entries_1_destination_tSeqIndex","width":5},{"name":"entries_1_destination_ttag","width":5},{"name":"entries_1_destination_ttagValid","width":1},{"name":"entries_1_destination_uGeneration","width":16},{"name":"entries_1_destination_uSeqGeneration","width":16},{"name":"entries_1_destination_uSeqIndex","width":5},{"name":"entries_1_destination_utag","width":5},{"name":"entries_1_destination_utagValid","width":1},{"name":"entries_1_destination_valid","width":1},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionBits","width":64},{"name":"entries_1_instructionLengthBytes","width":4},{"name":"entries_1_memory_attemptGeneration","width":16},{"name":"entries_1_memory_lsid","width":32},{"name":"entries_1_memory_pipeId","width":1},{"name":"entries_1_memory_rob_bid","width":8},{"name":"entries_1_memory_rob_brobGeneration","width":16},{"name":"entries_1_memory_rob_memberIndex","width":2},{"name":"entries_1_memory_rob_peId","width":8},{"name":"entries_1_memory_rob_residentGeneration","width":16},{"name":"entries_1_memory_rob_ridGeneration","width":16},{"name":"entries_1_memory_rob_ridSlot","width":6},{"name":"entries_1_memory_rob_stid","width":1},{"name":"entries_1_memory_transaction_generation","width":16},{"name":"entries_1_memory_transaction_value","width":64},{"name":"entries_1_memoryOrder_firstLid","width":32},{"name":"entries_1_memoryOrder_firstLsid","width":32},{"name":"entries_1_memoryOrder_firstSid","width":32},{"name":"entries_1_memoryOrder_requestCount","width":2},{"name":"entries_1_memoryOrder_yoldLid","width":32},{"name":"entries_1_memoryOrder_yoldLsid","width":32},{"name":"entries_1_memoryOrder_yoldValid","width":1},{"name":"entries_1_memoryOrder_yostLsid","width":32},{"name":"entries_1_memoryOrder_yostSid","width":32},{"name":"entries_1_memoryOrder_yostValid","width":1},{"name":"entries_1_memoryStore","width":1},{"name":"entries_1_memoryValid","width":1},{"name":"entries_1_opcode","width":12},{"name":"entries_1_pc","width":64},{"name":"entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_1_pcBufferIndexOffset_valid","width":1},{"name":"entries_1_result","width":64},{"name":"entries_1_resultValid","width":1},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robGroupLast","width":1},{"name":"entries_1_storeData","width":64},{"name":"entries_1_storeMask","width":8},{"name":"entries_1_trap_cause","width":32},{"name":"entries_1_trap_instruction_epoch","width":16},{"name":"entries_1_trap_instruction_instructionId","width":64},{"name":"entries_1_trap_instruction_peId","width":8},{"name":"entries_1_trap_instruction_stid","width":1},{"name":"entries_1_trap_kind","width":2},{"name":"entries_1_trap_rob_bid","width":8},{"name":"entries_1_trap_rob_brobGeneration","width":16},{"name":"entries_1_trap_rob_memberIndex","width":2},{"name":"entries_1_trap_rob_peId","width":8},{"name":"entries_1_trap_rob_residentGeneration","width":16},{"name":"entries_1_trap_rob_ridGeneration","width":16},{"name":"entries_1_trap_rob_ridSlot","width":6},{"name":"entries_1_trap_rob_stid","width":1},{"name":"entries_1_trap_targetPc","width":64},{"name":"entries_1_trap_tval","width":64},{"name":"entries_1_trap_valid","width":1},{"name":"entries_2_destination_atag","width":6},{"name":"entries_2_destination_kind","width":3},{"name":"entries_2_destination_pGeneration","width":16},{"name":"entries_2_destination_previousPGeneration","width":16},{"name":"entries_2_destination_previousPtag","width":7},{"name":"entries_2_destination_previousPtagValid","width":1},{"name":"entries_2_destination_previousTtag","width":5},{"name":"entries_2_destination_previousTtagValid","width":1},{"name":"entries_2_destination_previousUtag","width":5},{"name":"entries_2_destination_previousUtagValid","width":1},{"name":"entries_2_destination_ptag","width":7},{"name":"entries_2_destination_ptagValid","width":1},{"name":"entries_2_destination_tGeneration","width":16},{"name":"entries_2_destination_tSeqGeneration","width":16},{"name":"entries_2_destination_tSeqIndex","width":5},{"name":"entries_2_destination_ttag","width":5},{"name":"entries_2_destination_ttagValid","width":1},{"name":"entries_2_destination_uGeneration","width":16},{"name":"entries_2_destination_uSeqGeneration","width":16},{"name":"entries_2_destination_uSeqIndex","width":5},{"name":"entries_2_destination_utag","width":5},{"name":"entries_2_destination_utagValid","width":1},{"name":"entries_2_destination_valid","width":1},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionBits","width":64},{"name":"entries_2_instructionLengthBytes","width":4},{"name":"entries_2_memory_attemptGeneration","width":16},{"name":"entries_2_memory_lsid","width":32},{"name":"entries_2_memory_pipeId","width":1},{"name":"entries_2_memory_rob_bid","width":8},{"name":"entries_2_memory_rob_brobGeneration","width":16},{"name":"entries_2_memory_rob_memberIndex","width":2},{"name":"entries_2_memory_rob_peId","width":8},{"name":"entries_2_memory_rob_residentGeneration","width":16},{"name":"entries_2_memory_rob_ridGeneration","width":16},{"name":"entries_2_memory_rob_ridSlot","width":6},{"name":"entries_2_memory_rob_stid","width":1},{"name":"entries_2_memory_transaction_generation","width":16},{"name":"entries_2_memory_transaction_value","width":64},{"name":"entries_2_memoryOrder_firstLid","width":32},{"name":"entries_2_memoryOrder_firstLsid","width":32},{"name":"entries_2_memoryOrder_firstSid","width":32},{"name":"entries_2_memoryOrder_requestCount","width":2},{"name":"entries_2_memoryOrder_yoldLid","width":32},{"name":"entries_2_memoryOrder_yoldLsid","width":32},{"name":"entries_2_memoryOrder_yoldValid","width":1},{"name":"entries_2_memoryOrder_yostLsid","width":32},{"name":"entries_2_memoryOrder_yostSid","width":32},{"name":"entries_2_memoryOrder_yostValid","width":1},{"name":"entries_2_memoryStore","width":1},{"name":"entries_2_memoryValid","width":1},{"name":"entries_2_opcode","width":12},{"name":"entries_2_pc","width":64},{"name":"entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_2_pcBufferIndexOffset_valid","width":1},{"name":"entries_2_result","width":64},{"name":"entries_2_resultValid","width":1},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robGroupLast","width":1},{"name":"entries_2_storeData","width":64},{"name":"entries_2_storeMask","width":8},{"name":"entries_2_trap_cause","width":32},{"name":"entries_2_trap_instruction_epoch","width":16},{"name":"entries_2_trap_instruction_instructionId","width":64},{"name":"entries_2_trap_instruction_peId","width":8},{"name":"entries_2_trap_instruction_stid","width":1},{"name":"entries_2_trap_kind","width":2},{"name":"entries_2_trap_rob_bid","width":8},{"name":"entries_2_trap_rob_brobGeneration","width":16},{"name":"entries_2_trap_rob_memberIndex","width":2},{"name":"entries_2_trap_rob_peId","width":8},{"name":"entries_2_trap_rob_residentGeneration","width":16},{"name":"entries_2_trap_rob_ridGeneration","width":16},{"name":"entries_2_trap_rob_ridSlot","width":6},{"name":"entries_2_trap_rob_stid","width":1},{"name":"entries_2_trap_targetPc","width":64},{"name":"entries_2_trap_tval","width":64},{"name":"entries_2_trap_valid","width":1},{"name":"entries_3_destination_atag","width":6},{"name":"entries_3_destination_kind","width":3},{"name":"entries_3_destination_pGeneration","width":16},{"name":"entries_3_destination_previousPGeneration","width":16},{"name":"entries_3_destination_previousPtag","width":7},{"name":"entries_3_destination_previousPtagValid","width":1},{"name":"entries_3_destination_previousTtag","width":5},{"name":"entries_3_destination_previousTtagValid","width":1},{"name":"entries_3_destination_previousUtag","width":5},{"name":"entries_3_destination_previousUtagValid","width":1},{"name":"entries_3_destination_ptag","width":7},{"name":"entries_3_destination_ptagValid","width":1},{"name":"entries_3_destination_tGeneration","width":16},{"name":"entries_3_destination_tSeqGeneration","width":16},{"name":"entries_3_destination_tSeqIndex","width":5},{"name":"entries_3_destination_ttag","width":5},{"name":"entries_3_destination_ttagValid","width":1},{"name":"entries_3_destination_uGeneration","width":16},{"name":"entries_3_destination_uSeqGeneration","width":16},{"name":"entries_3_destination_uSeqIndex","width":5},{"name":"entries_3_destination_utag","width":5},{"name":"entries_3_destination_utagValid","width":1},{"name":"entries_3_destination_valid","width":1},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionBits","width":64},{"name":"entries_3_instructionLengthBytes","width":4},{"name":"entries_3_memory_attemptGeneration","width":16},{"name":"entries_3_memory_lsid","width":32},{"name":"entries_3_memory_pipeId","width":1},{"name":"entries_3_memory_rob_bid","width":8},{"name":"entries_3_memory_rob_brobGeneration","width":16},{"name":"entries_3_memory_rob_memberIndex","width":2},{"name":"entries_3_memory_rob_peId","width":8},{"name":"entries_3_memory_rob_residentGeneration","width":16},{"name":"entries_3_memory_rob_ridGeneration","width":16},{"name":"entries_3_memory_rob_ridSlot","width":6},{"name":"entries_3_memory_rob_stid","width":1},{"name":"entries_3_memory_transaction_generation","width":16},{"name":"entries_3_memory_transaction_value","width":64},{"name":"entries_3_memoryOrder_firstLid","width":32},{"name":"entries_3_memoryOrder_firstLsid","width":32},{"name":"entries_3_memoryOrder_firstSid","width":32},{"name":"entries_3_memoryOrder_requestCount","width":2},{"name":"entries_3_memoryOrder_yoldLid","width":32},{"name":"entries_3_memoryOrder_yoldLsid","width":32},{"name":"entries_3_memoryOrder_yoldValid","width":1},{"name":"entries_3_memoryOrder_yostLsid","width":32},{"name":"entries_3_memoryOrder_yostSid","width":32},{"name":"entries_3_memoryOrder_yostValid","width":1},{"name":"entries_3_memoryStore","width":1},{"name":"entries_3_memoryValid","width":1},{"name":"entries_3_opcode","width":12},{"name":"entries_3_pc","width":64},{"name":"entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_3_pcBufferIndexOffset_valid","width":1},{"name":"entries_3_result","width":64},{"name":"entries_3_resultValid","width":1},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robGroupLast","width":1},{"name":"entries_3_storeData","width":64},{"name":"entries_3_storeMask","width":8},{"name":"entries_3_trap_cause","width":32},{"name":"entries_3_trap_instruction_epoch","width":16},{"name":"entries_3_trap_instruction_instructionId","width":64},{"name":"entries_3_trap_instruction_peId","width":8},{"name":"entries_3_trap_instruction_stid","width":1},{"name":"entries_3_trap_kind","width":2},{"name":"entries_3_trap_rob_bid","width":8},{"name":"entries_3_trap_rob_brobGeneration","width":16},{"name":"entries_3_trap_rob_memberIndex","width":2},{"name":"entries_3_trap_rob_peId","width":8},{"name":"entries_3_trap_rob_residentGeneration","width":16},{"name":"entries_3_trap_rob_ridGeneration","width":16},{"name":"entries_3_trap_rob_ridSlot","width":6},{"name":"entries_3_trap_rob_stid","width":1},{"name":"entries_3_trap_targetPc","width":64},{"name":"entries_3_trap_tval","width":64},{"name":"entries_3_trap_valid","width":1},{"name":"entries_4_destination_atag","width":6},{"name":"entries_4_destination_kind","width":3},{"name":"entries_4_destination_pGeneration","width":16},{"name":"entries_4_destination_previousPGeneration","width":16},{"name":"entries_4_destination_previousPtag","width":7},{"name":"entries_4_destination_previousPtagValid","width":1},{"name":"entries_4_destination_previousTtag","width":5},{"name":"entries_4_destination_previousTtagValid","width":1},{"name":"entries_4_destination_previousUtag","width":5},{"name":"entries_4_destination_previousUtagValid","width":1},{"name":"entries_4_destination_ptag","width":7},{"name":"entries_4_destination_ptagValid","width":1},{"name":"entries_4_destination_tGeneration","width":16},{"name":"entries_4_destination_tSeqGeneration","width":16},{"name":"entries_4_destination_tSeqIndex","width":5},{"name":"entries_4_destination_ttag","width":5},{"name":"entries_4_destination_ttagValid","width":1},{"name":"entries_4_destination_uGeneration","width":16},{"name":"entries_4_destination_uSeqGeneration","width":16},{"name":"entries_4_destination_uSeqIndex","width":5},{"name":"entries_4_destination_utag","width":5},{"name":"entries_4_destination_utagValid","width":1},{"name":"entries_4_destination_valid","width":1},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionBits","width":64},{"name":"entries_4_instructionLengthBytes","width":4},{"name":"entries_4_memory_attemptGeneration","width":16},{"name":"entries_4_memory_lsid","width":32},{"name":"entries_4_memory_pipeId","width":1},{"name":"entries_4_memory_rob_bid","width":8},{"name":"entries_4_memory_rob_brobGeneration","width":16},{"name":"entries_4_memory_rob_memberIndex","width":2},{"name":"entries_4_memory_rob_peId","width":8},{"name":"entries_4_memory_rob_residentGeneration","width":16},{"name":"entries_4_memory_rob_ridGeneration","width":16},{"name":"entries_4_memory_rob_ridSlot","width":6},{"name":"entries_4_memory_rob_stid","width":1},{"name":"entries_4_memory_transaction_generation","width":16},{"name":"entries_4_memory_transaction_value","width":64},{"name":"entries_4_memoryOrder_firstLid","width":32},{"name":"entries_4_memoryOrder_firstLsid","width":32},{"name":"entries_4_memoryOrder_firstSid","width":32},{"name":"entries_4_memoryOrder_requestCount","width":2},{"name":"entries_4_memoryOrder_yoldLid","width":32},{"name":"entries_4_memoryOrder_yoldLsid","width":32},{"name":"entries_4_memoryOrder_yoldValid","width":1},{"name":"entries_4_memoryOrder_yostLsid","width":32},{"name":"entries_4_memoryOrder_yostSid","width":32},{"name":"entries_4_memoryOrder_yostValid","width":1},{"name":"entries_4_memoryStore","width":1},{"name":"entries_4_memoryValid","width":1},{"name":"entries_4_opcode","width":12},{"name":"entries_4_pc","width":64},{"name":"entries_4_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_4_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_4_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_4_pcBufferIndexOffset_valid","width":1},{"name":"entries_4_result","width":64},{"name":"entries_4_resultValid","width":1},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robGroupLast","width":1},{"name":"entries_4_storeData","width":64},{"name":"entries_4_storeMask","width":8},{"name":"entries_4_trap_cause","width":32},{"name":"entries_4_trap_instruction_epoch","width":16},{"name":"entries_4_trap_instruction_instructionId","width":64},{"name":"entries_4_trap_instruction_peId","width":8},{"name":"entries_4_trap_instruction_stid","width":1},{"name":"entries_4_trap_kind","width":2},{"name":"entries_4_trap_rob_bid","width":8},{"name":"entries_4_trap_rob_brobGeneration","width":16},{"name":"entries_4_trap_rob_memberIndex","width":2},{"name":"entries_4_trap_rob_peId","width":8},{"name":"entries_4_trap_rob_residentGeneration","width":16},{"name":"entries_4_trap_rob_ridGeneration","width":16},{"name":"entries_4_trap_rob_ridSlot","width":6},{"name":"entries_4_trap_rob_stid","width":1},{"name":"entries_4_trap_targetPc","width":64},{"name":"entries_4_trap_tval","width":64},{"name":"entries_4_trap_valid","width":1},{"name":"entries_5_destination_atag","width":6},{"name":"entries_5_destination_kind","width":3},{"name":"entries_5_destination_pGeneration","width":16},{"name":"entries_5_destination_previousPGeneration","width":16},{"name":"entries_5_destination_previousPtag","width":7},{"name":"entries_5_destination_previousPtagValid","width":1},{"name":"entries_5_destination_previousTtag","width":5},{"name":"entries_5_destination_previousTtagValid","width":1},{"name":"entries_5_destination_previousUtag","width":5},{"name":"entries_5_destination_previousUtagValid","width":1},{"name":"entries_5_destination_ptag","width":7},{"name":"entries_5_destination_ptagValid","width":1},{"name":"entries_5_destination_tGeneration","width":16},{"name":"entries_5_destination_tSeqGeneration","width":16},{"name":"entries_5_destination_tSeqIndex","width":5},{"name":"entries_5_destination_ttag","width":5},{"name":"entries_5_destination_ttagValid","width":1},{"name":"entries_5_destination_uGeneration","width":16},{"name":"entries_5_destination_uSeqGeneration","width":16},{"name":"entries_5_destination_uSeqIndex","width":5},{"name":"entries_5_destination_utag","width":5},{"name":"entries_5_destination_utagValid","width":1},{"name":"entries_5_destination_valid","width":1},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionBits","width":64},{"name":"entries_5_instructionLengthBytes","width":4},{"name":"entries_5_memory_attemptGeneration","width":16},{"name":"entries_5_memory_lsid","width":32},{"name":"entries_5_memory_pipeId","width":1},{"name":"entries_5_memory_rob_bid","width":8},{"name":"entries_5_memory_rob_brobGeneration","width":16},{"name":"entries_5_memory_rob_memberIndex","width":2},{"name":"entries_5_memory_rob_peId","width":8},{"name":"entries_5_memory_rob_residentGeneration","width":16},{"name":"entries_5_memory_rob_ridGeneration","width":16},{"name":"entries_5_memory_rob_ridSlot","width":6},{"name":"entries_5_memory_rob_stid","width":1},{"name":"entries_5_memory_transaction_generation","width":16},{"name":"entries_5_memory_transaction_value","width":64},{"name":"entries_5_memoryOrder_firstLid","width":32},{"name":"entries_5_memoryOrder_firstLsid","width":32},{"name":"entries_5_memoryOrder_firstSid","width":32},{"name":"entries_5_memoryOrder_requestCount","width":2},{"name":"entries_5_memoryOrder_yoldLid","width":32},{"name":"entries_5_memoryOrder_yoldLsid","width":32},{"name":"entries_5_memoryOrder_yoldValid","width":1},{"name":"entries_5_memoryOrder_yostLsid","width":32},{"name":"entries_5_memoryOrder_yostSid","width":32},{"name":"entries_5_memoryOrder_yostValid","width":1},{"name":"entries_5_memoryStore","width":1},{"name":"entries_5_memoryValid","width":1},{"name":"entries_5_opcode","width":12},{"name":"entries_5_pc","width":64},{"name":"entries_5_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_5_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_5_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_5_pcBufferIndexOffset_valid","width":1},{"name":"entries_5_result","width":64},{"name":"entries_5_resultValid","width":1},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robGroupLast","width":1},{"name":"entries_5_storeData","width":64},{"name":"entries_5_storeMask","width":8},{"name":"entries_5_trap_cause","width":32},{"name":"entries_5_trap_instruction_epoch","width":16},{"name":"entries_5_trap_instruction_instructionId","width":64},{"name":"entries_5_trap_instruction_peId","width":8},{"name":"entries_5_trap_instruction_stid","width":1},{"name":"entries_5_trap_kind","width":2},{"name":"entries_5_trap_rob_bid","width":8},{"name":"entries_5_trap_rob_brobGeneration","width":16},{"name":"entries_5_trap_rob_memberIndex","width":2},{"name":"entries_5_trap_rob_peId","width":8},{"name":"entries_5_trap_rob_residentGeneration","width":16},{"name":"entries_5_trap_rob_ridGeneration","width":16},{"name":"entries_5_trap_rob_ridSlot","width":6},{"name":"entries_5_trap_rob_stid","width":1},{"name":"entries_5_trap_targetPc","width":64},{"name":"entries_5_trap_tval","width":64},{"name":"entries_5_trap_valid","width":1}]},{"name":"box_to_dtu_trace","contract_id":"IFC-DTU-001","producer":"TOP/IFU/CTU/OOO/IEX/LSU","consumer":"DTU","lanes":6,"payload":"TracePacket","ports":[{"name":"count","width":3},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3},{"name":"entries_4_cycle","width":64},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionValid","width":1},{"name":"entries_4_kind","width":3},{"name":"entries_4_opcode","width":12},{"name":"entries_4_payload","width":64},{"name":"entries_4_pc","width":64},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robValid","width":1},{"name":"entries_4_source","width":3},{"name":"entries_5_cycle","width":64},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionValid","width":1},{"name":"entries_5_kind","width":3},{"name":"entries_5_opcode","width":12},{"name":"entries_5_payload","width":64},{"name":"entries_5_pc","width":64},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robValid","width":1},{"name":"entries_5_source","width":3}]},{"name":"external_to_dtu_debug_request","contract_id":"IFC-DTU-001","producer":"External Debug","consumer":"DTU","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_ooo_debug_request","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"OOO","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_dtu_debug_response","contract_id":"IFC-DTU-001","producer":"OOO","consumer":"DTU","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_external_debug_response","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Debug","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_trace_export","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Trace","lanes":6,"payload":"TracePacket","ports":[{"name":"count","width":3},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3},{"name":"entries_4_cycle","width":64},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionValid","width":1},{"name":"entries_4_kind","width":3},{"name":"entries_4_opcode","width":12},{"name":"entries_4_payload","width":64},{"name":"entries_4_pc","width":64},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robValid","width":1},{"name":"entries_4_source","width":3},{"name":"entries_5_cycle","width":64},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionValid","width":1},{"name":"entries_5_kind","width":3},{"name":"entries_5_opcode","width":12},{"name":"entries_5_payload","width":64},{"name":"entries_5_pc","width":64},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robValid","width":1},{"name":"entries_5_source","width":3}]},{"name":"dtu_performance_counter","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Counter","lanes":32,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"instruction_memory_request","contract_id":"IFC-MEMORY-001","producer":"IFU","consumer":"Memory","lanes":1,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"instruction_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"IFU","lanes":1,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]},{"name":"data_memory_request","contract_id":"IFC-MEMORY-001","producer":"LSU","consumer":"Memory","lanes":4,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"data_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"LSU","lanes":4,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]}]},{"name":"W8","width":8,"endpoints":[{"name":"top_io","contract_id":"IFC-TOP-EXT-002","producer":"Platform","consumer":"TOP","lanes":1,"payload":"TOPIO","ports":[{"name":"bootstrapComplete","width":1},{"name":"bootstrapReady","width":1},{"name":"cmdIssue_bits_instruction_epoch","width":16},{"name":"cmdIssue_bits_instruction_instructionId","width":64},{"name":"cmdIssue_bits_instruction_peId","width":8},{"name":"cmdIssue_bits_instruction_stid","width":1},{"name":"cmdIssue_bits_opcode","width":12},{"name":"cmdIssue_bits_rob_bid","width":8},{"name":"cmdIssue_bits_rob_brobGeneration","width":16},{"name":"cmdIssue_bits_rob_memberIndex","width":2},{"name":"cmdIssue_bits_rob_peId","width":8},{"name":"cmdIssue_bits_rob_residentGeneration","width":16},{"name":"cmdIssue_bits_rob_ridGeneration","width":16},{"name":"cmdIssue_bits_rob_ridSlot","width":6},{"name":"cmdIssue_bits_rob_stid","width":1},{"name":"cmdIssue_bits_sourceValid","width":4},{"name":"cmdIssue_bits_sourceValues_0","width":64},{"name":"cmdIssue_bits_sourceValues_1","width":64},{"name":"cmdIssue_bits_sourceValues_2","width":64},{"name":"cmdIssue_bits_sourceValues_3","width":64},{"name":"cmdIssue_bits_transactionId","width":64},{"name":"cmdIssue_ready","width":1},{"name":"cmdIssue_valid","width":1},{"name":"commit_bits_count","width":4},{"name":"commit_bits_entries_0_destination_atag","width":6},{"name":"commit_bits_entries_0_destination_kind","width":3},{"name":"commit_bits_entries_0_destination_pGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_0_destination_previousPtag","width":7},{"name":"commit_bits_entries_0_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousTtag","width":5},{"name":"commit_bits_entries_0_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_0_destination_previousUtag","width":5},{"name":"commit_bits_entries_0_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_0_destination_ptag","width":7},{"name":"commit_bits_entries_0_destination_ptagValid","width":1},{"name":"commit_bits_entries_0_destination_tGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_ttag","width":5},{"name":"commit_bits_entries_0_destination_ttagValid","width":1},{"name":"commit_bits_entries_0_destination_uGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_0_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_0_destination_utag","width":5},{"name":"commit_bits_entries_0_destination_utagValid","width":1},{"name":"commit_bits_entries_0_destination_valid","width":1},{"name":"commit_bits_entries_0_instruction_epoch","width":16},{"name":"commit_bits_entries_0_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_instruction_peId","width":8},{"name":"commit_bits_entries_0_instruction_stid","width":1},{"name":"commit_bits_entries_0_instructionBits","width":64},{"name":"commit_bits_entries_0_instructionLengthBytes","width":4},{"name":"commit_bits_entries_0_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_0_memory_lsid","width":32},{"name":"commit_bits_entries_0_memory_pipeId","width":1},{"name":"commit_bits_entries_0_memory_rob_bid","width":8},{"name":"commit_bits_entries_0_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_memory_rob_peId","width":8},{"name":"commit_bits_entries_0_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_memory_rob_stid","width":1},{"name":"commit_bits_entries_0_memory_transaction_generation","width":16},{"name":"commit_bits_entries_0_memory_transaction_value","width":64},{"name":"commit_bits_entries_0_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_0_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_0_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_0_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_0_memoryStore","width":1},{"name":"commit_bits_entries_0_memoryValid","width":1},{"name":"commit_bits_entries_0_opcode","width":12},{"name":"commit_bits_entries_0_pc","width":64},{"name":"commit_bits_entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_0_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_0_result","width":64},{"name":"commit_bits_entries_0_resultValid","width":1},{"name":"commit_bits_entries_0_rob_bid","width":8},{"name":"commit_bits_entries_0_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_rob_peId","width":8},{"name":"commit_bits_entries_0_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_rob_stid","width":1},{"name":"commit_bits_entries_0_robGroupLast","width":1},{"name":"commit_bits_entries_0_storeData","width":64},{"name":"commit_bits_entries_0_storeMask","width":8},{"name":"commit_bits_entries_0_trap_cause","width":32},{"name":"commit_bits_entries_0_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_0_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_0_trap_instruction_peId","width":8},{"name":"commit_bits_entries_0_trap_instruction_stid","width":1},{"name":"commit_bits_entries_0_trap_kind","width":2},{"name":"commit_bits_entries_0_trap_rob_bid","width":8},{"name":"commit_bits_entries_0_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_0_trap_rob_peId","width":8},{"name":"commit_bits_entries_0_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_0_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_0_trap_rob_stid","width":1},{"name":"commit_bits_entries_0_trap_targetPc","width":64},{"name":"commit_bits_entries_0_trap_tval","width":64},{"name":"commit_bits_entries_0_trap_valid","width":1},{"name":"commit_bits_entries_1_destination_atag","width":6},{"name":"commit_bits_entries_1_destination_kind","width":3},{"name":"commit_bits_entries_1_destination_pGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_1_destination_previousPtag","width":7},{"name":"commit_bits_entries_1_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousTtag","width":5},{"name":"commit_bits_entries_1_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_1_destination_previousUtag","width":5},{"name":"commit_bits_entries_1_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_1_destination_ptag","width":7},{"name":"commit_bits_entries_1_destination_ptagValid","width":1},{"name":"commit_bits_entries_1_destination_tGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_ttag","width":5},{"name":"commit_bits_entries_1_destination_ttagValid","width":1},{"name":"commit_bits_entries_1_destination_uGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_1_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_1_destination_utag","width":5},{"name":"commit_bits_entries_1_destination_utagValid","width":1},{"name":"commit_bits_entries_1_destination_valid","width":1},{"name":"commit_bits_entries_1_instruction_epoch","width":16},{"name":"commit_bits_entries_1_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_instruction_peId","width":8},{"name":"commit_bits_entries_1_instruction_stid","width":1},{"name":"commit_bits_entries_1_instructionBits","width":64},{"name":"commit_bits_entries_1_instructionLengthBytes","width":4},{"name":"commit_bits_entries_1_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_1_memory_lsid","width":32},{"name":"commit_bits_entries_1_memory_pipeId","width":1},{"name":"commit_bits_entries_1_memory_rob_bid","width":8},{"name":"commit_bits_entries_1_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_memory_rob_peId","width":8},{"name":"commit_bits_entries_1_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_memory_rob_stid","width":1},{"name":"commit_bits_entries_1_memory_transaction_generation","width":16},{"name":"commit_bits_entries_1_memory_transaction_value","width":64},{"name":"commit_bits_entries_1_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_1_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_1_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_1_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_1_memoryStore","width":1},{"name":"commit_bits_entries_1_memoryValid","width":1},{"name":"commit_bits_entries_1_opcode","width":12},{"name":"commit_bits_entries_1_pc","width":64},{"name":"commit_bits_entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_1_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_1_result","width":64},{"name":"commit_bits_entries_1_resultValid","width":1},{"name":"commit_bits_entries_1_rob_bid","width":8},{"name":"commit_bits_entries_1_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_rob_peId","width":8},{"name":"commit_bits_entries_1_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_rob_stid","width":1},{"name":"commit_bits_entries_1_robGroupLast","width":1},{"name":"commit_bits_entries_1_storeData","width":64},{"name":"commit_bits_entries_1_storeMask","width":8},{"name":"commit_bits_entries_1_trap_cause","width":32},{"name":"commit_bits_entries_1_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_1_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_1_trap_instruction_peId","width":8},{"name":"commit_bits_entries_1_trap_instruction_stid","width":1},{"name":"commit_bits_entries_1_trap_kind","width":2},{"name":"commit_bits_entries_1_trap_rob_bid","width":8},{"name":"commit_bits_entries_1_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_1_trap_rob_peId","width":8},{"name":"commit_bits_entries_1_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_1_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_1_trap_rob_stid","width":1},{"name":"commit_bits_entries_1_trap_targetPc","width":64},{"name":"commit_bits_entries_1_trap_tval","width":64},{"name":"commit_bits_entries_1_trap_valid","width":1},{"name":"commit_bits_entries_2_destination_atag","width":6},{"name":"commit_bits_entries_2_destination_kind","width":3},{"name":"commit_bits_entries_2_destination_pGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_2_destination_previousPtag","width":7},{"name":"commit_bits_entries_2_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousTtag","width":5},{"name":"commit_bits_entries_2_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_2_destination_previousUtag","width":5},{"name":"commit_bits_entries_2_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_2_destination_ptag","width":7},{"name":"commit_bits_entries_2_destination_ptagValid","width":1},{"name":"commit_bits_entries_2_destination_tGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_ttag","width":5},{"name":"commit_bits_entries_2_destination_ttagValid","width":1},{"name":"commit_bits_entries_2_destination_uGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_2_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_2_destination_utag","width":5},{"name":"commit_bits_entries_2_destination_utagValid","width":1},{"name":"commit_bits_entries_2_destination_valid","width":1},{"name":"commit_bits_entries_2_instruction_epoch","width":16},{"name":"commit_bits_entries_2_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_instruction_peId","width":8},{"name":"commit_bits_entries_2_instruction_stid","width":1},{"name":"commit_bits_entries_2_instructionBits","width":64},{"name":"commit_bits_entries_2_instructionLengthBytes","width":4},{"name":"commit_bits_entries_2_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_2_memory_lsid","width":32},{"name":"commit_bits_entries_2_memory_pipeId","width":1},{"name":"commit_bits_entries_2_memory_rob_bid","width":8},{"name":"commit_bits_entries_2_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_memory_rob_peId","width":8},{"name":"commit_bits_entries_2_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_memory_rob_stid","width":1},{"name":"commit_bits_entries_2_memory_transaction_generation","width":16},{"name":"commit_bits_entries_2_memory_transaction_value","width":64},{"name":"commit_bits_entries_2_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_2_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_2_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_2_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_2_memoryStore","width":1},{"name":"commit_bits_entries_2_memoryValid","width":1},{"name":"commit_bits_entries_2_opcode","width":12},{"name":"commit_bits_entries_2_pc","width":64},{"name":"commit_bits_entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_2_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_2_result","width":64},{"name":"commit_bits_entries_2_resultValid","width":1},{"name":"commit_bits_entries_2_rob_bid","width":8},{"name":"commit_bits_entries_2_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_rob_peId","width":8},{"name":"commit_bits_entries_2_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_rob_stid","width":1},{"name":"commit_bits_entries_2_robGroupLast","width":1},{"name":"commit_bits_entries_2_storeData","width":64},{"name":"commit_bits_entries_2_storeMask","width":8},{"name":"commit_bits_entries_2_trap_cause","width":32},{"name":"commit_bits_entries_2_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_2_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_2_trap_instruction_peId","width":8},{"name":"commit_bits_entries_2_trap_instruction_stid","width":1},{"name":"commit_bits_entries_2_trap_kind","width":2},{"name":"commit_bits_entries_2_trap_rob_bid","width":8},{"name":"commit_bits_entries_2_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_2_trap_rob_peId","width":8},{"name":"commit_bits_entries_2_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_2_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_2_trap_rob_stid","width":1},{"name":"commit_bits_entries_2_trap_targetPc","width":64},{"name":"commit_bits_entries_2_trap_tval","width":64},{"name":"commit_bits_entries_2_trap_valid","width":1},{"name":"commit_bits_entries_3_destination_atag","width":6},{"name":"commit_bits_entries_3_destination_kind","width":3},{"name":"commit_bits_entries_3_destination_pGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_3_destination_previousPtag","width":7},{"name":"commit_bits_entries_3_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousTtag","width":5},{"name":"commit_bits_entries_3_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_3_destination_previousUtag","width":5},{"name":"commit_bits_entries_3_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_3_destination_ptag","width":7},{"name":"commit_bits_entries_3_destination_ptagValid","width":1},{"name":"commit_bits_entries_3_destination_tGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_ttag","width":5},{"name":"commit_bits_entries_3_destination_ttagValid","width":1},{"name":"commit_bits_entries_3_destination_uGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_3_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_3_destination_utag","width":5},{"name":"commit_bits_entries_3_destination_utagValid","width":1},{"name":"commit_bits_entries_3_destination_valid","width":1},{"name":"commit_bits_entries_3_instruction_epoch","width":16},{"name":"commit_bits_entries_3_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_instruction_peId","width":8},{"name":"commit_bits_entries_3_instruction_stid","width":1},{"name":"commit_bits_entries_3_instructionBits","width":64},{"name":"commit_bits_entries_3_instructionLengthBytes","width":4},{"name":"commit_bits_entries_3_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_3_memory_lsid","width":32},{"name":"commit_bits_entries_3_memory_pipeId","width":1},{"name":"commit_bits_entries_3_memory_rob_bid","width":8},{"name":"commit_bits_entries_3_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_memory_rob_peId","width":8},{"name":"commit_bits_entries_3_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_memory_rob_stid","width":1},{"name":"commit_bits_entries_3_memory_transaction_generation","width":16},{"name":"commit_bits_entries_3_memory_transaction_value","width":64},{"name":"commit_bits_entries_3_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_3_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_3_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_3_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_3_memoryStore","width":1},{"name":"commit_bits_entries_3_memoryValid","width":1},{"name":"commit_bits_entries_3_opcode","width":12},{"name":"commit_bits_entries_3_pc","width":64},{"name":"commit_bits_entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_3_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_3_result","width":64},{"name":"commit_bits_entries_3_resultValid","width":1},{"name":"commit_bits_entries_3_rob_bid","width":8},{"name":"commit_bits_entries_3_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_rob_peId","width":8},{"name":"commit_bits_entries_3_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_rob_stid","width":1},{"name":"commit_bits_entries_3_robGroupLast","width":1},{"name":"commit_bits_entries_3_storeData","width":64},{"name":"commit_bits_entries_3_storeMask","width":8},{"name":"commit_bits_entries_3_trap_cause","width":32},{"name":"commit_bits_entries_3_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_3_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_3_trap_instruction_peId","width":8},{"name":"commit_bits_entries_3_trap_instruction_stid","width":1},{"name":"commit_bits_entries_3_trap_kind","width":2},{"name":"commit_bits_entries_3_trap_rob_bid","width":8},{"name":"commit_bits_entries_3_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_3_trap_rob_peId","width":8},{"name":"commit_bits_entries_3_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_3_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_3_trap_rob_stid","width":1},{"name":"commit_bits_entries_3_trap_targetPc","width":64},{"name":"commit_bits_entries_3_trap_tval","width":64},{"name":"commit_bits_entries_3_trap_valid","width":1},{"name":"commit_bits_entries_4_destination_atag","width":6},{"name":"commit_bits_entries_4_destination_kind","width":3},{"name":"commit_bits_entries_4_destination_pGeneration","width":16},{"name":"commit_bits_entries_4_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_4_destination_previousPtag","width":7},{"name":"commit_bits_entries_4_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_4_destination_previousTtag","width":5},{"name":"commit_bits_entries_4_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_4_destination_previousUtag","width":5},{"name":"commit_bits_entries_4_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_4_destination_ptag","width":7},{"name":"commit_bits_entries_4_destination_ptagValid","width":1},{"name":"commit_bits_entries_4_destination_tGeneration","width":16},{"name":"commit_bits_entries_4_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_4_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_4_destination_ttag","width":5},{"name":"commit_bits_entries_4_destination_ttagValid","width":1},{"name":"commit_bits_entries_4_destination_uGeneration","width":16},{"name":"commit_bits_entries_4_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_4_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_4_destination_utag","width":5},{"name":"commit_bits_entries_4_destination_utagValid","width":1},{"name":"commit_bits_entries_4_destination_valid","width":1},{"name":"commit_bits_entries_4_instruction_epoch","width":16},{"name":"commit_bits_entries_4_instruction_instructionId","width":64},{"name":"commit_bits_entries_4_instruction_peId","width":8},{"name":"commit_bits_entries_4_instruction_stid","width":1},{"name":"commit_bits_entries_4_instructionBits","width":64},{"name":"commit_bits_entries_4_instructionLengthBytes","width":4},{"name":"commit_bits_entries_4_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_4_memory_lsid","width":32},{"name":"commit_bits_entries_4_memory_pipeId","width":1},{"name":"commit_bits_entries_4_memory_rob_bid","width":8},{"name":"commit_bits_entries_4_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_memory_rob_peId","width":8},{"name":"commit_bits_entries_4_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_memory_rob_stid","width":1},{"name":"commit_bits_entries_4_memory_transaction_generation","width":16},{"name":"commit_bits_entries_4_memory_transaction_value","width":64},{"name":"commit_bits_entries_4_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_4_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_4_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_4_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_4_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_4_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_4_memoryStore","width":1},{"name":"commit_bits_entries_4_memoryValid","width":1},{"name":"commit_bits_entries_4_opcode","width":12},{"name":"commit_bits_entries_4_pc","width":64},{"name":"commit_bits_entries_4_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_4_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_4_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_4_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_4_result","width":64},{"name":"commit_bits_entries_4_resultValid","width":1},{"name":"commit_bits_entries_4_rob_bid","width":8},{"name":"commit_bits_entries_4_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_rob_peId","width":8},{"name":"commit_bits_entries_4_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_rob_stid","width":1},{"name":"commit_bits_entries_4_robGroupLast","width":1},{"name":"commit_bits_entries_4_storeData","width":64},{"name":"commit_bits_entries_4_storeMask","width":8},{"name":"commit_bits_entries_4_trap_cause","width":32},{"name":"commit_bits_entries_4_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_4_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_4_trap_instruction_peId","width":8},{"name":"commit_bits_entries_4_trap_instruction_stid","width":1},{"name":"commit_bits_entries_4_trap_kind","width":2},{"name":"commit_bits_entries_4_trap_rob_bid","width":8},{"name":"commit_bits_entries_4_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_4_trap_rob_peId","width":8},{"name":"commit_bits_entries_4_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_4_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_4_trap_rob_stid","width":1},{"name":"commit_bits_entries_4_trap_targetPc","width":64},{"name":"commit_bits_entries_4_trap_tval","width":64},{"name":"commit_bits_entries_4_trap_valid","width":1},{"name":"commit_bits_entries_5_destination_atag","width":6},{"name":"commit_bits_entries_5_destination_kind","width":3},{"name":"commit_bits_entries_5_destination_pGeneration","width":16},{"name":"commit_bits_entries_5_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_5_destination_previousPtag","width":7},{"name":"commit_bits_entries_5_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_5_destination_previousTtag","width":5},{"name":"commit_bits_entries_5_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_5_destination_previousUtag","width":5},{"name":"commit_bits_entries_5_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_5_destination_ptag","width":7},{"name":"commit_bits_entries_5_destination_ptagValid","width":1},{"name":"commit_bits_entries_5_destination_tGeneration","width":16},{"name":"commit_bits_entries_5_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_5_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_5_destination_ttag","width":5},{"name":"commit_bits_entries_5_destination_ttagValid","width":1},{"name":"commit_bits_entries_5_destination_uGeneration","width":16},{"name":"commit_bits_entries_5_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_5_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_5_destination_utag","width":5},{"name":"commit_bits_entries_5_destination_utagValid","width":1},{"name":"commit_bits_entries_5_destination_valid","width":1},{"name":"commit_bits_entries_5_instruction_epoch","width":16},{"name":"commit_bits_entries_5_instruction_instructionId","width":64},{"name":"commit_bits_entries_5_instruction_peId","width":8},{"name":"commit_bits_entries_5_instruction_stid","width":1},{"name":"commit_bits_entries_5_instructionBits","width":64},{"name":"commit_bits_entries_5_instructionLengthBytes","width":4},{"name":"commit_bits_entries_5_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_5_memory_lsid","width":32},{"name":"commit_bits_entries_5_memory_pipeId","width":1},{"name":"commit_bits_entries_5_memory_rob_bid","width":8},{"name":"commit_bits_entries_5_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_memory_rob_peId","width":8},{"name":"commit_bits_entries_5_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_memory_rob_stid","width":1},{"name":"commit_bits_entries_5_memory_transaction_generation","width":16},{"name":"commit_bits_entries_5_memory_transaction_value","width":64},{"name":"commit_bits_entries_5_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_5_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_5_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_5_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_5_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_5_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_5_memoryStore","width":1},{"name":"commit_bits_entries_5_memoryValid","width":1},{"name":"commit_bits_entries_5_opcode","width":12},{"name":"commit_bits_entries_5_pc","width":64},{"name":"commit_bits_entries_5_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_5_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_5_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_5_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_5_result","width":64},{"name":"commit_bits_entries_5_resultValid","width":1},{"name":"commit_bits_entries_5_rob_bid","width":8},{"name":"commit_bits_entries_5_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_rob_peId","width":8},{"name":"commit_bits_entries_5_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_rob_stid","width":1},{"name":"commit_bits_entries_5_robGroupLast","width":1},{"name":"commit_bits_entries_5_storeData","width":64},{"name":"commit_bits_entries_5_storeMask","width":8},{"name":"commit_bits_entries_5_trap_cause","width":32},{"name":"commit_bits_entries_5_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_5_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_5_trap_instruction_peId","width":8},{"name":"commit_bits_entries_5_trap_instruction_stid","width":1},{"name":"commit_bits_entries_5_trap_kind","width":2},{"name":"commit_bits_entries_5_trap_rob_bid","width":8},{"name":"commit_bits_entries_5_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_5_trap_rob_peId","width":8},{"name":"commit_bits_entries_5_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_5_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_5_trap_rob_stid","width":1},{"name":"commit_bits_entries_5_trap_targetPc","width":64},{"name":"commit_bits_entries_5_trap_tval","width":64},{"name":"commit_bits_entries_5_trap_valid","width":1},{"name":"commit_bits_entries_6_destination_atag","width":6},{"name":"commit_bits_entries_6_destination_kind","width":3},{"name":"commit_bits_entries_6_destination_pGeneration","width":16},{"name":"commit_bits_entries_6_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_6_destination_previousPtag","width":7},{"name":"commit_bits_entries_6_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_6_destination_previousTtag","width":5},{"name":"commit_bits_entries_6_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_6_destination_previousUtag","width":5},{"name":"commit_bits_entries_6_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_6_destination_ptag","width":7},{"name":"commit_bits_entries_6_destination_ptagValid","width":1},{"name":"commit_bits_entries_6_destination_tGeneration","width":16},{"name":"commit_bits_entries_6_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_6_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_6_destination_ttag","width":5},{"name":"commit_bits_entries_6_destination_ttagValid","width":1},{"name":"commit_bits_entries_6_destination_uGeneration","width":16},{"name":"commit_bits_entries_6_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_6_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_6_destination_utag","width":5},{"name":"commit_bits_entries_6_destination_utagValid","width":1},{"name":"commit_bits_entries_6_destination_valid","width":1},{"name":"commit_bits_entries_6_instruction_epoch","width":16},{"name":"commit_bits_entries_6_instruction_instructionId","width":64},{"name":"commit_bits_entries_6_instruction_peId","width":8},{"name":"commit_bits_entries_6_instruction_stid","width":1},{"name":"commit_bits_entries_6_instructionBits","width":64},{"name":"commit_bits_entries_6_instructionLengthBytes","width":4},{"name":"commit_bits_entries_6_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_6_memory_lsid","width":32},{"name":"commit_bits_entries_6_memory_pipeId","width":1},{"name":"commit_bits_entries_6_memory_rob_bid","width":8},{"name":"commit_bits_entries_6_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_6_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_6_memory_rob_peId","width":8},{"name":"commit_bits_entries_6_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_6_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_6_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_6_memory_rob_stid","width":1},{"name":"commit_bits_entries_6_memory_transaction_generation","width":16},{"name":"commit_bits_entries_6_memory_transaction_value","width":64},{"name":"commit_bits_entries_6_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_6_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_6_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_6_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_6_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_6_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_6_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_6_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_6_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_6_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_6_memoryStore","width":1},{"name":"commit_bits_entries_6_memoryValid","width":1},{"name":"commit_bits_entries_6_opcode","width":12},{"name":"commit_bits_entries_6_pc","width":64},{"name":"commit_bits_entries_6_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_6_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_6_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_6_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_6_result","width":64},{"name":"commit_bits_entries_6_resultValid","width":1},{"name":"commit_bits_entries_6_rob_bid","width":8},{"name":"commit_bits_entries_6_rob_brobGeneration","width":16},{"name":"commit_bits_entries_6_rob_memberIndex","width":2},{"name":"commit_bits_entries_6_rob_peId","width":8},{"name":"commit_bits_entries_6_rob_residentGeneration","width":16},{"name":"commit_bits_entries_6_rob_ridGeneration","width":16},{"name":"commit_bits_entries_6_rob_ridSlot","width":6},{"name":"commit_bits_entries_6_rob_stid","width":1},{"name":"commit_bits_entries_6_robGroupLast","width":1},{"name":"commit_bits_entries_6_storeData","width":64},{"name":"commit_bits_entries_6_storeMask","width":8},{"name":"commit_bits_entries_6_trap_cause","width":32},{"name":"commit_bits_entries_6_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_6_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_6_trap_instruction_peId","width":8},{"name":"commit_bits_entries_6_trap_instruction_stid","width":1},{"name":"commit_bits_entries_6_trap_kind","width":2},{"name":"commit_bits_entries_6_trap_rob_bid","width":8},{"name":"commit_bits_entries_6_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_6_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_6_trap_rob_peId","width":8},{"name":"commit_bits_entries_6_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_6_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_6_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_6_trap_rob_stid","width":1},{"name":"commit_bits_entries_6_trap_targetPc","width":64},{"name":"commit_bits_entries_6_trap_tval","width":64},{"name":"commit_bits_entries_6_trap_valid","width":1},{"name":"commit_bits_entries_7_destination_atag","width":6},{"name":"commit_bits_entries_7_destination_kind","width":3},{"name":"commit_bits_entries_7_destination_pGeneration","width":16},{"name":"commit_bits_entries_7_destination_previousPGeneration","width":16},{"name":"commit_bits_entries_7_destination_previousPtag","width":7},{"name":"commit_bits_entries_7_destination_previousPtagValid","width":1},{"name":"commit_bits_entries_7_destination_previousTtag","width":5},{"name":"commit_bits_entries_7_destination_previousTtagValid","width":1},{"name":"commit_bits_entries_7_destination_previousUtag","width":5},{"name":"commit_bits_entries_7_destination_previousUtagValid","width":1},{"name":"commit_bits_entries_7_destination_ptag","width":7},{"name":"commit_bits_entries_7_destination_ptagValid","width":1},{"name":"commit_bits_entries_7_destination_tGeneration","width":16},{"name":"commit_bits_entries_7_destination_tSeqGeneration","width":16},{"name":"commit_bits_entries_7_destination_tSeqIndex","width":5},{"name":"commit_bits_entries_7_destination_ttag","width":5},{"name":"commit_bits_entries_7_destination_ttagValid","width":1},{"name":"commit_bits_entries_7_destination_uGeneration","width":16},{"name":"commit_bits_entries_7_destination_uSeqGeneration","width":16},{"name":"commit_bits_entries_7_destination_uSeqIndex","width":5},{"name":"commit_bits_entries_7_destination_utag","width":5},{"name":"commit_bits_entries_7_destination_utagValid","width":1},{"name":"commit_bits_entries_7_destination_valid","width":1},{"name":"commit_bits_entries_7_instruction_epoch","width":16},{"name":"commit_bits_entries_7_instruction_instructionId","width":64},{"name":"commit_bits_entries_7_instruction_peId","width":8},{"name":"commit_bits_entries_7_instruction_stid","width":1},{"name":"commit_bits_entries_7_instructionBits","width":64},{"name":"commit_bits_entries_7_instructionLengthBytes","width":4},{"name":"commit_bits_entries_7_memory_attemptGeneration","width":16},{"name":"commit_bits_entries_7_memory_lsid","width":32},{"name":"commit_bits_entries_7_memory_pipeId","width":1},{"name":"commit_bits_entries_7_memory_rob_bid","width":8},{"name":"commit_bits_entries_7_memory_rob_brobGeneration","width":16},{"name":"commit_bits_entries_7_memory_rob_memberIndex","width":2},{"name":"commit_bits_entries_7_memory_rob_peId","width":8},{"name":"commit_bits_entries_7_memory_rob_residentGeneration","width":16},{"name":"commit_bits_entries_7_memory_rob_ridGeneration","width":16},{"name":"commit_bits_entries_7_memory_rob_ridSlot","width":6},{"name":"commit_bits_entries_7_memory_rob_stid","width":1},{"name":"commit_bits_entries_7_memory_transaction_generation","width":16},{"name":"commit_bits_entries_7_memory_transaction_value","width":64},{"name":"commit_bits_entries_7_memoryOrder_firstLid","width":32},{"name":"commit_bits_entries_7_memoryOrder_firstLsid","width":32},{"name":"commit_bits_entries_7_memoryOrder_firstSid","width":32},{"name":"commit_bits_entries_7_memoryOrder_requestCount","width":2},{"name":"commit_bits_entries_7_memoryOrder_yoldLid","width":32},{"name":"commit_bits_entries_7_memoryOrder_yoldLsid","width":32},{"name":"commit_bits_entries_7_memoryOrder_yoldValid","width":1},{"name":"commit_bits_entries_7_memoryOrder_yostLsid","width":32},{"name":"commit_bits_entries_7_memoryOrder_yostSid","width":32},{"name":"commit_bits_entries_7_memoryOrder_yostValid","width":1},{"name":"commit_bits_entries_7_memoryStore","width":1},{"name":"commit_bits_entries_7_memoryValid","width":1},{"name":"commit_bits_entries_7_opcode","width":12},{"name":"commit_bits_entries_7_pc","width":64},{"name":"commit_bits_entries_7_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"commit_bits_entries_7_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"commit_bits_entries_7_pcBufferIndexOffset_pcOffset","width":7},{"name":"commit_bits_entries_7_pcBufferIndexOffset_valid","width":1},{"name":"commit_bits_entries_7_result","width":64},{"name":"commit_bits_entries_7_resultValid","width":1},{"name":"commit_bits_entries_7_rob_bid","width":8},{"name":"commit_bits_entries_7_rob_brobGeneration","width":16},{"name":"commit_bits_entries_7_rob_memberIndex","width":2},{"name":"commit_bits_entries_7_rob_peId","width":8},{"name":"commit_bits_entries_7_rob_residentGeneration","width":16},{"name":"commit_bits_entries_7_rob_ridGeneration","width":16},{"name":"commit_bits_entries_7_rob_ridSlot","width":6},{"name":"commit_bits_entries_7_rob_stid","width":1},{"name":"commit_bits_entries_7_robGroupLast","width":1},{"name":"commit_bits_entries_7_storeData","width":64},{"name":"commit_bits_entries_7_storeMask","width":8},{"name":"commit_bits_entries_7_trap_cause","width":32},{"name":"commit_bits_entries_7_trap_instruction_epoch","width":16},{"name":"commit_bits_entries_7_trap_instruction_instructionId","width":64},{"name":"commit_bits_entries_7_trap_instruction_peId","width":8},{"name":"commit_bits_entries_7_trap_instruction_stid","width":1},{"name":"commit_bits_entries_7_trap_kind","width":2},{"name":"commit_bits_entries_7_trap_rob_bid","width":8},{"name":"commit_bits_entries_7_trap_rob_brobGeneration","width":16},{"name":"commit_bits_entries_7_trap_rob_memberIndex","width":2},{"name":"commit_bits_entries_7_trap_rob_peId","width":8},{"name":"commit_bits_entries_7_trap_rob_residentGeneration","width":16},{"name":"commit_bits_entries_7_trap_rob_ridGeneration","width":16},{"name":"commit_bits_entries_7_trap_rob_ridSlot","width":6},{"name":"commit_bits_entries_7_trap_rob_stid","width":1},{"name":"commit_bits_entries_7_trap_targetPc","width":64},{"name":"commit_bits_entries_7_trap_tval","width":64},{"name":"commit_bits_entries_7_trap_valid","width":1},{"name":"commit_ready","width":1},{"name":"commit_valid","width":1},{"name":"dataMemoryRequest_0_bits_accessKind","width":2},{"name":"dataMemoryRequest_0_bits_address","width":64},{"name":"dataMemoryRequest_0_bits_byteMask","width":8},{"name":"dataMemoryRequest_0_bits_command","width":3},{"name":"dataMemoryRequest_0_bits_data","width":64},{"name":"dataMemoryRequest_0_bits_identity_generation","width":16},{"name":"dataMemoryRequest_0_bits_identity_value","width":64},{"name":"dataMemoryRequest_0_bits_instructionSide","width":1},{"name":"dataMemoryRequest_0_bits_size","width":3},{"name":"dataMemoryRequest_0_ready","width":1},{"name":"dataMemoryRequest_0_valid","width":1},{"name":"dataMemoryRequest_1_bits_accessKind","width":2},{"name":"dataMemoryRequest_1_bits_address","width":64},{"name":"dataMemoryRequest_1_bits_byteMask","width":8},{"name":"dataMemoryRequest_1_bits_command","width":3},{"name":"dataMemoryRequest_1_bits_data","width":64},{"name":"dataMemoryRequest_1_bits_identity_generation","width":16},{"name":"dataMemoryRequest_1_bits_identity_value","width":64},{"name":"dataMemoryRequest_1_bits_instructionSide","width":1},{"name":"dataMemoryRequest_1_bits_size","width":3},{"name":"dataMemoryRequest_1_ready","width":1},{"name":"dataMemoryRequest_1_valid","width":1},{"name":"dataMemoryRequest_2_bits_accessKind","width":2},{"name":"dataMemoryRequest_2_bits_address","width":64},{"name":"dataMemoryRequest_2_bits_byteMask","width":8},{"name":"dataMemoryRequest_2_bits_command","width":3},{"name":"dataMemoryRequest_2_bits_data","width":64},{"name":"dataMemoryRequest_2_bits_identity_generation","width":16},{"name":"dataMemoryRequest_2_bits_identity_value","width":64},{"name":"dataMemoryRequest_2_bits_instructionSide","width":1},{"name":"dataMemoryRequest_2_bits_size","width":3},{"name":"dataMemoryRequest_2_ready","width":1},{"name":"dataMemoryRequest_2_valid","width":1},{"name":"dataMemoryRequest_3_bits_accessKind","width":2},{"name":"dataMemoryRequest_3_bits_address","width":64},{"name":"dataMemoryRequest_3_bits_byteMask","width":8},{"name":"dataMemoryRequest_3_bits_command","width":3},{"name":"dataMemoryRequest_3_bits_data","width":64},{"name":"dataMemoryRequest_3_bits_identity_generation","width":16},{"name":"dataMemoryRequest_3_bits_identity_value","width":64},{"name":"dataMemoryRequest_3_bits_instructionSide","width":1},{"name":"dataMemoryRequest_3_bits_size","width":3},{"name":"dataMemoryRequest_3_ready","width":1},{"name":"dataMemoryRequest_3_valid","width":1},{"name":"dataMemoryResponse_0_bits_address","width":64},{"name":"dataMemoryResponse_0_bits_attributesValid","width":1},{"name":"dataMemoryResponse_0_bits_cacheable","width":1},{"name":"dataMemoryResponse_0_bits_corrupt","width":1},{"name":"dataMemoryResponse_0_bits_data","width":64},{"name":"dataMemoryResponse_0_bits_denied","width":1},{"name":"dataMemoryResponse_0_bits_device","width":1},{"name":"dataMemoryResponse_0_bits_errorCause","width":32},{"name":"dataMemoryResponse_0_bits_identity_generation","width":16},{"name":"dataMemoryResponse_0_bits_identity_value","width":64},{"name":"dataMemoryResponse_0_bits_lineData","width":512},{"name":"dataMemoryResponse_0_bits_readable","width":1},{"name":"dataMemoryResponse_0_bits_writable","width":1},{"name":"dataMemoryResponse_0_ready","width":1},{"name":"dataMemoryResponse_0_valid","width":1},{"name":"dataMemoryResponse_1_bits_address","width":64},{"name":"dataMemoryResponse_1_bits_attributesValid","width":1},{"name":"dataMemoryResponse_1_bits_cacheable","width":1},{"name":"dataMemoryResponse_1_bits_corrupt","width":1},{"name":"dataMemoryResponse_1_bits_data","width":64},{"name":"dataMemoryResponse_1_bits_denied","width":1},{"name":"dataMemoryResponse_1_bits_device","width":1},{"name":"dataMemoryResponse_1_bits_errorCause","width":32},{"name":"dataMemoryResponse_1_bits_identity_generation","width":16},{"name":"dataMemoryResponse_1_bits_identity_value","width":64},{"name":"dataMemoryResponse_1_bits_lineData","width":512},{"name":"dataMemoryResponse_1_bits_readable","width":1},{"name":"dataMemoryResponse_1_bits_writable","width":1},{"name":"dataMemoryResponse_1_ready","width":1},{"name":"dataMemoryResponse_1_valid","width":1},{"name":"dataMemoryResponse_2_bits_address","width":64},{"name":"dataMemoryResponse_2_bits_attributesValid","width":1},{"name":"dataMemoryResponse_2_bits_cacheable","width":1},{"name":"dataMemoryResponse_2_bits_corrupt","width":1},{"name":"dataMemoryResponse_2_bits_data","width":64},{"name":"dataMemoryResponse_2_bits_denied","width":1},{"name":"dataMemoryResponse_2_bits_device","width":1},{"name":"dataMemoryResponse_2_bits_errorCause","width":32},{"name":"dataMemoryResponse_2_bits_identity_generation","width":16},{"name":"dataMemoryResponse_2_bits_identity_value","width":64},{"name":"dataMemoryResponse_2_bits_lineData","width":512},{"name":"dataMemoryResponse_2_bits_readable","width":1},{"name":"dataMemoryResponse_2_bits_writable","width":1},{"name":"dataMemoryResponse_2_ready","width":1},{"name":"dataMemoryResponse_2_valid","width":1},{"name":"dataMemoryResponse_3_bits_address","width":64},{"name":"dataMemoryResponse_3_bits_attributesValid","width":1},{"name":"dataMemoryResponse_3_bits_cacheable","width":1},{"name":"dataMemoryResponse_3_bits_corrupt","width":1},{"name":"dataMemoryResponse_3_bits_data","width":64},{"name":"dataMemoryResponse_3_bits_denied","width":1},{"name":"dataMemoryResponse_3_bits_device","width":1},{"name":"dataMemoryResponse_3_bits_errorCause","width":32},{"name":"dataMemoryResponse_3_bits_identity_generation","width":16},{"name":"dataMemoryResponse_3_bits_identity_value","width":64},{"name":"dataMemoryResponse_3_bits_lineData","width":512},{"name":"dataMemoryResponse_3_bits_readable","width":1},{"name":"dataMemoryResponse_3_bits_writable","width":1},{"name":"dataMemoryResponse_3_ready","width":1},{"name":"dataMemoryResponse_3_valid","width":1},{"name":"debugRequest_bits_address","width":64},{"name":"debugRequest_bits_command","width":3},{"name":"debugRequest_bits_data","width":64},{"name":"debugRequest_bits_stid","width":1},{"name":"debugRequest_bits_transactionId","width":64},{"name":"debugRequest_ready","width":1},{"name":"debugRequest_valid","width":1},{"name":"debugResponse_bits_accepted","width":1},{"name":"debugResponse_bits_data","width":64},{"name":"debugResponse_bits_error","width":1},{"name":"debugResponse_bits_transactionId","width":64},{"name":"debugResponse_ready","width":1},{"name":"debugResponse_valid","width":1},{"name":"instructionMemoryRequest_bits_accessKind","width":2},{"name":"instructionMemoryRequest_bits_address","width":64},{"name":"instructionMemoryRequest_bits_byteMask","width":8},{"name":"instructionMemoryRequest_bits_command","width":3},{"name":"instructionMemoryRequest_bits_data","width":64},{"name":"instructionMemoryRequest_bits_identity_generation","width":16},{"name":"instructionMemoryRequest_bits_identity_value","width":64},{"name":"instructionMemoryRequest_bits_instructionSide","width":1},{"name":"instructionMemoryRequest_bits_size","width":3},{"name":"instructionMemoryRequest_ready","width":1},{"name":"instructionMemoryRequest_valid","width":1},{"name":"instructionMemoryResponse_bits_address","width":64},{"name":"instructionMemoryResponse_bits_attributesValid","width":1},{"name":"instructionMemoryResponse_bits_cacheable","width":1},{"name":"instructionMemoryResponse_bits_corrupt","width":1},{"name":"instructionMemoryResponse_bits_data","width":64},{"name":"instructionMemoryResponse_bits_denied","width":1},{"name":"instructionMemoryResponse_bits_device","width":1},{"name":"instructionMemoryResponse_bits_errorCause","width":32},{"name":"instructionMemoryResponse_bits_identity_generation","width":16},{"name":"instructionMemoryResponse_bits_identity_value","width":64},{"name":"instructionMemoryResponse_bits_lineData","width":512},{"name":"instructionMemoryResponse_bits_readable","width":1},{"name":"instructionMemoryResponse_bits_writable","width":1},{"name":"instructionMemoryResponse_ready","width":1},{"name":"instructionMemoryResponse_valid","width":1},{"name":"interrupt_bits_cause","width":32},{"name":"interrupt_bits_priority","width":8},{"name":"interrupt_bits_stid","width":1},{"name":"interrupt_bits_valid","width":1},{"name":"interrupt_valid","width":1},{"name":"loadReissueRequest_bits_address","width":64},{"name":"loadReissueRequest_bits_allocationId_generation","width":16},{"name":"loadReissueRequest_bits_allocationId_value","width":64},{"name":"loadReissueRequest_bits_currentIdentity_attemptGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_lsid","width":32},{"name":"loadReissueRequest_bits_currentIdentity_pipeId","width":1},{"name":"loadReissueRequest_bits_currentIdentity_rob_bid","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_brobGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_memberIndex","width":2},{"name":"loadReissueRequest_bits_currentIdentity_rob_peId","width":8},{"name":"loadReissueRequest_bits_currentIdentity_rob_residentGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridGeneration","width":16},{"name":"loadReissueRequest_bits_currentIdentity_rob_ridSlot","width":6},{"name":"loadReissueRequest_bits_currentIdentity_rob_stid","width":1},{"name":"loadReissueRequest_bits_currentIdentity_transaction_generation","width":16},{"name":"loadReissueRequest_bits_currentIdentity_transaction_value","width":64},{"name":"loadReissueRequest_ready","width":1},{"name":"loadReissueRequest_valid","width":1},{"name":"lsuProtocolError","width":1},{"name":"lsuQuiescent","width":1},{"name":"maintenance_bits_address","width":64},{"name":"maintenance_bits_command","width":2},{"name":"maintenance_ready","width":1},{"name":"maintenance_valid","width":1},{"name":"maintenanceResult_bits_address","width":64},{"name":"maintenanceResult_bits_command","width":2},{"name":"maintenanceResult_bits_success","width":1},{"name":"maintenanceResult_ready","width":1},{"name":"maintenanceResult_valid","width":1},{"name":"memoryFault_bits_address","width":64},{"name":"memoryFault_bits_cause","width":1},{"name":"memoryFault_bits_identity_attemptGeneration","width":16},{"name":"memoryFault_bits_identity_lsid","width":32},{"name":"memoryFault_bits_identity_pipeId","width":1},{"name":"memoryFault_bits_identity_rob_bid","width":8},{"name":"memoryFault_bits_identity_rob_brobGeneration","width":16},{"name":"memoryFault_bits_identity_rob_memberIndex","width":2},{"name":"memoryFault_bits_identity_rob_peId","width":8},{"name":"memoryFault_bits_identity_rob_residentGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridGeneration","width":16},{"name":"memoryFault_bits_identity_rob_ridSlot","width":6},{"name":"memoryFault_bits_identity_rob_stid","width":1},{"name":"memoryFault_bits_identity_transaction_generation","width":16},{"name":"memoryFault_bits_identity_transaction_value","width":64},{"name":"memoryFault_bits_write","width":1},{"name":"memoryFault_ready","width":1},{"name":"memoryFault_valid","width":1},{"name":"pInit_bits_atag","width":5},{"name":"pInit_bits_epoch","width":16},{"name":"pInit_bits_generation","width":16},{"name":"pInit_bits_ptag","width":7},{"name":"pInit_bits_stid","width":1},{"name":"pInit_bits_value","width":64},{"name":"pInit_ready","width":1},{"name":"pInit_valid","width":1},{"name":"performanceCounters_0","width":64},{"name":"performanceCounters_1","width":64},{"name":"performanceCounters_2","width":64},{"name":"performanceCounters_3","width":64},{"name":"performanceCounters_4","width":64},{"name":"performanceCounters_5","width":64},{"name":"performanceCounters_6","width":64},{"name":"performanceCounters_7","width":64},{"name":"performanceCounters_8","width":64},{"name":"performanceCounters_9","width":64},{"name":"performanceCounters_10","width":64},{"name":"performanceCounters_11","width":64},{"name":"performanceCounters_12","width":64},{"name":"performanceCounters_13","width":64},{"name":"performanceCounters_14","width":64},{"name":"performanceCounters_15","width":64},{"name":"performanceCounters_16","width":64},{"name":"performanceCounters_17","width":64},{"name":"performanceCounters_18","width":64},{"name":"performanceCounters_19","width":64},{"name":"performanceCounters_20","width":64},{"name":"performanceCounters_21","width":64},{"name":"performanceCounters_22","width":64},{"name":"performanceCounters_23","width":64},{"name":"performanceCounters_24","width":64},{"name":"performanceCounters_25","width":64},{"name":"performanceCounters_26","width":64},{"name":"performanceCounters_27","width":64},{"name":"performanceCounters_28","width":64},{"name":"performanceCounters_29","width":64},{"name":"performanceCounters_30","width":64},{"name":"performanceCounters_31","width":64},{"name":"systemIssue_0_bits_immediate","width":64},{"name":"systemIssue_0_bits_instruction_epoch","width":16},{"name":"systemIssue_0_bits_instruction_instructionId","width":64},{"name":"systemIssue_0_bits_instruction_peId","width":8},{"name":"systemIssue_0_bits_instruction_stid","width":1},{"name":"systemIssue_0_bits_opcode","width":12},{"name":"systemIssue_0_bits_rob_bid","width":8},{"name":"systemIssue_0_bits_rob_brobGeneration","width":16},{"name":"systemIssue_0_bits_rob_memberIndex","width":2},{"name":"systemIssue_0_bits_rob_peId","width":8},{"name":"systemIssue_0_bits_rob_residentGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridGeneration","width":16},{"name":"systemIssue_0_bits_rob_ridSlot","width":6},{"name":"systemIssue_0_bits_rob_stid","width":1},{"name":"systemIssue_0_bits_transactionId","width":64},{"name":"systemIssue_0_ready","width":1},{"name":"systemIssue_0_valid","width":1},{"name":"trace_bits_count","width":4},{"name":"trace_bits_entries_0_cycle","width":64},{"name":"trace_bits_entries_0_instruction_epoch","width":16},{"name":"trace_bits_entries_0_instruction_instructionId","width":64},{"name":"trace_bits_entries_0_instruction_peId","width":8},{"name":"trace_bits_entries_0_instruction_stid","width":1},{"name":"trace_bits_entries_0_instructionValid","width":1},{"name":"trace_bits_entries_0_kind","width":3},{"name":"trace_bits_entries_0_opcode","width":12},{"name":"trace_bits_entries_0_payload","width":64},{"name":"trace_bits_entries_0_pc","width":64},{"name":"trace_bits_entries_0_rob_bid","width":8},{"name":"trace_bits_entries_0_rob_brobGeneration","width":16},{"name":"trace_bits_entries_0_rob_memberIndex","width":2},{"name":"trace_bits_entries_0_rob_peId","width":8},{"name":"trace_bits_entries_0_rob_residentGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridGeneration","width":16},{"name":"trace_bits_entries_0_rob_ridSlot","width":6},{"name":"trace_bits_entries_0_rob_stid","width":1},{"name":"trace_bits_entries_0_robValid","width":1},{"name":"trace_bits_entries_0_source","width":3},{"name":"trace_bits_entries_1_cycle","width":64},{"name":"trace_bits_entries_1_instruction_epoch","width":16},{"name":"trace_bits_entries_1_instruction_instructionId","width":64},{"name":"trace_bits_entries_1_instruction_peId","width":8},{"name":"trace_bits_entries_1_instruction_stid","width":1},{"name":"trace_bits_entries_1_instructionValid","width":1},{"name":"trace_bits_entries_1_kind","width":3},{"name":"trace_bits_entries_1_opcode","width":12},{"name":"trace_bits_entries_1_payload","width":64},{"name":"trace_bits_entries_1_pc","width":64},{"name":"trace_bits_entries_1_rob_bid","width":8},{"name":"trace_bits_entries_1_rob_brobGeneration","width":16},{"name":"trace_bits_entries_1_rob_memberIndex","width":2},{"name":"trace_bits_entries_1_rob_peId","width":8},{"name":"trace_bits_entries_1_rob_residentGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridGeneration","width":16},{"name":"trace_bits_entries_1_rob_ridSlot","width":6},{"name":"trace_bits_entries_1_rob_stid","width":1},{"name":"trace_bits_entries_1_robValid","width":1},{"name":"trace_bits_entries_1_source","width":3},{"name":"trace_bits_entries_2_cycle","width":64},{"name":"trace_bits_entries_2_instruction_epoch","width":16},{"name":"trace_bits_entries_2_instruction_instructionId","width":64},{"name":"trace_bits_entries_2_instruction_peId","width":8},{"name":"trace_bits_entries_2_instruction_stid","width":1},{"name":"trace_bits_entries_2_instructionValid","width":1},{"name":"trace_bits_entries_2_kind","width":3},{"name":"trace_bits_entries_2_opcode","width":12},{"name":"trace_bits_entries_2_payload","width":64},{"name":"trace_bits_entries_2_pc","width":64},{"name":"trace_bits_entries_2_rob_bid","width":8},{"name":"trace_bits_entries_2_rob_brobGeneration","width":16},{"name":"trace_bits_entries_2_rob_memberIndex","width":2},{"name":"trace_bits_entries_2_rob_peId","width":8},{"name":"trace_bits_entries_2_rob_residentGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridGeneration","width":16},{"name":"trace_bits_entries_2_rob_ridSlot","width":6},{"name":"trace_bits_entries_2_rob_stid","width":1},{"name":"trace_bits_entries_2_robValid","width":1},{"name":"trace_bits_entries_2_source","width":3},{"name":"trace_bits_entries_3_cycle","width":64},{"name":"trace_bits_entries_3_instruction_epoch","width":16},{"name":"trace_bits_entries_3_instruction_instructionId","width":64},{"name":"trace_bits_entries_3_instruction_peId","width":8},{"name":"trace_bits_entries_3_instruction_stid","width":1},{"name":"trace_bits_entries_3_instructionValid","width":1},{"name":"trace_bits_entries_3_kind","width":3},{"name":"trace_bits_entries_3_opcode","width":12},{"name":"trace_bits_entries_3_payload","width":64},{"name":"trace_bits_entries_3_pc","width":64},{"name":"trace_bits_entries_3_rob_bid","width":8},{"name":"trace_bits_entries_3_rob_brobGeneration","width":16},{"name":"trace_bits_entries_3_rob_memberIndex","width":2},{"name":"trace_bits_entries_3_rob_peId","width":8},{"name":"trace_bits_entries_3_rob_residentGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridGeneration","width":16},{"name":"trace_bits_entries_3_rob_ridSlot","width":6},{"name":"trace_bits_entries_3_rob_stid","width":1},{"name":"trace_bits_entries_3_robValid","width":1},{"name":"trace_bits_entries_3_source","width":3},{"name":"trace_bits_entries_4_cycle","width":64},{"name":"trace_bits_entries_4_instruction_epoch","width":16},{"name":"trace_bits_entries_4_instruction_instructionId","width":64},{"name":"trace_bits_entries_4_instruction_peId","width":8},{"name":"trace_bits_entries_4_instruction_stid","width":1},{"name":"trace_bits_entries_4_instructionValid","width":1},{"name":"trace_bits_entries_4_kind","width":3},{"name":"trace_bits_entries_4_opcode","width":12},{"name":"trace_bits_entries_4_payload","width":64},{"name":"trace_bits_entries_4_pc","width":64},{"name":"trace_bits_entries_4_rob_bid","width":8},{"name":"trace_bits_entries_4_rob_brobGeneration","width":16},{"name":"trace_bits_entries_4_rob_memberIndex","width":2},{"name":"trace_bits_entries_4_rob_peId","width":8},{"name":"trace_bits_entries_4_rob_residentGeneration","width":16},{"name":"trace_bits_entries_4_rob_ridGeneration","width":16},{"name":"trace_bits_entries_4_rob_ridSlot","width":6},{"name":"trace_bits_entries_4_rob_stid","width":1},{"name":"trace_bits_entries_4_robValid","width":1},{"name":"trace_bits_entries_4_source","width":3},{"name":"trace_bits_entries_5_cycle","width":64},{"name":"trace_bits_entries_5_instruction_epoch","width":16},{"name":"trace_bits_entries_5_instruction_instructionId","width":64},{"name":"trace_bits_entries_5_instruction_peId","width":8},{"name":"trace_bits_entries_5_instruction_stid","width":1},{"name":"trace_bits_entries_5_instructionValid","width":1},{"name":"trace_bits_entries_5_kind","width":3},{"name":"trace_bits_entries_5_opcode","width":12},{"name":"trace_bits_entries_5_payload","width":64},{"name":"trace_bits_entries_5_pc","width":64},{"name":"trace_bits_entries_5_rob_bid","width":8},{"name":"trace_bits_entries_5_rob_brobGeneration","width":16},{"name":"trace_bits_entries_5_rob_memberIndex","width":2},{"name":"trace_bits_entries_5_rob_peId","width":8},{"name":"trace_bits_entries_5_rob_residentGeneration","width":16},{"name":"trace_bits_entries_5_rob_ridGeneration","width":16},{"name":"trace_bits_entries_5_rob_ridSlot","width":6},{"name":"trace_bits_entries_5_rob_stid","width":1},{"name":"trace_bits_entries_5_robValid","width":1},{"name":"trace_bits_entries_5_source","width":3},{"name":"trace_bits_entries_6_cycle","width":64},{"name":"trace_bits_entries_6_instruction_epoch","width":16},{"name":"trace_bits_entries_6_instruction_instructionId","width":64},{"name":"trace_bits_entries_6_instruction_peId","width":8},{"name":"trace_bits_entries_6_instruction_stid","width":1},{"name":"trace_bits_entries_6_instructionValid","width":1},{"name":"trace_bits_entries_6_kind","width":3},{"name":"trace_bits_entries_6_opcode","width":12},{"name":"trace_bits_entries_6_payload","width":64},{"name":"trace_bits_entries_6_pc","width":64},{"name":"trace_bits_entries_6_rob_bid","width":8},{"name":"trace_bits_entries_6_rob_brobGeneration","width":16},{"name":"trace_bits_entries_6_rob_memberIndex","width":2},{"name":"trace_bits_entries_6_rob_peId","width":8},{"name":"trace_bits_entries_6_rob_residentGeneration","width":16},{"name":"trace_bits_entries_6_rob_ridGeneration","width":16},{"name":"trace_bits_entries_6_rob_ridSlot","width":6},{"name":"trace_bits_entries_6_rob_stid","width":1},{"name":"trace_bits_entries_6_robValid","width":1},{"name":"trace_bits_entries_6_source","width":3},{"name":"trace_bits_entries_7_cycle","width":64},{"name":"trace_bits_entries_7_instruction_epoch","width":16},{"name":"trace_bits_entries_7_instruction_instructionId","width":64},{"name":"trace_bits_entries_7_instruction_peId","width":8},{"name":"trace_bits_entries_7_instruction_stid","width":1},{"name":"trace_bits_entries_7_instructionValid","width":1},{"name":"trace_bits_entries_7_kind","width":3},{"name":"trace_bits_entries_7_opcode","width":12},{"name":"trace_bits_entries_7_payload","width":64},{"name":"trace_bits_entries_7_pc","width":64},{"name":"trace_bits_entries_7_rob_bid","width":8},{"name":"trace_bits_entries_7_rob_brobGeneration","width":16},{"name":"trace_bits_entries_7_rob_memberIndex","width":2},{"name":"trace_bits_entries_7_rob_peId","width":8},{"name":"trace_bits_entries_7_rob_residentGeneration","width":16},{"name":"trace_bits_entries_7_rob_ridGeneration","width":16},{"name":"trace_bits_entries_7_rob_ridSlot","width":6},{"name":"trace_bits_entries_7_rob_stid","width":1},{"name":"trace_bits_entries_7_robValid","width":1},{"name":"trace_bits_entries_7_source","width":3},{"name":"trace_ready","width":1},{"name":"trace_valid","width":1},{"name":"trap_bits_cause","width":32},{"name":"trap_bits_instruction_epoch","width":16},{"name":"trap_bits_instruction_instructionId","width":64},{"name":"trap_bits_instruction_peId","width":8},{"name":"trap_bits_instruction_stid","width":1},{"name":"trap_bits_kind","width":2},{"name":"trap_bits_rob_bid","width":8},{"name":"trap_bits_rob_brobGeneration","width":16},{"name":"trap_bits_rob_memberIndex","width":2},{"name":"trap_bits_rob_peId","width":8},{"name":"trap_bits_rob_residentGeneration","width":16},{"name":"trap_bits_rob_ridGeneration","width":16},{"name":"trap_bits_rob_ridSlot","width":6},{"name":"trap_bits_rob_stid","width":1},{"name":"trap_bits_targetPc","width":64},{"name":"trap_bits_tval","width":64},{"name":"trap_bits_valid","width":1},{"name":"trap_ready","width":1},{"name":"trap_valid","width":1}]},{"name":"ifu_to_ctu","contract_id":"IFC-IFU-CTU-001","producer":"IFU","consumer":"CTU","lanes":8,"payload":"FetchedPacket","ports":[{"name":"count","width":4},{"name":"entries_0_fetchFault","width":1},{"name":"entries_0_fetchFaultCause","width":32},{"name":"entries_0_identity_epoch","width":16},{"name":"entries_0_identity_instructionId","width":64},{"name":"entries_0_identity_peId","width":8},{"name":"entries_0_identity_stid","width":1},{"name":"entries_0_instruction","width":64},{"name":"entries_0_lengthBytes","width":4},{"name":"entries_0_pc","width":64},{"name":"entries_0_prediction_checkpointId","width":5},{"name":"entries_0_prediction_confidence","width":2},{"name":"entries_0_prediction_epoch","width":16},{"name":"entries_0_prediction_fallthroughPc","width":64},{"name":"entries_0_prediction_kind","width":3},{"name":"entries_0_prediction_predictionTag","width":64},{"name":"entries_0_prediction_provider","width":4},{"name":"entries_0_prediction_requestPc","width":64},{"name":"entries_0_prediction_taken","width":1},{"name":"entries_0_prediction_target","width":64},{"name":"entries_0_prediction_transactionId","width":64},{"name":"entries_0_prediction_valid","width":1},{"name":"entries_1_fetchFault","width":1},{"name":"entries_1_fetchFaultCause","width":32},{"name":"entries_1_identity_epoch","width":16},{"name":"entries_1_identity_instructionId","width":64},{"name":"entries_1_identity_peId","width":8},{"name":"entries_1_identity_stid","width":1},{"name":"entries_1_instruction","width":64},{"name":"entries_1_lengthBytes","width":4},{"name":"entries_1_pc","width":64},{"name":"entries_1_prediction_checkpointId","width":5},{"name":"entries_1_prediction_confidence","width":2},{"name":"entries_1_prediction_epoch","width":16},{"name":"entries_1_prediction_fallthroughPc","width":64},{"name":"entries_1_prediction_kind","width":3},{"name":"entries_1_prediction_predictionTag","width":64},{"name":"entries_1_prediction_provider","width":4},{"name":"entries_1_prediction_requestPc","width":64},{"name":"entries_1_prediction_taken","width":1},{"name":"entries_1_prediction_target","width":64},{"name":"entries_1_prediction_transactionId","width":64},{"name":"entries_1_prediction_valid","width":1},{"name":"entries_2_fetchFault","width":1},{"name":"entries_2_fetchFaultCause","width":32},{"name":"entries_2_identity_epoch","width":16},{"name":"entries_2_identity_instructionId","width":64},{"name":"entries_2_identity_peId","width":8},{"name":"entries_2_identity_stid","width":1},{"name":"entries_2_instruction","width":64},{"name":"entries_2_lengthBytes","width":4},{"name":"entries_2_pc","width":64},{"name":"entries_2_prediction_checkpointId","width":5},{"name":"entries_2_prediction_confidence","width":2},{"name":"entries_2_prediction_epoch","width":16},{"name":"entries_2_prediction_fallthroughPc","width":64},{"name":"entries_2_prediction_kind","width":3},{"name":"entries_2_prediction_predictionTag","width":64},{"name":"entries_2_prediction_provider","width":4},{"name":"entries_2_prediction_requestPc","width":64},{"name":"entries_2_prediction_taken","width":1},{"name":"entries_2_prediction_target","width":64},{"name":"entries_2_prediction_transactionId","width":64},{"name":"entries_2_prediction_valid","width":1},{"name":"entries_3_fetchFault","width":1},{"name":"entries_3_fetchFaultCause","width":32},{"name":"entries_3_identity_epoch","width":16},{"name":"entries_3_identity_instructionId","width":64},{"name":"entries_3_identity_peId","width":8},{"name":"entries_3_identity_stid","width":1},{"name":"entries_3_instruction","width":64},{"name":"entries_3_lengthBytes","width":4},{"name":"entries_3_pc","width":64},{"name":"entries_3_prediction_checkpointId","width":5},{"name":"entries_3_prediction_confidence","width":2},{"name":"entries_3_prediction_epoch","width":16},{"name":"entries_3_prediction_fallthroughPc","width":64},{"name":"entries_3_prediction_kind","width":3},{"name":"entries_3_prediction_predictionTag","width":64},{"name":"entries_3_prediction_provider","width":4},{"name":"entries_3_prediction_requestPc","width":64},{"name":"entries_3_prediction_taken","width":1},{"name":"entries_3_prediction_target","width":64},{"name":"entries_3_prediction_transactionId","width":64},{"name":"entries_3_prediction_valid","width":1},{"name":"entries_4_fetchFault","width":1},{"name":"entries_4_fetchFaultCause","width":32},{"name":"entries_4_identity_epoch","width":16},{"name":"entries_4_identity_instructionId","width":64},{"name":"entries_4_identity_peId","width":8},{"name":"entries_4_identity_stid","width":1},{"name":"entries_4_instruction","width":64},{"name":"entries_4_lengthBytes","width":4},{"name":"entries_4_pc","width":64},{"name":"entries_4_prediction_checkpointId","width":5},{"name":"entries_4_prediction_confidence","width":2},{"name":"entries_4_prediction_epoch","width":16},{"name":"entries_4_prediction_fallthroughPc","width":64},{"name":"entries_4_prediction_kind","width":3},{"name":"entries_4_prediction_predictionTag","width":64},{"name":"entries_4_prediction_provider","width":4},{"name":"entries_4_prediction_requestPc","width":64},{"name":"entries_4_prediction_taken","width":1},{"name":"entries_4_prediction_target","width":64},{"name":"entries_4_prediction_transactionId","width":64},{"name":"entries_4_prediction_valid","width":1},{"name":"entries_5_fetchFault","width":1},{"name":"entries_5_fetchFaultCause","width":32},{"name":"entries_5_identity_epoch","width":16},{"name":"entries_5_identity_instructionId","width":64},{"name":"entries_5_identity_peId","width":8},{"name":"entries_5_identity_stid","width":1},{"name":"entries_5_instruction","width":64},{"name":"entries_5_lengthBytes","width":4},{"name":"entries_5_pc","width":64},{"name":"entries_5_prediction_checkpointId","width":5},{"name":"entries_5_prediction_confidence","width":2},{"name":"entries_5_prediction_epoch","width":16},{"name":"entries_5_prediction_fallthroughPc","width":64},{"name":"entries_5_prediction_kind","width":3},{"name":"entries_5_prediction_predictionTag","width":64},{"name":"entries_5_prediction_provider","width":4},{"name":"entries_5_prediction_requestPc","width":64},{"name":"entries_5_prediction_taken","width":1},{"name":"entries_5_prediction_target","width":64},{"name":"entries_5_prediction_transactionId","width":64},{"name":"entries_5_prediction_valid","width":1},{"name":"entries_6_fetchFault","width":1},{"name":"entries_6_fetchFaultCause","width":32},{"name":"entries_6_identity_epoch","width":16},{"name":"entries_6_identity_instructionId","width":64},{"name":"entries_6_identity_peId","width":8},{"name":"entries_6_identity_stid","width":1},{"name":"entries_6_instruction","width":64},{"name":"entries_6_lengthBytes","width":4},{"name":"entries_6_pc","width":64},{"name":"entries_6_prediction_checkpointId","width":5},{"name":"entries_6_prediction_confidence","width":2},{"name":"entries_6_prediction_epoch","width":16},{"name":"entries_6_prediction_fallthroughPc","width":64},{"name":"entries_6_prediction_kind","width":3},{"name":"entries_6_prediction_predictionTag","width":64},{"name":"entries_6_prediction_provider","width":4},{"name":"entries_6_prediction_requestPc","width":64},{"name":"entries_6_prediction_taken","width":1},{"name":"entries_6_prediction_target","width":64},{"name":"entries_6_prediction_transactionId","width":64},{"name":"entries_6_prediction_valid","width":1},{"name":"entries_7_fetchFault","width":1},{"name":"entries_7_fetchFaultCause","width":32},{"name":"entries_7_identity_epoch","width":16},{"name":"entries_7_identity_instructionId","width":64},{"name":"entries_7_identity_peId","width":8},{"name":"entries_7_identity_stid","width":1},{"name":"entries_7_instruction","width":64},{"name":"entries_7_lengthBytes","width":4},{"name":"entries_7_pc","width":64},{"name":"entries_7_prediction_checkpointId","width":5},{"name":"entries_7_prediction_confidence","width":2},{"name":"entries_7_prediction_epoch","width":16},{"name":"entries_7_prediction_fallthroughPc","width":64},{"name":"entries_7_prediction_kind","width":3},{"name":"entries_7_prediction_predictionTag","width":64},{"name":"entries_7_prediction_provider","width":4},{"name":"entries_7_prediction_requestPc","width":64},{"name":"entries_7_prediction_taken","width":1},{"name":"entries_7_prediction_target","width":64},{"name":"entries_7_prediction_transactionId","width":64},{"name":"entries_7_prediction_valid","width":1}]},{"name":"ctu_to_ooo","contract_id":"IFC-CTU-OOO-001","producer":"CTU","consumer":"OOO","lanes":8,"payload":"D1Packet","ports":[{"name":"count","width":4},{"name":"entries_0_kind","width":1},{"name":"entries_0_parent_fetchFault","width":1},{"name":"entries_0_parent_fetchFaultCause","width":32},{"name":"entries_0_parent_identity_epoch","width":16},{"name":"entries_0_parent_identity_instructionId","width":64},{"name":"entries_0_parent_identity_peId","width":8},{"name":"entries_0_parent_identity_stid","width":1},{"name":"entries_0_parent_instruction","width":64},{"name":"entries_0_parent_lengthBytes","width":4},{"name":"entries_0_parent_pc","width":64},{"name":"entries_0_parent_prediction_checkpointId","width":5},{"name":"entries_0_parent_prediction_confidence","width":2},{"name":"entries_0_parent_prediction_epoch","width":16},{"name":"entries_0_parent_prediction_fallthroughPc","width":64},{"name":"entries_0_parent_prediction_kind","width":3},{"name":"entries_0_parent_prediction_predictionTag","width":64},{"name":"entries_0_parent_prediction_provider","width":4},{"name":"entries_0_parent_prediction_requestPc","width":64},{"name":"entries_0_parent_prediction_taken","width":1},{"name":"entries_0_parent_prediction_target","width":64},{"name":"entries_0_parent_prediction_transactionId","width":64},{"name":"entries_0_parent_prediction_valid","width":1},{"name":"entries_0_templateCount","width":8},{"name":"entries_0_templateImmediate","width":64},{"name":"entries_0_templateOpcode","width":12},{"name":"entries_0_templateOrdinal","width":8},{"name":"entries_1_kind","width":1},{"name":"entries_1_parent_fetchFault","width":1},{"name":"entries_1_parent_fetchFaultCause","width":32},{"name":"entries_1_parent_identity_epoch","width":16},{"name":"entries_1_parent_identity_instructionId","width":64},{"name":"entries_1_parent_identity_peId","width":8},{"name":"entries_1_parent_identity_stid","width":1},{"name":"entries_1_parent_instruction","width":64},{"name":"entries_1_parent_lengthBytes","width":4},{"name":"entries_1_parent_pc","width":64},{"name":"entries_1_parent_prediction_checkpointId","width":5},{"name":"entries_1_parent_prediction_confidence","width":2},{"name":"entries_1_parent_prediction_epoch","width":16},{"name":"entries_1_parent_prediction_fallthroughPc","width":64},{"name":"entries_1_parent_prediction_kind","width":3},{"name":"entries_1_parent_prediction_predictionTag","width":64},{"name":"entries_1_parent_prediction_provider","width":4},{"name":"entries_1_parent_prediction_requestPc","width":64},{"name":"entries_1_parent_prediction_taken","width":1},{"name":"entries_1_parent_prediction_target","width":64},{"name":"entries_1_parent_prediction_transactionId","width":64},{"name":"entries_1_parent_prediction_valid","width":1},{"name":"entries_1_templateCount","width":8},{"name":"entries_1_templateImmediate","width":64},{"name":"entries_1_templateOpcode","width":12},{"name":"entries_1_templateOrdinal","width":8},{"name":"entries_2_kind","width":1},{"name":"entries_2_parent_fetchFault","width":1},{"name":"entries_2_parent_fetchFaultCause","width":32},{"name":"entries_2_parent_identity_epoch","width":16},{"name":"entries_2_parent_identity_instructionId","width":64},{"name":"entries_2_parent_identity_peId","width":8},{"name":"entries_2_parent_identity_stid","width":1},{"name":"entries_2_parent_instruction","width":64},{"name":"entries_2_parent_lengthBytes","width":4},{"name":"entries_2_parent_pc","width":64},{"name":"entries_2_parent_prediction_checkpointId","width":5},{"name":"entries_2_parent_prediction_confidence","width":2},{"name":"entries_2_parent_prediction_epoch","width":16},{"name":"entries_2_parent_prediction_fallthroughPc","width":64},{"name":"entries_2_parent_prediction_kind","width":3},{"name":"entries_2_parent_prediction_predictionTag","width":64},{"name":"entries_2_parent_prediction_provider","width":4},{"name":"entries_2_parent_prediction_requestPc","width":64},{"name":"entries_2_parent_prediction_taken","width":1},{"name":"entries_2_parent_prediction_target","width":64},{"name":"entries_2_parent_prediction_transactionId","width":64},{"name":"entries_2_parent_prediction_valid","width":1},{"name":"entries_2_templateCount","width":8},{"name":"entries_2_templateImmediate","width":64},{"name":"entries_2_templateOpcode","width":12},{"name":"entries_2_templateOrdinal","width":8},{"name":"entries_3_kind","width":1},{"name":"entries_3_parent_fetchFault","width":1},{"name":"entries_3_parent_fetchFaultCause","width":32},{"name":"entries_3_parent_identity_epoch","width":16},{"name":"entries_3_parent_identity_instructionId","width":64},{"name":"entries_3_parent_identity_peId","width":8},{"name":"entries_3_parent_identity_stid","width":1},{"name":"entries_3_parent_instruction","width":64},{"name":"entries_3_parent_lengthBytes","width":4},{"name":"entries_3_parent_pc","width":64},{"name":"entries_3_parent_prediction_checkpointId","width":5},{"name":"entries_3_parent_prediction_confidence","width":2},{"name":"entries_3_parent_prediction_epoch","width":16},{"name":"entries_3_parent_prediction_fallthroughPc","width":64},{"name":"entries_3_parent_prediction_kind","width":3},{"name":"entries_3_parent_prediction_predictionTag","width":64},{"name":"entries_3_parent_prediction_provider","width":4},{"name":"entries_3_parent_prediction_requestPc","width":64},{"name":"entries_3_parent_prediction_taken","width":1},{"name":"entries_3_parent_prediction_target","width":64},{"name":"entries_3_parent_prediction_transactionId","width":64},{"name":"entries_3_parent_prediction_valid","width":1},{"name":"entries_3_templateCount","width":8},{"name":"entries_3_templateImmediate","width":64},{"name":"entries_3_templateOpcode","width":12},{"name":"entries_3_templateOrdinal","width":8},{"name":"entries_4_kind","width":1},{"name":"entries_4_parent_fetchFault","width":1},{"name":"entries_4_parent_fetchFaultCause","width":32},{"name":"entries_4_parent_identity_epoch","width":16},{"name":"entries_4_parent_identity_instructionId","width":64},{"name":"entries_4_parent_identity_peId","width":8},{"name":"entries_4_parent_identity_stid","width":1},{"name":"entries_4_parent_instruction","width":64},{"name":"entries_4_parent_lengthBytes","width":4},{"name":"entries_4_parent_pc","width":64},{"name":"entries_4_parent_prediction_checkpointId","width":5},{"name":"entries_4_parent_prediction_confidence","width":2},{"name":"entries_4_parent_prediction_epoch","width":16},{"name":"entries_4_parent_prediction_fallthroughPc","width":64},{"name":"entries_4_parent_prediction_kind","width":3},{"name":"entries_4_parent_prediction_predictionTag","width":64},{"name":"entries_4_parent_prediction_provider","width":4},{"name":"entries_4_parent_prediction_requestPc","width":64},{"name":"entries_4_parent_prediction_taken","width":1},{"name":"entries_4_parent_prediction_target","width":64},{"name":"entries_4_parent_prediction_transactionId","width":64},{"name":"entries_4_parent_prediction_valid","width":1},{"name":"entries_4_templateCount","width":8},{"name":"entries_4_templateImmediate","width":64},{"name":"entries_4_templateOpcode","width":12},{"name":"entries_4_templateOrdinal","width":8},{"name":"entries_5_kind","width":1},{"name":"entries_5_parent_fetchFault","width":1},{"name":"entries_5_parent_fetchFaultCause","width":32},{"name":"entries_5_parent_identity_epoch","width":16},{"name":"entries_5_parent_identity_instructionId","width":64},{"name":"entries_5_parent_identity_peId","width":8},{"name":"entries_5_parent_identity_stid","width":1},{"name":"entries_5_parent_instruction","width":64},{"name":"entries_5_parent_lengthBytes","width":4},{"name":"entries_5_parent_pc","width":64},{"name":"entries_5_parent_prediction_checkpointId","width":5},{"name":"entries_5_parent_prediction_confidence","width":2},{"name":"entries_5_parent_prediction_epoch","width":16},{"name":"entries_5_parent_prediction_fallthroughPc","width":64},{"name":"entries_5_parent_prediction_kind","width":3},{"name":"entries_5_parent_prediction_predictionTag","width":64},{"name":"entries_5_parent_prediction_provider","width":4},{"name":"entries_5_parent_prediction_requestPc","width":64},{"name":"entries_5_parent_prediction_taken","width":1},{"name":"entries_5_parent_prediction_target","width":64},{"name":"entries_5_parent_prediction_transactionId","width":64},{"name":"entries_5_parent_prediction_valid","width":1},{"name":"entries_5_templateCount","width":8},{"name":"entries_5_templateImmediate","width":64},{"name":"entries_5_templateOpcode","width":12},{"name":"entries_5_templateOrdinal","width":8},{"name":"entries_6_kind","width":1},{"name":"entries_6_parent_fetchFault","width":1},{"name":"entries_6_parent_fetchFaultCause","width":32},{"name":"entries_6_parent_identity_epoch","width":16},{"name":"entries_6_parent_identity_instructionId","width":64},{"name":"entries_6_parent_identity_peId","width":8},{"name":"entries_6_parent_identity_stid","width":1},{"name":"entries_6_parent_instruction","width":64},{"name":"entries_6_parent_lengthBytes","width":4},{"name":"entries_6_parent_pc","width":64},{"name":"entries_6_parent_prediction_checkpointId","width":5},{"name":"entries_6_parent_prediction_confidence","width":2},{"name":"entries_6_parent_prediction_epoch","width":16},{"name":"entries_6_parent_prediction_fallthroughPc","width":64},{"name":"entries_6_parent_prediction_kind","width":3},{"name":"entries_6_parent_prediction_predictionTag","width":64},{"name":"entries_6_parent_prediction_provider","width":4},{"name":"entries_6_parent_prediction_requestPc","width":64},{"name":"entries_6_parent_prediction_taken","width":1},{"name":"entries_6_parent_prediction_target","width":64},{"name":"entries_6_parent_prediction_transactionId","width":64},{"name":"entries_6_parent_prediction_valid","width":1},{"name":"entries_6_templateCount","width":8},{"name":"entries_6_templateImmediate","width":64},{"name":"entries_6_templateOpcode","width":12},{"name":"entries_6_templateOrdinal","width":8},{"name":"entries_7_kind","width":1},{"name":"entries_7_parent_fetchFault","width":1},{"name":"entries_7_parent_fetchFaultCause","width":32},{"name":"entries_7_parent_identity_epoch","width":16},{"name":"entries_7_parent_identity_instructionId","width":64},{"name":"entries_7_parent_identity_peId","width":8},{"name":"entries_7_parent_identity_stid","width":1},{"name":"entries_7_parent_instruction","width":64},{"name":"entries_7_parent_lengthBytes","width":4},{"name":"entries_7_parent_pc","width":64},{"name":"entries_7_parent_prediction_checkpointId","width":5},{"name":"entries_7_parent_prediction_confidence","width":2},{"name":"entries_7_parent_prediction_epoch","width":16},{"name":"entries_7_parent_prediction_fallthroughPc","width":64},{"name":"entries_7_parent_prediction_kind","width":3},{"name":"entries_7_parent_prediction_predictionTag","width":64},{"name":"entries_7_parent_prediction_provider","width":4},{"name":"entries_7_parent_prediction_requestPc","width":64},{"name":"entries_7_parent_prediction_taken","width":1},{"name":"entries_7_parent_prediction_target","width":64},{"name":"entries_7_parent_prediction_transactionId","width":64},{"name":"entries_7_parent_prediction_valid","width":1},{"name":"entries_7_templateCount","width":8},{"name":"entries_7_templateImmediate","width":64},{"name":"entries_7_templateOpcode","width":12},{"name":"entries_7_templateOrdinal","width":8}]},{"name":"ooo_to_iex_alu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":4},{"name":"uop_decoded_classification_dispatchDemand_1","width":4},{"name":"uop_decoded_classification_dispatchDemand_2","width":4},{"name":"uop_decoded_classification_dispatchDemand_3","width":4},{"name":"uop_decoded_classification_dispatchDemand_4","width":4},{"name":"uop_decoded_classification_dispatchDemand_5","width":4},{"name":"uop_decoded_classification_dispatchDemand_6","width":4},{"name":"uop_decoded_classification_dispatchDemand_7","width":4},{"name":"uop_decoded_classification_dispatchWrites","width":4},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_bru","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":4},{"name":"uop_decoded_classification_dispatchDemand_1","width":4},{"name":"uop_decoded_classification_dispatchDemand_2","width":4},{"name":"uop_decoded_classification_dispatchDemand_3","width":4},{"name":"uop_decoded_classification_dispatchDemand_4","width":4},{"name":"uop_decoded_classification_dispatchDemand_5","width":4},{"name":"uop_decoded_classification_dispatchDemand_6","width":4},{"name":"uop_decoded_classification_dispatchDemand_7","width":4},{"name":"uop_decoded_classification_dispatchWrites","width":4},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_agu","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":4},{"name":"uop_decoded_classification_dispatchDemand_1","width":4},{"name":"uop_decoded_classification_dispatchDemand_2","width":4},{"name":"uop_decoded_classification_dispatchDemand_3","width":4},{"name":"uop_decoded_classification_dispatchDemand_4","width":4},{"name":"uop_decoded_classification_dispatchDemand_5","width":4},{"name":"uop_decoded_classification_dispatchDemand_6","width":4},{"name":"uop_decoded_classification_dispatchDemand_7","width":4},{"name":"uop_decoded_classification_dispatchWrites","width":4},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_std","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":2,"payload":"StoreDispatchTxn","ports":[{"name":"aguPipe","width":1},{"name":"sta_memoryOrder_firstLid","width":32},{"name":"sta_memoryOrder_firstLsid","width":32},{"name":"sta_memoryOrder_firstSid","width":32},{"name":"sta_memoryOrder_requestCount","width":2},{"name":"sta_memoryOrder_yoldLid","width":32},{"name":"sta_memoryOrder_yoldLsid","width":32},{"name":"sta_memoryOrder_yoldValid","width":1},{"name":"sta_memoryOrder_yostLsid","width":32},{"name":"sta_memoryOrder_yostSid","width":32},{"name":"sta_memoryOrder_yostValid","width":1},{"name":"sta_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"sta_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"sta_pcBufferIndexOffset_pcOffset","width":7},{"name":"sta_pcBufferIndexOffset_valid","width":1},{"name":"sta_transactionId","width":64},{"name":"sta_trap_cause","width":32},{"name":"sta_trap_valid","width":1},{"name":"sta_uop_decoded_blockBoundary","width":1},{"name":"sta_uop_decoded_blockStart","width":1},{"name":"sta_uop_decoded_blockStop","width":1},{"name":"sta_uop_decoded_classification_complexBreak","width":1},{"name":"sta_uop_decoded_classification_dispatchClass","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_0","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_1","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_2","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_3","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_4","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_5","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_6","width":4},{"name":"sta_uop_decoded_classification_dispatchDemand_7","width":4},{"name":"sta_uop_decoded_classification_dispatchWrites","width":4},{"name":"sta_uop_decoded_classification_disposition","width":2},{"name":"sta_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"sta_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"sta_uop_decoded_classification_fastResolveClass","width":3},{"name":"sta_uop_decoded_classification_fusionHeadClass","width":2},{"name":"sta_uop_decoded_classification_fusionTailClass","width":2},{"name":"sta_uop_decoded_classification_implicitDestination","width":2},{"name":"sta_uop_decoded_classification_implicitSourceMask","width":4},{"name":"sta_uop_decoded_classification_kind","width":4},{"name":"sta_uop_decoded_classification_mayRedirect","width":1},{"name":"sta_uop_decoded_classification_mayTrap","width":1},{"name":"sta_uop_decoded_classification_mayTrapLate","width":1},{"name":"sta_uop_decoded_classification_memoryRequestCount","width":2},{"name":"sta_uop_decoded_classification_nonspeculative","width":1},{"name":"sta_uop_decoded_classification_pDestinationCount","width":2},{"name":"sta_uop_decoded_classification_pSourceCount","width":3},{"name":"sta_uop_decoded_classification_pcReadClass","width":4},{"name":"sta_uop_decoded_classification_pcReadRequired","width":1},{"name":"sta_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"sta_uop_decoded_classification_sideEffectOwner","width":3},{"name":"sta_uop_decoded_classification_splitKind","width":2},{"name":"sta_uop_decoded_classification_tAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uAllocationCount","width":2},{"name":"sta_uop_decoded_classification_uopCountMax","width":6},{"name":"sta_uop_decoded_classification_uopCountMin","width":6},{"name":"sta_uop_decoded_classification_valid","width":1},{"name":"sta_uop_decoded_destinations_0_atag","width":6},{"name":"sta_uop_decoded_destinations_0_kind","width":3},{"name":"sta_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_0_valid","width":1},{"name":"sta_uop_decoded_destinations_1_atag","width":6},{"name":"sta_uop_decoded_destinations_1_kind","width":3},{"name":"sta_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"sta_uop_decoded_destinations_1_valid","width":1},{"name":"sta_uop_decoded_earlyComplete","width":1},{"name":"sta_uop_decoded_immediate","width":64},{"name":"sta_uop_decoded_immediateValid","width":1},{"name":"sta_uop_decoded_instruction_kind","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"sta_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"sta_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"sta_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"sta_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"sta_uop_decoded_instruction_parent_instruction","width":64},{"name":"sta_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"sta_uop_decoded_instruction_parent_pc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"sta_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"sta_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"sta_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"sta_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"sta_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"sta_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"sta_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"sta_uop_decoded_instruction_templateCount","width":8},{"name":"sta_uop_decoded_instruction_templateImmediate","width":64},{"name":"sta_uop_decoded_instruction_templateOpcode","width":12},{"name":"sta_uop_decoded_instruction_templateOrdinal","width":8},{"name":"sta_uop_decoded_memory_accessBytes","width":4},{"name":"sta_uop_decoded_memory_addressMode","width":2},{"name":"sta_uop_decoded_memory_addressSourceMask","width":4},{"name":"sta_uop_decoded_memory_dataSourceMask","width":4},{"name":"sta_uop_decoded_memory_indexMode","width":2},{"name":"sta_uop_decoded_memory_indexShift","width":5},{"name":"sta_uop_decoded_memory_isLoad","width":1},{"name":"sta_uop_decoded_memory_isStore","width":1},{"name":"sta_uop_decoded_memory_offset","width":64},{"name":"sta_uop_decoded_memory_requestCount","width":2},{"name":"sta_uop_decoded_memory_signExtend","width":1},{"name":"sta_uop_decoded_memory_valid","width":1},{"name":"sta_uop_decoded_memory_writebackPreIndex","width":1},{"name":"sta_uop_decoded_memory_writebackValid","width":1},{"name":"sta_uop_decoded_opcode","width":12},{"name":"sta_uop_decoded_rob_bid","width":8},{"name":"sta_uop_decoded_rob_brobGeneration","width":16},{"name":"sta_uop_decoded_rob_memberIndex","width":2},{"name":"sta_uop_decoded_rob_peId","width":8},{"name":"sta_uop_decoded_rob_residentGeneration","width":16},{"name":"sta_uop_decoded_rob_ridGeneration","width":16},{"name":"sta_uop_decoded_rob_ridSlot","width":6},{"name":"sta_uop_decoded_rob_stid","width":1},{"name":"sta_uop_decoded_sources_0_atag","width":6},{"name":"sta_uop_decoded_sources_0_kind","width":3},{"name":"sta_uop_decoded_sources_0_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_0_valid","width":1},{"name":"sta_uop_decoded_sources_1_atag","width":6},{"name":"sta_uop_decoded_sources_1_kind","width":3},{"name":"sta_uop_decoded_sources_1_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_1_valid","width":1},{"name":"sta_uop_decoded_sources_2_atag","width":6},{"name":"sta_uop_decoded_sources_2_kind","width":3},{"name":"sta_uop_decoded_sources_2_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_2_valid","width":1},{"name":"sta_uop_decoded_sources_3_atag","width":6},{"name":"sta_uop_decoded_sources_3_kind","width":3},{"name":"sta_uop_decoded_sources_3_relativeIndex","width":6},{"name":"sta_uop_decoded_sources_3_valid","width":1},{"name":"sta_uop_decoded_uopClass","width":3},{"name":"sta_uop_decoded_valid","width":1},{"name":"sta_uop_destinations_0_atag","width":6},{"name":"sta_uop_destinations_0_kind","width":3},{"name":"sta_uop_destinations_0_pGeneration","width":16},{"name":"sta_uop_destinations_0_previousPGeneration","width":16},{"name":"sta_uop_destinations_0_previousPtag","width":7},{"name":"sta_uop_destinations_0_previousPtagValid","width":1},{"name":"sta_uop_destinations_0_previousTtag","width":5},{"name":"sta_uop_destinations_0_previousTtagValid","width":1},{"name":"sta_uop_destinations_0_previousUtag","width":5},{"name":"sta_uop_destinations_0_previousUtagValid","width":1},{"name":"sta_uop_destinations_0_ptag","width":7},{"name":"sta_uop_destinations_0_ptagValid","width":1},{"name":"sta_uop_destinations_0_tGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqGeneration","width":16},{"name":"sta_uop_destinations_0_tSeqIndex","width":5},{"name":"sta_uop_destinations_0_ttag","width":5},{"name":"sta_uop_destinations_0_ttagValid","width":1},{"name":"sta_uop_destinations_0_uGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqGeneration","width":16},{"name":"sta_uop_destinations_0_uSeqIndex","width":5},{"name":"sta_uop_destinations_0_utag","width":5},{"name":"sta_uop_destinations_0_utagValid","width":1},{"name":"sta_uop_destinations_0_valid","width":1},{"name":"sta_uop_destinations_1_atag","width":6},{"name":"sta_uop_destinations_1_kind","width":3},{"name":"sta_uop_destinations_1_pGeneration","width":16},{"name":"sta_uop_destinations_1_previousPGeneration","width":16},{"name":"sta_uop_destinations_1_previousPtag","width":7},{"name":"sta_uop_destinations_1_previousPtagValid","width":1},{"name":"sta_uop_destinations_1_previousTtag","width":5},{"name":"sta_uop_destinations_1_previousTtagValid","width":1},{"name":"sta_uop_destinations_1_previousUtag","width":5},{"name":"sta_uop_destinations_1_previousUtagValid","width":1},{"name":"sta_uop_destinations_1_ptag","width":7},{"name":"sta_uop_destinations_1_ptagValid","width":1},{"name":"sta_uop_destinations_1_tGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqGeneration","width":16},{"name":"sta_uop_destinations_1_tSeqIndex","width":5},{"name":"sta_uop_destinations_1_ttag","width":5},{"name":"sta_uop_destinations_1_ttagValid","width":1},{"name":"sta_uop_destinations_1_uGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqGeneration","width":16},{"name":"sta_uop_destinations_1_uSeqIndex","width":5},{"name":"sta_uop_destinations_1_utag","width":5},{"name":"sta_uop_destinations_1_utagValid","width":1},{"name":"sta_uop_destinations_1_valid","width":1},{"name":"sta_uop_sources_0_atag","width":6},{"name":"sta_uop_sources_0_kind","width":3},{"name":"sta_uop_sources_0_pGeneration","width":16},{"name":"sta_uop_sources_0_ptag","width":7},{"name":"sta_uop_sources_0_ptagValid","width":1},{"name":"sta_uop_sources_0_ready","width":1},{"name":"sta_uop_sources_0_tGeneration","width":16},{"name":"sta_uop_sources_0_tSeqGeneration","width":16},{"name":"sta_uop_sources_0_tSeqIndex","width":5},{"name":"sta_uop_sources_0_ttag","width":5},{"name":"sta_uop_sources_0_ttagValid","width":1},{"name":"sta_uop_sources_0_uGeneration","width":16},{"name":"sta_uop_sources_0_uSeqGeneration","width":16},{"name":"sta_uop_sources_0_uSeqIndex","width":5},{"name":"sta_uop_sources_0_utag","width":5},{"name":"sta_uop_sources_0_utagValid","width":1},{"name":"sta_uop_sources_0_valid","width":1},{"name":"sta_uop_sources_1_atag","width":6},{"name":"sta_uop_sources_1_kind","width":3},{"name":"sta_uop_sources_1_pGeneration","width":16},{"name":"sta_uop_sources_1_ptag","width":7},{"name":"sta_uop_sources_1_ptagValid","width":1},{"name":"sta_uop_sources_1_ready","width":1},{"name":"sta_uop_sources_1_tGeneration","width":16},{"name":"sta_uop_sources_1_tSeqGeneration","width":16},{"name":"sta_uop_sources_1_tSeqIndex","width":5},{"name":"sta_uop_sources_1_ttag","width":5},{"name":"sta_uop_sources_1_ttagValid","width":1},{"name":"sta_uop_sources_1_uGeneration","width":16},{"name":"sta_uop_sources_1_uSeqGeneration","width":16},{"name":"sta_uop_sources_1_uSeqIndex","width":5},{"name":"sta_uop_sources_1_utag","width":5},{"name":"sta_uop_sources_1_utagValid","width":1},{"name":"sta_uop_sources_1_valid","width":1},{"name":"sta_uop_sources_2_atag","width":6},{"name":"sta_uop_sources_2_kind","width":3},{"name":"sta_uop_sources_2_pGeneration","width":16},{"name":"sta_uop_sources_2_ptag","width":7},{"name":"sta_uop_sources_2_ptagValid","width":1},{"name":"sta_uop_sources_2_ready","width":1},{"name":"sta_uop_sources_2_tGeneration","width":16},{"name":"sta_uop_sources_2_tSeqGeneration","width":16},{"name":"sta_uop_sources_2_tSeqIndex","width":5},{"name":"sta_uop_sources_2_ttag","width":5},{"name":"sta_uop_sources_2_ttagValid","width":1},{"name":"sta_uop_sources_2_uGeneration","width":16},{"name":"sta_uop_sources_2_uSeqGeneration","width":16},{"name":"sta_uop_sources_2_uSeqIndex","width":5},{"name":"sta_uop_sources_2_utag","width":5},{"name":"sta_uop_sources_2_utagValid","width":1},{"name":"sta_uop_sources_2_valid","width":1},{"name":"sta_uop_sources_3_atag","width":6},{"name":"sta_uop_sources_3_kind","width":3},{"name":"sta_uop_sources_3_pGeneration","width":16},{"name":"sta_uop_sources_3_ptag","width":7},{"name":"sta_uop_sources_3_ptagValid","width":1},{"name":"sta_uop_sources_3_ready","width":1},{"name":"sta_uop_sources_3_tGeneration","width":16},{"name":"sta_uop_sources_3_tSeqGeneration","width":16},{"name":"sta_uop_sources_3_tSeqIndex","width":5},{"name":"sta_uop_sources_3_ttag","width":5},{"name":"sta_uop_sources_3_ttagValid","width":1},{"name":"sta_uop_sources_3_uGeneration","width":16},{"name":"sta_uop_sources_3_uSeqGeneration","width":16},{"name":"sta_uop_sources_3_uSeqIndex","width":5},{"name":"sta_uop_sources_3_utag","width":5},{"name":"sta_uop_sources_3_utagValid","width":1},{"name":"sta_uop_sources_3_valid","width":1},{"name":"std_memoryOrder_firstLid","width":32},{"name":"std_memoryOrder_firstLsid","width":32},{"name":"std_memoryOrder_firstSid","width":32},{"name":"std_memoryOrder_requestCount","width":2},{"name":"std_memoryOrder_yoldLid","width":32},{"name":"std_memoryOrder_yoldLsid","width":32},{"name":"std_memoryOrder_yoldValid","width":1},{"name":"std_memoryOrder_yostLsid","width":32},{"name":"std_memoryOrder_yostSid","width":32},{"name":"std_memoryOrder_yostValid","width":1},{"name":"std_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"std_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"std_pcBufferIndexOffset_pcOffset","width":7},{"name":"std_pcBufferIndexOffset_valid","width":1},{"name":"std_transactionId","width":64},{"name":"std_trap_cause","width":32},{"name":"std_trap_valid","width":1},{"name":"std_uop_decoded_blockBoundary","width":1},{"name":"std_uop_decoded_blockStart","width":1},{"name":"std_uop_decoded_blockStop","width":1},{"name":"std_uop_decoded_classification_complexBreak","width":1},{"name":"std_uop_decoded_classification_dispatchClass","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_0","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_1","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_2","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_3","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_4","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_5","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_6","width":4},{"name":"std_uop_decoded_classification_dispatchDemand_7","width":4},{"name":"std_uop_decoded_classification_dispatchWrites","width":4},{"name":"std_uop_decoded_classification_disposition","width":2},{"name":"std_uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"std_uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"std_uop_decoded_classification_fastResolveClass","width":3},{"name":"std_uop_decoded_classification_fusionHeadClass","width":2},{"name":"std_uop_decoded_classification_fusionTailClass","width":2},{"name":"std_uop_decoded_classification_implicitDestination","width":2},{"name":"std_uop_decoded_classification_implicitSourceMask","width":4},{"name":"std_uop_decoded_classification_kind","width":4},{"name":"std_uop_decoded_classification_mayRedirect","width":1},{"name":"std_uop_decoded_classification_mayTrap","width":1},{"name":"std_uop_decoded_classification_mayTrapLate","width":1},{"name":"std_uop_decoded_classification_memoryRequestCount","width":2},{"name":"std_uop_decoded_classification_nonspeculative","width":1},{"name":"std_uop_decoded_classification_pDestinationCount","width":2},{"name":"std_uop_decoded_classification_pSourceCount","width":3},{"name":"std_uop_decoded_classification_pcReadClass","width":4},{"name":"std_uop_decoded_classification_pcReadRequired","width":1},{"name":"std_uop_decoded_classification_requiresTargetValidation","width":1},{"name":"std_uop_decoded_classification_sideEffectOwner","width":3},{"name":"std_uop_decoded_classification_splitKind","width":2},{"name":"std_uop_decoded_classification_tAllocationCount","width":2},{"name":"std_uop_decoded_classification_uAllocationCount","width":2},{"name":"std_uop_decoded_classification_uopCountMax","width":6},{"name":"std_uop_decoded_classification_uopCountMin","width":6},{"name":"std_uop_decoded_classification_valid","width":1},{"name":"std_uop_decoded_destinations_0_atag","width":6},{"name":"std_uop_decoded_destinations_0_kind","width":3},{"name":"std_uop_decoded_destinations_0_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_0_valid","width":1},{"name":"std_uop_decoded_destinations_1_atag","width":6},{"name":"std_uop_decoded_destinations_1_kind","width":3},{"name":"std_uop_decoded_destinations_1_relativeIndex","width":6},{"name":"std_uop_decoded_destinations_1_valid","width":1},{"name":"std_uop_decoded_earlyComplete","width":1},{"name":"std_uop_decoded_immediate","width":64},{"name":"std_uop_decoded_immediateValid","width":1},{"name":"std_uop_decoded_instruction_kind","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFault","width":1},{"name":"std_uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"std_uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"std_uop_decoded_instruction_parent_identity_peId","width":8},{"name":"std_uop_decoded_instruction_parent_identity_stid","width":1},{"name":"std_uop_decoded_instruction_parent_instruction","width":64},{"name":"std_uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"std_uop_decoded_instruction_parent_pc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"std_uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"std_uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"std_uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"std_uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"std_uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"std_uop_decoded_instruction_parent_prediction_target","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"std_uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"std_uop_decoded_instruction_templateCount","width":8},{"name":"std_uop_decoded_instruction_templateImmediate","width":64},{"name":"std_uop_decoded_instruction_templateOpcode","width":12},{"name":"std_uop_decoded_instruction_templateOrdinal","width":8},{"name":"std_uop_decoded_memory_accessBytes","width":4},{"name":"std_uop_decoded_memory_addressMode","width":2},{"name":"std_uop_decoded_memory_addressSourceMask","width":4},{"name":"std_uop_decoded_memory_dataSourceMask","width":4},{"name":"std_uop_decoded_memory_indexMode","width":2},{"name":"std_uop_decoded_memory_indexShift","width":5},{"name":"std_uop_decoded_memory_isLoad","width":1},{"name":"std_uop_decoded_memory_isStore","width":1},{"name":"std_uop_decoded_memory_offset","width":64},{"name":"std_uop_decoded_memory_requestCount","width":2},{"name":"std_uop_decoded_memory_signExtend","width":1},{"name":"std_uop_decoded_memory_valid","width":1},{"name":"std_uop_decoded_memory_writebackPreIndex","width":1},{"name":"std_uop_decoded_memory_writebackValid","width":1},{"name":"std_uop_decoded_opcode","width":12},{"name":"std_uop_decoded_rob_bid","width":8},{"name":"std_uop_decoded_rob_brobGeneration","width":16},{"name":"std_uop_decoded_rob_memberIndex","width":2},{"name":"std_uop_decoded_rob_peId","width":8},{"name":"std_uop_decoded_rob_residentGeneration","width":16},{"name":"std_uop_decoded_rob_ridGeneration","width":16},{"name":"std_uop_decoded_rob_ridSlot","width":6},{"name":"std_uop_decoded_rob_stid","width":1},{"name":"std_uop_decoded_sources_0_atag","width":6},{"name":"std_uop_decoded_sources_0_kind","width":3},{"name":"std_uop_decoded_sources_0_relativeIndex","width":6},{"name":"std_uop_decoded_sources_0_valid","width":1},{"name":"std_uop_decoded_sources_1_atag","width":6},{"name":"std_uop_decoded_sources_1_kind","width":3},{"name":"std_uop_decoded_sources_1_relativeIndex","width":6},{"name":"std_uop_decoded_sources_1_valid","width":1},{"name":"std_uop_decoded_sources_2_atag","width":6},{"name":"std_uop_decoded_sources_2_kind","width":3},{"name":"std_uop_decoded_sources_2_relativeIndex","width":6},{"name":"std_uop_decoded_sources_2_valid","width":1},{"name":"std_uop_decoded_sources_3_atag","width":6},{"name":"std_uop_decoded_sources_3_kind","width":3},{"name":"std_uop_decoded_sources_3_relativeIndex","width":6},{"name":"std_uop_decoded_sources_3_valid","width":1},{"name":"std_uop_decoded_uopClass","width":3},{"name":"std_uop_decoded_valid","width":1},{"name":"std_uop_destinations_0_atag","width":6},{"name":"std_uop_destinations_0_kind","width":3},{"name":"std_uop_destinations_0_pGeneration","width":16},{"name":"std_uop_destinations_0_previousPGeneration","width":16},{"name":"std_uop_destinations_0_previousPtag","width":7},{"name":"std_uop_destinations_0_previousPtagValid","width":1},{"name":"std_uop_destinations_0_previousTtag","width":5},{"name":"std_uop_destinations_0_previousTtagValid","width":1},{"name":"std_uop_destinations_0_previousUtag","width":5},{"name":"std_uop_destinations_0_previousUtagValid","width":1},{"name":"std_uop_destinations_0_ptag","width":7},{"name":"std_uop_destinations_0_ptagValid","width":1},{"name":"std_uop_destinations_0_tGeneration","width":16},{"name":"std_uop_destinations_0_tSeqGeneration","width":16},{"name":"std_uop_destinations_0_tSeqIndex","width":5},{"name":"std_uop_destinations_0_ttag","width":5},{"name":"std_uop_destinations_0_ttagValid","width":1},{"name":"std_uop_destinations_0_uGeneration","width":16},{"name":"std_uop_destinations_0_uSeqGeneration","width":16},{"name":"std_uop_destinations_0_uSeqIndex","width":5},{"name":"std_uop_destinations_0_utag","width":5},{"name":"std_uop_destinations_0_utagValid","width":1},{"name":"std_uop_destinations_0_valid","width":1},{"name":"std_uop_destinations_1_atag","width":6},{"name":"std_uop_destinations_1_kind","width":3},{"name":"std_uop_destinations_1_pGeneration","width":16},{"name":"std_uop_destinations_1_previousPGeneration","width":16},{"name":"std_uop_destinations_1_previousPtag","width":7},{"name":"std_uop_destinations_1_previousPtagValid","width":1},{"name":"std_uop_destinations_1_previousTtag","width":5},{"name":"std_uop_destinations_1_previousTtagValid","width":1},{"name":"std_uop_destinations_1_previousUtag","width":5},{"name":"std_uop_destinations_1_previousUtagValid","width":1},{"name":"std_uop_destinations_1_ptag","width":7},{"name":"std_uop_destinations_1_ptagValid","width":1},{"name":"std_uop_destinations_1_tGeneration","width":16},{"name":"std_uop_destinations_1_tSeqGeneration","width":16},{"name":"std_uop_destinations_1_tSeqIndex","width":5},{"name":"std_uop_destinations_1_ttag","width":5},{"name":"std_uop_destinations_1_ttagValid","width":1},{"name":"std_uop_destinations_1_uGeneration","width":16},{"name":"std_uop_destinations_1_uSeqGeneration","width":16},{"name":"std_uop_destinations_1_uSeqIndex","width":5},{"name":"std_uop_destinations_1_utag","width":5},{"name":"std_uop_destinations_1_utagValid","width":1},{"name":"std_uop_destinations_1_valid","width":1},{"name":"std_uop_sources_0_atag","width":6},{"name":"std_uop_sources_0_kind","width":3},{"name":"std_uop_sources_0_pGeneration","width":16},{"name":"std_uop_sources_0_ptag","width":7},{"name":"std_uop_sources_0_ptagValid","width":1},{"name":"std_uop_sources_0_ready","width":1},{"name":"std_uop_sources_0_tGeneration","width":16},{"name":"std_uop_sources_0_tSeqGeneration","width":16},{"name":"std_uop_sources_0_tSeqIndex","width":5},{"name":"std_uop_sources_0_ttag","width":5},{"name":"std_uop_sources_0_ttagValid","width":1},{"name":"std_uop_sources_0_uGeneration","width":16},{"name":"std_uop_sources_0_uSeqGeneration","width":16},{"name":"std_uop_sources_0_uSeqIndex","width":5},{"name":"std_uop_sources_0_utag","width":5},{"name":"std_uop_sources_0_utagValid","width":1},{"name":"std_uop_sources_0_valid","width":1},{"name":"std_uop_sources_1_atag","width":6},{"name":"std_uop_sources_1_kind","width":3},{"name":"std_uop_sources_1_pGeneration","width":16},{"name":"std_uop_sources_1_ptag","width":7},{"name":"std_uop_sources_1_ptagValid","width":1},{"name":"std_uop_sources_1_ready","width":1},{"name":"std_uop_sources_1_tGeneration","width":16},{"name":"std_uop_sources_1_tSeqGeneration","width":16},{"name":"std_uop_sources_1_tSeqIndex","width":5},{"name":"std_uop_sources_1_ttag","width":5},{"name":"std_uop_sources_1_ttagValid","width":1},{"name":"std_uop_sources_1_uGeneration","width":16},{"name":"std_uop_sources_1_uSeqGeneration","width":16},{"name":"std_uop_sources_1_uSeqIndex","width":5},{"name":"std_uop_sources_1_utag","width":5},{"name":"std_uop_sources_1_utagValid","width":1},{"name":"std_uop_sources_1_valid","width":1},{"name":"std_uop_sources_2_atag","width":6},{"name":"std_uop_sources_2_kind","width":3},{"name":"std_uop_sources_2_pGeneration","width":16},{"name":"std_uop_sources_2_ptag","width":7},{"name":"std_uop_sources_2_ptagValid","width":1},{"name":"std_uop_sources_2_ready","width":1},{"name":"std_uop_sources_2_tGeneration","width":16},{"name":"std_uop_sources_2_tSeqGeneration","width":16},{"name":"std_uop_sources_2_tSeqIndex","width":5},{"name":"std_uop_sources_2_ttag","width":5},{"name":"std_uop_sources_2_ttagValid","width":1},{"name":"std_uop_sources_2_uGeneration","width":16},{"name":"std_uop_sources_2_uSeqGeneration","width":16},{"name":"std_uop_sources_2_uSeqIndex","width":5},{"name":"std_uop_sources_2_utag","width":5},{"name":"std_uop_sources_2_utagValid","width":1},{"name":"std_uop_sources_2_valid","width":1},{"name":"std_uop_sources_3_atag","width":6},{"name":"std_uop_sources_3_kind","width":3},{"name":"std_uop_sources_3_pGeneration","width":16},{"name":"std_uop_sources_3_ptag","width":7},{"name":"std_uop_sources_3_ptagValid","width":1},{"name":"std_uop_sources_3_ready","width":1},{"name":"std_uop_sources_3_tGeneration","width":16},{"name":"std_uop_sources_3_tSeqGeneration","width":16},{"name":"std_uop_sources_3_tSeqIndex","width":5},{"name":"std_uop_sources_3_ttag","width":5},{"name":"std_uop_sources_3_ttagValid","width":1},{"name":"std_uop_sources_3_uGeneration","width":16},{"name":"std_uop_sources_3_uSeqGeneration","width":16},{"name":"std_uop_sources_3_uSeqIndex","width":5},{"name":"std_uop_sources_3_utag","width":5},{"name":"std_uop_sources_3_utagValid","width":1},{"name":"std_uop_sources_3_valid","width":1},{"name":"stdPipe","width":1}]},{"name":"ooo_to_iex_system","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":4},{"name":"uop_decoded_classification_dispatchDemand_1","width":4},{"name":"uop_decoded_classification_dispatchDemand_2","width":4},{"name":"uop_decoded_classification_dispatchDemand_3","width":4},{"name":"uop_decoded_classification_dispatchDemand_4","width":4},{"name":"uop_decoded_classification_dispatchDemand_5","width":4},{"name":"uop_decoded_classification_dispatchDemand_6","width":4},{"name":"uop_decoded_classification_dispatchDemand_7","width":4},{"name":"uop_decoded_classification_dispatchWrites","width":4},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_cmd","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"DispatchTxn","ports":[{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pcBufferIndexOffset_allocationEpoch","width":16},{"name":"pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"pcBufferIndexOffset_pcOffset","width":7},{"name":"pcBufferIndexOffset_valid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_valid","width":1},{"name":"uop_decoded_blockBoundary","width":1},{"name":"uop_decoded_blockStart","width":1},{"name":"uop_decoded_blockStop","width":1},{"name":"uop_decoded_classification_complexBreak","width":1},{"name":"uop_decoded_classification_dispatchClass","width":4},{"name":"uop_decoded_classification_dispatchDemand_0","width":4},{"name":"uop_decoded_classification_dispatchDemand_1","width":4},{"name":"uop_decoded_classification_dispatchDemand_2","width":4},{"name":"uop_decoded_classification_dispatchDemand_3","width":4},{"name":"uop_decoded_classification_dispatchDemand_4","width":4},{"name":"uop_decoded_classification_dispatchDemand_5","width":4},{"name":"uop_decoded_classification_dispatchDemand_6","width":4},{"name":"uop_decoded_classification_dispatchDemand_7","width":4},{"name":"uop_decoded_classification_dispatchWrites","width":4},{"name":"uop_decoded_classification_disposition","width":2},{"name":"uop_decoded_classification_executionPipeCapability_0","width":10},{"name":"uop_decoded_classification_executionPipeCapability_1","width":10},{"name":"uop_decoded_classification_executionPipeCapability_2","width":10},{"name":"uop_decoded_classification_executionPipeCapability_3","width":10},{"name":"uop_decoded_classification_executionPipeCapability_4","width":10},{"name":"uop_decoded_classification_executionPipeCapability_5","width":10},{"name":"uop_decoded_classification_executionPipeCapability_6","width":10},{"name":"uop_decoded_classification_executionPipeCapability_7","width":10},{"name":"uop_decoded_classification_fastResolveClass","width":3},{"name":"uop_decoded_classification_fusionHeadClass","width":2},{"name":"uop_decoded_classification_fusionTailClass","width":2},{"name":"uop_decoded_classification_implicitDestination","width":2},{"name":"uop_decoded_classification_implicitSourceMask","width":4},{"name":"uop_decoded_classification_kind","width":4},{"name":"uop_decoded_classification_mayRedirect","width":1},{"name":"uop_decoded_classification_mayTrap","width":1},{"name":"uop_decoded_classification_mayTrapLate","width":1},{"name":"uop_decoded_classification_memoryRequestCount","width":2},{"name":"uop_decoded_classification_nonspeculative","width":1},{"name":"uop_decoded_classification_pDestinationCount","width":2},{"name":"uop_decoded_classification_pSourceCount","width":3},{"name":"uop_decoded_classification_pcReadClass","width":4},{"name":"uop_decoded_classification_pcReadRequired","width":1},{"name":"uop_decoded_classification_requiresTargetValidation","width":1},{"name":"uop_decoded_classification_sideEffectOwner","width":3},{"name":"uop_decoded_classification_splitKind","width":2},{"name":"uop_decoded_classification_tAllocationCount","width":2},{"name":"uop_decoded_classification_uAllocationCount","width":2},{"name":"uop_decoded_classification_uopCountMax","width":6},{"name":"uop_decoded_classification_uopCountMin","width":6},{"name":"uop_decoded_classification_valid","width":1},{"name":"uop_decoded_destinations_0_atag","width":6},{"name":"uop_decoded_destinations_0_kind","width":3},{"name":"uop_decoded_destinations_0_relativeIndex","width":6},{"name":"uop_decoded_destinations_0_valid","width":1},{"name":"uop_decoded_destinations_1_atag","width":6},{"name":"uop_decoded_destinations_1_kind","width":3},{"name":"uop_decoded_destinations_1_relativeIndex","width":6},{"name":"uop_decoded_destinations_1_valid","width":1},{"name":"uop_decoded_earlyComplete","width":1},{"name":"uop_decoded_immediate","width":64},{"name":"uop_decoded_immediateValid","width":1},{"name":"uop_decoded_instruction_kind","width":1},{"name":"uop_decoded_instruction_parent_fetchFault","width":1},{"name":"uop_decoded_instruction_parent_fetchFaultCause","width":32},{"name":"uop_decoded_instruction_parent_identity_epoch","width":16},{"name":"uop_decoded_instruction_parent_identity_instructionId","width":64},{"name":"uop_decoded_instruction_parent_identity_peId","width":8},{"name":"uop_decoded_instruction_parent_identity_stid","width":1},{"name":"uop_decoded_instruction_parent_instruction","width":64},{"name":"uop_decoded_instruction_parent_lengthBytes","width":4},{"name":"uop_decoded_instruction_parent_pc","width":64},{"name":"uop_decoded_instruction_parent_prediction_checkpointId","width":5},{"name":"uop_decoded_instruction_parent_prediction_confidence","width":2},{"name":"uop_decoded_instruction_parent_prediction_epoch","width":16},{"name":"uop_decoded_instruction_parent_prediction_fallthroughPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_kind","width":3},{"name":"uop_decoded_instruction_parent_prediction_predictionTag","width":64},{"name":"uop_decoded_instruction_parent_prediction_provider","width":4},{"name":"uop_decoded_instruction_parent_prediction_requestPc","width":64},{"name":"uop_decoded_instruction_parent_prediction_taken","width":1},{"name":"uop_decoded_instruction_parent_prediction_target","width":64},{"name":"uop_decoded_instruction_parent_prediction_transactionId","width":64},{"name":"uop_decoded_instruction_parent_prediction_valid","width":1},{"name":"uop_decoded_instruction_templateCount","width":8},{"name":"uop_decoded_instruction_templateImmediate","width":64},{"name":"uop_decoded_instruction_templateOpcode","width":12},{"name":"uop_decoded_instruction_templateOrdinal","width":8},{"name":"uop_decoded_memory_accessBytes","width":4},{"name":"uop_decoded_memory_addressMode","width":2},{"name":"uop_decoded_memory_addressSourceMask","width":4},{"name":"uop_decoded_memory_dataSourceMask","width":4},{"name":"uop_decoded_memory_indexMode","width":2},{"name":"uop_decoded_memory_indexShift","width":5},{"name":"uop_decoded_memory_isLoad","width":1},{"name":"uop_decoded_memory_isStore","width":1},{"name":"uop_decoded_memory_offset","width":64},{"name":"uop_decoded_memory_requestCount","width":2},{"name":"uop_decoded_memory_signExtend","width":1},{"name":"uop_decoded_memory_valid","width":1},{"name":"uop_decoded_memory_writebackPreIndex","width":1},{"name":"uop_decoded_memory_writebackValid","width":1},{"name":"uop_decoded_opcode","width":12},{"name":"uop_decoded_rob_bid","width":8},{"name":"uop_decoded_rob_brobGeneration","width":16},{"name":"uop_decoded_rob_memberIndex","width":2},{"name":"uop_decoded_rob_peId","width":8},{"name":"uop_decoded_rob_residentGeneration","width":16},{"name":"uop_decoded_rob_ridGeneration","width":16},{"name":"uop_decoded_rob_ridSlot","width":6},{"name":"uop_decoded_rob_stid","width":1},{"name":"uop_decoded_sources_0_atag","width":6},{"name":"uop_decoded_sources_0_kind","width":3},{"name":"uop_decoded_sources_0_relativeIndex","width":6},{"name":"uop_decoded_sources_0_valid","width":1},{"name":"uop_decoded_sources_1_atag","width":6},{"name":"uop_decoded_sources_1_kind","width":3},{"name":"uop_decoded_sources_1_relativeIndex","width":6},{"name":"uop_decoded_sources_1_valid","width":1},{"name":"uop_decoded_sources_2_atag","width":6},{"name":"uop_decoded_sources_2_kind","width":3},{"name":"uop_decoded_sources_2_relativeIndex","width":6},{"name":"uop_decoded_sources_2_valid","width":1},{"name":"uop_decoded_sources_3_atag","width":6},{"name":"uop_decoded_sources_3_kind","width":3},{"name":"uop_decoded_sources_3_relativeIndex","width":6},{"name":"uop_decoded_sources_3_valid","width":1},{"name":"uop_decoded_uopClass","width":3},{"name":"uop_decoded_valid","width":1},{"name":"uop_destinations_0_atag","width":6},{"name":"uop_destinations_0_kind","width":3},{"name":"uop_destinations_0_pGeneration","width":16},{"name":"uop_destinations_0_previousPGeneration","width":16},{"name":"uop_destinations_0_previousPtag","width":7},{"name":"uop_destinations_0_previousPtagValid","width":1},{"name":"uop_destinations_0_previousTtag","width":5},{"name":"uop_destinations_0_previousTtagValid","width":1},{"name":"uop_destinations_0_previousUtag","width":5},{"name":"uop_destinations_0_previousUtagValid","width":1},{"name":"uop_destinations_0_ptag","width":7},{"name":"uop_destinations_0_ptagValid","width":1},{"name":"uop_destinations_0_tGeneration","width":16},{"name":"uop_destinations_0_tSeqGeneration","width":16},{"name":"uop_destinations_0_tSeqIndex","width":5},{"name":"uop_destinations_0_ttag","width":5},{"name":"uop_destinations_0_ttagValid","width":1},{"name":"uop_destinations_0_uGeneration","width":16},{"name":"uop_destinations_0_uSeqGeneration","width":16},{"name":"uop_destinations_0_uSeqIndex","width":5},{"name":"uop_destinations_0_utag","width":5},{"name":"uop_destinations_0_utagValid","width":1},{"name":"uop_destinations_0_valid","width":1},{"name":"uop_destinations_1_atag","width":6},{"name":"uop_destinations_1_kind","width":3},{"name":"uop_destinations_1_pGeneration","width":16},{"name":"uop_destinations_1_previousPGeneration","width":16},{"name":"uop_destinations_1_previousPtag","width":7},{"name":"uop_destinations_1_previousPtagValid","width":1},{"name":"uop_destinations_1_previousTtag","width":5},{"name":"uop_destinations_1_previousTtagValid","width":1},{"name":"uop_destinations_1_previousUtag","width":5},{"name":"uop_destinations_1_previousUtagValid","width":1},{"name":"uop_destinations_1_ptag","width":7},{"name":"uop_destinations_1_ptagValid","width":1},{"name":"uop_destinations_1_tGeneration","width":16},{"name":"uop_destinations_1_tSeqGeneration","width":16},{"name":"uop_destinations_1_tSeqIndex","width":5},{"name":"uop_destinations_1_ttag","width":5},{"name":"uop_destinations_1_ttagValid","width":1},{"name":"uop_destinations_1_uGeneration","width":16},{"name":"uop_destinations_1_uSeqGeneration","width":16},{"name":"uop_destinations_1_uSeqIndex","width":5},{"name":"uop_destinations_1_utag","width":5},{"name":"uop_destinations_1_utagValid","width":1},{"name":"uop_destinations_1_valid","width":1},{"name":"uop_sources_0_atag","width":6},{"name":"uop_sources_0_kind","width":3},{"name":"uop_sources_0_pGeneration","width":16},{"name":"uop_sources_0_ptag","width":7},{"name":"uop_sources_0_ptagValid","width":1},{"name":"uop_sources_0_ready","width":1},{"name":"uop_sources_0_tGeneration","width":16},{"name":"uop_sources_0_tSeqGeneration","width":16},{"name":"uop_sources_0_tSeqIndex","width":5},{"name":"uop_sources_0_ttag","width":5},{"name":"uop_sources_0_ttagValid","width":1},{"name":"uop_sources_0_uGeneration","width":16},{"name":"uop_sources_0_uSeqGeneration","width":16},{"name":"uop_sources_0_uSeqIndex","width":5},{"name":"uop_sources_0_utag","width":5},{"name":"uop_sources_0_utagValid","width":1},{"name":"uop_sources_0_valid","width":1},{"name":"uop_sources_1_atag","width":6},{"name":"uop_sources_1_kind","width":3},{"name":"uop_sources_1_pGeneration","width":16},{"name":"uop_sources_1_ptag","width":7},{"name":"uop_sources_1_ptagValid","width":1},{"name":"uop_sources_1_ready","width":1},{"name":"uop_sources_1_tGeneration","width":16},{"name":"uop_sources_1_tSeqGeneration","width":16},{"name":"uop_sources_1_tSeqIndex","width":5},{"name":"uop_sources_1_ttag","width":5},{"name":"uop_sources_1_ttagValid","width":1},{"name":"uop_sources_1_uGeneration","width":16},{"name":"uop_sources_1_uSeqGeneration","width":16},{"name":"uop_sources_1_uSeqIndex","width":5},{"name":"uop_sources_1_utag","width":5},{"name":"uop_sources_1_utagValid","width":1},{"name":"uop_sources_1_valid","width":1},{"name":"uop_sources_2_atag","width":6},{"name":"uop_sources_2_kind","width":3},{"name":"uop_sources_2_pGeneration","width":16},{"name":"uop_sources_2_ptag","width":7},{"name":"uop_sources_2_ptagValid","width":1},{"name":"uop_sources_2_ready","width":1},{"name":"uop_sources_2_tGeneration","width":16},{"name":"uop_sources_2_tSeqGeneration","width":16},{"name":"uop_sources_2_tSeqIndex","width":5},{"name":"uop_sources_2_ttag","width":5},{"name":"uop_sources_2_ttagValid","width":1},{"name":"uop_sources_2_uGeneration","width":16},{"name":"uop_sources_2_uSeqGeneration","width":16},{"name":"uop_sources_2_uSeqIndex","width":5},{"name":"uop_sources_2_utag","width":5},{"name":"uop_sources_2_utagValid","width":1},{"name":"uop_sources_2_valid","width":1},{"name":"uop_sources_3_atag","width":6},{"name":"uop_sources_3_kind","width":3},{"name":"uop_sources_3_pGeneration","width":16},{"name":"uop_sources_3_ptag","width":7},{"name":"uop_sources_3_ptagValid","width":1},{"name":"uop_sources_3_ready","width":1},{"name":"uop_sources_3_tGeneration","width":16},{"name":"uop_sources_3_tSeqGeneration","width":16},{"name":"uop_sources_3_tSeqIndex","width":5},{"name":"uop_sources_3_ttag","width":5},{"name":"uop_sources_3_ttagValid","width":1},{"name":"uop_sources_3_uGeneration","width":16},{"name":"uop_sources_3_uSeqGeneration","width":16},{"name":"uop_sources_3_uSeqIndex","width":5},{"name":"uop_sources_3_utag","width":5},{"name":"uop_sources_3_utagValid","width":1},{"name":"uop_sources_3_valid","width":1}]},{"name":"ooo_to_iex_rob_noflush","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":1,"payload":"RobNoflushTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_noflush_ready","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"RobNoflushReadyTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_rob_resolve","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":8,"payload":"RobResolveTxn","ports":[{"name":"destinationIndex","width":1},{"name":"destinationValid","width":1},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"value","width":64}]},{"name":"iex_to_ooo_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_top_system_issue","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"TOP","lanes":1,"payload":"SystemIssueTxn","ports":[{"name":"immediate","width":64},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transactionId","width":64}]},{"name":"iex_to_ooo_pc_buffer_read_address","contract_id":"IFC-OOO-IEX-001","producer":"IEX","consumer":"OOO","lanes":6,"payload":"PcBufferReadAddress","ports":[{"name":"allocationEpoch","width":16},{"name":"pcBufferIndex","width":6},{"name":"stid","width":1},{"name":"valid","width":1}]},{"name":"ooo_to_iex_pc_buffer_read_pc_base","contract_id":"IFC-OOO-IEX-001","producer":"OOO","consumer":"IEX","lanes":6,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"iex_to_lsu_load_issue","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"LoadIssueTxn","ports":[{"name":"address","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"pc","width":64},{"name":"signed","width":1},{"name":"sizeBytes","width":4},{"name":"youngestStoreId","width":32},{"name":"youngestStoreLsid","width":32},{"name":"youngestStoreValid","width":1}]},{"name":"lsu_to_iex_load_allocation_preview","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadAllocationPreview","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_launch","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadLaunchTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64}]},{"name":"iex_to_lsu_store_reservation","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreReservationTxn","ports":[{"name":"aguPipe","width":1},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sizeBytes","width":4},{"name":"stdPipe","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64},{"name":"transactionId","width":64}]},{"name":"iex_to_lsu_store_address","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreAddressTxn","ports":[{"name":"address","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"iex_to_lsu_store_data","contract_id":"IFC-IEX-LSU-001","producer":"IEX","consumer":"LSU","lanes":2,"payload":"StoreDataTxn","ports":[{"name":"byteMask_0","width":8},{"name":"byteMask_1","width":8},{"name":"data_0","width":64},{"name":"data_1","width":64},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"memoryOrder_firstLid","width":32},{"name":"memoryOrder_firstLsid","width":32},{"name":"memoryOrder_firstSid","width":32},{"name":"memoryOrder_requestCount","width":2},{"name":"memoryOrder_yoldLid","width":32},{"name":"memoryOrder_yoldLsid","width":32},{"name":"memoryOrder_yoldValid","width":1},{"name":"memoryOrder_yostLsid","width":32},{"name":"memoryOrder_yostSid","width":32},{"name":"memoryOrder_yostValid","width":1},{"name":"pair","width":1},{"name":"requestCount","width":2},{"name":"sizeBytes","width":4}]},{"name":"lsu_to_iex_load_result","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadResultTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"data","width":64},{"name":"destination_atag","width":6},{"name":"destination_kind","width":3},{"name":"destination_pGeneration","width":16},{"name":"destination_previousPGeneration","width":16},{"name":"destination_previousPtag","width":7},{"name":"destination_previousPtagValid","width":1},{"name":"destination_previousTtag","width":5},{"name":"destination_previousTtagValid","width":1},{"name":"destination_previousUtag","width":5},{"name":"destination_previousUtagValid","width":1},{"name":"destination_ptag","width":7},{"name":"destination_ptagValid","width":1},{"name":"destination_tGeneration","width":16},{"name":"destination_tSeqGeneration","width":16},{"name":"destination_tSeqIndex","width":5},{"name":"destination_ttag","width":5},{"name":"destination_ttagValid","width":1},{"name":"destination_uGeneration","width":16},{"name":"destination_uSeqGeneration","width":16},{"name":"destination_uSeqIndex","width":5},{"name":"destination_utag","width":5},{"name":"destination_utagValid","width":1},{"name":"destination_valid","width":1},{"name":"destinationRelativeIndex","width":6},{"name":"identity_attemptGeneration","width":16},{"name":"identity_lsid","width":32},{"name":"identity_pipeId","width":1},{"name":"identity_rob_bid","width":8},{"name":"identity_rob_brobGeneration","width":16},{"name":"identity_rob_memberIndex","width":2},{"name":"identity_rob_peId","width":8},{"name":"identity_rob_residentGeneration","width":16},{"name":"identity_rob_ridGeneration","width":16},{"name":"identity_rob_ridSlot","width":6},{"name":"identity_rob_stid","width":1},{"name":"identity_transaction_generation","width":16},{"name":"identity_transaction_value","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1}]},{"name":"lsu_to_iex_load_reissue","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadReissueTxn","ports":[{"name":"address","width":64},{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_repick","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadRepickTxn","ports":[{"name":"allocationId_generation","width":16},{"name":"allocationId_value","width":64},{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64},{"name":"nextIdentity_attemptGeneration","width":16},{"name":"nextIdentity_lsid","width":32},{"name":"nextIdentity_pipeId","width":1},{"name":"nextIdentity_rob_bid","width":8},{"name":"nextIdentity_rob_brobGeneration","width":16},{"name":"nextIdentity_rob_memberIndex","width":2},{"name":"nextIdentity_rob_peId","width":8},{"name":"nextIdentity_rob_residentGeneration","width":16},{"name":"nextIdentity_rob_ridGeneration","width":16},{"name":"nextIdentity_rob_ridSlot","width":6},{"name":"nextIdentity_rob_stid","width":1},{"name":"nextIdentity_transaction_generation","width":16},{"name":"nextIdentity_transaction_value","width":64}]},{"name":"lsu_to_iex_load_cancel","contract_id":"IFC-IEX-LSU-001","producer":"LSU","consumer":"IEX","lanes":2,"payload":"LoadCancelTxn","ports":[{"name":"currentIdentity_attemptGeneration","width":16},{"name":"currentIdentity_lsid","width":32},{"name":"currentIdentity_pipeId","width":1},{"name":"currentIdentity_rob_bid","width":8},{"name":"currentIdentity_rob_brobGeneration","width":16},{"name":"currentIdentity_rob_memberIndex","width":2},{"name":"currentIdentity_rob_peId","width":8},{"name":"currentIdentity_rob_residentGeneration","width":16},{"name":"currentIdentity_rob_ridGeneration","width":16},{"name":"currentIdentity_rob_ridSlot","width":6},{"name":"currentIdentity_rob_stid","width":1},{"name":"currentIdentity_transaction_generation","width":16},{"name":"currentIdentity_transaction_value","width":64}]},{"name":"ooo_to_lsu_store_commit","contract_id":"IFC-IEX-LSU-001","producer":"OOO","consumer":"LSU","lanes":1,"payload":"StoreCommitAuthorizationTxn","ports":[{"name":"beat","width":1},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"lsu_internal_store_classify","contract_id":"IFC-IEX-LSU-001","producer":"LSU Translation","consumer":"LSU Commit Backend","lanes":1,"payload":"StoreMemoryClassifyTxn","ports":[{"name":"beat","width":1},{"name":"faultCause","width":32},{"name":"logicalFirstLsid","width":32},{"name":"logicalFirstStoreId","width":32},{"name":"memoryClass","width":2},{"name":"requestCount","width":2},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"transaction_generation","width":16},{"name":"transaction_value","width":64}]},{"name":"external_cmd_issue","contract_id":"IFC-TOP-EXT-001","producer":"IEX","consumer":"External CMD","lanes":1,"payload":"CmdIssueTxn","ports":[{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"opcode","width":12},{"name":"rob_bid","width":8},{"name":"rob_brobGeneration","width":16},{"name":"rob_memberIndex","width":2},{"name":"rob_peId","width":8},{"name":"rob_residentGeneration","width":16},{"name":"rob_ridGeneration","width":16},{"name":"rob_ridSlot","width":6},{"name":"rob_stid","width":1},{"name":"sourceValid","width":4},{"name":"sourceValues_0","width":64},{"name":"sourceValues_1","width":64},{"name":"sourceValues_2","width":64},{"name":"sourceValues_3","width":64},{"name":"transactionId","width":64}]},{"name":"owner_to_ooo_recovery_event","contract_id":"IFC-RECOVERY-001","producer":"IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryEvent","ports":[{"name":"cause","width":3},{"name":"instruction_epoch","width":16},{"name":"instruction_instructionId","width":64},{"name":"instruction_peId","width":8},{"name":"instruction_stid","width":1},{"name":"redirectPc","width":64},{"name":"transactionId","width":64},{"name":"trap_cause","width":32},{"name":"trap_instruction_epoch","width":16},{"name":"trap_instruction_instructionId","width":64},{"name":"trap_instruction_peId","width":8},{"name":"trap_instruction_stid","width":1},{"name":"trap_kind","width":2},{"name":"trap_rob_bid","width":8},{"name":"trap_rob_brobGeneration","width":16},{"name":"trap_rob_memberIndex","width":2},{"name":"trap_rob_peId","width":8},{"name":"trap_rob_residentGeneration","width":16},{"name":"trap_rob_ridGeneration","width":16},{"name":"trap_rob_ridSlot","width":6},{"name":"trap_rob_stid","width":1},{"name":"trap_targetPc","width":64},{"name":"trap_tval","width":64},{"name":"trap_valid","width":1},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_prepare","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"target_to_ooo_recovery_prepared","contract_id":"IFC-RECOVERY-001","producer":"IFU/CTU/IEX/LSU","consumer":"OOO","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_apply","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_recovery_abort","contract_id":"IFC-RECOVERY-001","producer":"OOO","consumer":"IFU/CTU/IEX/LSU","lanes":1,"payload":"RecoveryPlan","ports":[{"name":"cause","width":3},{"name":"firstKilled_bid","width":8},{"name":"firstKilled_brobGeneration","width":16},{"name":"firstKilled_memberIndex","width":2},{"name":"firstKilled_peId","width":8},{"name":"firstKilled_residentGeneration","width":16},{"name":"firstKilled_ridGeneration","width":16},{"name":"firstKilled_ridSlot","width":6},{"name":"firstKilled_stid","width":1},{"name":"firstKilledValid","width":1},{"name":"killedGroupCount","width":7},{"name":"killedMemberCount","width":9},{"name":"lastKilled_bid","width":8},{"name":"lastKilled_brobGeneration","width":16},{"name":"lastKilled_memberIndex","width":2},{"name":"lastKilled_peId","width":8},{"name":"lastKilled_residentGeneration","width":16},{"name":"lastKilled_ridGeneration","width":16},{"name":"lastKilled_ridSlot","width":6},{"name":"lastKilled_stid","width":1},{"name":"newEpoch","width":16},{"name":"phase","width":2},{"name":"redirectPc","width":64},{"name":"survivingTail_bid","width":8},{"name":"survivingTail_brobGeneration","width":16},{"name":"survivingTail_memberIndex","width":2},{"name":"survivingTail_peId","width":8},{"name":"survivingTail_residentGeneration","width":16},{"name":"survivingTail_ridGeneration","width":16},{"name":"survivingTail_ridSlot","width":6},{"name":"survivingTail_stid","width":1},{"name":"survivingTailValid","width":1},{"name":"transactionId","width":64},{"name":"trigger_bid","width":8},{"name":"trigger_brobGeneration","width":16},{"name":"trigger_memberIndex","width":2},{"name":"trigger_peId","width":8},{"name":"trigger_residentGeneration","width":16},{"name":"trigger_ridGeneration","width":16},{"name":"trigger_ridSlot","width":6},{"name":"trigger_stid","width":1}]},{"name":"ooo_commit","contract_id":"IFC-COMMIT-001","producer":"OOO","consumer":"TOP/DTU","lanes":8,"payload":"CommitTxn","ports":[{"name":"count","width":4},{"name":"entries_0_destination_atag","width":6},{"name":"entries_0_destination_kind","width":3},{"name":"entries_0_destination_pGeneration","width":16},{"name":"entries_0_destination_previousPGeneration","width":16},{"name":"entries_0_destination_previousPtag","width":7},{"name":"entries_0_destination_previousPtagValid","width":1},{"name":"entries_0_destination_previousTtag","width":5},{"name":"entries_0_destination_previousTtagValid","width":1},{"name":"entries_0_destination_previousUtag","width":5},{"name":"entries_0_destination_previousUtagValid","width":1},{"name":"entries_0_destination_ptag","width":7},{"name":"entries_0_destination_ptagValid","width":1},{"name":"entries_0_destination_tGeneration","width":16},{"name":"entries_0_destination_tSeqGeneration","width":16},{"name":"entries_0_destination_tSeqIndex","width":5},{"name":"entries_0_destination_ttag","width":5},{"name":"entries_0_destination_ttagValid","width":1},{"name":"entries_0_destination_uGeneration","width":16},{"name":"entries_0_destination_uSeqGeneration","width":16},{"name":"entries_0_destination_uSeqIndex","width":5},{"name":"entries_0_destination_utag","width":5},{"name":"entries_0_destination_utagValid","width":1},{"name":"entries_0_destination_valid","width":1},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionBits","width":64},{"name":"entries_0_instructionLengthBytes","width":4},{"name":"entries_0_memory_attemptGeneration","width":16},{"name":"entries_0_memory_lsid","width":32},{"name":"entries_0_memory_pipeId","width":1},{"name":"entries_0_memory_rob_bid","width":8},{"name":"entries_0_memory_rob_brobGeneration","width":16},{"name":"entries_0_memory_rob_memberIndex","width":2},{"name":"entries_0_memory_rob_peId","width":8},{"name":"entries_0_memory_rob_residentGeneration","width":16},{"name":"entries_0_memory_rob_ridGeneration","width":16},{"name":"entries_0_memory_rob_ridSlot","width":6},{"name":"entries_0_memory_rob_stid","width":1},{"name":"entries_0_memory_transaction_generation","width":16},{"name":"entries_0_memory_transaction_value","width":64},{"name":"entries_0_memoryOrder_firstLid","width":32},{"name":"entries_0_memoryOrder_firstLsid","width":32},{"name":"entries_0_memoryOrder_firstSid","width":32},{"name":"entries_0_memoryOrder_requestCount","width":2},{"name":"entries_0_memoryOrder_yoldLid","width":32},{"name":"entries_0_memoryOrder_yoldLsid","width":32},{"name":"entries_0_memoryOrder_yoldValid","width":1},{"name":"entries_0_memoryOrder_yostLsid","width":32},{"name":"entries_0_memoryOrder_yostSid","width":32},{"name":"entries_0_memoryOrder_yostValid","width":1},{"name":"entries_0_memoryStore","width":1},{"name":"entries_0_memoryValid","width":1},{"name":"entries_0_opcode","width":12},{"name":"entries_0_pc","width":64},{"name":"entries_0_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_0_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_0_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_0_pcBufferIndexOffset_valid","width":1},{"name":"entries_0_result","width":64},{"name":"entries_0_resultValid","width":1},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robGroupLast","width":1},{"name":"entries_0_storeData","width":64},{"name":"entries_0_storeMask","width":8},{"name":"entries_0_trap_cause","width":32},{"name":"entries_0_trap_instruction_epoch","width":16},{"name":"entries_0_trap_instruction_instructionId","width":64},{"name":"entries_0_trap_instruction_peId","width":8},{"name":"entries_0_trap_instruction_stid","width":1},{"name":"entries_0_trap_kind","width":2},{"name":"entries_0_trap_rob_bid","width":8},{"name":"entries_0_trap_rob_brobGeneration","width":16},{"name":"entries_0_trap_rob_memberIndex","width":2},{"name":"entries_0_trap_rob_peId","width":8},{"name":"entries_0_trap_rob_residentGeneration","width":16},{"name":"entries_0_trap_rob_ridGeneration","width":16},{"name":"entries_0_trap_rob_ridSlot","width":6},{"name":"entries_0_trap_rob_stid","width":1},{"name":"entries_0_trap_targetPc","width":64},{"name":"entries_0_trap_tval","width":64},{"name":"entries_0_trap_valid","width":1},{"name":"entries_1_destination_atag","width":6},{"name":"entries_1_destination_kind","width":3},{"name":"entries_1_destination_pGeneration","width":16},{"name":"entries_1_destination_previousPGeneration","width":16},{"name":"entries_1_destination_previousPtag","width":7},{"name":"entries_1_destination_previousPtagValid","width":1},{"name":"entries_1_destination_previousTtag","width":5},{"name":"entries_1_destination_previousTtagValid","width":1},{"name":"entries_1_destination_previousUtag","width":5},{"name":"entries_1_destination_previousUtagValid","width":1},{"name":"entries_1_destination_ptag","width":7},{"name":"entries_1_destination_ptagValid","width":1},{"name":"entries_1_destination_tGeneration","width":16},{"name":"entries_1_destination_tSeqGeneration","width":16},{"name":"entries_1_destination_tSeqIndex","width":5},{"name":"entries_1_destination_ttag","width":5},{"name":"entries_1_destination_ttagValid","width":1},{"name":"entries_1_destination_uGeneration","width":16},{"name":"entries_1_destination_uSeqGeneration","width":16},{"name":"entries_1_destination_uSeqIndex","width":5},{"name":"entries_1_destination_utag","width":5},{"name":"entries_1_destination_utagValid","width":1},{"name":"entries_1_destination_valid","width":1},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionBits","width":64},{"name":"entries_1_instructionLengthBytes","width":4},{"name":"entries_1_memory_attemptGeneration","width":16},{"name":"entries_1_memory_lsid","width":32},{"name":"entries_1_memory_pipeId","width":1},{"name":"entries_1_memory_rob_bid","width":8},{"name":"entries_1_memory_rob_brobGeneration","width":16},{"name":"entries_1_memory_rob_memberIndex","width":2},{"name":"entries_1_memory_rob_peId","width":8},{"name":"entries_1_memory_rob_residentGeneration","width":16},{"name":"entries_1_memory_rob_ridGeneration","width":16},{"name":"entries_1_memory_rob_ridSlot","width":6},{"name":"entries_1_memory_rob_stid","width":1},{"name":"entries_1_memory_transaction_generation","width":16},{"name":"entries_1_memory_transaction_value","width":64},{"name":"entries_1_memoryOrder_firstLid","width":32},{"name":"entries_1_memoryOrder_firstLsid","width":32},{"name":"entries_1_memoryOrder_firstSid","width":32},{"name":"entries_1_memoryOrder_requestCount","width":2},{"name":"entries_1_memoryOrder_yoldLid","width":32},{"name":"entries_1_memoryOrder_yoldLsid","width":32},{"name":"entries_1_memoryOrder_yoldValid","width":1},{"name":"entries_1_memoryOrder_yostLsid","width":32},{"name":"entries_1_memoryOrder_yostSid","width":32},{"name":"entries_1_memoryOrder_yostValid","width":1},{"name":"entries_1_memoryStore","width":1},{"name":"entries_1_memoryValid","width":1},{"name":"entries_1_opcode","width":12},{"name":"entries_1_pc","width":64},{"name":"entries_1_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_1_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_1_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_1_pcBufferIndexOffset_valid","width":1},{"name":"entries_1_result","width":64},{"name":"entries_1_resultValid","width":1},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robGroupLast","width":1},{"name":"entries_1_storeData","width":64},{"name":"entries_1_storeMask","width":8},{"name":"entries_1_trap_cause","width":32},{"name":"entries_1_trap_instruction_epoch","width":16},{"name":"entries_1_trap_instruction_instructionId","width":64},{"name":"entries_1_trap_instruction_peId","width":8},{"name":"entries_1_trap_instruction_stid","width":1},{"name":"entries_1_trap_kind","width":2},{"name":"entries_1_trap_rob_bid","width":8},{"name":"entries_1_trap_rob_brobGeneration","width":16},{"name":"entries_1_trap_rob_memberIndex","width":2},{"name":"entries_1_trap_rob_peId","width":8},{"name":"entries_1_trap_rob_residentGeneration","width":16},{"name":"entries_1_trap_rob_ridGeneration","width":16},{"name":"entries_1_trap_rob_ridSlot","width":6},{"name":"entries_1_trap_rob_stid","width":1},{"name":"entries_1_trap_targetPc","width":64},{"name":"entries_1_trap_tval","width":64},{"name":"entries_1_trap_valid","width":1},{"name":"entries_2_destination_atag","width":6},{"name":"entries_2_destination_kind","width":3},{"name":"entries_2_destination_pGeneration","width":16},{"name":"entries_2_destination_previousPGeneration","width":16},{"name":"entries_2_destination_previousPtag","width":7},{"name":"entries_2_destination_previousPtagValid","width":1},{"name":"entries_2_destination_previousTtag","width":5},{"name":"entries_2_destination_previousTtagValid","width":1},{"name":"entries_2_destination_previousUtag","width":5},{"name":"entries_2_destination_previousUtagValid","width":1},{"name":"entries_2_destination_ptag","width":7},{"name":"entries_2_destination_ptagValid","width":1},{"name":"entries_2_destination_tGeneration","width":16},{"name":"entries_2_destination_tSeqGeneration","width":16},{"name":"entries_2_destination_tSeqIndex","width":5},{"name":"entries_2_destination_ttag","width":5},{"name":"entries_2_destination_ttagValid","width":1},{"name":"entries_2_destination_uGeneration","width":16},{"name":"entries_2_destination_uSeqGeneration","width":16},{"name":"entries_2_destination_uSeqIndex","width":5},{"name":"entries_2_destination_utag","width":5},{"name":"entries_2_destination_utagValid","width":1},{"name":"entries_2_destination_valid","width":1},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionBits","width":64},{"name":"entries_2_instructionLengthBytes","width":4},{"name":"entries_2_memory_attemptGeneration","width":16},{"name":"entries_2_memory_lsid","width":32},{"name":"entries_2_memory_pipeId","width":1},{"name":"entries_2_memory_rob_bid","width":8},{"name":"entries_2_memory_rob_brobGeneration","width":16},{"name":"entries_2_memory_rob_memberIndex","width":2},{"name":"entries_2_memory_rob_peId","width":8},{"name":"entries_2_memory_rob_residentGeneration","width":16},{"name":"entries_2_memory_rob_ridGeneration","width":16},{"name":"entries_2_memory_rob_ridSlot","width":6},{"name":"entries_2_memory_rob_stid","width":1},{"name":"entries_2_memory_transaction_generation","width":16},{"name":"entries_2_memory_transaction_value","width":64},{"name":"entries_2_memoryOrder_firstLid","width":32},{"name":"entries_2_memoryOrder_firstLsid","width":32},{"name":"entries_2_memoryOrder_firstSid","width":32},{"name":"entries_2_memoryOrder_requestCount","width":2},{"name":"entries_2_memoryOrder_yoldLid","width":32},{"name":"entries_2_memoryOrder_yoldLsid","width":32},{"name":"entries_2_memoryOrder_yoldValid","width":1},{"name":"entries_2_memoryOrder_yostLsid","width":32},{"name":"entries_2_memoryOrder_yostSid","width":32},{"name":"entries_2_memoryOrder_yostValid","width":1},{"name":"entries_2_memoryStore","width":1},{"name":"entries_2_memoryValid","width":1},{"name":"entries_2_opcode","width":12},{"name":"entries_2_pc","width":64},{"name":"entries_2_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_2_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_2_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_2_pcBufferIndexOffset_valid","width":1},{"name":"entries_2_result","width":64},{"name":"entries_2_resultValid","width":1},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robGroupLast","width":1},{"name":"entries_2_storeData","width":64},{"name":"entries_2_storeMask","width":8},{"name":"entries_2_trap_cause","width":32},{"name":"entries_2_trap_instruction_epoch","width":16},{"name":"entries_2_trap_instruction_instructionId","width":64},{"name":"entries_2_trap_instruction_peId","width":8},{"name":"entries_2_trap_instruction_stid","width":1},{"name":"entries_2_trap_kind","width":2},{"name":"entries_2_trap_rob_bid","width":8},{"name":"entries_2_trap_rob_brobGeneration","width":16},{"name":"entries_2_trap_rob_memberIndex","width":2},{"name":"entries_2_trap_rob_peId","width":8},{"name":"entries_2_trap_rob_residentGeneration","width":16},{"name":"entries_2_trap_rob_ridGeneration","width":16},{"name":"entries_2_trap_rob_ridSlot","width":6},{"name":"entries_2_trap_rob_stid","width":1},{"name":"entries_2_trap_targetPc","width":64},{"name":"entries_2_trap_tval","width":64},{"name":"entries_2_trap_valid","width":1},{"name":"entries_3_destination_atag","width":6},{"name":"entries_3_destination_kind","width":3},{"name":"entries_3_destination_pGeneration","width":16},{"name":"entries_3_destination_previousPGeneration","width":16},{"name":"entries_3_destination_previousPtag","width":7},{"name":"entries_3_destination_previousPtagValid","width":1},{"name":"entries_3_destination_previousTtag","width":5},{"name":"entries_3_destination_previousTtagValid","width":1},{"name":"entries_3_destination_previousUtag","width":5},{"name":"entries_3_destination_previousUtagValid","width":1},{"name":"entries_3_destination_ptag","width":7},{"name":"entries_3_destination_ptagValid","width":1},{"name":"entries_3_destination_tGeneration","width":16},{"name":"entries_3_destination_tSeqGeneration","width":16},{"name":"entries_3_destination_tSeqIndex","width":5},{"name":"entries_3_destination_ttag","width":5},{"name":"entries_3_destination_ttagValid","width":1},{"name":"entries_3_destination_uGeneration","width":16},{"name":"entries_3_destination_uSeqGeneration","width":16},{"name":"entries_3_destination_uSeqIndex","width":5},{"name":"entries_3_destination_utag","width":5},{"name":"entries_3_destination_utagValid","width":1},{"name":"entries_3_destination_valid","width":1},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionBits","width":64},{"name":"entries_3_instructionLengthBytes","width":4},{"name":"entries_3_memory_attemptGeneration","width":16},{"name":"entries_3_memory_lsid","width":32},{"name":"entries_3_memory_pipeId","width":1},{"name":"entries_3_memory_rob_bid","width":8},{"name":"entries_3_memory_rob_brobGeneration","width":16},{"name":"entries_3_memory_rob_memberIndex","width":2},{"name":"entries_3_memory_rob_peId","width":8},{"name":"entries_3_memory_rob_residentGeneration","width":16},{"name":"entries_3_memory_rob_ridGeneration","width":16},{"name":"entries_3_memory_rob_ridSlot","width":6},{"name":"entries_3_memory_rob_stid","width":1},{"name":"entries_3_memory_transaction_generation","width":16},{"name":"entries_3_memory_transaction_value","width":64},{"name":"entries_3_memoryOrder_firstLid","width":32},{"name":"entries_3_memoryOrder_firstLsid","width":32},{"name":"entries_3_memoryOrder_firstSid","width":32},{"name":"entries_3_memoryOrder_requestCount","width":2},{"name":"entries_3_memoryOrder_yoldLid","width":32},{"name":"entries_3_memoryOrder_yoldLsid","width":32},{"name":"entries_3_memoryOrder_yoldValid","width":1},{"name":"entries_3_memoryOrder_yostLsid","width":32},{"name":"entries_3_memoryOrder_yostSid","width":32},{"name":"entries_3_memoryOrder_yostValid","width":1},{"name":"entries_3_memoryStore","width":1},{"name":"entries_3_memoryValid","width":1},{"name":"entries_3_opcode","width":12},{"name":"entries_3_pc","width":64},{"name":"entries_3_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_3_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_3_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_3_pcBufferIndexOffset_valid","width":1},{"name":"entries_3_result","width":64},{"name":"entries_3_resultValid","width":1},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robGroupLast","width":1},{"name":"entries_3_storeData","width":64},{"name":"entries_3_storeMask","width":8},{"name":"entries_3_trap_cause","width":32},{"name":"entries_3_trap_instruction_epoch","width":16},{"name":"entries_3_trap_instruction_instructionId","width":64},{"name":"entries_3_trap_instruction_peId","width":8},{"name":"entries_3_trap_instruction_stid","width":1},{"name":"entries_3_trap_kind","width":2},{"name":"entries_3_trap_rob_bid","width":8},{"name":"entries_3_trap_rob_brobGeneration","width":16},{"name":"entries_3_trap_rob_memberIndex","width":2},{"name":"entries_3_trap_rob_peId","width":8},{"name":"entries_3_trap_rob_residentGeneration","width":16},{"name":"entries_3_trap_rob_ridGeneration","width":16},{"name":"entries_3_trap_rob_ridSlot","width":6},{"name":"entries_3_trap_rob_stid","width":1},{"name":"entries_3_trap_targetPc","width":64},{"name":"entries_3_trap_tval","width":64},{"name":"entries_3_trap_valid","width":1},{"name":"entries_4_destination_atag","width":6},{"name":"entries_4_destination_kind","width":3},{"name":"entries_4_destination_pGeneration","width":16},{"name":"entries_4_destination_previousPGeneration","width":16},{"name":"entries_4_destination_previousPtag","width":7},{"name":"entries_4_destination_previousPtagValid","width":1},{"name":"entries_4_destination_previousTtag","width":5},{"name":"entries_4_destination_previousTtagValid","width":1},{"name":"entries_4_destination_previousUtag","width":5},{"name":"entries_4_destination_previousUtagValid","width":1},{"name":"entries_4_destination_ptag","width":7},{"name":"entries_4_destination_ptagValid","width":1},{"name":"entries_4_destination_tGeneration","width":16},{"name":"entries_4_destination_tSeqGeneration","width":16},{"name":"entries_4_destination_tSeqIndex","width":5},{"name":"entries_4_destination_ttag","width":5},{"name":"entries_4_destination_ttagValid","width":1},{"name":"entries_4_destination_uGeneration","width":16},{"name":"entries_4_destination_uSeqGeneration","width":16},{"name":"entries_4_destination_uSeqIndex","width":5},{"name":"entries_4_destination_utag","width":5},{"name":"entries_4_destination_utagValid","width":1},{"name":"entries_4_destination_valid","width":1},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionBits","width":64},{"name":"entries_4_instructionLengthBytes","width":4},{"name":"entries_4_memory_attemptGeneration","width":16},{"name":"entries_4_memory_lsid","width":32},{"name":"entries_4_memory_pipeId","width":1},{"name":"entries_4_memory_rob_bid","width":8},{"name":"entries_4_memory_rob_brobGeneration","width":16},{"name":"entries_4_memory_rob_memberIndex","width":2},{"name":"entries_4_memory_rob_peId","width":8},{"name":"entries_4_memory_rob_residentGeneration","width":16},{"name":"entries_4_memory_rob_ridGeneration","width":16},{"name":"entries_4_memory_rob_ridSlot","width":6},{"name":"entries_4_memory_rob_stid","width":1},{"name":"entries_4_memory_transaction_generation","width":16},{"name":"entries_4_memory_transaction_value","width":64},{"name":"entries_4_memoryOrder_firstLid","width":32},{"name":"entries_4_memoryOrder_firstLsid","width":32},{"name":"entries_4_memoryOrder_firstSid","width":32},{"name":"entries_4_memoryOrder_requestCount","width":2},{"name":"entries_4_memoryOrder_yoldLid","width":32},{"name":"entries_4_memoryOrder_yoldLsid","width":32},{"name":"entries_4_memoryOrder_yoldValid","width":1},{"name":"entries_4_memoryOrder_yostLsid","width":32},{"name":"entries_4_memoryOrder_yostSid","width":32},{"name":"entries_4_memoryOrder_yostValid","width":1},{"name":"entries_4_memoryStore","width":1},{"name":"entries_4_memoryValid","width":1},{"name":"entries_4_opcode","width":12},{"name":"entries_4_pc","width":64},{"name":"entries_4_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_4_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_4_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_4_pcBufferIndexOffset_valid","width":1},{"name":"entries_4_result","width":64},{"name":"entries_4_resultValid","width":1},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robGroupLast","width":1},{"name":"entries_4_storeData","width":64},{"name":"entries_4_storeMask","width":8},{"name":"entries_4_trap_cause","width":32},{"name":"entries_4_trap_instruction_epoch","width":16},{"name":"entries_4_trap_instruction_instructionId","width":64},{"name":"entries_4_trap_instruction_peId","width":8},{"name":"entries_4_trap_instruction_stid","width":1},{"name":"entries_4_trap_kind","width":2},{"name":"entries_4_trap_rob_bid","width":8},{"name":"entries_4_trap_rob_brobGeneration","width":16},{"name":"entries_4_trap_rob_memberIndex","width":2},{"name":"entries_4_trap_rob_peId","width":8},{"name":"entries_4_trap_rob_residentGeneration","width":16},{"name":"entries_4_trap_rob_ridGeneration","width":16},{"name":"entries_4_trap_rob_ridSlot","width":6},{"name":"entries_4_trap_rob_stid","width":1},{"name":"entries_4_trap_targetPc","width":64},{"name":"entries_4_trap_tval","width":64},{"name":"entries_4_trap_valid","width":1},{"name":"entries_5_destination_atag","width":6},{"name":"entries_5_destination_kind","width":3},{"name":"entries_5_destination_pGeneration","width":16},{"name":"entries_5_destination_previousPGeneration","width":16},{"name":"entries_5_destination_previousPtag","width":7},{"name":"entries_5_destination_previousPtagValid","width":1},{"name":"entries_5_destination_previousTtag","width":5},{"name":"entries_5_destination_previousTtagValid","width":1},{"name":"entries_5_destination_previousUtag","width":5},{"name":"entries_5_destination_previousUtagValid","width":1},{"name":"entries_5_destination_ptag","width":7},{"name":"entries_5_destination_ptagValid","width":1},{"name":"entries_5_destination_tGeneration","width":16},{"name":"entries_5_destination_tSeqGeneration","width":16},{"name":"entries_5_destination_tSeqIndex","width":5},{"name":"entries_5_destination_ttag","width":5},{"name":"entries_5_destination_ttagValid","width":1},{"name":"entries_5_destination_uGeneration","width":16},{"name":"entries_5_destination_uSeqGeneration","width":16},{"name":"entries_5_destination_uSeqIndex","width":5},{"name":"entries_5_destination_utag","width":5},{"name":"entries_5_destination_utagValid","width":1},{"name":"entries_5_destination_valid","width":1},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionBits","width":64},{"name":"entries_5_instructionLengthBytes","width":4},{"name":"entries_5_memory_attemptGeneration","width":16},{"name":"entries_5_memory_lsid","width":32},{"name":"entries_5_memory_pipeId","width":1},{"name":"entries_5_memory_rob_bid","width":8},{"name":"entries_5_memory_rob_brobGeneration","width":16},{"name":"entries_5_memory_rob_memberIndex","width":2},{"name":"entries_5_memory_rob_peId","width":8},{"name":"entries_5_memory_rob_residentGeneration","width":16},{"name":"entries_5_memory_rob_ridGeneration","width":16},{"name":"entries_5_memory_rob_ridSlot","width":6},{"name":"entries_5_memory_rob_stid","width":1},{"name":"entries_5_memory_transaction_generation","width":16},{"name":"entries_5_memory_transaction_value","width":64},{"name":"entries_5_memoryOrder_firstLid","width":32},{"name":"entries_5_memoryOrder_firstLsid","width":32},{"name":"entries_5_memoryOrder_firstSid","width":32},{"name":"entries_5_memoryOrder_requestCount","width":2},{"name":"entries_5_memoryOrder_yoldLid","width":32},{"name":"entries_5_memoryOrder_yoldLsid","width":32},{"name":"entries_5_memoryOrder_yoldValid","width":1},{"name":"entries_5_memoryOrder_yostLsid","width":32},{"name":"entries_5_memoryOrder_yostSid","width":32},{"name":"entries_5_memoryOrder_yostValid","width":1},{"name":"entries_5_memoryStore","width":1},{"name":"entries_5_memoryValid","width":1},{"name":"entries_5_opcode","width":12},{"name":"entries_5_pc","width":64},{"name":"entries_5_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_5_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_5_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_5_pcBufferIndexOffset_valid","width":1},{"name":"entries_5_result","width":64},{"name":"entries_5_resultValid","width":1},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robGroupLast","width":1},{"name":"entries_5_storeData","width":64},{"name":"entries_5_storeMask","width":8},{"name":"entries_5_trap_cause","width":32},{"name":"entries_5_trap_instruction_epoch","width":16},{"name":"entries_5_trap_instruction_instructionId","width":64},{"name":"entries_5_trap_instruction_peId","width":8},{"name":"entries_5_trap_instruction_stid","width":1},{"name":"entries_5_trap_kind","width":2},{"name":"entries_5_trap_rob_bid","width":8},{"name":"entries_5_trap_rob_brobGeneration","width":16},{"name":"entries_5_trap_rob_memberIndex","width":2},{"name":"entries_5_trap_rob_peId","width":8},{"name":"entries_5_trap_rob_residentGeneration","width":16},{"name":"entries_5_trap_rob_ridGeneration","width":16},{"name":"entries_5_trap_rob_ridSlot","width":6},{"name":"entries_5_trap_rob_stid","width":1},{"name":"entries_5_trap_targetPc","width":64},{"name":"entries_5_trap_tval","width":64},{"name":"entries_5_trap_valid","width":1},{"name":"entries_6_destination_atag","width":6},{"name":"entries_6_destination_kind","width":3},{"name":"entries_6_destination_pGeneration","width":16},{"name":"entries_6_destination_previousPGeneration","width":16},{"name":"entries_6_destination_previousPtag","width":7},{"name":"entries_6_destination_previousPtagValid","width":1},{"name":"entries_6_destination_previousTtag","width":5},{"name":"entries_6_destination_previousTtagValid","width":1},{"name":"entries_6_destination_previousUtag","width":5},{"name":"entries_6_destination_previousUtagValid","width":1},{"name":"entries_6_destination_ptag","width":7},{"name":"entries_6_destination_ptagValid","width":1},{"name":"entries_6_destination_tGeneration","width":16},{"name":"entries_6_destination_tSeqGeneration","width":16},{"name":"entries_6_destination_tSeqIndex","width":5},{"name":"entries_6_destination_ttag","width":5},{"name":"entries_6_destination_ttagValid","width":1},{"name":"entries_6_destination_uGeneration","width":16},{"name":"entries_6_destination_uSeqGeneration","width":16},{"name":"entries_6_destination_uSeqIndex","width":5},{"name":"entries_6_destination_utag","width":5},{"name":"entries_6_destination_utagValid","width":1},{"name":"entries_6_destination_valid","width":1},{"name":"entries_6_instruction_epoch","width":16},{"name":"entries_6_instruction_instructionId","width":64},{"name":"entries_6_instruction_peId","width":8},{"name":"entries_6_instruction_stid","width":1},{"name":"entries_6_instructionBits","width":64},{"name":"entries_6_instructionLengthBytes","width":4},{"name":"entries_6_memory_attemptGeneration","width":16},{"name":"entries_6_memory_lsid","width":32},{"name":"entries_6_memory_pipeId","width":1},{"name":"entries_6_memory_rob_bid","width":8},{"name":"entries_6_memory_rob_brobGeneration","width":16},{"name":"entries_6_memory_rob_memberIndex","width":2},{"name":"entries_6_memory_rob_peId","width":8},{"name":"entries_6_memory_rob_residentGeneration","width":16},{"name":"entries_6_memory_rob_ridGeneration","width":16},{"name":"entries_6_memory_rob_ridSlot","width":6},{"name":"entries_6_memory_rob_stid","width":1},{"name":"entries_6_memory_transaction_generation","width":16},{"name":"entries_6_memory_transaction_value","width":64},{"name":"entries_6_memoryOrder_firstLid","width":32},{"name":"entries_6_memoryOrder_firstLsid","width":32},{"name":"entries_6_memoryOrder_firstSid","width":32},{"name":"entries_6_memoryOrder_requestCount","width":2},{"name":"entries_6_memoryOrder_yoldLid","width":32},{"name":"entries_6_memoryOrder_yoldLsid","width":32},{"name":"entries_6_memoryOrder_yoldValid","width":1},{"name":"entries_6_memoryOrder_yostLsid","width":32},{"name":"entries_6_memoryOrder_yostSid","width":32},{"name":"entries_6_memoryOrder_yostValid","width":1},{"name":"entries_6_memoryStore","width":1},{"name":"entries_6_memoryValid","width":1},{"name":"entries_6_opcode","width":12},{"name":"entries_6_pc","width":64},{"name":"entries_6_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_6_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_6_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_6_pcBufferIndexOffset_valid","width":1},{"name":"entries_6_result","width":64},{"name":"entries_6_resultValid","width":1},{"name":"entries_6_rob_bid","width":8},{"name":"entries_6_rob_brobGeneration","width":16},{"name":"entries_6_rob_memberIndex","width":2},{"name":"entries_6_rob_peId","width":8},{"name":"entries_6_rob_residentGeneration","width":16},{"name":"entries_6_rob_ridGeneration","width":16},{"name":"entries_6_rob_ridSlot","width":6},{"name":"entries_6_rob_stid","width":1},{"name":"entries_6_robGroupLast","width":1},{"name":"entries_6_storeData","width":64},{"name":"entries_6_storeMask","width":8},{"name":"entries_6_trap_cause","width":32},{"name":"entries_6_trap_instruction_epoch","width":16},{"name":"entries_6_trap_instruction_instructionId","width":64},{"name":"entries_6_trap_instruction_peId","width":8},{"name":"entries_6_trap_instruction_stid","width":1},{"name":"entries_6_trap_kind","width":2},{"name":"entries_6_trap_rob_bid","width":8},{"name":"entries_6_trap_rob_brobGeneration","width":16},{"name":"entries_6_trap_rob_memberIndex","width":2},{"name":"entries_6_trap_rob_peId","width":8},{"name":"entries_6_trap_rob_residentGeneration","width":16},{"name":"entries_6_trap_rob_ridGeneration","width":16},{"name":"entries_6_trap_rob_ridSlot","width":6},{"name":"entries_6_trap_rob_stid","width":1},{"name":"entries_6_trap_targetPc","width":64},{"name":"entries_6_trap_tval","width":64},{"name":"entries_6_trap_valid","width":1},{"name":"entries_7_destination_atag","width":6},{"name":"entries_7_destination_kind","width":3},{"name":"entries_7_destination_pGeneration","width":16},{"name":"entries_7_destination_previousPGeneration","width":16},{"name":"entries_7_destination_previousPtag","width":7},{"name":"entries_7_destination_previousPtagValid","width":1},{"name":"entries_7_destination_previousTtag","width":5},{"name":"entries_7_destination_previousTtagValid","width":1},{"name":"entries_7_destination_previousUtag","width":5},{"name":"entries_7_destination_previousUtagValid","width":1},{"name":"entries_7_destination_ptag","width":7},{"name":"entries_7_destination_ptagValid","width":1},{"name":"entries_7_destination_tGeneration","width":16},{"name":"entries_7_destination_tSeqGeneration","width":16},{"name":"entries_7_destination_tSeqIndex","width":5},{"name":"entries_7_destination_ttag","width":5},{"name":"entries_7_destination_ttagValid","width":1},{"name":"entries_7_destination_uGeneration","width":16},{"name":"entries_7_destination_uSeqGeneration","width":16},{"name":"entries_7_destination_uSeqIndex","width":5},{"name":"entries_7_destination_utag","width":5},{"name":"entries_7_destination_utagValid","width":1},{"name":"entries_7_destination_valid","width":1},{"name":"entries_7_instruction_epoch","width":16},{"name":"entries_7_instruction_instructionId","width":64},{"name":"entries_7_instruction_peId","width":8},{"name":"entries_7_instruction_stid","width":1},{"name":"entries_7_instructionBits","width":64},{"name":"entries_7_instructionLengthBytes","width":4},{"name":"entries_7_memory_attemptGeneration","width":16},{"name":"entries_7_memory_lsid","width":32},{"name":"entries_7_memory_pipeId","width":1},{"name":"entries_7_memory_rob_bid","width":8},{"name":"entries_7_memory_rob_brobGeneration","width":16},{"name":"entries_7_memory_rob_memberIndex","width":2},{"name":"entries_7_memory_rob_peId","width":8},{"name":"entries_7_memory_rob_residentGeneration","width":16},{"name":"entries_7_memory_rob_ridGeneration","width":16},{"name":"entries_7_memory_rob_ridSlot","width":6},{"name":"entries_7_memory_rob_stid","width":1},{"name":"entries_7_memory_transaction_generation","width":16},{"name":"entries_7_memory_transaction_value","width":64},{"name":"entries_7_memoryOrder_firstLid","width":32},{"name":"entries_7_memoryOrder_firstLsid","width":32},{"name":"entries_7_memoryOrder_firstSid","width":32},{"name":"entries_7_memoryOrder_requestCount","width":2},{"name":"entries_7_memoryOrder_yoldLid","width":32},{"name":"entries_7_memoryOrder_yoldLsid","width":32},{"name":"entries_7_memoryOrder_yoldValid","width":1},{"name":"entries_7_memoryOrder_yostLsid","width":32},{"name":"entries_7_memoryOrder_yostSid","width":32},{"name":"entries_7_memoryOrder_yostValid","width":1},{"name":"entries_7_memoryStore","width":1},{"name":"entries_7_memoryValid","width":1},{"name":"entries_7_opcode","width":12},{"name":"entries_7_pc","width":64},{"name":"entries_7_pcBufferIndexOffset_allocationEpoch","width":16},{"name":"entries_7_pcBufferIndexOffset_pcBufferIndex","width":6},{"name":"entries_7_pcBufferIndexOffset_pcOffset","width":7},{"name":"entries_7_pcBufferIndexOffset_valid","width":1},{"name":"entries_7_result","width":64},{"name":"entries_7_resultValid","width":1},{"name":"entries_7_rob_bid","width":8},{"name":"entries_7_rob_brobGeneration","width":16},{"name":"entries_7_rob_memberIndex","width":2},{"name":"entries_7_rob_peId","width":8},{"name":"entries_7_rob_residentGeneration","width":16},{"name":"entries_7_rob_ridGeneration","width":16},{"name":"entries_7_rob_ridSlot","width":6},{"name":"entries_7_rob_stid","width":1},{"name":"entries_7_robGroupLast","width":1},{"name":"entries_7_storeData","width":64},{"name":"entries_7_storeMask","width":8},{"name":"entries_7_trap_cause","width":32},{"name":"entries_7_trap_instruction_epoch","width":16},{"name":"entries_7_trap_instruction_instructionId","width":64},{"name":"entries_7_trap_instruction_peId","width":8},{"name":"entries_7_trap_instruction_stid","width":1},{"name":"entries_7_trap_kind","width":2},{"name":"entries_7_trap_rob_bid","width":8},{"name":"entries_7_trap_rob_brobGeneration","width":16},{"name":"entries_7_trap_rob_memberIndex","width":2},{"name":"entries_7_trap_rob_peId","width":8},{"name":"entries_7_trap_rob_residentGeneration","width":16},{"name":"entries_7_trap_rob_ridGeneration","width":16},{"name":"entries_7_trap_rob_ridSlot","width":6},{"name":"entries_7_trap_rob_stid","width":1},{"name":"entries_7_trap_targetPc","width":64},{"name":"entries_7_trap_tval","width":64},{"name":"entries_7_trap_valid","width":1}]},{"name":"box_to_dtu_trace","contract_id":"IFC-DTU-001","producer":"TOP/IFU/CTU/OOO/IEX/LSU","consumer":"DTU","lanes":8,"payload":"TracePacket","ports":[{"name":"count","width":4},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3},{"name":"entries_4_cycle","width":64},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionValid","width":1},{"name":"entries_4_kind","width":3},{"name":"entries_4_opcode","width":12},{"name":"entries_4_payload","width":64},{"name":"entries_4_pc","width":64},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robValid","width":1},{"name":"entries_4_source","width":3},{"name":"entries_5_cycle","width":64},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionValid","width":1},{"name":"entries_5_kind","width":3},{"name":"entries_5_opcode","width":12},{"name":"entries_5_payload","width":64},{"name":"entries_5_pc","width":64},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robValid","width":1},{"name":"entries_5_source","width":3},{"name":"entries_6_cycle","width":64},{"name":"entries_6_instruction_epoch","width":16},{"name":"entries_6_instruction_instructionId","width":64},{"name":"entries_6_instruction_peId","width":8},{"name":"entries_6_instruction_stid","width":1},{"name":"entries_6_instructionValid","width":1},{"name":"entries_6_kind","width":3},{"name":"entries_6_opcode","width":12},{"name":"entries_6_payload","width":64},{"name":"entries_6_pc","width":64},{"name":"entries_6_rob_bid","width":8},{"name":"entries_6_rob_brobGeneration","width":16},{"name":"entries_6_rob_memberIndex","width":2},{"name":"entries_6_rob_peId","width":8},{"name":"entries_6_rob_residentGeneration","width":16},{"name":"entries_6_rob_ridGeneration","width":16},{"name":"entries_6_rob_ridSlot","width":6},{"name":"entries_6_rob_stid","width":1},{"name":"entries_6_robValid","width":1},{"name":"entries_6_source","width":3},{"name":"entries_7_cycle","width":64},{"name":"entries_7_instruction_epoch","width":16},{"name":"entries_7_instruction_instructionId","width":64},{"name":"entries_7_instruction_peId","width":8},{"name":"entries_7_instruction_stid","width":1},{"name":"entries_7_instructionValid","width":1},{"name":"entries_7_kind","width":3},{"name":"entries_7_opcode","width":12},{"name":"entries_7_payload","width":64},{"name":"entries_7_pc","width":64},{"name":"entries_7_rob_bid","width":8},{"name":"entries_7_rob_brobGeneration","width":16},{"name":"entries_7_rob_memberIndex","width":2},{"name":"entries_7_rob_peId","width":8},{"name":"entries_7_rob_residentGeneration","width":16},{"name":"entries_7_rob_ridGeneration","width":16},{"name":"entries_7_rob_ridSlot","width":6},{"name":"entries_7_rob_stid","width":1},{"name":"entries_7_robValid","width":1},{"name":"entries_7_source","width":3}]},{"name":"external_to_dtu_debug_request","contract_id":"IFC-DTU-001","producer":"External Debug","consumer":"DTU","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_ooo_debug_request","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"OOO","lanes":1,"payload":"DebugRequest","ports":[{"name":"address","width":64},{"name":"command","width":3},{"name":"data","width":64},{"name":"stid","width":1},{"name":"transactionId","width":64}]},{"name":"ooo_to_dtu_debug_response","contract_id":"IFC-DTU-001","producer":"OOO","consumer":"DTU","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_to_external_debug_response","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Debug","lanes":1,"payload":"DebugResponse","ports":[{"name":"accepted","width":1},{"name":"data","width":64},{"name":"error","width":1},{"name":"transactionId","width":64}]},{"name":"dtu_trace_export","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Trace","lanes":8,"payload":"TracePacket","ports":[{"name":"count","width":4},{"name":"entries_0_cycle","width":64},{"name":"entries_0_instruction_epoch","width":16},{"name":"entries_0_instruction_instructionId","width":64},{"name":"entries_0_instruction_peId","width":8},{"name":"entries_0_instruction_stid","width":1},{"name":"entries_0_instructionValid","width":1},{"name":"entries_0_kind","width":3},{"name":"entries_0_opcode","width":12},{"name":"entries_0_payload","width":64},{"name":"entries_0_pc","width":64},{"name":"entries_0_rob_bid","width":8},{"name":"entries_0_rob_brobGeneration","width":16},{"name":"entries_0_rob_memberIndex","width":2},{"name":"entries_0_rob_peId","width":8},{"name":"entries_0_rob_residentGeneration","width":16},{"name":"entries_0_rob_ridGeneration","width":16},{"name":"entries_0_rob_ridSlot","width":6},{"name":"entries_0_rob_stid","width":1},{"name":"entries_0_robValid","width":1},{"name":"entries_0_source","width":3},{"name":"entries_1_cycle","width":64},{"name":"entries_1_instruction_epoch","width":16},{"name":"entries_1_instruction_instructionId","width":64},{"name":"entries_1_instruction_peId","width":8},{"name":"entries_1_instruction_stid","width":1},{"name":"entries_1_instructionValid","width":1},{"name":"entries_1_kind","width":3},{"name":"entries_1_opcode","width":12},{"name":"entries_1_payload","width":64},{"name":"entries_1_pc","width":64},{"name":"entries_1_rob_bid","width":8},{"name":"entries_1_rob_brobGeneration","width":16},{"name":"entries_1_rob_memberIndex","width":2},{"name":"entries_1_rob_peId","width":8},{"name":"entries_1_rob_residentGeneration","width":16},{"name":"entries_1_rob_ridGeneration","width":16},{"name":"entries_1_rob_ridSlot","width":6},{"name":"entries_1_rob_stid","width":1},{"name":"entries_1_robValid","width":1},{"name":"entries_1_source","width":3},{"name":"entries_2_cycle","width":64},{"name":"entries_2_instruction_epoch","width":16},{"name":"entries_2_instruction_instructionId","width":64},{"name":"entries_2_instruction_peId","width":8},{"name":"entries_2_instruction_stid","width":1},{"name":"entries_2_instructionValid","width":1},{"name":"entries_2_kind","width":3},{"name":"entries_2_opcode","width":12},{"name":"entries_2_payload","width":64},{"name":"entries_2_pc","width":64},{"name":"entries_2_rob_bid","width":8},{"name":"entries_2_rob_brobGeneration","width":16},{"name":"entries_2_rob_memberIndex","width":2},{"name":"entries_2_rob_peId","width":8},{"name":"entries_2_rob_residentGeneration","width":16},{"name":"entries_2_rob_ridGeneration","width":16},{"name":"entries_2_rob_ridSlot","width":6},{"name":"entries_2_rob_stid","width":1},{"name":"entries_2_robValid","width":1},{"name":"entries_2_source","width":3},{"name":"entries_3_cycle","width":64},{"name":"entries_3_instruction_epoch","width":16},{"name":"entries_3_instruction_instructionId","width":64},{"name":"entries_3_instruction_peId","width":8},{"name":"entries_3_instruction_stid","width":1},{"name":"entries_3_instructionValid","width":1},{"name":"entries_3_kind","width":3},{"name":"entries_3_opcode","width":12},{"name":"entries_3_payload","width":64},{"name":"entries_3_pc","width":64},{"name":"entries_3_rob_bid","width":8},{"name":"entries_3_rob_brobGeneration","width":16},{"name":"entries_3_rob_memberIndex","width":2},{"name":"entries_3_rob_peId","width":8},{"name":"entries_3_rob_residentGeneration","width":16},{"name":"entries_3_rob_ridGeneration","width":16},{"name":"entries_3_rob_ridSlot","width":6},{"name":"entries_3_rob_stid","width":1},{"name":"entries_3_robValid","width":1},{"name":"entries_3_source","width":3},{"name":"entries_4_cycle","width":64},{"name":"entries_4_instruction_epoch","width":16},{"name":"entries_4_instruction_instructionId","width":64},{"name":"entries_4_instruction_peId","width":8},{"name":"entries_4_instruction_stid","width":1},{"name":"entries_4_instructionValid","width":1},{"name":"entries_4_kind","width":3},{"name":"entries_4_opcode","width":12},{"name":"entries_4_payload","width":64},{"name":"entries_4_pc","width":64},{"name":"entries_4_rob_bid","width":8},{"name":"entries_4_rob_brobGeneration","width":16},{"name":"entries_4_rob_memberIndex","width":2},{"name":"entries_4_rob_peId","width":8},{"name":"entries_4_rob_residentGeneration","width":16},{"name":"entries_4_rob_ridGeneration","width":16},{"name":"entries_4_rob_ridSlot","width":6},{"name":"entries_4_rob_stid","width":1},{"name":"entries_4_robValid","width":1},{"name":"entries_4_source","width":3},{"name":"entries_5_cycle","width":64},{"name":"entries_5_instruction_epoch","width":16},{"name":"entries_5_instruction_instructionId","width":64},{"name":"entries_5_instruction_peId","width":8},{"name":"entries_5_instruction_stid","width":1},{"name":"entries_5_instructionValid","width":1},{"name":"entries_5_kind","width":3},{"name":"entries_5_opcode","width":12},{"name":"entries_5_payload","width":64},{"name":"entries_5_pc","width":64},{"name":"entries_5_rob_bid","width":8},{"name":"entries_5_rob_brobGeneration","width":16},{"name":"entries_5_rob_memberIndex","width":2},{"name":"entries_5_rob_peId","width":8},{"name":"entries_5_rob_residentGeneration","width":16},{"name":"entries_5_rob_ridGeneration","width":16},{"name":"entries_5_rob_ridSlot","width":6},{"name":"entries_5_rob_stid","width":1},{"name":"entries_5_robValid","width":1},{"name":"entries_5_source","width":3},{"name":"entries_6_cycle","width":64},{"name":"entries_6_instruction_epoch","width":16},{"name":"entries_6_instruction_instructionId","width":64},{"name":"entries_6_instruction_peId","width":8},{"name":"entries_6_instruction_stid","width":1},{"name":"entries_6_instructionValid","width":1},{"name":"entries_6_kind","width":3},{"name":"entries_6_opcode","width":12},{"name":"entries_6_payload","width":64},{"name":"entries_6_pc","width":64},{"name":"entries_6_rob_bid","width":8},{"name":"entries_6_rob_brobGeneration","width":16},{"name":"entries_6_rob_memberIndex","width":2},{"name":"entries_6_rob_peId","width":8},{"name":"entries_6_rob_residentGeneration","width":16},{"name":"entries_6_rob_ridGeneration","width":16},{"name":"entries_6_rob_ridSlot","width":6},{"name":"entries_6_rob_stid","width":1},{"name":"entries_6_robValid","width":1},{"name":"entries_6_source","width":3},{"name":"entries_7_cycle","width":64},{"name":"entries_7_instruction_epoch","width":16},{"name":"entries_7_instruction_instructionId","width":64},{"name":"entries_7_instruction_peId","width":8},{"name":"entries_7_instruction_stid","width":1},{"name":"entries_7_instructionValid","width":1},{"name":"entries_7_kind","width":3},{"name":"entries_7_opcode","width":12},{"name":"entries_7_payload","width":64},{"name":"entries_7_pc","width":64},{"name":"entries_7_rob_bid","width":8},{"name":"entries_7_rob_brobGeneration","width":16},{"name":"entries_7_rob_memberIndex","width":2},{"name":"entries_7_rob_peId","width":8},{"name":"entries_7_rob_residentGeneration","width":16},{"name":"entries_7_rob_ridGeneration","width":16},{"name":"entries_7_rob_ridSlot","width":6},{"name":"entries_7_rob_stid","width":1},{"name":"entries_7_robValid","width":1},{"name":"entries_7_source","width":3}]},{"name":"dtu_performance_counter","contract_id":"IFC-DTU-001","producer":"DTU","consumer":"External Counter","lanes":32,"payload":"UInt","ports":[{"name":"","width":64}]},{"name":"instruction_memory_request","contract_id":"IFC-MEMORY-001","producer":"IFU","consumer":"Memory","lanes":1,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"instruction_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"IFU","lanes":1,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]},{"name":"data_memory_request","contract_id":"IFC-MEMORY-001","producer":"LSU","consumer":"Memory","lanes":4,"payload":"MemoryRequestTxn","ports":[{"name":"accessKind","width":2},{"name":"address","width":64},{"name":"byteMask","width":8},{"name":"command","width":3},{"name":"data","width":64},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"instructionSide","width":1},{"name":"size","width":3}]},{"name":"data_memory_response","contract_id":"IFC-MEMORY-001","producer":"Memory","consumer":"LSU","lanes":4,"payload":"MemoryResponseTxn","ports":[{"name":"address","width":64},{"name":"attributesValid","width":1},{"name":"cacheable","width":1},{"name":"corrupt","width":1},{"name":"data","width":64},{"name":"denied","width":1},{"name":"device","width":1},{"name":"errorCause","width":32},{"name":"identity_generation","width":16},{"name":"identity_value","width":64},{"name":"lineData","width":512},{"name":"readable","width":1},{"name":"writable","width":1}]}]}]} diff --git a/docs/chisel/generated/top-interface-manifest.md b/docs/chisel/generated/top-interface-manifest.md new file mode 100644 index 00000000..2107fb43 --- /dev/null +++ b/docs/chisel/generated/top-interface-manifest.md @@ -0,0 +1,190 @@ +# Generated TOP interface manifest + +This file is generated from the canonical Scala Bundle types. Do not edit it by hand. + +| Profile | Endpoint | Contract | Producer | Consumer | Lanes | Payload | Leaf ports | Payload bits | +|---|---|---|---|---|---:|---|---:|---:| +| W2 | `top_io` | [[IFC-TOP-EXT-002]] | Platform | TOP | 1 | `TOPIO` | 520 | 12892 | +| W2 | `ifu_to_ctu` | [[IFC-IFU-CTU-001]] | IFU | CTU | 2 | `FetchedPacket` | 43 | 1214 | +| W2 | `ctu_to_ooo` | [[IFC-CTU-OOO-001]] | CTU | OOO | 2 | `D1Packet` | 53 | 1400 | +| W2 | `ooo_to_iex_alu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2358 | +| W2 | `ooo_to_iex_bru` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2358 | +| W2 | `ooo_to_iex_agu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2358 | +| W2 | `ooo_to_iex_std` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `StoreDispatchTxn` | 512 | 4718 | +| W2 | `ooo_to_iex_system` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2358 | +| W2 | `ooo_to_iex_cmd` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2358 | +| W2 | `ooo_to_iex_rob_noflush` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `RobNoflushTxn` | 13 | 226 | +| W2 | `iex_to_ooo_rob_noflush_ready` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `RobNoflushReadyTxn` | 13 | 226 | +| W2 | `iex_to_ooo_rob_resolve` | [[IFC-OOO-IEX-001]] | IEX | OOO | 2 | `RobResolveTxn` | 29 | 528 | +| W2 | `iex_to_ooo_system_issue` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `SystemIssueTxn` | 15 | 302 | +| W2 | `ooo_to_top_system_issue` | [[IFC-OOO-IEX-001]] | OOO | TOP | 1 | `SystemIssueTxn` | 15 | 302 | +| W2 | `iex_to_ooo_pc_buffer_read_address` | [[IFC-OOO-IEX-001]] | IEX | OOO | 6 | `PcBufferReadAddress` | 4 | 24 | +| W2 | `ooo_to_iex_pc_buffer_read_pc_base` | [[IFC-OOO-IEX-001]] | OOO | IEX | 6 | `UInt` | 1 | 64 | +| W2 | `iex_to_lsu_load_issue` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `LoadIssueTxn` | 44 | 562 | +| W2 | `lsu_to_iex_load_allocation_preview` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadAllocationPreview` | 15 | 282 | +| W2 | `lsu_to_iex_load_launch` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadLaunchTxn` | 15 | 282 | +| W2 | `iex_to_lsu_store_reservation` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreReservationTxn` | 26 | 454 | +| W2 | `iex_to_lsu_store_address` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreAddressTxn` | 27 | 501 | +| W2 | `iex_to_lsu_store_data` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreDataTxn` | 30 | 581 | +| W2 | `lsu_to_iex_load_result` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadResultTxn` | 57 | 833 | +| W2 | `lsu_to_iex_load_reissue` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadReissueTxn` | 29 | 548 | +| W2 | `lsu_to_iex_load_repick` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadRepickTxn` | 28 | 484 | +| W2 | `lsu_to_iex_load_cancel` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadCancelTxn` | 13 | 202 | +| W2 | `ooo_to_lsu_store_commit` | [[IFC-IEX-LSU-001]] | OOO | LSU | 1 | `StoreCommitAuthorizationTxn` | 14 | 220 | +| W2 | `lsu_internal_store_classify` | [[IFC-IEX-LSU-001]] | LSU Translation | LSU Commit Backend | 1 | `StoreMemoryClassifyTxn` | 16 | 254 | +| W2 | `external_cmd_issue` | [[IFC-TOP-EXT-001]] | IEX | External CMD | 1 | `CmdIssueTxn` | 19 | 498 | +| W2 | `owner_to_ooo_recovery_event` | [[IFC-RECOVERY-001]] | IEX/LSU | OOO | 1 | `RecoveryEvent` | 32 | 618 | +| W2 | `ooo_recovery_prepare` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W2 | `target_to_ooo_recovery_prepared` | [[IFC-RECOVERY-001]] | IFU/CTU/IEX/LSU | OOO | 1 | `RecoveryPlan` | 41 | 459 | +| W2 | `ooo_recovery_apply` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W2 | `ooo_recovery_abort` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W2 | `ooo_commit` | [[IFC-COMMIT-001]] | OOO | TOP/DTU | 2 | `CommitTxn` | 181 | 2776 | +| W2 | `box_to_dtu_trace` | [[IFC-DTU-001]] | TOP/IFU/CTU/OOO/IEX/LSU | DTU | 2 | `TracePacket` | 41 | 750 | +| W2 | `external_to_dtu_debug_request` | [[IFC-DTU-001]] | External Debug | DTU | 1 | `DebugRequest` | 5 | 196 | +| W2 | `dtu_to_ooo_debug_request` | [[IFC-DTU-001]] | DTU | OOO | 1 | `DebugRequest` | 5 | 196 | +| W2 | `ooo_to_dtu_debug_response` | [[IFC-DTU-001]] | OOO | DTU | 1 | `DebugResponse` | 4 | 130 | +| W2 | `dtu_to_external_debug_response` | [[IFC-DTU-001]] | DTU | External Debug | 1 | `DebugResponse` | 4 | 130 | +| W2 | `dtu_trace_export` | [[IFC-DTU-001]] | DTU | External Trace | 2 | `TracePacket` | 41 | 750 | +| W2 | `dtu_performance_counter` | [[IFC-DTU-001]] | DTU | External Counter | 32 | `UInt` | 1 | 64 | +| W2 | `instruction_memory_request` | [[IFC-MEMORY-001]] | IFU | Memory | 1 | `MemoryRequestTxn` | 9 | 225 | +| W2 | `instruction_memory_response` | [[IFC-MEMORY-001]] | Memory | IFU | 1 | `MemoryResponseTxn` | 13 | 759 | +| W2 | `data_memory_request` | [[IFC-MEMORY-001]] | LSU | Memory | 4 | `MemoryRequestTxn` | 9 | 225 | +| W2 | `data_memory_response` | [[IFC-MEMORY-001]] | Memory | LSU | 4 | `MemoryResponseTxn` | 13 | 759 | +| W4 | `top_io` | [[IFC-TOP-EXT-002]] | Platform | TOP | 1 | `TOPIO` | 740 | 16416 | +| W4 | `ifu_to_ctu` | [[IFC-IFU-CTU-001]] | IFU | CTU | 4 | `FetchedPacket` | 85 | 2427 | +| W4 | `ctu_to_ooo` | [[IFC-CTU-OOO-001]] | CTU | OOO | 4 | `D1Packet` | 105 | 2799 | +| W4 | `ooo_to_iex_alu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2367 | +| W4 | `ooo_to_iex_bru` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W4 | `ooo_to_iex_agu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2367 | +| W4 | `ooo_to_iex_std` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `StoreDispatchTxn` | 512 | 4736 | +| W4 | `ooo_to_iex_system` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W4 | `ooo_to_iex_cmd` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W4 | `ooo_to_iex_rob_noflush` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `RobNoflushTxn` | 13 | 226 | +| W4 | `iex_to_ooo_rob_noflush_ready` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `RobNoflushReadyTxn` | 13 | 226 | +| W4 | `iex_to_ooo_rob_resolve` | [[IFC-OOO-IEX-001]] | IEX | OOO | 4 | `RobResolveTxn` | 29 | 528 | +| W4 | `iex_to_ooo_system_issue` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `SystemIssueTxn` | 15 | 302 | +| W4 | `ooo_to_top_system_issue` | [[IFC-OOO-IEX-001]] | OOO | TOP | 1 | `SystemIssueTxn` | 15 | 302 | +| W4 | `iex_to_ooo_pc_buffer_read_address` | [[IFC-OOO-IEX-001]] | IEX | OOO | 6 | `PcBufferReadAddress` | 4 | 24 | +| W4 | `ooo_to_iex_pc_buffer_read_pc_base` | [[IFC-OOO-IEX-001]] | OOO | IEX | 6 | `UInt` | 1 | 64 | +| W4 | `iex_to_lsu_load_issue` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `LoadIssueTxn` | 44 | 562 | +| W4 | `lsu_to_iex_load_allocation_preview` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadAllocationPreview` | 15 | 282 | +| W4 | `lsu_to_iex_load_launch` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadLaunchTxn` | 15 | 282 | +| W4 | `iex_to_lsu_store_reservation` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreReservationTxn` | 26 | 454 | +| W4 | `iex_to_lsu_store_address` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreAddressTxn` | 27 | 501 | +| W4 | `iex_to_lsu_store_data` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreDataTxn` | 30 | 581 | +| W4 | `lsu_to_iex_load_result` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadResultTxn` | 57 | 833 | +| W4 | `lsu_to_iex_load_reissue` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadReissueTxn` | 29 | 548 | +| W4 | `lsu_to_iex_load_repick` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadRepickTxn` | 28 | 484 | +| W4 | `lsu_to_iex_load_cancel` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadCancelTxn` | 13 | 202 | +| W4 | `ooo_to_lsu_store_commit` | [[IFC-IEX-LSU-001]] | OOO | LSU | 1 | `StoreCommitAuthorizationTxn` | 14 | 220 | +| W4 | `lsu_internal_store_classify` | [[IFC-IEX-LSU-001]] | LSU Translation | LSU Commit Backend | 1 | `StoreMemoryClassifyTxn` | 16 | 254 | +| W4 | `external_cmd_issue` | [[IFC-TOP-EXT-001]] | IEX | External CMD | 1 | `CmdIssueTxn` | 19 | 498 | +| W4 | `owner_to_ooo_recovery_event` | [[IFC-RECOVERY-001]] | IEX/LSU | OOO | 1 | `RecoveryEvent` | 32 | 618 | +| W4 | `ooo_recovery_prepare` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W4 | `target_to_ooo_recovery_prepared` | [[IFC-RECOVERY-001]] | IFU/CTU/IEX/LSU | OOO | 1 | `RecoveryPlan` | 41 | 459 | +| W4 | `ooo_recovery_apply` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W4 | `ooo_recovery_abort` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W4 | `ooo_commit` | [[IFC-COMMIT-001]] | OOO | TOP/DTU | 4 | `CommitTxn` | 361 | 5551 | +| W4 | `box_to_dtu_trace` | [[IFC-DTU-001]] | TOP/IFU/CTU/OOO/IEX/LSU | DTU | 4 | `TracePacket` | 81 | 1499 | +| W4 | `external_to_dtu_debug_request` | [[IFC-DTU-001]] | External Debug | DTU | 1 | `DebugRequest` | 5 | 196 | +| W4 | `dtu_to_ooo_debug_request` | [[IFC-DTU-001]] | DTU | OOO | 1 | `DebugRequest` | 5 | 196 | +| W4 | `ooo_to_dtu_debug_response` | [[IFC-DTU-001]] | OOO | DTU | 1 | `DebugResponse` | 4 | 130 | +| W4 | `dtu_to_external_debug_response` | [[IFC-DTU-001]] | DTU | External Debug | 1 | `DebugResponse` | 4 | 130 | +| W4 | `dtu_trace_export` | [[IFC-DTU-001]] | DTU | External Trace | 4 | `TracePacket` | 81 | 1499 | +| W4 | `dtu_performance_counter` | [[IFC-DTU-001]] | DTU | External Counter | 32 | `UInt` | 1 | 64 | +| W4 | `instruction_memory_request` | [[IFC-MEMORY-001]] | IFU | Memory | 1 | `MemoryRequestTxn` | 9 | 225 | +| W4 | `instruction_memory_response` | [[IFC-MEMORY-001]] | Memory | IFU | 1 | `MemoryResponseTxn` | 13 | 759 | +| W4 | `data_memory_request` | [[IFC-MEMORY-001]] | LSU | Memory | 4 | `MemoryRequestTxn` | 9 | 225 | +| W4 | `data_memory_response` | [[IFC-MEMORY-001]] | Memory | LSU | 4 | `MemoryResponseTxn` | 13 | 759 | +| W6 | `top_io` | [[IFC-TOP-EXT-002]] | Platform | TOP | 1 | `TOPIO` | 960 | 19938 | +| W6 | `ifu_to_ctu` | [[IFC-IFU-CTU-001]] | IFU | CTU | 6 | `FetchedPacket` | 127 | 3639 | +| W6 | `ctu_to_ooo` | [[IFC-CTU-OOO-001]] | CTU | OOO | 6 | `D1Packet` | 157 | 4197 | +| W6 | `ooo_to_iex_alu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2367 | +| W6 | `ooo_to_iex_bru` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W6 | `ooo_to_iex_agu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2367 | +| W6 | `ooo_to_iex_std` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `StoreDispatchTxn` | 512 | 4736 | +| W6 | `ooo_to_iex_system` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W6 | `ooo_to_iex_cmd` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2367 | +| W6 | `ooo_to_iex_rob_noflush` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `RobNoflushTxn` | 13 | 226 | +| W6 | `iex_to_ooo_rob_noflush_ready` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `RobNoflushReadyTxn` | 13 | 226 | +| W6 | `iex_to_ooo_rob_resolve` | [[IFC-OOO-IEX-001]] | IEX | OOO | 6 | `RobResolveTxn` | 29 | 528 | +| W6 | `iex_to_ooo_system_issue` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `SystemIssueTxn` | 15 | 302 | +| W6 | `ooo_to_top_system_issue` | [[IFC-OOO-IEX-001]] | OOO | TOP | 1 | `SystemIssueTxn` | 15 | 302 | +| W6 | `iex_to_ooo_pc_buffer_read_address` | [[IFC-OOO-IEX-001]] | IEX | OOO | 6 | `PcBufferReadAddress` | 4 | 24 | +| W6 | `ooo_to_iex_pc_buffer_read_pc_base` | [[IFC-OOO-IEX-001]] | OOO | IEX | 6 | `UInt` | 1 | 64 | +| W6 | `iex_to_lsu_load_issue` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `LoadIssueTxn` | 44 | 562 | +| W6 | `lsu_to_iex_load_allocation_preview` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadAllocationPreview` | 15 | 282 | +| W6 | `lsu_to_iex_load_launch` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadLaunchTxn` | 15 | 282 | +| W6 | `iex_to_lsu_store_reservation` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreReservationTxn` | 26 | 454 | +| W6 | `iex_to_lsu_store_address` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreAddressTxn` | 27 | 501 | +| W6 | `iex_to_lsu_store_data` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreDataTxn` | 30 | 581 | +| W6 | `lsu_to_iex_load_result` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadResultTxn` | 57 | 833 | +| W6 | `lsu_to_iex_load_reissue` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadReissueTxn` | 29 | 548 | +| W6 | `lsu_to_iex_load_repick` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadRepickTxn` | 28 | 484 | +| W6 | `lsu_to_iex_load_cancel` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadCancelTxn` | 13 | 202 | +| W6 | `ooo_to_lsu_store_commit` | [[IFC-IEX-LSU-001]] | OOO | LSU | 1 | `StoreCommitAuthorizationTxn` | 14 | 220 | +| W6 | `lsu_internal_store_classify` | [[IFC-IEX-LSU-001]] | LSU Translation | LSU Commit Backend | 1 | `StoreMemoryClassifyTxn` | 16 | 254 | +| W6 | `external_cmd_issue` | [[IFC-TOP-EXT-001]] | IEX | External CMD | 1 | `CmdIssueTxn` | 19 | 498 | +| W6 | `owner_to_ooo_recovery_event` | [[IFC-RECOVERY-001]] | IEX/LSU | OOO | 1 | `RecoveryEvent` | 32 | 618 | +| W6 | `ooo_recovery_prepare` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W6 | `target_to_ooo_recovery_prepared` | [[IFC-RECOVERY-001]] | IFU/CTU/IEX/LSU | OOO | 1 | `RecoveryPlan` | 41 | 459 | +| W6 | `ooo_recovery_apply` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W6 | `ooo_recovery_abort` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W6 | `ooo_commit` | [[IFC-COMMIT-001]] | OOO | TOP/DTU | 6 | `CommitTxn` | 541 | 8325 | +| W6 | `box_to_dtu_trace` | [[IFC-DTU-001]] | TOP/IFU/CTU/OOO/IEX/LSU | DTU | 6 | `TracePacket` | 121 | 2247 | +| W6 | `external_to_dtu_debug_request` | [[IFC-DTU-001]] | External Debug | DTU | 1 | `DebugRequest` | 5 | 196 | +| W6 | `dtu_to_ooo_debug_request` | [[IFC-DTU-001]] | DTU | OOO | 1 | `DebugRequest` | 5 | 196 | +| W6 | `ooo_to_dtu_debug_response` | [[IFC-DTU-001]] | OOO | DTU | 1 | `DebugResponse` | 4 | 130 | +| W6 | `dtu_to_external_debug_response` | [[IFC-DTU-001]] | DTU | External Debug | 1 | `DebugResponse` | 4 | 130 | +| W6 | `dtu_trace_export` | [[IFC-DTU-001]] | DTU | External Trace | 6 | `TracePacket` | 121 | 2247 | +| W6 | `dtu_performance_counter` | [[IFC-DTU-001]] | DTU | External Counter | 32 | `UInt` | 1 | 64 | +| W6 | `instruction_memory_request` | [[IFC-MEMORY-001]] | IFU | Memory | 1 | `MemoryRequestTxn` | 9 | 225 | +| W6 | `instruction_memory_response` | [[IFC-MEMORY-001]] | Memory | IFU | 1 | `MemoryResponseTxn` | 13 | 759 | +| W6 | `data_memory_request` | [[IFC-MEMORY-001]] | LSU | Memory | 4 | `MemoryRequestTxn` | 9 | 225 | +| W6 | `data_memory_response` | [[IFC-MEMORY-001]] | Memory | LSU | 4 | `MemoryResponseTxn` | 13 | 759 | +| W8 | `top_io` | [[IFC-TOP-EXT-002]] | Platform | TOP | 1 | `TOPIO` | 1180 | 23462 | +| W8 | `ifu_to_ctu` | [[IFC-IFU-CTU-001]] | IFU | CTU | 8 | `FetchedPacket` | 169 | 4852 | +| W8 | `ctu_to_ooo` | [[IFC-CTU-OOO-001]] | CTU | OOO | 8 | `D1Packet` | 209 | 5596 | +| W8 | `ooo_to_iex_alu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2376 | +| W8 | `ooo_to_iex_bru` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2376 | +| W8 | `ooo_to_iex_agu` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `DispatchTxn` | 255 | 2376 | +| W8 | `ooo_to_iex_std` | [[IFC-OOO-IEX-001]] | OOO | IEX | 2 | `StoreDispatchTxn` | 512 | 4754 | +| W8 | `ooo_to_iex_system` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2376 | +| W8 | `ooo_to_iex_cmd` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `DispatchTxn` | 255 | 2376 | +| W8 | `ooo_to_iex_rob_noflush` | [[IFC-OOO-IEX-001]] | OOO | IEX | 1 | `RobNoflushTxn` | 13 | 226 | +| W8 | `iex_to_ooo_rob_noflush_ready` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `RobNoflushReadyTxn` | 13 | 226 | +| W8 | `iex_to_ooo_rob_resolve` | [[IFC-OOO-IEX-001]] | IEX | OOO | 8 | `RobResolveTxn` | 29 | 528 | +| W8 | `iex_to_ooo_system_issue` | [[IFC-OOO-IEX-001]] | IEX | OOO | 1 | `SystemIssueTxn` | 15 | 302 | +| W8 | `ooo_to_top_system_issue` | [[IFC-OOO-IEX-001]] | OOO | TOP | 1 | `SystemIssueTxn` | 15 | 302 | +| W8 | `iex_to_ooo_pc_buffer_read_address` | [[IFC-OOO-IEX-001]] | IEX | OOO | 6 | `PcBufferReadAddress` | 4 | 24 | +| W8 | `ooo_to_iex_pc_buffer_read_pc_base` | [[IFC-OOO-IEX-001]] | OOO | IEX | 6 | `UInt` | 1 | 64 | +| W8 | `iex_to_lsu_load_issue` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `LoadIssueTxn` | 44 | 562 | +| W8 | `lsu_to_iex_load_allocation_preview` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadAllocationPreview` | 15 | 282 | +| W8 | `lsu_to_iex_load_launch` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadLaunchTxn` | 15 | 282 | +| W8 | `iex_to_lsu_store_reservation` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreReservationTxn` | 26 | 454 | +| W8 | `iex_to_lsu_store_address` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreAddressTxn` | 27 | 501 | +| W8 | `iex_to_lsu_store_data` | [[IFC-IEX-LSU-001]] | IEX | LSU | 2 | `StoreDataTxn` | 30 | 581 | +| W8 | `lsu_to_iex_load_result` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadResultTxn` | 57 | 833 | +| W8 | `lsu_to_iex_load_reissue` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadReissueTxn` | 29 | 548 | +| W8 | `lsu_to_iex_load_repick` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadRepickTxn` | 28 | 484 | +| W8 | `lsu_to_iex_load_cancel` | [[IFC-IEX-LSU-001]] | LSU | IEX | 2 | `LoadCancelTxn` | 13 | 202 | +| W8 | `ooo_to_lsu_store_commit` | [[IFC-IEX-LSU-001]] | OOO | LSU | 1 | `StoreCommitAuthorizationTxn` | 14 | 220 | +| W8 | `lsu_internal_store_classify` | [[IFC-IEX-LSU-001]] | LSU Translation | LSU Commit Backend | 1 | `StoreMemoryClassifyTxn` | 16 | 254 | +| W8 | `external_cmd_issue` | [[IFC-TOP-EXT-001]] | IEX | External CMD | 1 | `CmdIssueTxn` | 19 | 498 | +| W8 | `owner_to_ooo_recovery_event` | [[IFC-RECOVERY-001]] | IEX/LSU | OOO | 1 | `RecoveryEvent` | 32 | 618 | +| W8 | `ooo_recovery_prepare` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W8 | `target_to_ooo_recovery_prepared` | [[IFC-RECOVERY-001]] | IFU/CTU/IEX/LSU | OOO | 1 | `RecoveryPlan` | 41 | 459 | +| W8 | `ooo_recovery_apply` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W8 | `ooo_recovery_abort` | [[IFC-RECOVERY-001]] | OOO | IFU/CTU/IEX/LSU | 1 | `RecoveryPlan` | 41 | 459 | +| W8 | `ooo_commit` | [[IFC-COMMIT-001]] | OOO | TOP/DTU | 8 | `CommitTxn` | 721 | 11100 | +| W8 | `box_to_dtu_trace` | [[IFC-DTU-001]] | TOP/IFU/CTU/OOO/IEX/LSU | DTU | 8 | `TracePacket` | 161 | 2996 | +| W8 | `external_to_dtu_debug_request` | [[IFC-DTU-001]] | External Debug | DTU | 1 | `DebugRequest` | 5 | 196 | +| W8 | `dtu_to_ooo_debug_request` | [[IFC-DTU-001]] | DTU | OOO | 1 | `DebugRequest` | 5 | 196 | +| W8 | `ooo_to_dtu_debug_response` | [[IFC-DTU-001]] | OOO | DTU | 1 | `DebugResponse` | 4 | 130 | +| W8 | `dtu_to_external_debug_response` | [[IFC-DTU-001]] | DTU | External Debug | 1 | `DebugResponse` | 4 | 130 | +| W8 | `dtu_trace_export` | [[IFC-DTU-001]] | DTU | External Trace | 8 | `TracePacket` | 161 | 2996 | +| W8 | `dtu_performance_counter` | [[IFC-DTU-001]] | DTU | External Counter | 32 | `UInt` | 1 | 64 | +| W8 | `instruction_memory_request` | [[IFC-MEMORY-001]] | IFU | Memory | 1 | `MemoryRequestTxn` | 9 | 225 | +| W8 | `instruction_memory_response` | [[IFC-MEMORY-001]] | Memory | IFU | 1 | `MemoryResponseTxn` | 13 | 759 | +| W8 | `data_memory_request` | [[IFC-MEMORY-001]] | LSU | Memory | 4 | `MemoryRequestTxn` | 9 | 225 | +| W8 | `data_memory_response` | [[IFC-MEMORY-001]] | Memory | LSU | 4 | `MemoryResponseTxn` | 13 | 759 | diff --git a/docs/chisel/integrated-development-flow.md b/docs/chisel/integrated-development-flow.md index 91c8d5c9..268b962a 100644 --- a/docs/chisel/integrated-development-flow.md +++ b/docs/chisel/integrated-development-flow.md @@ -1,6 +1,6 @@ # LinxCore Integrated Development Flow -Date: 2026-07-13 +Date: 2026-07-31 ## Purpose @@ -13,6 +13,21 @@ QEMU proves architectural row streams, Chisel generated RTL proves DUT behavior, LinxCoreModel proves model convergence, and the superproject gates prove that the change still works across repos. +Directed Chisel behavior tests that do not need the full storage window use +the test-scope `SimulationParamProfiles` under +`chisel/src/test/scala/linxcore/params`. These profiles keep the selected +W2/W4/W6/W8 pipeline width and fixed identity fields but bound ROB, rename, IQ, +and LSU queue capacity. Main `ParamProfiles` remain mandatory for interface, +full-capacity, generated-RTL, lint, activation and workload evidence. + +Use `tools/chisel/run_chisel_tests.sh` for test execution. It supervises one +SBT process, emits periodic build heartbeats, accepts repeated `--only` +selectors, and defaults to one suite job. Pass `--jobs N` explicitly only when +the artifact and memory budget permits concurrent suites. Build-stall detection requires +simultaneous output inactivity, artifact inactivity and low descendant CPU; +architectural deadlock remains a simulated-cycle property checked by the +test-scope `SimulationProgress` helper. + For IFU packets, the normative target is two decoupled, non-lockstep pipelines: I-SIDE `I-F0..I-F4` and B-SIDE `B-F0..B-F4`. Model BFU F0–F4 provides the B-SIDE predictor behavior/timing reference. Model BHC, ITLB, and L1I behavior @@ -24,23 +39,61 @@ as final correction point, provider rank, and retained training; a reduced ## Current Handoff -The latest LSU packet is I0.15a production STQ-result ownership. I0.14's three -replicated `STQLoadForwardingPipeline` ports still snapshot canonical -`STQEntryBank` tags at E1 and read only generation-qualified `STQDataBank` -payload at E3. I0.15a separates byte selection from the common E3/E4 result -owner: `LoadForwardResultPipeline` consumes a typed selection, while -`STQLoadForwardResultPipeline` consumes the canonical retained STQ response -directly. `LoadSourceLineMerge` performs byte-exact partial L1D/SCB merge, and -the STQ query now carries baseline valid-mask plus split source-return evidence. -Selected data-not-ready stores enter ordinary E3/E4 replay classification; -unknown older addresses, stale generation, missing/ambiguous full LSID, and -cross-line/malformed queries take a separate retained hard-block boundary and -cannot masquerade as cache misses. The next LSU packet must bind exact -`OooIexLoadGeneration` values to canonical LIQ rows and make LIQ the sole -wait/miss/relaunch owner before connecting the three production ports. It must -also avoid duplicate retry or W1/W2 ownership between `OooIexLoadUnit` and -`ScalarLSULoadPath`. FSU/vector STD, cross-line split loads, -DTLB/PMP/PMA/device/coherence, timing, and workload promotion remain open. +The latest LSU packet is I0.15c-b3c3c retained structural-load ownership. +One private `LoadStructuralBlockPolicy` now consumes the live forwarding +fabric's raw hard-block channel. Exact unknown-older dependencies advance the +load-attempt generation and atomically rebind OOO metadata plus LIQ state to an +exact store wait; stale snapshots retry without a store key. Ambiguous full +LSID authority, invalid shapes, and cross-line overlap remain retained, +fail-closed `Unsupported` state. The production boundary exposes diagnostics, +not another raw consumer port. Exact dual-view recovery may kill the compact +policy record, but complete recovery still rejects while MDB or another +non-LIQ transient owner is live. + +Task 13 removes the combined execution/store shell and makes the canonical IEX +pipeline derive its topology directly from `CoreParams`. The scalar-load +metadata, LIQ/L1D/MDB/LRET, canonical STQ, and committed-store backend remain +separate mechanisms. Task 15 must connect them through the public IEX/LSU +interfaces with one metadata owner, one LIQ, one STQ, and one terminal result +owner. Recovery must join execution, load metadata, STQ/store, and scalar-load +owners before one common Apply event. Raw launch intent remains independent +from credit-qualified launch acceptance so replay rebind cannot create a +terminal-backpressure ready loop. + +The preceding I0.15c-b3c2 packet provides live three-pipe forwarding. +Every canonical LIQ launch atomically enters exactly one retained STQ query +queue; each queue obeys Decoupled retention under external backpressure. Hard +flush clears the transport, while typed precise recovery fences boundary fire +and preserves surviving query/result ownership and reservations. +Three retained STQ response lanes arbitrate into credit-controlled E3/E4, a +separate retained structural-hard-block boundary, and the b3c1 exact-result +retainer. Production elaboration contains no compatibility forwarding CAM. + +The preceding I0.15c-b2b execution-cluster cutover has +`OooIexCanonicalLoadOwnership` atomically join the three-AGU LIQ allocation +with the exact slot-plus-wrap terminal metadata sidecar; neither owner can +accept alone. Exact replay rebind is likewise one common LIQ/OOO transaction, +and canonical LRET/W1/W2 completion releases metadata only on the same terminal +fire. Recovery prepare now fences without consuming AGU producers, while only +the common recovery fire applies the exact kill. The emitted graph contains no +legacy load tracker. I0.15c-b2a qualifies speculative wakeup only from the +exact canonical LIQ launch attempt, emits old-generation cancel on exact +rebind, one-shot fault cancel independent of terminal backpressure, and +lane-qualified W1 bypass on ordinary data. Same-lane fault/rebind cancel +collision serializes without loss. The production execution cluster now owns +one canonical bridge for all three AGUs, exports its allocation/rebind/launch/ +completion ports through the closed OOO/IEX/store wrappers, joins its recovery +readiness into the common execution fire, and contains no duplicate load +request/retry/result owner. The obsolete `OooIexLoadUnit`, its capacity +parameter, UT, abstract memory messages, and module page are deleted. Dynamic +cluster IT proves E1 -> AGU -> canonical allocation -> launch wakeup -> atomic +P-file/ROB terminal publication. +The next I0.15c packet must replace the migration BID projection with common +BID/BROB ordering authority and extend recovery projection equality to MDB, +MissQ, ResolveQ, LRET, refill, and forwarding transport. Cross-line forwarding +and execution also remains intentionally unsupported. Physical SCB return, +FSU/vector STD, cross-line split loads, DTLB/PMP/PMA/device/coherence, timing, +and workload promotion remain open. The active backend handoff is OOO packet O8.3 physical closure. O4 P/T/U RENU, O5 dispatch/IEX residency, O6 fast resolve/non-flush, and O7 @@ -87,9 +140,9 @@ into one precise trap. `OooD1FusionHistory` retains one eligible tail per STID, supports same/cross-cycle forward-BSTART and backward-BSTOP fusion with up to three ordered parent references, and cancels only the recovered STID. -O2 is packet-complete. `OooIfuRawIngress` keeps the IFU four-wide while +O2 is packet-complete. `OOOD1D2Stage` keeps the IFU four-wide while reservoirs exact raw rows per STID and emits independent 2/4/6-wide prefixes; -`OooIfuD1Ingress` composes that adapter with canonical decode/fusion. CTU and +`OOOD1D2Stage` composes that adapter with canonical decode/fusion. CTU and complex parents retain their full raw identity/prediction sideband, rather than only a diversion mask. The current catalog deliberately has zero dispatch-owned complex forms, with CTU forms diverted and unresolved @@ -97,7 +150,7 @@ macro/atomic forms failing closed. O3 now implements D2 virtual grouping, retained D3 provisional allocation, atomic S1 grouped ROB publication and exact member completion, native BID/generation BROB ownership, a fixed-partition 64-entry PC-base buffer with byte-granular offsets, exact close ownership, and -wrap-qualified read/commit tokens. `OooRobBrobPcCoordinator` completes O3 by +wrap-qualified read/commit tokens. `OOOD3S1Graph` completes O3 by binding the immutable D3/BROB/PC view and driving one common publication and commit fire across every owner. O4 adds independent absolute P rename and relative T/U rename preparation without weakening that common-fire contract. @@ -141,13 +194,12 @@ dispatch cancels target provisional and exact killed published reservations, IEX prunes S1/S3 and frees killed S2/S3 rows with generation-qualified ready cleanup, and fast resolve cancels exact killed pending entries while unrelated STIDs continue. O7.2d1 retains one lower request inside -`OooRobBrobPcCoordinator`, waits out exposed D3 and retained-commit +`OOOD3S1Graph`, waits out exposed D3 and retained-commit obligations, captures the sole ROB plan after lower-owner validation, and -applies ROB/D3/BROB/PC together. O7.2d2 now lifts that transaction into -`OooO3RenameCoordinator`: one retained request captures the lower owner and -T/U suffix scanner, projects the sole ROB plan to dispatch, fast resolve, and -the external IEX owner, then fires lower recovery, all residency owners, and -P/T/U authorization on one apply. R4 completion waits for the complete +applies ROB/D3/BROB/PC together. The canonical replacement is public `OOO` +through `OOOD3S1Graph`: `RecoveryControl` retains the selected ROB plan, +prepares RENU, BROB, Dispatch, and the typed external recovery targets, then +fires one common apply. R4 completion waits for the complete youngest-to-oldest rename-source stream, killed-PTag returns, P survivor replay, and T/U cursor rebuild. Every PTag return, including commit and recovery, now invalidates the matching IEX ready generation on the same handshake before @@ -1556,7 +1608,7 @@ Promotion gate: R557 replay-loop fixture, R558 `replay-ldi-sdi-ldi-ldi-ldi-ldi-loop`, R561/R562/R563/R564/R565 phase-distance, identity, and different-LSID near-miss sideband, or a stronger multiple-return-load phasing fixture through - run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh with v24 sideband + historical v24 fetch/RF/ALU QEMU wrapper evidence (the wrapper is deleted) inspection requiring nonzero source-return, LRET-payload, publish-control, and LRET-sink enqueue overlap while W2 is occupied, then nonzero LRET sink pending/drain and IEX insert/residency/W1 @@ -1653,7 +1705,7 @@ Closeout evidence: unit log, generated-RTL/QEMU manifest, sideband counters, | 0. Wrapper and static sanity | Any Chisel, adapter, or fixture edit | `bash tools/chisel/build_chisel.sh`; touched Python adapter self-tests; relevant `--dry-run` wrapper | Build and wrapper selection work without entering a broad compare | | 1. Module contract | One module or bundle owner changed | `bash tools/chisel/run_chisel_tests.sh --only `; `bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only` for ROBID/ROB semantics | The assigned module contract is green | | 2. Adjacent generated RTL | Composition, top, monitor, or trace-owner changed | `bash tools/chisel/run_chisel_verilator_lint.sh`; nearest `run_chisel_*_xcheck.sh` wrapper | Generated RTL elaborates and the nearest harness compare is green | -| 3. QEMU row replay | The packet claims architectural row equivalence | `bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh ...`; `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh ...` | `crosscheck_manifest.json` shows zero mismatches and records raw/arch row counts | +| 3. Canonical frontend trace comparison | The packet claims architectural row equivalence | `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` | `crosscheck_manifest.json` shows zero mismatches and records raw/arch row counts | | 4. Model/toolchain convergence | Workload behavior or model parity is part of the claim | From superproject: `python3 tools/bringup/run_ai_workload_flow.py --profile smoke ...`; `python3 tools/bringup/run_benchmark_linux_flow.py --profile pr ...`; `model/LinxCoreModel/bin/gfsim -f ` only after the same ELF passed QEMU | QEMU-passing ELF also passes the selected model or workload profile | | 5. Closure | PR, submodule pin, or cross-lane behavior changed | `tests/test_stage_connectivity.sh`; `tests/test_runner_protocol.sh`; `tests/test_cosim_smoke.sh`; `tests/test_opcode_parity.sh`; `tests/test_trace_schema_and_mem.sh`; `tests/test_rob_bookkeeping.sh`; `tests/test_block_struct_pyc_flow.sh`; superproject strict closure | All required cross-repo gates for the claim pass | diff --git a/docs/chisel/interfaces/OooBundles.md b/docs/chisel/interfaces/OooBundles.md index 207d4064..441b1e8a 100644 --- a/docs/chisel/interfaces/OooBundles.md +++ b/docs/chisel/interfaces/OooBundles.md @@ -13,17 +13,17 @@ - Canonical typed fast-resolve owner: `chisel/src/main/scala/linxcore/ooo/OooFastResolve.scala` - Frontend recovery R4 bridge: - `chisel/src/main/scala/linxcore/ooo/OooFrontendRecoveryBridge.scala` + `chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala` - Tests: `chisel/src/test/scala/linxcore/ooo/OooParamsSpec.scala` - Tests: `chisel/src/test/scala/linxcore/ooo/OooBundlesSpec.scala` - Tests: `chisel/src/test/scala/linxcore/ooo/OooThreadStageBufferSpec.scala` - Tests: `chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala` - Integration tests: - `chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala` + `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` - Fast-resolve tests: `chisel/src/test/scala/linxcore/ooo/OooFastResolveSpec.scala` - Fast-resolve integration tests: - `chisel/src/test/scala/linxcore/ooo/OooO3FastResolveIntegrationSpec.scala` + `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` - Contract IDs: `LC-IF-CHISEL-OOO-001`, `LC-MA-PIPE-001`, `LC-MA-ROB-001` @@ -121,7 +121,7 @@ fallback while retrying the input unchanged. ## IFU raw ingress and CTU diversion -`OooIfuRawIngress` is the canonical width adapter. It consumes the existing +`OOOD1D2Stage` is the canonical width adapter. It consumes the existing fixed-four-wide `D1InstructionGroup`, keeps a power-of-two raw reservoir per STID, and emits the selected STID as a dense 2/4/6-wide `OooRawInstructionGroup`. It copies PE/STID/instruction/transaction/fetch, @@ -132,14 +132,14 @@ The reservoir supports same-bank enqueue/dequeue, partial prefixes, six-wide gather, stable backpressure, targeted exact pruning, and four-STID isolation. A canonical flush is a one-cycle publication barrier: only the addressed bank is mutated, and every unaffected bank resumes with the same head on the next -cycle. `OooIfuD1Ingress` composes this reservoir with +cycle. `OOOD1D2Stage` composes this reservoir with `OooD1FusionDecode`; its thread hint scans IFU banks while OOO independently selects the STID presented to D1. `OooD1DecodedPacket` carries `ctuParents` and `complexParents` alongside their masks. Every diverted lane therefore retains the exact raw parent and complete prediction record needed by the external CTU/complex owner. Masks are never an -authority to reconstruct identity. `OooCtuIngressBridge` retains one decoded +authority to reconstruct identity. `CTU` retains one decoded packet and at most one active lease per STID, emits any older ordinary prefix, then transfers the exact diverted parent through `OooCtuParentClaim`. @@ -226,7 +226,7 @@ has already completed. BROB, PC, rename, and IEX owners may prepare their resources independently, but no binding is architecturally visible before the single S1 publication handshake. -`OooS1GroupedRob` revalidates the dense group mask, plan/decoded PE/STID/epoch, +`ROB` revalidates the dense group mask, plan/decoded PE/STID/epoch, first RID, every consecutive slot/generation, member/parent bounds, binding valid-vector shape, initial completion mask, and vacancy of every target row. It writes all groups or none. A rejected or blocked request does not create a @@ -244,12 +244,12 @@ batch bounded by independent `retireGroupWidth`. The batch remains stable under backpressure. Only `commit.fire` clears rows, advances the physical head and epoch, and supplies the exact `OooRobGroupRelease` token that the D3 allocator will accept. BROB/PC commit authorization is not bypassed: -`OooRobBrobPcCoordinator` holds external `commit.valid` until every owner has +`OOOD3S1Graph` holds external `commit.valid` until every owner has validated the retained batch, then lets all four owners fire atomically. ## Canonical BROB -`OooBrob` is the sole native block-order owner for canonical OOO. +`BROB` is the sole native block-order owner for canonical OOO. Each STID has an independent 256-entry default ring. The architectural BID is only the ring slot; `BrobPointer.generation` is separate wrap state and neither allocation nor commit uses unsigned BID magnitude as age. @@ -336,7 +336,7 @@ multirow metadata-write realization; those remain explicit macro work. ## O3 ROB/BROB/PC coordinator -`OooRobBrobPcCoordinator` is the terminal O3 owner composition. It retains D3 +`OOOD3S1Graph` is the terminal O3 owner composition. It retains D3 reservations, asks BROB and PC for side-effect-free bindings, adds the next per-ROB-slot resident generation, and presents the fully bound grouped-ROB publication to later RENU/dispatch owners. `preparedValid` is an immutable @@ -396,7 +396,7 @@ and validates count, range, uniqueness, bank, generation, and current live ownership before changing any bit. A cycle-by-cycle checker proves the entire 128-tag namespace remains in exactly one lifecycle location. -`OooPRename` is the O4.2 P-map owner. It consumes the immutable O3 +`PRename` is the O4.2 P-map owner. It consumes the immutable O3 prepared publication together with the matching retained PTag lease. For every active P source it reads the selected STID's 24-entry SMAP and then applies all older destinations in the same transaction from oldest to youngest. A WAW @@ -408,9 +408,9 @@ false until O5 supplies the exact IQ reservation. Prepare is side-effect free. `OooPMapQEntry` records exact ROB member identity, transaction/uop/destination order, old mapping, and new mapping. The per-STID MapQ is an ordered ring, not a search-allocated collection. SMAP and MapQ mutate -only on the common O3 publication fire. `OooO3RenameCoordinator` joins D3 and -PTag claim on one reserve handshake, then joins ROB/BROB/PC publication, PTag -publication, SMAP update, and MapQ insertion on one terminal fire. +only on the common D3 publication fire. `OOOD3S1Graph` joins RENU preparation +with side-effect-free ROB/BROB preparation and Dispatch acceptance; one D3 fire +publishes ROB/BROB residency and the P/T/U rename state together. The ordered ring has a parameterized physical subbank layout. For logical index `q`, low `log2(pMapQSubbankCount)` bits select the subbank and the @@ -424,7 +424,7 @@ for a later two-cycle pointer-update loop; it does not itself add a cycle or relax commit/recovery exclusion. O4.3 adds the P architectural commit walk. Every physical ROB group carries its -exact `pMapQRows` obligation. `OooPRename` validates the retained ROB +exact `pMapQRows` obligation. `PRename` validates the retained ROB batch against the dense MapQ-head prefix using RID/native-BID/BROB/resident generations, transaction ID, member index, uop membership, queue index, and old/new mapping chain. It then drains at most `pTagReturnWidth` rows per cycle. @@ -448,7 +448,7 @@ P architectural commit is no longer a sealed seam. ## T/U sequential rename boundary -`OooTURename` is the O4.4 local-register owner. T and U have separate +`TURename` is the O4.4 local-register owner. T and U have separate per-STID sequence tails, physical-tag cursors, capacity counters, MapQ rings, and provisional leases. A relative source resolves `tail - (relativeIndex+1)` in its own namespace. The D3 preview walks expanded uops oldest-to-youngest, so @@ -470,10 +470,10 @@ independent T/U input. `OooTURenamePreparedTransaction` returns the pre-destination T/U sequence snapshots, resolved local sources, destination mappings, and exact MapQ rows used by later dispatch/recovery owners. -`OooO3RenameCoordinator` gates D3 admission on both PTag and T/U preparation, -cancels both leases by STID, and requires both P and T/U publication views -before asserting the shared permit. One terminal fire therefore publishes all -ROB/BROB/PC/P/T/U owners. +`RENU` gates D3 admission on both P and T/U preparation, cancels both leases by +STID, and requires both publication views before presenting the retained D3 +group. `OOOD3S1Graph` accepts that group only when ROB, BROB, and Dispatch can +share the same publication fire. O4.4.2 adds `OooTURetire` as the separate retire-source and relation- CMAP owner. `OooTURetirePublication` retains one exact source per logical uop, @@ -483,7 +483,7 @@ retained `OooRobCommitBatch` is accepted only when each group and each logical- uop bit matches exactly at the per-STID source head. The owner emits serialized `OooTURetireCommand` operations in T-before-U -pre-release, mark, and pressure-release order. `OooTURename` validates +pre-release, mark, and pressure-release order. `TURename` validates the full local sequence generation, exact ROB member, namespace, and physical deallocation head before mutating its MapQ. After exact-block relation cleanup, `OooTULocalBlockCommit` releases only the retired MapQ head prefix whose native @@ -513,7 +513,7 @@ input is exposed only by the atomic coordinator described below; no individual owner is a legal canonical recovery entry point. O4.4.3b adds the P recovery owner behind that authorization. For every killed -logical source, `OooPRename` proves that `pDestinationCount` exact +logical source, `PRename` proves that `pDestinationCount` exact rows occupy the P MapQ tail and belong to the source's full member, transaction, uop, STID, and epoch identity. It then returns each killed row's `current` PTag through the existing generation-qualified return channel before @@ -530,7 +530,7 @@ direct P-owner UT proves killed current-tag order, survivor replay, unchanged CMAP, unrelated-STID rename, and that the surviving MapQ prefix remains committable. O4.4.3c still owns T/U MapQ and sequence-cursor rollback. -O4.4.3c makes `OooTURename` consume the same authorized source +O4.4.3c makes `TURename` consume the same authorized source stream. A killed logical uop is accepted only when its `tSeqBefore` and `uSeqBefore`, destination sequences, wrap generations, physical tags, full ROB member, transaction, STID, and epoch describe the exact current T/U MapQ @@ -544,8 +544,8 @@ blocks same-STID reserve, publication, retire commands, and block commit until common finish. Unrelated STIDs continue. Direct UT covers mixed T/U rollback, sequence-generation wrap, physical-tag reuse, transaction-zero and zero-destination suffix rows, malformed authorization, and retire priority. -O4.4.3d exposes `OooO3RenameCoordinator.recoveryRequest` as the sole canonical -rename-recovery entry point. A request cannot enter while the target STID owns +The live rename-recovery entry point is RENU's typed `RecoveryTargetIO`, driven +by `RecoveryControl` inside `OOOD3S1Graph`. A request cannot enter while the target STID owns an already-retained D3 prepared row. From request capture through common finish, the retire-source scanner fences new reserve and publication only for that STID; other STIDs retain D3/S1 progress. @@ -598,14 +598,12 @@ epoch selected for generated child zero. Uops without a dispatch producer keep that binding invalid. Class is part of the identity because bank/entry numbers are class-local. -`OooO3RenameCoordinator` now joins dispatch prepare, reserve, and publication -with D3, ROB, BROB, PC, and P/T/U rename. No owner publishes unless every owner -accepts the same transaction. Its terminal output is an exact Decoupled -`OooIexS1Transaction`; the IEX S1 transfer and every O3/O4/O5.1 publication -owner share one fire. There is no Boolean permission seam that can publish the -owners without transferring the matching payload. Rename-local recovery -deliberately refuses a STID that still owns published dispatch rows; O7 must add one global -ROB/BROB/PC/IQ cancellation transaction before that fence can be removed. +`OOOD3S1Graph` joins Dispatch acceptance with D3, ROB, BROB, and P/T/U rename. +No owner publishes unless every owner accepts the same group. Its typed +`OOOIEXIO` outputs are retained Decoupled transactions; there is no Boolean +permission seam that can publish an owner without transferring the matching +payload. Recovery uses the same graph's prepare/apply protocol to remove only +the authorized target-STID suffix. The complete per-class/per-bank bitmap remains the lifecycle-conservation and diagnostic state view, but O8.2 no longer feeds it to a bank-wide first-free @@ -735,7 +733,7 @@ authorization. ## O6.2 exact non-flush window -`OooS1GroupedRob` is the only canonical OOO non-flush owner. Every published +`ROB` is the only canonical OOO non-flush owner. Every published group stores independent required and observed proof masks: - `ExceptionSafe` for a potentially trapping group after its defined @@ -766,7 +764,7 @@ legacy `bctrl.BrobNonFlushFrontier` is not this canonical authority. ## O7.1 exact grouped-ROB suffix recovery owner -`OooS1GroupedRob` exposes a direct owner-local prepare/apply interface for the +`ROB` exposes a direct owner-local prepare/apply interface for the future global recovery coordinator. `OooGlobalRecoveryRequest` wraps the existing exact rename key with `triggerMemberCount`; the trigger member must be the first physical child of exactly one retained logical uop. The ROB scans the @@ -791,7 +789,7 @@ A previously retained same-STID commit drains before prepare can become ready. The direct `recoveryFire` clears the exact suffix, optionally rewrites the partial pivot, updates occupancy, and resets the affected non-flush window. It is never exposed as an independent composed fire. O7.2d1 lets -`OooRobBrobPcCoordinator` drive it only as part of one retained common +`OOOD3S1Graph` drive it only as part of one retained common ROB/D3/BROB/PC apply. The public O3 seam remains closed until P/T/U rename, dispatch, IEX, fast resolve, frontend stages, and CTU join the same global transaction. @@ -817,7 +815,7 @@ same retained lower-owner transaction together with BROB and PC; O7.2d2 lets the enclosing O3 rename coordinator authorize that lower apply only after its core-physical upper owners prepare. -O7.2b1 adds `OooBrob` as the next independent owner. Prepare proves +O7.2b1 adds `BROB` as the next independent owner. Prepare proves that every killed row names an exact live native-BID/BROB-generation entry, that every killed block allocation is a contiguous suffix ending at the live BROB tail, and that per-block killed counts do not exceed live ROB-group counts. @@ -862,12 +860,12 @@ removes exact killed `BoundS2`/`ResidentS3` rows, and clears their matching P/T/U ready records. Fast resolve removes exact killed retained entries and excludes only the recovering STID from terminal arbitration. Each owner exposes a typed prepared count and a typed fail-closed reject. -`OooO3RenameCoordinator` consumes these direct ports in O7.2d2; frontend and -CTU owners still remain outside this core-physical recovery boundary. +`RecoveryControl` consumes these direct ports through `OOOD3S1Graph`; frontend +and CTU remain typed external recovery targets of public `OOO`. ## O7.2d1 retained ROB/D3/BROB/PC recovery subtransaction -`OooRobBrobPcCoordinator` retains one `OooGlobalRecoveryRequest` through +`OOOD3S1Graph` retains one `OooGlobalRecoveryRequest` through `Idle`, `Preparing`, and `Prepared`. R0 capture is backpressured when the target STID already exposes a D3 `Decoupled` publication or owns a retained ROB commit; those obligations must drain because an exposed valid cannot be retracted. @@ -889,12 +887,10 @@ history, frontend restart, and CTU remain later enclosing owners. ## O7.2d2 retained O3 core-physical recovery transaction -`OooO3RenameCoordinator.recoveryRequest` accepts the complete -`OooGlobalRecoveryRequest`. The coordinator retains that packet through -`CaptureOwners`, `PrepareOwners`, `Rebuild`, or `AbortOwners`; the selected -STID is fenced while unrelated STIDs retain reserve/publication progress. -The lower coordinator and T/U suffix scanner may handshake independently, but -no owner mutates during capture or prepare. +Public `OOO` accepts execution recovery events through `OOOIEXIO`, and +`RecoveryControl` obtains the sole exact plan from ROB before preparing every +internal and external target. The selected STID is fenced while unrelated +STIDs retain reserve/publication progress. No owner mutates during prepare. Once both retained authorities are ready, the sole ROB plan is projected to one `OooResidencyRecoveryPlan` for dispatch, fast resolve, and the external IEX @@ -921,13 +917,13 @@ legacy external PTag-return input. ## O7.2e frontend fence and canonical restart join -`OooFrontendRecoveryBridge` is the sole join between an applied O3 recovery +`RecoveryControl` is the sole join between an applied O3 recovery and the canonical IFU restart. Its input combines `OooGlobalRecoveryRequest` with one `IfuInnerFlush`. The bridge rejects a missing group/native BID, cross-PE/STID/epoch proposal, zero physical trigger extent, mismatched prune scope, or recovery-cause/reason mismatch before requesting O3. -Capture fences the target STID without mutation. `OooIfuRawIngress`, +Capture fences the target STID without mutation. `OOOD1D2Stage`, `OooD2ThreadStageBuffer`, and the O1 D2/D3/S1 stage buffer exclude a fenced row from selection and intake while preserving its payload and occupancy. A blocked old grant immediately falls forward to another eligible STID. The @@ -935,7 +931,7 @@ fence begins on the command-offer cycle and remains through R4. The exact typed O3 apply emits one target-only `stageCancel` and enables the retained IFU redirect. IFU enqueue readiness is not an acknowledgement. -Completion requires both `OooO3RenameCoordinator.recoveryCompleted` and a +Completion requires the public OOO recovery-target apply and a `LinxCoreIfu.canonicalFlush` whose entire proposal matches except for `newEpoch`, which only IFU may allocate. Either terminal event may arrive first. An exact pre-apply O3 abort emits no cancel or redirect and releases the @@ -949,7 +945,7 @@ different queued feedback event remains retained. ## O7.3 CTU prepare and common apply The frontend bridge admits the retained global request to O3 only after -`OooCtuIngressBridge` has accepted and echoed the same request through +`CTU` has accepted and echoed the same request through `OooCtuRecoveryPrepared`. The CTU snapshot records target packet and lease occupancy but does not clear either. A CTU reject returns the composite command before O3 can mutate; an O3 abort drives CTU abort. Exact O3 apply drives @@ -977,32 +973,23 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreOooShell bash tools/chisel/run_chisel_tests.sh --only OooOpcodeRecipeTable bash tools/chisel/run_chisel_tests.sh --only OooD1Decode bash tools/chisel/run_chisel_tests.sh --only OooD1FusionHistory -bash tools/chisel/run_chisel_tests.sh --only OooIfuRawIngress -bash tools/chisel/run_chisel_tests.sh --only OooIfuD1Ingress -bash tools/chisel/run_chisel_tests.sh --only OooCtuIngressBridge +bash tools/chisel/run_chisel_tests.sh --only OOODecodeSpec +bash tools/chisel/run_chisel_tests.sh --only CTUSpec bash tools/chisel/run_chisel_tests.sh --only OooD2GroupPlanner bash tools/chisel/run_chisel_tests.sh --only OooD2Stage -bash tools/chisel/run_chisel_tests.sh --only OooD3ReservationAllocator -bash tools/chisel/run_chisel_tests.sh --only OooS1GroupedRob -bash tools/chisel/run_chisel_tests.sh --only OooD3S1GroupedRobIntegration -bash tools/chisel/run_chisel_tests.sh --only OooBrob -bash tools/chisel/run_chisel_tests.sh --only OooD3S1BrobIntegration +bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec +bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec bash tools/chisel/run_chisel_tests.sh --only OooPcBuffer -bash tools/chisel/run_chisel_tests.sh --only OooRobBrobPcCoordinator -bash tools/chisel/run_chisel_tests.sh --only OooFrontendRecoveryBridge -bash tools/chisel/run_chisel_tests.sh --only OooFrontendIfuRecoveryIntegration -bash tools/chisel/run_chisel_tests.sh --only OooFrontendCtuRecoveryIntegration +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +bash tools/chisel/run_chisel_tests.sh --only CTUOOOIntegrationSpec bash tools/chisel/run_chisel_tests.sh --only OooPTagStagingPool -bash tools/chisel/run_chisel_tests.sh --only OooPRename -bash tools/chisel/run_chisel_tests.sh --only OooTURename +bash tools/chisel/run_chisel_tests.sh --only RENUSpec +bash tools/chisel/run_chisel_tests.sh --only TURenameSequenceSpec bash tools/chisel/run_chisel_tests.sh --only OooTURetire -bash tools/chisel/run_chisel_tests.sh --only OooDispatch +bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec bash tools/chisel/run_chisel_tests.sh --only OooIexIssue -bash tools/chisel/run_chisel_tests.sh --only OooO3IexIntegration bash tools/chisel/run_chisel_tests.sh --only OooFastResolve -bash tools/chisel/run_chisel_tests.sh --only OooO3FastResolveIntegration -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameRandomized ``` The tests cover 2/4/6 decode widths, 1/2/4 STIDs, exact field widths, three diff --git a/docs/chisel/issues.md b/docs/chisel/issues.md index 7254e99e..5d1195dc 100644 --- a/docs/chisel/issues.md +++ b/docs/chisel/issues.md @@ -407,7 +407,7 @@ Impact: Evidence: - Command: - `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r198-helper-split-marker-row-1024-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 24 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` + historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r198-helper-split-marker-row-1024-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 24 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 801cbabb2475059b784de7587207e3332fee7a24. - The run captured 1024 raw QEMU rows, extracted 953 expected rows, emitted the Chisel top in roughly 16 seconds, and built the Verilated model before failing in the comparator. @@ -439,7 +439,7 @@ Resolution: `restoreBid = flush.bid - 1`, so a block-stop redirect must ask to restore the just-finished block checkpoint rather than the checkpoint before it. - The passing R202 command: - `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r202-marker-stop-restore-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 24 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` + historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r202-marker-stop-restore-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 24 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 54e94094445468467128b9e00f638185420cec88. - Result: 1024 raw QEMU rows captured, 953 expected rows extracted, 288 marker commits admitted/filtered, 665 normalized QEMU/DUT rows compared, and zero mismatches. diff --git a/docs/chisel/linxcore-chisel-iex-improvement-design.md b/docs/chisel/linxcore-chisel-iex-improvement-design.md index 5c93586d..1642cbea 100644 --- a/docs/chisel/linxcore-chisel-iex-improvement-design.md +++ b/docs/chisel/linxcore-chisel-iex-improvement-design.md @@ -146,7 +146,7 @@ IEX 只消费一次解析后的 `RecoveryResolvedTxn`： | `ExecuteTxn` | `ExactCompletionKey`、`IssueRowId`、FU class、operand provenance、destination ownership、recovery generation | | `IssueRelease` | `IssueRowId`、execute owner ID、execute slot、execute slot generation、`ExactCompletionKey` | | `WritebackTxn` | exact key、destination class/tag/data、producer ID、exception metadata | -| `CompletionTxn` | exact key、supported/trap/result metadata、required-side-effect mask | +| `RobResolveTxn` | exact key、supported/trap/result metadata、required-side-effect mask | | `FuKill` | exact key或 resolved killed bit、owner slot generation | 所有跨 owner 请求采用 `Decoupled` 或等价 retained protocol。任何 producer @@ -595,26 +595,26 @@ source projection，不能继续让两者复制 parent 的全部 source payload 与部分 high-long load 仍被 generated catalog 分到 ALU/IEX，也必须先修 recipe ownership，不能在 AGU 中暗中接管。 -### 6.9 I0.9d 已实现：load generation、tracking、cancel 与 retry +### 6.9 I0.15c-b2b 已实现：canonical load generation、cancel 与 return -`OooIexLoadUnit` 在接受 typed AGU request 时分配 tracking entry 和完整 -`{producer RobMemberKey, loadGeneration}`。默认 16 entries，由参数 -`iexLoadTrackEntries` 控制。pending request 经过 fair arbiter 发往 memory；每次 -attempt 真正 fire 时才发送 `SpeculativeLoad` wakeup。consumer 可以在 IQ 中 -specReady，但 I1 必须等同 gene 的 bypass data，不能退回读取旧 RF 数据。 +早期 I0.9d 的独立 OOO load tracker 已被生产路径取代并删除。当前唯一 load +lifecycle owner 是 canonical scalar LSU 的 LIQ/LRET/W1/W2；OOO 仅保留完成 +terminal publication 所需的 immutable metadata sidecar。三个 AGU 经 fair、 +non-resident adapter 原子申请 `{loadId, LoadAttemptIdentity}`，地址、miss、 +forwarding、replay 和 data 不在 OOO 复制。 -response 必须匹配处于 awaiting 状态的完整 token。hit 对 byte/half/word 做 -D1 指定的 sign/zero extension，并保持 W1 bypass 与 terminal load result； -miss 对旧 gene 发 exact cancel，同一个 tracking owner 分配新 gene 后 retry； -fault 同样撤回 speculation，但保留 precise fault terminal。IQ/P1/I1/I2 已有的 -cancel contract 会清 consumer 的 `specReady/inFlight`，随后新 gene wakeup + -bypass 使其 repick。stale、duplicate、unknown 和 recovery 后迟到 response 均 -typed reject，不能命中其他 entry。 +只有 canonical LIQ 的精确 `{loadId,attempt}` launch 才发 +`SpeculativeLoad` wakeup；rebind 对旧 generation 发 cancel，fault cancel 是与 +terminal ready 解耦的一次性 policy event。普通返回提供 lane-qualified W1 +bypass，并在同一个 terminal fire 原子完成 P-file write、committed wakeup、 +ROB completion/fault 和 trace。stale completion、错误 row lease、producer、 +attempt 或 destination 均 fail-closed。 -load terminal 仍不直接写 P/T/U RF、不发 committed wakeup、不完成 ROB。后续 -atomic sink 必须在同一个 result accept 上完成 data write、committed readiness、 -ROB completion/fault 和 trace。physical cache/TLB、alignment/order、store -queue/forwarding 以及多 response/bypass port 仍未实现。 +execution cluster 已接入这个唯一 owner 并删除旧 tracker 及其容量参数。尚未 +完成的是把 cluster 暴露的 canonical port 与真实 `ScalarLSULoadPath`、三条 STQ +forward-result pipe、asynchronous cache/refill return 和整个 LSU recovery owner +组成一个 production top；physical cache/TLB、alignment、device/coherence 和 +cross-line load 仍属于后续包。 ### 6.10 I0.9e 已实现：统一 atomic terminal publication @@ -1225,7 +1225,7 @@ top后续还叠加 service/template等选择；输出核心接口是 - accepted write同时驱动 RF data/ready/wakeup。 2. `RobCompletionNetwork` - 参数化 completion lanes； - - full `CompletionTxn` 送 ROB； + - full `RobResolveTxn` 送 ROB； - exact residency lookup； - duplicate full identity检测； - fair arbitration与 producer credit。 diff --git a/docs/chisel/linxcore-chisel-lsu-improvement-design.md b/docs/chisel/linxcore-chisel-lsu-improvement-design.md index 9f965ff0..a41f83a6 100644 --- a/docs/chisel/linxcore-chisel-lsu-improvement-design.md +++ b/docs/chisel/linxcore-chisel-lsu-improvement-design.md @@ -22,7 +22,7 @@ 本文覆盖标量 load/store、L1D、地址翻译和属性分类、下级存储事务、LR/SC、MMIO、cache maintenance 与 fence。Tile/向量存储只定义共享边界，不在本文内展开。 -本文以源代码为事实来源，模块说明文档用于辅助理解。当前实现仍处于“canonical 岛 + reduced 顶层闭环 + helper 族”的过渡阶段，不能把单个测试通过等同于完整 memory subsystem 已闭合。 +本文以源代码为事实来源，模块说明文档用于辅助理解。当前实现仍处于“canonical 岛 + reduced 顶层闭环 + helper 族”的过渡阶段，不能把单个测试通过等同于完整 memory subsystem 已闭合。I0.15c-b3c2 已把 canonical load launch、三路 STQ 查询/响应、E3/E4 credit 和精确 LIQ 回写在 `ScalarLSULoadPath` 内闭合，但尚未把该边界与 OOO/store fabric 置于同一个 production wrapper 和 common recovery fire 下。 ## 2. 当前 Chisel 实现概览 @@ -47,7 +47,9 @@ flowchart LR 这条路径已经形成 load、store、共享 L1D 与 recovery boundary 的 canonical 组合点，但尚未成为完整核顶层唯一真实路径。尤其是： - frontend/AGU 到 LSU 的完整请求协议尚未闭合； -- store row 到 load E2 查询、SCB 返回和 STQ 返回仍有外部输入痕迹； +- production load 已有三路 retained STQ query/response 边界；该边界到 + `OooIexStoreStqFabric` 的 closed-wrapper 连接、hard-block consumer 与 + physical SCB source owner 仍未闭合； - 翻译/PMA 到属性 sidecar 的正式适配器、下级 memory/coherence 总线尚未闭合； exact memory-class sidecar 与 committed NC/MMIO serializer 已有独立 owner； - LR/SC reservation owner 仍主要组合在 reduced 路径； @@ -584,7 +586,7 @@ ingress、MMIO serializer和静态top组合。 ### 8.11 I0.9o 已实现：exact ROB commit-token ingress -`OooRobStoreCommitOwner`加入 grouped ROB、BROB/PC、P rename 和 T/U retire 的共同 +`CommitControl`加入 grouped ROB、BROB/PC、P rename 和 T/U retire 的共同 commit事务。它从 ROB row保存的每个logical uop memory-order tail重建store范围，验证 release head、RID/BROB/resident generation、member extent、组内和跨组memory chain， 然后把scalar/pair展开成一/两个有序beat token。prepare阶段无副作用；只有共同commit diff --git a/docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md b/docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md index a30860eb..bd2635a9 100644 --- a/docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md +++ b/docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md @@ -166,7 +166,7 @@ flowchart LR OOO -->|"IssueDispatchTxn"| IEX["IEX IQ + RF + FU"] OOO -->|"LsuReservation/Dispatch"| LSU["LSU + L1D + Memory"] IEX -->|"AguRequest"| LSU - IEX -->|"CompletionTxn"| OOO + IEX -->|"RobResolveTxn"| OOO LSU -->|"LoadResultTxn"| IEX LSU -->|"RecoveryEvent"| REC["OOO RecoveryFabric"] IEX -->|"RecoveryEvent"| REC @@ -313,7 +313,7 @@ LID/SID width；cache set/way/line/bank/latency。 | `D3ReservationTxn` | OOO | OOO/IEX/LSU | 最大连续 prefix，multi-owner 原子 token | | `IssueDispatchTxn` | OOO | IEX | exact identity、operand qtag/version、recovery context | | `AguRequest` | IEX | LSU | VA、size/mask、ordering class、full instruction identity | -| `CompletionTxn` | IEX | OOO | retained exact-key terminal transaction | +| `RobResolveTxn` | IEX | OOO | retained exact-key terminal resolve transaction | | `LoadResultTxn` | LSU | IEX W2 | retained full identity/LSID/result；accept 后返回 `LSU_RETURN_ACK` | | `RecoveryEvent` | IEX/LSU | OOO recovery | typed、retained、带 class/provenance；IFU fault 只走 D1 fault row | | `RecoveryResolvedTxn` | OOO recovery | 四域 | 单次 canonical resolve、prepare/commit/ack | diff --git a/docs/chisel/linxcore-chisel-ooo-improvement-design.md b/docs/chisel/linxcore-chisel-ooo-improvement-design.md index 852f731b..cdf9d181 100644 --- a/docs/chisel/linxcore-chisel-ooo-improvement-design.md +++ b/docs/chisel/linxcore-chisel-ooo-improvement-design.md @@ -692,7 +692,7 @@ key 中也缺少独立 BROB pointer/generation。 它是 OOO completion ingress retention 边界，仅负责： - 保留 IEX W2 或 external-engine exact-validation owner 已产生的 - `CompletionTxn`；LSU load 不直接进入该 retainer； + `RobResolveTxn`；LSU load 不直接进入该 retainer； - 进行 exact identity、duplicate 和 stale-residency qualification； - 在 ROB backpressure 下稳定输出； - 接受 central recovery 对 pending completion 的清除。 @@ -896,10 +896,10 @@ resolve；consumer 也尚无 all-owner prepare/ack。 Production O7.2d2/d2e 已经实现本节核心事务：O3 对 ROB/D3/BROB/PC、 P/T/U、dispatch、IEX、fast resolve 做一次 exact common apply；外层 -`OooFrontendRecoveryBridge` 在 prepare 期间只 fence STID，apply 后才清 +`RecoveryControl` 在 prepare 期间只 fence STID，apply 后才清 D1/D2/S1，并等待 typed rebuild completion 与 IFU `canonicalFlush`。 -O7.3 已把 CTU 纳入该原子边界：`OooFrontendRecoveryBridge` 先要求 -`OooCtuIngressBridge` 对目标 STID 做 side-effect-free prepare/fence，随后 +O7.3 已把 CTU 纳入该原子边界：`RecoveryControl` 先要求 +`CTU` 对目标 STID 做 side-effect-free prepare/fence，随后 才向 O3 提交请求；O3 exact apply 同拍取消 CTU retained packet/lease 与 D1/D2/S1，abort 则只释放 fence。剩余缺口主要是 LSU/global producer 接入、跨 source arbitration，以及 O9 外部 CTU recipe engine/top wiring， @@ -1115,7 +1115,7 @@ token、ROB issue/completion bookkeeping 和 completion retention。 ScalarLSU 拥有 LIQ/STQ/SCB/MDB/MissQ/RefillQ/L1D、full LSID memory age、 store visibility 和 retained load-result payload。load result 先进入 IEX -统一 W2 network，再由 IEX 发布 source-qualified exact `CompletionTxn`； +统一 W2 network，再由 IEX 发布 source-qualified exact `RobResolveTxn`； OOO 不直接驱动 load RF/wakeup，也不维护第二条 LSU completion shortcut。 OOO 只协调 D3 reservation、保存 row memory sidecar、接受统一 completion 和 LSU recovery candidate，并把 central recovery transaction fanout 给 diff --git a/docs/chisel/linxcore-chisel-ooo-load-attempt-liq-binding-plan.md b/docs/chisel/linxcore-chisel-ooo-load-attempt-liq-binding-plan.md deleted file mode 100644 index d4141b58..00000000 --- a/docs/chisel/linxcore-chisel-ooo-load-attempt-liq-binding-plan.md +++ /dev/null @@ -1,190 +0,0 @@ -# OOO Load Attempt / Canonical LIQ Binding Plan - -## 1. Status and scope - -This document freezes the production ownership seam between the OOO load -producer and the scalar LSU. I0.15b implements the first bounded packet: - -- exact OOO-compatible producer and attempt-generation sidecar, -- atomic co-allocation with one canonical LIQ row, -- generation-qualified rebind of that same resident row, -- exact retention through LIQ, LHQ/ResolveQ, LRET, W1, and W2, -- flush, stale-token, lifecycle-race, and row-reuse rejection. - -I0.15b does **not** claim that the OOO load path is fully integrated. I0.15c-a -now adds the production-width three-AGU allocation bridge, parent-PC capture, -and exact youngest-older-store LSID tail required by canonical forwarding. The -existing `OooIexLoadUnit` still remains a duplicate request/retry/result owner -until I0.15c-b routes the accepted bridge transaction into -`ScalarLSULoadPath` and returns its terminal result. - -## 2. Ownership - -| State or decision | Sole owner | Contract | -|---|---|---| -| ROB-member producer identity and speculative attempt generation | OOO | `RobMemberKey + load generation`; a generation alone is never authoritative. | -| Physical load residency and `loadId` slot/wrap lease | `LoadInflightQueue` | Allocation, Wait/Repick/L1DcMiss/L2Wait/Resolved, replay, refill, and row release. | -| Memory ordering | Scalar LSU | Full LSID, store snapshot, wait-store, forwarding, miss, and replay rules never use the OOO attempt token as an ordering key. | -| Terminal return residency | LRET queue and W1/W2 pipeline | Retains the exact attempt until the terminal atomic side effects fire. | -| ROB acceptance of a returned load | Future OOO/LSU adapter | Must validate both canonical LSU row identity and the exact producer/attempt token. | - -The OOO token is a sidecar. It cannot mutate LIQ status, select forwarding, -compare load/store age, or replace full LSID authority. - -## 3. Exact attempt ABI - -`LoadAttemptIdentity` contains: - -- attempt `valid`, -- producer `valid`, PE ID, STID, -- native BID valid/value and BROB generation, -- RID slot and RID generation, -- ROB member index and resident generation, -- load-attempt generation. - -The LSU bundle is deliberately independent of `OooParams`; the adapter maps -`RobMemberKey` field by field. Protocol fields reserve 16 bits for scope/index -values and 32 bits for generations. A bridge must use elaboration-time -`require` checks proving every native width fits and must zero-extend. -`LoadAttemptIdentity.requireBridgeFits` is the executable proof point: the -production `OooParams` profile passes, while any over-wide native field rejects -during elaboration. Silent truncation, reconstruction from legacy -`bid/gid/rid`, and opaque hash matching are forbidden. - -An invalid attempt is legal for legacy/non-OOO allocation, but it cannot use -the rebind port. A token marked valid without valid producer and native-BID -identity is malformed and allocation rejects it. Production OOO allocation -must provide a valid exact token. - -## 4. Handshakes - -### 4.1 Initial allocation - -`allocValid && allocReady` creates the canonical LIQ row and captures the -attempt in the same state transition. There is no later best-effort sideband -join. The returned `allocLoadId` is the physical LIQ lease used by subsequent -rebind requests. - -### 4.2 Rebind - -`attemptRebind` carries `{loadId, current, next}`. Acceptance requires: - -1. no hard or precise flush, -2. an exact valid slot-plus-wrap `loadId` match, -3. a resident row in `Wait`, `L1DcMiss`, or `L2Wait`, -4. no same-cycle launch/pick of that row, -5. exact equality between the row token and `current`, -6. identical producer identity in `current` and `next`, -7. `next.generation == current.generation + 1` modulo the protocol width. - -Rebind changes only `row.attempt`. It preserves address, destination, full -LSID, miss state, wait-store state, forwarded bytes, source-return evidence, -and allocation lease. Wrong producer, stale/skipped generation, terminal -residency, same-cycle launch, flush, and row reuse all reject without mutation. - -### 4.3 Terminal return - -The exact token follows this carrier chain: - -```text -LoadInflightAlloc - -> LoadInflightRow - -> LoadHitRecord / ResolveQ - -> LoadReplayReturnLretPayload - -> LRET queue - -> ScalarLSULoadReturnPipeline W1/W2 - -> completion.payload.attempt -``` - -`robLookupAttempt` exposes the same token during the pre-insert ROB validation -cycle. Invalid/data-blocked formatter output emits an invalid zero token. -Queue compaction, W1/W2 backpressure, and precise survivor movement copy the -whole retained entry and therefore cannot substitute a newer row's identity. - -## 5. Recovery and race precedence - -Hard and precise flush outrank allocation, rebind, launch, replay/refill -mutation, and terminal publication. A request visible during a flush reports -`blockedByFlush` and cannot fire. A precise flush may preserve an older row, -but rebind is still suppressed for the flush cycle; the producer retries only -after the surviving row and recovery epoch are stable. - -Rebind is rejected once the row is `Repick` or `Resolved`. This prevents an E4 -result or already-retained terminal return from changing generation under the -consumer. Same-cycle launch/pick is also rejected so the launched attempt and -resident row token cannot disagree. - -## 6. Verification matrix - -| Level | Required evidence | -|---|---| -| LIQ UT | co-allocation; exact next-generation rebind; same generation/different producer; skipped/stale generation; launch race; hard/precise flush; natural same-slot/opposite-wrap reuse; generation wrap. | -| LRET UT | formatter invalidation on missing data; exact token under queue backpressure and compaction. | -| W1/W2 UT | exact `robLookupAttempt`; W1/W2 retention under blocked terminal sinks; precise survivor retention. | -| OOO/LSU IT | alloc -> miss/cancel -> rebind -> final return; recovery with pending response; stale response after row reuse; exact ROB-member acceptance. | -| Parameter gate | unequal `LIQ=4`, `ROB=8`, `STQ=4`, `LSID=40`; 2/4/6 OOO widths once the adapter is present. | - -I0.15b contains dynamic LIQ and W1/W2 tests at unequal capacities and a -40-bit LSID. It also executes the production-width fit proof and rejects -truncating bridge configurations. The OOO/LSU IT rows remain I0.15c exit -criteria. - -## 7. Remaining gaps - -### I0.15c-a: typed allocation seam (implemented) - -- `OooIexLoadLiqAllocAdapter` fairly arbitrates the three physical AGU lanes - into one canonical LIQ allocation port without retaining a second request. -- The adapter calls `LoadAttemptIdentity.requireBridgeFits` and maps every - `RobMemberKey` field, attempt generation, 40-bit full LSID, GPR destination, - address, access size/sign, PC, and physical return-pipe lane explicitly. -- Every scalar load now obtains its architectural parent PC at P1/I1 even when - the address is base/index relative. MDB/store-set/replay indexing is not - allowed to depend on a zero placeholder PC. -- `OooMemoryIdState` now retains - `{youngestStoreLsidValid, youngestStoreLsid}`. A type-local store counter is - insufficient to reconstruct the unified LSID when loads and stores - interleave; the allocator updates this tail on store allocation and existing - ROB snapshots/recovery carry it as part of the exact state. -- Dynamic UT proves three-lane fairness, output backpressure, no generation - consumption on recovery, destructive draining of hard-flushed and exact - killed requests, fail-closed missing PC, exact producer plus displaced-PTag - mapping, narrow projection checks, and unequal `LIQ=4`, `ROB=8`, `STQ=4`, - `LSID=40` geometry. -- Same-BID replay wake ordering now uses the 40-bit wake/snapshot LSIDs rather - than their ROBID projections. Missing full authority and half-range serial - ambiguity fail closed and are exported as LIQ diagnostic masks. -- Allocation keeps speculative wakeup disabled until I0.15c-b supplies the - exact wake/cancel owner in the same live composition. - -### I0.15c-b: make canonical residency live - -- Route all three production load lanes from AGU issue into canonical LIQ - allocation/launch and route terminal W2 results back to exact OOO completion. -- Replace `OooIexLoadUnit`'s duplicated request/miss/retry/result residency; - OOO retains only speculative dependency/cancel policy. -- Make one common recovery plan fence OOO attempt state, LIQ state, LRET, and - W1/W2 before apply. -- Add exact fault/exception terminal payload and prove data/fault are mutually - exclusive. - -### I0.15d and later: close memory-response identity - -- E3/E4 launch tracking currently retains a LIQ index, while cache/refill and - source-return packets are not all attempt-tagged. Every asynchronous return - must revalidate the canonical row lease and relevant attempt generation. -- Compose the three canonical STQ forwarding response pipes directly with - LIQ launch/result mutation; remove the remaining abstract compatibility CAM. -- Close physical DTLB, PMP/PMA, L1D/coherence, device/MMIO, cross-line, and - exception flows under the same owner contract. -- Add timeout/liveness counters, safe-mode behavior, DFX observability, formal - stale-response properties, synthesis timing, and natural workloads. - -## 8. Relationship to `Documents/a.txt` - -The reference notebook motivates speculative load issue, load-generation -cancel/replay, LIQ repick, and retained return mechanisms. LinxCore reuses -those physical techniques but does not copy ARM-specific queue IDs or recovery -semantics. Linx native ROB/BROB member generations, full LSID ordering, and -canonical LIQ ownership remain authoritative; a queue index or numerical load -generation alone is insufficient. diff --git a/docs/chisel/mainline-loop-ledger.md b/docs/chisel/mainline-loop-ledger.md new file mode 100644 index 00000000..bb8635d6 --- /dev/null +++ b/docs/chisel/mainline-loop-ledger.md @@ -0,0 +1,796 @@ +# Chisel mainline execution ledger + +This ledger records the evidence and workflow boundary of each implementation +loop in +`docs/superpowers/plans/2026-07-31-core-mainline-restructure.md`. Commit and +push identities are filled only after the corresponding operation succeeds. + +## Loop 1 — NDF contract spine and reference boundary + +- Scope: Task 1 only; documentation contracts and their executable checker. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `test-driven-development`, `systematic-debugging`, + `verification-before-completion`, and the `linx-core` domain workflow. +- Workflow: confirm a clean dedicated branch; run the existing Chisel baseline; + add checker tests; observe the expected missing-checker RED; implement the + smallest dependency-free checker; create the live clause spine and pinned + reference projections; run focused, local-reference, and Chisel regression + gates. +- RED evidence: `python3 -m unittest tests.test_ndf_profile -v` failed all + seven cases because `tools/spec/check_ndf_profile.py` did not exist. +- GREEN evidence: nine checker tests pass; the live profile reports 27 + clauses, 13 L1 MUST clauses, 13 covered requirements, zero open questions, + and two pinned structural-method references. Strict local-reference + verification reports the same result. `bash tools/chisel/build_chisel.sh` + completes successfully. +- Debug evidence: strict source verification initially treated a checkout HEAD + as the pinned Git identity. Read-only inspection proved that the pinned + commit object existed on another ref. A new regression test now requires + object identity rather than working-branch identity. A second regression + test ensures malformed local-reference metadata reports validation errors + without a Python traceback. +- Result: the contract hierarchy, ownership rules, pipeline boundary, reference + boundary, and executable profile check are established without changing RTL. +- Remaining gap: RTL still follows the pre-restructure hierarchy. Task 2 owns + the centralized parameter profiles and is the next loop. +- skill-evolve: no-update — this loop adds a repository-specific documentation + profile and does not discover a reusable LinxCore hardware invariant beyond + the existing domain skill. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Make the core contract independently reviewable before RTL moves`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded in the loop handoff after the immutable commit exists. + +## Loop 9 — Canonical ROB, BROB, commit, and precise recovery authority + +- Scope: Task 9 only, including twelve review/fix rounds needed to close the + canonical owner semantics before any Task-10 dispatch or TOP cutover. The + loop adds `linxcore.ooo.ROB`, `BROB`, `CommitControl`, and + `RecoveryControl`; it does not integrate the old `OooO3RenameCoordinator` + or change live TOP ownership. +- Baseline and references: the final round starts from the reviewed round-11 + commit `83c86230` plus the atomic-cutover plan commit `989fc583`. NDF + revision `09cfe646931183caee82dd913f77f516b82134df` supplies stable clause + identity and L1/L2/L3 verification edges; Linx semantics remain repository + owned. +- Governing clauses: `OOO-010..013`, `MEC-OOO-006`, `VER-OOO-003`, + `IFC-RECOVERY-001`, `MEC-RECOVERY-001`, `IFC-COMMIT-001`, and + `MEC-COMMIT-001`, together with the exact identity and continuous-prefix + contracts. +- RED evidence: initial Task-9 tests failed because the four canonical owners + did not exist. Review rounds then exposed release-before-apply, preview + mutation, bank geometry, age-token ambiguity, stale/mismatched recovery + responses, compact-suffix endpoint errors, closed-block straddling, wrapped + tail repair, unbound BROB publication, and non-causal target acknowledgements. + Round 12 finally observed real ROB/BROB coordinated publication blocked at + the first unbound D3 packet and a matching target beat held before Prepare + incorrectly triggering Apply on retry. +- GREEN evidence: `OOORobCommitSpec` passes 21/21 and `OOORecoverySpec` + passes 43/43. The latter uses a real ROB/BROB coordinator to prove + allocator-authored BID 0/1/2/3, same-packet members, BID wrap and BROB + generation, resident-generation reuse, release, and suffix recovery. A + same-DUT held-beat/abort/retry test proves only a fresh causal target response + can authorize Apply. +- Cross-gate evidence: ROBID passes 3/3; the generated BROB order-state probe + passes; ROB bookkeeping commits 4623 rows; `TopInterfaceSpec` passes 9/9; + `InterfaceManifestSpec` passes 2/2; the generated interface manifest is + exact; the NDF profile reports 113 clauses, 52 L1 MUST clauses, 59 verified + targets, zero open questions, and two verified references. The forbidden + external-narrative scan is empty. Standard Chisel build and Verilator 5.044 + lint pass. +- Ownership result: ROB owns grouped resident identity, exact completion, + ordered preview/retire/release, candidate status, and compact suffix + recovery. BROB owns per-STID BID/generation allocation and block lifecycle. + Their prepare graph exchanges allocator-authored BROB binding and + ROB-authored resident identity, then mutates only on one common fire. + CommitControl owns the retained all-owner commit authorization. + RecoveryControl owns the single ROB-authored plan and causal all-target + prepare barrier; stale/early beats are drainable but never acknowledgement + authority. +- Independent review: the first round-12 pass found one HIGH test-strength + issue because the held target beat regression adapted to ready instead of + requiring pre-Prepare drain. The corrected test asserts ready before the + state transition, proves the drain, and passes its 3/3 focused subset. Final + re-review reports zero remaining findings and verdict `APPROVE`. +- Remaining gap: these owners remain standalone. Task 10 freezes the checked + production-owner/call-site/deletion manifest; Task 11 then atomically cuts + RENU D3/S1 dispatch onto these owners without importing the duplicate O3 + coordinator. +- skill-evolve: no-update — all twelve rounds apply existing exact-identity, + single-owner, retained ready/valid, causal recovery, parameterization, and + verification rules already captured by the LinxCore skill. +- Branch: `codex/chisel-gap-superpowers` +- Commits: Task-9 history is retained in the branch; the round-12 Lore commit + has intent `Bind every ROB resident to causal BROB and recovery authority`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded after the immutable commit exists. + +## Loop 10 — Checked production-owner cutover manifest + +- Scope: Task 10 Steps 2–4 only. Task 9 Step 1 is already closed by pushed + commit `2758fb00`; this loop does not modify `ROB.scala`, `BROB.scala`, + `RecoveryControl.scala`, or `OOORecoverySpec.scala` and does not begin the + Task-11 OOO dispatch cutover. +- RED evidence: the exact command + `python3 -m unittest tests.test_production_owner_manifest -v` first failed + with `ModuleNotFoundError: No module named + 'tests.test_production_owner_manifest'`. After the fixture suite was added, + the same command failed because + `tools/chisel/check_production_owner_manifest.py` did not exist. +- GREEN evidence: seven real CLI/temporary-repository tests pass. They prove + acceptance of a complete manifest and rejection of duplicate ROB, rename, + IQ, LSU-pipeline, cache, and recovery owners; an unknown scanned Scala + emitter; missing production evidence; a stateful adapter; a deletion target + with active callers; and missing NDF L1/L2/L3/interface-manifest homes. +- Checked baseline: the repository manifest records 23 IFU/CTU/OOO/IEX/LSU/ + DTU state categories and classifies all 40 scanned Chisel emitters. The + checker reports one owner per state key and an executable NDF L1/L2/L3 + mapping. The generated TOP interface manifest is current. Strict NDF local + reference verification reports 113 clauses, 52 L1 MUST clauses, 59 verified + targets, zero open questions, and two references. `git diff --check` passes. +- Ownership result: Task-9 `PRename`, `TURename`, `ROB`, `BROB`, + `CommitControl`, and `RecoveryControl` stay canonical but standalone until + Task 11. Production IEX and LSU mechanisms are named in place rather than + copied behind new stateful boxes. Evidence status distinguishes public-box, + standalone, and mechanism-only proof from later canonical-TOP promotion. +- Entry-point result: `Reduced*`, `*Probe`, and old `LinxCore*Top` emitters are + executable fixtures or legacy paths, never production entry points. No + production `TOP` emitter is claimed before Task 17. +- Independent-review fix round 1: 17 real CLI tests now close six manifest + bypass classes. Schema v2 uses a checker-owned closed inventory for all 23 + state domains and exact canonical symbols/primary mechanisms. It discovers + deletion-target callers and accepts live pre-cutover targets only as + `planned-active` with an exact caller set; only caller-free targets may be + `deletion-ready`. It also discovers and classifies four existing adapter- + named mechanisms, distinguishes public Modules from pending IEX/LSU/DTU + boxes, checks evidence/reachability obligations, owns emitter classification + across App/`def main`/`@main`/wrapper forms, and enforces repo-contained typed + NDF layer roles without path reuse. +- Independent-review fix round 2: 29 real CLI tests close the six remaining + bypasses. Scala caller discovery strips comments and literals and resolves + braced import aliases. Every state domain now has an exact checker-owned + `(symbol, path)` mechanism set. Twelve exact managed boundaries cover + Adapter, Wrapper, and state-owning Bridge classes, including transitive + stateful children; each legacy exception is tied to a domain, cutover task, + and exact deletion target. `production-promoted` fails closed until Task 17 + owns its activation-artifact schema. All 40 emitters have exact FQCN/path/ + classification registrations, including cross-file wrapper reachability; + names cannot self-grant an exemption. NDF roles reject symlinks and detect + hard-linked identity reuse by device/inode. The live checker passes in 6.6 + seconds after emitter propagation was reduced to one definitions/calls index + per Scala source. A final regression also proves a registered non-production + emitter cannot be moved into the production list without Task-17 authority. +- Independent-review fix round 3: five new RED probes close the remaining + repository-identity gaps. Multiline braced alias imports now resolve exact + deletion callers. A shared Scala index resolves package-qualified and + import-aliased constructor edges by FQCN, propagates retained state through + exact `Module(new ...)` children, and makes a compatibility boundary with an + unresolved child fail closed. Emitter reachability resolves object identity + across files, including object `apply`, qualified helpers, and nullary + qualified calls, rather than matching bare method names. All 34 focused + tests pass; the unchanged live manifest remains 23 owners, 40 emitters, and + 12 adapters. The successful CLI reuses validation results for its summary + and completes in 3.40 seconds on the recorded run, below the ten-second + review bound. +- Independent-review fix round 4: the shared Scala index now canonicalizes + `_root_`, rejects unresolved qualified deletion references, scopes imports + to the owning definition, and propagates child state over exact FQCN edges. + Its callable graph is keyed by owner FQCN and callable identity, covering + App bodies, `main`, `@main`, imported or aliased nullary calls, qualified + helpers, and object `apply`. Thirty-nine real CLI tests pass; the live + 23-owner/40-emitter/12-boundary checker remains below the ten-second bound. +- Independent-review fix round 5: one final RED proved that a fully-qualified + cross-package object invocation such as `sink.ApplyEmitSink()` bypassed the + callable graph. Qualified-call lookup now falls back to resolving the full + object FQCN and its `apply` callable. The focused emitter subset passes + 11/11, the full checker suite passes 40/40, and final scoped re-review finds + the issue addressed with no new Critical or Important finding. +- Final checked baseline: `py_compile`, Ruff, the strict NDF profile, generated + TOP interface-manifest parity, protected Task-9 file comparison, and + `git diff --check` pass. The final live checker completes in 5.82 seconds. + Review round 5 reports no open finding. +- Remaining boundary: Task 11 must update this manifest in the same atomic + commit that changes OOO D3/S1 call sites and deletes the displaced legacy + owner chain. The controller owns push and remote-equality confirmation before + Task 11 begins. +- skill-evolve: no-update — the loop makes the existing single-owner, + no-stateful-adapter, production-evidence, and NDF-layer rules executable; it + introduces no new reusable LinxCore hardware invariant. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit has intent + `Freeze one production owner before changing another boundary`. +- Push target: `origin/codex/chisel-gap-superpowers`; final review is clean and + commit `0c998275d9e8b05cbb444295e76643685c4a6d7e` was pushed with local, + tracking-ref, and remote-advertised branch identity equal before Task 11. + +## Loop 7 — Canonical DEC and retained OOO D1/D2 admission + +- Scope: Task 7 only, preceded by the NDF/interface planning correction in + `89f081ed`. This loop adds the canonical combinational DEC and public OOO + D1/D2 slice. It does not allocate physical ROB/BROB state, rename registers, + dispatch to issue queues, or integrate the box in TOP. +- Baseline: implementation started from LinxCore `5780f40d`; the plan pins the + SuperscalarNPU reference boundary and normative_language/NDF revision + `09cfe646931183caee82dd913f77f516b82134df`, including `option`, `default`, + `explore`, and `couples-with` semantics. +- Governing clauses: `IFC-CTU-OOO-001`, `MEC-CTU-OOO-001`, `OOO-001..005`, + `MEC-OOO-001..002`, `D-PREFIX-001`, `D-IDENTITY-001`, `ARC-TOP-020..021`, + `PRM-WIDTH-001`, `VER-IFC-001`, `VER-ARC-005..006`, `VER-OOO-001`, + `REF-NDF-001`, and `REF-SNPU-001`. +- RED evidence: `OOODecodeSpec` first failed to compile because `DEC`, `OOO`, + and `D2AdmissionGroup` did not exist. A template fetch-fault regression then + observed `trap.valid=0`. Independent review exposed a legal CTU repacking + case that combined an ordinary instruction with template children while D2 + was occupied; the real CTU-to-OOO test timed out after 64 cycles because DEC + rejected the mixed tagged union and held ready low. +- GREEN evidence: `OOODecodeSpec` passes 8/8 checks for 16/32/48/64-bit + normalization, template children, typed traps, mixed-lane fusion isolation, + full-width virtual RID identity, recovery and W2/W4/W6/W8 elaboration. + `CTUOOOIntegrationSpec` passes 3/3, including retained backpressure followed + by exact in-order draining of a repacked ordinary-plus-template prefix. + `OooD1DecodeSpec` passes 12/12 and proves the legacy dense-prefix assertion + remains the default; `CTUSpec` passes 11/11; `TopInterfaceSpec` passes 9/9; + and `InterfaceManifestSpec` passes 2/2. +- Generated/spec evidence: opcode generator tests pass 6/6 and decode parity + covers 686 forms and 678 mnemonics. The generated interface manifest is + current and unchanged because the existing CTU-to-OOO endpoint remains a + `D1Packet`; the Task-7 slice adds no canonical TOP endpoint yet. The NDF + profile reports 97 clauses, 43 L1 MUST clauses, 46 verified targets, zero + open questions, and two verified local references. +- Build evidence: the standard Chisel build passes. Generated TOP elaboration + and Verilator 5.044 lint pass. `git diff --check` passes and the opcode parity + generator's pre-existing `xb` row side effect was restored rather than + admitted into this loop. +- Ownership result: all public D1/D2 payloads and `OOOD1D2IO` live under + `top/interface`. DEC owns no state. D2 retains immutable virtual RID group + and member intent from full-width tail snapshots but never advances the + tail. `residentBound` and `brobBound` remain false; BID, BROB generation and + resident generation are explicitly unallocated. Recovery prepare fences one + STID, matching apply cancels only that row, and abort releases the fence + without mutation. +- Independent review: the first pass found two blocking design defects: mixed + CTU packets could deadlock admission, and public OOO interface types were in + the implementation package. The same implementer repaired both under TDD. + A fresh final reviewer inspected `89f081ed..b46b0e83`, independently ran the + NDF and diff checks, and reported 0 critical, 0 important, 0 minor findings + with verdict `APPROVE`. +- Remaining gap: Task 8 owns D3 rename and resource reservation. Physical + P/T/U mapping, SMAP/CMAP/MAPQ, freelists, unique ROB/BROB binding, early ROB + completion and S1 dispatch remain absent. TOP integration remains Task 17; + natural Dhrystone/CoreMark and scalar linx-avs evidence remain Tasks 18–19. +- skill-evolve: no-update — single-owner allocation, full identity retention, + retained ready/valid, exact recovery and generated-decode rules already + exist in the LinxCore domain workflow. +- Branch: `codex/chisel-gap-superpowers` +- Commits: plan correction `89f081ed`, initial implementation `54c05d72`, and + reviewed mixed-packet/interface repair `b46b0e83`. +- Push target: `origin/codex/chisel-gap-superpowers`; controller push and + remote equality are the final loop handoff. + +## Loop 8 — D2/D3 rename with separate P and T/U owners + +- Scope: Task 8 only. This loop adds the D2-to-D3 RENU slice, public + `OOOD2D3` payloads, and central rename generation parameters. It does not + instantiate ROB/BROB physical binding, S1 dispatch, issue queues, LSU + allocation, or TOP end-to-end benchmark flow. +- Reference/contract boundary: NDF revision + `09cfe646931183caee82dd913f77f516b82134df` supplies stable clause identity, + L0-L3 refinement, typed graph edges, history and verification coverage. + SuperscalarNPU supplies only typed-interface grouping and reviewable TOP + wiring patterns. Neither source defines Linx payload semantics or RTL. +- Governing clauses: `ARC-TOP-021`, `OOO-006..009`, `PRM-RENAME-001`, + `MEC-OOO-003..005`, `VER-OOO-002`, `VER-PRM-004`, plus the Task-7 D1/D2 + clauses and continuous-prefix identity rules. +- RED evidence: the expanded rename suite first ran 15 checks with 10 passing + and 5 failing. It exposed relative-source underflow acceptance, incorrect + same-uop WAW history, non-survivor recovery, missing cross-domain release + atomicity, and conflated physical/MapQ generations. Later directed REDs + exposed malformed release and D2 prefixes, and the final backpressure RED + observed `recovery.prepare.ready=1` where a held target D3 row required 0. +- GREEN evidence: `RENUSpec` passes 15/15 checks, `RENUAtomicSpec` passes 7/7, + and `TURenameSequenceSpec` passes 4/4. Together they cover D3-only + publication, P RAW/WAW forwarding, independent T/U physical and sequence + domains, exact all-or-none release, capacity exhaustion, stale generations, + zero-destination sidecars, STID-scoped survivor recovery, held-target + irrevocability, unrelated-STID progress, unequal capacities and behavioral + W2/W4/W6/W8 publication. `OOODecodeSpec` passes 8/8 and + `CTUOOOIntegrationSpec` passes 3/3 without integrating RENU into the OOO box. +- Interface/parameter evidence: `TopInterfaceSpec` passes 9/9, + `CoreConfigurationSpec` passes 12/12, `OooParamsSpec` passes 4/4, + `CoreParamsInterfaceClosureSpec` passes 2/2, and `InterfaceManifestSpec` + passes 2/2. The generated TOP interface manifest is an exact current + projection. The NDF profile reports 107 clauses, 48 L1 MUST clauses, 54 + verified targets, zero open questions, and two verified local references. + The forbidden external-architecture-name scan under `docs/spec` is empty. +- Build evidence: `bash tools/chisel/build_chisel.sh` passes. Generated TOP + elaboration and Verilator 5.044 lint pass. `git diff --check` is clean. +- Ownership result: `PRename` is the P SMAP/CMAP/free/generation/MapQ owner. + `TURename` separately owns T and U physical cursors, sequence generations + and MapQs. `RENU` owns only per-STID provisional D3 retention, exact + cross-owner publication/release coordination and the recovery handshake. + The public D2/D3 payload and per-uop release history live in `top/interface`. +- Independent review: the first final review blocked recovery because prepare + could switch a target D3 payload held under backpressure and found a vacuous + recovery test with mismatched plans. The repaired version blocks prepare + until the irrevocable target fires, keeps unrelated STIDs live, and performs + observable suffix pruning with an exact plan. A fresh read-only reviewer + returned `APPROVE` with no remaining correctness or scope blocker. +- Remaining gap: this is a standalone RENU slice. ROB/BROB identity remains + virtual, release has no real commit producer, and dispatch/S1 is absent. + Task 9 must establish ROB/BROB, commit and precise-recovery authority; Task + 10 must join rename publication to real ROB/BROB and dispatch readiness. +- skill-evolve: no-update — this reinforces existing LinxCore invariants + around single state owner, exact identity, retained ready/valid, and + recovery scope; no shared skill change is needed. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Preserve absolute and relative register semantics with separate owners`. +- Push target: `origin/codex/chisel-gap-superpowers`; controller push and + remote equality are the final loop handoff. + +## Loop 6 — B-SIDE prediction and IFU recovery consolidation + +- Scope: Task 6 only. This loop creates the public `linxcore.ifu.BSide`, + `Prediction`, and `IFURecovery`/`IFUBackendFeedback` boundaries, wires + `LinxCoreIfu` through those names, and keeps the public `IFU` W2/W4/W6/W8 + fixed-64-bit delivery surface unchanged. It does not add a second predictor, + history queue, redirect arbiter, or backend feedback state owner. +- Baselines: implementation started from LinxCore + `833c354cb38a3e3d2d47226a62c4b4e2b2f03dbb`; superproject + `54635e8cb1119e5f199228cb7db330b168bf7dc0`; LinxCoreModel + `31555f49dbb020c8eb9f26f7df98310a7415b69d`; QEMU + `c9f9570aa70da7e193ff8857bd9bde2cf052e546`. +- Governing clauses: `IFU-001..008`, `MEC-IFU-001..006`, + `IFC-IFU-CTU-001`, `MEC-IFU-CTU-001`, `IFC-RECOVERY-001`, + `VER-IFU-001..005`, and the interface manifest clause. Interface Bundle + shapes did not change, so the generated top-interface manifest is a check + input rather than a regenerated artifact. +- Interface fanout: producer `IFU`/`ISide`/`BSide`; consumers CTU, external + memory, and OOO-authored recovery/validation producers. Backend facts enter + IFU only as OOO-authored validation or typed recovery data; there is no + direct IEX-to-IFU control input. +- RED evidence: `IFUPredictionSpec` and `IFURecoverySpec` first failed + compilation with missing `BSide`, `IFURecovery`, and `IFUBackendFeedback` + symbols, proving that the public boundary did not exist. +- GREEN evidence: `IFUPredictionSpec` passes six checks covering the complete + Sequential/B-F0/B-F1/B-F2/B-F3/B-F4 provider order, stale training rejection + without predictor mutation, exact checkpoint-owned GHR recovery, canonical + RAS recovery, exact public B-SIDE training, and public B-SIDE elaboration. + The B-F3 case drives real public behavior: B-F2/BIM predicts taken, the test + returns the canonical prune, and B-F3/ShortTage corrects to not-taken before + final seal. `IFURecoverySpec` passes four checks covering + backend-over-prediction priority, retained redirect hold under backpressure, + structurally typed OOO-authored feedback with no IEX control port, and atomic + mispredict training plus backend recovery. `IFUCTUIntegrationSpec` passes two + checks whose behavioral traffic, retained backpressure, scoped recovery + fence/apply, and fixed-64-bit payload assertions all execute in + W2/W4/W6/W8; elaboration also exposes the explicit B-SIDE/recovery modules in + every profile. +- Adjacent evidence: `IFUISideSpec`, `CTUSpec`, interface/manifest/NDF checks, + Chisel build, Verilator lint, and diff hygiene are recorded in the Task 6 + report after the full wrapper ladder completes. +- Result: prediction remains speculative and owned below one B-SIDE boundary; + typed recovery remains singular and overrides unpublished prediction + corrections through the canonical redirect owner. The IFU-to-CTU payload + remains the same complete fixed-64-bit fetched-packet interface from Loop 5. +- Independent review: round one required real lower-provider, checkpoint/state, + and W2/W4/W6/W8 behavioral coverage. Round two accepted those repairs but + rejected a constant-only B-F3 rank check. Systematic debugging then proved + that B-F3 is intentionally silent when ShortTage agrees with B-F2 and that + B-F4 waits for exact boundary metadata; the final public-path regression + forces a legal BIM/ShortTage direction conflict. Round three reports zero + critical, important, or minor findings. +- Remaining gap: public IFU exposes typed recovery today; live backend + validation/training waits for the later TOP/OOO integration packet to supply + the OOO-authored producer. Natural ELF/commit evidence remains Tasks 18–19. +- skill-evolve: no-update — the reusable invariants are already covered by the + existing LinxCore workflow: single state owner, exact identity matching, + retained ready/valid, and OOO-owned recovery authority. +- Branch: `codex/chisel-gap-superpowers` +- Commits: `7b1319e4..fdb1078e`, beginning with the Lore intent + `Keep prediction speculative while recovery authority remains singular` and + ending with the independently approved B-F3 behavioral proof. +- Push target: `origin/codex/chisel-gap-superpowers`; controller will push. + +## Loop 2 — Central parameters and configurable profiles + +- Scope: Task 2 plus the NDF interface-contract refinement requested while the + loop was active; no box state or datapath was migrated. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `test-driven-development`, `verification-before-completion`, and the + `linx-core` domain workflow. +- Workflow: add the W2/W4/W6/W8 profile test first; observe missing central + parameter types; implement immutable module records and cross-parameter + checks; add value-only legacy adapters behind their own RED/GREEN cycle; + expose and close the old OOO W8 sizing gaps; project parameter options, + coupling and verification into the local NDF profile; expand Task 3 with + boundary homes and L1/L2/L3 interface acceptance. +- RED evidence: `CoreConfigurationSpec` first failed because + `linxcore.params`, profiles and adapters did not exist. A later adapter test + failed first on the old 2/4/6 decode-width restriction, then on W8 + store-commit and PC-bank capacity. The new NDF coupling test failed because + `couples-with` was not yet a checked edge. +- GREEN evidence: `CoreConfigurationSpec` passes 9 tests, including all four + profiles, invalid combinations, topology defaults and value-only adapters. + `OooParamsSpec` passes 3 tests including W8 decode construction. + `CoreParamsInterfaceClosureSpec` passes 2 compatibility tests. + The 10 NDF-checker tests pass; the live profile reports 37 clauses, 17 L1 + MUST clauses, 18 verification targets, zero open questions and two pinned + references under both ordinary and strict local-reference checks. + `bash tools/chisel/build_chisel.sh` completes successfully. +- Result: the central parameter boundary now owns principal widths, module + resources and validation. W4 preserves the requested IEX/LSU topology; + W2/W4/W6/W8 are constructible profiles. Temporary adapters derive dependent + legacy capacities but own no state. +- Interface-plan refinement: Task 3 now freezes eight contract homes + (IFU–CTU, CTU–OOO, OOO–IEX, IEX–LSU, recovery, commit, DTU and memory), + requires stable NDF IDs and typed edges, and separates L1 observable + contracts, L2 Bundle mechanisms and L3 executable checks. Generated + manifests remain projections of elaborated Bundles rather than a competing + field source. +- Remaining gap: the typed Bundles, complete box IOs and generated manifest do + not exist yet. Task 3 owns that implementation. +- skill-evolve: no-update — width/resource coupling is specific to this core; + no new reusable invariant is needed in the shared LinxCore skill. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Keep every width and resource choice explicit at one boundary`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded in the loop handoff after the immutable commit exists. + +## Loop 3 — Typed TOP interfaces and generated manifest + +- Scope: Task 3 only, plus the smallest wrapper repair needed to execute the + required generated-RTL lint; no box state or datapath was migrated. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `using-git-worktrees`, `test-driven-development`, + `systematic-debugging`, `requesting-code-review`, + `verification-before-completion`, and the `linx-core` domain workflow. +- Workflow: establish eight interface contract homes; observe the missing-L3 + coverage failure; add Bundle tests and observe the missing-type compile + failure; implement canonical transactions and box IOs; generate JSON and + Markdown projections from the canonical payload Bundles; run focused, + compatibility, build, NDF, generated-file, and Verilator gates; resolve an + independent code review before closeout. +- RED evidence: the NDF checker reported exactly eight missing verification + edges for the new L1 interface requirements. `TopInterfaceSpec` then failed + because `FetchedPacket`, `D1Packet`, identities, uops, boundary IOs, and the + manifest model did not exist. +- GREEN evidence: the interface suite passes eight checks across W2/W4/W6/W8, + count-only prefixes, 64-bit instruction containers, generation-qualified + identities, configurable native BID slots, P/T/U rename tags, independent + CMD and LDA/STA/STD paths, prepare/prepared/apply/abort recovery, retained + payload assertions, and aggregate IO elaboration. The manifest suite passes + two checks and `render_top_interface_manifest.py --check` reports exact + generated JSON/Markdown parity. The NDF profile reports 58 clauses, 25 L1 + MUST clauses, 26 verified targets, zero open questions, and two pinned + references. +- Compatibility evidence: the existing `InterfaceBundles` suite passes nine + tests and `CoreConfigurationSpec` passes nine tests. The standard Chisel + build and full existing-top Verilator lint pass. These are no-regression and + structural evidence only; this loop does not claim new-mainline composition + or workload replacement. +- Debug evidence: the first full lint attempt exhausted a 1 GiB JVM because + `emit_verilog.sh` did not consume the validated + `LINX_CHISEL_SBT_MEM_MB` boundary used by the build and test wrappers. The + wrapper now sources the shared environment and passes the configured heap to + the server invocation. After one clean cache restoration, elaboration and + Verilator lint complete successfully. +- Review evidence: independent review found that the first manifest omitted + recovery `prepared` and `abort`, and that native BID was fixed at eight bits. + The manifest now covers the complete recovery target protocol and guards its + channel set against `RecoveryTargetIO`; native BID width derives from the + configurable per-STID BROB slot count while BROB generation remains + independent. Directed 64- and 512-slot tests prove six- and nine-bit BID + shapes. +- Result: every cross-box payload has one canonical class under + `top/interface`; each box and TOP has one directioned IO aggregate; every + manifest endpoint names an NDF contract home; and checked-in generated + projections are rejected when they drift from the Scala model. +- Remaining gap: the new IO classes are not yet connected to box + implementations. Task 4 owns CTU and its retained Instruction Buffer before + IFU/OOO composition begins. +- skill-evolve: no-update — exact identity separation, recovery + prepare/apply, retained ready/valid payloads, and the 4 GiB wrapper contract + are already present in the LinxCore workflow; this loop applies them to the + new interface boundary. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Give every box one typed contract and one direction of authority`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded in the loop handoff after the immutable commit exists. + +## Loop 4 — CTU template descriptions and retained Instruction Buffer + +- Scope: Task 4 only. This loop creates the new CTU box, canonical template + child descriptions, retained D1 buffering, CTU behavior clauses, and focused + verification. It does not connect IFU or OOO and does not migrate ROB, + BROB, rename, issue, or LSU state. +- Baselines: LinxCore `34e337d393893e095361457eb639a7eb2c572694`, + superproject `54635e8cb1119e5f199228cb7db330b168bf7dc0`, + LinxCoreModel `31555f49dbb020c8eb9f26f7df98310a7415b69d`, and + QEMU `c9f9570aa70da7e193ff8857bd9bde2cf052e546`. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `test-driven-development`, `systematic-debugging`, + `requesting-code-review`, `verification-before-completion`, and the + `linx-core` domain workflow. +- Workflow: inspect the generated opcode catalog and existing canonical + template row definitions; add CTU and Instruction Buffer tests first; + observe the missing-module RED; implement catalog-backed template + recognition, child descriptors, retained packetization, scoped recovery and + trace; replace an expensive square compaction network with ordered sparse + slots; add L1/L2 behavior clauses, observe missing L3 coverage, then add + executable conformance edges; run focused, adjacent, build, profile and + generated-RTL gates; resolve independent review before closeout. +- RED evidence: `CTUSpec` and `InstructionBufferSpec` first failed compilation + because `CTU`, `TemplateDecode`, `TemplateExpand`, and the retained + `InstructionBuffer` did not exist. The NDF checker later reported five + missing `verifies` edges for `CTU-001..005` and exposed one misspelled + ownership reference. +- GREEN evidence: `CTUSpec` passes eleven checks covering width-wide ordinary + transfer, complete identity/prediction retention, FENTRY/FEXIT/FRET recipes, + malformed-range fallback, multi-packet expansion, cross-parent ordering, + stable backpressure, exact prepare/apply and abort recovery, retained trace, + W2/W4/W6/W8 packetization, and absence of backend state owners. + `InstructionBufferSpec` passes four new checks; its wildcard gate also keeps + thirteen existing frontend buffer checks green. `TopInterfaceSpec` passes + eight checks. The standard Chisel build and existing-top Verilator lint pass. + The NDF profile reports 69 clauses, 30 L1 MUST clauses, 31 verified targets, + zero open questions and two pinned references. +- Independent review: a separate code-review pass inspected all four CTU RTL + owners, both focused test suites, both NDF documents, and the adjacent opcode + metadata state. It reported zero blocker, high, or medium findings and + independently reran `CTUSpec` at eleven of eleven and `TopInterfaceSpec` at + eight of eight. +- Debug evidence: the first implementation used a self-referential decode + match wire, which FIRRTL correctly rejected as a combinational cycle. A + catalog-order expression chain removed the cycle. The first exact recovery + compactor selected every destination from every retained 64-bit operation + and made one CTU test run take almost sixteen minutes. Ordered sparse slots + with one 64-bit enqueue order per entry reduce selection to + `ctuOutputWidth × instructionBufferEntries`; the same suite completes in + under two minutes while preserving target-STID invalidation and unrelated + order. +- Result: ordinary and template-derived operations share one retained D1 + stream. Template children retain their raw parent and describe only row + identity, ordinal, count and child immediate; OOO remains responsible for + D1/D2 validation and D3 resource reservation. IFU readiness is registered + away from OOO readiness through packet retention and pre-cycle buffer + credit. +- Remaining gap: CTU is not yet connected to the new IFU and OOO boxes. + Tasks 5–7 own I-SIDE delivery, B-SIDE/recovery composition, and D1/D2 + validation plus ROB admission. +- skill-evolve: no-update — this loop applies existing generated-decode, + retained ready/valid, exact recovery, and single-owner rules. It adds no + reusable invariant beyond the installed LinxCore workflow. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Make template expansion a retained boundary instead of frontend glue`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded in the loop handoff after the immutable commit exists. + +## Loop 5 — IFU I-SIDE and fixed-64-bit delivery + +- Scope: Task 5 only, plus a planning-only interface-refinement amendment. + This loop creates the public `IFU`, reuses the existing I-SIDE lookup, + miss/refill, cross-line, prediction-join, and epoch owners, adds the retained + canonical Fetch Buffer, and exposes typed instruction-memory traffic. It + does not extract the final B-SIDE owner or connect IFU to CTU in TOP. +- Baselines: implementation started from LinxCore + `3bcbb841455b2b74be672f189ef9bbd222ed45c2`; the interface work-order + amendment is `31d1f98ede5e9370361781334bfae5b37184114f`; + superproject `54635e8cb1119e5f199228cb7db330b168bf7dc0`, + LinxCoreModel `31555f49dbb020c8eb9f26f7df98310a7415b69d`, and QEMU + `c9f9570aa70da7e193ff8857bd9bde2cf052e546`. +- Governing clauses: `IFC-IFU-CTU-001`, `MEC-IFU-CTU-001`, + `IFC-MEMORY-001`, `MEC-MEMORY-001`, `IFU-001..007`, + `MEC-IFU-001..005`, and `D-IFU-001`. One-hop dependencies cover width + profiles, prefix packets, exact identity, CTU/OOO ownership, recovery, and + observational trace. +- Interface fanout: producer `IFU`/`ISide`; consumers CTU and external memory; + canonical payloads `FetchedPacket`, `MemoryRequestTxn`, + `MemoryResponseTxn`, and `RecoveryTargetIO`; central checks in + `ParamChecks`; generated manifest and IFU/interface/CTU adjacent tests. + TOP wiring remains intentionally not applicable until Task 17. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `test-driven-development`, `systematic-debugging`, + `requesting-code-review`, `verification-before-completion`, and the + `linx-core` domain workflow. +- RED evidence: `IFUISideSpec` first failed compilation with sixteen missing + `IFU`, `ISide`, `FetchBuffer`, and parameter symbols. A later configuration + test proved that a trace packet narrower than the IFU prefix had no guard. + The first public two-STID extension also showed that holding all older STID0 + output prevents observing younger STID1 output; allowing the ordered prefix + to drain proves the intended independent forward progress. A trace-stall + extension then proved that the first trace implementation incorrectly + consumed architectural delivery credit. Finally, a directed denied-line + response timed out because the adapter substituted zero data instead of + publishing a fetch fault. +- GREEN evidence: `IFUISideSpec` passes four checks: retained W2/W4/W6/W8 + repacketization with stable stall and 2/4/6/8-byte lengths; scoped pruning + with a legal two-STID profile; W2/W4/W6/W8 public IFU elaboration; and a + public two-STID flow covering ITLB replay, I-cache refill, stale-response + rejection, cross-line assembly, exact prepare/apply, unrelated survivor + retention, redirected nonzero-STID progress, recovery-fence release, + non-blocking stable trace, and denied-line conversion to an exact + `fetchFault` with its original cause. + `CoreConfigurationSpec` passes ten checks including the new trace-width + constraint. +- Adjacent evidence: the unchanged private IFU path passes all seven + `LinxCoreIfuSpec` scenarios; `CTUSpec` passes eleven checks; + `TopInterfaceSpec` passes eight; `InterfaceManifestSpec` passes two; the + generated manifest is exact; the Chisel build and existing-top Verilator + lint pass. The NDF checker tests pass ten of ten and the live profile reports + 86 clauses, 37 L1 MUST clauses, 38 verification targets, zero open questions + and two pinned references. +- Independent review: the first pass found two high-priority issues: + instruction-line errors were converted to zero data, and the then-current + trace-stall/multi-STID test was red. The line-fault owner, non-blocking trace + path, directed regressions, and `D-IFU-001` resolve both. The second pass + reports zero critical, high, medium, or low findings and independently + reruns `IFUISideSpec` at four of four, `CoreConfigurationSpec` at ten of ten, + the manifest check, and the live NDF profile. +- Debug evidence: the first profile-elaboration test used four full simulator + builds and was replaced with direct SystemVerilog elaboration. The first + stable-payload assertion attempted `asUInt` outside a hardware module and + was replaced by field snapshots. A one-STID dynamic index warning was + removed with a static Scala branch. The final two-STID elaboration still + reports three pre-existing aggregate-enum cast warnings inside the retained + F0 prediction-context selector; Task 6 owns that B-SIDE/F0 consolidation. +- Result: IFU now presents one retained `count + Vec` stream of complete + 64-bit instruction containers independent of its four-lane private assembly + geometry. Translation and line requests have explicit access kinds and + exact generation-qualified response matching. A denied/corrupt line beat + cannot install substituted or partial L1I data and instead retains one + canonical fault with the original cause. Trace loss cannot consume IFU-to-CTU + credit. The canonical payload carries architectural fetch, prediction, and + fault identity only; CTU preserves it, and OOO remains the ROB/BROB + allocation owner. +- Remaining gap: Task 6 must extract/consolidate B-SIDE prediction, remove the + retained enum-cast warnings, and close final IFU recovery integration. + IFU-to-CTU adjacent composition remains Task 6, and natural ELF/commit + evidence remains Tasks 18–19. +- skill-evolve: no-update — exact identity, retained ready/valid, + generation-qualified stale rejection, scoped recovery, and single-state + ownership are already established LinxCore workflow rules. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Make fixed-width instruction delivery independent of fetch geometry`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded in the loop handoff after the immutable commit exists. + +## Loop 11 — Canonical OOO memory order and exact NFRDY authorization + +- Scope: Task 13 Steps 2–3 only. This loop closes the canonical OOO-to-IEX + memory-control payload, the unique OOO memory-order owner, ROB recovery + snapshots, and the exact noflush-ready authorization prerequisite. It does + not activate the public IEX box; private IEX ingress and terminal conversion + remain Step 4. +- Skills: repository-pinned `using-superpowers`, `executing-plans`, + `test-driven-development`, `requesting-code-review`, + `verification-before-completion`, and the `linx-core` domain workflow. +- Owner decision: `OooMemoryOrderAllocator` is the sole per-STID owner of the + full program-order LSID, load-only LID, store-only SID, YOST, and YOLD tails. + IEX owns each memory transaction and its initial attempt; LSU owns replay, + reissue, repick, rebind, and every later attempt. Dispatch transaction IDs, + ROB identities, prefix lanes, and physical queue rows never synthesize + memory identity. +- Interface mapping: DEC normalizes `DecodedMemoryControl`; one common D3 fire + publishes `MemoryOrderMeta` with `DispatchTxn` while ROB retains the exact + before/after `MemoryOrderState`. IEX presents one exact + `RobNoflushReadyTxn` NFRDY proof; CommitControl continuously matches it to a + live per-STID ROB head before emitting `RobNoflushTxn` authorization. +- RED and debug evidence: the first integration run exposed nine stale fixture + expectations after memory order became mandatory. Independent review then + found four important gaps: the proof did not encode completed legality and + drain authority, per-STID suppression could be lost, the recovery suffix + offset could wrap at full ROB capacity, and L3 coverage omitted the common + graph. The first fix review found one further gap: an exact proof was still + consumed while its STID was recovery-fenced. Generated interface projections + also correctly failed until regenerated. +- GREEN evidence: `TopInterfaceSpec` passes 12/12 and + `InterfaceManifestSpec` passes 5/5. `OooMemoryOrderAllocatorSpec` passes 4/4; + `OOOMemoryOrderIntegrationSpec` passes 3/3; `OOORecoverySpec` passes 44/44; + `OOORobCommitSpec` passes 23/23; `OOODecodeSpec` passes 8/8; and the combined + OOO/CTU adjacent suite passes 7/7, including W2/W4/W6/W8 elaboration. The + standard Chisel build and Verilator 5.044 lint pass. The generated interface + manifest is exact; the owner checker reports 24 closed owners, 40 classified + emitters, and 10 declared adapters; the NDF profile reports 126 clauses, 56 + L1 MUST clauses, 65 verified targets, zero open questions, and two verified + references. +- Recovery and authorization result: provisional memory state cancels without + publication; target apply restores the ROB-authored survivor tail while + abort and peer STIDs preserve state. A full-capacity youngest branch kills + zero members without wrapping its suffix count. Stale or mismatched NFRDY + proofs drain without authorization; an exact unaccepted proof is retained + across a recovery fence; and fired suppression remains attached to the exact + resident head so peer arbitration cannot duplicate it. +- Deletion and adapter result: no stateful adapter or parallel memory-order + owner was added. This prerequisite loop deletes no live private IEX + mechanism; Step 4 converts those mechanisms in place and removes displaced + private ingress, lease, readiness-shadow, terminal, and recovery-projection + surfaces in the same atomic cutover. +- Independent review: the second fix review reports every previous important + finding addressed, zero new critical or important findings, and verdict + `APPROVE`. +- Remaining gap: Task 13 Step 4 owns private IEX ingress, IQ and terminal + conversion; Step 5 then closes the Task-14 LSU prerequisite graph and commits + the joint prerequisite boundary. No public IEX/LSU activation is claimed by + this loop. +- skill-evolve: no-update — this loop applies existing single-owner, exact + identity, retained ready/valid, common-fire, recovery-fence, and + generation-qualified protocol rules already captured by the LinxCore skill. +- Branch: `codex/chisel-gap-superpowers` +- Commit: the enclosing Lore commit with intent + `Bind OOO memory order and NFRDY to one publication`. +- Push target: `origin/codex/chisel-gap-superpowers`; exact commit and remote + equality are recorded after the immutable commit exists. + +## Loop 18 — Natural W2 closure and workload-driven execution coverage + +- Status: in progress. This loop uses the natural ELF harness to close the + connected TOP path before any Dhrystone or CoreMark success claim. Its + iteration profile is W2, a 2048 MiB SBT heap, one outer build job, 20,000 + maximum cycles, a 2,000-cycle heartbeat, and a 3,000-cycle deadlock window. + W4/W6/W8 generation is deferred during workload debugging. The simulation + rename/ROB floor remains 16 rows because the prior 4-row profile deadlocked + while an open block held all rename capacity. The natural runner now defaults + to this W2/one-job/20k/2k/3k iteration profile; final benchmark and width + gates can override each value explicitly. Four focused runner tests prove + the new defaults, self-test manifest, explicit parallel override, and invalid + job-count rejection. +- Ownership decision: Option A remains authoritative. IEX allocates each + memory transaction and its initial attempt; LSU owns replay, reissue, + repick, rebind, and all subsequent attempts. +- Current workload evidence: exact P/T/U readiness and cross-epoch P wakeup + repairs advanced the retained owner into ALU execution. Completing the base + scalar shift family then advanced the same W2 natural ELF from 27 to 36 + commits. The run stopped at cycle 3,497 after last progress at cycle 496, + with activation IFU 116, CTU 5, OOO 36, IEX 14, and LSU 9. This is forward + progress, not a benchmark pass. A second fresh W2 model containing the + load-immediate repair advanced to 37 commits and stopped at cycle 3,488 + after last progress at cycle 488, with activation IFU 114, CTU 5, OOO 37, + IEX 14, and LSU 9. The terminal state is still deadlock. +- Compact-memory classification and typed T-destination propagation then + advanced the same ELF from 37 to 40 commits. The single-job W2 run stopped + at cycle 3,522 after last progress at cycle 522, with activation IFU 135, + CTU 5, OOO 40, IEX 21, and LSU 10. Static ELF decode places + `OP_C_SETC_NE` at `pc=0x10100` immediately after the last committed + `OP_C_SEXT_W`; that is the next candidate owner, not yet a retained-state + proof. No benchmark pass is claimed. +- Current focused evidence: the 12-case register/immediate, 64-bit/word, + logical/arithmetic shift regression passes 1/1. A temporary read-only probe + then identified the next exact owner as zero-source `OP_HL_LUI`, with + `OP_LUI` retained behind it. The probe was removed. A four-case regression + for normalized `OP_LUI/OP_HL_LUI/OP_HL_LIS/OP_HL_LIU` now passes 1/1. +- Focused compact-memory evidence passes frontend offset normalization, all + four D1 forms, AGU/LIQ/terminal T-destination propagation, the 8/8 catalog + form suite, and the 689-entry deterministic recipe audit. +- Resource evidence: the shift-focused GREEN retained approximately 117.4 MB + before cleanup with 3.69 GB peak RSS; the load-immediate GREEN retained + approximately 117.3 MB with 3.68 GB peak RSS. The fresh W2 TOP elaboration + took approximately 649 seconds and produced an approximately 534 MB model + directory before cleanup. The second elaboration reused caches and completed + in 72 seconds; its single-thread Verilator build took 470.597 seconds and + the complete disposable directory occupied 494 MB. Internal ChiselSim + Verilator still uses `-j 0`, so internal job control remains open even though + all outer wrappers use one job. A temporary root-probe rebuild was stopped + when PCH invalidation attempted to recompile the large generated unit; the + probe was removed. +- The bounded W2 scalar IQ is now two entries total, one in each of the two + retained banks, instead of four. This preserves the canonical execution + topology, two load/two store pipes, 16-row rename/ROB forward-progress + floors, and all fixed identity widths. The parameter RED observed 4 != 2; + GREEN passes all 16 profile cases. A fresh RTL-only W2 emission reduced SV + from 63,896,864 to 55,722,033 bytes (12.8%) and from 198 to 194 files; its + one-row-bank dynamic-index warnings were eliminated with a static selector. + The completed pre-change natural build occupied 532 MB. A new full + Verilator model is deferred until the next execution fix is ready. +- Remaining gap: identify the post-LUI exact owner without rebuilding RTL for + diagnostics, continue W2 closure, then reach natural scalar AVS, Dhrystone, + and CoreMark with the required mismatch-free commit evidence. Width-matrix + and broader final gates follow only after W2 natural closure. +- Branch: `codex/chisel-gap-superpowers`. +- Commit and push: pending loop closure; no immutable benchmark-success + identity is claimed by this interim ledger entry. diff --git a/docs/chisel/microarchitecture-cross-stack-audit.md b/docs/chisel/microarchitecture-cross-stack-audit.md index 42122857..91f20821 100644 --- a/docs/chisel/microarchitecture-cross-stack-audit.md +++ b/docs/chisel/microarchitecture-cross-stack-audit.md @@ -1,6 +1,86 @@ # LinxCore Chisel Cross-Stack Audit -Date: 2026-07-23 +Date: 2026-07-30 + +## Production owner-graph re-audit + +This pass distinguishes three things that older status summaries sometimes +mixed together: a module existing in source, focused UT/IT evidence for that +module, and the module being the unique owner in the production elaboration +graph. The repository contains 435 main Chisel source files and 410 Chisel +test files across the backend, block-control, execute, frontend, LSU, OOO, +rename, ROB, recovery, system, and top packages. That breadth is substantial, +but file count is not production closure. + +The current top-level graph is: + +| Entry point | Hardware actually instantiated | Status | +| --- | --- | --- | +| `LinxCoreComposition` | `LinxCoreIfu`, `IfuLineMemoryBridge`, `D1InstructionDecodeStage`, and `IfuBackendFeedbackBridge` | Canonical production IFU boundary. Its IO explicitly leaves full rename/dispatch/issue outside the wrapper. | +| `LinxCoreTop` | `ReducedCommitROB`, canonical `ScalarLSU`, load-completion bridge, and scalar GPR sink | Bring-up shell, not a complete core. It has no production IFU-to-OOO-to-IEX graph. | +| `LinxCoreBenchmarkAutonomousTop` | canonical `LinxCoreComposition` plus `LinxCoreFrontendFetchRfAluTraceTop` and benchmark-only line-fill adapter | Workload-capable promotion harness. The IFU is production, while the backend is still a trace top containing reduced owners and benchmark memory/service seams. | + +Direct source evidence is in +[`LinxCoreComposition.scala`](../../chisel/src/main/scala/linxcore/top/LinxCoreComposition.scala), +[`LinxCoreTop.scala`](../../chisel/src/main/scala/linxcore/top/LinxCoreTop.scala), +and +[`LinxCoreBenchmarkAutonomousTop.scala`](../../chisel/src/main/scala/linxcore/top/LinxCoreBenchmarkAutonomousTop.scala). +The benchmark top selects `useProductionD1Ingress=true`, but also selects the +reduced store dispatch and STA bridge. Its live backend instantiates +`ReducedRobCompletionArbiter`, `ReducedScalarAluExecute`, +`ReducedScalarWritebackArbiter`, `ReducedServiceRequestPath`, reduced template +state, and reduced store/load replay owners. Those names describe real +production-graph residency, not merely stale documentation. + +### Ranked document-to-hardware gaps + +| Rank | Gap | Current evidence | Closure criterion | +| ---: | --- | --- | --- | +| 1 | No single production core top owns IFU -> OOO -> IEX -> LSU -> commit. | The canonical IFU and canonical ScalarLSU live in different top graphs; the workload graph joins production IFU to a reduced trace backend. | One named production top elaborates the complete owner graph and becomes the default workload/trace gate. | +| 2 | The parameterized OOO implementation is ahead of its production placement. | O0-O7 focused owners exist, including 2/4/6 ingress, grouped ROB/BROB/PC, P/T/U rename, dispatch/IEX residency, recovery, and OOO-side CTU lease/reinsertion. The benchmark still feeds `D1DecodedLaneQueue` into the legacy single-row `DecodeRenameROBPath`. | Complete O8 physical banking/timing, then replace the legacy benchmark backend with the OOO shell without a parallel shadow owner. | +| 3 | IEX production ownership is not unique. | The workload graph still uses `ReducedScalarAluExecute`, reduced completion/writeback arbitration, and a trace-top RF/issue fabric. System/CSR/trap/interrupt execution does not have a production owner in this graph. | One D3 -> IQ -> IEX -> W2 graph owns execution, RF readiness, ROB completion, and system side effects; reduced arbiters leave production elaboration. | +| 4 | LSU canonical islands are not yet the sole memory owner. | `ScalarLSU` contains canonical STQ/SCB/LIQ/L1D/recovery components, but the workload graph enables reduced STQ/STA, memory overlay, resident-forward, and replay state. Translation/protection, attributes, complete lower-memory/coherence, and several cross-line cases remain open. | Bind OOO/IEX load/store generation to canonical LSU identities, remove shadow state, then prove natural workload and recovery behavior through cache/MMU/lower-memory owners. | +| 5 | CTU has an OOO-side protocol but no production recipe engine/top connection. | `CTU` owns parent claim, lease, plan, ordered child reinsertion, and recovery prepare/apply. Current handoff explicitly leaves the external recipe engine and production-top wiring to O9. | A CTU outside IFU and OOO expands `FENTRY`/`FEXIT`/template parents, writes canonical children through the retained lease, and participates in the same recovery transaction. | +| 6 | Status documents have different freshness levels. | `integrated-development-flow.md`, `development-loop.md`, and the packet ledger describe O8/O9 accurately; the Chisel README previously still described OOO as O0/O1 with decode, fusion, RENU, and recovery wholly future work. | Keep the short README synchronized to the authoritative handoff and mark long historical ledgers as evidence history rather than current placement. | +| 7 | The workload top is too monolithic for easy owner auditing. | `LinxCoreFrontendFetchRfAluTraceTop.scala` is roughly 12.9k lines and combines execution, template, store, replay, recovery, diagnostics, and trace adapters. | Promote bounded production modules behind stable interfaces; keep trace tops as observers/wrappers rather than state owners. | + +### Fresh gate status + +The 2026-07-30 re-audit ran the three focused top-entry suites after a clean +`Test/compile`: + +| Gate | Result | Meaning | +| --- | --- | --- | +| `LinxCoreCompositionSpec` | 3/3 pass | The canonical IFU composition elaborates and preserves tagged line transport, B-F4 join, four-wide D1, backend validation, and canonical recovery. | +| `LinxCoreTopSpec` | 3/3 pass | The reduced commit-ROB plus canonical ScalarLSU shell elaborates. | +| `LinxCoreBenchmarkAutonomousTopSpec` | 15/15 pass | The workload top elaborates after the replay-LIQ bridge carries the canonical LIQ row lease and exact attempt into LRET, then preserves the data-or-fault result in the retained entry. | +| `LinxCoreFrontendFetchRfAluTraceTopSpec` | 44/44 pass | The full legacy live-top composition consumes the expanded LRET bundle without uninitialized fields. | +| historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 8d2985c2d7971383315212995e5f2ce6f0fb4863. | historical pass; 3 rows, 0 mismatches | At the cited source commit, emitted RTL compiled under Verilator and matched the bounded reference stream. | + +The immediate LRET elaboration regression is closed. The repair is deliberately +limited to migration safety: it preserves exact canonical identity through the +hybrid workload graph but does not make the reduced trace backend a production +owner. Natural frozen-ELF benchmark reruns remain a separate promotion gate. + +### Maturity assessment + +- **IFU: high module maturity, medium system maturity.** The canonical + I-SIDE/B-SIDE/Instruction-Buffer/D1 graph and real-workload evidence are + strong. Atomic four-lane handoff into the production OOO graph, SoC PTW/L1I + binding, complete predictor policy, and lower-memory error handling remain. +- **OOO: medium-high module maturity, medium integration maturity.** O0-O7 are + unusually complete at focused-owner level. O8 physical implementation and + O9 CTU/top/workload promotion are the decisive remaining steps. +- **IEX: medium module maturity, low-medium production-placement maturity.** + Useful issue/RF/pipeline components exist, but the workload owner is still + reduced and system execution is incomplete. +- **LSU: medium-high component maturity, medium-low unique-owner maturity.** + The canonical component set is broad and heavily tested; dual canonical and + reduced state paths are still the main architectural risk. +- **Whole core: medium-low current-head maturity.** Natural CoreMark/Dhrystone are meaningful + vertical evidence, but they currently validate a hybrid production/reduced + graph. The autonomous top now elaborates and its bounded generated-RTL gate + passes; neither result proves that the final production core top is closed. ## Scope and acceptance boundary diff --git a/docs/chisel/module-index.md b/docs/chisel/module-index.md index 8f411187..8f4e6e9b 100644 --- a/docs/chisel/module-index.md +++ b/docs/chisel/module-index.md @@ -33,9 +33,9 @@ when their source remains available for focused tests. | `IfuBackendFeedbackBridge` | `linxcore.frontend` | `docs/chisel/modules/frontend/IfuBackendFeedbackBridge.md` | post-B-F4 adapter for Dispatch direct/call and BRU SETC validation, atomic actual-result training plus exact-keyed BRU recovery, and typed GHR/RAS restore-and-apply | | `IfuLineMemoryBridge` | `linxcore.top` | `docs/chisel/modules/top/IfuLineMemoryBridge.md` | tagged 64-byte IFU memory adapter with multiple outstanding rows, stable request FIFO, out-of-order tag-plus-PA response matching, exact identity reconstruction, and retained refill backpressure | | `LinxCoreComposition` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreComposition.md` | Single frontend composition owner connecting canonical IFU, tagged line memory, fixed-width four-wide D1 full decode, and exact Dispatch/BRU feedback with canonical recovery | -| `OooPRename` | `linxcore.ooo` | `docs/chisel/modules/ooo/OooPRename.md` | Absolute-index P rename owner with 24-entry SMAP/CMAP per STID, generation-qualified PTag leases, parameterized physically subbanked ordered MapQ, exact bounded commit, and killed-tail/survivor-replay recovery | -| `OooTURename` | `linxcore.ooo` | `docs/chisel/interfaces/OooBundles.md` | O4.4.1 per-STID T/U sequential rename owner with independent namespaces, same-bundle relative-source bypass, exact provisional leases, wrap-qualified local mappings, and ROB-member-owned MapQ publication | -| `OooO3RenameCoordinator` | `linxcore.ooo` | `docs/chisel/modules/ooo/OooO3RenameCoordinator.md` | D3/S1 atomic seam joining ROB/BROB/PC, PTag/P/T/U rename, dispatch/IEX/fast-resolve, commit, and recovery; exposes independent live occupancy, absolute tail/generation/epoch, and monotonic transaction identity for verification | +| `PRename` | `linxcore.ooo` | `docs/chisel/modules/ooo/PRename.md` | Absolute-index P rename owner with 24-entry SMAP/CMAP per STID, generation-qualified PTag leases, parameterized physically subbanked ordered MapQ, exact bounded commit, and killed-tail/survivor-replay recovery | +| `TURename` | `linxcore.ooo` | `docs/chisel/interfaces/OooBundles.md` | O4.4.1 per-STID T/U sequential rename owner with independent namespaces, same-bundle relative-source bypass, exact provisional leases, wrap-qualified local mappings, and ROB-member-owned MapQ publication | +| `OOO` / `OOOD3S1Graph` | `linxcore.ooo` | `docs/chisel/modules/backend/OooDispatch.md` | Public D1-through-S1 owner graph joining RENU, ROB, BROB, dispatch, commit, and recovery on one D3 publication boundary; bounded four-STID integration covers publish and recovery | | `F4DecodeWindow` | `linxcore.frontend` | `docs/chisel/modules/frontend/F4DecodeWindow.md` | Verification-only 8-byte combinational slicer; excluded from architectural I-F4 | | `F4DenseSlotQueue` | `linxcore.frontend` | `docs/chisel/modules/frontend/F4DenseSlotQueue.md` | Verification-only serialized-slot fixture; excluded from the IFU graph | | `BfuBodyCutPredictor` | `linxcore.frontend` | `docs/chisel/modules/frontend/BfuBodyCutPredictor.md` | Verification-only predictor fixture; excluded from B-SIDE ownership | @@ -53,12 +53,6 @@ when their source remains available for focused tests. | `FrontendDecodeStage` | `linxcore.frontend` | `docs/chisel/modules/frontend/FrontendDecodeStage.md` | Verification packet-window wrapper reusing the shared fixed-width instruction decode leaf; it is not the D1 transport owner | | `FrontendRegAliasClassify` | `linxcore.frontend` | `docs/chisel/modules/frontend/FrontendRegAliasClassify.md` | Unit-green R43 scalar reg6 GPR/T/U alias classifier used by frontend operand decode | | `FrontendOperandDecode` | `linxcore.frontend` | `docs/chisel/modules/frontend/FrontendOperandDecode.md` | Scalar architectural operand/immediate field owner with model-derived GPR/T/U aliases, compact/macro overrides, PCR offsets, and D1-normalized 32/48-bit ADDTPC page displacements | -| `ReducedScalarAluExecute` | `linxcore.execute` | `docs/chisel/modules/execute/ReducedScalarAluExecute.md` | Unit-green R375 reduced scalar ADD/ADDI/SUBI/ADDTPC/MOVI/MOVR/CSEL/C.ADD/C.AND/C.SETRET plus model SrcR modifiers for register ADD/ADDW/SUB/AND/OR, compact extension rows, XORI, SSRSET, signed/unsigned SETC sidebands, target-priority FRET.STK load/redirect arbitration, single-save/ranged FENTRY, HL.LUI, shifts, C.LDI/LDI/LBUI/PCR read-only load lookup, PCR byte/half/word/doubleword stores, SDI/OP_SD/C.SDI/C.SWI/SBI store sidebands, P-only scalar source fields, GPR-only RF writeback side effects for T/U destinations, source-phys diagnostics, load replay BID/GID/RID sidecars, return signedness, one-destination replay sideband, RF-derived load source-trace lookup sideband, and W2 issue-queue release identity | -| `ScalarGPRFile` | `linxcore.execute` | `docs/chisel/modules/execute/ScalarGPRFile.md` | Canonical parameterized scalar P data/ready-table owner directly used by both live RF/issue tops, with request-versus-commit writes, independent-tag multiport completion, and explicit same-tag/collision checks | -| `ScalarGPRIssueWakeupProbe` | `linxcore.execute` | `docs/chisel/modules/execute/ScalarGPRFile.md` | Generated-RTL proof that request-only writes do not wake and committed P writeback updates RF/ready/IQ next state for next-cycle pick | -| `ScalarIssueCandidateArbiter` | `linxcore.execute` | `docs/chisel/modules/execute/ScalarIssueFabric.md` | Per-STID oldest candidate suppression plus advancing round-robin arbitration without cross-STID RID comparison | -| `ScalarIssueFabric` / `ScalarIssueFabricProbe` | `linxcore.execute` | `docs/chisel/modules/execute/ScalarIssueFabric.md` | Live parameterized scalar bank owner with least-occupied enqueue, bank-local candidate formation, atomic shared I1 grant/cancel, independent I2 arbitration, Linx control/store frontiers, and generated contention/retry proof | -| `ScalarIssueExternalControlFence` | `linxcore.execute` | `docs/chisel/modules/execute/ScalarIssueFabric.md` | Exact STID/BID/RID redirect frontier retained from FRET.STK W2 until accepted central recovery cleanup | | `OooIexIssue` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexIssue.md` | Canonical S1/S2/S3 IQ scheduling/payload, readiness, in-flight, parameterized exact release, duplicate-target rejection, and retained-recovery owner with disjoint per-class picker-domain projections | | `OooIexIssueBlockMatrix` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexIssueBlockMatrix.md` | Typed row/STID/domain early-block reasons for class pressure, LDQ/STQ windows, structural, latency, reflow, sidedoor, result-bus, power, and global policy | | `OooIexStageCancel` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexStageCancel.md` | Backpressurable exact I1/I2 late-cancel token using the shared pipe-local reason taxonomy and typed stale-request evidence | @@ -72,16 +66,12 @@ when their source remains available for focused tests. | `OooIexAluPipeline` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexAluPipeline.md` | Typed ALU E1 compute with generated-recipe whitelist, retained W1 bypass and W2 terminal ownership, GPR/T/U destinations, and exact recovery/load-cancel suppression | | `OooIexBruPipeline` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexBruPipeline.md` | Typed BRU E1 value/BCTRL compute with D1-normalized ADDTPC, generated-recipe whitelist, retained atomic E2 transaction, and exact recovery/load-cancel suppression | | `OooIexAguPipeline` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexAguPipeline.md` | Typed scalar-load AGU using D1-normalized memory controls, retained LSU request ownership, generated-recipe coverage, and exact recovery/load-cancel suppression | -| `OooIexLoadUnit` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexLoadUnit.md` | Parameterized exact load tracker with producer-qualified generations, speculative wakeup, hit bypass/result, miss cancel/new-generation retry, precise fault, and recovery suppression | | `OooIexTerminalPublish` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexTerminalPublish.md` | Fair ALU/BRU/load terminal arbiter with atomic multi-destination P/T/U write, committed wakeup, optional BCTRL, execution trace, and exact ROB completion | -| `OooIexIssueP1Lane` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexIssueP1Lane.md` | One-domain compatibility composition around one canonical IQ owner, exact bridge, and P1/I1/I2 lane | | `OooIexIssueP1Fabric` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexIssueP1Fabric.md` | Parameterized N-domain composition with one IQ owner, disjoint per-class bank projections, isolated ordinary/late retry, and aggregate quiescence | | `OooIexAtomicReadArbiter` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexAtomicReadArbiter.md` | Polynomial complete-group P/T/U/PC I1 RF allocation using total priority rank, greedy resource packing, cross-STID fairness, and exact response routing | | `OooIexOperandFiles` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexOperandFiles.md` | Canonical P data/ready owner wrapper with generation-qualified P identity, independent exact STID-local T/U sequence owners, valid-independent write preflight, and duplicate-target fail-closed mutation | | `OooIexIssueReadFabric` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexIssueReadFabric.md` | Direct canonical IQ-to-I2 composition using exact speculative-ready/load-cancel, bypass provenance, atomic multi-domain RF-needed reads, real P/T/U data owners, and exact repick | -| `OooRobStoreCommitOwner` | `linxcore.ooo` | `docs/chisel/modules/ooo/OooRobStoreCommitOwner.md` | Exact grouped-ROB memory-tail validator and atomic multi-enqueue store-beat owner participating in common architectural commit | -| `ReducedScalarIssuePick` | `linxcore.execute` | `docs/chisel/modules/execute/ReducedScalarIssuePick.md` | Bank-local P1/I1/I2 owner with oldest-per-STID candidate formation, cross-STID RR pick, explicit I1 grant, cancel, and retry | -| `ReducedScalarIssueQueue` | `linxcore.execute` | `docs/chisel/modules/execute/ReducedScalarIssueQueue.md` | Resident scalar issue bank with committed P wakeup, local T/U readiness, per-STID oldest-ready selection, inflight retention, exact release, and compaction | +| `CommitControl` | `linxcore.ooo` | `docs/chisel/modules/ooo/CommitControl.md` | Exact grouped-ROB memory-tail validator and atomic multi-enqueue store-beat owner participating in common architectural commit | | `DispatchROBAllocator` | `linxcore.backend` | `docs/chisel/modules/backend/DispatchROBAllocator.md` | R656 backend allocation bridge with ROB/BROB allocation, exact resident lookup, per-STID watermarks, canonical `BID_W` cleanup input, and separately qualified pointer diagnostics | | `BrobLiveBidResolver` | `linxcore.bctrl` | `docs/chisel/modules/bctrl/BrobLiveBidResolver.md` | R655 parameterized canonical BID slot resolver over one selected STID bounded live window, with explicit internal wrap pointer and mismatch diagnostics | | `BrobOrderState` | `linxcore.bctrl` | `docs/chisel/modules/bctrl/BrobOrderState.md` | R656 parameterized per-STID allocation tail, commit head, live count, width-enforced canonical-slot recovery, exact-head metadata lookup, and irrevocable fair ordered retirement | @@ -90,7 +80,6 @@ when their source remains available for focused tests. | `DecodeLoadStoreIdAssign` | `linxcore.backend` | `docs/chisel/modules/backend/DecodeLoadStoreIdAssign.md` | R653 per-STID all-row LSID snapshot plus independent load_id/sid advancement, exact-lane recovery, and generated multi-lane proof | | `DecodeRenameQueue` | `linxcore.backend` | `docs/chisel/modules/backend/DecodeRenameQueue.md` | Unit-green R44 registered raw decoded-uop queue between frontend decode and scalar rename | | `DecodeRenameROBPath` | `linxcore.backend` | `docs/chisel/modules/backend/DecodeRenameROBPath.md` | Backend composition with a direct fixed-width predecoded D1 input, optional verification packet adapter, atomic ROB/BROB allocation, rename/store/marker lifecycles, recovery cleanup, exact full-BID lookup, owner-selected per-STID watermarks, and the four-lane non-LSU producer bank | -| `ReducedRobCompletionArbiter` | `linxcore.backend` | `docs/chisel/modules/backend/ReducedRobCompletionArbiter.md` | R364 execute-priority ROB completion-port arbiter between ordinary execute completion and the dormant replay-W2 completion source | | `FullBidRecoveryBridge` | `linxcore.recovery` | `docs/chisel/modules/recovery/FullBidRecoveryBridge.md` | Unit-green recovery handoff from full block BID to ring ROBID pruning sidecar | | `RecoveryCleanupControl` | `linxcore.recovery` | `docs/chisel/modules/recovery/RecoveryCleanupControl.md` | R656 registered selected-request owner with retained cleanup intent, typed fanout, canonical `BID_W` block key, separate implementation pointer context, and raw-ring compatibility input | | `RecoveryNonLsuProducerBank` | `linxcore.recovery` | `docs/chisel/modules/recovery/RecoveryProducers.md` | R657 parameterized bank for independently retained BCC miss, IEX slow-insert, IEX IQ-stall, and PE mismatch sources, appended after stable external lanes | @@ -122,28 +111,25 @@ when their source remains available for focused tests. | `StoreDispatchToSTQ` | `linxcore.lsu` | `docs/chisel/modules/lsu/StoreDispatchToSTQ.md` | Unit-green R670 bridge carrying canonical full LSID plus the temporary recovery projection from executed store-dispatch heads into typed STQ requests | | `STQInsertProbe` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQInsertProbe.md` | Unit-green R670 read-only STQ insert readiness probe using full-LSID equality for split-half identity | | `StoreDispatchSTQPath` | `linxcore.lsu` | `docs/chisel/modules/lsu/StoreDispatchSTQPath.md` | Unit-green R267 queue-backed store dispatch to STQ composition with independent STA/STD readiness probes, T/U/PC sidecar-capable payloads, and forwarded LSU T/U source diagnostics | -| `ReducedStoreExecResultBridge` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedStoreExecResultBridge.md` | Unit-green R239 reduced-top adapter from ALU store completion sidebands to matched STA/STD execution-result inputs | -| `ReducedStoreCommitFreeOwner` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedStoreCommitFreeOwner.md` | R670 scalar STQ promotion owner using full-width LSID for early-safe and pending-store authorization while BID/GID/RID remain ROB-sized | | `STQFlushPrune` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQFlushPrune.md` | R671 typed STQ cleanup using STID scope, BID/group policy, authoritative full-LSID modular age, and conservative missing/ambiguous handling | | `STQEntryBank` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQEntryBank.md` | Unit-green R671 STQ state owner retaining full LSID for split identity and typed recovery while load-side projection remains temporary | | `STQCommitQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQCommitQueue.md` | Unit-green R748 exact logical-store frontier with scalar/pair completeness, same-STID ordering, peer bypass, and atomic beat issue | | `STQCommitDrain` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQCommitDrain.md` | Unit-green R748 retained one-to-four-fragment drain with exact row revalidation, per-row SCB free, and one-per-logical-store completion | -| `OooIexLoadLiqAllocAdapter` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexLoadLiqAllocAdapter.md` | Unit-green R759 three-AGU typed allocation bridge with exact attempt, parent PC, full LSID, and youngest-store boundary | +| `LoadIexIssuePipeline` | `linxcore.iex` | `docs/chisel/modules/execute/LoadIexIssuePipeline.md` | Canonical multi-lane load issue carrying IQ-retained transaction/initial attempt, full LSID, retained backpressure, and LSU-owned replay/rebind | +| `OooIexCanonicalLoadOwnership` | `linxcore.ooo` | `docs/chisel/modules/execute/OooIexCanonicalLoadOwnership.md` | Atomic LIQ/OOO ownership with launch-qualified speculative wakeup, exact replay/fault cancel, lane-qualified W1 bypass, terminal completion, and two-phase recovery without duplicate load residency | +| `OooIexLoadTerminalMetadata` | `linxcore.iex` | `docs/chisel/modules/execute/OooIexCanonicalLoadOwnership.md` | Metadata-only terminal owner that revalidates the IQ-allocated memory transaction and initial attempt, then tracks LSU-owned replay attempts through exact completion | | `STQRobCommitIngress` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQRobCommitIngress.md` | Exact semantic ROB-token matcher making physical STQ promotion and CommitQ enqueue one atomic edge without a slot sideband | | `STQMemoryAttributeOwner` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQMemoryAttributeOwner.md` | Exact translation/PMA sidecar keyed by physical lease generation, semantic owner, and logical beat; stale slot reuse and unknown/fault commit fail closed | | `STQCommittedStoreSerializer` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQCommittedStoreSerializer.md` | Single-outstanding committed NormalNonCacheable/DeviceMmio transport retaining scalar/pair fragments through exact terminal response | | `STQSCBCommitBackend` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQSCBCommitBackend.md` | External-row production backend joining exact ROB token resolution, typed classification, CommitQ, SCB/serializer drain, and terminal free without owning a second STQ | | `SCBCommitIngress` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBCommitIngress.md` | Unit-green R19 scalar SCB ingress owner; 64-byte line allocation, same-line merge, and byte-valid wakeup masks | -| `SCBCommitBridge` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBCommitBridge.md` | Unit-green R20 SCB capacity-feedback bridge; model batch gate and STQ free masks after accepted SCB admission | | `SCBEgressSelect` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBEgressSelect.md` | Unit-green R21 SCB valid-line egress selector; full-line priority and deterministic not-full fallback | | `SCBLookupControl` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBLookupControl.md` | Unit-green R22 SCB lookup outcome owner; writable-hit update/free and L2 write/upgrade request descriptors | | `SCBStateUpdate` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBStateUpdate.md` | Unit-green R23 SCB row-state transition owner; hit free, miss state, and response-driven `Miss -> Lookup` masks | | `SCBRowBank` | `linxcore.lsu` | `docs/chisel/modules/lsu/SCBRowBank.md` | Unit-green R670 registered SCB owner accepting full-LSID drain requests while line coalescing remains physical-address based | -| `ReducedStoreMemoryOverlay` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedStoreMemoryOverlay.md` | R670 reduced committed-memory image retaining full LSID request metadata without changing old-to-young byte merge order | | `STQSCBCommitPath` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQSCBCommitPath.md` | Unit-green cacheable/serialized committed-store composition; typed memory-class routing and exact SCB-or-terminal-response STQ release | -| `ScalarLSU` | `linxcore.lsu` | `docs/chisel/modules/lsu/ScalarLSU.md` | R676 canonical scalar LSU composition with full-LSID store/load/MDB resources, retained central recovery publication, retained miss/refill/cross-line owners, and SCB plus load lookup/update wiring into `ScalarL1D` | | `ScalarLSURecoverySource` | `linxcore.lsu` | `docs/chisel/modules/lsu/ScalarLSURecoverySource.md` | R640 oldest-eligible exact full-BID promotion boundary between retained MDB and central recovery arbitration | -| `ScalarLSULoadPath` | `linxcore.lsu` | `docs/chisel/modules/lsu/ScalarLSULoadPath.md` | R676 canonical load-path composition with LIQ/ResolveQ/MDB/LRET/W1/W2 ownership, retained R673 miss queue, R674 refill transport, R675 sequential cross-line assembly, and `ScalarL1D` as active-phase line-data owner | +| `ScalarLSULoadPath` | `linxcore.lsu` | `docs/chisel/modules/lsu/ScalarLSULoadPath.md` | I0.15c-b3c2 canonical load-path composition with LIQ/ResolveQ/MDB/LRET/W1/W2 ownership plus three retained production STQ query/response lanes, bounded exact-result credit, and compatibility-CAM-free production elaboration | | `ScalarLSULoadReturnPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/ScalarLSULoadReturnPipeline.md` | R672/R676 canonical parameterized scoped W1/W2 owner with full-LSID retention, exact ROB validation, typed recovery, same-cycle stage replacement, and atomic resolve/GPR-writeback/wakeup completion; upstream cache/miss/refill/cross-line sources are canonical while parallel cross-half launch remains staged | | `LoadMissQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadMissQueue.md` | R673 canonical cacheable scalar load miss owner with independent depth, launch-time worst-case reservation, FIFO first-miss requests, exact slot/generation/line responses, full Linx dependent identity, and issued-orphan preservation | | `LoadRefillTransport` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadRefillTransport.md` | R674 canonical dual-ingress scalar refill FIFO accepting exact miss responses and external refills with deterministic miss-then-external order, post-dequeue capacity, and typed-recovery data hold | @@ -160,11 +146,11 @@ when their source remains available for focused tests. | `MDBQueueFanout` | `linxcore.lsu` | `docs/chisel/modules/lsu/MDBQueueFanout.md` | R635 canonical MDB queue/fanout child; atomic LU/SU fanout, phase freeze on output backpressure, SU ready-store wakeup, recovery-cleared transient queues, persistent SSIT state, and quiescence output | | `LoadReplayMdbLookupWaitPlan` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadReplayMdbLookupWaitPlan.md` | R635 canonical MDB LU-hit to LIQ wait planner; matches exactly one scalar Wait/Repick row by `(BID, LSID)`, permits unresolved native store index/LSID, and holds fanout until native row mutation accepts | | `LoadStoreForwarding` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadStoreForwarding.md` | Unit-green R30 scalar store-to-load byte forwarding owner; nearest older store selection, ready-byte merge, and wait-store replay masks | -| `STQLoadForwardingPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQLoadForwardingPipeline.md` | I0.14 production three-pipe E1 tag snapshot/E3 physical-data query owner with per-byte nearest-older forwarding, unknown-address hard blocking, exact generation revalidation, and retained recovery-aware responses | +| `STQLoadForwardingPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQLoadForwardingPipeline.md` | I0.15c-b3a production three-pipe E1 tag snapshot/E3 physical-data query owner with exact canonical row/attempt/return-pipe identity, per-byte nearest-older forwarding, fail-closed validation, and retained recovery-aware responses | | `LoadSourceLineMerge` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md` | I0.15a byte-exact partial L1D/SCB source merger; SCB overrides only valid bytes while source-return evidence remains split | -| `STQLoadForwardResultPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md` | I0.15a direct canonical-STQ response consumer; normal and selected-wait results enter the common E3/E4 owner while structural uncertainty is retained on a separate hard-block boundary | +| `STQLoadForwardResultPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md` | I0.15c-b3c2 direct canonical-STQ response consumer; exact identity and split source evidence stay aligned through credit-controlled E3/E4 while structural uncertainty uses an independent retained hard-block boundary | +| `LoadForwardResultRetainer` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadForwardResultRetainer.md` | I0.15c-b3c1 bounded exact-result owner; retryable recovery/row-writer conflicts retain the FIFO head, while acceptance or permanent stale rejection drains it | | `ResidentStoreForwardStoreSnapshot` | `linxcore.lsu` | `docs/chisel/modules/lsu/ResidentStoreForwardStoreSnapshot.md` | Unit-green R283 reusable resident STQ row to `LoadStoreForwardStore` snapshot boundary, shared by ready resident forwarding and replay-LIQ E2 store-vector plumbing | -| `ReducedStoreResidentForward` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedStoreResidentForward.md` | Unit-green R283 reduced-top adapter from resident STQ rows to `LoadStoreForwarding`, now using the shared resident-store snapshot boundary for byte masks, line data, and BID/LSID/PC identity | | `ResidentStoreReplayWakeup` | `linxcore.lsu` | `docs/chisel/modules/lsu/ResidentStoreReplayWakeup.md` | Unit-green R268 producer-side bridge from resident wait-store identity to typed `LoadReplayWakeupRequest` diagnostics | | `LoadLookupArbiter` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadLookupArbiter.md` | Unit/top-green R296 execute-priority shared sparse-memory lookup selector for reduced execute loads and replay-LIQ base-data requests | | `LoadReplayLaunchReadiness` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadReplayLaunchReadiness.md` | Unit/top-green R300 replay-LIQ launch arm predicate and blocker diagnostics, now consuming `LoadReplaySourceReturnReadiness` and `LoadReplayReturnReadiness` while keeping live launch disabled until return-pipe availability is real | @@ -272,13 +258,8 @@ when their source remains available for focused tests. | `LoadReplayReturnPipeSelect` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadReplayReturnPipeSelect.md` | Unit/top-green R305 reduced replay-LIQ IEX return-pipe mask/select boundary that consumes `LoadReplayReturnPipePermit` and feeds `LoadReplayReturnReadiness` | | `LoadReplayReturnReadiness` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadReplayReturnReadiness.md` | Unit/top-green R305 reduced replay-LIQ return-pipe readiness owner that gates returned sources with `LoadReplayReturnPipeSelect` availability while the current top keeps LRET/mem-wakeup sinks low | | `LoadReplayBaseDataAlign` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadReplayBaseDataAlign.md` | Unit/top-green R295 scalar replay baseline data aligner that converts a 64-bit sparse-memory response into 64-byte `LoadForwardPipeline` line data and valid-mask diagnostics while launch remains disabled | -| `ReducedLoadWaitReplaySlot` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedLoadWaitReplaySlot.md` | Unit-green R375 registered reduced wait-store slot that holds the selected resident wait key after the live forwarder drops wait reporting, consumes the typed wakeup through `LoadReplayWakeup`, and publishes a diagnostic relaunch candidate with PC/address/size, return signedness, one destination, RF-derived source traces, BID/GID/RID/LSID identity, and forwarding snapshot | -| `ReducedLoadReplayRelaunchQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedLoadReplayRelaunchQueue.md` | Unit-green R375 finite relaunch-candidate queue that consumes one-cycle reduced wait-slot candidates, preserves full load identity plus destination, source traces, return signedness, and forwarding snapshot, and exposes pending/drop diagnostics before real LIQ relaunch wiring exists | -| `ReducedLoadReplayLiqAllocAdapter` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocAdapter.md` | Unit-green R375 combinational bridge from queued reduced replay candidates to `LoadInflightQueue` allocation payloads, preserving `loadLsId`, destination, source traces, return signedness, and the forwarding snapshot while consuming the queue head only on downstream allocation acceptance | -| `ReducedLoadReplayLiqAllocPath` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocPath.md` | Unit/top-green R669 replay LIQ composition with independently sized LIQ, ROB identity, and physical store-row domains; source-shaped mutation requests retain the full STQ row selector through the native mutation bridge | -| `ReducedLoadReplayCompletionDrain` | `linxcore.lsu` | `docs/chisel/modules/lsu/ReducedLoadReplayCompletionDrain.md` | Unit/live-green R275 diagnostic completion matcher that drains queued reduced replay candidates only when the same held load completes in W2 with matching PC/address/size plus BID/GID/RID/LSID while carrying the forwarding snapshot through the candidate port | | `LoadForwardPipeline` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadForwardPipeline.md` | Unit-green R418 registered E2/E3/E4 load-forwarding boundary; final byte-valid mask, wait-store replay, delayed load-data/SCB/STQ return sidebands, and E4 wakeup gating on all source bits plus return readiness | -| `LoadInflightQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadInflightQueue.md` | R672 canonical active-load owner with parameterized full LSID through allocation, residency, typed cleanup, LHQ publication, replay/refill, and native row mutation | +| `LoadInflightQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadInflightQueue.md` | I0.15c-b3c1 canonical active-load owner with exact external `{loadId,attempt,returnPipe}` E4 apply, permanent stale versus retryable owner-conflict classification, and compatibility-CAM-free production elaboration | | `LoadInflightRowMutationApply` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadInflightRowMutationApply.md` | Unit-green R412/R413 combinational LIQ row-image apply preview for future replay STQ response mutation; preserves row identity, consumes the native request shape now produced by `LoadInflightRowMutationRequestBridge`, and blocks invalid or non-`Repick` row writes before registered LIQ mutation is enabled | | `LoadInflightLaunchSelect` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadInflightLaunchSelect.md` | Unit-green R375 combinational LIQ relaunch selector that exposes WAIT/no-wait-store/data-hit/request-complete masks, selects the oldest scalar row by BID/load-LSID order, and republishes selected-row return signedness, destination, and source traces without driving top-level launch yet | | `LoadResolveQueue` | `linxcore.lsu` | `docs/chisel/modules/lsu/LoadResolveQueue.md` | R672 ResolveQ/LHQ owner with full-LSID precise cleanup and retirement plus full-identity MDB conflict export | @@ -299,16 +280,8 @@ when their source remains available for focused tests. | `BID` / `BROB` metadata | `linxcore.bctrl` | `docs/chisel/modules/bctrl/BROB.md` | Unit-green Packet C | | `BlockMarkerLifecycle` | `linxcore.bctrl` | `docs/chisel/modules/bctrl/BlockMarkerLifecycle.md` | Unit-green R174 reduced active marker/scalar-created block context owner with STID-indexed active state, marker readiness, retired marker-source readiness/fire, row-owned retired boundary BID install, malformed retired boundary backpressure, scalar-done source selection, same-slot pre-retire, scalar redirect STID cleanup, scalar-created block-start STID install, active-query STID diagnostics, and block-last BID-match closure across lanes | | `BlockMarkerRetireSourceSerializer` | `linxcore.bctrl` | `docs/chisel/modules/bctrl/BlockMarkerRetireSourceSerializer.md` | Unit-green R173 BCTRL marker retire-source queue integrated into `DecodeRenameROBPath` deallocation credit, recovery flush pruning, and `BlockMarkerLifecycle` readiness; compacts ROB marker sources in slot order and exposes one policy-free marker source at a time | -| `LinxCoreTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreTop.md` | R664 reduced commit shell with live canonical scalar-LRET RID validation and external-priority W2-to-ROB completion; full recovery remains staged | -| `ScalarLoadCompletionROBBridge` | `linxcore.top` | `docs/chisel/modules/top/ScalarLoadCompletionROBBridge.md` | R664 combinational owner for exact reduced-ROB lookup and external-priority atomic scalar W2 completion arbitration | -| `ScalarLoadGPRCompletionSink` | `linxcore.top` | `docs/chisel/modules/top/ScalarLoadGPRCompletionSink.md` | R665 physical GPR writeback/P-tag wakeup owner joining scalar W2 fire to canonical RF state with parameterized external-write bandwidth | | `LinxCoreFrontendTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendTraceTop.md` | Unit-green R80 frontend packet to commit-row generated-RTL xcheck with temporary completion surrogate | | `LinxCoreFrontendFetchTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendFetchTraceTop.md` | R94 fetch-source/window/decode/ROB generated-RTL fixture; does not implement I-F0–I-F4 or B-F0–B-F4 | -| `LinxCoreFrontendAluTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendAluTraceTop.md` | Unit-green R81 frontend packet to ALU-produced completion-row generated-RTL xcheck | -| `LinxCoreFrontendRfAluTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendRfAluTraceTop.md` | Live RF/ALU path with canonical GPR ownership, parameterized scalar issue banks, atomic shared I1 grant/cancel, independent I2 arbitration, dependent rows, and generated-RTL comparison | -| `LinxCoreFrontendFetchRfAluTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md` | Unit/top-green through R470 live fetch-source to RF-backed queued ALU completion-row generated-RTL xcheck with model-sized 128-entry GGPR capacity, 7-bit physical tags, binary or sparse ELF fetch-memory bytes, sparse-ELF load lookup, committed store mutation for reduced store sidebands, external/QEMU-trace/live-QEMU-ELF-derived expected rows, dense 8-byte response windows through `F4DenseSlotQueue`, row-derived RF preloads and SP shadow, BSTART/BSTOP skip rows, marker-stop and conditional/direct marker redirects with backend active-context clear, scalar-created active block tracking, reduced store-dispatch bypass, expanded scalar/local ALU/store/SETC subset, reduced replay ResolveQ diagnostics plus delayed LIQ clear, commit-watermark retire feedback, execute scalar-redirect precise-prune wiring, replay-LIQ selected launch-row identity/request-mask/return-signedness/destination/source-trace diagnostics, replay-LIQ base-data align, source-return readiness with live-disabled local STQ snapshot evidence/readiness and external-SCB pending/returned request owners, return-pipe readiness boundary, launch-readiness, dormant return-data/LRET-payload/source-trace/writeback-candidate/wakeup-candidate diagnostics, LRET FIFO capacity now feeding upstream readiness while publish fire and drain remain disabled, live-disabled replay writeback and wakeup sink readiness diagnostics plus a pre-W2 side-effect live-control mask owner replacing raw side-effect-ready tie-offs, IEX setMemData/ROB-resolve/lane-completion/pipe-insert diagnostics with reduced scalar shape ownership, live-disabled E4 pipe-residency request control, dormant replay-W2 ROB completion source plus execute-priority completion arbiter, W2 slot source-trace diagnostics feeding dormant W2 replay load commit-row trace-source and row candidate with ROB-fed instruction metadata while ROB-row source traces remain disabled, dormant W2 row-fill enable control, dormant W2 replay-row lifecycle guard, dormant W2 replay-row clear-request selector, dormant W2 replay-row lifecycle commit permit, dormant W2 clear/commit identity guard, launch/E4/LHQ-valid diagnostics, replay-LIQ MDB conflict diagnostics from accepted STQ insert plus active/ResolveQ load snapshots, replay-LIQ MDB fanout/SSIT/BMDB diagnostics from selected conflict records, dormant replay-LIQ MDB lookup command diagnostics, surfaced dormant MDB delete/decay boundary diagnostics, live-top MDB lookup wait-plan diagnostics from fanout LU/SU outputs plus current LIQ rows with wrapper-validated sidecar bridge counters and opt-in nonzero counter requirements but without enabling row mutation, and a live-disabled IEX return-pipe occupancy request owner feeding the forced-full occupancy path and LRET drain permit with generated-RTL replay zero-mismatch through R391 | -| `LinxCoreFrontendFetchRfAluMarkerRowsTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md` | R180 filtered QEMU comparator mode emits the marker-row wrapper, admits the first CoreMark marker row into ROB, validates and filters its marker commit, and compares the following scalar rows with zero mismatches; default live CoreMark top remains in marker-skip mode | -| `LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop` | `linxcore.top` | `docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md` | Unit-green R445 opt-in reduced-store wrapper that selects `ReducedLoadReplayLiqAllocPath` as the replay queue consumer, exposes LIQ allocation/residency plus launch-selector, selected-row identity/request-mask/return-signedness/destination/source-trace diagnostics, base-data align, source-return readiness with local STQ snapshot evidence/readiness and external-SCB pending/returned diagnostics, split STQ/store versus SCB source-return E2 sidebands, return-pipe readiness, dormant return-data extraction, LRET-payload subset with destination, GPR writeback-candidate diagnostics, live-disabled replay RF writeback sink diagnostics, ready-table/issue-wakeup candidate diagnostics, live-disabled wakeup-sink readiness diagnostics, pre-W2 side-effect live-control masks, publish-ready diagnostics, LRET FIFO capacity readiness, live-disabled IEX return-pipe occupancy request and forced-full occupancy, dormant IEX drain/setMemData/ROB-resolve/lane-completion/pipe-insert diagnostics with reduced scalar shape ownership, live-disabled E4 pipe-residency request control, launch-readiness, launch/E4/LHQ-valid diagnostics, wires resident STQ snapshots and shaped baseline line data into the replay E2 boundary, appends path-local LHQ hit records into `LoadResolveQueue`, clears the source LIQ row after accepted insertion, retires ResolveQ rows from ROB commit LSID watermarks, drives queue-local precise flush from execute scalar-redirect LSID sidecars, feeds MDB conflict diagnostics from accepted STQ insert plus active/ResolveQ load snapshots, records selected conflicts into MDB fanout/SSIT diagnostics, wires dormant MDB lookup commands from replay-LIQ launch acceptance, enables guarded source row mutation through the reduced LIQ bridge after live-permit/head-proof plus native write-control checks, surfaces dormant MDB delete/decay boundary diagnostics, and keeps relaunch disabled because live publish, wakeup, writeback, FIFO drain, pipe residency, raw external STQ response, and replay-row lifecycle mutation remain inactive | | QEMU cross-check adapter | tooling | `docs/chisel/verification/qemu-crosscheck.md` | Adapter self-test green; generated-RTL compares emit `crosscheck_manifest.json`; metadata-aware QEMU trace replay bridge and R141 finite-window length handling added; bounded CoreMark ELF prefix replay passes with explicit QEMU memory; full compare awaits real frontend/backend rows | | Integrated development flow | coordination | `docs/chisel/integrated-development-flow.md` | Short launch surface for packet ownership, harness boundaries, tiered gates, first-divergence ownership, and compiler/QEMU/Chisel/LinxCoreModel/superproject promotion | | Agent development loop | coordination | `docs/chisel/agent-loop.md` | ROB/cross-check-first module loop and skill-evolve closeout runbook | diff --git a/docs/chisel/modules/backend/DecodeLoadStoreIdAssign.md b/docs/chisel/modules/backend/DecodeLoadStoreIdAssign.md index 8a9000d7..d4438502 100644 --- a/docs/chisel/modules/backend/DecodeLoadStoreIdAssign.md +++ b/docs/chisel/modules/backend/DecodeLoadStoreIdAssign.md @@ -142,6 +142,6 @@ bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath bash tools/chisel/run_chisel_tests.sh --only DecodeRenameQueue bash tools/chisel/run_chisel_tests.sh --only FrontendDecodeStage bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run ``` diff --git a/docs/chisel/modules/backend/DecodeRenameROBPath.md b/docs/chisel/modules/backend/DecodeRenameROBPath.md index b6472bc0..8fa8e5fe 100644 --- a/docs/chisel/modules/backend/DecodeRenameROBPath.md +++ b/docs/chisel/modules/backend/DecodeRenameROBPath.md @@ -281,7 +281,7 @@ This closes the elaboration-only gap for marker-row admission; it still leaves marker-aware QEMU/DUT comparison and the default live-top switch to later packets. R180 extends the generated-RTL QEMU comparator with an explicit marker-row -mode. `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --marker-rows` +mode. historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --marker-rows` Provenance: source commit 742c3c991d1c9a48e92001d58d4704b3ebead754. emits the marker-row wrapper, asks the shared driver to admit legal marker rows, validates their ROB commits as marker-shaped rows, and filters those validated marker commits before scalar QEMU comparison. The first CoreMark @@ -933,6 +933,9 @@ and strong non-flush authorization remain separate. Focused gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only BlockMarkerLifecycle bash tools/chisel/run_chisel_tests.sh --only BlockMarkerDecodeContextSpec @@ -957,6 +960,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-di bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r173-marker-retire-source-flush-prune-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r192-marker-row-brob-retire-drain-128-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 128 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf ``` +Provenance: source commit e4d8f6bae895a562afb4f254660ffe6be8174b9d, source commit 4fdfdc4d431f4d660d0bfab605842c67b073b35d, source commit 34a3f8a684716189bf26c2e36508b5f2e65c0de8, source commit b8b94fa82e4f67d3c322b71fd92ccd11b4b36786, source commit bbc05af27289fb29f17402bc0d82512f08f52a46. + Affected gates: @@ -971,7 +976,7 @@ bash tools/chisel/run_chisel_tests.sh --only GPRRenameCheckpoint bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendTraceTop bash tools/chisel/run_chisel_frontend_trace_top_lint.sh bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run ``` diff --git a/docs/chisel/modules/backend/OooDispatch.md b/docs/chisel/modules/backend/OooDispatch.md index 15bb7ac6..5f1ff988 100644 --- a/docs/chisel/modules/backend/OooDispatch.md +++ b/docs/chisel/modules/backend/OooDispatch.md @@ -13,9 +13,9 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooDispatch.scala` - `chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala` - `chisel/src/main/scala/linxcore/ooo/OooParams.scala` -- `chisel/src/test/scala/linxcore/ooo/OooDispatchSpec.scala` +- `chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooHierarchicalFreeSlotSelectSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` The behavioral reference is `tools/LinxCoreModel/model/iex/iex_dispatch.cpp::DispatchUnit::dispatch`. The @@ -82,10 +82,9 @@ generation update are unchanged. ```bash bash tools/chisel/run_chisel_tests.sh --only OooHierarchicalFreeSlotSelect -bash tools/chisel/run_chisel_tests.sh --only OooDispatch +bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles -bash tools/chisel/run_chisel_tests.sh --only OooO3IexIntegration -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec ``` The selector UT covers empty, first/last, cross-leaf, one-entry-leaf, and diff --git a/docs/chisel/modules/backend/ReducedRobCompletionArbiter.md b/docs/chisel/modules/backend/ReducedRobCompletionArbiter.md deleted file mode 100644 index 850ff082..00000000 --- a/docs/chisel/modules/backend/ReducedRobCompletionArbiter.md +++ /dev/null @@ -1,94 +0,0 @@ -# ReducedRobCompletionArbiter - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/backend/ReducedRobCompletionArbiter.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/backend/ReducedRobCompletionArbiterSpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/iex/pipe/lda_pipe.cpp`: `LDAPipe::runW2` - - `model/LinxCoreModel/model/iex/pipe/agu_pipe.cpp`: `AGUPipe::runW2` - - `model/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp`: `SimInstInfo::GenRslvBus` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/backend/DecodeRenameROBPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayReturnPipeW2RobCompleteSource.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/rob/ROBEntryBank.scala` -- Contract IDs: `LC-CHISEL-BACKEND-ROB-COMPLETE-ARBITER-001` - -## Purpose - -`ReducedRobCompletionArbiter` owns the reduced top's single ROB completion-port -choice before `DecodeRenameROBPath`. Before R364, the top wired execute -completion directly into the backend path. R364 adds a replay-W2 completion -source, so completion-port selection is now explicit and testable. - -Execute keeps priority. Replay completion is selected only when execute has no -completion in the same cycle. - -## Interface - -| Direction | Signal | Description | -|---|---|---| -| input | `executeCompleteValid` | Ordinary execute completion candidate. | -| input | `executeCompleteRobValue` | Execute RID value. | -| input | `executeCompleteRowValid` / `executeCompleteRow` | Execute completion row replacement payload. | -| input | `replayCompleteValid` | Replay-W2 ROB completion candidate. | -| input | `replayCompleteRobValue` | Replay RID value. | -| input | `replayCompleteRowValid` / `replayCompleteRow` | Replay row replacement payload; currently false/zero from R364 source. | -| output | `completeValid` | Selected completion-port valid. | -| output | `completeRobValue` | Selected completion RID. | -| output | `completeRowValid` / `completeRow` | Selected row replacement payload. | -| output | `selectedExecute` / `selectedReplay` | Source selection diagnostics. | -| output | `replayBlockedByExecute` | Replay was present but execute owned the port. | - -## Logic Design - -```text -selectedExecute = executeCompleteValid -selectedReplay = replayCompleteValid && !executeCompleteValid -completeValid = selectedExecute || selectedReplay -``` - -All selected fields follow the chosen source. When neither source is selected, -`completeRobValue` is zero, `completeRowValid` is false, and `completeRow` is -zero. - -This arbiter does not decide whether replay W2 may fire. The LSU -`LoadReplayReturnPipeW2RobCompleteSource` publishes structural port readiness -to the resolve sink before a future replay side-effect request can reach this -arbiter. - -## Integration - -`LinxCoreFrontendFetchRfAluTraceTop` wires: - -- execute side from `ReducedScalarAluExecute.complete*`; -- replay side from `LoadReplayReturnPipeW2RobCompleteSource.complete*`; -- selected output to `DecodeRenameROBPath.complete*`; -- diagnostics under `robCompleteArbiter*`. - -`DecodeRenameROBPath` still arbitrates marker-internal completion after this -top-level source choice. A selected execute or replay completion has priority -over marker completion in the path, preserving the existing execute-first -behavior and adding replay as the next external completion source. - -## Deferred Owners - -- Replay completion row replacement with full load commit trace sidebands. -- Multi-source ROB completion scaling beyond one execute and one replay source. -- Live replay completion enable; R363 still keeps replay W2 side effects - dormant through the atomic live-request gate. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedRobCompletionArbiter -bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RobCompleteSource -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r364-replay-w2-rob-complete-source-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh -``` - -Reference tests cover execute priority, replay selection while execute is idle, -idle-output suppression, and Chisel elaboration. diff --git a/docs/chisel/modules/bctrl/BlockMarkerDecodeContext.md b/docs/chisel/modules/bctrl/BlockMarkerDecodeContext.md index 8d08f174..9e2ed0af 100644 --- a/docs/chisel/modules/bctrl/BlockMarkerDecodeContext.md +++ b/docs/chisel/modules/bctrl/BlockMarkerDecodeContext.md @@ -123,7 +123,7 @@ The integration split is: - `bash tools/chisel/run_chisel_tests.sh --only BlockMarkerLifecycleSpec` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPathSpec` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTopSpec` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r176-marker-decode-context-prep-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r176-marker-decode-context-prep-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 6d84e2191a19259fa6fef8ffe92884debdc4f02e. R176 tests cover scalar seeding, boundary replacement of an active BID, stop reuse and clear, STID isolation, flush/redirect/ROB block-last cleanup, malformed diff --git a/docs/chisel/modules/bctrl/BlockMarkerLifecycle.md b/docs/chisel/modules/bctrl/BlockMarkerLifecycle.md index a3cc68f3..43b2a321 100644 --- a/docs/chisel/modules/bctrl/BlockMarkerLifecycle.md +++ b/docs/chisel/modules/bctrl/BlockMarkerLifecycle.md @@ -190,9 +190,9 @@ still instantiates one lane. - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` - `bash tools/chisel/run_chisel_tests.sh --only BlockMarkerLifecycleSpec` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPathSpec` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r168-block-marker-lifecycle-smoke --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 30 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r172-retired-marker-lifecycle-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r192-marker-row-brob-retire-drain-128-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 128 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r168-block-marker-lifecycle-smoke --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 30 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 43a750265cc579217dfc2d90d449e497331af3d7. +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r172-retired-marker-lifecycle-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 34a3f8a684716189bf26c2e36508b5f2e65c0de8. +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r192-marker-row-brob-retire-drain-128-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 128 --allow-block-markers --allow-block-loop-reentry --marker-rows --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit bbc05af27289fb29f17402bc0d82512f08f52a46. The R172 focused test adds retired-boundary and malformed-boundary reference cases. The live CoreMark gate captured 6000 QEMU rows, normalized 5138 QEMU/DUT diff --git a/docs/chisel/modules/bctrl/BlockMarkerRetireSourceSerializer.md b/docs/chisel/modules/bctrl/BlockMarkerRetireSourceSerializer.md index 2eb255e2..065193da 100644 --- a/docs/chisel/modules/bctrl/BlockMarkerRetireSourceSerializer.md +++ b/docs/chisel/modules/bctrl/BlockMarkerRetireSourceSerializer.md @@ -109,8 +109,8 @@ does not discard older already-retained marker evidence. - `bash tools/chisel/run_chisel_tests.sh --only BlockMarkerRetireSourceSerializer` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r172-retired-marker-lifecycle-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r173-marker-retire-source-flush-prune-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r172-retired-marker-lifecycle-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit 34a3f8a684716189bf26c2e36508b5f2e65c0de8. +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r173-marker-retire-source-flush-prune-6000-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 6000 --allow-block-markers --allow-block-loop-reentry --max-seconds 16 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` Provenance: source commit b8b94fa82e4f67d3c322b71fd92ccd11b4b36786. Focused tests cover slot-order compaction, full-window admission backpressure, flush suffix pruning, base-on-BID inclusive pruning, clear/drop behavior, and diff --git a/docs/chisel/modules/execute/LoadIexIssuePipeline.md b/docs/chisel/modules/execute/LoadIexIssuePipeline.md new file mode 100644 index 00000000..eb9be4cd --- /dev/null +++ b/docs/chisel/modules/execute/LoadIexIssuePipeline.md @@ -0,0 +1,74 @@ +# LoadIexIssuePipeline + +## Purpose + +`LoadIexIssuePipeline` is the non-resident issue boundary between the selected +load-address lanes and the canonical LSU Load Inflight Queue. `OooIexIssue` +has already allocated the memory transaction and initial attempt when it +retained the load in IQ. This pipeline copies those identities exactly. LSU +becomes the sole LIQ residency owner on the common allocation fire and owns +every later replay, repick, and attempt rebind. + +Source and tests: + +- `chisel/src/main/scala/linxcore/iex/LoadIexIssuePipeline.scala` +- `chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala` + +## Contract + +The pipeline fairly arbitrates `laneCount` retained +`OooIexAguLoadRequest` inputs into the current one-wide LIQ allocation port. +W4 derives `laneCount=2` from the two load-address pipes. Other legal test +configurations may choose a different positive lane count only when the LSU +return-pipe count covers every selected lane. + +One accepted issue maps: + +- the complete producer `RobMemberKey` into `LoadAttemptIdentity`; +- one wrap-qualified IEX memory-transaction value and generation which remain + unchanged across every LSU replay/rebind; +- one non-rewinding initial attempt generation; +- full LSID and exact youngest-older-store LSID from OOO memory order; +- ROB/BROB projections plus PE/STID scope; +- parent PC, effective address, access size/sign, and GPR destination; +- the displaced physical GPR mapping required by the load return contract; +- the selected address lane into one LSU return-pipe identity. + +`LoadAttemptIdentity.requireBridgeFits` proves at elaboration that the complete +OOO identity, full LSID, PC, architectural tag, and physical tag fit the LSU +payload. A malformed issue is rejected rather than truncated or consumed. + +## Backpressure and recovery + +The pipeline owns no request queue or identity serial. An AGU lane retains its +request while the LIQ allocation port is blocked. The candidate allocation and +accepted sideband remain derived from the same selected request; `alloc.fire` +copies the already retained initial attempt without advancing IEX identity. + +Recovery Prepare fences the affected STID without mutation. Apply drains an +exact killed visible request and prunes matching retained metadata through the +common recovery transaction; Abort preserves it. The serial owner is upstream +of this bridge and never rewinds, so an old return cannot alias a later load. + +## Verification + +```bash +bash tools/chisel/run_chisel_tests.sh --only LoadIexIssuePipelineSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexCanonicalLoadOwnershipSpec +bash tools/chisel/run_chisel_tests.sh --only OooMemoryOrderAllocatorSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexAguPipelineSpec +``` + +The directed suite covers W4 two-lane derivation, unequal LIQ/ROB/STQ +capacities, 40-bit full LSID, exact field mapping, retained backpressure, +fair multi-lane admission, selected return-pipe identity, displaced PTag, +missing-PC rejection, recovery Apply/Abort, peer-STID survival, and generation +continuity. + +## Remaining boundary + +Task 15 connects this mechanism through the public IEX and LSU boxes. That +cutover must preserve the single transaction/initial-attempt owner in +`OooIexIssue` and +the single replay/rebind owner in LSU; it may not reintroduce an adapter or a +second LIQ residency table. diff --git a/docs/chisel/modules/execute/OooIexAguPipeline.md b/docs/chisel/modules/execute/OooIexAguPipeline.md index 0c8fe862..7ff909d3 100644 --- a/docs/chisel/modules/execute/OooIexAguPipeline.md +++ b/docs/chisel/modules/execute/OooIexAguPipeline.md @@ -86,8 +86,8 @@ and malformed memory/class rejection. ## Remaining gaps -- live connection through `OooIexLoadLiqAllocAdapter` into canonical LIQ - allocation/launch (the typed allocation ABI is implemented); +- public IEX/LSU connection through `LoadIexIssuePipeline` into canonical LIQ + allocation/launch; W4 keeps two load-address lanes and two load pipes; - load hit/miss return, size extraction, sign/zero extension, bypass, and speculative/committed wakeup; - miss cancellation, replay, poison, and exact repick; diff --git a/docs/chisel/modules/execute/OooIexAtomicReadArbiter.md b/docs/chisel/modules/execute/OooIexAtomicReadArbiter.md index 4538697b..9e84f18f 100644 --- a/docs/chisel/modules/execute/OooIexAtomicReadArbiter.md +++ b/docs/chisel/modules/execute/OooIexAtomicReadArbiter.md @@ -32,7 +32,7 @@ those ranks once. At each rank it accepts the complete group only when its P/T/U/PC demand fits the remaining independent resources. This polynomial greedy selection is exactly the lexicographic optimum: preserve the oldest request, then add every lower-priority complete group that still fits. It -scales to the formal fourteen-picker issue profile without a `2^N` elaboration +scales to the parameter-derived issue profile without a `2^N` elaboration network. Priority is wrap-qualified `{ridGeneration,ridSlot,memberIndex}` age within one STID, then advancing STID round-robin order across STIDs. It never partially grants a uop. @@ -55,15 +55,15 @@ The focused UT covers an older three-P-source group excluding a younger two-source peer from three ports, cross-STID round-robin turnover, mixed P/T/U/PC mapping, complete response routing, a missing T response, and a malformed operand class, and a mixed logical source group whose bypassed P -source is absent from the RF mask. A second case presents fourteen same-STID -pickers to six P ports and proves that the six oldest complete groups win. +source is absent from the RF mask. A larger case proves the oldest complete +groups win when requests exceed available P ports. ## Remaining gaps - Connect the exposed PC requests to `OooPcBuffer` in the canonical top. - Connect physical LSU resolve producers to the lane/IQ exact cancel path; the arbiter itself remains outside replay-state ownership. -- Synthesize and place the rank/greedy hierarchy at fourteen pickers; add a +- Synthesize and place the rank/greedy hierarchy at the canonical topology; add a registered arbitration boundary only if measured timing requires it. `OooIexIssueReadFabric` now connects P/T/U requests to the exact operand owners diff --git a/docs/chisel/modules/execute/OooIexCanonicalLoadOwnership.md b/docs/chisel/modules/execute/OooIexCanonicalLoadOwnership.md new file mode 100644 index 00000000..4007c763 --- /dev/null +++ b/docs/chisel/modules/execute/OooIexCanonicalLoadOwnership.md @@ -0,0 +1,109 @@ +# OooIexCanonicalLoadOwnership + +## Purpose + +`OooIexCanonicalLoadOwnership` is the canonical ownership boundary between +the parameterized OOO AGU load lanes and the canonical scalar LSU. W4 uses two +lanes. It composes the non-resident `LoadIexIssuePipeline` with the metadata-only +`OooIexLoadTerminalMetadata` sidecar without adding a second address, miss, +replay, refill, or result queue. + +Source and test owners: + +- `chisel/src/main/scala/linxcore/ooo/OooIexCanonicalLoadOwnership.scala` +- `chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala` +- `chisel/src/main/scala/linxcore/iex/OooIexLoadTerminalMetadata.scala` +- `chisel/src/test/scala/linxcore/iex/OooIexLoadTerminalMetadataSpec.scala` + +Linx canonical LIQ row leases, complete `LoadAttemptIdentity`, full LSID, +grouped-ROB member identity, and P/T/U destinations define the contract. + +## Atomic allocation + +The configured AGU inputs are fairly serialized by +`LoadIexIssuePipeline`. One accepted transaction simultaneously: + +- allocates the canonical LIQ row exposed on `liqAlloc`; +- captures the exact LIQ slot-plus-wrap lease from `liqAllocLoadId`; +- installs `{loadId, attempt, OooIexLoadGeneration, AGU request}` in the OOO + terminal metadata sidecar. + +Neither half can fire alone. Backpressure from the LIQ or a still-live terminal +sidecar propagates to the originating AGU. The ownership wrapper retains no +load request payload; the AGU remains the producer until the common fire and +the LIQ becomes the lifecycle owner afterward. + +## Replay and terminal ownership + +An OOO replay-policy rebind is also an all-or-none transaction. The wrapper +projects the canonical row lease back to the LIQ `ROBID` shape and requires the +LIQ and OOO sidecar to accept the same current-to-next attempt transition. +Skipped generations, stale leases, producer mismatch, and terminal races fail +closed in the two canonical owners. + +The scalar LSU reports an accepted physical attempt through +`attemptLaunch={loadId,attempt}`. Only an exact resident sidecar match emits a +`SpeculativeLoad` wakeup, on the original AGU lane, with the complete P/T/U +destination and `OooIexLoadGeneration`. Allocation itself never wakes a +consumer. An accepted rebind cancels the old generation on that lane; the next +exact launch wakes the new generation. + +Canonical `ScalarLSULoadReturnEntry` completion is accepted only when its full +row lease, attempt, producer, destination, and data/fault outcome match the +sidecar. W2 backpressure retains that metadata until the same `result.fire` +releases the canonical completion and sidecar. Fault results require zero data; +ordinary data results carry no fault. +An ordinary retained result also publishes lane-qualified W1 bypass. A fault +publishes no bypass and emits its exact cancel only on terminal fire. If a +fault and an unrelated rebind target the same physical load lane in one cycle, +fault cancel wins and the rebind is held for the next cycle; neither cancel is +merged or dropped. + +## Recovery + +Recovery Prepare, Apply, and Abort are separate phases of the common typed +transaction: + +- Prepare fences only the affected STID and does not consume an AGU producer; +- the metadata owner validates and retains the exact plan before reporting + `prepared`; +- matching Apply prunes the exact terminal sidecars and drains only visible + killed requests; +- matching Abort preserves both the sidecars and visible requests. + +Surviving AGU requests remain held and can proceed after the recovery fence is +removed. There is no second hard-flush protocol at this boundary. + +## Verification + +```bash +bash tools/chisel/run_chisel_tests.sh --only OooIexCanonicalLoadOwnershipSpec +bash tools/chisel/run_chisel_tests.sh --only LoadIexIssuePipelineSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexLoadTerminalMetadataSpec +``` + +The IT uses unequal `LIQ=4`, `ROB=8`, `STQ=4`, and `LSID=40` geometry. It +covers parameterized allocation including the W4 two-lane profile, +LIQ/sidecar atomicity, exact slot-wrap identity, +terminal backpressure, ordinary data, precise fault, atomic rebind, stale +completion rejection, exact launch wakeup, replay/fault cancellation, same-lane +cancel serialization, W1 bypass, common recovery fencing/kill, and generated +SystemVerilog structure. The emitted graph contains the non-resident issue +pipeline and terminal metadata owner and contains no migration tracker. + +## Remaining integration gaps + +Task 13 removed the combined execution/store shell. Task 15 must connect the +`OooIexIssue` identity owner, this atomic wrapper, its non-resident +`LoadIexIssuePipeline`, the existing `ScalarLSU` children, and the +canonical STQ directly through the public IEX/LSU interfaces without +introducing another load-lifecycle owner or another combined private shell. Small +default OOO profiles cap default LIQ population to the available ROB identity +domain rather than widening or truncating native BID projection. Remaining +work is to: + +- extend the local LIQ recovery kill-equivalence proof to + MissQ/ResolveQ/LRET and the final global recovery authority; +- attempt-qualify every asynchronous cache/refill return, then add physical + DTLB/PMP/PMA/L1D/coherence/device and cross-line handling; +- close synthesis timing and natural Dhrystone/CoreMark workloads. diff --git a/docs/chisel/modules/execute/OooIexE1TransferFabric.md b/docs/chisel/modules/execute/OooIexE1TransferFabric.md index 31c9f96d..6d584575 100644 --- a/docs/chisel/modules/execute/OooIexE1TransferFabric.md +++ b/docs/chisel/modules/execute/OooIexE1TransferFabric.md @@ -13,7 +13,7 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexPhysicalProfile.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexE1TransferFabricSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexIssueE1IntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` ## Static topology @@ -34,18 +34,16 @@ physical class/bank. The validated matrix directly drives `pickBankEnables`, each retained slot's accepted class/bank/capability projection, and release-port ownership. Canonical IQ storage is never copied. -[`OooIexPhysicalProfile`](OooIexPhysicalProfile.md) freezes the first complete -profile: six ALU, three AGU, two BRU, and one external FSU residency owner, -expanded into fourteen picker/execution lanes. AGU0/1 each expose an LDA and -STA picker; AGU2 exposes LDA only. STD shares ALU0/3 residency, SYS shares -ALU2/5, and FSU/CMD share the external FSU owner. Boundary rows remain -fast-resolved and own no IQ bank. +[`OooIexPhysicalProfile`](OooIexPhysicalProfile.md) derives the canonical +topology from `CoreParams`: two ALU owners, two AGU owners with independent LDA +and STA pickers, one BRU owner, one system/multicycle owner, one CMD owner, and +one floating/vector owner. The two ALU owners also admit the two STD paths. +Boundary rows remain fast-resolved and own no IQ bank. -`OooIexLinxE1TransferFabric` is the production specialization. It accepts one -formal profile and derives every transfer slot, capability predicate, bank -projection, and release owner from that profile. Paired with -`OooIexLinxIssueReadFabric`, neither half can silently substitute an ad-hoc -picker topology. +`OooIexLinxE1TransferFabric` accepts one formal profile and derives every +transfer slot, capability predicate, bank projection, and release owner from +that profile. Paired with `OooIexIssueReadFabric`, neither half can silently +substitute an ad-hoc picker topology. ## Transfer and release arbitration @@ -54,12 +52,11 @@ round-robin arbiter is instantiated per `iexReleaseWidth` port. Pickers mapped to the same port serialize fairly and a loser retains its complete I2 transaction without issuing an early release. Pickers mapped to different ports may transfer on the same edge. For every winner, `i2.fire`, exact issue -release, IQ row removal, dispatch-slot return, and E1 capture remain one -ownership transaction. +release, IQ row removal, and E1 capture remain one ownership transaction. -The IQ and dispatch owners independently reject duplicate physical targets -across valid release lanes. Thus a bad static/dynamic composition cannot -double-free a row even when release throughput is widened. +The IQ owner rejects duplicate physical targets across valid release lanes. +Thus a bad static/dynamic composition cannot double-remove a row even when +release throughput is widened. ## Canonical in-flight authority @@ -74,7 +71,7 @@ second issued-state owner. ```bash bash tools/chisel/run_chisel_tests.sh --only OooIexE1TransferFabricSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueE1IntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` The fabric UT proves static ALU/BRU mapping, multi-class ALU/STD admission, @@ -82,17 +79,17 @@ simultaneous capability-disjoint AGU LDA/STA transfer, wrong-bank rejection, unsafe overlap/release-port rejection, fair same-port serialization, retained loser ownership, independent E1 backpressure, and simultaneous ALU/BRU transfer on distinct ports. The -integration test connects the real canonical IQ/read fabric to this transfer -fabric using the same static domain declarations and proves both rows can -reach E1 on one edge exactly when both IQ rows and dispatch reservations are -returned. The formal-profile UT elaborates the production specialization. +mechanism test connects the real canonical IQ/read fabric to this transfer +fabric using the same static domain declarations and proves parallel and +denied paths preserve exact ownership. The formal-profile UT elaborates the +parameter-derived specialization. ## Remaining gaps - `OooIexPipeline` now owns the canonical issue/read-to-E1 composition; direct fabric instantiation remains a focused-test surface. -- connect shared DIV/PAC/SYS busy/latency state to issue policy and exact - stage-cancel; same-cycle ALU2/ALU5 arbitration is owned before RF read; +- connect shared multicycle/PAC/system busy and latency state to issue policy + and exact stage-cancel; - connect picker-specific E1 outputs to typed execution units; - connect retained recovery apply and physical load-cancel producers in the canonical top; diff --git a/docs/chisel/modules/execute/OooIexExecutionPipeline.md b/docs/chisel/modules/execute/OooIexExecutionPipeline.md index 280a7bee..38a870cf 100644 --- a/docs/chisel/modules/execute/OooIexExecutionPipeline.md +++ b/docs/chisel/modules/execute/OooIexExecutionPipeline.md @@ -2,8 +2,8 @@ ## Purpose -`OooIexExecutionPipeline` is the production static composition from the OOO -S1 publication boundary through physical IQ residency, P1/I1/I2 operand +`OooIexExecutionPipeline` is the private canonical composition from classed +OOO dispatch through physical IQ residency, P1/I1/I2 operand acquisition, retained E1 ownership, typed scalar execution, W1 bypass, and atomic terminal publication. @@ -20,12 +20,10 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexExecutionCluster.scala` - `chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala` - `chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala` -- `chisel/src/main/scala/linxcore/ooo/OooIexExecutionStorePipeline.scala` - `chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexExecutionClusterSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexExecutionStoreIntegrationSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala` ## Static execution topology @@ -43,19 +41,18 @@ expand to fourteen capability-disjoint picker/execution lanes: | BRU0 / BRU1 | branch/control | | FSU0 | floating/vector or engine command | -Six simple ALU pipes, two BRU pipes, three load-address AGUs, and three scalar -load trackers are internal. Store address, store data, multicycle ALU, system, +Six simple ALU pipes, two BRU pipes, three load-address AGUs, and one canonical +three-lane load ownership bridge are internal. Store address, store data, +multicycle ALU, system, pointer authentication, floating/vector, and engine-command transactions are explicit retained outputs. An unimplemented family is therefore backpressured at its E1 owner; it is never silently consumed by an ALU fallback. When `requireStoreReservation` is enabled, every split store also emits an -exact reservation request while retained in S1. Its S2 publication is blocked -until canonical STQ allocation fires. `OooIexStoreStqFabric` is the production -owner for that request and for the two STA/two STD retained outputs. -`OooIexExecutionStorePipeline` is now the production boundary that makes all -of those connections private; the lower-level execution pipeline retains its -ports only for focused unit composition. +exact reservation request before its canonical IQ publication. The surviving +execution wrapper leaves the typed reservation and STA/STD boundaries private +for the Task-15 public composition; it does not recreate the removed legacy +execution/store shell. Every route requires one generated recipe capability, the expected IQ class, and the exact physical owner lane. Zero/multiple capabilities, wrong class, @@ -85,18 +82,16 @@ repick without modifying non-speculative RF readiness. ## Recovery and quiescence -One held `OooResidencyRecoveryPlan` is prepared by the canonical issue owner -and the canonical STQ/store owner. The production wrapper publishes ready only -when both projections are ready. One common `recoveryFire` then applies that -same plan to issue/read/E1, internal execution, retained STA/STD, and exact -WAIT-state STQ rows on one edge. Recovery prepare fences STQ reservation, -fill, commit-mark, and free mutation. A recovery pivot that would retain only -one child of a split store is rejected even after the children have left IQ -residency. +One canonical `RecoveryPlan` is retained independently by the issue/E1 owner +and execution cluster. The wrapper publishes prepared only after both owners +echo the complete transaction. Apply and Abort are forwarded only after an +exact full-transaction match; malformed Apply cannot mutate I1/I2/E1 or later +execution residency. Recovery preparation and a prepared transaction both +keep `empty` deasserted. `empty` is true only when both the issue/read/E1 pipeline and the execution cluster are empty. It does not treat an empty IQ as backend quiescence while a -W1/W2/load-tracker or retained external transaction still owns work. +W1/W2/load-metadata or retained external transaction still owns work. ## Reference alignment @@ -124,7 +119,8 @@ bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabric The terminal UT covers dual publication, independent cluster backpressure, and fire-qualified round-robin advancement. The cluster UT covers every explicit external family, malformed capability rejection, concurrent ALU W1 bypass, -and two-lane W2 publication. The production-top structural IT elaborates all +two-lane W2 publication, and one complete E1/AGU/canonical-allocation/launch/ +load-terminal transaction. The production-top structural IT elaborates all eight classes, eight banks, fourteen picker/E1 lanes, two terminal lanes, and the canonical STQ/store fabric. The adjacent dynamic IT drives the formal STA and STD execution lanes and proves that both halves fill one pre-reserved STQ @@ -142,8 +138,8 @@ graph; O8/O9 must close that structural compile cost. - Implement internal multicycle ALU/divide, system, pointer-authentication, floating/vector, and engine-command owners instead of leaving retained integration boundaries. -- Connect the three scalar-load memory ports to the canonical TLB/L1D/LIQ - adapter, including sidedoor/reissue and physical arbitration loss. +- Connect sidedoor/reissue and physical memory arbitration-loss policy around + the now-installed scalar load port. - Replace cluster-local terminal modulo assignment only if synthesis shows a materially better fixed port map; do not introduce a global all-to-all result crossbar without measured timing evidence. diff --git a/docs/chisel/modules/execute/OooIexExecutionStorePipeline.md b/docs/chisel/modules/execute/OooIexExecutionStorePipeline.md deleted file mode 100644 index 71800bd9..00000000 --- a/docs/chisel/modules/execute/OooIexExecutionStorePipeline.md +++ /dev/null @@ -1,90 +0,0 @@ -# OooIexExecutionStorePipeline - -## Purpose - -`OooIexExecutionStorePipeline` is the canonical production boundary that -composes the formal fourteen-lane scalar/control execution pipeline with the -generation-qualified STQ/store fabric and committed-store backend. Store -reservation, two STA lanes, two STD lanes, load cancellation, exact ROB commit -resolution, CommitQ insertion, SCB/serialized drain, terminal free, and store -recovery are private connections. There is no pre-STQ address/data join owner -and no external physical-index commit authority. - -The lower-level `OooIexExecutionPipeline` and `OooIexStoreStqFabric` remain -independently testable. `OooO3IexStorePipeline` is the canonical upper owner; -it instantiates this wrapper and closes O3 completion, recycle, recovery, -PC-read, fast-result, and semantic store-commit connections. - -## Store transaction ownership - -Every split store remains resident in issue S1 until its complete one- or -two-row STQ reservation fires. S2 cannot publish the physical children without -the lease. Formal execution lanes then transfer STA and STD independently into -retained store owners. Each owner looks up the existing STQ lease using full -ROB/BROB/member, LSID/store-ID, beat, and lease-generation identity; execution -cannot allocate a row by CAM. - -The canonical STQ row is the only convergence owner. A fill conflict, stale -lease, duplicate match, or identity mismatch keeps the transaction retained -and reports a typed diagnostic. - -After translation/PMA classifies the exact physical lease, the grouped ROB -supplies a semantic `STQRobCommitToken` without an STQ index. The backend -rediscovers one converged row, promotes it to COMMIT, and inserts its CommitQ -token atomically. Cacheable accepted last fragments and the final exact -serialized response are the only physical-row free sources. - -## Common recovery - -The wrapper sends one held recovery plan to both execution/IQ residency and -the STQ/store fabric. It publishes `recoveryPrepareReady` and -`recoveryPrepared.valid` only when both owners have accepted an exact, -side-effect-free projection. While prepare is held, STQ reservation, execute -acceptance, fill, commit-mark, and free mutation are fenced. - -`recoveryFire` is converted into one private common fire. On that edge: - -- IQ/read/E1 and internal execution owners apply their killed set; -- retained STA/STD owners cancel matching work; -- only exact killed `WAIT` STQ rows are freed; -- no physical lease generation is rewound. - -A committed row, malformed owner, or pivot that retains only one physical -child of a split store rejects the entire common transaction. No owner mutates -independently. - -## Verification - -```bash -bash tools/chisel/build_chisel.sh -bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionPipeline -bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionStoreIntegration -bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabric -bash tools/chisel/run_chisel_tests.sh --only OooIexStorePipeline -bash tools/chisel/run_chisel_tests.sh --only OooStqReservationProjection -bash tools/chisel/run_chisel_tests.sh --only OooStqRecoveryProjection -bash tools/chisel/run_chisel_tests.sh --only STQEntryBank -``` - -The structural gate elaborates the full fourteen-lane wrapper. A focused -recovery-join UT proves that a single prepared owner cannot fire, both owners -must rendezvous, and execution rejection has priority over the synthesized -store rejection. The adjacent dynamic IT pre-reserves a scalar store, drives -its STA through `agu0-sta` and its STD through `alu0` in the same cycle, and -proves that the expected address and data appear in the same canonical STQ -row. The extended IT classifies that lease, commits it without a physical-index -sideband, observes CommitQ and SCB admission, and proves terminal row release. -Focused fabric UT additionally proves prepare fencing, no pre-fire mutation, -common-fire application, split-store partial-cut rejection, and retained -serialized terminal free across recovery prepare. - -## Remaining gaps - -- Replace the typed test PMA producer with the physical translation/PMP/PMA - result path and connect the uncached/device response fabric. -- Add the physical store-data bank, forwarding/overlap checks, load violation - replay, and serial-wrap quiescence. -- Add Device loads, atomics/fences, L1D/coherence, and precise fault - publication. -- Close default-width generated-graph cost, synthesis timing, sustained - two-STA/two-STD pressure, O9 top promotion, CoreMark, and Dhrystone. diff --git a/docs/chisel/modules/execute/OooIexIssue.md b/docs/chisel/modules/execute/OooIexIssue.md index f2d8fffe..3284bad8 100644 --- a/docs/chisel/modules/execute/OooIexIssue.md +++ b/docs/chisel/modules/execute/OooIexIssue.md @@ -13,16 +13,15 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooBundles.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexRecoverySpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` The first downstream read-stage packet is documented separately in [`OooIexP1I2Lane`](OooIexP1I2Lane.md). It consumes a selected joined row but does not take ownership of the physical IQ entry. Oldest-ready selection and canonical speculative ownership are documented in [`OooIexOldestReadyPicker`](OooIexOldestReadyPicker.md). -The exact selected-payload join and executable one-/multi-domain compositions are -documented in [`OooIexPickP1Bridge`](OooIexPickP1Bridge.md) and -[`OooIexIssueP1Lane`](OooIexIssueP1Lane.md), plus +The exact selected-payload join and multi-domain composition are documented in +[`OooIexPickP1Bridge`](OooIexPickP1Bridge.md) and [`OooIexIssueP1Fabric`](OooIexIssueP1Fabric.md). The first class-specific terminal handoff is documented in [`OooIexE1TransferSlot`](OooIexE1TransferSlot.md). @@ -64,7 +63,9 @@ retry acceptance, or query pickability. A capability-mismatched row remains resident and not in flight; it is never silently redirected to an incompatible pipe. -The scheduling row contains exact PE/STID/epoch/transaction, canonical +The scheduling row contains exact PE/STID/epoch/dispatch transaction, +the IEX memory transaction and initial load attempt allocated on the canonical +Dispatch-to-IQ acceptance edge, canonical speculative `inFlight`, and `RobMemberKey`, the class/bank/write-port/entry/reservation generation, and generation-qualified P/T/U source/destination tags. The payload sidecar keeps @@ -77,8 +78,9 @@ adding those wide controls to the wakeup/recovery scan row. I0.9g adds the logical uop's full memory-order allocation beside those controls. S1 accepts a memory transaction only when its exact per-STID lease identity joined the O3 publication; S2 copies the logical range into every physical child sidecar. -STA and STD therefore share the same logical store range without treating an -IQ slot or future STQ row as the full SID/LSID authority. +STA and STD therefore share the same logical store range and IEX memory +transaction without treating an IQ slot or future STQ row as the full +SID/LSID authority. Recovery never rewinds either IEX serial. I0.15c-a also retains each GPR destination's displaced physical mapping in the wide sidecar. The compact scheduling row still carries only the current PTag; @@ -145,7 +147,7 @@ oldest-ready selection, so AGU LDA and STA pickers can observe one residency owner without ever claiming the same row. The canonical `inFlight` update is still the final same-cycle collision guard. Retry is accepted only by the picker whose projection and capability currently cover the reservation. -Domain-zero aliases preserve the focused one-lane interface. +The parameter-derived profile supplies every canonical domain projection. Release is fail-closed. It requires an in-flight row, the exact member, and complete dispatch reservation, including class-local entry, write port, and @@ -158,44 +160,38 @@ chooses a winner for an ambiguous double-free request. ## Recovery -The owner consumes a compact `OooResidencyRecoveryPlan` projected from the -complete grouped-ROB plan. Prepare captures the immutable request, validates -retained S1 immediately, then scans one parameterized entry slice from every -physical class/bank per cycle. The default +The owner consumes the canonical `RecoveryPlan` directly; there is no private +IEX recovery projection. Prepare accepts only a legal suffix-window plan, +retains the exact typed transaction, and then scans one parameterized entry +slice from every physical class/bank per cycle. The default `iexRecoveryScanEntriesPerBankPerCycle=1` takes `iqEntriesPerBank` scan cycles; larger power-of-two divisors trade read/CAM width for latency. Capture plus scan exposes prepared-ready after `iexRecoveryScanCycles + 1` cycles. The scan is side-effect free. It overwrites every stored row-kill bit during a -complete pass and accumulates exact `BoundS2`/`ResidentS3` counts, pending-S3 -lane membership, and generation-qualified P/T/U ready-scoreboard kill masks. -Changing the offered plan while it is retained or finding a malformed live -row rejects the request. Deasserting prepare before `Prepared` aborts only the -scan metadata. Neither case mutates S1/S2/S3 or readiness state. - -P-ready is a global scoreboard, so a numerical PTag can be recycled and -rewritten by a peer while recovery is retained. Capture snapshots the complete -`{valid,generation,stid,epoch}` owner identity used by the scan. Common apply -clears a retained P-ready mask bit only when the live identity still equals -that snapshot; a new generation/STID/epoch survives unchanged. +complete pass by testing each resident schedule row with +`RecoveryPlanContract.suffixMember`. Changing the transaction during a retained +recovery cannot substitute a different plan: `Prepared` returns the retained +plan, while Apply and Abort must match it under +`sameTransactionIgnoringPhase`. Neither Prepare nor scanning mutates IQ +residency. P/T/U data and readiness remain exclusively owned by +`OooIexOperandFiles` and are not shadowed or cleared here. Prepare freezes target-STID admission, transition, release, and wakeup while unrelated STIDs continue. After every slice validates, the owner holds the -prepared result and its exact masks until the global common apply. Apply -prunes killed lanes from retained S1 and pending S3, frees exact killed -`BoundS2` and `ResidentS3` rows, and clears matching P/T/U readiness records. -A surviving partial pivot remains resident and pickable. Because wakeup is a -non-backpressured `Valid` input, target-STID wakeup during prepare is an -assertion failure rather than a silently dropped readiness event; global R0-R4 -must quiesce those producers before prepare. +prepared result and its exact row mask until the global common decision. An +exact Apply frees only suffix-member IQ rows; an exact Abort preserves all +rows. Surviving prefix rows remain resident and pickable. A mismatched Apply or +Abort is rejected by assertion rather than being interpreted as a new recovery +transaction. ## Remaining gaps -- The formal 12-owner/14-picker residency/capability profile, runtime - capability admission, and dual AGU LDA/STA pickers are implemented. Shared - DIV/PAC/SYS arbitration remains open; broad dispatch class alone remains - insufficient. +- The parameter-derived residency/capability profile, runtime capability + admission, and dual AGU LDA/STA pickers are implemented. Busy/latency + feedback from multicycle/PAC/system owners remains open; broad dispatch class + alone remains insufficient. - Canonical-top wiring for the implemented P/T/U RF owners, shared read-port arbitration, speculative-ready, exact bypass, and load-cancel paths; physical result/wakeup/LSU-resolve producers remain open. @@ -212,10 +208,8 @@ must quiesce those producers before prepare. unbounded dispatch slot encoder is closed by O8.2's bounded hierarchy. - Per-class multi-pick liveness counters and coverage closure. -The legacy `ReducedScalarIssue*` modules remain compatibility evidence until a -later IEX packet replaces their top-level consumers. `OooIexP1I2Lane` now -replaces their read-stage semantics for the canonical path. They are not used -as the semantic authority for this module. +Old `ReducedScalarIssue*` evidence is not part of this canonical path and must +be removed with the old top chain before final cutover. ## Verification @@ -223,13 +217,11 @@ as the semantic authority for this module. bash tools/chisel/run_chisel_tests.sh --only OooIexIssue bash tools/chisel/run_chisel_tests.sh --only OooIexOldestReadyPicker bash tools/chisel/run_chisel_tests.sh --only OooIexPickP1Bridge -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1Lane bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1Fabric bash tools/chisel/run_chisel_tests.sh --only OooIexE1TransferFabric -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueE1Integration +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec bash tools/chisel/run_chisel_tests.sh --only OooIexRecovery -bash tools/chisel/run_chisel_tests.sh --only OooO3IexIntegration -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec ``` The focused UT covers retained-stage timing, fair STID arbitration, target @@ -282,17 +274,14 @@ The same 2-bank x 4-entry main IEX owner is now 176,457 lines, a bounded 1.6% increase over the 173,709-line recovery-scan baseline. The picker has no payload-memory reference. -I0.3 adds an explicit 913-line token-to-payload join. In the focused 2-bank × -4-entry composition, `OooIexIssueP1Lane` is 8,244 lines and contains separate -158,376-line IQ, 913-line bridge, and 2,992-line P1/I1/I2 lane modules. The -bridge RTL has no `payloadRows` or `scheduleRows` storage reference; it only -checks the readyless joined row supplied by the IQ owner. +I0.3 adds an explicit token-to-payload join. The bridge RTL has no +`payloadRows` or `scheduleRows` storage reference; it only checks the readyless +joined row supplied by the IQ owner. In the directly comparable first IEX stage test, the main owner is now 176,764 lines, 307 lines above I0.2 and 1.8% above the 173,709-line bounded-recovery baseline. -I0.4's focused two-domain composition is 12,129 SystemVerilog lines around one -163,798-line `OooIexIssue`, two 913-line bridges, and two 2,992-line lanes. -The fabric contains exactly one `OooIexIssue` instance and no schedule/payload -storage reference. These are structural elaboration counts, not timing or area -claims. +The current fabric contains exactly one `OooIexIssue` instance and no second +schedule/payload storage owner. `IEXMechanismSpec` proves matching main/bounded +W2/W4/W6/W8 topology and dynamically elaborates the bounded W4/W2 mechanisms; +full-capacity generated RTL remains a dedicated closure gate. diff --git a/docs/chisel/modules/execute/OooIexIssueBlockMatrix.md b/docs/chisel/modules/execute/OooIexIssueBlockMatrix.md index 75b8e231..fdf93885 100644 --- a/docs/chisel/modules/execute/OooIexIssueBlockMatrix.md +++ b/docs/chisel/modules/execute/OooIexIssueBlockMatrix.md @@ -66,9 +66,7 @@ resident row again. - `bash tools/chisel/run_chisel_tests.sh --only OooIexIssueBlockMatrixSpec` - exact integration case: `OooIexIssueSpec` test containing `policy blocks a resident row` -- `bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1FabricSpec` -- `bash tools/chisel/run_chisel_tests.sh --only OooIexIssueReadFabricSpec` -- `bash tools/chisel/run_chisel_tests.sh --only OooIexIssueE1IntegrationSpec` +- `bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec` - `bash tools/chisel/build_chisel.sh` The UT covers load/store qualification, accumulated shared and private @@ -81,7 +79,7 @@ normal pick. - concrete LSU LDQ/STQ-window and sidedoor producers in the canonical static top; - concrete busy/latency/reflow/result-bus producers for every typed execution - pipe; same-cycle DIV/PAC/SYS sharing between ALU2/ALU5 is already resolved - before RF read, while later conflicts use exact I1/I2 stage-cancel and repick; + pipe; shared multicycle/PAC/system conflicts are resolved before RF read, + while later conflicts use exact I1/I2 stage-cancel and repick; - liveness counters and safe-mode peer suppression; - measured workload validation of the static ALU/AGU/STD/BRU mapping. diff --git a/docs/chisel/modules/execute/OooIexIssueP1Fabric.md b/docs/chisel/modules/execute/OooIexIssueP1Fabric.md index a0a92a10..c7774477 100644 --- a/docs/chisel/modules/execute/OooIexIssueP1Fabric.md +++ b/docs/chisel/modules/execute/OooIexIssueP1Fabric.md @@ -11,7 +11,7 @@ IQ scheduling row, ready scoreboard, or payload sidecar owner. Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexIssueP1FabricSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` ## Topology contract @@ -26,8 +26,7 @@ Each domain has its own retained oldest-ready token, sidecar join, retry merge, atomic read attempt/decision, source/PC responses, and I2 output. Recovery apply is shared because it is one architectural event, but each private I1/I2 lane evaluates exact member membership independently. Dispatch publication, -wakeup state, terminal IQ release, and PTag recycling remain single-owner -interfaces. +wakeup state, and terminal IQ release remain single-owner interfaces. Each domain also exposes two backpressurable resource-cancel inputs, one for I1 and one for I2. The private lane proves the exact stage/member/reservation @@ -38,38 +37,31 @@ ready-to-valid combinational loop. `lanesEmpty` reports private P1/I1/I2 and retained retry residency. `empty` additionally -requires no retained S1 row, no BoundS2/ResidentS3 IQ row, and no retained +requires no BoundS2/ResidentS3 IQ row and no retained recovery scan. It is the fabric quiescence signal; queue-empty or lane-empty alone is insufficient. -The default parameter remains one domain so existing focused modules and tests -use domain-zero aliases. `OooIexIssueP1Lane` explicitly requires that default; -multi-domain integrations instantiate this fabric. +The domain count is derived from `CoreParams` through +`OooIexPhysicalProfile.fromCoreParams`; the canonical W4 topology contains the +two ALU paths, two LDA and two STA pickers, one BRU path, one +system/multicycle path, one floating/vector path, and one CMD path. ## Verification ```bash -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1FabricSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` -The two-domain IT installs ALU and PC-reading BRU children together, observes -simultaneous I1 attempts, grants ALU while denying BRU, and proves only the BRU -row returns to pickable state. It then repicks/grants BRU, drains both I2 lanes, -releases both canonical IQ rows, and checks aggregate `empty`. The same DUT is -then reused with two ALU domains on disjoint banks to prove that legal -same-class partition. A negative test configures overlapping ALU/bank -projections and requires the topology assertion to fire. - -For the focused 2-bank × 4-entry geometry, generated RTL contains one -`OooIexIssue`, two `OooIexPickP1Bridge`, and two `OooIexP1I2Lane` instances. -The 12,129-line fabric has no schedule/payload storage reference; the single -multi-port IQ owner is 163,798 lines. These are structure counts, not physical -area or timing claims. +The mechanism suite compares the main and bounded W2/W4/W6/W8 topology, +dynamically elaborates the bounded W4 fabric, proves parallel ALU claims and +isolation of a denied path, and exercises exact retry through the real read fabric. +Focused child suites retain malformed-topology, +stage-cancel, and recovery coverage. ## Remaining gaps -- Instantiate the formal 14-picker specialization in the canonical top; the - static class/bank/capability contract is now enforced at elaboration. +- Instantiate the parameter-derived picker topology in the canonical top; the + static class/bank/capability contract is enforced at elaboration. - Connect class-specific physical resource owners to early policy and exact I1/I2 stage-cancel inputs. - Compose the implemented operand-read fabric with `OooPcBuffer` at the diff --git a/docs/chisel/modules/execute/OooIexIssueP1Lane.md b/docs/chisel/modules/execute/OooIexIssueP1Lane.md deleted file mode 100644 index 066ca9fe..00000000 --- a/docs/chisel/modules/execute/OooIexIssueP1Lane.md +++ /dev/null @@ -1,48 +0,0 @@ -# OooIexIssueP1Lane - -## Purpose - -`OooIexIssueP1Lane` is the first executable canonical IQ-to-I2 composition. It -instantiates one `OooIexIssue`, one `OooIexPickP1Bridge`, and one -`OooIexP1I2Lane` for a topology-neutral class/bank picker domain. -It is the domain-zero compatibility composition and requires -`iexIssueDomainCount=1`; parameterized parallel issue uses -[`OooIexIssueP1Fabric`](OooIexIssueP1Fabric.md). - -Source and test owners: - -- `chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Lane.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexIssueP1LaneSpec.scala` - -## Transaction flow - -1. S3 scheduling state selects and retains an exact oldest-ready token. -2. The bridge uses its class/bank/entry to read and prove the canonical joined - row. -3. P1 accepts the generated PC controls and complete row; the IQ sets only its - canonical `inFlight` bit. -4. I1 requests every P/T/U source and optional PC token atomically. -5. Denial or invalid response returns the exact member/reservation to the IQ; - the row becomes pickable again. A complete grant retains all data at I2. - -The lane cannot accept a replacement P1 on a denial/invalid-response edge. -Malformed bridge joins wait for lane capacity. The composition asserts that -bridge and lane retry outputs never collide, then merges them into the IQ's -single exact retry input. - -The IQ's exact retained recovery apply is forwarded to the lane. Target I1/I2 -residency is canceled on the same common apply as target IQ rows; peer STIDs -remain independent. - -## Verification - -```bash -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1LaneSpec -``` - -The IT publishes one PC-reading BRU row through real S1/S2/S3, observes the -generated parent token at I1, denies the read, proves exact retry clears -`inFlight`, observes the same row repick, then grants the PC read and checks the -retained I2 result. For its focused 2-bank × 4-entry geometry, the composition -is 8,244 SystemVerilog lines around separate 158,376-line IQ, 913-line bridge, -and 2,992-line lane modules. These are structure counts, not area/timing claims. diff --git a/docs/chisel/modules/execute/OooIexIssueReadFabric.md b/docs/chisel/modules/execute/OooIexIssueReadFabric.md index bea20fec..418924a8 100644 --- a/docs/chisel/modules/execute/OooIexIssueReadFabric.md +++ b/docs/chisel/modules/execute/OooIexIssueReadFabric.md @@ -9,7 +9,7 @@ decisions and operand values. Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexIssueReadFabricSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` ## Composition contract @@ -28,23 +28,20 @@ in-flight, and retry owner. Every picker contributes one complete retained I1 attempt after exact W1/W2/W3 bypass selection. It also exports that row's one-hot recipe capability independently from the compact RF request bundle. -Production callers use `OooIexLinxIssueReadFabric`. This specialization derives -the picker count, class/bank projections, capabilities, release geometry, and -shared-resource participants from one `OooIexPhysicalProfile`. The base module -still accepts dynamic `pickBankEnables` for focused harnesses, but when -`staticDomains` is present the elaborated constants are authoritative and the -external mask cannot alter residency visibility. Elaboration rejects a -capability list that differs from the static domains or a shared-resource -participant that does not advertise the required capability. - -Configured shared resources arbitrate before RF reads. The formal profile has -three independent resources shared by ALU2 and ALU5: DIV, PAC, and SYS. Two -requests for different resources may proceed together; two requests for the -same resource use work-conserving round-robin. The fairness base advances only -when the winning attempt also receives the atomic RF grant. A losing attempt -remains in its original I1 lane, keeps its canonical IQ `inFlight` claim, and -retries arbitration without delete/reinsert state. Invalid or non-one-hot -capability metadata is blocked and reported separately. +Canonical callers construct `OooIexIssueReadFabric` from `CoreParams`. It +derives picker count, class/bank projections, capabilities, release geometry, +and shared-resource participants from one `OooIexPhysicalProfile`. +Elaboration rejects inconsistent static-domain capabilities or a +shared-resource participant that does not advertise the required capability. + +Configured shared resources arbitrate before RF reads. Multicycle, PAC, and +system requests use independent arbitration. Requests for different resources +may proceed together; requests for the same resource use work-conserving +round-robin. The fairness base advances only when the winning attempt also +receives the atomic RF grant. A losing attempt remains in its original I1 lane, +keeps its canonical IQ `inFlight` claim, and retries arbitration without +delete/reinsert state. Invalid or non-one-hot capability metadata is blocked +and reported separately. The surviving attempts enter the shared atomic RF arbiter. Bypass hits retain complete provenance in I2 and are removed from RF demand; @@ -73,28 +70,25 @@ physical owner uses the exact retained stage token. ## Verification ```bash -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueReadFabricSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` -The shared-resource UT proves ALU2/ALU5 same-resource exclusion, accepted-grant -round-robin rotation, independent DIV/PAC concurrency, ordinary-ALU bypass, +The shared-resource test proves same-resource exclusion, accepted-grant +round-robin rotation, independent multicycle/PAC concurrency, ordinary-ALU bypass, malformed capability rejection, and fail-closed inconsistent static metadata. -The IT drives the compatibility bank-mask input to zero while a static ALU -domain still selects its declared bank, then publishes one ready ALU row whose -generation-qualified PTag has no -physical data. I1 receives a complete port grant but no P response, rejects the -attempt, and clears only that row's in-flight claim. After the exact P owner is -initialized, the row is repicked and reaches retained I2 with the expected -64-bit value. The test then drains I2, performs exact terminal IQ release, and -requires aggregate quiescence. +The mechanism suite publishes a ready ALU row whose generation-qualified PTag +has no physical data. I1 receives a complete port grant but no P response, +rejects the attempt, and clears only that row's in-flight claim. After the +exact P owner is initialized, the row is repicked and reaches retained I2 with +the expected 64-bit value. ## Remaining gaps -- Compose the six PC ports with `OooPcBuffer` in the canonical top. -- Connect the implemented `OooIexLoadUnit` speculative wakeup, bypass, and - miss/fault cancel outputs to the canonical issue ports in the static top. +- Compose the PC ports with `OooPcBuffer` in the canonical top. +- Connect the execution cluster's canonical speculative wakeup, bypass, and + replay/fault cancel outputs to these issue ports in the final static top. - Connect execution-unit busy/latency reservations to early policy and static E1/reflow/result-bus owners to the exact stage-cancel channels. -- `OooIexPipeline` now instantiates the specialized read and E1 fabrics from - one formal profile and makes I2/release wiring private. Connect that - production boundary to O3 PC reads and typed execution owners. +- `OooIexPipeline` instantiates read and E1 fabrics from one formal profile and + makes I2/release wiring private. Connect that boundary to OOO PC reads and + typed execution owners. diff --git a/docs/chisel/modules/execute/OooIexLoadLiqAllocAdapter.md b/docs/chisel/modules/execute/OooIexLoadLiqAllocAdapter.md deleted file mode 100644 index da2d084e..00000000 --- a/docs/chisel/modules/execute/OooIexLoadLiqAllocAdapter.md +++ /dev/null @@ -1,78 +0,0 @@ -# OooIexLoadLiqAllocAdapter - -## Purpose - -`OooIexLoadLiqAllocAdapter` is the typed allocation boundary between the three -production scalar-load AGUs and the one canonical LSU load-inflight queue. It -does not retain a load request: AGU lanes hold `valid` under backpressure, and -the LIQ becomes the sole lifecycle owner on the common allocation fire. - -Source and tests: - -- `chisel/src/main/scala/linxcore/ooo/OooIexLoadLiqAllocAdapter.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexLoadLiqAllocAdapterSpec.scala` - -## Contract - -The adapter fairly arbitrates three `OooIexAguLoadRequest` inputs into the -current single LIQ allocation port. An accepted transaction maps: - -- the complete producer `RobMemberKey` into `LoadAttemptIdentity`; -- an allocation-serial attempt generation which never rewinds on recovery; -- full LSID and exact youngest-older-store LSID from the OOO memory-order tail; -- native ROB/BROB projections plus PE/STID scope; -- parent PC, effective address, access size/sign, and GPR destination; -- the displaced physical GPR mapping required by the canonical return ABI; -- the physical AGU lane into one of three LSU return-pipe identities. - -The bridge invokes `LoadAttemptIdentity.requireBridgeFits` at elaboration and -also proves the OOO RID, BID projection, LSID, PC, scope, architectural tag, -and physical tag widths fit the selected LSU configuration. It rejects rather -than truncates. - -## Admission and recovery - -Admission requires exact OOO member scope, scalar-load recipe/owner/class, -one-request memory-order evolution, a canonical current/previous GPR mapping, -and a valid parent PC. Flush or exact grouped-ROB recovery suppresses -allocation and asserts `ready` only as a destructive cancellation handshake -for the affected AGU request. This drains visible pre-recovery requests without -allocating them, so they cannot reappear after the recovery pulse. Recovery -does not reset or consume the allocation generation. - -This packet deliberately sets `specWakeup=false`. I0.15c-b may enable it only -when exact speculative wakeup and cancellation are composed atomically with -canonical LIQ launch/return ownership. - -`OooMemoryIdState.youngestStoreLsid` is an architectural implementation -boundary for forwarding, not an optimization. `storeId - 1` identifies the -youngest store in the type-local stream, while only this retained field gives -its position in the unified load/store LSID stream. - -## Verification - -```bash -bash tools/chisel/run_chisel_tests.sh --only OooIexLoadLiqAllocAdapter -bash tools/chisel/run_chisel_tests.sh --only OooMemoryOrderAllocator -bash tools/chisel/run_chisel_tests.sh --only OooIexPickP1Bridge -bash tools/chisel/run_chisel_tests.sh --only OooIexAguPipeline -``` - -The directed adapter suite uses unequal `LIQ=4`, `ROB=8`, `STQ=4`, and -`LSID=40` capacities. It covers exact field mapping, all three lanes, fair -serial admission, downstream backpressure, lane-to-return-pipe identity, -exact narrow ROBID projections beside full identities, displaced PTag mapping, -missing-PC rejection, destructive hard/precise recovery drain, and generation -continuity. - -## Remaining gaps - -- connect `alloc` and returned `loadId` to live `ScalarLSULoadPath` residency; -- expose canonical LIQ launch/repick and bind speculative wakeup/cancel to - accepted attempt transitions; -- compose the three STQ snapshot/result pipes with LIQ E1/E3/E4; -- extend LRET terminal metadata or add an immutable lease-checked sidecar so - LSU results can reconstruct `OooIexLoadResult` without lifecycle ownership; -- make one recovery apply fence OOO, LIQ, MissQ, ResolveQ, LRET, and W1/W2; -- remove the duplicate `OooIexLoadUnit` tracker only after the live path and - stale-return/recovery IT gates pass. diff --git a/docs/chisel/modules/execute/OooIexLoadUnit.md b/docs/chisel/modules/execute/OooIexLoadUnit.md deleted file mode 100644 index bb083034..00000000 --- a/docs/chisel/modules/execute/OooIexLoadUnit.md +++ /dev/null @@ -1,98 +0,0 @@ -# OooIexLoadUnit - -## Purpose - -`OooIexLoadUnit` is the current migration-era scalar-load owner after a typed -AGU request is accepted. It -allocates an exact load attempt, retains multiple outstanding requests, emits -speculative readiness, accepts out-of-order exact responses, retries misses, -and retains hit/fault results for a later atomic writeback/commit sink. - -Source and test owners: - -- `chisel/src/main/scala/linxcore/ooo/OooIexLoadUnit.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexLoadUnitSpec.scala` - -The lifecycle follows the load-tracking and replay intent in `Documents/a.txt` -and the request/response boundary in -`tools/LinxCoreModel/model/iex/pipe/agu_pipe.cpp::runE1Load`. Linx grouped ROB, -P/T/U tags, generated recipes, and memory semantics remain authoritative. - -This is no longer the target production residency. I0.15c-a adds -`OooIexLoadLiqAllocAdapter`; I0.15c-b will move request/miss/replay/return -ownership into the existing canonical LIQ/MissQ/ResolveQ/LRET path and then -delete this duplicated tracker. Until that cutover, the execution cluster -continues to instantiate this module and must not also connect the same load -to canonical LSU residency. - -## Tracking ownership - -`iexLoadTrackEntries` is a positive power-of-two parameter, default 16. Each -entry has one of four states: - -```text -Free -> RequestPending -> AwaitingResponse -> ResultPending -> Free - ^ | - +-- Miss --+ -``` - -AGU acceptance requires a free entry, an exact P/T/U destination, and no live -entry for the same producer ROB member. The entry allocates -`{producer RobMemberKey, generation}`; a numerical generation alone is never -an identity. A fair request arbiter presents pending entries to memory. - -Every accepted memory attempt emits a `SpeculativeLoad` wakeup containing the -destination identity and exact load token. Consumers may become IQ-local -`specReady`, but I1 still requires a matching bypass before it can advance. - -## Response and replay - -Responses match only an `AwaitingResponse` entry with the complete load token: - -- `Hit`: byte/half/word data is sign- or zero-extended from the D1 control; - doubleword data is preserved. The result and W1 bypass remain stable until - the terminal result is accepted. -- `Miss`: the old generation is canceled, the same tracking owner allocates a - new generation, and the request returns to `RequestPending`. The next - request fire emits a new speculative wakeup. Existing IQ/P1/I1/I2 consumers - observe the cancel and repick through the canonical issue owner. -- `Fault`: the speculative generation is canceled and a precise fault result - is retained without bypass. - -Unknown, duplicate, stale, or post-recovery responses are consumed through a -typed rejection and cannot mutate another entry. Grouped-ROB recovery removes -only matching entries. - -## Publication boundary - -This unit does not directly write P/T/U data files, emit a committed wakeup, -complete ROB, or publish trace. `OooIexLoadResult` is accepted by the -implemented `OooIexTerminalPublish`, which writes data, publishes committed -readiness, traces the result/fault, and completes the ROB member on one common -terminal fire. Canonical static-top wiring remains open. - -## Verification - -```bash -bash tools/chisel/run_chisel_tests.sh --only OooParamsSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexLoadUnitSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1LaneSpec -``` - -The load UT covers generation allocation, request backpressure, speculative -wakeup, signed-byte extension, retained bypass/result, exact hit, miss cancel, -new-generation retry, malformed identity/access and duplicate-producer -rejection, stale-response rejection, precise fault, recovery, and post-recovery -response rejection. The issue/lane regression proves that the -same cancel contract poisons retained I2 and clears canonical IQ `inFlight`, -then a new generation wakes, bypasses, and repicks the consumer. - -## Remaining gaps - -- physical cache/TLB request and response adapter, ordering, alignment, and - access-fault generation; -- store AGU/STD source projection, join, store queue, forwarding, and commit; -- canonical connection to `OooIexTerminalPublish`, grouped ROB, IQ, and trace; -- multi-port load response/bypass bandwidth and latency reservation; -- canonical static-top connection and end-to-end AGU/LSU/IQ replay IT; -- synthesis timing, randomized pressure, and workload evidence. diff --git a/docs/chisel/modules/execute/OooIexP1I2Lane.md b/docs/chisel/modules/execute/OooIexP1I2Lane.md index 3802189a..bd80f5c2 100644 --- a/docs/chisel/modules/execute/OooIexP1I2Lane.md +++ b/docs/chisel/modules/execute/OooIexP1I2Lane.md @@ -13,7 +13,7 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexStageCancel.scala` - `chisel/src/main/scala/linxcore/ooo/OooBundles.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexP1I2LaneSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexP1I2PcIntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` ## Stage contract @@ -57,11 +57,9 @@ serialize fairly; domains on distinct ports can transfer together. ## PC timing -The current `OooPcBuffer` is readyless and returns reconstructed -`base + byteOffset` data combinationally from one fixed replica port. I1 -requests the token and I2 registers the returned full PC. This differs from -the ARM reference notes, which describe an I1 base-array read followed by I2 -address reconstruction, but preserves the same visible I2 timing boundary. +The current `OooPcBuffer` is readyless and returns the selected base PC. I1 +requests the generation-qualified buffer index; I2 adds the retained byte +offset and registers the reconstructed full PC. A synchronous PC or RF macro must add an explicit retained response stage or split I1 into request/response phases. It must not hide latency by holding an @@ -69,9 +67,9 @@ unregistered request token or duplicating allocation/recovery ownership. ## Recovery -`OooResidencyRecoveryPlan` membership is checked independently for retained I1 -and I2 rows. A matching recovery suppresses the affected output in the apply -cycle, clears the retained stage, and reports the exact member/reservation in +Canonical `RecoveryPlan` membership is checked independently for retained I1 +and I2 rows. Only an accepted Apply phase suppresses the affected output, +clears the retained stage, and reports the exact member/reservation in `recoveryCanceled(0)` for I1 or `(1)` for I2. An unrelated STID continues. ## Speculative load cancellation @@ -120,8 +118,7 @@ wins a same-cycle race and does not generate a duplicate ordinary retry. ```bash bash tools/chisel/run_chisel_tests.sh --only OooIexP1I2LaneSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexP1I2PcIntegrationSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1LaneSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` The focused UT covers backpressure stability, P/T source masks, optional PC, @@ -130,7 +127,7 @@ exact cross-STID recovery, stale load-bypass rejection, RF-mask subtraction, retained I2 bypass provenance, stale load-cancel rejection, simultaneous I1/I2 exact resource cancellation with two retained retries, stale stage-token rejection, and exact I2 poison. -The issue/lane IT additionally proves canonical IQ in-flight return plus a new -generation wakeup/bypass/reissue. The PC IT allocates and publishes a real PC-buffer token, -reads it through the fixed readyless port, and proves that the full PC and -source value are retained at I2. +The mechanism test additionally proves canonical IQ in-flight return and wires +a real PC buffer through the readyless read arbiter. It allocates and publishes +a PC-buffer token, reads the base, and proves I2 retains the reconstructed PC +and source value. diff --git a/docs/chisel/modules/execute/OooIexPhysicalProfile.md b/docs/chisel/modules/execute/OooIexPhysicalProfile.md index af0dc52a..7eb90162 100644 --- a/docs/chisel/modules/execute/OooIexPhysicalProfile.md +++ b/docs/chisel/modules/execute/OooIexPhysicalProfile.md @@ -3,9 +3,8 @@ ## Purpose `OooIexPhysicalProfile` is the elaboration-time source of truth for physical -issue residency, picker multiplicity, and execution-lane capabilities. It -prevents five different concepts from being collapsed into one dispatch -class or one numerical "domain": +Issue Queue residency, picker multiplicity, and execution-lane capabilities. +It keeps five concepts distinct: 1. the logical class assigned by generated decode metadata; 2. the class/bank rows retained by one residency owner; @@ -19,81 +18,71 @@ Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexE1TransferFabric.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexPhysicalProfileSpec.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexAtomicReadArbiterSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` -## Formal topology +## Canonical topology -`OooIexLinxPhysicalProfile` defines twelve disjoint residency owners, fourteen -picker functions, fourteen execution lanes, and fourteen exact release ports. -Residency owner count is a storage/topology property; picker count is issue -bandwidth and must not be used to duplicate IQ rows. +`OooIexPhysicalProfile.fromCoreParams` derives eight disjoint residency +owners, ten picker functions, ten execution lanes, and ten exact release ports +for the current W4 configuration. Decode, dispatch, and issue width remain +parameterized through W2/W4/W6/W8. Execution resources remain the specified +2 ALU, 1 BRU, 2 AGU, 2 STD, 1 system/multicycle queue, and 1 CMD queue. +Residency-owner count is a storage property; picker count must not be used to +duplicate IQ rows. | Residency owner | Logical residency | Picker functions | Declared capabilities | |---|---|---|---| -| ALU0 | partition of ALU; lower-half STD banks | `alu0` | simple ALU, store data | -| ALU1 | partition of ALU | `alu1` | simple ALU | -| ALU2 | partition of ALU; lower-half SYS banks | `alu2` | simple/multi-cycle ALU, PAC, system | -| ALU3 | partition of ALU; upper-half STD banks | `alu3` | simple ALU, store data | -| ALU4 | partition of ALU | `alu4` | simple ALU | -| ALU5 | partition of ALU; upper-half SYS banks | `alu5` | simple/multi-cycle ALU, PAC, system | +| ALU0 | partition of ALU and STD banks | `alu0` | simple ALU, store data | +| ALU1 | partition of ALU and STD banks | `alu1` | simple ALU, store data | | AGU0 | partition of AGU | `agu0-lda`, `agu0-sta` | load address, store address | | AGU1 | partition of AGU | `agu1-lda`, `agu1-sta` | load address, store address | -| AGU2 | partition of AGU | `agu2-lda` | load address only | -| BRU0 | partition of BRU | `bru0` | branch | -| BRU1 | partition of BRU | `bru1` | branch | -| FSU0 | all FSU and CMD banks | `fsu0` | floating/vector, engine command | +| BRU0 | all BRU banks | `bru0` | branch | +| SYS0 | ALU/SYS banks | `sys0` | multicycle ALU, PAC, system | +| FSU0 | all FSU banks | `fsu0` | floating/vector | +| CMD0 | all CMD banks | `cmd0` | engine command | Boundary metadata is fast-resolved and owns no physical IQ bank. For every other generated class, the union of residency-owner masks covers every configured bank exactly once. Picker projections may overlap only when their -declared capability sets are disjoint. Consequently the LDA and STA picker of -AGU0 or AGU1 can observe the same physical banks without being eligible for -the same row. ALU masks preserve two physical clusters; STD and SYS follow the -same lower/upper split. The profile requires at least eight even-numbered IQ -banks so both ALU clusters contain at least four banks. +declared capability sets are disjoint. Each AGU's LDA and STA picker can +therefore observe the same physical banks without becoming eligible for the +same row. ALU and STD masks preserve the two physical integer clusters. ## Capability boundary Capability is retained as profile metadata rather than inferred from class. This distinction is required because: -- AGU contains both LDA and STA recipes, but AGU2 cannot accept STA; -- ALU contains simple, multi-cycle, and pointer-authentication recipes, but - only ALU2/5 accept the latter two; -- STD and SYS share physical ALU queues without becoming ordinary ALU - operations; -- FSU and engine commands share one external selection domain but require - different downstream execution behavior. +- AGU contains LDA and STA recipes with separate picker functions over each + shared AGU residency owner; +- simple ALU work and system/multicycle/PAC work have separate owners even + when both observe ALU-class banks; +- STD shares physical ALU queues without becoming an ordinary ALU operation; +- FSU and engine commands use separate owners and downstream behavior. -Generated recipe metadata now carries one capability requirement per dispatch +Generated recipe metadata carries one capability requirement per dispatch class. `OooIexCapabilityTopology` projects the static owner declarations into a class-by-bank matrix for D3. Reservation considers only free banks whose physical owner covers the recipe requirement. S2 stores the selected child's -requirement beside the compact scheduling state; S3 candidate creation, -retained-token claim, retry, and query all revalidate it against the static -domain capability. I2-to-E1 transfer performs the final check from the full -recipe before ownership and exact IQ release can fire. - -All checks are fail-closed: a nonzero dispatch demand needs exactly one known -capability, and a picker must cover every required bit. Therefore -AGU2 cannot receive STA, and DIV/REM-class work can be reserved or selected -only by ALU2/5. Default constructors retain a permissive topology for focused -legacy unit harnesses; the formal profile exposes `capabilityTopology` and -`transferConfigs` for canonical integration. - -The same separation now models picker multiplicity directly. AGU0/1 each have -independent load- and store-address pickers over one residency owner, whereas -AGU2 has only a load picker. The two typed pickers can issue together when -both have ready rows. DIV, PAC, and SYS remain independent physical resources -shared by ALU2/ALU5. Their I1 arbiter uses the separate execution-lane identity -without changing residency or picker ownership. +requirement beside compact scheduling state; S3 candidate creation, retained +token claim, retry, and query revalidate it against the static capability. +I2-to-E1 transfer performs the final check before ownership and exact IQ +release can fire. + +All checks fail closed: a nonzero dispatch demand needs exactly one known +capability, and a picker must cover every required bit. The formal profile +exposes `capabilityTopology` and `transferConfigs` for canonical integration. +Multicycle, PAC, and system reservations remain independent physical +resources; their I1 arbiter uses execution-lane identity without changing +residency or picker ownership. ## Scaling the read boundary -The formal profile exceeds the earlier eight-picker limit. `OooParams` now -allows up to sixteen picker functions, and `OooIexAtomicReadArbiter` computes a -total priority rank followed by greedy complete-group packing. The network is -polynomial in picker count and preserves the prior lexicographic selection -contract without enumerating `2^N` subsets. +`OooParams` allows up to sixteen picker functions, and +`OooIexAtomicReadArbiter` computes a total priority rank followed by greedy +complete-group packing. The network is polynomial in picker count and +preserves the lexicographic selection contract without enumerating `2^N` +subsets. ## Verification @@ -102,26 +91,29 @@ bash tools/chisel/run_chisel_tests.sh --only OooIexPhysicalProfileSpec bash tools/chisel/run_chisel_tests.sh --only OooIexAtomicReadArbiterSpec bash tools/chisel/run_chisel_tests.sh --only OooIexE1TransferFabricSpec bash tools/chisel/run_chisel_tests.sh --only OooIexOldestReadyPickerSpec -bash tools/chisel/run_chisel_tests.sh --only OooDispatchSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1FabricSpec +bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec bash tools/chisel/run_chisel_tests.sh --only OooIexE1TransferSlotSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` -The profile UT proves exact owner/picker/lane names, 12/14/14 counts, complete -disjoint residency coverage, capability-disjoint picker overlap, required -capability placement, representative cluster masks, invalid topology -rejection, and fourteen-picker transfer-fabric elaboration. Dispatch, -P1-fabric, and E1-slot tests prove recipe capability -steering, unsupported-row residency without claim, and final retained-transfer -rejection. The RF arbiter UT proves six oldest complete P-read groups win -from the configured contenders. Fabric and picker tests prove multi-class +The profile UT proves exact owner/picker/lane names, disjoint residency +coverage, capability-disjoint picker overlap, required capability placement, +representative cluster masks, and invalid topology rejection. +`IEXMechanismSpec` proves that main and bounded W2/W4/W6/W8 configurations +derive the same physical topology and dynamically elaborates the bounded +mechanisms. Full-capacity RTL generation remains a separate closure gate. +Dispatch and E1-slot tests prove recipe steering, unsupported-row residency +without claim, and final retained-transfer rejection. The RF arbiter tests +oldest complete read-group selection. Fabric and picker tests prove multi-class admission, simultaneous AGU LDA/STA selection, wrong-bank rejection, and oldest selection across ALU/STD projections. ## Remaining work - connect shared-resource busy/latency and result-bus reservations; -- `OooIexPipeline` now instantiates the profile in the canonical static - issue/read/E1 top; typed execution and LSU owners remain to be connected; -- synthesize the fourteen-picker rank, RF crossbar, release fanout, and picker - matrix at the default geometry. +- connect `OooIexPipeline` to the typed execution and LSU owners; +- remove the older `OooIexLinxPhysicalProfile.apply` alternate topology after + its remaining focused tests and helper defaults migrate to + `fromCoreParams`; +- synthesize the parameter-derived rank, RF crossbar, release fanout, and + picker matrix at the default geometry. diff --git a/docs/chisel/modules/execute/OooIexPipeline.md b/docs/chisel/modules/execute/OooIexPipeline.md index fb5ad5cb..778a5441 100644 --- a/docs/chisel/modules/execute/OooIexPipeline.md +++ b/docs/chisel/modules/execute/OooIexPipeline.md @@ -2,32 +2,34 @@ ## Purpose -`OooIexPipeline` is the canonical production composition from retained IEX S1 -publication through P1, I1 operand acquisition, retained I2, and typed E1 -execution-lane capture. It replaces the former test-only wiring between -`OooIexIssueReadFabric` and `OooIexE1TransferFabric`. +`OooIexPipeline` is the canonical composition from classed OOO dispatch +through IQ residency, P1 selection, I1 operand acquisition, retained I2, and +typed E1 execution-lane capture. It privately composes +`OooIexIssueReadFabric` with `OooIexE1TransferFabric`. Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexPipeline.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexIssueE1IntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` +- `chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala` ## Ownership contract -The constructor accepts one `OooIexPhysicalProfile`. The same object creates -both `OooIexLinxIssueReadFabric` and `OooIexLinxE1TransferFabric`, so the +The constructor accepts `CoreParams` and derives one +`OooIexPhysicalProfile`. The same object configures both +`OooIexIssueReadFabric` and `OooIexLinxE1TransferFabric`, so the following properties cannot be configured independently: - picker count and class/bank visibility; - recipe capabilities and shared DIV/PAC/SYS participants; - execution-lane identity; -- exact IQ and dispatch release ports. +- exact IQ release ports. The I2 channels and issue-release channels are private to the module. For each -winning lane, I2 advancement, exact canonical IQ deletion, dispatch-slot -return, and retained E1 capture are one handshake. The public boundary exposes -only S1 admission and typed E1 outputs; it cannot acknowledge an E1 transfer -without also returning the exact IQ and dispatch owners. +winning lane, I2 advancement, exact canonical IQ deletion, and retained E1 +capture are one handshake. The public boundary exposes classed dispatch and +typed E1 outputs; it cannot acknowledge an E1 transfer without also releasing +the exact IQ owner. This matches the LinxCoreModel owner order in `model/iex/iex.cpp::{Work,Xfer,SubReleaseIQEntryI2}` and the stage contract in @@ -39,16 +41,16 @@ ownership authority. ## Recovery and external owners -The existing retained issue-recovery scan remains the preparation authority. -`recoveryFire` is legal only while the exact plan is still valid and prepared. -On that edge the same plan reaches the E1 transfer slots, so killed S1/IQ/P1/ -I1/I2 state and already-transferred E1 state observe one physical recovery -event. An assertion rejects an unprepared or withdrawn recovery fire. +The retained issue-recovery scan remains the preparation authority. The +canonical `RecoveryTargetIO` prepare handshake is side-effect free; only an +accepted Apply or Abort phase can mutate retained state. The accepted exact +plan reaches the E1 transfer slots on the same event, so killed IQ/P1/I1/I2 +state and already-transferred E1 state observe one recovery decision. `OooIexPipeline` does not duplicate other canonical owners: -- PC requests remain six readyless token reads to the `OooPcBuffer` already - owned by `OooO3RenameCoordinator`; +- PC requests remain readyless typed outputs at this Task-13 mechanism + boundary; public `OOO` does not claim a private execution PC-buffer owner; - P/T/U initialization, allocation clears, and terminal writes remain public connections to rename/writeback owners; - load cancellation, bypass, issue policy, and exact I1/I2 late cancellation @@ -62,32 +64,27 @@ transfer slots being empty. Queue-only emptiness is not pipeline quiescence. ```bash bash tools/chisel/build_chisel.sh -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueE1IntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionPipelineSpec ``` -The integration test instantiates the formal twelve-residency-owner, -fourteen-picker, fourteen-execution-lane profile. A source-free ALU row and a -PC-reading BRU row select ALU0 and BRU0, transfer together through their -production release ports, return the exact dispatch reservations, disappear -from canonical IQ residency, remain retained under E1 backpressure, and make -aggregate quiescence true only after both typed E1 consumers fire. - -The IT uses the minimum two-entry-per-bank geometry while preserving all -twelve owners, fourteen pickers, and fourteen lanes. Detailed retry, cancel, -shared-resource, and malformed-topology scenarios remain in the smaller child -fabric UTs because compiling the complete production topology is intentionally -a heavyweight integration gate. +The mechanism suite proves matching main/bounded W2/W4/W6/W8 configurations, +dynamically elaborates bounded W4/W2 mechanisms, proves parallel ALU claims and +denial isolation, and connects real operand files plus a real PC-buffer read path. +The execution-pipeline suite covers typed lane routing and +terminal behavior. Detailed retry, cancel, shared-resource, and malformed +topology scenarios remain in focused child-fabric tests. ## Remaining gaps -- Connect the six PC request tokens and responses directly to the existing O3 - coordinator in the canonical OOO/IEX composition. -- Promote `OooIexExecutionPipeline` as the O9 canonical top consumer. It now - connects every typed lane to an internal ALU/BRU/scalar-load owner or an - explicit retained unfinished-family boundary and returns W1/load bypass, - speculative/committed wakeup, and exact load-cancel traffic. +- Connect the PC request tokens and responses directly to `OooPcBuffer` in the + canonical OOO/IEX composition. +- Complete `OooIexExecutionPipeline` as the canonical typed E1 consumer. It + connects implemented ALU/BRU/scalar-load lanes and explicit retained + unfinished-family boundaries while returning bypass, wakeup, and exact + load-cancel traffic. - Close the retained store/multicycle/system/PAuth/FSU/CMD boundaries with - their production owners; do not replace them with permissive sinks. + their canonical owners; do not replace them with permissive sinks. - Drive early issue policy and late stage cancellation from measured execution-lane, reflow, latency, side-door, and result-bus reservations. - Run default-width synthesis/timing and natural workload activation after the diff --git a/docs/chisel/modules/execute/OooIexStageCancel.md b/docs/chisel/modules/execute/OooIexStageCancel.md index 9c2fe107..48098973 100644 --- a/docs/chisel/modules/execute/OooIexStageCancel.md +++ b/docs/chisel/modules/execute/OooIexStageCancel.md @@ -46,12 +46,12 @@ and reason evidence; it does not change lane or IQ state. ```bash bash tools/chisel/run_chisel_tests.sh --only OooIexP1I2LaneSpec -bash tools/chisel/run_chisel_tests.sh --only OooIexIssueP1LaneSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec ``` The lane UT holds the retry consumer off while exact requests target different I2 and I1 members together. It proves I2-first arbitration, two retained retry identities, downstream suppression, quiescence accounting, and ordered drain. It also proves a stale identity is rejected while the real I1 attempt remains -live. The canonical-IQ IT proves an accepted I2 sidedoor-class cancel clears -only the matching `inflight` row and repicks it into I1. +live. The mechanism suite proves an accepted cancel clears only the matching +`inflight` row and preserves exact retry ownership. diff --git a/docs/chisel/modules/execute/OooIexStoreStqFabric.md b/docs/chisel/modules/execute/OooIexStoreStqFabric.md index 5ab45233..651535ce 100644 --- a/docs/chisel/modules/execute/OooIexStoreStqFabric.md +++ b/docs/chisel/modules/execute/OooIexStoreStqFabric.md @@ -2,18 +2,15 @@ ## Purpose -`OooIexStoreStqFabric` is the canonical static composition for retained store -execution and Store Queue residency. It replaces the single-lease integration -harness with a production-shaped owner that can keep multiple logical stores +`OooIexStoreStqFabric` is the retained store-execution and Store Queue +residency mechanism. It can keep multiple logical stores live at once, accept two independent STA lanes and two independent STD lanes, and converge both halves only in `STQEntryBank`. Source and test owners: - `chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala` -- `chisel/src/main/scala/linxcore/ooo/OooIexExecutionStorePipeline.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexStoreStqFabricSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooIexExecutionStoreIntegrationSpec.scala` - `chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala` - `chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala` @@ -49,7 +46,14 @@ byte-mask phase followed by a data phase; only the returned exact lease can set the metadata row's `dataReady`. Commit drain and forwarding consumers observe the same joined row projection, so the physical data array has one owner. -The same held `OooResidencyRecoveryPlan` is prepared by both retained store +Before an address fill mutates STQ, `lateStaCandidate` exposes its complete MDB +probe and remains stable while `lateStaPermit` is false. `lateStaProbe` is the +accepted side-effect pulse, not the capacity request. This permits a composed +MDB owner to reserve record/wait/recovery capacity before STQ acceptance and +prevents a store address from becoming visible without its conflict side +effect. + +The same held `RecoveryPlan` is prepared by both retained store pipelines and the STQ. Prepare is side-effect free and fences reserve, STA/STD acceptance, fill, commit-mark, and free mutation. Recovery can fire only when every killed STQ row is an exact `WAIT` row; one common fire then cancels the @@ -61,18 +65,16 @@ Issue recovery also rejects a pivot that would retain only one physical child of a logical split store. STA/STD recovery is therefore all-or-none while the store is retained before S2 and after its physical rows reach IQ residency. -The fabric's commit-mark and mask-free ports are private connections in -`OooIexExecutionStorePipeline` and `OooO3IexStorePipeline`. Semantic ROB store -tokens are matched to exact STQ leases by `STQSCBCommitBackend`; accepted SCB -last fragments are the terminal free authority. The remaining store path gap -is memory-system behavior, not raw physical-index commit ownership. +`STQSCBCommitBackend` matches semantic ROB store tokens to exact STQ leases; +accepted SCB last fragments are the terminal free authority. Task 13 removed +the separate IEX-plus-store shell, so the public IEX/LSU connection remains a +Task 15 integration boundary rather than a second store-ownership path. ## Verification ```bash bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabric bash tools/chisel/run_chisel_tests.sh --only STQDataBank -bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionStoreIntegration bash tools/chisel/run_chisel_tests.sh --only OooIexIssue bash tools/chisel/run_chisel_tests.sh --only OooIexStorePipeline bash tools/chisel/run_chisel_tests.sh --only OooStqReservationProjection @@ -81,12 +83,12 @@ bash tools/chisel/run_chisel_tests.sh --only STQEntryBank ``` The focused fabric UT covers two simultaneously resident logical stores with -crossed STA/STD lanes, two simultaneous independent STD data-bank writes, +crossed STA/STD lanes, retained late-STA capacity backpressure, two +simultaneous independent STD data-bank writes, refusal of unreserved execution, side-effect-free recovery prepare, mutation fencing, common-fire application, and rejection of -a split-store partial cut after the rows have transferred from IQ. The adjacent -execution/store IT drives the formal STA and STD lanes and observes address and -data in one pre-reserved canonical row. The issue test proves malformed +a split-store partial cut after the rows have transferred from IQ. The issue +test proves malformed reservation recipes fail before S1, S1 residency and S2 blocking until canonical reservation fires, and rejection of a recovery cut between STA and STD before reservation, after reservation, and in resident S3. @@ -95,11 +97,10 @@ STD before reservation, after reservation, and in resident S3. - Extend the physical data bank beyond the current scalar payload contract to vector/FSU widths, cross-bank ECC/parity, and explicit power-gating policy. -- Compose the joined canonical STQ snapshot into store-to-load forwarding, - partial-overlap detection, violation - replay, and LIQ/STQ memory-order checks. - Connect translation, PMP/PMA, MMIO classification, L1D/coherence, and externally visible fault publication. +- Connect canonical IEX STA/STD lanes to this mechanism and the canonical LSU + boundary without reintroducing the deleted combined shell. - Prove sustained two-STA pressure alongside the now-directed two-STD path, pair-store all-or-none behavior, default-width synthesis/timing, and O9 workload promotion. diff --git a/docs/chisel/modules/execute/OooIexTerminalPublish.md b/docs/chisel/modules/execute/OooIexTerminalPublish.md index d43c5fc5..f1eb2034 100644 --- a/docs/chisel/modules/execute/OooIexTerminalPublish.md +++ b/docs/chisel/modules/execute/OooIexTerminalPublish.md @@ -70,7 +70,7 @@ multi-destination terminal fork. ```bash bash tools/chisel/run_chisel_tests.sh --only OooIexTerminalPublishSpec bash tools/chisel/run_chisel_tests.sh --only OooIexOperandFilesSpec -bash tools/chisel/run_chisel_tests.sh --only OooS1GroupedRobFaultSpec +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec bash tools/chisel/run_chisel_tests.sh --only OooIexAluPipelineSpec bash tools/chisel/run_chisel_tests.sh --only OooIexBruPipelineSpec ``` diff --git a/docs/chisel/modules/execute/ReducedScalarAluExecute.md b/docs/chisel/modules/execute/ReducedScalarAluExecute.md deleted file mode 100644 index abeaa2e9..00000000 --- a/docs/chisel/modules/execute/ReducedScalarAluExecute.md +++ /dev/null @@ -1,674 +0,0 @@ -# ReducedScalarAluExecute - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/execute/ReducedScalarAluExecuteSpec.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/bctrl/spe/SPERename.cpp` - - `model/LinxCoreModel/model/iex/pipe/alu_pipe.cpp` - - `model/LinxCoreModel/model/iex/pipe/lda_pipe.cpp` - - `model/LinxCoreModel/model/iex/pipe/agu_pipe.cpp` - - `model/LinxCoreModel/model/iex/iex_rf.cpp` - - `model/LinxCoreModel/model/iex/rtable.cpp` - - `model/LinxCoreModel/model/iex/iex.cpp` - - `model/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp` - - `model/LinxCoreModel/isa/calculate/arithmetic/Arithmetic.cpp` - - `model/LinxCoreModel/isa/calculate/others/Others.cpp` - - `model/LinxCoreModel/isa/calculate/pc/PC.cpp` - - `model/LinxCoreModel/isa/calculate/store/Store.cpp` - - `model/LinxCoreModel/isa/calculate/compound/Compound.cpp` - - `model/LinxCoreModel/isa/ISACommon/OpcodeManager.h` - - `model/LinxCoreModel/isa/ISACommon/OpcodeManager.cpp` - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `model/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::handleSTQReceive` - - `LDQInfo::waitStore` - - `emulator/qemu/target/linx/translate.c` -- Contract IDs: `LC-IF-CHISEL-IEX-ALU-001`, `LC-IF-CHISEL-XCHK-006` - -## Purpose - -`ReducedScalarAluExecute` is the first Chisel scalar execute owner behind the -frontend trace path. It consumes one `RenamedUop`, computes a reduced -model-derived ALU subset, and emits both a ROB completion index and a -writeback-shaped `CommitTraceRow`. It emits the normal reduced issue-queue -release identity when a row reaches W2, plus a distinct E1 release identity -when an ordinary load transfers completion ownership to LIQ. - -This is not the final scalar integer execution unit. Source values are supplied -by the owning wrapper: the R81 top uses explicit testbench operands, while the -R82 RF-backed top reads `srcData` from a reduced scalar physical register file. -The full issue queue, bypass, wakeup, replay, and recovery paths remain later -owners. - -R266 adds a reduced load wait-hold input for the optional resident-STQ -forwarding path. When the current E-stage load overlaps an older resident store -whose data is not ready, the owning top asserts the wait input, this module -keeps the load resident in E, and the issue queue remains backpressured. This -models the first visible part of the LinxCoreModel LDQ `waitStore` path without -claiming a full LIQ/LDQ replay or wakeup implementation. -R269 exposes the E-stage load PC alongside the existing load lookup address, -size, BID, and LSID so the reduced top can remember the model wait-store match -identity used by `LDQInfo::handleSUWakeup`. -R311 also exposes the E-stage load's first renamed destination as -`loadLookupDst`, matching the model return path where `IEX::setMemWakeup` and -`IEX::setMemData` recover destination ownership from the ROB instruction. -R375 exposes `loadLookupSourceTraceValid/source0/source1` from the same -E-stage RF-returned source data used for execution. The model evidence is -`SimInstInfo::GenRFReqBus` plus `RFRetSetData`, where `iex_rf.cpp` fills -`psrcs_`, and `LDAPipe::runI1/runI2` plus `AGUPipe::runI1/runI2`, where load -pipes request and consume those source operands before W2. The sideband is -disabled for the synthetic `FRET.STK` RA-load return path and is not -reconstructed from ROB allocation rows. - -When the top enables live LIQ admission, `loadLiqEnable/loadLiqAccepted` -replace the direct E-stage ordinary-load result path with an explicit E1 -ownership handshake. `loadLiqEligible` qualifies that handoff. A valid -eligible load holds in E until accepted; on acceptance it does not enter direct -W1/W2 completion, and the LIQ-owned LRET/W1/W2 path becomes the sole -completion/writeback owner. `FRET.STK` RA-load returns deliberately report -`loadLiqEligible=false`: until LIQ carries their synthetic RA writeback, SP -restore, and redirect atomically, they retain direct execute ownership. The -synthetic RA-load form is selected by an explicit not-taken condition, or by -an absent condition with no live target owner; -when the condition is absent, an active block or SETC target remains the -redirect owner when present, and no target falls back to the RA load. In this -mode LIQ, rather than the direct resident-store lookup, -owns ordinary load store-forward wait and replay handling. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `inValid` | `Bool` | valid | One renamed scalar uop is available. | -| output | `inReady` | `Bool` | ready | The E stage can capture a new uop. | -| input | `in` | `RenamedUop` | with `inValid && inReady` | Renamed scalar uop from `DecodeRenameROBPath`. | -| input | `srcData` | `Vec(3, UInt(64.W))` by default | with accepted uop | Operand values supplied by the reduced top harness. | -| input | `flushValid` | `Bool` | pulse | Clears E/W1/W2 pipeline state and suppresses same-cycle completion/redirect outputs. | -| input | `loadLookupData` | `UInt(64.W)` by default | combinational with E-stage load lookup | Read-only reduced load data returned by the owning top for reduced load rows including `OP_C_LDI`, `OP_LDI`, `OP_LD_PCR`, `OP_HL_LD_PCR`, and the R132 `FRET.STK` RA-load path. | -| input | `loadLookupWaitBlocked` | `Bool` | combinational with E-stage load lookup | R266 reduced LSU hold request. Asserted by the owning top when the load data path found a wait-hit against an older not-ready resident store. | -| input | `loadLiqEnable`, `loadLiqAccepted` | `Bool`, `Bool` | combinational with E-stage load lookup | Enables E1-to-LIQ admission and reports acceptance by the LIQ adapter. When enabled, `loadLiqAccepted` is the only condition that releases a load from E. | -| input | `fretStkFallbackTargetValid`, `fretStkFallbackTarget` | `Bool`, `UInt(pcWidth.W)` | combinational | Active-marker fallback target used by reduced `FRET.STK` when no explicit SETC target is live. | -| input | `fretStkConditionValid`, `fretStkConditionTaken` | `Bool`, `Bool` | sampled in E1 | Latest reduced SETC condition. `FRET.STK` takes the latched/fallback target when it is present and the condition is absent or taken; a valid false condition, or an absent condition with no target owner, selects the RA-load return path when the restore range includes `x10`. The E1 sample travels with the return through W1/W2, so a younger marker boundary cannot alter the already-issued return. | -| input | `stackPointerData` | `UInt(64.W)` by default | combinational | Reduced SP shadow used by macro `FENTRY` rows and R132 `FRET.STK` RA-load address generation. | -| output | `completeValid` | `Bool` | valid | W2-stage supported uop completed. | -| output | `completeRobValue` | `UInt(log2Ceil(robEntries).W)` | with `completeValid` | ROB row to complete. | -| output | `completeRow` | `CommitTraceRow` | with `completeValid` | Commit-trace payload carrying PC, source data, destination data, writeback, ROB ID, and block BID sideband. | -| output | `completeDstPhysValid` | `Bool` | with `completeValid` | Destination physical tag and data are valid for a scalar GPR writeback. | -| output | `completeDstPhysTag` | `UInt(physRegWidth.W)` | with `completeDstPhysValid` | Renamed physical destination tag copied from `in.dst(0).physTag`; R132 `FRET.STK` RA-load uses reduced identity tag `x10` because decode remains no-destination. | -| output | `completeDstData` | `UInt(64.W)` by default | with `completeDstPhysValid` | ALU result for the RF/ready-table writeback owner. | -| output | `releaseValid` | `Bool` | valid | W2-stage uop reached the reduced issue-queue release point, including unsupported reduced opcodes. | -| output | `releaseBid` | `ROBID` | with `releaseValid` | Block identity copied from the W2 uop. | -| output | `releaseGid` | `ROBID` | with `releaseValid` | Group identity copied from the W2 uop for reduced replay completion matching. | -| output | `releaseRid` | `ROBID` | with `releaseValid` | ROB identity copied from the W2 uop. | -| output | `releaseStid` | `UInt(threadIdWidth.W)` | with `releaseValid` | STID copied from the W2 uop. | -| output | `liqReleaseValid` | `Bool` | valid | A live E1 load was accepted by LIQ and has no direct W2 completion. | -| output | `liqReleaseBid`, `liqReleaseRid`, `liqReleaseStid` | mixed | with `liqReleaseValid` | Issue-queue identity of that LIQ-owned E1 load. This is independent of the normal W2 release port. | -| output | `branchConditionValid` | `Bool` | with `completeValid` | Reduced conditional-block decision is valid for a completed compare row. | -| output | `branchConditionTaken` | `Bool` | with `branchConditionValid` | `OP_C_SETC_EQ`, `OP_C_SETC_NE`, `OP_SETC_LT`, `OP_SETC_LTU`, `OP_SETC_LTUI`, and reduced SETC target rows used by the reduced block-control owner. | -| output | `loadLookupValid` | `Bool` | E-stage valid | The current E-stage uop requests reduced read-only load data. | -| output | `loadLiqEligible` | `Bool` | with `loadLookupValid` | The lookup is an ordinary scalar load that may transfer E1 completion ownership to LIQ. False for the synthetic `FRET.STK` RA-load return, which remains on direct execute until LIQ owns its RA/SP/redirect effects. | -| output | `loadLookupAddr` | `UInt(64.W)` by default | with `loadLookupValid` | Byte address for the reduced read-only load lookup. | -| output | `loadLookupPc` | `UInt(pcWidth.W)` | with `loadLookupValid` | R269 PC sideband for the reduced wait-store replay slot. | -| output | `loadLookupBid`, `loadLookupGid`, `loadLookupRid` | `ROBID` | with `loadLookupValid` | R274 model ROB identity sidecars for reduced replay candidates. | -| output | `loadLookupDst` | `RenamedDestination` | with `loadLookupValid` | R311 first destination sideband captured with the load lookup for future replay LRET/writeback/wakeup ownership. | -| output | `loadLookupSourceTraceValid` | `Bool` | with ordinary load `loadLookupValid` | R375 source-trace sideband valid. Suppressed for `FRET.STK` RA-load returns because that synthetic path does not have ordinary load source provenance. | -| output | `loadLookupSource0`, `loadLookupSource1` | `CommitOperandTrace` | with `loadLookupSourceTraceValid` | R375 source operand trace copied from E-stage `srcData(0/1)` and the accepted uop's P-class architectural source tags. | -| output | `fretStkSpRestoreValid` | `Bool` | with `completeValid` | The condition-false `FRET.STK` RA-load path also restores architectural `x1/sp`. | -| output | `fretStkSpRestoreData` | `UInt(64.W)` by default | with `fretStkSpRestoreValid` | Restored SP value, `stackPointerData + in.imm`, for the owning top's scalar-SP shadow. | -| output | `redirectValid` | `Bool` | with `completeValid` | Reduced scalar redirect request for `FRET.STK` target-taken rows or condition-false RA-load return rows. | -| output | `redirectPc` | `UInt(pcWidth.W)` | with `redirectValid` | Return target selected from the loaded RA for R132 load-return rows, otherwise from `C.SETC.TGT`/`SETC.TGT` first and active-marker fallback second. | -| output | `accepted` | `Bool` | pulse | `inValid && inReady`. | -| output | `busy` | `Bool` | state | Any E/W1/W2 pipe stage is occupied. | -| output | `loadWaitHold` | `Bool` | state/diagnostic | The current E-stage load lookup is held by the direct wait-store input, or by LIQ allocation backpressure when live admission is enabled. | -| output | `unsupported` | `Bool` | pulse | W2 uop reached execute but is outside the reduced opcode subset. | -| output | `unsupportedOpcode` | `UInt(opcodeWidth.W)` | with `unsupported` | Unsupported opcode ID for diagnostics. | - -## State - -- `eValid/eUop/eSrcData`: accepted renamed uop and source values. -- `w1Valid/w1Uop/w1SrcData/w1Result/w1Supported`: first writeback pipe stage, - including the E1-sampled `FRET.STK` condition. -- `w2Valid/w2Uop/w2SrcData/w2Result/w2Supported`: completion pipe stage, - including the same return-local condition sample. - -The pipe is intentionally single-issue and in-order for the reduced frontend -trace path. - -## Logic Design - -`SPERename::InsertToSIEXQ` routes `ARITHMETIC`, `IMMEDIATE`, `MOVE`, and the -PC-relative constant path used by `ADDTPC` toward scalar execution. -`ALUPipe::Work` advances the uop through P1/I1/I2/E0/EX/W1/W2, calls -`SimInstInfo::Execute` in EX, and publishes the resolve bus at W2. -`SimInstInfo::Execute` runs `PrePareSrc`, `Calculate`, and `ProcessDst`; -arithmetic `ADD` returns `src0 + src1`, `ADDI` uses the decoded immediate, -`SUBI` subtracts the decoded immediate, -`MOVR/MOVI` move the source/immediate into the destination, and -`PC::CalcInstAddTPC` computes `(pc & ~0xfff) + imm`. `PC::CalcInstSetret` -computes `pc + imm`, and the compact `C.SETRET` form reaches execute as a -decoded alias of the `C.MOVI` low-opcode encoding when the destination is -`ra/x10`. `OP_HL_LUI` materializes the sign-extended 48-bit-format IMM32 -payload directly into the destination; the frontend packs `pfx16[15:4]` over -`main32[31:12]` before execute receives `in.imm`. R111 adds `OP_SLL`, which -left-shifts SrcL by the low six bits of SrcR; CoreMark's first instance reads -T0 and U0 local sources and writes U0. R112 adds the matching logical-right -shift `OP_SRL` for the following CoreMark local-source row. R108 adds a narrow -`FENTRY` -macro-template subset based on -`GenCodeFENTRY`: for the current CoreMark single-save form, the reduced decoder -reads the saved GPR and old SP, execute writes `SP - imm` back to SP, and the -completion row carries one 8-byte store at `newSP + imm - 8`. This is not a -general stack-template or LSU implementation. `ReadyState::GetSrcData` and -`InitGGPRRtable` show that scalar source data is attached to physical GPR tags, -so the Chisel execute owner also exports the destination physical tag for the -reduced RF writeback path. R109 keeps that RF writeback side effect scoped to -`DestinationKind.Gpr`; a T/U destination still produces a QEMU-shaped -architectural `dst`/`wb` completion row, but the reduced scalar RF is not -cleared or written for the local-register alias. -R113 adds `OP_OR` for the next local-source row and a narrow `OP_C_LDI` -zero-load row: the execute owner emits the QEMU-shaped 8-byte load sideband and -returns zero data only for the current reduced CoreMark prefix, not for general -memory execution. R114 adds the compressed local arithmetic row `OP_C_ADD`: -the compressed source fields select local T/U sources, the row writes implicit -T destination tag `31`, and QEMU still suppresses those local source fields in -commit JSONL. The current QEMU row also omits the local destination/writeback -fields for `C.ADD`, so the expected-row reducer synthesizes the implicit T -writeback from the LinxCoreModel compressed arithmetic contract while keeping -the QEMU PC/instruction stream and local-source history as the proof input. -R115 adds `OP_SRA` and the same dense-packet `OP_SLLI` row. `OP_SRA` follows -the LinxCoreModel arithmetic calculator default: signed 64-bit right shift by -`src1 & 0x3f`. `OP_SLLI` uses the model `@shift_i` immediate source, -`shamt_20_25`, carried in `RenamedUop.imm` by `FrontendOperandDecode`. - -The Chisel module implements the first reduced subset: - -| Opcode | Result | -|---|---| -| `OP_ADD` | `srcData(0) + SrcR`, including model SrcR modifier and shift fields | -| `OP_ADDI` | `srcData(0) + in.imm` | -| `OP_SUB` | `srcData(0) - SrcR`, including model SrcR modifier and shift fields | -| `OP_SUBI` | `srcData(0) - in.imm` | -| `OP_AND` | `srcData(0) & SrcR`, including model SrcR modifier and shift fields | -| `OP_ANDI` | `srcData(0) & in.imm` | -| `OP_ANDIW` | sign-extended low-32-bit `srcData(0) & in.imm` | -| `OP_ADDTPC` | `(in.pc & ~0xfff) + in.imm` | -| `OP_C_MOVI` | `in.imm` | -| `OP_C_MOVR` | `srcData(0)` | -| `OP_C_ADD` | `srcData(0) + srcData(1)` | -| `OP_C_SLLI`, `OP_C_SRLI` | shift implicit `t#1` source left/right by `uimm5` and write implicit `t` | -| `OP_C_AND` | `srcData(0) & srcData(1)` | -| `OP_C_SUB` | `srcData(0) - srcData(1)` | -| `OP_C_SEXT_B/H/W` | sign-extend `srcData(0)` from 8, 16, or 32 bits | -| `OP_C_ZEXT_B/H/W` | zero-extend `srcData(0)` from 8, 16, or 32 bits | -| `OP_C_LDI` | `loadLookupData`, with a reduced 8-byte load sideband at `srcData(0) + in.imm` | -| `OP_C_SDI` | `0`, with a reduced 8-byte store sideband at `srcData(0) + (in.imm << 3)` and store data `srcData(1)` | -| `OP_C_SWI` | `0`, with a reduced 4-byte store sideband at `srcData(0) + (in.imm << 2)` and store data `srcData(1)` | -| `OP_C_SETC_EQ` | `0`, with branch sideband taken when validity-masked `srcData(0) == srcData(1)` | -| `OP_C_SETC_NE` | `0`, with branch sideband taken when validity-masked `srcData(0) != srcData(1)` | -| `OP_C_SETC_TGT` | `0`, latches `srcData(0)` as the reduced dynamic target | -| `OP_C_SETRET` | `in.pc + in.imm` | -| `OP_CMP_EQI` | `1` when `srcData(0) == in.imm`, otherwise `0` | -| `OP_CSEL` | `srcData(0)` when `srcData(2) != 0`, otherwise `srcData(1)` | -| `OP_FENTRY` | `stackPointerData - in.imm`; the store address uses the ranged save count to place the first saved register | -| `OP_FRET_STK` | redirect-only while a live SETC/marker target is selected; on an explicit condition-false path, or when no condition and no target owner exist, load `x10/ra` from `stackPointerData + in.imm - 8`, emit an 8-byte load sideband, write reduced RF tag `x10`, emit `fretStkSpRestoreData = stackPointerData + in.imm`, and redirect to the loaded value | -| `OP_HL_LIS`, `OP_HL_LUI` | sign-extended 32-bit immediate | -| `OP_HL_LIU` | zero-extended 32-bit immediate | -| `OP_HL_ADDI`, `OP_HL_SUBI` | 64-bit add/subtract with the frontend-zero-extended `uimm24` | -| `OP_HL_ADDIW`, `OP_HL_SUBIW` | low-32-bit add/subtract with `uimm24`, then sign-extend | -| `OP_HL_ANDI`, `OP_HL_ORI`, `OP_HL_XORI` | 64-bit logical operation with the frontend-sign-extended `simm24` | -| `OP_HL_ANDIW`, `OP_HL_ORIW`, `OP_HL_XORIW` | low-32-bit logical operation with sign-extended `simm24`, then sign-extend | -| `OP_HL_LD_PCR` | `loadLookupData`, with an 8-byte load sideband at `in.pc + in.imm` | -| `OP_HL_SB_PCR` | `0`, with a reduced 1-byte store sideband at `in.pc + in.imm` and store data `srcData(0)` | -| `OP_HL_SD_PCR` | `0`, with a reduced 8-byte store sideband at `in.pc + in.imm` and store data `srcData(0)` | -| `OP_HL_SH_PCR` | `0`, with a reduced 2-byte store sideband at `in.pc + in.imm` and store data `srcData(0)` | -| `OP_HL_SW_PCR` | `0`, with a reduced 4-byte store sideband at `in.pc + in.imm` and store data `srcData(0)` | -| `OP_LBUI` | zero-extended byte from `loadLookupData(7, 0)`, with a reduced 1-byte load sideband at `srcData(0) + in.imm` | -| `OP_LD_PCR` | `loadLookupData`, with an 8-byte load sideband at `in.pc + in.imm` | -| `OP_LDI` | `loadLookupData`, with a reduced 8-byte load sideband at `srcData(0) + (in.imm << 3)` | -| `OP_SETC_LT` | `0`, with branch sideband taken when signed `srcData(0) < SrcR`, including model SrcR modifier and shift fields | -| `OP_SETC_TGT` | `0`, latches `srcData(0)` as the reduced dynamic target | -| `OP_SETC_LTU` | `0`, with branch sideband taken when unsigned `srcData(0) < srcData(1)` | -| `OP_SETC_LTUI` | `0`, with branch sideband taken when unsigned `srcData(0) < in.imm` | -| `OP_ADDW` | sign-extended low-32-bit `srcData(0) + srcData(1)` | -| `OP_SD` | `0`, with a reduced 8-byte indexed store sideband at `srcData(1) + (srcData(2) << 3)` and store data `srcData(0)` | -| `OP_SDI` | `0`, with a reduced 8-byte store sideband at `srcData(1) + (in.imm << 3)` and store data `srcData(0)` | -| `OP_SWI` | `0`, with a reduced 4-byte store sideband at `srcData(1) + (in.imm << 2)` and store data `srcData(0)` | -| `OP_MUL` | low 64 bits of `srcData(0) * srcData(1)` | -| `OP_MULW` | sign-extended low-32-bit `srcData(0) * srcData(1)` | -| `OP_MULU` | low 64 bits of unsigned `srcData(0) * srcData(1)` | -| `OP_MULUW` | sign-extended low 32 bits of unsigned `srcData(0) * srcData(1)` | -| `OP_MAX`, `OP_MIN` | signed 64-bit maximum/minimum | -| `OP_MAXU`, `OP_MINU` | unsigned 64-bit maximum/minimum | -| `OP_BIC`, `OP_BIS` | clear/set the ring-selected `SrcL` bitfield | -| `OP_CTZ` | trailing-zero count of the ring-selected field | -| `OP_SBI` | `0`, with a reduced 1-byte store sideband at `srcData(1) + in.imm` and store data `srcData(0)` | -| `OP_SLL` | `srcData(0) << srcData(1)(5, 0)` | -| `OP_SLLI` | `srcData(0) << in.imm(5, 0)` | -| `OP_SRL` | `srcData(0) >> srcData(1)(5, 0)` | -| `OP_SRA` | `srcData(0).asSInt >> srcData(1)(5, 0)` | -| `OP_SSRSET` | `0`, with no writeback side effect | -| `OP_XORI` | `srcData(0) ^ in.imm` | -| `OP_OR` | `srcData(0) \| SrcR`, including model SrcR modifier and shift fields | -| `OP_ORI` | `srcData(0) \| in.imm` | - -R138 adds model-aligned `OP_CSEL`. `FrontendOperandDecode` maps `srcData(0)` to -`SrcL`, `srcData(1)` to `SrcR`, and `srcData(2)` to `SrcP`; execute therefore -selects `SrcL` when the predicate is nonzero. The row reducer currently admits -the CoreMark frontier shape where `SrcP` is a reduced T/U local source. A -scalar-predicate CSEL row needs a source-2 trace-schema extension before it can -be promoted in the QEMU-shaped reduced-row gate. - -`OP_ADDTPC` uses the `FrontendOperandDecode` `ImmIMM20` path, where the -20-bit immediate is sign-extended and shifted left by 12 before reaching -execute. This matches the model and linker contract for page-relative address -materialization and is intentionally separate from `C.SETRET`, whose compact -form uses `uimm5 << 1` and `pc + imm` return-address semantics. - -The completion row copies identity and control fields from the accepted -`RenamedUop`, fills source register/data fields only for scalar -`OperandClass.P` operands, fills `dst` and `wb` from `uop.dst(0)` plus the -computed result, -exports the same result and destination physical tag on `completeDst*` only for -scalar GPR destinations, and leaves memory/trap fields zero. T/U destinations -remain visible in the completion row for the comparator, but their local -register data path is owned by `ScalarTURenameBridge`, the reduced local-value -overlay in the live top, and later T/U issue owners rather than by the scalar -RF. T/U local sources are consumed internally and suppressed from the -QEMU-shaped source fields. -R375 reuses that same real E-stage source-data rule for replay-load -provenance: ordinary load lookups export only P-class `src0/src1` operand -traces copied from `eSrcData`, while T/U/local sources remain suppressed and -`FRET.STK` RA-load returns keep `loadLookupSourceTraceValid=false`. This -matches LinxCoreModel's RF-return provenance and avoids treating ROB -allocation metadata as source data. -R110 proves this for CoreMark's first `HL.LUI`, which writes architectural tag -`31` as a T destination while scalar RF writeback remains gated off. -R133 proves the same row shape for post-return `OP_ADDTPC`: the ALU already -computes `(pc & ~0xfff) + imm`, while the reduced QEMU extractor now admits -architectural tags `30`/`31` as legal U/T destinations for ADDTPC rows. -R134 adds the high-long `OP_HL_SD_PCR` store sideband observed after that -return packet. The frontend supplies the model split PCR-store offset as -`in.imm`; execute emits no destination/writeback, computes `addr = pc + imm`, -sets `mem.isStore`, writes 8 bytes, and uses `srcData(0)` as store data. The -reduced lane keeps this opcode-specific because the generated HL PCR metadata -still routes these rows through the ALU envelope rather than the full LSU/STQ -path. -R135 admits `OP_CMP_EQI` as a regular destination-producing compare, not a -SETC branch sideband. LinxCoreModel maps `OP_CMP_EQI` to `CalcCmpEQ` with the -signed immediate decoded as source 1, and QEMU lowers it with `setcond EQ`; -the reduced execute result is therefore `1` when `srcData(0) == imm`, else -`0`. The promoted CoreMark row writes architectural `x30/U0`. -R136 carries the following 32-bit `OP_LDI` row when it writes architectural -`x31/T0`. This does not add a new load datapath: the R122 read-only sparse-ELF -lookup already serves `OP_LDI`; the R136 packet only admits the local T -destination shape in the QEMU row reducer while keeping scalar RF side effects -gated to real GPR destinations. The promoted live gate also proved the -preceding condition-false `FRET.STK` RA-load path restores architectural -`x1/sp` to `stackPointerData + imm` even though the visible commit row writes -only `x10/ra`; execute now exposes that restore as a sideband for the reduced -top's SP shadow. The promoted gate captures 1620 raw QEMU rows, extracts 1496 -expected rows, and compares 1094 normalized QEMU/DUT rows with zero mismatches. -R138 unblocks the next CSEL frontier by aligning QEMU, LLVM MC lowering, the -reduced row reducer, and Chisel execute to LinxCoreModel/Sail true-to-`SrcL` -semantics. The Chisel operation is side-effect free and destination-producing; -the trace row still suppresses local T/U sources, so the reducer uses the local -overlay for the observed `SrcP` and `SrcR` local aliases. -R139 adds the first unsigned byte load-immediate row, `OP_LBUI`, from the -post-CSEL CoreMark frontier. LinxCoreModel routes `LBUI` through `CalcLoadAddr` -with `accMemAddr = SrcL + simm12`, and QEMU uses `MO_UB`. The reduced execute -path requests that unscaled byte address, masks the sparse lookup data to 8 -bits, emits `mem.size = 1`, and allows the local T destination tag `31` to feed -the following local-source `ADDW`. The promoted live gate captures 1642 raw QEMU -rows, extracts 1518 expected rows, and compares 1114 normalized QEMU/DUT rows -with zero mismatches. A larger 1660-row probe now fails later at a conditional -marker drain around `pc=0x40005d94`; that is a block-control frontier, not an -`LBUI` load-data mismatch. -R111 proves the same local-source row shape for CoreMark `SLL`: the row reads -T0/U0, writes architectural U tag `30`, emits `0x100000000`, and leaves scalar -source fields invalid to match QEMU. -R112 proves that the same shift family can write either local class in the -reduced trace: the later `SLL` and `SRL` rows write architectural T tag `31`, -while scalar RF side effects remain gated to GPR destinations. -R113 proves `OP_OR` as another local-source row writing U tag `30`, then admits -the immediately following `C.LDI` zero-load row writing T tag `31`. The -reduced memory sideband address is `srcData(0) + uop.imm`; starting in R117, -`FrontendOperandDecode` provides `uop.imm` as signed bits `[15:11]` shifted -left by 3. This remains a prefix gate only; nonzero load data must wait for a -real data-memory/LSU owner. -R114 proves `OP_C_ADD` at `pc=0x4000553c`, where compressed source fields -decode to T0/U0 and the implicit destination writes T0. This is still a -local-source reduced ALU row, not a general compressed ALU expansion. Because -QEMU currently emits that row without `dst`/`wb`, the reducer patches only this -expected row to the model-derived implicit T writeback before comparison. -R115 proves `OP_SRA` at `pc=0x4000553e` and the paired `OP_SLLI` at -`pc=0x40005542`. Both read local T state, write architectural T tag `31`, and -keep scalar RF side effects gated off; `SLLI` is included with `SRA` because -the live frontend emits both slots in the same dense packet. -R117 admits `OP_C_SETC_NE` as a reduced no-writeback compare row. The row -exists to keep the live CoreMark prefix moving through a local/scalar compare -that QEMU emits without destination fields; execute marks it supported and -returns a zero reference result, while the decoded invalid destination keeps -the commit row free of writeback. -R119 extends that row into the reduced conditional-block sideband. When -`OP_C_SETC_NE` completes, `branchConditionValid` pulses and -`branchConditionTaken` is the not-equal comparison of validity-masked source -data. Invalid operands are treated as zero for the decision sideband, matching -the completion-row source suppression policy used by local T/U operands. -R121 adds the matching compact equality compare `OP_C_SETC_EQ` and the 32-bit -`OP_LDI` zero-load row encountered after repeated CoreMark loop trips. -`OP_C_SETC_EQ` shares the no-writeback completion shape and branch sideband, -but the decision is `src0 == src1`. `OP_LDI` is a narrow reduced load bridge: -execute returns the observed zero read data and emits one 8-byte load sideband -at `srcData(0) + (uop.imm << 3)`. This remains a bounded CoreMark prefix -contract; nonzero loads require the real data-memory/LSU owner. -R122 replaces that zero-only load shortcut with an explicit read-only load -lookup owned by the live top and harness. For `OP_C_LDI` and `OP_LDI`, execute -publishes `loadLookupValid/loadLookupAddr` while the row is in E and captures -`loadLookupData` as the result and memory read data. The current live harness -serves that data from the sparse ELF image and returns zero for missing bytes; -this is still not an LSU, cache, store-forwarding, or memory-mutation owner. -R122 also admits the first 32-bit `OP_SETC_LTU` compare at `pc=0x400055e4`. -It is a no-writeback condition row whose branch sideband is the unsigned -comparison `src0 < src1`. -R124 admits the indexed 64-bit store `OP_SD` at `pc=0x400055f2`. The model -and QEMU decode use `SrcL` (`rs1`) as the base, `SrcR` (`rs2`) as the index, -and `SrcD` (`bits[31:27]`) as the store payload. The reduced execute owner -therefore emits a no-writeback 8-byte store sideband with -`addr = srcData(1) + (srcData(2) << 3)` and `wdata = srcData(0)`. -`FrontendOperandDecode` supplies that model order as -`src0=SrcD`, `src1=SrcL`, and `src2=SrcR`. The current CoreMark row has a -local T0 base, visible scalar `x2` index, and local U0 payload, so the -QEMU-shaped completion row projects the visible base/index as source 0/1 while -keeping the local payload internal. This is still a reduced sideband owner, -not a general LSU/STQ path or a scalar-src2 commit-trace schema. -R125 extends the reduced live CoreMark envelope with `OP_SUBI`, compressed -local `OP_C_AND`, a local/scalar `OP_ADD` row, and compressed store-immediate -`OP_C_SDI`. The reducer validates `SUBI` as `src0 - uimm12`, lets 32-bit `ADD` -use encoded local or scalar source fields independently, and applies the same -QEMU trace-gap synthesis used by `C.ADD` to `C.AND` when the QEMU row omits -the implicit T destination/writeback. For `C.SDI`, the compressed source -contract is the encoded base plus signed bits `[15:11] << 3`, with T0 as the -store payload; the Chisel execute row receives that as base on `srcData(0)`, -payload on `srcData(1)`, and emits a no-writeback 8-byte store sideband. This -is still a reduced committed-store sideband, not a full LSU/STQ path. -R118 admits the first ordinary scalar store-immediate row, `OP_SDI`. The C++ -model decodes the 32-bit form as `src0=SrcL` store data, `src1=SrcR` address -base, and `src2=simm12_7_s5_25_7 << 3`; `Store::CalcStoreAddr` computes -`src1 + src2`, and `GetStoreDataSrcIndex` selects source 0 for non-PCR stores. -Linx QEMU's `trans_sdi` matches that contract with data from `SrcL` and -address `SrcR + simm12 * 8`. The reduced execute owner therefore emits a -no-writeback 8-byte store sideband with `addr = srcData(1) + (uop.imm << 3)` -and `wdata = srcData(0)`. The current CoreMark row uses a suppressed local T0 -base and visible scalar x5 store data. -R126 extends the reduced envelope through the first PCR return sequence and -byte store. `LD.PCR` and `HL.LD.PCR` request load data at `pc + imm`, where -the frontend has already decoded the unshifted PCR immediate. `C.SETC.TGT` and -`SETC.TGT` latch a dynamic target from source 0. `FRET.STK` suppresses all -source/destination/writeback fields in the QEMU-shaped row, emits -`next_pc = latchedTarget`, requests a scalar frontend redirect, and clears the -latched target. Ranged `FENTRY` computes the first save address from the saved -register count instead of assuming one saved register. `ADDW` sign-extends the -low 32-bit sum, and `SBI` emits a no-writeback 1-byte store using the unscaled -split immediate and base on source 1. These are still reduced CoreMark-prefix -contracts, not a general LSU or dynamic-control implementation. -R127 extends that contract for return-block cleanup. `FRET.STK` redirects to -an explicit SETC target when one is live, otherwise to the active marker target -provided by the top. `flushValid` kills all pipeline stages and gates -completion/redirect side effects during backend cleanup. `FENTRY` now consumes -the top-owned SP shadow instead of a visible source lane; ranged forms in the -current reduced trace suppress store data rather than reading a synthetic -source that QEMU does not expose. -R128 admits the first 32-bit SETC immediate compare encountered by CoreMark, -`OP_SETC_LTUI` at `pc=0x4000d1e4`. It is a no-writeback condition row: execute -returns zero in the completion payload, asserts the branch-condition sideband, -and compares `srcData(0)` against the decoded unsigned immediate. It does not -claim the full commit-condition storage path. -R129 admits the following `OP_ANDIW` row at `pc=0x4000d210`. The model -calculates the immediate form as `src0 & imm`, truncates the result to -32 bits, and sign-extends it back to 64 bits. The current CoreMark row writes -architectural alias `x30/U0`, so it remains a local-destination completion row -without scalar RF writeback. -R130 admits `OP_MULW` at `pc=0x4000d21a` and the adjacent compressed -`OP_C_SUB` tail at `pc=0x4000d21e`. LinxCoreModel routes `MULW` through the -multicycle group, but the architectural result is still the low-32 product of -source 0 and source 1 sign-extended to 64 bits. The reduced RF/ALU top computes -that result for the bounded CoreMark prefix while preserving the future -ownership boundary: this is not a general multicycle-pipeline replacement. The -following `C.SUB` uses the same implicit-T local writeback contract as -`C.ADD`/`C.AND`; the QEMU trace row omits destination/writeback fields, so the -expected-row reducer synthesizes the `T0` completion from the encoded sources. -R131 extends the same CoreMark packet through immediate logical ALU rows, -word-store immediates, scalar subtraction, and a scalar-result multiply: -`OP_ANDI` at `pc=0x4000d220`, `OP_SWI` at `pc=0x4000d22a` and -`pc=0x4000d23a`, `OP_ORI` at `pc=0x4000d284`, `OP_SUB` at `pc=0x4000d288`, -and `OP_MUL` at `pc=0x4000d2a6`. `SWI` uses the model store-immediate shape -with source 0 as store data, source 1 as base, and the split immediate scaled -by four. The QEMU reducer also now lets ordinary shift and logical rows read -either scalar-visible or local-overlay sources per encoded operand, which is -needed by the scalar-visible `OP_SLL` row at `pc=0x4000d292`. The slice stops -before the richer `FRET.STK` return/load packet at `pc=0x4000d2d4`. -R132 admits that `FRET.STK` return/load packet. The top supplies the latest -SETC condition to execute. While the condition remains true, `FRET.STK` keeps -the R126/R127 redirect-only row shape and does not allocate or write `ra`. -When the condition is known false and the encoded restore range includes -`x10/ra`, execute requests the sparse-memory load at `SP + stacksize - 8`, -emits the QEMU-shaped `dst/wb x10` and load sideband, writes reduced RF tag -`x10`, and redirects to the loaded RA. The decode stage intentionally still -marks `FRET.STK` as no visible destination; the reduced RF write is an -execute-owned macro-template approximation until a full template uop protocol -exists. - -R141 tightens that `FRET.STK` arbitration. A pending SETC target or active -marker fallback target wins when the condition is absent or taken; the -RA-load-return path wins only when there is no target pending or when a valid -condition explicitly says not-taken. This matches CoreMark shapes where the -same restore-range encoding can either loop to a block target or finally load -`ra` from the stack. R141 also promotes the current scalar subset through -model SrcR modifiers for register `ADD/ADDW/SUB/AND/OR`, compact -sign/zero-extension rows, `XORI`, `SSRSET`, signed `SETC_LT`, compact word -stores, and high-long PCR byte/half/word/doubleword stores. - -For reduced `OP_FENTRY`, the completion row intentionally suppresses internal -source fields so it matches QEMU's macro row, while preserving the architectural -SP writeback and one store sideband (`mem.valid`, `mem.isStore`, `mem.addr`, -`mem.wdata`, and `mem.size=8`). The reduced top/harness compares that memory -sideband through the common JSONL comparator. -For reduced `OP_SDI`, the completion row carries `mem.valid`, `mem.isStore`, -`mem.addr`, `mem.wdata`, and `mem.size=8` but leaves `dst`/`wb` invalid. It -does not model store queue drain, cache state, or memory mutation. -For reduced `OP_SWI`, the completion row has the same no-writeback store -shape, but the address is `srcData(1) + (uop.imm << 2)`, the store payload is -`srcData(0)`, and `mem.size=4`. -For reduced `OP_SD`, the completion row has the same no-writeback store shape, -but the address comes from `srcData(1) + (srcData(2) << 3)`, the store payload -comes from `srcData(0)`, and the QEMU-shaped visible source projection exposes -base/index rather than the internal payload-first source order. -For reduced `OP_C_SDI`, the completion row uses the same no-writeback store -shape, with address from the compressed base plus scaled immediate and payload -from the decoded T0 source carried on `srcData(1)`. - -`releaseValid` is intentionally tied to any valid W2 row, not only supported -rows. The reduced issue queue has already marked the row issued when execute -accepted it; an unsupported reduced opcode must still release that resident -queue entry so the top does not deadlock while surfacing `unsupported`. - -`liqReleaseValid` is intentionally separate. A first-pass live load accepted -by LIQ is suppressed from W1/W2 to prevent a duplicate direct completion, but -the issued queue row must still be released. W2 and E1 handoff may coincide, -so collapsing the two identities onto one release port would leave one issued -row resident and eventually prevent the top from becoming idle. - -For R266 load wait-hold, the E-stage load remains resident while -`loadLookupWaitBlocked` is asserted. Older W1/W2 work continues to drain; the -held load does not advance to W1, does not emit completion/release, and keeps -`inReady` low through the existing occupied-E rule. When the wait input drops, -the load recomputes with the now-ready `loadLookupData` and advances normally. -This is a reduced stand-in for `LDQInfo::waitStore`: the top can prevent wrong -retirement on resident store-data waits before a real LIQ/LDQ replay row and -store-unit wakeup path exists. - -R307 also derives `loadLookupReturnSignExtend` from the accepted load opcode. -Signed byte, halfword, and word load classes assert the bit; unsigned and -64-bit load classes leave it low. The reduced top captures this sideband with -the wait-store replay candidate so later replay-return data extraction can -choose the model `SignExtend` behavior without carrying a raw opcode through -the current diagnostic LIQ row. - -R311 derives `loadLookupDst` from `eUop.dst(0)` only while the E-stage load -lookup is valid. The output is disabled as `DestinationKind.None` otherwise. -The sideband is intentionally limited to one destination because the current -reduced scalar load subset returns one GPR result; multi-destination pair, -vector, and tile loads remain future return-payload owners. - -## Timing - -The reduced pipe captures a uop into E when `inValid && inReady`, computes the -result when E advances to W1, and emits completion and the normal release from -W2. There is no downstream completion backpressure yet, so the owning top must -only connect this module to a completion consumer that can accept one -completion when `completeValid` pulses. A live LIQ handoff instead emits the -separate E1 `liqRelease*` identity in its acceptance cycle. - -If `loadWaitHold` is asserted, W1/W2 still drain but E does not advance. The -hold is cleared only by `flushValid` or by the owning top deasserting -`loadLookupWaitBlocked` for the same resident E-stage load. - -With `loadLiqEnable`, an E-stage entry with `loadLiqEligible` instead holds -until `loadLiqAccepted`. That accepted ordinary load is deliberately suppressed -from direct W1, so it cannot race or duplicate the LIQ-owned completion. -`FRET.STK` RA-load returns are not eligible and therefore continue through -direct W1/W2, preserving their coupled RA writeback, SP restore, and redirect. -`inReady` may accept a replacement uop in the acceptance cycle; if allocation -is blocked, the original eligible E-stage metadata remains stable. - -## Flush/Recovery - -`flushValid` clears E/W1/W2 state, clears pending SETC target state, and gates -same-cycle completion, release, branch-decision, redirect, load-lookup, and -unsupported diagnostics. It is a reduced backend cleanup hook for live -CoreMark redirect evidence, not full replay or exception recovery. - -Later execute owners must add recovery age checks, replay, bypass -invalidation, and exception-priority behavior before this module can sit -behind a general speculative issue queue. -The R266 wait-hold path is not a replay mechanism: it does not allocate an -LIQ/LDQ row, remember wait-store identity, or consume store-unit wakeups. - -## Trace/Observability - -`completeRow` is the first Chisel-owned nonzero writeback payload in the -frontend trace lane. It is designed to feed `ROBEntryBank.completeRow` through -`LinxCoreFrontendAluTraceTop` and then the existing commit monitor and -QEMU-shaped comparator. `completeDstPhysValid/Tag/Data` feed -`ScalarGPRFile` in `LinxCoreFrontendRfAluTraceTop`, allowing later -frontend rows to read earlier Chisel writebacks through renamed physical tags. -`completeSrcPhysValid/Tag` are diagnostic sidebands used by the live -CoreMark harness to correlate issue-time source physical tags with the -writeback/rename map when debugging alias or premature-free hazards. -`releaseValid/Bid/Gid/Rid/Stid` and `liqReleaseValid/Bid/Rid/Stid` feed the -two release lanes of `ReducedScalarIssueQueue`, so a normal W2 row and an -LIQ-owned E1 load can each retire their issued residency in the same cycle. -The W2 identity still feeds `ReducedLoadReplayCompletionDrain` in the reduced -top, ensuring a queued replay candidate is drained only by the exact load row -that produced it. - -## Non-vector/tile coverage status - -The operational v0.57 denominator is 547 canonical instruction forms after -excluding 184 vector forms, 30 tile/PTO descriptors, and eight vector-mode -block descriptors. Coverage is layered; do not collapse frontend decode, -parser acceptance, RTL semantics, and cross-stack executable alignment into one -number. Against that denominator: - -- strict frontend decode covers 547/547 forms (100.00%); `XB ACR-ID,C-ID` is - explicit decode-only because it requires the platform CAC/XBINFO table and - exception contract before executable semantics; -- the parser-supported scalar subset is 208/547 forms (38.0256%); -- active dirty candidate RTL semantics cover 207/547 forms (37.8428%); -- 207/547 forms (37.8428%) are cross-stack aligned; `CSEL` matches - Sail, LinxCoreModel, QEMU, LLVM MC lowering, and this Chisel module on - `SrcP, SrcL, SrcR` ordering and true-to-`SrcL` selection. - -The latest scalar packet adds `BIC`, `BIS`, `CTZ`, signed and unsigned -`MIN/MAX`, `MULU/MULUW`, eight HL immediate ALU forms, `HL.LIS/LIU`, and -compressed `C.SLLI/SRLI`. It also repairs `BXS/BXU/CLZ/BCNT` to the -Sail/LinxCoreModel 64-bit ring semantics. QEMU -currently rejects ring-wrapping fields for these bitfield operations and is -therefore not used as the semantic oracle for wrap encodings. - -The final clean QEMU scoped ledger promotes SETC immediate forms into the -aligned numerator: L2=10, L3=10, rejected=0, aggregate parent commit -`960946c8`. The reporter now has zero QEMU executable observation pending -items for that bucket. - -The next uncovered groups are not all ALU-local. Nineteen HL long-offset memory -forms remain pending and are not counted in the aligned numerator until the -general LSU/memory owner can carry them. Atomic forms require an LR/SC/AMO -memory owner. The unsupported dual-destination bucket contains 10 exact -`HL.MUL`, `HL.MULU`, `HL.DIV*`, and `HL.REM*` forms that fail closed until an -explicit result/commit-argument owner exists. `SETC` commit-argument forms -need their commit-condition argument owner; XB CAC/XBINFO forms require the -platform table and exception contract; system/cache/TLB/BCTRL forms require -CSR, trap, maintenance, or block-control owners. `OP_UCVTF` remains -semantic-pending because full ISA coverage needs FRM input, FFLAGS update, -illegal type traps, and `u32/u64 -> f32/f64`; the reduced `ud2fs`/RNE -prototype must not count as aligned. `REV` cannot be copied from QEMU because -its current translator is explicitly simplified to a whole-register byte swap, -whereas Sail specifies byte reversal inside a ring-selected field. - -The completion-backpressure checkpoint at commit `35d2f9c5` validated 48/48 -plus build. Its reusable design rule is that retainer ingress readiness must -come from registered resident occupancy, not from downstream completion-ready -signals, ROB acceptance, or same-cycle dequeue-created capacity; terminal -completion, RF writeback, wakeup, redirect, and release side effects remain -owned by the final `completeFire` boundary. - -## Safe commitWidth=2 benchmark boundary - -The final APPROVE performance closeout for safe `commitWidth=2` does not change -`ReducedScalarAluExecute` semantics. It closes the ROB/top/testbench -side-effect and terminal contract around a wider commit window: ROB stop-after -covers committed stores, traps, block-last rows, and marker rows; the top has -no `sideEffectQueue`; and the benchmark testbench observes both commit lanes. -The required gates were ROB 22/22, top 15/15, and unit test 14/14. - -The approved FishToucher evidence is CoreMark 9,917 cycles / 1,426 commits / -IPC 0.143793485933 with 12 dual-lane commit cycles at -`/Users/zhoubot/linx-isa/runs/linxcore-commitw2-safe-20260725/compare9920-coremark-100k/report/natural_manifest.json` -and Dhrystone 7,916 cycles / 1,150 commits / IPC 0.145275391612 with 12 -dual-lane commit cycles at -`/Users/zhoubot/linx-isa/runs/linxcore-commitw2-safe-20260725/compare7919-dhrystone-100k/report/natural_manifest.json`. -Do not cite prototype manifests from -`/Users/zhoubot/linx-isa/runs/linxcore-commitw2-natural-20260725/` as best -evidence; the 9,917/1,402 and 7,916/1,126 rows are invalid/untrusted because -they predate the final side-effect, terminal, and all-lane harness contract. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute` -- `bash tools/chisel/run_chisel_tests.sh --only ScalarGPRFile` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendAluTraceTop` -- `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r106-coremark-addtpc-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 4 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r107-coremark-hl-call-setret-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 8 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r108-coremark-fentry-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 11 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r110-coremark-hl-lui-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 13 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r111-coremark-sll-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 14 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r112-coremark-sll-srl-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 17 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r113-coremark-or-c-ldi-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 19 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r118-coremark-sdi-42-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 42 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r119-coremark-cond-bstart-50-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 50 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r125-coremark-1024-frontier-probe-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r128-setc-ltui-1477-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1477 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r129-andiw-1479-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1479 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r130-mulw-csub-1481-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1481 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r131-andi-swi-ori-sub-mul-1595-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1595 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r132-fret-stk-load-1597-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1597 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r134-hl-sd-pcr-1611-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1611 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r135-cmp-eqi-1619-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1619 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `python3 tools/chisel/trace_schema_adapter.py --self-test` diff --git a/docs/chisel/modules/execute/ReducedScalarIssuePick.md b/docs/chisel/modules/execute/ReducedScalarIssuePick.md deleted file mode 100644 index e0b01b3c..00000000 --- a/docs/chisel/modules/execute/ReducedScalarIssuePick.md +++ /dev/null @@ -1,145 +0,0 @@ -# ReducedScalarIssuePick - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/execute/ReducedScalarIssuePickSpec.scala` -- Parent owner: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/iex/iex_iq.cpp` - - `model/LinxCoreModel/model/iex/iex.cpp` - - `model/LinxCoreModel/model/iex/pipe/iex_pipe.h` - - `model/LinxCoreModel/model/iex/pipe/alu_pipe.cpp` -- Contract IDs: `LC-IF-CHISEL-IEX-PICK-001`, `LC-IF-CHISEL-XCHK-008` - -## Purpose - -`ReducedScalarIssuePick` is the reduced scalar issue-owner boundary between -queue residency and execute capture. `ReducedScalarIssueQueue` owns row -storage, registered source readiness, release, and compaction. This module owns -the selected-row P1 pick lock, I1 RF read request, I1 read-cancel, I2 execute -handoff, and issue-block diagnostics. - -This is one bank's P1/I1/I2 timing slice. `ScalarIssueFabric` arbitrates shared -RF reads and I2 output across pickers. Bypass selection, load-miss suppression, -and speculative replay remain outside this child. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `selectableMask` | `UInt(depth.W)` | combinational | Queue-owned resident rows that are valid, not issued, and source-ready. | -| input | `entries` | `Vec(depth, RenamedUop)` | with `selectableMask` | Resident queue payloads. The picker reads only the selected row. | -| input | `headValid`, `headIssued` | `Bool` | diagnostic | Queue head state used for block-cause reporting. | -| input | `notIssuedCount` | `UInt(log2Ceil(depth + 1).W)` | diagnostic | Count of resident rows that have not yet issued. | -| input | `flushValid` | `Bool` | pulse | Clears P1/I1/I2 owner state. Parent queue separately clears residency. | -| output | `readValid` | `Vec(3, Bool)` | I1 valid | I1 row's valid source lanes. No RF read is requested in P1. | -| output | `readTags` | `Vec(3, UInt(physRegWidth.W))` | with `readValid` | I1 row's physical source tags. | -| output | `readOperandClass` | `Vec(3, OperandClass)` | with `readValid` | I1 row's source operand classes for scalar RF versus local T/U read selection in the parent top. | -| output | `readRelTag` | `Vec(3, UInt(archRegWidth.W))` | with `readValid` | I1 row's frontend relative tags used for local T/U queue lookup. | -| input | `readData` | `Vec(3, UInt(immWidth.W))` | combinational | RF read data captured when I1 advances to I2. | -| input | `readGrant` | `Bool` | I1 grant | Parent fabric admitted this bank's complete read group. | -| output | `readAttemptValid`, `readFire` | `Bool` | attempt/fire | I1 can accept into I2, and the granted group advanced. | -| output | `readUop` | `RenamedUop` | with `readAttemptValid` | Identity supplied to shared same-STID-age/cross-STID-RR arbitration. | -| output | `issueValid` | `Bool` | valid | I2 row is present and can be offered to execute. | -| input | `issueReady` | `Bool` | ready | Downstream execute can accept the I2 row. | -| output | `issueFire` | `Bool` | pulse | I2 row is accepted by execute. Queue residency is still released later by ALU release. | -| output | `issueUop` | `RenamedUop` | with `issueValid` | I2 row payload for execute. | -| output | `issueSrcData` | `Vec(3, UInt(immWidth.W))` | with `issueValid` | I2-captured RF data to pass into execute. | -| output | `pickFire` | `Bool` | pulse | P1 selected a resident row and parent queue must lock it as in-flight. | -| output | `cancelFire` | `Bool` | pulse | I1 read readiness failed; parent queue must clear the in-flight lock for `cancelIndex`. | -| output | `cancelIndex` | `UInt(log2Ceil(depth).W)` | with `cancelFire` | Queue slot whose in-flight lock is cancelled. | -| output | `i1Valid`, `i2Valid`, `stageBusy` | `Bool` | diagnostic | Reduced issue-owner stage occupancy. | -| output | `selectedValid`, `selectedIndex` | mixed | diagnostic | Oldest selectable row by queue slot. | -| output | `selectedReadReady` | `Bool` | diagnostic | I1 read readiness when I1 is occupied; otherwise the current P1 candidate's read readiness. | -| output | `blockedBySource` | `Bool` | diagnostic | Queue contains non-issued work but no selectable source-ready row. | -| output | `blockedByRead` | `Bool` | diagnostic | I1 row requested RF reads, but readiness was not confirmed and the pick will cancel. | -| output | `blockedByOutput` | `Bool` | diagnostic | I2 row is valid, but execute is backpressuring. | -| output | `blockedByIssued` | `Bool` | diagnostic | Head is issued and no younger row is selectable. | - -## State - -The module owns the reduced issue pipe registers: - -- `i1Valid`, `i1Index`, `i1Uop`: selected P1 row after the queue lock is set. -- `i2Valid`, `i2Uop`, `i2SrcData`: granted RF-read row waiting for execute - acceptance. -- `rrBase`: rotating bank-local start slot used after reducing selectable rows - to one oldest candidate per STID. - -Queue residency and source-ready state remain in `ReducedScalarIssueQueue`; -execute pipeline state remains in `ReducedScalarAluExecute`. - -## Logic Design - -The picker first suppresses every selectable row that has an earlier selectable -peer with the same STID. It then scans the surviving per-STID oldest candidates -from `rrBase`. Pick advances the pointer past the chosen slot. This preserves -oldest-ready order within an STID without comparing unrelated STID ages. - -P1 fires when a candidate exists and I1 can accept a new row. `pickFire` -locks the parent queue slot as in-flight, then the selected payload is captured -into I1 on the clock edge. I1 drives the read tags, operand classes, and -relative tags for the captured row. The parent top may use those sidebands to -route scalar P reads to the RF and local T/U reads to a local-value owner. If -I1 presents `readAttemptValid` only when I2 can accept. A parent `readGrant` -captures all `readData` lanes into I2 atomically. Denial emits -`cancelFire/cancelIndex`; the parent bank clears `inflight` but preserves the -resident row and source readiness. I2 backpressure suppresses a new attempt -instead of creating a false denial. - -I2 owns the valid/ready boundary into `ReducedScalarAluExecute`. `issueValid` -is I2 occupancy, and `issueFire` means execute accepted the I2 row. Issue fire -does not remove the queue entry; later release still comes from the execute -owner by `(bid, rid, stid)`. - -## Model Alignment - -`IssueState::Select` picks in the issue stage and marks only the selected row -issued. The pipe model then separates stages: `P1` is the issue-stage -interface, `I1` generates RF read requests, and `I2` receives RF return and -bypass data before execution proceeds. `IEX::releaseIQEntry` later releases -issued rows from the queue according to the configured release point. - -R88 mirrors the reduced P1/I1/I2 slice of that split: - -1. queue storage exports a selectable mask; -2. this module chooses one oldest selectable row per STID, round-robins among - those candidates in P1, and asks the parent - queue to lock it in-flight; -3. I1 drives RF read tags for the captured row; -4. failed I1 arbitration cancels the in-flight lock without deallocating the - queue row; -5. I2 presents the captured row/data to execute; -6. execute acceptance and later ALU release stay separate. - -Load-miss suppression, bypass selection, wider issue, and speculative replay -remain future issue-owner packets. - -## Timing - -This reduced owner has one P1 pick cycle, one I1 RF-read cycle, and one I2 -execute-accept cycle. It still does not make wakeup visible same-cycle: -`selectableMask` is already based on the parent queue's registered source-ready -state. A row picked in P1 can issue to execute only after the I1 RF read -confirms and the row reaches I2. - -## Flush/Recovery - -`flushValid` clears I1 and I2 state. The parent queue separately clears -resident rows and in-flight locks. I1 read-cancel is intentionally not a flush: -it clears only the locked queue row and leaves residency/source-ready state -intact for a later pick attempt. - -## Trace/Observability - -The parent top exposes P1 pick, I1/I2 stage-valid state, I1 cancel, selected -valid/index, selected-read-ready, and block causes. `blockedByRead` identifies -the I1 cancel condition. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssuePick` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop` -- `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` diff --git a/docs/chisel/modules/execute/ReducedScalarIssueQueue.md b/docs/chisel/modules/execute/ReducedScalarIssueQueue.md deleted file mode 100644 index bcdf6bdc..00000000 --- a/docs/chisel/modules/execute/ReducedScalarIssueQueue.md +++ /dev/null @@ -1,281 +0,0 @@ -# ReducedScalarIssueQueue - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala` -- Child picker: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/execute/ReducedScalarIssueQueueSpec.scala` -- Parent fabric: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala` -- Generated proof: `rtl/LinxCore/tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/iex/iex_iq.cpp` - - `model/LinxCoreModel/model/iex/iex_iq.h` - - `model/LinxCoreModel/model/iex/iex_dispatch.cpp` - - `model/LinxCoreModel/model/iex/iex.cpp` - - `model/LinxCoreModel/model/iex/pipe/alu_pipe.cpp` -- Contract IDs: `LC-IF-CHISEL-IEX-IQ-001`, `LC-IF-CHISEL-XCHK-008` - -## Purpose - -`ReducedScalarIssueQueue` is the resident row bank beneath -`ScalarIssueFabric`. It stores renamed scalar rows, owns registered source -readiness and `inflight`, forms bank-local candidates, and preserves exact rows -across I1 denial until a later retry. The parent fabric owns cross-bank read and -issue arbitration; `ScalarGPRFile` owns P data and non-speculative readiness. - -R85 moves source readiness into registered per-entry state. The queue still -selects only the FIFO head, but RF ready-table changes update resident entries -on the next clock edge rather than feeding directly into same-cycle issue -selection. - -R86 changes reduced selection from head-only to oldest-ready among resident -non-issued entries. Issued in-flight entries remain resident and ineligible, -and their age position is preserved until release compacts the queue. - -R87 splits the selected-row pick/read/confirm logic into -`ReducedScalarIssuePick`. The queue remains the residency, source-readiness, -release, and compaction owner, while the child picker owns oldest-ready -selected-row RF read requests, read-confirm gating, issue fire, and block -diagnostics. - -R88 turns that child into a reduced P1/I1/I2 issue owner. The queue now locks -the selected row at P1 `pickFire`, clears the lock on I1 `cancelFire`, and -keeps the row resident until the existing ALU release path removes it. - -The canonical P-wakeup input closes the model `WakeupIQTag` timing contract. -`ScalarGPRFile.write.fire` updates the global ready table and broadcasts the -same physical P tag to resident IQ rows. Matching source next state updates on -that edge and is pick-visible in the following cycle. A write request without -commit cannot wake the queue. T/U readiness remains separate and scoped. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `inValid` | `Bool` | valid | Rename output row is available for enqueue. | -| output | `inReady` | `Bool` | ready | Queue can accept the row, including one or two same-cycle releases from a full queue. | -| input | `in` | `RenamedUop` | with `inValid` | Renamed scalar row, physical sources, destination physical tag, ROB identity, and decoded sidecars. | -| input | `flushValid` | `Bool` | valid | Clears the reduced queue. | -| input | `releaseValid` | `Bool` | valid | ALU pipe has reached the reduced release point for an issued row. | -| input | `releaseBid` | `ROBID` | with `releaseValid` | Block identity of the issued row to remove. | -| input | `releaseRid` | `ROBID` | with `releaseValid` | ROB identity of the issued row to remove. | -| input | `releaseStid` | `UInt(threadIdWidth.W)` | with `releaseValid` | STID of the issued row to remove. | -| input | `secondaryReleaseValid` | `Bool` | valid | Independent second release lane, used when a live E1 load transfers ownership to LIQ while another row reaches W2. | -| input | `secondaryReleaseBid`, `secondaryReleaseRid`, `secondaryReleaseStid` | mixed | with `secondaryReleaseValid` | Issued-row identity to remove on the independent second release lane. | -| input | `readyMask` | `UInt(physRegCount.W)` | combinational | Reduced scalar RF ready-table snapshot used to initialize and update resident source-ready bits. | -| input | `pWakeupValid`, `pWakeupTag` | valid/tag | committed write fire | Global committed P wakeup from the canonical GPR owner. | -| input | `localTReadyMask`, `localUReadyMask` | `UInt(4.W)` | combinational | Reduced local T/U queue readiness snapshots for source aliases in the live CoreMark prefix. | -| output | `readValid` | `Vec(3, Bool)` | combinational | Valid source lanes for the selected ready row. | -| output | `readTags` | `Vec(3, UInt(physRegWidth.W))` | combinational | Physical source tags for the selected ready row. | -| output | `readOperandClass` | `Vec(3, OperandClass)` | combinational | Source operand class for each selected read lane so the top can choose scalar RF versus local T/U data. | -| output | `readRelTag` | `Vec(3, UInt(archRegWidth.W))` | combinational | Frontend relative T/U source tag for local queue lookup. | -| input | `readData` | `Vec(3, UInt(immWidth.W))` | combinational | Physical RF data for the selected ready row. | -| input | `readGrant` | `Bool` | I1 grant | Parent fabric admitted this bank's complete read group. A low grant on an active attempt cancels only `inflight`. | -| output | `readAttemptValid`, `readFire` | `Bool` | attempt/fire | I1 can advance into I2, and the complete granted read actually advanced. | -| output | `readUop` | `RenamedUop` | with `readAttemptValid` | Full identity used by cross-bank per-STID arbitration. | -| output | `issueValid` | `Bool` | valid | At least one resident non-issued row has all valid sources ready. | -| input | `issueReady` | `Bool` | ready | Downstream execute can accept the selected row. | -| output | `issueUop` | `RenamedUop` | with `issueValid` | Oldest ready non-issued row for execute. | -| output | `issueSrcData` | `Vec(3, UInt(immWidth.W))` | with `issueValid` | RF-sourced operand data for execute capture. | -| output | `enqueueFire` | `Bool` | pulse | Row accepted into the queue. | -| output | `pickFire` | `Bool` | pulse | P1 selected a resident row and the queue locked it in-flight. | -| output | `issueFire` | `Bool` | pulse | I2 row accepted by execute. This does not deallocate queue residency. | -| output | `cancelFire` | `Bool` | pulse | I1 read readiness failed and the selected row's in-flight lock was cleared. | -| output | `releaseFire` | `Bool` | pulse | At least one issued row matched a release identity and was removed. Two distinct rows may retire in one cycle. | -| output | `enqueueDstValid` | `Bool` | pulse | Enqueued row allocated a scalar GPR destination physical tag. T/U destinations do not clear scalar RF readiness. | -| output | `enqueueDstTag` | `UInt(physRegWidth.W)` | with `enqueueDstValid` | Destination physical tag to mark not-ready in the RF. | -| output | `empty`, `full` | `Bool` | diagnostic | Occupancy status. | -| output | `count` | `UInt(log2Ceil(depth + 1).W)` | diagnostic | Queue occupancy. | -| output | `issuedCount`, `notIssuedCount` | `UInt(log2Ceil(depth + 1).W)` | diagnostic | Current in-flight and selectable resident-row counts. | -| output | `headValid` | `Bool` | diagnostic | Queue has a head row. | -| output | `headIssued` | `Bool` | diagnostic | Queue head has already issued and is waiting for release. | -| output | `headPc`, `headOpcode`, `headSrcValidMask`, `headSrcOperandClass`, `headSrcPhysTag`, `headSrcRelTag` | mixed | diagnostic | Head-row payload and source-lane shape used by live CoreMark stall diagnostics. | -| output | `sourceReadyMask` | `UInt(3.W)` | diagnostic | Registered readiness bits for the current head, with invalid lanes treated as ready. | -| output | `allSourcesReady` | `Bool` | diagnostic | Every valid source lane for the head is ready; invalid lanes are ready by definition. | -| output | `pWakeupMatched`, `pWakeupMatchCount` | mixed | diagnostic | Number of valid, non-issued P sources matched by the committed broadcast. | -| output | `selectedValid` | `Bool` | diagnostic | An oldest-ready non-issued row was found for issue. | -| output | `selectedIndex` | `UInt(log2Ceil(depth).W)` | with `selectedValid` | Queue slot selected for RF read and execute issue. | -| output | `selectedReadReady` | `Bool` | diagnostic | Selected row's valid RF read lanes are all ready. | -| output | `i1Valid`, `i2Valid`, `stageBusy` | `Bool` | diagnostic | Reduced issue-owner P1/I1/I2 stage occupancy from `ReducedScalarIssuePick`. | -| output | `blockedBySource` | `Bool` | diagnostic | Queue contains non-issued work, but no resident row is currently source-ready. | -| output | `blockedByRead` | `Bool` | diagnostic | A resident row was selected, but RF read readiness was not confirmed. | -| output | `blockedByOutput` | `Bool` | diagnostic | Selected row is ready but execute is backpressuring. | -| output | `blockedByIssued` | `Bool` | diagnostic | Head row has issued and no younger non-issued row is currently selectable. | - -## State - -- `entries[depth]`: packed FIFO storage for renamed rows. -- `valid[depth]`: per-entry validity. -- `issued[depth]`: reduced in-flight lock. P1 pick sets it, I1 cancel clears - it, and ALU release removes the row. The name stays `issued` to preserve the - existing issue/release accounting surface until a fuller issue-state type is - introduced. -- `srcReady[depth][3]`: registered source-ready state initialized at enqueue - from `readyMask` and updated once per cycle while the row is resident. -- `count`: queue occupancy. -- `ReducedScalarIssuePick.rrBase`: bank-local fairness pointer across the - oldest selectable candidate from every represented STID. - -The depth must be a power of two and greater than one. - -## Logic Design - -The queue accepts one row when `inValid && inReady`. `inReady` is high when the -queue is not full or when an issued row releases in the same cycle, so a full -queue can sustain one release plus one enqueue. - -On enqueue, `enqueueDstValid` is asserted only for `DestinationKind.Gpr`. -`ScalarTURenameBridge` may overlay a T/U destination onto the `RenamedUop` for -model-local register ownership, but that destination must not invalidate a -scalar physical RF entry in this reduced queue/RF composition. - -The queue builds a selectable mask over resident rows. A row is selectable when -it is valid, not already in flight, and every valid source lane's registered -`srcReady` bit is set. `ReducedScalarIssuePick` keeps only the oldest selectable -slot for each STID, then round-robins across those per-STID candidates. It does -not compare RID age between different STIDs. P1 locks the chosen row; an -explicit parent `readGrant` advances the complete read group into I2. Denial -clears the lock and leaves the row in place for retry. - -`readyMask` snapshots the canonical scalar RF ready table. On enqueue, each -scalar P source lane captures `!src.valid || readyMask(src.physTag)`. T and U -source lanes instead sample `localTReadyMask(src.relTag(1,0))` or -`localUReadyMask(src.relTag(1,0))`. While resident, each lane ORs in the same -class-specific readiness predicate on the next clock edge. In parallel, a -committed `pWakeupValid` compares `pWakeupTag` against every valid, non-issued -P source. This explicit next-state path avoids an extra ready-mask polling edge -while preserving the rule that wakeup at N cannot affect selection until N+1. -T/U operands never match the global P broadcast. The RF `readReady` response -remains wired for observability and read-port contract continuity, not as the -direct issue predicate. - -R141 adds one top-specific scalar exception: architectural `x1/sp` sources are -considered ready by the queue because `LinxCoreFrontendFetchRfAluTraceTop` -feeds their data from the reduced `scalarSpValue` shadow rather than from the -ordinary scalar RF readiness table. This prevents model-sized 128-entry -renaming from stalling when `sp` has been renamed to a non-identity physical -tag but the reduced top still owns SP as macro-control state. - -R111 also exposes each selected source lane's `operandClass` and `relTag`. -`LinxCoreFrontendFetchRfAluTraceTop` uses those sidebands to suppress scalar RF -reads for local T/U sources and to feed operand data from the reduced local -T/U overlay. This is a temporary value path for the live CoreMark prefix until -full local-bank data execution replaces it. - -R127 adds head-row diagnostics for PC, opcode, source-valid mask, operand -classes, physical tags, and relative tags. These are diagnostic-only outputs -used by the live QEMU harness to distinguish true local-source waits from -stale local-overlay backpressure. - -Each release lane removes at most one in-flight row whose `(bid, rid, stid)` -matches its release payload. The primary lane has priority if both lanes name -the same row; otherwise two distinct issued rows may be removed in one cycle. -Remaining rows are compacted toward slot 0, preserving FIFO order. In-flight -rows are ineligible for another pick, but they do not force the queue back to -head-only issue: a younger ready non-issued row can be picked while an older -in-flight row waits for W2 release. This follows the C++ model's -select/release split without deallocating on P1 pick or execute acceptance. - -On enqueue, `enqueueDstValid/enqueueDstTag` publish the allocated destination -physical tag so the RF can mark that tag not-ready at queue admission. That -matches the reduced dataflow: later rows may enqueue behind a producer and then -wait at the queue head until the producer's W2 writeback marks the tag ready. - -## Model Alignment - -The C++ model's `IssueState::insert` stores renamed instructions in an issue -queue, `IssueState::Wakeup` marks matching physical sources ready, and -`IssueState::Select` picks a ready row for issue while respecting model -restrictions. `IssueState::ReleaseEntry` removes an already issued row when the -model receives the later release event. - -The reduced Chisel owner preserves the minimum contract needed by the current -RF-backed scalar ALU lane: - -1. renamed rows are stored before execute; -2. source readiness is checked against physical RF state, not per-uop top - fixtures; -3. dependent rows can enqueue before their producer commits; -4. a ready younger row can issue when older resident rows are not selectable; -5. issue preserves the row's ROB identity and renamed sidecars into execute; -6. committed P writeback updates global readiness and matching IQ next state - from one event; -7. T/U local sources use local queue readiness and relative tags rather than - scalar RF physical tags. - -The remaining reduction is execution-class coverage and speculative replay. -The parent fabric now performs live banked I1/I2 arbitration and this bank owns -real cancellation/retry. The scalar slice still lacks the full physical -BRU/AGU/STD/CMD queue layout, two-write-port dispatch, speculative load bypass -repair, and T/U point-to-point qtag wakeup. - -R85 removes the earlier same-cycle RF-readiness-to-issue shortcut. The -committed P-wakeup input now matches `IssueQueue::WakeupIQTag`: it updates the -IQ next state and ready table from one accepted producer event, making wakeup -at cycle N visible to pick at N+1. Speculative replay, -bypass, and T/U qtag routing remain later work. - -R86 implements the first age-selection slice: `IssueState::Select` scans -resident entries, ignores issued entries, and commits the oldest ready -candidate. Chisel preserves that ordering over the compacted queue image. - -R87 introduces an explicit issue-owner child for the reduced P1/I1/I2 split: -queue state computes source-ready candidates, `ReducedScalarIssuePick` owns -pick/read/confirm, and execute/release remains in the ALU owner. - -R88 makes that split stateful. `IssueState::Select` marks the selected entry -issued before the pipe moves it through `p1_inst`, `i1_inst`, and `i2_inst`. -`ALUPipe::runI1` generates RF read requests, `runI2` consumes RF return, and -`ALUPipe::move` queues scalar ALU IQ release only when the I2 row enters -execution. The reduced Chisel queue therefore locks on P1, may cancel the lock -from I1 read readiness failure, emits execute valid from I2, and removes the -row only on the existing ALU release identity. - -## Timing - -The queue is combinational on selectable-mask generation, release match, and -committed P-tag matching, and registered on enqueue, source-ready update, P1 -lock, I1 cancel, release, and flush. RF ready-table and committed wakeup updates -do not directly affect the current cycle's selection. `readGrant` is consumed -only when I2 can accept; denial clears the in-flight lock, while I2 backpressure -holds I1 without manufacturing a cancellation. - -The parent fabric now banks wakeup/select, issued/in-flight tracking, and -release. Wakeup still cannot let a newly woken row win selection in the same -cycle. - -The bank also publishes read-only resident control and store frontier views to -the parent. It does not surrender row ownership: BRU plus Linx `FRET.STK` -classification lets the fabric block younger same-STID control crossing, and -store publication lets the fabric preserve oldest-store issue across banks. -Both remain resident through exact release. - -## Flush/Recovery - -`flushValid` clears the queue pointers, validity, and count. It does not -restore RF readiness, rename maps, ROB rows, or speculative checkpoints; those -remain owned by existing recovery and future issue/ready-table packets. - -## Trace/Observability - -The parent `LinxCoreFrontendRfAluTraceTop` exposes enqueue, P1 pick, I1 cancel, -I2 issue, release, count, issued/not-issued count, head-valid, head-issued, -head payload/source-lane shape, source-ready mask, selected-valid/index, -selected-read-ready, I1/I2 stage valids, source-block, read-block, -issued-block, and output-block diagnostics. -The Verilator fixture drives three dependent scalar rows, enqueues all rows -before draining commits, and compares the resulting commit rows against -QEMU-shaped reference data. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssuePick` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop` -- `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r111-coremark-sll-tu-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 14 --allow-block-markers --max-seconds 8 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf` -- `python3 tools/chisel/trace_schema_adapter.py --self-test` -- `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` -- `bash tools/chisel/build_chisel.sh` -- `bash tools/chisel/run_chisel_verilator_lint.sh` diff --git a/docs/chisel/modules/execute/ReducedScalarWritebackArbiter.md b/docs/chisel/modules/execute/ReducedScalarWritebackArbiter.md deleted file mode 100644 index 115d6c24..00000000 --- a/docs/chisel/modules/execute/ReducedScalarWritebackArbiter.md +++ /dev/null @@ -1,89 +0,0 @@ -# ReducedScalarWritebackArbiter - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarWritebackArbiter.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterSpec.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/iex/iex.cpp`: `IEX::setMemData` - - `tools/LinxCoreModel/model/iex/iex.cpp`: `IEX::setMemWakeup` - - `tools/LinxCoreModel/model/iex/iex_iq.cpp`: `IssueQueue::WakeupIQTag` - - `tools/LinxCoreModel/model/iex/rtable.cpp`: `ReadyState::SetRegReadyTable` -- Contract IDs: `LC-IF-CHISEL-IEX-WB-001`, `LC-IF-CHISEL-LSU-REPLAY-RETURN-014` - -## Purpose - -`ReducedScalarWritebackArbiter` owns the single reduced scalar RF write-port -choice between ordinary execute completion and the future replay-return GPR -writeback path. - -The current top wires the replay side from the W2 -`LoadReplayReturnPipeW2WritebackArbiterInput` boundary. R362 drives -`replayEnable` from the shared W2 side-effect live-control owner; that owner's -request remains false, so the arbiter still preserves execute-only RF mutation -while proving the final replay writeback handoff path. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `executeValid` | `Bool` | pulse | Ordinary ALU/load execute completion has a scalar physical GPR result. | -| input | `executeTag` | `UInt(physRegWidth.W)` | with `executeValid` | Physical destination tag for execute writeback. | -| input | `executeData` | `UInt(dataWidth.W)` | with `executeValid` | Data for execute writeback. | -| input | `replayEnable` | `Bool` | static/dynamic gate | Permits replay-return writeback candidates to use the RF port. | -| input | `replayValid` | `Bool` | pulse | Replay-return path has a GPR writeback candidate. | -| input | `replayTag` | `UInt(physRegWidth.W)` | with `replayValid` | Physical destination tag for replay writeback. | -| input | `replayData` | `UInt(dataWidth.W)` | with `replayValid` | Data for replay writeback. | -| output | `writeValid` | `Bool` | pulse | Selected RF write-port valid. | -| output | `writeTag` | `UInt(physRegWidth.W)` | with `writeValid` | Selected physical destination tag. | -| output | `writeData` | `UInt(dataWidth.W)` | with `writeValid` | Selected writeback data. | -| output | `selectedExecute` | `Bool` | diagnostic | Execute completion won the port. | -| output | `selectedReplay` | `Bool` | diagnostic | Replay completion won the port. | -| output | `replayBlockedByDisabled` | `Bool` | diagnostic | A replay candidate was present while replay writeback was disabled. | -| output | `replayBlockedByExecute` | `Bool` | diagnostic | A replay candidate was present but execute used the port. | - -## Logic Design - -The LinxCoreModel splits load-return side effects across several owners: -`IEX::setMemData` copies returned load data into ROB destination state, -`IEX::setMemWakeup` decides when a returned memory request has enough real -responses to wake dependents, `IssueQueue::WakeupIQTag` fans the wakeup through -issue queues and calls `SetRegReadyTable`, and `ReadyState::SetRegReadyTable` -marks the destination ready. The reduced Chisel lane still has one scalar RF -write port, so the replay-return data side effect must arbitrate with ordinary -execute completion before it can become live. - -The arbiter is combinational: - -- execute writeback always has priority; -- replay can write only when `replayEnable && replayValid && !executeValid`; -- disabled replay candidates are reported without mutating outputs; -- blocked same-cycle replay candidates are reported when execute owns the port; -- stale output tag/data fields are zero when no source is selected. - -In `LinxCoreFrontendFetchRfAluTraceTop`, `replayValid` is the W2 writeback -arbiter-input candidate valid, and `replayTag`/`replayData` are the same W2 -boundary's live-gated write fields. Because `replayEnable` remains false -through the shared W2 live-control owner, candidate rows cannot select the RF -port until W2 writeback, resolve, wakeup, clear/refill, and replay-row -lifecycle mutation are promoted together. - -## Timing - -No state is stored in the arbiter. The selected output drives -`ScalarGPRFile.write(0)` request and commit together. Accepted `write.fire` -performs RF/ready mutation and broadcasts committed P wakeup on the rising -edge. - -## Trace/Observability - -`LinxCoreFrontendFetchRfAluTraceTop` exposes the selected RF write as the -existing `rfWrite*` signals and publishes replay-specific arbitration -diagnostics under `reducedLoadReplayLiqWritebackArbiter*`. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarWritebackArbiter` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r314-replay-writeback-arbiter-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r362-replay-pipe-w2-writeback-rf-arbiter-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` diff --git a/docs/chisel/modules/execute/ScalarGPRFile.md b/docs/chisel/modules/execute/ScalarGPRFile.md deleted file mode 100644 index fd842caf..00000000 --- a/docs/chisel/modules/execute/ScalarGPRFile.md +++ /dev/null @@ -1,83 +0,0 @@ -# ScalarGPRFile - -## Source Mapping - -- Chisel: `chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala` -- Tests: `chisel/src/test/scala/linxcore/execute/ScalarGPRFileSpec.scala` -- Generated issue proof: `tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh` -- Model: `model/LinxCoreModel/model/iex/iex_rf.cpp`, `RegFile::recieveWFReqFromRT`; - `model/LinxCoreModel/model/iex/iex_iq.cpp`, `IssueQueue::WakeupIQTag`; - `model/LinxCoreModel/configs/core.toml`, `ggpr_count` - -## Contract - -`ScalarGPRFile` is the canonical scalar physical GPR data and non-speculative -P-tag ready-table owner. Its capacity, read-port count, and write-port count -are independent parameters. The default 128 physical entries match -LinxCoreModel `ggpr_count`; exactly 24 architectural identity tags reset ready. - -A write port has two phases: - -1. `requestValid` reserves/arbitrates the candidate tag and produces `ready`. -2. `commit` authorizes state mutation; `fire` is request, commit, and ready. - -Request without commit never changes data or readiness. This distinction lets -a retained W2 producer hold a port candidate while ROB resolve or another -required side effect is blocked. - -## Interface - -| Signal | Contract | -|---|---| -| `readValid/readTag` | Parameterized combinational physical-tag reads. | -| `readData/readReady` | Registered data and non-speculative readiness; an invalid read request is ready by convention. | -| `initValid/initTag/initData` | Bring-up initialization of one identity-mapped tag. | -| `clearValid/clearTag` | Rename allocation marks one destination not-ready. | -| `write[*].requestValid/tag/data` | Candidate write payload used for port and same-tag arbitration. | -| `write[*].ready` | The port request has no higher-priority same-tag request. | -| `write[*].commit/fire` | Commit authorization and accepted state mutation. | -| `readyMask` | Current P-tag ready table consumed by issue queues. | -| `clearWriteCollision` | Rename clear and committed write target one tag in the same cycle. | -| `duplicateWriteCommit` | More than one committed port targets one tag. | -| `protocolError` | Non-unique or incoherent state mutation. | - -## Arbitration And Timing - -Lower-numbered ports have same-tag priority. Independent tags may commit in -the same cycle. A one-port configuration serializes every producer; additional -ports increase bandwidth without changing physical identity width. - -Reads observe current registered state. Clear and committed writes update on -the rising edge. A committed write stores data and sets readiness together, so -the same `write.fire` event also drives the live issue queue's P-wakeup input. -Matching valid, non-issued P sources capture readiness on that edge and may be -picked in the following cycle. Request without commit drives no wakeup. There -is no same-cycle pick effect. - -Clear/write collision and duplicate committed writes are errors rather than -implicit priority rules. Reusing a physical tag before its prior producer has -finished is an ownership failure that must be fixed at rename/recovery. - -## Scope - -This module owns global scalar GPR (`P`) state only. T/U local-link banks use -PE/STID-scoped storage and qtag point-to-point wakeup. Vector, predicate-mask, -stack, and architectural-control state are separate owners. No ARM register, -condition-code, exception-level, or exclusive-monitor behavior is present. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ScalarGPRFileSpec` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueueSpec` -- `bash tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh` -- `bash tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` - -The generated probe proves request hold without mutation, same-tag external -priority, independent dual-port writes, scalar data retention, P-tag readiness, -and exact ROB completion from one W2 acceptance. - -The generated issue probe proves that an uncommitted request leaves a resident -dependent row blocked, while committed writeback updates data, P readiness, -and exactly matching IQ source next state together. The row becomes -pick-visible on the next cycle and reads the committed value through the -canonical GPR owner. diff --git a/docs/chisel/modules/execute/ScalarIssueFabric.md b/docs/chisel/modules/execute/ScalarIssueFabric.md deleted file mode 100644 index 93390278..00000000 --- a/docs/chisel/modules/execute/ScalarIssueFabric.md +++ /dev/null @@ -1,152 +0,0 @@ -# ScalarIssueFabric - -## Source Mapping - -- Fabric: `chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala` -- Candidate policy: `chisel/src/main/scala/linxcore/execute/ScalarIssueCandidateArbiter.scala` -- Resident bank: `chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala` -- P1/I1/I2 child: `chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala` -- Retained redirect frontier: `chisel/src/main/scala/linxcore/execute/ScalarIssueExternalControlFence.scala` -- Parameters: `chisel/src/main/scala/linxcore/common/CoreParams.scala` -- Unit tests: `chisel/src/test/scala/linxcore/execute/ScalarIssueFabricSpec.scala` -- Generated proof: `tools/chisel/run_chisel_scalar_issue_fabric_probe.sh` -- Golden contract: `docs/architecture/microarchitecture.md` - -## Purpose - -`ScalarIssueFabric` is the live scalar ALU residency and shared-issue owner. It -replaces the former one-queue composition in both RF/ALU tops with multiple -independent resident banks while preserving the existing aggregate top -interface for commit, recovery, and trace tooling. - -The packet intentionally implements the scalar ALU slice, not the complete -eight-class physical IQ layout. The default two banks represent the primary -ALU queue and its shared spill path. BRU, AGU, STD, and CMD class routing and -two-write-port S1/S2 dispatch remain separate integration work. - -## Parameters - -| Parameter | Constraint | Meaning | -|---|---|---| -| `depth` | Power of two; divisible by `bankCount` | Total resident scalar rows across all banks. | -| `bankCount` | Power of two greater than one | Number of independently resident scalar banks. | -| `depth / bankCount` | At least two | Rows owned by each child bank. | -| `ScalarBackendParams.scalarIssueBanks` | Same as `bankCount` | Live-top bank configuration. | -| `ScalarBackendParams.gprReadPorts` | At least three | Physical scalar RF read ports; one granted uop receives three source lanes atomically. | - -## Ownership - -- Each `ReducedScalarIssueQueue` owns its rows, source readiness, and - `inflight` bits. -- The fabric owns enqueue-bank choice and the shared I1 and I2 arbitration - pointers. -- `ScalarGPRFile` remains the only scalar P data and non-speculative readiness - owner. -- Release and committed P wakeup are broadcast to every bank because their - exact resident owner is not known at the top boundary. -- Resident banks publish control and store frontier rows; the fabric owns only - shared admission policy and never mutates those rows. - -## Enqueue - -One live rename row is routed to the non-full bank with the smallest current -occupancy. Equal occupancy selects the lower physical bank index. The row is -written only when the selected child reports `inReady`; aggregate `inReady` -does not claim capacity from a different bank after selection. - -This policy matches the C++ model's least-occupied lane placement for the -current one-uop dispatch surface. It does not claim the golden two-write-port -same-cycle dispatch contract. - -## Candidate Policy - -Every bank forms at most one candidate for each represented STID by retaining -the oldest selectable queue slot for that STID. It then round-robins across -those per-STID candidates. The fabric applies the same policy across bank -candidates: - -1. candidates with the same STID may be compared by wrap-aware RID age; -2. candidates with different STIDs are never age-compared; -3. round-robin state chooses among surviving STID candidates; -4. fairness advances only when the selected transaction advances. - -An invalid candidate RID is a protocol error. It must not alias RID zero or -silently receive a grant. - -## Control And Store Frontiers - -I1 admission is additionally constrained by two per-STID ordering frontiers: - -- a younger row cannot pass an older resident BRU or Linx `FRET.STK` control - row; -- a younger store cannot pass an older resident store, while loads and - non-memory work remain eligible under their normal dependency rules. - -Both comparisons use wrap-aware RID age only after STID equality. Resident -control ownership lasts through exact `(STID, BID, RID)` release. A redirecting -`FRET.STK` transfers that exact identity to `ScalarIssueExternalControlFence` -at W2, and the full live top retains it until central recovery accepts cleanup. -This closes the release-to-recovery gap without globally flushing older issue -or split-store ownership. - -The bank/arbitration mechanism is ISA-neutral. Classifying `FRET.STK` and -retaining its Linx block redirect identity are explicit Linx integration; no -ARM return state, flags, barriers, or exception-level behavior is imported. - -## I1 Read Admission - -Each bank may hold one P1-selected uop in I1. When multiple banks attempt I1 in -the same cycle, `ScalarIssueCandidateArbiter` grants one complete three-lane -read group. The winner captures all returned operand data and advances to I2. -Every loser emits `cancelFire`, clears only its bank-local `inflight` bit, and -keeps the row resident for a later pick. - -If I2 cannot accept a bank's I1 row, that bank does not present a new read -attempt and therefore cannot be falsely cancelled by arbitration. Partial -source grants are forbidden. - -The C++ model currently services all scalar read requests and has no scalar RF -denial. Finite Chisel ports are an ISA-neutral physical enhancement; generated -commit comparison proves cancellation and retry remain architecturally -invisible. - -## I2 Issue Arbitration - -Every bank has independent I2 residency. If execute backpressure allows more -than one bank to retain an I2 row, the second shared arbiter chooses one using -the same same-STID age and cross-STID fairness rules. Only the selected bank -observes `issueReady`. Unselected I2 rows remain stable. - -I2 acceptance does not deallocate the resident bank row. Exact later release -by `(STID, BID, RID)` removes it. - -## Verification - -Run: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ScalarIssueCandidateArbiter -bash tools/chisel/run_chisel_tests.sh --only ScalarIssueFabric -bash tools/chisel/run_chisel_scalar_issue_fabric_probe.sh -``` - -The generated Verilator probe proves: - -- same-STID oldest-RID selection; -- cross-STID RR service without cross-lane RID comparison; -- least-occupied bank spill; -- wakeup at N and simultaneous bank picks at N+1; -- one atomic I1 winner and one cancellation under contention; -- retained-row retry and later read grant; -- two independently resident I2 rows under execute backpressure; -- oldest-first I2 issue and preserved operand data. -- younger same-STID control and store blocking through exact release; -- unrelated-STID progress while another STID owns a control frontier. - -CoreMark and live top comparisons are required as architectural no-regression -evidence. Nonzero fabric counters are workload-activation evidence only when -the full RF/ALU top, rather than the reduced commit-only top, generated them. -The R667 full-path CoreMark probe activates control and store frontiers and -passes the original banked-issue redirect divergence. It later stops at the -pre-existing reduced-store condition where a full STQ blocks ready STD updates -behind STA insertion; that STA/STD arbitration repair is a separate LSU packet. diff --git a/docs/chisel/modules/frontend/BfuBodyCutPredictor.md b/docs/chisel/modules/frontend/BfuBodyCutPredictor.md index ecbe1d7b..4aa46c29 100644 --- a/docs/chisel/modules/frontend/BfuBodyCutPredictor.md +++ b/docs/chisel/modules/frontend/BfuBodyCutPredictor.md @@ -66,11 +66,12 @@ The affected top-level replay also passes with this module in the path. R153 uses resolved geometry for cold body-end cuts and trains a local body window for later header-visible cuts without allowing forward/fallthrough `BSTART` rows to clip the body: -`BUILD_DIR=generated/r153-local-body-window-4000-rtl-replay-v6 +historical evidence only (no current runnable equivalent): `BUILD_DIR=generated/r153-local-body-window-4000-rtl-replay-v6 FETCH_QEMU_TRACE=generated/r153-next-frontier-4000-qemu-probe/traces/qemu.live.raw.jsonl FETCH_QEMU_MAX_ROWS=0 FETCH_QEMU_ALLOW_BLOCK_MARKERS=1 FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY=1 FETCH_ELF=tests/benchmarks/build/coremark_real.elf -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh`Provenance: source commit a5fcc91113af69f650cd1915aa007c70a1074ca4. + compares 3280 normalized QEMU/DUT rows with zero mismatches. diff --git a/docs/chisel/modules/frontend/BfuLocalBodyWindow.md b/docs/chisel/modules/frontend/BfuLocalBodyWindow.md index 9e07f3da..53a0fee2 100644 --- a/docs/chisel/modules/frontend/BfuLocalBodyWindow.md +++ b/docs/chisel/modules/frontend/BfuLocalBodyWindow.md @@ -75,6 +75,9 @@ bash tools/chisel/run_chisel_tests.sh --only BfuLocalBodyWindow The R153 top-level replay also passed after integrating this module with the resolved body-end fallback: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash BUILD_DIR=generated/r153-local-body-window-4000-rtl-replay-v6 \ FETCH_QEMU_TRACE=generated/r153-next-frontier-4000-qemu-probe/traces/qemu.live.raw.jsonl \ @@ -84,6 +87,8 @@ FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY=1 \ FETCH_ELF=tests/benchmarks/build/coremark_real.elf \ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 916be29f5138cf997ddb0fd6c114fb6e32ff1ba8. + That replay compared 3280 normalized rows with zero mismatches and reported 483 BFU static/external geometry matches. diff --git a/docs/chisel/modules/frontend/BfuPendingRuntimeBodyEndCandidate.md b/docs/chisel/modules/frontend/BfuPendingRuntimeBodyEndCandidate.md index f9a95dea..9ae5535d 100644 --- a/docs/chisel/modules/frontend/BfuPendingRuntimeBodyEndCandidate.md +++ b/docs/chisel/modules/frontend/BfuPendingRuntimeBodyEndCandidate.md @@ -78,6 +78,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop R157 generated-RTL replay gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash BUILD_DIR=generated/r157-promoted-runtime-source-4000-rtl-replay \ FETCH_QEMU_TRACE=generated/r153-next-frontier-4000-qemu-probe/traces/qemu.live.raw.jsonl \ @@ -87,6 +90,8 @@ FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY=1 \ FETCH_ELF=tests/benchmarks/build/coremark_real.elf \ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit e1b0611e3772ea326a530aca3e58333bb178dfba. + The R157 replay compared 3280 normalized QEMU/DUT rows with zero mismatches and reported zero pending-candidate replay mismatches. Delayed promoted-runtime diff --git a/docs/chisel/modules/frontend/BfuRuntimeBodyEndOracle.md b/docs/chisel/modules/frontend/BfuRuntimeBodyEndOracle.md index 38e3585d..df25379e 100644 --- a/docs/chisel/modules/frontend/BfuRuntimeBodyEndOracle.md +++ b/docs/chisel/modules/frontend/BfuRuntimeBodyEndOracle.md @@ -85,6 +85,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop R157 generated-RTL replay gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash BUILD_DIR=generated/r157-promoted-runtime-source-4000-rtl-replay \ FETCH_QEMU_TRACE=generated/r153-next-frontier-4000-qemu-probe/traces/qemu.live.raw.jsonl \ @@ -94,6 +97,8 @@ FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY=1 \ FETCH_ELF=tests/benchmarks/build/coremark_real.elf \ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit e7f0f23d1fdf973e68ddff36e150d4d1e4a57ff4. + The R157 replay compared 3280 normalized QEMU/DUT rows with zero mismatches and reported: diff --git a/docs/chisel/modules/frontend/F4DenseSlotQueue.md b/docs/chisel/modules/frontend/F4DenseSlotQueue.md index 67b34fe3..6998998b 100644 --- a/docs/chisel/modules/frontend/F4DenseSlotQueue.md +++ b/docs/chisel/modules/frontend/F4DenseSlotQueue.md @@ -125,8 +125,8 @@ on a single-instruction response window. - `bash tools/chisel/run_chisel_tests.sh --only FrontendFetchPacketSource` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `BUILD_DIR=generated/r102-default-fetch-rf-alu-trace-top-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r102-dense-qemu-elf-xcheck --elf generated/r102-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` +- historical evidence only (no current runnable equivalent): `BUILD_DIR=generated/r102-default-fetch-rf-alu-trace-top-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit d56ea4f505b0e4db9dcd81604e8fdd19bf1ce965. +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r102-dense-qemu-elf-xcheck --elf generated/r102-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf --expected-rows 0 --capture-rows 5 --allow-block-markers --max-seconds 5` Provenance: source commit d56ea4f505b0e4db9dcd81604e8fdd19bf1ce965. R102 evidence records both generated-RTL cross-check manifests as `status: "pass"`, `compared_rows: 3`, and `mismatch_count: 0`. diff --git a/docs/chisel/modules/frontend/FrontendDecodeStage.md b/docs/chisel/modules/frontend/FrontendDecodeStage.md index 7bba5d9e..00495221 100644 --- a/docs/chisel/modules/frontend/FrontendDecodeStage.md +++ b/docs/chisel/modules/frontend/FrontendDecodeStage.md @@ -138,7 +138,7 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Cross-check smoke: ```bash -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_verilator_lint.sh ``` diff --git a/docs/chisel/modules/frontend/LinxCoreIfu.md b/docs/chisel/modules/frontend/LinxCoreIfu.md index cc693473..e413a401 100644 --- a/docs/chisel/modules/frontend/LinxCoreIfu.md +++ b/docs/chisel/modules/frontend/LinxCoreIfu.md @@ -77,7 +77,7 @@ twice while multiple cachelines are in flight. ## Redirect and Epoch Ownership -`IfuRedirectArbiter` is the sole canonical epoch allocator. Proposal priority +`linxcore.ifu.IFURecovery` wraps the sole canonical epoch allocator. Proposal priority is: ```text @@ -97,10 +97,12 @@ when accepted. The returned canonical prune restores the request-owned B-F0 GHR and complete RAS snapshots, then applies each delta once. ITLB miss carries unkeyed GHR/RAS restore actions so B-SIDE can use the trigger row or oldest killed snapshot; start carries explicit GHR/RAS reset. -`IfuBackendFeedbackBridge` constructs backend BRU recovery with the retained -mispredict row key plus actual conditional and RAS deltas. The accepted event -still enters through `backendRedirect`; the bridge never bypasses canonical -epoch allocation. +`linxcore.ifu.IFUBackendFeedback` constructs backend BRU recovery with the +retained mispredict row key plus actual conditional and RAS deltas. The +accepted event still enters through `backendRedirect`; the bridge never +bypasses canonical epoch allocation and has no direct IEX control port. The +public `IFU` shell does not instantiate this queue without a live OOO-authored +producer. Non-branch OOO exception/nuke/debug/CTU recovery uses the typed `OooRecovery` reason. It follows the same canonical epoch owner and broadcast path; only the proposal source and prune metadata differ. @@ -134,9 +136,10 @@ The canonical production owner graph is deliberately small: | Boundary | Production owner | |---|---| | I-SIDE | `ISideF0PcSelect` through `ISideF4Predecode`, `ISideITLB`, `ISideL1I`, `ISideFetchMissTable`, `ISideLineContextQueue` | -| B-SIDE | `BSidePredictionPipeline`, `BSideHistoryQueue` | +| B-SIDE | `linxcore.ifu.BSide` over `BSidePredictionPipeline`, `BSideHistoryQueue` | | Join and queue | `IfuPredictionJoin`, `InstructionBuffer`, `D1DecodeGroupGather` | -| External transport | `IfuLineMemoryBridge`, `IfuBackendFeedbackBridge` | +| Recovery and feedback | `linxcore.ifu.IFURecovery`, `linxcore.ifu.IFUBackendFeedback` | +| External transport | `IfuLineMemoryBridge` | | Production composition | `LinxCoreComposition` | The historical body-geometry helpers were renamed from migration-era @@ -205,6 +208,15 @@ checkpoint collision, I-F3 rejects a continuation collision despite matching transaction/STID/epoch, B-F4 keeps long-TAGE above static fallback, and non-conditional resolutions do not train BIM/TAGE. +The Loop 6 public-boundary packet additionally proves that the new +`linxcore.ifu` B-SIDE wrapper preserves B-F4 provider rank and stale-training +rejection, `IFURecovery` gives backend typed recovery priority over a held +prediction correction while retaining redirect backpressure, `IFUBackendFeedback` +pairs mispredict training with backend recovery atomically and exposes no IEX +control port, and public `IFU` W2/W4/W6/W8 elaboration contains the explicit +B-SIDE and redirect-recovery boundaries without changing the fixed-64-bit IFU-to-CTU +payload. + Run: ```bash diff --git a/docs/chisel/modules/lsu/LoadForwardResultRetainer.md b/docs/chisel/modules/lsu/LoadForwardResultRetainer.md new file mode 100644 index 00000000..fe7193dd --- /dev/null +++ b/docs/chisel/modules/lsu/LoadForwardResultRetainer.md @@ -0,0 +1,34 @@ +# LoadForwardResultRetainer + +## Purpose + +`LoadForwardResultRetainer` is the bounded owner between registered STQ E4 +results and the canonical `LoadInflightQueue` apply seam. It prevents a valid +asynchronous forwarding result from disappearing when recovery or another +exact-row writer temporarily owns the LIQ cycle. + +## Contract + +- Input is ready/valid traffic carrying the complete + `LoadInflightForwardResult` payload. +- The FIFO head remains stable while LIQ reports `sinkRetryRequired`. +- `sinkAccepted` and `sinkRejectedPermanent` are terminal decisions and each + dequeues exactly one head. +- Terminal and retry decisions are mutually exclusive; a decision without a + resident head is a sticky protocol error. +- Hard flush clears buffered results. Typed precise recovery is a retryable + LIQ decision, so the exact result survives the recovery cycle and is then + accepted or rejected stale against post-recovery state. + +The module owns only result transport. It does not own LIQ rows, STQ rows, +load attempts, recovery selection, or E4 classification. + +## Verification + +```bash +bash tools/chisel/run_chisel_tests.sh --only LoadForwardResultRetainer +bash tools/chisel/run_chisel_tests.sh --only LoadAttemptBinding +``` + +The directed tests prove retry retention, exact acceptance drain, permanent +stale drain, recovery classification, and clean protocol diagnostics. diff --git a/docs/chisel/modules/lsu/LoadInflightQueue.md b/docs/chisel/modules/lsu/LoadInflightQueue.md index 0661bf21..e1c63be6 100644 --- a/docs/chisel/modules/lsu/LoadInflightQueue.md +++ b/docs/chisel/modules/lsu/LoadInflightQueue.md @@ -87,6 +87,24 @@ row reuse reject without mutation. The sidecar is copied into the LHQ/ResolveQ record and terminal return path but is never used for LSU ordering or replay selection. +I0.15c-b3b adds the production external forwarding-result apply seam. With +`useExternalForwardResult=true`, the LIQ elaborates without the compatibility +`LoadForwardPipeline` or its abstract store CAM. A result carries the complete +classified E4 payload plus `{canonical loadId, attempt, returnPipeIndex}`. The +row mutates only when all three identities match the resident row, the row owns +one accepted launch through `forwardPending`, no flush is active, and no +competing row mutation wins that cycle. Stale row reuse, stale attempts, +cross-pipe responses, pick-only `Repick` rows, and duplicate returns are typed +as permanent stale results. Recovery and exact-row mutation conflicts are +typed as retryable owner conflicts. Every rejection leaves row data unchanged. + +Compatibility mode remains the default for existing standalone LSU tops. It +captures the same exact identity at launch and routes the old local forwarding +pipeline through the common apply logic, so internal and external modes no +longer maintain separate E4 row-mutation implementations. `forwardPending` is +owned by the canonical LIQ row: launch sets it; the first accepted exact result +or recovery clears it. + This packet turns the standalone forwarding pipeline into reusable row state without taking ownership of full LDQ/LIQ recovery, miss-queue ownership, ready-table update, issue wakeup fanout, L2/CHI response queues, or @@ -143,6 +161,28 @@ resident row, even when a later slot is free. The queue derives the forwarding query from the resident row address, size, tile bit, and `(youngestStoreId, youngestStoreLsId)` snapshot. +### Exact External Forwarding Result + +| Signal | Description | +|---|---| +| `forwardResultValid` / `forwardResult` | Presents one classified E4 result with exact canonical row, attempt, and physical return-pipe identity. The producer retains a transiently blocked result until `...Accepted` or handles a typed permanent rejection. | +| `forwardResultAccepted` | The exact resident row owns a pending launch and will apply the result this cycle. | +| `forwardResultRejected` | No row mutation occurred for the presented result. | +| `forwardResultRejectedByLoadId` | The canonical slot-plus-wrap lease is malformed, out of range, stale, or nonresident. | +| `forwardResultRejectedByAttempt` | The row lease matched but the producer-qualified attempt did not. | +| `forwardResultRejectedByPipe` | Row and attempt matched but the physical return pipe did not. | +| `forwardResultRejectedByLifecycle` | No accepted launch is pending, the result is a duplicate, recovery is active, or another exact row mutation owns the cycle. | +| `forwardResultRejectedPermanent` | The producer may discard the result because row, attempt, pipe, or pending-launch authority can no longer accept it. | +| `forwardResultRetryRequired` | The exact result remains live but recovery or another exact-row writer owns this cycle; the producer must retain and retry it. | +| `forwardResultRetryByRecovery` | Retry is required because hard or typed recovery currently fences LIQ mutation. | +| `forwardResultRetryByMutationConflict` | Retry is required because clear, MDB mutation, replay wakeup, or refill owns the exact row this cycle. | + +External result mode is a compile-time production choice. Generated RTL for +that mode contains neither `LoadForwardPipeline` nor `LoadStoreForwarding`. +`LoadForwardResultRetainer` holds retryable heads and dequeues only on exact +acceptance or permanent stale rejection. The three canonical STQ lookup pipes +will connect to that retained seam in the next I0.15c-b3c packet. + ### Pick Without Forwarding | Signal | Description | @@ -235,7 +275,7 @@ can drive this port. |---|---| | `e4UpdateValid` | A launched row received an E4 outcome. | | `e4UpdateIndex` | LIQ slot updated by E4. | -| `e4MissKind` | Local E4 outcome from `LoadForwardPipeline`. | +| `e4MissKind` | Classified E4 outcome from the selected compatibility or external result owner. | | `e4WakeupValid` | E4 can wake/return the load. | | `lhqRecordValid` | The E4 outcome resolved as a hit and publishes an LHQ record. | | `lhqRecord` | Load ID, row identity including load LSID and PC, line address, byte mask, final line data, and forwarded mask. | diff --git a/docs/chisel/modules/lsu/LoadLookupArbiter.md b/docs/chisel/modules/lsu/LoadLookupArbiter.md index 6b5f2fb9..e1008ed7 100644 --- a/docs/chisel/modules/lsu/LoadLookupArbiter.md +++ b/docs/chisel/modules/lsu/LoadLookupArbiter.md @@ -81,4 +81,4 @@ later packet owns return-pipe availability. - `bash tools/chisel/run_chisel_tests.sh --only LoadLookupArbiter` - `bash tools/chisel/run_chisel_tests.sh --only LoadReplayLaunchReadiness` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r296-replay-liq-load-lookup-arb-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r296-replay-liq-load-lookup-arb-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit bc53de79e34fb497254aa01551bcda16db9b3f35. diff --git a/docs/chisel/modules/lsu/LoadReplayBaseDataAlign.md b/docs/chisel/modules/lsu/LoadReplayBaseDataAlign.md index 5f975ce6..e076f27b 100644 --- a/docs/chisel/modules/lsu/LoadReplayBaseDataAlign.md +++ b/docs/chisel/modules/lsu/LoadReplayBaseDataAlign.md @@ -88,5 +88,5 @@ source-return ownership. - `bash tools/chisel/run_chisel_tests.sh --only LoadLookupArbiter` - `bash tools/chisel/run_chisel_tests.sh --only LoadReplayLaunchReadiness` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r295-replay-liq-base-align-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r296-replay-liq-load-lookup-arb-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r295-replay-liq-base-align-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit c8d4fd7475006bc26217838f624b53d1a397dcff. +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r296-replay-liq-load-lookup-arb-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit bc53de79e34fb497254aa01551bcda16db9b3f35. diff --git a/docs/chisel/modules/lsu/LoadReplayLaunchReadiness.md b/docs/chisel/modules/lsu/LoadReplayLaunchReadiness.md index b5ef854d..79e7cf77 100644 --- a/docs/chisel/modules/lsu/LoadReplayLaunchReadiness.md +++ b/docs/chisel/modules/lsu/LoadReplayLaunchReadiness.md @@ -122,4 +122,4 @@ later condition is only reported after the earlier source conditions are met. - `bash tools/chisel/run_chisel_tests.sh --only LoadReplayLaunchReadiness` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. diff --git a/docs/chisel/modules/lsu/LoadReplayResolvedRowHitRecord.md b/docs/chisel/modules/lsu/LoadReplayResolvedRowHitRecord.md index 22cb417c..fa337be8 100644 --- a/docs/chisel/modules/lsu/LoadReplayResolvedRowHitRecord.md +++ b/docs/chisel/modules/lsu/LoadReplayResolvedRowHitRecord.md @@ -94,6 +94,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Live QEMU/Verilator fixture gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash FETCH_REPLAY_LIQ_REQUIRE_NONZERO=wait_replay_capture_accepted,wait_replay_relaunch_valid,replay_queue_enqueue_accepted,replay_queue_out_fire,liq_alloc_accepted,liq_base_lookup_granted,source_return_query_issued,source_return_response_apply_valid,source_row_mutation_request_valid,liq_row_mutation_write_enable,resolve_queue_push_accepted,resolve_queue_valid,mdb_conflict_store_valid \ FETCH_REPLAY_LIQ_REQUIRE_ZERO=mdb_lookup_wait_plan_lookup_hit,mdb_lookup_wait_plan_wait_intent_valid,mdb_lookup_wait_plan_request_valid \ @@ -105,6 +108,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --disable-store-memory-mutation \ --max-seconds 8 ``` +Provenance: source commit 4f0addd4bb0789ce1b3e1e096662ce1f5ef435d5. + The R495 run compares 3 normalized QEMU/DUT rows with zero mismatches. The sideband report shows `resolve_queue_push_accepted=1`, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnCompleteRepickSelect.md b/docs/chisel/modules/lsu/LoadReplayReturnCompleteRepickSelect.md index 733bc0e7..cffdf8bb 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnCompleteRepickSelect.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnCompleteRepickSelect.md @@ -129,5 +129,5 @@ drain policy. - `python3 -m py_compile tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py` - `git diff --check` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REPLAY_LIQ_REQUIRE_NONZERO=...liq_return_complete_valid LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r542-replay-return-complete-selector-diagnostics --fixture replay-ldi-sdi-ldi-loop --capture-rows 18 --reduced-store-replay-liq --disable-store-memory-mutation --expect-load-pcs 0x10002,0x1000a,0x10002,0x1000a,0x10002,0x1000a --expect-store-pcs 0x10006,0x10006,0x10006 --max-seconds 8` +- historical evidence only (no current runnable equivalent): `FETCH_REPLAY_LIQ_REQUIRE_NONZERO=...liq_return_complete_valid LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r542-replay-return-complete-selector-diagnostics --fixture replay-ldi-sdi-ldi-loop --capture-rows 18 --reduced-store-replay-liq --disable-store-memory-mutation --expect-load-pcs 0x10002,0x1000a,0x10002,0x1000a,0x10002,0x1000a --expect-store-pcs 0x10006,0x10006,0x10006 --max-seconds 8` Provenance: source commit b7334210c47395adb685a568109f2aade78e2863. - `python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py --expect-reduced-store-replay-liq generated/r542-replay-return-complete-selector-diagnostics/report/frontend_fetch_rf_alu_sideband_stats.json --require-nonzero replay_liq.wait_replay_capture_accepted --require-nonzero replay_liq.replay_queue_out_fire --require-nonzero replay_liq.liq_alloc_accepted --require-nonzero replay_liq.source_return_response_apply_valid --require-nonzero replay_liq.liq_row_mutation_write_enable --require-nonzero replay_liq.liq_return_complete_repick_mask_nonzero --require-nonzero replay_liq.liq_return_complete_source_returned_mask_nonzero` diff --git a/docs/chisel/modules/lsu/LoadReplayReturnConsumerReady.md b/docs/chisel/modules/lsu/LoadReplayReturnConsumerReady.md index 738db6a3..820a8f51 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnConsumerReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnConsumerReady.md @@ -102,11 +102,16 @@ blocking because model data return cannot skip the load-return queue. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnConsumerReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. + Reference tests cover normal replay returns requiring both sinks, speculative and stack rows requiring only LRET, LRET-before-wakeup blocker ordering, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnDataExtract.md b/docs/chisel/modules/lsu/LoadReplayReturnDataExtract.md index 664cb0c9..d9376fcd 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnDataExtract.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnDataExtract.md @@ -138,12 +138,17 @@ mem-wakeup is visible until both halves are complete. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnDataExtract bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r306-replay-return-data-extract-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r308-replay-return-data-diagnostic-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 5bcb5db729304392661417ace8c9aea74cb89408, source commit 00697f670488cf259c7cda71c3bd0309749e5983. + Reference tests cover little-endian byte extraction, byte/halfword/word sign-extension, unsigned zero-extension, incomplete byte masks, complete and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnFinalMetadataCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnFinalMetadataCandidate.md index 148cf150..80c849c4 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnFinalMetadataCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnFinalMetadataCandidate.md @@ -97,6 +97,9 @@ setMemData admission Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnFinalMetadataCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnTloadCompletionCandidate @@ -105,6 +108,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeInsertCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r326-replay-final-metadata-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d5f722a9965f94e0b0eff6596978019f1c7431b2. + Reference tests cover final metadata pass-through, no-op branch-resolve side-effect reporting, disabled/flush/missing-input blockers, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnIexDataCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnIexDataCandidate.md index a3c757e8..dc943f66 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnIexDataCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnIexDataCandidate.md @@ -121,12 +121,17 @@ clear occur later at the atomic W2 boundary. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexDataCandidate bash tools/chisel/run_chisel_tests.sh --only ROBRowStatusLookup bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r321-replay-rob-row-status-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 8872275941ea309bfb99a8ab57254403013ba462. + Reference tests cover successful pre-mutation admission, missing ROB-row blocking, need-flush skipping, disabled/flush/no-entry/invalid-entry blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnIexDrainPermit.md b/docs/chisel/modules/lsu/LoadReplayReturnIexDrainPermit.md index 872f9489..8cad05e2 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnIexDrainPermit.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnIexDrainPermit.md @@ -89,6 +89,9 @@ when that slot is occupied and drains when it becomes free. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancy bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancyLiveControl @@ -97,6 +100,8 @@ bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadReturnQueue bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r383x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 7627ea56dce492d2c53d7f4ef56ef40ac57db82c. + Reference tests cover pipe-free mask formation, lowest-free-pipe selection, full-pipe blocking, disabled/flush/no-entry blocker ordering, masked occupancy diff --git a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeInsertCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeInsertCandidate.md index 6f9d17c2..e3ad53c0 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeInsertCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeInsertCandidate.md @@ -164,6 +164,9 @@ IEX insert candidate's pipe selection or wakeup payload logic. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeInsertCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandidate @@ -177,6 +180,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexDrainPermit bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r322-replay-iex-pipe-insert-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 36e6875403e79f4f196e5fe9df9631f283e26a74. + Reference tests cover successful insert-candidate formation, wakeup-required suppression for speculative or stack rows, disabled/flush/no-setMemData/no-pipe diff --git a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancy.md b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancy.md index 44ed5642..c56be145 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancy.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancy.md @@ -97,6 +97,9 @@ single-pipe reduced configuration. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancy bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancyLiveControl @@ -105,6 +108,8 @@ bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadReturnQueue bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r383x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 7627ea56dce492d2c53d7f4ef56ef40ac57db82c. + Reference tests cover forced-full default behavior, live mask pass-through, mask clipping, disabled/flush blockers, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancyLiveControl.md b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancyLiveControl.md index ba6e0a6e..58c2fe6d 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancyLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnIexPipeOccupancyLiveControl.md @@ -100,6 +100,9 @@ keeps `drainReady=false`. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancyLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeOccupancy @@ -107,6 +110,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexDrainPermit bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r388x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit f2632800fc4dc77ab083f44bc734bca39a0d7f59. + Reference tests cover disabled request behavior, live source pass-through, source-missing blocking, disabled/flush blockers, mask clipping, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnLaneCompletionCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnLaneCompletionCandidate.md index 47adc782..8ffeca3d 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnLaneCompletionCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnLaneCompletionCandidate.md @@ -116,6 +116,9 @@ or clear replay-LIQ rows. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnLaneCompletionCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnReducedScalarShapeControl @@ -125,6 +128,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeInsertCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r324-replay-lane-completion-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 5962f94fa0fc57dbb6534f4a8d0e6c2e54e28dd3. + Reference tests cover ordinary scalar pass-through, scalar load-pair incomplete/complete cases, vector/MEM incomplete/complete cases, disabled, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnLretPayload.md b/docs/chisel/modules/lsu/LoadReplayReturnLretPayload.md index 6af4c762..4f63f9f9 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnLretPayload.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnLretPayload.md @@ -26,26 +26,29 @@ ## Purpose -`LoadReplayReturnLretPayload` formats the diagnostic subset of the model -`MemReqBus` that becomes observable once a selected replay-LIQ row has valid -scalar return data. In LinxCoreModel, `LDQInfo::returnData` sets +`LoadReplayReturnLretPayload` formats the retained scalar terminal result that +becomes publishable once a selected LIQ attempt has exactly one outcome: +return data or a terminal fault. In LinxCoreModel, `LDQInfo::returnData` sets `data_vld`, writes the updated bus into `lsuIexLretArray[iexIdx]`, then calls `IEX::setMemWakeup` only when the row is neither `specWakeup` nor `stack_vld`. -This module does not enqueue LRET and does not wake dependents. It preserves -the known request identity and data fields so the future enqueue owner has a -named boundary: +This combinational formatter does not own queue state or wake dependents. The +canonical `ScalarLSULoadPath` and the compatibility workload bridge consume its +output at LRET admission. It preserves: -- BID/GID/RID and load LSID, +- BID/GID/RID, full load LSID, canonical LIQ slot/generation lease, and exact + load-attempt identity, - PC, address, size, scalar return data, +- terminal fault validity/cause, with data forced to zero for a fault result, - one renamed destination sideband, - selected return-pipe index, - `specWakeup`/`stackValid` and derived wakeup-required predicate. R311 carries the reduced one-destination payload from the load uop captured by `ReducedLoadWaitReplaySlot`, through the replay FIFO and LIQ row, and into this -diagnostic formatter. The real IEX LRET enqueue and mem-wakeup fanout remain -deferred. +formatter. Later packets connected the formatter to the retained LRET queue; +production IEX terminal metadata and final atomic side effects remain separate +owners. R376 carries the RF-derived `CommitOperandTrace` pair from the selected replay-LIQ launch row into this LRET payload. The sideband is copied only when @@ -73,10 +76,13 @@ return candidates but has no complete scalar return data to publish. | `dataValid` | `LoadReplayReturnDataExtract` has a complete scalar return value. | | `selectedBid`/`selectedGid`/`selectedRid` | Selected row identity. | | `selectedLoadLsId` | Selected row load sequence identity. | +| `selectedLoadId` | Canonical LIQ slot plus generation lease for the selected resident row. | +| `selectedAttempt` | Exact producer and replay-attempt generation bound to this load. | | `selectedPc`/`selectedAddr`/`selectedSize` | Request PC, address, and size. | | `selectedDst` | Selected row destination sideband captured from the renamed load uop. | | `selectedSourceTraceValid` / `selectedSource0` / `selectedSource1` | R376 source operand trace sideband captured at reduced RF load execution and preserved through the replay-LIQ row. | | `returnData` | Sign/zero-extended scalar return data. | +| `faultValid` / `faultCause` | Terminal fault outcome and cause. Exactly one of `dataValid` and `faultValid` must be asserted for publication. | | `returnPipeIndex` | Selected future IEX return-pipe index. | | `specWakeup` | Model row suppresses regular dependent wakeup. | | `stackValid` | Model row suppresses regular dependent wakeup. | @@ -86,13 +92,16 @@ return candidates but has no complete scalar return data to publish. | Signal | Description | |---|---| | `candidateValid` | `enable && launchValid`. | -| `payloadValid` | Candidate has valid extracted data. Diagnostic-only in R311. | +| `payloadValid` | Candidate has exactly one terminal outcome: data XOR fault. | | `payload*` | Selected identity, request, destination, data, pipe, and sideband fields, zeroed when invalid. | +| `payloadLoadId` / `payloadAttempt` | Canonical row lease and exact attempt retained for stale-return rejection after LIQ reuse. | +| `payloadFaultValid` / `payloadFaultCause` | Fault result retained to terminal IEX publication; payload data is zero on fault. | | `payloadSourceTraceValid` / `payloadSource0` / `payloadSource1` | R376 source operand trace sideband, copied from the selected replay-LIQ row only while `payloadValid` is true. | | `wakeupRequired` | `payloadValid && !specWakeup && !stackValid`. | | `blockedByDisabled` | A selected row exists while replay-LIQ mode is disabled. | | `blockedByNoCandidate` | Replay-LIQ mode is enabled but no row is selected. | | `blockedByData` | Candidate exists but scalar return data is not valid. | +| `malformedOutcome` | Candidate has neither outcome or asserts data and fault together. | ## State @@ -114,7 +123,8 @@ R310 mirrors only the known scalar subset: ```text candidateValid = enable && launchValid -payloadValid = candidateValid && dataValid +outcomeExact = dataValid XOR faultValid +payloadValid = candidateValid && outcomeExact wakeupRequired = payloadValid && !specWakeup && !stackValid ``` @@ -124,8 +134,9 @@ extraction is blocked. R376 applies the same guard to source-trace fields. ## Deferred Owners -- Real IEX LRET queue entry type and enqueue. -- Real mem-wakeup publication and ready-table/issue wakeup fanout. +- Production OOO/IEX terminal sidecar allocation and exact terminal-fire + retirement for every execution cluster. +- Full mem-wakeup publication and ready-table/issue wakeup fanout. - Real ready-table/issue wakeup mutation; R313 exposes only a diagnostic wakeup candidate. - Real RF writeback arbitration; R312 exposes only a diagnostic GPR writeback @@ -138,12 +149,20 @@ extraction is blocked. R376 applies the same guard to source-trace fields. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnLretPayload bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r311-replay-destination-sideband-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 25d98c36ac758f093c47ed91eb07ba77b2a21016. + Reference tests cover selected-row identity/data forwarding, speculative and -stack wakeup suppression, invalid-data blocking, destination forwarding, -stale-field suppression, and Chisel elaboration. +stack wakeup suppression, exact attempt/row-lease retention, data-or-fault +exclusivity, destination forwarding, stale-field suppression, and Chisel +elaboration. The current integration repair also runs +`LoadAttemptBinding`, `ScalarLSULoadPath`, the 44-case live-top suite, the +15-case autonomous-top suite, and the bounded generated-RTL xcheck. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeBudget.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeBudget.md index 45dde02e..66ab6019 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeBudget.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeBudget.md @@ -94,12 +94,17 @@ owners. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeBudget bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnConsumerReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. + Reference tests cover budget availability, disabled wrapper gating, source-return blocker ordering, budget-disabled blocker ordering, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipePermit.md b/docs/chisel/modules/lsu/LoadReplayReturnPipePermit.md index 9f959c77..d38663a4 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipePermit.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipePermit.md @@ -84,11 +84,16 @@ grouping remain deferred to a later pipe-budget owner. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipePermit bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. + Reference tests cover permit-valid mask generation, source blocking before pipe-budget blocking, disabled/no-row diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceCandidate.md index 1a537b6c..7cab2c81 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceCandidate.md @@ -93,6 +93,9 @@ agreement. W2 atomic request promotion remains disabled. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyAdvanceCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyAdvanceLiveControl @@ -101,6 +104,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r385x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 2b3065202e6f23b9ccb377c674fd1195ddd1ad89. + Reference tests cover enabled LDA advance, live-disabled AGU blocking, disabled/flush/no-slot blockers, invalid target rejection, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceLiveControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceLiveControl.md index 2de3403e..7a6e0e11 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyAdvanceLiveControl.md @@ -95,6 +95,9 @@ blocker is W2 atomic request promotion, not residency advance. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyAdvanceLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyAdvanceCandidate @@ -102,6 +105,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r385x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 2b3065202e6f23b9ccb377c674fd1195ddd1ad89. + Reference tests cover disabled request gating, live request with resident-slot evidence, disabled/flush blockers, empty-slot and invalid-target blockers, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyCandidate.md index 29874428..deaa4307 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyCandidate.md @@ -123,6 +123,9 @@ the slot observes no writes and only reports dormant occupancy/no-write state. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnReducedScalarShapeControl @@ -133,6 +136,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnTimingStatsCandidat bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r328-replay-pipe-residency-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit cf23d5ca549e71abb143cbe8d3991f45fe677464. + Reference tests cover scalar LDA target diagnostics, vector AGU target diagnostics, live-disabled blocking, occupied-pipe blocking, disabled/flush diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyLiveControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyLiveControl.md index 9ccdd81a..9b9c8be4 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencyLiveControl.md @@ -95,6 +95,9 @@ write. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandidate @@ -102,6 +105,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencySlot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r384x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 1d0b387baa3c447c9e4ffe4aaf303ae319598fdc. + Reference tests cover disabled request gating, live request with accepted free-pipe evidence, disabled/flush blockers, missing insert evidence, occupied diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencySlot.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencySlot.md index add4042e..67562950 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencySlot.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeResidencySlot.md @@ -124,6 +124,9 @@ LDA/AGU pipe pipeline. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencySlot bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyLiveControl @@ -134,6 +137,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeInsertCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r329-replay-pipe-residency-slot-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 90bf4a8c9ef168a5ccdfeed667a791d4f5c32aab. + Reference tests cover scalar LDA capture, vector AGU capture, occupied-slot blocking, flush and clear priority, disabled/no-write/invalid-target blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeSelect.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeSelect.md index 2324220a..06b90ef2 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeSelect.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeSelect.md @@ -97,11 +97,16 @@ carry remain deferred. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeSelect bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. + Reference tests cover lowest-pipe selection, source blocking before pipe blocking, no-pipe blocking after source completion, disabled/no-row diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW1AdvanceCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW1AdvanceCandidate.md index d76d906b..4c6c8106 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW1AdvanceCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW1AdvanceCandidate.md @@ -97,6 +97,9 @@ that the W2 slot consumes. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1AdvanceCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot @@ -106,6 +109,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencySlot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r333-replay-pipe-w2-slot-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 6b87caf793172fb0ae491fc8b45a79e8a6d3931e. + Reference tests cover scalar LDA advance, vector AGU live-disabled residency, disabled/flush/empty-slot blockers, invalid target-family rejection, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW1Slot.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW1Slot.md index e117c88d..a7d8566c 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW1Slot.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW1Slot.md @@ -133,6 +133,9 @@ does not create a distinct W1 candidate near W2 live clear. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1Slot bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1AdvanceCandidate @@ -143,6 +146,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r333-replay-pipe-w2-slot-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 6b87caf793172fb0ae491fc8b45a79e8a6d3931e. + Reference tests cover scalar LDA capture, vector AGU capture, occupied-slot blocking, flush and clear priority, disabled/no-write/invalid-target blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AdvanceControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AdvanceControl.md index af2180bb..00afea60 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AdvanceControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AdvanceControl.md @@ -162,6 +162,9 @@ replay RF writeback, ready-table mutation, or issue wakeup. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AdvanceControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SlotReplacePlan @@ -172,6 +175,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1AdvanceCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r355-replay-pipe-w2-advance-control-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit bbb63ed416d0ac9f8bcbf612ca21d70b6d91b238. + Reference tests cover current empty-only pass-through, future promotion selection, disabled/flush blockers, incoherent future write evidence, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicLiveRequestControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicLiveRequestControl.md index d590aca9..5fc6bfd4 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicLiveRequestControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicLiveRequestControl.md @@ -105,6 +105,9 @@ remain disabled. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicLiveRequestControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectLiveControl @@ -112,6 +115,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2PromotionCont bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r363-replay-pipe-w2-atomic-live-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 28b0ca97dab579a6f0c1a8739b61021ace1d6786. + Reference tests cover disabled default behavior, the shared active request gate, disabled/flush blockers, no-evidence diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicPrereqSnapshot.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicPrereqSnapshot.md index a446f69d..584f9886 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicPrereqSnapshot.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicPrereqSnapshot.md @@ -176,6 +176,9 @@ replay-LIQ resolved-row lifecycle match. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicPrereqSnapshot bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicRequestGate @@ -184,6 +187,8 @@ BUILD_DIR=generated/r533-replay-w2-prereq-snapshot-top-xcheck bash tools/chisel/ BUILD_DIR=generated/r534-replay-w2-atomic-live-mode-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh git diff --check ``` +Provenance: source commit 34eac0a1d68d6fd2be28b8ffb7294279d988a353, source commit b24fa65643cd91b4aa967d1b160abd76bbbea8bb. + Reference tests cover same-identity snapshot reuse, identity mismatch, flush clear, invalid resident identity suppression, ordered missing-prerequisite diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicRequestGate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicRequestGate.md index b89bfb27..bd02a0fa 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicRequestGate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2AtomicRequestGate.md @@ -174,6 +174,9 @@ request, and diagnostic logic across multiple helpers. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicRequestGate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicRequestEnablePolicy @@ -183,6 +186,8 @@ BUILD_DIR=generated/r534-replay-w2-atomic-live-mode-xcheck bash tools/chisel/run BUILD_DIR=generated/r535-replay-w2-sideband-counters-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh git diff --check ``` +Provenance: source commit 34eac0a1d68d6fd2be28b8ffb7294279d988a353, source commit b24fa65643cd91b4aa967d1b160abd76bbbea8bb, source commit 9bad278a54152932cbc4b2b92d242437d14f2e1b. + The R533 generated-RTL manifest is `generated/r533-replay-w2-prereq-snapshot-top-xcheck/report/crosscheck_manifest.json`; diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearCommitGuard.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearCommitGuard.md index 630c0899..c67c5167 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearCommitGuard.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearCommitGuard.md @@ -122,11 +122,16 @@ the next owner is row-fill candidate readiness. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ClearCommitGuard bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r365-replay-w2-clear-commit-guard-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 25a4351f2873798033a7c5e4c69a51b6f4231198. + Reference tests cover coherent clear/commit evidence, dormant live-clear disable, missing ROB completion, resolve-vs-slot mismatch, ROB-vs-slot and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearIntent.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearIntent.md index 61b4c048..7f4f949c 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearIntent.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ClearIntent.md @@ -114,6 +114,9 @@ mutation, issue wakeup, or replay-row lifecycle. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ClearIntent bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireComplete @@ -123,6 +126,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2PromotionCont bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r351-replay-pipe-w2-clear-intent-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit a4d41c244bba613795fff8230575868965044f11. + Reference tests cover dormant clear intent, live-clear gating, no-slot stray evidence, disabled/flush suppression, missing pre-clear evidence, missing diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2CompletionCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2CompletionCandidate.md index a0483c7b..b8213796 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2CompletionCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2CompletionCandidate.md @@ -132,6 +132,9 @@ live returned-load pipe retirement. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2CompletionCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest @@ -145,6 +148,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1AdvanceCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r334-replay-pipe-w2-completion-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 526a39b3f8d93300aac95e26998ba668457420c2. + Reference tests cover ready scalar LDA completion, side-effect-not-ready hold, missing and non-GPR destination classification, disabled/flush/no-slot/invalid diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PostLretEnqueueHold.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PostLretEnqueueHold.md index c9513c9f..172a1074 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PostLretEnqueueHold.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PostLretEnqueueHold.md @@ -108,6 +108,9 @@ The reduced replay-LIQ top exposes the default-off environment knob Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2PostLretEnqueueHold bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -122,6 +125,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 2d86408e16aa60f018919b2d714c7bf7302ed747. + R575 generated-RTL/QEMU evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PromotionControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PromotionControl.md index 76d0f327..f5f0788a 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PromotionControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2PromotionControl.md @@ -107,6 +107,9 @@ write the replay RF path, mutate ready-table state, or wake the issue queue. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2PromotionControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicLiveRequestControl @@ -117,6 +120,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AdvanceContro bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r356-replay-pipe-w2-promotion-control-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 96c83fbf2d7ecc4e2229d020a65424ce93b48a1c. + Reference tests cover default disabled behavior, empty-slot promotion, same-cycle clear/refill promotion, disabled/flush/missing-clear blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RefillReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RefillReady.md index 9c8ba043..a948848e 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RefillReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RefillReady.md @@ -99,6 +99,9 @@ ROB/RF/ready-table state. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RefillReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ClearIntent @@ -108,6 +111,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r352-replay-pipe-w2-refill-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit f920390b0e409f6efcb32a5fbb36118638585b1c. + Reference tests cover empty W2 readiness, occupied W2 blocking, dormant same-cycle refill eligibility, future live clear refill readiness, invalid diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ReplayRowLifecycleReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ReplayRowLifecycleReady.md index 3472be1a..95ce73d1 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ReplayRowLifecycleReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ReplayRowLifecycleReady.md @@ -193,12 +193,17 @@ overlap those retained-record candidates. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ReplayRowLifecycleReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RowFillEnableControl bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r368-replay-w2-row-lifecycle-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 32bc8a5be254c0956e0dafe3a23aacf82de57dca. + Reference tests cover unique resolved-row match, live-clear-disabled dormancy, invalid slot identity, absent resolved row, duplicate resolved rows, disabled / diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveArbiterInput.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveArbiterInput.md index 455b2851..c0237434 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveArbiterInput.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveArbiterInput.md @@ -99,12 +99,17 @@ Top-level diagnostics are exposed under Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveArbiterInput bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveFirePayload bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r359-replay-pipe-w2-resolve-arbiter-input-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit c4ac20fa43fa81183e6d3a5ab9e3fb0cd1d26e6a. + Reference tests cover live-disabled candidate hold, live-enabled payload copy, disabled/flush blockers, active no-payload diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveFirePayload.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveFirePayload.md index b262688d..c75a282f 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveFirePayload.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveFirePayload.md @@ -108,6 +108,9 @@ ready-table mutation, issue wakeup, or replay-row lifecycle. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveFirePayload bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireVector @@ -116,6 +119,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectIss bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r347-replay-pipe-w2-resolve-fire-payload-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 496caf55f72c09d39b570e4b67165b87c6d03587. + Reference tests cover legal fire-qualified copying, fire without payload, payload without fire, disabled/flush suppression, incomplete payloads, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveRequest.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveRequest.md index 94029a72..49159f23 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveRequest.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveRequest.md @@ -110,12 +110,17 @@ ROB/PE resolve mutation boundary fire-qualified and still observational. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveRequest bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r340-replay-pipe-w2-resolve-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d7032df2cd659799ee98713e8bff7c1527988784. + Reference tests cover legal payload copying, dormant resident-slot behavior, request-without-slot diagnostics, invalid target diagnostics, invalid identity diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveSinkReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveSinkReady.md index 12d85d1f..3ac02dfa 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveSinkReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2ResolveSinkReady.md @@ -93,6 +93,9 @@ needed before live `runW2` retirement. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveSinkReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectReady @@ -100,6 +103,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2CompletionCan bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r336-replay-pipe-w2-resolve-sink-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 0eb359c736d3440a6c42eab7c76bdcfe8d003e84. + Reference tests cover live resolve readiness, live-disabled arming, sink backpressure priority, disabled/flush/no-resolve diagnostics, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecord.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecord.md index 2b71b81c..147c8fb9 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecord.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecord.md @@ -407,6 +407,9 @@ full-record drop, same-cycle consume/recapture, and Chisel elaboration. R577 integration gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ @@ -419,9 +422,14 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 011bdc01668d93790b73d82db8f9711a7fd1d991. + R578 lifecycle-match diagnostic gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -433,9 +441,14 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit a298341c872d88397137bf2688bca976b3aeee79. + R579 lifecycle-ready consume diagnostic gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -447,6 +460,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 3db850c702489ed05e08bf13fcf3827a4bce2f38. + R581 retained-record lifecycle request probe gate uses the same fixture and builds `generated/r581-replay-w2-retire-record-request-probe-xcheck`. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe.md index 0adf78c1..0d66f991 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe.md @@ -100,6 +100,9 @@ enable. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordAtomicRequestProbe bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -113,3 +116,5 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 25f35a111deffbe25e035028b87d85032414b37a. + diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordBundleTransferPlan.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordBundleTransferPlan.md index b3011c27..f92d1ad7 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordBundleTransferPlan.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordBundleTransferPlan.md @@ -116,6 +116,9 @@ all four suppression intent counters at `5`, and Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordBundleTransferPlan bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -129,6 +132,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 2956dab211280da472d99e7bbe171e74a565f99c. + Reference tests cover full-bundle transfer planning, already-ready default promotion, partial duplicates, missing record, missing pre-arm evidence, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordCommitRowCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordCommitRowCandidate.md index 722c51f1..d232c7fc 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordCommitRowCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordCommitRowCandidate.md @@ -143,6 +143,9 @@ no-physical-complete retained fallback case. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordCommitRowCandidate bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -162,3 +165,5 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_commit_row_fill_candidate \ generated/r583-replay-retire-record-commit-row-candidate-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit 7d48906fc10cfdfc424c2383c649a32ef9a515cb. + diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness.md index 63744e1e..db3dcae3 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness.md @@ -138,6 +138,9 @@ precondition. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordDefaultPromotionReadiness bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -151,6 +154,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit a06cbf77f1f0244131dbf51493055d9e37578636. + Reference tests cover ready, physical-duplicate block, probe-active block, missing record, missing candidates, missing lifecycle evidence, flush, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDuplicateVector.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDuplicateVector.md index f67ee68d..650acb87 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDuplicateVector.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordDuplicateVector.md @@ -133,6 +133,9 @@ bundle suppression or transfer. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordDuplicateVector bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -146,6 +149,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 835b5465163b2ef8a246f8ea8d88e2c2870338d2. + Reference tests cover full model-order duplicate bundles, partial vectors, single duplicates, missing-record, missing-pre-arm, no-duplicate, flush, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy.md index 684d7d3c..84cedafd 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy.md @@ -321,6 +321,9 @@ suppression intent counters at five, and zero incomplete-bundle blockers. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordFallbackOwnerPolicy bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -355,6 +358,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit d4773e5115797fafba9d28afd20d3e27b860090e, source commit 45a5ae3f71e5fc0b88588520726ff94cf39124a4, source commit 21d95f1c2a26998cf801efcce28dd453f0bcc588. + The reference tests cover unique retained ownership, physical duplicate blocking, missing-candidate blocking, the global fallback arm, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch.md index 5220a941..a13e211e 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch.md @@ -118,6 +118,9 @@ metadata and payload-source blockers are no longer active in this fixture. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordInstructionMetadataLatch bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -138,9 +141,14 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_instruction_metadata_capture_from_w2 \ generated/r584-replay-retire-record-metadata-probe-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit a3624948d19a4e6c7bd52e141017ed30f1d4a03d. + R585 payload-source/latch-hold gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -161,5 +169,7 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_commit_row_candidate_blocked_by_no_metadata \ generated/r585-replay-retire-record-payload-source-latch-hold-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit 6c060ca96723ab7ee62faa65118228b4666f2791. + skill-evolve: no-update (R585 applies the existing prove-before-promote and top-split rules; the payload-source rule is now captured in this module contract). diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard.md index 82c02b7d..e1e4e648 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard.md @@ -112,6 +112,9 @@ stimulus before `fallbackClearValid` can be armed. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordLifecycleClearFallbackGuard bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -125,6 +128,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 64fa8922fc057114dda438948d2883353d136e49. + Reference tests cover duplicate physical-clear suppression, no-physical-clear fallback emission, missing retained lifecycle-clear and capture blockers, the diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch.md index 68ef00ed..9b8488a8 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch.md @@ -116,6 +116,9 @@ or reordering the physical W2 lifecycle path. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordLifecycleEvidenceLatch bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -135,3 +138,5 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle \ generated/r586-replay-retire-record-lifecycle-evidence-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit 4abf86b498e60b5e1ad1a17350649b4d0c0eeace. + diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe.md index 6050a971..3fd835dc 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe.md @@ -116,6 +116,9 @@ source before retrying atomic request promotion. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordLifecycleRequestProbe bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -129,6 +132,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit b4bea35e3e347e4ce35c5a89fbac79f01dc56b44. + Reference tests cover full live-promotion candidate formation, missing lifecycle row, missing atomic request, missing row-fill candidate, missing diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordModelOrderProof.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordModelOrderProof.md index a4181a8f..21b7241d 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordModelOrderProof.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordModelOrderProof.md @@ -121,6 +121,9 @@ does not by itself promote the retained fallback path into default behavior. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordModelOrderProof bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -135,6 +138,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 83fae006e03ce7c5fd33fb52806e5c439744143b. + Reference tests cover full eligibility, missing return side-effect evidence, missing retire-clear evidence, missing record, owner-disabled, flush, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary.md index d7f4bb44..33543957 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressBoundary.md @@ -102,6 +102,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Probe-enabled generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -114,6 +117,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit c3508a4102dfbd876bc350b011fca45486b65984. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof.md index c7dfe8e1..954728ed 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressClearProof.md @@ -117,6 +117,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Generated-RTL/QEMU R605 gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -130,6 +133,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit ee68ab3f8b34ec429019b2c4699067104ac03598. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof.md index 342fdbad..e5af46f5 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressIdentityProof.md @@ -151,6 +151,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Probe-enabled generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -163,6 +166,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 24314269a5dfaa0dc417850d9d4232deba935209. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask.md index 96685a89..8ea76035 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressLiveMask.md @@ -108,6 +108,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Generated-RTL/QEMU R604 gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -121,6 +124,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 1394c260fcee5ad8c5938e5a1e23cee1dc29ad83. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary.md index c3921d87..b53494e6 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressOwnershipBoundary.md @@ -136,6 +136,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Probe-enabled generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -148,6 +151,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 1cbf885a7240e489c10e54c5bafcbf1fbae13761. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan.md index 5d0acb62..62ff195a 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressPlan.md @@ -106,6 +106,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -117,6 +120,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit 4cffc0dc50d2c4b38e21f305132be44d63c753ae. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe.md index beb24e15..ea096174 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressProbe.md @@ -111,6 +111,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Default generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -122,6 +125,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit c5c65ed88c1e3431e4b175050236b4fa7b215896. + Default evidence: @@ -143,6 +148,9 @@ w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask=0 Probe-enabled generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -155,6 +163,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit c5c65ed88c1e3431e4b175050236b4fa7b215896. + Probe-enabled evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect.md index a98e1a63..8b7f9bd0 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordPhysicalBundleSuppressSelect.md @@ -139,6 +139,9 @@ bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop Promoted generated-RTL/QEMU replay-LIQ gate: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ LINXCORE_REPLAY_LIQ_W2_COMPLETION_DELAY_CYCLES=12 \ @@ -152,6 +155,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --reduced-store-replay-liq --disable-store-memory-mutation \ --allow-residual-replay-liq-wait ``` +Provenance: source commit affb9c6c5875335188201fd7928359a71ea63b2f. + Evidence: diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard.md index 737ff681..d29e7608 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard.md @@ -133,6 +133,9 @@ RID/tag/data. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordRfWritebackFallbackGuard bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -153,6 +156,8 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_rf_fallback_writeback_valid \ generated/r588-replay-retire-record-rf-fallback-guard-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit b8281956c94d934a94389012d160430054b982ba. + Reference tests cover duplicate physical-writeback suppression, no-physical fallback emission, payload-mismatch diagnostics, missing retained-writeback and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard.md index 30752deb..030e0763 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard.md @@ -149,6 +149,9 @@ requirement. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordRobCompleteFallbackGuard bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -171,6 +174,8 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-nonzero replay_liq.w2_retire_record_commit_row_complete_candidate \ generated/r587-replay-retire-record-rob-fallback-guard-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit a780b5e5271c5a408c8811081d40011e59742795. + Reference tests cover duplicate physical-complete suppression, fallback emission when no physical completion was captured, missing retained-row/capture blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRowFillEnableControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRowFillEnableControl.md index 1e2ce5b3..b7916203 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRowFillEnableControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordRowFillEnableControl.md @@ -106,6 +106,9 @@ writeback, and replay wakeup. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordRowFillEnableControl bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -128,3 +131,5 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate \ generated/r586-replay-retire-record-lifecycle-evidence-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit 4abf86b498e60b5e1ad1a17350649b4d0c0eeace. + diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard.md index 1f6e5c3b..c08271cb 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard.md @@ -130,6 +130,9 @@ stimulus before `fallbackWakeupValid` can be armed. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RetireRecordWakeupFallbackGuard bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop @@ -150,6 +153,8 @@ python3 tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py \ --require-zero replay_liq.w2_retire_record_wakeup_fallback_wakeup_valid \ generated/r589-replay-retire-record-wakeup-fallback-guard-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json ``` +Provenance: source commit 6d022525cd261fa08ab2627a8a11147af82ab67b. + Reference tests cover duplicate physical-wakeup suppression, no-physical fallback emission, payload-mismatch diagnostics, missing retained-wakeup and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RobCompleteSource.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RobCompleteSource.md index 617c99cf..67259fec 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RobCompleteSource.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RobCompleteSource.md @@ -125,12 +125,17 @@ proven. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RobCompleteSource bash tools/chisel/run_chisel_tests.sh --only ReducedRobCompletionArbiter bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r364-replay-w2-rob-complete-source-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 79a60b9180e9e4db044bb40fae76da37bf649201. + Reference tests cover idle-port completion, execute-port blocking, row-fill input pass-through, disabled/flush suppression, invalid RID diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RowFillEnableControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RowFillEnableControl.md index 05ce5138..700925e5 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RowFillEnableControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2RowFillEnableControl.md @@ -137,12 +137,17 @@ owner is the lifecycle row match that feeds pre-request policy evidence. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RowFillEnableControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2CommitRowCandidate bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r367-replay-w2-row-fill-enable-control-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit f5f0f744d53344a499f12755d5631ab63f3f92d0. + Reference tests cover the fully armed row-fill case, request-disabled dormancy, ordered missing-prerequisite blockers, disabled/flush/no-candidate blockers, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectCompletionPermit.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectCompletionPermit.md index a782cbde..a428b614 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectCompletionPermit.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectCompletionPermit.md @@ -117,6 +117,9 @@ path remains the R335 readiness join, so fixture behavior is unchanged. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectCompletionPermit bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectReady @@ -126,6 +129,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupSinkRea bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r345-replay-pipe-w2-side-effect-completion-permit-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit e4efacf6f58d7ae46cfb83db18e0585ecc12552d. + Reference tests cover full side-effect permit, resolve-only permit, missing sink masks, disabled/flush/no-candidate dormancy, empty required-mask diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectFireVector.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectFireVector.md index eb1354db..1ba2c0d2 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectFireVector.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectFireVector.md @@ -128,6 +128,9 @@ also observational and still does not feed W2 clear or replay-row lifecycle. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireVector bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectIssuePermit @@ -136,6 +139,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectCom bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r346-replay-pipe-w2-side-effect-fire-vector-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 2f09ba7aecf87b057152c1aad7492383bc70c4dc. + Reference tests cover full-mask fire, resolve-only fire, no-accept dormancy, disabled/flush blockers, empty accepted masks, request and payload mismatches, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectIssuePermit.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectIssuePermit.md index b447242a..7e19ea14 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectIssuePermit.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectIssuePermit.md @@ -118,6 +118,9 @@ and does not feed W2 clear. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectIssuePermit bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireVector @@ -129,6 +132,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupSinkRea bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r344-replay-pipe-w2-side-effect-issue-permit-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 6c296d510ce6dbb193813f593dcd40d28cc1fd75. + Reference tests cover full side-effect acceptance, resolve-only acceptance, per-sink live-readiness blockers, dormant no-plan behavior, disabled/flush diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectLiveControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectLiveControl.md index bb81d4fd..f4b20a4b 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectLiveControl.md @@ -108,6 +108,9 @@ R334 does not clear the W2 slot, and R351/R356 promotion remains dormant. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2AtomicLiveRequestControl @@ -118,6 +121,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRea bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r357-replay-pipe-w2-side-effect-live-control-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit bb6aa74587a3acd4a528ea513ce114a859be4259. + Reference tests cover live-disabled default behavior, required-sink mask selection, disabled/flush blockers, no-candidate/no-required-sink blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectPayloadPlan.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectPayloadPlan.md index e2f6078c..a382d8d2 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectPayloadPlan.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectPayloadPlan.md @@ -126,6 +126,9 @@ replay RF writeback, ready-table state, or issue wakeup. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectPayloadPlan bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest @@ -137,6 +140,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFir bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r343-replay-pipe-w2-side-effect-payload-plan-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d0136678e41af6b3bf62a3ff95b5e7154e4d605f. + Reference tests cover full side-effect masks, resolve-only masks, dormant request behavior, disabled/flush blockers, request-mask mismatch, missing diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectReady.md index 740c9313..4b7333d3 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectReady.md @@ -131,6 +131,9 @@ replace this module or feed W2 clear. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectLiveControl @@ -143,6 +146,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r335-replay-pipe-w2-side-effect-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 7c6d65970809b6b7025298c2536ed512db9b7ede. + Reference tests cover all-side-effect readiness, resolve-only readiness, independent missing-sink blockers, optional writeback/wakeup suppression, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectRequest.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectRequest.md index ec50a261..ada42484 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectRequest.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SideEffectRequest.md @@ -117,6 +117,9 @@ clear W2. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2ResolveRequest @@ -126,6 +129,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRea bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r339-replay-pipe-w2-side-effect-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 13fdea577829129ca7632e998dbd8f008a9acc8b. + Reference tests cover all-side-effect requests, resolve-only requests, pre-completion blocking, illegal completed shapes, side-effect valid pulses diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2Slot.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2Slot.md index 697b0959..5f48df0f 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2Slot.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2Slot.md @@ -250,6 +250,9 @@ phasing experiment or model-derived side-effect retire boundary, not Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2CompletionCandidate @@ -259,6 +262,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r354-replay-pipe-w2-slot-replace-mode-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 40a2092f9f10c237866e3d1948009fce9ca52f9d. + Reference tests cover scalar LDA capture, vector AGU capture, occupied-slot blocking, flush and clear priority, disabled/no-write/invalid-target blockers, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SlotReplacePlan.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SlotReplacePlan.md index c50fa3fd..9dc0ee7a 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SlotReplacePlan.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2SlotReplacePlan.md @@ -186,6 +186,9 @@ clears, proving they are not different-candidate replacement opportunities. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SlotReplacePlan bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2RefillReady @@ -196,6 +199,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW1AdvanceCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r353-replay-pipe-w2-slot-replace-plan-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 8aa183746c2b6892b2549c4317b20a96ecc9d32d. + Reference tests cover empty-slot write matching, occupied-slot blocking, dormant same-cycle replacement eligibility, future live-clear replacement, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupArbiterInput.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupArbiterInput.md index 23c78d4f..9910de68 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupArbiterInput.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupArbiterInput.md @@ -101,12 +101,17 @@ Top-level diagnostics are exposed under Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupArbiterInput bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupFirePayload bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r360-replay-pipe-w2-wakeup-arbiter-input-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 226bb6ccf5db8be740f08ac0134885ddea648dba. + Reference tests cover live-disabled candidate hold, live-enabled payload copy, disabled/flush blockers, active no-payload diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupFirePayload.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupFirePayload.md index 2b8afca2..0af266af 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupFirePayload.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupFirePayload.md @@ -114,6 +114,9 @@ but that pre-arbiter boundary keeps `liveEnable=false` in the reduced top. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupFirePayload bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireVector @@ -122,6 +125,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectIss bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r349-replay-pipe-w2-wakeup-fire-payload-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 9973deb8604bfa239c6653ea1a3c11d7d9e57228. + Reference tests cover legal GPR and non-GPR fire-qualified copying, fire without payload, payload without fire, disabled/flush suppression, invalid diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupRequest.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupRequest.md index f1746720..df8519dc 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupRequest.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupRequest.md @@ -125,6 +125,9 @@ is also observational until the ready-table and issue-wakeup owners are live. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupRequest bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest @@ -133,6 +136,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupSinkRea bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r342-replay-pipe-w2-wakeup-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 0ac01b2824f2805b7e285dc121ad5e9abac764bc. + Reference tests cover legal GPR payload copying, scalar local-link payload preservation, dormant resident-slot behavior, request-without-slot diagnostics, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupSinkReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupSinkReady.md index ab8fd903..d329a93f 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupSinkReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WakeupSinkReady.md @@ -103,6 +103,9 @@ payload remains dormant until this sink's live enable is asserted. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupSinkReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WakeupRequest @@ -112,6 +115,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r338-replay-pipe-w2-wakeup-sink-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 991cdd220eb2d14ee3a47f30849b98dba2717b36. + Reference tests cover live wakeup readiness, live-disabled arming, abstract wakeup-sink backpressure priority, disabled/flush/no-wakeup diagnostics, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackArbiterInput.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackArbiterInput.md index 2cb4546d..ae38d84b 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackArbiterInput.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackArbiterInput.md @@ -92,12 +92,17 @@ single-port RF arbitration diagnostics remain under Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WritebackArbiterInput bash tools/chisel/run_chisel_tests.sh --only ReducedScalarWritebackArbiter bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r362-replay-pipe-w2-writeback-rf-arbiter-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 8a2d680b8c0e80cc0514f8c496e562ce9f49d8fe. + Reference tests cover live-disabled candidate hold, live-enabled payload copy, disabled/flush blockers, active no-payload diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackFirePayload.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackFirePayload.md index 0d3ce7a3..3af94787 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackFirePayload.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackFirePayload.md @@ -114,6 +114,9 @@ or replay-row lifecycle. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WritebackFirePayload bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectFireVector @@ -122,6 +125,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectIss bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r348-replay-pipe-w2-writeback-fire-payload-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d69b72d826fa8b10e682181f83747737d0150484. + Reference tests cover legal fire-qualified copying, fire without payload, payload without fire, disabled/flush suppression, invalid target and identity, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackRequest.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackRequest.md index 8d401fa7..43858ae6 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackRequest.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackRequest.md @@ -120,12 +120,17 @@ observational and does not feed the scalar RF writeback arbiter or RF state. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WritebackRequest bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectRequest bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r341-replay-pipe-w2-writeback-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit c8c03d3b2b81f212deb9d5d5d169769096443056. + Reference tests cover legal GPR payload copying, dormant resident-slot behavior, request-without-slot diagnostics, invalid target diagnostics, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackSinkReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackSinkReady.md index 04ab5aca..ccc88805 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackSinkReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPipeW2WritebackSinkReady.md @@ -96,6 +96,9 @@ needed before live `runW2` retirement. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2WritebackSinkReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2SideEffectReady @@ -104,6 +107,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2Slot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r337-replay-pipe-w2-writeback-sink-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 76ac95ccca1dbec5b8cda276a32738636ffe62e9. + Reference tests cover live writeback readiness, live-disabled arming, scalar RF port backpressure priority, disabled/flush/no-writeback diagnostics, and diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPublishControl.md b/docs/chisel/modules/lsu/LoadReplayReturnPublishControl.md index 8bedc4f7..ca97a544 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPublishControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPublishControl.md @@ -105,11 +105,16 @@ issue queues. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPublishControl bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r316-replay-publish-control-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 49da342e5584519b56ef71819c92f29b7516228a. + Reference tests cover full live fire, armed-but-disabled behavior, publish-readiness blockers, side-effect blockers, disabled/empty payload diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPublishReady.md b/docs/chisel/modules/lsu/LoadReplayReturnPublishReady.md index e7ebf0dc..0f64f5ec 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPublishReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPublishReady.md @@ -92,11 +92,16 @@ their join point observable at the top boundary. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPublishReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r309-replay-return-publish-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit a496d8933ea3840d0f5303e685befd6796c47562. + Reference tests cover publish-ready assertion, data-before-consumer blocker ordering, empty/disabled candidate diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnPublishRequest.md b/docs/chisel/modules/lsu/LoadReplayReturnPublishRequest.md index df6c2eea..01f547e7 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnPublishRequest.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnPublishRequest.md @@ -98,11 +98,16 @@ payload. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPublishRequest bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r317-replay-publish-request-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 3c8269fe064c5e697bc7054a9fca76a9c8ac2a0c. + Reference tests cover all-request fanout, LRET-only fanout, no-fire suppression, illegal fire-without-payload diagnostics, independent request mask diff --git a/docs/chisel/modules/lsu/LoadReplayReturnReadiness.md b/docs/chisel/modules/lsu/LoadReplayReturnReadiness.md index 4e90d6ea..b99145f7 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnReadiness.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnReadiness.md @@ -99,11 +99,16 @@ The LinxCoreModel return loop computes an IEX return-pipe budget, assigns Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnReadiness bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r305-replay-liq-return-consumer-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 50f1228e88ac2e43d1ac43600a28d71178525dd5. + Reference tests cover ready, source blocking before pipe blocking, return-pipe blocking after source completion, disabled/no-row diagnostics, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnReducedScalarShapeControl.md b/docs/chisel/modules/lsu/LoadReplayReturnReducedScalarShapeControl.md index e678c212..a9f15564 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnReducedScalarShapeControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnReducedScalarShapeControl.md @@ -112,6 +112,9 @@ preserving the previous constants. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnReducedScalarShapeControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnRobResolveDataCandidate @@ -121,6 +124,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r386x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 9d2f71540490e1ec0d3a6f28833766d527f4aa21. + Reference tests cover active scalar-shape outputs, disabled and flush diagnostics, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnRobResolveDataCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnRobResolveDataCandidate.md index 0ec38bd6..09830822 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnRobResolveDataCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnRobResolveDataCandidate.md @@ -125,6 +125,9 @@ coordinates RF writeback, wakeup, completion, and exact LIQ row clear. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnRobResolveDataCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnLaneCompletionCandidate @@ -133,6 +136,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexDataCandidate bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r323-replay-rob-resolve-data-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 5e99d0e3c2dbd02f1dc7bf5f19659b4af346f8fa. + Reference tests cover successful reduced scalar resolve request formation, absent reduced-destination diagnostics, unsupported multi-lane blocking, diff --git a/docs/chisel/modules/lsu/LoadReplayReturnSideEffectLiveControl.md b/docs/chisel/modules/lsu/LoadReplayReturnSideEffectLiveControl.md index b679e8bc..4b6f43ed 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnSideEffectLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnSideEffectLiveControl.md @@ -107,12 +107,17 @@ wakeup, ROB/PE resolve, replay-row lifecycle clear, or pipe residency. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnSideEffectLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPublishControl bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r381x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 92ab63d0920324fcfbc5c43d0df81c008a96b09d. + Reference tests cover disabled live request, required-mask shaping, LRET-only publication, disabled/flush/no-payload blockers, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/LoadReplayReturnSideEffectReady.md b/docs/chisel/modules/lsu/LoadReplayReturnSideEffectReady.md index c2e1a326..9ebf6846 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnSideEffectReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnSideEffectReady.md @@ -105,11 +105,16 @@ In `LinxCoreFrontendFetchRfAluTraceTop`, R315 wires: Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnSideEffectReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r315-replay-side-effect-ready-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit b83cedaf397c8b20125f2667aaf91dfe2fc5d851. + Reference tests cover all-side-effect readiness, LRET-only readiness, missing sink diagnostics, optional writeback/wakeup suppression, disabled/empty payload diff --git a/docs/chisel/modules/lsu/LoadReplayReturnTimingStatsCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnTimingStatsCandidate.md index 04fc4244..28e069dc 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnTimingStatsCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnTimingStatsCandidate.md @@ -112,6 +112,9 @@ setMemData admission Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnTimingStatsCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnFinalMetadataCandidate @@ -120,6 +123,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeResidencyCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r327-replay-timing-stats-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 369e1dca6696cc5eed55b25822a87db1c3c2faf7. + Reference tests cover sideband copy intent, `ldRntCycle` stamping, unsigned latency increment, underflow diagnostics, disabled/flush/missing-input diff --git a/docs/chisel/modules/lsu/LoadReplayReturnTloadCompletionCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnTloadCompletionCandidate.md index e003c91a..587f317d 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnTloadCompletionCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnTloadCompletionCandidate.md @@ -119,6 +119,9 @@ ROB `subInstCnt`, publish tile-SCB data, update pipe-view logs, set Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnTloadCompletionCandidate bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnReducedScalarShapeControl @@ -128,6 +131,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnIexPipeInsertCandid bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r325-replay-tload-completion-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit bb172ee9388c827604cb3c49904dd2d55ef0950c. + Reference tests cover ordinary scalar pass-through, non-final and final TLOAD sub-instruction returns, disabled/flush/no-lane-completion/invalid-count diff --git a/docs/chisel/modules/lsu/LoadReplayReturnWakeupCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnWakeupCandidate.md index 848a3fd6..01bdff40 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnWakeupCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnWakeupCandidate.md @@ -83,11 +83,16 @@ remain future owners. It consumes `payloadWakeupRequired` from Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnWakeupCandidate bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r313-replay-return-wakeup-candidate-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 7ea14290f475914fa20c5f21cdd7751b282d0450. + Reference tests cover GPR wakeup candidate formation, suppressed regular wakeup, missing destination diagnostics, non-GPR wakeup surfacing, disabled diff --git a/docs/chisel/modules/lsu/LoadReplayReturnWakeupSinkReady.md b/docs/chisel/modules/lsu/LoadReplayReturnWakeupSinkReady.md index af2812f3..cf803ed1 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnWakeupSinkReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnWakeupSinkReady.md @@ -103,6 +103,9 @@ writeback, ROB/PE resolve, replay-row lifecycle clear, or pipe residency. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnWakeupSinkReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnConsumerReady @@ -110,6 +113,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnSideEffectReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r379x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 991c004cc237d672c11bf3d220d1687aa883ccdf. + Reference tests cover live wakeup readiness, live-disabled arming, sink backpressure priority, disabled/flush/no-wakeup diagnostics, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplayReturnWritebackCandidate.md b/docs/chisel/modules/lsu/LoadReplayReturnWritebackCandidate.md index 17c64946..4d6df953 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnWritebackCandidate.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnWritebackCandidate.md @@ -81,11 +81,16 @@ returns remain future owners. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnWritebackCandidate bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r312-replay-return-writeback-candidate-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 80b73c7d314d9f44cb1fe27f6f6bf43acb6a3512. + Reference tests cover GPR writeback candidate formation, missing destination diagnostics, non-GPR suppression, disabled payload blocking, stale-field diff --git a/docs/chisel/modules/lsu/LoadReplayReturnWritebackSinkReady.md b/docs/chisel/modules/lsu/LoadReplayReturnWritebackSinkReady.md index 1cc14e80..98146104 100644 --- a/docs/chisel/modules/lsu/LoadReplayReturnWritebackSinkReady.md +++ b/docs/chisel/modules/lsu/LoadReplayReturnWritebackSinkReady.md @@ -98,12 +98,17 @@ wakeup, ROB/PE resolve, replay-row lifecycle clear, or pipe residency. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnWritebackSinkReady bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnSideEffectReady bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r380x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit ab2032141b62b6f20572cb5b83b120db1bbf204c. + Reference tests cover live writeback readiness, live-disabled arming, RF port backpressure priority, disabled/flush/no-writeback diagnostics, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnReadiness.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnReadiness.md index 0edb3275..479c2ed1 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnReadiness.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnReadiness.md @@ -155,6 +155,9 @@ from already flush-pruned replay-LIQ state. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnReadiness bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotEvidence @@ -163,6 +166,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnScbLiveContro bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r299-replay-liq-source-return-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit a2d0495450fdfe23e2203bcb7ced5815587635d4. + Reference tests cover the current no-external-SCB reduced path, base-data blocking, local snapshot blocking, future pending-SCB blocking, disabled/no-row diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnScbLiveControl.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnScbLiveControl.md index 6e3b068f..0275813e 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnScbLiveControl.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnScbLiveControl.md @@ -107,6 +107,9 @@ Flush clears `active`, suppresses both external SCB outputs, and reports Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnScbLiveControl bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnReadiness @@ -114,6 +117,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayLaunchReadiness bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r389x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 881e6e69ef42baab8e236e11ffb6b6fcc2004080. + Reference tests cover the current no-SCB reduced path, pending/waiting SCB evidence, returned SCB evidence, returned-without-pending diagnostics, diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotAcceptedToken.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotAcceptedToken.md index 30f38142..382cf60e 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotAcceptedToken.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotAcceptedToken.md @@ -204,6 +204,9 @@ cycle is active. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotAcceptedToken bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath @@ -211,6 +214,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotResponseMatch FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r408x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit de8e150bcc06a5441fb46d40d2dd75276768740d. + Reference tests cover accepted-token capture, same-cycle bypass plus consume, resident-token preservation, response consumption, disabled/flush/stale diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotEvidence.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotEvidence.md index 4928f0d3..eab104b3 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotEvidence.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotEvidence.md @@ -144,6 +144,9 @@ snapshot completion. Evidence visible during flush is reported through Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotEvidence bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath @@ -154,6 +157,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnReadiness bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r395x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 0161d86dd94c776153a9b89c17a5a4e3073ee48a. + Reference tests cover idle/no-row behavior, selected-row query requirement, query wait, no-data response completion, data response merge diagnostics, diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotIdentityMatch.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotIdentityMatch.md index 65cd2bb8..3eeefb9f 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotIdentityMatch.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotIdentityMatch.md @@ -139,6 +139,9 @@ through `blockedByFlush`. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotIdentityMatch bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotAcceptedToken @@ -149,6 +152,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r397x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 2833121366f5fad6a7cfe30bf08177864f693cf8. + Reference tests cover disabled/flush suppression, no-query blocking, missing-selected blocking, stale-row rejection, cluster/entry mismatch diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotPath.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotPath.md index c40e8e1f..3e49f80c 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotPath.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotPath.md @@ -757,6 +757,9 @@ keeps LSID-less marker cleanup on the hard-clear path. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestControl @@ -782,6 +785,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadStoreForwarding bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r410x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d9aadbe6f8e963d0b353ae1591e91d6a325703be. + Reference tests cover legacy readiness preservation, dormant query/response behavior, future live accepted-token response completion, flush handling, diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotQueryIssue.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotQueryIssue.md index 7c771fc5..a1eefc06 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotQueryIssue.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotQueryIssue.md @@ -125,6 +125,9 @@ Flush clears `active`, `requestActive`, `queryCandidate`, `queryValid`, and Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotQueryIssue bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestControl @@ -135,6 +138,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r395x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 0161d86dd94c776153a9b89c17a5a4e3073ee48a. + Reference tests cover disabled/flush suppression, disabled live request with a selected row, enabled request with no selected row, sink backpressure, successful diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotReadyControl.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotReadyControl.md index 17f7dd28..bcac68d8 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotReadyControl.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotReadyControl.md @@ -138,6 +138,9 @@ behavior. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotReadyControl bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath @@ -149,6 +152,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayLaunchReadiness bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r395x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 0161d86dd94c776153a9b89c17a5a4e3073ee48a. + Reference tests cover legacy snapshot readiness preservation, optional live snapshot release, required live snapshot blocking/release, disabled/flush/ diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestControl.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestControl.md index d9b517f0..bbb27e00 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestControl.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestControl.md @@ -119,6 +119,9 @@ Flush clears `active`, `requestActive`, `queryCandidate`, and Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestControl bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath @@ -127,6 +130,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r403x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 4e80c172318446d3ef1f26558cb89ce684f200c0. + Reference tests cover the dormant reduced-top shape, live-ready request, raw-sink stall, token-capacity stall, disabled/flush/no-launch diagnostics, and diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestPayload.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestPayload.md index a8f6f0a1..b0afba77 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestPayload.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestPayload.md @@ -139,12 +139,17 @@ request queue owner. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestPayload bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r402x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 5a3454d3a20efd15aa4c2d856fdfc966536df531. + Reference tests cover accepted selected-row payload publication, no-issue blocking, invalid/stale selected rows, disabled/flush suppression, and Chisel diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestQueue.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestQueue.md index 6876d868..14cbe418 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestQueue.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestQueue.md @@ -133,6 +133,9 @@ admission/drain for a deterministic recovery cycle. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestQueue bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestSink @@ -140,6 +143,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r404x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 3ac7026ab681721abe6aa3e0a1bbb33371856829. + Reference tests cover FIFO order, empty-queue same-cycle bypass, full-queue enqueue after resident drain, precise `FlushBus` pruning and compaction, diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestSink.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestSink.md index 71e6d370..a7bf2f56 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestSink.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotRequestSink.md @@ -152,6 +152,9 @@ the visible request head. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotRequestSink bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotLookup @@ -161,6 +164,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r406x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit b530f99b83b53faf7d329fb45c026720d6801705. + Reference tests cover request acceptance only with both sink and response readiness, independent raw-sink and response backpressure, request-identity diff --git a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotResponseMatch.md b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotResponseMatch.md index 26f9e788..a18e177e 100644 --- a/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotResponseMatch.md +++ b/docs/chisel/modules/lsu/LoadReplaySourceReturnStoreSnapshotResponseMatch.md @@ -144,6 +144,9 @@ Response evidence visible during flush is reported through `blockedByFlush`. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotResponseMatch bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshotPath @@ -153,6 +156,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplaySourceReturnStoreSnapshot bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r398x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit d4ca17100186e59c2326df7c7cc73c763aea0484. + Reference tests cover disabled/flush suppression, no-query blocking, unmatched response suppression, SCB-order blocking, ordered wait-store/data evidence, a diff --git a/docs/chisel/modules/lsu/LoadResolveQueue.md b/docs/chisel/modules/lsu/LoadResolveQueue.md index d736c41f..b2df1046 100644 --- a/docs/chisel/modules/lsu/LoadResolveQueue.md +++ b/docs/chisel/modules/lsu/LoadResolveQueue.md @@ -198,12 +198,17 @@ retires the ResolveQ row. R457 additionally proves the exported conflict-row view feeds `MDBConflictDetect` before that retire watermark drains the row. Older focused fixtures remain: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r285-replay-liq-resolveq-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r286-replay-liq-resolve-clear-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r287-replay-liq-resolve-retire-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r289-replay-liq-resolve-precise-flush-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 30a807d9c918569dca6c206d70f42e1d57934c14, source commit 9be80c0e5c63ab69ff9fc2431908933bc66e1acb, source commit 3a1370fc58a165968cd6952c6fb5f993fc5e074c, source commit cd49c163989ed4bb03d622c44e82bd344a53fc3c. + Reference tests cover push/backpressure, inclusive retire pruning, flush clearing, precise `FlushBus` pruning and compaction, conflict-row sidecar preservation, diff --git a/docs/chisel/modules/lsu/MDBConflictDetect.md b/docs/chisel/modules/lsu/MDBConflictDetect.md index 52536ed6..a0df808e 100644 --- a/docs/chisel/modules/lsu/MDBConflictDetect.md +++ b/docs/chisel/modules/lsu/MDBConflictDetect.md @@ -164,7 +164,7 @@ suppressed without importing the ARM-specific model bypass. - `bash tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r290-replay-liq-mdb-detect-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r290-replay-liq-mdb-detect-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 63ee97686659f111f268b8a85c88109f67a04da4. - `bash tools/chisel/run_chisel_tests.sh --only STQCommitQueue` - `bash tools/chisel/run_chisel_tests.sh --only STQEntryBank` - `bash tools/chisel/run_chisel_tests.sh --only STQSCBCommitPath` diff --git a/docs/chisel/modules/lsu/MDBQueueFanout.md b/docs/chisel/modules/lsu/MDBQueueFanout.md index dd7725c0..13083405 100644 --- a/docs/chisel/modules/lsu/MDBQueueFanout.md +++ b/docs/chisel/modules/lsu/MDBQueueFanout.md @@ -235,10 +235,10 @@ the same full identity through backpressure and fanout. - `bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayChiselPath` - `bash tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r291-replay-liq-mdb-fanout-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r292-replay-liq-mdb-lookup-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r293-replay-liq-mdb-delete-boundary-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `FETCH_REPLAY_LIQ_REQUIRE_NONZERO=wait_replay_capture_accepted,wait_replay_relaunch_valid,replay_queue_enqueue_accepted,replay_queue_out_fire,liq_alloc_accepted,liq_base_lookup_granted,source_return_query_issued,source_return_response_apply_valid,source_row_mutation_request_valid,liq_row_mutation_write_enable,resolve_queue_push_accepted,resolve_queue_valid,mdb_conflict_store_valid,mdb_conflict_store_with_resolve_queue_valid,mdb_conflict_resolve_candidate,mdb_conflict_valid,mdb_fanout_record_valid,mdb_fanout_record_accepted,mdb_fanout_record_processed,mdb_fanout_bmdb_report,mdb_fanout_ssit_nonempty,mdb_fanout_lookup_valid,mdb_fanout_lookup_accepted,mdb_fanout_lookup_processed FETCH_REPLAY_LIQ_REQUIRE_ZERO=mdb_lookup_wait_plan_lookup_hit,mdb_lookup_wait_plan_wait_intent_valid,mdb_lookup_wait_plan_request_valid LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r498-replay-liq-mdb-lookup-query-gate --fixture replay-ldi-sdi-ldi --reduced-store-replay-liq --disable-store-memory-mutation --max-seconds 8` +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r291-replay-liq-mdb-fanout-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 61f1c84082b5a4d8e5fe31586406000a018708fe. +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r292-replay-liq-mdb-lookup-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit c4accd44922e2fa88e26ed8b08da9e3cbedd61b5. +- historical evidence only (no current runnable equivalent): `FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r293-replay-liq-mdb-delete-boundary-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 6f5f2912397fd6f136f18beb51b869dc579f4cee. +- historical evidence only (no current runnable equivalent): `FETCH_REPLAY_LIQ_REQUIRE_NONZERO=wait_replay_capture_accepted,wait_replay_relaunch_valid,replay_queue_enqueue_accepted,replay_queue_out_fire,liq_alloc_accepted,liq_base_lookup_granted,source_return_query_issued,source_return_response_apply_valid,source_row_mutation_request_valid,liq_row_mutation_write_enable,resolve_queue_push_accepted,resolve_queue_valid,mdb_conflict_store_valid,mdb_conflict_store_with_resolve_queue_valid,mdb_conflict_resolve_candidate,mdb_conflict_valid,mdb_fanout_record_valid,mdb_fanout_record_accepted,mdb_fanout_record_processed,mdb_fanout_bmdb_report,mdb_fanout_ssit_nonempty,mdb_fanout_lookup_valid,mdb_fanout_lookup_accepted,mdb_fanout_lookup_processed FETCH_REPLAY_LIQ_REQUIRE_ZERO=mdb_lookup_wait_plan_lookup_hit,mdb_lookup_wait_plan_wait_intent_valid,mdb_lookup_wait_plan_request_valid LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r498-replay-liq-mdb-lookup-query-gate --fixture replay-ldi-sdi-ldi --reduced-store-replay-liq --disable-store-memory-mutation --max-seconds 8` Provenance: source commit 5831aa67b2beea67358dabe8e38b21430b5bf005. - `bash tools/chisel/run_chisel_tests.sh --only STQCommitQueue` - `bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob` - `python3 tools/chisel/trace_schema_adapter.py --self-test` diff --git a/docs/chisel/modules/lsu/ReducedLiveLoadLiqCapture.md b/docs/chisel/modules/lsu/ReducedLiveLoadLiqCapture.md deleted file mode 100644 index d39f2f0a..00000000 --- a/docs/chisel/modules/lsu/ReducedLiveLoadLiqCapture.md +++ /dev/null @@ -1,79 +0,0 @@ -# ReducedLiveLoadLiqCapture - -`ReducedLiveLoadLiqCapture` is the E1 admission boundary for an ordinary scalar -load owned by the reduced load-inflight queue (LIQ). It converts the current -E-stage lookup metadata into one `ReducedLoadReplayCandidate` and keeps execute -authoritative until the LIQ allocator accepts that candidate. It does not -fabricate a result or read sparse memory. - -The shape follows the model's separation between IEX address formation, -`LDQInfo::insert`, `LDQInfo::pickL1`, and the later return/writeback path. -The reduced implementation uses the existing `LoadInflightQueue`, -`LoadForwardPipeline`, and LRET/W1/W2 owners for later stages; this module owns -only the E1-to-LIQ contract. - -R672-B carries `loadLsIdFullValid/loadLsIdFull` and the authoritative -youngest-store full snapshot from the accepted execute load into -`ReducedLoadReplayCandidate`; projected LSIDs remain compatibility fields and -do not decide forwarding order. - -## Contract - -Live capture owns only first-pass LIQ admission. A captured row enters LIQ in -`Wait` and must be launched through `LoadForwardPipeline` before it may become -an E4 `Repick` return candidate. The legacy source-return snapshot mutation -path is intentionally disabled while this owner is active: allowing that path -to mutate a newly allocated live row would let it return without a LIQ launch. -For live rows, E2's SCB, STQ, and return-port inputs are initially satisfied; -resident-store forwarding and its replay wakeup remain the owner when an E4 -load actually waits on unavailable store data. LRET capacity is checked only -by the post-E4 return owner, so it cannot block the pipeline before the row's -first return candidate exists. - -| Signal | Direction | Meaning | -| --- | --- | --- | -| `captureEnable` | input | Enables live ordinary-load admission. Disabled or flushed captures are inert. | -| `loadValid` plus metadata | input | Current E1 lookup and its destination, source trace, and ROB/LS identities. | -| `allocReady` | input | LIQ-adapter consumption permission for the current candidate. | -| `candidateValid`, `candidate` | output | Complete LIQ allocation request; metadata is meaningful only while valid. | -| `captureAccepted` | output | LIQ accepted the E1 load. Execute may retire the entry without producing its direct W1 result. | -| `blockedByAlloc` | output | A valid live load could not enter LIQ; E1 holds the same entry and retries. | - -`captureAccepted` is never asserted when disabled, flushed, invalid, or -backpressured. The top-level boundary maps `RenamedDestination` to -`LoadReplayDestination` before this module, preserving the old physical tag -needed by LRET/W1/W2 writeback and wakeup ownership. - -## Pipeline ownership - -```text -E1 scalar load - -> ReducedLiveLoadLiqCapture - -> ReducedLoadReplayLiqAllocPath / LoadInflightQueue - -> E2/E3/E4 LoadForwardPipeline - -> LRET -> W1 -> W2 completion, writeback, wakeup -``` - -The capture path intentionally has no storage of its own. Backpressure holds -the source E1 register, preventing duplicate allocations and preserving the -metadata needed by the LIQ adapter. Flush takes precedence over both the -candidate and acceptance. - -For the live-load wrapper, LIQ E2 launch is gated by base-data and source -readiness, not by pre-existing LRET-pipe readiness. LRET is a post-E4 return -consumer; allowing it to gate E2 would create a circular wait in which no -launch can create the result required to reserve the return pipe. - -## Verification - -`ReducedLiveLoadLiqCaptureSpec` locks the admission truth table and elaborates -the metadata surface. The adjacent execute gate verifies that a captured load -leaves E1 only after the acceptance handshake. The bounded CoreMark/QEMU gate -must show nonzero live-load LIQ allocation and launch counts before this owner -is considered exercised. - -## Deliberate limits - -This is not a cache, memory-response owner, or replay-slot replacement. Load -misses, store-forward waits, refills, and architectural CoreMark termination -remain owned by their corresponding LSU and harness contracts. diff --git a/docs/chisel/modules/lsu/ReducedLoadReplayCompletionDrain.md b/docs/chisel/modules/lsu/ReducedLoadReplayCompletionDrain.md deleted file mode 100644 index b6ba8eef..00000000 --- a/docs/chisel/modules/lsu/ReducedLoadReplayCompletionDrain.md +++ /dev/null @@ -1,164 +0,0 @@ -# ReducedLoadReplayCompletionDrain - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayCompletionDrain.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayCompletionDrainSpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::waitStore` - - `LDQInfo::handleSUWakeup` - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayWakeup.scala` -- Contract IDs: `LC-CHISEL-LSU-STQ-FWD-006` - -## Purpose - -`ReducedLoadReplayCompletionDrain` consumes a queued reduced replay candidate -only when the same load later completes through the reduced execute pipeline. -This models the current reduced-top approximation: the load is held in E while -the resident store is not ready, then advances to W1/W2 and completes once the -store becomes forwardable. - -This is not a full relaunch owner. It does not allocate or mutate -`LoadInflightQueue`, issue a second load, update a ready table, or wake -dependent consumers. It only drains the diagnostic candidate queue when the -reduced in-place completion matches the remembered load identity. R274 expands -that identity check to the model ROB sidecars `BID/GID/RID` plus reduced -`LSID`, preserving the same sidecar shape carried by LinxCoreModel `MemReqBus` -into LDQ rows. R275 leaves matching on that load-completion identity unchanged -but preserves the candidate's forwarding snapshot -`(youngestStoreId, youngestStoreLsId)` through the queue so a later real -`LoadInflightQueue` handoff does not have to recover it from implicit reduced -top aliases. - -## Interface - -### Inputs - -| Signal | Description | -|---|---| -| `candidateValid` | Queue head valid from `ReducedLoadReplayRelaunchQueue`. | -| `candidate` | Remembered replay candidate: load PC, address, size, BID, GID, RID, reduced LSID, and forwarding snapshot `(youngestStoreId, youngestStoreLsId)`. | -| `completeValid` | Reduced execute completion valid. | -| `completeMemLoad` | Completion row is a load memory side effect. | -| `completePc` | Completion row PC. | -| `completeAddr` | Completion row memory address. | -| `completeSize` | Completion row memory size. | -| `completeBid` | Completed row BID. | -| `completeGid` | Completed row GID sidecar. | -| `completeRid` | Completed row RID sidecar. | -| `completeLsId` | Completed row reduced LSID. | - -### Outputs - -| Signal | Description | -|---|---| -| `consumeReady` | Exact match; drive the queue dequeue handshake. | -| `matchValid` | Candidate and load completion were comparable and all identity fields matched. | -| `mismatch` | Candidate and load completion were comparable but at least one identity field differed. | -| `pcMismatch` | PC mismatch diagnostic. | -| `addrMismatch` | Address mismatch diagnostic. | -| `sizeMismatch` | Size mismatch diagnostic. | -| `bidMismatch` | BID mismatch diagnostic. | -| `gidMismatch` | GID mismatch diagnostic. | -| `ridMismatch` | RID mismatch diagnostic. | -| `lsIdMismatch` | LSID mismatch diagnostic. | - -## State - -The module is combinational and stateless. The queue owns candidate residency; -execute owns completion timing. - -## Logic Design - -The model replay path clears a load's wait-store bit through -`LDQInfo::handleSUWakeup`, after which the row can return to the normal wait -and launch path. The reduced top does not yet own full LIQ row launch. Instead -it keeps the load resident in execute while `ReducedStoreResidentForward` -reports wait and completes that same load when forwarding becomes ready. - -R273/R274 therefore drains the queued candidate only on an exact in-place -completion match: - -1. Require a valid queue head and a valid load completion. -2. Compare candidate and completion PC. -3. Compare load address and size from the completion memory sideband. -4. Compare BID, GID, and RID using valid, wrap, and value. -5. Compare reduced LSID using valid, wrap, and value. -6. Assert `consumeReady` only when every compared completion-identity field - matches. The forwarding snapshot is carried through this module's candidate - port but is not part of the current in-place W2 completion comparison. - -If a candidate is pending and a different load completion appears, the module -reports mismatch diagnostics but leaves the candidate queued. That preserves -the first divergence for debug instead of silently discarding the wrong -candidate. - -## Flush/Recovery - -The module has no internal flush state. `ReducedLoadReplayRelaunchQueue` -handles flush clearing and suppresses queue output during flush. - -## Deferred Owners - -- A real LIQ/LDQ relaunch consumer. -- Arbitration between replay candidates and newly issued loads. -- Ready-table or dependent-consumer wakeup. -- Precise replay-candidate recovery pruning by BID/GID/RID/LSID. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayCompletionDrain -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayRelaunchQueue -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadWaitReplaySlot -bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute -bash tools/chisel/run_chisel_tests.sh --only ResidentStoreReplayWakeup -bash tools/chisel/run_chisel_tests.sh --only LoadReplayWakeup -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreResidentForward -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -git diff --check -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r273-replay-completion-drain-1024-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --reduced-store-dispatch-stq --disable-store-memory-mutation --max-seconds 30 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r274-replay-full-identity-1024-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --reduced-store-dispatch-stq --disable-store-memory-mutation --max-seconds 30 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r275-replay-forwarding-snapshot-1024-qemu-elf-xcheck --elf tests/benchmarks/build/coremark_real.elf --expected-rows 0 --capture-rows 1024 --allow-block-markers --allow-block-loop-reentry --reduced-store-dispatch-stq --disable-store-memory-mutation --max-seconds 30 -- -nographic -monitor none -machine virt -m 1280M -kernel tests/benchmarks/build/coremark_real.elf -``` - -Reference tests cover exact completion consumption, non-load completion -suppression, mismatch diagnostics without consumption, absent-candidate -suppression, and Chisel elaboration of match diagnostics. - -R273 live evidence: - -- `generated/r273-replay-completion-drain-1024-qemu-elf-xcheck/report/crosscheck_manifest.json` -- `status=pass`, `comparator_status=0` -- `compared_rows=665`, `mismatch_count=0` -- `cbstop_counts dut=0 qemu=0 inflation_ratio=1.0 warn=false` -- `model/LinxCoreModel=3c0878da3aa1e06669b718e93269f094e7244066` - -R274 live evidence: - -- `generated/r274-replay-full-identity-1024-qemu-elf-xcheck/report/crosscheck_manifest.json` -- `status=pass`, `comparator_status=0` -- `compared_rows=665`, `mismatch_count=0` -- `cbstop_counts dut=0 qemu=0 inflation_ratio=1.0 warn=false` -- `rtl/LinxCore=18d8a800f59e50e4aa912e65e56cab1ae2e37f33` -- `model/LinxCoreModel=3c0878da3aa1e06669b718e93269f094e7244066` -- `emulator/qemu=8f6de68e091dbef19a89b977f3d18cbbc6f43b68` - -R275 live evidence: - -- `generated/r275-replay-forwarding-snapshot-1024-qemu-elf-xcheck/report/crosscheck_manifest.json` -- `status=pass`, `comparator_status=0` -- `compared_rows=665`, `mismatch_count=0` -- `cbstop_counts dut=0 qemu=0 inflation_ratio=1.0 warn=false` -- `rtl/LinxCore=49ed3f993750cb61ec1e829a424154b5d249d8b2` -- `model/LinxCoreModel=793722e85c62eade9ab4e8481c9577dc5b9c98f7` -- `emulator/qemu=ea87f8ca51381e2d0d42424974fe13364a5e074e` diff --git a/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocAdapter.md b/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocAdapter.md deleted file mode 100644 index 3fcacc75..00000000 --- a/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocAdapter.md +++ /dev/null @@ -1,154 +0,0 @@ -# ReducedLoadReplayLiqAllocAdapter - -## R672-B LSID Authority Contract - -The adapter's `LoadInflightAlloc` output uses the configured `lsidWidth` rather -than a ROB-derived or fixed width. Accepted live and relaunched candidates carry -canonical load and youngest-store full-LSID authority, and the adapter copies -both validity/value pairs into `LoadInflightAlloc` without reconstructing them -from projections. - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapterSpec.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `model/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::insert` - - `LDQInfo::updateWaitInfo` - - `LDQInfo::handleSUWakeup` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayWakeup.scala` -- Contract IDs: `LC-CHISEL-LSU-LIQ-002` - -## Purpose - -`ReducedLoadReplayLiqAllocAdapter` is the first typed handoff from the reduced -wait-store replay queue to the real `LoadInflightQueue` allocation shape. It -converts a stable `ReducedLoadReplayCandidate` into `LoadInflightAlloc` without -launching the load, mutating LIQ rows directly, waking consumers, or consuming -the queue head until the downstream allocation boundary is ready. - -The adapter preserves four identity domains: - -- load identity: `BID/GID/RID/loadLsId`, plus PC, address, and size; -- store-order snapshot: `(youngestStoreId, youngestStoreLsIdFull)`, plus a - reduced compatibility projection, captured when - the load originally observed the blocking store relation. -- replay-return signedness: the opcode-derived `returnSignExtend` bit that - later feeds scalar return-data extraction. -- replay destination: the compact renamed destination sideband captured with - the original load lookup for later LRET/writeback/wakeup ownership. -- replay source trace: the R375 RF-derived `sourceTraceValid/source0/source1` - operands captured with the original execute lookup. These fields carry real - source data and must not be replaced by ROB allocation source-register - metadata. - -Keeping those domains separate mirrors the model split between the load row's -own `MemReqBus` identity and the store-forwarding eligibility snapshot used by -`STQ::lookupForLoad` and later store-unit replay wakeups. - -## Interface - -### Inputs - -| Signal | Description | -|---|---| -| `flush` | Suppresses allocation and queue consumption for the cycle. | -| `candidateValid` | Queue-head valid from `ReducedLoadReplayRelaunchQueue`. | -| `candidate` | `ReducedLoadReplayCandidate` payload containing load identity, destination, source traces, return signedness, and forwarding snapshot. | -| `allocReady` | Downstream `LoadInflightQueue.allocReady` or equivalent allocation credit. | - -### Outputs - -| Signal | Description | -|---|---| -| `allocValid` | A usable replay candidate is being presented as `LoadInflightAlloc`. | -| `alloc` | Mapped LIQ allocation payload. `isTile`, `specWakeup`, and `stackValid` are false for this reduced scalar replay path. | -| `consumeReady` | Queue-head consume pulse. Asserted only when `allocValid && allocReady`. | -| `blockedByAlloc` | Candidate is usable, but downstream allocation is backpressured. | -| `candidateUsable` | `candidateValid && candidate.valid && !flush`; exposed for diagnostics. | - -## State - -The adapter is combinational and owns no storage. The replay queue remains the -resident-state owner for pending candidates. `LoadInflightQueue` remains the -registered LIQ row owner after `consumeReady` fires. - -## Logic Design - -The C++ model sequence is: - -1. `STQ::lookupForLoad` finds overlapping older stores by `(BID, LSID)` order - and records a wait-store producer when selected bytes are not data-ready. -2. `LDQInfo::updateWaitInfo` / `waitStore` records that producer on the load - row and leaves the load in a wait state. -3. `LDQInfo::handleSUWakeup` clears matching wait-store state and may merge - store data into miss rows when the waking store is no newer than the load's - store-order snapshot. -4. The load returns to the ordinary wait/relaunch path. - -The reduced replay path already owns steps 1 through 3 diagnostically: -`ReducedStoreResidentForward` selects the producer, `ReducedLoadWaitReplaySlot` -captures and clears it through `LoadReplayWakeup`, and -`ReducedLoadReplayRelaunchQueue` makes the clear event persistent. This adapter -adds the next boundary: the queue head can become a normal LIQ allocation -request without reconstructing identity from top-level wires. - -Mapping is direct: - -- `candidate.bid/gid/rid/loadLsId` -> `alloc.bid/gid/rid/loadLsId` -- `candidate.pc/addr/size` -> `alloc.pc/addr/size` -- `candidate.returnSignExtend` -> `alloc.returnSignExtend` -- `candidate.dst` -> `alloc.dst` -- `candidate.sourceTraceValid/source0/source1` -> - `alloc.sourceTraceValid/source0/source1` -- `candidate.youngestStoreId/youngestStoreLsId` -> - `alloc.youngestStoreId/youngestStoreLsId` -- `candidate.youngestStoreLsIdFullValid/youngestStoreLsIdFull` -> - `alloc.youngestStoreLsIdFullValid/youngestStoreLsIdFull` -- reduced scalar flags are false: `isTile=false`, `specWakeup=false`, - `stackValid=false` - -## Timing - -`allocValid` stays high while the queue head is usable and `allocReady` is low. -`consumeReady` is the only queue pop condition and is asserted only on the -accepted allocation cycle. This follows the model queue rule: inspect the head -while stalled, consume it only when ownership transfers. - -## Flush/Recovery - -`flush` masks the combinational allocation request and deasserts -`consumeReady`. The queue and LIQ owners still own their own registered flush -state. This module does not prune by BID/LSID; precise LSU recovery remains a -future LIQ/LDQ owner. - -## Deferred Owners - -- Wiring `ReducedLoadReplayLiqAllocPath` into `LinxCoreFrontendFetchRfAluTraceTop`. -- Full LIQ allocation/relaunch arbitration with newly issued loads. -- Load-store conflict recovery and LHQ/ResolveQ movement. -- Ready-table and dependent-consumer wakeup after relaunch. -- Precise flush pruning by load BID/RID/LSID. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayLiqAllocAdapter -bash tools/chisel/run_chisel_tests.sh --only LoadInflightQueue -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadWaitReplaySlot -``` - -Reference tests cover identity/snapshot/destination mapping, allocation -backpressure, flush/absent-candidate suppression, and Chisel elaboration of the -allocation handshake plus `loadLsId`, destination, and forwarding snapshot -fields. diff --git a/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocPath.md b/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocPath.md deleted file mode 100644 index d85968e3..00000000 --- a/docs/chisel/modules/lsu/ReducedLoadReplayLiqAllocPath.md +++ /dev/null @@ -1,429 +0,0 @@ -# ReducedLoadReplayLiqAllocPath - -## R672-B LSID Authority Contract - -`lsidWidth` is independent of LIQ, STQ, and ROB capacity. The composition -threads it through allocation payloads, resident LIQ rows, precise flush, -launch/return selectors, resolved LHQ publication, and native row-mutation -wait metadata. Candidate full-LSID authority reaches LIQ residency before -snapshot selection. The R672-B forwarding owner consumes that resident full -snapshot for same-BID order; the projection does not authorize ordering. - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPathSpec.scala`, - `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayToLiqPathSpec.scala`, - `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::insert` - - `LDQInfo::updateWaitInfo` - - `LDQInfo::handleSUWakeup` - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadInflightLaunchSelect.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadInflightRowMutationRequestBridge.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayReturnConsumerReady.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadResolveQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala` -- Contract IDs: `LC-CHISEL-LSU-LIQ-003` - -## Purpose - -`ReducedLoadReplayLiqAllocPath` is the composition boundary between queued -reduced replay candidates and registered LIQ row state. It instantiates -`ReducedLoadReplayLiqAllocAdapter`, `LoadInflightQueue`, and the R280 -`LoadInflightLaunchSelect` selector. It still uses the LIQ allocation handshake -as the only authority for consuming the replay queue head, and R311 carries the -candidate's compact replay destination sideband through allocation, residency, -selected-row diagnostics, and the LRET-payload diagnostic boundary. R375 -carries the candidate's RF-derived source-trace sideband through the same -allocation, residency, and selected-row diagnostic path while keeping the W2 -commit-row source provider disabled. - -This module is intentionally narrower than full replay. It does not drive the -LIQ launch port unless `launchEnable` is explicitly asserted by the parent, and -the reduced top keeps that input disabled. It also does not arbitrate new loads -against replay loads or wake dependent consumers. Its job is to prove that the -candidate payload can become normal LIQ residency, expose when resident rows -satisfy the model-derived scalar replay-pick predicate, and provide the -path-local launch/E4/LHQ diagnostic boundary needed before the top enables live -replay. R285 gives the path-local `lhqRecord` output a top-level -`LoadResolveQueue` storage consumer, and R286 has the top feed back a delayed -`clearResolved` request once that consumer accepts the record. Retire and live -MDB publication remain outside this module. - -R417 replaces the R416 tie-off with a source-shaped row-mutation bridge. The -path accepts the R410 -`LoadReplaySourceReturnStoreSnapshotRowMutationRequest` payload shape, uses -`LoadInflightRowMutationRequestBridge` to translate the source wait-store ID -width into the LIQ-native `storeEntries` width, and drives the child -`LoadInflightQueue` native row-mutation port. R445 lets the current reduced top -drive the source path's guarded `rowMutationLiveEnable` true, so the bridge and -native writer can now accept source-shaped local-STQ response mutations after -the source head-proof and LIQ write-control guards pass. R428 forwards the -bridge, native write-control, and aggregate row-mutation blocker diagnostics -through the reduced top IO so -future live-mutation packets can be compared at the wrapper boundary before -changing the enable policy. R429 also forwards the child LIQ write-control -blocker reasons, making the model-required valid/Repick/SCB-return and -same-row writer-conflict prerequisites visible without changing the disabled -live arm. - -R418 splits the E2 source-return inputs passed into `LoadInflightQueue`. -`e2ScbReturned` now carries only the SCB source bit, while `e2StqReturned` -carries the local STQ/store-source bit from `LoadReplaySourceReturnReadiness`. -The downstream `LoadForwardPipeline` still requires load-data, SCB, and -STQ/store source bits before asserting the combined `sourcesReturned` row -state. R453 exposes the child LIQ refill wakeup input at this composition -boundary so a generated-RTL fixture can prove allocated replay rows become -launchable through the existing row-owned refill path; the live reduced top -ties this input inactive. R464 exposes the child LIQ replay-wakeup input and -completion masks at the same boundary. R513 removes the stale live-top -replay-wakeup tie-off, so resident-store wakes now reach the child -`LoadInflightQueue`; the generated-RTL wait/replay probe uses the same -interface to supply SCB source-return evidence through the native -`LoadReplayWakeup` owner before an MDB row mutation writes. R449 adds an -end-to-end reference-owner test for the -pre-launch half of -the path. It proves that a relaunch candidate generated by the wait-store owner -can be queued and allocated into LIQ residency with the original load identity -and forwarding snapshot intact. It is not a live top replay proof; the current -live architectural store/load probe still produces zero wait/replay counters. - -R487 forwards the child LIQ `scbReturn*` proof port. This gives the top-level -source-return accepted-token owner a narrow way to record model -`handleSCBReceive` ordering evidence on a selected `Repick` row without -driving the broader replay-wakeup byte-merge path. - -R489 keeps the same pass-through clear interface but records the widened child -LIQ contract: `clearResolvedValid` may now clear either an explicit -`Resolved` row or a complete source-returned `Repick` row selected by the -parent replay-return lifecycle path. - -R512 localizes `LoadReplayWakeMatchDiagnostics` under this path so replay-wake -predicate masks are sampled from the same LIQ row image that feeds the child -`LoadInflightQueue` clear path. The top still exports the masks for generated -RTL sideband evidence, but no longer owns a separate diagnostic instance over a -second observation boundary. - -R513 proves the reduced top's live replay-wakeup input is no longer suppressed -by the refill tie-off helper. The loop fixture now records nonzero path-local -`StoreUnit`, full-match, and wait-store-clear counters and drains cleanly. -R514 scales that same fixture from 18 to 36 captured QEMU rows without RTL -changes. The longer gate records five replay-queue fires and three path-local -wait-store clears while still draining cleanly, so the R513 fix is not only a -single-pass coincidence. - -R555 tightens the parent clear ownership around replay-return lifecycle. A -direct LHQ hit that appends to `LoadResolveQueue` still uses the R286 delayed -clear path. A replay-return row that has just become return-complete no longer -uses the old complete-`Repick` head clear when that row is also the selected -return-complete target; it remains visible as `Resolved` until the W2 lifecycle -owner matches the resident slot identity. When that W2 lifecycle clear is -accepted, the top retires the matching ResolveQ entry by the row's BID and -load LSID. This keeps LIQ row clear and ResolveQ retirement coupled for -replay-return rows without changing this composition's pass-through -`clearResolved` interface. - -## Interface - -### Inputs - -| Signal | Description | -|---|---| -| `flush` | Flushes the internal LIQ and suppresses candidate consumption. | -| `candidateValid` | Queue-head valid from `ReducedLoadReplayRelaunchQueue`. | -| `candidate` | Queued reduced replay candidate with load identity, destination, source traces, return signedness, and forwarding snapshot. | -| `launchEnable` | Parent-owned arm bit. When low, selector diagnostics remain visible but `LoadInflightQueue.launchValid` is not driven. | -| `pickValid` / `pickIndex` | Parent-owned R486 pick-only request. It marks the selected LIQ row `Repick` without running `LoadForwardPipeline`. | -| `scbReturnValid` / `scbReturnIndex` | Parent-owned R487 SCB-return proof request. It marks a selected `Repick` row `scbReturned` without merging data. | -| `e2Stores` | Abstract STQ forwarding rows for the `LoadForwardPipeline` launch path. R283 top wiring feeds a `ResidentStoreForwardStoreSnapshot` vector while keeping launch disabled. | -| `e2BaseData` / `e2BaseValidMask` | Baseline line data and valid bytes for relaunches that do not already have row-owned data. R295 top wiring shapes the selected row's scalar sparse-memory response through `LoadReplayBaseDataAlign` while keeping launch disabled; R296 gates those inputs with `LoadLookupArbiter.replayGranted` so execute-returned sparse-memory bytes cannot feed the replay row. R297 routes the same grant-qualified data-return predicate through `LoadReplayLaunchReadiness`. | -| `e2LoadDataReturned` / `e2ScbReturned` / `e2StqReturned` / `e2ReturnReady` | Source-return and return-slot readiness sidebands consumed by `LoadForwardPipeline`. R418 drives `e2ScbReturned` from `LoadReplaySourceReturnReadiness.scbSourceReturned` and `e2StqReturned` from `storeSourceReturned`. R305 drives `e2ReturnReady` from `LoadReplayReturnReadiness` fed by the consumer-ready, budget, permit, and select split; the reduced top arms the budget but keeps the downstream LRET and mem-wakeup sinks low. | -| `replayWakeValid` / `replayWake` | Pass-through store-unit/SCB replay wakeup to the child `LoadInflightQueue`. The live reduced top forwards resident-store replay wakeups and holds an unconsumed ready-store wake while its resident store still matches; the generated-RTL wait/replay probe drives the same interface to mark a live target row source-returned before an MDB wait mutation. | -| `clearResolvedValid` | Pass-through clear request for future tests or consumers that resolve rows. Since R489, the child LIQ also accepts a complete source-returned `Repick` row on this path. | -| `clearResolvedIndex` | LIQ slot for `clearResolvedValid`. | -| `rowMutationRequestValid` / `rowMutationRequestTargetMask` / `rowMutationRequestTargetIndex` | Source-shaped R410 row-mutation request validity and LIQ target. Current top drives these from `LoadReplaySourceReturnStoreSnapshotPath`, whose live arm remains false. | -| `rowMutationSetWaitStatus` / `rowMutationKeepRepickStatus` / `rowMutationClearReturnState` | Future status and split-return-state writes for wait-store rewait or continued repick. | -| `rowMutationLineWrite` / `rowMutationWaitStoreWrite` | Future row-data and wait-store-state write enables. | -| `rowMutationNextWaitStore*` | Source-shaped wait-store payload. The bridge converts `rowMutationNextWaitStoreInfo` from source ID width to native `storeEntries` width. | -| `rowMutationNextLineData` / `rowMutationNextValidMask` / `rowMutationNextDataComplete` | Future row data image from the source snapshot row-state plan. | -| `rowMutationNextScbReturned` / `rowMutationNextStqReturned` / `rowMutationNextStoreSourceReturned` | Future split source-return state from the source snapshot row-state plan. | -| `refillValid` / `refill` | Pass-through read-refill wakeup to the child `LoadInflightQueue`. The live reduced top ties this inactive; the generated-RTL wait/replay probe drives it to make an allocated replay row launchable through row-owned data. | - -### Outputs - -| Signal | Description | -|---|---| -| `candidateConsumeReady` | Connects to replay-queue `outReady`; high only when LIQ allocation accepts. | -| `candidateUsable` | The queue head is valid and not masked by flush. | -| `candidateBlockedByAlloc` | Queue head is usable but the LIQ allocation pointer is not free. | -| `allocValid` | Adapter-presented allocation request. | -| `allocReady` | LIQ allocation pointer is free and flush is inactive. | -| `allocAccepted` | Candidate allocated into LIQ row state this cycle. | -| `allocIndex` | LIQ allocation slot. | -| `allocLoadId` | Slot-plus-wrap `LID` assigned by `LoadInflightQueue`. | -| `rows` | Current LIQ row image. | -| `occupiedMask` | Resident LIQ rows. | -| `waitMask` | Rows in `Wait`. | -| `waitStoreMask` | Rows waiting on a store. This path allocates replay-ready rows, so newly allocated rows do not set it. | -| `launchWaitMask` | `LoadInflightLaunchSelect` view of valid `Wait` rows. | -| `launchWaitStoreBlockedMask` | `Wait` rows still blocked by wait-store state. | -| `launchTileBlockedMask` | `Wait` rows suppressed because this selector is scalar-only. | -| `launchUnblockedWaitMask` | Scalar `Wait` rows with no wait-store block. | -| `launchRequestCompleteMask` | Unblocked rows whose row-owned valid bytes cover the requested load bytes. | -| `launchDataHitMask` | Unblocked rows with `l1Hit`, `storeBypass`, or complete requested row-owned bytes. | -| `launchCandidateMask` | Enabled `launchDataHitMask` candidates. | -| `launchMask` | One-hot oldest selected scalar candidate. Diagnostic only in this path. | -| `launchValid` / `launchIndex` | Selector request before parent `launchEnable` qualification. | -| `launchCandidateCount` | Number of selector candidates. | -| `launchSelected*` | R294/R305/R307/R311/R375 selected launch-row identity from `LoadInflightLaunchSelect`: LIQ load ID, BID/GID/RID, load LSID, PC, address, size, replay-return signedness, replay destination, source trace, 64-byte request mask, `specWakeup`, and `stackValid`. These signals remain diagnostic while `launchEnable` is low. | -| `launchDriveValid` | Actual valid presented to `LoadInflightQueue.launchValid`; low unless the parent-owned `launchEnable && launchValid` predicate is true. Since R305, the reduced top drives return readiness from `LoadReplayReturnReadiness` fed by `LoadReplayReturnConsumerReady` plus the budget/permit/select split; the LRET and mem-wakeup sinks remain low, so launch stays disabled. | -| `launchReady` | Selected row is launch-ready in `LoadInflightQueue`. | -| `launchAccepted` | Selected row entered `Repick` through `LoadInflightQueue`. | -| `pickReady` / `pickAccepted` | Child LIQ response for the R486 pick-only path. | -| `scbReturnReady` / `scbReturnAccepted` | Child LIQ response for the R487 SCB-return proof path. | -| `repickMask` / `missMask` / `resolvedMask` | Pass-through LIQ state masks after any enabled relaunches. | -| `e4UpdateValid` / `e4UpdateIndex` / `e4MissKind` / `e4WakeupValid` | Pass-through E4 outcome diagnostics from the launched-row pipeline. | -| `lhqRecordValid` / `lhqRecord` | Path-local resolved-load hit record, including load PC after R284. R285 top wiring can append this row to `LoadResolveQueue`; R286 top wiring clears the resolved LIQ row after that append is accepted. This module itself does not own ResolveQ backpressure, retire, or MDB publication. | -| `residentCount` | Resident LIQ row count. | -| `empty` / `full` | LIQ occupancy diagnostics. | -| `missPending` | Pass-through LIQ miss-pending diagnostic. | -| `clearResolvedAccepted` | Pass-through `LoadInflightQueue` clear response. | -| `rowMutationBridgeValid` / `rowMutationSourceStoreIndexFits` | R417 bridge admission diagnostics before the native LIQ row-mutation port. | -| `rowMutationInvalid*` | Bridge/payload invalid diagnostics for out-of-range source store index, conflicting status writes, wait-store payload without wait status, and inconsistent split-return state. | -| `rowMutationWriteEnable` / `rowMutationApplyValid` / `rowMutationTargetEvidenceValid` / `rowMutationWriteConflict` | Native `LoadInflightQueue` row-mutation storage diagnostics from the R416 row owner. | -| `rowMutationBlockedByBridge` / `rowMutationBlockedByControl` | Request blocked before native shape conversion or by the LIQ row-mutation write-control policy. | -| `rowMutationControlBlockedBy*` | R429 detailed native write-control blocker reasons from `LoadInflightQueue`: invalid target row, not-Repick state, missing SCB return, E4 update conflict, clear-resolved conflict, replay-wakeup conflict, refill conflict, launch conflict, and allocation conflict. | -| `replayWakeWaitStoreCandidateMask` / `replayWakeBidMatchMask` / `replayWakeLsIdMatchMask` / `replayWakePcMatchMask` / `replayWakeFullMatchMask` / `replayWakeStoreUnit` / `replayWakeStoreUnitFullMatchMask` | R512 path-local replay-wake predicate diagnostics sampled from this path's LIQ row image before the top sideband counters classify active store-unit full matches. | -| `replayWakeWaitStoreClearMask` / `replayWakeMergeMask` / `replayWakeCompletedMask` | Child LIQ replay-wakeup diagnostics passed through for generated-RTL evidence. R512 records these beside the path-local predicate masks so full-match and clear-mask evidence share the same owner boundary. | -| `refillAccepted` / `refillWakeMask` | Child LIQ refill-wakeup diagnostics. | - -## State - -The composition owns no state beyond its child `LoadInflightQueue`. The replay -queue remains the pending-candidate owner before `candidateConsumeReady`, and -`LoadInflightQueue` owns row residency after `allocAccepted`. - -## Logic Design - -The C++ model creates load rows in `LDQInfo::insert`, records wait-store -state through `LDQInfo::updateWaitInfo` / `waitStore`, and later clears -matching store waits in `LDQInfo::handleSUWakeup`. Once wait-store state is -cleared, the row returns to the normal wait/relaunch path. In Chisel, the -reduced wait slot and replay queue produce the same cleared load as a -`ReducedLoadReplayCandidate`. - -`ReducedLoadReplayLiqAllocPath` maps that candidate into real LIQ residency: - -1. `ReducedLoadReplayLiqAllocAdapter` converts the candidate into - `LoadInflightAlloc`. -2. `LoadInflightQueue.allocReady` backpressures the adapter when the allocation - pointer names a resident row. -3. `candidateConsumeReady` fires only with `allocAccepted`, transferring - ownership from the replay queue into LIQ row state. -4. The allocated row stays in `Wait` with row-owned `loadLsId` plus the - forwarding snapshot `(youngestStoreId, youngestStoreLsId)`. -5. `LoadInflightLaunchSelect` scans the resulting LIQ row image and exposes the - model `pickL1` predicates: `Wait`, no wait-store block, non-tile, - data-hit/request-complete, and oldest `(BID, loadLsId)` selection. - R294 carries the selector's selected-row PC, address, size, load ID, - BID/GID/RID, load LSID, and request-byte mask through this path so the - parent can wire base-data lookup and launch arbitration later without - re-scanning the row array. - R305 extends that selected-row surface with `specWakeup` and `stackValid` - so `LoadReplayReturnConsumerReady` can require the model mem-wakeup sink - only for rows that did not already get speculative wakeup and are not stack - loads. - R307 extends the same surface with `returnSignExtend`, preserving the - opcode-derived sign/zero-extension choice needed by - `LoadReplayReturnDataExtract`. R311 extends the same surface with the - compact replay destination sideband so later return-payload and wakeup - owners do not need to reconstruct the renamed destination from top-level - context. R375 extends the same surface with RF-derived - `sourceTraceValid/source0/source1` so future replay W2 commit-row source - fill can consume row-owned provenance rather than ROB allocation metadata. - R295 has the top consume that selected row in `LoadReplayBaseDataAlign`, - producing dormant `e2BaseData/e2BaseValidMask` inputs for the same selected - row. R296 drives those dormant inputs only when `LoadLookupArbiter` grants - the selected replay row on the shared sparse-memory lookup port. R297 adds - `LoadReplayLaunchReadiness` as the parent launch arm predicate, R299 feeds - its source-return input from `LoadReplaySourceReturnReadiness`, and R300 - feeds its return-ready input from `LoadReplayReturnReadiness`. R305 inserts - `LoadReplayReturnConsumerReady` behind the budget arm, separating the - always-required IEX LRET sink from the conditional mem-wakeup sink. Launch - stays disabled until those sinks are real. -6. R282 adds an explicit parent-owned `launchEnable` gate. When it is high, - the selector's `launchValid/launchIndex` drive `LoadInflightQueue`, which - relaunches the row through `LoadForwardPipeline` using `e2Stores`, - `e2BaseData`, `e2BaseValidMask`, and source-return sidebands. When it is - low, all selector diagnostics remain visible but no LIQ state is mutated by - launch. -7. R486 adds a parent-owned pick-only gate in parallel with launch. The reduced - top drives this from the source-return snapshot query issue so the selected - row enters `Repick` before STQ response matching, but final launch/E4 still - waits for source-return and replay-return readiness. -8. R487 forwards a parent-owned SCB-return proof gate in parallel with launch - and pick. The top drives it from the source-return accepted token after that - token is resident, matching the model order where SCB receive records - `scbRnt` before STQ receive applies the store snapshot. -9. R417 adds the source-shaped row-mutation bridge in parallel with launch - selection. The bridge accepts the R410 request shape, blocks malformed or - out-of-range wait-store identities, and feeds the child LIQ native mutation - port. The native writer still enforces the R416 target-row and same-cycle - conflict policy before mutating registered row state. -10. R418 passes split SCB and STQ/store source-return bits to the child LIQ so - E4 row state can preserve `scbReturned` and `stqReturned` separately while - keeping the combined `sourcesReturned` wakeup behavior unchanged. -11. R453 passes read-refill wakeups through to the child LIQ. Refilled rows use - the normal `LoadRefillWakeup` update path: matching working rows return to - `Wait` with `l1Hit` and full row-owned valid bytes, allowing - `LoadInflightLaunchSelect` to select them without changing allocation or - row-mutation ownership. -12. R454 drives the existing E2 source-return and return-ready sidebands from - the generated-RTL fixture, then observes the child LIQ's existing E4 - outcome, LHQ hit-record, and `Resolved` status outputs. The E4/LHQ - observation is one cycle after launch, and the registered `Resolved` mask - follows on the next clock. -13. R455 composes the fixture LHQ record with `LoadResolveQueue` and feeds the - child LIQ `clearResolved` input one cycle after the queue accepts the - record, matching the R286 top-level delayed-clear contract. -14. R464 passes replay wakeups through to the child LIQ. A parent-provided SCB - wake uses the existing `LoadReplayWakeup` logic to merge bytes and mark - matching non-`Repick` working rows `scbReturned/sourcesReturned`. If that - row is then launched, `LoadInflightQueue` preserves the source-return - evidence into `Repick`, satisfying the row-mutation write-control - prerequisite for MDB wait re-mutation. -15. R555 splits parent clear ownership for replay-return rows. Direct LHQ - ResolveQ insertion still drives delayed existing clear, while returned-load - W2 lifecycle clear retires ResolveQ from the same row image it clears from - LIQ. - -The replay and refill wakeup ports remain inactive in this owner unless a -parent wires them; the live reduced top ties both inactive through helper -wiring. The R283 -reduced top keeps `launchEnable` low but feeds `e2Stores` from a shared -`ResidentStoreForwardStoreSnapshot`, so the path has model-shaped resident STQ -store candidates available before live replay launch is armed. Base-data and -return-readiness boundaries are wired but disabled where required; live -arbitration wiring remains deferred. R285 consumes the -path-local LHQ hit-record output in the top-level `LoadResolveQueue`, but this -path still relies on the parent to decide when a resolved row should clear LIQ -state or become visible to MDB conflict detection. R286 records that parent -clear timing: the top delays `clearResolvedValid` until the cycle after -ResolveQ accepts the LHQ record, when the source LIQ row is resident in -`Resolved` state. -R417 connects the child LIQ native row-mutation port to the source-shaped -bridge in this composition. R445 promotes the upstream source live arm, so this -path may now write the child LIQ row when the source proof and native -write-control checks both pass. -R429 only forwards the existing child LIQ write-control blocker reasons; it -does not change the bridge request, write-enable predicate, or registered row -mutation behavior. - -## Timing - -The path is a single-cycle ready/valid allocation boundary around the replay -queue head. If LIQ is full, `candidateBlockedByAlloc` is high and -`candidateConsumeReady` remains low, so the queue keeps the head resident. A -same-cycle flush suppresses allocation and consumption. - -## Flush/Recovery - -`flush` is passed directly to `LoadInflightQueue` and the adapter. It clears -resident LIQ state and returns the allocation pointer to slot zero. Precise -LSU recovery pruning by BID/RID/LSID is still a deferred LIQ/LDQ recovery -owner. - -## Deferred Owners - -- Live default `LinxCoreFrontendFetchRfAluTraceTop` replay replacement. R279 - wires this composition only through the opt-in reduced-store replay-LIQ - wrapper and diagnostics. -- Top-level launch selection between new loads and replay loads. R281 exposes - `LoadInflightLaunchSelect` through this path and the opt-in top diagnostics, - and R282 adds the path-local launch drive gate, but the reduced top still - leaves that gate disabled. -- External SCB replay response ownership and real LRET/mem-wakeup sink - readiness for enabled relaunch. -- Live enable of `LoadReplaySourceReturnStoreSnapshotRowMutationRequest` and - raw source-response evidence that can produce active row-mutation requests. -- Default/live LIQ ResolveQ insertion and load-store conflict publication. -- Ready-table, bypass, and dependent-consumer wakeup. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayLiqAllocPath -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayToLiqPath -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayChiselPath -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayLiqAllocAdapter -bash tools/chisel/run_chisel_tests.sh --only LoadInflightQueue -bash tools/chisel/run_chisel_tests.sh --only LoadInflightLaunchSelect -bash tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -``` - -Reference tests cover allocation-pointer order, preservation of load LSID, -destination, and forwarding snapshot sidecars, full-LIQ backpressure without -queue consumption, flush clearing, and Chisel elaboration with the adapter, LIQ -row owner, and launch selector child modules. R282 elaboration also locks the path-local -`launchEnable`, E2 forwarding inputs, launch accepted/ready outputs, E4 -diagnostics, LHQ hit-record output, and miss-pending diagnostic. -R429 elaboration also locks the detailed row-mutation write-control blocker -output names so downstream top-level diagnostics can distinguish model -prerequisite failures from same-row writer conflicts. -R449 locks the cross-owner wait-store-to-LIQ allocation contract while live -launch, source-return mutation, and row lifecycle side effects remain disabled. -R451 adds a test-only Chisel composition probe that connects the real STQ row -owner through the resident-forward, wait-slot, replay-wakeup, relaunch-queue, -and LIQ allocation modules. This probe is fixture evidence for the -address-ready/data-late timing window R450 could not reach through the live -`LDI`/`SDI`/`LDI` top stimulus; it is not itself QEMU/live promotion evidence. -R452 makes the probe executable through Verilator. The generated-RTL harness -asserts that the relaunch queue fires into this LIQ path and that the first -resident LIQ row preserves the `youngestStoreLsId` sidecar from the blocking -store. -R453 extends that generated-RTL harness to drive a refill wakeup after LIQ -allocation, assert that the refilled row becomes a launch candidate, and then -assert `launchEnable` long enough for `launchAccepted` to move the row into -`Repick`. The passing report records `liq_refill=true`, -`liq_launch_valid=true`, `liq_launch_accepted=true`, and `launch_load_lsid=3`. -R454 extends the same harness to drive source-return and return-port readiness -on the launch cycle. The passing report records `liq_e4_update=true`, -`liq_lhq_record=true`, `liq_resolved=true`, and -`e4_cycles_after_launch=1`, proving the existing path-local E4/LHQ diagnostics -and registered resolved-row transition under generated RTL. The proof remains -fixture-driven and does not promote the live reduced top. -R455 extends the same harness through the next owner boundary: -`LoadResolveQueue` accepts the LHQ record, the delayed `clearResolved` request -clears the LIQ row, and the ResolveQ record remains resident. The passing -report records `resolve_queue_push=true`, `liq_clear_resolved=true`, and -`resolve_queue_count=1`. This remains generated-RTL fixture evidence because -the replay launch, refill, source-return sidebands, and return readiness are -harness-driven. -R464 locks the replay-wakeup pass-through and positive MDB row-write evidence. -The generated-RTL report records `liq_replay_wake_completed_mask=2`, -`liq_scb_returned_mask_before_mdb_write=2`, -`mdb_lookup_wait_plan_write=true`, `mdb_lookup_wait_plan_apply=true`, and -`liq_wait_store_mask_after_mdb_write=2`, proving the row write uses native LIQ -source-return evidence rather than bypassing write-control. -R487 locks the direct SCB-return proof pass-through at this composition -boundary. Focused elaboration checks cover `scbReturnValid`, `scbReturnReady`, -and `scbReturnAccepted` so the top can drive model ordering evidence without -changing replay-wakeup ownership. -R489 keeps the same `clearResolved*` pass-through while relying on -`LoadInflightQueue` to classify complete source-returned `Repick` rows as -clearable terminal rows. - -R669 sizes `rowMutationNextWaitStoreInfo.storeIndex` with `storeEntries` -instead of `idEntries`. This keeps a physical STQ row above the ROB count -intact until the existing mutation bridge validates and writes the LIQ row. diff --git a/docs/chisel/modules/lsu/ReducedLoadReplayRelaunchQueue.md b/docs/chisel/modules/lsu/ReducedLoadReplayRelaunchQueue.md deleted file mode 100644 index c7de0500..00000000 --- a/docs/chisel/modules/lsu/ReducedLoadReplayRelaunchQueue.md +++ /dev/null @@ -1,156 +0,0 @@ -# ReducedLoadReplayRelaunchQueue - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueueSpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::waitStore` - - `LDQInfo::handleSUWakeup` - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `tools/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp` - - `SimInstInfo::GenRFReqBus` - - `SimInstInfo::RFRetSetData` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocAdapter.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayLiqAllocPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayCompletionDrain.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ResidentStoreReplayWakeup.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayWakeup.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala` -- Contract IDs: `LC-CHISEL-LSU-STQ-FWD-005` - -## Purpose - -`ReducedLoadReplayRelaunchQueue` is the first owner after -`ReducedLoadWaitReplaySlot` that consumes a wait-store-clear relaunch -candidate. The wait slot emits only a one-cycle pulse when -`LoadReplayWakeup` clears the remembered wait-store key; this queue records -that pulse into a finite FIFO so a later LIQ or issue owner can observe a -stable pending replay request. - -R672-B parameterizes candidate LSID width and preserves load full-LSID -validity/value across FIFO residency and bypass. - -This module does not launch a load, allocate or mutate `LoadInflightQueue` -rows, update a ready table, or wake dependent consumers. It owns only -candidate admission, FIFO ordering, flush clearing, dequeue handshake, and -overflow diagnostics. In the reduced top after R273, -`ReducedLoadReplayCompletionDrain` drives `outReady` only when the held load -later completes with matching identity. R275 makes the candidate payload match -the future LIQ allocation/relaunch boundary more directly by carrying the -forwarding snapshot `(youngestStoreId, youngestStoreLsId)` as explicit -sidecars in addition to BID/GID/RID/reduced-LSID load identity. -R307 also preserves the replay-return signedness sideband derived from the -original load opcode, so the queued request can later drive the standalone -return-data extractor without recovering opcode class from top-level wires. -R311 preserves the captured renamed destination sideband for the later -LRET/wakeup payload owner. R375 preserves the original RF-derived -`sourceTraceValid/source0/source1` operands in the same FIFO entry so replay W2 -row-fill work can consume real source data instead of reconstructing it from -allocation metadata. - -## Interface - -### Inputs - -| Signal | Description | -|---|---| -| `flush` | Clears the queue and suppresses enqueue/dequeue for the cycle. | -| `enqueueValid` | Candidate-valid pulse from the reduced wait-store slot. | -| `enqueue` | `ReducedLoadReplayCandidate` payload: remembered load PC, address, size, return signedness, destination, source traces, BID, GID, RID, reduced LSID, and forwarding snapshot `(youngestStoreId, youngestStoreLsId)`. | -| `outReady` | Consumer readiness for the queue head. In the reduced top this comes from `ReducedLoadReplayCompletionDrain`; future LIQ/issue work may replace that diagnostic consumer. | - -### Outputs - -| Signal | Description | -|---|---| -| `enqueueReady` | FIFO can accept the candidate this cycle. A simultaneous dequeue opens space. | -| `enqueueAccepted` | Candidate was stored in the queue. | -| `enqueueDropped` | A one-cycle candidate was valid while the queue was full and no dequeue opened space. | -| `outValid` | Queue head is valid. | -| `out` | Queue-head relaunch candidate payload, including the R375 source-trace sideband. | -| `outFire` | Queue head was consumed by `outReady`. | -| `pending` | At least one relaunch candidate is resident. | -| `full` | FIFO is full. | -| `empty` | FIFO is empty. | -| `count` | Resident candidate count. | - -## State - -The module owns a small circular FIFO of `ReducedLoadReplayCandidate` entries, -with registered head pointer, tail pointer, and occupancy count. Stored -payloads force `valid=true` on admission so the output valid handshake remains -the authority for queue residency. Empty payloads explicitly disable every -ROBID-shaped sidecar, including GID/RID and the forwarding snapshot; the -destination, source traces, and scalar return signedness sidebands clear with -the empty payload. - -## Logic Design - -The model load replay sequence is: - -1. `STQ::lookupForLoad` identifies an older not-ready store and records the - blocking store identity in the load request. -2. `LDQInfo::waitStore` marks the load row waiting and returns it to the model - wait state. -3. `LDQInfo::handleSUWakeup` clears wait-store state when a ready store wakeup - matches `(BID, LSID, PC)`. -4. The row becomes eligible for the normal wait/relaunch path again. - -`ReducedLoadWaitReplaySlot` covers steps 1 through 3 for a single reduced-top -diagnostic row. `ReducedLoadReplayRelaunchQueue` covers the next boundary: -the cleared load identity is no longer a transient pulse and can be consumed -by a later owner in FIFO order. - -Admission accepts `enqueueValid && enqueue.valid` when the queue is not full, -or when the current head is also consumed in the same cycle. If the queue is -full and no dequeue occurs, the module reports `enqueueDropped` because the -upstream candidate is a one-cycle pulse and cannot be backpressured by the -current wait-slot owner. - -## Timing - -`outValid` and `out` describe the pre-cycle queue head. If `outReady` and -`enqueueValid` are both asserted while full, the old head is consumed and the -new candidate is written into the freed slot. Occupancy remains full. - -The integrated reduced top currently drives `outReady` from -`ReducedLoadReplayCompletionDrain`, so a queued candidate is consumed only -when the held load completes in W2 with matching PC, address, size, BID, -GID/RID, and LSID. Later LIQ/issue work should replace that diagnostic drain -with a real relaunch admission boundary. - -## Flush/Recovery - -`flush` clears entries, pointers, and count, and suppresses admission, -dequeue, and drop reporting for that cycle. The reduced top drives it from the -same reduced-store flush used by the wait slot. - -## Deferred Owners - -- A real consumer that allocates or selects a `LoadInflightQueue` row. -- Integration of `ReducedLoadReplayLiqAllocPath` with the reduced top. -- Relaunch arbitration with newly issued loads. -- Ready-table or dependent-consumer wakeup. -- Multiple load wait slots feeding a shared queue. -- Precise LSU recovery pruning by load BID/LSID. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayRelaunchQueue -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayCompletionDrain -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadWaitReplaySlot -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -``` - -Reference tests cover FIFO ordering, same-cycle dequeue/enqueue into a full -queue, full-drop diagnostics, flush clearing and admission suppression, and -Chisel elaboration of queue diagnostics. diff --git a/docs/chisel/modules/lsu/ReducedLoadWaitReplaySlot.md b/docs/chisel/modules/lsu/ReducedLoadWaitReplaySlot.md deleted file mode 100644 index 466dc169..00000000 --- a/docs/chisel/modules/lsu/ReducedLoadWaitReplaySlot.md +++ /dev/null @@ -1,220 +0,0 @@ -# ReducedLoadWaitReplaySlot - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadWaitReplaySlot.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedLoadWaitReplaySlotSpec.scala`, - `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayToLiqPathSpec.scala`, - `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `tools/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::waitStore` - - `LDQInfo::handleSUWakeup` - - `tools/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp` - - `SimInstInfo::GenRFReqBus` - - `SimInstInfo::RFRetSetData` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreResidentForward.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ResidentStoreReplayWakeup.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadReplayWakeup.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedLoadReplayRelaunchQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala` -- Contract IDs: `LC-CHISEL-LSU-STQ-FWD-004` - -## Purpose - -`ReducedLoadWaitReplaySlot` is the first reduced-top consumer-side bridge for -resident store-data waits. It captures the E-stage load identity and selected -wait-store key while `ReducedStoreResidentForward` reports a wait hit, keeps -that key registered after the live forwarder stops reporting a wait, and feeds -the resulting store-unit wakeup through the existing `LoadReplayWakeup` owner. - -R672-B retains both the load's full LSID and its youngest-store full-LSID -snapshot in the wait slot and copies them into the relaunch candidate. These -are separate from the selected wait store's full LSID in -`LoadStoreForwardWait`; all three identities survive independently. - -This is still diagnostic integration. The slot proves the replay request shape -can clear a remembered wait-store row by `(BID, LSID, PC)` and now publishes a -one-cycle relaunch candidate carrying the remembered load identity. R274 -extends that candidate to preserve the model `MemReqBus` ROB sidecars -`BID/GID/RID` plus reduced `LSID`, matching the identity carried through the -model LDQ insert/wait path. R275 also records the -`LoadInflightQueue` forwarding snapshot `(youngestStoreId, -youngestStoreLsId, youngestStoreLsIdFull)` as explicit candidate sidecars, rather than leaving it -implicit in the reduced top's current BID/LSID aliases. R307 carries the -derived replay-return signedness bit beside address and size, using the model -opcode class that later feeds `SignExtend`. R311 carries the renamed load -destination sideband from the held execute uop beside the same replay -candidate, matching the model's later ROB `pdsts_` lookup. R375 also captures -the RF-derived `sourceTraceValid/source0/source1` sideband from -`ReducedScalarAluExecute`, preserving original load source operands through -the wait-store clear boundary instead of deriving them from ROB or LIQ -metadata later. In the reduced top after R272, -`ReducedLoadReplayRelaunchQueue` consumes that pulse into a finite pending -queue. The slot itself does not drive a launch port, wake dependent consumers, -or replace the full `LoadInflightQueue` owner. R449 adds a chained reference -proof that carries the same owner handoff through resident forwarding, -wait-slot capture, resident store wakeup, relaunch queue storage, and -replay-LIQ allocation before any live top stimulus can naturally produce that -timing. - -## Interface - -### Inputs - -| Signal | Description | -|---|---| -| `flush` | Clears the registered wait slot. | -| `captureValid` | Captures the current reduced E-stage load as waiting on a resident store. | -| `capturePc` | PC of the waiting load. | -| `captureAddr` | Byte address of the waiting load. | -| `captureSize` | Byte size of the waiting load. | -| `captureReturnSignExtend` | Derived scalar return signedness for future replay-return data extraction. | -| `captureDst` | Renamed destination sideband from the held load uop. | -| `captureSourceTraceValid` | R375 RF-derived source-trace sideband valid from the held load uop. | -| `captureSource0`, `captureSource1` | R375 original source operand traces captured from execute-stage RF-return data. | -| `captureBid` | Load allocation snapshot BID. | -| `captureGid` | Load allocation snapshot GID sidecar. | -| `captureRid` | Load allocation snapshot RID sidecar. | -| `captureLsId` | Load allocation snapshot LSID in `ROBID` form. | -| `captureYoungestStoreId` | Forwarding snapshot BID used by the later LIQ/forwarding handoff. In the current reduced top this aliases `captureBid`. | -| `captureYoungestStoreLsId` | Forwarding snapshot LSID used by the later LIQ/forwarding handoff. In the current reduced top this aliases `captureLsId`. | -| `captureYoungestStoreLsIdFullValid`, `captureYoungestStoreLsIdFull` | Authoritative parameterized snapshot used for same-BID forwarding order. | -| `captureWaitStore` | Selected not-ready store key from `ReducedStoreResidentForward`: STQ index, BID, projected LSID, full-LSID authority/value, and PC. | -| `replayWakeValid` | Store-unit replay wakeup valid from `ResidentStoreReplayWakeup`. | -| `replayWake` | Typed `LoadReplayWakeupRequest` consumed by `LoadReplayWakeup`, including the selected store's full-LSID authority/value. | - -### Outputs - -| Signal | Description | -|---|---| -| `active` | A reduced wait-store slot is currently remembered. | -| `captureAccepted` | A valid wait-store capture was accepted this cycle. | -| `waitStoreClear` | `LoadReplayWakeup` matched the remembered wait-store key and cleared the diagnostic slot. | -| `waitStoreClearMask` | Two-entry mask from the internal `LoadReplayWakeup`; bit 0 is the real slot and bit 1 is tied to an empty row. | -| `storedWaitStore` | Registered wait-store key, including parameterized full LSID. The reduced top feeds this back to `ResidentStoreReplayWakeup` so ready stores can wake a load after the live forwarder no longer reports a wait. | -| `relaunch.valid` | One-cycle candidate pulse when the remembered wait-store key is cleared and no same-cycle capture wins the slot. | -| `relaunch.pc` | PC of the remembered load. | -| `relaunch.addr` | Byte address of the remembered load. | -| `relaunch.size` | Byte size of the remembered load. | -| `relaunch.returnSignExtend` | Captured scalar return signedness sideband. | -| `relaunch.dst` | Captured renamed destination sideband for future LRET/wakeup payload construction. | -| `relaunch.sourceTraceValid` | Captured source-trace validity for future replay W2 commit-row source fill. | -| `relaunch.source0`, `relaunch.source1` | Captured original source operand traces; not ROB allocation placeholders. | -| `relaunch.bid` | BID snapshot captured with the remembered load. | -| `relaunch.gid` | GID snapshot captured with the remembered load. | -| `relaunch.rid` | RID snapshot captured with the remembered load. | -| `relaunch.loadLsId` | Reduced LSID captured with the remembered load. | -| `relaunch.youngestStoreId` | Forwarding snapshot BID captured with the remembered load. | -| `relaunch.youngestStoreLsId` | Forwarding snapshot LSID captured with the remembered load. | -| `relaunch.youngestStoreLsIdFullValid`, `relaunch.youngestStoreLsIdFull` | Authoritative full forwarding snapshot captured with the remembered load. | -| `slotPc` | PC of the remembered load row. | -| `slotAddr` | Address of the remembered load row. | - -## State - -The module owns one registered `LoadInflightRow` image plus an `active` bit. -Internally it presents a two-entry row vector to `LoadReplayWakeup` because -that owner requires a power-of-two LIQ depth greater than one. Entry 0 is the -real reduced wait slot; entry 1 is permanently empty. - -## Logic Design - -The model sequence is: - -1. `STQ::lookupForLoad` finds an older store whose address overlaps the load - but whose data is not ready. -2. `LDQInfo::waitStore` records that blocking store's identity and the load - remains unresolved. -3. Later, `LDQInfo::handleSUWakeup` receives a store-unit wakeup and clears - wait-store state when `(BID, LSID, PC)` matches. - -R269 maps that sequence onto the reduced top: - -1. Capture a synthetic one-row LIQ image when the E-stage load is held by a - resident wait hit. -2. Publish the registered `waitStore` key back to `ResidentStoreReplayWakeup`. - This registration is required because the live forwarder reports a wait - only while the store data is not ready; once the store becomes ready, the - live path switches to ready forwarding. -3. Consume the resulting `LoadReplayWakeupRequest` through the same - `LoadReplayWakeup` module used by `LoadInflightQueue`. -4. Clear the diagnostic slot when the wakeup matches the remembered - wait-store key by `(storeId, storeLsId, storeLsIdFull, pc)`. Full-LSID - comparison is mandatory, and missing full authority is a non-match. -5. Publish a one-cycle relaunch candidate containing the stored load PC, - address, size, derived return signedness, renamed destination, RF-derived - source operand traces, BID, GID, RID, reduced LSID, and forwarding snapshot - `(youngestStoreId, youngestStoreLsIdFull)`, with the reduced LSID retained - as a compatibility sidecar. This is the future LIQ/issue - handoff boundary; it does not itself relaunch the load. -6. In the reduced top, `ReducedLoadReplayRelaunchQueue` stores that one-cycle - pulse as a stable pending diagnostic until a later LIQ/issue consumer - exists. - -## Timing - -Capture is registered. A newly captured wait key becomes visible to -`ResidentStoreReplayWakeup` on the following cycle. Store wakeup consumption is -combinational through `LoadReplayWakeup` and clears the slot on the next clock -edge. The relaunch candidate is valid in that clear cycle and carries the -pre-clear registered load identity. - -If capture and clear are both asserted in one cycle, capture wins and the -candidate is suppressed. In the integrated reduced top, the matching wakeup -appears when the store is ready and the live wait-hit has dropped, so same-cycle -capture/clear is not expected for the same load. - -## Flush/Recovery - -`flush` clears the slot and suppresses capture/wakeup consumption. The reduced -top drives it from the reduced-store flush condition: backend pipe flush, -run start, run restart, or disabling the optional reduced-STQ path. - -## Deferred Owners - -- Real `LoadInflightQueue` allocation for reduced execute-stage loads. -- Connecting the queued relaunch candidate to a real LIQ or issue/ready-table - launch boundary. -- Consumer wakeup after wait-store clear. -- Multiple waiting loads and wakeup arbitration. -- Cross-line resident replay publication. -- MDB conflict publication and precise recovery pruning. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadWaitReplaySlot -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayToLiqPath -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayChiselPath -bash tools/chisel/run_chisel_tests.sh --only ReducedLoadReplayRelaunchQueue -bash tools/chisel/run_chisel_tests.sh --only ResidentStoreReplayWakeup -bash tools/chisel/run_chisel_tests.sh --only LoadReplayWakeup -bash tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -git diff --check -``` - -Reference tests cover capture/clear behavior, mismatched wake suppression, -capture overwrite, relaunch-candidate identity, flush clearing, and Chisel -elaboration through `LoadReplayWakeup`. R449 adds the multi-owner reference -chain proving a not-ready resident store blocks a younger load, the stored wait -key does not wake until the store row is ready, the clear produces a relaunch -candidate, the queue preserves it, and replay-LIQ allocation preserves -`youngestStoreLsId`. R451 adds a test-only Chisel probe that wires the real -`STQEntryBank`, `ReducedStoreResidentForward`, this slot, -`ResidentStoreReplayWakeup`, `ReducedLoadReplayRelaunchQueue`, and -`ReducedLoadReplayLiqAllocPath` modules together. The companion reference case -locks the R450 timing conclusion: a ready store at load lookup forwards -normally, while an address-ready/data-late resident store is the required -window for wait-store capture and later relaunch. R452 promotes that probe into -a main-source generated-RTL fixture and Verilator harness. The executable proof -drives a ready-store negative case and a split STA/STD case through the real -module chain, then records nonzero wait capture, wake clear, relaunch queue -fire, LIQ allocation, and `youngest_store_lsid=1` in a JSON report. diff --git a/docs/chisel/modules/lsu/ReducedStoreCommitFreeOwner.md b/docs/chisel/modules/lsu/ReducedStoreCommitFreeOwner.md deleted file mode 100644 index 7a4e2174..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreCommitFreeOwner.md +++ /dev/null @@ -1,235 +0,0 @@ -# ReducedStoreCommitFreeOwner - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreCommitFreeOwner.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreCommitFreeOwnerSpec.scala` -- Generated probe: `rtl/LinxCore/tools/chisel/run_chisel_store_non_flush_gate_probe.sh` -- Integrated users: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/backend/DecodeRenameROBPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/StoreDispatchSTQPath.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/store_unit/store_unit.cpp` - - `StoreUnit::GetCommitID` - - `StoreUnit::checkCommit` - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::retire` - - `STQ::commit` - - `STQ::free` - -## Purpose - -`ReducedStoreCommitFreeOwner` is the reduced-top lifecycle owner that connects -ROB commit rows to the optional queue-backed STQ path. It observes committed -store rows from `DecodeRenameROBPath`, matches them to resident STQ rows by the -model `CommitTrace.identity` tuple plus STID, and marks the matched STQ row -committed only after the row's full block BID lies inside BROB's strong -non-flush prefix or the row is an older scalar store in the exact oldest ROB -block. It buffers the full block BID, STID, LSID, and committed-store identity -when either authorization or the matching STQ row is not ready. Independently, -it scans ready resident scalar rows against the ROB commit-head BID/LSID so -split-store merge timing cannot lose an already established safe frontier. -It can also run in a legacy direct-free mode that issues a later single-index -committed-row free, but `LinxCoreFrontendFetchRfAluTraceTop` disables that mode -after R241 and frees rows from the SCB accepted-`last` mask instead. - -This module is intentionally narrower than the full LSU commit path. It lets -`LinxCoreFrontendFetchRfAluTraceTop(useReducedStoreDispatchStq=true)` prove -store-dispatch residency and ROB-to-STQ mark ownership, but it does not own -cache update, MDB conflict detection, or full load-store forwarding. R258 adds -a separate reduced store-memory overlay for committed-byte visibility; this -owner still only marks and frees STQ rows. - -## Sizing Contract - -`entries` sizes physical pending slots, STQ row vectors, masks, and mark/free -indices. `robEntries` sizes BID/GID/RID identity, commit-memory-order bundles, -and retained identity registers. The compatibility default makes them equal; -the integrated top passes both explicitly and the focused suite proves -16 physical STQ rows with an 8-entry ROB domain. - -## Interface - -Inputs: - -- `enable`: activates the reduced owner. When low, the owner clears pending - state and drives no mark/free commands. -- `directFreeEnable`: enables the legacy direct-free queue. The reduced top - drives this low so accepted marks feed `STQCommitDrain` and `SCBRowBank` - rather than this owner. -- `flushValid`: clears pending mark/free state. The reduced top asserts this - on backend flush, start, restart, and while the optional STQ path is disabled. -- `activeStid`: STID used to match committed rows against resident STQ rows. -- `nonFlushValid`, `nonFlushHeadBid`, `nonFlushPrefixCount`: selected STID's - exact strong-safe BROB prefix. Head plus count, not BID magnitude, proves - membership. -- `oldestRobValid`, `oldestRobBid`, `oldestRobLsId`, `oldestRobStid`: exact - commit-head snapshot used by the scalar resident early-safe predicate. -- `commitMemoryOrder`: ROB commit-window LSID snapshots used to latch - early-safe authority for retained store identities. -- `commit`, `commitValidMask`: monitored ROB commit window from - `DecodeRenameROBPath`. -- `stqRows`: current STQ row image forwarded from `StoreDispatchSTQPath`. -- `markCommitAccepted`, `markCommitIgnored`: result of the mark command after - `STQEntryBank` checks row state. -- `commitFreeAccepted`, `commitFreeIgnored`, - `commitFreeAcceptedMask`, `commitFreeIgnoredMask`: result feedback for the - legacy single-row committed free command. With `directFreeEnable=0`, these - inputs are diagnostic only. - -Outputs: - -- `markCommitValid`, `markCommitIndex`: one pending STQ row to move from - `Wait` to `Commit`. -- `commitFreeValid`, `commitFreeIndex`: one previously marked row to free when - `directFreeEnable=1`; tied inactive by the reduced top after R241. -- `commitStoreSeen`, `commitStoreMatched`, `commitStoreUnmatched`: current - commit-window diagnostics. -- `commitStoreBlockedByNonFlush`: a current committed store is outside the - selected strong prefix or lacks a valid full block BID. -- `matchMask`: STQ rows matched by current committed store rows. -- `earlySafeMatchMask`, `residentEarlySafeMask`: rows authorized by a retained - commit LSID frontier or by the current exact ROB-head BID/LSID snapshot. -- `pendingCommitIdentityMask`: buffered committed-store identities that are - waiting for a future resident STQ row with the same model identity. -- `pendingCommitEarlySafeMask`: retained identities whose later same-block - commit LSID proof has been latched across delayed STA/STD merge. -- `pendingMarkMask`, `pendingFreeMask`, - `pendingMarkCount`, `pendingFreeCount`: registered owner state. -- `markBlocked`, `freeBlocked`: command was issued but the STQ bank did not - accept it. -- `idle`: no pending mark or free work remains. - -## Logic Design - -The owner does not maintain a parallel insertion map. `StoreDispatchToSTQ` -already stamps each STQ row with the renamed uop's model `bid/gid/rid`, -`lsId`, and STID sidecars. The ROB commit row exposes the same model identity -through `CommitTraceRow.identity`. A committed store row matches an STQ row -when: - -1. the commit slot is valid, -2. the commit row is a store memory row, -3. the commit row has a model `CommitTrace.identity` value, -4. the STQ row is valid, `Wait`, `ST_ALL`, address-ready, and data-ready, -5. the STQ row model `bid/gid/rid` equals the commit identity, -6. the STQ row STID equals `activeStid`, -7. either the commit row lies in the strong non-flush prefix or its scalar LSID - is strictly older than a later committed LSID in the exact oldest block. - -The model `GetOldestLSID` fallback does not wait for a committed-store identity. -For every ready resident scalar row, the owner also requires exact STID and -wrap-qualified BID equality with the ROB head and strict wrap-qualified -`row.lsId < head.lsId`. Tile rows are excluded. Recovery clears retained -identity/frontier state, while the live ROB head is recomputed from surviving -state. - -Matched rows set bits in `pendingMarkMask`. If a committed store identity does -not match a currently markable STQ row, the owner records that identity in a -small pending-commit buffer together with STID and full block BID. Later cycles -compare resident STQ rows against both the current commit window and buffered -identities, recheck the current strong prefix, then clear the buffered identity -once a matching row becomes markable. This covers both STQ-residency races and -frontier advance after ROB commit observation. - -The owner presents the lowest pending mark bit as a single `markCommitValid` -command. When `STQEntryBank` accepts that command, the bit leaves -`pendingMarkMask`. If `directFreeEnable` is asserted, the bit also enters -`pendingFreeMask`; on a later cycle the owner presents the lowest pending free -bit as a single `commitFreeValid` command and accepted free clears the bit. If -`directFreeEnable` is deasserted, `pendingFreeMask` is held empty and another -owner must free the committed row. - -The register boundary matters. Commit-window observation only sets pending mark -bits for a later cycle. In direct-free mode, accepted marks create pending free -bits for a later cycle. In the reduced top's R241 mode, accepted marks enqueue -`STQCommitDrain` and SCB accepted `last` fragments become the free source. - -## Model Alignment - -The C++ model separates store lifecycle into two phases: - -- `STQ::retire` marks ready stores as `STQ_COMMIT` when block/ROB order makes - them non-flushable, then pushes their indices into `storeCommitQ`. -- `STQ::commit` drains `storeCommitQ` in order, sends one or two memory - requests to SCB, and calls `free(i)` only after the downstream request is - accepted. - -This reduced owner preserves the ROB-to-STQ `Wait -> Commit` transition. The -R240 direct-free mode preserved `Commit -> Free` with a top-only debug -assumption. R241 disables that mode in the reduced top and wires the accepted -mark into `STQCommitDrain`, with `SCBRowBank.commitFreeMask` as the only STQ -free source. Program-order memory effects, external memory mutation, and -load/store interaction are still outside this owner. - -R652 connects the model's non-flush mechanism to this transition without -importing ARM architectural behavior. The generated owner probe proves an -unsafe committed store remains retained, a later prefix advance releases it, -and accepted recovery clears the retained and pending state. The generated -BROB probe separately proves per-STID blocking, exception exclusion, and a -strong prefix spanning full-BID rollover. - -R668 completes scalar STQ liveness from model `STQ::isStqCmtable`. It retains -later commit-LSID evidence across split-row availability and, critically, -publishes the ROB commit-head `(STID, BID, LSID)` so ready resident scalar rows -older than that frontier can promote directly. The generated probe covers -late row appearance, tile rejection, recovery clear, and direct resident -authorization. A 2,048-row CoreMark capture produces 1,914 reduced rows and -compares 1,467 normalized architectural commits with zero mismatches and zero -CBSTOP after the former 969-row full-STQ stop. - -R253 corrects the reduced owner matching contract: commit rows must match STQ -rows through model `bid/gid/rid`, not the physical ROB sideband, and unmatched -committed-store identities must be retained until the split-store path has -inserted a ready `ST_ALL` row. The focused owner gate passes, the 240-row -live-QEMU reduced-store wrapper compares 162 rows with zero mismatches, and a -direct replay over the 726-row R252 expected stream compares 495 architectural -rows with zero mismatches. - -R254-R257 leave the owner logic unchanged and scale the same reduced-store -proof. The live wrapper passes at 1024 raw CoreMark/QEMU rows with 665 compared -rows. Reusing the R254 generated testbench against fresh loop-reentry-enabled -captures then passes at 2048, 4096, and 8192 raw rows, comparing 1467, 3369, -and 7172 rows respectively with zero mismatches. - -R258 keeps this owner unchanged. It consumes the downstream SCB accepted -fragment stream in `ReducedStoreMemoryOverlay`, so the reduced top can prove -later load visibility without harness-side sparse memory mutation. R259 also -feeds ROB committed store rows to the overlay before SCB acceptance, matching -the model `storeCommitQ` visibility used by `STQ::lookupForLoad`. The -commit/free owner remains responsible only for ROB-to-STQ mark identity and -free-source integration; SCB accepted `last` fragments remain the only STQ -free source in the reduced top. - -## Deferred Owners - -- Replace the reduced store-memory overlay with full load lookup, - store-forwarding, wait/replay, and cache interaction. -- Add MDB conflict publication and precise recovery cleanup for committed STQ - rows if the full exception model requires it. - -## Verification - -Focused gate: - -```bash -sbt "testOnly linxcore.lsu.ReducedStoreCommitFreeOwnerSpec" -bash tools/chisel/run_chisel_store_non_flush_gate_probe.sh -``` - -Integrated gate used for R241: - -```bash -sbt "testOnly linxcore.lsu.STQCommitQueueSpec linxcore.lsu.STQCommitDrainSpec linxcore.lsu.STQSCBCommitPathSpec linxcore.lsu.ReducedStoreCommitFreeOwnerSpec linxcore.lsu.ReducedStoreExecResultBridgeSpec linxcore.backend.DecodeRenameROBPathSpec linxcore.top.LinxCoreFrontendFetchRfAluTraceTopSpec" -``` - -The tests cover commit-identity-to-STQ matching, pending commit identity -buffering, pending mark/free progression, direct-free disable behavior, -unmatched store diagnostics, non-ready row rejection, drain flush clearing, and -top/backend elaboration of the SCB-backed free diagnostics. - -R670 removes LSID compression from scalar early-safe authorization and pending -commit retention. Commit frontiers, oldest-ROB watermarks, resident STQ rows, -and buffered store identities compare in the full `lsidWidth` domain through -`LSIDOrder`; BID/GID/RID matching remains ROB-sized. diff --git a/docs/chisel/modules/lsu/ReducedStoreExecResultBridge.md b/docs/chisel/modules/lsu/ReducedStoreExecResultBridge.md deleted file mode 100644 index ff4a70ad..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreExecResultBridge.md +++ /dev/null @@ -1,155 +0,0 @@ -# ReducedStoreExecResultBridge - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreExecResultBridge.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreExecResultBridgeSpec.scala` -- Related Chisel: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/StoreDispatchSTQPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/StoreDispatchToSTQ.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/rename/StoreSplitPayload.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/store_unit/store_unit.cpp` - - `StoreUnit::store` - - `StoreUnit::insertStq` - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQueueEntryInfo::init` - - `STQ::mergeStore` - - `STQ::retire` - - `STQ::commit` - -## Purpose - -`ReducedStoreExecResultBridge` is a reduced-top adapter between -`ReducedScalarAluExecute` store commit sidebands and the queue-head execution -result contract required by `StoreDispatchSTQPath`. - -The existing reduced ALU computes store address, data, and size as part of the -QEMU-shaped commit trace row. `StoreDispatchSTQPath` deliberately does not -consume commit trace rows directly; it waits for explicit STA/STD execution -results matching the visible store-dispatch queue heads. This bridge buffers -reduced ALU store completions and presents a `StoreDispatchExecResult` only -when the current STA or STD queue head has the same `(bid,rid,stid)` identity. - -This module does not mark stores committed, free STQ rows, issue memory -requests, mutate memory, publish MDB conflicts, or implement load forwarding. -`ReducedStoreCommitFreeOwner` owns the temporary reduced-top ROB-to-STQ mark -bridge; R241 routes committed-row frees through `STQCommitDrain` and -`SCBRowBank` accepted `last` fragments. - -## Interface - -Inputs: - -- `flushValid`: clears all buffered reduced store results. -- `completeValid`, `completeRow`, `completeBid`, `completeRid`, - `completeStid`: reduced ALU completion sideband. A result is captured only - when `completeRow.mem.valid && completeRow.mem.isStore`. -- `staQueueValid`, `staQueue`: visible STA-side queue head from - `StoreDispatchSTQPath`. -- `stdQueueValid`, `stdQueue`: visible STD-side queue head from - `StoreDispatchSTQPath`. -- `staConsumed`, `stdConsumed`: selected/dequeue pulses from - `StoreDispatchSTQPath`. - -Outputs: - -- `staExec`, `stdExec`: explicit execution results for matching queue heads. -- `completeStoreValid`: a store completion is being considered for capture. -- `captureFire`: the store completion entered the bridge buffer. -- `captureBlocked`: the store completion could not enter because the buffer - was full. -- `captureDuplicate`: a live buffered result already has the same identity. -- `staMatch`, `stdMatch`: the current queue head has a buffered result. -- `validMask`, `bufferCount`: bridge occupancy diagnostics. - -## Logic Design - -The bridge stores only the data needed to satisfy `StoreDispatchExecResult`: -ROB block ID, ROB row ID, STID, address, write data, and size. PE ID, TID, and -STID on the output are taken from the matching queue payload so the STQ request -inherits the same dispatch-side thread identity as the payload. - -A queue head matches a buffered result when: - -1. the queue head is valid, -2. the buffered result is valid, -3. `bid` and `rid` match with full `ROBID` wrap/value comparison, -4. the buffered `stid` matches the queue payload's thread ID. - -STA and STD matches are computed independently. If both halves of a split store -are present, `StoreDispatchToSTQ` still owns the one-request-per-cycle choice -and gives STA priority. The bridge therefore keeps a split-store result after -STA consumption and clears it after STD consumption. For an unsplit store, STA -consumption clears the result immediately because `StoreSplitStoreType.All` -has no STD half. - -Capture is first-free-slot. Duplicate completions are reported and not -recaptured. Overflow is reported as `captureBlocked`; the completion is not -silently converted into a queue-head result. - -## Model Alignment - -The C++ model separates store dispatch and STQ mutation: - -- `StoreUnit::store` drains STA work and STD work from execution queues. -- `STQ::mergeStore` allows a split half to merge with an existing row by store - identity. -- `STQueueEntryInfo::init` marks address/data readiness according to - `ST_ADDR`, `ST_DATA`, or `ST_ALL`. -- `STQ::retire` and `STQ::commit` are later lifecycle steps. - -The bridge preserves that separation for the reduced top. It only supplies the -execution-result side of the dispatch queue contract; it does not collapse -retire/commit/free into ALU completion. - -R450 adds an opt-in split-STD delay to this bridge for replay-LIQ stimulus -experiments. When `stdDelayCycles > 0`, consuming a split STA half arms a -per-buffered-result counter and suppresses the matching `stdExec.valid` while -the counter is nonzero. The default value is zero, so ordinary reduced-store -top behavior remains unchanged. The replay-LIQ emit wrapper can set -`LINXCORE_REPLAY_LIQ_STD_DELAY_CYCLES` to produce emitted RTL with the delay -counter present. This hook is stimulus shaping only; it does not by itself -prove load replay. - -## Deferred Owners - -- External store memory mutation after the reduced top accepts stores into - `SCBRowBank`. -- MDB integration and memory-side conflict publication. -- Load-store forwarding and replay wakeup from resident STQ rows. -- Stack-valid and non-scalar execution metadata beyond the current reduced - scalar sideband. - -## Verification - -Focused gate: - -```bash -sbt "testOnly linxcore.lsu.ReducedStoreExecResultBridgeSpec" -``` - -Integrated gate used for R239: - -```bash -sbt "testOnly linxcore.lsu.ReducedStoreExecResultBridgeSpec linxcore.top.LinxCoreFrontendFetchRfAluTraceTopSpec" -``` - -The tests cover store capture, queue-head mismatch, split-store retention -after STA consumption, unsplit clearing after STA consumption, overflow -reporting, bridge elaboration, and top-level diagnostic elaboration. R450 also -covers delayed split-STD matching and elaborates the opt-in delayed branch. - -R450 live probe: - -```bash -LINXCORE_REPLAY_LIQ_STD_DELAY_CYCLES=4 bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh --build-dir generated/r450-std-delay-ldi-sdi-ldi-replay-probe --elf /tmp/linx_r449_ldi_sdi_probe.elf --expected-rows 0 --capture-rows 6 --allow-block-markers --reduced-store-replay-liq --disable-store-memory-mutation --max-seconds 8 -``` - -That probe emits a delayed replay-LIQ top, passes 4 compared rows with zero -mismatches, and still records zero resident-store wake, wait-replay, queue, -LIQ allocation/launch, source-return, and row-mutation counters. The result -narrows the remaining live-stimulus problem: delaying STD after STA is -insufficient unless the younger load is driven while the STA-only row is -resident. diff --git a/docs/chisel/modules/lsu/ReducedStoreMemoryOverlay.md b/docs/chisel/modules/lsu/ReducedStoreMemoryOverlay.md deleted file mode 100644 index b25b02e4..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreMemoryOverlay.md +++ /dev/null @@ -1,228 +0,0 @@ -# ReducedStoreMemoryOverlay - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreMemoryOverlay.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreMemoryOverlaySpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- Harness switch: - - `rtl/LinxCore/tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp` - - `rtl/LinxCore/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` - - `rtl/LinxCore/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::commit` - - `STQ::lookupForLoad` - - `STQ::free` - - `tools/LinxCoreModel/model/lsu/store_unit/store_unit.cpp` - - `StoreUnit::checkCommit` - - `StoreUnit::GetCommitID` - -## Purpose - -`ReducedStoreMemoryOverlay` is the reduced-top memory visibility bridge for -`LinxCoreFrontendFetchRfAluTraceTop(useReducedStoreDispatchStq=true)`. It -records committed store fragments from ROB commit rows and from the reduced -`SCBRowBank`, then overlays their bytes onto later 64-bit scalar load lookup -data from the sparse ELF base image. The ROB commit-row feed mirrors the -model's `storeCommitQ` load visibility before SCB acceptance; the SCB accepted -feed keeps the bridge aligned with the downstream memory-side drain. Together -they let the reduced-store CoreMark gate prove store-visible loads without -relying on the C++ harness to mutate its sparse memory image after matched -store rows. - -The module is intentionally a reduced trace-top bridge, not a replacement for -the full LSU memory system. It does not own cache state, TSO/fence completion, -load replay, MDB conflict publication, or the complete model `lookupForLoad` -wait/conflict policy. It makes committed store bytes visible to the reduced -scalar load lookup path; R265 then applies ready resident STQ forwarding after -this committed overlay. - -## Interface - -Inputs: - -- `flush`: clears all overlay lines. The top asserts this on test/run start, - restart, or when the optional reduced-store STQ path is disabled. It is not - tied to ordinary backend redirects because accepted SCB fragments are already - committed memory-side state. -- `storeReqs`: `STQCommitDrainRequest` lanes produced by the reduced top. Each - lane carries valid, full BID/LSID identity, address, size, data, and `last` - sidecars. The parent must - present same-cycle accepted lanes in old-to-young program order because later - lanes overwrite overlapping bytes in the overlay line image. -- `storeAcceptedMask`: one bit per request lane. Commit-row bypass lanes are - accepted when the monitored commit row is a valid store; SCB lanes are - accepted from `SCBRowBank.acceptedMask`. Only valid requests whose lane bit - is set update the overlay. -- `loadValid`, `loadAddr`: reduced scalar load lookup request from - `ReducedScalarAluExecute`. -- `baseLoadData`: immutable 64-bit little-endian data read by the harness from - the sparse ELF image. - -Outputs: - -- `loadData`: `baseLoadData` with any matching overlay bytes substituted. -- `loadForwardMask`: one bit per returned byte indicating overlay hit. -- `lines`: diagnostic image of each overlay line. -- `validMask`, `lineCount`: diagnostic occupancy. -- `storeDroppedMask`: one bit per accepted request that could not find a - matching or free overlay line. - -## Logic Design - -The overlay stores fixed 64-byte line entries. An accepted store request first -matches an existing valid line by aligned 64-byte address. If no line matches, -the request allocates the lowest free line. If neither a matching line nor a -free line exists, `storeDroppedMask` pulses for that request and the overlay -state is unchanged. - -For an accepted update, the module builds a byte mask from the request address -low bits and request size, then merges the little-endian request data into the -target line. Multiple accepted lanes are applied in lane order through a -combinational ingress chain before the line registers update. The parent must -therefore route older store fragments first and younger fragments later. In the -current reduced top, `STQCommitDrain`/`SCBRowBank` accepted lanes are older -resident `storeCommitQ` work selected from the registered commit queue, so they -are applied before current ROB commit-row bypass lanes. - -For a load lookup, each of the eight returned bytes independently checks the -registered overlay lines by the byte's 64-byte line address and byte offset. -This per-byte selection lets a 64-bit load span two overlay lines. A byte with -no overlay hit falls back to the harness-supplied sparse-image `baseLoadData`. - -## Model Alignment - -The C++ `STQ::retire` path marks ready stores as committed and pushes their -indices into `storeCommitQ`. `STQ::commit` then drains that queue toward SCB in -program order and frees each STQ row only after the downstream request is -accepted. A wide or cross-cacheline store may produce more than one downstream -memory request. The reduced top still wires accepted SCB `last` fragments as -the STQ free source through `SCBRowBank`; this overlay also consumes those -fragments as an idempotent downstream memory-side data source. - -The model `STQ::lookupForLoad` can see committed store state before SCB accepts -the drain request: it checks resident older/equal stores and the `storeCommitQ` -when assembling load bytes. R259 therefore feeds ROB committed store rows into -the overlay without waiting for SCB acceptance. R262 preserves that visibility -while ordering same-cycle overlay updates old-to-young: current SCB accepted -fragments from the registered commit queue are older than current ROB commit -rows and must not overwrite a younger commit-row byte. `ReducedStoreMemoryOverlay` -implements only that committed-byte visibility subset. It does not model load -wait/replay, younger-store conflicts, MDB recovery publication, or cache -coherence. - -R670 retains the full commit-row LSID on both direct-bypass fragments and -publishes the per-commit-lane bypass identity at the reduced-top diagnostic -boundary. The overlay's physical byte merge remains address-based; LSID is -request metadata for ordering evidence, not a cache-line lookup key. - -## Deferred Owners - -- Replace the overlay plus ready-only resident forwarding with the full - load/store forwarding and replay owner. -- Publish MDB conflicts and recovery cleanup for precise exceptions. -- Connect real cache/SCB memory state instead of a trace-top sparse-image base. -- Add capacity or eviction policy if a longer reduced-store proof exceeds the - fixed overlay line budget. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreMemoryOverlay -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreResidentForward -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -``` - -R258 generated-RTL evidence: - -```bash -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --build-dir generated/r258-store-memory-overlay-1024-qemu-elf-xcheck \ - --elf tests/benchmarks/build/coremark_real.elf \ - --expected-rows 0 --capture-rows 1024 \ - --allow-block-markers --reduced-store-dispatch-stq \ - --disable-store-memory-mutation \ - --max-seconds 8 \ - -- -nographic -monitor none -machine virt -m 1280M \ - -kernel tests/benchmarks/build/coremark_real.elf -``` - -The live wrapper captured and built the reduced top. The generated binary was -then rerun directly with `--disable-store-memory-mutation`, and the neutral -QEMU/DUT comparator passed at -`generated/r258-store-memory-overlay-1024-qemu-elf-xcheck/report-no-harness-store/crosscheck_manifest.json` -with 665 compared rows and zero mismatches. - -R259 2048-row no-harness-mutation evidence: - -```bash -FETCH_REDUCED_STORE_DISPATCH_STQ=1 \ -FETCH_DISABLE_STORE_MEMORY_MUTATION=1 \ -FETCH_EXPECTED_ROWS=generated/r259-reduced-store-overlay-commit-bypass-2048-qemu-elf-xcheck/qemu.expected.jsonl \ -FETCH_ELF=tests/benchmarks/build/coremark_real.elf \ -BUILD_DIR=generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck \ - bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh -``` - -The first 2048-row no-mutation probe with SCB-only overlay data failed at a -load from a committed store that had not yet reached SCB acceptance. The R259 -commit-row bypass feed passes at -`generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck/report/crosscheck_manifest.json` -with 1467 compared rows and zero mismatches. - -R260 scale evidence reuses the R259 generated binary against the R256 4096-row -loop-reentry expected stream with `--disable-store-memory-mutation`, then runs -the common comparator: - -```bash -generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck/obj_dir/linxcore_frontend_fetch_rf_alu_trace_top_tb \ - --dut-trace generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/traces/dut.no-harness-store.jsonl \ - --qemu-trace generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/traces/qemu.no-harness-store.jsonl \ - --expected-rows generated/r256-reduced-store-scale-4096-reuse-r254-bin-qemu-elf-xcheck/qemu.expected.loop-reentry.jsonl \ - --memory-hex generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck/elf.fetch.mem \ - --disable-store-memory-mutation -bash tools/chisel/run_chisel_qemu_crosscheck.sh \ - --qemu-trace generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/traces/qemu.no-harness-store.jsonl \ - --dut-trace generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/traces/dut.no-harness-store.jsonl \ - --report-dir generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/report \ - --max-commits 3370 --mode failfast -``` - -The comparator passes at -`generated/r260-reduced-store-overlay-commit-row-4096-reuse-r259-bin-xcheck/report/crosscheck_manifest.json` -with 3369 compared rows and zero mismatches. - -R261 repeats the same no-harness-mutation direct replay pattern at the existing -8192-row expected-stream depth: - -```bash -generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck/obj_dir/linxcore_frontend_fetch_rf_alu_trace_top_tb \ - --dut-trace generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/traces/dut.no-harness-store.jsonl \ - --qemu-trace generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/traces/qemu.no-harness-store.jsonl \ - --expected-rows generated/r257-reduced-store-scale-8192-reuse-r254-bin-qemu-elf-xcheck/qemu.expected.loop-reentry.jsonl \ - --memory-hex generated/r259-reduced-store-overlay-commit-row-2048-trace-xcheck/elf.fetch.mem \ - --disable-store-memory-mutation -bash tools/chisel/run_chisel_qemu_crosscheck.sh \ - --qemu-trace generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/traces/qemu.no-harness-store.jsonl \ - --dut-trace generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/traces/dut.no-harness-store.jsonl \ - --report-dir generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/report \ - --max-commits 7173 --mode failfast -``` - -The comparator passes at -`generated/r261-reduced-store-overlay-commit-row-8192-reuse-r259-bin-xcheck/report/crosscheck_manifest.json` -with 7172 compared rows and zero mismatches. - -R263 scale evidence reruns the reduced-store live QEMU wrapper with -`--disable-store-memory-mutation`, `--reduced-store-dispatch-stq`, and a fresh -16384-row CoreMark capture after the R262 old-to-young lane ordering change. -The run reduces 16250 expected rows, normalizes 14780 QEMU/DUT rows, compares -14779 rows, and passes with zero mismatches in -`generated/r263-reduced-store-overlay-old-to-young-16384-qemu-elf-xcheck/report/crosscheck_manifest.json`. - -R670 carries the full parameterized LSID on every accepted store request at -this final reduced committed-memory boundary. Overlay byte merge order remains -the parent commit/drain lane order; the overlay does not reinterpret LSID age. diff --git a/docs/chisel/modules/lsu/ReducedStoreResidentForward.md b/docs/chisel/modules/lsu/ReducedStoreResidentForward.md deleted file mode 100644 index 3d9d9186..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreResidentForward.md +++ /dev/null @@ -1,155 +0,0 @@ -# ReducedStoreResidentForward - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreResidentForward.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreResidentForwardSpec.scala` -- Integrated user: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `tools/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `STQ::retire` - - `STQ::commit` - - `tools/LinxCoreModel/model/lsu/store_unit/stq.h` - - `tools/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::handleSTQReceive` - - `LDQInfo::waitStore` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/LoadStoreForwarding.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ResidentStoreForwardStoreSnapshot.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreMemoryOverlay.scala` -- Contract IDs: `LC-CHISEL-LSU-STQ-FWD-002` - -## Purpose - -`ReducedStoreResidentForward` is the reduced-top adapter that lets ready -resident STQ rows feed scalar load data before the store commits. It uses -`ResidentStoreForwardStoreSnapshot` to map `STQEntryBankRow` state into the -generic `LoadStoreForwarding` selector, constructs a synthetic 64-byte -cacheline from the current 64-bit load window, and extracts the returned 64-bit -load data after ready store bytes are overlaid. - -This is still a reduced trace-top bridge. The module preserves the incoming -base load data when an older store is not data-ready and reports the wait hit -through diagnostics. R266 wires that diagnostic to an execute-stage hold in -`LinxCoreFrontendFetchRfAluTraceTop`, but this module still does not mutate -LIQ/LDQ state or consume store-unit wakeups. A later replay owner must consume -the wait-store identity before this can replace the full model load pipeline. - -## Sizing Contract - -`entries` sizes the resident STQ vector, eligible mask, and wait-store index; -`robEntries` sizes load/store BID and current transitional LSID identity -fields. `lsidWidth` independently sizes the authoritative full LSID carried by -resident rows and the selected wait-store result. Forwarding selection never -derives either identity width from the number of resident rows. The focused -suite includes 16-STQ/8-ROB and 40-bit full-LSID contracts. - -## Interface - -### Load Query - -| Signal | Description | -|---|---| -| `enable` | Enables the reduced resident-forward path. Disabled mode passes through `baseLoadData`. | -| `loadValid` | Execute-stage scalar load lookup is active. | -| `loadAddr` | Byte address of the 64-bit reduced load window. | -| `loadSize` | Load size in bytes. The R265 integration uses 1-byte `LBUI` and 8-byte scalar load forms. | -| `loadBid` | Load BID used as the youngest visible store snapshot. | -| `loadLsId` | Reduced load-LSID projection retained for compatibility diagnostics. | -| `loadLsIdFullValid` | The load snapshot carries authoritative full-LSID order. | -| `loadLsIdFull` | Parameterized full load snapshot LSID used for same-BID forwarding order. | -| `baseLoadData` | 64-bit load data after the committed-store memory overlay. | -| `rows` | Resident STQ row image from `StoreDispatchSTQPath`. | - -### Outputs - -| Signal | Description | -|---|---| -| `loadData` | Final 64-bit load data. Ready resident store bytes are included only when no wait byte is selected. | -| `loadForwardMask` | One bit per returned byte forwarded from ready resident STQ rows. | -| `waitMask` | One bit per returned byte whose nearest older resident store is not data-ready. | -| `eligibleStoreMask` | STQ rows accepted by the resident-forward candidate filter. | -| `waitStore` | Selected not-ready resident store identity from `LoadStoreForwarding`: valid bit, STQ index, BID, projected LSID, full-LSID authority/value, and PC. Same-BID selection uses the full identity. | -| `fullLsIdMissingMask` | Relevant same-BID rows excluded because full-LSID authority is absent. | -| `fullLsIdAmbiguousMask` | Relevant same-BID rows excluded by exactly half-range serial ambiguity. | -| `readyForward` | At least one byte was forwarded and no wait byte blocked the load. | -| `waitBlocked` | A nearest older resident store is not data-ready for at least one requested byte. R266 top integration uses this to hold execute. | -| `loadCrossesLine` | Load crosses a 64-byte line and is left on the base overlay path in this ready-only packet. | - -## State - -The module is combinational. It owns no STQ, LDQ, SCB, cache, or replay state. -`LinxCoreFrontendFetchRfAluTraceTop` wires it after `ReducedStoreMemoryOverlay` -and before `ReducedScalarAluExecute.loadLookupData`. - -## Logic Design - -The model `STQ::lookupForLoad` first scans working resident STQ rows whose -address is ready, whose byte range overlaps the load, and whose `(bid, lsID)` -is older than or equal to the load's `(bid, lsID)`. Ready stores provide bytes. -Not-ready stores set wait bits. The nearest older store wins per byte. - -The Chisel adapter preserves that selector rule through `LoadStoreForwarding` -with reduced-top limits: - -1. Retain the execute load's full LSID beside its reduced compatibility - projection. Same-BID ordering uses only the full value. -2. Suppress cross-line load queries and cross-line resident store candidates. - The committed-store overlay still handles cross-line committed fragments. -3. Build a synthetic 64-byte `cacheData` line by placing the eight - `baseLoadData` bytes at the load address offset. -4. Use `ResidentStoreForwardStoreSnapshot` to convert resident STQ rows into - line-addressed `LoadStoreForwardStore` candidates with model-style BID, - LSID, PC, byte-mask, and positioned-line-data sidecars. -5. Run `LoadStoreForwarding`, then extract the load-window bytes from the - merged 64-byte line. -6. If `waitMask` is nonzero, preserve `baseLoadData` and report - `waitBlocked`. The R266 top consumes that diagnostic as execute - backpressure; replay row mutation remains outside this adapter. - -## Timing - -R265 wires the adapter combinationally after `ReducedStoreMemoryOverlay`. -The final reduced load-data order is: - -1. harness sparse ELF base data, -2. committed-store/SCB accepted overlay data, -3. ready resident STQ forwarding data when no wait byte is selected. - -Ready hits continue through the reduced execute pipe. Wait hits hold the -E-stage load through the R266 execute wait input until the resident store data -becomes ready or a flush clears the pipe. A later packet may move this work -behind a registered LIQ/forward pipeline. - -## Flush/Recovery - -The module has no flush input. The top disables it when -`useReducedStoreDispatchStq=false`; STQ row validity and flush pruning are -owned by `StoreDispatchSTQPath` and `STQEntryBank`. - -## Deferred Owners - -- LIQ/LDQ wait-store row mutation and replay wakeups. -- Cross-line resident store/load forwarding. -- MDB conflict publication and recovery cleanup. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreResidentForward -bash tools/chisel/run_chisel_tests.sh --only ResidentStoreForwardStoreSnapshot -bash tools/chisel/run_chisel_tests.sh --only LoadStoreForwarding -bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute -bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop -``` - -Reference tests cover ready resident forwarding over committed overlay data, -same-BID full-LSID source selection beyond the projection width, missing -authority refusal, not-ready wait pass-through, cross-line -suppression, selected wait-store identity including PC, and Chisel elaboration -with diagnostics. A 40-bit structural test locks resident-row to selected-wait -full-LSID width preservation. diff --git a/docs/chisel/modules/lsu/ReducedStoreStaAddressExecBridge.md b/docs/chisel/modules/lsu/ReducedStoreStaAddressExecBridge.md deleted file mode 100644 index bb55f6b4..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreStaAddressExecBridge.md +++ /dev/null @@ -1,147 +0,0 @@ -# ReducedStoreStaAddressExecBridge - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreStaAddressExecBridge.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreStaAddressExecBridgeSpec.scala` -- Related Chisel: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/rename/StoreSplitPayload.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/StoreDispatchToSTQ.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreExecResultBridge.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/bctrl/spe/SPERename.cpp` - - `SPERename::InsertToStoreIEX` - - `model/LinxCoreModel/model/iex/iex_dispatch.cpp` - - store-address dispatch handling for `OpcodeIsStore && type == ST_ADDR` - - `model/LinxCoreModel/model/iex/iex_iq.cpp` - - AgeQueue insertion of loads and `ST_ADDR` store work - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQueueEntryInfo::init` - - `STQ::mergeStore` - -## Purpose - -`ReducedStoreStaAddressExecBridge` is the reduced-top owner for early split -store-address execution. It converts a visible STA queue head plus externally -supplied address-source read data into the `StoreDispatchExecResult` consumed -by `StoreDispatchToSTQ`. - -This is intentionally separate from `ReducedStoreExecResultBridge`. The older -bridge buffers full reduced-ALU store completions, so STA cannot reach the STQ -until the full store instruction has issued with both address and data operands -ready. The C++ model does not require that coupling: rename splits a store into -STA and STD work, the issue side can dispatch `ST_ADDR`, and STQ merge records -`addrRdy=true, dataRdy=false` for an address-only half. - -## Interface - -Inputs: - -- `enable`: enables the reduced STA bridge. -- `queueValid`, `queue`: current store queue head. The bridge emits for - address halves (`storeType == Addr`) and unsplit all-store rows - (`storeType == All`) whose address can be produced directly. -- `srcReadReady`: readiness for the original source lanes required by the - address formula. -- `srcReadData`: read data for the source lanes used by the address formula. - -Outputs: - -- `exec`: `StoreDispatchExecResult` for the STA half. Data is zero because STQ - address-only insertion does not need store data. -- `candidate`: the current queue head is a valid address-half candidate. -- `supportedOpcode`: the queue-head opcode has a known reduced-store address - formula. -- `addrSourceMask`: source-lane mask required by the formula. -- `addrSourceReady`: every required source lane is still present in the payload - and externally reported ready. -- `blockedBySource`: candidate is supported but an address source is not ready - or was removed from the payload. -- `blockedByUnsupported`: candidate opcode is not covered by this reduced - bridge. - -## Logic Design - -The bridge supports the reduced scalar store address formulas already used by -`ReducedScalarAluExecute`: - -- PCR stores: `pc + imm`, no address RF source required. -- `OP_SDI`: `src1 + (imm << 3)`, size 8. -- `OP_SWI`: `src1 + (imm << 2)`, size 4. -- `OP_SBI`: `src1 + imm`, size 1. -- `OP_SD`: `src1 + (src2 << 3)`, size 8. -- `OP_SC_W`: address from `SrcR`/source lane 1, store data from `SrcL`/source - lane 0, size 4. `SrcP`/source lane 2 is ignored. -- `OP_C_SDI`: `src0 + (imm << 3)`, size 8. -- `OP_C_SWI`: `src0 + (imm << 2)`, size 4. - -For every required source lane, the bridge requires both the payload source -valid bit and the external read-ready bit. This is deliberate: R475 proved the -live `LDI`/`SDI`/`LDI` stimulus already exposes a STA queue head, but the -current reduced top has no spare RF/local read owner for that queue head. -Adding this bridge first creates the exact next interface boundary: a top-level -owner must provide read data/readiness for the address lanes without waiting -for full scalar-store issue. - -The compressed store cases are marked supported but still require source 0. -Current non-PCR/non-`SC.W` `StoreSplitPayload` zeroes STA source 0, so the -bridge reports `blockedBySource` for those rows. That preserves the existing -payload contract and makes the compact-store source-loss visible instead of -silently computing from a zeroed operand. `SC.W` is a deliberate exception: -the splitter preserves source 0 so the bridge can carry store data while still -requiring source 1 for the address. - -## Model Alignment - -The model path splits store address and store data before execution: - -1. `SPERename::InsertToStoreIEX` clones a store into `ST_ADDR` and `ST_DATA` - work for split stores. -2. IEX dispatch treats store-address work as the row that can enter the LSU - address path. -3. `STQueueEntryInfo::init` records address-only rows with address ready and - data not ready. -4. `STQ::mergeStore` later merges the STD half by identity. - -`ReducedStoreStaAddressExecBridge` follows the same ownership boundary for the -reduced Chisel bring-up path: STA address calculation is a first-class producer -of `StoreDispatchExecResult`, while STD/data can remain on the existing -full-completion bridge until a dedicated STD owner is introduced. - -## Verification - -Focused gate: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreStaAddressExecBridge -``` - -R476 covered: - -- `OP_SDI` computes address from source 1 and ignores store-data source 0. -- `OP_SDI` blocks when source 1 is not ready. -- `OP_SC_W` accepts unsplit `All` and split `Addr` rows, requires only source - lanes 0 and 1, emits `SrcR` as address and `SrcL` as store data, and ignores - source lane 2. -- PCR store STA computes from `pc + imm` without RF source readiness. -- `OP_C_SDI` exposes the current STA source-0 payload loss as a source block. -- The Chisel module elaborates with the reduced top interface parameters. - -## Deferred Owners - -- Default-on live promotion. R479 wires top-level RF/local read data and - opt-in STA selection for replay-LIQ trials, but the switch remains disabled - by default because the enabled fixture still fails final idle drain. -- Arbitration between the existing scalar issue RF reads and STA address reads. -- Replay-LIQ allocation-row lifecycle after early STA. R480 proves the enabled - early-STA trial leaves `replayLiqResidentCount=1` while ResolveQ and all - reduced-store commit/drain/STQ state are empty at timeout. R481 identifies - the resident head as row 0 in `Wait` state with load id 0, RID/load-LSID 2, - PC `0x1000a`, size 8, and no wait-store, bypass, data-complete, or source - return bits. R483 fixes the launch selector's circular data-hit gate: the row - now becomes a launch candidate and completes base lookup, but launch - acceptance remains blocked by source-return/SCB readiness. The next owner is - replay source-return readiness and row lifecycle clear, not STA address - execution or the idle predicate. -- STD/data execution ownership beyond the existing buffered full-store bridge. diff --git a/docs/chisel/modules/lsu/ReducedStoreWaitReplayChiselPathProbe.md b/docs/chisel/modules/lsu/ReducedStoreWaitReplayChiselPathProbe.md deleted file mode 100644 index 90f94cde..00000000 --- a/docs/chisel/modules/lsu/ReducedStoreWaitReplayChiselPathProbe.md +++ /dev/null @@ -1,359 +0,0 @@ -# ReducedStoreWaitReplayChiselPathProbe - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathProbe.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/ReducedStoreWaitReplayChiselPathSpec.scala` -- Verilator harness: `rtl/LinxCore/tools/chisel/reduced_store_wait_replay_chisel_path_tb.cpp` -- Wrapper: `rtl/LinxCore/tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` - - `STQ::lookupForLoad` - - `model/LinxCoreModel/model/lsu/load_unit/ldq.cpp` - - `LDQInfo::handleSTQReceive` - - `LDQInfo::waitStore` - - `LDQInfo::handleSUWakeup` -- Contract IDs: `LC-CHISEL-LSU-STQ-FWD-006` - -## Purpose - -`ReducedStoreWaitReplayChiselPathProbe` is a bounded generated-RTL fixture for -the reduced store-wait replay path. It composes the real Chisel owners used by -the reduced replay-LIQ path: - -- `STQEntryBank` -- `ReducedStoreResidentForward` -- `ReducedLoadWaitReplaySlot` -- `ResidentStoreReplayWakeup` -- `ReducedLoadReplayRelaunchQueue` -- `ReducedLoadReplayLiqAllocPath` -- `LoadResolveQueue` -- `MDBConflictDetect` -- `MDBQueueFanout` -- `LoadReplayMdbLookupWaitPlan` - -The probe exists because R450 showed that delaying split STD data in the live -top does not force the younger load to execute while the resident store is -address-ready and data-late. This fixture drives that microarchitectural -window directly and proves the owner chain through generated RTL. - -## Sizing and Authority - -`lsidWidth` is independent of `entries` and defaults to 40 for this fixture. -It sizes STQ rows, resident forwarding, selected wait keys, replay wakeups, -LIQ/ResolveQ rows, and MDB payloads. The fixture accepts explicit -`loadLsIdFullValid/loadLsIdFull` inputs, captures them with the waiting load, -and retains them per allocated LIQ slot for ResolveQ and MDB planner evidence. -It never reconstructs full LSID from the projected `ROBID` fields. - -## Interface - -### Store Insert - -| Signal | Description | -|---|---| -| `storeInsertValid` | Drives one STQ insert request. | -| `storeInsert` | Native `STQStoreRequest`. The harness uses `Addr` for STA, `Data` for STD merge, and `All` for the ready-store negative case. | -| `storeInsertAccepted` | STQ insert accepted. | -| `stqOccupiedMask` | Resident STQ rows. | -| `stqAddrReadyMask` | Address-ready resident rows. | -| `stqDataReadyMask` | Data-ready resident rows. | - -### Load Lookup - -| Signal | Description | -|---|---| -| `loadValid` | Younger load lookup is active. | -| `loadAddr` | Load byte address. | -| `loadSize` | Load size in bytes. | -| `loadBid` | Younger load BID. | -| `loadLsId` | Younger load LSID. | -| `loadLsIdFullValid` / `loadLsIdFull` | Explicit full-LSID authority and value retained by the fixture for ResolveQ/MDB evidence. | -| `baseLoadData` | Base data presented to the resident-forward path. | -| `captureEnable` | Allows `ReducedLoadWaitReplaySlot` to capture a wait-store hit. | - -### Diagnostics - -| Signal | Description | -|---|---| -| `forwardWaitBlocked` | Resident store forwarder selected a not-ready older store. | -| `forwardReady` | Resident store forwarder can return ready store bytes. | -| `forwardWaitStoreValid` | Forwarder produced a wait-store identity. | -| `forwardWaitStoreIndex` | STQ row selected as the blocking store. | -| `waitSlotCaptureAccepted` | Wait slot captured the blocking store key. | -| `waitSlotActive` | Wait slot is resident. | -| `wakeValid` | Ready store row emitted a store-unit replay wakeup. | -| `waitStoreClear` | Store wakeup cleared the wait slot. | -| `relaunchQueueOutFire` | Relaunch queue handed the replay candidate to LIQ allocation. | -| `liqAllocAccepted` | LIQ accepted the replay candidate. | -| `liqRefillValid` / `liqRefillLineAddr` / `liqRefillData` | Fixture-driven refill wakeup for the allocated replay row. | -| `liqRefillAccepted` / `liqRefillWakeMask` | LIQ refill wakeup was accepted and matched resident rows. | -| `liqReplayWakeValid` / `liqReplayWake` | Fixture-driven typed `LoadReplayWakeupRequest` passed through the reduced LIQ path for source-return evidence. | -| `liqReplayWakeMergeMask` / `liqReplayWakeCompletedMask` | Child LIQ replay-wakeup merge and completion masks. | -| `liqLaunchEnable` | Fixture-owned launch arm for `ReducedLoadReplayLiqAllocPath`. | -| `liqE2LoadDataReturned` / `liqE2ScbReturned` / `liqE2StqReturned` / `liqE2ReturnReady` | Fixture-owned source-return and return-port sidebands for the launched replay row. | -| `liqLaunchValid` / `liqLaunchReady` / `liqLaunchDriveValid` / `liqLaunchAccepted` | Selector, readiness, gated drive, and accepted launch diagnostics. | -| `liqLaunchSelectedLoadLsId` | Selected launch row preserved the original load LSID. | -| `liqE4UpdateValid` / `liqE4UpdateIndex` / `liqE4WakeupValid` | E4 outcome diagnostics for the launched replay row. | -| `liqLhqRecordValid` / `liqLhqRecordLoadLsId` / `liqLhqRecordData` | LHQ hit-record diagnostics emitted when the replay row resolves. | -| `resolveQueuePushAccepted` | Probe-local `LoadResolveQueue` accepted the LHQ hit record. | -| `resolveQueueRetireValid` / `resolveQueueRetireBid` / `resolveQueueRetireLsId` | Fixture-owned ResolveQ retire watermark input. | -| `resolveQueueRetireMask` / `resolveQueueRetireCount` | ResolveQ rows selected by the retire watermark before compaction. | -| `resolveQueueValidMask` / `resolveQueueCount` / `resolveQueueFirstLoadLsId` | ResolveQ residency diagnostics after the LHQ record is appended. | -| `mdbStore` | Fixture-owned store-arrival probe for the local `MDBConflictDetect` instance. | -| `mdbResolveCandidateMask` | ResolveQ rows classified as scalar conflicts for the current store probe. | -| `mdbConflictValid` / `mdbConflictFromResolveQueue` / `mdbConflictResolveIndex` | Selected MDB conflict source and index diagnostics. | -| `mdbInnerFlush` / `mdbNukeFlush` | Same-BID versus cross-BID conflict classification from `MDBConflictDetect`. | -| `mdbConflictLoadLsId` / `mdbConflictLoadPc` | Selected load identity retained in the MDB conflict record. | -| `mdbFanoutRecordReady` / `mdbFanoutRecordAccepted` / `mdbFanoutRecordProcessed` | Fixture-local `MDBQueueFanout.recordIn` queue and process diagnostics. | -| `mdbFanoutBmdbReportValid` / `mdbFanoutBmdbLoadBid` / `mdbFanoutBmdbStoreBid` / `mdbFanoutBmdbStoreStid` | BMDB report intent produced when `MDBQueueFanout` accepts the conflict record into `MDBSSIT`. | -| `mdbFanoutSsitValidMask` | Fixture-local SSIT valid rows after the conflict record is processed. | -| `mdbLookupValid` | Fixture-owned MDB lookup request for the resolved load. | -| `mdbFanoutLookupReady` / `mdbFanoutLookupAccepted` / `mdbFanoutLookupProcessed` | `MDBQueueFanout.lookupIn` queue and lookup-processing diagnostics. | -| `mdbDeleteValid` / `mdbDeleteWaitStorePc` | Fixture-owned failed-wait delete request equivalent to `delete_lu_mdb_q`; `mdbDeleteWaitStorePc` supplies model `wait_tpc`. | -| `mdbFanoutDeleteReady` / `mdbFanoutDeleteAccepted` / `mdbFanoutDeleteProcessed` | `MDBQueueFanout.deleteIn` queue and delete-processing diagnostics. | -| `mdbFanoutDeleteMatched` / `mdbFanoutDeleteDroppedBelowStall` / `mdbFanoutDeleteReleased` | SSIT delete result diagnostics for decay below stall threshold and final zero-weight release. | -| `mdbFanoutLuOutDequeued` / `mdbFanoutLuOutHit` | LU lookup-result fanout diagnostics. | -| `mdbFanoutSuOutDequeued` / `mdbFanoutSuOutHit` | SU lookup-result fanout diagnostics. | -| `mdbFanoutSuMatchedStore` / `mdbFanoutSuStorePending` / `mdbFanoutSuWakeupValid` | Store-side MDB check result against the resident STQ rows. | -| `mdbFanoutSuWakeupStoreIndex` / `mdbFanoutSuWakeupBid` | Store-side wakeup identity selected by `MDBQueueFanout`. | -| `mdbLookupUseLiveLoad` | Fixture selector that builds `MDBQueueFanout.lookupIn.ldInfo` from the current live load identity inputs instead of the resident ResolveQ row. | -| `mdbLookupWaitPlanLookupHit` | Fixture-local `LoadReplayMdbLookupWaitPlan` saw the LU lookup hit. | -| `mdbLookupWaitPlanCandidateMask` / `mdbLookupWaitPlanTargetIndex` | Current LIQ row match diagnostics for the LU hit. | -| `mdbLookupWaitPlanWaitIntentValid` / `mdbLookupWaitPlanRequestValid` | Load-side wait intent and native mutation request diagnostics from the planner. | -| `mdbLookupWaitPlanBlockedByNoTarget` | The planner saw an LU hit but found no current matching LIQ row. | -| `mdbLookupWaitPlanBlockedByMissingStoreIndex` / `mdbLookupWaitPlanBlockedByMissingStoreLsId` | Native store identity blockers from the planner. | -| `rowMutationBridgeValid` / `rowMutationTargetEvidenceValid` | LIQ row-mutation bridge/control evidence for the planner request. | -| `rowMutationWriteEnable` / `rowMutationApplyValid` | Native LIQ row-mutation write and apply diagnostics. | -| `rowMutationBlockedByControl` / `rowMutationControlBlockedByScbNotReturned` / `rowMutationControlBlockedByE4UpdateConflict` | Control blockers proving why a valid fixture request did not write the LIQ row. | -| `liqClearResolvedPending` / `liqClearResolvedAccepted` | Probe-local delayed clear request back into LIQ after ResolveQ accepts the LHQ record. | -| `liqWaitMask` / `liqWaitStoreMask` / `liqRepickMask` / `liqResolvedMask` | LIQ row status and wait-store masks before launch, after launch, and after MDB/E4 mutation. | -| `liqSourcesReturnedMask` / `liqScbReturnedMask` / `liqStqReturnedMask` | LIQ row source-return evidence masks. | -| `liqFirstYoungestStoreLsId` | Allocated LIQ row preserved the forwarding snapshot sidecar. | - -## Logic Design - -The generated-RTL harness runs two scenarios: - -1. A ready `ST_ALL` row is inserted, then a younger load looks up the same - address. The forwarder reports ready forwarding and no wait-store key is - captured. -2. A split `STA` row is inserted, then a younger load looks up the same - address while the store has `addrReady=1` and `dataReady=0`. The forwarder - reports a wait hit, the wait slot captures the store key, a later matching - `STD` merge makes the row ready, `ResidentStoreReplayWakeup` emits a store - wakeup, the wait slot clears into a relaunch candidate, the queue fires, and - `ReducedLoadReplayLiqAllocPath` allocates a resident LIQ row. -3. The harness drives a read-refill wakeup for the allocated row's cacheline. - This gives the row complete row-owned bytes through the existing - `LoadRefillWakeup` path, making `LoadInflightLaunchSelect` assert - `launchValid`. With `liqLaunchEnable` asserted for one cycle, the LIQ row - accepts launch and enters `Repick`. -4. The same launch cycle drives all source-return sidebands and return-port - readiness. One cycle later the fixture observes `e4UpdateValid`, - `e4WakeupValid`, and `lhqRecordValid`. The fixture then performs the - explicit `markResolved` handshake; E4 does not bypass the return owner. -5. The probe appends the LHQ hit record to `LoadResolveQueue` on the E4 - cycle. A fixture-local pending-clear register captures the accepted - `loadId.value`, waits for `markResolved`, and only then drives - `clearResolved`, clearing the LIQ row while the ResolveQ record remains - resident. -6. The harness drives a cross-BID ResolveQ retire watermark, which needs no - same-BID LSID ordering authority. The fixture intentionally keeps retire - full-LSID valid low because it has no independent retire full-LSID input; - the following cycle compacts ResolveQ to empty without fabricating one. -7. Before the retire watermark, the harness drives a fixture-owned store probe - matching the older resident store. `MDBConflictDetect` consumes - `LoadResolveQueue.conflictRows`, selects ResolveQ row zero as a scalar - conflict, and classifies the cross-BID conflict as a nuke flush. -8. The same conflict cycle feeds the selected record into a fixture-local - `MDBQueueFanout`. The next cycle processes the queued record, publishes - BMDB report intent, and allocates an SSIT row. Lookup, delete, and - store-wakeup fanout remain tied off in this fixture. -9. The harness drives a second identical conflict record to reinforce the SSIT - row above the model stall threshold, then drives two lookup requests. The - first lookup after nuke learning is suppressed and clears the nuke marker; - the second lookup fans out a hit to LU and SU. The SU path scans the - resident STQ rows and emits a store wakeup for row zero. -10. The harness then drives three fixture-owned MDB delete requests with the - learned load PC and store wait PC. The first two deletes decay the SSIT row - below the stall threshold while retaining the row, and the third delete - releases the zero-weight row, matching `MDB::handleMDBDelete` / - `MDB::dec`. -11. R462 composes `LoadReplayMdbLookupWaitPlan` beside `MDBQueueFanout`. At the - existing second lookup point, LU/SU lookup hits and SU wakeup has native - store identity, but the original source LIQ row has already resolved and - been cleared into ResolveQ. The planner therefore reports - `blockedByNoTarget` with an empty candidate mask and does not emit a native - wait-store mutation request. This is the desired guard for this fixture - ordering; a positive mutation proof needs a later dynamic load that is - currently resident in LIQ when the learned SSIT lookup hits. -12. R463 wires the planner request into `ReducedLoadReplayLiqAllocPath`'s - existing row-mutation bridge and adds a fixture live-lookup selector. The - harness allocates a second replay row, accepts the live MDB lookup one - cycle before launching that row, and samples the LU/SU hit after the row - enters `Repick`. The planner now reports a live candidate at LIQ row 1 and - emits `requestValid`; the request reaches the bridge/control path, then - stops because the fixture has not yet supplied source-return evidence for a - safe row write. -13. R464 drives the existing LIQ replay-wakeup path with an SCB wake for the - second row before launch. `LoadReplayWakeup` marks row 1 - `scbReturned/sourcesReturned`, launch preserves that evidence into - `Repick`, and the MDB wait-plan request then passes native write control. - The generated-RTL harness requires `rowMutationWriteEnable=true`, - `rowMutationApplyValid=true`, and the following row image to return to - `Wait` with `waitStore` armed and return-state evidence cleared. - -This is fixture evidence for the reduced owner chain. It is not architectural -QEMU/DUT replacement evidence and does not prove live top scheduling can yet -create this timing window. - -## Verification - -Focused gates: - -```bash -bash tools/chisel/run_chisel_tests.sh --only ReducedStoreWaitReplayChiselPath -bash tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh -``` - -The wrapper emits SystemVerilog under -`generated/chisel-verilog/reduced-store-wait-replay-chisel-path`, builds a -Verilator executable, and writes: - -```text -generated/chisel-reduced-store-wait-replay-chisel-path/report/reduced_store_wait_replay_chisel_path.json -``` - -The JSON schema is `linxcore.reduced_store_wait_replay_chisel_path.v1`. A -passing R452 report records `ready_forward_observed=true`, -`sta_wait_capture=true`, `not_ready_wake_blocked=true`, -`std_wake_clear=true`, `relaunch_queue_fire=true`, `liq_alloc=true`, and -`youngest_store_lsid=1`. - -R493 adds `tools/chisel/validate_reduced_store_wait_replay_chisel_path.py` and -makes the wrapper validate the R464 positive MDB wait-plan row-write proof by -default. The packet also ties the newer `ReducedLoadReplayLiqAllocPath` -`pick`, `scbReturn`, and `markResolved` inputs inactive in this probe, because -this fixture's R464 positive path uses `LoadReplayWakeup` for SCB evidence and -does not exercise those later live-top ports. A passing wrapper run now -requires: - -- `mdb_lookup_wait_plan_scb_evidence=true` -- `mdb_lookup_wait_plan_write=true` -- `mdb_lookup_wait_plan_apply=true` -- `mdb_lookup_wait_plan_wait_status_after_write=true` -- nonzero `liq_replay_wake_completed_mask` -- nonzero `liq_scb_returned_mask_before_mdb_write` -- nonzero `liq_sources_returned_mask_before_mdb_write` -- nonzero `liq_wait_mask_after_mdb_write` -- nonzero `liq_wait_store_mask_after_mdb_write` - -The requirement lists can be overridden with -`REDUCED_STORE_WAIT_REPLAY_REQUIRE_TRUE` and -`REDUCED_STORE_WAIT_REPLAY_REQUIRE_NONZERO` when a future packet deliberately -builds a narrower diagnostic report. The default remains a regression guard -for the generated-RTL proof that learned MDB lookup can write a live LIQ row -back to native wait-store state after SCB source-return evidence arrives. - -R453 extends the same report with `liq_refill=true`, -`liq_launch_valid=true`, `liq_launch_accepted=true`, and -`launch_load_lsid=3`. This remains generated-RTL fixture evidence: the refill -and launch arm are harness-driven, and the live reduced top still ties the -alloc-path refill wakeup inactive. - -R454 extends the report with `liq_e4_update=true`, `liq_lhq_record=true`, -`liq_resolved=true`, and `e4_cycles_after_launch=1`. This proves the fixture -can carry the launched replay row through the existing `LoadForwardPipeline` -E4 outcome and `LoadInflightQueue` resolved-row write. It still is not live -QEMU/DUT replay-LIQ promotion evidence because the launch, source-return -sidebands, return readiness, and refill are harness-driven. - -R455 extends the report with `resolve_queue_push=true`, -`liq_clear_resolved=true`, and `resolve_queue_count=1`. The probe now composes -the real `LoadResolveQueue` beside the LIQ path and applies the existing -delayed clear rule after the LHQ record is accepted. This remains fixture -evidence because the replay launch and return sidebands are still -harness-driven. - -R456 extends the report with `resolve_queue_retired=true` and -`resolve_queue_count_after_retire=0`. The harness drives a commit watermark -one LSID newer than the resolved load, proving the same generated-RTL fixture -can drain the ResolveQ row through the model strict older-than retire rule -after the source LIQ row has been cleared. - -R457 extends the report with `mdb_resolve_conflict=true`, -`mdb_nuke_flush=true`, `mdb_resolve_candidate_mask=1`, and -`mdb_conflict_load_lsid=3`. The probe composes `MDBConflictDetect` with the -real `LoadResolveQueue.conflictRows`, ties active LDQ rows inactive, and lets -the harness drive an older overlapping store probe before ResolveQ retire. -This proves generated RTL exposes the resolved replay row to the MDB conflict -classifier and applies the model cross-BID nuke classification. It is still -fixture evidence, not live MDB/recovery publication, because the store probe, -replay launch, refill, source-return sidebands, return readiness, and retire -watermark are harness-driven. - -R458 extends the report with `mdb_fanout_record_accepted=true`, -`mdb_fanout_record_processed=true`, `mdb_bmdb_report=true`, and -`mdb_fanout_ssit_valid_mask=1`. The probe converts the selected -`MDBConflictDetect.record` into the same `MDBQueueBus` shape used by the live -top and feeds a fixture-local `MDBQueueFanout.recordIn` path. This proves -generated RTL can move the ResolveQ conflict record into MDB record learning -and BMDB report intent. It is still fixture evidence: lookup/delete producers, -store-wakeup fanout, live BMDB mutation, recovery publication, and ROB nuke -retirement are not driven here. - -R459 extends the report with `mdb_fanout_record_reinforced=true`, -`mdb_lookup_first_suppressed=true`, `mdb_lookup_hit=true`, -`mdb_su_wakeup=true`, and `mdb_su_wakeup_store_index=0`. The probe now feeds -`MDBQueueFanout.lookupIn` from the resident ResolveQ row and exposes real -resident STQ rows to the SU wakeup scan. The harness follows the model SSIT -contract: reinforce the same load/store pair, consume the first-after-nuke -suppressed lookup, then prove the later lookup hits and wakes the ready store. -This remains fixture evidence because lookup timing is harness-owned and no -live load wait-state mutation, recovery flush publication, or ROB nuke -retirement is driven. - -R460 extends the report with `mdb_delete_accepted=true`, -`mdb_delete_dropped_below_stall=true`, and `mdb_delete_released=true`. The -probe now feeds `MDBQueueFanout.deleteIn` from the resident ResolveQ load PC -plus fixture-provided `wait_tpc`, proving generated RTL can decay the learned -SSIT row after a failed wait and release it only after the model zero-weight -delete. This remains fixture evidence because the failed-wait timer and delete -producer are harness-owned. - -R462 extends the report with `mdb_lookup_wait_plan_no_target=true` and -`mdb_lookup_wait_plan_candidate_mask=0` while preserving the R459 -`mdb_lookup_hit=true`, `mdb_su_wakeup=true`, and -`mdb_su_wakeup_store_index=0` fields. This proves the fixture-composed -`LoadReplayMdbLookupWaitPlan` sees the LU hit and resolved SU store identity, -but correctly suppresses a native wait-store mutation request because the -source LIQ row has already been cleared after ResolveQ accepted the LHQ record. -The next positive mutation proof must use a later dynamic load row that is -still resident in LIQ when the learned MDB lookup hits. - -R463 extends the report with `mdb_lookup_wait_plan_live_target=true`, -`mdb_lookup_wait_plan_request=true`, `mdb_lookup_wait_plan_bridge=true`, -`mdb_lookup_wait_plan_control_blocked=true`, -`mdb_lookup_wait_plan_live_candidate_mask=2`, and -`mdb_lookup_wait_plan_live_target_index=1`. The probe now wires -`LoadReplayMdbLookupWaitPlan.request*` into `ReducedLoadReplayLiqAllocPath` -row mutation and lets the harness drive a second live load identity into MDB -lookup. This proves generated RTL can carry a learned SSIT lookup into a -specific live LIQ `Repick` row and through the row-mutation bridge/control -surface. It is still not a positive LIQ row-write proof because the control -path correctly blocks the write until source-return evidence is available. - -R464 extends the report with `mdb_lookup_wait_plan_scb_evidence=true`, -`mdb_lookup_wait_plan_control_blocked=false`, -`mdb_lookup_wait_plan_write=true`, `mdb_lookup_wait_plan_apply=true`, -`mdb_lookup_wait_plan_wait_status_after_write=true`, -`liq_replay_wake_completed_mask=2`, -`liq_scb_returned_mask_before_mdb_write=2`, -`liq_sources_returned_mask_before_mdb_write=2`, -`liq_wait_mask_after_mdb_write=2`, and -`liq_wait_store_mask_after_mdb_write=2`. The proof is still generated-RTL -fixture evidence: the SCB wake, live MDB lookup timing, and launch arm are -harness-driven, but the row write itself uses the native -`LoadReplayWakeup -> LoadInflightQueue -> LoadInflightRowMutationPath` -ownership path. diff --git a/docs/chisel/modules/lsu/SCBCommitBridge.md b/docs/chisel/modules/lsu/SCBCommitBridge.md deleted file mode 100644 index 5c8e97e4..00000000 --- a/docs/chisel/modules/lsu/SCBCommitBridge.md +++ /dev/null @@ -1,127 +0,0 @@ -# SCBCommitBridge - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/SCBCommitBridge.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/lsu/SCBCommitBridgeSpec.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/l1/SCB.h` - - `model/LinxCoreModel/model/l1/SCB.cpp` - - `model/LinxCoreModel/model/l1/cluster.cpp` - - `model/LinxCoreModel/model/lsu/lsu.cpp` - - `model/LinxCoreModel/model/lsu/store_unit/stq.cpp` -- Related Chisel contracts: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/STQCommitDrain.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/SCBCommitIngress.scala` -- Contract IDs: `LC-CHISEL-LSU-SCB-BRIDGE-001` - -## Purpose - -`SCBCommitBridge` is the first Chisel owner for the capacity feedback boundary -between committed STQ drain descriptors and SCB line storage. It composes -`SCBCommitIngress`, gates ingress with the model `SCBuffer::full()` rule, and -returns the committed-row free mask only after the final descriptor for a row is -accepted into SCB. - -The module owns: - -- the model batch gate for committed-store SCB admission, -- masking `STQCommitDrainRequest.valid` before structural SCB insertion, -- stalled fragment reporting when the model batch gate is closed, -- final-fragment-to-`STQEntryBank.commitFreeMask` conversion, -- pass-through observability for SCB entries and wakeups. - -It does not own DCache lookup/update, full/not-full eviction, L2/CHI request -generation, write-response matching, MDB conflict prediction, load forwarding, -or fence/store-drain completion. `SCBEgressSelect` is the next owner for -choosing a valid SCB line to present to those future paths. - -`SCBRowBank` is the later registered composition owner that reuses this -capacity/free-mask contract while also owning one mutable SCB row image around -egress lookup and state update. `STQSCBCommitPath` is the full LSU composition -owner that now consumes the row-bank free-mask surface; this standalone bridge -remains a focused combinational contract and regression point. - -## Interface - -### Inputs - -| Signal | Type | Description | -|---|---|---| -| `reqs` | `Vec[STQCommitDrainRequest]` | Candidate store fragments from `STQCommitDrain`. Split stores must present the first fragment with `last=0` and the second with `last=1`. | - -### Outputs - -| Signal | Description | -|---|---| -| `modelBatchReady` | True when current SCB free entries are at least the bridge request width, matching model `!scb.full()`. | -| `modelFull` | Inverse of `modelBatchReady`; valid descriptors must stall before freeing STQ rows. | -| `acceptedMask` | Descriptor lanes admitted into `SCBCommitIngress`. | -| `stalledMask` | Valid descriptor lanes not admitted because the model gate or structural ingress blocked them. | -| `structuralBlockedMask` | Raw `SCBCommitIngress.blockedMask` after model gating. | -| `commitFreeMaskValid/commitFreeMask/commitFreeCount` | STQ bank free command for rows whose accepted descriptor has `last=1`. | -| `wakeups` | SCB line-valid wakeups from accepted fragments. | -| `entries/validMask/fullLineMask/entryCount/freeCount/ingressFull` | SCB entry diagnostics forwarded from `SCBCommitIngress`, including the model entry state used by egress selection. | - -## State - -`SCBCommitBridge` owns no additional state. It owns the composition boundary -and instantiates `SCBCommitIngress`, which owns the registered SCB line entries. - -## Logic Design - -The bridge first observes the current SCB `freeCount` from the ingress owner. -The model `SCBuffer::full()` returns true when `free_list.size() < n_store_in`; -this Chisel packet maps `n_store_in` to `requestCount`. Therefore: - -```text -modelBatchReady = freeCount >= requestCount -``` - -If `modelBatchReady` is false, every valid request lane is reported in -`stalledMask` and no descriptor is presented to `SCBCommitIngress`. This is -intentionally more conservative than the structural ingress rule: even a -same-line hit stalls while the model batch gate is closed. - -If `modelBatchReady` is true, request lanes pass through to -`SCBCommitIngress`. Accepted lanes update SCB state and produce wakeups. The -bridge converts accepted descriptors with `last=1` into `commitFreeMask` bits -for their `stqIndex`; this preserves the model ordering where `STQ::free` -happens after the memory-side queue accepts all descriptors for the store. - -## Timing - -The bridge is combinational around the current registered SCB ingress state. -Accepted descriptors update SCB entries on the next clock through -`SCBCommitIngress`. `commitFreeMask` is valid in the admission cycle and should -be consumed only by an integration owner that uses this bridge as the sole -source of committed-row frees. - -## Flush/Recovery - -There is no flush input. The bridge handles committed stores that have already -left flushable STQ `Wait` state. Recovery-domain pruning remains in -`STQFlushPrune` and `STQEntryBank`. - -## Trace/Observability - -`modelBatchReady`, `modelFull`, `stalledMask`, and `commitFreeMask` are the -first probe surface for the model queue-stall boundary between STQ commit drain -and SCB insertion. They are not architectural commit rows and do not yet -participate in QEMU-vs-DUT trace comparison. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only SCBCommitBridge` -- `bash tools/chisel/run_chisel_tests.sh --only SCBEgressSelect` -- `bash tools/chisel/run_chisel_tests.sh --only SCBCommitIngress` -- `bash tools/chisel/run_chisel_tests.sh --only STQCommitDrain` -- `bash tools/chisel/run_chisel_tests.sh --only STQCommitQueue` -- `bash tools/chisel/run_chisel_tests.sh --only STQEntryBank` -- `bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob` -- `python3 tools/chisel/trace_schema_adapter.py --self-test` -- `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - -Focused reference tests cover model-batch admission, split-store final-fragment -freeing, conservative same-line-hit stall under model full, exact free-count -admission, and Chisel elaboration. diff --git a/docs/chisel/modules/lsu/SCBResponseBuffer.md b/docs/chisel/modules/lsu/SCBResponseBuffer.md index 8cc36f68..ed54046c 100644 --- a/docs/chisel/modules/lsu/SCBResponseBuffer.md +++ b/docs/chisel/modules/lsu/SCBResponseBuffer.md @@ -118,7 +118,7 @@ source. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover FIFO order, simultaneous legal-head pop plus diff --git a/docs/chisel/modules/lsu/SCBResponseDecode.md b/docs/chisel/modules/lsu/SCBResponseDecode.md index 0f0764a6..e85334ef 100644 --- a/docs/chisel/modules/lsu/SCBResponseDecode.md +++ b/docs/chisel/modules/lsu/SCBResponseDecode.md @@ -116,7 +116,7 @@ full top emits live memory-event trace payloads. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover legal WriteResp, legal UpgradeResp, wrong diff --git a/docs/chisel/modules/lsu/SCBResponseRetryQueue.md b/docs/chisel/modules/lsu/SCBResponseRetryQueue.md index 8bd319aa..acc49113 100644 --- a/docs/chisel/modules/lsu/SCBResponseRetryQueue.md +++ b/docs/chisel/modules/lsu/SCBResponseRetryQueue.md @@ -108,7 +108,7 @@ memory-event traces. It is not an architectural commit trace source. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover FIFO order, simultaneous pop/enqueue space, diff --git a/docs/chisel/modules/lsu/SCBResponseRetrySelect.md b/docs/chisel/modules/lsu/SCBResponseRetrySelect.md index c28b040f..11240737 100644 --- a/docs/chisel/modules/lsu/SCBResponseRetrySelect.md +++ b/docs/chisel/modules/lsu/SCBResponseRetrySelect.md @@ -125,7 +125,7 @@ comparison until live memory sideband trace rows exist. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover retry priority over ordinary egress, diff --git a/docs/chisel/modules/lsu/SCBRowBank.md b/docs/chisel/modules/lsu/SCBRowBank.md index b4ccf99f..05d46cf8 100644 --- a/docs/chisel/modules/lsu/SCBRowBank.md +++ b/docs/chisel/modules/lsu/SCBRowBank.md @@ -166,7 +166,7 @@ QEMU-vs-DUT commit comparator. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover model-batch admission, pre-cycle free-count diff --git a/docs/chisel/modules/lsu/SCBStateUpdate.md b/docs/chisel/modules/lsu/SCBStateUpdate.md index b9040e92..32dbd59a 100644 --- a/docs/chisel/modules/lsu/SCBStateUpdate.md +++ b/docs/chisel/modules/lsu/SCBStateUpdate.md @@ -129,7 +129,7 @@ comparison until the full LSU exposes memory event trace payloads. - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_verilator_lint.sh` Focused reference tests cover valid lookup start, same-cycle miss, writable-hit diff --git a/docs/chisel/modules/lsu/STQDataBank.md b/docs/chisel/modules/lsu/STQDataBank.md index dc1ded45..a14820bd 100644 --- a/docs/chisel/modules/lsu/STQDataBank.md +++ b/docs/chisel/modules/lsu/STQDataBank.md @@ -75,7 +75,7 @@ while the current scalar commit interface uses the low parameterized payload. bash tools/chisel/run_chisel_tests.sh --only STQDataBank bash tools/chisel/run_chisel_tests.sh --only STQEntryBank bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabric -bash tools/chisel/run_chisel_tests.sh --only OooO3IexStorePipeline +bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionStoreIntegration bash tools/chisel/build_chisel.sh ``` diff --git a/docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md b/docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md index 24ba02a9..b9eb6e58 100644 --- a/docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md +++ b/docs/chisel/modules/lsu/STQLoadForwardResultPipeline.md @@ -23,17 +23,36 @@ merged valid mask. ## Contract -`STQLoadForwardQuery` now carries the merged baseline line together with: +`STQLoadForwardQuery` carries the merged baseline line together with: - `baseValidMask`; - `loadDataReturned`; -- `scbReturned`. +- `scbReturned`; +- the canonical LIQ `loadId` lease; +- the producer-qualified `attempt` generation; +- the physical `returnPipeIndex`. The retained STQ response returns those fields unchanged inside `query`. A normal response is translated directly into `LoadForwardSelection`, so the canonical STQ owner is not expanded into another `LoadStoreForwardStore` CAM image. +I0.15c-b3a registers only the minimal `{loadId, attempt, returnPipeIndex}` +identity sidecar in parallel with the common result pipeline; it does not +duplicate the 64-byte baseline query image. `e3Identity` and `e4Identity` are +aligned with their corresponding valid bits under bubbles and back-to-back +traffic, and recovery flush clears both valid stages. Downstream LIQ mutation +can compare `{loadId, attempt}` before accepting an asynchronous forwarding +result instead of trusting an opaque token or a bare row index. + +I0.15c-b3c2 adds an explicit `normalReady` credit boundary. Normal STQ +responses do not enter E3 unless the downstream E3/E4 plus retained-result +owner has capacity. Structural hard blocks use their independent ready path, +so a full normal-result transport cannot hide or consume a hard-block record. +The E4 boundary also carries separate `scbReturned` and `stqReturned` evidence +into the canonical LIQ result instead of reconstructing source completion from +the merged byte mask. + Selected data-not-ready stores are normal results. Their `waitMask` and exact `waitStore` identity enter E3/E4 and classify as `StoreDataNotReady` for LIQ mutation. @@ -98,17 +117,22 @@ The directed suite proves: - byte-exact SCB-over-L1D partial merging; - partial baseline plus canonical STQ bytes completing one load; +- back-to-back exact row/attempt/return-pipe identity alignment in E3/E4; - selected not-ready store identity reaching E4; - hard-block backpressure without E3/E4 leakage; +- independent normal-result credit backpressure without blocking hard blocks; - flush suppression; - unequal `STQ=4`, `ROB=8`, `LSID=40`, and non-default token width. ## Remaining integration gap -I0.15a freezes the selector/result seam, but it does not yet claim the complete -OOO load lifecycle. The next packet must bind an exact -`OooIexLoadGeneration` to one canonical LIQ row, drive the three STQ query -ports from accepted load launches/relaunches, mutate wait/miss state only in -that LIQ owner, and return a hit/fault through the existing atomic OOO terminal -fabric. `OooIexLoadUnit` and `ScalarLSULoadPath` must not both own retry or -W1/W2 publication for the same production load. +I0.15c-b2b gives every production OOO load one exact canonical LIQ lease and +attempt identity and removes the former duplicate retry/return owner. +I0.15c-b3a carries that identity through the STQ asynchronous result pipe, and +I0.15c-b3c2 now drives three retained query lanes from canonical LIQ launches, +accepts the three retained STQ response lanes, reserves result capacity, and +applies exact E4 results back to that LIQ owner. The remaining boundary is the +closed OOO/store-fabric/scalar-LSU wrapper: common two-phase recovery, +structural-hard-block policy, final BID/BROB ordering projection, physical SCB +source ownership, and the translation/cache/coherence system still require +integration. No additional OOO request/retry/data residency may be introduced. diff --git a/docs/chisel/modules/lsu/STQLoadForwardingPipeline.md b/docs/chisel/modules/lsu/STQLoadForwardingPipeline.md index 400032f2..67ce1690 100644 --- a/docs/chisel/modules/lsu/STQLoadForwardingPipeline.md +++ b/docs/chisel/modules/lsu/STQLoadForwardingPipeline.md @@ -38,6 +38,21 @@ shared snapshot register. cross-line store, malformed query identity, and a cross-line load all fail closed through `blocked`. +I0.15c-b3a makes every accepted query attempt-qualified. In addition to the +ordering fields, the request carries: + +- `loadId`: the exact canonical LIQ slot-plus-wrap lease; +- `attempt`: the complete producer-qualified load-attempt generation; +- `returnPipeIndex`: the physical load-return pipe selected at allocation. + +The STQ pipe preserves all three fields without interpreting them. A malformed +identity may occupy the elastic lookup pipe, but result qualification fails +closed if the LIQ lease is invalid, its current bridge generation is not +representable, the attempt is malformed, the attempt STID differs from the +ordering STID, or the request is presented to a different physical STQ pipe. +The upper canonical LIQ owner remains responsible for checking the slot against +its configured capacity when the result is applied. + Recovery prepare asserts `hold`, suppressing both request ready and response valid so neither admission nor response fire can race the store recovery projection. The common accepted recovery edge asserts `flush` and removes both @@ -60,8 +75,9 @@ I0.15a adds `baseValidMask`, `loadDataReturned`, and `scbReturned` to the query sidecar and connects the retained response to `STQLoadForwardResultPipeline`. Partial L1D/SCB data and canonical STQ bytes can therefore share the common E3/E4 result owner without expanding STQ rows into -a second CAM image. Exact OOO load-generation-to-LIQ binding and replay -mutation remain the next integration packet. +a second CAM image. I0.15c-b3a binds every asynchronous response to the exact +canonical row, attempt generation, and physical return pipe. Direct LIQ result +application and replay mutation remain the next integration packet. ## Verification @@ -73,6 +89,7 @@ Directed UT uses unequal `STQ=4`, `ROB=8`, `LSID=40` and covers: - multiple unknown older addresses with nearest wait-owner selection; - E3 metadata reuse and physical-data generation rejection; - malformed identity and cross-line load rejection; +- canonical-row, producer-attempt/STID, and physical-pipe mismatch rejection; - overlapping cross-line-store rejection without false non-overlap blocking; - retained response backpressure across recovery prepare; - recovery-prepare response suppression and recovery removal of residency. @@ -90,7 +107,6 @@ Run: bash tools/chisel/run_chisel_tests.sh --only STQLoadForwardingPipeline bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabric bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionStoreIntegration -bash tools/chisel/run_chisel_tests.sh --only OooO3IexStorePipeline ``` ## Model and reference evidence diff --git a/docs/chisel/modules/lsu/STQRobCommitIngress.md b/docs/chisel/modules/lsu/STQRobCommitIngress.md index b9f8576a..ec0290ef 100644 --- a/docs/chisel/modules/lsu/STQRobCommitIngress.md +++ b/docs/chisel/modules/lsu/STQRobCommitIngress.md @@ -25,7 +25,6 @@ outputs. A physical slot number from ROB is never trusted. `STQRobCommitIngressSpec` covers unique acceptance, CommitQ backpressure, missing/duplicate rows, half-filled rows, and recovery fencing. -`OooRobStoreCommitStqIntegrationSpec` starts from a grouped ROB pair-store -batch, drains two semantic beats without a physical-index sideband, and proves -two committed STQ rows, atomic four-fragment SCB admission, and one logical -completion. +`STQSCBCommitPathSpec` starts from a grouped ROB pair-store batch, drains two +semantic beats without a physical-index sideband, and proves two committed STQ +rows, atomic four-fragment SCB admission, and one logical completion. diff --git a/docs/chisel/modules/lsu/STQSCBCommitBackend.md b/docs/chisel/modules/lsu/STQSCBCommitBackend.md index 3664d05d..b2e7faf7 100644 --- a/docs/chisel/modules/lsu/STQSCBCommitBackend.md +++ b/docs/chisel/modules/lsu/STQSCBCommitBackend.md @@ -2,7 +2,7 @@ ## Purpose -`STQSCBCommitBackend` is the production committed-store backend for an STQ +`STQSCBCommitBackend` is the committed-store backend for an STQ owned by another module. It exists so `OooIexStoreStqFabric` remains the sole physical STQ owner while the exact ROB commit ingress, CommitQ, typed translation/PMA sidecar, cacheable SCB path, and serialized non-cacheable/MMIO @@ -44,22 +44,20 @@ The external STQ owner independently prepares and applies WAIT-only recovery. This separation is intentional: speculative row pruning belongs to the STQ; non-flush committed transport belongs to this backend. -## Production composition +## Canonical composition -`OooIexExecutionStorePipeline` instantiates one `OooIexStoreStqFabric` and one -`STQSCBCommitBackend`. The backend reads that fabric's rows and drives its -mark/free ports privately. Production IO exposes exact ROB tokens and typed -memory-classification tokens; raw physical mark/free controls are no longer an -external architectural seam. +Task 15 must compose one `OooIexStoreStqFabric` and one +`STQSCBCommitBackend` behind the public IEX/LSU interface. The backend reads +that fabric's rows and drives its mark/free ports privately. Public IO exposes +exact ROB tokens and typed memory-classification tokens; raw physical mark/free +controls are not an architectural seam. -`STQSCBCommitPath` remains a lower-level compatibility/reference composition -that owns its own STQ. It must not be instantiated beside the production store -fabric. +`STQSCBCommitPath` is a lower-level self-owned-STQ test composition. It must +not be instantiated beside the canonical store fabric. ## Verification ```bash -bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionStoreIntegration bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionPipeline bash tools/chisel/run_chisel_tests.sh --only STQRobCommitIngress bash tools/chisel/run_chisel_tests.sh --only STQMemoryAttributeOwner @@ -68,19 +66,15 @@ bash tools/chisel/run_chisel_tests.sh --only STQCommittedStoreSerializer bash tools/chisel/run_chisel_tests.sh --only STQSCBCommitPath ``` -The dynamic production-adjacent IT sends STA and STD through real formal -execution lanes, observes their convergence in one pre-reserved STQ row, -classifies the exact lease, commits it without a physical-index sideband, and -proves CommitQ/SCB admission plus terminal row release. The structural gate -elaborates the full fourteen-lane wrapper with the backend in hierarchy. A -second dynamic case returns the final serialized response while recovery -prepare fences STQ mutation and proves that the row frees only after the fence -drops. +Focused tests classify an exact lease, commit it without a physical-index +sideband, and prove CommitQ/SCB admission plus terminal row release. A second +case returns the final serialized response while recovery prepare fences STQ +mutation and proves that the row frees only after the fence drops. ## Remaining gaps -- connect `OooO3RenameCoordinator.storeCommit` directly at the next canonical - O3-to-IEX top boundary; +- connect the semantic store-commit boundary through the Task 15 public + IEX/LSU composition; - replace the test PMA producer with the physical DTLB/PMP/PMA result owner; - connect the serialized request/response transport and precise terminal error publication; diff --git a/docs/chisel/modules/lsu/STQSCBCommitPath.md b/docs/chisel/modules/lsu/STQSCBCommitPath.md index 1fa9229b..4fafc875 100644 --- a/docs/chisel/modules/lsu/STQSCBCommitPath.md +++ b/docs/chisel/modules/lsu/STQSCBCommitPath.md @@ -120,7 +120,7 @@ ordinary recovery. Reset remains the architectural abort boundary. - `bash tools/chisel/run_chisel_tests.sh --only STQCommitQueueSpec` - `bash tools/chisel/run_chisel_tests.sh --only STQCommitDrainSpec` - `bash tools/chisel/run_chisel_tests.sh --only STQEntryBankSpec` -- `bash tools/chisel/run_chisel_tests.sh --only OooRobStoreCommitStqIntegrationSpec` +- `bash tools/chisel/run_chisel_tests.sh --only OooIexStoreStqFabricSpec` - `bash tools/chisel/run_chisel_tests.sh --only ScalarLSUSpec` - `bash tools/chisel/build_chisel.sh` - `bash tests/test_microarchitecture_contract.sh` diff --git a/docs/chisel/modules/lsu/ScalarLSU.md b/docs/chisel/modules/lsu/ScalarLSU.md deleted file mode 100644 index ed6ecc08..00000000 --- a/docs/chisel/modules/lsu/ScalarLSU.md +++ /dev/null @@ -1,207 +0,0 @@ -# ScalarLSU - -## Source Mapping - -- Chisel: `chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala` -- Parameters: `chisel/src/main/scala/linxcore/common/CoreParams.scala` -- Store child: `chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala` -- Load child: `chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala` -- MDB child: `chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala` -- Recovery-source child: - `chisel/src/main/scala/linxcore/lsu/ScalarLSURecoverySource.scala` -- Recovery-boundary child: - `chisel/src/main/scala/linxcore/lsu/ScalarLSURecoveryBoundary.scala` -- Tests: `chisel/src/test/scala/linxcore/lsu/ScalarLSUSpec.scala` -- Model reference: `model/LinxCoreModel/model/core/Core.cpp`, - `Core::BuildScalarLSU`; `model/LinxCoreModel/model/lsu/lsu.h`, - `LoadStoreUnit` -- Contract IDs: `LC-MA-MEM-001`, `LC-MA-RES-001` - -## Purpose - -`ScalarLSU` is the canonical Chisel ownership boundary for scalar memory -execution. R633 moved the proven STQ-to-SCB store composition beneath this -owner. R634 adds canonical LIQ-to-ResolveQ ownership with shared typed recovery. -R635 integrates scalar MDB conflict detection, SSIT/fanout, live wait mutation, -and typed conflict-flush publication. R636 adds per-row failed-wait age plus -atomic LIQ release and MDB delete feedback. R637 adds a parameterized retained -recovery-report boundary and wrap-qualified oldest BID/RID eligibility. R638 -adds exact allocator/ROB full-BID lookup and promotion. R639 proves the central -multi-source arbiter. R640 removes local cleanup selection from ScalarLSU and -publishes its exactly promoted MDB report through `ScalarLSURecoverySource`. -R658 makes `ScalarLSURecoveryBoundary` the sole report-STID watermark selector -shared with the reduced integration lane and parameterizes scalar STID count. -R659 replaces the reduced lane's duplicate MDB pieces with the complete -`ScalarLSUMDBPath` and deletes the delivery-only owner. R673 adds retained -cacheable load misses, R674 adds bounded refill transport, and R675 adds -sequential cross-line scalar assembly. R676 adds the canonical parameterized -scalar L1D arrays. Memory classification, the complete lower-memory/coherence -fabric, and final reduced-top replacement remain open, so this is not yet a -complete LSU. - -## Parameter Contract - -`CoreParams.robEntries` controls the slot-plus-wrap width of BID, GID, RID, -LSID, and typed flush identities. `ScalarLsuParams` independently controls: - -- `stqEntries` -- `stidCount` -- `commitQueueEntries` and `commitIssueWidth` -- `scbEntries` and `scbResponseBufferDepth` -- `liqEntries`, `loadMissQueueEntries`, `loadRefillQueueEntries`, and - `resolveQueueEntries` -- MDB SSIT, command, output, retained wait-plan, and recovery-report queue entries -- `mdbFailedWaitTimeoutCycles` -- MDB confidence/weight policy -- `loadSizeWidth`, architectural/physical register-tag widths, and PC width -- address, data, PE, STID, TID, size, and SIMT-lane widths -- `lineBytes` and `mapQDepth` -- `l1dSets` and `l1dWays` - -The STQ family retains backward-compatible constructors, but an explicit -`robEntries` value now propagates through insert probing, flush pruning, row -storage, commit ordering, and drain requests. STQ capacity no longer determines -architectural identity width. - -## Linx Adaptation - -The owner preserves ISA-neutral queueing, merge, drain, response buffering, -and cache-line coalescing mechanisms. Recovery uses Linx `FlushBus` scopes and -wrap-qualified BID/GID/RID/LSID sidecars. The module has no ARM exception-level, -exclusive-monitor, flags, barrier-encoding, or acquire/release instruction -state. - -## Current Composition - -The `store` child `STQSCBCommitPath` owns speculative STQ rows, ordered committed-store -drain, SCB coalescing/state, and buffered raw responses. An SCB-accepted final -fragment is the only committed-row free source. `LinxCoreTop.idle` now requires -an empty reduced ROB, STQ, commit-drain queue, SCB row bank, and SCB response -buffer. The `load` child `ScalarLSULoadPath` owns active LIQ rows, resolved -load records, shared typed pruning, transfer credit, and source-row clear. -It also owns `ScalarLSUMDBPath`; accepted address-bearing stores are capacity -gated before conflict publication, and accepted scalar loads enter MDB lookup -before launch. Stable failed predictions age per LIQ row and release only with -accepted SSIT delete enqueue. Top-level idle also requires MDB transient queues -and retained wait/wakeup/recovery state to be empty. -R673 adds `LoadMissQueue` beneath the load child. Accepted launches reserve -worst-case miss capacity, E4 data misses become retained line transactions, -and exact generated responses feed LIQ refill. Miss entries, issued orphans, -and reservations participate in top-level idle. -R674 adds `LoadRefillTransport` beneath the same child. Exact miss responses -and external refills use independent ready/valid ingress, may both enqueue in -one cycle, and drain to LIQ in deterministic FIFO order. Buffered refill state -also participates in top-level idle. -R675 retains one architectural load identity while first- and second-line -phases independently use forwarding, miss, refill, and replay. The completed -first line remains in the LIQ row; only the completed second phase may assemble -and publish one scalar result. Sequential launch is a throughput policy, not a -second architectural load. -R676 adds `ScalarL1D` beneath the load child and connects SCB lookup/update -through the parent, so scalar load and committed store paths share one cache -tag/data/permission owner. Refills, duplicate protection, eviction, and cache -state are no longer external base-data assumptions. The reusable load child -exposes this store-side connection as a separate internal `scbCache` port; -the public `ScalarLSUIO.load` interface does not expose ignored duplicate SCB -cache inputs. - -`ScalarLSU` connects the retained MDB report to -`ScalarLSURecoveryBoundary`, which selects one watermark from the -`stidCount`-sized owner vectors before `ScalarLSURecoverySource` performs age -and identity promotion. The caller supplies per-STID oldest BID/RID -watermarks, the exact ROB lookup result, and central source readiness. An -out-of-range report issues no lookup and remains retained. Non-immediate -reports remain queued until age, identity echo, full-sideband validity, ring -projection, and arbiter acceptance all pass. Lookup failure cannot fall back -to ring-only cleanup. - -The LSU exports `FullBidFlushReq source` and does not instantiate -`RecoveryCleanupControl`. It therefore cannot impose full-over-MDB or any other -competing-source priority. `RecoverySourceArbiter` owns retained producer -selection; `RecoveryCleanupControl` owns the selected registered intent and -side-effect fanout. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ScalarLSUSpec` -- `bash tools/chisel/run_chisel_tests.sh --only LoadMissQueueSpec` -- `bash tools/chisel/run_chisel_tests.sh --only LoadRefillTransportSpec` -- `bash tools/chisel/run_chisel_load_miss_queue_probe.sh` -- `bash tools/chisel/run_chisel_load_refill_transport_probe.sh` -- `bash tools/chisel/run_chisel_tests.sh --only ScalarL1DSpec` -- `bash tools/chisel/run_chisel_scalar_l1d_probe.sh` -- `bash tools/chisel/run_chisel_scalar_l1d_scb_probe.sh` -- R676 final: 269 suites and 1,630 tests; expanded LSU promotion gate; - generated cache, SCB/L1D composition, and composed cross-line proof; 1,467-row CoreMark - no-regression with zero mismatches and zero CBSTOP. -- R675 final: 268 suites and 1,626 tests; expanded LSU promotion gate; - generated hit/hit, hit/miss/refill/hit, and precise-recovery cross-line - proof; 1,467-row CoreMark no-regression with zero mismatches and zero CBSTOP. -- R674 final: 268 suites and 1,622 tests; expanded LSU promotion gate; both - generated miss/refill probes; 1,467-row CoreMark no-regression with zero - mismatches and zero CBSTOP. -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreTopSpec` -- focused STQ, drain, insert-probe, and flush-prune suites -- `bash tools/chisel/run_chisel_top_xcheck.sh` - -R635 elaborates a 32-entry ROB identity with independently sized STQ, LIQ, -ResolveQ, SSIT, MDB command/output queues, and wait-plan queue. Focused tests -cover typed conflict recovery, retained multi-row waits, lookup hold-until- -mutation, and pre-launch `Wait` row mutation. This remains partial LSU evidence -until cache/miss, final recovery, and load-return owners are integrated. - -R636 adds `LoadWaitStoreTimeoutSpec` and extends the canonical generated-RTL -probe through three timeout-driven delete commands: two SSIT weight decays and -one final release. The implementation uses deterministic row-keyed age instead -of the model's ineffective shared `oldestPending` counter enable. The full -suite passes 247 suites and 1,466 tests; canonical top xcheck passes 3 rows -with zero mismatches; and reduced CoreMark passes 665 rows with zero mismatches -at `generated/r636-final-failed-wait-coremark/report/crosscheck_manifest.json`. - -R637 proves report retention in the canonical MDB generated-RTL lane and a -separate `RecoveryCleanupControl` to real `ROBEntryBank` path. Ring-only input -never asserts full-BID BCTRL/BROB cleanup authority. The generated path also -proves non-oldest retention, full-over-ring priority, and consume-plus-replace. -The real ROB prune also preserves a younger different-STID row. The full suite -passes 249 suites and 1,474 tests; canonical top xcheck passes 3 -rows with zero mismatches; and reduced CoreMark passes 426 rows with zero -mismatches at -`generated/r637-final-mdb-recovery-coremark/report/crosscheck_manifest.json`. - -R638 adds focused `ROBFullBidLookupSpec` and -`RingFullBidRecoveryBridgeSpec`. The evolved generated recovery probe rejects a -wrong RID, recovers allocator-stamped full BIDs, enables block cleanup only -after exact promotion, and retains the different-STID row during ROB prune. -The full suite passes 251 suites and 1,481 tests; canonical top xcheck passes 3 -rows with zero mismatches; and reduced CoreMark passes 426 rows with zero -mismatches and zero CBSTOP at -`generated/r638-final-full-bid-recovery-coremark/report/crosscheck_manifest.json`. - -R639 extends the real-ROB generated probe with `RecoverySourceArbiter` and -proves simultaneous admission, same-STID oldest selection, losing-source -retention, invalid-STID rejection, and cross-STID fairness. This is harness -evidence; production ScalarLSU-to-central-arbiter wiring remains open. - -R640 extracts `ScalarLSURecoverySource`, removes LSU-local cleanup arbitration, -and uses that same production source owner in the real-ROB generated path ahead -of `RecoverySourceArbiter`. Focused elaboration rejects any -`RecoveryCleanupControl` child beneath ScalarLSU. -The full suite passes 251 suites and 1,483 tests; canonical top xcheck passes 3 -rows with zero mismatches; and reduced CoreMark passes 426 rows with zero -mismatches and zero CBSTOP at -`generated/r640-final-scalar-lsu-recovery-source-coremark/report/crosscheck_manifest.json`. - -R658 shares `ScalarLSURecoveryBoundary` with the retained reduced MDB delivery -lane and proves that invalid STID blocks lookup, source publication, and report -release. The full suite passes 261 suites and 1,544 tests; the generated MDB -probe passes; the live fixture compares 3 rows; and the CoreMark replay compares -426 rows with zero mismatches and zero CBSTOP at -`generated/r658-final-scalar-lsu-recovery-boundary-coremark/report/crosscheck_manifest.json`. -R659 additionally requires the live reduced top to elaborate exactly one -`ScalarLSUMDBPath`, `MDBConflictDetect`, and `MDBQueueFanout`, contain the -shared recovery boundary, and contain no delivery-only recovery hierarchy. - -R670 makes `CoreParams.lsidWidth` the canonical scalar LSU memory-order width -and passes it into the STQ-to-SCB store composition. This changes no ARM-visible -state and leaves cache-line coalescing, ROB identity, and queue sizing -independent. diff --git a/docs/chisel/modules/lsu/ScalarLSULoadPath.md b/docs/chisel/modules/lsu/ScalarLSULoadPath.md index 6353b593..63e6e0d3 100644 --- a/docs/chisel/modules/lsu/ScalarLSULoadPath.md +++ b/docs/chisel/modules/lsu/ScalarLSULoadPath.md @@ -10,8 +10,13 @@ - Refill transport: `chisel/src/main/scala/linxcore/lsu/LoadRefillTransport.scala` - Load return: `chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueue.scala` - Return W1/W2: `chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnPipeline.scala` +- STQ result transport: + `chisel/src/main/scala/linxcore/lsu/STQLoadForwardResultPipeline.scala` and + `chisel/src/main/scala/linxcore/lsu/LoadForwardResultRetainer.scala` - Tests: `chisel/src/test/scala/linxcore/lsu/ScalarLSULoadPathSpec.scala` and `chisel/src/test/scala/linxcore/lsu/LoadAttemptBindingSpec.scala` +- Forwarding IT: + `chisel/src/test/scala/linxcore/lsu/ScalarLSULoadForwardIntegrationSpec.scala` - Generated proof: `tools/chisel/run_chisel_scalar_lsu_load_path_return_probe.sh` - Model: `model/LinxCoreModel/model/lsu/load_unit/ldq.cpp`, `LDQInfo::returnData`, `LDQInfo::flush`, and `LDQInfo::CheckMovRslvQ`; @@ -32,6 +37,10 @@ lifecycle instead of relying on reduced-top pending bits and sideband wiring. free slots, and the row's exact `(STID, return pipe)` lane has unreserved capacity, and physical miss entries exceed outstanding miss reservations. Launch acceptance increments both return-lane and miss reservations. + `launchValid/launchIndex` remain the raw arbitration intent. OOO + may additionally enable a metadata permit before acceptance; same-row + replay rebind is conservatively excluded from the raw intent without + depending on the downstream credit-qualified permit. 3. E4 releases both launch reservations on hit, miss, or replay. A data miss atomically enters `LoadMissQueue`; a hit extracts final scalar data and enters ResolveQ plus the selected LRET queue atomically; @@ -66,6 +75,17 @@ lifecycle instead of relying on reduced-top pending bits and sideband wiring. row, may be rebound only by an exact consecutive-generation transaction, and survives ResolveQ/LRET plus W1/W2 retention. `robLookupAttempt` and terminal `completion.payload.attempt` expose the same identity. +13. `useExternalStqForwarding` mode atomically places every accepted launch + into exactly one retained query queue selected from the parameterized load + pipes; W4 has two queues. Hard flush + clears them; typed precise recovery fences external fire while preserving + surviving requests and recomputing their return/miss reservations. + The selected queue retains `valid` and the complete payload while the STQ + pipe is backpressured. Returned normal responses reserve bounded E3/E4 plus + result-FIFO capacity before acceptance; structural uncertainty exits on a + separate retained `hardBlock` port. The complete classified result then + remains owned by `LoadForwardResultRetainer` until the exact LIQ row accepts + it or classifies it as permanently stale. `transferProtocolError` reports missing ResolveQ/LRET capacity, a partial sink acceptance, or a new accepted transfer while an older source clear is blocked. @@ -86,12 +106,13 @@ stage entries; W1/W2 residency participates in load-path quiescence. The attempt sidecar is not an LSU ordering identity. BID/group/full-LSID and the LIQ slot-plus-wrap lease remain authoritative for lifecycle and recovery. -The future OOO adapter must validate both domains and may not reconstruct the +The installed OOO adapter validates both domains and may not reconstruct the producer key from legacy ROB IDs. `liqEntries` must not exceed the ROB identity domain used by replay -diagnostics. Reduced tops with a smaller ROB therefore select a matching LIQ -size explicitly; the production defaults remain independently configurable. +diagnostics. Explicit configurations must satisfy that relation; the default +OOO canonical adapter caps its default LIQ population to the available ROB +identity domain rather than widening or truncating native BID projection. ## Recovery @@ -138,13 +159,38 @@ one little-endian extended value. The generated return-path probe covers both hit/hit and hit/miss/refill/hit sequences and verifies the second miss uses the next aligned line. +The retained STQ forwarding mechanism is parameterized by +`CoreParams.lsu.loadPipes`; W4 instantiates exactly two query/response lanes. +`STQLoadForwardResultPipeline` and `LoadForwardResultRetainer` remain the +single forwarding-result owners. Task 15 connects them directly to +`LoadIexIssuePipeline`, `OooIexCanonicalLoadOwnership`, and the canonical STQ +through the typed IEX/LSU boundary. The deleted combined scalar-load/store +shell is not an integration layer and must not be recreated. + +The remaining integration gaps are explicit: + +- install the retained load and store owners in the full IEX/LSU topology + without duplicating LIQ, forwarding, metadata, or STQ state; +- extend recovery projection equality beyond resident LIQ rows to all LSU + queues and the final BID/BROB recovery adapter; +- define and connect the policy consumer for retained structural `hardBlock` + responses; +- replace the native-BID projection with the final common BID/BROB ordering + adapter and prove wrap/age behavior across block boundaries; +- connect the physical SCB source-return owner, DTLB/PMP/PMA, coherence, and + lower-memory transactions; +- close timing and workload promotion. Focused forwarding IT is not a + Dhrystone/CoreMark closure claim. + ## Verification +- `bash tools/chisel/run_chisel_tests.sh --only LSUMechanismSpec` - `bash tools/chisel/run_chisel_tests.sh --only LoadInflightQueueSpec` - `bash tools/chisel/run_chisel_tests.sh --only LoadMissQueueSpec` - `bash tools/chisel/run_chisel_tests.sh --only LoadRefillTransportSpec` - `bash tools/chisel/run_chisel_tests.sh --only LoadResolveQueueSpec` - `bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadPathSpec` +- `bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadForwardIntegration` - `bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadReturnPipelineSpec` - `bash tools/chisel/run_chisel_tests.sh --only ScalarLSUMDBPathSpec` - `bash tools/chisel/run_chisel_tests.sh --only LoadWaitStoreTimeoutSpec` @@ -156,6 +202,9 @@ next aligned line. - `bash tools/chisel/run_chisel_tests.sh --only ScalarL1DSpec` - `bash tools/chisel/run_chisel_scalar_l1d_probe.sh` - `bash tools/chisel/run_chisel_scalar_l1d_scb_probe.sh` +- The forwarding IT executes five reset-separated scenarios in one bounded + simulation. Its generated directory is 47 MiB rather than the prior 243 MiB + five-elaboration shape. - R676 final: 269 suites and 1,630 tests; expanded LSU promotion gate; generated cache, SCB/L1D composition, and hit/miss/refill/cross-line proof; 1,467-row CoreMark diff --git a/docs/chisel/modules/lsu/ScalarLSURecoverySource.md b/docs/chisel/modules/lsu/ScalarLSURecoverySource.md index 66b42292..d442be6b 100644 --- a/docs/chisel/modules/lsu/ScalarLSURecoverySource.md +++ b/docs/chisel/modules/lsu/ScalarLSURecoverySource.md @@ -96,7 +96,7 @@ selection and invalid-scope rejection therefore have one implementation. - `bash tools/chisel/run_chisel_tests.sh --only ScalarLSU` - `bash tools/chisel/run_chisel_tests.sh --only RecoveryCleanupROBProbeSpec` - `bash tools/chisel/run_chisel_recovery_cleanup_rob_probe.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` R640 passes 251 suites and 1,483 tests. The generated real-ROB path and canonical MDB probe pass. The canonical top cross-check passes 3 rows with zero diff --git a/docs/chisel/modules/lsu/StoreDispatchQueues.md b/docs/chisel/modules/lsu/StoreDispatchQueues.md index d64ec267..f4013784 100644 --- a/docs/chisel/modules/lsu/StoreDispatchQueues.md +++ b/docs/chisel/modules/lsu/StoreDispatchQueues.md @@ -141,7 +141,7 @@ bash tools/chisel/run_chisel_tests.sh --only STQEntryBank bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles bash tools/chisel/run_chisel_tests.sh --only DispatchROBAllocator bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run bash tools/chisel/build_chisel.sh bash tools/chisel/run_chisel_verilator_lint.sh diff --git a/docs/chisel/modules/lsu/StoreDispatchSTQPath.md b/docs/chisel/modules/lsu/StoreDispatchSTQPath.md index bc1b6d70..9bde5229 100644 --- a/docs/chisel/modules/lsu/StoreDispatchSTQPath.md +++ b/docs/chisel/modules/lsu/StoreDispatchSTQPath.md @@ -148,7 +148,7 @@ bash tools/chisel/run_chisel_tests.sh --only StoreSplitPayload bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run bash tools/chisel/build_chisel.sh bash tools/chisel/run_chisel_verilator_lint.sh diff --git a/docs/chisel/modules/lsu/StoreDispatchToSTQ.md b/docs/chisel/modules/lsu/StoreDispatchToSTQ.md index 4ddf78a8..38cc52fa 100644 --- a/docs/chisel/modules/lsu/StoreDispatchToSTQ.md +++ b/docs/chisel/modules/lsu/StoreDispatchToSTQ.md @@ -165,7 +165,7 @@ bash tools/chisel/run_chisel_tests.sh --only StoreSplitPayload bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath bash tools/chisel/run_chisel_tests.sh --only InterfaceBundles bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run bash tools/chisel/build_chisel.sh bash tools/chisel/run_chisel_verilator_lint.sh diff --git a/docs/chisel/modules/ooo/OooCtuIngressBridge.md b/docs/chisel/modules/ooo/CTU.md similarity index 90% rename from docs/chisel/modules/ooo/OooCtuIngressBridge.md rename to docs/chisel/modules/ooo/CTU.md index fd6691ee..9eb43093 100644 --- a/docs/chisel/modules/ooo/OooCtuIngressBridge.md +++ b/docs/chisel/modules/ooo/CTU.md @@ -1,8 +1,8 @@ -# OooCtuIngressBridge +# CTU ## Purpose -`OooCtuIngressBridge` is the production OOO-side boundary for the external +`CTU` is the production OOO-side boundary for the external Code Template Unit. It sits after D1 decode/fusion and before D2 grouping. It owns ingress ordering and lease lifetime, but not template recipe computation, physical-resource allocation, execution, or architectural effects. @@ -51,9 +51,9 @@ apply must be the same event as O3 common apply. ## Verification ```bash -bash tools/chisel/run_chisel_tests.sh --only OooCtuIngressBridge -bash tools/chisel/run_chisel_tests.sh --only OooIfuD1Ingress -bash tools/chisel/run_chisel_tests.sh --only OooFrontendCtuRecoveryIntegration +bash tools/chisel/run_chisel_tests.sh --only CTUSpec +bash tools/chisel/run_chisel_tests.sh --only OOODecodeSpec +bash tools/chisel/run_chisel_tests.sh --only CTUOOOIntegrationSpec ``` The tests cover mixed normal/template/normal order, six-child multi-RID diff --git a/docs/chisel/modules/ooo/OooRobStoreCommitOwner.md b/docs/chisel/modules/ooo/CommitControl.md similarity index 90% rename from docs/chisel/modules/ooo/OooRobStoreCommitOwner.md rename to docs/chisel/modules/ooo/CommitControl.md index d709a261..6b41f364 100644 --- a/docs/chisel/modules/ooo/OooRobStoreCommitOwner.md +++ b/docs/chisel/modules/ooo/CommitControl.md @@ -1,6 +1,6 @@ -# OooRobStoreCommitOwner +# CommitControl -`OooRobStoreCommitOwner` is the OOO-side owner of ROB-authorized scalar-store +`CommitControl` is the OOO-side owner of ROB-authorized scalar-store tokens. It participates in the same terminal commit transaction as grouped ROB/BROB/PC deallocation and P/T/U retirement. @@ -30,7 +30,7 @@ maxMemoryRequestsPerInstruction`. ## Verification -`OooRobStoreCommitOwnerSpec` checks atomic scalar-plus-pair capture, output +`OOORobCommitSpec` checks atomic scalar-plus-pair capture, output stability under backpressure, exact beat ordering, broken cross-group chain rejection, and modular full-serial wrap. The end-to-end store integration test connects this owner to the physical STQ matcher and SCB path. diff --git a/docs/chisel/modules/ooo/OooMemoryOrderAllocator.md b/docs/chisel/modules/ooo/OooMemoryOrderAllocator.md index 2d691bf1..cf2f1fe8 100644 --- a/docs/chisel/modules/ooo/OooMemoryOrderAllocator.md +++ b/docs/chisel/modules/ooo/OooMemoryOrderAllocator.md @@ -11,7 +11,7 @@ Source and tests: - `chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala` - `chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala` -- `chisel/src/test/scala/linxcore/ooo/OooO3IexIntegrationSpec.scala` +- `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` ## State and owner events @@ -70,9 +70,8 @@ and queue wrap must not alter serial identity. ```bash bash tools/chisel/run_chisel_tests.sh --only OooMemoryOrderAllocator -bash tools/chisel/run_chisel_tests.sh --only OooO3IexIntegration -bash tools/chisel/run_chisel_tests.sh --only OooRobBrobPcCoordinator -bash tools/chisel/run_chisel_tests.sh --only OooS1GroupedRob +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec bash tools/chisel/run_chisel_tests.sh --only OooIexStoreIssueFrontier bash tools/chisel/build_chisel.sh ``` diff --git a/docs/chisel/modules/ooo/OooO3IexStorePipeline.md b/docs/chisel/modules/ooo/OooO3IexStorePipeline.md deleted file mode 100644 index 2a473c05..00000000 --- a/docs/chisel/modules/ooo/OooO3IexStorePipeline.md +++ /dev/null @@ -1,66 +0,0 @@ -# OooO3IexStorePipeline - -## Purpose - -`OooO3IexStorePipeline` is the production composition from grouped D2 input -through D3/S1 O3 ownership, typed issue/execute, exact grouped-ROB completion, -and canonical STQ/CommitQ/SCB store retirement. - -It instantiates `OooO3RenameCoordinator` with the formal physical profile's -real capability topology and connects it directly to -`OooIexExecutionStorePipeline`. The following seams are private: - -- O3 S1 publication into retained IEX residency; -- exact dispatch-slot release and PTag recycle; -- every execution terminal completion lane plus fast completion through the - retained ROB completion buffer; -- semantic ROB store-commit tokens into the sole canonical STQ backend; -- PC-buffer reads requested by issue; -- one common O3/IEX/STQ recovery prepare and apply transaction; -- fast-result PRF writeback and issue wakeup. - -The boundary still exports real architectural or SoC consumers: BCTRL and -trace, memory requests/responses, external execution families, translation/PMA -classification, cache/device store transport, ROB commit, non-flush evidence, -and global recovery requests. - -## Ownership guarantees - -No external Boolean ready can publish S1, discard an execution completion, -recycle a PTag, or acknowledge a committed store. All such handshakes end at -the owner that mutates the corresponding retained state. - -Two ordinary completion lanes and fast resolve may arrive in one cycle. They -enter `OooRobCompletionBuffer` together and drain through the current -single-write ROB without producer loss. Store retirement carries semantic -ROB/BROB/member and full memory-order identity; it never exposes an STQ index. - -## Verification - -```bash -env LINX_CHISEL_SBT_MEM_MB=4096 \ - bash tools/chisel/run_chisel_tests.sh --only OooO3IexStorePipeline -env LINX_CHISEL_SBT_MEM_MB=4096 \ - bash tools/chisel/run_chisel_tests.sh --only OooRobStoreCommitStqIntegration -``` - -The top structural IT uses bounded test capacities and CHIRRTL elaboration so -the complete owner graph fits the 4 GiB local JVM budget. Child SystemVerilog -and dynamic tests independently cover O3 recovery, fourteen-lane execution, -fast resolve, canonical STA/STD convergence, exact ROB-token matching, -CommitQ, SCB, serialized completion, and terminal STQ release. A full combined -SystemVerilog emission was intentionally not claimed: it exceeded the 4 GiB -test heap during FIRRTL lowering. - -## Remaining production gaps - -- Replace typed test classification with physical DTLB/PMP/PMA ownership and - connect the selected uncached/device fabric. -- Add the physical store-data bank, load forwarding and overlap checks, - violation detection/replay, and serial-wrap quiescence. -- Implement retained multicycle/system/pointer-authentication/floating-vector/ - engine-command owners rather than leaving explicit typed boundaries. -- Close default-width synthesis timing and generated-graph cost, then promote - this owner beneath the IFU/CTU/D1 core top. -- Run CoreMark and Dhrystone only after that canonical top promotion; current - focused gates are integration evidence, not benchmark completion. diff --git a/docs/chisel/modules/ooo/OooO3RenameCoordinator.md b/docs/chisel/modules/ooo/OooO3RenameCoordinator.md deleted file mode 100644 index b53360bc..00000000 --- a/docs/chisel/modules/ooo/OooO3RenameCoordinator.md +++ /dev/null @@ -1,130 +0,0 @@ -# OooO3RenameCoordinator - -## Purpose - -`OooO3RenameCoordinator` is the atomic seam between D2 virtual -planning and the D3/S1 physical owners. It composes grouped ROB/BROB/PC -reservation, PTag staging and P rename, independent T/U rename, dispatch -reservation, full memory-order serial allocation, IEX S1 publication, fast -resolve, commit, and retained recovery. No child owner may publish or recover -independently through this wrapper. - -`OooRobStoreCommitOwner` is a commit peer of P rename and T/U retirement. -Its side-effect-free exactness/credit probe joins commit start; its complete -semantic store-beat batch is captured only on the same terminal -ROB/BROB/PC deallocation fire. The resulting `storeCommit` stream is -independently backpressured by LSU and never carries a physical STQ index. - -`OooMemoryOrderAllocator` is joined at the same three boundaries as the other -physical owners. D2 prepare proves recipe-derived load/store demand and claims -one complete per-STID serial suffix at D3 reserve. The exact lease reaches ROB -group bindings and IEX S1 on the common publication fire. A provisional lease -may roll back only through private same-STID cancel; a published tail may move -back only through the grouped-ROB recovery plan and the common all-owner apply. -Full LSID/LID/SID values are independent from RID, BID, LHQ, and STQ capacity. - -Execution completion is a retained vector boundary. Every physical terminal -lane plus fast resolve may publish in the same cycle into -`OooRobCompletionBuffer`; the buffer preserves lane/FIFO order and drains the -current single-write grouped ROB without forcing completed producers to wait -behind a one-result arbiter. The buffer joins the same global recovery -prepare/apply transaction and compacts only exact surviving members. - -## D3 identity and pointer domains - -The D3 reservation allocator owns four independent per-STID state domains: - -- `headSlot/headGeneration` identifies the oldest live published group and - advances only when an exact release is accepted; -- `tailSlot/tailGeneration` identifies the next absolute wrap-qualified ROB - group reservation and advances on reserve; -- `tailEpoch` invalidates D2 virtual-tail previews whenever reserve, release, - cancel, or recovery changes the reservation view; -- `nextTransactionId` identifies the next D3 reservation transaction and - advances monotonically modulo its configured width after accepted reserve. - -Recovery may rewind the wrap-qualified tail to the exact surviving suffix end. -It must not rewind transaction identity. Recovery also advances `tailEpoch`, -so a D2 plan made from the pre-recovery tail is stale even when the restored -numeric slot happens to match it. - -These domains must not be derived from an instruction serial number, a -cumulative issued count, or current ROB occupancy. In particular: - -```text -accepted reserve: tail += groupCount; tailEpoch += 1; transactionId += 1 -accepted release: head += groupCount; tailEpoch += 1 -accepted recovery: tail = exact newTail; tailEpoch += 1; transactionId holds -``` - -`usedGroups` and `publishedGroups` describe live physical occupancy. They -shrink on recovery and therefore are not transaction counters. - -## Recovery composition - -The grouped ROB is the sole exact kill-set authority. The lower -`OooRobBrobPcCoordinator` validates the retained ROB plan independently -against D3 head/count/tail state, BROB state, and PC-buffer state. The upper -coordinator then prepares dispatch, IEX, fast-resolve, memory-order, and P/T/U -owners and fires one common destructive apply. Rejection or abort mutates no -owner. The memory-order owner uses the original pivot/killed-row chain to prove -the old published tail, while the surviving pivot's per-logical-uop snapshot -defines the new trimmed tail. - -The following outputs are read-only verification and integration visibility: - -- `d3UsedGroups`, `d3PublishedGroups`; -- `d3TailSlot`, `d3TailGeneration`, `d3TailEpoch`; -- `d3NextTransactionId`. - -They expose the real owner state to independent reference models. They are not -alternate allocation inputs and must not be used to reconstruct a new tail or -transaction identity in glue. - -## Reference-model evidence - -The LinxCoreModel keeps the same conceptual separation: - -- `SPEROB::allocROB` advances allocation state independently from live size; -- `SPEROB::flush` truncates exact live entries and restores the allocation - position; -- `GPRRename::Flush` frees killed MapQ PTags and rebuilds speculative mapping - from committed state plus survivors. - -The O8.3a randomized scoreboard therefore maintains independent instruction -serial, transaction ID, head, tail, tail epoch, and live-source state. After -every publication or recovery it compares those domains separately with the -DUT, including recovery after RID wrap. - -## Verification - -```bash -bash tools/chisel/run_chisel_tests.sh --only OooD3ReservationAllocator -bash tools/chisel/run_chisel_tests.sh --only OooRobBrobPcCoordinator -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameRandomized -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator -bash tools/chisel/run_chisel_tests.sh --only OooMemoryOrderAllocator -bash tools/chisel/run_chisel_tests.sh --only OooO3IexIntegration -bash tools/chisel/run_chisel_tests.sh --only OooRobCompletionBuffer -bash tools/chisel/build_chisel.sh -``` - -Directed coverage includes a nonzero ROB head, tail-generation wrap, exact -recovery to slot zero of the new generation, unchanged transaction identity, -advanced tail epoch, and successful reuse of the restored tail. The randomized -four-STID integration crosses publication and survivor/trigger-kill recovery -while comparing all P/T/U and grouped-ROB occupancy state after every event. - -## Remaining O8 work - -O8.3a closes absolute recovery-tail/reference-model behavior. O8.3b-d establish -MapQ retained read timing and the ROB physical bank/subbank address boundary; -O8.3e bounds the ROB recovery scan, and O8.3f separates retained head -selection, banked payload read, and commit-driven pointer mutation. O8.3g adds -the PC-buffer banked address boundary without changing this coordinator's -token or common-fire protocol. O8.3h lets the PC owner join preparation only -after its bounded retained scan, while the coordinator continues to hold the -same plan. Physical PC metadata/read realization, combinational -commit/non-flush prefix discovery, occupancy/in-flight/PTag-aware dispatch -steering, safe-mode policy, and complete 2/4/6 timing closure remain separate -O8 packets. diff --git a/docs/chisel/modules/ooo/OooPcBuffer.md b/docs/chisel/modules/ooo/OooPcBuffer.md index a3c24468..81e2bcd1 100644 --- a/docs/chisel/modules/ooo/OooPcBuffer.md +++ b/docs/chisel/modules/ooo/OooPcBuffer.md @@ -111,8 +111,7 @@ It is not evidence for a bank count or port realization. commit clear, exact recovery clear, and surviving-row coherence; - 1/2/4-bank elaboration paired with 2/4/6 decode widths. -`OooRobBrobPcCoordinatorSpec`, `OooO3RenameCoordinatorSpec`, -`OooO3IexIntegrationSpec`, and `OooFrontendIfuRecoveryIntegrationSpec` cover +`OOORecoverySpec` and `OOOIntegrationSpec` cover the common O3 publication/commit/recovery transaction and both adjacent IEX and real-IFU recovery boundaries. diff --git a/docs/chisel/modules/ooo/OooRobCompletionBuffer.md b/docs/chisel/modules/ooo/OooRobCompletionBuffer.md index 3f6a51bf..a5da4cfe 100644 --- a/docs/chisel/modules/ooo/OooRobCompletionBuffer.md +++ b/docs/chisel/modules/ooo/OooRobCompletionBuffer.md @@ -23,9 +23,9 @@ malformed row rejects the common recovery. On the common apply edge, only killed members are removed; survivors from the target STID and all rows from other STIDs are compacted in original FIFO order. -This owner participates in `OooO3RenameCoordinator`'s global prepare/apply -rendezvous. Completion state therefore cannot escape suffix recovery or be -dropped by a local flush shortcut. +This remains an independently tested Task-12 mechanism. Public +`OOOD3S1Graph` currently routes typed completion through its arbitration into +ROB, whose canonical recovery removes the authorized suffix. ## Verification @@ -33,7 +33,7 @@ dropped by a local flush shortcut. env LINX_CHISEL_SBT_MEM_MB=4096 \ bash tools/chisel/run_chisel_tests.sh --only OooRobCompletionBuffer env LINX_CHISEL_SBT_MEM_MB=4096 \ - bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator + bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec ``` The focused UT covers three-producer same-cycle admission and ordered drain, diff --git a/docs/chisel/modules/ooo/OooPRename.md b/docs/chisel/modules/ooo/PRename.md similarity index 96% rename from docs/chisel/modules/ooo/OooPRename.md rename to docs/chisel/modules/ooo/PRename.md index 48a23a69..0bd304c4 100644 --- a/docs/chisel/modules/ooo/OooPRename.md +++ b/docs/chisel/modules/ooo/PRename.md @@ -1,8 +1,8 @@ -# OooPRename +# PRename ## Purpose -`OooPRename` is the absolute-index P-register rename +`PRename` is the absolute-index P-register rename owner. Each STID owns a 24-entry speculative map (SMAP), a 24-entry committed map (CMAP), and one logically ordered P MapQ. Prepare resolves sources and performs oldest-to-youngest same-bundle RAW/WAW forwarding without mutation. @@ -74,8 +74,8 @@ exact identity rules. ```bash bash tools/chisel/run_chisel_tests.sh --only OooParams -bash tools/chisel/run_chisel_tests.sh --only OooPRename -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator +bash tools/chisel/run_chisel_tests.sh --only RENUSpec +bash tools/chisel/run_chisel_tests.sh --only RENUAtomicSpec bash tools/chisel/build_chisel.sh ``` diff --git a/docs/chisel/modules/ooo/OooS1GroupedRob.md b/docs/chisel/modules/ooo/ROB.md similarity index 97% rename from docs/chisel/modules/ooo/OooS1GroupedRob.md rename to docs/chisel/modules/ooo/ROB.md index db440186..7e44ebee 100644 --- a/docs/chisel/modules/ooo/OooS1GroupedRob.md +++ b/docs/chisel/modules/ooo/ROB.md @@ -1,6 +1,6 @@ -# OooS1GroupedRob +# ROB -`OooS1GroupedRob` owns published grouped-ROB state, exact member completion, +`ROB` owns published grouped-ROB state, exact member completion, non-flush evidence, retained commit batches, and exact suffix recovery for all STIDs. @@ -93,7 +93,7 @@ commit-selection policy work. ## Verification -`OooS1GroupedRobSpec` covers: +`OOORobCommitSpec` covers: - atomic publication and retained ordered commit; - separate head-token and payload-read stages, stable retained output, and @@ -110,7 +110,7 @@ commit-selection policy work. then the odd subbank, followed by exact completion reads at RID slots 0 and 8. -`OooS1GroupedRobFaultSpec` separately covers exact runtime fault/cause +`OOORecoverySpec` separately covers exact runtime fault/cause retention at commit and killed-member fault/cause pruning in a surviving intra-group recovery pivot. diff --git a/docs/chisel/modules/ooo/OooFrontendRecoveryBridge.md b/docs/chisel/modules/ooo/RecoveryControl.md similarity index 79% rename from docs/chisel/modules/ooo/OooFrontendRecoveryBridge.md rename to docs/chisel/modules/ooo/RecoveryControl.md index bed1f259..1e80b0c9 100644 --- a/docs/chisel/modules/ooo/OooFrontendRecoveryBridge.md +++ b/docs/chisel/modules/ooo/RecoveryControl.md @@ -1,8 +1,8 @@ -# OooFrontendRecoveryBridge +# RecoveryControl ## Purpose -`OooFrontendRecoveryBridge` closes recovery R4 across the external CTU, exact +`RecoveryControl` closes recovery R4 across the external CTU, exact O3 physical transaction, and `LinxCoreIfu`. It does not derive a restart PC from ROB state. The recovery producer supplies one composite command containing the exact OOO suffix authority and matching full IFU redirect metadata. @@ -34,13 +34,13 @@ with `killTrigger`, or branch/non-branch cause disagrees with `BruRecovery` / ## CTU and stage integration `ctuPrepare` carries the complete `OooGlobalRecoveryRequest` to -`OooCtuIngressBridge`. `ctuPrepared` must echo that exact request and may report +`CTU`. `ctuPrepared` must echo that exact request and may report retained packet/claim/expansion state plus the active lease. No CTU state is mutated during this phase. `ctuApply` is asserted only with exact O3 common apply; `ctuAbort` is asserted only for the exact pre-apply O3 abort. A CTU prepare reject prevents O3 admission and reports `CtuRejected`. -`fence` connects to `OooIfuD1Ingress`, `OooD2Stage`, and every +`fence` connects to `OOOD1D2Stage`, `OooD2Stage`, and every retained D2/D3/S1 stage owner. `stageCancel` clears fusion history and the post-D1 retained stages only after O3 apply. `canonicalFlush` performs exact raw-reservoir pruning and epoch rebasing after IFU accepts the redirect. @@ -52,14 +52,12 @@ target payload remains resident for abort recovery or later apply-time clear. ## Verification ```bash -bash tools/chisel/run_chisel_tests.sh --only OooFrontendRecoveryBridge -bash tools/chisel/run_chisel_tests.sh --only OooFrontendIfuRecoveryIntegration -bash tools/chisel/run_chisel_tests.sh --only OooFrontendCtuRecoveryIntegration -bash tools/chisel/run_chisel_tests.sh --only OooCtuIngressBridge -bash tools/chisel/run_chisel_tests.sh --only OooIfuRawIngress +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +bash tools/chisel/run_chisel_tests.sh --only CTUOOOIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only CTUSpec +bash tools/chisel/run_chisel_tests.sh --only OOODecodeSpec bash tools/chisel/run_chisel_tests.sh --only OooD2Stage bash tools/chisel/run_chisel_tests.sh --only OooThreadStageBuffer -bash tools/chisel/run_chisel_tests.sh --only OooO3RenameCoordinator ``` The tests cover retained request/redirect backpressure, both R4 terminal diff --git a/docs/chisel/modules/recovery/RecoveryBackendControl.md b/docs/chisel/modules/recovery/RecoveryBackendControl.md index 8e9d8f9c..9e8a57a4 100644 --- a/docs/chisel/modules/recovery/RecoveryBackendControl.md +++ b/docs/chisel/modules/recovery/RecoveryBackendControl.md @@ -85,9 +85,11 @@ owner can provide the authoritative full BID for the incremented cleanup BID. - `bash tools/chisel/run_chisel_tests.sh --only RecoveryBackendControlSpec` - `bash tools/chisel/run_chisel_recovery_cleanup_rob_probe.sh` - `bash tools/chisel/run_chisel_scalar_redirect_recovery_source_probe.sh` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 49102fa1f0a34eb9a548dfcb7fa6c9556a1a017f. -The focused test proves composition and handshake-qualified ROB publication. -The generated real-ROB probe proves exact lookup, blocked-intent stability, and -resident-row pruning. The full fetch/RF/ALU cross-check protects commit -behavior through the integrated backend boundary. +The active focused test proves composition and handshake-qualified ROB +publication. The active generated real-ROB probe proves exact lookup, +blocked-intent stability, and resident-row pruning. At the cited source commit, +the now-removed full fetch/RF/ALU cross-check historically protected commit +behavior through the integrated backend boundary; it has no current runnable +equivalent. diff --git a/docs/chisel/modules/recovery/RecoverySourceArbiter.md b/docs/chisel/modules/recovery/RecoverySourceArbiter.md index 13107836..89e08e9b 100644 --- a/docs/chisel/modules/recovery/RecoverySourceArbiter.md +++ b/docs/chisel/modules/recovery/RecoverySourceArbiter.md @@ -105,7 +105,7 @@ production backend-top wiring remain open. - `bash tools/chisel/run_chisel_tests.sh --only RecoveryCleanupROBProbeSpec` - `bash tools/chisel/run_chisel_recovery_cleanup_rob_probe.sh` - `bash tools/chisel/run_chisel_tests.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` R639 passes 251 suites and 1,482 tests. The generated probe passes exact lookup, same-STID oldest selection, consume-and-replace, invalid-STID rejection, and diff --git a/docs/chisel/modules/recovery/ScalarRedirectRecoverySource.md b/docs/chisel/modules/recovery/ScalarRedirectRecoverySource.md index 02219e86..db446ad0 100644 --- a/docs/chisel/modules/recovery/ScalarRedirectRecoverySource.md +++ b/docs/chisel/modules/recovery/ScalarRedirectRecoverySource.md @@ -58,10 +58,11 @@ transport does not derive memory-order width from ring identity. - `bash tools/chisel/run_chisel_tests.sh --only ScalarRedirectRecoverySourceSpec` - `bash tools/chisel/run_chisel_scalar_redirect_recovery_source_probe.sh` - `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTopSpec` -- `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 49102fa1f0a34eb9a548dfcb7fa6c9556a1a017f. -The generated-RTL probe proves cycle-level publish-once retention, +The active generated-RTL probe proves cycle-level publish-once retention, missing-identity and invalid-RID blocking, backpressure, consume-and-replace, cancellation priority, same-cycle publication suppression, and sidecar -retention. The integrated tests and cross-check prove unchanged architectural -commit behavior. +retention. The active integrated tests prove unchanged architectural commit +behavior. At the cited source commit, the removed cross-check historically +provided additional commit evidence; it has no current runnable equivalent. diff --git a/docs/chisel/modules/rename/StoreSplitPayload.md b/docs/chisel/modules/rename/StoreSplitPayload.md index c6a63b79..1640007c 100644 --- a/docs/chisel/modules/rename/StoreSplitPayload.md +++ b/docs/chisel/modules/rename/StoreSplitPayload.md @@ -164,7 +164,7 @@ bash tools/chisel/run_chisel_tests.sh --only DecodeLoadStoreIdAssign bash tools/chisel/run_chisel_tests.sh --only ScalarDecodeRenameBridge bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob -bash tools/chisel/run_chisel_top_xcheck.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run ``` diff --git a/docs/chisel/modules/rob/ROBRowCommitTraceLookup.md b/docs/chisel/modules/rob/ROBRowCommitTraceLookup.md index 24cbebd1..7e41c81d 100644 --- a/docs/chisel/modules/rob/ROBRowCommitTraceLookup.md +++ b/docs/chisel/modules/rob/ROBRowCommitTraceLookup.md @@ -119,6 +119,9 @@ the incomplete W2 side-effect stage. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only ROBRowCommitTraceLookup bash tools/chisel/run_chisel_tests.sh --only ROBEntryBank @@ -128,6 +131,8 @@ bash tools/chisel/run_chisel_tests.sh --only LoadReplayReturnPipeW2CommitRowTrac bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r373x bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 401f95d23c9c6c2bd498fcc31bf9d3bad8fe0aee. + Reference tests cover live matched-row metadata, disabled source trace, invalid RID, free slot, stale RID, NeedFlush suppression, missing instruction diff --git a/docs/chisel/modules/rob/ROBRowStatusLookup.md b/docs/chisel/modules/rob/ROBRowStatusLookup.md index 2c970566..9dcd933f 100644 --- a/docs/chisel/modules/rob/ROBRowStatusLookup.md +++ b/docs/chisel/modules/rob/ROBRowStatusLookup.md @@ -111,6 +111,9 @@ owner is W2 atomic request/evidence production, not row-status lookup. Focused gates: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_tests.sh --only ROBRowStatusLookup bash tools/chisel/run_chisel_tests.sh --only ROBEntryBank @@ -119,6 +122,8 @@ bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendFetchRfAluTraceTop FETCH_REDUCED_STORE_REPLAY_LIQ=1 BUILD_DIR=generated/r321-replay-rob-row-status-xcheck bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit 8872275941ea309bfb99a8ab57254403013ba462. + Reference tests cover matching non-free rows, `NeedFlush` rows, invalid RID blocking, free-slot blocking, stale RID blocking, and Chisel elaboration. diff --git a/docs/chisel/modules/rob/ReducedCommitROB.md b/docs/chisel/modules/rob/ReducedCommitROB.md index 27247406..35899c8d 100644 --- a/docs/chisel/modules/rob/ReducedCommitROB.md +++ b/docs/chisel/modules/rob/ReducedCommitROB.md @@ -131,19 +131,21 @@ single-row retire window, and the post-drain idle window. The smoke deliberately writes one invalid fixed-width output slot; the adapter must filter it before comparison. -The same C++ harness also has an `--input-trace` mode used by -`run_chisel_trace_replay_xcheck.sh`. In that mode it loads bounded normalized -commit rows, allocates and completes one row at a time through the top shell, -writes DUT JSONL from the Chisel commit port, and writes a matching -QEMU-shaped reference stream for the comparator. This is cross-check -infrastructure; it does not replace the future live ROB/CMT execution path. +At the cited source commit, the same C++ harness had an `--input-trace` mode +used by historical evidence only (no current runnable equivalent): `run_chisel_trace_replay_xcheck.sh` Provenance: source commit ed70d74d700d5c4bcd20dc3ce768b23329d8deea. . +In that mode it loaded bounded normalized commit rows, allocated and completed +one row at a time through the top shell, +wrote DUT JSONL from the Chisel commit port, and wrote a matching QEMU-shaped +reference stream for the comparator. That was historical cross-check +infrastructure; it did not replace the live ROB/CMT execution path, and the +removed wrapper has no current runnable equivalent. ## Verification - `bash tools/chisel/run_chisel_tests.sh --only ReducedCommitROB` - `bash tools/chisel/run_chisel_rob_bookkeeping.sh --reduced-rob` - `bash tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `bash tools/chisel/run_chisel_trace_replay_xcheck.sh` +- historical evidence only (no current runnable equivalent): `bash tools/chisel/run_chisel_trace_replay_xcheck.sh` Provenance: source commit ed70d74d700d5c4bcd20dc3ce768b23329d8deea. - `bash tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` - `python3 tools/chisel/trace_schema_adapter.py --self-test` diff --git a/docs/chisel/modules/top/LinxCoreFrontendAluTraceTop.md b/docs/chisel/modules/top/LinxCoreFrontendAluTraceTop.md deleted file mode 100644 index ed0ffb2c..00000000 --- a/docs/chisel/modules/top/LinxCoreFrontendAluTraceTop.md +++ /dev/null @@ -1,129 +0,0 @@ -# LinxCoreFrontendAluTraceTop - -> **Architecture status — reduced verification top.** This wrapper records the -> current migration fixture and does not define production IFU stages. -> Production uses decoupled I-F0–I-F4/B-F0–B-F4, an independent -> Instruction Buffer, and four-wide 64-bit D1. - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendAluTraceTop.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/top/LinxCoreFrontendAluTraceTopSpec.scala` -- Verilator driver: `rtl/LinxCore/tools/chisel/frontend_alu_trace_top_tb.cpp` -- Gate: `rtl/LinxCore/tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- Child owners: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/frontend/F4DecodeWindow.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/backend/DecodeRenameROBPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/bctrl/spe/SPERename.cpp` - - `model/LinxCoreModel/model/iex/pipe/alu_pipe.cpp` - - `model/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp` - - `model/LinxCoreModel/isa/calculate/arithmetic/Arithmetic.cpp` - - `model/LinxCoreModel/isa/calculate/others/Others.cpp` -- Contract IDs: `LC-IF-CHISEL-TOP-003`, `LC-IF-CHISEL-XCHK-006` - -## Purpose - -`LinxCoreFrontendAluTraceTop` is the R81 successor to the R80 frontend trace -top. It drives raw frontend packets through the legacy window-decode fixture, -decode/rename, -BROB/ROB reservation, post-rename row update, and a reduced scalar ALU execute -owner before committing rows through the monitored ROB path. - -This wrapper removes the external completion surrogate for the scalar -`ADD`/`ADDI`/compressed move smoke. It still is not a bootable core because -fetch, issue, register-file reads, LSU, traps, recovery, and memory are not -live behind this top. - -R82 adds `LinxCoreFrontendRfAluTraceTop` as the RF-backed successor. Keep this -R81 top and gate as the regression for the temporary `operandData` path, but do -not extend it with more per-uop operand fixture inputs. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `in` | `FrontendDecodePacket` | `in.valid` | Host/testbench supplied 8-byte frontend window, PC, PE/STID, packet UID, and checkpoint ID. | -| input | `operandData` | `Vec(3, UInt(64.W))` by default | held until `executeAccepted` | Reduced source values for the selected renamed uop. | -| input | `frontendFlushValid` | `Bool` | valid | Flushes F4/decode queue state in this reduced top. | -| input | `deallocReady` | `Bool` | ready | Allows retired rows to deallocate through the integrated ROB/T-U retire path. | -| output | `f4ValidMask`, `f4SlotCount` | mixed | combinational | F4 slot-valid shape for the input window. | -| output | `decodeReady` | `Bool` | ready | Wrapped decode/rename/ROB path can accept the next frontend packet. | -| output | `selectedValid`, `selectedRobValue`, `selectedBlockBid` | mixed | diagnostic | First valid decoded slot and allocator identities. | -| output | `decRenPushFire`, `decRenPopFire`, `decRenCount` | mixed | diagnostic | Decode-to-rename queue events and occupancy. | -| output | `renamedOutValid`, `renamedAccepted` | `Bool` | diagnostic | Rename output visibility from `DecodeRenameROBPath`. | -| output | `executeAccepted`, `executeBusy` | `Bool` | diagnostic | Reduced scalar ALU capture and occupancy. | -| output | `executeCompleteValid`, `executeCompleteRobValue` | mixed | diagnostic | ALU completion pulse and target ROB row. | -| output | `executeUnsupported`, `executeUnsupportedOpcode` | mixed | diagnostic | Reduced ALU unsupported-opcode pulse. | -| output | `robAllocFire`, `robRenameUpdateFire` | `Bool` | pulse | BROB/ROB reservation and post-rename row update pulses. | -| output | `completeAccepted`, `completeIgnored` | `Bool` | pulse | ROB completion result from ALU-produced completion. | -| output | `commit.rows` | `Vec(commitWidth, CommitTraceRow)` | row `valid` | Monitored commit rows, now including ALU-produced source, destination, and writeback data for the reduced opcode subset. | -| output | `commit*`, `dealloc*`, `*Mask`, `idle` | mixed | diagnostic | Commit monitor, ROB lifecycle, and occupancy observability inherited from `DecodeRenameROBPath`. | - -## State - -The wrapper owns no architectural state. State lives in child owners: - -- `F4DecodeWindow`: combinational frontend-window slicing. -- `DecodeRenameROBPath`: decode-to-rename queue, scalar/T-U rename, BROB/ROB, - commit, and deallocation. -- `ReducedScalarAluExecute`: reduced E/W1/W2 scalar ALU pipe. - -## Logic Design - -The wrapper is identical to `LinxCoreFrontendTraceTop` up to the rename output, -then connects `path.io.renamedOutValid/renamedOut` to -`ReducedScalarAluExecute`. `path.io.renamedOutReady` is driven by the ALU -input readiness. The ALU completion outputs drive -`path.io.completeValid`, `path.io.completeRobValue`, -`path.io.completeRowValid`, and `path.io.completeRow`. - -`operandData` is an explicit bring-up input. Verilator drivers must hold it -stable until `executeAccepted` because the ALU captures source values at the -rename-to-execute handoff. `LinxCoreFrontendRfAluTraceTop` is the replacement -boundary for persistent RF-sourced operands; future packets should extend that -RF/issue lane rather than adding more top-level operand fixtures here. - -## Model Alignment - -`SPERename::InsertToSIEXQ` sends arithmetic, immediate, and move instructions -to the scalar ALU IEX queue. `ALUPipe` resolves the instruction in its execute -pipe and publishes a resolve bus at W2. The wrapper mirrors that ordering at -the reduced top boundary: decode/rename allocates and patches the ROB row -first, ALU completion later marks the same ROB row complete with result data, -and the ROB commit head emits the architectural trace row. - -## Timing - -One frontend packet can be accepted when `decodeReady` is high. The selected -uop later leaves the decode-to-rename queue when the reduced ALU is ready. -ALU completion arrives from W2 and the ROB can commit the completed row on a -later cycle if it is at the commit head. - -## Flush/Recovery - -Only the frontend flush input is live. Backend cleanup, checkpoint restore, -ROB prune, LSU cleanup, precise traps, and redirect restart remain tied off in -this wrapper. - -## Trace/Observability - -`tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` emits the top, -builds the shared Verilator harness in the default operand-fixture mode, drives -three frontend packets (`ADD`, `ADDI`, and compressed `MOVR`), supplies operand -data, waits for ALU completion, dumps DUT commit JSONL, and compares it against -QEMU-shaped rows with nonzero source, destination, and writeback data. - -The current gate is a reduced generated-RTL proof, not a full QEMU boot -comparison. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendAluTraceTop` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute` -- `bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` -- `python3 tools/chisel/trace_schema_adapter.py --self-test` -- `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` diff --git a/docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md b/docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md deleted file mode 100644 index acea8fab..00000000 --- a/docs/chisel/modules/top/LinxCoreFrontendFetchRfAluTraceTop.md +++ /dev/null @@ -1,243 +0,0 @@ -# LinxCoreFrontendFetchRfAluTraceTop - -> **Architecture status — reduced verification top.** Its fetch source, -> window slicer, dense-slot queue, and reduced BFU helpers are migration -> fixtures only. They do not define I-F0–I-F4, B-F0–B-F4, Instruction Buffer, -> or D1 production ownership. - -## Status - -- Package: `linxcore.top` -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTop.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/top/LinxCoreFrontendFetchRfAluTraceTopSpec.scala` -- Generated RTL gate: `rtl/LinxCore/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- CoreMark replay gate: `rtl/LinxCore/tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh` -- Architecture source of truth: `rtl/LinxCore/docs/architecture/microarchitecture.md` - -This top is the live scalar Chisel integration harness. It connects fetch, -decode, rename, ROB/BROB, issue, RF, scalar execute, reduced store execution, -LIQ replay, MDB recovery, load-return queues, W1/W2 completion, and commit -trace publication. It is not a second architecture definition; this page -describes how the golden contracts are composed in the current RTL. - -## Configuration - -The top is parameterized by `CoreParams`, interface widths, and local queue -depths. Important independent capacities include: - -| Parameter | Owner | -| --- | --- | -| `robEntries`, `commitWidth` | ROB and architectural commit. | -| `decRenQueueDepth`, `issueQueueDepth` | Scalar frontend/backend buffering. | -| `ScalarBackendParams.scalarIssueBanks` | Equal resident scalar issue banks in the live ALU slice. | -| `ScalarBackendParams.gprReadPorts` | Physical scalar RF read ports; at least one atomic three-source group. | -| `storeDispatchQueueDepth`, `storeExecBufferEntries` | Split STA/STD execution. | -| `ScalarLsuParams.stqEntries` | Speculative store rows. | -| `ScalarLsuParams.liqEntries` | Active scalar load rows. | -| `ScalarLsuParams.mdb*Entries` | Predictor, fanout, wait-plan, and recovery queues. | -| `ScalarLsuParams.loadReturnQueueEntries` | Entries in each STID/return-pipe LRET lane. | -| `ScalarLsuParams.loadReturnPipeCount` | Scalar IEX return pipes. The current reduced W1/W2 integration exposes one shared pipe. | -| `scalarStidCount` | Independent scalar STID lanes. | - -Queue capacities do not define BID/GID/RID/LSID widths. The current reduced -W1/W2 integration requires `loadReturnPipeCount == 1`; the queue bank itself -supports multiple pipes and preserves the parameter for the later W1/W2 -widening packet. - -## Ownership Graph - -```text -FrontendFetchPacketSource - -> F4DecodeWindow / F4DenseSlotQueue - -> DecodeRenameROBPath - -> GPR/T/U rename, ROB/BROB, recovery fabric - -> split STA/STD dispatch - -> ScalarIssueFabric - -> ReducedScalarIssueQueue banks - -> shared I1/I2 candidate arbiters - -> ScalarGPRFile - -> ReducedScalarAluExecute - -> scalar completion / redirect - -> live load request - -Store side: - STA/STD -> StoreDispatchSTQPath -> STQ -> commit queue -> SCB - | | - +-> ScalarLSUMDBPath - -Load side: - load request -> ReducedLoadReplayLiqAllocPath - -> forwarding / source-return / MDB mutation - -> return extraction and publication - -> ScalarLSULoadReturnQueueBank - -> IEX E4 -> W1 -> W2 - -> ROB resolve + RF writeback + issue wakeup + LIQ clear -``` - -The reduced timing modules are implementation adapters. They do not redefine -Linx memory ordering, block recovery, or architectural state. - -## Frontend and Backend - -- Fetch requests and responses are retained through explicit ready/valid - boundaries. -- Dense decode slots enter one rename/ROB allocation boundary. A row cannot - become visible to issue unless its rename, ROB, and required block metadata - allocations are all accepted. -- GPR rename uses SMAP/CMAP/MapQ state. T/U local links use the local queue and - relation-map contract. -- Issue observes registered ready state. A committed `ScalarGPRFile.write.fire` - updates P readiness and matching resident IQ next state together; wakeup in - a cycle becomes eligible for selection on the next cycle. T/U stays scoped. -- Scalar rows route to the least-occupied resident bank. Each bank and each - shared boundary choose the oldest candidate only within a matching STID and - use round-robin service across STIDs. I1 denial cancels only the attempt; - residency and source readiness remain for retry. -- ROB completion from execute and W2 load return shares an explicit arbiter; - execute priority cannot cause the W2 row to clear before its completion is - accepted. - -## Store Path - -- STA and STD reserve one shared store identity at dispatch and may complete - independently. -- Address-bearing STQ insertion is admitted only when the canonical MDB owner - can consume the probe or a finite replay adapter has credit. -- Data-only STD completion bypasses address-side MDB backpressure. -- The actual accepted STQ fragment type qualifies MDB commit. Pre-permit - intent is used only to compute readiness and cannot create a side effect. -- STQ rows become SCB-visible only after ROB commit and the strong per-STID - non-flush prefix authorize the exact full block BID. -- SCB completion and response ownership remain separate from request issue. - -## Load and MDB Path - -- A scalar load allocation and its PC-keyed MDB lookup are accepted atomically. -- LIQ rows retain PE/STID/TID, BID/GID/RID/load-LSID, destination, store - snapshot, line data, and replay state. -- Store forwarding is byte-selective. A missing byte from the youngest - eligible older store blocks rather than falling through to stale data. -- `ScalarLSUMDBPath` owns lookup, SSIT state, conflict detection, multi-row - wait plans, failed-wait decay/delete, store wakeup, and retained recovery. -- Source-return and MDB mutations share one native row-mutation arbiter with - source-specific qualification. -- MDB recovery enters the central backend fabric only after report-STID - watermark selection and exact resident full-BID lookup. - -## Load-Return Pipeline - -### Publication - -Returned line data passes source readiness, consumer readiness, return-pipe -budget, pipe permit/select, byte extraction, and publish control. Publication -is atomic with enqueue into `ScalarLSULoadReturnQueueBank`. - -The queue-bank admission split is deliberate: - -1. STID-local `preEnqueueReady` participates in consumer readiness before a - return pipe is selected. -2. Final `enqueueReady` validates the selected STID/pipe lane. -3. An assertion requires every live published return to be accepted. - -This prevents a cycle from queue readiness through return-pipe selection back -to queue readiness. - -### Retention and Recovery - -- Each STID/pipe lane is an independent FIFO sized by - `loadReturnQueueEntries`. -- Shared IEX drain uses round-robin arbitration across nonempty lanes. -- An empty queue does not bypass combinationally to IEX. -- Start, restart, and frontend hard reset clear all lanes. -- Accepted typed backend recovery selectively prunes matching PE/STID/TID and - BID/GID/LSID entries while preserving older and independent entries. -- Queue-head validity, ROB row status, and E4 residency are checked before - drain. - -### E4, W1, and W2 - -- IEX drains only when the residency stage can retain the payload. -- E4 and W1 are registered storage boundaries. -- W2 forms resolve, writeback, and wakeup requests from one resident entry. -- Required sinks must all be ready before the side-effect vector fires. -- ROB completion, commit-row data, RF writeback, issue wakeup, and exact LIQ - lifecycle clear correspond to the same W2 transaction. -- A held W2 entry remains stable under execute writeback or completion-port - contention. - -## Recovery - -Recovery producers are independently retained. The central fabric arbitrates -BCC, IEX, PE, scalar redirect, and LSU sources, resolves full block identity, -and publishes one consumed cleanup intent. - -The top applies that accepted intent consistently to: - -- ROB and BROB pruning; -- rename checkpoint cleanup; -- issue and execution stages; -- speculative STQ and LIQ state; -- MDB report and probe retention; -- scoped LRET queue pruning; -- frontend restart selection. - -No local LSU or return-pipe helper may independently choose a different flush. - -## Commit and Trace - -- Commit rows come from the resident ROB, not reconstructed execute payloads. -- Load W2 completion may supply returned destination data and source metadata - to the same commit-row owner used by ordinary scalar completion. -- Marker filtering and block termination preserve Linx BSTART/BSTOP semantics. -- The generated trace is normalized and compared against QEMU. CoreMark replay - is a no-regression gate; it does not by itself prove activation of every - recovery or contention path. - -## Required Invariants - -1. Rename, ROB, BROB, and issue admission agree on every accepted row. -2. LIQ allocation and MDB lookup acceptance are equal. -3. Every accepted address-bearing store enters canonical MDB processing. -4. Every published load return enters exactly one scoped LRET queue. -5. A queue entry is removed only by accepted IEX drain, typed recovery prune, - or hard reset/restart. -6. W2 clears only after all required physical side effects are accepted. -7. RID selects the ROB row; STID selects the scalar lane; BID/GID/LSID retain - ordering and recovery meaning. -8. No ARM exception level, condition flag, exclusive monitor, barrier - encoding, or acquire/release policy is imported into Linx behavior. - -## Verification - -The normal packet gate includes: - -```bash -cd rtl/LinxCore/chisel -sbt --server --batch --no-colors --mem 4096 'testOnly *' - -cd rtl/LinxCore -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh -bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh \ - --qemu-trace \ - --build-dir generated/-coremark \ - --max-commits 426 --replay-rows 14656 -``` - -Focused R661 coverage includes `ScalarLSULoadReturnQueueSpec`, -`LoadReplayReturnLretPayloadSpec`, and -`LinxCoreFrontendFetchRfAluTraceTopSpec`. - -## Remaining Work - -- Move the live return queue and E4/W1/W2 boundary beneath the complete - `ScalarLSU` hierarchy instead of the reduced integration top. -- Widen the live W1/W2 datapath beyond one return pipe while preserving - per-pipe queue credit and atomic side effects. -- Integrate cache, miss queue, refill, cross-line merge, and memory-response - ownership under the same typed recovery boundary. -- Connect natural BCC/IEX/PE trigger generation and workloads that activate - sustained recovery and contention paths. -- Replace residual historical diagnostic names in RTL interfaces as their - corresponding owners become canonical; git history remains the archive. -- Add the remaining BRU/AGU/STD/CMD physical queue classes, two-write-port - S1/S2 dispatch, and wider issue/execution grants around this scalar ALU slice. diff --git a/docs/chisel/modules/top/LinxCoreFrontendRfAluTraceTop.md b/docs/chisel/modules/top/LinxCoreFrontendRfAluTraceTop.md deleted file mode 100644 index 12b946e1..00000000 --- a/docs/chisel/modules/top/LinxCoreFrontendRfAluTraceTop.md +++ /dev/null @@ -1,239 +0,0 @@ -# LinxCoreFrontendRfAluTraceTop - -> **Architecture status — reduced verification top.** Packet-window inputs -> and any `F4*` signal names describe the current fixture, not architectural -> I-F4. Production I-F4 is I-SIDE stage 4 and is followed by an independent -> Instruction Buffer. - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreFrontendRfAluTraceTop.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/top/LinxCoreFrontendRfAluTraceTopSpec.scala` -- Verilator driver: `rtl/LinxCore/tools/chisel/frontend_alu_trace_top_tb.cpp` -- Gate: `rtl/LinxCore/tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- Child owners: - - `rtl/LinxCore/chisel/src/main/scala/linxcore/frontend/F4DecodeWindow.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/backend/DecodeRenameROBPath.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ScalarIssueFabric.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ScalarIssueCandidateArbiter.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssueQueue.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarIssuePick.scala` - - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ReducedScalarAluExecute.scala` -- LinxCoreModel evidence: - - `model/LinxCoreModel/model/bctrl/spe/GPRRename.cpp` - - `model/LinxCoreModel/model/iex/rtable.cpp` - - `model/LinxCoreModel/model/iex/iex_rf.cpp` - - `model/LinxCoreModel/model/iex/iex_iq.cpp` - - `model/LinxCoreModel/model/iex/iex_dispatch.cpp` - - `model/LinxCoreModel/model/iex/pipe/alu_pipe.cpp` - - `model/LinxCoreModel/model/ModelCommon/SimInstInfo.cpp` -- Contract IDs: `LC-IF-CHISEL-TOP-004`, `LC-IF-CHISEL-XCHK-008` - -## Purpose - -`LinxCoreFrontendRfAluTraceTop` is the R83 RF-backed successor to -`LinxCoreFrontendAluTraceTop`. It drives raw frontend packets through the -legacy window-decode fixture, -decode/rename, ROB allocation/update, the canonical scalar physical RF, a -parameterized scalar issue-bank fabric, and the reduced scalar ALU execute pipe, then commits -through the monitored ROB path. - -The top removes the R81 `operandData` per-uop fixture. Testbench preloads only -architectural identity registers, and later source values must come from -Chisel RF writeback state keyed by renamed physical tags. Unlike R82, rename -output no longer feeds execute directly: rows enqueue into -`ScalarIssueFabric` and issue only when a bank-selected row's RF source tags -are ready. Issued rows remain resident in the queue until -`ReducedScalarAluExecute` reaches W2 and returns the row's release identity. - -R85 routes the RF ready mask into the issue queue so source readiness is -registered per resident entry instead of using same-cycle RF `readReady` to -pick a row. - -R86 lets the reduced issue queue pick the oldest resident ready non-issued row, -so an issued or not-ready head no longer forces all younger ready rows to wait. - -R87 keeps the top-level dataflow stable while exposing the new issue-pick -read-confirm boundary: the issue queue's child picker selects the ready row, -drives RF read tags, and blocks issue when selected-row RF readiness is not -confirmed. - -R88 exposes the reduced P1/I1/I2 timing split: P1 pick locks a queue row, I1 -drives RF read tags and may cancel the lock if RF readiness is not confirmed, -and I2 presents the captured row/data to execute. - -R667 replaces the single live queue with `ScalarIssueFabric`. Total capacity -is split across `ScalarBackendParams.scalarIssueBanks`; enqueue chooses the -least-occupied bank, each bank forms oldest-per-STID candidates, and shared I1 -and I2 arbiters use same-STID RID age plus cross-STID round-robin fairness. -I1 denial clears only the losing bank's `inflight` attempt and leaves its row -resident for retry. - -R111 adds local T/U source ports to `ReducedScalarIssueQueue` for the live -fetch CoreMark path. This older packet-fixture top remains scalar-P only and -ties those local readiness masks empty; T/U local source execution is owned by -`LinxCoreFrontendFetchRfAluTraceTop`. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `in` | `FrontendDecodePacket` | `in.valid` | Host/testbench supplied frontend window, PC, PE/STID, packet UID, and checkpoint ID. | -| input | `rfInitValid` | `Bool` | pulse | Preload one identity-mapped architectural scalar GPR. | -| input | `rfInitArchTag` | `UInt(archRegWidth.W)` | with `rfInitValid` | Architectural GPR tag for reduced initialization. | -| input | `rfInitData` | `UInt(64.W)` by default | with `rfInitValid` | Initial scalar GPR data. | -| input | `frontendFlushValid` | `Bool` | valid | Flushes F4/decode queue state in this reduced top. | -| input | `deallocReady` | `Bool` | ready | Allows retired rows to deallocate through the integrated ROB/T-U retire path. | -| output | `f4ValidMask`, `f4SlotCount` | mixed | combinational | F4 slot-valid shape for the input window. | -| output | `decodeReady` | `Bool` | ready | Wrapped decode/rename/ROB path can accept the next frontend packet. | -| output | `selectedValid`, `selectedRobValue`, `selectedBlockBid` | mixed | diagnostic | First valid decoded slot and allocator identities. | -| output | `decRenPushFire`, `decRenPopFire`, `decRenCount` | mixed | diagnostic | Decode-to-rename queue events and occupancy. | -| output | `renamedOutValid`, `renamedAccepted` | `Bool` | diagnostic | Rename output visibility from `DecodeRenameROBPath`. | -| output | `executeAccepted`, `executeBusy` | `Bool` | diagnostic | Reduced scalar ALU capture and occupancy. | -| output | `executeCompleteValid`, `executeCompleteRobValue` | mixed | diagnostic | ALU completion pulse and target ROB row. | -| output | `executeUnsupported`, `executeUnsupportedOpcode` | mixed | diagnostic | Reduced ALU unsupported-opcode pulse. | -| output | `rfReadReadyMask`, `rfAllReadReady`, `rfReadyMask` | mixed | diagnostic | Reduced physical RF readiness observability. | -| output | `rfWriteValid`, `rfWriteTag`, `rfWriteData` | mixed | diagnostic | Execute-to-RF physical writeback event. | -| output | `rfStateError` | `Bool` | diagnostic | Out-of-range RF init/clear/write attempt. | -| output | `issueQueueEnqueueFire`, `issueQueuePickFire`, `issueQueueIssueFire`, `issueQueueCancelFire`, `issueQueueReleaseFire` | `Bool` | pulse | Reduced issue queue admission, P1 lock, I2 execute issue, I1 cancel, and release events. | -| output | `issueQueueCount`, `issueQueueIssuedCount`, `issueQueueNotIssuedCount` | mixed | diagnostic | Reduced issue queue resident, in-flight, and selectable occupancy. | -| output | `issueQueueHeadValid`, `issueQueueHeadIssued` | mixed | diagnostic | Reduced issue queue head-valid and head-issued state. | -| output | `issueQueueSourceReadyMask` | `UInt(3.W)` | diagnostic | Registered source-ready bits for the current issue-queue head. | -| output | `issueQueueAllSourcesReady` | `Bool` | diagnostic | Queue-head source readiness after invalid-lane masking. | -| output | `issueQueueSelectedValid`, `issueQueueSelectedIndex`, `issueQueueSelectedReadReady` | mixed | diagnostic | Oldest ready non-issued P1 candidate and current I1/P1 RF read readiness. | -| output | `issueQueueI1Valid`, `issueQueueI2Valid`, `issueQueueStageBusy` | `Bool` | diagnostic | Reduced issue-owner stage occupancy. | -| output | `issueQueueBlockedBySource`, `issueQueueBlockedByRead`, `issueQueueBlockedByOutput`, `issueQueueBlockedByIssued` | `Bool` | diagnostic | Queue blocked by source readiness, selected-row RF read readiness, execute backpressure, or issued-head residency with no selectable younger row. | -| output | `issueQueueBankOccupancy`, `issueQueueBank*Mask` | mixed | diagnostic | Per-bank residency, pick, I1 attempt/grant, and I2 valid/grant state. | -| output | `issueQueueSimultaneousPick`, `issueQueueReadContention`, `issueQueueReadArbitrationLoss`, `issueQueueIssueContention` | `Bool` | diagnostic | Live bank overlap, I1 denial, and I2 contention evidence. | -| output | `robAllocFire`, `robRenameUpdateFire` | `Bool` | pulse | BROB/ROB reservation and post-rename row update pulses. | -| output | `completeAccepted`, `completeIgnored` | `Bool` | pulse | ROB completion result from ALU-produced completion. | -| output | `commit.rows` | `Vec(commitWidth, CommitTraceRow)` | row `valid` | Monitored commit rows including RF-sourced source values and ALU writeback data. | -| output | `commit*`, `dealloc*`, `*Mask`, `idle` | mixed | diagnostic | Commit monitor, ROB lifecycle, and occupancy observability inherited from `DecodeRenameROBPath`. | - -## State - -The wrapper owns no state directly. State lives in child owners: - -- `F4DecodeWindow`: combinational frontend-window slicing. -- `DecodeRenameROBPath`: decode-to-rename queue, scalar/T-U rename, BROB/ROB, - commit, and deallocation. -- `ScalarGPRFile`: canonical physical scalar GPR data and P-ready bits. -- `ScalarIssueFabric`: least-occupied dispatch plus shared I1/I2 arbitration. -- `ReducedScalarIssueQueue`: one resident bank's source-ready, inflight, - release, and compaction state. -- `ReducedScalarIssuePick`: P1 selected-row lock, I1 RF-read/cancel, I2 - execute handoff, and issue-block owner. -- `ReducedScalarAluExecute`: reduced E/W1/W2 scalar ALU pipe. - -## Logic Design - -`DecodeRenameROBPath` emits a single accepted `RenamedUop` into -`ScalarIssueFabric`. The selected child bank owns the resident source-readiness -boundary: -`path.io.renamedOutReady` is driven by queue capacity, while the selected -oldest-per-STID issue row is chosen by `ReducedScalarIssuePick`. The parent -fabric arbitrates simultaneous bank I1 attempts atomically, routes the granted -bank to `ScalarGPRFile`, and clears a denied bank's lock for retry. A separate -arbiter selects among resident bank I2 outputs. -The RF `readyMask` feeds the queue's registered resident source-ready bits. -Invalid source lanes are treated as ready inside the picker. -The local T/U ready-mask inputs are tied to zero in this top, so any T/U source -row remains unsupported here rather than reading scalar RF aliases. - -When a row enqueues with a scalar destination, the top clears the destination -physical tag readiness in the RF through `issue.enqueueDst*`. When any resident -non-issued row has all valid sources ready and execute is ready, the oldest -ready row's `issue.issue*` drives `ReducedScalarAluExecute`. When execute completes, -`completeDstPhysValid/Tag/Data` commit the destination physical tag and mark it -ready. The same `write.fire` event broadcasts the P tag into the issue queue, -so matching resident sources update with the ready table and become -pick-visible on the next cycle. Independently, the ALU W2 -`releaseValid/Bid/Rid/Stid` payload returns to the issue queue so the issued -entry can be removed and younger FIFO rows can become the head. - -This removes the R82 accepted-output readiness loop. `rfAllReadReady` remains a -top diagnostic, but readiness that affects execution now flows from the RF into -the issue queue's registered resident source-ready state rather than back into -rename acceptance. - -## Model Alignment - -`GPRRename::Build` initializes architectural scalar GPR tags as identity -physical tags and leaves higher physical tags free. `GPRRename::RenameSrc` -maps scalar sources through the speculative map, while `RenameDst` allocates a -new physical destination tag. `ReadyState::GetSrcData` and the RF read path -populate source operand data from the physical tag state, and the ALU pipe -publishes result data at W2. - -The RF-backed top mirrors this reduced ordering: - -1. preload identity physical tags for architectural fixture inputs; -2. decode/rename maps sources and allocates a physical destination; -3. the renamed row enters a reduced issue queue; -4. the issue queue samples the RF ready mask and committed P-wakeup events into resident source-ready bits; -5. the issue-pick owner locks the selected row in P1; -6. I1 reads RF data for the selected physical source tags and cancels only the - in-flight lock if readiness is not confirmed; -7. I2 presents the read-confirmed row/data to execute; -8. execute W2 releases the issued queue entry by `(bid, rid, stid)`; -9. execute completion updates ROB commit payload and writes the destination RF - tag; -10. later rows can source the just-written physical tag through the speculative - rename map. - -The current RF-backed Verilator fixture proves this with dependent rows: - -| Row | Expected data source | -|---|---| -| `ADD r3, r4, r5` | `r4/r5` are RF preloads. | -| `ADDI r6, r3, 0x7ff` | `r3` reads the physical tag written by row 0. | -| `C.MOVR r5, r6` | `r6` reads the physical tag written by row 1. | - -## Timing - -The top remains serialized and single-issue. Frontend packets can enqueue -renamed rows ahead of execute. The reduced issue queue selects the oldest ready -non-issued resident row for P1 lock, requests RF data from I1 on the following -cycle, and presents data to execute from I2. Issued/in-flight rows stay -resident and ineligible until I1 cancel clears the lock or the ALU W2 release -compacts the queue; younger ready rows may still issue around an issued or -not-ready head. RF ready-table updates become issue-visible after the issue -queue samples them on a clock edge. The ALU completes from W2, and the ROB -commit head emits the monitored row after completion. - -## Flush/Recovery - -Only `frontendFlushValid` is live. It clears the frontend/decode path and the -reduced issue queue. Backend cleanup, checkpoint restore, physical-tag -free/restore, full issue replay, precise traps, LSU cleanup, and redirect -restart remain tied off or delegated to existing child owners. This top is -replacement evidence for RF-backed scalar operand sourcing through a reduced -issue boundary, not a full speculative execution path. - -## Trace/Observability - -`tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` emits the top, -builds the shared Verilator harness with `LINXCORE_RF_ALU_TRACE_TOP`, preloads -`r4=10` and `r5=32`, enqueues the three dependent frontend packets before -draining commits, dumps DUT commit JSONL, and compares three QEMU-shaped rows -with nonzero source, destination, and writeback data. - -The old `run_chisel_frontend_alu_trace_top_xcheck.sh` remains the R81 -regression for the temporary operand fixture top. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ScalarGPRFile` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarIssueQueue` -- `bash tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh` -- `bash tools/chisel/run_chisel_tests.sh --only ReducedScalarAluExecute` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendRfAluTraceTop` -- `bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreFrontendAluTraceTop` -- `bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` -- `python3 tools/chisel/trace_schema_adapter.py --self-test` -- `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` -- `bash tools/chisel/build_chisel.sh` -- `bash tools/chisel/run_chisel_verilator_lint.sh` diff --git a/docs/chisel/modules/top/LinxCoreFrontendTraceTop.md b/docs/chisel/modules/top/LinxCoreFrontendTraceTop.md index 3d01684b..29f8b304 100644 --- a/docs/chisel/modules/top/LinxCoreFrontendTraceTop.md +++ b/docs/chisel/modules/top/LinxCoreFrontendTraceTop.md @@ -145,6 +145,6 @@ payloads remain tied to current reduced owners. - `bash tools/chisel/run_chisel_frontend_trace_top_lint.sh` - `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` - `bash tools/chisel/run_chisel_tests.sh --only DecodeRenameROBPath` -- `bash tools/chisel/run_chisel_trace_replay_xcheck.sh` +- `bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh --dry-run` - `python3 tools/chisel/trace_schema_adapter.py --self-test` - `bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run` diff --git a/docs/chisel/modules/top/LinxCoreTop.md b/docs/chisel/modules/top/LinxCoreTop.md deleted file mode 100644 index e5d7e465..00000000 --- a/docs/chisel/modules/top/LinxCoreTop.md +++ /dev/null @@ -1,176 +0,0 @@ -# LinxCoreTop - -## Source Mapping - -- Chisel: `rtl/LinxCore/chisel/src/main/scala/linxcore/top/LinxCoreTop.scala` -- Tests: `rtl/LinxCore/chisel/src/test/scala/linxcore/top/LinxCoreTopSpec.scala` -- Current child owners: `rtl/LinxCore/chisel/src/main/scala/linxcore/rob/ReducedCommitROB.scala`, - `rtl/LinxCore/chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala`, - `rtl/LinxCore/chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala` -- LinxCoreModel evidence: `model/LinxCoreModel/model/bctrl/spe/SPEROB.cpp`, - `model/LinxCoreModel/model/interface/CommitInfo.h`, - `model/LinxCoreModel/model/iex/pipe/lda_pipe.cpp`, - `model/LinxCoreModel/model/iex/iex_rf.cpp` -- Contract IDs: `LC-IF-CHISEL-TOP-001`, `LC-IF-CHISEL-XCHK-003` - -## Purpose - -`LinxCoreTop` is the current Chisel top-level bring-up shell. It is not yet the -full LinxCore frontend, decode, issue, execute, recovery, and commit system. It -instantiates the monitored `ReducedCommitROB` and canonical `ScalarLSU` store, -active/resolved load, and scalar MDB boundaries. Live failed-wait delete timing, -oldest eligibility, and exact recovery-source promotion are integrated beneath -the LSU owner. The reduced ROB supplies exact slot-plus-wrap validation for -canonical scalar LRET dequeue and consumes canonical W2 resolve through one -external-priority completion bridge. Canonical scalar GPR data and P-tag -readiness are owned by `ScalarGPRFile`; W2 GPR writeback and ordinary wakeup -join exact ROB completion through `ScalarLoadGPRCompletionSink`. Full-BID -recovery-source lookup, central cleanup, T/U local-link completion, cache/miss -queues, and full recovery remain staged. - -`LinxCoreFrontendTraceTop` is the separate next bring-up top for raw frontend -window to commit-row flow. Keep this reduced replay top stable for existing -xchecks while that newer wrapper grows toward live Verilator execution. - -## Interface - -| Direction | Signal | Type | Valid/ready | Description | -|---|---|---|---|---| -| input | `allocValid` | `Bool` | valid | Sends `allocRow` into the reduced ROB tail. | -| output | `allocReady` | `Bool` | ready | True when the reduced ROB can accept `allocRow`. | -| output | `allocDuplicateIdentity` | `Bool` | combinational | True when `allocRow.identity.(bid,gid,rid)` duplicates a live reduced ROB row. | -| input | `allocRow` | `CommitTraceRow` | `allocValid && allocReady` | Commit-trace-shaped row used as the temporary reduced top input payload. | -| input | `completeValid` | `Bool` | valid | Marks one reduced ROB slot complete. | -| input | `completeRobValue` | `UInt(log2Ceil(robEntries).W)` | `completeValid` | Reduced ROB slot index to complete. | -| output | `scalarLoadCompleteSelected` | `Bool` | combinational | Canonical scalar W2 won the shared reduced-ROB completion port. | -| output | `completeCollision` | `Bool` | combinational | External completion held a simultaneous scalar W2 candidate. | -| input | `scalarGprInit*` | valid/tag/data | pulse | Bring-up initialization of one canonical scalar GPR tag. | -| input | `scalarGprClear*` | valid/tag | pulse | Rename-side destination allocation clear for the canonical P ready table. | -| input | `externalGprWrite*` | valid/tag/data | valid/ready | Existing non-load scalar writeback source. | -| output | `externalGprWriteReady/Fire` | `Bool` | handshake | External GPR port grant and committed write. | -| input/output | `scalarGprReadTag/Data/Ready` | tag/data/ready | combinational | Diagnostic physical-tag read of canonical GPR state. | -| output | `scalarGprReadyMask` | `UInt(gprPhysRegs.W)` | state | Non-speculative P-tag readiness consumed by issue. | -| output | `scalarLoadWritebackSelected` | `Bool` | fire | W2 committed returned data to its physical GPR tag. | -| output | `scalarLoadWakeupPublished` | `Bool` | fire | W2 published ordinary P-tag readiness. | -| output | `scalarLoadBlockedByExternalWrite` | `Bool` | combinational | Configured physical write bandwidth held W2. | -| output | `scalarLoadBlockedByUnsupportedDestination` | `Bool` | combinational | T/U completion is rejected until its local-link sink exists. | -| output | `scalarBackendContractError` | `Bool` | combinational | ROB/RF/wakeup ownership or fire coherence failed. | -| bidirectional boundary | `scalarLsu.store` | `STQSCBCommitPathIO` | typed per signal | Canonical scalar LSU store request, flush, cache/response, state, and diagnostic boundary. | -| bidirectional boundary | `scalarLsu.load` | `ScalarLSULoadPathIO` | typed per signal | Canonical LIQ/ResolveQ allocation, launch, forwarding, replay/refill, recovery, retire, and state boundary. | -| bidirectional boundary | `scalarLsu.recovery` | `ScalarLSURecoverySourcePortIO` | typed valid/ready | Promoted full-BID source and readiness, oldest BID/RID watermark, and exact ROB lookup request/result. Cleanup is not owned by this reduced shell. | -| output | `commit.rows` | `Vec(commitWidth, CommitTraceRow)` | row `valid` | Head-ordered retired rows from the reduced ROB. | -| output | `commitValidMask` | `UInt(commitWidth.W)` | combinational | Reduced ROB commit valid mask. | -| output | `commitCount` | `UInt` | combinational | Number of rows retiring this cycle. | -| output | `commitMonitorValidMask` | `UInt(commitWidth.W)` | combinational | Monitor-derived valid mask for the exported commit window. | -| output | `commitMonitorValidCount` | `UInt` | combinational | Monitor-derived valid row count. | -| output | `commitSkippedSlot` | `Bool` | combinational | Monitor error flag for non-prefix valid rows. | -| output | `commitDuplicateIdentity` | `Bool` | combinational | Monitor error flag for duplicate `CommitInfo` identity in one retire window. | -| output | `commitSlotMismatch` | `Bool` | combinational | Monitor error flag for a row whose slot label does not match its vector position. | -| output | `commitInvalidSideEffect` | `Bool` | combinational | Monitor error flag for side-effect envelopes on invalid fixed-width slots. | -| output | `commitContractError` | `Bool` | combinational | OR of all monitor error flags. | -| output | `empty` | `Bool` | combinational | Reduced ROB has no live entries. | -| output | `full` | `Bool` | combinational | Reduced ROB has no free entries. | -| output | `size` | `UInt(log2Ceil(robEntries + 1).W)` | combinational | Reduced ROB live-entry count. | -| output | `headValid` | `Bool` | combinational | Reduced ROB head slot contains a live row. | -| output | `headComplete` | `Bool` | combinational | Reduced ROB head slot is live and complete. | -| output | `headRobValue` | `UInt(log2Ceil(robEntries).W)` | combinational | Current reduced ROB head slot. | -| output | `idle` | `Bool` | combinational | True when the reduced ROB and speculative/response LSU state are quiescent. | - -## State - -State is owned by `ReducedCommitROB`, `ScalarLSU`, and `ScalarGPRFile` children. -`LinxCoreTop` owns no registers of its own. - -## Logic Design - -The top computes `CommitTraceParams` from `CoreParams` so top-level commit width -and ROB slot width stay tied to the core configuration. It wires external -allocation into `ReducedCommitROB`. `ScalarLoadCompletionROBBridge` routes the -canonical LRET RID lookup to the reduced ROB and arbitrates external execute -completion against canonical scalar W2 resolve. External completion has fixed -priority; W2 remains resident and retries because resolve-ready is withheld. -When scalar W2 wins, the full RID reaches the ROB exact-completion port and is -revalidated against the resident slot generation before the completion bit can -change. The legacy external completion input remains a trusted slot-only -reduced-harness interface and is not the canonical scalar-load contract. A -same-slot external/scalar candidate is rejected as duplicate source ownership; -only different-slot contention may hold and retry. - -`ScalarLoadGPRCompletionSink` classifies the same selected W2 payload and -returns physical writeback and wakeup readiness. External GPR writeback owns -port 0. A one-port configuration serializes load completion behind it; wider -configurations permit independent tags to use another port while same-tag -requests retain external priority. GPR request/grant does not mutate state. -Only canonical W2 fire commits data and the P ready bit. T/U destinations are -not misrouted into global GPR state: the top withholds acceptance and raises an -explicit backend contract error until the point-to-point local-link sink is -integrated. - -The three readiness inputs embedded in the exposed -`scalarLsu.load.loadReturn` bundle are outer integration allow gates. Each is -ANDed with the corresponding resident ROB or GPR-sink readiness; an external -allow can hold W2 but cannot bypass exact internal ownership. The top forwards the -commit window and monitor flags, and reports `idle` when the reduced ROB is -empty and the scalar LSU reports its STQ, commit-drain queue, SCB row bank, SCB -response buffer, LIQ, ResolveQ, pending load transfer, MDB command/fanout -queues, retained wait plans, registered MDB store wakeup, and retained recovery -source empty. - -This keeps the first top-level Chisel structure aligned with the -LinxCoreModel-derived `SPEROB::commit` walk: rows retire in contiguous completed -head order, and invalid fixed-width slots are zeroed before adapter filtering. - -## Timing - -Timing is inherited from `ReducedCommitROB`: completion is registered and is not -visible to commit selection until the next cycle. The completion bridge is -combinational and adds no retained state. Exact-completion readiness is part of -the W2 atomic rendezvous, so stale/free RID rejection holds the W2 slot. GPR -port arbitration is combinational from the retained W2 candidate. Data and -P-tag readiness update on the same edge as accepted writeback; issue observes -that non-speculative readiness no earlier than the following pick cycle. - -## Flush/Recovery - -The scalar LSU accepts typed Linx store and load flush boundaries, including -precise LIQ/ResolveQ pruning. It retains MDB recovery, checks the external -oldest BID/RID watermark, and publishes an exactly promoted full-BID source. -The reduced ROB cannot supply canonical BID/RID, answer the exact full-BID -lookup, or consume that source, so full checkpoint restore, rename cleanup, -all-source arbitration, and precise trap ownership are not implemented in this -shell. Future integrated top work must -replace the reduced ROB interface with real frontend/backend ownership while -keeping commit rows monitored before cross-check use. - -## Trace/Observability - -`commit.rows` is the top-level Chisel commit observation surface for the current -bring-up shell. `commitContractError` must remain false before emitted JSONL is -treated as QEMU/DUT evidence. It now includes `scalarBackendContractError` so -ROB/RF/wakeup ownership failures invalidate the same evidence stream. - -`tools/chisel/run_chisel_trace_replay_xcheck.sh` now exercises this surface -with adapter-normalized input rows instead of only the built-in three-row smoke. -That gate is still a replay harness: it proves the top can export and compare a -bounded external commit stream, not that frontend/decode/execute/LSU generated -those rows from an ELF. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreTop` -- `bash tools/chisel/run_chisel_verilator_lint.sh` -- `bash tools/chisel/run_chisel_top_xcheck.sh` -- `bash tools/chisel/run_chisel_trace_replay_xcheck.sh` -- `bash tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` -- `bash tools/chisel/run_chisel_frontend_trace_top_lint.sh` -- `bash tools/chisel/build_chisel.sh` - -Current tests cover parameter derivation from `CoreParams`, top-level -elaboration with `ReducedCommitROB`, `CommitTraceMonitor`, `ScalarLSU`, and its -STQ-to-SCB and LIQ-to-ResolveQ children, and top Verilator -lint over all emitted SystemVerilog files. The top xcheck emits a dedicated -8-entry, two-wide `LinxCoreTop` configuration and reuses the reduced ROB -Verilator trace harness to prove the top-level commit observation surface -against QEMU-shaped reference rows. The trace replay xcheck uses the same top -configuration and comparator path but drives rows loaded from an external -normalized JSONL stream. diff --git a/docs/chisel/modules/top/ScalarLoadCompletionROBBridge.md b/docs/chisel/modules/top/ScalarLoadCompletionROBBridge.md deleted file mode 100644 index 62e9bf39..00000000 --- a/docs/chisel/modules/top/ScalarLoadCompletionROBBridge.md +++ /dev/null @@ -1,52 +0,0 @@ -# ScalarLoadCompletionROBBridge - -## Source Mapping - -- Chisel: `chisel/src/main/scala/linxcore/top/ScalarLoadCompletionROBBridge.scala` -- Parent: `chisel/src/main/scala/linxcore/top/LinxCoreTop.scala` -- ROB: `chisel/src/main/scala/linxcore/rob/ReducedCommitROB.scala` -- Tests: `chisel/src/test/scala/linxcore/top/ScalarLoadCompletionROBBridgeSpec.scala` -- Generated proof: `tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` -- Model: `model/LinxCoreModel/model/iex/iex.cpp`, `IEX::setMemData`; - `model/LinxCoreModel/model/iex/pipe/lda_pipe.cpp`, `LDAPipe::runW2` - -## Contract - -The bridge owns one reduced physical ROB-completion port. External execute -completion has fixed priority. When both sources are candidates, scalar -resolve-ready is low, the W2 slot remains resident, and `collision` is set. -Legal contention requires different ROB slots. A same-slot external and scalar -candidate is a duplicate-owner protocol violation because the legacy external -port has no generation or producer identity with which to prove idempotence. -When scalar resolve fires, the bridge forwards the complete slot-plus-wrap RID -through the ROB's exact-completion port and reports `scalarLoadSelected`. -Scalar resolve-ready also requires the ROB to revalidate that exact RID in the -same cycle. A free, stale, or invalid RID therefore holds W2 and cannot mutate -the completion bit. - -The bridge also routes the canonical queue-head RID lookup to the reduced ROB. -The ROB validates slot plus wrap generation before LRET can enter W1. This -read-only lookup is distinct from the full-BID recovery lookup and does not -fabricate block authority. - -The bridge is combinational. It must not retain or reconstruct completion -payloads, truncate RID generation, or emit both completion sources in one -cycle. The external source uses the legacy trusted slot-only harness port; -canonical scalar W2 does not. - -## Scope - -Shared completion arbitration and exact generation lookup are ISA-neutral. -The identity is Linx RID state; ARM exception levels, flags, exclusives, -barriers, acquire/release policy, and return state are not imported. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ScalarLoadCompletionROBBridgeSpec` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreTopSpec` -- `bash tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` - -The generated probe cycles the ROB through wrap and slot reuse, rejects a stale -pre-wrap RID, proves exact wrapped completion, and covers legal different-row -external-completion contention. The reference test classifies same-row -contention as a duplicate-owner protocol violation. diff --git a/docs/chisel/modules/top/ScalarLoadGPRCompletionSink.md b/docs/chisel/modules/top/ScalarLoadGPRCompletionSink.md deleted file mode 100644 index 3616c33f..00000000 --- a/docs/chisel/modules/top/ScalarLoadGPRCompletionSink.md +++ /dev/null @@ -1,75 +0,0 @@ -# ScalarLoadGPRCompletionSink - -## Source Mapping - -- Chisel: `chisel/src/main/scala/linxcore/top/ScalarLoadGPRCompletionSink.scala` -- Parent: `chisel/src/main/scala/linxcore/top/LinxCoreTop.scala` -- GPR owner: `chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala` -- Tests: `chisel/src/test/scala/linxcore/top/ScalarLoadGPRCompletionSinkSpec.scala` -- Generated proof: `tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` -- Model: `model/LinxCoreModel/model/iex/pipe/lda_pipe.cpp`, `LDAPipe::runW2`; - `model/LinxCoreModel/model/iex/iex_iq.cpp`, `IssueQueue::WakeupIQTag` - -## Contract - -The sink is the physical scalar-GPR side of the canonical W2 rendezvous. It -classifies the resident load destination, requests write bandwidth, and returns -writeback/wakeup readiness to `ScalarLSULoadReturnPipeline`. It commits no -state from candidate validity alone. - -When W2 resolves: - -- a GPR destination commits returned data to its physical tag; -- ordinary non-speculative P wakeup publishes by setting the same ready bit; -- writeback and wakeup fires must match the destination/speculation shape; -- the sink and exact ROB completion are accepted in one cycle. - -External writeback uses port 0. With one configured port it blocks scalar W2. -With multiple ports, different tags may complete together; a same-tag external -write retains priority and holds W2. W2 retries with its complete payload. - -## Destination Policy - -`DestinationKind.Gpr` is supported. No-destination returns require neither GPR -write nor GPR wakeup. Speculative-wakeup and stack sidebands suppress ordinary -wakeup according to the canonical LRET payload. - -T/U destinations are deliberately not converted to GPR writes. An ordinary -T/U wakeup request keeps `loadWakeupReady` low, reports -`loadBlockedByUnsupportedDestination`, and raises `protocolError` until the -local-link bank/qtag owner is connected. W2 is not accepted and no ROB, GPR, or -P-ready evidence is valid for that request. This explicit integration failure -prevents a silent permanent stall or an ISA-invalid substitution. - -## State And Timing - -The sink owns no retained arbitration state. `ScalarGPRFile` owns data and -readiness. Port grants are combinational from stable W2 candidates; mutation is -registered only from fire. Same-tag external contention and a one-port -configuration therefore backpressure W2 without early ROB completion, RF -write, or ready-table update. - -## Diagnostics - -- `loadWriteRequired` and `loadWakeupRequired` expose payload classification. -- `loadWritebackSelected` reports committed scalar GPR data. -- `loadWakeupPublished` reports committed ordinary P-tag readiness. -- `loadBlockedByExternalWrite` distinguishes physical-port contention. -- `loadBlockedByUnsupportedDestination` distinguishes the staged T/U path. -- `protocolError` checks resolve/writeback/wakeup fire coherence, GPR state - ownership, and unsupported T/U integration requests. - -## Verification - -- `bash tools/chisel/run_chisel_tests.sh --only ScalarLoadGPRCompletionSinkSpec` -- `bash tools/chisel/run_chisel_tests.sh --only LinxCoreTopSpec` -- `bash tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh` - -The generated probe clears a physical tag, proves a same-tag external write -holds scalar completion, retries W2, and then observes returned data, ready bit, -wakeup publication, and ROB completion together. It also proves independent -external and scalar tags use two configured ports in one cycle, a one-port -configuration serializes different tags, and a T destination reports the -explicit contract error without mutating ROB or GPR state. Each public -resolve/writeback/wakeup allow is also withdrawn independently to prove that -the resident W2 and every side effect remain held. diff --git a/docs/chisel/ooo-opcode-recipe-audit.md b/docs/chisel/ooo-opcode-recipe-audit.md index e4cf8a44..07ec2b9b 100644 --- a/docs/chisel/ooo-opcode-recipe-audit.md +++ b/docs/chisel/ooo-opcode-recipe-audit.md @@ -14,9 +14,9 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | Opcode | ID | Recipe | Disposition | Uops | Dispatch | Capabilities | PC read | Owner | Reason | |---|---:|---|---|---:|---|---|---|---|---| | `OP_INVALID` | 0 | `ILLEGAL` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `ILLEGAL` | internal or invalid opcode | -| `OP_BSTART_CUBE` | 1 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_CUBE` | 1 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_BSTART_FALL` | 2 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_BSTART_FIXP` | 3 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_FIXP` | 3 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_BSTART_FP_CALL` | 4 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_FP_COND` | 5 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_FP_DIRECT` | 6 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | @@ -26,24 +26,24 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_BSTART_FP_RET` | 10 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_ICALL` | 11 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_IND` | 12 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_BSTART_MPAR` | 13 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_BSTART_MSEQ` | 14 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_MPAR` | 13 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_MSEQ` | 14 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_BSTART_RET` | 15 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_SPLIT_COND` | 16 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_SPLIT_DIRECT` | 17 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_STD_CALL` | 18 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_STD_COND` | 19 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_BSTART_STD_DIRECT` | 20 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_BSTART_SYS` | 21 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_BSTART_TEPL` | 22 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_BSTART_TMA` | 23 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_BSTART_VPAR` | 24 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_BSTART_VSEQ` | 25 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_SYS` | 21 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_TEPL` | 22 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_TMA` | 23 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_VPAR` | 24 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_BSTART_VSEQ` | 25 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_C_BSTART_COND` | 26 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_DIRECT` | 27 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_FP` | 28 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_C_BSTART_MPAR` | 29 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_C_BSTART_MSEQ` | 30 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_C_BSTART_MPAR` | 29 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_C_BSTART_MSEQ` | 30 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_C_BSTART_STD_CALL` | 31 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_STD_COND` | 32 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_STD_DIRECT` | 33 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | @@ -51,29 +51,29 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_C_BSTART_STD_ICALL` | 35 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_STD_IND` | 36 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_C_BSTART_STD_RET` | 37 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_C_BSTART_SYS` | 38 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_C_BSTART_VPAR` | 39 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | -| `OP_C_BSTART_VSEQ` | 40 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_C_BSTART_SYS` | 38 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_C_BSTART_VPAR` | 39 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | +| `OP_C_BSTART_VSEQ` | 40 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_C_BSTOP` | 41 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_B_ARG` | 42 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_ARG_DN2NZ` | 43 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_ARG_DN2ZN` | 44 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_ARG_ND2ZN` | 45 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_ARG_NORM` | 46 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_ARG_NZ2DN` | 47 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_CATR` | 48 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_DATR` | 49 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_DIM_LB0` | 50 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_DIM_LB1` | 51 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_DIM_LB2` | 52 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_EQ` | 53 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_GE` | 54 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_GEU` | 55 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_HINT` | 56 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_HINT_TRACE` | 57 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_LT` | 58 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_LTU` | 59 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_NE` | 60 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | +| `OP_B_ARG` | 42 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_ARG_DN2NZ` | 43 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_ARG_DN2ZN` | 44 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_ARG_ND2ZN` | 45 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_ARG_NORM` | 46 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_ARG_NZ2DN` | 47 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_CATR` | 48 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_DATR` | 49 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_DIM_LB0` | 50 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_DIM_LB1` | 51 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_DIM_LB2` | 52 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_EQ` | 53 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_GE` | 54 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_GEU` | 55 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_HINT` | 56 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_HINT_TRACE` | 57 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_LT` | 58 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_LTU` | 59 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_NE` | 60 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | | `OP_ADD` | 61 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_ADDI` | 62 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_ADDIW` | 63 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | @@ -109,7 +109,7 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_HL_BSTART_FP_COND` | 93 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_HL_BSTART_FP_DIRECT` | 94 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_HL_BSTART_FP_FALL` | 95 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_HL_BSTART_SYS` | 96 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_HL_BSTART_SYS` | 96 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_HL_CASB` | 97 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | | `OP_HL_CASD` | 98 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | | `OP_HL_CASH` | 99 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | @@ -437,9 +437,9 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_SW_UMAX` | 421 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | | `OP_SW_UMIN` | 422 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | | `OP_SW_XOR` | 423 | `ATOMIC_UNRESOLVED` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `LSU` | atomic child and terminal-result ownership must be explicit | -| `OP_BIOR` | 424 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_BTEXT` | 425 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | -| `OP_B_IOT` | 426 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | generated dispatch recipe | +| `OP_BIOR` | 424 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_BTEXT` | 425 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | +| `OP_B_IOT` | 426 | `SINGLE` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | | `OP_ERCOV` | 427 | `ILLEGAL` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `ILLEGAL` | template child recipe is not yet architecturally frozen | | `OP_ESAVE` | 428 | `ILLEGAL` | `ILLEGAL` | 0..0 | `NONE` | `NONE` | `NONE/NONE` | `ILLEGAL` | template child recipe is not yet architecturally frozen | | `OP_FENTRY` | 429 | `CTU_TEMPLATE` | `CTU` | 2..23 | `NONE` | `NONE` | `NONE/NONE` | `CTU` | external CTU owns the canonical child stream | @@ -583,12 +583,12 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_C_B_DIM` | 567 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_B_DIMI` | 568 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_EBREAK` | 569 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | -| `OP_C_LDI` | 570 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | -| `OP_C_LWI` | 571 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | +| `OP_C_LDI` | 570 | `SCALAR_LOAD` | `DISPATCH` | 1..1 | `AGU` | `AGU:LOAD_ADDRESS` | `NONE/NONE` | `LSU` | compact scalar load allocates the next T destination | +| `OP_C_LWI` | 571 | `SCALAR_LOAD` | `DISPATCH` | 1..1 | `AGU` | `AGU:LOAD_ADDRESS` | `NONE/NONE` | `LSU` | compact scalar load allocates the next T destination | | `OP_C_MOVI` | 572 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_MOVR` | 573 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_OR` | 574 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | -| `OP_C_SDI` | 575 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | +| `OP_C_SDI` | 575 | `SCALAR_STORE` | `DISPATCH` | 2..2 | `STD` | `AGU:STORE_ADDRESS,STD:STORE_DATA` | `NONE/NONE` | `LSU` | compact scalar store consumes base plus relative T#1 | | `OP_C_SEXT_B` | 576 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_SEXT_H` | 577 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_SEXT_W` | 578 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | @@ -596,7 +596,7 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_C_SRLI` | 580 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_SSRGET` | 581 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_SUB` | 582 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | -| `OP_C_SWI` | 583 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | +| `OP_C_SWI` | 583 | `SCALAR_STORE` | `DISPATCH` | 2..2 | `STD` | `AGU:STORE_ADDRESS,STD:STORE_DATA` | `NONE/NONE` | `LSU` | compact scalar store consumes base plus relative T#1 | | `OP_C_ZEXT_B` | 584 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_ZEXT_H` | 585 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_C_ZEXT_W` | 586 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | @@ -649,7 +649,7 @@ Catalog records: **689**; unique opcode IDs: **658**; primary-parent PC reads: * | `OP_LSRGET` | 634 | `SINGLE` | `DISPATCH` | 1..1 | `SYS` | `SYS:SYSTEM` | `NONE/NONE` | `COMMIT` | generated dispatch recipe | | `OP_L_BSTART_FP` | 635 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | | `OP_L_BSTART_STD` | 636 | `BOUNDARY` | `FAST_RESOLVE` | 0..1 | `NONE` | `NONE` | `NONE/NONE` | `BCTRL` | pure boundary may fuse or publish one ordered metadata member | -| `OP_L_BSTART_SYS` | 637 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `BCTRL` | engine header requires a command child plus BROB metadata | +| `OP_L_BSTART_SYS` | 637 | `ENGINE_CMD` | `DISPATCH` | 1..1 | `CMD` | `CMD:ENGINE_COMMAND` | `NONE/NONE` | `COMMIT` | engine header requires a command child plus BROB metadata | | `OP_MADD` | 638 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_MADDW` | 639 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | | `OP_MAX` | 640 | `SINGLE` | `DISPATCH` | 1..1 | `ALU` | `ALU:SIMPLE_ALU` | `NONE/NONE` | `IEX` | generated dispatch recipe | diff --git a/docs/chisel/production-owner-manifest.md b/docs/chisel/production-owner-manifest.md new file mode 100644 index 00000000..676b71e1 --- /dev/null +++ b/docs/chisel/production-owner-manifest.md @@ -0,0 +1,609 @@ +# LinxCore production-owner cutover manifest + +This document freezes the one-owner decision before the atomic +`TOP -> IFU -> CTU -> OOO -> IEX -> LSU` cutovers. It is both a review page and +an executable manifest consumed by +`tools/chisel/check_production_owner_manifest.py`. Later cutover tasks must +update the owner, caller, evidence, and deletion records in the same commit as +the boundary change. + +## Authority and NDF projection + +- **L1 contract homes** state observable ownership and interface obligations in + `docs/spec/10-architecture/ownership.md`, `docs/spec/10-architecture/top.md`, + and the eight `docs/spec/30-interfaces/` homes. +- **L2 mechanism evidence** is the production mechanism/file ownership below + each public box plus the generated typed Bundle projection in + `docs/chisel/generated/top-interface-manifest.json`. +- **L3 verification evidence** is the executable owner/contract fixture named + on every row. `standalone-verified` means the owner is proved in isolation + but is not yet promoted through canonical `TOP`; promotion requires the + later task's nonzero generated-RTL/workload evidence. + +`TOPIO.scala` and the generated interface manifest are the contract homes for +future TOP wiring. They do not own architectural state. `IFU`, `CTU`, `OOO`, `IEX`, +`LSU`, and `DTU` are the permanent public boxes; a public interface Bundle is +not a compatibility owner. + +## Entry-point classification + +`linxcore.top.EmitTOP` is the sole active core emitter. Every retained `*Probe` is a +verification entry point and cannot promote an owner. +`EmitD1DecodeRenameROBIngress` remains a standalone fixture. + +## Machine-readable manifest + +The JSON block is normative for the checker. Every deletion target names an +exact Scala symbol. A `planned-active` target must declare exactly the callers +discovered in main Scala; a `deletion-ready` target is accepted only when both +sets are empty. Compatibility adapters must be stateless. Pre-cutover legacy +state owners whose historical names end in `Adapter` are recorded separately +as `legacy-state-owner`, must report their discovered state honestly, and must +carry a deletion task; they are never compatibility adapters or promotion +evidence. + +```json production-owner-manifest +{ + "schema_version": 2, + "completed_cutover_tasks": [13, 15, 16, 17], + "ndf": { + "L1": [ + "docs/spec/10-architecture/ownership.md", + "docs/spec/10-architecture/top.md", + "docs/spec/30-interfaces/ifu-ctu.md", + "docs/spec/30-interfaces/ctu-ooo.md", + "docs/spec/30-interfaces/ooo-iex.md", + "docs/spec/30-interfaces/iex-lsu.md", + "docs/spec/30-interfaces/recovery.md", + "docs/spec/30-interfaces/commit.md", + "docs/spec/30-interfaces/dtu.md", + "docs/spec/30-interfaces/memory.md" + ], + "L2": [ + "chisel/src/main/scala/linxcore/top/interface/TOPIO.scala", + "docs/chisel/generated/top-interface-manifest.json" + ], + "L3": [ + "chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala", + "chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala", + "tests/test_production_owner_manifest.py" + ], + "interface_manifest": "docs/chisel/generated/top-interface-manifest.json" + }, + "entry_points": { + "production": [ + {"name": "linxcore.top.EmitTOP", "path": "chisel/src/main/scala/linxcore/top/EmitTOP.scala", "classification": "production", "root_symbol": "TOP", "boxes": ["IFU", "CTU", "OOO", "IEX", "LSU", "DTU"], "production_evidence": [".superpowers/sdd/2026-07-31-core-mainline-restructure/task-18-report.md"]} + ], + "non_production": [ + {"name": "linxcore.bctrl.EmitBrobOrderStateProbe", "path": "chisel/src/main/scala/linxcore/bctrl/BrobOrderStateProbe.scala", "classification": "probe"}, + {"name": "linxcore.bctrl.EmitBrobStoreCountPublisherProbe", "path": "chisel/src/main/scala/linxcore/bctrl/BrobStoreCountPublisherProbe.scala", "classification": "probe"}, + {"name": "linxcore.bctrl.EmitBrobStoreRangeStateProbe", "path": "chisel/src/main/scala/linxcore/bctrl/BrobStoreRangeStateProbe.scala", "classification": "probe"}, + {"name": "linxcore.backend.EmitD1DecodeRenameROBIngress", "path": "chisel/src/main/scala/linxcore/backend/D1DecodeRenameROBIngress.scala", "classification": "fixture"}, + {"name": "linxcore.frontend.EmitD1InstructionDecodeProbe", "path": "chisel/src/main/scala/linxcore/frontend/D1InstructionDecodeProbe.scala", "classification": "probe"}, + {"name": "linxcore.backend.EmitDecodeLoadStoreIdAssignProbe", "path": "chisel/src/main/scala/linxcore/backend/DecodeLoadStoreIdAssignProbe.scala", "classification": "probe"}, + {"name": "linxcore.rename.EmitGPRRenameStidProbe", "path": "chisel/src/main/scala/linxcore/rename/GPRRenameStidProbe.scala", "classification": "probe"}, + {"name": "linxcore.frontend.EmitIfuBackendFeedbackBridgeProbe", "path": "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridgeProbe.scala", "classification": "probe"}, + {"name": "linxcore.top.EmitIfuLineMemoryBridgeProbe", "path": "chisel/src/main/scala/linxcore/top/IfuLineMemoryBridgeProbe.scala", "classification": "probe"}, + {"name": "linxcore.top.EmitLinxCoreCompositionProbe", "path": "chisel/src/main/scala/linxcore/top/LinxCoreCompositionProbe.scala", "classification": "probe"}, + {"name": "linxcore.frontend.EmitLinxCoreIfuThroughputProbe", "path": "chisel/src/main/scala/linxcore/frontend/LinxCoreIfuThroughputProbe.scala", "classification": "probe"}, + {"name": "linxcore.lsu.EmitLoadMissQueueProbe", "path": "chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala", "classification": "probe"}, + {"name": "linxcore.lsu.EmitLoadRefillTransportProbe", "path": "chisel/src/main/scala/linxcore/lsu/LoadRefillTransportProbe.scala", "classification": "probe"}, + {"name": "linxcore.recovery.EmitRecoveryClassMergeProbe", "path": "chisel/src/main/scala/linxcore/recovery/RecoveryClassMergeProbe.scala", "classification": "probe"}, + {"name": "linxcore.recovery.EmitRecoveryCleanupROBProbe", "path": "chisel/src/main/scala/linxcore/recovery/RecoveryCleanupROBProbe.scala", "classification": "probe"}, + {"name": "linxcore.recovery.EmitRecoveryProducerProbe", "path": "chisel/src/main/scala/linxcore/recovery/RecoveryProducerProbe.scala", "classification": "probe"}, + {"name": "linxcore.rob.EmitReducedCommitROB", "path": "chisel/src/main/scala/linxcore/rob/EmitReducedCommitROB.scala", "classification": "reduced"}, + {"name": "linxcore.lsu.EmitScalarL1DScbProbe", "path": "chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala", "classification": "probe"}, + {"name": "linxcore.lsu.EmitScalarLSULoadPathReturnProbe", "path": "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala", "classification": "probe"}, + {"name": "linxcore.lsu.EmitScalarLSULoadReturnQueueProbe", "path": "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueueProbe.scala", "classification": "probe"}, + {"name": "linxcore.lsu.EmitScalarLSUMDBPathProbe", "path": "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala", "classification": "probe"} + ] + }, + "adapters": [ + { + "symbol": "linxcore.top.IfuWindowLineFillAdapter", + "path": "chisel/src/main/scala/linxcore/top/IfuWindowLineFillAdapter.scala", + "role": "legacy-state-owner", + "stateful": true, + "status": "planned-deletion", + "owner_domain": "instruction_cache", + "cutover_task": 17, + "deletion_target": "linxcore.top.IfuWindowLineFillAdapter" + }, + { + "symbol": "linxcore.ifu.ISideMemoryAdapter", + "path": "chisel/src/main/scala/linxcore/ifu/ISide.scala", + "role": "legacy-state-owner", + "stateful": true, + "status": "planned-deletion", + "owner_domain": "instruction_cache", + "cutover_task": 17, + "deletion_target": "linxcore.ifu.ISideMemoryAdapter" + }, + { + "symbol": "linxcore.frontend.IfuBackendFeedbackBridge", + "path": "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridge.scala", + "role": "legacy-state-owner", "stateful": true, "status": "planned-deletion", + "owner_domain": "ifu_recovery_redirect", "cutover_task": 17, + "deletion_target": "linxcore.frontend.IfuBackendFeedbackBridge" + }, + { + "symbol": "linxcore.rename.ScalarDecodeRenameBridge", + "path": "chisel/src/main/scala/linxcore/rename/ScalarDecodeRenameBridge.scala", + "role": "legacy-state-owner", "stateful": true, "status": "planned-deletion", + "owner_domain": "rename_p", "cutover_task": 11, + "deletion_target": "linxcore.rename.ScalarDecodeRenameBridge" + }, + { + "symbol": "linxcore.rename.ScalarTURenameBridge", + "path": "chisel/src/main/scala/linxcore/rename/ScalarTURenameBridge.scala", + "role": "legacy-state-owner", "stateful": true, "status": "planned-deletion", + "owner_domain": "rename_tu", "cutover_task": 11, + "deletion_target": "linxcore.rename.ScalarTURenameBridge" + }, + { + "symbol": "linxcore.top.IfuLineMemoryBridge", + "path": "chisel/src/main/scala/linxcore/top/IfuLineMemoryBridge.scala", + "role": "legacy-state-owner", "stateful": true, "status": "planned-deletion", + "owner_domain": "instruction_cache", "cutover_task": 17, + "deletion_target": "linxcore.top.IfuLineMemoryBridge" + } + ], + "owners": [ + { + "subsystem": "IFU", + "state_key": "instruction_cache", + "canonical_owner": "ISideL1I", + "mechanism_files": ["chisel/src/main/scala/linxcore/frontend/ISideL1I.scala"], + "public_box": "IFU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ifu/IFU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IFUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 17, + "deletion_targets": [ + {"path": "chisel/src/main/scala/linxcore/top/IfuWindowLineFillAdapter.scala", "symbol": "linxcore.top.IfuWindowLineFillAdapter", "status": "deletion-ready", "active_callers": []}, + {"path": "chisel/src/main/scala/linxcore/ifu/ISide.scala", "symbol": "linxcore.ifu.ISideMemoryAdapter", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/ifu/ISide.scala"]}, + {"path": "chisel/src/main/scala/linxcore/top/IfuLineMemoryBridge.scala", "symbol": "linxcore.top.IfuLineMemoryBridge", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/top/IfuLineMemoryBridgeProbe.scala", "chisel/src/main/scala/linxcore/top/LinxCoreComposition.scala"]} + ], + "adapters": [] + }, + { + "subsystem": "IFU", + "state_key": "predictor_history", + "canonical_owner": "BSide", + "mechanism_files": ["chisel/src/main/scala/linxcore/ifu/BSide.scala", "chisel/src/main/scala/linxcore/frontend/BSideHistoryQueue.scala", "chisel/src/main/scala/linxcore/frontend/BSidePredictionPipeline.scala"], + "public_box": "IFU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ifu/IFU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IFUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 17, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "IFU", + "state_key": "ifu_recovery_redirect", + "canonical_owner": "IFURecovery", + "mechanism_files": ["chisel/src/main/scala/linxcore/ifu/IFURecovery.scala", "chisel/src/main/scala/linxcore/frontend/IfuRedirectArbiter.scala"], + "public_box": "IFU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ifu/IFU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IFUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 17, + "deletion_targets": [ + {"path": "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridgeProbe.scala", "symbol": "linxcore.frontend.IfuBackendFeedbackBridgeProbe", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridgeProbe.scala"]}, + {"path": "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridge.scala", "symbol": "linxcore.frontend.IfuBackendFeedbackBridge", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridgeProbe.scala", "chisel/src/main/scala/linxcore/top/LinxCoreComposition.scala"]} + ], + "adapters": [] + }, + { + "subsystem": "CTU", + "state_key": "instruction_buffer", + "canonical_owner": "InstructionBuffer", + "mechanism_files": ["chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala", "chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala", "chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala"], + "public_box": "CTU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ctu/CTU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/CTUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ctu/CTU.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ctu/CTUSpec.scala", "chisel/src/test/scala/linxcore/ctu/InstructionBufferSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ctu/CTUSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 17, + "deletion_targets": [{"path": "chisel/src/main/scala/linxcore/frontend/InstructionBuffer.scala", "symbol": "linxcore.frontend.InstructionBuffer", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala"]}], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "rename_p", + "canonical_owner": "PRename", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/PRename.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/RENU.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/RENUSpec.scala", "chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala", "level": "L3", "status": "standalone-verified"}], + "cutover_task": 11, + "deletion_targets": [ + {"path": "chisel/src/main/scala/linxcore/rename/ScalarDecodeRenameBridge.scala", "symbol": "linxcore.rename.ScalarDecodeRenameBridge", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/rename/ScalarTURenameBridge.scala"]} + ], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "rename_tu", + "canonical_owner": "TURename", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/TURename.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/RENU.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/RENUSpec.scala", "chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala", "level": "L3", "status": "standalone-verified"}], + "cutover_task": 11, + "deletion_targets": [ + {"path": "chisel/src/main/scala/linxcore/rename/ScalarTURenameBridge.scala", "symbol": "linxcore.rename.ScalarTURenameBridge", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/backend/DecodeRenameROBPath.scala"]} + ], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "memory_order", + "canonical_owner": "OooMemoryOrderAllocator", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OooMemoryOrderAllocatorSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala", "case": "publishes DEC memory demand as stable full-order metadata", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 13, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "rob", + "canonical_owner": "ROB", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/ROB.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 11, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "brob", + "canonical_owner": "BROB", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/BROB.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 11, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "commit", + "canonical_owner": "CommitControl", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/CommitControl.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala", "case": "commits one completed canonical OOO publication exactly once", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala", "case": "CommitControl requires exact NFRDY and never repeats a resident head", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 11, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "recovery", + "canonical_owner": "RecoveryControl", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 11, + "deletion_targets": [ + {"path": "chisel/src/main/scala/linxcore/recovery/RecoveryCleanupControl.scala", "symbol": "linxcore.recovery.RecoveryCleanupControl", "status": "planned-active", "active_callers": ["chisel/src/main/scala/linxcore/recovery/RecoveryFabric.scala"]} + ], + "adapters": [] + }, + { + "subsystem": "OOO", + "state_key": "dispatch_reservation", + "canonical_owner": "OooD3ReservationAllocator", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala", "chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala", "chisel/src/main/scala/linxcore/ooo/OooDispatch.scala"], + "public_box": "OOO", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/OOOIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/Dispatch.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala", "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 11, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "IEX", + "state_key": "issue_queue", + "canonical_owner": "OooIexIssue", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala", "chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala"], + "public_box": "IEX", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/iex/IEX.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IEXIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala", "chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexIssueSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 13, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "IEX", + "state_key": "physical_register_data_readiness", + "canonical_owner": "OooIexOperandFiles", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala", "chisel/src/main/scala/linxcore/ooo/OooIexPDataFile.scala"], + "public_box": "IEX", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/iex/IEX.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IEXIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OooIexIssueReadFabric.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexOperandFilesSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 13, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "IEX", + "state_key": "execution_pipeline", + "canonical_owner": "OooIexExecutionPipeline", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala", "chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala"], + "public_box": "IEX", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/iex/IEX.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IEXIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/iex/IEX.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala", "chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala", "chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexExecutionPipelineSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexTerminalFabricSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 13, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "IEX", + "state_key": "memory_transaction_and_initial_attempt_serial", + "canonical_owner": "OooIexIssue", + "mechanism_files": ["chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala"], + "public_box": "IEX", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/iex/IEX.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/IEXIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/ooo/OooIexIssueP1Fabric.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala", "chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala", "chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/iex/LoadIexIssuePipelineSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/ooo/OooIexCanonicalLoadOwnershipSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 13, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "lsu_pipeline", + "canonical_owner": "LSU", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/LSU.scala", "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala", "chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/top/TOP.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/lsu/LoadMissQueueSpec.scala", "level": "L3", "status": "standalone-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "store_queue", + "canonical_owner": "STQEntryBank", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala", "chisel/src/main/scala/linxcore/lsu/STQDataBank.scala", "chisel/src/main/scala/linxcore/lsu/STQCommitQueue.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala", "chisel/src/main/scala/linxcore/lsu/StoreDispatchSTQPath.scala", "chisel/src/main/scala/linxcore/ooo/OooIexStoreStqFabric.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/STQEntryBankSpec.scala", "chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "store_commit_buffer", + "canonical_owner": "SCBRowBank", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala", "chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala", "chisel/src/main/scala/linxcore/lsu/STQSCBCommitPath.scala", "chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/SCBRowBankSpec.scala", "chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "load_inflight_queue", + "canonical_owner": "LoadInflightQueue", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala", "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LoadInflightQueueSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "load_resolve_queue", + "canonical_owner": "LoadResolveQueue", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/LoadResolveQueue.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LoadResolveQueueSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "memory_dependency", + "canonical_owner": "ScalarLSUMDBPath", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala", "chisel/src/main/scala/linxcore/lsu/MDBConflictDetect.scala", "chisel/src/main/scala/linxcore/lsu/MDBSSIT.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala", "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala", "chisel/src/test/scala/linxcore/lsu/MDBConflictDetectSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/ScalarLSUMDBPathSpec.scala", "level": "L3", "status": "standalone-verified"}, {"fixture": "chisel/src/test/scala/linxcore/lsu/MDBConflictDetectSpec.scala", "level": "L3", "status": "standalone-verified"}], + "cutover_task": 15, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "cache", + "canonical_owner": "ScalarL1D", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala", "chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala", "chisel/src/main/scala/linxcore/lsu/LoadRefillTransport.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala", "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/ScalarL1DSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 16, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "data_translation", + "canonical_owner": "DSideTranslation", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/Translation.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/LSU.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 16, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "lower_memory_transactions", + "canonical_owner": "LSULowerTransactionRecovery", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/LSURecovery.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/lsu/LSU.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 16, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "LSU", + "state_key": "lsu_recovery", + "canonical_owner": "LSU", + "mechanism_files": ["chisel/src/main/scala/linxcore/lsu/LSU.scala"], + "public_box": "LSU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/LSUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/top/TOP.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala", "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 16, + "deletion_targets": [], + "adapters": [] + }, + { + "subsystem": "DTU", + "state_key": "trace_debug_performance_observation", + "canonical_owner": "DTU", + "mechanism_files": ["chisel/src/main/scala/linxcore/dtu/DTU.scala", "chisel/src/main/scala/linxcore/dtu/DebugControl.scala", "chisel/src/main/scala/linxcore/dtu/TraceExport.scala", "chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala"], + "public_box": "DTU", + "public_box_status": "module", + "public_box_file": "chisel/src/main/scala/linxcore/dtu/DTU.scala", + "public_interface_file": "chisel/src/main/scala/linxcore/top/interface/DTUIO.scala", + "active_callers": ["chisel/src/main/scala/linxcore/top/TOP.scala"], + "verification_fixtures": ["chisel/src/test/scala/linxcore/dtu/DTUSpec.scala", "chisel/src/test/scala/linxcore/iex/DTUActivationTraceSpec.scala", "chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala"], + "production_evidence": [{"fixture": "chisel/src/test/scala/linxcore/dtu/DTUSpec.scala", "case": "trace observation never backpressures a stalled exporter", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/iex/DTUActivationTraceSpec.scala", "case": "stalled external trace export cannot suppress terminal or commit progress", "level": "L3", "status": "public-box-verified"}, {"fixture": "chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala", "case": "OOO accepts halt only at a commit boundary and resume releases it", "level": "L3", "status": "public-box-verified"}], + "cutover_task": 17, + "deletion_targets": [], + "adapters": [] + } + ] +} +``` + +## Cutover rule + +A later task may change an owner only by updating its production mechanism, +public-box reachability, all active callers, L3 evidence, and deletion targets +atomically. A `standalone-verified` or `mechanism-verified-cutover-pending` row +is not production replacement evidence. A compatibility adapter may retain no +queue, map, ROB, cache, predictor, readiness table, or recovery transaction. +Any pre-existing stateful legacy owner named `Adapter` stays planned for the +same atomic deletion as its closed state domain. diff --git a/docs/chisel/replay-liq-qemu-candidate-locator.md b/docs/chisel/replay-liq-qemu-candidate-locator.md index f34aef9c..5f7184a5 100644 --- a/docs/chisel/replay-liq-qemu-candidate-locator.md +++ b/docs/chisel/replay-liq-qemu-candidate-locator.md @@ -2,17 +2,26 @@ Date: 2026-07-07 +Status: historical archive. Task 15 deleted the replay-LIQ locator, scanners, +report builders, and specialized RF/ALU QEMU wrappers described on this page. +No supported current equivalent exists for those workflows. Their commands, +schemas, and results remain here only as historical evidence and are not +runnable from the current tree. The surviving +`tools/chisel/build_frontend_fetch_rf_seed.py` helper does not restore the +deleted downstream replay flows. + ## Purpose -`tools/chisel/find_replay_liq_qemu_candidates.py` scans QEMU-shaped commit -JSONL and reports memory-row clusters that may be useful for later natural -replay-LIQ probes. It is intentionally a locator only: it does not prove +`tools/chisel/find_replay_liq_qemu_candidates.py` scanned QEMU-shaped commit +JSONL and reported memory-row clusters that could be useful for later natural +replay-LIQ probes. It was intentionally a locator only: it did not prove replay-LIQ behavior, MDB learning, STQ wait-store state, or DUT equivalence. -The tool exists because R607-R611 showed that early CoreMark prefixes can pass -the generated-RTL/QEMU comparator with zero natural replay-LIQ counters. Before -spending another Verilator build on a wider window, agents should first use -QEMU-only capture plus this locator to identify concrete store/load PC windows. +The tool existed because R607-R611 showed that early CoreMark prefixes could +pass the generated-RTL/QEMU comparator with zero natural replay-LIQ counters. +The historical workflow used QEMU-only capture plus this locator to identify +concrete store/load PC windows before spending another Verilator build on a +wider window. ## Model Evidence @@ -33,7 +42,10 @@ QEMU commit rows do not carry the required model timing or live queue state. They can identify address reuse, same-cacheline reuse, and approximate PC windows; generated RTL sideband counters remain the acceptance surface. -## Interface +## Historical Interface + +The following locator invocation was valid before Task 15 deleted the script. +It has no supported current equivalent: ```bash python3 tools/chisel/find_replay_liq_qemu_candidates.py \ @@ -44,15 +56,24 @@ python3 tools/chisel/find_replay_liq_qemu_candidates.py \ --lookback-rows 1024 ``` -Use `--raw-input` when scanning a reduced preview and the matching raw trace is -available. The reduced preview can filter or skip rows relative to the raw QEMU -stream; its candidate row numbers are therefore not safe `--qemu-skip-rows` -arguments by themselves. With `--raw-input`, each top candidate includes a +Historical command provenance: source commit +`7e2931bc6550ccf344b6d367e672f978381dca58`. + +The historical workflow used `--raw-input` when scanning a reduced preview and +the matching raw trace was available. The reduced preview could filter or skip +rows relative to the raw QEMU stream; its candidate row numbers therefore were +not safe `--qemu-skip-rows` arguments by themselves. With `--raw-input`, each +top candidate included a `probe_hint.raw_dynamic_window` with absolute raw `--qemu-skip-rows` and `--capture-rows` arguments for QEMU-only reproduction. -For later raw intervals that do not form a strict reduced-row prefix, capture -raw QEMU rows only and run the locator directly on `qemu.live.raw.jsonl`: +For later raw intervals that did not form a strict reduced-row prefix, the +historical workflow captured raw QEMU rows and ran the locator directly on +`qemu.live.raw.jsonl`. Both programs in this preserved command are absent, and +there is no supported current procedure: + + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. ```bash bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ @@ -69,27 +90,30 @@ python3 tools/chisel/find_replay_liq_qemu_candidates.py \ --input generated//traces/qemu.live.raw.jsonl \ --output generated//report/replay_liq_qemu_candidates.json ``` +Provenance: source commit 39902e672a8c1fb75a0eeb02b5280c12a89935b3. + -Useful filters: +The deleted locator accepted these filters: -- `--min-second-row ` ignores early candidates whose later memory row is +- `--min-second-row ` ignored early candidates whose later memory row was before `n`. -- `--max-second-row ` caps the later memory row. -- `--exact-overlap-only` drops same-line-only candidates. -- `--no-dedupe-pairs` shows repeated dynamic instances of the same PC/address +- `--max-second-row ` capped the later memory row. +- `--exact-overlap-only` dropped same-line-only candidates. +- `--no-dedupe-pairs` showed repeated dynamic instances of the same PC/address pair. -- `--self-test` runs the built-in synthetic store/load overlap check. +- `--self-test` ran the built-in synthetic store/load overlap check. -Wrapper sampling knobs: +The deleted wrapper accepted these sampling knobs: -- `--qemu-skip-rows ` discards filtered QEMU rows before writing the bounded - capture. It is allowed only with `--qemu-only`. -- `--qemu-raw-only` exits after raw QEMU capture and skips the reduced-row - extractor. It is for arbitrary skipped intervals whose first row may not be a - strict sequential reduced prefix. +- `--qemu-skip-rows ` discarded filtered QEMU rows before writing the bounded + capture. It was allowed only with `--qemu-only`. +- `--qemu-raw-only` exited after raw QEMU capture and skipped the reduced-row + extractor. It supported arbitrary skipped intervals whose first row might + not be a strict sequential reduced prefix. -For repeated later-window probes, use the interval scanner instead of -hand-written shell loops: +For repeated later-window probes, the historical workflow used the interval +scanner instead of hand-written shell loops. The scanner is absent and has no +supported current equivalent: ```bash python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ @@ -101,55 +125,63 @@ python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ --max-seconds 60 ``` -The scanner writes one subdirectory per skip interval, preserves each wrapper -stdout/stderr log, runs the locator on `qemu.live.raw.jsonl`, and emits +Historical command provenance: source commit +`462b359a5bd6620585ea14d7706e70345345bc74`. + +The scanner wrote one subdirectory per skip interval, preserved each wrapper +stdout/stderr log, ran the locator on `qemu.live.raw.jsonl`, and emitted `report/interval_scan_summary.json` with schema -`linxcore.replay_liq_qemu_interval_scan.v1`. Its output has the same claim -boundary as the locator: skipped raw QEMU intervals are candidate hints only. -If the wrapped QEMU command leaves a complete raw trace but does not return, -the scanner records `wrapper_timed_out=true`, terminates the wrapper process -group, and still runs the locator on the complete bounded trace. -Use `--skip-range START:STOP:STEP` for inclusive non-adjacent sweeps; repeated -ranges are appended to explicit `--skips` and duplicate offsets are removed -while preserving first occurrence order. The summary includes aggregate +`linxcore.replay_liq_qemu_interval_scan.v1`. Its output had the same claim +boundary as the locator: skipped raw QEMU intervals were candidate hints only. +If the wrapped QEMU command left a complete raw trace but did not return, the +scanner recorded `wrapper_timed_out=true`, terminated the wrapper process +group, and still ran the locator on the complete bounded trace. +`--skip-range START:STOP:STEP` represented inclusive non-adjacent sweeps; +repeated ranges were appended to explicit `--skips`, and duplicate offsets were +removed while preserving first-occurrence order. The summary included aggregate `load_interval_count`, `candidate_interval_count`, `first_load_interval`, and -`first_candidate_interval` fields so agents can tell whether a sweep found a +`first_candidate_interval` fields so agents could tell whether a sweep found a usable phase without hand-inspecting every per-interval report. -The JSON report schema is -`linxcore.replay_liq_qemu_candidate_locator.v1`. Its `claim_boundary` field is -part of the contract: candidate output is not QEMU/DUT proof. R617 adds +The JSON report used schema +`linxcore.replay_liq_qemu_candidate_locator.v1`. Its `claim_boundary` field was +part of the contract: candidate output was not QEMU/DUT proof. R617 added `row_space` and per-candidate `probe_hint` fields. `probe_hint.pc_filter` -contains a PC-range preflight fragment, but PC filtering can select an earlier -dynamic occurrence of the same PC range. Run the QEMU-only wrapper with the -candidate's `expected_memory_pcs.args` before spending generated-RTL time on -that range. `probe_hint.raw_dynamic_window` is only QEMU-only dynamic-window -reproduction; skipped raw rows are not generated-RTL replacement evidence. +contained a PC-range preflight fragment, but PC filtering could select an +earlier dynamic occurrence of the same PC range. The historical workflow ran +the QEMU-only wrapper with the candidate's `expected_memory_pcs.args` before +spending generated-RTL time on that range. `probe_hint.raw_dynamic_window` was +only QEMU-only dynamic-window reproduction; skipped raw rows were not +generated-RTL replacement evidence. That preflight workflow has no supported +current equivalent. ## Logic Design -The locator parses rows with `mem_valid=1` into memory events: +The locator parsed rows with `mem_valid=1` into memory events: - row index and cycle, - PC and instruction bits, - load/store class, - byte address, size, cacheline, and memory data. -For each later memory event, it scans prior memory events within -`--lookback-rows` and records: +For each later memory event, it scanned prior memory events within +`--lookback-rows` and recorded: - `store_before_load`: possible STQ lookup/forwarding/wait-store candidate, - `load_before_store`: possible store-arrival MDB conflict candidate. -Candidates score exact byte overlap highest, then same-cacheline reuse, then -short row distance. Default output deduplicates repeated dynamic instances by -kind, PC pair, and address/cacheline pair so the top list is suitable for +Candidates scored exact byte overlap highest, then same-cacheline reuse, then +short row distance. Default output deduplicated repeated dynamic instances by +kind, PC pair, and address/cacheline pair so the top list was suitable for window selection. ## R612 Evidence R612 ran a QEMU-only CoreMark capture: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --build-dir generated/r612-coremark-qemu-memory-candidates-16384 \ @@ -160,6 +192,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ -nographic -monitor none -machine virt -m 1280M \ -kernel tests/benchmarks/build/coremark_real.elf ``` +Provenance: source commit 7e2931bc6550ccf344b6d367e672f978381dca58. + The reducer produced 16,250 expected rows. Locator results: @@ -169,18 +203,22 @@ The reducer produced 16,250 expected rows. Locator results: rows `1585 -> 1589`, PCs `0x4000d7e6 -> 0x4000d7f2`, address `0x4ffefb68`; - after-row-4096 scan: 868 memory events, all stores, zero candidates. -This is negative later-window evidence for the first 16K-row prefix. The next -natural CoreMark replay-LIQ search should not simply widen the same early -prefix by a small factor; it needs a way to skip into a later load-bearing -phase, locate a different direct-boot interval, or return to focused replay -fixtures for positive replacement evidence. +This was negative later-window evidence for the first 16K-row prefix. The +historical conclusion was that the next natural CoreMark replay-LIQ search +should not simply widen the same early prefix by a small factor; it needed a +way to skip into a later load-bearing phase, locate a different direct-boot +interval, or return to focused replay fixtures. The deleted search workflow +has no supported current equivalent. ## R613 Evidence -R613 adds `--qemu-skip-rows` and `--qemu-raw-only` to -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh`. +R613 added `--qemu-skip-rows` and `--qemu-raw-only` to the now-deleted +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` Provenance: source commit 39902e672a8c1fb75a0eeb02b5280c12a89935b3. . -The non-QEMU-only guard rejects skipped captures: +The non-QEMU-only guard rejected skipped captures: + + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. ```bash bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ @@ -188,8 +226,10 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --expected-rows 0 --capture-rows 8 \ --qemu-skip-rows 1 ``` +Provenance: source commit 39902e672a8c1fb75a0eeb02b5280c12a89935b3. + -The wrapper exits with: +The wrapper exited with: ```text error: --qemu-skip-rows is allowed only with --qemu-only @@ -197,6 +237,9 @@ error: --qemu-skip-rows is allowed only with --qemu-only A raw skipped sample after the R611 boundary: + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. + ```bash bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ --build-dir generated/r613-coremark-qemu-raw-skip4096-sample \ @@ -208,16 +251,22 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ -nographic -monitor none -machine virt -m 1280M \ -kernel tests/benchmarks/build/coremark_real.elf ``` +Provenance: source commit 39902e672a8c1fb75a0eeb02b5280c12a89935b3. + Result: 512 raw rows were captured after 4096 skipped rows. The locator found -37 memory events, all stores, zero loads, and zero candidates. This confirms -the R612 post-4096 store-only shape with a smaller interval artifact and gives -future agents a cheap loop for later interval sampling. +37 memory events, all stores, zero loads, and zero candidates. This confirmed +the R612 post-4096 store-only shape with a smaller interval artifact and gave +later work a cheap loop for interval sampling while the wrapper still existed. +There is no supported current equivalent for that loop. ## R614 Evidence -R614 adds `tools/chisel/scan_replay_liq_qemu_intervals.py` and manually samples -larger skipped CoreMark intervals before closing the packet: +R614 added the now-deleted `tools/chisel/scan_replay_liq_qemu_intervals.py` and +manually sampled larger skipped CoreMark intervals before closing the packet: + + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. ```bash bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ @@ -230,6 +279,8 @@ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ -nographic -monitor none -machine virt -m 1280M \ -kernel tests/benchmarks/build/coremark_real.elf ``` +Provenance: source commit 462b359a5bd6620585ea14d7706e70345345bc74. + The same command shape was repeated for skip offsets 65,536 and 262,144. Each interval captured 2,048 raw rows. Locator results: @@ -240,17 +291,18 @@ interval captured 2,048 raw rows. Locator results: | `generated/r614-coremark-qemu-raw-skip65536-sample` | 146 | 146 | 0 | 0 | `0x40006310` | | `generated/r614-coremark-qemu-raw-skip262144-sample` | 146 | 146 | 0 | 0 | `0x40006310` | -This is additional negative interval-selection evidence. It does not supersede -R611 generated-RTL/QEMU no-regression evidence and does not prove replay-LIQ -behavior. The next agent should either run a broader QEMU-only scanner sweep -with non-adjacent skips to find a load-bearing phase, or return to the focused -replay fixtures that already produce positive retained physical-bundle -sidebands. +This was additional negative interval-selection evidence. It did not supersede +R611 generated-RTL/QEMU no-regression evidence and did not prove replay-LIQ +behavior. The historical follow-up proposed either a broader QEMU-only scanner +sweep with non-adjacent skips or a return to focused replay fixtures. The +scanner and specialized fixture wrapper are now absent, with no supported +current equivalent. ## R615 Evidence -R615 extends the scanner interface with inclusive skip ranges and aggregate -summary fields, then runs a bounded non-adjacent sweep: +R615 extended the now-deleted scanner interface with inclusive skip ranges and +aggregate summary fields, then ran a bounded non-adjacent sweep. The preserved +command is historical and is not runnable on the current tree: ```bash python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ @@ -264,9 +316,12 @@ python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ --stop-on-load ``` -The summary artifact is +Historical command provenance: source commit +`fd79c40af09fbc60848800e7ebd978ed0a511e36`. + +The summary artifact was `generated/r615-coremark-qemu-interval-scan/report/interval_scan_summary.json`. -It reports schema `linxcore.replay_liq_qemu_interval_scan.v1`, +It reported schema `linxcore.replay_liq_qemu_interval_scan.v1`, `scanned_interval_count=4`, `load_interval_count=0`, and `candidate_interval_count=0`. Each interval completed the bounded raw trace and timed out only at the wrapper process boundary after capture: @@ -278,15 +333,17 @@ timed out only at the wrapper process boundary after capture: | 1,572,864 | 256 | 18 | 18 | 0 | 0 | | 2,097,152 | 256 | 18 | 18 | 0 | 0 | -This is still candidate-location evidence only. The broader sampled CoreMark -steady-state intervals do not expose natural replay-LIQ load clusters, so the -next positive-proof packet should return to focused replay fixtures unless a -new QEMU-only interval-selection hypothesis is being tested. +This was still candidate-location evidence only. The broader sampled CoreMark +steady-state intervals did not expose natural replay-LIQ load clusters. The +historical recommendation was to return to focused replay fixtures unless a +new QEMU-only interval-selection hypothesis was being tested; those deleted +flows have no supported current equivalent. ## R617 Evidence -R617 annotates locator candidates with raw-row probe hints. Re-running the R612 -reduced-preview candidate scan with the matching raw trace: +R617 annotated locator candidates with raw-row probe hints. It reran the R612 +reduced-preview candidate scan with the matching raw trace using this now- +deleted command: ```bash python3 tools/chisel/find_replay_liq_qemu_candidates.py \ @@ -297,13 +354,16 @@ python3 tools/chisel/find_replay_liq_qemu_candidates.py \ --lookback-rows 1024 ``` -The top R612 reduced-preview candidate remains the exact store-before-load pair -at PCs `0x4000d7e6 -> 0x4000d7f2`, address `0x4ffefb68`, but it now carries +Historical command provenance: source commit +`e6830114f23594e1883479ec9377e93e0ce0068e`. + +The top R612 reduced-preview candidate remained the exact store-before-load pair +at PCs `0x4000d7e6 -> 0x4000d7f2`, address `0x4ffefb68`, and it carried `probe_hint.raw_dynamic_window.args = ["--qemu-skip-rows", "1715", -"--capture-rows", "6"]`. This matters because the candidate's reduced rows -`1585 -> 1589` are not raw row offsets. +"--capture-rows", "6"]`. This mattered because the candidate's reduced rows +`1585 -> 1589` were not raw row offsets. -The matching QEMU-only scanner gate: +The matching QEMU-only scanner gate used this now-deleted command: ```bash python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ @@ -320,21 +380,26 @@ python3 tools/chisel/scan_replay_liq_qemu_intervals.py \ --stop-on-candidate ``` -It reports one interval, one load-bearing interval, and one candidate-bearing -interval. The per-interval candidate report repeats the absolute raw dynamic +Historical command provenance: source commit +`e6830114f23594e1883479ec9377e93e0ce0068e`. + +It reported one interval, one load-bearing interval, and one candidate-bearing +interval. The per-interval candidate report repeated the absolute raw dynamic window `--qemu-skip-rows 1715 --capture-rows 6`. R617 also ran a PC-filter preflight on `0x4000d7e6..0x4000d7f3` with expected store PC `0x4000d7e6` and expected load PC `0x4000d7f2`. That preflight failed -because the first dynamic occurrence of the PC range does not include the load. -Do not convert this candidate into a generated-RTL CoreMark run by PC filter -alone; first find a stateful unskipped capture strategy or prove a QEMU-only -expected-memory-PC preflight for the exact generated-RTL command shape. +because the first dynamic occurrence of the PC range did not include the load. +The historical conclusion did not authorize converting this candidate into a +generated-RTL CoreMark run by PC filter alone; it required a stateful unskipped +capture strategy or a QEMU-only expected-memory-PC preflight for the exact +generated-RTL command shape. No supported current equivalent implements that +preflight. ## R618 Context Pack -R618 adds a separate context-pack validator rather than changing the locator -claim. Run: +R618 added a separate context-pack validator rather than changing the locator +claim. The following deleted-tool commands were the historical invocation: ```bash python3 tools/chisel/build_replay_liq_selector_context_pack.py @@ -342,28 +407,37 @@ python3 tools/chisel/build_replay_liq_selector_context_pack.py \ --validate-only generated/r618-replay-liq-selector-context-pack/report/replay_liq_selector_context_pack.json ``` -The manifest combines R611 zero-natural CoreMark no-regression evidence, R616 -positive focused selector-origin proof, and the R617 raw-window hint. It is -valid only if those remain distinct: the R617 raw dynamic window is an +Historical command provenance: source commit +`8f7892f827cbb39a7b2938ec5e2af52b2b005747`. + +The manifest combined R611 zero-natural CoreMark no-regression evidence, R616 +positive focused selector-origin proof, and the R617 raw-window hint. It was +valid only if those remained distinct: the R617 raw dynamic window was an address-cluster hint, not generated-RTL/DUT replay-LIQ proof. ## R619 Probe Plan -R619 adds a command planner on top of the R618 context pack: +R619 added a command planner on top of the R618 context pack. The planner is +now absent, and this command remains historical evidence only: ```bash python3 tools/chisel/plan_replay_liq_selector_probe.py --print-commands ``` -The planner emits QEMU-only preflight commands for the raw window and PC-filter -forms, each guarded by the expected store/load PCs. It also emits -`generated_rtl.status = "blocked"`. This is the required handoff shape until a -future packet proves that the exact generated-RTL command shape has a passing -QEMU-only expected-memory-PC preflight. +Historical command provenance: source commit +`aa56ffe1089eae8bd4a148012fd5fe017b700863`. + +The planner emitted QEMU-only preflight commands for the raw-window and +PC-filter forms, each guarded by the expected store/load PCs. It also emitted +`generated_rtl.status = "blocked"`. This was the required handoff shape until a +future packet proved that the exact generated-RTL command shape had a passing +QEMU-only expected-memory-PC preflight. No supported current planner replaces +it. ## R620 Preflight Evidence -R620 runs the safe preflights and records the results: +R620 ran the safe preflights and recorded the results with this now-deleted +report builder: ```bash python3 tools/chisel/build_replay_liq_selector_preflight_report.py @@ -371,16 +445,19 @@ python3 tools/chisel/build_replay_liq_selector_preflight_report.py \ --validate-only generated/r620-replay-liq-selector-preflight-report/report/replay_liq_selector_preflight_report.json ``` -The raw skipped-window QEMU-only preflight passes with 6 raw rows, 5 reduced +Historical command provenance: source commit +`7db7cb38e7b965ccff1e5341a6c4440373a4b91b`. + +The raw skipped-window QEMU-only preflight passed with 6 raw rows, 5 reduced preview rows, store PC `0x4000d7e6`, load PC `0x4000d7f2`, and memory address -`0x4ffefb68`. The PC-filter form captures zero rows in the fresh bounded run, -so the report keeps generated RTL blocked. This reinforces the same boundary: -the raw window is a reproducible QEMU candidate hint, not DUT replay-LIQ proof. +`0x4ffefb68`. The PC-filter form captured zero rows in the fresh bounded run, +so the report kept generated RTL blocked. This reinforced the same boundary: +the raw window was a reproducible QEMU candidate hint, not DUT replay-LIQ proof. ## R621 Unskipped Prefix Evidence -R621 proves that the R617 top candidate can be reached without skipped QEMU -rows and records the generated-RTL boundary: +R621 proved that the R617 top candidate could be reached without skipped QEMU +rows and recorded the generated-RTL boundary with now-deleted tools: ```bash python3 tools/chisel/find_replay_liq_qemu_candidates.py \ @@ -394,23 +471,27 @@ python3 tools/chisel/build_replay_liq_selector_unskipped_prefix_report.py \ --validate-only generated/r621-replay-liq-selector-unskipped-prefix-report/report/replay_liq_selector_unskipped_prefix_report.json ``` -The unskipped QEMU-only preflight captures 1721 raw rows and reduces 1590 -preview rows. The top candidate remains the exact store-before-load pair +Historical command provenance: source commit +`9061ca3a8e8810938b25c054a94b19ef0349dcef`. + +The unskipped QEMU-only preflight captured 1721 raw rows and reduced 1590 +preview rows. The top candidate remained the exact store-before-load pair `0x4000d7e6 -> 0x4000d7f2` at address `0x4ffefb68`, rows `1585 -> 1589`, -score 1186. The matching unskipped generated-RTL/QEMU CoreMark prefix passes +score 1186. The matching unskipped generated-RTL/QEMU CoreMark prefix passed with 1169 compared rows, zero mismatches, and zero QEMU/DUT CBSTOP rows, and -the generated-RTL preview contains the same target pair. +the generated-RTL preview contained the same target pair. -This is the first safe generated-RTL command shape for the candidate, but the -sideband counters still report zero natural replay-LIQ/MDB activity: +This was the first safe generated-RTL command shape for the candidate, but the +sideband counters still reported zero natural replay-LIQ/MDB activity: `liq_alloc_accepted=0`, `replay_queue_out_fire=0`, `lret_w2_slot_accepted=0`, -`w2_promotion_live=0`, selector-from-promotion/probe counters are zero, and -MDB fanout/record counters are zero. Treat R621 as candidate-present +`w2_promotion_live=0`, selector-from-promotion/probe counters were zero, and +MDB fanout/record counters were zero. R621 therefore remained candidate-present no-regression coverage, not replay-LIQ replacement proof. ## R622 Activation Gap Report -R622 records why R621 does not activate replay-LIQ: +R622 recorded why R621 did not activate replay-LIQ with this now-deleted report +builder: ```bash python3 tools/chisel/build_replay_liq_activation_gap_report.py @@ -418,24 +499,31 @@ python3 tools/chisel/build_replay_liq_activation_gap_report.py \ --validate-only generated/r622-replay-liq-activation-gap-report/report/replay_liq_activation_gap_report.json ``` -The report consumes the R621 unskipped-prefix report plus the R621 generated-RTL -sideband stats. It classifies the run as memory-path active but pre-ResolveQ: +Historical command provenance: source commit +`1ef0a899cbadc187292014804aea2e7df6f29524`. + +The report consumed the R621 unskipped-prefix report plus the R621 generated-RTL +sideband stats. It classified the run as memory-path active but pre-ResolveQ: `load_lookup_valid=180`, `store_stq_resident=512`, and store dequeue counters -are nonzero, while `resident_store_eligible=0`, +were nonzero, while `resident_store_eligible=0`, `load_lookup_execute_with_eligible_store=0`, `load_lookup_execute_with_wait_store=0`, `resolve_queue_push_accepted=0`, `resolve_queue_valid=0`, `mdb_conflict_valid=0`, `wait_replay_capture_accepted=0`, and `liq_alloc_accepted=0`. -The next generated-RTL replay-LIQ proof attempt must first find or construct a -run where `load_lookup_execute_with_eligible_store > 0`; otherwise QEMU -store/load address clusters remain commit-stream hints rather than live -resident-store overlap stimuli. +The historical conclusion required a later generated-RTL replay-LIQ proof +attempt to find or construct a run where +`load_lookup_execute_with_eligible_store > 0`; otherwise QEMU store/load +address clusters remained commit-stream hints rather than live resident-store +overlap stimuli. The deleted report flow has no supported current equivalent. ## R623 Focused Eligible-Store Proof -R623 constructs the missing eligible-store stimulus on the focused replay -fixture and records the proof boundary: +R623 constructed the missing eligible-store stimulus on the focused replay +fixture and recorded the proof boundary: + + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. ```bash LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1 \ @@ -456,9 +544,11 @@ python3 tools/chisel/build_replay_liq_eligible_store_proof_report.py python3 tools/chisel/build_replay_liq_eligible_store_proof_report.py \ --validate-only generated/r623-replay-liq-eligible-store-proof-report/report/replay_liq_eligible_store_proof_report.json ``` +Provenance: source commit 7f2e4bccd85a69a2d432a02107f0c5af36c27dcd. + -The generated-RTL/QEMU run passes with 18 compared rows, zero mismatches, and -zero QEMU/DUT CBSTOP rows. Sideband counters prove the focused activation +The generated-RTL/QEMU run passed with 18 compared rows, zero mismatches, and +zero QEMU/DUT CBSTOP rows. Sideband counters proved the focused activation chain: `load_lookup_execute_with_eligible_store=18`, `load_lookup_execute_with_wait_store=12`, `resident_store_eligible=18`, `resolve_queue_push_accepted=8`, `resolve_queue_valid=66`, @@ -467,14 +557,16 @@ chain: `load_lookup_execute_with_eligible_store=18`, `replay_queue_out_fire=6`, `lret_w2_slot_accepted=6`, and `w2_promotion_live=5`. -Treat R623 as current-head focused-fixture replay-LIQ activation proof. It does -not replace the R621/R622 CoreMark boundary: natural CoreMark replacement still -requires the same nonzero activation counters in a CoreMark or natural workload -generated-RTL run. +R623 was focused-fixture replay-LIQ activation proof at its cited source commit. +It did not replace the R621/R622 CoreMark boundary: natural CoreMark replacement +still required the same nonzero activation counters in a CoreMark or natural +workload generated-RTL run. The specialized proof command is not supported on +the current tree. ## R624 Activation Artifact Scan -R624 adds a cheap scanner for existing generated sideband artifacts: +R624 added a cheap scanner for existing generated sideband artifacts. The +scanner is now absent, and these commands are historical only: ```bash python3 tools/chisel/scan_replay_liq_activation_artifacts.py @@ -482,18 +574,21 @@ python3 tools/chisel/scan_replay_liq_activation_artifacts.py \ --validate-only generated/r624-replay-liq-activation-artifact-scan/report/replay_liq_activation_artifact_scan.json ``` -The current report scans 34 local sideband artifacts. It finds 17 artifacts -with the full activation counter chain positive, but all 17 are classified as -focused/synthetic; `coremark_positive_count=0`. Treat this as triage, not new -proof. After each CoreMark or natural generated-RTL run, rerun the scanner and -promote only artifacts whose workload class is CoreMark/natural and whose -eligible-store, ResolveQ, MDB, LIQ, replay-output, and W2-promotion counters -are all nonzero. +Historical command provenance: source commit +`ce89429592645e6160530a72e3a213e1a07e7206`. + +The R624 report scanned 34 local sideband artifacts. It found 17 artifacts with +the full activation counter chain positive, but all 17 were classified as +focused/synthetic; `coremark_positive_count=0`. This was triage, not new proof. +The historical procedure reran the scanner after each CoreMark or natural +generated-RTL run and promoted only artifacts with the required nonzero +counters. No supported current scanner performs that triage. ## R625 Natural Activation Probe Plan -R625 expands the unskipped CoreMark candidate handoff and records why the -current PC-filter surfaces should stay out of Verilator: +R625 expanded the unskipped CoreMark candidate handoff and recorded why its +PC-filter surfaces were excluded from Verilator. The following locator and +planner commands are no longer runnable: ```bash python3 tools/chisel/find_replay_liq_qemu_candidates.py \ @@ -507,24 +602,28 @@ python3 tools/chisel/build_replay_liq_natural_activation_probe_plan.py \ --validate-only generated/r625-replay-liq-natural-activation-probe-plan/report/replay_liq_natural_activation_probe_plan.json ``` -The expanded report has 91 candidates and 12 narrow exact store-before-load -candidates. The known top candidate PC filter remains blocked by R620 -(`pc_filter_status=empty`). R625 samples three more narrow PC filters: -`0x400055f2..0x40005645` is empty, while `0x40005682..0x40005701` and -`0x400055b6..0x40005601` each capture 32 QEMU rows but fail reduced-row -extraction before a legal expected preview is produced. Treat those PC filters -as blocked launch shapes. +Historical command provenance: source commit +`fc4bd24bab84273139a4be417f025aef2febbc7b`. + +The expanded report had 91 candidates and 12 narrow exact store-before-load +candidates. The known top candidate PC filter remained blocked by R620 +(`pc_filter_status=empty`). R625 sampled three more narrow PC filters: +`0x400055f2..0x40005645` was empty, while `0x40005682..0x40005701` and +`0x400055b6..0x40005601` each captured 32 QEMU rows but failed reduced-row +extraction before a legal expected preview was produced. Those PC filters were +blocked launch shapes. -The next natural-workload proof path must not rerun Verilator on blocked PC -filters. It needs one of: checkpoint/state replay for skipped raw windows, a -legal natural workload shard whose unskipped prefix reaches eligible-store -overlap from reset, or a QEMU-only PC-filter preflight that first passes both -reduced-row extraction and exact memory-PC guards. +The historical conclusion prohibited rerunning Verilator on the blocked PC +filters. It required checkpoint/state replay for skipped raw windows, a legal +natural workload shard whose unskipped prefix reached eligible-store overlap +from reset, or a QEMU-only PC-filter preflight that passed both reduced-row +extraction and exact memory-PC guards. No supported current tool supplies that +workflow. ## R626 PC-Filter Preflight Search and Failed RTL Attempt -R626 adds an automated QEMU-only search over narrow exact store-before-load -CoreMark candidates: +R626 added an automated QEMU-only search over narrow exact store-before-load +CoreMark candidates. Its search and report-builder scripts are now absent: ```bash python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ @@ -539,33 +638,36 @@ python3 tools/chisel/build_replay_liq_pc_filter_activation_report.py \ --validate-only generated/r626-replay-liq-pc-filter-activation-report/report/replay_liq_pc_filter_activation_report.json ``` -The first scanned candidate passes the QEMU-only guard: -`0x4000d7e6..0x4000d7f3` captures 6 raw rows, reduces 5 preview rows, and -contains the expected store/load PCs `0x4000d7e6 -> 0x4000d7f2`. This only -authorizes spending Verilator time on the same shape; it is not replay-LIQ +Historical command provenance: source commit +`c4f05d865e8185cbaed47fe3c981b674da2be883`. + +The first scanned candidate passed the QEMU-only guard: +`0x4000d7e6..0x4000d7f3` captured 6 raw rows, reduced 5 preview rows, and +contained the expected store/load PCs `0x4000d7e6 -> 0x4000d7f2`. This only +authorized spending Verilator time on the same shape; it was not replay-LIQ proof. -The matching generated-RTL attempt reaches the guarded row and fails before -`crosscheck_manifest.json` or sideband stats are emitted. The saved stderr at +The matching generated-RTL attempt reached the guarded row and failed before +`crosscheck_manifest.json` or sideband stats were emitted. The saved stderr at `generated/r626-coremark-pc-filter-4000d7e6-4000d7f2-rtl-xcheck-abs/report/generated-rtl-attempt.stderr.txt` -records a first-row dst/wb mismatch: PC and instruction match -(`0x4000d7e6`, `0x02a50041`), QEMU expects `(rd=1, value=1342110568)`, and the -DUT reports `(rd=1, value=18446744073709551608)`. Treat this as a -generated-RTL failure classification packet, not natural CoreMark replay-LIQ -activation proof. +recorded a first-row dst/wb mismatch: PC and instruction matched +(`0x4000d7e6`, `0x02a50041`), QEMU expected `(rd=1, value=1342110568)`, and the +DUT reported `(rd=1, value=18446744073709551608)`. This was a generated-RTL +failure classification packet, not natural CoreMark replay-LIQ activation +proof. ## R627 PC-Filter State-Seed Audit -R627 turns the R626 failure into a pre-Verilator audit in +R627 turned the R626 failure into a pre-Verilator audit in the now-deleted `tools/chisel/search_replay_liq_pc_filter_preflights.py` schema v2. The scanner -now keeps two decisions separate: +kept two decisions separate: - QEMU-only trial status: did the PC filter produce a legal reduced preview with the expected memory PCs? - generated-RTL readiness: does the first non-skipped reduced row expose enough source state for the Verilator harness to preload architectural RF state? -Running the same top candidate: +The same top candidate was run with this historical command: ```bash python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ @@ -577,18 +679,21 @@ python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ --stop-on-pass ``` -produces `status=pass` for the QEMU-only trial but -`generated_rtl.status="blocked"`. The first reduced row is +Historical command provenance: source commit +`fbf25256828963960e14744a04214f53dbc44a43`. + +That run produced `status=pass` for the QEMU-only trial but +`generated_rtl.status="blocked"`. The first reduced row was `pc=0x4000d7e6`, `insn=0x02a50041`, `mem_valid=1`, `dst_valid=1`, -`src0_valid=0`, and `src1_valid=0`, so the harness cannot reconstruct the -hidden register state needed to start the reduced top at that PC. Future -agents must require `state_seed_audit.status="ready"` before promoting any -PC-filter preflight to generated RTL. +`src0_valid=0`, and `src1_valid=0`, so the harness could not reconstruct the +hidden register state needed to start the reduced top at that PC. The +historical promotion rule required `state_seed_audit.status="ready"` before a +PC-filter preflight could advance to generated RTL. ## R628 Full Narrow PC-Filter State-Seed Scan -R628 runs the v2 scanner over all 12 narrow exact store-before-load candidates -from the R625 expanded CoreMark report: +R628 ran the v2 scanner over all 12 narrow exact store-before-load candidates +from the R625 expanded CoreMark report. The scanner is absent today: ```bash python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ @@ -599,23 +704,26 @@ python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ --max-seconds 20 ``` -The report records `trial_count=12`, `pass_count=1`, +Historical command provenance: source commit +`c5537a72e2f0a1ba2d10b21a4c6558f3ea0bcfb6`. + +The report recorded `trial_count=12`, `pass_count=1`, `state_seed_ready_count=0`, and `generated_rtl.status="blocked"`. The top -candidate is QEMU-pass but RF-state insufficient; the other 11 candidates -capture QEMU rows but produce `preview_rows=0`, so reduced-row extraction fails -before memory-PC or RF-state readiness can be proven. This closes the current +candidate was QEMU-pass but RF-state insufficient; the other 11 candidates +captured QEMU rows but produced `preview_rows=0`, so reduced-row extraction +failed before memory-PC or RF-state readiness could be proven. This closed the 12-candidate narrow PC-filter path for generated RTL. -The scanner now supports `--stop-on-generated-ready`, which stops only when a -passing QEMU-only trial also has `state_seed_audit.status="ready"`. Use that -mode for future broader PC-filter searches; do not use a plain QEMU pass as a -generated-RTL launch authorization. +The scanner supported `--stop-on-generated-ready`, which stopped only when a +passing QEMU-only trial also had `state_seed_audit.status="ready"`. That was the +historical mode for broader PC-filter searches; a plain QEMU pass did not +authorize a generated-RTL launch. There is no supported current equivalent. ## R629 RF-Seeded PC-Filter Replay -R629 adds an explicit RF seed artifact path for PC-filter launches that pass -QEMU memory-PC guards but start after hidden predecessor state. Build the seed -for the top R617/R621 candidate from the unfiltered R621 raw prefix: +R629 added an explicit RF seed artifact path for PC-filter launches that passed +QEMU memory-PC guards but started after hidden predecessor state. It built the +seed for the top R617/R621 candidate from the unfiltered R621 raw prefix: ```bash python3 tools/chisel/build_frontend_fetch_rf_seed.py \ @@ -626,13 +734,21 @@ python3 tools/chisel/build_frontend_fetch_rf_seed.py \ --validate-only generated/r629-coremark-pc-filter-rf-seed/rf_seed.jsonl ``` -The seed contains 17 reduced GPR rows and records -`source_corrections=1`; the launch-critical row is `x1=0x4ffefb70`, which lets +Historical command provenance: source commit +`dc38d2b8dd6e07338517543d306c2da5aae14feb`. + +The seed contained 17 reduced GPR rows and recorded +`source_corrections=1`; the launch-critical row was `x1=0x4ffefb70`, which let the first PC-filtered store produce QEMU's expected `rd1/mem_addr=0x4ffefb68`. -The direct live-QEMU wrapper was flaky for this narrow PC-filter during R629 -and sometimes timed out with zero captured rows. Use the scanner-owned passing -raw trace as the replay source for generated RTL: +The direct live-QEMU wrapper was flaky for this narrow PC filter during R629 +and sometimes timed out with zero captured rows. The historical workflow used +the scanner-owned passing raw trace as the replay source for generated RTL. +Both the scanner and downstream replay wrapper are absent today, and there is +no supported current equivalent: + + +> Historical evidence only; this preserved pre-cutover command has no current runnable equivalent. Its cited artifact and commit provenance remain the evidence; do not use it as a current procedure. ```bash python3 tools/chisel/search_replay_liq_pc_filter_preflights.py \ @@ -655,20 +771,24 @@ FETCH_DISABLE_STORE_MEMORY_MUTATION=1 \ FETCH_RF_SEED=generated/r629-coremark-pc-filter-rf-seed/rf_seed.jsonl \ bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh ``` +Provenance: source commit dc38d2b8dd6e07338517543d306c2da5aae14feb. + -The generated-RTL replay passes the neutral comparator: +The generated-RTL replay passed the neutral comparator: `generated/r629-coremark-pc-filter-seeded-trace-replay/report/crosscheck_manifest.json` -reports `compared_rows=3`, `mismatch_count=0`, and zero QEMU/DUT CBSTOP rows. -This proves the R626 first-row RF launch-state mismatch is fixed for the top -PC filter. It is not replay-LIQ activation proof: sideband stats in the same -report still have zero eligible-store, ResolveQ, MDB, LIQ allocation, +reported `compared_rows=3`, `mismatch_count=0`, and zero QEMU/DUT CBSTOP rows. +This proved that the R626 first-row RF launch-state mismatch was fixed for the +top PC filter at the cited source commit. It was not replay-LIQ activation +proof: sideband stats in the same report still had zero eligible-store, +ResolveQ, MDB, LIQ allocation, replay-output, and row-mutation counters. The next natural CoreMark packet -must use RF seeding only as launch infrastructure and still require positive -replay-LIQ sideband counters. +was required to use RF seeding only as launch infrastructure and still require +positive replay-LIQ sideband counters. ## R630 Seeded Raw-Window Scanner -R630 adds an end-to-end seeded generated-RTL scanner for candidate windows: +R630 added an end-to-end seeded generated-RTL scanner for candidate windows. +The scanner is now absent, and the following invocation is historical only: ```bash python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ @@ -680,29 +800,33 @@ python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ --validate-only generated/r630-replay-liq-qemu-seeded-window-scan/report/seeded_window_scan.json ``` -The scanner consumes the R625 candidate report and the R621 unfiltered raw -trace by default. For each raw dynamic-window hint, it builds an RF seed before -`qemu_skip_rows`, slices the raw window, runs -`run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` with +Historical command provenance: source commit +`1a6f9f893de0ecece52fe3fa54eb29dccd47ab66`. + +The scanner consumed the R625 candidate report and the R621 unfiltered raw +trace by default. For each raw dynamic-window hint, it built an RF seed before +`qemu_skip_rows`, sliced the raw window, ran +historical evidence only (no current runnable equivalent): `run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` Provenance: source commit 1a6f9f893de0ecece52fe3fa54eb29dccd47ab66. with `FETCH_REDUCED_STORE_REPLAY_LIQ=1`, `FETCH_DISABLE_STORE_MEMORY_MUTATION=1`, -and `FETCH_RF_SEED=`, then records both +and `FETCH_RF_SEED=`, then recorded both `crosscheck_manifest.json` and `frontend_fetch_rf_alu_sideband_stats.json`. -The first R630 trial replays the top R617/R621 candidate -(`skip=1715`, `rows=6`). It produces a 17-register RF seed with one source -correction and passes the generated-RTL comparator with `compared_rows=3`, -`mismatch_count=0`, and zero CBSTOP rows. The report still classifies the trial +The first R630 trial replayed the top R617/R621 candidate +(`skip=1715`, `rows=6`). It produced a 17-register RF seed with one source +correction and passed the generated-RTL comparator with `compared_rows=3`, +`mismatch_count=0`, and zero CBSTOP rows. The report classified the trial as `compare_pass_no_activation` because every required replay-LIQ activation -counter remains zero, including eligible-store overlap, ResolveQ, MDB fanout, -LIQ allocation, replay output, and W2 promotion. Use this scanner for broader -seeded-window searches; do not treat a seeded comparator pass as replay-LIQ -replacement evidence unless `activation_positive_count > 0`. +counter remained zero, including eligible-store overlap, ResolveQ, MDB fanout, +LIQ allocation, replay output, and W2 promotion. The historical workflow used +this scanner for broader seeded-window searches and did not treat a seeded +comparator pass as replay-LIQ replacement evidence unless +`activation_positive_count > 0`. No supported current scanner replaces it. ## R631 Resumed Seeded-Window Sweep -R631 adds `--skip-windows ` to -`tools/chisel/scan_replay_liq_qemu_seeded_windows.py` so an agent can resume -after already-classified eligible windows: +R631 added `--skip-windows ` to the now-deleted +`tools/chisel/scan_replay_liq_qemu_seeded_windows.py` so a scan could resume +after already-classified eligible windows. This command is historical only: ```bash python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ @@ -713,12 +837,15 @@ python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ --wrapper-timeout-seconds 420 ``` -The resumed sweep covers the next three small R625 windows after the R630 top +Historical command provenance: source commit +`f0b1369128ea386fce8bf9d6c79addcb6b5381f0`. + +The resumed sweep covered the next three small R625 windows after the R630 top case. `generated/r631-replay-liq-qemu-seeded-window-scan-next3/report/seeded_window_scan.json` -records `activation_positive_count=0` and `compare_pass_count=2`. Window 1 -(`skip=1591`, `rows=29`) fails before manifest generation because the expected -rows require conflicting initial RF data for `reg=1`. A focused rerun with the -updated classifier: +recorded `activation_positive_count=0` and `compare_pass_count=2`. Window 1 +(`skip=1591`, `rows=29`) failed before manifest generation because the expected +rows required conflicting initial RF data for `reg=1`. A focused rerun used +the updated classifier through this historical command: ```bash python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ @@ -729,18 +856,22 @@ python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ --wrapper-timeout-seconds 420 ``` -reports `status="rf_source_conflict"` for that window. Windows 2 and 3 -(`skip=1659`, `rows=14`; `skip=1660`, `rows=19`) pass the generated-RTL +Historical command provenance: source commit +`f0b1369128ea386fce8bf9d6c79addcb6b5381f0`. + +The rerun reported `status="rf_source_conflict"` for that window. Windows 2 +and 3 +(`skip=1659`, `rows=14`; `skip=1660`, `rows=19`) passed the generated-RTL comparator with 12 and 15 compared rows, zero mismatches, and zero CBSTOP rows, -but all required replay-LIQ activation counters remain zero. The next seeded -search should start at `--skip-windows 4` or deliberately include larger -capture windows; the first four eligible R625 windows are not replay-LIQ -activation proof. +but all required replay-LIQ activation counters remained zero. The historical +follow-up was to start at `--skip-windows 4` or deliberately include larger +capture windows; the first four eligible R625 windows were not replay-LIQ +activation proof. That follow-up is unsupported on the current tree. ## R632 Larger Seeded-Window Sweep -R632 resumes from the next two larger R625 windows after the first four -classified windows: +R632 resumed from the next two larger R625 windows after the first four +classified windows. The preserved scanner commands are not currently runnable: ```bash python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ @@ -753,12 +884,15 @@ python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ --validate-only generated/r632-replay-liq-qemu-seeded-window-scan-next2-large/report/seeded_window_scan.json ``` -The report records zero compare-passing or activation-positive trials. Window 4 -(`skip=1525`, `rows=109`) is classified as `rf_source_conflict`: the reduced -expected rows require conflicting initial RF data for `reg=1`, so one scalar RF -seed cannot describe the skipped launch state. Window 5 (`skip=1286`, +Historical command provenance: source commit +`4f5461cea238ee5d47a482c6d39431add7463f50`. + +The report recorded zero compare-passing or activation-positive trials. Window +4 (`skip=1525`, `rows=109`) was classified as `rf_source_conflict`: the reduced +expected rows required conflicting initial RF data for `reg=1`, so one scalar +RF seed could not describe the skipped launch state. Window 5 (`skip=1286`, `rows=124`) initially failed before manifest generation because `C.SDI` read an -empty U0 local source. A focused classifier rerun: +empty U0 local source. A focused classifier rerun used this historical command: ```bash python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ @@ -769,10 +903,14 @@ python3 tools/chisel/scan_replay_liq_qemu_seeded_windows.py \ --wrapper-timeout-seconds 900 ``` -records `status="local_source_missing"` in +Historical command provenance: source commit +`4f5461cea238ee5d47a482c6d39431add7463f50`. + +The rerun recorded `status="local_source_missing"` in `generated/r632-replay-liq-qemu-seeded-window-local-source-missing/report/seeded_window_scan.json`. -This proves the current scalar RF seed path is still insufficient for skipped -windows that consume hidden T/U local source state. The first six eligible R625 -windows now provide no replay-LIQ activation proof. The next seeded scan can -resume at `--skip-windows 6`, but larger windows with local-source dependencies -should wait for an explicit local T/U checkpoint or seed boundary. +This proved that the scalar RF seed path at the time was insufficient for +skipped windows that consumed hidden T/U local source state. The first six +eligible R625 windows provided no replay-LIQ activation proof. The historical +next step was to resume at `--skip-windows 6`, while larger windows with local- +source dependencies awaited an explicit local T/U checkpoint or seed boundary. +No supported current seeded scanner or local-state replay equivalent exists. diff --git a/docs/chisel/verification/chisel-flow.md b/docs/chisel/verification/chisel-flow.md index a8a34780..77a7465f 100644 --- a/docs/chisel/verification/chisel-flow.md +++ b/docs/chisel/verification/chisel-flow.md @@ -32,19 +32,15 @@ retained training. | `brob-xcheck` | `tools/chisel/run_chisel_tests.sh --only BROB` | Run Packet C BID encoding and BROB metadata lifecycle tests. | | `commit-monitor-xcheck` | `tools/chisel/run_chisel_tests.sh --only CommitTraceMonitor` | Run Phase 1 fixed-width commit-window contract checks. | | `reduced-rob-xcheck` | `tools/chisel/run_chisel_reduced_rob_xcheck.sh` | Emit `ReducedCommitROB`, build the Verilator harness, assert commit-window monitor outputs, and compare normalized DUT rows against QEMU-shaped reference rows. | -| `top-xcheck` | `tools/chisel/run_chisel_top_xcheck.sh` | Emit the reduced `LinxCoreTop` xcheck configuration, build the same Verilator harness against top-level IO, assert monitor outputs, and compare normalized DUT rows against QEMU-shaped reference rows. | +| `frontend-trace-top-xcheck` | `tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` | Emit the canonical frontend trace top, build its Verilator harness, and compare normalized DUT rows against QEMU-shaped reference rows. Use `--dry-run` for the non-RTL dependency and argument smoke. | | `frontend-fetch-trace-top-xcheck` | `tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh` | Verification-only fixture: drive a bounded memory window through `FrontendFetchPacketSource`, the window slicer, and reduced decode/ROB; this does not prove I-F0–I-F4 or B-F0–B-F4. | | `frontend-alu-trace-top-xcheck` | `tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` | Emit `LinxCoreFrontendAluTraceTop`, build the Verilator harness, drive frontend packets through reduced scalar ALU execute, and compare nonzero writeback rows against QEMU-shaped reference rows. | | `frontend-rf-alu-trace-top-xcheck` | `tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` | Emit `LinxCoreFrontendRfAluTraceTop`, build the shared Verilator harness in RF mode, preload identity scalar registers, enqueue dependent scalar ALU rows through the reduced issue queue, and compare RF-sourced writeback rows against QEMU-shaped reference rows. | -| `frontend-fetch-rf-alu-trace-top-xcheck` | `tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` | Verification-only fixture: drive PC request/response windows through the current source/window path, reduced rename/ROB, RF-backed issue, and ALU execute; it is not production IFU pipeline evidence. | -| `frontend-fetch-rf-alu-qemu-elf-xcheck` | `tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` | Capture a bounded live QEMU commit prefix from a direct-boot ELF, validate the selected rows as the strict reduced scalar subset, pair them with `FETCH_ELF` sparse fetch memory, and run the live fetch RF/ALU generated-RTL comparator gate. | -| `frontend-fetch-rf-alu-qemu-fixture-elf` | `tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh` | Build a tiny legal-entry direct-boot ELF (`C.BSTART.STD; ADD; ADDI; C.MOVR; C.BSTOP`) and print the scalar PC filter used by the live QEMU ELF xcheck. | | `frontend-fetch-rf-alu-fixture-rows` | `tools/chisel/frontend_fetch_rf_alu_fixture_rows.py --self-test` | Validate the default QEMU-shaped expected-row fixture used when `FETCH_EXPECTED_ROWS` is unset. | | `frontend-fetch-rf-alu-qemu-rows` | `tools/chisel/frontend_fetch_rf_alu_qemu_rows.py --self-test` | Validate strict QEMU commit JSONL prefix extraction for the reduced scalar RF/ALU gate used by `FETCH_QEMU_TRACE`. | | `frontend-fetch-elf-memory` | `tools/chisel/frontend_fetch_elf_memory.py --self-test` | Validate the ELF64 little-endian PT_LOAD extractor that creates sparse address-to-byte fetch-memory images for `FETCH_ELF` runs. | | `commit-jsonl-writer` | `tools/chisel/commit_trace_jsonl.h` | Shared C++ helper used by Verilator harnesses to emit QEMU-shaped reference rows and DUT sideband rows without per-harness field spelling drift. | | `qemu-crosscheck` | `tools/chisel/run_chisel_qemu_crosscheck.sh` | Normalize QEMU and DUT commit JSONL, run the neutral comparator, and emit `crosscheck_manifest.json` tying raw traces, normalized traces, reports, QEMU binary, row counts, and git context into one evidence bundle. | -| `qemu-trace-replay-xcheck` | `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh` | Capture or consume a bounded QEMU commit JSONL prefix, replay those rows through the current Chisel commit surface in an isolated build directory, and preserve comparator manifest evidence. | The target shape follows the useful part of the OpenXiangShan flow: make Chisel generation, simulation/emulator construction, and architectural cross-checking @@ -95,7 +91,7 @@ expectations from QEMU-shaped JSONL and the wrapper sizes the comparator window from that row count. R99 adds `FETCH_QEMU_TRACE`, which normalizes an existing QEMU commit JSONL and extracts a strict sequential reduced-scalar prefix into the expected-row stream. R100 adds -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh`, which captures a +The now-deleted historical fetch/RF/ALU QEMU wrapper captured a bounded live QEMU prefix from a direct-boot ELF, optionally filters the scalar PC range after the legal entry block header, and runs the same `FETCH_ELF` plus `FETCH_QEMU_TRACE` comparator path. Chisel now owns packet creation, F4 diff --git a/docs/chisel/verification/qemu-crosscheck.md b/docs/chisel/verification/qemu-crosscheck.md index ccad8526..766d10ee 100644 --- a/docs/chisel/verification/qemu-crosscheck.md +++ b/docs/chisel/verification/qemu-crosscheck.md @@ -1,71 +1,51 @@ # QEMU Cross-Check Adapter -## Purpose +## Current Contract -Phase 0B creates the neutral commit-row path before the full Chisel core exists. -The adapter lets Chisel, pyCircuit, and QEMU traces flow into the existing -`tools/trace/crosscheck_qemu_linxcore.py` comparator without baking producer -details into the comparator itself. +The supported generated-RTL comparison entrypoint is +`tools/chisel/run_chisel_frontend_trace_top_xcheck.sh`. It emits +`LinxCoreFrontendTraceTop`, builds `tools/chisel/frontend_trace_top_tb.cpp`, +produces QEMU-shaped reference and DUT JSONL, and calls the neutral +`tools/chisel/run_chisel_qemu_crosscheck.sh` comparator. -## Partial sideband on harness failure - -When the generated-RTL trace harness exhausts its bounded commit wait, it -still writes the requested `--sideband-stats` JSON before exiting nonzero. The -partial report is diagnostic evidence only; it must not be used as a passing -comparison result, but it preserves LIQ/LRET event counts needed to locate a -stalled ownership boundary. - -The fetch/RF/ALU driver also samples the commit monitor immediately after each -drain tick. A legal two-wide retirement can expose the following completed ROB -row only after that edge; collecting only before the next expected-row advance -would silently omit it and create a false QEMU/DUT divergence. The pending -commit queue therefore remains the sole source of comparator order, but it is -filled both before and after a drain edge. +Displaced reduced-top, trace-replay, fetch/RF/ALU, and fixture-builder wrappers +were deleted. Historical evidence that names them is not a current command +contract and must not be copied into a gate. ## Tools +- `tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` +- `tools/chisel/frontend_trace_top_tb.cpp` - `tools/chisel/commit_trace_jsonl.h` - `tools/chisel/trace_schema_adapter.py` - `tools/chisel/run_chisel_qemu_crosscheck.sh` -- `tools/chisel/run_chisel_reduced_rob_xcheck.sh` -- `tools/chisel/run_chisel_top_xcheck.sh` -- `tools/chisel/run_chisel_trace_replay_xcheck.sh` -- `tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh` -- `tools/chisel/run_chisel_frontend_trace_top_lint.sh` -- `tools/chisel/run_chisel_frontend_trace_top_xcheck.sh` -- `tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh` -- `tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh` -- `tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh` -- `tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` -- `tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` -- `tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh` -- `tools/chisel/frontend_fetch_rf_alu_qemu_rows.py` - `tools/trace/crosscheck_qemu_linxcore.py` ## Evidence Manifest -For non-dry-run comparisons, `run_chisel_qemu_crosscheck.sh` now writes -`crosscheck_manifest.json` next to the comparator reports. The manifest schema -is `linxcore.chisel.crosscheck_manifest.v1` and records: +The common comparator writes `crosscheck_manifest.json` beside its normalized +traces and reports. The manifest records raw and normalized inputs, selected +row bounds, mismatch status, first divergence, and repository provenance. +Failure still emits a manifest, so a nonzero result remains diagnosable but is +never passing evidence. + +## Current Gates -- selected QEMU binary, -- raw QEMU and DUT trace paths, -- normalized QEMU and DUT trace paths, -- comparator report paths, -- row counts, mismatch count, first mismatch, and CBSTOP inflation summary, -- `max_commits` plus the raw `normalize_rows` window used before metadata - filtering, -- `rtl/LinxCore` and superproject `HEAD` plus dirty flags. +```bash +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh --dry-run +python3 tools/chisel/check_crosscheck_wrapper_dependencies.py +python3 tools/chisel/trace_schema_adapter.py --self-test +bash tools/chisel/run_chisel_frontend_trace_top_lint.sh +bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh +``` -The wrapper preserves the comparator exit status after writing the manifest. -On a mismatch, the manifest is still emitted with `status: "fail"` so agents -can archive the complete evidence bundle before debugging the first -divergence. +The `--dry-run` gate is intentionally non-RTL: it validates the canonical +emitter object, emitted top name, C++ harness binding, and exact common +cross-check arguments without invoking SBT, FIRRTL/CIRCT, or Verilator. ## Normalized Fields -The adapter emits the mandatory commit fields currently required by the -QEMU/LinxCore comparator: +The adapter requires the architectural commit fields: ```text pc insn len wb_valid wb_rd wb_data @@ -76,389 +56,13 @@ mem_valid mem_is_store mem_addr mem_wdata mem_rdata mem_size trap_valid trap_cause traparg0 next_pc ``` -It also preserves sideband fields when present: `seq`, `cycle`, `slot`, `bid`, -`gid`, `rid`, `rob_valid`, `rob_wrap`, `rob_value`, `block_bid_valid`, and -`block_bid`. - -For nested Chisel rows, the adapter accepts `identity.bid`, `identity.gid`, -`identity.rid`, `rob.valid`, `rob.wrap`, `rob.value`, `blockBidValid`, -`blockBid`, `mem.isStore`, `trap.arg0`, and `nextPc`. Rows with `valid: 0` are -filtered before sequence numbering so a fixed-width commit vector can be dumped -without creating false comparator rows. - -## Shared C++ Writer - -Generated-RTL Verilator harnesses should emit commit JSONL through -`tools/chisel/commit_trace_jsonl.h` instead of open-coding JSON strings. The -helper owns two wire formats: - -- `write_qemu_commit_jsonl`: architectural fields only, matching the QEMU - commit trace shape in `target/linx/helper.c` and the trace-manager plugin. -- `write_dut_commit_jsonl`: the same architectural fields plus fixed-width - Chisel sidebands: `valid`, `seq`, `cycle`, `slot`, `bid/gid/rid`, - `rob_valid/rob_wrap/rob_value`, `block_bid_valid`, and `block_bid`. - -Harness-specific code still owns how it reads Verilated pins and how it builds -expected rows. The shared writer only owns spelling, default zeros, and boolean -encoding. This preserves the LinxCoreModel split between 32-bit -`CommitInfo(bid,gid,rid)` identity and the 64-bit hardware `block_bid` while -future live Chisel tops are wired into the same neutral comparator path. - -## QEMU Binary Selection - -`run_chisel_qemu_crosscheck.sh` uses this priority: - -1. explicit `QEMU=...` -2. `emulator/qemu/build-linx/qemu-system-linx64` -3. legacy `emulator/qemu/build/qemu-system-linx64` - -## Gates - -```bash -bash tools/chisel/run_chisel_qemu_crosscheck.sh --dry-run -python3 tools/chisel/trace_schema_adapter.py --self-test -bash tools/chisel/run_chisel_reduced_rob_xcheck.sh -bash tools/chisel/run_chisel_top_xcheck.sh -bash tools/chisel/run_chisel_trace_replay_xcheck.sh -bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh --dry-run -bash tools/chisel/run_chisel_frontend_trace_top_lint.sh -bash tools/chisel/run_chisel_frontend_trace_top_xcheck.sh -bash tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh -bash tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh -bash tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh -bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r100-live-qemu-fixture -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf \ - --expected-rows 3 --capture-rows 3 --pc-lo 0x10002 --pc-hi 0x1000b \ - --max-seconds 5 -bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh --out-dir generated/r101-live-qemu-fixture -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --elf generated/r101-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf \ - --expected-rows 0 --capture-rows 5 --allow-block-markers \ - --max-seconds 5 -``` - -For first-pass scalar-load ownership, the generated-RTL wrapper accepts -`--reduced-store-live-load-liq`. It selects the distinct -`LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop`, where an E1 load -must allocate in LIQ before its LRET/W1/W2 completion. Use the existing -reduced-store/replay-LIQ options only for their respective harnesses: all four -top selections are mutually exclusive. A bounded live-load run must retain -the manifest and sideband statistics and show LIQ allocation plus launch -before it is treated as evidence of the new owner. - -`VERILATOR_BUILD_JOBS` controls the Verilator `--build-jobs` value used by the -fetch/RF/ALU runner. It defaults to `0` (Verilator auto-parallelism); set an -explicit positive value only when host contention requires a lower bound. - -`run_chisel_trace_replay_xcheck.sh` is the bridge between synthetic reduced -smokes and a live QEMU/CoreMark window. It accepts a flat or nested commit -JSONL with `--input-trace`, normalizes it through `trace_schema_adapter.py`, -replays the bounded row stream through the `LinxCoreTop` commit export in a -Verilator harness, and compares the resulting DUT JSONL against the same rows -as QEMU-shaped reference data. When `--input-trace` is omitted it generates a -four-row fixture covering writeback, store, load, and trap envelopes. - -`run_chisel_qemu_trace_replay_xcheck.sh` is the QEMU-facing replay bridge. In -`--elf` mode it first runs `tools/qemu/run_qemu_commit_trace.sh` to collect a -QEMU JSONL trace, then runs `run_chisel_trace_replay_xcheck.sh` in -`generated/chisel-qemu-trace-replay-xcheck`. In `--qemu-trace` mode it skips -QEMU execution and replays an existing QEMU JSONL trace. Both paths preserve -the comparator `crosscheck_manifest.json` under the isolated report directory. -The bridge first normalizes a wider raw window, then slices the replay input to -the smallest prefix that contains the requested number of non-metadata -architectural rows. This keeps QEMU BSTART/template/control metadata from -starving the compare window while avoiding extra DUT tail rows after the -bounded compare point. -Metadata filtering must not drop non-sequential control rows. Side-effect-free -macro/template rows are treated as metadata only when `next_pc == pc + len`; -rows such as `FRET.STK` carry architectural redirect evidence through -`next_pc` and must remain in the compare stream. - -In `--elf` mode, `--replay-rows` also bounds the raw QEMU prefix collected from -the FIFO before the wrapper stops QEMU. If QEMU exits before opening or -producing the FIFO, the reader is killed and the wrapper must fail with an -empty-trace error rather than hanging. Direct-boot CoreMark-style ET_DYN images -currently carry physical load segments at `0x40000000`, while the Linx QEMU -`virt` machine defaults to 128 MiB of RAM. Use an explicit memory argument for -that class of ELF: - -`tools/qemu/run_qemu_commit_trace.sh --max-seconds N` is a hard wall-clock -limit on every supported host. It uses `timeout`/`gtimeout` when available and -otherwise starts QEMU in a Python-owned process group, sends `SIGTERM`, then -escalates to `SIGKILL` after two seconds. A timed-out producer returns `124`; -bounded-prefix callers may retain already captured rows, but must never leave a -QEMU process running because a host lacks GNU coreutils. - -```bash -bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh \ - --build-dir generated/r91-coremark-elf-prefix \ - --elf tests/benchmarks/build/coremark_real.elf \ - --max-commits 4 \ - --replay-rows 128 \ - --max-seconds 10 \ - -- -nographic -monitor none -machine virt -m 1280M \ - -kernel tests/benchmarks/build/coremark_real.elf -``` - -R91 evidence for that command captured 128 raw QEMU rows, sliced 5 replay rows -containing 4 architectural commits, and passed the Chisel replay cross-check -with `compared_rows: 4` and `mismatch_count: 0`. - -The common wrapper exposes the same distinction directly: - -```bash -bash tools/chisel/run_chisel_qemu_crosscheck.sh \ - --qemu-trace \ - --dut-trace \ - --max-commits 4 \ - --normalize-rows 8 -``` - -`--max-commits` is the architectural compare window. `--normalize-rows` is the -raw row window presented to schema normalization before comparator metadata -filtering. - -For bounded windows, comparator length handling is metadata-aware. If QEMU and -DUT both terminate after the same metadata-filtered architectural prefix before -`--max-commits`, the compare passes; this is the expected shape for finite -expected-row files that still contain side-effect-free marker/sysreg metadata. -The comparator still fails if the DUT has extra architectural rows or if QEMU -has remaining architectural rows while the DUT ended before the requested -bounded window. - -QEMU-row replay gate: - -```bash -bash tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh \ - --elf \ - --max-commits 32 \ - --max-seconds 30 -``` - -Reduced live-QEMU ELF gate: - -```bash -bash tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh \ - --out-dir generated/r100-live-qemu-fixture -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --elf generated/r100-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf \ - --expected-rows 3 \ - --capture-rows 3 \ - --pc-lo 0x10002 \ - --pc-hi 0x1000b \ - --max-seconds 5 -``` - -This gate captures a bounded QEMU JSONL prefix through a FIFO, validates the -selected rows with `frontend_fetch_rf_alu_qemu_rows.py`, extracts the same ELF -PT_LOAD bytes with `FETCH_ELF`, and compares the live fetch RF/ALU DUT rows -through the common manifest-producing comparator. The PC range skips the legal -entry `BSTART` for now; block-header execution is a later DUT feature. QEMU -termination after the bounded rows are captured is expected only when the -manifest reports `status: "pass"`. - -R101 adds the reduced block-marker form: - -```bash -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --elf generated/r101-live-qemu-fixture/frontend_fetch_rf_alu_qemu_fixture.elf \ - --expected-rows 0 \ - --capture-rows 5 \ - --allow-block-markers \ - --max-seconds 5 -``` - -`--allow-block-markers` passes legal `BSTART`/`BSTOP` rows through the -expected-row stream as `skip` entries. The Verilator harness fetches and -decodes them, asserts the reduced marker diagnostics, and requires no ROB -allocation or issue enqueue for those rows. The comparator receives only the -non-skip scalar architectural rows. R101 evidence captured five raw QEMU rows -for `C.BSTART; ADD; ADDI; C.MOVR; C.BSTOP`, compared three scalar commits, -and produced a manifest with `status: "pass"`, `compared_rows: 3`, and -`mismatch_count: 0`. - -R500 adds a QEMU/reducer-only stop point for fixture validation: - -```bash -bash tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh \ - --build-dir generated/r500-replay-loop-qemu-only \ - --fixture replay-ldi-sdi-ldi-loop \ - --qemu-only \ - --expect-load-pcs 0x10002,0x1000a,0x10002,0x1000a \ - --expect-store-pcs 0x10006,0x10006 \ - --max-seconds 8 -``` - -`--qemu-only` still builds the requested fixture, captures the bounded QEMU -FIFO prefix, and runs `frontend_fetch_rf_alu_qemu_rows.py`, but exits before -the Verilator harness and does not emit a QEMU/DUT -`crosscheck_manifest.json`. Treat this as stimulus/reducer evidence only. The -R500 replay-loop run captured 12 raw QEMU rows, reduced them to 10 preview -rows, and proved the repeated memory sequence needed by later MDB wait-plan -work: load PCs `0x10002,0x1000a,0x10002,0x1000a`, store PCs -`0x10006,0x10006`, with legal skip rows -`0x10000->0x10002`, `0x1000e->0x10014`, `0x10014->0x10000`, and -`0x10000->0x10002`. - -R501 makes the replay-loop stimulus proof self-checking by adding -`--expect-load-pcs` and `--expect-store-pcs` to the same wrapper. These -options compare the reduced preview's exact memory PC sequence before any -optional RTL run and print the observed load/store PC lists on success. - -Full compare gate, once a Chisel commit trace exists: - -```bash -bash tools/chisel/run_chisel_qemu_crosscheck.sh \ - --qemu-trace \ - --dut-trace \ - --report-dir \ - --max-commits 1000 -``` - -Expected report outputs: - -```text -/qemu.normalized.jsonl -/dut.normalized.jsonl -/crosscheck_report.json -/crosscheck_report.md -/crosscheck_mismatches.json -/crosscheck_manifest.json -``` +It also preserves fixed DUT identity sidebands when present. The shared C++ +writer owns field spelling and default values; harnesses own only their pin to +row projection. -## Current Status +## Proof Boundary -The adapter, shared C++ commit JSONL writer, wrapper, typed Chisel commit-row -bundles, reduced ROB Verilator smoke, reduced top Verilator smoke, top trace -replay smoke, QEMU trace replay bridge, -frontend-window trace-top Verilator lint, frontend-window trace-top Verilator -xcheck, live frontend fetch trace-top Verilator xcheck, frontend-window ALU -trace-top Verilator xcheck, RF-backed ALU trace-top Verilator xcheck, live -frontend fetch RF-backed ALU trace-top Verilator xcheck, and reduced live -QEMU ELF fetch RF/ALU xcheck are ready. The common -wrapper emits a machine-readable `crosscheck_manifest.json` for generated-RTL -comparisons and future full QEMU-vs-DUT windows. -`run_chisel_reduced_rob_xcheck.sh` and `run_chisel_top_xcheck.sh` currently -compare three Verilator-produced rows with zero mismatches. -`run_chisel_trace_replay_xcheck.sh` proves that a normalized external commit -row stream can drive the top-level commit observation surface and pass the same -comparator. `run_chisel_qemu_trace_replay_xcheck.sh` can feed archived or fresh -QEMU rows into that same replay path while the live Chisel top is still being -connected. `run_chisel_frontend_trace_top_xcheck.sh` drives raw frontend -packets containing scalar `ADD`, `ADDI`, and compressed move rows through -`LinxCoreFrontendTraceTop`, uses the explicit completion surrogate to retire -the allocated ROB rows, dumps DUT JSONL, and compares three rows against a -QEMU-shaped reference with zero mismatches. -`run_chisel_frontend_fetch_trace_top_xcheck.sh` drives a bounded instruction -window fixture through `FrontendFetchPacketSource`, the legacy window slicer, -and the reduced -decode/ROB path in `LinxCoreFrontendFetchTraceTop`, uses the explicit -completion surrogate to retire allocated ROB rows, and compares three rows -against a QEMU-shaped reference with zero mismatches. Its manifest under -`generated/chisel-frontend-fetch-trace-top-xcheck/report` records -`status: "pass"`, `compared_rows: 3`, and `mismatch_count: 0`. -`run_chisel_frontend_alu_trace_top_xcheck.sh` drives the same reduced frontend -smoke through `LinxCoreFrontendAluTraceTop`, replaces the completion surrogate -with `ReducedScalarAluExecute`, and compares three rows with nonzero source, -destination, and writeback data against QEMU-shaped reference rows with zero -mismatches. `run_chisel_frontend_rf_alu_trace_top_xcheck.sh` drives dependent -scalar rows through `LinxCoreFrontendRfAluTraceTop`, preloads only identity RF -registers, enqueues rows through the reduced issue queue before draining -commits, reads later sources from Chisel physical RF writeback state, and -compares three rows with zero mismatches. Its report directory now includes a -manifest with `status: "pass"`, `compared_rows: 3`, and `mismatch_count: 0`. -`run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh` drives the same -dependent scalar smoke through `LinxCoreFrontendFetchRfAluTraceTop`, replaces -testbench-supplied frontend packets with a live PC request/response source, -serves instruction bytes from a `FETCH_MEMORY_BIN`, `FETCH_MEMORY_HEX`, or -`FETCH_ELF` image, reads expected PC/length/source/writeback rows from -QEMU-shaped JSONL selected by `FETCH_EXPECTED_ROWS`, and preserves RF-backed -reduced issue and ALU completion. When `FETCH_EXPECTED_ROWS` is unset, the -wrapper emits `fixture.expected.jsonl` and sizes `--max-commits` from the -expected row count. It can also derive that expected-row stream from an -existing QEMU commit JSONL with `FETCH_QEMU_TRACE`; the helper writes -`qemu.expected.jsonl` only after validating a strict sequential reduced-scalar -prefix (`ADD`, `ADDI`, `C.MOVI`, or `C.MOVR`, scalar GPRs only, no memory or -trap side effects). -Its manifest under -`generated/chisel-frontend-fetch-rf-alu-trace-top-xcheck/report` records -`status: "pass"`, `compared_rows: 3`, and `mismatch_count: 0`. -`run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh` captures the legal-entry -fixture ELF through live QEMU, either filters the scalar prefix after -`BSTART` or preserves `BSTART`/`BSTOP` as reduced skip rows, runs the R99/R101 -row reducer plus R97 sparse ELF memory path, and passes with `status: "pass"`, -`compared_rows: 3`, and `mismatch_count: 0` under -`generated/chisel-frontend-fetch-rf-alu-qemu-elf-xcheck/report`. -Dense packets and non-ALU row enrichment remain later packets. -The admitted-marker CoreMark path has a clean 6000-row scale baseline under -`generated/r227-row-order-6000-marker-qemu-elf-xcheck/report`. That run captures -6000 raw QEMU rows, extracts 5866 expected rows, admits and filters 728 marker -commits, normalizes 5138 QEMU/DUT rows, compares 5137 rows, and passes with -`summary.mismatch_count: 0` and no CBSTOP divergence. Its manifest records clean -LinxCore `b2684c8938b1c4cccd2638f3fcfa5363d7792104`, clean LinxCoreModel -`3c0878da3aa1e06669b718e93269f094e7244066`, and clean QEMU -`5cfb672a711bb2172bfe7de6c6b7bd1bdb47e902`; the outer superproject was dirty -only from unrelated local state. -The follow-on R228 gate under -`generated/r228-row-order-8192-marker-qemu-elf-xcheck/report` extends that -baseline to 8192 raw QEMU rows, 8058 expected rows, 885 filtered marker commits, -7173 normalized QEMU/DUT rows, and 7172 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R229 gate under -`generated/r229-row-order-12288-marker-qemu-elf-xcheck/report` extends it again -to 12288 raw QEMU rows, 12154 expected rows, 1177 filtered marker commits, -10977 normalized QEMU/DUT rows, and 10976 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R230 gate under -`generated/r230-row-order-16384-marker-qemu-elf-xcheck/report` extends it again -to 16384 raw QEMU rows, 16250 expected rows, 1470 filtered marker commits, -14780 normalized QEMU/DUT rows, and 14779 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R231 gate under -`generated/r231-row-order-24576-marker-qemu-elf-xcheck/report` extends it again -to 24576 raw QEMU rows, 24442 expected rows, 2055 filtered marker commits, -22387 normalized QEMU/DUT rows, and 22386 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R232 gate under -`generated/r232-row-order-32768-marker-qemu-elf-xcheck/report` extends it again -to 32768 raw QEMU rows, 32634 expected rows, 2640 filtered marker commits, -29994 normalized QEMU/DUT rows, and 29993 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R233 gate under -`generated/r233-row-order-49152-marker-qemu-elf-xcheck/report` extends it again -to 49152 raw QEMU rows, 49018 expected rows, 3811 filtered marker commits, -45207 normalized QEMU/DUT rows, and 45206 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R234 gate under -`generated/r234-row-order-65536-marker-qemu-elf-xcheck/report` extends it again -to 65536 raw QEMU rows, 65402 expected rows, 4981 filtered marker commits, -60421 normalized QEMU/DUT rows, and 60420 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R235 gate under -`generated/r235-row-order-98304-marker-qemu-elf-xcheck/report` extends it again -to 98304 raw QEMU rows, 98170 expected rows, 7321 filtered marker commits, -90849 normalized QEMU/DUT rows, and 90848 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R236 gate under -`generated/r236-row-order-131072-marker-qemu-elf-xcheck/report` extends it again -to 131072 raw QEMU rows, 130938 expected rows, 9662 filtered marker commits, -121276 normalized QEMU/DUT rows, and 121275 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R237 gate under -`generated/r237-row-order-196608-marker-qemu-elf-xcheck/report` extends it again -to 196608 raw QEMU rows, 196474 expected rows, 14343 filtered marker commits, -182131 normalized QEMU/DUT rows, and 182130 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The R238 gate under -`generated/r238-row-order-262144-marker-qemu-elf-xcheck/report` extends it again -to 262144 raw QEMU rows, 262010 expected rows, 19024 filtered marker commits, -242986 normalized QEMU/DUT rows, and 242985 compared rows with -`summary.mismatch_count: 0` and no CBSTOP divergence. -The QEMU trace replay bridge now has bounded live-ELF prefix evidence using -`tests/benchmarks/build/coremark_real.elf` with explicit `-m 1280M`; the -default 128 MiB QEMU run fails fast with an empty-trace error because the ELF -segment at `0x40000000` does not fit. -Full-core QEMU comparison remains blocked until the Chisel top emits live -architectural commit rows from real fetch, full issue, LSU, and recovery paths. +The canonical frontend trace top is a bounded reduced verification surface. +It is useful for frontend-packet to commit-row plumbing and comparator closure; +it is not evidence for a bootable full core, cache hierarchy, or unrestricted +QEMU/CoreMark execution. diff --git a/docs/flows/superpowers.md b/docs/flows/superpowers.md new file mode 100644 index 00000000..c58b4bb3 --- /dev/null +++ b/docs/flows/superpowers.md @@ -0,0 +1,87 @@ +# Superpowers Harness Integration + +## Contract + +LinxCore pins [obra/superpowers](https://github.com/obra/superpowers) as the +repository-local agent workflow harness. The checkout is a nested git +submodule at `tools/superpowers`; release `v6.2.0` is pinned at commit +`3dcbd5c4b48e02263fbf4a3c01e3fe4f81d584d9` under the MIT license. + +The Codex plugin registers the upstream skills with the harness. `AGENTS.md` +is the repository session-start integration point: it requires the +`using-superpowers` bootstrap before any response or action. Superpowers owns +the general development process (brainstorming, planning, TDD, debugging, +review, and branch completion). The installed `linx-core` skill remains the +domain authority for RTL ownership, BID/BROB semantics, model comparison, +generated-RTL evidence, and superproject closure. + +This is intentionally a pinned upstream checkout rather than copied skill +files. Local copies would silently drift and, without a session-start +bootstrap, would not constitute a working harness integration. + +## Initialize + +From the LinxCore repository root, use the idempotent setup wrapper: + +```bash +bash tools/setup_superpowers.sh +``` + +The wrapper performs the equivalent explicit steps: + +```bash +git submodule update --init --recursive tools/superpowers +git -C tools/superpowers describe --tags --exact-match +codex plugin marketplace add ./tools/superpowers +codex plugin add superpowers@superpowers-dev +``` + +The tag command must report `v6.2.0`, and `codex plugin list` must report +`superpowers@superpowers-dev` as installed and enabled. + +The plugin registration is stored in the user's Codex configuration, while +the marketplace source remains this repository's pinned checkout. Re-run the +wrapper after moving the checkout. The repository pin is retained so CI, +reviewers, and other supported coding agents share one auditable workflow +version. + +## Acceptance + +Static repository checks: + +```bash +test -f tools/superpowers/skills/using-superpowers/SKILL.md +git -C tools/superpowers diff --quiet +git submodule status tools/superpowers +codex plugin list | grep 'superpowers@superpowers-dev.*installed, enabled' +``` + +A new clean agent session is the behavioral acceptance gate. The first user +message below must cause `brainstorming` to be invoked before code is written: + +```text +Let's make a react todo list +``` + +For a LinxCore hardware request, the corresponding acceptance is that the +Superpowers process skill is selected first and `linx-core` is then selected +as the domain skill before repository inspection or modification. + +The 2026-07-30 clean-session acceptance passed after plugin registration: the +exact todo-list prompt announced the required Superpowers workflow and loaded +`brainstorming` before any code or scaffold action. The same test failed before +plugin registration, proving that a submodule plus passive skill files is not +sufficient. + +## Updating + +1. Review the upstream release notes and license. +2. Move `tools/superpowers` to an annotated stable release, never an + unrecorded floating branch head. +3. Update the release and commit recorded in this document. +4. Run the static and clean-session acceptance gates. +5. Commit the gitlink and documentation together. + +Set `SUPERPOWERS_DISABLE_TELEMETRY=1` when the optional visual-companion +version request is not desired. Superpowers documents that this disables its +optional telemetry without changing skill behavior. diff --git a/docs/spec/00-charter/glossary.md b/docs/spec/00-charter/glossary.md new file mode 100644 index 00000000..5199b1da --- /dev/null +++ b/docs/spec/00-charter/glossary.md @@ -0,0 +1,37 @@ +# LinxCore contract glossary + +## Box {#D-BOX-001} + + +A **box** is one of TOP, IFU, CTU, OOO, IEX, LSU, or DTU. A box owns its local +state and exposes typed transactions; it does not reach into another box's +state. + +## Transaction fire {#D-FIRE-001} + + +A transaction **fires** when both `valid` and `ready` are true in the same +cycle. A state owner may consume or allocate state only on the fire it owns. + +## Continuous prefix packet {#D-PREFIX-001} + + +A **continuous prefix packet** represents lanes `[0, count)` with lane 0 oldest. +No valid lane may appear after an invalid lane. Any mask used for observation +is derived from `count`, not maintained as independent state. + +## Instruction and micro-operation identities {#D-IDENTITY-001} + + +`bid` identifies the block context, `rid` identifies the ROB allocation, and +`uid` distinguishes micro-operations belonging to one instruction. `atag` is +the architectural register identity; `ptag`, `ttag`, and `utag` are renamed +physical or relative identities. + +## Recovery prepare and apply {#D-RECOVERY-001} + + +**Prepare** stops new affected work and collects owner acknowledgements. +**Apply** changes architectural visibility and releases or restores state. +Separating the phases prevents one owner from observing a partially recovered +machine. diff --git a/docs/spec/00-charter/scope.md b/docs/spec/00-charter/scope.md new file mode 100644 index 00000000..61d2662d --- /dev/null +++ b/docs/spec/00-charter/scope.md @@ -0,0 +1,25 @@ +# LinxCore contract scope + +## One maintained core chain {#ARC-TOP-001} + + +The maintained Chisel core MUST have one architectural path: +`TOP -> IFU -> CTU -> OOO -> IEX -> LSU`, with DTU observing the path through +explicit trace and debug interfaces. TOP is wiring and external adaptation, +not a second owner of pipeline state. + +## Linx semantics are authoritative {#ARC-TOP-002} + + +The Linx ISA manual, approved LinxCore decisions, and stable clauses in this +tree MUST define architectural behavior. External sources may contribute +mechanisms and documentation structure, but cannot introduce another ISA's +register, exception, memory, or instruction semantics. + +## Replacement evidence precedes deletion {#ARC-TOP-003} + + +An old state-owning implementation MUST remain available until its replacement +passes the required unit, adjacent integration, generated-RTL, and natural +workload gates. After equivalent evidence exists, the old owner is removed +rather than retained as a second selectable chain. diff --git a/docs/spec/10-architecture/ownership.md b/docs/spec/10-architecture/ownership.md new file mode 100644 index 00000000..b12615ac --- /dev/null +++ b/docs/spec/10-architecture/ownership.md @@ -0,0 +1,24 @@ +# State ownership + +## OOO owns architectural retirement {#ARC-TOP-020} + + +OOO MUST be the sole owner of ROB allocation, in-order commit, precise trap and +interrupt selection, and the global recovery plan. IFU, CTU, IEX, and LSU own +only their local speculative state and report completion, fault, redirect, or +recovery acknowledgement through typed transactions. + +## Rename domains remain distinct {#ARC-TOP-021} + + +RENU MUST keep absolute GPR rename state separate from relative T/U rename +state. GPR architectural tags allocate physical tags from a free list; T/U +relative indices allocate ordered tags. SMAP, CMAP, and MAPQ transitions must +be atomic for the accepted instruction prefix. + +## DTU is an observer {#ARC-TOP-022} + + +DTU MUST own debug and trace collection only. Trace backpressure cannot block +architectural commit, and DTU cannot become an alternate owner of ROB, +recovery, interrupt, or trap state. diff --git a/docs/spec/10-architecture/pipeline.md b/docs/spec/10-architecture/pipeline.md new file mode 100644 index 00000000..232da67c --- /dev/null +++ b/docs/spec/10-architecture/pipeline.md @@ -0,0 +1,33 @@ +# Main pipeline + +## IFU to CTU boundary {#ARC-TOP-030} + + +IFU MUST deliver D1 packets containing instructions expanded to the common +64-bit representation plus complete fetch and prediction identity. CTU handles +template-block, FENTRY, and FEXIT expansion and writes ordinary or expanded +micro-operation candidates into the instruction buffer. + +## OOO covers D1 through S1 {#ARC-TOP-031} + + +OOO MUST cover D1 decode, D2 ROB reservation and backpressure, D2-to-D3 rename, +D3 early completion, and D3-to-S1 dispatch. Decode normalizes 16-, 32-, 48-, +and 64-bit encodings to one uop shape carrying `bid`, `rid`, opcode, +source/destination validity and tags, and prediction metadata. + +## Dispatch targets typed queues {#ARC-TOP-032} + + +Dispatch MUST classify uops into typed IEX or LSU destinations before one +atomic prefix fire. ALU, BRU, AGU, STD, system/multicycle, and CMD resources +remain distinguishable; CMD uses its own issue queue. LSU exposes two load and +two store paths in the default profile. + +## Precise recovery crosses owners explicitly {#ARC-TOP-033} + + +Recovery MUST use complete instruction identity and explicit prepare/apply +transactions across all affected state owners. Redirect, trap, interrupt, and +debug causes converge on OOO arbitration, while each box performs only its +local flush, rollback, or cancellation. diff --git a/docs/spec/10-architecture/top.md b/docs/spec/10-architecture/top.md new file mode 100644 index 00000000..7bad25cd --- /dev/null +++ b/docs/spec/10-architecture/top.md @@ -0,0 +1,28 @@ +# TOP architecture + +## TOP is a typed router {#ARC-TOP-010} + + +TOP MUST instantiate the configured boxes, connect their typed interfaces, and +adapt external memory, interrupt, reset, and debug ports. TOP MUST NOT own ROB +entries, rename maps, issue queues, cache policy, age selection, commit policy, +or recovery arbitration. + +The callable `TOP` contains exactly one IFU, CTU, OOO, IEX, LSU, and DTU in one +clock/reset domain. It contains no `Reg`, `Mem`, or `Queue`, and IEX has no +direct control path to IFU. Recovery reaches IFU only from its OOO owner. + +## Box interfaces have one source of truth {#ARC-TOP-011} + + +All cross-box Bundle definitions and complete box IO definitions MUST live +under `linxcore/top/interface`. A generated interface manifest and executable +shape tests must describe the same elaborated types. + +## Principal widths share one parameter hierarchy {#ARC-TOP-012} + + +IFU, CTU, OOO, and IEX widths MUST be derived from a centralized parameter +profile supporting 2, 4, 6, and 8 lanes. Resource counts that are not lane +widths, including execution-pipe and LSU-pipe counts, remain explicit +parameters with validated defaults. diff --git a/docs/spec/20-behavior/commit-trap.md b/docs/spec/20-behavior/commit-trap.md new file mode 100644 index 00000000..6cffd618 --- /dev/null +++ b/docs/spec/20-behavior/commit-trap.md @@ -0,0 +1,35 @@ +# Commit, trap, interrupt, and debug behavior + +## Keep commit selection in OOO {#CMT-001} + + +OOO MUST select one ordered commit prefix and coordinate ROB, rename, BROB, +and PC-buffer release on the same accepted transaction. TOP and DTU MUST only +route or observe the selected transaction. Trace readiness MUST NOT qualify +commit acceptance. + +## Halt at a precise commit boundary {#CMT-002} + + +OOO MUST retain an accepted halt request until the requested STID reaches a +precise commit boundary. A synchronous fault at that boundary MUST take +priority. When the debug action is accepted, OOO MUST report a typed Debug +trap, stop later commits, and return the matching debug response. Resume MUST +clear the OOO-owned halted state; DTU MUST own no copy of that state. + +## Commit-control mechanism {#MEC-CMT-001} + + +`linxcore.ooo.CommitControl` owns commit/trap/interrupt/debug selection and the +halted bit. Its interrupt arbitration first qualifies requests against the ROB +boundary STID. `linxcore.dtu.DebugControl` only transports the typed request +and response. + +## Commit-control verification {#VER-CMT-001} + + +`CommitControlDebugSpec` MUST prove normal commit, synchronous-fault priority, +precise interrupt selection, halt at a commit boundary, and resume in one +bounded control harness. `RecoveryIntegrationSpec` MUST prove the same +contracts across the integration fixtures. `DTUSpec` MUST prove that DTU has +no commit or recovery authority. diff --git a/docs/spec/20-behavior/ctu.md b/docs/spec/20-behavior/ctu.md new file mode 100644 index 00000000..7c6bda94 --- /dev/null +++ b/docs/spec/20-behavior/ctu.md @@ -0,0 +1,81 @@ +# CTU behavior + +## Preserve ordinary instruction transfer {#CTU-001} + + +CTU MUST transfer every non-template instruction as one `Encoded64` +front-end operation without changing its instruction identity, PC, raw +64-bit container, length, fetch fault, or prediction metadata. + +## Describe template children from the canonical catalog {#CTU-002} + + +CTU MUST recognize template parents from the generated opcode catalog and +emit one ordered, non-recursive `TemplateUop` description for each canonical +child. Every child MUST retain the complete architectural parent and MUST +carry its zero-based ordinal, total child count, row kind, and row-specific +immediate. An unsupported or malformed template range MUST NOT create a +partial child sequence. + +## Retain the D1 stream across backpressure {#CTU-003} + + +CTU MUST preserve program order across parents, template children, input +packets, and output packets. Its Instruction Buffer MUST retain all accepted +operations until OOO accepts them, present at most the configured +`ctuOutputWidth` oldest operations as one continuous prefix, and keep that +prefix stable while OOO is not ready. OOO readiness MUST NOT form a +combinational path to IFU readiness. + +## Apply recovery only at the terminal phase {#CTU-004} + + +CTU MUST retain and echo a recovery prepare transaction without mutating its +packet, expansion, trace, or Instruction Buffer state. A matching apply MUST +remove retained work for the target STID before any such work can transfer; +unrelated STIDs MUST keep their relative order. A matching abort MUST release +the fence without changing retained work. + +## Keep backend allocation outside CTU {#CTU-005} + + +CTU MUST NOT allocate or duplicate ROB, BROB, rename-map, issue-queue, or LSU +state. Its template children are descriptions that continue through OOO +D1/D2 validation before D3 performs one backend reservation decision. + +## Template recipe mechanism {#MEC-CTU-001} + + +`TemplateDecode` filters the generated opcode catalog for FENTRY, FEXIT, and +the two return-template forms. It derives the inclusive architectural +register range from the encoded start and end fields, including wrap from +register 23 to register 2. `TemplateExpand` reuses the canonical template row +definition: + +- FENTRY emits validation, stack subtract, one store per range member, then + the final parent row. +- FEXIT emits validation, stack add, one load per range member, then the final + parent row. +- The return forms add their required target validation, target publication, + stack update, restore, and final rows around the ordered load sequence. + +The parent raw container remains attached to every child so OOO can validate +the recipe rather than trusting a CTU-local decode copy. + +## Retained buffer mechanism {#MEC-CTU-002} + + +`InstructionBuffer` stores each operation in one valid slot together with a +monotonic 64-bit enqueue order. It selects the oldest valid entries for the +D1 prefix, allocates new input only from pre-cycle free slots, and therefore +does not bypass dequeue readiness into enqueue readiness. Recovery invalidates +only slots whose retained parent STID matches the accepted plan; remaining +orders are not rewritten. + +## CTU trace mechanism {#MEC-CTU-003} + + +CTU emits one retained pipeline trace packet when the first child chunk of a +template parent enters the Instruction Buffer. The event carries the parent +identity, PC, parent opcode, and total child count. Trace backpressure may +hold the first child chunk but MUST NOT duplicate it. diff --git a/docs/spec/20-behavior/dtu.md b/docs/spec/20-behavior/dtu.md new file mode 100644 index 00000000..0fff01a6 --- /dev/null +++ b/docs/spec/20-behavior/dtu.md @@ -0,0 +1,44 @@ +# DTU behavior + +## Observe without controlling retirement {#DTU-001} + + +DTU MUST accept commit and trace observations without owning ROB, commit, +trap, interrupt, or recovery state. A stalled external trace consumer MUST NOT +backpressure commit or any observed box. DTU MAY drop a newly observed trace +packet while an older exported packet is stalled, but the retained packet MUST +remain stable until accepted. + +## Request debug control through OOO {#DTU-002} + + +DTU MUST retain an accepted debug request until the OOO control owner accepts +it. DTU MUST NOT choose a halt boundary, synthesize a recovery plan, or mutate +architectural state. The response returned by OOO MUST preserve the request +transaction identity. + +## Count observations only {#DTU-003} + + +Performance counters MUST be monotonic observations. Counter values MUST NOT +qualify commit, recovery, interrupt, debug, or trace readiness. + +## DTU mechanism {#MEC-DTU-002} + + +`linxcore.dtu.DTU` composes `DebugControl`, `TraceExport`, and +`PerformanceCounters`. `DebugControl` retains request transport only. +`TraceExport` owns one loss-tolerant output slot and keeps its observation +input ready. `PerformanceCounters` records accepted trace packets, dropped +trace packets, observed commit transactions and instructions, and accepted +debug requests. + +## DTU verification {#VER-DTU-001} + + +`DTUSpec` MUST cover stalled trace export, drop accounting, commit observation, +retained halt/resume request transport, and structural absence of recovery and +commit-control ownership inside DTU. `DTUActivationTraceSpec` MUST stall the +external trace consumer while proving live IEX terminal publication and commit +progress, accepted and dropped DTU observations, and stability of the retained +export packet. diff --git a/docs/spec/20-behavior/iex.md b/docs/spec/20-behavior/iex.md new file mode 100644 index 00000000..c1bf312b --- /dev/null +++ b/docs/spec/20-behavior/iex.md @@ -0,0 +1,97 @@ +# IEX behavior + +## Retain classed dispatch until one exact terminal fire {#IEX-001} + + +IEX MUST accept the canonical ALU, branch, load/store address, store-data, +system, and CMD dispatch classes without translating them through a reduced +issue boundary. Backpressure MUST preserve the complete transaction and its +`RobIdentity`. A completed instruction MUST update ROB resolve, every required +register-file destination, wakeup, trace, and recovery output in one atomic +terminal transaction; no consumer may observe a partial fire. + +## Allocate memory identities before LSU admission {#IEX-002} + + +IEX MUST allocate a non-reused memory transaction when a memory uop becomes +resident. One logical store shares that transaction across its STA and STD +children. A load also receives its initial attempt generation on the same +Dispatch-to-IQ acceptance edge. LSU backpressure, cancellation, and recovery +MUST NOT rewind either serial. + +The architectural P-register boot map is initialized before dispatch becomes +eligible. Every STID begins with architectural tag `n` mapped to physical tag +`n`, generation zero; no classed dispatch may observe a partially initialized +map. + +The public IEX-to-LSU boundary carries semantic identities only. Physical LIQ +or STQ indices, lease generations, and private queue rows MUST remain inside +LSU. Store reservation MUST succeed before the associated STA/STD pair becomes +eligible to issue. + +## Rebind and complete only the retained load attempt {#IEX-003} + + +IEX MUST accept load reissue, repick, cancel, launch, and result events only +for the exact retained `(RobIdentity, memory transaction, LSID, attempt +generation)` tuple. Reissue and repick advance the attempt once and may select +a new retained pipe. Stale, unknown, or skipped-generation events MUST NOT +write a register, wake a dependent uop, resolve ROB, or emit memory traffic. + +The retained replay policy is Option A: IEX owns the unchanged memory +transaction and initial attempt, while LSU authors each exact consecutive +reissue or repick attempt and atomically rebinds its existing allocation. One +accepted rebind publishes one cancel for +the old attempt and one new unique-attempt launch. Physical LIQ passes are +counted separately from unique `{transaction, attempt}` launches and from +lower-memory requests. A refill may therefore cause another physical pass for +the same new attempt without creating another attempt, cancel, or request. +Only an exact canceled predecessor with the same live row, transaction, pipe, +destination, and well-formed outcome may be consumed as stale; future, +skipped, malformed, wrong-row, wrong-transaction, and wrong-pipe returns remain +rejected and protocol-visible. + +Recovery Prepare MUST fence only the affected STID without mutation. Apply +MUST prune matching IEX metadata; Abort MUST preserve it. A peer STID remains +eligible throughout the transaction. + +## Keep system and CMD ownership separate {#IEX-004} + + +System/multicycle and CMD operations MUST remain in independent resident +queues. A system side effect requires the exact OOO head permit and exits via +`SystemIssueTxn`, which OOO forwards losslessly to TOP. CMD leaves IEX only +through `CmdIssueTxn`. Generated CMD recipes remain CMD-class, +`ENGINE_COMMAND`-capable, commit-owned, and nonspeculative; they MUST NOT be +reclassified into the System queue. For both classes, the permit, side effect, no-value ROB +resolve, execution trace, and resident-owner release MUST fire atomically. A +stalled CMD MUST +NOT block an older branch recovery, and permit withdrawal MUST prevent a head +side effect from firing. An open-current branch recovery that kills the +original closing marker MUST drain killed ROB/BROB state while retaining the +survivor PC base for a redirected-epoch closing marker; only that redirected +closure permits the PC owner to drain. A killed CMD MUST remain unable to +publish after its external sink is later released. + +## Canonical public composition {#MEC-IEX-001} + + +`linxcore.iex.IEX` is a state-free public shell around the retained +`OooIexExecutionPipeline`. The private issue queues, operand files, functional +pipelines, load metadata, and terminal rendezvous remain the sole owners of +their state. The shell projects only canonical `OOOIEXIO`, `IEXLSUIO`, CMD, +and trace transactions; OOO losslessly projects System issue to its public +side-effect boundary. + +## IEX verification {#VER-IEX-001} + + +`IEXIssueSpec`, `IEXPipesSpec`, and `IEXTerminalSpec` MUST cover stable +backpressure, complete identity retention, the W4 2-ALU/1-BRU/2-AGU/2-STD +topology, independent system/CMD queues, exact load lifecycle transitions, +continuous oldest-first terminal transport, and atomic terminal behavior. +`OOOIEXLSUActivationSpec` and the generated-RTL +activation probe MUST observe nonzero activation for every W4 execution class +before a displaced owner is deleted. The activation evidence MUST distinguish +unique attempt launches, raw LIQ passes, and lower-memory requests, and MUST +finish with zero mismatches. diff --git a/docs/spec/20-behavior/ifu.md b/docs/spec/20-behavior/ifu.md new file mode 100644 index 00000000..c8c79421 --- /dev/null +++ b/docs/spec/20-behavior/ifu.md @@ -0,0 +1,125 @@ +# IFU behavior + +## Deliver complete variable-length instructions {#IFU-001} + + +IFU MUST assemble every accepted 2-, 4-, 6-, or 8-byte instruction into one +64-bit container before transfer to CTU. The configured W2, W4, W6, or W8 +delivery width is a maximum continuous prefix; a shorter retained prefix MAY +be transferred without padding it with invalid instructions. + +## Retain exact I-SIDE miss identity {#IFU-002} + + +Every translation request, cache-line beat, refill, retry, and cross-line +continuation MUST retain a generation-qualified transaction identity. +An unmatched memory response MUST be drained as stale and MUST NOT mutate a +live translation, line fill, cache row, or fetched instruction. A denied or +corrupt instruction-line response MUST become one canonical fetch fault with +the returned error cause and MUST NOT install zero or partial data in L1I. + +## Isolate fetch geometry from CTU backpressure {#IFU-003} + + +The Fetch Buffer MUST retain accepted instructions in program order and hold +the complete visible packet stable while CTU is not ready. CTU readiness MUST +NOT form a combinational path to I-SIDE cache lookup, translation lookup, or +external memory-request readiness. + +## Apply scoped recovery after prepare {#IFU-004} + + +IFU MUST echo an accepted recovery prepare without mutating I-SIDE state. A +matching apply MUST fence IFU-to-CTU transfer, remove retained instructions for +the selected STID, redirect that STID, and reject older-epoch returns. A +matching abort MUST release the fence without removing retained instructions. + +## Join prediction before architectural delivery {#IFU-005} + + +I-SIDE and prediction MAY run independently, but an instruction MUST NOT enter +the canonical Fetch Buffer until its transaction has a final prediction +sidecar or an explicit sequential result. Later prediction correction MUST use +the same recovery path as every other IFU redirect. + +## Keep B-SIDE prediction speculative {#IFU-008} + + +B-SIDE MUST be the only IFU predictor state owner. I-SIDE and B-SIDE are +independent and non-lockstep; matching across the engines MUST use STID, +request identity, generation or epoch, and checkpoint identity. Speculative +provider order is B-F4, B-F3, B-F2, B-F1, B-F0, then sequential. Backend typed +recovery is not a prediction provider and MUST override any unpublished +prediction correction through the recovery path. + +## Leave backend identity allocation to OOO {#IFU-006} + + +IFU MUST attach architectural instruction identity, fetch epoch, prediction +checkpoint, target, and fetch-fault information. IFU and CTU MUST NOT allocate +ROB or BROB residency. OOO D1/D2 validates the encoded or template operation +and OOO D3 allocates the complete backend identity. + +## Keep trace observational {#IFU-007} + + +IFU trace backpressure MUST NOT stall instruction assembly, Fetch Buffer +dequeue, or IFU-to-CTU transfer. Once a trace packet is presented as valid it +MUST remain stable until accepted; later events MAY be dropped while that +single retained observation is blocked. + +## Parameterized retained delivery mechanism {#MEC-IFU-001} + + +The line assembler produces a dense private instruction group. `FetchBuffer` +stores each member with a monotonic local order and presents at most +`fetchWidth` oldest members as `count + Vec`. New input uses only pre-cycle +free slots, so dequeue readiness cannot bypass into the upstream ready path. + +## Translation and line-fill mechanism {#MEC-IFU-002} + + +ITLB and L1I lookup remain parallel retained owners. A miss records the +complete fetch request before issuing memory traffic. The memory adapter marks +translation and instruction-line requests with distinct `MemoryAccessKind` +values, converts a cache line to ordered 64-bit beats, and accepts a response +only when both transaction value and generation match the retained request. +An erroneous line beat terminates assembly, retains the original fetch request +and error cause, and enters the same canonical fault packet path as a +translation access fault. + +## Prediction rendezvous mechanism {#MEC-IFU-003} + + +The prediction join retains I-SIDE groups and prediction updates under the +same fetch transaction. It publishes groups in order only after I-SIDE +completion and final prediction availability. Correction and terminal steering +remain explicit events rather than edits to already transferred packets. + +## B-SIDE prediction mechanism {#MEC-IFU-006} + + +`linxcore.ifu.BSide` is the public owner boundary for B-F0 through B-F4 and +reuses the existing retained predictor/history implementation as its body. +BTB, BIM, TAGE, loop, RAS, GHR, response, training, and checkpoint recovery +state MUST remain below that one boundary. `linxcore.ifu.IFURecovery` is the +canonical redirect arbiter, and `linxcore.ifu.IFUBackendFeedback` converts +OOO-authored validation into paired training and typed backend recovery. IFU +MUST NOT expose a direct IEX control input. + +## IFU recovery mechanism {#MEC-IFU-004} + + +Prepare retains the exact plan and fences no state. Apply prunes the canonical +Fetch Buffer immediately, retains the redirect until the I-SIDE accepts it, +and keeps IFU-to-CTU transfer fenced throughout that interval. Physical line +requests already issued before recovery may drain as orphans; their identity +cannot recreate killed architectural work. + +## Non-blocking trace mechanism {#MEC-IFU-005} + + +One retained trace packet isolates the Decoupled trace endpoint. A new +IFU-to-CTU fire fills an empty trace slot or replaces a trace accepted in the +same cycle. When the slot is blocked, the trace payload remains stable and new +observations are dropped without changing Fetch Buffer readiness. diff --git a/docs/spec/20-behavior/lsu.md b/docs/spec/20-behavior/lsu.md new file mode 100644 index 00000000..da746f76 --- /dev/null +++ b/docs/spec/20-behavior/lsu.md @@ -0,0 +1,84 @@ +# LSU behavior + +## Own each scalar memory row exactly once {#LSU-001} + + +LSU MUST be the sole owner of physical STQ, SCB, CommitQ, LIQ, MDB, miss, +refill, load-return, and scalar L1D state. The public boundary MUST resolve +semantic identities to private rows without exposing a physical queue index or +lease generation. A second compatibility or reduced owner MUST NOT receive the +same architectural transaction. + +## Join store reservation, address, data, class, and commit exactly {#LSU-002} + + +A logical store MUST reserve all required STQ beats atomically before either +STA or STD issues. Address and data may arrive in either order and on different +cycles. Pair stores retain one logical identity and two consecutive beats. +Translation/protection classification and ROB commit authorization MUST match +the complete semantic owner, logical first LSID/store ID, request count, and +beat. Stale or ambiguous matches MUST fail closed and mutate no row. + +Only a fully joined, classified, committed store may become externally +visible. Store forwarding MUST honor unresolved older stores and must not +replace exact program-order comparison with a physical row index. + +## Retain the complete load-attempt lifecycle {#LSU-003} + + +An accepted load issue MUST atomically bind the IEX-owned initial attempt to +one LSU-owned LIQ row. LSU owns every later reissue, repick, launch, replay, +MDB wait, miss/refill, and cancellation transition. Responses MUST match the +current attempt and allocation generation; stale responses MUST NOT resolve or +write back. The two W4 load pipes retain independent backpressure and return +identity. + +An accepted replay rebind from `Wait`, `L1DcMiss`, or `L2Wait` MUST preserve +the LIQ allocation, address, destination, transaction, and pipe while advancing +only the attempt. LIQ and every mutable old-attempt owner apply the transition +on one common ready/fire edge. An issued MissQ dependent is removed by exact +`{loadId, attempt, pipe}` match and its lower-memory identity remains as a +tombstone. The tombstone accepts and drops the eventual old response without +refill; a new attempt on the same line allocates a distinct lower-memory +identity and completes only from its own response. Terminal, completed, +nonconsecutive, stale, or ambiguous rebinds fail closed. + +SCB lookup MUST use the exact semantic store identity. A stale or ambiguous +SCB match returns no forwarding authority and mutates neither SCB nor LIQ. + +## Apply one scoped recovery transaction {#LSU-004} + + +Recovery Prepare MUST fence new lower-memory publication and compute the exact +STQ, LIQ, MDB, miss, refill, and return rows that Apply would remove. Prepared +MUST remain withheld until translation, cache-miss, load-return, store-drain, +and every public lower-memory transaction are quiescent. Prepare and Abort MUST +NOT mutate those owners. Apply MUST prune the same killed set from every owner +while preserving unrelated STIDs and non-killed older rows. + +## Canonical public composition {#MEC-LSU-001} + + +`linxcore.lsu.LSU` is the one public composition owner. +`OooIexStoreStqFabric` owns store reservation and STQ/data rows, +`STQSCBCommitBackend` owns classification, CommitQ, and SCB state, +`ScalarLSULoadPath` owns LIQ, MDB, L1D, miss/refill, and load-return state, +`DSideTranslation` owns retained D-side translation, and +`LSULowerTransactionRecovery` owns exact outstanding lower-memory identities. +Translation replay and data-miss replay remain separate. Scalar L1D line and +global invalidation MUST fail closed while any affected line is dirty; neither +operation may silently discard dirty data. + +## LSU verification {#VER-LSU-001} + + +`LSUStoreSpec`, `LSULoadSpec`, `LSUMemorySpec`, `LSUIntegrationSpec`, and +`IEXLSUIntegrationSpec` MUST cover crossed +STA/STD arrival, pair stores, exact classification and commit, forwarding, +unresolved older stores, independent load pipes, MDB replay, miss/refill, +stale-response rejection, translation, memory attributes, dirty maintenance, +lane-local backpressure, exact lower-transaction drain, and scoped recovery. +Generated-RTL activation MUST observe nonzero load and store traffic before a +displaced LSU public shell or alternate memory owner is deleted. It MUST also +prove exact MissQ tombstone drain, distinct replay request identity, and one +architectural load completion. diff --git a/docs/spec/20-behavior/ooo.md b/docs/spec/20-behavior/ooo.md new file mode 100644 index 00000000..7bb163ac --- /dev/null +++ b/docs/spec/20-behavior/ooo.md @@ -0,0 +1,499 @@ +# OOO behavior + +## Normalize every D1 operation before speculative ownership {#OOO-001} + + +OOO D1 MUST convert every accepted `Encoded64` instruction and every +non-recursive CTU `TemplateUop` into the same `DecodedUop` shape. Encoded +decode MUST retain the original 2-, 4-, 6-, or 8-byte length when selecting a +generated opcode recipe. Template children MUST bypass encoded decode and +retain their parent, ordinal, count, row kind, immediate, prediction, fault, +and instruction identity. A continuous packet MAY contain both operation +kinds after Instruction Buffer repacking; OOO MUST normalize it per lane and +preserve the original order. + +## Admit one complete D1 prefix atomically {#OOO-002} + + +OOO D2 MUST accept or stall the complete `[0, count)` decoded prefix. It MUST +NOT admit a lane suffix independently, create a second validity mask with +holes, or change any retained field while its D2 consumer applies +backpressure. The W2, W4, W6, and W8 profiles MUST elaborate from the central +parameter source. + +## Retain virtual ROB identity without publishing residency {#OOO-003} + + +For every accepted D2 prefix, OOO MUST retain an older-first virtual ROB +group and member intent using the complete `ridSlot` and `ridGeneration` +widths. D2 MUST NOT advance the physical RID tail, publish a ROB row, allocate +a BROB entry, or present zero-valued BID or resident fields as bound identity. +D3 remains the sole provisional RID-tail mutator, and later BROB/ROB owners +bind residency through explicit state. + +## Preserve precise decode faults {#OOO-004} + + +An illegal encoded instruction or an IFU fetch fault MUST produce one decoded +row with an explicit typed precise-trap intent. The faulting instruction's +identity and metadata MUST remain attached to that row; the fault MUST NOT be +encoded as a substitute opcode or consumed on behalf of a neighboring lane. + +## Fence and cancel retained D2 state by STID {#OOO-005} + + +Recovery prepare MUST retain and echo the exact plan and fence new or visible +D2 work for only its target STID without mutation. A matching apply MUST +remove that STID's retained D2 row. A matching abort MUST release the fence +without removing the row. Unrelated STIDs MUST remain eligible for admission +and output arbitration. + +## Canonical decode mechanism {#MEC-OOO-001} + + +`linxcore.ooo.DEC` is a stateless Decoupled transform. For encoded traffic it +uses the generated, length-qualified `OooOpcodeRecipeTable` decode path and +maps the resulting opcode, dispatch class, operand classes, architectural +tags, immediate, boundary, and trap state into the top-level interface +`DecodedUop`. For template traffic it maps `TemplateRowKind` directly to a +named uop class and never decodes the parent instruction again. A sparse +encoded-lane projection preserves encoded fusion and compaction only across +adjacent encoded lanes; a template lane is an ordering and fusion boundary. +The encoded results and direct template results are then compacted together +in original input-lane order. The exact +canonical `FrontEndOp` is copied from CTU after decode selection so 16-bit +legacy generation defaults cannot narrow architectural identity or prediction +metadata. + +## Retained D2 admission mechanism {#MEC-OOO-002} + + +The public D1/D2 payloads and complete slice IO live in +`linxcore.top.interface.OOOD1D2`, while `linxcore.ooo.OOO` holds at most one +immutable `D2AdmissionGroup` per STID. +Each transaction carries `count`, virtual group count and keys, decoded rows, +typed trap intent, and explicit false `residentBound` and `brobBound` state. +Group and member indices are assigned older-first from the D3-owned tail +snapshot; RID wrap increments the full-width virtual generation. A retained +grant keeps the selected transaction stable until fire or a matching recovery +operation. + +## D1/D2 verification {#VER-OOO-001} + + +`OOODecodeSpec` MUST cover all four instruction lengths, template bypass, +mixed encoded/template ordering and fusion isolation, +operand and prediction metadata, illegal and fetch-fault traps, W2/W4/W6/W8 +elaboration, atomic stall behavior, RID wrap with non-zero high generation +bits, and STID-scoped recovery. `CTUOOOIntegrationSpec` MUST cover ordinary +and expanded template traffic, including an Instruction Buffer-repacked mixed +prefix, through the adjacent boxes with backpressure and without loss, +duplication, reordering, or recursive expansion. +## Rename absolute P registers exactly {#OOO-006} + + +The absolute scalar GPR namespace has 24 architectural registers per STID. +`PRename` MUST be the sole owner of per-STID SMAP, per-STID CMAP, the shared +physical P free list, P generation tokens, and per-STID P MapQ +head/tail/count. P rename MUST resolve same-prefix RAW and WAW dependencies +from older destinations in the accepted prefix before consulting SMAP, and +each P destination MUST retain an exact history row for its current and +previous physical tags. + +## Rename relative T and U sequences exactly {#OOO-007} + + +T and U are independent ordered relative namespaces. A source with relative +index `n` resolves the sequence entry `tail-(n+1)` in its own namespace, with +same-prefix destinations participating in the visible sequence before older +MapQ rows. T and U destinations MUST allocate independent sequential local +tags without using P maps or the P free list. Physical tag index/generation +and MapQ sequence index/generation MUST be distinct tokens so unequal physical +and MapQ capacities remain exact across either wrap point. + +## Publish rename atomically through D3 {#OOO-008} + + +RENU MUST prepare one complete D2 prefix atomically only when P, T, U, +provisional retention, and all required history capacities can accept the +whole prefix. From-D2 acceptance MUST retain only the provisional D3 payload. +Visible P SMAP, P free-list, P MapQ, T/U tails, and T/U MapQs MUST mutate only +on the common D3 fire. If D3 backpressures the prefix, the complete renamed +payload and all history rows MUST remain stable and MUST NOT be published +twice. A recovery prepare targeting a D3 transaction already presented under +backpressure MUST remain unaccepted until that irrevocable transaction fires; +it MUST NOT switch the presented payload to another STID. Recovery MAY proceed +in parallel when the presented transaction belongs to an unrelated STID. + +## Recover rename state by target STID and surviving tail {#OOO-009} + + +Commit release MUST match the owning MapQ head, exact `RobIdentity`, and +generation-qualified history before mutating committed state. The complete +continuous release prefix MUST be accepted or rejected as one transaction +across P, T, and U; a validity hole or stale token in any domain MUST prevent +all three owners from applying it. Accepted P commit updates CMAP and returns +only the previous P tag. Accepted T/U commit advances only the matching +namespace head. Commit release MUST NOT race an active recovery transaction. +Recovery prepare MUST be non-mutating and MUST fence only its target STID; +unrelated STIDs remain eligible for admission and publication. Matching +recovery apply MUST affect only the target STID, +preserve the surviving ordered prefix, prune the killed suffix, return killed +current P tags, rewind T/U cursors to the survivor boundary, and rebuild P +SMAP from CMAP plus P survivors. Abort MUST leave all owner state unchanged. + +## Parameterize rename generations independently {#PRM-RENAME-001} + + +The P tag generation width and T/U local sequence generation width MUST be +configured in the central OOO parameter record. Adapters MUST NOT fall back to +an implicit 8-bit generation. P MapQ depth, P physical capacity, T/U physical +capacity, and ROB capacity are independent domains; each MUST be validated for +its own worst accepted prefix rather than derived from another domain. + +## D2/D3 rename interface mechanism {#MEC-OOO-003} + + +`linxcore.top.interface.OOOD2D3` defines `RENUD2D3IO`, +`RenameCommitReleaseEntry`, `RenameCommitReleaseTxn`, and the public D2/D3 +payloads. The D3 +group preserves D2 virtual ROB/group/member intent, decoded uop data, renamed +source and destination tags, early-complete sideband, and exact per-slot +history rows. RENU combines the P and T/U owner overlays into this single +payload and sends the same retained row back to both owners on the common D3 +publication pulse. + +## P rename owner mechanism {#MEC-OOO-004} + + +`linxcore.ooo.PRename` owns the P-domain speculative and committed maps, +physical free state, per-tag generation tokens, and per-STID P MapQ. P rename +prepare resolves sources from SMAP plus older same-prefix destinations and +records each destination's MapQ index and generation token. Publication +appends exact history rows. Release mutates CMAP and returns previous tags +only when the release matches the current MapQ head order and exact ROB +identity. Recovery rebuilds the target STID from CMAP plus surviving rows and +does not mutate non-target STIDs. + +## T/U rename owner mechanism {#MEC-OOO-005} + + +`linxcore.ooo.TURename` owns independent T and U MapQ local-sequence +index/generation state and separate physical-tag cursors. Prepare rejects the +whole prefix if any relative source underflows the visible local history. D3 +rows carry the T and U sequence snapshots seen before each uop. Publication +advances only the target STID local tails and counts. Recovery applies only to +the target STID and leaves aborts non-mutating. A renamed T/U source retains +the producer allocation epoch together with its physical tag and MapQ +sequence. IEX readiness, wakeup, bypass, and operand-file reads MUST qualify +that source with the retained producer epoch, not with the consuming +instruction's frontend epoch. + +## Rename owner verification {#VER-OOO-002} + + +`RENUSpec`, `RENUAtomicSpec`, and `TURenameSequenceSpec` MUST cover D3-only +publication, P same-prefix forwarding, same-lane +dual-destination WAW history, T/U relative allocation, T/U underflow +whole-prefix rejection, pending D3 backpressure stability, zero-destination +boundary sidecars, cross-domain all-or-none exact release, malformed-prefix +rejection, stale generation rejection, STID-scoped recovery fencing with +survivors, target-row irrevocability and unrelated progress, independent +physical/MapQ capacities and generations, +and W2/W4/W6/W8 behavioral publication. + +## Rename parameter verification {#VER-PRM-004} + + +`CoreConfigurationSpec` MUST prove that rename generation widths are centrally +configured and fail closed at zero. It MUST also prove that P MapQ, T/U MapQ, +P physical, T physical, and U physical capacities are validated independently +against one worst-case rename prefix. + +## Publish grouped ROB residency and complete by exact identity {#OOO-010} + + +`linxcore.ooo.ROB` MUST be the canonical grouped ROB residency owner. D3 +prepare MUST be side-effect free and MUST return exact `RobIdentity` bindings +for the continuous accepted prefix. Prepare MUST validate the ROB-owned RID +tail, STID, group/member order, free resident rows, and any BROB-prepared +BID/generation binding before it reports readiness. Only the caller-controlled +publication fire may install resident rows, advance the RID tail, and mark +early-complete zero-operand or boundary uops complete. Completion reports MUST +be consumed at the inspection boundary and reported as accepted or rejected +separately; stale, duplicate, wrong-generation, wrong-member, or wrong-BID +completions MUST NOT mutate ROB state. Release readiness MUST be +side-effect-free and MUST validate the complete retained prefix before the +common commit fire can retire or deallocate any row. ROB commit preview +observation MUST NOT move an entry from `Completed` to `Retired`; that state +transition is owned by the explicit common commit-apply boundary. ROB resident +member state is physically indexed by `robBankCount` bank/row geometry, and +unsupported non-divisible bank profiles MUST fail closed. + +## Own per-STID BROB residency exactly {#OOO-011} + + +`linxcore.ooo.BROB` MUST own a generation-qualified circular block table per +STID. D3 prepare MUST walk groups older-first, allocate a native BID only at a +typed block start, carry the current block across groups, close it only at a +typed block stop, and mutate table/head/tail state only on the common +publication fire. Release readiness MUST validate the complete retained +prefix and free the head block only when the exact final ROB member for that +block is included. Recovery prepare MUST be non-mutating; recovery apply MUST +match the retained plan and prune only the target-STID suffix while preserving +older blocks, current surviving blocks, exact `used` accounting, and unrelated +STIDs. BROB publication MUST store the ROB-prepared, allocator-bound ROB +identity for each active lane, not the provisional D3 ROB identity, and MUST +reject publication unless every active ROB-prepared lane matches the raw D3 +PE/STID/RID/member fields and the BROB-prepared BID/BROB generation for that +lane. Recovery prepare MUST validate the exact local BROB projection of the +ROB-authored suffix, including first/last endpoint BID and BROB generation, +before retaining an action. Stale BID generation release or recovery attempts +MUST be rejected without changing unrelated STIDs. +If a valid block's first member survives but its recorded last member lies in +the killed suffix, recovery apply MUST retain the exact BID/generation and +table occupancy for that block, preserve closed/open/current semantics, and +shorten only the block's recorded last ROB identity to the surviving tail. The +recovered next-free pointer MUST be the modulo successor of that retained BID, +with generation incremented exactly on successor wrap, so wholly killed younger +slots become reachable without selecting the live survivor slot. + +## Retain in-order commit until every release owner accepts {#OOO-012} + + +`linxcore.ooo.CommitControl` MUST retain one complete oldest-first commit +prefix, rename-release transaction, BROB release, ROB release, and trap +selection while any consumer backpressures or withholds side-effect-free +readiness. `CommitControl.out.valid` is the common fire candidate and MUST be +asserted for non-empty commit prefixes only when ROB, RENU, and BROB all +report exact release readiness. Zero-lane head trap and interrupt-boundary +transactions MUST be allowed to fire once without fabricating ordinary release +readiness. Duplicate suppression MUST compare the exact accepted +`CommitControlTxn` signature: commit count, active ROB identities, companion +release facts, trap validity, kind, cause, and identity. A changed prefix +length, trap cause/kind, or ordinary/trap shape is a distinct transaction even +when the first ROB identity is unchanged. The retained prefix MUST NOT be +recomputed or repeated while a `Valid` ROB preview remains asserted after the +common fire. `Completed` and `Retired` are separate ROB states; physical ROB +rows and previous physical registers are freed only on the matching common +commit fire. +Secondary destination history MUST remain in the companion +`RenameCommitReleaseTxn` even when `CommitEntry.destination` exposes only the +primary projection. + +## Select precise traps, interrupts, and recovery from one ROB plan {#OOO-013} + + +`linxcore.ooo.RecoveryControl` MUST be the sole global recovery event arbiter +and plan distributor. Producer events admitted into one arbitration boundary +are retained as a complete contender set until every active producer has a +matching ROB candidate status. ROB candidate status is the only authority for +exact residency, non-retired eligibility, global allocation age, and +synchronous head-trap priority; RecoveryControl MUST NOT derive global age from +STID/RID concatenation, select from a partial status set, or drop a candidate +before matching status is known. A +synchronous head trap wins over an interrupt at the same precise boundary; an +`Exception` cause without ROB status proving a precise head trap MUST NOT +outrank an older ordinary recovery event. Interrupts are admitted only at an +explicit precise ROB head boundary and cannot bypass an unresolved producer +contender. Recovery prepare MUST ask ROB for one +retained `RecoveryPlan` +containing the exact compact killed suffix, offer the identical plan exactly +once to every target in `Prepare`, wait for every causal matching +acknowledgement, ignore stale, pre-prepare, wrong-phase, or otherwise +mismatched acknowledgements, and emit exactly one terminal decision. A target +acknowledgement is causal only when the target `prepared` beat fires in +`Prepare` phase for the same transaction and the corresponding target +`Prepare` request already fired or fires in the same cycle. +If abort arrives before ROB accepts the request, RecoveryControl cancels the +request locally and emits no fabricated owner terminal. A held `robPrepared` +beat observed before ROB accepts the request MUST drain without becoming that +request's plan, and abort-suppressed requests MUST NOT let such a beat attach +to a later request. If ROB has accepted the request but has not yet returned +the ROB-authored plan, RecoveryControl +waits for a response that correlates to the exact retained request and then +emits only the matching ROB abort terminal; target owners that never received +`Prepare` observe no abort. Stale, unrelated, wrong-phase, or otherwise +mismatched ROB responses in a legal ROB response window MUST be drained from +the Decoupled channel but MUST NOT overwrite the retained plan, enter target +prepare, emit ROB abort, clear abort-pending state, or cause the request to be +reissued after it has already fired. Correlation matches the request phase, +transaction ID, cause, full trigger identity, redirect PC, and new epoch while +allowing only the ROB-authored killed-suffix and survivor-tail fields to +differ. If abort arrives while target preparation is pending, the retained +ROB-authored plan is broadcast as non-mutating `Abort` to every target and as +the matching ROB abort terminal. Abort coincident with the final target acknowledgement has +non-mutating priority over `Apply`. Once the common one-cycle `Apply` is +visible, it is irrevocably committed and a same-cycle abort request MUST NOT +schedule a later abort for the same plan. +Branch recovery preserves the trigger and kills younger members; memory-order +replay recovery kills the trigger and younger members. ROB-authored recovery +plans MUST distinguish killed member count from affected ROB group count and +must identify the exact surviving ordered tail. ROB and BROB recovery apply +MUST mutate only once for a retained matching `Apply` transaction; stale, +duplicate, mismatched, or wrong-phase apply is non-mutating. Abort MUST be +non-mutating and MUST clear only the matching retained transaction. If a ROB +or BROB owner observes simultaneous matching `Apply` and `Abort`, it MUST +choose the non-mutating abort path and perform no suffix mutation. +BROB recovery prepare MUST retain the exact local action and apply that action +without recomputing from mutable table state; partial recovery of any open or +closed block that straddles the killed suffix preserves the surviving block and +rewinds its last ROB owner. A malformed compact suffix whose first or last +endpoint does not name the live BROB BID/generation and stored endpoint +identity MUST be rejected during prepare. + +## ROB/BROB/commit/recovery owner mechanisms {#MEC-OOO-006} + + +The Task-9 canonical owner files are `linxcore.ooo.ROB`, +`linxcore.ooo.BROB`, `linxcore.ooo.CommitControl`, and +`linxcore.ooo.RecoveryControl`. Cross-owner payloads live under +`linxcore.top.interface.OOORob` and `linxcore.top.interface.Recovery`. +These owners use `CoreParams` directly and do not instantiate or wrap the +legacy `Ooo*`, `rob.*`, `bctrl.*`, or `recovery.*` owners. + +ROB and BROB publication is one combinational prepare followed by one common +mutation fire. Every active D3 lane MUST receive allocator-authored BID and +BROB generation plus matching STID from `BROBPrepared`, including a lane whose +raw D3 payload has `brobBound = false`; ROB MUST stamp BID/generation plus its +own resident generation into the exact prepared ROB identity. A lane already +marked `brobBound` MUST match the allocator binding, and a lane already marked +`residentBound` MUST match the ROB-owned resident generation. Count, +active/inactive lane shape, STID, block-allocation marker, same-block +BID/generation continuity, RID/member identity, and generation mismatches MUST +backpressure the common publication before either owner mutates. + +## ROB/BROB/commit/recovery owner verification {#VER-OOO-003} + + +`OOORobCommitSpec` and `OOORecoverySpec` MUST cover grouped ROB publication, +same-group member commit order, STID arbitration, exact completion acceptance +and rejection, stale slot reuse rejection, per-STID BROB BID/generation +checks, whole-prefix release rejection, final-member BROB release, retained +commit under independent owner readiness, secondary-destination release +history, precise trap priority, memory-order recovery, branch same-group +younger-member kill, exact suffix membership including generation and member +index, distinct killed member/group counts, survivor-tail repair, BROB +survivor accounting, nontrivial ROB bank geometry, recovery age-token width +guarding, source arbitration with delayed and retained ROB statuses, interrupt +holdoff behind unresolved producers, ROB recovery request/response, +wrong-phase and duplicate apply rejection, ROB/BROB abort termination, closed +BROB straddling-block survivor shortening, +ROB-prepared BROB publication identity binding for unbound D3 residency, +real ROB/BROB coordinated publication across nonzero BID, BID wrap, +resident-generation reuse, release, and suffix recovery, +one-prepare-per target barriers, pre-prepare target acknowledgement rejection, +wrong-phase target acknowledgement rejection, mismatched acknowledgement +rejection, common apply, request-phase ROB abort, target-prepare abort +priority, visible-apply abort suppression, legal Decoupled drain without +semantic acceptance for pre-request and stale/unrelated ROB responses in +RequestRob, WaitRob, and WaitRobAbort, +target prepared-beat drain outside target preparation without acknowledgement, +including a matching beat held before Prepare followed by same-transaction +abort and retry, +simultaneous terminal fail-closed behavior, and +non-mutating abort. + +## Dispatch one atomic canonical D3 prefix {#OOO-014} + + +The public `linxcore.ooo.OOO` graph MUST publish one RENU-authored D3 prefix +to ROB, BROB, and dispatch on one common fire. Dispatch readiness MUST require +the exact side-effect-free ROB and BROB prepared identities for every active +lane; a count or identity mismatch MUST backpressure publication without +retaining or mutating dispatch state. The retained published packet MUST drain +oldest-first as one continuous prefix and MUST retry only its undispatched +suffix under class-channel backpressure. ALU, BRU, AGU, system, and CMD credit +are independent; CMD MUST NOT consume system credit. A store MUST consume AGU +and STD credit atomically and publish an identical `DispatchTxn` to both +channels. Early-complete and boundary lanes MUST consume neither IEX credit nor +an output channel because completion is already represented by the canonical +ROB publication. A matching recovery apply MUST suppress same-cycle output +and discard only a retained suffix for the target STID; abort MUST be +non-mutating. + +## Canonical D3/S1 dispatch mechanisms {#MEC-OOO-007} + + +`linxcore.ooo.Dispatch` is the canonical D3/S1 boundary. +`OooD3ReservationAllocator` retains at most one already-published canonical +packet and its suffix cursor; it does not own ROB, BROB, rename, commit, or +global recovery state. `OooDispatch` performs stateless class and credit +mapping, and `OooHierarchicalFreeSlotSelect` selects the oldest active slot at +the continuous-prefix boundary for widths W2, W4, W6, and W8. The production +`OOO` graph directly instantiates RENU, ROB, BROB, Dispatch, CommitControl, and +RecoveryControl and MUST NOT instantiate the displaced O3 coordinator or a +second owner for any of those states. + +## Canonical D3/S1 dispatch verification {#VER-OOO-004} + + +`OOODispatchSpec` MUST cover complete payload mapping, exact prepared-owner +rejection without mutation, continuous-prefix suffix retry, atomic STA+STD +credit, CMD separation, early-complete no-output behavior, recovery-coincident +suppression, abort preservation, and W2/W4/W6/W8 elaboration. +`OOOIntegrationSpec` MUST elaborate the public canonical owner graph at all +four widths, while `OOORecoverySpec` retains the recovery barrier and terminal +transaction coverage. + +## Allocate memory order on the common D3 publication {#OOO-015} + + +OOO MUST be the sole owner of each STID's full LSID, load-only LID, store-only +SID, YOST, and YOLD program-order state. DEC MUST normalize each uop's memory +request count before allocation. The allocator MUST prepare the complete D3 +prefix without mutation and publish its per-lane `MemoryOrderMeta` only on the +same common fire that publishes RENU, ROB, BROB, and dispatch state. Dispatch +transaction IDs, ROB generations, prefix lanes, and physical queue rows MUST +NOT synthesize any memory-order identity. ROB MUST retain the exact before and +after state associated with each resident member. Recovery prepare MUST be +non-mutating; matching apply MUST restore only the target STID from the +ROB-authored survivor snapshot, while abort and peer-STID recovery preserve +the state. + +## Authorize exact unresolved noflush head work {#OOO-016} + + +ROB MUST expose a noflush candidate only for the oldest live, unresolved, +unretired, trap-free resident row behind a fully completed, trap-free prefix +whose recipe is a no-destination system or CMD uop. Completed older members of +the same atomic BROB block MUST NOT require partial retirement before the next +noflush row can be authorized. +CommitControl MUST require an exact matching `RobNoflushReadyTxn` NFRDY proof +from the execution/side-effect owners before it presents authorization. The +proof means input and legality checks completed without a local trap and every +older effect drained. CommitControl MUST preserve the candidate's exact +dispatch transaction, instruction identity, and ROB identity under +backpressure, continuously revalidate per-STID head residency and eligibility, +and authorize it at most once while that member remains resident. Recovery +prepare for the same STID MUST withdraw an unconsumed authorization; peer-STID +recovery and arbitration MUST NOT mutate or re-enable it. The authorization +alone MUST NOT retire, resolve, or apply the side effect. + +## Memory-order and noflush owner mechanisms {#MEC-OOO-008} + + +`linxcore.ooo.OooMemoryOrderAllocator` is the unique per-STID memory-order +owner. `linxcore.ooo.OOOD3S1Graph` joins its prepare and publication decisions +to the existing common D3 fire. `linxcore.ooo.ROB` retains memory-order +snapshots and publishes the exact resident-head preview; +`linxcore.ooo.CommitControl` retains and publishes `RobNoflushTxn`. +`OOOD3S1Graph` forwards accepted `SystemIssueTxn` beats losslessly through the +public `OOOIO` side-effect boundary. The +canonical payload homes are `linxcore.top.interface.OOOD2D3`, `OOOIEX`, and +`OOORob`. + +## Memory-order and noflush verification {#VER-OOO-005} + + +`OooMemoryOrderAllocatorSpec` MUST cover mixed load/store prefixes, +multi-request uops, exact LSID/LID/SID assignment, YOST/YOLD boundaries, +unpublished-suffix cancellation, recovery preview, and abort preservation. +`OOOMemoryOrderIntegrationSpec` MUST cover common-fire backpressure stability, +target-STID restore, peer-STID survival, exact graph-level NFRDY proof, and +exactly-once authorization. `OOORobCommitSpec` MUST cover oldest-unresolved ROB +eligibility, stale-proof drain, stable identity under backpressure, same-STID +recovery withdrawal, peer-STID arbitration, resident-head exactly-once +suppression, and loss-of-head invalidation. `OOORecoverySpec` MUST cover a +full-capacity youngest branch with zero killed members and unchanged memory +tail. diff --git a/docs/spec/20-behavior/recovery.md b/docs/spec/20-behavior/recovery.md new file mode 100644 index 00000000..82e9533d --- /dev/null +++ b/docs/spec/20-behavior/recovery.md @@ -0,0 +1,42 @@ +# Recovery behavior + +## Select one precise recovery action {#REC-001} + + +OOO MUST select the architectural recovery event. A synchronous head fault +MUST take priority over debug and interrupt requests. An interrupt request is +eligible only when its STID matches the precise ROB boundary; arbitration MUST +select the highest-priority eligible request. + +## Apply after every required acknowledgement {#REC-002} + + +The same typed `RecoveryPlan` MUST fan out in Prepare phase. Apply MUST remain +withheld until every required target has accepted Prepare and returned an +exact matching Prepared acknowledgement. A missing or stale acknowledgement +MUST NOT partially apply recovery. + +## Keep cleanup local to the target STID {#REC-003} + + +IFU, CTU, OOO, IEX, and LSU MUST own only their local cleanup. Prepare MUST +fence the target STID without preventing unrelated-STID admission or forward +progress where the local storage and protocol permit it. Apply MUST prune only +the plan's exact killed set; Abort MUST release the fence without mutation. + +## Recovery mechanism {#MEC-REC-001} + + +`linxcore.ooo.RecoveryControl` retains candidate selection and the common +Prepare/Prepared/Apply barrier. TOP routes the typed target ports without +recomputing age or kill membership. Each public box compares the complete +transaction identity before acknowledging or applying its local action. + +## Recovery verification {#VER-REC-001} + + +`CommitControlDebugSpec` MUST cover interrupt STID qualification and +synchronous-fault priority. `RecoveryControlBarrierSpec` MUST cover prepare +fanout, missing-acknowledgement stall, and one common apply. +`RecoveryIntegrationSpec` MUST cover the same contracts together with +unrelated-STID CTU progress. diff --git a/docs/spec/30-interfaces/commit.md b/docs/spec/30-interfaces/commit.md new file mode 100644 index 00000000..5842e8e9 --- /dev/null +++ b/docs/spec/30-interfaces/commit.md @@ -0,0 +1,66 @@ +# Commit interface + +## OOO-owned architectural commit {#IFC-COMMIT-001} + + +OOO shall publish architectural commit as a continuous oldest-first prefix. +An ordinary prefix shall not cross a BROB BID/generation boundary; a younger +block becomes eligible only after the current head block's prefix applies. +Each committed entry shall carry its complete ROB and instruction identities, +architectural result, memory side effect summary, and precise trap state. +Commit-side release to rename, ROB, and BROB owners shall use side-effect-free +readiness followed by one common fire. The visible commit transaction, rename +release, ROB release, and BROB release are one retained boundary; no physical +row or previous physical register may be freed from a readiness check or from +an unacknowledged `Valid` pulse. A zero-lane precise trap or interrupt +boundary carries no ordinary release lanes and may fire once without requiring +ROB, rename, or BROB release readiness. + +For a system or CMD side effect, OOO shall authorize only the exact head member +after all input and legality checks complete without a pending trap and every +older effect drains. Recovery Prepare has priority over issuing or consuming +that authorization. The matching authorization, system/CMD issue, side-effect +acceptance, and no-value ROB resolve shall form one common fire and shall occur +exactly once. + +## Commit transaction Bundle {#MEC-COMMIT-001} + + +`CommitTxn` uses `count + Vec(retireWidth, CommitEntry)`. TOP and DTU observe +the same OOO-produced transaction; observation does not create a second commit +owner or an independent retirement decision. + +`RobNoflushTxn` is a head-member authorization for one precise system or CMD +side effect. It is derived by OOO commit control after all older effects drain, +does not retire the member by itself, and cannot be retained or regenerated by +IEX. Its matching side-effect issue and no-value `RobResolveTxn` fire in one +atomic rendezvous. + +`RobNoflushReadyTxn` is the exact NFRDY proof consumed by commit control before +that authorization. Its transaction, instruction, and ROB identities must +match the same per-STID resident head. The proof is legal only after the +producing execution row has completed its input and legality checks and the +authoritative side-effect owners report every older effect drained. It is not +an authorization and cannot resolve or retire the member. Under backpressure, +the proof remains stable; loss of head residency, eligibility, or a matching +recovery fence immediately withdraws the authorization candidate. +An exact unaccepted proof is not consumed while that fence is active; stale, +mismatched, or already-authorized proofs remain drainable. + +`RenameCommitReleaseTxn` is the companion release payload for complete +destination history. It preserves every destination slot even when the public +`CommitEntry.destination` field carries only the primary projection for +architectural observation. + +`CommitControlTxn` carries the public commit prefix plus companion rename, +ROB, and BROB release payloads. The owner-level ready signals are not +acknowledgements; they are exact prepare decisions used to decide whether the +single `CommitControl.out.fire` may authorize every release side effect. ROB +commit preview observation is side-effect-free; ROB retirement state advances +only on the matching common commit-apply pulse. Duplicate suppression is keyed +to the complete accepted `CommitControlTxn` signature, not only the first ROB +identity. A changed count, active-lane identity, companion release payload, +trap kind, trap cause, trap identity, or ordinary/trap shape is a distinct +transaction even when `rob.valid` remains asserted. Inactive lanes outside the +active `count` prefix are canonical zeroes for this comparison and MUST NOT +make an identical active transaction repeat. diff --git a/docs/spec/30-interfaces/ctu-ooo.md b/docs/spec/30-interfaces/ctu-ooo.md new file mode 100644 index 00000000..918d1a6f --- /dev/null +++ b/docs/spec/30-interfaces/ctu-ooo.md @@ -0,0 +1,16 @@ +# CTU to OOO interface + +## Canonical D1 prefix transfer {#IFC-CTU-OOO-001} + + +CTU shall present OOO with a continuous program-order prefix of canonical +front-end operations. An entry shall be either one encoded 64-bit instruction +container or one non-recursive template uop and shall retain its architectural +parent identity. + +## D1 packet Bundle {#MEC-CTU-OOO-001} + + +`D1Packet` uses `count + Vec(decodeWidth, FrontEndOp)`. +`FrontEndOp.kind` distinguishes encoded instructions from template uops; +`CTUIO.toOoo` and `OOOIO.fromCtu` share the same payload definition. diff --git a/docs/spec/30-interfaces/dtu.md b/docs/spec/30-interfaces/dtu.md new file mode 100644 index 00000000..547951a0 --- /dev/null +++ b/docs/spec/30-interfaces/dtu.md @@ -0,0 +1,17 @@ +# DTU interface + +## Debug and trace remain observational {#IFC-DTU-001} + + +DTU shall consume typed trace and commit observations and may issue typed debug +requests. DTU shall not own commit, trap, interrupt, cache, predictor, rename, +or recovery state. + +## Trace and debug Bundles {#MEC-DTU-001} + + +`TraceEvent` retains source, event kind, instruction identity, ROB identity, +PC, opcode, and payload. `DTUIO` receives parameterized trace and commit +observations plus an external debug request, exports trace and performance +counters, and transports the debug request and matching response through a +typed owner-facing control channel. TOP routes that control channel to OOO. diff --git a/docs/spec/30-interfaces/iex-lsu.md b/docs/spec/30-interfaces/iex-lsu.md new file mode 100644 index 00000000..fd95c974 --- /dev/null +++ b/docs/spec/30-interfaces/iex-lsu.md @@ -0,0 +1,31 @@ +# IEX to LSU interface + +## Independent address and store-data paths {#IFC-IEX-LSU-001} + + +IEX shall provide independently backpressured load-address, store-address, and +store-data transactions. The default topology shall expose two paths of each +kind, and LSU responses shall match complete memory and ROB identities rather +than address or queue slot alone. OOO shall allocate program-order memory IDs, +IEX shall allocate each memory transaction and initial load attempt on the +canonical Dispatch-to-IQ acceptance edge, and LSU shall own LIQ reissue, +repick, and later attempt rebind. + +## LSU request and result Bundles {#MEC-IEX-LSU-001} + + +`IEXLSUIO` uses parameterized vectors of `LoadIssueTxn`, `StoreAddressTxn`, and +`StoreDataTxn`; `LoadResultTxn` carries the latest accepted `MemoryIdentity`. +The same load-pipe count sizes independent LSU-to-IEX `LoadReissueTxn`, +`LoadRepickTxn`, and `LoadCancelTxn` vectors. Reissue and repick carry exact +current/next attempt identities; load cancel is retained under backpressure and +cancels speculative dependents without freeing LIQ residency. Store address +and data remain separate transactions until the LSU-owned join accepts both +exact identities. + +`LoadReissueTxn` and `LoadRebindApplyTxn` implement the Option-A ownership +transfer. The memory transaction, allocation, destination, and pipe remain +unchanged; only the attempt advances to its exact modulo successor. The common +fire cancels the old exact attempt in every LSU owner and returns the LIQ row +to replay eligibility. An issued lower-memory transaction is retained only as +a stale-response tombstone and cannot coalesce with the new attempt. diff --git a/docs/spec/30-interfaces/ifu-ctu.md b/docs/spec/30-interfaces/ifu-ctu.md new file mode 100644 index 00000000..1081af62 --- /dev/null +++ b/docs/spec/30-interfaces/ifu-ctu.md @@ -0,0 +1,18 @@ +# IFU to CTU interface + +## Fixed-container fetch transfer {#IFC-IFU-CTU-001} + + +IFU shall transfer each accepted instruction to CTU in a 64-bit container with +an explicit 2, 4, 6, or 8 byte length. A packet shall contain one continuous +program-order prefix, and every entry shall carry its complete instruction and +prediction identity. + +## Fetched packet Bundle {#MEC-IFU-CTU-001} + + +`FetchedPacket` uses `count + Vec(fetchWidth, FetchedInstruction)`. +`IFUIO.toCtu` and `CTUIO.fromIfu` use that one payload type with opposite +directions; neither endpoint defines a sender- or receiver-specific copy. +The payload carries architectural fetch and prediction identity, not a +provisional ROB or BROB allocation. diff --git a/docs/spec/30-interfaces/memory.md b/docs/spec/30-interfaces/memory.md new file mode 100644 index 00000000..cff0db58 --- /dev/null +++ b/docs/spec/30-interfaces/memory.md @@ -0,0 +1,30 @@ +# External memory interface + +## Identity-qualified memory traffic {#IFC-MEMORY-001} + + +Instruction and data memory requests and asynchronous responses shall carry a +transaction identity with generation. A response shall not be accepted by +address, queue slot, or low transaction bits alone. + +## Memory request and response Bundles {#MEC-MEMORY-001} + + +`MemoryRequestTxn` and `MemoryResponseTxn` share `MemoryTransactionIdentity`. +Each request also carries a `MemoryAccessKind` that distinguishes instruction +line, instruction translation, ordinary data, and device traffic without +overloading the coherence command. `TOPIO` exposes separate instruction and +data channels so cache, device, and recovery ownership cannot be inferred from +an untyped shared payload. + +Responses carry both scalar `data` and a complete cacheline `lineData`. +Acquire responses use `lineData` as the refill image before the requesting +cache owner merges its exact store bytes. A denied or corrupt ownership +response must not grant permission, refill a line, or complete the requesting +store transaction successfully. + +The live LSU translates load and store virtual addresses before allocating or +mutating their private rows. Translation requests use an identity namespace +distinct from cache-miss traffic, and only an exact value-plus-generation +response may refill either owner. The LSU publishes quiescence only after all +translation and data transactions accepted on its public memory lanes drain. diff --git a/docs/spec/30-interfaces/ooo-iex.md b/docs/spec/30-interfaces/ooo-iex.md new file mode 100644 index 00000000..5ef6ab5a --- /dev/null +++ b/docs/spec/30-interfaces/ooo-iex.md @@ -0,0 +1,65 @@ +# OOO to IEX interface + +## Typed dispatch and resolve {#IFC-OOO-IEX-001} + + +OOO shall dispatch renamed uops through class-specific channels, with CMD kept +independent from system and multicycle work. IEX shall return resolves using +the complete ROB member identity carried by the dispatched uop. A system or CMD +side effect shall remain resident until its exact ROB noflush authorization and +consumer readiness participate in the same resolve rendezvous. + +Every dispatch, resolve, trace, and commit packet is a continuous `[0, count)` +prefix. A lane outside the prefix is invalid and cannot carry an independent +side effect. Terminal queues retain each accepted prefix until all coupled +consumers fire. + +## Dispatch and resolve Bundles {#MEC-OOO-IEX-001} + + +`OOOIEXIO` groups ALU, BRU, AGU, STD, system, and CMD `DispatchTxn` channels +without flattening fixed lane names. `RobResolveTxn` echoes `RobIdentity`; +backpressure never authorizes identity or payload mutation. `RobNoflushTxn` +authorizes one exact head member and is not a retained queue owner. +`RobNoflushReadyTxn` is the exact IEX-to-OOO NFRDY proof for the same member; +its `valid` means operand and legality checks are complete without a local +trap and the authoritative side-effect owners report every older effect +drained. OOO accepts a matching proof only while the same unresolved member is +the oldest unresolved row behind a fully completed, trap-free per-STID ROB +prefix. This permits a younger System/CMD row in the same atomic BROB block to +complete without requiring an impossible partial block retirement. A stale or +mismatched proof is drained without +authorization, while a matching proof and authorization remain one retained +ready/valid rendezvous. Recovery fencing holds `ready` low for an exact, +unaccepted proof; Abort therefore resumes the same proof instead of requiring +the producer to regenerate it. +`SystemIssueTxn` is forwarded losslessly through public `OOOIO` to its TOP +side-effect owner. The TOP-projected `CmdIssueTxn` remains a separate public +IEX transaction. Neither endpoint may be tied ready or silently drained. + +`DispatchTxn.trap` carries the precise decode-trap intent owned by OOO from +the canonical D3 lane into IEX. Its validity and cause are immutable parts of +the dispatch payload and therefore remain stable under backpressure. A +`StoreDispatchTxn` copies the same intent into both its STA and STD members; +the atomic store beat cannot expose one member with a missing or different +trap intent. IEX may transport and resolve this intent but does not create a +second decode-trap owner. + +`DispatchTxn.pcBufferIndexOffset` carries the exact `pcBufferIndex`、 +`pcOffset` and `allocationEpoch` prepared by the OOO PC buffer on the common +D3 publication edge. IEX retains those fields in the IQ. A uop that needs its +PC presents `PcBufferReadAddress` during I1; OOO returns the exact PC base +through the readyless `pcBufferReadPcBase` vector, and IEX adds the retained PC +offset in I2. A stale PC buffer index/allocation epoch produces no valid PC +base and must repick without execution. The complete PC is not copied through +the IQ and IEX owns no PC buffer rows. + +`DispatchTxn.memoryOrder` is stable logical order metadata. `requestCount` +states the number of memory requests represented by the uop; `firstLsid`, +`firstLid`, and `firstSid` are respectively the first full memory-order, load, +and store serials assigned to that uop. `YOST` identifies the youngest older +store by full LSID and SID, while `YOLD` identifies the youngest older load by +full LSID and LID. Invalid `YOST` or `YOLD` fields are canonical zeroes. These +fields are program-order identities only: they never contain a dispatch +transaction, IEX memory transaction, load-attempt generation, pipe route, or +physical LIQ/STQ row. diff --git a/docs/spec/30-interfaces/recovery.md b/docs/spec/30-interfaces/recovery.md new file mode 100644 index 00000000..e9058256 --- /dev/null +++ b/docs/spec/30-interfaces/recovery.md @@ -0,0 +1,105 @@ +# Recovery interface + +## One precise recovery authority {#IFC-RECOVERY-001} + + +IEX, LSU, and other detecting owners shall report typed recovery events to OOO. +OOO shall be the only producer of a global recovery plan. Every affected owner +shall prepare without mutation and shall mutate only on the matching apply +transaction routed by TOP. + +## Recovery event and plan Bundles {#MEC-RECOVERY-001} + + +`RecoveryEvent` names the exact trigger and proposed redirect. +`RecoveryPlan` carries one transaction ID, phase, cause, exact trigger, +surviving tail, redirect, new epoch, and one compact ROB-authored killed +suffix descriptor: `firstKilledValid`, `firstKilled`, `lastKilled`, +`killedGroupCount`, and `killedMemberCount`. The descriptor identifies the +unique contiguous live ROB suffix without emitting a capacity-sized vector. +`killedGroupCount` counts affected ROB groups, not killed members, and the +surviving tail names the exact ordered live member immediately before the +suffix when one exists. +Owner-local structures that coalesce multiple ROB members into one entry must +derive their exact local action from this compact suffix. In particular, a BROB +block whose first member survives while its recorded last member lies in the +suffix remains the same BID/generation and is shortened to the surviving tail +on matching Apply; the owner restores its next-free pointer to the modulo +successor of that retained BID/generation rather than the old pre-recovery +tail. BROB targets must reject Prepare when the compact suffix endpoints do not +match the live endpoint BID, BROB generation, and stored ROB identities for the +owner-local projection. +Box IOs reuse these types; no direct IEX- or LSU-to-IFU recovery-control path +exists. + +For an affected load, Prepare fences new issue, reissue, repick, cancel, and +result fires without changing the retained attempt. Apply removes the exact +matching IEX metadata and LSU LIQ residency; Abort preserves both. Point-to- +point `LoadCancelTxn` is only a speculative-dependent cancellation and MUST NOT +be used as a recovery, residency-release, or transaction-reuse protocol. + +Recovery control requests the ROB-authored plan through an explicit +Decoupled request/response. Targets receive the retained ROB plan in Prepare +phase until their individual prepare fires, return one matching prepared +transaction, and mutate only on the later common Apply broadcast. Recovery +control counts a target prepared transaction only when that target's Prepare +request has already fired or fires in the same cycle, the response fires in +Prepare phase, and the transaction matches the retained plan. Stale, +pre-prepare, wrong-phase, or otherwise mismatched target responses are +drainable Decoupled beats in every controller state, but they are not target +acknowledgement authority outside `PrepareTargets`. In particular, a matching +beat already held before the controller enters target preparation MUST fire +and drain before the target Prepare request becomes visible; it cannot satisfy +that request later and cannot survive an abort into a same-transaction retry. +A matching Abort broadcast terminates the retained transaction without owner +mutation. +RecoveryControl also exposes a dedicated `robAbort: Valid[RecoveryPlan]` +terminal for the ROB request side. If abort arrives after `robPrepare.fire` +but before `robPrepared.fire`, RecoveryControl waits for the exact +ROB-authored response and then emits only this ROB abort terminal; it does not +broadcast a stale or default target plan. A ROB response is exact only by the +request fields: `RecoveryPlanContract.sameRobRequest` requires Prepare phase, +transaction ID, cause, full trigger identity, redirect PC, and new epoch to +match the retained seed request while deliberately ignoring the ROB-authored +survivor-tail and killed-suffix fields. Unsolicited responses before +`robPrepare.fire` are drainable stale Decoupled transactions and are not +accepted as the current plan, even if the held beat matches a later seed +request. Stale, unrelated, wrong-phase, or otherwise mismatched ROB responses +inside `RequestRob`, `WaitRob`, or `WaitRobAbort` are also Decoupled +transactions: RecoveryControl drains them when the response window is legal, +but they are not semantically accepted as the current plan. A same-cycle +mismatched response does not prevent the request from firing once. Canonical +ROB and BROB owner IOs +consume explicit matching `RecoveryPlan` Abort inputs and clear only the +retained transaction named by the shared transaction-equality helper. Stale, +duplicate, mismatched, or wrong-phase Apply and Abort packets are +non-mutating. Simultaneous matching Apply and Abort fail closed by taking the +non-mutating Abort path; owner mutation is gated off before any assertion or +diagnostic. +Abort during target preparation is a single terminal decision: if it coincides +with the final target acknowledgement barrier, Abort wins and Apply is not +registered. Once Apply is already visible to targets, the plan is committed and +RecoveryControl must not schedule a later Abort for that same plan. +An exception event wins global arbitration only when it carries a precise trap +payload; the `Exception` enum value alone does not outrank an older ordinary +event. + +`RecoveryCandidateLookup` and `RecoveryCandidateStatus` are public ROB-facing +candidate arbitration payloads. RecoveryControl publishes retained producer +events as lookup candidates. ROB returns matching status with exact +eligible/rejected state, a globally comparable allocation-age token, and a +head-trap bit proving synchronous trap priority. RecoveryControl selects only +among matching eligible ROB statuses and deliberately discards matching +rejected candidates without blocking another eligible source. +All producer candidates admitted into one arbitration boundary remain live +until every active producer has an exact matching eligible or rejected status; +an interrupt candidate cannot bypass an unresolved producer. The allocation-age +token uses `RecoveryAge.tokenWidth(CoreParams)` and is compared with the +wrap-safe `RecoveryAge.older` relation. The token space must be more than twice +the maximum live ROB-member window so no live producer pair can be exactly +half-range ambiguous. + +`RecoveryPlanContract` defines equality while ignoring only `phase`, exact +membership in the compact suffix, and legal empty/non-empty suffix shape. +Recovery targets MUST use this helper rather than private global-age +comparisons or partial transaction matching. diff --git a/docs/spec/30-interfaces/top-external.md b/docs/spec/30-interfaces/top-external.md new file mode 100644 index 00000000..9c891f53 --- /dev/null +++ b/docs/spec/30-interfaces/top-external.md @@ -0,0 +1,35 @@ +# TOP external interface + +## Backpressured external CMD issue {#IFC-TOP-EXT-001} + + +TOP shall expose CMD as an independently backpressured output. Each command +shall carry the exact instruction and ROB member identities, opcode, and source +operands retained by IEX. An absent or blocked command sink shall retain the +transaction without mutation and shall not authorize a resolve or external +side effect. + +## External CMD Bundle {#MEC-TOP-EXT-001} + + +`TOPIO` projects one `Decoupled[CmdIssueTxn]` endpoint. Its `valid` and payload +remain stable until `fire`. The same fire participates in the matching +`RobNoflushTxn` consumption, external CMD acceptance, and no-value +`RobResolveTxn`; TOP contains no queue, retry owner, always-ready sink, or +independent completion path for this endpoint. + +## Complete external TOP endpoint {#IFC-TOP-EXT-002} + + +`TOPIO` is the sole platform boundary for instruction memory, one data-memory +lane per LSU request lane, GPR bootstrap, synchronous interrupt, debug, system +and CMD issue, LSU authorization/maintenance, commit, trap, trace, counters, +and LSU health. The interrupt request is sampled in the core clock domain; a +platform with asynchronous interrupt pins MUST synchronize and qualify them +before presenting `InterruptRequest`. No asynchronous reset or raw clock pin +is part of `TOPIO`. + +External memory requests use the typed `MemorySize` log2-byte encoding: +`Bytes1=0` through `Bytes64=6`. The 64-byte instruction/cache-line request is +therefore representable without truncation. Semantic 1/2/4/8-byte sizes inside +IEX and LSU remain separate from this external transport encoding. diff --git a/docs/spec/40-constraints/parameters.md b/docs/spec/40-constraints/parameters.md new file mode 100644 index 00000000..b14e996f --- /dev/null +++ b/docs/spec/40-constraints/parameters.md @@ -0,0 +1,88 @@ +# Core parameter contracts + +## Principal lane-width profile {#PRM-WIDTH-001} + + + +The maintained profiles MAY select 2, 4, 6, or 8 lanes. The selected profile +sets IFU fetch and CTU transfer width, CTU input and output width, OOO decode, +rename, D3-prefix, dispatch and retire width, and IEX issue width. W4 is the +default; every listed value remains an elaboration target. + +## Widths have one configuration source {#PRM-WIDTH-002} + + +Every box-local principal width MUST equal the corresponding value in the +central `WidthParams`. A box-local copy cannot silently select a different +profile. + +## Adjacent widths preserve an accepted prefix {#PRM-WIDTH-003} + + +IFU fetch capacity MUST cover the CTU output prefix, CTU input and output +capacity MUST cover their configured transfer, and OOO dispatch capacity MUST +cover the complete accepted D3 prefix. An unsupported or under-provisioned +combination MUST fail before hardware elaboration. + +## Execution and LSU resource topology {#PRM-RESOURCE-001} + + + +Execution-unit, issue-queue, load-pipe and store-pipe counts are explicit +parameters rather than aliases for lane width. Resource exploration MAY vary +positive counts subject to the cross-parameter capacity rules. + +## Default resource topology {#PRM-RESOURCE-002} + + +The default profile MUST provide two ALU pipes, one BRU pipe, two AGU pipes, +two STD pipes, one system/multicycle queue, one independent CMD issue queue, +two load pipes and two store pipes. + +## Central validation precedes publication {#PRM-VALIDATION-001} + + +A `CoreParams` value MUST pass centralized width, identity, storage and +resource validation before it is published to a module or interface +generator. Invalid widths, zero physical paths, insufficient queue capacity, +non-power-of-two identity stores, singleton BROB rings, and incompatible +adjacent widths MUST fail with a configuration error. BROB entries per STID +MUST be a power of two and at least two so native BID width is nonzero. + +## PC buffer geometry {#PRM-PC-BUFFER-001} + + + +The OOO PC buffer has independently configured entry、bank、write-port、 +read-port、replica、PC-offset、allocation-epoch and recovery-scan parameters. +The maintained W2/W4/W6/W8 profiles use 64 entries, three PC-base write ports, +six readyless read ports and three replicas. W2/W4 use four banks; W6/W8 use +eight banks so one retire prefix remains bank-coverable. A wider decode prefix +does not create extra PC-base write ports: D1/D2 admission must stop before a +packet would require more than three new PC bases. + +## Parameter projections own no state {#PRM-PROJECTION-001} + + +`CoreParams` is the sole public configuration source. An internal mechanism +may project immutable geometry from it, but that projection MUST own no +hardware state, create no alternate public boundary and change no transaction +semantics. + +## LSU capacities and identities remain independent {#PRM-LSU-SIZING-001} + + +Load-pipe count、load-return-pipe count、LIQ depth、STQ depth、ROB identity +capacity and full-LSID width MUST remain independently configured. The W4 +topology uses two load pipes and two store pipes; no forwarding helper may +infer a third load pipe. Unequal `16 STQ / 8 ROB / 40-bit LSID` geometry MUST +elaborate without truncating an identity or changing queue ownership. + +## Directed simulation may bound storage only {#PRM-SIMULATION-001} + + +Directed W2/W4/W6/W8 tests MAY use `SimulationParamProfiles` to reduce local +ROB、rename、IQ、LIQ、STQ and cache-related storage. Those profiles MUST preserve +the selected principal widths、the two-load/two-store topology and fixed +identity-field widths. They cannot replace main-profile interface、capacity、 +generated-RTL、timing or workload evidence. diff --git a/docs/spec/50-verification/benchmark-acceptance.md b/docs/spec/50-verification/benchmark-acceptance.md new file mode 100644 index 00000000..04e006cb --- /dev/null +++ b/docs/spec/50-verification/benchmark-acceptance.md @@ -0,0 +1,15 @@ +# Benchmark acceptance + +Task 18 accepts only a naturally executed ELF through emitted W4 `TOP` with +external memory, UART, and finisher behavior owned by the harness. Instruction +or commit replay is not accepted as a natural run. + +The bounded scalar linx-avs smoke is currently `BLOCKED_EXTERNAL_ARTIFACT`: +the canonical source entry is +`/Users/zhoubot/linx-isa/avs/compiler/linx-llvm/tests/run.sh`, its pinned clang +is absent, and the `avs` tree contains no ELF. The missing compiler is not +built and no fixture ELF may substitute for this gate. Once the pinned ELF is +available, acceptance requires finisher pass, nonzero IFU/CTU/OOO/IEX/LSU +activation, followed by the separately defined bounded architectural +cross-check. The natural harness itself declares `comparison_kind=none` and +does not manufacture a zero-mismatch claim. diff --git a/docs/spec/50-verification/contract-spine.md b/docs/spec/50-verification/contract-spine.md new file mode 100644 index 00000000..48ce7d5a --- /dev/null +++ b/docs/spec/50-verification/contract-spine.md @@ -0,0 +1,55 @@ +# Contract-spine verification + +## Single-chain structural check {#VER-ARC-001} + + +A structural test MUST inspect the elaborated TOP and reject a second stateful +core chain or policy state owned by TOP. + +## Linx semantic review gate {#VER-ARC-002} + + +Each imported mechanism MUST name its Linx contract and rejected foreign +semantics in a reviewable reference projection. + +## Replacement and deletion gate {#VER-ARC-003} + + +The deletion task MUST require passing replacement evidence and MUST reject old +state-owning identifiers in live source, tests, emitters, harnesses, and +current architecture pages. + +## Interface and parameter checks {#VER-ARC-004} + + +Executable tests MUST compare elaborated interface shapes with the generated +manifest and elaborate all width profiles 2, 4, 6, and 8, including invalid +cross-parameter combinations. + +## Ownership checks {#VER-ARC-005} + + +Unit and integration tests MUST prove single-owner ROB/commit/recovery, +atomic rename-map transitions, and non-blocking DTU observation. +Task-9 owner closure additionally requires `OOORobCommitSpec` and +`OOORecoverySpec` to prove exact ROB-member ordering, same-group branch suffix +recovery, semantic completion rejection without producer deadlock, BROB +BID/generation release validation, whole-prefix release rejection, final-member +BROB release, side-effect-free owner readiness plus one common commit fire, +typed block start/stop propagation, retained recovery source arbitration, ROB +request/response, one-prepare-per-target barriers, mismatched acknowledgement +rejection, and a multi-target recovery prepare/apply barrier. + +## Front-end and OOO pipeline checks {#VER-ARC-006} + + +Coverage MUST include 16-, 32-, 48-, and 64-bit instruction forms, template +expansion, complete identities, D1/D2 backpressure, ROB reservation, rename, +early completion, and suffix retry. + +## Dispatch and recovery checks {#VER-ARC-007} + + +Coverage MUST exercise every typed queue and default execution/LSU path, plus +recovery coincident with dispatch, completion, memory side effects, trap, and +interrupt. diff --git a/docs/spec/50-verification/ctu-conformance.md b/docs/spec/50-verification/ctu-conformance.md new file mode 100644 index 00000000..607f90b7 --- /dev/null +++ b/docs/spec/50-verification/ctu-conformance.md @@ -0,0 +1,27 @@ +# CTU conformance + +## Ordinary and template stream conformance {#VER-CTU-001} + + +`CTUSpec` shall check width-wide ordinary transfer, exact parent and +prediction preservation, FENTRY and FEXIT row recipes, expansion across more +than one D1 packet, cross-parent ordering, output stability under +backpressure, and W2/W4/W6/W8 packet shapes. `InstructionBufferSpec` shall +check retained FIFO order, pre-cycle-full backpressure, simultaneous +independent enqueue/dequeue, and stable output. + +## Recovery conformance {#VER-CTU-002} + + +`CTUSpec` shall check that prepare echoes the exact transaction without +mutation and that apply removes only the target STID. `InstructionBufferSpec` +shall check that recovery suppresses transfer on the apply cycle, removes all +matching slots, and preserves unrelated operations in their original order. + +## CTU ownership conformance {#VER-CTU-003} + + +`CTUSpec` shall inspect the elaborated CTU hierarchy and require that it +contains only the CTU decode, child-description, retained-buffer, and trace +owners. The hierarchy shall contain no ROB, BROB, rename, issue-queue, or LSU +state owner. diff --git a/docs/spec/50-verification/ifu-conformance.md b/docs/spec/50-verification/ifu-conformance.md new file mode 100644 index 00000000..e463db23 --- /dev/null +++ b/docs/spec/50-verification/ifu-conformance.md @@ -0,0 +1,45 @@ +# IFU conformance + +## Fixed delivery and backpressure conformance {#VER-IFU-001} + + +`IFUISideSpec` shall elaborate W2, W4, W6, and W8 IFU profiles, preserve +2-, 4-, 6-, and 8-byte instruction lengths, accept partial packets, and hold +the complete visible packet stable while CTU is stalled. + +## I-SIDE miss and cross-line conformance {#VER-IFU-002} + + +`IFUISideSpec` shall observe an ITLB miss, translation refill, I-cache miss, +ordered line-beat refill, and a cross-line instruction assembled into one +64-bit container. It shall inject a mismatched generation-qualified memory +response and prove that the live request remains unchanged. It shall also +inject a denied instruction-line response, prove that no line refill is +installed, and observe one fetch-fault packet with the original error cause. + +## Recovery and ownership conformance {#VER-IFU-003} + + +`IFUISideSpec` shall check exact prepare echo, a fenced matching apply, scoped +STID pruning, preservation of unrelated retained instructions, redirected +nonzero-STID progress, prediction metadata retention, and the absence of ROB +or BROB identity allocation from the IFU-to-CTU payload. + +## Observational trace conformance {#VER-IFU-004} + + +`IFUISideSpec` shall hold the trace consumer not ready across multiple +IFU-to-CTU transfers, prove that instruction delivery continues, and prove +that the already-presented trace packet remains stable. + +## B-SIDE and recovery conformance {#VER-IFU-005} + + +`IFUPredictionSpec` shall check public B-SIDE provider rank behavior, +checkpoint-owned stale training rejection, and elaboration under the +`linxcore.ifu` package. `IFURecoverySpec` shall check backend-over-prediction +redirect priority, retained redirect hold under backpressure, atomic +mispredict training plus recovery, and the absence of a direct IEX control +port. `IFUCTUIntegrationSpec` shall check retained IFU-to-CTU backpressure, +scoped recovery fencing, and W2/W4/W6/W8 public IFU elaboration with explicit +B-SIDE and redirect-recovery boundaries. diff --git a/docs/spec/50-verification/interface-conformance.md b/docs/spec/50-verification/interface-conformance.md new file mode 100644 index 00000000..b9ac7b8a --- /dev/null +++ b/docs/spec/50-verification/interface-conformance.md @@ -0,0 +1,62 @@ +# Interface conformance + +## Front-end packet conformance {#VER-IFC-FRONTEND-001} + + +`TopInterfaceSpec` shall elaborate W2, W4, W6, and W8 fetch and D1 packets, +check 64-bit instruction containers and continuous-prefix counts, and prove +that the IFU/CTU and CTU/OOO endpoints reuse the canonical payload types. + +## Backend dispatch and LSU conformance {#VER-IFC-BACKEND-001} + + +`TopInterfaceSpec` shall check class-specific OOO/IEX channels, an independent +CMD channel, two default load-address paths, two store-address paths, two +store-data paths, and identity-qualified resolves and load results. It shall +distinguish initial `LoadIssueTxn`, LIQ `LoadReissueTxn`, translated +`LoadRepickTxn`, speculative-dependent `LoadCancelTxn`, and terminal +`LoadResultTxn`; no queue row or lane may substitute for `MemoryIdentity`. +The same tests shall prove one `RobResolveTxn` per ROB member and independent +resident system/multicycle and CMD paths under backpressure. + +## Recovery and commit conformance {#VER-IFC-CONTROL-001} + + +`TopInterfaceSpec` shall check separate prepare and apply endpoints, complete +cutoff identities, an OOO-owned continuous commit prefix, and stable retained +payloads while a consumer applies backpressure. System and CMD tests shall +reject a noflush authorization for a non-head, locally faulted, or +recovery-targeted member; prove Recovery Prepare priority and withdrawal of an +unused killed authorization; and prove that authorization consumption, +side-effect acceptance, and the matching no-value `RobResolveTxn` fire +atomically and exactly once. + +## TOP external CMD conformance {#VER-IFC-TOP-EXT-001} + + +`TopInterfaceSpec` shall elaborate the `CmdIssueTxn` TOP endpoint in W2, W4, +W6, and W8, hold its complete identity and payload stable under backpressure, +and prove that an absent sink causes no CMD fire, resolve, or side effect. +`InterfaceManifestSpec` shall reject an always-ready sink or a second CMD +completion endpoint. + +## DTU and memory conformance {#VER-IFC-EDGE-001} + + +`TopInterfaceSpec` shall check observational trace connectivity and +generation-qualified instruction/data memory traffic without a DTU-owned +architectural-control state. + +The same tests MUST prove that external `MemorySize.Bytes64` elaborates as the +three-bit value six, every W4 LSU request/response lane is projected, and no +four-bit byte-count field can truncate a cache-line request. + +## Generated interface projection {#VER-IFC-MANIFEST-001} + + +`InterfaceManifestSpec` and +`tools/chisel/render_top_interface_manifest.py --check` shall compare the +checked-in JSON and Markdown projections with the endpoint and leaf shapes +derived from the elaborated canonical Bundles, including the external +`CmdIssueTxn` endpoint. Generated projections are +evidence and shall not define fields independently of the Scala types. diff --git a/docs/spec/50-verification/parameter-profiles.md b/docs/spec/50-verification/parameter-profiles.md new file mode 100644 index 00000000..c14c659a --- /dev/null +++ b/docs/spec/50-verification/parameter-profiles.md @@ -0,0 +1,63 @@ +# Parameter-profile verification + +## Principal profile elaboration check {#VER-PRM-001} + + +`CoreConfigurationSpec` MUST construct W2, W4, W6 and W8, compare every +box-local principal width with `WidthParams`, and reject unsupported or +under-provisioned combinations before elaboration. + +## Resource topology and validation check {#VER-PRM-002} + + +`CoreConfigurationSpec` MUST check the complete default IEX and LSU topology +and MUST exercise failure cases for invalid profile width, adjacent-width +capacity, D3-prefix dispatch capacity, zero load/store pipe counts, and a +singleton BROB ring that would otherwise publish zero-width native BID fields. +It MUST keep small legal BROB rings and the default 256-entry ring as explicit +native BID width checks. + +## Parameter projection check {#VER-PRM-003} + + +Focused tests MUST prove that internal parameter projections preserve +applicable width, identity, ROB, rename, queue and pipe sizing without +introducing a stateful hardware owner or alternate public boundary. The +central W8 profile MUST remain constructible through each active projection. + +## LSU external-size and identity check {#VER-PRM-005} + + +`TopInterfaceSpec`, `InterfaceManifestSpec`, and `LSUMemorySpec` MUST jointly +check independent LSU lane/capacity/identity widths and the typed external +memory-size encoding, including the exact `Bytes64=6` cache-line value. + +## Directed-simulation capacity profiles + +`SimulationParamProfiles` is bounded configuration for directed behavior, +elaboration, lint, and harness port validation that do not need the full +storage window. Its W2/W4/W6/W8 variants preserve the +selected fetch, CTU, decode, rename, D3, dispatch, issue, and retire widths, the +configured execution and LSU pipe counts, and every fixed transaction or +generation width. They may reduce local ROB, BROB, PC Buffer, rename, IQ, and LSU +queue capacities, including the local index widths derived from those +capacities. + +The scalar IQ minimum is four entries: with two banks this preserves two +addressable rows per bank and a nonzero reservation-slot width. Wider directed +profiles use the selected width's next power of two. + +The W8 directed profile is intentionally capped at sixteen one-instruction ROB +groups, twelve recipe uops per instruction, eight IQ entries, two LQ entries, +two STQ entries, and two store-commit entries. Sixteen ROB groups are the +smallest power-of-two capacity that can expose the nonwrapped tail after one +complete eight-group prefix. Rename and PC capacities remain at the smallest +legal values that retain that prefix. Twelve recipe uops is the minimum +accepted by the current OOO ordinary-group/CTU recipe invariant. This keeps +width and split-store behavior observable without reproducing the +full-capacity RTL volume in every behavioral simulation. + +These profiles are not full-capacity, timing, performance, or workload +evidence. Their generated RTL may prove bounded topology and harness +connectivity only; main-profile evidence continues to use +`ParamProfiles.W2/W4/W6/W8`. diff --git a/docs/spec/decisions/D-IEX-LSU-LOAD-001.md b/docs/spec/decisions/D-IEX-LSU-LOAD-001.md new file mode 100644 index 00000000..b8453298 --- /dev/null +++ b/docs/spec/decisions/D-IEX-LSU-LOAD-001.md @@ -0,0 +1,44 @@ +# IEX and LSU load-issue ownership decision + +## Separate program order, first issue, and LIQ replay ownership {#D-IEX-LSU-LOAD-001} + + +**Context.** A load carries program-order identity from OOO, execution identity +through IEX, and physical residency inside LSU. Giving all three identities to +one queue row would couple architectural age to a reusable physical index and +would make replay, backpressure, and precise recovery ambiguous. + +**Decision.** OOO allocates the full program-order `LSID`, the load-only `LID`, +the store-only `SID`, and the `YOST`/`YOLD` older-memory boundaries. IEX +allocates a non-reused memory transaction for +each retained memory uop; the independently issued STA and STD children of one +store share that transaction. IEX allocates both identities on the canonical +Dispatch-to-IQ acceptance edge, when the memory uop first becomes retained +IEX state. Every complete candidate then remains stable through issue and LIQ +backpressure. LSU owns LIQ residency and every later load-attempt transition. + +LIQ reissue and LIQ repick are distinct mechanisms. `LoadReissueTxn` is used +when address translation is still required; `LoadRepickTxn` is used when the +physical address is already available and the load-result path can run again. +Each accepted transition carries the exact current and next `MemoryIdentity`. +ROB identity, memory transaction, and `lsid` remain equal; attempt generation +advances exactly once. `pipeId` names the retained route of that attempt and +may change only as part of the accepted reissue or repick transition. +`LoadCancelTxn` flows from LSU to IEX only to cancel speculative dependents of +the current attempt; it neither frees LIQ residency nor creates the next +attempt. + +OOO recovery is the only terminal kill protocol. `RecoveryPlan` Prepare fences +affected lifecycle traffic without mutation, Apply prunes the matching IEX and +LSU state on the common transaction, and Abort preserves both. Transaction and +attempt serials never rewind. A LIQ/STQ row, ROB generation, or pipe lane is +never a substitute for the complete identity. + +**Consequence.** The selected ownership is option A: IEX owns transaction and +initial attempt allocation; LSU owns replay, repick, and rebind. Stale or +skipped-generation lifecycle inputs are drainable rejection events and cannot +produce resolve, wakeup, memory traffic, or owner mutation. + +**Supersession.** A later ownership decision must replace these channels and +both owner mutations atomically. Two live transaction or attempt allocators are +never a permitted compatibility state. diff --git a/docs/spec/decisions/D-IEX-ROB-RESOLVE-001.md b/docs/spec/decisions/D-IEX-ROB-RESOLVE-001.md new file mode 100644 index 00000000..581b4198 --- /dev/null +++ b/docs/spec/decisions/D-IEX-ROB-RESOLVE-001.md @@ -0,0 +1,28 @@ +# IEX to ROB resolve decision + +## Resolve one ROB member per transaction {#D-IEX-ROB-RESOLVE-001} + + +**Context.** One decoded instruction may create multiple uops and multiple +P/T/U destinations while still occupying one ROB member. ROB needs a precise +resolved/trap state transition, but it must not become a second physical +register-file or wakeup-data owner. + +**Decision.** `RobResolveTxn` names exactly one complete ROB member identity. +An ordinary terminal rendezvous resolves that member once. Destination ordinal +zero may be projected as `destinationIndex/value` for architectural +observation, while every valid P/T/U destination writes and wakes atomically +on the same terminal fire. A no-destination uop resolves with canonical-zero +destination fields. A precise trap resolves once with exact trap metadata and +without register-file write or wakeup. An early-resolved member is marked at +ROB admission and emits no later terminal resolve. A recovery-killed member +emits no resolve. + +**Consequence.** ROB stores resolved and trap state, not a multi-destination +value array. Backpressure retains the full resolve, register-file write, +wakeup, trace, and recovery rendezvous; none of those effects may occur from a +readiness check or a partial fire. + +**Supersession.** A later resolve-shape decision must replace the ROB consumer, +terminal producer, register-file writes, and wakeups in one cutover. Parallel +completion and resolve protocols are forbidden. diff --git a/docs/spec/decisions/D-IEX-SYS-CMD-001.md b/docs/spec/decisions/D-IEX-SYS-CMD-001.md new file mode 100644 index 00000000..0a19db1e --- /dev/null +++ b/docs/spec/decisions/D-IEX-SYS-CMD-001.md @@ -0,0 +1,45 @@ +# System, multicycle, and CMD issue decision + +## Keep system/multicycle and CMD residency independent {#D-IEX-SYS-CMD-001} + + +**Context.** System operations, multicycle execution, and externally consumed +CMD operations have different completion and backpressure conditions. Treating +any of them as an immediate value or routing them to an always-ready sink would +lose precise side-effect ordering. + +**Decision.** System and multicycle work share one resident queue; CMD has an +independent resident queue. Unsupported operations remain resident and fail +closed. OOO may issue one exact `RobNoflushTxn` only for the head member after +all input and legality checks complete without a pending trap, all older +effects are drained, and no recovery Prepare targets its STID. This transaction +authorizes one named side effect; it is not the scalar noflush window boundary +and is not a second resolve owner. + +IEX presents those completed checks as one exact `RobNoflushReadyTxn`. Its +valid beat is the NFRDY proof and must match the per-STID resident ROB head in +transaction, instruction, and ROB identity. OOO drains stale proofs without +granting authorization, preserves a matching proof under backpressure, and +suppresses a fired member until that exact head leaves residency. Arbitration +or progress on another STID cannot clear or duplicate that suppression. + +A no-destination system side effect uses `SystemIssueTxn`. The matching +noflush authorization, system issue, side-effect application, and no-value +`RobResolveTxn` form one atomic rendezvous. A CMD operation uses `CmdIssueTxn` +on the TOP external projection; the matching authorization, external issue, +and no-value resolve likewise fire atomically. A missing external sink applies +backpressure and cannot drop or auto-resolve CMD. Destination-producing system +operations fail closed until a response-bearing contract is specified. + +Recovery Prepare takes priority over new authorization. Apply removes killed +resident rows and unused authorization; Abort preserves them. A side effect +whose atomic rendezvous has fired is exactly once and cannot be undone by a +younger recovery. + +**Consequence.** System/multicycle and CMD capacity, wakeup, backpressure, and +verification remain independent even though both use ROB-authored precise +side-effect authorization. + +**Supersession.** Any response-bearing system or CMD design must replace the +corresponding request, authorization, resolve, and recovery behavior together. +An always-ready compatibility sink is never a valid transition mechanism. diff --git a/docs/spec/decisions/D-IFU-001.md b/docs/spec/decisions/D-IFU-001.md new file mode 100644 index 00000000..f221b3ff --- /dev/null +++ b/docs/spec/decisions/D-IFU-001.md @@ -0,0 +1,19 @@ +# IFU line-error decision + +## Reject erroneous line data before L1I installation {#D-IFU-001} + + +**Context.** The lower-memory response distinguishes denied and corrupt +instruction-line beats and carries an architectural error cause. Treating +those beats as zero data would discard the error and create executable bytes +that memory never supplied. + +**Decision.** The I-SIDE memory adapter terminates the active line assembly on +the first denied or corrupt beat. It retains the exact fetch request and error +cause, emits one canonical fetch-fault instruction, and does not publish an +L1I refill. Recovery may later discard that retained fault only by changing +the affected STID epoch. + +**Consequence.** CTU and OOO receive memory and translation fetch faults through +the same `FetchedInstruction` contract. No cache row or ordinary instruction +may be produced from partial or substituted line data. diff --git a/docs/spec/ndf.yaml b/docs/spec/ndf.yaml new file mode 100644 index 00000000..d57f3f4e --- /dev/null +++ b/docs/spec/ndf.yaml @@ -0,0 +1,5 @@ +project: linxcore +version: 0.1 +layers: L0,L1,L2,L3 +clause_heading: "## Title {#CLAUSE-ID}" +metadata_comment: "" diff --git a/docs/spec/refs/ndf.md b/docs/spec/refs/ndf.md new file mode 100644 index 00000000..3b9f55f7 --- /dev/null +++ b/docs/spec/refs/ndf.md @@ -0,0 +1,13 @@ +# Normative Design Framework projection + +## Documentation structure reference {#REF-NDF-001} + + + +The pinned repository informs clause IDs, refinement layers, typed +relationships, reference projections, decision records, and verification +coverage. LinxCore uses a deliberately small local profile implemented by +`tools/spec/check_ndf_profile.py`; it does not require the external CLI. + +NDF supplies document structure, not Linx architectural or microarchitectural +semantics. diff --git a/docs/spec/refs/superscalar-npu.md b/docs/spec/refs/superscalar-npu.md new file mode 100644 index 00000000..bba017d7 --- /dev/null +++ b/docs/spec/refs/superscalar-npu.md @@ -0,0 +1,13 @@ +# superscalarNPU interface projection + +## Typed interface organization reference {#REF-SNPU-001} + + + +The pinned checkout informs interface organization: group payloads by +transaction, keep box IO declarations near the top boundary, and make +connectivity reviewable independently of internal implementation. + +Its fixed lane shapes, NPU-specific payloads, and any direct recovery shortcut +are not LinxCore contracts. LinxCore interfaces derive widths from the central +profile and route recovery through the OOO-owned plan. diff --git a/docs/superpowers/plans/2026-07-31-core-mainline-restructure.md b/docs/superpowers/plans/2026-07-31-core-mainline-restructure.md new file mode 100644 index 00000000..e757af02 --- /dev/null +++ b/docs/superpowers/plans/2026-07-31-core-mainline-restructure.md @@ -0,0 +1,2087 @@ +# Core Mainline Restructure Implementation Plan + +> **For agentic workers:** REQUIRED SUB-SKILL: Use superpowers:subagent-driven-development (recommended) or superpowers:executing-plans to implement this plan task-by-task. Steps use checkbox (`- [ ]`) syntax for tracking. + +**Goal:** 建立唯一的 `TOP -> IFU -> CTU -> OOO -> IEX -> LSU` Chisel 主链，接入 `DTU`，支持主要宽度 2/4/6/8 配置，跑通无指令预录和无提交回放的 Dhrystone、CoreMark，并删除旧顶层、`Reduced*` 实现和过期改进文档。 + +**Architecture:** 采用并行新链替换方式：先冻结参数、跨 box typed Bundle 和状态所有权，再逐个接入 IFU、CTU、OOO、IEX、LSU、DTU，最后用自然 ELF、提交对比和恢复压力测试证明新链闭合后删除旧链。`TOP` 只实例化和路由；ROB/提交/精确恢复裁决属于 OOO，各 box 只拥有本地状态及本地清理动作。 + +**Tech Stack:** Scala 2.13、Chisel 7.3、sbt、ScalaTest/chiseltest、Verilator、Python 3 标准库、Linx QEMU、LinxCoreModel、仓内自然 ELF harness。 + +## Global Constraints + +- 对外公开的主要 Chisel module 名严格为 `TOP`、`IFU`、`CTU`、`OOO`、`IEX`、`LSU`、`DTU`；这些名字不添加 `LinxCore` 前缀。 +- Scala package 继续使用 `linxcore`，避免无关的全仓 package 迁移。 +- 参数定义只放在 `chisel/src/main/scala/linxcore/params/`。 +- 跨 box 的 payload、协议和 box IO 只放在 `chisel/src/main/scala/linxcore/top/interface/`；box 私有 entry、queue row、arbiter state 不得放入该目录。 +- IFU、OOO、IEX 的主要宽度必须能以 2、4、6、8 四种 profile elaboration；默认 profile 为 W4。 +- IEX 默认物理拓扑为 2 ALU、1 BRU、2 AGU、2 STD、1 system/multicycle queue、1 独立 CMD IQ。 +- LSU 默认物理拓扑为 2 load pipe、2 store pipe。 +- IFU 对 CTU 输出已经拼成 64-bit 容器的 16/32/48/64-bit 指令，不输出 `is_upper` 半指令协议。 +- CTU 位于 IFU 和 OOO 之间，拥有模板展开与 Instruction Buffer；FENTRY、FEXIT 和模板块展开成规范化 uop 后进入 Instruction Buffer。 +- OOO 范围固定为 D1、D2、D3、S1，以及 DEC、RENU、ROB、BROB；S1 后的 issue/read/execute 属于 IEX。 +- RENU 必须保留 atag，并分别输出 ptag、ttag、utag；P 绝对索引和 T/U 相对索引使用两套不同的 SMAP/CMAP/MAPQ 机制。 +- DTU 仅拥有 debug、trace 和性能观测；精确恢复、interrupt/trap 和 commit control 分布在 OOO、相关 box 与 TOP 路由中。 +- `a.txt`、`b.txt`、`superscalarNPU` 只提供机制、拓扑和接口组织参考， + 不定义 Linx ISA 语义。机制进入 `docs/spec/` 时必须改写为项目自身条款， + 不保留来源文件名或外部架构叙事。 +- NDF 只作为规范组织方法；不增加外部 NDF 工具依赖。 +- 不新增第三方依赖。规范检查器只使用 Python 3 标准库。 +- 每个状态只有一个 owner；迁移期 adapter 不得复制队列、map、ROB、cache、predictor 或恢复状态。 +- 所有可反压 payload 在 `valid && !ready` 时保持稳定；状态改变只发生在 owner 的 `fire`。 +- 跨周期、跨队列和异步返回必须携带完整、带 generation/wrap 的身份；只按 slot、低位 RID 或 PC 匹配必须失败关闭。 +- 实现任务采用测试先行；每个任务完成窄 UT、邻接 IT、生成 RTL lint 和 Lore 格式提交后，才能进入下一个依赖任务。 + +--- + +## 1. Authority, References, and Decision Rules + +### 1.1 Authoritative sources + +发生冲突时按以下顺序裁决： + +1. Linx ISA 仓内规范、生成 opcode metadata 和当前架构契约。 +2. Linx QEMU 的架构可见行为与 LinxCoreModel 的微架构行为。 +3. 本计划后续建立的 `docs/spec/` 稳定条款和已批准决策记录。 +4. 当前 Chisel 中已经通过 exact-identity、recovery 和 cross-check 门禁的模块。 +5. 外部参考资料。 + +任何外部参考与前四项冲突时，必须在 `docs/spec/decisions/` 记录“采纳、改写或拒绝”，禁止静默选择外部行为。 + +### 1.2 Reference identities + +| Reference | Frozen identity | Allowed use | +|---|---|---| +| `/Users/zhoubot/Documents/a.txt` | SHA-256 `693ee46c63799d64982cc98ddc9dbf1405d64d9ad5bf9918429ac6d8ca880f62` | OOO、IEX、LSU 的队列、级间边界、rename、ROB、dispatch、replay 机制参考 | +| `/Users/zhoubot/Documents/b.txt` | SHA-256 `98b1cc8277088508cbe5ce6f3d5d39643b1252ab64e5ca9e154d0eebb2e93405` | IFU decoupled engines、预测、checkpoint、buffer 和恢复机制参考 | +| `hengliao1972/normative_language` | `main@09cfe646931183caee82dd913f77f516b82134df` | 条款 ID、精化层、外部投影、决策记录和验证覆盖组织方法 | +| `TerryMarvoloYuan/superscalarNPU` | `origin/main@3ae82dbc2bd68346255bfb6d8175495490ae2d3a` | 按方向划分接口组、TOP 只连线、CMD 独立接口、LDA/STA/STD 分流和接口变更 fanout 参考 | + +### 1.3 Explicitly rejected copying + +- 不复制 superscalarNPU 固定四路的 `lane0...lane3` 扁平端口；改用参数化 `Vec`。 +- 不复制 superscalarNPU 的 32-bit `inst + is_upper` 跨槽协议；IFU 边界为完整 64-bit 容器。 +- 不复制 IEX 直接控制 IFU 的第二条恢复路径；IEX/LSU 报告事件，OOO 裁决，TOP 分发。 +- 不复制按目的 box 重复展开的 flush wire；使用统一 typed recovery transaction。 +- 不复制 `a.txt`、`b.txt` 中的外部 ISA 指令、异常级、condition flags、 + barrier、exclusive monitor 或寄存器命名。 +- 不把外部资料的固定资源数当作本项目常量；所有采纳值必须进入 `params/` 并通过本项目约束检查。 + +## 2. Target Source Layout + +```text +chisel/src/main/scala/linxcore/ +├── params/ +│ ├── CoreParams.scala +│ ├── WidthParams.scala +│ ├── IFUParams.scala +│ ├── CTUParams.scala +│ ├── OOOParams.scala +│ ├── IEXParams.scala +│ ├── LSUParams.scala +│ ├── DTUParams.scala +│ ├── ParamProfiles.scala +│ └── ParamChecks.scala +├── top/ +│ ├── TOP.scala +│ ├── EmitTOP.scala +│ └── interface/ +│ ├── Identity.scala +│ ├── Packet.scala +│ ├── IFUCTU.scala +│ ├── CTUOOO.scala +│ ├── OOOIEX.scala +│ ├── IEXLSU.scala +│ ├── Commit.scala +│ ├── Recovery.scala +│ ├── TrapInterrupt.scala +│ ├── Memory.scala +│ ├── DTU.scala +│ ├── TOPIO.scala +│ ├── IFUIO.scala +│ ├── CTUIO.scala +│ ├── OOOIO.scala +│ ├── IEXIO.scala +│ ├── LSUIO.scala +│ └── DTUIO.scala +├── ifu/ +│ ├── IFU.scala +│ ├── ISide.scala +│ ├── BSide.scala +│ ├── Prediction.scala +│ ├── FetchBuffer.scala +│ └── IFURecovery.scala +├── ctu/ +│ ├── CTU.scala +│ ├── TemplateDecode.scala +│ ├── TemplateExpand.scala +│ └── InstructionBuffer.scala +├── ooo/ +│ ├── OOO.scala +│ ├── DEC.scala +│ ├── RENU.scala +│ ├── PRename.scala +│ ├── TURename.scala +│ ├── ROB.scala +│ ├── BROB.scala +│ ├── Dispatch.scala +│ ├── CommitControl.scala +│ └── RecoveryControl.scala +├── iex/ +│ ├── IEX.scala +│ ├── IssueFabric.scala +│ ├── RegisterFiles.scala +│ ├── ALUPipes.scala +│ ├── BRUPipe.scala +│ ├── AGUPipes.scala +│ ├── STDPipes.scala +│ ├── SystemMulticycleQueue.scala +│ ├── CMDIssueQueue.scala +│ └── TerminalFabric.scala +├── lsu/ +│ ├── LSU.scala +│ ├── LoadPipes.scala +│ ├── StorePipes.scala +│ ├── LoadQueues.scala +│ ├── StoreQueues.scala +│ ├── MemoryDependency.scala +│ ├── Translation.scala +│ ├── L1D.scala +│ └── LSURecovery.scala +└── dtu/ + ├── DTU.scala + ├── DebugControl.scala + ├── TraceExport.scala + └── PerformanceCounters.scala +``` + +Box 私有实现可以继续拆分成小文件；上表给出必须存在的 owner 文件和目录边界，不要求把现有经过验证的小模块重新合并成大文件。 + +本计划的 Task 10–20 受 +[`2026-08-01-production-owner-atomic-cutover-design.md`](../specs/2026-08-01-production-owner-atomic-cutover-design.md) +约束。目标文件名定义 public box 和 owner 边界，不要求为了匹配文件名重写 +已经通过 production 证据的内部机制。IFU、OOO、IEX、LSU 的后续工作必须 +优先原地升级仓内 production mechanism；禁止创建第二个有状态 owner 再长期 +并行验证。 + +每个 subsystem 在 public interface 切换前可以执行 behavior-preserving preparation， +但 preparation 不得改变 active boundary、不得增加第二个状态 owner。interface +cutover 必须在一个 loop 内同时完成 production mechanism 改造、所有调用者更新、 +canonical box 接线、同层级 replacement evidence、旧入口删除、commit 和 push。 +临时 adapter 只能存在于未提交工作树，必须无状态且不得进入 cutover commit。 + +## 3. Canonical Transaction Shapes + +以下类型名构成唯一 canonical vocabulary。基础类型由 Task 3 创建； +`DecodedMemoryControl`、`MemoryOrderMeta`、load-attempt lifecycle、system +commit 和 engine-command 类型由 Task 13 在对应决策获批后追加。后续任务 +不得另造同义类型： + +```scala +final case class WidthParams( + fetchWidth: Int, + ctuOutputWidth: Int, + decodeWidth: Int, + renameWidth: Int, + dispatchWidth: Int, + issueWidth: Int, + retireWidth: Int +) + +class InstructionIdentity(p: CoreParams) extends Bundle +class RobIdentity(p: CoreParams) extends Bundle +class MemoryIdentity(p: CoreParams) extends Bundle +class PredictionMeta(p: CoreParams) extends Bundle +class FetchedInstruction(p: CoreParams) extends Bundle +class FetchedPacket(p: CoreParams) extends Bundle +class FrontEndOp(p: CoreParams) extends Bundle +class D1Packet(p: CoreParams) extends Bundle +class DecodedMemoryControl(p: CoreParams) extends Bundle +class DecodedUop(p: CoreParams) extends Bundle +class RenamedUop(p: CoreParams) extends Bundle +class MemoryOrderMeta(p: CoreParams) extends Bundle +class DispatchTxn(p: CoreParams) extends Bundle +class RobResolveTxn(p: CoreParams) extends Bundle +class LoadIssueTxn(p: CoreParams) extends Bundle +class StoreAddressTxn(p: CoreParams) extends Bundle +class StoreDataTxn(p: CoreParams) extends Bundle +class LoadResultTxn(p: CoreParams) extends Bundle +class LoadReissueTxn(p: CoreParams) extends Bundle +class LoadRepickTxn(p: CoreParams) extends Bundle +class LoadCancelTxn(p: CoreParams) extends Bundle +class RobNoflushTxn(p: CoreParams) extends Bundle +class SystemIssueTxn(p: CoreParams) extends Bundle +class CmdIssueTxn(p: CoreParams) extends Bundle +class RecoveryEvent(p: CoreParams) extends Bundle +class RecoveryPlan(p: CoreParams) extends Bundle +class CommitTxn(p: CoreParams) extends Bundle +class TrapEvent(p: CoreParams) extends Bundle +class TraceEvent(p: CoreParams) extends Bundle +``` + +Packet 统一使用 `count + Vec(maxWidth, payload)` 表示 slot0 最老的连续前缀；禁止同时维护另一份可产生洞的 valid mask。若外部 trace 需要 mask，只能从 `count` 派生。 + +`FrontEndOp` 是 CTU 到 OOO 的 tagged union： + +```scala +object FrontEndOpKind extends ChiselEnum { + val Encoded64, TemplateUop = Value +} + +class FrontEndOp(p: CoreParams) extends Bundle { + val kind = FrontEndOpKind() + val parent = new FetchedInstruction(p) + val templateOrdinal = UInt(8.W) + val templateCount = UInt(8.W) + val templateOpcode = UInt(p.opcodeWidth.W) + val templateImmediate = UInt(p.dataWidth.W) +} +``` + +`Encoded64` 的 64-bit 指令容器、原始 2/4/6/8-byte 长度、预测、fault 和 +architectural identity 都由 `parent` 携带，并在 OOO DEC 中完成 decode。 +`TemplateUop` 由 CTU 用显式的 ordinal/count/opcode/immediate 描述，禁止在 +`FrontEndOp` 中嵌套 `DecodedUop` 或递归解码 parent；它仍经过 D1/D2 的统一 +合法性、ROB identity intent 和反压处理，随后与 encoded 路径汇合成唯一的 +`DecodedUop`。本节的 Scala 名称必须与生成 interface manifest 一致；字段表 +以 Bundle elaboration 为准，计划和 NDF 条款不得维护另一份冲突的宽度真值。 + +## 4. NDF-Style Contract Spine + +本计划采用受限 NDF profile，不依赖外部 CLI： + +```text +docs/spec/ +├── ndf.yaml +├── 00-charter/{scope.md,glossary.md} +├── 10-architecture/{top.md,ownership.md,pipeline.md} +├── 20-behavior/{ifu.md,ctu.md,ooo.md,iex.md,lsu.md,dtu.md,recovery.md,commit-trap.md} +├── 30-interfaces/{top-external.md,ifu-ctu.md,ctu-ooo.md,ooo-iex.md,iex-lsu.md,recovery.md,commit.md,dtu.md,memory.md} +├── 40-constraints/{parameters.md,resources.md,timing.md} +├── 50-verification/{interface-conformance.md,module-coverage.md,benchmark-acceptance.md} +├── decisions/ +├── open/ +└── refs/{superscalar-npu.md,ndf.md} +``` + +条款前缀固定为： + +```text +ARC-TOP IFC-TOP-EXT IFC-IFU-CTU IFC-CTU-OOO IFC-OOO-IEX +IFC-IEX-LSU IFU CTU OOO IEX +LSU DTU REC CMT PRM +VER D Q REF-SNPU REF-NDF +``` + +层次固定为 L0 intent、L1 observable contract、L2 mechanism、L3 executable check。每个 `level=must layer=L1` 条款在主链启用前必须被至少一个 `VER-*` 条款通过 `verifies=` 覆盖。 + +### 4.1 Interface contracts as an NDF refinement graph + +接口设计同时维护三种结构： + +1. **Tree:** 每个跨 box 边界只有一个 `docs/spec/30-interfaces/*.md` + 归属文件，每个 payload 和完整 box IO 只有一个 + `linxcore/top/interface/*.scala` 定义位置。 +2. **Graph:** L2 Bundle/协议条款通过 `refines=` 指向 L1 可观察契约， + 通过 `depends-on=` 指向 identity、parameter、recovery 或 ownership 条款； + L3 检查通过 `verifies=` 指回被覆盖条款。跨边界宽度和资源耦合使用 + `couples-with=`，不在散文中隐式表达。 +3. **History:** 接口条款 ID 跨文件移动和标题重命名保持稳定。破坏性字段、 + 方向或时序变更必须在同一提交中更新 Bundle、所有 producer/consumer、 + generated manifest、验证条款和 `decisions/` 记录；被替代条款使用 + `superseded-by`，不得静默删除或复用 ID。 + +每个接口文件必须按以下精化层组织： + +| Layer | Required content | Acceptance evidence | +|---|---|---| +| L1 observable contract | producer、consumer、顺序、原子 fire、反压、恢复后的可观察结果 | adjacent-box IT | +| L2 mechanism | 唯一 Bundle 类型、方向、`count + Vec` 形状、完整 identity、owner、prepare/apply 处理 | Bundle shape UT、protocol assertions | +| L3 executable check | W2/W4/W6/W8 elaboration、stall stability、identity round trip、stale response rejection | ScalaTest/chiseltest + generated manifest check | + +每个 L1 公共接口契约都必须记录以下 NDF 风格事实。这些内容是语义要求， +不是第二份手工维护的端口表： + +| 契约事实 | 必须明确的决策 | +|---|---| +| 稳定身份 | 永久 clause ID、状态、`since`，以及被替代时的 `superseded-by` | +| 端点 | 精确 producer、consumer、方向和唯一 contract-home 文件 | +| 时钟域 | 时钟域、reset 置位/释放语义，以及输入是否为 raw/asynchronous | +| 传输 | handshake、原子 `fire`、顺序、反压保持、取消和重试行为 | +| 所有权 | 接受时分配或修改的状态，以及负责该变化的唯一 owner | +| 架构控制 | recovery、commit、trap/interrupt 和 debug 影响，包括适用处的 prepare/apply | +| 身份 | 拒绝 stale work 所需的完整 transaction identity 和 generation/wrap 字段 | +| 参数耦合 | 决定 lane 或位宽的中央参数；固定协议事实不得写成 `option` 条款 | +| 证据 | L2 Bundle/owner 投影，以及至少一个 L3 elaboration、assertion、UT 或 adjacent-box IT | + +初始 canonical core 只使用一个同步 clock/reset domain。未来任何 raw 或 +asynchronous 外部输入都必须在 `IFC-TOP-EXT-*` 中显式标注，由 TOP 边界上 +唯一、明确归属的 conditioner 终止，并在进入 box owner 前完成验证。 +仅有 `Flipped`、`Valid` 或 `Decoupled` 声明不能替代 CDC 契约。 + +L1/L2 文档不得复制 Scala 字段表。Scala Bundle elaboration 是字段名、位宽、 +嵌套和方向的可执行来源；生成的 JSON/Markdown manifest 是其可评审投影。 +NDF 条款规定语义、所有权和协议不变量，并链接 manifest 和测试证据。 + +两份外部参考承担不同职责：superscalarNPU 只帮助确定 typed transaction、 +方向分组和 TOP 连线的代码组织；NDF 只帮助确定接口契约如何被稳定 ID、精化边、 +版本历史和可执行证据追踪。前者不能定义 Linx payload 语义，后者不能替代 Scala +Bundle 或 RTL。最终唯一真值仍是 Linx `docs/spec` 条款、中央参数、可 elaboration +Bundle 以及由 Bundle 生成的 manifest。 + +### 4.2 Interface boundary matrix + +Task 3 先冻结八个 box/owner 边界，再允许 box 实现依赖它们； +Task 18 在唯一 `TOP` 切换时冻结 `top-external.md` 组合边界： + +| Contract home | Producer -> consumer | Data plane | Control/return plane | Required identity | +|---|---|---|---|---| +| `top-external.md` | Platform/harness <-> TOP | `TOPIO` composition of instruction/data memory, interrupt/debug ingress, commit/trap/trace egress | per-channel handshake plus declared clock/reset/CDC policy; no architectural state in TOP | each leaf retains the complete identity required by its home contract | +| `ifu-ctu.md` | IFU -> CTU | fixed-64-bit `FetchedPacket` continuous prefix | CTU backpressure; OOO-authored recovery routed through TOP | fetch generation, `stid`, block/instruction identity, prediction checkpoint | +| `ctu-ooo.md` | CTU -> OOO | `D1Packet[FrontEndOp]` after Instruction Buffer retention | OOO admission backpressure and recovery pruning | original instruction identity plus expansion member identity | +| `ooo-iex.md` | OOO -> IEX | atomic `DispatchTxn` routed by uop class | completion, fault and redirect events return to OOO | full ROB generation, `bid/rid/uid`, renamed tags | +| `iex-lsu.md` | IEX -> LSU | separate load-address, store-address and store-data transactions | load result, memory fault, retry/replay event | ROB identity plus LSID generation and split/access member | +| `recovery.md` | OOO -> all owners | typed `RecoveryPlan` prepare/apply phases | per-owner acknowledgement and stale-work rejection | recovery generation and precise cutoff identity | +| `commit.md` | OOO -> owners/TOP | ordered `CommitTxn` prefix and side-effect authorization | completion/ack only where architecturally required | ROB generation and architectural parent identity | +| `dtu.md` | boxes/TOP -> DTU | loss-tolerant trace/performance events | debug requests enter through typed TOP/OOO control path | event sequence plus originating instruction identity when applicable | +| `memory.md` | IFU/LSU <-> TOP memory adapters | independent instruction/data request and response channels | credit/backpressure/error return | transaction generation; never address-only matching | + +所有 Decoupled payload 都遵守 `valid && !ready` 全字段稳定；`fire` 之前 +receiver 不得消费或分配状态。数据流与 recovery/commit/debug 控制流使用不同 +transaction 类型，禁止用复用 opcode 或 sideband boolean 创建第二套隐式协议。 +IEX/LSU 只能报告事件给 OOO，不能形成直达 IFU 的恢复控制路径。 + +### 4.3 Parameter options and interface coupling + +主要宽度使用 NDF `option` 条款记录 `default=4`、`explore=2,4,6,8`， +并以 `couples-with` 显式连接 IFU transfer、CTU output、OOO +decode/rename/dispatch、IEX issue 和 packet manifest。执行单元数、LSU pipe +数、队列深度及 identity 位宽是独立参数，但任何组合必须在生成接口之前通过 +`ParamChecks`。已选默认值与仍允许 elaboration 的集合都保留在条款中， +避免把当前默认拓扑误写成不可配置常量。 + +### 4.4 IFU -> CTU -> OOO refinement chain + +前端接口不以一张扁平字段表作为设计源，而是按可观察行为、实现机制和验证证据 +形成一条可追踪的精化链： + +| Refinement layer | IFU -> CTU | CTU -> OOO | +|---|---|---| +| L1 observable contract | `IFC-IFU-CTU-001`: IFU 交付按程序序排列的完整指令前缀；stall 时保持稳定；恢复后不泄漏被清理指令 | `IFC-CTU-OOO-001`: CTU 交付保序的 encoded/template-op 前缀；OOO admission 反压不得丢失或重复成员 | +| L2 mechanism | `MEC-IFU-CTU-001`: `FetchedPacket(count, entries)`，每项携带完整 64-bit 容器、原始长度、fetch/prediction/fault identity；不携带临时 ROB/BROB allocation | `MEC-CTU-OOO-001`: `D1Packet(count, entries)`，成员为 `FrontEndOp` tagged union；模板展开成员保留 parent/member identity | +| L3 executable check | `IFUISideSpec`、`IFUCTUIntegrationSpec`、W2/W4/W6/W8 manifest、stall/recovery assertions | `CTUSpec`、`CTUOOOIntegrationSpec`、W2/W4/W6/W8 admission、identity round trip 和 recovery pruning | + +状态所有权沿该链只向前移动一次：IFU `FetchBuffer` 拥有已拼接 +`FetchedInstruction`；CTU `InstructionBuffer` 拥有已分类/展开的 +`FrontEndOp`；OOO D1/D2 才执行统一 decode、uop classification 和 +ROB/BROB identity admission。预测 checkpoint、fetch fault 和 instruction +identity 必须穿过 CTU 保持原值；CTU 不得预分配 ROB/BROB，也不得根据 IEX +资源限制裁剪 uop。恢复使用独立 typed transaction，不把 flush、redirect 或 +commit 掩码塞进数据 payload。 + +### 4.5 Interface change work order + +Task 3 之后的每个接口相关 implementation loop 必须以一份可复现工作单开始： + +1. 记录 `docs/spec` 所在 LinxCore commit 作为 spec baseline，并列出本任务 + 直接修改或实现的 L1/L2 clause ID。 +2. 读取这些 clause 在 `refines`、`depends-on`、`couples-with` 和 + `verifies` 图上的一跳邻域；禁止只看 Scala Bundle 后猜测语义。 +3. 在写 RTL 前列出 producer、consumer、TOP wiring、parameter check、 + clock/reset/CDC policy、recovery/commit handling、generated manifest 和 adjacent-box test 的 + fanout。任何一项不适用都要写出理由。 +4. 新字段或新通道必须先归入现有 contract home；若改变 observable + contract，则同一提交增加 decision record。替换既有条款时保留原 ID 并用 + `superseded-by` 指向新条款，不静默删除。 +5. 提交前运行 NDF checker、Bundle/manifest check 和被影响的 adjacent-box + integration test，并在 loop ledger 中记录 clause delta 与剩余未覆盖边界。 + +接口评审使用“语义 diff”而不只看文本 diff：逐项检查条款新增/修改/替代、 +typed edge 变化、L1 coverage 变化、Bundle leaf 变化及 endpoint fanout。 +测试发现的歧义先落为 `Q-*` open clause，再由 decision record 关闭；不得只在 +测试或会话记录中保留未决设计。 + +## 5. Execution Tasks + +### Task 1: Establish the contract spine and reference boundary + +**Files:** +- Create: `docs/spec/ndf.yaml` +- Create: `docs/spec/00-charter/scope.md` +- Create: `docs/spec/00-charter/glossary.md` +- Create: `docs/spec/10-architecture/top.md` +- Create: `docs/spec/10-architecture/ownership.md` +- Create: `docs/spec/10-architecture/pipeline.md` +- Create: `docs/spec/50-verification/contract-spine.md` +- Create: `docs/spec/refs/superscalar-npu.md` +- Create: `docs/spec/refs/ndf.md` +- Create: `tools/spec/check_ndf_profile.py` +- Create: `tests/test_ndf_profile.py` +- Create: `docs/chisel/mainline-loop-ledger.md` + +**Interfaces:** +- Consumes: 本计划、仓内架构文档和两个结构方法 reference identity。 +- Produces: 稳定 clause ID、owner 词汇表、外部参考投影规则和 `check_ndf_profile.py` CI 入口。 + +- [ ] **Step 1: Write failing checker tests** + +测试至少构造重复 ID、悬空 `[[ID]]`、缺少 `kind/level/layer/status`、L1 MUST 无 `verifies=`、错误 reference hash 五种失败样例，以及一个通过样例。 + +```python +def test_rejects_unverified_l1_must(self): + result = run_checker(fixture("unverified_l1_must")) + self.assertNotEqual(result.returncode, 0) + self.assertIn("missing verifies edge", result.stderr) +``` + +- [ ] **Step 2: Run the failing tests** + +Run: `python3 -m unittest tests.test_ndf_profile -v` + +Expected: FAIL because `tools/spec/check_ndf_profile.py` does not exist. + +- [ ] **Step 3: Implement the minimal checker and contract files** + +Checker CLI 固定为 +`python3 tools/spec/check_ndf_profile.py docs/spec [--verify-local-references]`。 +内部保持 clause parse、ID/link、L1 coverage 和 reference identity +validation 可独立测试，不把 Markdown 或 YAML parser 暴露为仓外 API。 + +只实现本计划使用的 metadata 子集；禁止引入 YAML/Markdown parser 依赖。 +普通 CI 只检查 reference revision/SHA-256 的格式与必填性，不要求 +本地 checkout 存在。开发机可显式传 `--verify-local-references`， +此时核对可用 checkout 中冻结的 identity。 + +- [ ] **Step 4: Run checker tests and the live spec check** + +Run: + +```bash +python3 -m unittest tests.test_ndf_profile -v +python3 tools/spec/check_ndf_profile.py docs/spec +``` + +Expected: PASS；输出 clause 数、L1 MUST 数、已覆盖数、开放 `Q-*` 数和 reference identity 检查结果。 + +- [ ] **Step 5: Commit** + +Commit intent: `Make the core contract independently reviewable before RTL moves` + +### Task 2: Create the parameter hierarchy and W2/W4/W6/W8 profiles + +**Files:** +- Create: `chisel/src/main/scala/linxcore/params/CoreParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/WidthParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/IFUParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/CTUParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/OOOParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/IEXParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/LSUParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/DTUParams.scala` +- Create: `chisel/src/main/scala/linxcore/params/ParamProfiles.scala` +- Create: `chisel/src/main/scala/linxcore/params/ParamChecks.scala` +- Create: `chisel/src/test/scala/linxcore/params/CoreConfigurationSpec.scala` +- Create: `docs/spec/40-constraints/parameters.md` +- Create: `docs/spec/50-verification/parameter-profiles.md` +- Modify: `chisel/src/main/scala/linxcore/common/CoreParams.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/OooParams.scala` + +**Interfaces:** +- Consumes: `PRM-*` clauses. +- Produces: `CoreParams`, `ParamProfiles.W2/W4/W6/W8`, module-specific parameter records and centralized cross-parameter validation. + +- [ ] **Step 1: Write failing profile tests** + +Tests必须检查四个 profile，默认 W4 拓扑，以及非法 width=3、IFU width 小于 CTU 输出、OOO dispatch 小于连续 D3 prefix、load/store pipe count 为零等失败情况。 + +```scala +Seq(2, 4, 6, 8).foreach { width => + it(s"accepts W$width") { + ParamChecks.validate(ParamProfiles.forWidth(width)) + } +} +``` + +- [ ] **Step 2: Run the failing test** + +Run: `bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec` + +Expected: FAIL because `linxcore.params` does not exist. + +- [ ] **Step 3: Implement the parameter records** + +核心形状固定为： + +```scala +final case class IEXParams( + issueWidth: Int = 4, + aluPipes: Int = 2, + bruPipes: Int = 1, + aguPipes: Int = 2, + stdPipes: Int = 2, + systemMulticycleQueues: Int = 1, + cmdIssueQueues: Int = 1 +) + +final case class LSUParams( + loadPipes: Int = 2, + storePipes: Int = 2, + loadQueueEntries: Int = 16, + storeQueueEntries: Int = 16 +) +``` + +把现有 `common.CoreParams` 和 `ooo.OooParams` 改成临时 value-only +type/constructor adapter；adapter 只转换参数，不能拥有状态。每个 subsystem +cutover 必须在最后一个调用者迁移后立即删除对应 adapter；Task 20 只允许清理 +无 active caller 的 residual adapter。 + +- [ ] **Step 4: Run profile tests and compile** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec +bash tools/chisel/build_chisel.sh +``` + +Expected: PASS for W2/W4/W6/W8；所有非法配置在 elaboration 前给出明确 `require` 消息。 + +- [ ] **Step 5: Commit** + +Commit intent: `Keep every width and resource choice explicit at one boundary` + +### Task 3: Create typed TOP interfaces and generated manifests + +**Files:** +- Create: every file listed under `top/interface/` in Section 2. +- Create: `chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala` +- Create: `chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala` +- Create: `chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala` +- Create: `tools/chisel/render_top_interface_manifest.py` +- Create: `docs/spec/30-interfaces/*.md` +- Create: `docs/chisel/generated/top-interface-manifest.json` +- Create: `docs/chisel/generated/top-interface-manifest.md` +- Modify: `docs/spec/50-verification/interface-conformance.md` + +**Interfaces:** +- Consumes: `CoreParams`, Section 3 transaction names, `IFC-*` clauses. +- Produces: all cross-box payloads, all box IO classes, generated interface manifest and protocol assertions. + +- [ ] **Step 1: Write L1/L2 interface clauses and the failing coverage check** + +为 Section 4.2 的八个 box/owner 边界分别建立唯一归属文件。 +每个文件至少包含一个 +L1 observable contract、一个 `refines=` 该契约的 L2 mechanism 条款， +以及预先声明的 L3 `VER-*` 覆盖边。先运行 NDF checker，确认缺少对应 +Bundle/manifest evidence 时 Task 3 仍未满足验收条件。 + +- [ ] **Step 2: Write failing Bundle shape and protocol tests** + +Tests覆盖四种 width、64-bit instruction、continuous-prefix count、complete identities、CMD 独立通道、2 LDA/2 STA/2 STD 通路、recovery prepare/apply，以及 stall 时 payload 稳定。 + +```scala +test(new InterfaceHoldProbe(ParamProfiles.W4)) { dut => + enqueueOnePacket(dut) + dut.io.out.ready.poke(false.B) + val held = snapshot(dut.io.out.bits) + dut.clock.step(3) + snapshot(dut.io.out.bits) shouldBe held +} +``` + +- [ ] **Step 3: Run the failing tests** + +Run: `bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec` + +Expected: FAIL because interface classes do not exist. + +- [ ] **Step 4: Implement transaction and box IO types** + +每个 transaction 只定义一次。`IFUIO`、`CTUIO`、`OOOIO`、`IEXIO`、`LSUIO`、`DTUIO` 组合这些 transaction；禁止复制字段形成 sender/receiver 两套类。 + +每个端口必须能追溯到一个 Section 4.2 contract home。producer 与 consumer +复用同一个 payload 类型，只在 IO 组合处改变方向。所有 packet 使用 +`count + Vec(maxWidth, payload)`；recovery、commit、trace、memory +response 使用各自 transaction，完整 identity 不得被 adapter 截断。 + +- [ ] **Step 5: Generate and verify manifests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec +python3 tools/chisel/render_top_interface_manifest.py --check +python3 tools/spec/check_ndf_profile.py docs/spec +``` + +Expected: PASS；JSON/Markdown 与 Bundle elaboration 一致，手工修改生成文件会被 `--check` 拒绝。 + +- [ ] **Step 6: Review the NDF trace and interface fanout** + +对每个 L1 `IFC-*` 条款检查至少一个 L2 `refines=` 和一个 L3 +`verifies=`；检查每个 manifest endpoint 都有 contract home，且没有 +sender/receiver 同义 Bundle、无直接 IEX/LSU-to-IFU 控制、无 slot-only +或 address-only 返回匹配。接口变更 fanout 必须覆盖所有 producer、 +consumer、TOP wiring、manifest 和验证条款。 + +- [ ] **Step 7: Commit** + +Commit intent: `Give every box one typed contract and one direction of authority` + +### Task 4: Build CTU and the Instruction Buffer boundary + +**Files:** +- Create: `chisel/src/main/scala/linxcore/ctu/CTU.scala` +- Create: `chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala` +- Create: `chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala` +- Create: `chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala` +- Create: `chisel/src/test/scala/linxcore/ctu/CTUSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ctu/InstructionBufferSpec.scala` +- Create: `docs/spec/20-behavior/ctu.md` + +**Interfaces:** +- Consumes: `Decoupled[FetchedPacket]` from IFU, typed recovery plan. +- Produces: `Decoupled[D1Packet]` to OOO and CTU trace events. + +- [ ] **Step 1: Write failing CTU tests** + +Cover ordinary pass-through, FENTRY expansion, FEXIT expansion, template producing more uops than one output packet, no cross-packet reorder, buffer full backpressure, recovery pruning, and W2/W4/W6/W8 packetization. + +- [ ] **Step 2: Run failing tests** + +Run: `bash tools/chisel/run_chisel_tests.sh --only CTUSpec` + +Expected: FAIL because CTU does not exist. + +- [ ] **Step 3: Implement CTU** + +`TemplateExpand` emits `FrontEndOpKind.TemplateUop`; ordinary instructions emit `Encoded64`。Instruction Buffer owns all retained entries and preserves identity/prediction metadata through backpressure. + +- [ ] **Step 4: Run CTU and interface gates** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only CTUSpec +bash tools/chisel/run_chisel_tests.sh --only InstructionBufferSpec +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +``` + +Expected: PASS with no combinational IFU-ready to OOO-ready path through CTU. + +- [ ] **Step 5: Commit** + +Commit intent: `Make template expansion a retained boundary instead of frontend glue` + +### Task 5: Consolidate the IFU I-SIDE and fixed-64-bit delivery + +**Files:** +- Create: `chisel/src/main/scala/linxcore/ifu/IFU.scala` +- Create: `chisel/src/main/scala/linxcore/ifu/ISide.scala` +- Create: `chisel/src/main/scala/linxcore/ifu/FetchBuffer.scala` +- Create: `chisel/src/test/scala/linxcore/ifu/IFUISideSpec.scala` +- Create: `docs/spec/20-behavior/ifu.md` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/frontend/ISide*.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/frontend/LinxCoreIfu.scala` + +**Interfaces:** +- Consumes: I-side memory request/response, redirect/recovery, prediction response. +- Produces: fixed-64-bit `FetchedPacket` to CTU and prediction request to B-SIDE. + +- [ ] **Step 1: Write failing I-SIDE tests** + +Cover 2/4/6/8 delivery, 2/4/6/8-byte input instruction lengths, cross-line assembly, ITLB miss, I-cache miss/refill, partial packet, output hold under CTU stall, scoped recovery, stale refill rejection and independent STID progress. + +- [ ] **Step 2: Run failing tests** + +Run: `bash tools/chisel/run_chisel_tests.sh --only IFUISideSpec` + +- [ ] **Step 3: Move proven mechanisms behind `IFU`** + +Reuse existing ITLB/L1I/miss-table/line-assembler logic by relocating or instantiating it under the new owner。Do not copy it into a second stateful implementation. + +- [ ] **Step 4: Run focused and generated RTL gates** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IFUISideSpec +bash tools/chisel/run_chisel_tests.sh --only CTUSpec +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +``` + +- [ ] **Step 5: Commit** + +Commit intent: `Make fixed-width instruction delivery independent of fetch geometry` + +### Task 6: Consolidate B-SIDE prediction and IFU recovery + +**Files:** +- Create: `chisel/src/main/scala/linxcore/ifu/BSide.scala` +- Create: `chisel/src/main/scala/linxcore/ifu/Prediction.scala` +- Create: `chisel/src/main/scala/linxcore/ifu/IFURecovery.scala` +- Create: `chisel/src/test/scala/linxcore/ifu/IFUPredictionSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ifu/IFURecoverySpec.scala` +- Create: `chisel/src/test/scala/linxcore/ifu/IFUCTUIntegrationSpec.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/frontend/BSide*.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/frontend/IfuRedirectArbiter.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridge.scala` + +**Interfaces:** +- Consumes: prediction request, OOO redirect/commit/training. +- Produces: prediction response and corrected fetch direction to I-SIDE. + +- [ ] **Step 1: Write failing predictor/recovery tests** + +Cover provider rank, BTB/TAGE/BIM/RAS/loop history ownership, checkpoint restore, correction before final prediction seal, mispredict redirect, redirect priority, repeated stall, stale training rejection and no direct IEX-to-IFU control. + +- [ ] **Step 2: Run failing tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IFUPredictionSpec +bash tools/chisel/run_chisel_tests.sh --only IFURecoverySpec +``` + +- [ ] **Step 3: Implement B-SIDE and recovery composition** + +All backend facts arrive through OOO-authored interfaces。IEX branch result may be present inside an OOO completion/recovery event but cannot connect directly to IFU. + +- [ ] **Step 4: Run IFU+CTU integration** + +Run: `bash tools/chisel/run_chisel_tests.sh --only IFUCTUIntegrationSpec` + +Expected: sustained traffic, retained backpressure, redirect and scoped cleanup pass in W2/W4/W6/W8. + +- [ ] **Step 5: Commit** + +Commit intent: `Keep prediction speculative while recovery authority remains singular` + +### Task 7: Build OOO D1/D2 decode and ROB identity admission + +**Files:** +- Create: `chisel/src/main/scala/linxcore/ooo/OOO.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/DEC.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/OOODecodeSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/CTUOOOIntegrationSpec.scala` +- Create: `docs/spec/20-behavior/ooo.md` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/ooo/OooD1Decode.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/ooo/OooD2Stage.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/ooo/OooOpcodeRecipeTable.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/backend/D1DecodeRenameROBIngress.scala` + +**Interfaces:** +- Consumes: `Decoupled[D1Packet]` from CTU. +- Produces: retained D2 decoded group carrying complete virtual ROB allocation + intent；physical ROB/BROB publication 仍由后续唯一 owner 完成。 + +- [ ] **Step 1: Write failing decode tests** + +Cover normal 16/32/48/64 encodings represented in 64 bits, template uop bypass, bid/rid/opcode, source/destination valid, atag, prediction metadata, illegal opcode trap, prefix acceptance and D1/D2 backpressure. + +- [ ] **Step 2: Run failing tests** + +Run: `bash tools/chisel/run_chisel_tests.sh --only OOODecodeSpec` + +- [ ] **Step 3: Implement DEC and D1/D2 stage records** + +DEC outputs exactly one common `DecodedUop` shape for encoded and CTU-expanded +inputs。D2 只有在整个连续 lane prefix 能被原子保留时才生成完整 RID/group/member +intent；D2 preview 不发布 physical ROB row，也不分配 BROB。已验证的 D3 allocator +保持 RID tail 的唯一可变 owner，BROB 在后续任务绑定 BID/generation。任何 legacy +adapter 都不得把 `CoreParams` 的 16-bit epoch/RID/BROB/resident generation +截断到旧的 8-bit 默认值。 + +- [ ] **Step 4: Run opcode parity and decode integration** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only OOODecodeSpec +bash tests/test_opcode_parity.sh +bash tools/chisel/run_chisel_tests.sh --only CTUOOOIntegrationSpec +``` + +- [ ] **Step 5: Commit** + +Commit intent: `Normalize every instruction form before speculative ownership begins` + +### Task 8: Build RENU with separate P and T/U rename machines + +**Files:** +- Create: `chisel/src/main/scala/linxcore/top/interface/OOOD2D3.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/RENU.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/PRename.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/TURename.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/RENUSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/RENUAtomicSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/TURenameSequenceSpec.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/OooParams.scala` +- Modify: `chisel/src/main/scala/linxcore/params/OOOParams.scala` +- Modify: `chisel/src/main/scala/linxcore/params/ParamChecks.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/OOOIEX.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/ooo/OooPRename.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/ooo/OooTURename.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/rename/*.scala` + +**Interfaces:** +- Consumes: D2 `DecodedUop` prefix, commit releases, recovery plan. +- Produces: D3 `RenamedUop` prefix with atag plus ptag/ttag/utag and reservation claims. + +`OOOD2D3.scala` is the canonical public internal-stage contract and defines +`RENUD2D3IO`, `RenameCommitReleaseEntry`, and `RenameCommitReleaseTxn`. +Each D3 lane preserves the Task-7 virtual ROB/group/member intent, +generation-qualified P/T/U rename history, separate T/U physical-tag and +MapQ-sequence generations, and wrap-qualified T/U sequences. Commit release +is a continuous, cross-domain all-or-none prefix; it is per uop and can carry +every destination history row, including zero-destination boundary uops. It +does not reuse the single-destination external `CommitEntry` shape. + +RENU is two-phase. D2 acceptance may retain one exact provisional P/T/U lease +per STID, but SMAP, CMAP, MapQ and visible physical ownership change only on the +common D3 publication fire. Task 10 later joins that fire with ROB/BROB and +dispatch readiness. Task 8 MUST NOT advance the physical RID tail, bind BID or +resident generations, allocate issue/LSU state, or choose commit/trap order. +Recovery prepare cannot revoke a D3 transaction already presented under +backpressure: it waits for that target transaction to fire, while an unrelated +presented STID and unrelated admissions remain eligible. + +- [x] **Step 1: Write failing rename tests** + +Cover 24 architectural P registers, free-list exhaustion, same-cycle dependency forwarding, SMAP/CMAP/MAPQ updates, T/U relative source lookup, sequential T/U allocation, block checkpoint, commit, wrap, replay and scoped recovery. + +Also cover W2/W4/W6/W8 behavioral publication, unequal P MapQ/T/U MapQ/ROB and +T/U physical capacities, generation-qualified stale release rejection, +provisional cancellation, stable D3 backpressure, and recovery that rebuilds P +SMAP from CMAP plus survivors while rewinding only the target STID's T/U suffix. +The backpressure test MUST hold one target-STID D3 row, present recovery prepare, +prove `prepare.ready == false` and bit-for-bit D3 stability, then prove prepare +acceptance only after that row fires. A separate two-STID test MUST cancel an +unpublished target lease while an unrelated row remains presented. + +- [x] **Step 2: Run failing tests** + +Run: `bash tools/chisel/run_chisel_tests.sh --only RENUSpec` + +- [x] **Step 3: Implement independent rename owners** + +P uses free-list physical allocation；T/U use ordered relative allocation。Shared wrapper performs one atomic prefix preparation and one common publication but never merges their internal maps. Central parameters own PTag and local-sequence generation widths plus independent queue/capacity checks; adapters cannot fall back to historical eight-bit generations. + +- [x] **Step 4: Run unequal-capacity and width profile tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only RENUSpec +bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec +bash tools/chisel/run_chisel_tests.sh --only OooParamsSpec +bash tools/chisel/run_chisel_tests.sh --only CoreParamsInterfaceClosureSpec +``` + +Expected: tests include unequal P MapQ/TU MapQ/ROB capacities and W2/W4/W6/W8. + +- [x] **Step 5: Commit** + +Commit intent: `Preserve absolute and relative register semantics with separate owners` + +### Task 9: Consolidate ROB, BROB, commit and precise recovery authority + +**Files:** +- Create: `chisel/src/main/scala/linxcore/ooo/ROB.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/BROB.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/CommitControl.scala` +- Create: `chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/OOORobCommitSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/rob/*.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/bctrl/BROB.scala` +- Migrate mechanisms from: `chisel/src/main/scala/linxcore/recovery/*.scala` + +**Interfaces:** +- Consumes: D2 allocation, D3 rename update, IEX/LSU completion and fault events, interrupt requests. +- Produces: commit transactions, trap selection, predictor training, recovery prepare/apply, ROB/BROB releases. + +- [x] **Step 1: Write failing owner tests** + +Cover grouped ROB allocation, per-STID BROB, exact completion, slot reuse rejection, in-order commit, early D3 completion for no-operand/boundary uops, interrupt at precise boundary, trap priority, branch recovery, LSU recovery, all-owner prepare barrier and apply acknowledgement. + +- [x] **Step 2: Run failing tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +``` + +- [x] **Step 3: Implement the single recovery plan owner** + +`RecoveryEvent` is retained at producers；OOO resolves one `RecoveryPlan` containing exact kill set and redirect。TOP distributes the same plan object; no box recomputes global age. + +- [x] **Step 4: Run ROB, BROB and recovery cross-gates** + +Run: + +```bash +bash tools/chisel/run_chisel_rob_bookkeeping.sh --robid-only +bash tools/chisel/run_chisel_brob_order_state_probe.sh +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +bash tests/test_rob_bookkeeping.sh +``` + +- [x] **Step 5: Commit** + +Commit intent: `Make one ROB decision govern commit, traps, and precise cleanup` + +### Task 10: Close Task 9 and freeze the production-owner cutover manifest + +**Files:** +- Modify: `chisel/src/main/scala/linxcore/ooo/ROB.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/BROB.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala` +- Modify: `chisel/src/test/scala/linxcore/ooo/OOORecoverySpec.scala` +- Create: `docs/chisel/production-owner-manifest.md` +- Create: `tools/chisel/check_production_owner_manifest.py` +- Create: `tests/test_production_owner_manifest.py` +- Modify: `docs/chisel/mainline-loop-ledger.md` + +**Interfaces:** +- Consumes: reviewed Task-9 ROB/BROB/commit/recovery owners and all live + Chisel emitters. +- Produces: a checked one-owner/call-site/deletion manifest that every later + atomic cutover must update. + +- [x] **Step 1: Close the current Task-9 RED cases** + +Require `ROB` to consume and stamp allocator-authored BROB identity on every +active D3 lane, including initially unbound lanes, while `BROB` stores only the +resulting ROB-prepared resident identity. Require `RecoveryControl` to drain a +target prepared beat outside `PrepareTargets` without acknowledgement so a +beat held before Prepare cannot survive abort into a same-transaction retry. + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only OOORobCommitSpec +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +``` + +Expected: both suites pass with zero failures; no Task-10 dispatch change is +mixed into this repair. + +- [x] **Step 2: Write the owner-manifest checker RED** + +Fixtures must reject duplicate ROB/rename/IQ/LSU/cache/recovery owners, +unknown emitters, missing production evidence, stateful adapters and legacy +deletion targets with active callers. + +Run: `python3 -m unittest tests.test_production_owner_manifest -v` + +Expected: FAIL because the checker and manifest do not exist. + +- [x] **Step 3: Record exact owner and call-site decisions** + +For every IFU、CTU、OOO、IEX、LSU、DTU state category record：canonical +owner、production mechanism files、public box、active callers、verification +fixtures、cutover task and files deleted at cutover。Classify `Reduced*`、 +`*Probe` and old `LinxCore*Top` as non-production entry points. + +- [x] **Step 4: Prove the checked baseline** + +Run: + +```bash +python3 -m unittest tests.test_production_owner_manifest -v +python3 tools/chisel/check_production_owner_manifest.py +python3 tools/spec/check_ndf_profile.py --verify-local-references docs/spec +git diff --check +``` + +- [x] **Step 5: Commit and push before starting Task 11** + +Commit intent: `Freeze one production owner before changing another boundary` + +The branch must report zero commits ahead of its configured upstream after the +push. If push is unavailable, stop before Task 11 and record the exact remote +blocker in the ledger. + +### Task 11: Atomically cut canonical OOO onto production D3/S1 mechanisms + +**Files:** +- Modify: `chisel/src/main/scala/linxcore/ooo/OOO.scala` +- Create or modify: `chisel/src/main/scala/linxcore/ooo/Dispatch.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooDispatch.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala` +- Modify: `chisel/src/test/scala/linxcore/ooo/OOODispatchSpec.scala` +- Modify: `chisel/src/test/scala/linxcore/ooo/OOOIntegrationSpec.scala` +- Modify: `docs/chisel/production-owner-manifest.md` +- Delete: displaced old D3/S1 public wrappers and tests named by the manifest. + +**Interfaces:** +- Consumes: canonical RENU D3 prefix, ROB/BROB prepared identities and + side-effect-free IEX/LSU credit previews. +- Produces: classed canonical `DispatchTxn` traffic plus exact early-completion + publication through the Task-9 ROB owner. + +- [ ] **Step 1: Freeze the D3/S1 mapping and write RED tests** + +Map every field from the proven reservation/dispatch mechanisms to +`D3RenameGroup` and `DispatchTxn`. Cover continuous-prefix admission, atomic +multi-owner credit, split STA+STD, CMD separation, no-op early completion, +suffix retry and recovery-coincident suppression. + +Run: `bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec` + +- [ ] **Step 2: Prepare mechanisms without adding owners** + +Refactor the existing selectors/classifiers in place. They may calculate +previews but may not own ROB、BROB、rename、commit or global recovery state. +Do not instantiate `OooO3RenameCoordinator` inside canonical `OOO`. + +- [ ] **Step 3: Perform the single OOO cutover** + +In one working-tree transaction update `OOO`、all IEX/LSU credit callers、 +tests、emitters and docs to the canonical payloads. Any temporary payload +adapter must be removed before the GREEN run. + +- [ ] **Step 4: Delete displaced OOO entry points and prove one owner** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only OOODispatchSpec +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +``` + +Expected: CTU through canonical D3/S1 passes W2/W4/W6/W8; the active graph has +one ROB/BROB/rename/recovery owner and no old O3 public wrapper. + +- [ ] **Step 5: Commit and push** + +Commit intent: `Cut production dispatch onto one canonical OOO owner graph` + +### Task 12: Prepare production IEX mechanisms without changing the live boundary + +**Files:** +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexIssue*.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIex*Pipeline.scala` +- Modify in place: `chisel/src/main/scala/linxcore/execute/ScalarGPRFile.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXMechanismSpec.scala` +- Modify: `docs/chisel/production-owner-manifest.md` + +**Interfaces:** +- Consumes: existing production `OooParams`/grouped-S1 behavior and the frozen + canonical `CoreParams`/`DispatchTxn` mapping. +- Produces: behavior-preserving IEX internals ready for one public-interface + cutover in joint Task 15; no new public IEX owner is activated in this task. + +- [ ] **Step 1: Characterize the production baseline** + +Add tests for per-class IQ residency、same-STID age、cross-STID fairness、P/T/U +atomic reads、retry、two ALU、one BRU、two AGU、two STD、terminal retention and +scoped recovery. Record which production child owns each state category. + +- [ ] **Step 2: Run the production-mechanism baseline** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexExecutionPipeline +``` + +- [ ] **Step 3: Refactor only private boundaries** + +Centralize value-only parameter conversion and split oversized private files +only where needed. Preserve the current public boundary for this task; create +no `IEX` state owner and no persistent canonical-to-old payload adapter. + +- [ ] **Step 4: Prove behavior preservation and topology** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexPhysicalProfileSpec +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +python3 tools/chisel/check_production_owner_manifest.py +``` + +- [ ] **Step 5: Commit and push** + +Commit intent: `Prepare production IEX owners without creating a second core` + +### Task 13: Close the canonical OOO-IEX prerequisites without a live cutover + +Task-12 review proved the private IEX mechanisms, but the first public-cutover +RED exposed three missing contracts: canonical D1 memory controls, a live +`OooMemoryOrderAllocator`/ROB recovery-tail join, and an IEX-LSU attempt +lifecycle. This task closes those prerequisites while the public `IEX` box +remains absent. The one-time public switch moves to the joint Task-15 cutover, +after LSU has prepared the matching LIQ replay owner. + +**Files:** +- Create: `docs/spec/decisions/D-IEX-LSU-LOAD-001.md` +- Create: `docs/spec/decisions/D-IEX-ROB-RESOLVE-001.md` +- Create: `docs/spec/decisions/D-IEX-SYS-CMD-001.md` +- Modify: `chisel/src/main/scala/linxcore/top/interface/CTUOOO.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/OOOIEX.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/IEXLSU.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/IEXIO.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/TOPIO.scala` +- Modify: `chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala` +- Modify: `chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala` +- Modify: `chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala` +- Modify: `docs/chisel/generated/top-interface-manifest.json` +- Modify: `docs/chisel/generated/top-interface-manifest.md` +- Modify: `docs/spec/30-interfaces/ooo-iex.md` +- Modify: `docs/spec/30-interfaces/iex-lsu.md` +- Create: `docs/spec/30-interfaces/top-external.md` +- Modify: `docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md` +- Modify: `docs/chisel/linxcore-chisel-ooo-improvement-design.md` +- Modify: `docs/chisel/linxcore-chisel-iex-improvement-design.md` +- Modify: `chisel/src/main/scala/linxcore/ooo/DEC.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/OOOD3S1Graph.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooPcBuffer.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/ROB.scala` +- Modify: `chisel/src/main/scala/linxcore/ooo/CommitControl.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexIssue*.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexTerminal*.scala` +- Rename in place: `chisel/src/main/scala/linxcore/ooo/OooIexLoadLiqAllocAdapter.scala` + to `chisel/src/main/scala/linxcore/iex/LoadIexIssuePipeline.scala` +- Rename in place: `chisel/src/main/scala/linxcore/ooo/OooIexLoadTerminalMetadata.scala` + to `chisel/src/main/scala/linxcore/iex/OooIexLoadTerminalMetadata.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexCanonicalLoadOwnership.scala` +- Modify in place: `chisel/src/main/scala/linxcore/ooo/OooIexBruPipeline.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/OOOMemoryOrderIntegrationSpec.scala` +- Create: `chisel/src/test/scala/linxcore/ooo/OOOPcBufferIntegrationSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXPrivateIngressSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXPrivateTerminalSpec.scala` +- Modify: `docs/chisel/production-owner-manifest.md` +- Modify: `docs/superpowers/specs/2026-08-01-production-owner-atomic-cutover-design.md` + +**Interfaces:** +- Consumes: Task-11 canonical `DecodedUop`/`DispatchTxn`, Task-12 production + IEX owners and the common canonical `RecoveryPlan`. +- Produces: frozen memory/order/attempt contracts and private production owners + that are directly composable by Task 15; it produces no public `IEX` module + and changes no live TOP boundary. + +- [x] **Step 1: Approve and record the three load-bearing decisions** + +Decision gate closed on 2026-08-02 with option A for IEX/LSU load-attempt +ownership and the resolve/system/CMD contracts below. + +Write the decision records with stable NDF identities and supersession rules. +The recommended contract is: + +1. `D-IEX-LSU-LOAD-001`: OOO allocates the full program-order `LSID`, the + load-only `LID`, the store-only `SID`, and the `YOST`/`YOLD` older-memory + boundaries; IEX allocates a non-reused transaction for each retained memory + uop on the Dispatch-to-IQ acceptance edge, shares it across one store's + STA/STD children, and allocates the initial load attempt on that same edge; + LSU owns LIQ residency and + every later reissue、repick and attempt rebind. No physical LIQ/STQ row, pipe lane + or ROB generation may synthesize any of these identities. +2. `D-IEX-ROB-RESOLVE-001`: one `RobResolveTxn` resolves one ROB member. + `destinationIndex/value` describe destination ordinal zero only when it is + architecturally useful; every P/T/U destination still writes and wakes in + the same terminal rendezvous, while ROB stores resolved/trap state rather + than a multi-destination value array. +3. `D-IEX-SYS-CMD-001`: system/multicycle and CMD remain separate resident + queues. Unsupported operations stay resident/fail closed. OOO grants an + exact head-only `RobNoflushTxn`; a system side effect executes through + `SystemIssueTxn`, while CMD leaves IEX only through `CmdIssueTxn` on the TOP + external projection. Neither class may be replaced by immediate-value + resolve or an always-ready sink. This + decision refines `IFC-TOP-EXT` and must name the external engine-command + endpoint before Task 15. + +The load-issue decision fixes these event rules: + +- IEX allocates one transaction for each retained memory uop, with one store + transaction shared by its STA/STD children. It also allocates the initial + attempt for a retained load, before any LSU sink fire. The + candidate identity remains bit-stable under backpressure and the non-resetting + serial advances once; cancellation never reuses it. +- `LoadReissueTxn` is LSU-to-IEX `Decoupled` for a LIQ load that still requires + address translation. It carries the previous and next complete identities; + ROB identity、transaction and `lsid` remain equal, attempt generation + advances exactly once, and `pipeId` may change only to the route retained by + this transition. Fire atomically rebinds the LIQ and retained IEX metadata, + then reuses the load-address pipe. The colliding normal IEX issue remains unpicked + or is retained for a later pick. +- `LoadRepickTxn` is LSU-to-IEX `Decoupled` for a LIQ load whose physical + address is already available. It carries the same current/next identity rule, + selects and retains its `pipeId` on fire, and uses the load-result pipe + without consuming the address-translation resource. IEX accepts only a + matching resident load attempt. +- `LoadCancelTxn` is LSU-to-IEX `Decoupled` and names the exact current attempt whose + speculative wakeup cannot produce a result. It clears dependent source-ready + state and cancels dependent pipes, but it does not remove LIQ residency or + allocate an attempt. The later reissue or repick performs the rebind. +- Recovery termination is not a point-to-point load-cancel protocol. OOO's + `RecoveryPlan` fences the affected STID during Prepare and prunes the exact + IEX metadata and LSU residency set only on Apply; Abort preserves both. +- stale、unknown and skipped-generation lifecycle inputs are consumed once into + a typed rejection event so they cannot deadlock a shared channel; they change + no owner state and cannot produce resolve、wakeup or memory traffic. +- `LoadResultTxn` must match the latest retained identity after every accepted + rebind. Return-pipe index, LIQ slot and ROB generation are never substitutes + for that comparison. +- recovery Prepare fences lifecycle traffic only for the affected STID and + computes the exact killed identity set without mutation. Apply emits one + common recovery mutation that prunes both IEX metadata and LSU LIQ state; + Abort changes neither. Transaction and attempt serial allocators never roll + back, and peer-STID LIQ rows survive. + +The unique IEX identity owner is `OooIexIssue`, where a logical memory uop +first becomes retained. `LoadIexIssuePipeline`, renamed in place from +`OooIexLoadLiqAllocAdapter` and moved under the IEX package in the same commit, +is a non-resident bridge that copies the retained identity into LIQ. Task 13 +updates every private caller and leaves no alias, wrapper or old class. Core +reset initializes the transaction value/generation and initial-attempt serials; +recovery Prepare/Apply/Abort never rewinds them. The +owner manifest gains state key `memory_transaction_and_initial_attempt_serial` +with private-mechanism cutover Task 13 and public-box activation Task 15. + +The ROB resolve decision fixes every case: + +| Case | `RobResolveTxn.fire` | ROB transition | Destination fields | RF/wakeup | Trap/recovery | +|---|---|---|---|---|---| +| ordinary, destination 0 valid | once at terminal rendezvous | unresolved to resolved | `valid=true,index=0,value=writeback(0)` | every valid destination fires atomically | none | +| ordinary, no destination | once at terminal rendezvous | unresolved to resolved | `valid=false,index=0,value=0` | none | none | +| multiple destinations | one member resolve | unresolved to resolved | ordinal 0 only | every valid P/T/U destination fires atomically | none | +| early-resolved | no terminal resolve | marked resolved by ROB admission | all zero/not emitted | none | none | +| precise trap | once at terminal rendezvous | resolved with trap | `valid=false,index=0,value=0` | none | exact `TrapEvent` | +| recovery-killed before fire | never | cleared by recovery apply | not emitted | none | recovery event/plan only | + +ROB retains resolved/trap state only and does not treat `value` as a rename or +retirement data owner. + +The system/CMD decision fixes ownership and backpressure: + +- `RobNoflushTxn` carries the exact ROB/instruction identity and is + valid only while that unresolved member is the ROB head, all input and + legality checks have completed without a pending trap, every older effect is + drained and no recovery prepare targets its STID. It is authorization, not + a second resolve or retained queue owner. The transaction names one member + proven safe for the requested side effect; it is not the scalar + `NOFLUSHRID` boundary itself. +- `RobNoflushReadyTxn` is the exact NFRDY proof from the execution and + side-effect owners. Its transaction, instruction and ROB identities match + the per-STID resident head; a stale proof drains without authorization. + Fired suppression remains attached to that STID and exact resident head, so + peer-STID arbitration cannot reauthorize it. +- `SystemIssueTxn` carries the same exact identity, opcode and + immediate, and is legal only for a no-destination recipe whose side effect is + owned by commit control. IEX keeps the system row resident and the request + stable until the matching permit and CommitControl ready are present; system + issue fire, side-effect application and the IEX no-value resolve fire + form one atomic rendezvous. Any destination-producing system opcode fails + closed until a response-bearing ISA contract is added. +- `CmdIssueTxn` carries exact ROB/instruction identity, opcode and source + values. IEX asserts it only while the matching head-only permit is valid and + keeps the CMD row resident until the TOP external command sink accepts it; + noflush authorization consumption、CMD issue fire and no-value resolve form one + atomic rendezvous. Recovery before that fire cancels the permit and preserves + external side-effect precision. An absent sink backpressures the CMD queue + rather than dropping or auto-completing the command. +- recovery prepare has priority over issuing a new permit or consuming a + system/CMD request. Apply removes a killed resident system/CMD row and any + unconsumed permit; abort preserves both. Once a head-authorized system or CMD + atomic rendezvous has fired, the external/commit side effect and ROB + resolve are exactly once and cannot be undone by a younger recovery. + +Do not begin Steps 2-5 until these three decisions are accepted. If the +accepted alternative differs, update the Bundle schemas and tests in this task +before implementation; never preserve two protocol variants. + +- [x] **Step 2: Add canonical memory control and order payloads test-first** + +Add `DecodedMemoryControl` to `DecodedUop`; its fields are `valid`、`isLoad`、 +`isStore`、address mode、access bytes、sign extension、offset、index transform、 +address/data source masks、writeback controls and normalized `requestCount`. +Add `MemoryOrderMeta` to +`DispatchTxn`; it carries only stable logical order (`requestCount`、 +`firstLsid`、`firstLid`、`firstSid`、`YOST` and `YOLD`), never +`MemoryTransactionIdentity`、attempt generation or physical pipe identity. + +Rename the displaced `LoadRequestTxn` to `LoadIssueTxn` and extend `IEXLSUIO` +with `LoadReissueTxn`、`LoadRepickTxn` and `LoadCancelTxn` from Step 1. Add +`SystemIssueTxn` to the OOO-IEX return direction, `RobNoflushTxn` to its +OOO-to-IEX direction, and `CmdIssueTxn` to `IEXIO`/the external TOP projection. Add interface +manifest assertions proving exact field widths, directions, W2/W4/W6/W8 vector +sizes, stable IDs and that `MemoryIdentity` fields are never derived from ROB, +RID, queue slot or lane ordinal. + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec +python3 tools/chisel/render_top_interface_manifest.py --check +python3 tools/spec/check_ndf_profile.py docs/spec +``` + +- [x] **Step 3: Restore the unique OOO memory-order owner** + +Migrate `OooMemoryOrderAllocator` in place to canonical D2/D3 payloads and +connect it to `OOOD3S1Graph`. DEC supplies normalized demand; allocator prepare, +ROB/BROB/RENU preparation and dispatch credit participate in one D3 fire. +Publication stores memory-before/after snapshots in ROB; recovery restores the +same per-STID tail from the canonical suffix plan. Do not add a serial counter +to `OooDispatch`. Add the exact `RobNoflushReadyTxn` NFRDY proof and extend the +integration fixture with a head-only system/CMD permit, denial for a non-head, +stale proof or recovery-fenced member, exact permit identity stability under +backpressure, per-STID exactly-once suppression and permit withdrawal before +any side effect when recovery prepare wins. + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only OOOMemoryOrderIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only OOORecoverySpec +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec +``` + +- [x] **Step 4: Convert private IEX ingress and terminal owners in place** + +Change the private IEX admission path to consume classed canonical dispatch +directly. Preserve `OooIexIssue` as the only IQ owner and +`OooIexOperandFiles` as the only P/T/U data/readiness owner; delete the old +grouped-S1 lease, dispatch-release dependency and global P/T/U readiness +shadow. A single accepted `StoreDispatchTxn` creates STA/STD children +atomically with one logical memory-order identity. + +Preserve `OooPcBuffer` as the only PC-base residency owner and convert it in +place to the canonical `CoreParams` and `RecoveryPlan` contracts. Its prepare +readiness joins RENU、ROB、BROB、memory-order and dispatch readiness on the one +D3 publication edge; its commit release joins the one commit-control edge; +prepare is side-effect free、Apply removes only the exact suffix and Abort +preserves it. `DispatchTxn` carries one typed base/index/offset/generation +`PcBufferIndexOffset`. IEX retains that PC buffer index and PC offset in the IQ and uses the +existing readyless PC-buffer read during I1→I2. Do not carry a complete PC +through the IQ、instantiate an IEX-side PC table or add a retained compatibility +adapter around the owner. + +Retain existing ALU/BRU/AGU and terminal state. Change terminal publication in +place to canonical `RobResolveTxn` and `RecoveryEvent`; RF writes、wakeup、trace、 +resolve and any recovery event still rendezvous on one terminal fire. +Recovery consumers use canonical `RecoveryPlan` directly and match apply/abort +with the complete transaction, never through an `OooResidencyRecoveryPlan` +projection. Private fixtures must cover initial identity allocation exactly +once, blocked rebind stability, atomic LSU/IEX rebind, launch of only the latest +attempt, common-edge recovery cancel/prune, abort preservation, peer-STID +survival, ordinal-zero/no-destination/trap/killed resolve cases and +head-authorized system/CMD side-effect fire. + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IEXPrivateIngressSpec +bash tools/chisel/run_chisel_tests.sh --only IEXPrivateTerminalSpec +bash tools/chisel/run_chisel_tests.sh --only OOOPcBufferIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only IEXMechanismSpec +bash tools/chisel/run_chisel_tests.sh --only OooIexTerminalFabricSpec +``` + +- [x] **Step 5: Prove the prerequisite graph and commit** + +Verify no public `IEX` module and no new IQ、RF、terminal、recovery or +memory-order owner exists. W2/W4/W6/W8 must elaborate the private production +graph; W4 remains 2 ALU、1 BRU、2 AGU、2 STD、1 system/multicycle queue and +1 CMD queue. + +Run: + +```bash +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +git diff --check +``` + +Commit intent: `Close the canonical prerequisites for the joint IEX LSU cutover` + +### Task 14: Prepare LSU mechanisms and resolve the two-pipe contract + +**Files:** +- Modify in place: `chisel/src/main/scala/linxcore/lsu/ScalarLSU.scala` +- Modify in place: `chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala` +- Modify in place: existing `STQ*`、`SCB*`、LIQ、ResolveQ、MDB、MissQ、 + refill、load-return and `ScalarL1D` mechanism files. +- Create: `chisel/src/test/scala/linxcore/lsu/LSUMechanismSpec.scala` +- Modify: `docs/chisel/production-owner-manifest.md` +- Modify: `docs/spec/40-constraints/parameters.md` + +**Interfaces:** +- Consumes: existing `ScalarLSUIO` behavior and the Task-13 approved + `IEXLSUIO` issue/reissue/repick/cancel contract plus `LSUIO` mapping. +- Produces: LSU internals ready for one public-boundary cutover in + Task 15, with independent physical queue, ROB identity and full-LSID sizes; + no public `LSU` or `IEX` module becomes live in this task. + +- [x] **Step 1: Freeze and test the mechanism baseline** + +Cover two STA、two STD、two load issues、typed initial attempt binding、exact +reissue/repick rebind and load cancel、STQ/SCB commit、LIQ/MDB/replay、miss/refill、load +return、L1D update and typed recovery. Add unequal-capacity W2/W4/W6/W8 +elaboration with 16 STQ rows、8 ROB entries and 40-bit LSID. + +- [x] **Step 2: Resolve the three-load-pipe assumption before cutover** + +Remove any helper requirement that derives a three-pipe topology +from the old external-forwarding shape. The W4 contract is exactly two load +pipes; queue depth、return-pipe count and ROB identity capacity remain +independent parameters. + +- [x] **Step 3: Refactor private LSU mechanisms only** + +Centralize value-only parameter conversion and canonical identity helpers +without changing the live `ScalarLSU` public boundary and without adding a +second STQ、SCB、LIQ、MDB、L1D or recovery owner. + +- [x] **Step 4: Prove behavior preservation** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only LSUMechanismSpec +bash tools/chisel/run_chisel_tests.sh --only ScalarLSU +bash tools/chisel/run_chisel_tests.sh --only ScalarLSULoadPath +bash tools/chisel/run_chisel_tests.sh --only ScalarL1D +bash tools/chisel/run_chisel_store_non_flush_gate_probe.sh +bash tools/chisel/run_chisel_brob_store_range_state_probe.sh +python3 tools/chisel/check_production_owner_manifest.py +``` + +The two-pipe forwarding IT uses one bounded simulation with explicit reset +between five scenarios. Its generated directory falls from 243 MiB to 47 MiB +while retaining exact result、hard recovery、typed recovery and BID fail-closed +coverage. + +- [x] **Step 5: Commit and push** + +Commit intent: `Prepare the LSU without cloning its state owners` + +### Task 15: Atomically cut OOO-IEX-LSU onto the canonical typed boundaries + +**Files:** +- Create: `chisel/src/main/scala/linxcore/iex/IEX.scala` +- Create: `chisel/src/main/scala/linxcore/lsu/LSU.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXIssueSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXPipesSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/IEXTerminalSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/OOOIEXIntegrationSpec.scala` +- Create: `chisel/src/test/scala/linxcore/lsu/LSUStoreSpec.scala` +- Create: `chisel/src/test/scala/linxcore/lsu/LSULoadSpec.scala` +- Create: `chisel/src/test/scala/linxcore/lsu/IEXLSUIntegrationSpec.scala` +- Create: `chisel/src/test/scala/linxcore/iex/OOOIEXLSUActivationSpec.scala` +- Create: `chisel/src/main/scala/linxcore/iex/EmitOOOIEXLSUActivationProbe.scala` +- Create: `tools/chisel/ooo_iex_lsu_activation_tb.cpp` +- Create: `tools/chisel/run_ooo_iex_lsu_activation_probe.sh` +- Create: `docs/spec/20-behavior/iex.md` +- Create: `docs/spec/20-behavior/lsu.md` +- Modify: `chisel/src/main/scala/linxcore/ooo/OOO.scala` +- Modify: `docs/chisel/production-owner-manifest.md` +- Modify in place: production LSU mechanisms prepared by Task 14. +- Modify in place: production IEX mechanisms prepared by Task 13. +- Delete: old `ScalarLSU` outer public boundary after its production children + are composed by `LSU`. +- Delete: displaced `ReducedScalar*` and `Reduced*` LSU owners、old IEX/LSU + wrappers、emitters、tests and docs named by the owner manifest after every + active caller moves in this same cutover. + +**Interfaces:** +- Consumes: canonical classed `DispatchTxn`/`StoreDispatchTxn`, exactly 2 + canonical load-address、2 store-address、2 store-data transactions, the + approved attempt lifecycle、OOO commit authorization、lower-memory responses + and canonical recovery. +- Produces: one public `IEX` and one public `LSU`; retained `LoadResultTxn`、 + atomic `RobResolveTxn`/RF write/wakeup、store/load resolve or fault、 + committed memory requests、reservation credits and recovery acknowledgement. + +- [x] **Step 1: Write both public boundaries RED** + +IEX RED covers stable classed-dispatch backpressure、exact identity retention、 +CMD/system independence、load-attempt rebind、two ALU、one BRU、two AGU、two +STD and one atomic completion/RF/wakeup/recovery terminal fire. LSU RED covers +address/data merge、pair operations、two-pipe independence、forwarding、 +unresolved older store、MDB replay、miss/refill、stale response rejection、 +lane-local backpressure、committed-store visibility and scoped recovery. +Add collisions for `rebind + cancel`, stale lifecycle events, affected-STID +recovery with a peer STID live, `CMD stalled + older BRU recovery`, system/CMD +head-permit withdrawal, and exactly-once head side-effect fire. + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only IEXIssueSpec +bash tools/chisel/run_chisel_tests.sh --only IEXPipesSpec +bash tools/chisel/run_chisel_tests.sh --only IEXTerminalSpec +bash tools/chisel/run_chisel_tests.sh --only LSUStoreSpec +bash tools/chisel/run_chisel_tests.sh --only LSULoadSpec +``` + +- [x] **Step 2: Perform one joint public-owner change** + +Create state-free composition shells `IEX` and `LSU`; change OOO, the prepared +private IEX graph, the prepared private LSU graph and every live caller directly +to canonical `OOOIEXIO`、`IEXLSUIO` and `LSUIO`. `IEX` owns no duplicate IQ、 +RF、FU、terminal or recovery state. `LSU` owns no duplicate STQ、SCB、LIQ、MDB、 +cache or recovery state. Initial identity binding and every rebind/launch/cancel +must use the approved typed lifecycle; remove every temporary conversion Bundle +before GREEN. + +- [x] **Step 3: Run pre-deletion cutover promotion** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only LSUStoreSpec +bash tools/chisel/run_chisel_tests.sh --only LSULoadSpec +bash tools/chisel/run_chisel_tests.sh --only IEXIssueSpec +bash tools/chisel/run_chisel_tests.sh --only IEXPipesSpec +bash tools/chisel/run_chisel_tests.sh --only IEXTerminalSpec +bash tools/chisel/run_chisel_tests.sh --only OOOIEXIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only IEXLSUIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only OOOIEXLSUActivationSpec --jobs 1 --artifact-budget-bytes 8589934592 +bash tools/chisel/run_chisel_tests.sh --only OOOIntegrationSpec --jobs 1 --artifact-budget-bytes 8589934592 +bash tools/chisel/run_chisel_store_non_flush_gate_probe.sh +bash tools/chisel/run_chisel_brob_store_range_state_probe.sh +bash tools/chisel/run_ooo_iex_lsu_activation_probe.sh +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +``` + +Expected: W2/W4/W6/W8 elaborate the one live OOO-IEX-LSU graph. W4 contains +2 ALU、1 BRU、2 AGU、2 STD、1 system/multicycle queue、1 CMD queue、2 load +pipes and 2 store pipes. No active `ReducedScalar*` IEX owner or displaced LSU +owner remains. + +The emitted-RTL activation probe is a retained subsystem harness, not a second +core. It drives a bounded canonical uop program through the emitted public +graph, compares completion、RF write、branch target and memory transactions to +literal reference results with zero mismatch, and requires nonzero ALU、BRU、 +AGU、STD、load、store、system and CMD activation. It also observes independent +backpressure, performs one exact rebind, and proves one affected-STID recovery +while a peer STID progresses. Old-chain deletion is forbidden unless this +generated-RTL bounded-reference evidence is GREEN. + +- [x] **Step 4: Delete both displaced chains and rerun closure** + +Only after every Step-3 gate is GREEN, delete the old reduced issue/RF/ALU/ +completion graph, old IEX public wrappers, the old `ScalarLSU` public shell and +reduced LSU owners after `rg` proves no active caller. Retain production IEX +helpers and production STQ/SCB/LIQ/MDB/cache helpers even when a historical +private class name remains; naming alone is not authority to rewrite state. + +Rerun the generated-RTL reference and structural closure on the post-deletion +tree: + +```bash +bash tools/chisel/run_ooo_iex_lsu_activation_probe.sh +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +git diff --check +``` + +- [x] **Step 5: Commit (push intentionally deferred for review)** + +Commit intent: `Switch OOO IEX and LSU once and retire both reduced chains` + +**Completion report (2026-08-03):** The atomic cutover is complete. The +post-deletion public suites passed for issue, pipes, terminal, store, load, +OOO-IEX, and IEX-LSU boundaries. `OOOIEXLSUActivationSpec` passed 8/8 cases +under the 8 GiB artifact gate (`4,511,675,564` bytes), and the retained emitted +RTL harness reproduced the exact bounded-reference counters with +`mismatch_count=0`. The production-owner checker reports 25 closed owners, 24 +classified emitters, and 6 declared adapters; its 45 tests pass. Chisel compile, +Verilator lint, shell syntax checks, module-index link closure, legacy-symbol +source closure, and `git diff --check` are green. The displaced reduced IEX/LSU +chains and legacy top/probe callers were deleted only after the promotion gates; +generated artifacts were removed before commit. The commit is local only so the +review gate can inspect the atomic change before any push. + +### Task 16: Close translation, cache, lower memory and recovery inside the live LSU + +**Files:** +- Create or modify: `chisel/src/main/scala/linxcore/lsu/Translation.scala` +- Modify in place: `chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala` +- Create or modify: `chisel/src/main/scala/linxcore/lsu/LSURecovery.scala` +- Modify: `chisel/src/main/scala/linxcore/lsu/LSU.scala` +- Create: `chisel/src/test/scala/linxcore/lsu/LSUMemorySpec.scala` +- Create: `chisel/src/test/scala/linxcore/lsu/LSUIntegrationSpec.scala` +- Modify: `docs/chisel/production-owner-manifest.md` +- Delete: residual displaced DTLB/cache/lower-memory/recovery wrappers named by + the manifest after equivalent evidence passes. + +**Interfaces:** +- Consumes: canonical virtual requests、lower-memory responses、commit and the + common prepare/prepared/apply/abort recovery transaction. +- Produces: physical memory requests、precise access faults、retained responses + and LSU quiescence from the already-live Task-15 LSU box. + +- [ ] **Step 1: Write memory-system RED tests** + +Cover DTLB hit/miss/refill、access classification、alignment、PMP/PMA、 +cacheable/device routing、LR/SC identity、fence drain、miss retry、response +generation mismatch and complete recovery quiescence. + +- [ ] **Step 2: Extend the live LSU without creating a side implementation** + +Reuse `ScalarL1D` and existing miss/refill/lower-memory mechanisms in place. +Translation replay and data replay remain separate. Recovery quiescence covers +queues、pipe reservations、MissQ/refill、load returns、store drain and all +outstanding lower-memory transactions. + +- [ ] **Step 3: Delete residual displaced memory wrappers** + +Update all callers in this loop and remove wrappers that no longer own a live +path. Do not create `L1D.scala` as a copy of `ScalarL1D`; rename only if the +same commit updates every caller and preserves the owner. + +- [ ] **Step 4: Run LSU promotion** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only LSUMemorySpec +bash tools/chisel/run_chisel_tests.sh --only LSUIntegrationSpec +bash tools/chisel/run_chisel_tests.sh --only IEXLSUIntegrationSpec +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +``` + +- [ ] **Step 5: Commit and push** + +Commit intent: `Close memory and recovery inside the one live LSU owner` + +### Task 17: Integrate distributed trap, interrupt, commit and DTU + +**Files:** +- Create: `chisel/src/main/scala/linxcore/dtu/DTU.scala` +- Create: `chisel/src/main/scala/linxcore/dtu/DebugControl.scala` +- Create: `chisel/src/main/scala/linxcore/dtu/TraceExport.scala` +- Create: `chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala` +- Create: `chisel/src/test/scala/linxcore/dtu/DTUSpec.scala` +- Create: `chisel/src/test/scala/linxcore/top/RecoveryIntegrationSpec.scala` +- Create: `docs/spec/20-behavior/dtu.md` +- Create: `docs/spec/20-behavior/recovery.md` +- Create: `docs/spec/20-behavior/commit-trap.md` +- Modify: `docs/chisel/production-owner-manifest.md` +- Delete: displaced debug/trace/system-control wrappers after canonical DTU + observation and request paths pass equivalent evidence. + +**Interfaces:** +- Consumes: commit/trace events, debug requests, interrupt inputs and distributed recovery acknowledgement. +- Produces: debug halt/resume requests, trace stream and performance counters. + +- [ ] **Step 1: Write failing distributed-control tests** + +Cover precise interrupt selection, synchronous fault priority, debug halt at commit boundary, trace non-backpressure, recovery prepare/apply fanout, one missing ack stall, unrelated-STID progress and no DTU ownership of commit or recovery state. + +- [ ] **Step 2: Run failing tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only DTUSpec +bash tools/chisel/run_chisel_tests.sh --only RecoveryIntegrationSpec +``` + +- [ ] **Step 3: Implement DTU and distributed control wiring** + +OOO selects the architectural action；each box applies local cleanup；TOP routes；DTU observes and may request debug state changes through typed interfaces. + +Integrate existing production trace、counter and system-control mechanisms in +place. DTU may not become a second commit/recovery state machine; temporary +old-to-new control adapters must be absent from the Task-17 commit. + +- [ ] **Step 4: Run trace schema gates** + +Run: + +```bash +bash tests/test_trace_schema_and_mem.sh +python3 tools/chisel/trace_schema_adapter.py --self-test +bash tools/chisel/run_chisel_tests.sh --only DTUSpec +python3 tools/chisel/check_production_owner_manifest.py +``` + +- [ ] **Step 5: Delete displaced control wrappers, commit and push** + +Commit intent: `Keep debug observable without creating a second control machine` + +### Task 18: Assemble TOP and the natural ELF harness + +**Files:** +- Create: `chisel/src/main/scala/linxcore/top/TOP.scala` +- Create: `chisel/src/main/scala/linxcore/top/EmitTOP.scala` +- Create: `chisel/src/test/scala/linxcore/top/TOPSpec.scala` +- Create: `chisel/src/test/scala/linxcore/top/TOPWidthProfilesSpec.scala` +- Create: `tools/chisel/top_natural_tb.cpp` +- Create: `tools/chisel/run_top_natural.sh` +- Create: `tools/chisel/run_dual_benchmark_gate.sh` +- Create: `tests/test_top_natural.py` +- Modify: `docs/spec/30-interfaces/top-external.md` +- Modify: `chisel/src/main/scala/linxcore/top/interface/EmitInterfaceManifest.scala` +- Modify: `chisel/src/test/scala/linxcore/top/interface/TopInterfaceSpec.scala` +- Modify: `chisel/src/test/scala/linxcore/top/interface/InterfaceManifestSpec.scala` +- Modify: `tools/chisel/render_top_interface_manifest.py` +- Modify: `docs/chisel/generated/top-interface-manifest.json` +- Modify: `docs/chisel/generated/top-interface-manifest.md` +- Modify: `docs/spec/10-architecture/top.md` +- Modify: `docs/spec/50-verification/interface-conformance.md` +- Modify: `docs/spec/50-verification/benchmark-acceptance.md` +- Modify: `docs/chisel/production-owner-manifest.md` +- Modify: `tools/chisel/check_production_owner_manifest.py` +- Delete: `chisel/src/main/scala/linxcore/top/LinxCore*Top.scala` +- Delete: corresponding old top emitters、harness entry points and top-only + tests after the canonical TOP smoke and bounded comparison pass. + +**Interfaces:** +- Consumes: all box IOs, external memory, interrupt and debug pins. +- Produces: emitted `TOP.sv`, the manifested external `TOPIO` contract, + commit/trace output, UART/finisher and natural-run manifests. + +- [ ] **Step 1: Write failing TOP connectivity tests** + +Tests instantiate W2/W4/W6/W8 and assert every cross-box field is driven once, no box IO is tied off in W4, no direct IEX-to-IFU control exists, TOP contains no Queue/Reg-based architectural owner and all trace channels are non-blocking. Add a failing manifest assertion that `TOPIO` is present as the external composition endpoint and every leaf resolves to `IFC-TOP-EXT-*`; that clause may depend on the existing memory、commit and DTU leaf contracts without copying their payload definitions. The contract test must also assert the single core clock/reset domain, preserve the Task-13 `CmdIssueTxn` ready/valid endpoint without an always-ready sink, and reject an unqualified raw/asynchronous input. + +- [ ] **Step 2: Run failing tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only TOPSpec +bash tools/chisel/run_chisel_tests.sh --only TOPWidthProfilesSpec +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec +``` + +- [ ] **Step 3: Implement TOP and harness** + +`TOP` instantiates exactly one IFU、CTU、OOO、IEX、LSU、DTU。Harness owns ELF memory loading、UART、finisher 和 manifest formatting but no instruction/commit oracle. + +This is the one active top-emitter cutover. Update build、CI、Verilator、trace +and benchmark callers、the owner checker inventory、the machine-readable +production entry-point row and its exact evidence in the same loop. The owner +manifest must refer to this as Task 18. No old top may remain callable after +the cutover commit. + +- [ ] **Step 4: Run elaboration, lint and harness self-tests** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only TOPSpec +bash tools/chisel/run_chisel_tests.sh --only TOPWidthProfilesSpec +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec +python3 tools/chisel/render_top_interface_manifest.py --check +python3 tools/spec/check_ndf_profile.py docs/spec +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +python3 -m unittest tests.test_top_natural -v +``` + +- [ ] **Step 5: Run bounded canonical smoke, delete old tops, commit and push** + +Run a bounded scalar linx-avs ELF through emitted W4 `TOP` and require nonzero +IFU/CTU/OOO/IEX/LSU activation plus zero architectural mismatch for the +captured prefix. Then delete the old tops and rerun: + +```bash +python3 tools/chisel/check_production_owner_manifest.py +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_verilator_lint.sh +``` + +Commit intent: `Expose one routable core without moving ownership into TOP` + +### Task 19: Run end-to-end functional and benchmark promotion + +**Files:** +- Modify: `tools/chisel/run_top_natural.sh` +- Modify: `tools/chisel/run_dual_benchmark_gate.sh` +- Create or modify: `tools/chisel/run_scalar_linx_avs_gate.sh` +- Modify: `tests/test_dhrystone_crosscheck_1000.sh` +- Modify: `tests/test_coremark_crosscheck_1000.sh` +- Create: `tools/chisel/run_top_recovery_stress.sh` +- Create: `docs/chisel/top-mainline-benchmark-evidence.md` +- Modify: `docs/spec/50-verification/module-coverage.md` +- Modify: `docs/spec/50-verification/benchmark-acceptance.md` + +**Interfaces:** +- Consumes: emitted W4 TOP and frozen workload ELFs. +- Produces: natural manifests, revision manifests, commit traces, cross-check reports and activation counters for every box. + +- [ ] **Step 1: Freeze workload identities** + +Record exact scalar linx-avs、Dhrystone and CoreMark ELF paths、SHA-256 values、 +runner SHA-256、TOP git SHA、superproject SHA、reset PC/SP and completion +signature before running. All workloads must use the Task-18 active TOP; +reduced replay or old-top evidence is rejected. + +- [ ] **Step 2: Run scalar linx-avs promotion first** + +Run: `bash tools/chisel/run_scalar_linx_avs_gate.sh --top TOP --profile W4` + +Expected: every selected scalar AVS ELF starts from real fetch, terminates +naturally, reports nonzero activation for all required boxes and has zero +bounded architectural mismatch. + +- [ ] **Step 3: Run Dhrystone without oracle or replay** + +Run: + +```bash +bash tools/chisel/run_top_natural.sh \ + --elf ../../workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/dhrystone/dhrystone.elf \ + --build-dir generated/top-mainline/dhrystone \ + --max-cycles 3000000 +``` + +Expected: exit 0, `terminal_status=finisher_pass`, no unsupported service, no unexpected trap, nonzero commit count, and nonzero IFU/CTU/OOO/IEX/LSU activation. + +- [ ] **Step 4: Run CoreMark without oracle or replay** + +Run: + +```bash +bash tools/chisel/run_top_natural.sh \ + --elf ../../workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/coremark/coremark.elf \ + --build-dir generated/top-mainline/coremark \ + --max-cycles 3000000 +``` + +Expected: same functional conditions as Dhrystone. + +- [ ] **Step 5: Run bounded architectural cross-checks** + +Run: + +```bash +bash tests/test_dhrystone_crosscheck_1000.sh +bash tests/test_coremark_crosscheck_1000.sh +``` + +Expected: 1000 compared architectural commits with zero mismatch for each workload；manifests identify the same ELF bytes used by natural runs. + +- [ ] **Step 6: Run the dual benchmark gate** + +Run: + +```bash +bash tools/chisel/run_dual_benchmark_gate.sh \ + --build-root generated/top-mainline/dual +``` + +Expected: both functional runs pass。IPC is recorded as a baseline and is not allowed to be omitted；a later performance campaign may raise a numerical IPC threshold without changing functional acceptance. + +- [ ] **Step 7: Run recovery and long-latency stress** + +Run: `bash tools/chisel/run_top_recovery_stress.sh --profile W4 --seed-count 100` + +Expected: all seeds terminate, no duplicate commit, no stale writeback, no lost recovery ack, no committed wrong-path memory side effect. + +- [ ] **Step 8: Check the unique owner graph, commit and push evidence** + +Run: `python3 tools/chisel/check_production_owner_manifest.py` + +Commit intent: `Prove the new core chain with natural workloads and exact commits` + +### Task 20: Remove residual orphans and close the repository + +**Files:** +- Delete: residual unreachable `Reduced*`、old top、compatibility adapter、probe + and test files that earlier subsystem cutovers were unable to remove only + because another not-yet-cut caller still existed. +- Delete: parameter/interface migration helpers with no canonical caller. +- Delete: `docs/chisel/linxcore-chisel-ifu-improvement-design.md` +- Delete: `docs/chisel/linxcore-chisel-ooo-improvement-design.md` +- Delete: `docs/chisel/linxcore-chisel-iex-improvement-design.md` +- Delete: `docs/chisel/linxcore-chisel-lsu-improvement-design.md` +- Delete: `docs/chisel/linxcore-chisel-microarchitecture-improvement-design.md` +- Delete: obsolete natural harness and runner files replaced by Task 18. +- Modify: `docs/chisel/README.md` +- Modify: `docs/chisel/module-index.md` +- Modify: `docs/architecture/linxcore_top_design.md` +- Modify: `docs/architecture/interfaces.md` +- Modify: `docs/chisel/production-owner-manifest.md` +- Modify: build/test file lists and CI entry points. + +**Interfaces:** +- Consumes: passing Task 19 evidence. +- Produces: one live implementation chain, no compatibility owner and current documentation pointing only to TOP/IFU/CTU/OOO/IEX/LSU/DTU. + +- [ ] **Step 1: Prove earlier cutovers already removed active legacy owners** + +Run the owner manifest checker and add a repository gate that rejects live +old-chain identifiers: + +```bash +python3 tools/chisel/check_production_owner_manifest.py +if rg -n '(class|object|new)[[:space:]]+(Reduced[A-Za-z0-9_]*|LinxCore[A-Za-z0-9_]*Top)' \ + chisel/src/main/scala chisel/src/test/scala; then + echo "old Chisel chain remains" >&2 + exit 1 +fi +``` + +The gate may allow historical commit text, but not live source、tests、emitters、 +harnesses or current architecture pages. Any stateful legacy owner discovered +here is a failed earlier cutover: repair that subsystem and rerun its promotion +gate before continuing Task 20. + +- [ ] **Step 2: Delete residual non-stateful orphans** + +Verify Task-19 natural manifests and cross-check reports, then delete only +unreachable residual wrappers、aliases、fixtures、docs and tool entries. Task 20 +must not be the first deletion point for an active state owner. + +- [ ] **Step 3: Remove adapters and duplicate owners** + +Delete parameter adapters from Task 2、old interface aliases from Task 3 and +any remaining temporary migration wrapper from Tasks 4–18。Do not keep dead +code under an archive source directory；Git history is the archive. + +- [ ] **Step 4: Run the complete closure suite** + +Run: + +```bash +python3 tools/spec/check_ndf_profile.py docs/spec +bash tools/chisel/build_chisel.sh +bash tools/chisel/run_chisel_tests.sh +bash tools/chisel/run_chisel_verilator_lint.sh +bash tools/chisel/run_dual_benchmark_gate.sh --build-root generated/top-mainline/final +cmake -S . -B build +cmake --build build -j"$(sysctl -n hw.ncpu 2>/dev/null || nproc)" +bash tests/test_stage_connectivity.sh +bash tests/test_runner_protocol.sh +bash tests/test_cosim_smoke.sh +bash tests/test_opcode_parity.sh +bash tests/test_trace_schema_and_mem.sh +bash tests/test_rob_bookkeeping.sh +bash tests/test_block_struct_pyc_flow.sh +``` + +Expected: all commands pass；old-chain grep returns no matches；`git status --short` is empty after evidence cleanup and intended commits. + +- [ ] **Step 5: Update current documents and remove superseded plans** + +Current architecture pages must point to `docs/spec/` clauses and generated interface manifest。Historical rationale remains in Git；过期改进计划不保留为并列权威。 + +- [ ] **Step 6: Commit, push and update the superproject gitlink** + +Commit intent: `Leave one maintained core after replacement evidence closes` + +## 6. Review and Stop Rules + +Every task ends at a reviewer gate。A task is not complete when only its unit test passes；it must also pass the listed adjacent interface and generated RTL gate。 + +Stop and repair the current task when any of the following occurs： + +- a payload changes while stalled； +- a state mutation occurs without owner `fire`； +- a completion or recovery matches only a slot/low RID； +- one instruction partially mutates ROB/rename/IQ/LSU owners； +- TOP contains queue、age、rename、commit、cache 或 recovery policy； +- a reference mechanism introduces non-Linx architectural semantics； +- W2/W4/W6/W8 中任一 profile 无法 elaboration； +- natural benchmark uses expected rows、commit replay、instruction injection 或 QEMU oracle； +- a preparation task changes the public interface or creates a second state owner； +- a cutover commit retains a temporary adapter、old callable emitter or displaced + state owner； +- a deletion removes the only passing implementation before its replacement has + equivalent same-level evidence； +- a green loop ends with local commits not pushed to the configured upstream。 + +## 7. Completion Evidence Matrix + +| Requirement | Required evidence | +|---|---| +| Major widths support 2/4/6/8 | `CoreConfigurationSpec`、`TOPWidthProfilesSpec` and emitted RTL for all four profiles | +| IFU fixed 64-bit output | IFU tests covering original 2/4/6/8-byte lengths and interface manifest showing 64-bit container | +| CTU template expansion | CTU UT for FENTRY/FEXIT/template blocks plus IFU→CTU→OOO IT | +| OOO D1-D3/S1 | decode、RENU、ROB/BROB、dispatch UT and `OOOIntegrationSpec` | +| P vs T/U rename separation | independent exhaustion、checkpoint、commit、recovery tests with unequal capacities | +| IEX requested topology | elaborated W4 manifest and simultaneous 2 ALU/1 BRU/2 AGU/2 STD tests | +| Separate system/multicycle and CMD queues | independent backpressure and completion tests | +| LSU 2 load/2 store | simultaneous-pipe UT、forward/replay/store visibility IT and manifest | +| Precise recovery | exact identity reuse、all-owner prepare/apply、trap/interrupt/debug tests | +| DTU scope | trace cannot block commit and DTU owns no ROB/recovery state | +| TOP routing only | structural connectivity test and source review gate | +| Production-owner reuse | checked owner manifest, active-emitter reachability, no duplicate state owner and no stateful adapter | +| Scalar linx-avs | natural finisher pass, nonzero box activation and bounded zero-mismatch report through emitted TOP | +| Dhrystone | natural finisher pass + 1000-commit zero-mismatch report | +| CoreMark | natural finisher pass + 1000-commit zero-mismatch report | +| Old chain removed | source/test/tool/doc grep gate and full closure suite | +| Repository clean | `git status --short` empty after reproducible generated intermediates are pruned | + +## 8. Commit and Integration Discipline + +每个 task 使用独立 Lore commit。提交正文至少记录实际影响本 task 的 +`Constraint:`、已经比较并拒绝的方案及原因 `Rejected:`、实际 +`Confidence:`、实际 `Scope-risk:`、后续修改必须保留的 owner/identity/ +handshake 约束 `Directive:`、本次真正运行的命令 `Tested:`，以及明确由 +后续 task 承接的门禁 `Not-tested:`。禁止照抄字段说明或填写虚构测试。 + +Task 10 冻结 production-owner manifest。Task 11、13、15、16、17、18 是 +subsystem cutover task：同层级 replacement evidence 通过后，必须在本 task +删除已被替代的旧入口，不得将删除统一推迟到 Task 20。Task 12 和 Task 14 +是 preparation task，只允许 behavior-preserving private refactor，不得改变 +active public interface 或增加第二个 owner。Task 20 只删除 residual orphan。 +最终合入 LinxCore 主分支后，更新 LinxISA superproject 的 `rtl/LinxCore` +gitlink，并在 superproject 侧完成独立提交和远端推送。 + +每个执行 loop 还必须： + +1. 追加 `docs/chisel/mainline-loop-ledger.md`，记录本轮使用的技能、实际工作流、验证证据、发现的缺口和下一轮边界； +2. 明确记录 `skill-evolve: update` 或 `skill-evolve: no-update` 及理由； +3. 完成一个符合 Lore protocol 的 commit； +4. 将当前分支 push 到 upstream；台账记录 branch、enclosing commit intent + 和 push target，loop handoff 在 commit 已存在后记录 exact SHA 与远端相等性。 + +## 9. Final Definition of Done + +只有同时满足以下条件，整个计划才完成： + +1. `TOP` 是唯一活动 Chisel core 顶层。 +2. `TOP` 只连接 IFU、CTU、OOO、IEX、LSU、DTU 和外部端口。 +3. 参数、接口和 box IO 位于规定目录，生成 manifest 与 elaborated Bundle 一致。 +4. W2/W4/W6/W8 全部通过 elaboration、接口和结构测试。 +5. W4 默认 profile 具有 2 ALU、1 BRU、2 AGU、2 STD、独立 system/multicycle 和 CMD IQ、2 load pipe、2 store pipe。 +6. OOO 是唯一 ROB、commit、精确 trap/interrupt 和全局 recovery plan owner。 +7. production mechanisms 直接位于 canonical box owner graph 中；不存在 + committed compatibility adapter、重复状态 owner 或仅为匹配目标文件名而 + 重写的平行机制。 +8. scalar linx-avs、Dhrystone、CoreMark 都从真实 ELF 取指开始自然结束， + 并通过限定提交对比。 +9. live source、tests、emitters、harnesses 和 current docs 中不存在旧顶层或 `Reduced*` 链。 +10. `docs/spec/` 只使用 Linx 术语与项目内条款，不保留外部来源文件名或 + 外部架构叙事。 +11. 完整 LinxCore closure suite 通过。 +12. LinxCore 工作树干净，提交遵循 Lore protocol；合入后 superproject gitlink 已更新。 diff --git a/docs/superpowers/plans/2026-08-03-simulator-heartbeat-parallel-build.md b/docs/superpowers/plans/2026-08-03-simulator-heartbeat-parallel-build.md new file mode 100644 index 00000000..ecd5db91 --- /dev/null +++ b/docs/superpowers/plans/2026-08-03-simulator-heartbeat-parallel-build.md @@ -0,0 +1,716 @@ +# Simulator Heartbeat and Parallel Build Implementation Plan + +> **For agentic workers:** REQUIRED SUB-SKILL: Use superpowers:subagent-driven-development (recommended) or superpowers:executing-plans to implement this plan task-by-task. Steps use checkbox (`- [ ]`) syntax for tracking. + +**Goal:** Make Chisel tests observable and bounded, run independent suites with memory-safe parallelism, and shrink directed-test elaboration by using legal test-only capacity profiles. + +**Architecture:** A Python process supervisor wraps the single SBT invocation and reports build liveness without confusing a CPU-active compile with deadlock. Pure Scala test helpers own simulated-cycle progress checks. Test-only parameter profiles preserve the selected W2/W4/W6/W8 lane topology while reducing capacity-derived structures; unchanged main profiles remain the only source of interface, generated-RTL, activation, and closure evidence. + +**Tech Stack:** Bash, Python 3 standard library and `unittest`, SBT 2, Scala 2.13, ScalaTest, Chisel 7.3, ChiselSim, Verilator. + +## Global Constraints + +- Keep main-source `ParamProfiles.W2`, `W4`, `W6`, and `W8` unchanged. +- Preserve fetch, CTU, decode, rename, D3, dispatch, issue, and retire widths at 2/4/6/8 in the corresponding simulation profile. +- Preserve W4 topology: 2 ALU, 1 BRU, 2 AGU, 2 STD, one system/multicycle queue, one CMD queue, 2 load pipes, and 2 store pipes. +- Preserve fixed PC, instruction, transaction, generation, full-LSID, memory-attempt, epoch, and recovery widths. +- Treat capacity-derived RID slot, BID, PC Buffer index, P/T/U tag, and MapQ index widths as local to the selected simulation profile; never use that profile as interface-width or full-identity-space evidence. +- Add no hardware watchdog, debug-only ready signal, TOP port, queue owner, recovery policy, compatibility path, or third-party dependency. +- Keep IEX as owner of memory transaction and initial load-attempt allocation; keep LSU as owner of replay, repick, and rebind. +- Do not start another Chisel, SBT, or Verilator process until the pre-existing W8 process has exited and its generated directory has been released for cleanup. +- Preserve the child command exit status. Supervisor-detected idle stall and wall-limit expiration use exit status 124. +- Use one SBT server per runner invocation. Default suite concurrency is 2. +- Heartbeat default is 30 seconds; idle-stall default is 600 seconds; wall limit is disabled by default; low-activity threshold is aggregate descendant CPU below 1 percent. + +--- + +## File Structure + +- `tools/chisel/chisel_test_supervisor.py`: process-group lifecycle, output/artifact/CPU sampling, heartbeat records, stall classification, signal forwarding, and final summary. +- `tools/chisel/run_chisel_tests.sh`: public runner CLI, environment validation, selector construction, and one supervised SBT command. +- `chisel/build.sbt`: environment-derived Test task concurrency limit. +- `tests/test_chisel_test_supervisor.py`: deterministic supervisor and CLI regression tests using synthetic child commands. +- `tests/test_chisel_test_runner.py`: fake-SBT runner contract tests; no Scala compilation. +- `chisel/src/test/scala/linxcore/params/SimulationParamProfiles.scala`: test-scope W2/W4/W6/W8 capacity profiles. +- `chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala`: profile legality, topology, fixed-width, and main-profile isolation tests. +- `chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala`: simulated-cycle progress accounting and diagnostic failure. +- `chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala`: pure Scala tests for progress reset and exact threshold failure. +- `chisel/src/test/scala/linxcore/ooo/OOOD3ContinuousPrefixSpec.scala`: use the W8 simulation profile while preserving the eight-lane three-three-two behavior. +- `docs/chisel/generated/simulation-artifact-baseline.json`: checked baseline and reduced-run metrics for the W8 case. +- `docs/chisel/integrated-development-flow.md`: runner options, profile evidence boundary, and measured artifact reduction. + +### Task 1: Add legal test-only capacity profiles + +**Files:** +- Create: `chisel/src/test/scala/linxcore/params/SimulationParamProfiles.scala` +- Create: `chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala` + +**Interfaces:** +- Consumes: `linxcore.params.ParamProfiles`, `CoreParams`, `OOOParams`, `IEXParams`, and `LSUParams`. +- Produces: `SimulationParamProfiles.W2`, `W4`, `W6`, `W8`, and `forWidth(width: Int): CoreParams` for behavior-only simulations. + +- [x] **Step 1: Write the profile invariants before the profile object exists** + +Create `SimulationParamProfilesSpec` with these assertions: + +```scala +package linxcore.params + +import org.scalatest.funsuite.AnyFunSuite + +class SimulationParamProfilesSpec extends AnyFunSuite { + private val widths = Seq(2, 4, 6, 8) + + test("simulation profiles preserve every principal width and fixed identity domain") { + widths.foreach { width => + val main = ParamProfiles.forWidth(width) + val sim = SimulationParamProfiles.forWidth(width) + ParamChecks.validate(sim) + assert(sim.widths == WidthParams.uniform(width)) + assert(sim.pcWidth == main.pcWidth) + assert(sim.instructionWidth == main.instructionWidth) + assert(sim.instructionIdWidth == main.instructionIdWidth) + assert(sim.transactionIdWidth == main.transactionIdWidth) + assert(sim.lsidWidth == main.lsidWidth) + assert(sim.memoryTransactionIdWidth == main.memoryTransactionIdWidth) + assert(sim.memoryTransactionGenerationWidth == main.memoryTransactionGenerationWidth) + assert(sim.memoryAttemptGenerationWidth == main.memoryAttemptGenerationWidth) + assert(sim.epochWidth == main.epochWidth) + assert(sim.ridGenerationWidth == main.ridGenerationWidth) + assert(sim.brobGenerationWidth == main.brobGenerationWidth) + } + } + + test("W4 simulation topology remains two one two two and two load two store") { + val p = SimulationParamProfiles.W4 + assert((p.iex.aluPipes, p.iex.bruPipes, p.iex.aguPipes, p.iex.stdPipes) == + (2, 1, 2, 2)) + assert(p.iex.systemMulticycleQueues == 1) + assert(p.iex.cmdIssueQueues == 1) + assert((p.lsu.loadPipes, p.lsu.storePipes) == (2, 2)) + assert((p.ooo.pcWritePorts, p.ooo.pcReadPorts) == (3, 6)) + } + + test("W8 directed profile uses the minimum retained capacities for the proof") { + val p = SimulationParamProfiles.W8 + assert(p.ifu.fetchBufferEntries == 8) + assert(p.ifu.predictionCheckpointEntries == 8) + assert(p.ctu.instructionBufferEntries == 8) + assert(p.ctu.maxTemplateUops == 2) + assert(p.ooo.robGroupsPerStid == 16) + assert(p.ooo.maxInstructionsPerRobGroup == 1) + assert(p.ooo.maxUopsPerInstruction == 12) + assert(p.ooo.robBankCount == 8) + assert(p.ooo.brobEntriesPerStid == 8) + assert(p.ooo.pcBufferEntries == 8) + assert(p.ooo.pcBankCount == 8) + assert(p.ooo.gprPhysRegs == 64) + assert(p.ooo.gprMapQDepthPerStid == 16) + assert(p.ooo.tPhysRegs == 16) + assert(p.ooo.uPhysRegs == 16) + assert(p.ooo.tuMapQDepthPerStid == 16) + assert(p.iex.scalarIssueEntries == 8) + assert((p.lsu.loadQueueEntries, p.lsu.storeQueueEntries) == (2, 2)) + assert(p.lsu.loadReturnQueueEntries == 2) + assert(p.lsu.storeCommitQueueEntries == 2) + assert(p.lsu.scbEntries == 4) + } + + test("simulation capacity changes never mutate main profiles") { + assert(ParamProfiles.W8.ooo.robGroupsPerStid == 64) + assert(ParamProfiles.W8.ooo.brobEntriesPerStid == 256) + assert(ParamProfiles.W8.ooo.gprMapQDepthPerStid == 256) + assert(ParamProfiles.W8.iex.scalarIssueEntries == 64) + assert(ParamProfiles.W8.lsu.loadQueueEntries == 16) + } +} +``` + +- [x] **Step 2: Run the test and verify the missing object is the first failure** + +Run after the pre-existing W8 process exits: + +```bash +bash tools/chisel/run_chisel_tests.sh --only SimulationParamProfilesSpec +``` + +Expected: compile failure naming `SimulationParamProfiles` as missing. + +- [x] **Step 3: Implement one width-derived test-scope profile constructor** + +Create `SimulationParamProfiles.scala` with a private constructor that starts from the unchanged main profile and copies only capacities: + +```scala +package linxcore.params + +object SimulationParamProfiles { + private def nextPowerOfTwo(value: Int): Int = + if (value <= 1) 1 + else 1 << (32 - Integer.numberOfLeadingZeros(value - 1)) + + private def bounded(width: Int): CoreParams = { + val main = ParamProfiles.forWidth(width) + val prefixCapacity = nextPowerOfTwo(width) + val robCapacity = nextPowerOfTwo(width + 1) + val pcBankCount = if (width <= 4) 4 else 8 + val issueCapacity = math.max(4, prefixCapacity) + val renameDestinationDemand = width * main.maxDestinationOperands + val renameQueueCapacity = nextPowerOfTwo(renameDestinationDemand) + val gprCapacity = nextPowerOfTwo( + main.ooo.stidCount * main.ooo.gprArchRegs + renameDestinationDemand) + main.copy( + ifu = main.ifu.copy( + fetchBufferEntries = prefixCapacity, + predictionCheckpointEntries = prefixCapacity), + ctu = main.ctu.copy( + instructionBufferEntries = prefixCapacity, + maxTemplateUops = 2), + ooo = main.ooo.copy( + robGroupsPerStid = robCapacity, + maxInstructionsPerRobGroup = 1, + maxUopsPerInstruction = 12, + robBankCount = prefixCapacity, + brobEntriesPerStid = math.max(2, prefixCapacity), + pcBufferEntries = pcBankCount, + pcBankCount = pcBankCount, + pcRecoveryScanGroupsPerCycle = math.min(4, prefixCapacity), + gprPhysRegs = gprCapacity, + gprMapQDepthPerStid = renameQueueCapacity, + tPhysRegs = renameQueueCapacity, + uPhysRegs = renameQueueCapacity, + tuMapQDepthPerStid = renameQueueCapacity), + iex = main.iex.copy(scalarIssueEntries = issueCapacity), + lsu = main.lsu.copy( + loadQueueEntries = 2, + storeQueueEntries = 2, + loadReturnQueueEntries = 2, + storeCommitQueueEntries = 2, + scbEntries = 4)) + } + + val W2: CoreParams = bounded(2) + val W4: CoreParams = bounded(4) + val W6: CoreParams = bounded(6) + val W8: CoreParams = bounded(8) + + def forWidth(width: Int): CoreParams = width match { + case 2 => W2 + case 4 => W4 + case 6 => W6 + case 8 => W8 + case _ => throw new IllegalArgumentException( + s"unsupported simulation width $width; supported widths are 2, 4, 6, and 8") + } +} +``` + +- [x] **Step 4: Run the focused profile test** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only SimulationParamProfilesSpec +``` + +Expected: all profile tests pass and `ParamChecks.validate` accepts W2/W4/W6/W8. + +- [x] **Step 5: Commit only the profile files** + +```bash +git commit --only -m "Add capacity-bounded Chisel simulation profiles" -- \ + chisel/src/test/scala/linxcore/params/SimulationParamProfiles.scala \ + chisel/src/test/scala/linxcore/params/SimulationParamProfilesSpec.scala +git push origin codex/chisel-gap-superpowers +``` + +### Task 2: Supervise one command with observable build liveness + +**Files:** +- Create: `tools/chisel/chisel_test_supervisor.py` +- Create: `tests/test_chisel_test_supervisor.py` + +**Interfaces:** +- Consumes: a child command, artifact root, optional log path, heartbeat/stall/wall seconds, low CPU threshold, and optional artifact budget. +- Produces: heartbeat lines prefixed `linx-chisel-heartbeat `, one final JSON summary prefixed `linx-chisel-summary `, the child exit status, or 124 for supervisor timeout. + +- [x] **Step 1: Write supervisor unit tests against stable Python interfaces** + +The test imports these names: + +```python +from tools.chisel.chisel_test_supervisor import ( + ArtifactSnapshot, + SupervisorConfig, + parse_non_negative_int, + parse_positive_int, + snapshot_artifacts, + supervise, +) +``` + +Cover these exact cases with temporary directories and `sys.executable -c ...` child commands: + +```python +class ChiselTestSupervisorTest(unittest.TestCase): + def test_positive_and_non_negative_values_reject_invalid_text(self): ... + def test_output_progress_prevents_idle_stall(self): ... + def test_artifact_progress_prevents_idle_stall(self): ... + def test_cpu_active_silent_child_is_not_called_stalled(self): ... + def test_silent_idle_child_exits_124_with_diagnostics(self): ... + def test_child_failure_status_is_preserved(self): ... + def test_artifact_budget_names_largest_file(self): ... + def test_interrupt_reaches_the_child_process_group(self): ... +``` + +Unit tests use 1-second public intervals and bounded children. The CPU-active child performs a Python integer loop; the idle child sleeps. Artifact progress appends one byte every 200 ms. The interrupt test starts a child that writes its received `SIGTERM` to a temporary file. + +- [x] **Step 2: Run the tests and verify the module is missing** + +Run: + +```bash +python3 -m unittest tests.test_chisel_test_supervisor -v +``` + +Expected: import failure for `tools.chisel.chisel_test_supervisor`. + +- [x] **Step 3: Implement the supervisor with standard-library-only types** + +Define these public records and functions: + +```python +@dataclasses.dataclass(frozen=True) +class ArtifactSnapshot: + bytes: int + latest_mtime_ns: int + file_count: int + largest: tuple[tuple[str, int], ...] + +@dataclasses.dataclass(frozen=True) +class SupervisorConfig: + heartbeat_seconds: int = 30 + stall_seconds: int = 600 + wall_seconds: int = 0 + low_cpu_percent: float = 1.0 + artifact_root: pathlib.Path | None = None + artifact_budget_bytes: int = 0 + log_path: pathlib.Path | None = None + selector: str = "all" + +def parse_positive_int(name: str, text: str) -> int: ... +def parse_non_negative_int(name: str, text: str) -> int: ... +def snapshot_artifacts(root: pathlib.Path | None) -> ArtifactSnapshot: ... +def supervise(config: SupervisorConfig, command: Sequence[str]) -> int: ... +def main(argv: Sequence[str] | None = None) -> int: ... +``` + +`supervise` must: + +1. start the child with `start_new_session=True`, merged stdout/stderr, and line-buffered binary forwarding; +2. continuously tee child output to the terminal and optional log; +3. sample descendant PID/PPID/CPU/RSS/command from `ps -axo pid=,ppid=,%cpu=,rss=,command=` and compute the descendant closure from the child PID; +4. classify `sbt`, `scala-compile`, `elaboration`, `firrtl`, `verilation`, `cxx-build`, `simulation`, or `result` from the most active descendant command and recent output; +5. update independent timestamps for output and artifact progress; +6. declare idle stall only when output and artifacts are unchanged for `stall_seconds` and aggregate descendant CPU is below `low_cpu_percent`; +7. emit heartbeat and final summary records with selector, phase, elapsed seconds, quiet seconds, artifact bytes, process count, aggregate CPU, RSS, peak RSS, and most-active command; +8. forward `SIGINT`/`SIGTERM` to the child process group, wait 5 seconds, then send `SIGKILL` only to surviving members; +9. fail an artifact budget after the child exits successfully, naming total bytes and the five largest files; +10. preserve every nonzero child status unchanged. + +- [x] **Step 4: Run supervisor tests and static syntax validation** + +Run: + +```bash +python3 -m py_compile tools/chisel/chisel_test_supervisor.py +python3 -m unittest tests.test_chisel_test_supervisor -v +``` + +Expected: both commands pass; the idle-stall test returns 124 and contains a final diagnostic summary. + +- [x] **Step 5: Commit and push the supervisor** + +```bash +git commit --only -m "Supervise Chisel tests with build heartbeats" -- \ + tools/chisel/chisel_test_supervisor.py \ + tests/test_chisel_test_supervisor.py +git push origin codex/chisel-gap-superpowers +``` + +### Task 3: Route the Chisel runner through one bounded SBT invocation + +**Files:** +- Modify: `tools/chisel/run_chisel_tests.sh` +- Modify: `chisel/build.sbt` +- Create: `tests/test_chisel_test_runner.py` + +**Interfaces:** +- Consumes: repeated `--only SUITE`, `--all`, `--heartbeat-seconds`, `--stall-seconds`, `--wall-seconds`, `--jobs`, `--artifact-budget-bytes`, and matching `LINX_CHISEL_*` environment values. +- Produces: one supervisor invocation, one SBT server command, and an SBT Test concurrency ceiling equal to `LINX_CHISEL_TEST_JOBS`. + +- [x] **Step 1: Write fake-SBT runner contract tests** + +Create a temporary executable named `sbt` at the front of `PATH`. It records arguments and `LINX_CHISEL_TEST_JOBS`, then exits with a requested status. Tests assert: + +```python +class ChiselTestRunnerTest(unittest.TestCase): + def test_repeated_only_selectors_form_one_test_only_command(self): ... + def test_all_and_only_are_mutually_exclusive(self): ... + def test_default_jobs_is_two(self): ... + def test_cli_jobs_overrides_environment(self): ... + def test_zero_stall_disables_idle_termination(self): ... + def test_invalid_numeric_options_fail_before_sbt(self): ... + def test_fake_sbt_failure_status_is_preserved(self): ... +``` + +For selectors `FooSpec` and `BarSpec`, the recorded final SBT command must be exactly: + +```text +testOnly *FooSpec* *BarSpec* +``` + +- [x] **Step 2: Run the tests and observe the first unsupported option** + +Run: + +```bash +python3 -m unittest tests.test_chisel_test_runner -v +``` + +Expected: failure because the runner currently accepts only one `--only` and has no supervisor options. + +- [x] **Step 3: Implement CLI validation and one supervised command** + +Update `run_chisel_tests.sh` to collect selectors in a Bash array and validate public integers before invoking Python. Defaults are: + +```bash +LINX_CHISEL_HEARTBEAT_SECONDS="${LINX_CHISEL_HEARTBEAT_SECONDS:-30}" +LINX_CHISEL_STALL_SECONDS="${LINX_CHISEL_STALL_SECONDS:-600}" +LINX_CHISEL_WALL_SECONDS="${LINX_CHISEL_WALL_SECONDS:-0}" +LINX_CHISEL_TEST_JOBS="${LINX_CHISEL_TEST_JOBS:-2}" +LINX_CHISEL_ARTIFACT_BUDGET_BYTES="${LINX_CHISEL_ARTIFACT_BUDGET_BYTES:-0}" +``` + +The script constructs an argument array, never an `eval` string, then executes: + +```bash +exec python3 "${ROOT_DIR}/tools/chisel/chisel_test_supervisor.py" \ + --selector "${selector_summary}" \ + --heartbeat-seconds "${LINX_CHISEL_HEARTBEAT_SECONDS}" \ + --stall-seconds "${LINX_CHISEL_STALL_SECONDS}" \ + --wall-seconds "${LINX_CHISEL_WALL_SECONDS}" \ + --artifact-root "${CHISEL_DIR}/build" \ + --artifact-budget-bytes "${LINX_CHISEL_ARTIFACT_BUDGET_BYTES}" \ + -- "${sbt_command[@]}" +``` + +- [x] **Step 4: Apply the SBT concurrency ceiling** + +In `chisel/build.sbt`, parse `LINX_CHISEL_TEST_JOBS` once, reject non-positive values with a clear message, retain `Test / parallelExecution := true`, and add: + +```scala +Global / concurrentRestrictions += Tags.limit(Tags.Test, chiselTestJobs) +``` + +The default is 2. This setting limits independent Test tasks within the one SBT server; it does not spawn another SBT client. + +- [x] **Step 5: Run runner tests and shell syntax validation** + +Run: + +```bash +bash -n tools/chisel/run_chisel_tests.sh +python3 -m unittest tests.test_chisel_test_runner -v +``` + +Expected: all fake-SBT cases pass without creating `chisel/build`. + +- [x] **Step 6: Compile the SBT configuration after the existing W8 run is cleaned** + +Run: + +```bash +LINX_CHISEL_TEST_JOBS=2 \ + bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec +``` + +Expected: the first heartbeat names the selected suite and job count; the test passes. + +- [x] **Step 7: Commit and push runner integration** + +```bash +git commit --only -m "Bound Chisel suite parallelism in one SBT server" -- \ + tools/chisel/run_chisel_tests.sh \ + chisel/build.sbt \ + tests/test_chisel_test_runner.py +git push origin codex/chisel-gap-superpowers +``` + +### Task 4: Detect architectural deadlock from simulated-cycle progress + +**Files:** +- Create: `chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala` +- Create: `chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala` + +**Interfaces:** +- Consumes: current simulated cycle, zero or more named progress observations, and a harness-specific diagnostic callback. +- Produces: `SimulationProgress.observe(cycle, events)` and `SimulationProgress.requireAlive(cycle)`; no hardware IO. + +- [x] **Step 1: Write pure Scala progress tests** + +Cover exact threshold behavior: + +```scala +package linxcore.testutil + +import org.scalatest.funsuite.AnyFunSuite + +class SimulationProgressSpec extends AnyFunSuite { + test("a typed progress event resets the idle-cycle window") { + val progress = new SimulationProgress(8, () => "rob=1,liq=0") + progress.observe(7, Seq(SimulationProgressEvent("dispatch", "rid=3"))) + progress.requireAlive(15) + } + + test("the first cycle beyond the limit reports the last identity and occupancy") { + val progress = new SimulationProgress(8, () => "rob=1,liq=1") + progress.observe(4, Seq(SimulationProgressEvent("memory-rebind", "attempt=2"))) + val error = intercept[IllegalStateException] { + progress.requireAlive(13) + } + assert(error.getMessage.contains("lastCycle=4")) + assert(error.getMessage.contains("memory-rebind")) + assert(error.getMessage.contains("attempt=2")) + assert(error.getMessage.contains("rob=1,liq=1")) + } + + test("empty observations do not create synthetic progress") { + val progress = new SimulationProgress(2, () => "iq=1") + progress.observe(0, Seq.empty) + assertThrows[IllegalStateException](progress.requireAlive(3)) + } +} +``` + +- [x] **Step 2: Run the test and verify the missing type failure** + +Run after the current build exits: + +```bash +bash tools/chisel/run_chisel_tests.sh --only SimulationProgressSpec +``` + +Expected: compile failure naming `SimulationProgress` and `SimulationProgressEvent`. + +- [x] **Step 3: Implement the cycle-domain helper** + +Use these signatures: + +```scala +final case class SimulationProgressEvent(kind: String, identity: String) + +final class SimulationProgress( + maxIdleCycles: Long, + diagnostics: () => String) { + require(maxIdleCycles > 0, "maxIdleCycles must be positive") + + def observe(cycle: Long, events: Iterable[SimulationProgressEvent]): Unit + def requireAlive(cycle: Long): Unit +} +``` + +`observe` records only non-empty events, rejects decreasing cycles, and retains the most recent event list. `requireAlive` fails when `cycle - lastProgressCycle > maxIdleCycles`, including current cycle, last cycle, event kinds and identities, and the callback text. The helper imports no Chisel hardware packages. + +- [x] **Step 4: Run the focused helper test** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only SimulationProgressSpec +``` + +Expected: all three tests pass. + +- [x] **Step 5: Commit and push the test helper** + +```bash +git commit --only -m "Detect simulation deadlock from typed progress" -- \ + chisel/src/test/scala/linxcore/testutil/SimulationProgress.scala \ + chisel/src/test/scala/linxcore/testutil/SimulationProgressSpec.scala +git push origin codex/chisel-gap-superpowers +``` + +### Task 5: Migrate the W8 continuous-prefix proof and measure artifact reduction + +**Files:** +- Modify: `chisel/src/test/scala/linxcore/ooo/OOOD3ContinuousPrefixSpec.scala` +- Create: `docs/chisel/generated/simulation-artifact-baseline.json` + +**Interfaces:** +- Consumes: `SimulationParamProfiles.W8`, the canonical D3 graph, three PC Buffer writes, six reads, and the existing eight-lane retained transaction. +- Produces: the unchanged three-three-two publication proof plus measured before/after artifact evidence. + +- [x] **Step 1: Preserve the pre-change result and clean only after exit** + +Wait for the already-running full-profile W8 process. Record exit status, elapsed time, peak RSS, total generated bytes, generated line count, and five largest files. After every descendant exits, remove only its ignored `chisel/build/chiselsim/OOOD3ContinuousPrefixSpec` directory and report that the generated directory is safe to clean. + +- [x] **Step 2: Change only the selected test profile** + +Replace: + +```scala +import linxcore.params.ParamProfiles +simulate(new OOOD3S1Graph(ParamProfiles.W8)) +``` + +with: + +```scala +import linxcore.params.SimulationParamProfiles +simulate(new OOOD3S1Graph(SimulationParamProfiles.W8)) +``` + +Do not change the eight-lane input, the 96-cycle bound, the expected tail transitions `Seq(3, 6, 8)`, or transaction/RID/LSID/PTag/PC Buffer continuity assertions. + +- [x] **Step 3: Run the bounded W8 case with a checked artifact budget** + +Run: + +```bash +LINX_CHISEL_ARTIFACT_BUDGET_BYTES=1073741824 \ + bash tools/chisel/run_chisel_tests.sh \ + --only OOOD3ContinuousPrefixSpec \ + --heartbeat-seconds 30 \ + --stall-seconds 600 \ + --jobs 1 +``` + +Expected: PASS, tail transitions `3,6,8`, total artifact bytes below 1 GiB, +and no idle-stall classification while Verilator is CPU-active. + +- [x] **Step 4: Write the machine-readable before/after report** + +Create a JSON object with schema +`linxcore.chisel.simulation_artifact_baseline.v1`, suite +`OOOD3ContinuousPrefixSpec`, and case +`W8 publishes one retained D3 transaction as three three two`. Both +`main_profile` and `simulation_profile` contain the captured non-empty Git SHA, +positive elapsed seconds, positive peak RSS bytes, positive generated bytes, +positive generated line count, and a non-empty `largest_files` array of +repository-relative path/byte pairs. Add: + +```json +"result_parity": { + "passed": true, + "tail_transitions": [3, 6, 8], + "published_lanes": 8 +} +``` + +Before commit, load the JSON with Python and assert both measurements are +positive, the reduced generated-byte count is below 1073741824, and every +result-parity field equals the values above. + +- [x] **Step 5: Re-run the full-profile non-simulation contract gates** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh --only CoreConfigurationSpec +bash tools/chisel/run_chisel_tests.sh --only TopInterfaceSpec +bash tools/chisel/run_chisel_tests.sh --only InterfaceManifestSpec +python3 tools/chisel/render_top_interface_manifest.py --check +``` + +Expected: W2/W4/W6/W8 main profiles and their interface widths remain unchanged. + +- [x] **Step 6: Leave the migrated test in the Task-13 atomic cutover commit** + +Because `OOOD3ContinuousPrefixSpec.scala` is part of the uncommitted Task-13 graph, do not create a separate commit for it. Stage it only with Task 13 after the private OOO/IEX graph, owner manifest, NDF, docs, deletion set, and all Task-13 replacement evidence are green. + +### Task 6: Document, validate, and close the infrastructure loop + +**Files:** +- Modify: `docs/chisel/integrated-development-flow.md` +- Modify: `docs/superpowers/specs/2026-08-03-simulator-heartbeat-parallel-build-design.md` +- Modify: this plan's checkboxes as each task completes. + +**Interfaces:** +- Consumes: supervisor CLI, SBT job limit, progress helper, profile contract, and measured W8 report. +- Produces: reproducible operator guidance and reviewable completion evidence. + +- [x] **Step 1: Document exact runner controls and evidence boundaries** + +Add one concise section that lists: + +```text +--heartbeat-seconds / LINX_CHISEL_HEARTBEAT_SECONDS (default 30) +--stall-seconds / LINX_CHISEL_STALL_SECONDS (default 600; 0 disables) +--wall-seconds / LINX_CHISEL_WALL_SECONDS (default 0; disabled) +--jobs / LINX_CHISEL_TEST_JOBS (default 2) +--artifact-budget-bytes / LINX_CHISEL_ARTIFACT_BUDGET_BYTES (default 0; disabled) +``` + +State that build stall requires simultaneous output, artifact, and low-CPU inactivity; architectural deadlock uses simulated cycles; simulation profiles cannot supply interface or full-capacity evidence. + +- [x] **Step 2: Run non-Chisel static and Python verification** + +Run: + +```bash +bash -n tools/chisel/run_chisel_tests.sh +python3 -m py_compile tools/chisel/chisel_test_supervisor.py +python3 -m unittest \ + tests.test_chisel_test_supervisor \ + tests.test_chisel_test_runner -v +git diff --check +``` + +Expected: all pass. + +- [x] **Step 3: Run the focused Scala verification in one bounded SBT invocation** + +Run: + +```bash +bash tools/chisel/run_chisel_tests.sh \ + --only SimulationParamProfilesSpec \ + --only SimulationProgressSpec \ + --only OOOD3ContinuousPrefixSpec \ + --jobs 2 +``` + +Expected: all selected suites pass, heartbeats remain visible, and no artifact budget is exceeded. + +- [x] **Step 4: Verify NDF, interface, and owner evidence remain valid** + +Run: + +```bash +python3 tools/spec/check_ndf_profile.py docs/spec +python3 tools/chisel/render_top_interface_manifest.py --check +python3 tools/chisel/check_production_owner_manifest.py +``` + +Expected: all pass; no simulator helper is listed as a hardware owner or public interface. + +- [x] **Step 5: Clean ignored generated artifacts after every process exits** + +Remove only ignored Chisel/SBT/Verilator output created by these tests. Preserve source, tests, checked manifests, the artifact baseline JSON, and all Task-13 edits. Verify no simulator descendant remains before cleanup. + +- [x] **Step 6: Commit and push the documentation closure** + +```bash +git commit --only -m "Document bounded Chisel simulation evidence" -- \ + docs/chisel/integrated-development-flow.md \ + docs/chisel/generated/simulation-artifact-baseline.json \ + docs/superpowers/specs/2026-08-03-simulator-heartbeat-parallel-build-design.md \ + docs/superpowers/plans/2026-08-03-simulator-heartbeat-parallel-build.md +git push origin codex/chisel-gap-superpowers +``` + +Expected: local `HEAD` equals `origin/codex/chisel-gap-superpowers`; unrelated Task-13 index and working-tree changes remain intact. + +## Execution Order + +Run Tasks 1-4 without starting Scala verification while the pre-existing W8 process is alive; Python-only tests may run concurrently with it. After that process exits, capture its baseline, clean its ignored directory, run the pending focused Scala tests, migrate the W8 profile, and complete Tasks 5-6. Because native subagent dispatch is disabled for this execution context, use the inline `superpowers:executing-plans` workflow and preserve the task-by-task verification gates above. diff --git a/docs/superpowers/plans/2026-08-05-linxcore-core-architecture-diagram.md b/docs/superpowers/plans/2026-08-05-linxcore-core-architecture-diagram.md new file mode 100644 index 00000000..5bb0e1a0 --- /dev/null +++ b/docs/superpowers/plans/2026-08-05-linxcore-core-architecture-diagram.md @@ -0,0 +1,187 @@ +# LinxCore Core Architecture Diagram Implementation Plan + +> **For agentic workers:** REQUIRED SUB-SKILL: Use superpowers:subagent-driven-development (recommended) or superpowers:executing-plans to implement this plan task-by-task. Steps use checkbox (`- [ ]`) syntax for tracking. + +**Goal:** Produce an editable, source-grounded LinxCore core architecture diagram and a PNG first-review preview. + +**Architecture:** Model the canonical/full pyCircuit `LinxCoreTop` as a grouped directed graph, lay it out with the Agents365 Graphviz generator, and add the reduced Chisel `TOP` as an explicitly non-canonical inset group. Structural validation runs before rendering; visual inspection is performed on a non-embedded PNG preview. + +**Tech Stack:** draw.io XML, Agents365 `drawio-skill` 2.1.0, Python 3, Graphviz 14.1.2, draw.io Desktop CLI. + +## Global Constraints + +- The canonical/full pyCircuit topology is the main view. +- The Chisel `TOP` inset must be labelled `Reduced typed composition lane (not the full core)`. +- Primary data and command flow is solid; recovery, replay, flush, and redirect flow is red and dashed. +- Bring-up or staged-integration ownership is visually distinguished from promoted ownership. +- Diagram labels remain in English to match source and architecture documentation. +- Preserve all pre-existing uncommitted work in the LinxCore checkout. + +--- + +### Task 1: Encode the source-grounded architecture graph + +**Files:** +- Create: `docs/architecture/diagrams/linxcore-core-architecture.graph.json` + +**Interfaces:** +- Consumes: `docs/architecture/linxcore_top_design.md`, `docs/architecture/overview.md`, `docs/architecture/module-catalog.md`, `src/top/top.py`, and `chisel/src/main/scala/linxcore/top/TOP.scala`. +- Produces: Agents365 autolayout JSON with `direction`, `nodes`, and `edges` fields. + +- [ ] **Step 1: Create the diagram directory and graph source** + +Use `apply_patch` to add one JSON object with `direction: "LR"`, grouped nodes for Frontend, Decode/OOO, Commit/Recovery, LSU/Memory, Block Fabric/Engines, Observability, and the Chisel inset. Include solid primary-flow edges and labels prefixed `RECOVERY:` for recovery/flush paths so they can be restyled after generation. + +- [ ] **Step 2: Validate the graph-source syntax** + +Run: + +```bash +python3 -m json.tool docs/architecture/diagrams/linxcore-core-architecture.graph.json >/dev/null +``` + +Expected: exit status 0 with no output. + +- [ ] **Step 3: Cross-check required ownership labels** + +Run: + +```bash +rg -n 'I-F0|B-F4|Instruction Buffer|D3 / Rename|ROB|BISQ|BCTRL|BROB|LIQ|STQ|MDB|SCB|VEC|CUBE|TMA|TAU|Reduced typed composition lane' docs/architecture/diagrams/linxcore-core-architecture.graph.json +``` + +Expected: every listed ownership label appears at least once. + +### Task 2: Generate and structurally validate the editable draw.io file + +**Files:** +- Create: `docs/architecture/diagrams/linxcore-core-architecture.drawio` +- Modify: `docs/architecture/diagrams/linxcore-core-architecture.drawio` only if recovery-edge styling or inset annotation requires a focused XML correction. + +**Interfaces:** +- Consumes: `linxcore-core-architecture.graph.json`. +- Produces: uncompressed native draw.io XML. + +- [ ] **Step 1: Generate the graph with Graphviz auto-layout** + +Run: + +```bash +python3 /Users/zhoubot/.codex/skills/drawio-skill/scripts/autolayout.py \ + docs/architecture/diagrams/linxcore-core-architecture.graph.json \ + --tune -o docs/architecture/diagrams/linxcore-core-architecture.drawio +``` + +Expected: stderr reports `wrote ...drawio` with non-zero node and edge counts. + +- [ ] **Step 2: Apply architecture-specific edge styling** + +Use `apply_patch` for a focused XML edit: edges whose generated labels begin with `RECOVERY:` receive `dashed=1;strokeColor=#b85450;` and the visible `RECOVERY:` prefix is removed. Do not alter node coordinates produced by Graphviz. + +- [ ] **Step 3: Run strict structural validation and readability scoring** + +Run: + +```bash +python3 /Users/zhoubot/.codex/skills/drawio-skill/scripts/validate.py \ + --strict --score docs/architecture/diagrams/linxcore-core-architecture.drawio +``` + +Expected: zero errors, zero warnings, exit status 0, and a numeric readability score. + +- [ ] **Step 4: Confirm XML ownership and edge endpoints** + +Run: + +```bash +rg -n 'Reduced typed composition lane|BCTRL|BROB|source=|target=' docs/architecture/diagrams/linxcore-core-architecture.drawio +``` + +Expected: the inset label, block-control nodes, and generated directed edges are present. + +### Task 3: Render and inspect the first-review preview + +**Files:** +- Create: `docs/architecture/diagrams/linxcore-core-architecture.png` + +**Interfaces:** +- Consumes: validated `linxcore-core-architecture.drawio`. +- Produces: width-capped, non-embedded PNG suitable for visual inspection. + +- [ ] **Step 1: Install draw.io Desktop only if the CLI is absent** + +Run: + +```bash +brew install --cask drawio +``` + +Expected: `/Applications/draw.io.app/Contents/MacOS/draw.io` exists and prints a version. Skip this step when `drawio --version` already succeeds. + +- [ ] **Step 2: Export the clean preview** + +Run with the resolved draw.io binary: + +```bash +drawio -x -f png --width 2000 -b 10 \ + -o docs/architecture/diagrams/linxcore-core-architecture.png \ + docs/architecture/diagrams/linxcore-core-architecture.drawio +``` + +Expected: a readable PNG no larger than 2000 pixels wide. Do not pass `-e` for this review preview. + +- [ ] **Step 3: Inspect the PNG with image vision** + +Open the PNG with the local image viewer and check: no overlapping sibling nodes, no clipped labels, no off-canvas content, all main ownership groups visible, recovery arrows visually distinct, and the Chisel inset clearly marked non-canonical. + +- [ ] **Step 4: Perform at most two focused correction rounds** + +For each observed defect, edit only the graph JSON or generated XML responsible for that defect, regenerate/re-export, and repeat structural plus visual inspection. Stop after two correction rounds and present the current preview. + +- [ ] **Step 5: Commit the graph source, draw.io file, and preview together** + +Run: + +```bash +git add docs/architecture/diagrams/linxcore-core-architecture.graph.json \ + docs/architecture/diagrams/linxcore-core-architecture.drawio \ + docs/architecture/diagrams/linxcore-core-architecture.png +git commit -m "docs: add LinxCore core architecture diagram" +``` + +Expected: one commit containing only the three diagram artifacts. + +### Task 4: Produce the editable embedded PNG after user approval + +**Files:** +- Create: `docs/architecture/diagrams/linxcore-core-architecture.drawio.png` + +**Interfaces:** +- Consumes: user-approved `.drawio` source. +- Produces: final PNG with embedded editable draw.io XML. + +- [ ] **Step 1: Export the approved embedded PNG** + +Run: + +```bash +drawio -x -f png -e -s 2 -b 10 \ + -o docs/architecture/diagrams/linxcore-core-architecture.drawio.png \ + docs/architecture/diagrams/linxcore-core-architecture.drawio +python3 /Users/zhoubot/.codex/skills/drawio-skill/scripts/repair_png.py \ + docs/architecture/diagrams/linxcore-core-architecture.drawio.png +``` + +Expected: repaired PNG ends with a valid IEND chunk and opens in draw.io with editable XML. + +- [ ] **Step 2: Commit the approved final export** + +Run: + +```bash +git add docs/architecture/diagrams/linxcore-core-architecture.drawio.png +git commit -m "docs: export editable LinxCore architecture preview" +``` + +Expected: one commit containing only the final embedded PNG. + diff --git a/docs/superpowers/specs/2026-07-31-scalar-load-structural-block-policy-design.md b/docs/superpowers/specs/2026-07-31-scalar-load-structural-block-policy-design.md new file mode 100644 index 00000000..d80f1671 --- /dev/null +++ b/docs/superpowers/specs/2026-07-31-scalar-load-structural-block-policy-design.md @@ -0,0 +1,108 @@ +# Scalar Load Structural-Block Policy Design + +## Purpose + +The installed OOO/IEX scalar-load path currently exports STQ forwarding +`hardBlock` as an external `Decoupled` response. If that response is accepted, +the canonical LIQ row remains `Repick` with `forwardPending = true`; no normal +E4 result can subsequently clear it. This design replaces that uncontrolled +production seam with one retained structural-block policy owner and an atomic +OOO-metadata/LIQ retry transaction. + +## Scope + +This packet owns only structural forwarding outcomes between the private STQ +forwarding fabric and the installed scalar LIQ. It does not add cross-line +load execution, invent a cache-miss classification, change STQ ordering, or +create a second load-lifecycle owner. + +## Classification + +The policy captures each accepted hard-block response in a compact resident +record containing the exact canonical load identity, exact current attempt, +return-pipe identity, optional exact wait-store identity, and reason bits. It +classifies the record in this priority order: + +1. Missing or ambiguous full LSID authority, malformed query identity, + cross-line store, cross-line load, or an `unknownOlder` response without an + exact wait-store key is `Unsupported`. +2. A stale STQ snapshot is `RetrySnapshot`, even when the response also reports + an unknown older store, because the captured store key may itself be stale. +3. An unknown older store with a complete exact key is `WaitStore`. + +`WaitStore` and `RetrySnapshot` increment the attempt generation by exactly +one while preserving the producer identity. `Unsupported` remains resident, +raises `protocolError`, and can be cleared only by hard flush or by an accepted +typed recovery that proves the owning load is killed. + +## Ownership and handshake + +`LoadStructuralBlockPolicy` is the sole consumer of the private forwarding +fabric's raw `hardBlock` output. It retains compact state under downstream +backpressure. The production external O3 boundary exposes diagnostics, not a +payload dequeue port. + +For retryable records, the policy supplies the internal candidate to the +existing `OooIexCanonicalLoadOwnership` rebind path. External rebind remains +supported but waits while an internal structural retry is resident. The +canonical owner must atomically accept all three effects: + +- cancel the old OOO terminal-metadata generation; +- bind the next generation; +- mutate the exact LIQ row from `Repick + forwardPending` to `Wait`. + +The LIQ structural-retry mutation validates the full load ID, current attempt, +next consecutive attempt, return pipe, lifecycle state, and wait-store key. +On acceptance it clears `forwardPending` and all partial forwarding-result +state. `WaitStore` installs the exact wait-store record; `RetrySnapshot` +installs no wait-store so the normal picker can retry with a fresh STQ +snapshot. No producer drops its resident record until this common handshake +fires. + +## Recovery + +Recovery prepare is side-effect free. A resident policy record permits prepare +only when both the OOO recovery plan and LSU projection identify the same +canonical LIQ row as killed. A surviving resident structural record blocks +prepare because a wait-store key captured before pruning cannot be assumed +valid after recovery. The record clears only on the common recovery fire. +Hard flush clears it unconditionally. + +The raw forwarding pipeline must still be empty before a recovery snapshot is +accepted; this prevents a response that has not yet reached policy ownership +from crossing the recovery boundary. + +## Diagnostics + +The production external interface reports: + +- structural block pending; +- structural block unsupported; +- structural disposition and reason bits; +- exact load ID and attempt for the resident record; +- aggregate protocol error. + +These signals are observation-only. They cannot consume or rewrite the owner. + +## Verification + +Unit tests must prove retained stability under backpressure, classification +priority, exact generation increment, fail-closed unsupported residency, hard +flush clearing, and recovery kill versus survivor behavior. LIQ tests must +prove the exact `Repick + forwardPending` mutation and reject stale identity, +wrong pipe, malformed wait-store, and concurrent mutation conflicts. +Integration tests must drive a real forwarding hard block through the installed +OOO/IEX path and observe one atomic metadata cancel/rebind plus LIQ retry state. +Generated RTL and structure gates must prove that the raw O3 `hardBlock` +dequeue port is absent and only one canonical load lifecycle owner remains. + +## Alternatives rejected + +- Treat every hard block as ordinary `Wait`: this masks missing ordering + authority and can create an unwakeable wait. +- Treat every hard block as a cache miss: structural STQ uncertainty is not a + cache hierarchy outcome. +- Raise a precise architectural trap now: no approved Linx fault cause or ROB + trap payload contract exists for these implementation failures. +- Add a second LIQ/metadata retry owner: it would violate the existing atomic + canonical ownership boundary. diff --git a/docs/superpowers/specs/2026-08-01-production-owner-atomic-cutover-design.md b/docs/superpowers/specs/2026-08-01-production-owner-atomic-cutover-design.md new file mode 100644 index 00000000..9822f12a --- /dev/null +++ b/docs/superpowers/specs/2026-08-01-production-owner-atomic-cutover-design.md @@ -0,0 +1,258 @@ +# LinxCore Production-Owner Atomic Cutover Design + +## 1. Objective + +Complete the canonical LinxCore Chisel graph by promoting the production-level +owners already present in the repository instead of building a parallel copy +of each subsystem. Keep one buildable implementation at every committed loop +boundary, converge each public interface once, and delete the displaced live +legacy entry points in the same subsystem cutover loop. + +Git history is the archive. The live source tree must not retain compatibility +owners, archive directories, duplicate emitters, or reduced implementations +after their production replacement has passed the same-level evidence gate. + +## 2. Decisions + +### 2.1 Preserve Tasks 1-9 + +Retain the contract spine, central parameters, typed TOP interfaces, CTU, IFU, +DEC, RENU, PRename, TURename, canonical ROB/BROB, CommitControl, and +RecoveryControl. Finish the current Task-9 correctness loop and push its +commits before starting the new cutover sequence. + +The production `OooO3RenameCoordinator` cannot become the new OOO box as a +whole because it owns another ROB/BROB/rename/recovery composition. Reuse its +proven private mechanisms only after assigning every state table to one +canonical owner. + +### 2.2 Promote production mechanisms in place + +Use the following repository mechanisms as the implementation starting point: + +- IFU: the existing `LinxCoreIfu` and I-SIDE/B-SIDE owners already composed + below the public `IFU` box; +- OOO dispatch: the existing reservation, hierarchical free-slot selection, + dispatch classification, fast-resolve, and store-commit mechanisms; +- IEX: the existing `OooIexIssue*`, operand-file, execution-pipeline, terminal, + and `ScalarGPRFile` mechanisms; +- LSU: the existing `ScalarLSU` internals, STQ/SCB/CommitQ, LIQ/ResolveQ/MDB, + miss/refill/load-return, and `ScalarL1D` mechanisms. + +Do not create a second stateful implementation merely to satisfy a target +class or filename. Public `OOO`, `IEX`, and `LSU` boxes are permanent typed +composition boundaries; they are not compatibility adapters. + +### 2.3 Use one atomic cutover per closed owner graph + +Normally one subsystem boundary is one cutover. When a typed identity is +allocated across two adjacent owners and neither side can become live without +the other's retained LIQ replay protocol, prepare both sides independently and cut +the closed adjacent graph in one loop. The OOO-IEX-LSU switch uses this joint +exception: Task 13 closes private canonical prerequisites, Task 14 prepares the +matching LSU replay owner, and Task 15 activates both public boxes together. + +A cutover loop must finish all of the following before its commit: + +1. freeze the producer/consumer payload and parameter mapping; +2. modify the selected production mechanisms to consume canonical types; +3. update every live producer, consumer, harness, emitter, test, and document; +4. connect the subsystem through the canonical public box; +5. delete the displaced legacy wrapper, reduced owner, and obsolete test path; +6. pass focused, adjacent, generated-RTL, and bounded architectural gates; +7. commit and push the green tree. + +A temporary adapter may exist only inside the uncommitted working tree during +the cutover. It must own no state and must be absent from the cutover commit. + +### 2.4 Separate preparation from interface cutover + +Large production modules may need several behavior-preserving preparation +loops. Preparation may split files, centralize parameters, add assertions, or +expand tests, but it must not create a second owner or change the public +subsystem interface. The subsequent cutover loop changes the public interface +and all call sites once. + +### 2.5 Delete legacy incrementally + +Deletion no longer waits for the final repository task. Once a subsystem has +equivalent unit, adjacent-integration, generated-RTL, and bounded workload +evidence through the canonical graph, delete the displaced live chain in that +same loop. The final cleanup task removes only residual orphans and proves the +absence of old active identifiers. + +### 2.6 Freeze Task-13 issue and resolve terminology + +OOO allocates the full program-order `LSID`, the load-only `LID`, the +store-only `SID`, and the `YOST`/`YOLD` older-memory boundaries. IEX allocates +one memory transaction for each retained memory uop, +shares it across one store's STA/STD children, and allocates the initial load +attempt when it retains `LoadIssueTxn`. LSU owns LIQ reissue, LIQ repick, and +every later attempt rebind. `LoadReissueTxn` is reserved for a load that still needs address +translation; `LoadRepickTxn` is reserved for a translated load returning to the +load-result path; `LoadCancelTxn` flows from LSU to IEX only to cancel +speculative dependents. OOO `RecoveryPlan`, not load cancel, terminates killed +IEX and LSU residency. + +IEX reports one `RobResolveTxn` for one ROB member. System/multicycle and CMD +retain separate resident queues. `RobNoflushReadyTxn` carries the exact NFRDY +proof that legality checks have completed without a local trap and every older +effect has drained. Commit control matches that proof to the exact per-STID +resident head before `RobNoflushTxn` authorizes one precise head-member side +effect. `SystemIssueTxn` carries system work, and `CmdIssueTxn` is the +independently backpressured TOP external CMD transaction. Task 13 removes the +displaced completion/request/adapter names in the same change that introduces +these interfaces; aliases do not survive the cutover. + +### 2.7 Freeze the private IEX cutover mapping + +`OooIexIssue` consumes `OOODispatchChannels` directly. The canonical dispatch +transaction carries program identity, renamed operands, execution class and +logical memory order; it never carries a physical IQ bank, entry, write port +or reservation lease. `OooIexIssue` chooses those private residency fields on +the accepting edge and remains their sole owner until an exact internal issue +release or recovery apply removes the row. There is no OOO-facing dispatch +release acknowledgement. + +The field mapping is fixed as follows: + +| Canonical field | Private retained field | Rule | +| --- | --- | --- | +| `DispatchTxn.transactionId` | IQ row transaction | copied exactly and stable for the row lifetime | +| `RenamedUop.decoded.instruction.parent.identity` | instruction key | copied exactly; never reconstructed from an IQ slot | +| `RenamedUop.decoded.rob` | resident ROB member | copied with every generation-qualified field | +| `RenamedUop.decoded.uopClass` | issue class and capability route | class selects the eligible private residency owner; the chosen bank and entry remain IEX-private | +| `RenamedUop.sources` | row source identity | P/T/U tag, sequence and generation are copied exactly; `ready` is the initial row scheduling state | +| `RenamedUop.destinations` | execution destination identity | current and previous mappings remain payload, not a second rename owner | +| `DispatchTxn.memoryOrder` | logical order sidecar | LSID/LID/SID and YOST/YOLD metadata are copied exactly; no memory transaction or attempt is synthesized here | +| `DispatchTxn.pcBufferIndexOffset` | IQ-row PC buffer index and PC offset | the OOO PC buffer prepares `pcBufferIndex`、`pcOffset` and `allocationEpoch` on the common D3 publication edge; IEX retains only those fields and reads the PC base from the owning OOO buffer in I1→I2 | + +One accepted `StoreDispatchTxn` reserves and installs both STA and STD rows or +neither. Both children retain the same ROB identity, transaction identity and +logical store-order range; only their execution class, selected private row +and requested AGU/STD pipe differ. Backpressure on either child keeps the +complete incoming store beat stable and causes no partial mutation. + +`OooIexOperandFiles` is the only global P/T/U data and readiness owner. An IQ +row may retain its own registered `ready` and speculative-ready bits for +scheduling, initialized from `RenamedSource.ready` and changed by exact +generation-qualified wakeup or load cancel. `OooIexIssue` must not retain a +global P/T/U scoreboard, consume a PTag recycle protocol, or infer late +readiness from tag index alone. + +`OooPcBuffer` remains the only PC-base residency owner. It participates in the +same D3 prepare/publication transaction as RENU, ROB, BROB, memory order and +dispatch, retires only on the common commit-control edge, and consumes the +canonical recovery prepare/apply/abort transaction directly. The OOO-IEX +boundary carries a typed `PcBufferIndexOffset` plus readyless read request and +response vectors; it never copies the complete PC into every IQ row and never +creates an IEX-side PC table. A required read that misses the exact +PC buffer index/allocation epoch binding repicks without executing. + +The same `PcBufferIndexOffset` is retained in `D3RenameLane` and `CommitEntry`; +`CommitEntry.robGroupLast` marks the final retiring member of one ROB group. +Those fields let the PC buffer validate its exact group lifetime on the common +commit edge without adding PC-buffer rows to the global recovery plan. + +`OooIexTerminalPublish` emits `RobResolveTxn` directly. Its transaction and ROB +identity come from the retained IQ row. Destination fields describe ordinal +zero only; a no-destination or trap resolve sets them to zero while every +legal P/T/U write and wakeup remains part of the same terminal rendezvous. +Any branch or trap `RecoveryEvent` is also accepted on that edge. A blocked RF +write, wakeup, trace, resolve, control update or required recovery event blocks +all terminal mutation and keeps every payload stable. + +Every private IEX recovery consumer retains the canonical `RecoveryPlan` +prepare request, reports that same request as prepared, and matches apply or +abort with `RecoveryPlanContract.sameTransactionIgnoringPhase`. Apply removes +only `RecoveryPlanContract.suffixMember` rows; abort preserves them and a peer +STID is never fenced or pruned by another STID's plan. + +The Task-13 Step-4 deletion set is the grouped `OooIexS1Transaction` ingress, +the dispatch-reservation release dependency, the global P/T/U readiness +shadow, the PTag recycle seam, `OooResidencyRecoveryPlan` projections on IEX +owners, and the displaced LIQ-allocation adapter name. No alias, wrapper or +committed compatibility conversion survives the loop. + +## 3. Canonical Owner Rules + +Maintain a checked owner manifest for architectural state, including ROB, +BROB, rename maps and freelists, IQ residency, physical register data and +readiness, STQ/SCB/LIQ/MDB/cache state, commit, and recovery arbitration. Every +state category has exactly one live owner reachable from the active emitter. + +An implementation is not promoted because its unit test passes or because its +name contains `canonical`. Promotion requires: + +- reachability from the canonical public box and active generated top; +- complete typed identity, backpressure, and recovery behavior; +- nonzero activation evidence at the relevant generated-RTL or workload gate; +- absence of a second live state owner for the same architectural state. + +Probe modules and reduced workload paths remain verification fixtures only +until their mechanism is reachable through the canonical graph. Delete a +fixture when it exists only to support a displaced implementation. + +## 4. Cutover Sequence + +1. Close Task 9 and freeze the owner/call-site manifest. +2. Cut OOO D3/S1 dispatch onto the canonical RENU/ROB/BROB owners. +3. Prepare the production IEX mechanisms without changing their live boundary. +4. Close canonical OOO-IEX prerequisites: D1 memory controls, the unique OOO + memory-order/recovery owner, private IEX canonical ingress/terminal and the + approved IEX-LSU issue/reissue/repick lifecycle; keep public `IEX` absent. +5. Prepare the production LSU internals, implement the matching typed load + lifecycle and resolve the two-load-pipe contract without a public cutover. +6. Atomically activate the canonical OOO-IEX-LSU graph, then delete the reduced + issue/execute/completion chain, old `ScalarLSU` boundary and displaced LSU + entry points in the same loop. +7. Integrate DTU, distributed recovery, trap, interrupt, and commit observation. +8. Promote one active `TOP` emitter and natural ELF harness; delete old tops. +9. Run natural scalar linx-avs, Dhrystone, CoreMark, bounded commit comparison, + and recovery stress. +10. Remove residual orphan sources, docs, tools, and generated intermediates; + run full closure and update the superproject gitlink. + +## 5. Evidence Ladder + +Run evidence in increasing cost order: + +1. owner unit and contract tests; +2. upstream/downstream adjacent integration; +3. W2/W4/W6/W8 elaboration and interface-manifest parity; +4. generated-RTL lint and subsystem activation probes; +5. bounded scalar linx-avs and QEMU commit comparison; +6. natural Dhrystone/CoreMark and 1000-commit comparison; +7. multi-seed recovery/long-latency stress and the full closure suite. + +Do not repeatedly run the full benchmark suite during local RED/GREEN fixes. +Run the complete promotion ladder at the subsystem cutover commit and final +closure. + +## 6. Loop and Git Discipline + +Each loop records its owner decision, interface mapping, files deleted, +verification evidence, generated-artifact cleanup, and remaining boundary. +Every green loop ends with one Lore commit and an immediate push. A loop may +not begin while earlier local commits remain unpushed unless the remote is +unavailable and the ledger records the exact blocker. + +Generated Verilog trees, `obj_dir`, wave files, and compiler intermediates are +reproducible and must be pruned. Preserve only manifests, reports, bounded +trace excerpts, and evidence explicitly cited by current documentation. + +## 7. Success Criteria + +The migration succeeds when: + +- one active `TOP` reaches exactly one IFU, CTU, OOO, IEX, LSU, and DTU box; +- production mechanisms are reused behind canonical typed interfaces without + duplicate state owners or committed compatibility adapters; +- W2/W4/W6/W8 elaborate and W4 exposes the required physical topology; +- scalar linx-avs, natural Dhrystone, and natural CoreMark pass through the + same emitted TOP and frozen ELF identities; +- bounded architectural comparison reports zero mismatches; +- live source, tests, emitters, harnesses, and current docs contain no + displaced top or `Reduced*` chain; +- the LinxCore branch is pushed, clean, fully verified, and pinned by the + LinxISA superproject. diff --git a/docs/superpowers/specs/2026-08-03-simulator-heartbeat-parallel-build-design.md b/docs/superpowers/specs/2026-08-03-simulator-heartbeat-parallel-build-design.md new file mode 100644 index 00000000..8bf9e925 --- /dev/null +++ b/docs/superpowers/specs/2026-08-03-simulator-heartbeat-parallel-build-design.md @@ -0,0 +1,282 @@ +# LinxCore Simulator Heartbeat and Parallel Build Design + +## 1. Objective + +Make Chisel verification observable, bounded, and faster without weakening the +microarchitecture being proved. The test runner reports continuous build +progress, simulation harnesses detect architectural deadlock from explicit +progress events, and behavior tests use smaller legal capacities while keeping +the full W2/W4/W6/W8 lane widths and physical execution topology. + +This work changes verification infrastructure only. It adds no hardware state, +TOP port, queue owner, recovery policy, or compatibility path. + +## 2. Baseline and Root Cause + +`tools/chisel/run_chisel_tests.sh` currently invokes one foreground SBT command. +It emits no status between SBT log records and cannot distinguish elaboration, +FIRRTL lowering, Verilation, C++ compilation, or simulation. + +The Task-13 W8 continuous D3 lane test exposed the cost of using full-capacity +parameters for a narrow behavior proof: + +- generated SystemVerilog: 11,365,751 lines; +- generated `PRename.sv`: 8,183,231 lines and about 781 MiB; +- total generated simulator input: about 1 GiB; +- Verilator resident footprint: about 11.9 GiB, with a 22.6 GiB peak; +- active phase after several hours: `V3Split::splitReorderAll` at approximately + one fully occupied CPU core. + +The invocation already contains `-j 0`. Verilator therefore uses all available +parallelism for Verilation and C++ build phases that support it. More shell +parallelism cannot accelerate a single oversized sequential pass. The primary +repair is to reduce irrelevant capacities for behavior simulation, then use +bounded suite-level concurrency so independent models build in parallel +without exhausting memory. + +## 3. Selected Design + +### 3.1 Separate build liveness from architectural progress + +The runner owns process supervision. The simulation test or natural workload +harness owns architectural progress detection. Neither layer infers the other. + +The runner classifies the active phase from its descendant process tree: + +1. SBT startup and Scala compilation; +2. Chisel elaboration; +3. FIRRTL lowering; +4. Verilation; +5. C++ compilation and link; +6. simulator execution; +7. result collection. + +Every heartbeat reports: + +- suite and test selector; +- phase and total elapsed time; +- time since the last output byte; +- time since the last generated-file size or modification change; +- descendant CPU usage, resident memory, and active process count; +- generated artifact bytes; +- the most active descendant command. + +The default heartbeat interval is 30 seconds. `LINX_CHISEL_HEARTBEAT_SECONDS` +and a matching command-line option may override it with a positive integer. + +### 3.2 Build stall policy + +A silent build is not a stalled build when its process tree is consuming CPU or +its generated files are changing. The runner declares a build stall only when +all of the following remain true for the configured stall window: + +- no new output bytes; +- no generated-file size or modification progress; +- aggregate descendant CPU remains below the low-activity threshold; +- the supervised command is still alive. + +The default stall window is 600 seconds. A stall exits with status 124 after +printing the latest heartbeat, process tree, artifact summary, and log tail. +`LINX_CHISEL_STALL_SECONDS=0` disables automatic build-stall termination but +does not disable heartbeats. An optional wall-time limit remains separate and +is disabled by default because a high-CPU Verilation pass is not deadlock. + +The runner forwards `INT` and `TERM` to the complete process group, waits for a +bounded graceful exit, and then reports every process that survived. It never +deletes build artifacts while a descendant remains alive. + +### 3.3 Simulation deadlock policy + +Architectural deadlock is measured in simulated cycles, not wall-clock time or +log silence. A shared test helper tracks the last cycle with one or more typed +progress events: + +- accepted input or dispatch lane; +- architectural commit; +- execution completion or ROB resolve; +- memory request, response, replay, repick, or store visibility transition; +- recovery prepare, prepared, apply, or abort handshake; +- trap, interrupt, or command transaction; +- natural workload termination. + +Each long-running simulation declares the progress events relevant to that +harness and a maximum number of cycles without them. When the limit expires, +the helper fails with the cycle, last progress event, retained identities, +queue or stage occupancy exposed by the harness, and the most recent commit or +memory transaction. Short directed tests may retain their existing bounded +loops; they do not acquire an unrelated global timeout. + +The checker is test-only code. Hardware must not gain a watchdog register, +debug-only ready signal, or progress port to satisfy the test infrastructure. +DTU remains the debug and trace unit; commit and recovery ownership remain in +OOO and TOP distribution remains policy-free. + +### 3.4 Bounded parallelism + +One runner invocation uses one SBT server and may accept multiple suite +selectors. SBT schedules independent suites concurrently. The runner and SBT +share one `LINX_CHISEL_TEST_JOBS` limit so the number of concurrent simulator +builds is explicit and reproducible. + +The default is one simulator suite. The user may raise it explicitly after +considering available memory. The runner records the selected job count in +every heartbeat and final summary. It does not launch independent SBT clients +against the same workspace. + +Within one Verilator model, Verilation and C++ build parallelism remain +enabled. The implementation uses separate build and Verilation job settings +when supported, compilation-speed optimization for behavior tests, output +splitting, and cache-compatible generated outputs. Parallel C++ compilation +does not substitute for lowering the RTL size. + +### 3.5 Simulation parameter profiles + +Behavior simulation uses test-only `SimulationParamProfiles` under +`chisel/src/test/scala/linxcore/params`. Main-source `ParamProfiles.W2`, `W4`, +`W6`, and `W8` remain unchanged and remain mandatory for elaboration, interface +manifest, generated RTL, lint, activation, natural workload, and final closure +evidence. + +Simulation profiles preserve the lane topology and every explicitly configured +fixed-width transaction domain: + +- fetch, CTU, decode, rename, D3, dispatch, issue, and retire widths; +- two ALU, one BRU, two AGU, two STD, one system/multicycle queue, and one CMD + queue; +- two load pipes and two store pipes; +- three PC Buffer write ports and six read ports; +- source and destination counts; +- PC, instruction, PE, instruction, transaction, generation, full LSID, + memory-attempt, epoch, and recovery widths that are independent of a local + storage capacity. + +The current RTL derives RID slot, BID, PC Buffer index, P/T/U tag and MapQ +index widths from their corresponding capacities. Those local widths therefore +narrow in a capacity-reduced simulation profile. Such a profile proves +behavior and identity continuity within that legal configuration; it cannot +prove full-profile interface widths or full identity-space wrap. Interface +manifests, identity-width conformance, generated RTL, activation and closure +always use the unchanged main profiles. A future physical-capacity/identity- +capacity split must be implemented as an architectural parameter change, not +hidden inside this test-only profile. + +They reduce only capacities that are irrelevant to a directed behavior proof. +Each width uses its own next-power-of-two prefix and rename-demand capacity; +W2 and W4 are not padded to W8 storage geometry. The scalar IQ retains a +four-entry minimum so its two banks each have at least two addressable rows; +this avoids a zero-bit reservation slot while remaining far below the main +64-entry capacity. +The W8 continuous D3 lane test uses this initial profile: + +| Capacity | Main profile | Simulation profile | Preserved behavior | +| --- | ---: | ---: | --- | +| ROB groups per STID | 64 | 16 | one complete W8 D3 lane set and its nonwrapped tail | +| instructions per ROB group | 4 | 1 | eight independent RID groups | +| maximum recipe uops | 32 | 12 | current ordinary-group/CTU recipe invariant | +| ROB banks | 8 | 8 | eight-lane allocation geometry | +| BROB entries per STID | 256 | 8 | one W8 branch-order window | +| PC Buffer entries | 64 | 8 | eight bases and 3W/6R behavior | +| PC Buffer banks | 8 for W8 | 8 | W8 retire and PC bank geometry | +| integer physical registers | 128 | 64 | 24 committed mappings plus 16 W8 destinations | +| integer MapQ entries per STID | 256 | 16 | one maximum rename destination set | +| T physical registers | 32 | 16 | one maximum rename destination set | +| U physical registers | 32 | 16 | one maximum rename destination set | +| T/U MapQ entries per STID | 32 | 16 | one maximum rename destination set | +| scalar Issue Queue entries | 64 | 8 | one complete W8 admission prefix | +| IFU and CTU retained entries | 32 | at least the selected width | one full transfer | +| maximum CTU template uops | 32 | 2 | scalar/store-split directed behavior | +| load/store queues | 16/16 | 2/2 | two load and two store pipes | +| load-return/store-commit queues | 16/16 | 2/2 | one event per physical pipe | +| SCB entries | 16 | 4 | one two-pipe split-store batch | + +No test may use the simulation profile to claim full-capacity wrap, occupancy, +fairness, recovery-depth, or stress behavior. Those tests select the smallest +capacity that still covers the claimed boundary, or use the unchanged main +profile. The test name and evidence record state which profile was used. + +### 3.6 Generated artifact accounting + +The runner reports generated bytes and the largest generated files at exit. +Representative behavior suites have a checked artifact-size budget so a +capacity or elaboration regression cannot silently recreate a gigabyte-scale +model. Exceeding the budget is a test-infrastructure failure with an actionable +message naming the suite, profile, total bytes, largest file, and configured +budget. + +Full TOP and closure builds use separately declared budgets. A behavior-test +budget must never be reused to reject a required full-configuration build. + +## 4. Interfaces and Files + +The implementation plan will cover these surfaces: + +- modify `tools/chisel/run_chisel_tests.sh` for the public command-line + contract and one-SBT invocation; +- add one process-supervision helper under `tools/chisel` with unit tests that + use synthetic commands rather than Chisel builds; +- add SBT job-limit configuration derived from `LINX_CHISEL_TEST_JOBS`; +- add test-only `SimulationParamProfiles` and parameter-invariant tests; +- migrate `OOOD3ContinuousPrefixSpec` to the W8 simulation profile; +- add a shared simulation progress checker and focused unit tests; +- integrate progress events into long-running graph and natural workload + harnesses as those harnesses become active in Tasks 13 and 18-19; +- document runner options and artifact budgets in the Chisel development flow. + +The process supervisor and progress checker own no hardware protocol and are +not architectural state owners or compatibility adapters. + +## 5. Error Handling + +Every failure answers what stopped, why it stopped, and how to reproduce it: + +- invalid heartbeat, stall, job, or budget values fail before SBT starts; +- build stall prints low-activity evidence and exits 124; +- wall-time expiration states that it is a wall limit, not a deadlock claim; +- architectural deadlock prints cycle-based progress evidence and fails the + exact simulation test; +- artifact-budget failure identifies the profile and largest generated file; +- child process failure preserves its exit status and log tail; +- interruption terminates the process group before cleanup is permitted. + +## 6. Verification + +Implementation follows test-first order: + +1. supervisor unit tests with silent-active, silent-idle, output-progress, + artifact-progress, child-failure, and signal-forwarding commands; +2. runner argument and environment validation tests; +3. progress-checker unit tests for forward progress, exact threshold failure, + and diagnostic payload; +4. `SimulationParamProfiles` tests proving W2/W4/W6/W8 widths, W4 topology, + fixed transaction widths, PC Buffer 3W/6R, minimum legal capacities, and + explicit rejection of simulation profiles as interface-manifest evidence; +5. the W8 D3 lane test proving the same three-three-two accepted sequence with + bounded artifact size; +6. focused Task-13 tests, interface manifest, W2/W4/W6/W8 full-profile + elaboration, generated RTL, and Verilator lint; +7. natural workload progress and deadlock tests when the active TOP harness is + introduced. + +The before/after report records wall time, peak resident memory, generated +bytes, generated line count, and result parity for the W8 case. + +## 7. Success Criteria + +The design is complete when: + +- a silent active build emits periodic heartbeats and is never classified as + deadlocked; +- a silent idle build fails after the configured stall window with complete + diagnostics; +- a simulation with no declared architectural progress fails at its cycle + threshold; +- independent suites build concurrently within the configured memory-safe job + limit; +- the W8 D3 behavior test preserves eight lanes, 3W PC Buffer acceptance, the + three-three-two sequence, and complete identity continuity; +- W8 behavior-test generated bytes and peak memory fall substantially from the + recorded baseline; +- unchanged main W2/W4/W6/W8 profiles still pass elaboration, lint, activation, + and closure gates; +- no hardware owner, interface, or architectural behavior changes solely for + verification infrastructure. diff --git a/docs/superpowers/specs/2026-08-05-linxcore-core-architecture-diagram-design.md b/docs/superpowers/specs/2026-08-05-linxcore-core-architecture-diagram-design.md new file mode 100644 index 00000000..45362d32 --- /dev/null +++ b/docs/superpowers/specs/2026-08-05-linxcore-core-architecture-diagram-design.md @@ -0,0 +1,59 @@ +# LinxCore Core Architecture Diagram Design + +## Goal + +Create one editable draw.io architecture diagram that explains the current +LinxCore core without presenting a reduced bring-up shell as the complete +implementation. + +## Considered approaches + +1. Draw only the canonical pyCircuit `LinxCoreTop`. This is architecturally + accurate but hides the active Chisel replacement lane. +2. Draw only the Chisel `TOP`. This is compact and matches current Scala + composition, but it would incorrectly imply that the reduced typed shell is + the complete core. +3. Draw the canonical pyCircuit core as the main view and add a small Chisel + `TOP` inset. This preserves the full contract while showing the active + replacement boundary. This is the selected approach. + +## Main view + +Use a left-to-right data-flow layout with six visually distinct regions: + +- Frontend: I-SIDE `I-F0..I-F4`, Instruction Buffer, D1, plus the decoupled + B-SIDE `B-F0..B-F4` predictor path. +- Decode and OOO: D2, D3/Rename, S1, S2/S3-IQ, P0/P1, I1/I2, and IEX. +- Commit and recovery: ROB, R0..R4, commit, PC buffer, RENU, and flush/restart. +- LSU and memory: LIQ, LHQ, MDB, STQ, L1D, SCB/store drain, and external + instruction/data memory. +- Block fabric and engines: BISQ, BRENU, BCTRL, BROB, VEC, CUBE, TMA, TAU, + and TMU. +- Observability: commit, block, and pipeview probes plus trace/debug output. + +Solid arrows show primary data or command movement. Red dashed arrows show +flush, recovery, replay, or redirect control. Grey dashed outlines identify +current bring-up or staged-integration behavior rather than a fully promoted +owner. + +## Chisel inset + +Add a compact inset labelled `Reduced typed composition lane (not the full +core)` with the current public chain `IFU -> CTU -> OOO -> IEX -> LSU`, DTU +observability, external instruction/data memory, and OOO recovery feedback to +IFU/CTU/LSU. + +## Outputs + +- `docs/architecture/diagrams/linxcore-core-architecture.drawio` +- `docs/architecture/diagrams/linxcore-core-architecture.png` for review +- After approval, `linxcore-core-architecture.drawio.png` with embedded XML + +## Validation + +- Run the bundled `validate.py --strict --score` structural checks. +- Export a clean PNG without embedded XML for visual inspection. +- Check for clipped labels, overlaps, off-canvas nodes, missing connections, + edge-through-node collisions, and ambiguous ownership. +- Keep all labels in English to match canonical source and architecture docs. + diff --git a/src/common/opcode_catalog.yaml b/src/common/opcode_catalog.yaml index d4779b36..8e57f51b 100644 --- a/src/common/opcode_catalog.yaml +++ b/src/common/opcode_catalog.yaml @@ -862,12 +862,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -930,12 +930,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -998,12 +998,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1066,12 +1066,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1134,12 +1134,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1202,12 +1202,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1270,12 +1270,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1338,12 +1338,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1406,12 +1406,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1474,12 +1474,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1542,12 +1542,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1610,12 +1610,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1678,12 +1678,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1746,12 +1746,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1814,12 +1814,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1882,12 +1882,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -1950,12 +1950,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2020,12 +2020,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2090,12 +2090,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2160,12 +2160,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2228,12 +2228,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2296,12 +2296,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2364,12 +2364,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -2500,12 +2500,12 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": false, "may_trap_late": false, "may_redirect": false, - "nonspeculative": false, + "nonspeculative": true, "dispatch_class": "CMD", "dispatch_writes": 1, "dispatch_demand": { @@ -3180,7 +3180,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -3384,7 +3384,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4064,7 +4064,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4132,7 +4132,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4200,7 +4200,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4268,7 +4268,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4336,7 +4336,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4404,7 +4404,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4472,7 +4472,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4744,7 +4744,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4812,7 +4812,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4880,7 +4880,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -4948,7 +4948,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5016,7 +5016,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5084,7 +5084,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5152,7 +5152,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5220,7 +5220,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5288,7 +5288,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5356,7 +5356,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5424,7 +5424,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5492,7 +5492,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5560,7 +5560,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5628,7 +5628,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5696,7 +5696,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5764,7 +5764,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5832,7 +5832,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5900,7 +5900,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -5968,7 +5968,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -6036,7 +6036,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -7056,7 +7056,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -7124,7 +7124,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -7668,7 +7668,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -7736,7 +7736,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -7804,7 +7804,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -8121,8 +8121,8 @@ "pattern": "..........011010", "mask": "0x3f", "match": "0x1a", - "major_cat": "COMPRESSED", - "minor_cat": "compressed", + "major_cat": "LOAD", + "minor_cat": "compressed_load", "rd_kind": "NONE", "rs1_kind": "REG", "rs2_kind": "NONE", @@ -8134,7 +8134,7 @@ "op_id": 570, "ooo": { "disposition": "DISPATCH", - "recipe_kind": "SINGLE", + "recipe_kind": "SCALAR_LOAD", "uop_count_min": 1, "uop_count_max": 1, "complex_break": false, @@ -8144,18 +8144,18 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "IEX", + "side_effect_owner": "LSU", "requires_target_validation": false, - "may_trap": false, - "may_trap_late": false, + "may_trap": true, + "may_trap_late": true, "may_redirect": false, "nonspeculative": false, - "dispatch_class": "ALU", + "dispatch_class": "AGU", "dispatch_writes": 1, "dispatch_demand": { - "ALU": 1, + "ALU": 0, "BRU": 0, - "AGU": 0, + "AGU": 1, "STD": 0, "FSU": 0, "SYS": 0, @@ -8163,21 +8163,21 @@ "BOUNDARY": 0 }, "dispatch_capabilities": { - "ALU": "SIMPLE_ALU", + "ALU": "NONE", "BRU": "NONE", - "AGU": "NONE", + "AGU": "LOAD_ADDRESS", "STD": "NONE", "FSU": "NONE", "SYS": "NONE", "CMD": "NONE", "BOUNDARY": "NONE" }, - "memory_request_count": 0, + "memory_request_count": 1, "p_source_count": 1, "p_destination_count": 0, - "t_allocation_count": 0, + "t_allocation_count": 1, "u_allocation_count": 0, - "reason": "generated dispatch recipe", + "reason": "compact scalar load allocates the next T destination", "pc_read_parent": "NONE", "pc_read_class": "NONE" } @@ -8189,8 +8189,8 @@ "pattern": "..........001010", "mask": "0x3f", "match": "0xa", - "major_cat": "COMPRESSED", - "minor_cat": "compressed", + "major_cat": "LOAD", + "minor_cat": "compressed_load", "rd_kind": "NONE", "rs1_kind": "REG", "rs2_kind": "NONE", @@ -8202,7 +8202,7 @@ "op_id": 571, "ooo": { "disposition": "DISPATCH", - "recipe_kind": "SINGLE", + "recipe_kind": "SCALAR_LOAD", "uop_count_min": 1, "uop_count_max": 1, "complex_break": false, @@ -8212,18 +8212,18 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "IEX", + "side_effect_owner": "LSU", "requires_target_validation": false, - "may_trap": false, - "may_trap_late": false, + "may_trap": true, + "may_trap_late": true, "may_redirect": false, "nonspeculative": false, - "dispatch_class": "ALU", + "dispatch_class": "AGU", "dispatch_writes": 1, "dispatch_demand": { - "ALU": 1, + "ALU": 0, "BRU": 0, - "AGU": 0, + "AGU": 1, "STD": 0, "FSU": 0, "SYS": 0, @@ -8231,21 +8231,21 @@ "BOUNDARY": 0 }, "dispatch_capabilities": { - "ALU": "SIMPLE_ALU", + "ALU": "NONE", "BRU": "NONE", - "AGU": "NONE", + "AGU": "LOAD_ADDRESS", "STD": "NONE", "FSU": "NONE", "SYS": "NONE", "CMD": "NONE", "BOUNDARY": "NONE" }, - "memory_request_count": 0, + "memory_request_count": 1, "p_source_count": 1, "p_destination_count": 0, - "t_allocation_count": 0, + "t_allocation_count": 1, "u_allocation_count": 0, - "reason": "generated dispatch recipe", + "reason": "compact scalar load allocates the next T destination", "pc_read_parent": "NONE", "pc_read_class": "NONE" } @@ -8461,8 +8461,8 @@ "pattern": "..........111010", "mask": "0x3f", "match": "0x3a", - "major_cat": "COMPRESSED", - "minor_cat": "compressed", + "major_cat": "STORE", + "minor_cat": "compressed_store", "rd_kind": "NONE", "rs1_kind": "REG", "rs2_kind": "NONE", @@ -8474,50 +8474,50 @@ "op_id": 575, "ooo": { "disposition": "DISPATCH", - "recipe_kind": "SINGLE", - "uop_count_min": 1, - "uop_count_max": 1, + "recipe_kind": "SCALAR_STORE", + "uop_count_min": 2, + "uop_count_max": 2, "complex_break": false, - "late_split_kind": "NONE", + "late_split_kind": "STORE_ADDRESS_DATA", "fusion_head_class": "NONE", "fusion_tail_class": "NONE", "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "IEX", + "side_effect_owner": "LSU", "requires_target_validation": false, - "may_trap": false, - "may_trap_late": false, + "may_trap": true, + "may_trap_late": true, "may_redirect": false, "nonspeculative": false, - "dispatch_class": "ALU", - "dispatch_writes": 1, + "dispatch_class": "STD", + "dispatch_writes": 2, "dispatch_demand": { - "ALU": 1, + "ALU": 0, "BRU": 0, - "AGU": 0, - "STD": 0, + "AGU": 1, + "STD": 1, "FSU": 0, "SYS": 0, "CMD": 0, "BOUNDARY": 0 }, "dispatch_capabilities": { - "ALU": "SIMPLE_ALU", + "ALU": "NONE", "BRU": "NONE", - "AGU": "NONE", - "STD": "NONE", + "AGU": "STORE_ADDRESS", + "STD": "STORE_DATA", "FSU": "NONE", "SYS": "NONE", "CMD": "NONE", "BOUNDARY": "NONE" }, - "memory_request_count": 0, - "p_source_count": 1, + "memory_request_count": 1, + "p_source_count": 2, "p_destination_count": 0, "t_allocation_count": 0, "u_allocation_count": 0, - "reason": "generated dispatch recipe", + "reason": "compact scalar store consumes base plus relative T#1", "pc_read_parent": "NONE", "pc_read_class": "NONE" } @@ -9209,8 +9209,8 @@ "pattern": "..........101010", "mask": "0x3f", "match": "0x2a", - "major_cat": "COMPRESSED", - "minor_cat": "compressed", + "major_cat": "STORE", + "minor_cat": "compressed_store", "rd_kind": "NONE", "rs1_kind": "REG", "rs2_kind": "NONE", @@ -9222,50 +9222,50 @@ "op_id": 583, "ooo": { "disposition": "DISPATCH", - "recipe_kind": "SINGLE", - "uop_count_min": 1, - "uop_count_max": 1, + "recipe_kind": "SCALAR_STORE", + "uop_count_min": 2, + "uop_count_max": 2, "complex_break": false, - "late_split_kind": "NONE", + "late_split_kind": "STORE_ADDRESS_DATA", "fusion_head_class": "NONE", "fusion_tail_class": "NONE", "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "IEX", + "side_effect_owner": "LSU", "requires_target_validation": false, - "may_trap": false, - "may_trap_late": false, + "may_trap": true, + "may_trap_late": true, "may_redirect": false, "nonspeculative": false, - "dispatch_class": "ALU", - "dispatch_writes": 1, + "dispatch_class": "STD", + "dispatch_writes": 2, "dispatch_demand": { - "ALU": 1, + "ALU": 0, "BRU": 0, - "AGU": 0, - "STD": 0, + "AGU": 1, + "STD": 1, "FSU": 0, "SYS": 0, "CMD": 0, "BOUNDARY": 0 }, "dispatch_capabilities": { - "ALU": "SIMPLE_ALU", + "ALU": "NONE", "BRU": "NONE", - "AGU": "NONE", - "STD": "NONE", + "AGU": "STORE_ADDRESS", + "STD": "STORE_DATA", "FSU": "NONE", "SYS": "NONE", "CMD": "NONE", "BOUNDARY": "NONE" }, - "memory_request_count": 0, - "p_source_count": 1, + "memory_request_count": 1, + "p_source_count": 2, "p_destination_count": 0, "t_allocation_count": 0, "u_allocation_count": 0, - "reason": "generated dispatch recipe", + "reason": "compact scalar store consumes base plus relative T#1", "pc_read_parent": "NONE", "pc_read_class": "NONE" } @@ -15420,7 +15420,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, @@ -29036,7 +29036,7 @@ "fast_resolve_class": "NONE", "implicit_source_mask": 0, "implicit_destination": "NONE", - "side_effect_owner": "BCTRL", + "side_effect_owner": "COMMIT", "requires_target_validation": false, "may_trap": true, "may_trap_late": false, diff --git a/src/common/opcode_meta_gen.py b/src/common/opcode_meta_gen.py index 5cd13f47..2b69262e 100644 --- a/src/common/opcode_meta_gen.py +++ b/src/common/opcode_meta_gen.py @@ -171,12 +171,12 @@ class OpcodeMeta: "c_cmp_eqi": OpcodeMeta(op_id=320, symbol="OP_C_CMP_EQI", mnemonic="c_cmp_eqi", major_cat="BRU_SETC_CMP", minor_cat="c_pred", insn_len=16, mask=0xf83f, match=0x2c, rd_kind="NONE", rs1_kind="NONE", rs2_kind="NONE", imm_kind="SIMM5_6_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_cmp_nei": OpcodeMeta(op_id=321, symbol="OP_C_CMP_NEI", mnemonic="c_cmp_nei", major_cat="BRU_SETC_CMP", minor_cat="c_pred", insn_len=16, mask=0xf83f, match=0x82c, rd_kind="NONE", rs1_kind="NONE", rs2_kind="NONE", imm_kind="SIMM5_6_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_ebreak": OpcodeMeta(op_id=569, symbol="OP_C_EBREAK", mnemonic="c_ebreak", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0xc02c, rd_kind="NONE", rs1_kind="NONE", rs2_kind="NONE", imm_kind="UIMM5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), - "c_ldi": OpcodeMeta(op_id=570, symbol="OP_C_LDI", mnemonic="c_ldi", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x1a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), - "c_lwi": OpcodeMeta(op_id=571, symbol="OP_C_LWI", mnemonic="c_lwi", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0xa, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), + "c_ldi": OpcodeMeta(op_id=570, symbol="OP_C_LDI", mnemonic="c_ldi", major_cat="LOAD", minor_cat="compressed_load", insn_len=16, mask=0x3f, match=0x1a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), + "c_lwi": OpcodeMeta(op_id=571, symbol="OP_C_LWI", mnemonic="c_lwi", major_cat="LOAD", minor_cat="compressed_load", insn_len=16, mask=0x3f, match=0xa, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_movi": OpcodeMeta(op_id=572, symbol="OP_C_MOVI", mnemonic="c_movi", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x16, rd_kind="REG", rs1_kind="NONE", rs2_kind="NONE", imm_kind="SIMM5_6_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_movr": OpcodeMeta(op_id=573, symbol="OP_C_MOVR", mnemonic="c_movr", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x6, rd_kind="REG", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_or": OpcodeMeta(op_id=574, symbol="OP_C_OR", mnemonic="c_or", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x38, rd_kind="NONE", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), - "c_sdi": OpcodeMeta(op_id=575, symbol="OP_C_SDI", mnemonic="c_sdi", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x3a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), + "c_sdi": OpcodeMeta(op_id=575, symbol="OP_C_SDI", mnemonic="c_sdi", major_cat="STORE", minor_cat="compressed_store", insn_len=16, mask=0x3f, match=0x3a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_setc_eq": OpcodeMeta(op_id=322, symbol="OP_C_SETC_EQ", mnemonic="c_setc_eq", major_cat="BRU_SETC_CMP", minor_cat="c_pred", insn_len=16, mask=0x3f, match=0x26, rd_kind="NONE", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_setc_ne": OpcodeMeta(op_id=323, symbol="OP_C_SETC_NE", mnemonic="c_setc_ne", major_cat="BRU_SETC_CMP", minor_cat="c_pred", insn_len=16, mask=0x3f, match=0x36, rd_kind="NONE", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_setc_tgt": OpcodeMeta(op_id=324, symbol="OP_C_SETC_TGT", mnemonic="c_setc_tgt", major_cat="BRU_SETC_CMP", minor_cat="c_pred", insn_len=16, mask=0xf83f, match=0x1c, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), @@ -187,7 +187,7 @@ class OpcodeMeta: "c_srli": OpcodeMeta(op_id=580, symbol="OP_C_SRLI", mnemonic="c_srli", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0x182c, rd_kind="NONE", rs1_kind="NONE", rs2_kind="NONE", imm_kind="UIMM5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_ssrget": OpcodeMeta(op_id=581, symbol="OP_C_SSRGET", mnemonic="c_ssrget", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0x802c, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_sub": OpcodeMeta(op_id=582, symbol="OP_C_SUB", mnemonic="c_sub", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x18, rd_kind="NONE", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), - "c_swi": OpcodeMeta(op_id=583, symbol="OP_C_SWI", mnemonic="c_swi", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0x3f, match=0x2a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), + "c_swi": OpcodeMeta(op_id=583, symbol="OP_C_SWI", mnemonic="c_swi", major_cat="STORE", minor_cat="compressed_store", insn_len=16, mask=0x3f, match=0x2a, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM5_11_S5", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_zext_b": OpcodeMeta(op_id=584, symbol="OP_C_ZEXT_B", mnemonic="c_zext_b", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0x581c, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_zext_h": OpcodeMeta(op_id=585, symbol="OP_C_ZEXT_H", mnemonic="c_zext_h", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0x601c, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), "c_zext_w": OpcodeMeta(op_id=586, symbol="OP_C_ZEXT_W", mnemonic="c_zext_w", major_cat="COMPRESSED", minor_cat="compressed", insn_len=16, mask=0xf83f, match=0x681c, rd_kind="NONE", rs1_kind="REG", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn16.decode"), @@ -734,7 +734,6 @@ class OpcodeMeta: "xor": OpcodeMeta(op_id=297, symbol="OP_XOR", mnemonic="xor", major_cat="ALU_INT", minor_cat="alu", insn_len=32, mask=0x707f, match=0x4005, rd_kind="REG", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn32.decode"), "xori": OpcodeMeta(op_id=298, symbol="OP_XORI", mnemonic="xori", major_cat="ALU_INT", minor_cat="alu", insn_len=32, mask=0x707f, match=0x4015, rd_kind="REG", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM12_20_S12", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn32.decode"), "xoriw": OpcodeMeta(op_id=299, symbol="OP_XORIW", mnemonic="xoriw", major_cat="ALU_INT", minor_cat="alu", insn_len=32, mask=0x707f, match=0x4035, rd_kind="REG", rs1_kind="REG", rs2_kind="NONE", imm_kind="SIMM12_20_S12", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn32.decode"), - "xb": OpcodeMeta(op_id=627, symbol="OP_XB", mnemonic="xb", major_cat="CMD_PIPE", minor_cat="cmd", insn_len=32, mask=0x7fff, match=0x6f81, rd_kind="NONE", rs1_kind="NONE", rs2_kind="NONE", imm_kind="NONE", block_kind="NONE", cmd_kind="BLOCK_SPLIT", flags="", source_file="insn32.decode"), "xorw": OpcodeMeta(op_id=300, symbol="OP_XORW", mnemonic="xorw", major_cat="ALU_INT", minor_cat="alu", insn_len=32, mask=0x707f, match=0x4025, rd_kind="REG", rs1_kind="REG", rs2_kind="REG", imm_kind="NONE", block_kind="NONE", cmd_kind="NONE", flags="", source_file="insn32.decode"), } diff --git a/tests/test_benchmark_autonomous_natural.py b/tests/test_benchmark_autonomous_natural.py deleted file mode 100644 index ea1ed8c6..00000000 --- a/tests/test_benchmark_autonomous_natural.py +++ /dev/null @@ -1,580 +0,0 @@ -import json -import subprocess -import tempfile -import unittest -from pathlib import Path - - -ROOT = Path(__file__).resolve().parents[1] -TB = ROOT / "tools" / "chisel" / "benchmark_autonomous_top_natural_tb.cpp" -RUNNER = ROOT / "tools" / "chisel" / "run_chisel_benchmark_autonomous_top_natural.sh" - - -class BenchmarkAutonomousNaturalTests(unittest.TestCase): - def compile_self_test(self, directory: Path) -> Path: - exe = directory / "natural_self_test" - subprocess.run( - [ - "c++", - "-std=c++17", - "-DLINXCORE_BENCHMARK_AUTONOMOUS_NATURAL_SELF_TEST", - "-I", - str(ROOT / "tools" / "chisel"), - str(TB), - "-o", - str(exe), - ], - check=True, - cwd=ROOT, - ) - return exe - - def load_manifest_without_duplicate_keys(self, manifest: Path): - def reject_duplicates(pairs): - seen = set() - result = {} - for key, value in pairs: - if key in seen: - raise AssertionError(f"duplicate manifest key: {key}") - seen.add(key) - result[key] = value - return result - - return json.loads(manifest.read_text(encoding="utf-8"), object_pairs_hook=reject_duplicates) - - def test_cpp_helpers_self_test(self): - with tempfile.TemporaryDirectory() as tmp: - exe = self.compile_self_test(Path(tmp)) - result = subprocess.run([str(exe), "--self-test"], check=True, text=True, capture_output=True) - self.assertIn("benchmark-autonomous-natural-self-test: ok", result.stdout) - - def test_cpp_rejects_forbidden_oracle_options(self): - with tempfile.TemporaryDirectory() as tmp: - exe = self.compile_self_test(Path(tmp)) - result = subprocess.run( - [ - str(exe), - "--memory-hex", - "m.mem", - "--reset-pc", - "0x1000", - "--reset-sp", - "0x2000", - "--commit-trace", - "c.jsonl", - "--uart-output", - "u.txt", - "--manifest", - "m.json", - "--expected-rows", - "rows.jsonl", - ], - text=True, - capture_output=True, - ) - self.assertNotEqual(result.returncode, 0) - self.assertIn("forbidden", result.stderr) - - def test_cpp_terminal_self_tests_publish_manifest_fields(self): - cases = { - "finisher-pass": (0, "finisher_pass", 0x5555, True, ""), - "finisher-fail": (1, "finisher_fail", 0x3333, False, ""), - "exit-pass": (0, "finisher_pass", 0x5555, True, ""), - "exit-fail": (1, "finisher_fail", 0, False, ""), - "trap": (1, "trap", 0, False, ""), - "timeout": (1, "timeout", 0, False, ""), - "uart": (1, "halted", 0, False, "OK\n"), - } - with tempfile.TemporaryDirectory() as tmp: - tmp_path = Path(tmp) - exe = self.compile_self_test(tmp_path) - for case, (returncode, status, code, passed, uart) in cases.items(): - manifest = tmp_path / f"{case}.json" - uart_output = tmp_path / f"{case}.uart" - result = subprocess.run( - [ - str(exe), - "--self-test-case", - case, - "--manifest", - str(manifest), - "--uart-output", - str(uart_output), - ], - text=True, - capture_output=True, - ) - self.assertEqual(result.returncode, returncode, (case, result.stderr, result.stdout)) - payload = self.load_manifest_without_duplicate_keys(manifest) - self.assertEqual(payload["terminal_status"], status) - self.assertIn("ipc", payload) - self.assertAlmostEqual(payload["ipc"], payload["commits"] / payload["cycles"]) - self.assertEqual(payload["performance"], {}) - self.assertEqual(payload["finisher_code"], code) - self.assertEqual(payload["finisher_pass"], passed) - self.assertEqual(payload["uart"], uart) - if case == "exit-pass": - self.assertEqual(payload["service_requests"], 1) - self.assertEqual(payload["last_service_nr"], 93) - self.assertEqual(payload["sys_exit_code"], 0) - elif case == "exit-fail": - self.assertEqual(payload["service_requests"], 1) - self.assertEqual(payload["last_service_nr"], 93) - self.assertEqual(payload["sys_exit_code"], 7) - else: - self.assertEqual(payload["service_requests"], 0) - self.assertIsNone(payload["last_service_nr"]) - self.assertIsNone(payload["sys_exit_code"]) - self.assertEqual(payload["service_responses"], 0) - self.assertIsNone(payload["unsupported_service_nr"]) - self.assertEqual(uart_output.read_text(encoding="utf-8"), uart) - self.assertEqual(payload["schema"], "linxcore.benchmark_autonomous_natural.v1") - self.assertEqual(payload["artifacts"]["event_trace"], "self-test.events.jsonl") - self.assertEqual(payload["artifacts"]["uart_output"], str(uart_output)) - - def test_cpp_service_responder_self_test_publishes_manifest_fields(self): - with tempfile.TemporaryDirectory() as tmp: - tmp_path = Path(tmp) - exe = self.compile_self_test(tmp_path) - subprocess.run([str(exe), "--self-test"], check=True, text=True, capture_output=True) - payload = self.load_manifest_without_duplicate_keys( - Path("/tmp/linxcore-natural-self-test-manifest.json") - ) - self.assertEqual(payload["service_requests"], 1) - self.assertEqual(payload["service_responses"], 1) - self.assertEqual(payload["last_service_nr"], 96) - self.assertAlmostEqual(payload["ipc"], 3 / 9) - self.assertEqual(payload["performance"], {}) - self.assertIsNone(payload["unsupported_service_nr"]) - self.assertIsNone(payload["sys_exit_code"]) - - def test_cpp_exit_self_tests_use_no_response_and_manifest_exit_code(self): - with tempfile.TemporaryDirectory() as tmp: - tmp_path = Path(tmp) - exe = self.compile_self_test(tmp_path) - pass_manifest = tmp_path / "exit-pass.json" - fail_manifest = tmp_path / "exit-fail.json" - pass_uart = tmp_path / "exit-pass.uart" - fail_uart = tmp_path / "exit-fail.uart" - - pass_result = subprocess.run( - [ - str(exe), - "--self-test-case", - "exit-pass", - "--manifest", - str(pass_manifest), - "--uart-output", - str(pass_uart), - ], - text=True, - capture_output=True, - ) - fail_result = subprocess.run( - [ - str(exe), - "--self-test-case", - "exit-fail", - "--manifest", - str(fail_manifest), - "--uart-output", - str(fail_uart), - ], - text=True, - capture_output=True, - ) - - self.assertEqual(pass_result.returncode, 0, pass_result.stderr) - self.assertEqual(fail_result.returncode, 1, fail_result.stderr) - passing = self.load_manifest_without_duplicate_keys(pass_manifest) - failing = self.load_manifest_without_duplicate_keys(fail_manifest) - self.assertEqual(passing["terminal_status"], "finisher_pass") - self.assertIs(passing["finisher_pass"], True) - self.assertEqual(passing["sys_exit_code"], 0) - self.assertEqual(passing["last_service_nr"], 93) - self.assertEqual(passing["service_requests"], 1) - self.assertEqual(passing["service_responses"], 0) - self.assertEqual(failing["terminal_status"], "finisher_fail") - self.assertIs(failing["finisher_pass"], False) - self.assertEqual(failing["sys_exit_code"], 7) - self.assertEqual(failing["last_service_nr"], 93) - self.assertEqual(failing["service_requests"], 1) - self.assertEqual(failing["service_responses"], 0) - - def test_cpp_finisher_pass_uses_first_cycle_code(self): - with tempfile.TemporaryDirectory() as tmp: - tmp_path = Path(tmp) - exe = self.compile_self_test(tmp_path) - manifest = tmp_path / "pass.json" - uart_output = tmp_path / "pass.uart" - subprocess.run( - [ - str(exe), - "--self-test-case", - "finisher-pass", - "--manifest", - str(manifest), - "--uart-output", - str(uart_output), - ], - check=True, - text=True, - capture_output=True, - ) - payload = self.load_manifest_without_duplicate_keys(manifest) - self.assertEqual(payload["finisher_code"], 0x5555) - self.assertIs(payload["finisher_pass"], True) - self.assertEqual(payload["terminal_status"], "finisher_pass") - - def test_runner_rejects_forbidden_oracle_options_before_tools(self): - result = subprocess.run( - [ - "bash", - str(RUNNER), - "--elf", - "tests/benchmarks/build/dhrystone_real.elf", - "--expected-rows", - "rows.jsonl", - ], - cwd=ROOT, - text=True, - capture_output=True, - ) - self.assertNotEqual(result.returncode, 0) - self.assertIn("forbidden", result.stderr) - - def test_runner_has_no_expected_or_qemu_harness_inputs(self): - text = RUNNER.read_text(encoding="utf-8") - self.assertNotIn("--qemu-trace \"", text) - self.assertNotIn("--expected-rows \"", text) - self.assertIn("frontend_fetch_elf_memory.py", text) - self.assertIn("EmitLinxCoreBenchmarkAutonomousTop", text) - self.assertIn("--event-trace \"${EVENT_TRACE}\"", text) - self.assertIn("\"event_trace\": {\"path\": str(event), \"sha256\": sha256(event)}", text) - - def test_runner_uses_canonical_direct_boot_stack_by_default(self): - text = RUNNER.read_text(encoding="utf-8") - self.assertIn('DIRECT_BOOT_SP="0x0000000007fefff0"', text) - self.assertIn('RESET_SP="${RESET_SP:-${DIRECT_BOOT_SP}}"', text) - self.assertNotIn('RESET_SP="${RESET_SP:-${ELF_STACK}}"', text) - self.assertIn("--reset-sp)", text) - - def test_cpp_iterates_both_commit_lanes_in_slot_order(self): - driver = TB.read_text(encoding="utf-8") - - self.assertIn("read_commit_row(\n const VLinxCoreBenchmarkAutonomousTop &dut,\n int slot)", driver) - self.assertIn("dut.io_commit_rows_1_valid", driver) - self.assertIn("commit_rows_this_cycle", driver) - self.assertIn("for (int slot = 0; slot < 2; ++slot)", driver) - self.assertIn("const auto row = read_commit_row(dut, slot);", driver) - self.assertIn("commit_rows_per_cycle_hist[clamp_hist_index(commit_rows", driver) - self.assertNotIn("commit_rows_per_cycle_hist[commit_valid ? 1 : 0]++", driver) - - def test_head_issue_observability_is_passive_and_serialized(self): - live_top = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreFrontendFetchRfAluTraceTop.scala" - ).read_text(encoding="utf-8") - top = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreBenchmarkAutonomousTop.scala" - ).read_text(encoding="utf-8") - driver = TB.read_text(encoding="utf-8") - - forwarded = { - "io.debugCommitHeadStatus := live.io.commitHeadStatus.asUInt", - "io.debugCommitHeadRobValue := live.io.commitHeadRobValue", - "io.debugRobOccupiedMask := live.io.occupiedMask", - "io.debugRobCompletedMask := live.io.completedMask", - "io.debugTuRenameSourceUnderflowMask := live.io.tuRenameSourceUnderflowMask", - "io.debugTuRenameBlockedByTAlloc := live.io.tuRenameBlockedByTAlloc", - "io.debugTuRenameBlockedByUAlloc := live.io.tuRenameBlockedByUAlloc", - "io.debugTuRenameTUsedEntries := live.io.tuRenameTUsedEntries", - "io.debugTuRenameUUsedEntries := live.io.tuRenameUUsedEntries", - "io.debugGprReservationCount := live.io.gprReservationCount", - "io.debugGprReservationNeed := live.io.gprReservationNeed", - "io.debugGprFreeCount := live.io.gprFreeCount", - "io.debugGprMapQValidCount := live.io.gprMapQValidCount", - "io.debugGprMapQFreeCount := live.io.gprMapQFreeCount", - "io.debugGprFreeListMismatchCount := live.io.gprFreeListMismatchCount", - "io.debugGprCommitAccepted := live.io.gprCommitAccepted", - "io.debugGprCommitBlockBid := live.io.gprCommitBlockBid", - "io.debugGprCommittedMapQCount := live.io.gprCommittedMapQCount", - "io.debugGprReleasedPhysCount := live.io.gprReleasedPhysCount", - "io.debugRobRenameUpdateAttemptValid := live.io.robRenameUpdateAttemptValid", - "io.debugRobRenameUpdateReady := live.io.robRenameUpdateReady", - "io.debugRobRenameUpdateFire := live.io.robRenameUpdateFire", - "io.debugRobRenameUpdateIgnored := live.io.robRenameUpdateIgnored", - "io.debugIssueHeadPc := live.io.issueQueueHeadPc", - "io.debugIssueHeadStid := live.io.issueQueueHeadStid", - "io.debugIssueHeadBidValue := live.io.issueQueueHeadBidValue", - "io.debugIssueHeadRidValue := live.io.issueQueueHeadRidValue", - "io.debugIssueHeadSrcPhysTag := live.io.issueQueueHeadSrcPhysTag", - "io.debugIssueSourceReadyMask := live.io.issueQueueSourceReadyMask", - "io.debugIssueScalarSpOrderBlocked := live.io.issueQueueScalarSpOrderBlocked", - "io.debugIssueBankScalarSpOrderBlockedMask := live.io.issueQueueBankScalarSpOrderBlockedMask", - "io.debugScalarSpStid0IssueHeadValid := live.io.scalarSpStid0IssueHeadValid", - "io.debugScalarSpStid0IssueHeadBidValue := live.io.scalarSpStid0IssueHeadBidValue", - "io.debugScalarSpStid0IssueHeadRidValue := live.io.scalarSpStid0IssueHeadRidValue", - "io.debugRfReadyMask := live.io.rfReadyMask", - "io.debugPWakeupValid := live.io.rfWriteValid", - "io.debugPWakeupTag := live.io.rfWriteTag", - "io.debugExecuteUnsupported := live.io.executeUnsupported", - "io.debugExecuteCompleteRobValue := live.io.executeCompleteRobValue", - "io.debugRobCompleteResultBits := Cat(live.io.completeIgnored, live.io.completeAccepted)", - } - for connection in forwarded: - self.assertIn(connection, top) - self.assertNotIn("live.io.", top.split("private val row =", 1)[0].split("Input(", 1)[0]) - - identity_sources = { - "io.issueQueueInputPc := Mux(inputValid, issue.io.in.pc, 0.U)", - "io.issueQueueInputRidValue := Mux(inputValid, issue.io.in.rid.value, 0.U)", - "io.issueQueueOutputPc := Mux(outputValid, issue.io.issueUop.pc, 0.U)", - "io.issueQueueOutputOpcode := Mux(outputValid, issue.io.issueUop.opcode, 0.U)", - "io.issueQueueOutputRidValue := Mux(outputValid, issue.io.issueUop.rid.value, 0.U)", - "io.executeAcceptedIdentityValid := accepted", - "io.executeAcceptedPc := Mux(accepted, issue.io.issueUop.pc, 0.U)", - "io.executeAcceptedRidValue := Mux(accepted, issue.io.issueUop.rid.value, 0.U)", - "io.issueQueueHeadStid := issue.io.headStid", - "io.issueQueueHeadBidValue := Mux(issue.io.headValid, issue.io.headBid.value, 0.U)", - "io.issueQueueHeadRidValue := Mux(issue.io.headValid, issue.io.headRid.value, 0.U)", - "io.issueQueueScalarSpOrderBlocked := issue.io.scalarSpOrderBlocked", - "io.issueQueueBankScalarSpOrderBlockedMask := issue.io.bankScalarSpOrderBlockedMask", - "io.scalarSpStid0IssueHeadValid := scalarSpOrder.io.issueHeadValidByStid(0)", - "scalarSpOrder.io.issueHeadBidByStid(0).value", - "scalarSpOrder.io.issueHeadRidByStid(0).value", - } - for connection in identity_sources: - self.assertIn(connection, live_top) - self.assertIn("val accepted = executeAccepted", live_top) - self.assertIn( - "LinxCoreFrontendFetchRfAluTraceTopIssueDiagnosticsWiring.connect(", - live_top, - ) - self.assertIn("scalarSpOrder,", live_top) - self.assertNotIn("issueQueueHeadPc := Mux", live_top) - - identity_forwarding = { - "io.debugIssueInputPc := live.io.issueQueueInputPc", - "io.debugIssueInputRidValue := live.io.issueQueueInputRidValue", - "io.debugIssueOutputPc := live.io.issueQueueOutputPc", - "io.debugIssueOutputRidValue := live.io.issueQueueOutputRidValue", - "io.debugExecuteAcceptedPc := live.io.executeAcceptedPc", - "io.debugExecuteAcceptedRidValue := live.io.executeAcceptedRidValue", - } - for connection in identity_forwarding: - self.assertIn(connection, top) - - serialized = { - "perf_manifest_json", - "performance", - "ipc", - "frontend", - "decode_rename", - "issue", - "execute", - "completion", - "commit", - "rob_head", - "load_store_service", - "blocked_bits_hist", - "rows_per_cycle_hist", - "commit_head_status", - "commit_head_rob_value", - "rob_occupied_mask", - "rob_completed_mask", - "decode_block_bits", - "decode_ready_bits", - "local_pending_counts", - "local_ready_masks", - "tu_rename_source_underflow_mask", - "tu_rename_blocked_by_t_alloc", - "tu_rename_blocked_by_u_alloc", - "tu_rename_t_used_entries", - "tu_rename_u_used_entries", - "gpr_reservation_count", - "gpr_reservation_need", - "gpr_free_count", - "gpr_mapq_valid_count", - "gpr_mapq_free_count", - "gpr_free_list_mismatch_count", - "gpr_commit_accepted", - "gpr_commit_block_bid", - "gpr_committed_mapq_count", - "gpr_released_phys_count", - "rob_rename_update_attempt_valid", - "rob_rename_update_ready", - "rob_rename_update_fire", - "rob_rename_update_ignored", - "issue_head_pc", - "issue_head_stid", - "issue_head_bid_valid", - "issue_head_bid_value", - "issue_head_rid_valid", - "issue_head_rid_value", - "issue_head_src0_phys_tag", - "issue_source_ready_mask", - "issue_scalar_sp_order_blocked", - "issue_bank_scalar_sp_order_blocked_mask", - "scalar_sp_stid0_issue_head_valid", - "scalar_sp_stid0_issue_head_bid_valid", - "scalar_sp_stid0_issue_head_bid_value", - "scalar_sp_stid0_issue_head_rid_valid", - "scalar_sp_stid0_issue_head_rid_value", - "rf_ready_mask", - "p_wakeup_tag", - "p_wakeup_head_match", - "execute_unsupported", - "execute_complete_rob_value", - "rob_complete_arbiter_bits", - "rob_complete_result_bits", - "issue_input_pc", - "issue_input_rid_value", - "issue_output_valid", - "issue_output_pc", - "issue_output_opcode", - "issue_output_rid_value", - "execute_accepted_identity_valid", - "execute_accepted_pc", - "execute_accepted_rid_value", - } - for field in serialized: - self.assertIn(field, driver) - - def test_tu_occupancy_width_preserves_31_and_32(self): - top = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreBenchmarkAutonomousTop.scala" - ).read_text(encoding="utf-8") - driver = TB.read_text(encoding="utf-8") - - self.assertIn("private val tuCountWidth = log2Ceil(mapQDepth + 1)", top) - self.assertIn("coreParams.scalarLsu.mapQDepth", top) - self.assertIn("debugTuRenameTUsedEntries = Output(UInt(tuCountWidth.W))", top) - self.assertIn("debugTuRenameUUsedEntries = Output(UInt(tuCountWidth.W))", top) - self.assertNotIn("debugTuRenameTUsedEntries = Output(UInt(3.W))", top) - self.assertNotIn("debugTuRenameUUsedEntries = Output(UInt(3.W))", top) - - alias_mask = (1 << 3) - 1 - self.assertEqual(31 & alias_mask, 7) - self.assertEqual(32 & alias_mask, 0) - self.assertNotEqual(31, 32) - self.assertIn("std::uint64_t tu_rename_t_used_entries = 0;", driver) - self.assertIn("std::uint64_t tu_rename_u_used_entries = 0;", driver) - - def test_tu_retire_lifecycle_observability_is_forwarded_and_serialized(self): - top = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreBenchmarkAutonomousTop.scala" - ).read_text(encoding="utf-8") - driver = TB.read_text(encoding="utf-8") - - forwarded = { - "io.debugTuRetireCommandValid := live.io.tuRetireCommandValid", - "io.debugTuRetireCommandFire := live.io.tuRetireCommandFire", - "io.debugTuRetireLocalBlockCommitPending := live.io.tuRetireLocalBlockCommitPending", - "io.debugTuRetireLocalBlockCommitValid := live.io.tuRetireLocalBlockCommitValid", - "io.debugTuRetireLocalBlockCommitReady := live.io.tuRetireLocalBlockCommitReady", - "io.debugTuRetireLocalBlockCommitFire := live.io.tuRetireLocalBlockCommitFire", - "io.debugTuRetireAccepted := live.io.tuRetireAccepted", - "io.debugTuRetireMiss := live.io.tuRetireMiss", - "io.debugTuRetireReleaseMismatch := live.io.tuRetireReleaseMismatch", - "io.debugTuRetireUnsupported := live.io.tuRetireUnsupported", - "io.debugRobDeallocValidMask := live.io.deallocValidMask", - "io.debugRobDeallocCount := live.io.deallocCount", - "io.debugRobDeallocBlockLastValid := live.io.robDeallocBlockLastValid", - "io.debugRobDeallocBlockLastBlockBid := live.io.robDeallocBlockLastBlockBid", - "io.debugBlockScalarDoneFire := live.io.blockScalarDoneFire", - "io.debugBlockScalarDoneBid := live.io.blockScalarDoneBid", - "io.debugBlockRetireFire := live.io.blockRetireFire", - "io.debugBlockRetireBid := live.io.blockRetireBid", - } - for connection in forwarded: - self.assertIn(connection, top) - - serialized = { - "tu_retire_command_valid", - "tu_retire_command_fire", - "tu_retire_local_block_commit_pending", - "tu_retire_local_block_commit_valid", - "tu_retire_local_block_commit_ready", - "tu_retire_local_block_commit_fire", - "tu_retire_accepted", - "tu_retire_miss", - "tu_retire_release_mismatch", - "tu_retire_unsupported", - "rob_dealloc_valid_mask", - "rob_dealloc_count", - "rob_dealloc_block_last_valid", - "rob_dealloc_block_last_block_bid", - "block_scalar_done_fire", - "block_scalar_done_bid", - "block_retire_fire", - "block_retire_bid", - } - for field in serialized: - self.assertIn(field, driver) - - def test_autonomous_top_opts_into_reduced_sc_store_execution(self): - top_path = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreBenchmarkAutonomousTop.scala" - ) - live_top_path = ( - ROOT - / "chisel" - / "src" - / "main" - / "scala" - / "linxcore" - / "top" - / "LinxCoreFrontendFetchRfAluTraceTop.scala" - ) - top = top_path.read_text(encoding="utf-8") - live_top = live_top_path.read_text(encoding="utf-8") - - self.assertIn("useReducedStoreDispatchStq = true", top) - self.assertIn("useReducedStoreStaAddressExecBridge = true", top) - self.assertIn("val useReducedStoreDispatchStq: Boolean = false", live_top) - self.assertIn("val useReducedStoreStaAddressExecBridge: Boolean = false", live_top) - self.assertIn( - "storeStaAddressExecBridge.io.enable := useReducedStoreStaAddressExecBridge && useReducedStoreDispatchStq", - live_top, - ) - self.assertIn("scalarScIssueGate.ready", live_top) - self.assertNotIn("val ready = false.B", live_top) - - -if __name__ == "__main__": - unittest.main() diff --git a/tests/test_chisel_test_runner.py b/tests/test_chisel_test_runner.py new file mode 100644 index 00000000..839e7972 --- /dev/null +++ b/tests/test_chisel_test_runner.py @@ -0,0 +1,179 @@ +import json +import os +from pathlib import Path +import stat +import subprocess +import tempfile +import textwrap +import unittest + + +class ChiselTestRunnerTest(unittest.TestCase): + repo_root = Path(__file__).resolve().parents[1] + runner = ( + repo_root + / "tools" + / "chisel" + / "run_chisel_tests.sh" + ) + + def setUp(self): + self.temp_dir = tempfile.TemporaryDirectory() + self.root = Path(self.temp_dir.name) + self.bin_dir = self.root / "bin" + self.bin_dir.mkdir() + self.capture = self.root / "sbt.json" + fake_sbt = self.bin_dir / "sbt" + fake_sbt.write_text( + textwrap.dedent( + """ + #!/usr/bin/env python3 + import json + import os + from pathlib import Path + import sys + + Path(os.environ["FAKE_SBT_CAPTURE"]).write_text( + json.dumps({ + "argv": sys.argv[1:], + "jobs": os.environ.get("LINX_CHISEL_TEST_JOBS"), + }), + encoding="utf-8", + ) + raise SystemExit(int(os.environ.get("FAKE_SBT_STATUS", "0"))) + """ + ).lstrip(), + encoding="utf-8", + ) + fake_sbt.chmod(fake_sbt.stat().st_mode | stat.S_IXUSR) + + def tearDown(self): + self.temp_dir.cleanup() + + def run_runner(self, *args: str, extra_env: dict[str, str] | None = None): + env = os.environ.copy() + env.update( + { + "PATH": f"{self.bin_dir}{os.pathsep}{env['PATH']}", + "FAKE_SBT_CAPTURE": str(self.capture), + "LINX_CHISEL_ARTIFACT_ROOT": str(self.root / "artifacts"), + "LINX_CHISEL_HEARTBEAT_SECONDS": "1", + } + ) + if extra_env: + env.update(extra_env) + return subprocess.run( + ["bash", str(self.runner), *args], + cwd=self.runner.parents[2], + env=env, + capture_output=True, + text=True, + ) + + def read_capture(self): + return json.loads(self.capture.read_text(encoding="utf-8")) + + def test_repeated_only_selectors_form_one_test_only_command(self): + result = self.run_runner("--only", "FooSpec", "--only", "BarSpec") + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + captured = self.read_capture() + self.assertEqual(captured["argv"][-1], "testOnly *FooSpec* *BarSpec*") + self.assertEqual(captured["argv"].count("--server"), 1) + + def test_test_name_limits_one_suite_to_one_small_scenario(self): + result = self.run_runner( + "--only", "FooSpec", "--test-name", "joined") + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertEqual( + self.read_capture()["argv"][-1], + "testOnly *FooSpec* -- -z joined", + ) + + def test_all_and_only_are_mutually_exclusive(self): + result = self.run_runner("--all", "--only", "FooSpec") + + self.assertEqual(result.returncode, 2) + self.assertIn("mutually exclusive", result.stderr) + self.assertFalse(self.capture.exists()) + + def test_default_jobs_is_one(self): + result = self.run_runner("--only", "FooSpec") + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertEqual(self.read_capture()["jobs"], "1") + summary = next( + line.removeprefix("linx-chisel-summary ") + for line in result.stdout.splitlines() + if line.startswith("linx-chisel-summary ") + ) + self.assertEqual(json.loads(summary)["jobs"], 1) + + def test_default_heap_is_two_gib(self): + result = self.run_runner("--only", "FooSpec") + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + argv = self.read_capture()["argv"] + self.assertEqual(argv[argv.index("--mem") + 1], "2048") + + def test_ooo_integration_uses_bounded_simulation_profiles(self): + source = ( + self.repo_root + / "chisel" + / "src" + / "test" + / "scala" + / "linxcore" + / "ooo" + / "OOOIntegrationSpec.scala" + ).read_text(encoding="utf-8") + + self.assertIn("SimulationParamProfiles", source) + self.assertNotIn("{ParamProfiles,", source) + self.assertNotIn("val base = ParamProfiles.", source) + + def test_cli_jobs_overrides_environment(self): + result = self.run_runner( + "--only", + "FooSpec", + "--jobs", + "3", + extra_env={"LINX_CHISEL_TEST_JOBS": "5"}, + ) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertEqual(self.read_capture()["jobs"], "3") + + def test_zero_stall_disables_idle_termination(self): + result = self.run_runner("--only", "FooSpec", "--stall-seconds", "0") + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertTrue(self.capture.exists()) + + def test_invalid_numeric_options_fail_before_sbt(self): + cases = ( + ("--heartbeat-seconds", "0"), + ("--stall-seconds", "-1"), + ("--wall-seconds", "-1"), + ("--jobs", "0"), + ("--artifact-budget-bytes", "-1"), + ) + for option, value in cases: + with self.subTest(option=option, value=value): + self.capture.unlink(missing_ok=True) + result = self.run_runner("--only", "FooSpec", option, value) + self.assertEqual(result.returncode, 2) + self.assertIn("error:", result.stderr) + self.assertFalse(self.capture.exists()) + + def test_fake_sbt_failure_status_is_preserved(self): + result = self.run_runner( + "--only", "FooSpec", extra_env={"FAKE_SBT_STATUS": "7"}) + + self.assertEqual(result.returncode, 7, result.stdout + result.stderr) + self.assertEqual(self.read_capture()["argv"][-1], "testOnly *FooSpec*") + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_chisel_test_supervisor.py b/tests/test_chisel_test_supervisor.py new file mode 100644 index 00000000..4c67b179 --- /dev/null +++ b/tests/test_chisel_test_supervisor.py @@ -0,0 +1,234 @@ +import contextlib +import io +import json +import os +from pathlib import Path +import subprocess +import sys +import tempfile +import textwrap +import time +import unittest + +from tools.chisel.chisel_test_supervisor import ( + SupervisorConfig, + parse_non_negative_int, + parse_positive_int, + snapshot_artifacts, + supervise, +) + + +class ChiselTestSupervisorTest(unittest.TestCase): + def run_supervised(self, config: SupervisorConfig, program: str, *args: str): + output = io.StringIO() + with contextlib.redirect_stdout(output): + status = supervise(config, [sys.executable, "-c", program, *args]) + return status, output.getvalue() + + def test_positive_and_non_negative_values_reject_invalid_text(self): + self.assertEqual(parse_positive_int("heartbeat", "3"), 3) + self.assertEqual(parse_non_negative_int("stall", "0"), 0) + for text in ("", "0", "-1", "1.5", "one"): + with self.subTest(kind="positive", text=text): + with self.assertRaisesRegex(ValueError, "heartbeat"): + parse_positive_int("heartbeat", text) + for text in ("", "-1", "1.5", "one"): + with self.subTest(kind="non-negative", text=text): + with self.assertRaisesRegex(ValueError, "stall"): + parse_non_negative_int("stall", text) + + def test_snapshot_artifacts_reports_total_and_largest_files(self): + with tempfile.TemporaryDirectory() as temp_dir: + root = Path(temp_dir) + (root / "small.bin").write_bytes(b"a" * 3) + nested = root / "nested" + nested.mkdir() + (nested / "large.bin").write_bytes(b"b" * 11) + + snapshot = snapshot_artifacts(root) + + self.assertEqual(snapshot.bytes, 14) + self.assertEqual(snapshot.file_count, 2) + self.assertEqual(snapshot.largest[0], ("nested/large.bin", 11)) + + def test_output_progress_prevents_idle_stall(self): + program = textwrap.dedent( + """ + import time + for index in range(6): + print(f"tick={index}", flush=True) + time.sleep(0.25) + """ + ) + status, output = self.run_supervised( + SupervisorConfig(heartbeat_seconds=1, stall_seconds=1), program) + + self.assertEqual(status, 0) + self.assertIn("tick=5", output) + self.assertNotIn('"reason": "idle-stall"', output) + + def test_artifact_progress_prevents_idle_stall(self): + with tempfile.TemporaryDirectory() as temp_dir: + artifact = Path(temp_dir) / "progress.bin" + program = textwrap.dedent( + """ + from pathlib import Path + import sys + import time + target = Path(sys.argv[1]) + for _ in range(6): + with target.open("ab") as stream: + stream.write(b"x") + stream.flush() + time.sleep(0.25) + """ + ) + status, output = self.run_supervised( + SupervisorConfig( + heartbeat_seconds=1, + stall_seconds=1, + artifact_root=Path(temp_dir)), + program, + str(artifact), + ) + + self.assertEqual(status, 0) + self.assertEqual(artifact.stat().st_size, 6) + self.assertNotIn('"reason": "idle-stall"', output) + + def test_cpu_active_silent_child_is_not_called_stalled(self): + program = textwrap.dedent( + """ + import time + deadline = time.monotonic() + 1.5 + value = 1 + while time.monotonic() < deadline: + value = (value * 17 + 3) % 1000003 + """ + ) + status, output = self.run_supervised( + SupervisorConfig(heartbeat_seconds=1, stall_seconds=1), program) + + self.assertEqual(status, 0) + self.assertNotIn('"reason": "idle-stall"', output) + + def test_silent_idle_child_exits_124_with_diagnostics(self): + status, output = self.run_supervised( + SupervisorConfig(heartbeat_seconds=1, stall_seconds=1), + "import time; time.sleep(10)", + ) + + self.assertEqual(status, 124) + self.assertIn('"reason": "idle-stall"', output) + self.assertIn("linx-chisel-summary ", output) + self.assertIn('"phase":', output) + + def test_child_failure_status_is_preserved(self): + status, output = self.run_supervised( + SupervisorConfig(heartbeat_seconds=1, stall_seconds=0), + "raise SystemExit(7)", + ) + + self.assertEqual(status, 7) + self.assertIn('"child_status": 7', output) + + def test_artifact_budget_names_largest_file(self): + with tempfile.TemporaryDirectory() as temp_dir: + artifact = Path(temp_dir) / "oversized.bin" + program = "from pathlib import Path; import sys; Path(sys.argv[1]).write_bytes(b'x' * 64)" + status, output = self.run_supervised( + SupervisorConfig( + heartbeat_seconds=1, + stall_seconds=0, + artifact_root=Path(temp_dir), + artifact_budget_bytes=32), + program, + str(artifact), + ) + + self.assertEqual(status, 2) + self.assertIn('"reason": "artifact-budget"', output) + self.assertIn("oversized.bin", output) + self.assertIn('"artifact_bytes": 64', output) + + def test_interrupt_reaches_the_child_process_group(self): + supervisor = ( + Path(__file__).resolve().parents[1] + / "tools" + / "chisel" + / "chisel_test_supervisor.py" + ) + with tempfile.TemporaryDirectory() as temp_dir: + root = Path(temp_dir) + child = root / "child.py" + started = root / "started" + terminated = root / "terminated" + child.write_text( + textwrap.dedent( + """ + from pathlib import Path + import signal + import sys + import time + + started = Path(sys.argv[1]) + terminated = Path(sys.argv[2]) + + def stop(signum, frame): + del frame + terminated.write_text(str(signum), encoding="utf-8") + raise SystemExit(0) + + signal.signal(signal.SIGTERM, stop) + started.write_text("ready", encoding="utf-8") + while True: + time.sleep(0.1) + """ + ), + encoding="utf-8", + ) + process = subprocess.Popen( + [ + sys.executable, + str(supervisor), + "--heartbeat-seconds", + "1", + "--stall-seconds", + "0", + "--", + sys.executable, + str(child), + str(started), + str(terminated), + ], + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + text=True, + ) + try: + deadline = time.monotonic() + 5 + while not started.exists() and time.monotonic() < deadline: + time.sleep(0.05) + self.assertTrue(started.exists(), "child did not start") + + process.terminate() + output, _ = process.communicate(timeout=8) + + self.assertEqual(process.returncode, 143, output) + self.assertTrue(terminated.exists(), output) + self.assertEqual(terminated.read_text(encoding="utf-8"), "15") + summary = next( + line.removeprefix("linx-chisel-summary ") + for line in output.splitlines() + if line.startswith("linx-chisel-summary ") + ) + self.assertEqual(json.loads(summary)["reason"], "signal") + finally: + if process.poll() is None: + process.kill() + process.wait() + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_crosscheck_metadata.py b/tests/test_crosscheck_metadata.py index 1f94757f..dba43ab7 100644 --- a/tests/test_crosscheck_metadata.py +++ b/tests/test_crosscheck_metadata.py @@ -97,12 +97,12 @@ def test_common_crosscheck_failure_persists_manifest_and_status(self) -> None: self.assertEqual(manifest["comparator_status"], 1) self.assertEqual(manifest["summary"]["mismatch_count"], report["mismatch_count"]) - def test_frontend_elf_wrapper_shell_syntax(self) -> None: + def test_canonical_frontend_wrapper_shell_syntax(self) -> None: proc = subprocess.run( [ "bash", "-n", - str(ROOT / "tools" / "chisel" / "run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh"), + str(ROOT / "tools" / "chisel" / "run_chisel_frontend_trace_top_xcheck.sh"), ], cwd=ROOT, text=True, @@ -112,172 +112,6 @@ def test_frontend_elf_wrapper_shell_syntax(self) -> None: ) self.assertEqual(proc.returncode, 0, proc.stdout + proc.stderr) - def _write_jsonl(self, path: Path, rows: list[dict]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text("".join(json.dumps(row) + "\n" for row in rows), encoding="utf-8") - - def _write_frontend_common_bundle(self, build_dir: Path, *, mismatch: bool) -> None: - traces = build_dir / "traces" - report_dir = build_dir / "report" - report_dir.mkdir(parents=True, exist_ok=True) - qemu_live = traces / "qemu.live.raw.jsonl" - qemu_preview = traces / "qemu.live.expected.preview.jsonl" - qemu_ref = traces / "qemu.reference.jsonl" - dut = traces / "dut.chisel.jsonl" - norm_qemu = report_dir / "qemu.normalized.jsonl" - norm_dut = report_dir / "dut.normalized.jsonl" - - qemu_row = self._commit_row(next_pc=0x1004) - dut_row = self._commit_row(next_pc=0x1008 if mismatch else 0x1004) - self._write_jsonl(qemu_live, [qemu_row, qemu_row]) - self._write_jsonl(qemu_preview, [qemu_row]) - self._write_jsonl(qemu_ref, [qemu_row]) - self._write_jsonl(dut, [dut_row]) - self._write_jsonl(norm_qemu, [qemu_row]) - self._write_jsonl(norm_dut, [dut_row]) - - first_mismatch = None - mismatch_count = 0 - if mismatch: - first_mismatch = { - "seq": 0, - "field": "next_pc", - "qemu": 0x1004, - "dut": 0x1008, - "qemu_pc": 0x1000, - "dut_pc": 0x1000, - } - mismatch_count = 1 - - report = { - "qemu_rows": 1, - "dut_rows": 1, - "compared_rows": 1, - "mismatch_count": mismatch_count, - "first_mismatch": first_mismatch, - } - (report_dir / "crosscheck_report.json").write_text( - json.dumps(report, indent=2) + "\n", - encoding="utf-8", - ) - (report_dir / "crosscheck_mismatches.json").write_text( - json.dumps([first_mismatch] if first_mismatch else [], indent=2) + "\n", - encoding="utf-8", - ) - (report_dir / "crosscheck_report.md").write_text("# report\n", encoding="utf-8") - common_manifest = { - "status": "fail" if mismatch else "pass", - "inputs": { - "qemu_trace": str(qemu_ref), - "dut_trace": str(dut), - }, - "normalized": { - "qemu_trace": str(norm_qemu), - "dut_trace": str(norm_dut), - }, - "reports": { - "json": str(report_dir / "crosscheck_report.json"), - "mismatches": str(report_dir / "crosscheck_mismatches.json"), - "markdown": str(report_dir / "crosscheck_report.md"), - "manifest": str(report_dir / "crosscheck_manifest.json"), - }, - } - (report_dir / "crosscheck_manifest.json").write_text( - json.dumps(common_manifest, indent=2) + "\n", - encoding="utf-8", - ) - - def _run_frontend_finalize_fixture( - self, - *, - mismatch: bool, - qemu_args: tuple[str, ...] = ("-nographic", "-kernel", "fixture.elf"), - ) -> tuple[subprocess.CompletedProcess[str], dict, dict]: - with tempfile.TemporaryDirectory() as tmpdir: - build_dir = Path(tmpdir) / "frontend-bundle" - self._write_frontend_common_bundle(build_dir, mismatch=mismatch) - status = "fail" if mismatch else "pass" - exit_status = "1" if mismatch else "0" - proc = subprocess.run( - [ - "bash", - str(ROOT / "tools" / "chisel" / "run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh"), - "--build-dir", - str(build_dir), - "--elf", - str(build_dir / "fixture.elf"), - "--qemu-bin", - "/bin/true", - "--expected-rows", - "7", - "--capture-rows", - "8", - "--pc-lo", - "0x1000", - "--pc-hi", - "0x1004", - "--allow-block-markers", - "--finalize-only", - "generated-rtl", - status, - exit_status, - "--", - *qemu_args, - ], - cwd=ROOT, - text=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - check=False, - ) - report_dir = build_dir / "report" - report = json.loads((report_dir / "frontend_fetch_rf_alu_qemu_elf_report.json").read_text(encoding="utf-8")) - manifest = json.loads( - (report_dir / "frontend_fetch_rf_alu_qemu_elf_manifest.json").read_text(encoding="utf-8") - ) - leftovers = list(report_dir.glob(".frontend_fetch_rf_alu_qemu_elf_*.tmp")) - self.assertEqual(leftovers, []) - return proc, report, manifest - - def test_frontend_finalize_only_pass_bundle_is_self_describing(self) -> None: - proc, report, manifest = self._run_frontend_finalize_fixture(mismatch=False) - self.assertEqual(proc.returncode, 0, proc.stdout + proc.stderr) - self.assertEqual(report["schema"], "linxcore.chisel.frontend_fetch_rf_alu_qemu_elf_report.v2") - self.assertEqual(manifest["schema"], "linxcore.chisel.frontend_fetch_rf_alu_qemu_elf_manifest.v2") - self.assertEqual(manifest["status"], "pass") - self.assertEqual(manifest["counts"]["expected_preview_rows"], 1) - self.assertEqual(manifest["counts"]["dut_captured_rows"], 1) - self.assertEqual(manifest["counts"]["compared_rows"], 1) - self.assertEqual(manifest["mismatch_count"], 0) - self.assertIsNone(manifest["first_mismatch"]) - self.assertEqual(manifest["selected"]["expected_rows"], 7) - self.assertEqual(manifest["selected"]["capture_rows"], 8) - self.assertEqual(manifest["selected"]["qemu_args"], ["-nographic", "-kernel", "fixture.elf"]) - self.assertIn("linxcore", manifest["git"]) - self.assertIn("dirty", manifest["git"]["linxcore"]) - self.assertTrue(any(item["path"].endswith("qemu.live.expected.preview.jsonl") for item in manifest["artifacts"])) - self.assertTrue(all(item["sha256"] for item in manifest["artifacts"])) - self.assertEqual(report["proof_boundary"], manifest["proof_boundary"]) - self.assertNotIn("natural full-core execution", manifest["status"]) - - def test_frontend_finalize_only_mismatch_preserves_status_and_first_mismatch(self) -> None: - proc, report, manifest = self._run_frontend_finalize_fixture(mismatch=True) - self.assertEqual(proc.returncode, 1, proc.stdout + proc.stderr) - self.assertEqual(report["status"], "fail") - self.assertEqual(manifest["exit_status"], 1) - self.assertEqual(manifest["counts"]["qemu_live_raw_rows"], 2) - self.assertEqual(manifest["counts"]["expected_preview_rows"], 1) - self.assertEqual(manifest["counts"]["dut_captured_rows"], 1) - self.assertEqual(manifest["mismatch_count"], 1) - self.assertEqual(manifest["first_mismatch"]["field"], "next_pc") - self.assertEqual(report["first_mismatch"], manifest["first_mismatch"]) - self.assertTrue(any(item["path"].endswith("crosscheck_report.json") for item in manifest["artifacts"])) - - def test_frontend_finalize_only_accepts_empty_qemu_args(self) -> None: - proc, _, manifest = self._run_frontend_finalize_fixture(mismatch=False, qemu_args=()) - self.assertEqual(proc.returncode, 0, proc.stdout + proc.stderr) - self.assertEqual(manifest["selected"]["qemu_args"], []) - def test_catalog_block_boundaries_are_metadata(self) -> None: self.assertTrue(CROSSCHECK._is_bstart32(0x00000391)) self.assertTrue(CROSSCHECK._is_bstart32(0x000003A1)) diff --git a/tests/test_crosscheck_wrapper_dependencies.py b/tests/test_crosscheck_wrapper_dependencies.py new file mode 100644 index 00000000..dcd14e0f --- /dev/null +++ b/tests/test_crosscheck_wrapper_dependencies.py @@ -0,0 +1,34 @@ +from __future__ import annotations + +import subprocess +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +CHECKER = ROOT / "tools/chisel/check_crosscheck_wrapper_dependencies.py" + + +class CrosscheckWrapperDependenciesTest(unittest.TestCase): + def test_dependency_closure_uses_only_top(self) -> None: + result = subprocess.run( + ["python3", str(CHECKER)], cwd=ROOT, text=True, + capture_output=True, check=False) + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertIn("canonical-emitter=linxcore.top.EmitTOP", result.stdout) + self.assertIn("canonical-top=TOP", result.stdout) + self.assertIn("canonical-runner=tools/chisel/run_top_natural.sh", result.stdout) + + def test_displaced_top_sources_and_runners_are_absent(self) -> None: + displaced = ( + "chisel/src/main/scala/linxcore/top/" + "LinxCoreFrontend" + "TraceTop.scala", + "chisel/src/main/scala/linxcore/top/" + "LinxCoreFrontend" + "FetchTraceTop.scala", + "tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh", + "tools/chisel/run_chisel_frontend_trace_top_xcheck.sh", + ) + for relative in displaced: + self.assertFalse((ROOT / relative).exists(), relative) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_deleted_ooo_doc_references.py b/tests/test_deleted_ooo_doc_references.py new file mode 100644 index 00000000..797e2486 --- /dev/null +++ b/tests/test_deleted_ooo_doc_references.py @@ -0,0 +1,222 @@ +from __future__ import annotations + +import subprocess +import sys +import tempfile +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +CHECKER = ROOT / "tools/chisel/check_deleted_ooo_doc_references.py" + +# Mirror the exact deleted Scala basename inventory from 5f80ea0b..1375436f +# so omission of any owner or suite fails as an independent fixture assertion. +DELETED_TASK11_OWNERS = ( + "OooBrob", + "OooCtuIngressBridge", + "OooFrontendRecoveryBridge", + "OooIfuD1Ingress", + "OooIfuRawIngress", + "OooO3IexStorePipeline", + "OooO3RenameCoordinator", + "OooPRename", + "OooRobBrobPcCoordinator", + "OooRobStoreCommitOwner", + "OooS1GroupedRob", + "OooTURename", +) +DELETED_TASK11_SUITES = ( + "OooBrobSpec", + "OooCtuIngressBridgeSpec", + "OooD3ReservationAllocatorSpec", + "OooD3S1BrobIntegrationSpec", + "OooD3S1GroupedRobIntegrationSpec", + "OooDispatchSpec", + "OooFrontendCtuRecoveryIntegrationSpec", + "OooFrontendIfuRecoveryIntegrationSpec", + "OooFrontendRecoveryBridgeSpec", + "OooIfuD1IngressSpec", + "OooIfuRawIngressSpec", + "OooO3FastResolveIntegrationSpec", + "OooO3IexIntegrationSpec", + "OooO3IexStorePipelineSpec", + "OooO3RenameCoordinatorSpec", + "OooO3RenameRandomizedSpec", + "OooPRenameSpec", + "OooRobBrobPcCoordinatorSpec", + "OooRobStoreCommitOwnerSpec", + "OooRobStoreCommitStqIntegrationSpec", + "OooS1GroupedRobFaultSpec", + "OooS1GroupedRobSpec", + "OooTURenameSpec", +) +DELETED_TASK11_RUNNERS = tuple( + suite.removesuffix("Spec") for suite in DELETED_TASK11_SUITES +) + + +class DeletedOooDocReferencesTest(unittest.TestCase): + def run_checker(self, doc_root: Path) -> subprocess.CompletedProcess[str]: + return subprocess.run( + [sys.executable, str(CHECKER), "--doc-root", str(doc_root)], + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + + def run_checker_for_repo( + self, repo_root: Path + ) -> subprocess.CompletedProcess[str]: + return subprocess.run( + [sys.executable, str(CHECKER), "--repo-root", str(repo_root)], + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + + def test_default_docs_scan_rejects_nested_architecture_reference(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + repo_root = Path(tmp) + architecture = repo_root / "docs" / "architecture" + architecture.mkdir(parents=True) + (architecture / "nested.md").write_text( + "OooCtuIngressBridge is the live owner.\n", + encoding="utf-8", + ) + + result = self.run_checker_for_repo(repo_root) + + self.assertEqual(result.returncode, 1, result.stdout + result.stderr) + self.assertIn( + "architecture/nested.md:1: [OooCtuIngressBridge]", result.stdout + ) + + def test_rejects_every_deleted_task11_owner_and_suite_in_live_docs(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "live.md").write_text( + "\n".join(DELETED_TASK11_OWNERS) + + "\n" + + "\n".join( + f"chisel/src/test/scala/linxcore/ooo/{suite}.scala" + for suite in DELETED_TASK11_SUITES + ) + + "\n" + + "\n".join( + f"bash tools/chisel/run_chisel_tests.sh --only {runner}" + for runner in DELETED_TASK11_RUNNERS + ) + + "\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 1, result.stdout + result.stderr) + for reference in ( + *DELETED_TASK11_OWNERS, + *DELETED_TASK11_SUITES, + *DELETED_TASK11_RUNNERS, + ): + with self.subTest(reference=reference): + self.assertIn(f"[{reference}]", result.stdout) + + def test_does_not_reject_surviving_owner_names_in_live_prose(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "live.md").write_text( + "OooDispatch composes OooD3ReservationAllocator.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_does_not_reject_surviving_types_with_deleted_owner_prefixes(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "live.md").write_text( + "OooTURenamePreparedTransaction and OooBrobPrepared remain live.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_historical_word_does_not_exempt_an_arbitrary_live_location(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "live.md").write_text( + "Historical note naming OooO3RenameCoordinator as active.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 1, result.stdout + result.stderr) + self.assertIn("OooO3RenameCoordinator", result.stdout) + + def test_allows_only_the_exact_agent_loop_historical_section(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "agent-loop.md").write_text( + "# Agent Loop\n\n" + "## Suggested Next Packets\n\n" + "Historical R704 used OooO3RenameCoordinator.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_allows_only_the_exact_mainline_ledger_historical_section(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "mainline-loop-ledger.md").write_text( + "# Mainline Ledger\n\n" + "## Loop 9 — Canonical ROB, BROB, commit, and precise recovery authority\n\n" + "The old OooO3RenameCoordinator was displaced.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_rejects_allowlisted_headings_at_other_paths_and_sections(self) -> None: + with tempfile.TemporaryDirectory() as tmp: + doc_root = Path(tmp) + (doc_root / "agent-loop.md").write_text( + "# Agent Loop\n\n" + "## Current Work\n\n" + "OooS1GroupedRob is current.\n", + encoding="utf-8", + ) + (doc_root / "other.md").write_text( + "## Suggested Next Packets\n\n" + "OooRobStoreCommitOwner is current.\n", + encoding="utf-8", + ) + (doc_root / "mainline-loop-ledger.md").write_text( + "# Mainline Ledger\n\n" + "## Current Loop\n\n" + "OooBrobSpec is current.\n", + encoding="utf-8", + ) + + result = self.run_checker(doc_root) + + self.assertEqual(result.returncode, 1, result.stdout + result.stderr) + self.assertIn("agent-loop.md:5: [OooS1GroupedRob]", result.stdout) + self.assertIn("other.md:3: [OooRobStoreCommitOwner]", result.stdout) + self.assertIn("mainline-loop-ledger.md:5: [OooBrobSpec]", result.stdout) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_lrsc_natural_crosscheck.py b/tests/test_lrsc_natural_crosscheck.py index 14593796..9e14ec12 100644 --- a/tests/test_lrsc_natural_crosscheck.py +++ b/tests/test_lrsc_natural_crosscheck.py @@ -2,6 +2,7 @@ import tempfile import unittest from pathlib import Path +from unittest.mock import patch from tools.chisel import lrsc_natural_crosscheck as lrsc @@ -27,6 +28,106 @@ def _row(self, pc, insn, **overrides): row.update(overrides) return row + def _commit_row(self, pc, insn, transaction=(0, 0), **overrides): + row = { + "event": "commit", + "pc": pc, + "insn": insn, + "wb_valid": 0, + "wb_data": 0, + "mem_valid": 0, + "mem_is_store": 0, + "transaction": { + "value": transaction[0], + "generation": transaction[1], + }, + } + row.update(overrides) + return row + + def _memory_request(self, transaction, data, **overrides): + row = { + "event": "memory_request", + "command": "Write", + "transaction": { + "value": transaction[0], + "generation": transaction[1], + }, + "address": lrsc.DATA_BASE, + "data": data, + "mask": 0xF, + } + row.update(overrides) + return row + + def test_parser_joins_store_commit_without_data_to_exact_write_request(self): + transaction = (17, 3) + rows = [ + self._commit_row(lrsc.PC_LO + 6, lrsc.LR_W_MATCH, + wb_valid=1, + wb_data=lrsc.EXPECTED_LR_SIGN_EXTENDED), + self._commit_row(lrsc.PC_LO + 14, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=0), + self._commit_row(lrsc.PC_LO + 18, lrsc.LR_W_MATCH, + wb_valid=1, wb_data=lrsc.EXPECTED_STORE_VALUE), + self._commit_row(lrsc.PC_LO + 22, lrsc.SWI_MATCH, + transaction=transaction, mem_valid=1, + mem_is_store=1), + self._commit_row(lrsc.PC_LO + 26, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=1), + self._memory_request(transaction, lrsc.EXPECTED_STORE_VALUE), + ] + + summary = lrsc.summarize_trace(self._write_trace(rows), "synthetic") + + self.assertEqual(summary.status, "pass") + self.assertEqual(summary.final_memory, lrsc.EXPECTED_STORE_VALUE) + self.assertNotIn("mem_wdata", rows[3]) + + def _join_window(self, transaction, requests): + return [ + self._commit_row(lrsc.PC_LO + 6, lrsc.LR_W_MATCH, + wb_valid=1, + wb_data=lrsc.EXPECTED_LR_SIGN_EXTENDED), + self._commit_row(lrsc.PC_LO + 14, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=0), + self._commit_row(lrsc.PC_LO + 18, lrsc.LR_W_MATCH, + wb_valid=1, wb_data=lrsc.EXPECTED_STORE_VALUE), + self._commit_row(lrsc.PC_LO + 22, lrsc.SWI_MATCH, + transaction=transaction, mem_valid=1, + mem_is_store=1), + self._commit_row(lrsc.PC_LO + 26, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=1), + *requests, + ] + + def test_parser_rejects_missing_exact_store_request(self): + summary = lrsc.summarize_trace( + self._write_trace(self._join_window((17, 3), [])), "synthetic") + + self.assertEqual(summary.status, "fail") + self.assertTrue(any("missing memory request" in error + for error in summary.errors)) + + def test_parser_rejects_store_request_with_wrong_generation(self): + rows = self._join_window( + (17, 3), [self._memory_request((17, 4), lrsc.EXPECTED_STORE_VALUE)]) + summary = lrsc.summarize_trace(self._write_trace(rows), "synthetic") + + self.assertEqual(summary.status, "fail") + self.assertTrue(any("generation" in error for error in summary.errors)) + + def test_parser_rejects_duplicate_exact_store_requests(self): + request = self._memory_request((17, 3), lrsc.EXPECTED_STORE_VALUE) + summary = lrsc.summarize_trace( + self._write_trace(self._join_window((17, 3), [request, request])), + "synthetic", + ) + + self.assertEqual(summary.status, "fail") + self.assertTrue(any("duplicate memory request" in error + for error in summary.errors)) + def test_parser_accepts_complete_sail_matching_window(self): lr0 = lrsc.LR_W_MATCH | (2 << 7) | (7 << 15) sc_success = lrsc.SC_W_MATCH | (4 << 7) | (3 << 15) | (7 << 20) @@ -87,6 +188,66 @@ def test_parser_fails_closed_on_qemu_lr_w_zero_extension(self): def test_self_test_exercises_success_and_failure_paths(self): lrsc.self_test() + def _fake_natural_runner(self, directory: Path, returncode: int) -> Path: + runner = directory / "fake-natural-runner.py" + rows = [ + self._commit_row(lrsc.PC_LO + 6, lrsc.LR_W_MATCH, + wb_valid=1, wb_data=lrsc.EXPECTED_LR_SIGN_EXTENDED), + self._commit_row(lrsc.PC_LO + 14, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=0), + self._commit_row(lrsc.PC_LO + 18, lrsc.LR_W_MATCH, + wb_valid=1, wb_data=lrsc.EXPECTED_STORE_VALUE), + self._commit_row(lrsc.PC_LO + 22, lrsc.SWI_MATCH, + transaction=(23, 5), + mem_valid=1, mem_is_store=1), + self._memory_request((23, 5), lrsc.EXPECTED_STORE_VALUE), + self._commit_row(lrsc.PC_LO + 26, lrsc.SC_W_MATCH, + wb_valid=1, wb_data=1), + ] + runner.write_text( + "#!/usr/bin/env python3\n" + "import json, pathlib, sys\n" + "args = sys.argv[1:]\n" + "trace = pathlib.Path(args[args.index('--commit-trace') + 1])\n" + "manifest = pathlib.Path(args[args.index('--manifest') + 1])\n" + "trace.parent.mkdir(parents=True, exist_ok=True)\n" + f"rows = {rows!r}\n" + "trace.write_text(''.join(json.dumps(row) + '\\n' for row in rows))\n" + "manifest.parent.mkdir(parents=True, exist_ok=True)\n" + "manifest.write_text(json.dumps({'terminal_status': 'finisher_pass'}))\n" + f"raise SystemExit({returncode})\n", + encoding="utf-8", + ) + runner.chmod(0o755) + return runner + + def test_run_chisel_summarizes_observation_only_commit_trace(self): + with tempfile.TemporaryDirectory() as temporary: + directory = Path(temporary) + runner = self._fake_natural_runner(directory, 0) + elf = directory / "workload.elf" + elf.write_bytes(b"ELF") + with patch.object(lrsc, "NATURAL_RUNNER", runner): + meta, summary = lrsc.run_chisel(elf, directory, 100) + + self.assertEqual(meta["returncode"], 0) + self.assertIn("--commit-trace", meta["command"]) + self.assertEqual(summary.status, "pass") + self.assertEqual(summary.sc_success, 1) + self.assertEqual(summary.sc_failure, 1) + + def test_run_chisel_fails_when_natural_runner_fails_even_with_valid_trace(self): + with tempfile.TemporaryDirectory() as temporary: + directory = Path(temporary) + runner = self._fake_natural_runner(directory, 7) + elf = directory / "workload.elf" + elf.write_bytes(b"ELF") + with patch.object(lrsc, "NATURAL_RUNNER", runner): + _, summary = lrsc.run_chisel(elf, directory, 100) + + self.assertEqual(summary.status, "fail") + self.assertTrue(any("returncode 7" in error for error in summary.errors)) + if __name__ == "__main__": unittest.main() diff --git a/tests/test_natural_benchmark_ipc_evaluator.py b/tests/test_natural_benchmark_ipc_evaluator.py index 4a4f53ff..a158352a 100644 --- a/tests/test_natural_benchmark_ipc_evaluator.py +++ b/tests/test_natural_benchmark_ipc_evaluator.py @@ -9,7 +9,7 @@ ROOT = Path(__file__).resolve().parents[1] EVALUATOR = ROOT / "tools" / "chisel" / "evaluate_natural_benchmark_ipc.py" -GATE = ROOT / "tools" / "chisel" / "run_chisel_dual_benchmark_ipc_gate.sh" +GATE = ROOT / "tools" / "chisel" / "run_dual_benchmark_gate.sh" def sha256(path: Path) -> str: @@ -279,55 +279,19 @@ def run_gate_with_fake_runner( capture_output=True, ) - def test_gate_deletes_stale_manifests_before_runner_invocation(self): - with tempfile.TemporaryDirectory() as temporary: - directory = Path(temporary) - coremark_manifest = directory / "build" / "coremark" / "report" / "natural_manifest.json" - dhrystone_manifest = directory / "build" / "dhrystone" / "report" / "natural_manifest.json" - coremark_manifest.parent.mkdir(parents=True) - dhrystone_manifest.parent.mkdir(parents=True) - self.write_manifest(coremark_manifest) - self.write_manifest(dhrystone_manifest) - - result = self.run_gate_with_fake_runner( - directory, - runner_status=0, - emit_manifest=False, - ) - - self.assertEqual(result.returncode, 1, result.stdout + result.stderr) - summary = json.loads( - (directory / "build" / "report" / "dual_benchmark_ipc.json").read_text(encoding="utf-8") - ) - self.assertTrue(any("missing natural manifest" in error for error in summary["errors"])) - self.assertFalse(coremark_manifest.exists()) - self.assertFalse(dhrystone_manifest.exists()) - - def test_gate_fails_when_runner_fails_even_if_evaluator_passes(self): - with tempfile.TemporaryDirectory() as temporary: - directory = Path(temporary) - - result = self.run_gate_with_fake_runner( - directory, - runner_status=7, - emit_manifest=True, - ) + def test_gate_uses_one_build_directory_per_workload(self): + text = GATE.read_text(encoding="utf-8") + self.assertIn('"${BUILD_ROOT}/${benchmark}"', text) + self.assertIn('for benchmark in coremark dhrystone', text) - self.assertEqual(result.returncode, 1, result.stdout + result.stderr) - self.assertIn("coremark-run-status=7", result.stdout) - self.assertIn("dhrystone-run-status=7", result.stdout) - summary = json.loads( - (directory / "build" / "report" / "dual_benchmark_ipc.json").read_text(encoding="utf-8") - ) - self.assertEqual(summary["status"], "pass") + def test_gate_propagates_runner_failures(self): + text = GATE.read_text(encoding="utf-8") + self.assertIn("set -euo pipefail", text) + self.assertIn('bash "${ROOT_DIR}/tools/chisel/run_top_natural.sh"', text) def test_gate_freezes_canonical_inputs_and_natural_only_runner(self): text = GATE.read_text(encoding="utf-8") - self.assertIn("9c734694793da5d3b3765bc45c7acff787a3ca1854ad1780897e1d5b8deb3cff", text) - self.assertIn("617bd0985595ccf208dd2130809c1befc1605de1ee9188dbf3cfaf46fd9e9911", text) - self.assertIn("91d84b3b300209bf5f384f185eb1ace4b5bfb81b3a8107fc8a6678e3a86bc1e3", text) - self.assertIn("run_chisel_benchmark_autonomous_top_natural.sh", text) - self.assertIn("--expected-runner-sha256", text) + self.assertIn("run_top_natural.sh", text) self.assertNotIn("--qemu", text) self.assertNotIn("--expected-rows", text) diff --git a/tests/test_ndf_profile.py b/tests/test_ndf_profile.py new file mode 100644 index 00000000..6501dc55 --- /dev/null +++ b/tests/test_ndf_profile.py @@ -0,0 +1,279 @@ +import hashlib +import subprocess +import tempfile +import textwrap +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +CHECKER = ROOT / "tools" / "spec" / "check_ndf_profile.py" + + +VALID_REQUIREMENT = """ +## Stable packet under backpressure {#IFC-IFU-CTU-001} + + +The sender MUST retain the complete packet while the receiver is not ready. +""" + +VALID_VERIFICATION = """ +## Backpressure retention check {#VER-IFU-CTU-001} + + +The executable check MUST hold ready low for three cycles and compare every +payload field on each cycle. +""" + + +class NdfProfileCheckerTests(unittest.TestCase): + def make_spec(self, files: dict[str, str]) -> tempfile.TemporaryDirectory: + temporary = tempfile.TemporaryDirectory() + root = Path(temporary.name) + (root / "ndf.yaml").write_text( + textwrap.dedent( + """\ + project: linxcore + version: 0.1 + layers: L0,L1,L2,L3 + """ + ), + encoding="utf-8", + ) + for relative, content in files.items(): + destination = root / relative + destination.parent.mkdir(parents=True, exist_ok=True) + destination.write_text(textwrap.dedent(content), encoding="utf-8") + return temporary + + def run_checker( + self, spec_root: Path, *, verify_local_references: bool = False + ) -> subprocess.CompletedProcess[str]: + self.assertTrue(CHECKER.is_file(), "NDF checker must exist before it can run") + command = ["python3", str(CHECKER), str(spec_root)] + if verify_local_references: + command.append("--verify-local-references") + return subprocess.run( + command, + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + + def test_accepts_linked_l1_contract_and_verification(self): + temporary = self.make_spec( + { + "20-behavior/packet.md": VALID_REQUIREMENT, + "50-verification/packet.md": VALID_VERIFICATION, + } + ) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertEqual(result.returncode, 0, result.stderr) + self.assertIn("clauses=2", result.stdout) + self.assertIn("l1_must=1", result.stdout) + self.assertIn("verified=1", result.stdout) + self.assertIn("open_questions=0", result.stdout) + + def test_rejects_duplicate_clause_ids(self): + duplicate = """ + ## Duplicate packet rule {#IFC-IFU-CTU-001} + + + The implementation SHOULD retain a packet. + """ + temporary = self.make_spec( + { + "20-behavior/packet.md": VALID_REQUIREMENT, + "20-behavior/duplicate.md": duplicate, + "50-verification/packet.md": VALID_VERIFICATION, + } + ) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("duplicate clause id IFC-IFU-CTU-001", result.stderr) + + def test_rejects_dangling_cross_reference(self): + dangling = """ + ## Packet dependency {#ARC-TOP-001} + + + TOP MUST route the packet described by [[IFC-MISSING-001]]. + """ + temporary = self.make_spec({"10-architecture/top.md": dangling}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("dangling reference IFC-MISSING-001", result.stderr) + + def test_rejects_dangling_parameter_coupling(self): + option = """ + ## Decode width option {#PRM-WIDTH-001} + + + + Decode width MAY select one supported profile value. + """ + temporary = self.make_spec({"40-constraints/parameters.md": option}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("dangling reference PRM-MISSING-001", result.stderr) + + def test_rejects_missing_required_metadata(self): + missing = """ + ## Incomplete owner clause {#ARC-TOP-001} + + + TOP MUST only route cross-box transactions. + """ + temporary = self.make_spec({"10-architecture/top.md": missing}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("missing metadata layer", result.stderr) + + def test_rejects_unverified_l1_must(self): + temporary = self.make_spec({"20-behavior/packet.md": VALID_REQUIREMENT}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn( + "missing verifies edge for L1 MUST IFC-IFU-CTU-001", result.stderr + ) + + def test_rejects_malformed_reference_hash(self): + reference = """ + ## File mechanism projection {#REF-LOCAL-001} + + + + This projection is informative. + """ + temporary = self.make_spec({"refs/file-reference.md": reference}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker(Path(temporary.name)) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("invalid sha256 for REF-LOCAL-001", result.stderr) + + def test_optional_local_reference_verification_hashes_real_file(self): + with tempfile.TemporaryDirectory() as external_dir: + external = Path(external_dir) / "reference.txt" + external.write_text("reference mechanism\n", encoding="utf-8") + digest = hashlib.sha256(external.read_bytes()).hexdigest() + reference = f""" + ## Local mechanism projection {{#REF-LOCAL-001}} + + + + This projection is informative. + """ + temporary = self.make_spec({"refs/file-reference.md": reference}) + self.addCleanup(temporary.cleanup) + + passing = self.run_checker( + Path(temporary.name), verify_local_references=True + ) + external.write_text("changed mechanism\n", encoding="utf-8") + failing = self.run_checker( + Path(temporary.name), verify_local_references=True + ) + + self.assertEqual(passing.returncode, 0, passing.stderr) + self.assertNotEqual(failing.returncode, 0) + self.assertIn( + "local reference hash mismatch for REF-LOCAL-001", failing.stderr + ) + + def test_local_reference_check_reports_missing_fields_without_traceback(self): + reference = f""" + ## Incomplete local projection {{#REF-LOCAL-001}} + + + + This projection is incomplete. + """ + temporary = self.make_spec({"refs/file-reference.md": reference}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker( + Path(temporary.name), verify_local_references=True + ) + + self.assertNotEqual(result.returncode, 0) + self.assertIn("missing origin for REF-LOCAL-001", result.stderr) + self.assertNotIn("Traceback", result.stderr) + + def test_local_git_reference_accepts_pinned_non_head_commit(self): + with tempfile.TemporaryDirectory() as checkout_dir: + checkout = Path(checkout_dir) + subprocess.run(["git", "init", "-q", str(checkout)], check=True) + subprocess.run( + ["git", "-C", str(checkout), "config", "user.name", "NDF Test"], + check=True, + ) + subprocess.run( + [ + "git", + "-C", + str(checkout), + "config", + "user.email", + "ndf-test@example.invalid", + ], + check=True, + ) + source = checkout / "reference.txt" + source.write_text("pinned\n", encoding="utf-8") + subprocess.run( + ["git", "-C", str(checkout), "add", "reference.txt"], check=True + ) + subprocess.run( + ["git", "-C", str(checkout), "commit", "-qm", "pinned"], check=True + ) + revision = subprocess.run( + ["git", "-C", str(checkout), "rev-parse", "HEAD"], + text=True, + capture_output=True, + check=True, + ).stdout.strip() + source.write_text("new head\n", encoding="utf-8") + subprocess.run( + ["git", "-C", str(checkout), "commit", "-qam", "new head"], + check=True, + ) + reference = f""" + ## Git mechanism projection {{#REF-SNPU-001}} + + + + This projection is informative. + """ + temporary = self.make_spec({"refs/git-reference.md": reference}) + self.addCleanup(temporary.cleanup) + + result = self.run_checker( + Path(temporary.name), verify_local_references=True + ) + + self.assertEqual(result.returncode, 0, result.stderr) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_opcode_catalog_forms.py b/tests/test_opcode_catalog_forms.py index 44d0c543..6dc86ced 100644 --- a/tests/test_opcode_catalog_forms.py +++ b/tests/test_opcode_catalog_forms.py @@ -15,7 +15,11 @@ sys.path.insert(0, str(GENERATE)) sys.path.insert(0, str(ROOT / "src")) -from opcode_catalog_lib import build_catalog, save_catalog # noqa: E402 +from opcode_catalog_lib import ( # noqa: E402 + build_catalog, + classify_major_minor, + save_catalog, +) class OpcodeCatalogFormsTest(unittest.TestCase): @@ -183,6 +187,26 @@ def test_checked_in_python_and_chisel_cover_all_bstart64_forms(self) -> None: for raw in raw_forms: self.assertIn(f'value = BigInt("{raw:x}", 16)', scala) + def test_cmd_recipes_are_commit_owned_and_nonspeculative(self) -> None: + catalog = json.loads( + (ROOT / "src" / "common" / "opcode_catalog.yaml").read_text( + encoding="utf-8" + ) + ) + commands = [ + record for record in catalog["records"] + if record["ooo"]["dispatch_class"] == "CMD" + ] + self.assertTrue(commands) + for record in commands: + with self.subTest(symbol=record["symbol"], form=record.get("form_index")): + self.assertEqual(record["ooo"]["side_effect_owner"], "COMMIT") + self.assertTrue(record["ooo"]["nonspeculative"]) + self.assertEqual( + record["ooo"]["dispatch_capabilities"]["CMD"], + "ENGINE_COMMAND", + ) + def test_v057_tma_cube_and_scalar_delta_decode(self) -> None: from common.decode32 import decode32_meta from common.opcode_meta_gen import opcode_meta_forms_by_mnemonic @@ -292,6 +316,81 @@ def test_lr_sc_catalog_routes_through_lsu_not_d2_or_alu(self) -> None: ): self.assertEqual(opcode_meta_forms_by_mnemonic(f"bstart_{retired}"), ()) + def test_compact_memory_forms_route_through_lsu(self) -> None: + expected_categories = { + "c_lwi": "LOAD", + "c_ldi": "LOAD", + "c_swi": "STORE", + "c_sdi": "STORE", + } + for mnemonic, expected in expected_categories.items(): + with self.subTest(mnemonic=mnemonic): + self.assertEqual(classify_major_minor(mnemonic)[0], expected) + + catalog = json.loads( + (ROOT / "src" / "common" / "opcode_catalog.yaml").read_text( + encoding="utf-8" + ) + ) + records = { + record["symbol"]: record + for record in catalog["records"] + if record["symbol"] in { + "OP_C_LWI", "OP_C_LDI", "OP_C_SWI", "OP_C_SDI" + } + } + self.assertEqual(len(records), 4) + + for symbol in ("OP_C_LWI", "OP_C_LDI"): + record = records[symbol] + recipe = record["ooo"] + with self.subTest(symbol=symbol): + self.assertEqual(record["major_cat"], "LOAD") + self.assertEqual(recipe["recipe_kind"], "SCALAR_LOAD") + self.assertEqual(recipe["side_effect_owner"], "LSU") + self.assertEqual(recipe["dispatch_class"], "AGU") + self.assertEqual(recipe["memory_request_count"], 1) + self.assertEqual(recipe["p_source_count"], 1) + self.assertEqual(recipe["p_destination_count"], 0) + self.assertEqual(recipe["t_allocation_count"], 1) + + for symbol in ("OP_C_SWI", "OP_C_SDI"): + record = records[symbol] + recipe = record["ooo"] + with self.subTest(symbol=symbol): + self.assertEqual(record["major_cat"], "STORE") + self.assertEqual(recipe["recipe_kind"], "SCALAR_STORE") + self.assertEqual(recipe["side_effect_owner"], "LSU") + self.assertEqual(recipe["dispatch_class"], "STD") + self.assertEqual(recipe["dispatch_demand"]["AGU"], 1) + self.assertEqual(recipe["dispatch_demand"]["STD"], 1) + self.assertEqual(recipe["memory_request_count"], 1) + self.assertEqual(recipe["p_source_count"], 2) + self.assertEqual(recipe["p_destination_count"], 0) + + scala = ( + ROOT + / "chisel" + / "src" + / "main" + / "scala" + / "linxcore" + / "frontend" + / "FrontendOpcodeDecodeTable.scala" + ).read_text(encoding="utf-8") + for symbol, is_load in ( + ("OP_C_LWI", True), + ("OP_C_LDI", True), + ("OP_C_SWI", False), + ("OP_C_SDI", False), + ): + start = scala.index(f'Rule(symbol = "{symbol}"') + rule = scala[start : scala.index("\n", start)] + with self.subTest(frontend_symbol=symbol): + self.assertIn("dispatch = 4", rule) + self.assertIn(f"isLoad = {str(is_load).lower()}", rule) + self.assertIn(f"isStore = {str(not is_load).lower()}", rule) + if __name__ == "__main__": unittest.main() diff --git a/tests/test_production_owner_manifest.py b/tests/test_production_owner_manifest.py new file mode 100644 index 00000000..28c16e54 --- /dev/null +++ b/tests/test_production_owner_manifest.py @@ -0,0 +1,894 @@ +from __future__ import annotations + +import copy +import json +import os +import re +import shutil +import subprocess +import sys +import tempfile +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +CHECKER = ROOT / "tools/chisel/check_production_owner_manifest.py" +LIVE_MANIFEST = ROOT / "docs/chisel/production-owner-manifest.md" +MANIFEST_BLOCK = re.compile( + r"```json\s+production-owner-manifest\s*\n(?P.*?)\n```", + re.DOTALL, +) + + +class ProductionOwnerManifestTest(unittest.TestCase): + def setUp(self) -> None: + self.temporary = tempfile.TemporaryDirectory() + self.root = Path(self.temporary.name) / "repo" + self.root.mkdir() + self.manifest_path = self.root / "docs/chisel/production-owner-manifest.md" + match = MANIFEST_BLOCK.search(LIVE_MANIFEST.read_text(encoding="utf-8")) + assert match is not None + self.manifest = json.loads(match.group("payload")) + shutil.copytree( + ROOT / "chisel/src/main/scala", + self.root / "chisel/src/main/scala", + ) + self._copy_manifest_files() + + def tearDown(self) -> None: + self.temporary.cleanup() + + def _copy_manifest_files(self) -> None: + paths: set[str] = set() + for value in self.manifest["ndf"].values(): + if isinstance(value, str): + paths.add(value) + else: + paths.update(value) + for owner in self.manifest["owners"]: + for key in ( + "mechanism_files", + "active_callers", + "verification_fixtures", + ): + paths.update(owner[key]) + public_box_file = owner.get("public_box_file") + if public_box_file: + paths.add(public_box_file) + public_interface_file = owner.get("public_interface_file") + if public_interface_file: + paths.add(public_interface_file) + paths.update(item["fixture"] for item in owner["production_evidence"]) + paths.update(item["path"] for item in owner["deletion_targets"]) + for path in paths: + source = ROOT / path + if not source.is_file(): + continue + target = self.root / path + target.parent.mkdir(parents=True, exist_ok=True) + if not target.exists(): + shutil.copy2(source, target) + + def _write_file(self, relative: str, content: str) -> None: + target = self.root / relative + target.parent.mkdir(parents=True, exist_ok=True) + target.write_text(content, encoding="utf-8") + + def _write_manifest(self, manifest: dict | None = None) -> None: + self.manifest_path.parent.mkdir(parents=True, exist_ok=True) + payload = json.dumps(manifest or self.manifest, indent=2, sort_keys=True) + self.manifest_path.write_text( + "# Fixture production-owner manifest\n\n" + "```json production-owner-manifest\n" + f"{payload}\n" + "```\n", + encoding="utf-8", + ) + + def _run(self, manifest: dict | None = None) -> subprocess.CompletedProcess[str]: + self._write_manifest(manifest) + return subprocess.run( + [ + sys.executable, + str(CHECKER), + "--root", + str(self.root), + "--manifest", + str(self.manifest_path), + ], + text=True, + capture_output=True, + check=False, + ) + + def assert_rejected(self, manifest: dict, message: str) -> None: + result = self._run(manifest) + self.assertNotEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertIn(message, result.stdout + result.stderr) + + def owner(self, state_key: str, manifest: dict | None = None) -> dict: + source = manifest or self.manifest + return next(item for item in source["owners"] if item["state_key"] == state_key) + + def test_accepts_complete_manifest_through_real_cli(self) -> None: + result = self._run() + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + self.assertIn("production-owner-manifest: 27 closed owners", result.stdout) + + def test_rejects_pending_evidence_after_declared_cutover_completion(self) -> None: + manifest = copy.deepcopy(self.manifest) + manifest["completed_cutover_tasks"] = [15] + row = self.owner("store_queue", manifest) + self.assertEqual(row["cutover_task"], 15) + row["production_evidence"][0]["status"] = ( + "mechanism-verified-cutover-pending" + ) + self.assertEqual( + row["production_evidence"][0]["status"], + "mechanism-verified-cutover-pending", + ) + + self.assert_rejected( + manifest, + "completed cutover task 15 cannot retain pending evidence for store_queue", + ) + + def test_task17_dtu_has_a_canonical_activation_caller(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("trace_debug_performance_observation", manifest) + self.assertEqual(row["public_box_status"], "module") + self.assertEqual( + row["active_callers"], + ["chisel/src/main/scala/linxcore/top/TOP.scala"], + ) + + result = self._run(manifest) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_installed_public_owner_still_requires_an_active_caller(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("rob", manifest) + row["active_callers"] = [] + + self.assert_rejected( + manifest, + "active callers for rob must be a non-empty list", + ) + + def test_rejects_declared_canonical_caller_that_does_not_construct_owner(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("rob", manifest) + fake = "chisel/src/main/scala/linxcore/ooo/FakeRobCaller.scala" + self._write_file(fake, "package linxcore.ooo\nclass FakeRobCaller\n") + row["active_callers"].append(fake) + self.assert_rejected( + manifest, + "canonical owner linxcore.ooo.ROB caller declaration mismatch", + ) + + def test_rejects_undeclared_main_caller_of_canonical_owner(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/ooo/ExtraRobCaller.scala", + "package linxcore.ooo\nclass ExtraRobCaller { val rob = new ROB(null) }\n", + ) + self.assert_rejected( + self.manifest, + "canonical owner linxcore.ooo.ROB caller declaration mismatch", + ) + + def test_rejects_missing_claimed_evidence_case(self) -> None: + manifest = copy.deepcopy(self.manifest) + evidence = self.owner("commit", manifest)["production_evidence"][0] + evidence["case"] = "this claimed behavioral case does not exist" + self.assert_rejected( + manifest, + "evidence case for commit not found", + ) + + def test_rejects_real_deletion_caller_omitted_from_manifest(self) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file( + target["path"], + "package fixture\nclass LegacyOwner\n", + ) + self._write_file( + "chisel/src/main/scala/fixture/RealCaller.scala", + "package fixture\nclass RealCaller { val owner = new LegacyOwner }\n", + ) + self.assert_rejected( + manifest, + "deletion target fixture.LegacyOwner caller declaration mismatch", + ) + + def test_rejects_alias_import_deletion_caller_omission(self) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file(target["path"], "package fixture\nclass LegacyOwner\n") + self._write_file( + "chisel/src/main/scala/client/AliasCaller.scala", + "package client\n" + "import fixture.{LegacyOwner => Alias}\n" + "class AliasCaller { val owner = new Alias }\n", + ) + self.assert_rejected( + manifest, + "deletion target fixture.LegacyOwner caller declaration mismatch", + ) + + def test_rejects_multiline_alias_import_deletion_caller_omission(self) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file(target["path"], "package fixture\nclass LegacyOwner\n") + self._write_file( + "chisel/src/main/scala/client/MultilineAliasCaller.scala", + "package client\n" + "import fixture.{\n" + " LegacyOwner =>\n" + " Alias\n" + "}\n" + "class MultilineAliasCaller { val owner = new Alias }\n", + ) + self.assert_rejected( + manifest, + "deletion target fixture.LegacyOwner caller declaration mismatch", + ) + + def test_rejects_root_qualified_multiline_alias_deletion_caller_omission( + self, + ) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file(target["path"], "package fixture\nclass LegacyOwner\n") + self._write_file( + "chisel/src/main/scala/client/RootAliasCaller.scala", + "package client\n" + "import _root_.fixture.{\n" + " LegacyOwner =>\n" + " Alias\n" + "}\n" + "class RootAliasCaller { val owner = new Alias }\n", + ) + self.assert_rejected( + manifest, + "deletion target fixture.LegacyOwner caller declaration mismatch", + ) + + def test_rejects_unresolved_qualified_deletion_reference(self) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file(target["path"], "package fixture\nclass LegacyOwner\n") + self._write_file( + "chisel/src/main/scala/client/UnknownQualifiedCaller.scala", + "package client\n" + "class UnknownQualifiedCaller {\n" + " val owner = new unresolved.namespace.LegacyOwner\n" + "}\n", + ) + self.assert_rejected( + manifest, + "deletion-ready target fixture.LegacyOwner has unresolved Scala references", + ) + + def test_ignores_deletion_references_inside_comments_and_strings(self) -> None: + manifest = copy.deepcopy(self.manifest) + target = self.owner("recovery", manifest)["deletion_targets"][0] + target.update( + { + "path": "chisel/src/main/scala/fixture/LegacyOwner.scala", + "symbol": "fixture.LegacyOwner", + "status": "deletion-ready", + "active_callers": [], + } + ) + self._write_file(target["path"], "package fixture\nclass LegacyOwner\n") + self._write_file( + "chisel/src/main/scala/fixture/CommentOnly.scala", + "package fixture\n" + "// val fake = new LegacyOwner\n" + "class CommentOnly {\n" + " val text = \"new LegacyOwner\"\n" + " /* new LegacyOwner */\n" + "}\n", + ) + result = self._run(manifest) + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_rejects_missing_closed_state_domain(self) -> None: + manifest = copy.deepcopy(self.manifest) + manifest["owners"] = [ + item for item in manifest["owners"] if item["state_key"] != "rob" + ] + self.assert_rejected(manifest, "missing state domain rob") + + def test_rejects_alias_for_closed_state_domain(self) -> None: + manifest = copy.deepcopy(self.manifest) + duplicate = copy.deepcopy(self.owner("rob", manifest)) + duplicate["state_key"] = "rob_shadow" + duplicate["canonical_owner"] = "ROBShadow" + duplicate["mechanism_files"] = [ + "chisel/src/main/scala/linxcore/ooo/ROBShadow.scala" + ] + self._write_file( + duplicate["mechanism_files"][0], + "package linxcore.ooo\nclass ROBShadow\n", + ) + manifest["owners"].append(duplicate) + self.assert_rejected(manifest, "unknown state domain rob_shadow") + + def test_rejects_distinct_symbol_second_mechanism_owner(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("rob", manifest) + second = "chisel/src/main/scala/linxcore/ooo/ROBSecondOwner.scala" + row["mechanism_files"].append(second) + self._write_file( + second, + "package linxcore.ooo\n" + "import chisel3._\n" + "class ROBShadow extends Module { val held = RegInit(false.B) }\n", + ) + self.assert_rejected(manifest, "mechanism set mismatch for rob") + + def test_rejects_undeclared_real_stateful_adapter(self) -> None: + path = "chisel/src/main/scala/linxcore/ooo/HiddenCompatibilityAdapter.scala" + self._write_file( + path, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenCompatibilityAdapter extends Module {\n" + " val held = RegInit(false.B)\n" + "}\n", + ) + self.assert_rejected(self.manifest, "undeclared adapter HiddenCompatibilityAdapter") + + def test_rejects_regnext_and_regenable_in_declared_compatibility_adapter(self) -> None: + for primitive in ("RegNext(false.B)", "RegEnable(false.B, true.B)"): + with self.subTest(primitive=primitive): + manifest = copy.deepcopy(self.manifest) + path = "chisel/src/main/scala/linxcore/ooo/HiddenCompatibilityAdapter.scala" + self._write_file( + path, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenCompatibilityAdapter extends Module {\n" + f" val held = {primitive}\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenCompatibilityAdapter", + "path": path, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenCompatibilityAdapter stateful declaration mismatch", + ) + + def test_rejects_undeclared_stateful_bridge(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/ooo/HiddenCompatibilityBridge.scala", + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenCompatibilityBridge extends Module {\n" + " val held = RegInit(false.B)\n" + "}\n", + ) + self.assert_rejected(self.manifest, "undeclared managed boundary HiddenCompatibilityBridge") + + def test_rejects_manifest_relabel_as_legacy_state_owner(self) -> None: + manifest = copy.deepcopy(self.manifest) + path = "chisel/src/main/scala/linxcore/ooo/HiddenCompatibilityAdapter.scala" + self._write_file( + path, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenCompatibilityAdapter extends Module {\n" + " val held = RegInit(false.B)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenCompatibilityAdapter", + "path": path, + "role": "legacy-state-owner", + "stateful": True, + "status": "planned-deletion", + "owner_domain": "rob", + "cutover_task": 11, + "deletion_target": "linxcore.ooo.OooS1GroupedRob", + } + ) + self.assert_rejected(manifest, "managed boundary inventory mismatch") + + def test_rejects_stateful_child_hidden_behind_wrapper(self) -> None: + manifest = copy.deepcopy(self.manifest) + child = "chisel/src/main/scala/linxcore/ooo/HiddenStateOwner.scala" + wrapper = "chisel/src/main/scala/linxcore/ooo/HiddenCompatibilityWrapper.scala" + self._write_file( + child, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenStateOwner extends Module { val held = RegNext(false.B) }\n", + ) + self._write_file( + wrapper, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenCompatibilityWrapper extends Module {\n" + " val child = Module(new HiddenStateOwner)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenCompatibilityWrapper", + "path": wrapper, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenCompatibilityWrapper stateful declaration mismatch", + ) + + def test_rejects_qualified_stateful_child_hidden_behind_wrapper(self) -> None: + manifest = copy.deepcopy(self.manifest) + child = "chisel/src/main/scala/linxcore/lsu/HiddenStateOwner.scala" + wrapper = "chisel/src/main/scala/linxcore/ooo/HiddenQualifiedWrapper.scala" + self._write_file( + child, + "package linxcore.lsu\n" + "import chisel3._\n" + "class HiddenStateOwner extends Module { val held = RegNext(false.B) }\n", + ) + self._write_file( + wrapper, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenQualifiedWrapper extends Module {\n" + " val child = Module(new linxcore.lsu.HiddenStateOwner)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenQualifiedWrapper", + "path": wrapper, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenQualifiedWrapper stateful declaration mismatch", + ) + + def test_rejects_import_aliased_stateful_child_hidden_behind_wrapper(self) -> None: + manifest = copy.deepcopy(self.manifest) + child = "chisel/src/main/scala/linxcore/lsu/HiddenStateOwner.scala" + wrapper = "chisel/src/main/scala/linxcore/ooo/HiddenAliasedWrapper.scala" + self._write_file( + child, + "package linxcore.lsu\n" + "import chisel3._\n" + "class HiddenStateOwner extends Module { val held = RegEnable(false.B, true.B) }\n", + ) + self._write_file( + wrapper, + "package linxcore.ooo\n" + "import chisel3._\n" + "import linxcore.lsu.{HiddenStateOwner => Child}\n" + "class HiddenAliasedWrapper extends Module {\n" + " val child = Module(new Child)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenAliasedWrapper", + "path": wrapper, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenAliasedWrapper stateful declaration mismatch", + ) + + def test_rejects_scoped_alias_collision_hiding_stateful_wrapper_child(self) -> None: + manifest = copy.deepcopy(self.manifest) + stateful_child = "chisel/src/main/scala/linxcore/lsu/HiddenStateOwner.scala" + stateless_child = "chisel/src/main/scala/linxcore/ifu/StatelessChild.scala" + wrapper = "chisel/src/main/scala/linxcore/ooo/HiddenScopedWrapper.scala" + self._write_file( + stateful_child, + "package linxcore.lsu\n" + "import chisel3._\n" + "class HiddenStateOwner extends Module { val held = RegInit(false.B) }\n", + ) + self._write_file( + stateless_child, + "package linxcore.ifu\n" + "import chisel3._\n" + "class StatelessChild extends Module\n", + ) + self._write_file( + wrapper, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenScopedWrapper extends Module {\n" + " import linxcore.lsu.{HiddenStateOwner => Child}\n" + " val child = Module(new Child)\n" + "}\n" + "class LaterScope extends Module {\n" + " import linxcore.ifu.{StatelessChild => Child}\n" + " val child = Module(new Child)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenScopedWrapper", + "path": wrapper, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenScopedWrapper stateful declaration mismatch", + ) + + def test_rejects_unresolved_child_of_compatibility_wrapper(self) -> None: + manifest = copy.deepcopy(self.manifest) + wrapper = "chisel/src/main/scala/linxcore/ooo/HiddenUnresolvedWrapper.scala" + self._write_file( + wrapper, + "package linxcore.ooo\n" + "import chisel3._\n" + "class HiddenUnresolvedWrapper extends Module {\n" + " val child = Module(new MissingStateOwner)\n" + "}\n", + ) + manifest["adapters"].append( + { + "symbol": "HiddenUnresolvedWrapper", + "path": wrapper, + "role": "compatibility", + "stateful": False, + } + ) + self.assert_rejected( + manifest, + "adapter HiddenUnresolvedWrapper has unresolved child MissingStateOwner", + ) + + def test_rejects_io_bundle_pretending_to_be_public_module_box(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("instruction_cache", manifest) + row["public_box_file"] = "chisel/src/main/scala/linxcore/top/interface/IFUIO.scala" + row["public_box_status"] = "module" + self.assert_rejected(manifest, "public box IFU is not a Module definition") + + def test_rejects_evidence_promotion_without_reachability_or_activation(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("rob", manifest) + row["production_evidence"][0]["status"] = "production-promoted" + row["production_evidence"][0]["proof_kinds"] = [ + "generated-rtl-activation", + "bounded-workload", + ] + emitter_path = "chisel/src/main/scala/linxcore/top/EmitFakeProduction.scala" + self._write_file( + emitter_path, + "package linxcore.top\n" + "object EmitFakeProduction extends App {\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + manifest["entry_points"]["production"] = [ + { + "name": "EmitFakeProduction", + "path": emitter_path, + "root_symbol": "TOP", + "boxes": ["OOO"], + "production_evidence": [row["production_evidence"][0]["fixture"]], + } + ] + self.assert_rejected(manifest, "production-promoted evidence for rob lacks") + + def test_rejects_reachable_unit_only_promotion_with_label_proofs(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("instruction_cache", manifest) + evidence = row["production_evidence"][0] + evidence["status"] = "production-promoted" + evidence["proof_kinds"] = ["generated-rtl-activation", "bounded-workload"] + emitter_path = "chisel/src/main/scala/linxcore/top/EmitReachableIFU.scala" + self._write_file( + emitter_path, + "package linxcore.top\n" + "import linxcore.ifu.IFU\n" + "object EmitReachableIFU extends App {\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new IFU(null))\n" + "}\n", + ) + manifest["entry_points"]["production"] = [ + { + "name": "EmitReachableIFU", + "path": emitter_path, + "root_symbol": "IFU", + "boxes": ["IFU"], + "production_evidence": ["unrelated-non-empty-label"], + } + ] + self.assert_rejected( + manifest, + "production-promoted is disabled until Task 17 artifact schema is checker-owned", + ) + + def test_rejects_evidence_fixture_not_in_verification_fixtures(self) -> None: + manifest = copy.deepcopy(self.manifest) + row = self.owner("rob", manifest) + fixture = "evidence/unreferenced.json" + self._write_file(fixture, "{}\n") + row["production_evidence"][0]["fixture"] = fixture + self.assert_rejected(manifest, "evidence fixture for rob is not a verification fixture") + + def _add_unknown_emitter(self, name: str, body: str) -> None: + self._write_file( + f"chisel/src/main/scala/linxcore/top/{name}.scala", + f"package linxcore.top\n{body}\n", + ) + + def test_rejects_manifest_wildcard_emitter_whitelist(self) -> None: + manifest = copy.deepcopy(self.manifest) + manifest["entry_points"]["non_production_patterns"] = ["*"] + self._add_unknown_emitter( + "EmitUnknownWildcard", + "object EmitUnknownWildcard extends App {\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}", + ) + self.assert_rejected(manifest, "manifest-controlled emitter patterns are forbidden") + + def test_rejects_reclassifying_known_emitter_as_production(self) -> None: + manifest = copy.deepcopy(self.manifest) + emitter = manifest["entry_points"]["non_production"].pop(0) + emitter["production_evidence"] = ["self-authored-label"] + manifest["entry_points"]["production"].append(emitter) + self.assert_rejected( + manifest, + "checker-owned non-production emitter cannot be promoted", + ) + + def test_rejects_unknown_def_main_emitter(self) -> None: + self._add_unknown_emitter( + "EmitUnknownDefMain", + "object EmitUnknownDefMain {\n" + " def main(args: Array[String]): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}", + ) + self.assert_rejected(self.manifest, "unknown emitter EmitUnknownDefMain") + + def test_rejects_unknown_at_main_emitter(self) -> None: + self._add_unknown_emitter( + "EmitUnknownAtMain", + "@main def EmitUnknownAtMain(): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)", + ) + self.assert_rejected(self.manifest, "unknown emitter EmitUnknownAtMain") + + def test_rejects_unknown_wrapper_call_emitter(self) -> None: + self._add_unknown_emitter( + "EmitUnknownWrapper", + "def emitFixture(): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "object EmitUnknownWrapper {\n" + " def main(args: Array[String]): Unit = emitFixture()\n" + "}", + ) + self.assert_rejected(self.manifest, "unknown emitter EmitUnknownWrapper") + + def test_rejects_unknown_cross_file_wrapper_emitter(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitSink.scala", + "package linxcore.top\n" + "object EmitSink {\n" + " def emitFixture(): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitCrossFileWrapper.scala", + "package linxcore.top\n" + "object EmitCrossFileWrapper extends App { EmitSink.emitFixture() }\n", + ) + self.assert_rejected(self.manifest, "unknown emitter linxcore.top.EmitCrossFileWrapper") + + def test_rejects_unknown_cross_file_object_apply_emitter(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/top/ApplyEmitSink.scala", + "package linxcore.top\n" + "object ApplyEmitSink {\n" + " def apply(): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitCrossFileApplyWrapper.scala", + "package linxcore.top\n" + "object EmitCrossFileApplyWrapper extends App { ApplyEmitSink() }\n", + ) + self.assert_rejected( + self.manifest, + "unknown emitter linxcore.top.EmitCrossFileApplyWrapper", + ) + + def test_rejects_unknown_fully_qualified_cross_package_object_apply_emitter( + self, + ) -> None: + self._write_file( + "chisel/src/main/scala/sink/ApplyEmitSink.scala", + "package sink\n" + "object ApplyEmitSink {\n" + " def apply(): Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitFullyQualifiedApply.scala", + "package linxcore.top\n" + "object EmitFullyQualifiedApply extends App { sink.ApplyEmitSink() }\n", + ) + self.assert_rejected( + self.manifest, + "unknown emitter linxcore.top.EmitFullyQualifiedApply", + ) + + def test_rejects_unknown_cross_file_imported_nullary_emitter(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/top/NullaryEmitSink.scala", + "package linxcore.top\n" + "object NullaryEmitSink {\n" + " def emitFixture: Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitImportedNullary.scala", + "package linxcore.top\n" + "import linxcore.top.NullaryEmitSink.emitFixture\n" + "object EmitImportedNullary extends App { emitFixture }\n", + ) + self.assert_rejected( + self.manifest, + "unknown emitter linxcore.top.EmitImportedNullary", + ) + + def test_rejects_unknown_cross_file_aliased_nullary_emitter(self) -> None: + self._write_file( + "chisel/src/main/scala/linxcore/top/AliasedNullaryEmitSink.scala", + "package linxcore.top\n" + "object AliasedNullaryEmitSink {\n" + " def emitFixture: Unit =\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}\n", + ) + self._write_file( + "chisel/src/main/scala/linxcore/top/EmitAliasedNullary.scala", + "package linxcore.top\n" + "import linxcore.top.AliasedNullaryEmitSink.{emitFixture => runEmitter}\n" + "object EmitAliasedNullary extends App { runEmitter }\n", + ) + self.assert_rejected( + self.manifest, + "unknown emitter linxcore.top.EmitAliasedNullary", + ) + + def test_rejects_unregistered_emitter_with_misleading_reduced_name(self) -> None: + self._add_unknown_emitter( + "EmitProductionReducedEscape", + "object EmitProductionReducedEscape extends App {\n" + " circt.stage.ChiselStage.emitSystemVerilogFile(new Object)\n" + "}", + ) + self.assert_rejected( + self.manifest, + "unknown emitter linxcore.top.EmitProductionReducedEscape", + ) + + def test_rejects_external_and_traversal_paths(self) -> None: + external = Path(self.temporary.name) / "outside.md" + external.write_text("outside\n", encoding="utf-8") + for value in (str(external), "../outside.md"): + with self.subTest(value=value): + manifest = copy.deepcopy(self.manifest) + manifest["ndf"]["L1"] = [value] + self.assert_rejected(manifest, "path escapes repository root") + + def test_rejects_ndf_layer_misclassification(self) -> None: + manifest = copy.deepcopy(self.manifest) + manifest["ndf"]["L1"] = [manifest["ndf"]["interface_manifest"]] + self.assert_rejected(manifest, "NDF L1 path must be Markdown under docs/spec") + + def test_rejects_same_file_reused_across_ndf_layers(self) -> None: + manifest = copy.deepcopy(self.manifest) + shared = manifest["ndf"]["L1"][0] + manifest["ndf"]["L1"] = [shared] + manifest["ndf"]["L2"] = [shared] + manifest["ndf"]["L3"] = [shared] + manifest["ndf"]["interface_manifest"] = shared + self.assert_rejected(manifest, "NDF path reused across layer roles") + + def test_rejects_interface_manifest_outside_l2(self) -> None: + manifest = copy.deepcopy(self.manifest) + manifest["ndf"]["L2"] = [ + "chisel/src/main/scala/linxcore/top/interface/TOPIO.scala" + ] + self.assert_rejected(manifest, "interface manifest must be an NDF L2 member") + + def test_rejects_ndf_symlink_alias_across_roles(self) -> None: + manifest = copy.deepcopy(self.manifest) + source = self.root / manifest["ndf"]["L1"][0] + alias = self.root / "tests/ownership_alias.py" + alias.parent.mkdir(parents=True, exist_ok=True) + alias.symlink_to(source) + manifest["ndf"]["L3"].append("tests/ownership_alias.py") + self.assert_rejected(manifest, "NDF normative path must not be a symlink") + + def test_rejects_ndf_hardlink_identity_across_roles(self) -> None: + manifest = copy.deepcopy(self.manifest) + source = self.root / manifest["ndf"]["L1"][0] + alias = self.root / "tests/ownership_hardlink.py" + alias.parent.mkdir(parents=True, exist_ok=True) + os.link(source, alias) + manifest["ndf"]["L3"].append("tests/ownership_hardlink.py") + self.assert_rejected(manifest, "NDF file identity reused across layer roles") + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_scalar_instruction_coverage_report.py b/tests/test_scalar_instruction_coverage_report.py index 41cd5848..ab6218a3 100644 --- a/tests/test_scalar_instruction_coverage_report.py +++ b/tests/test_scalar_instruction_coverage_report.py @@ -67,10 +67,10 @@ def test_reports_current_frontend_and_alu_coverage(self) -> None: ) self.assertEqual( report["cross_stack_aligned_support"]["covered"], - 207, + contract["expected"]["cross_stack_aligned_support"]["covered"], ) self.assertEqual(report["cross_stack_aligned_support"]["known_divergences"], {}) - self.assertEqual(report["reduced_scalar_alu_support"]["parser_supported"], 208) + self.assertEqual(report["reduced_scalar_alu_support"]["parser_supported"], 17) parser_symbols = { symbol for item in report["reduced_scalar_alu_support"]["supported_by_parser"] diff --git a/tests/test_task15_warning_matrix_classifier.py b/tests/test_task15_warning_matrix_classifier.py new file mode 100644 index 00000000..8deb2a6f --- /dev/null +++ b/tests/test_task15_warning_matrix_classifier.py @@ -0,0 +1,69 @@ +from __future__ import annotations + +import importlib.util +import subprocess +import tempfile +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +MODULE_PATH = ROOT / "tools" / "chisel" / "classify_task15_warning_matrix.py" +SPEC = importlib.util.spec_from_file_location("task15_warning_matrix", MODULE_PATH) +assert SPEC is not None and SPEC.loader is not None +CLASSIFIER = importlib.util.module_from_spec(SPEC) +SPEC.loader.exec_module(CLASSIFIER) + + +class Task15WarningMatrixClassifierTest(unittest.TestCase): + def matrix(self, warning: str = "") -> str: + return "\n".join( + line + for width in CLASSIFIER.WIDTHS + for line in ( + f"TASK15_WARNING_MATRIX_BEGIN {width}", + warning if width == "W4" else "", + f"TASK15_WARNING_MATRIX_END {width}", + ) + if line + ) + + def test_clean_matrix_has_no_target_warning(self) -> None: + sections, outside = CLASSIFIER.classify(self.matrix()) + self.assertEqual(outside, []) + self.assertTrue(all(not rows for rows in sections.values())) + + def test_target_warning_is_retained_in_its_width(self) -> None: + sections, _ = CLASSIFIER.classify(self.matrix("[W004] width mismatch")) + self.assertEqual(sections["W4"], ["[W004] width mismatch"]) + + def test_incomplete_matrix_is_rejected(self) -> None: + with self.assertRaises(ValueError): + CLASSIFIER.classify("TASK15_WARNING_MATRIX_BEGIN W2") + + def run_classifier(self, text: str) -> subprocess.CompletedProcess[str]: + with tempfile.NamedTemporaryFile(mode="w", suffix=".log") as log: + log.write(text) + log.flush() + return subprocess.run( + ["python3", str(MODULE_PATH), log.name], + cwd=ROOT, + text=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + check=False, + ) + + def test_non_target_warning_inside_matrix_fails(self) -> None: + proc = self.run_classifier(self.matrix("[W099] unexpected warning")) + self.assertEqual(proc.returncode, 1, proc.stdout + proc.stderr) + self.assertIn("rejected=W099", proc.stdout) + + def test_warning_outside_matrix_fails(self) -> None: + proc = self.run_classifier("[W777] outside\n" + self.matrix()) + self.assertEqual(proc.returncode, 1, proc.stdout + proc.stderr) + self.assertIn("outside=W777", proc.stdout) + + +if __name__ == "__main__": + unittest.main() diff --git a/tests/test_top_natural.py b/tests/test_top_natural.py new file mode 100644 index 00000000..0274caf9 --- /dev/null +++ b/tests/test_top_natural.py @@ -0,0 +1,334 @@ +from __future__ import annotations + +import json +import subprocess +import tempfile +import unittest +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[1] +RUNNER = ROOT / "tools/chisel/run_top_natural.sh" +TB = ROOT / "tools/chisel/top_natural_tb.cpp" +VPI_CONFIG = ROOT / "tools/chisel/top_natural.vlt" + + +class TopNaturalHarnessTest(unittest.TestCase): + def test_runner_reuses_one_emit_for_vpi_and_lint(self) -> None: + source = RUNNER.read_text(encoding="utf-8") + self.assertIn('--lint) LINT=1', source) + self.assertEqual(source.count('runMain ${EMIT_MAIN}'), 1) + self.assertIn( + 'verilator --lint-only --top-module CoreTOPHarness', source + ) + + def test_runner_exposes_only_core_top_ports_to_vpi(self) -> None: + runner = RUNNER.read_text(encoding="utf-8") + self.assertTrue(VPI_CONFIG.is_file()) + config = VPI_CONFIG.read_text(encoding="utf-8") + + self.assertNotIn("--public-flat-rw", runner) + self.assertIn("top_verilator_harness.sv", runner) + self.assertIn("--top-module CoreTOPHarness", runner) + self.assertIn('TOP_VPI_CONFIG="${ROOT_DIR}/tools/chisel/top_natural.vlt"', runner) + self.assertIn('public_flat_rw -module "CoreTOP" -port "io_*"', config) + self.assertIn('public_flat_rw -module "ROB" -port "io_headStatus*"', config) + self.assertIn( + 'public_flat_rw -module "OooIexExecutionPipeline" ' + '-port "io_residentEntries*"', + config, + ) + self.assertIn( + 'public_flat_rw -module "OooIexExecutionPipeline" ' + '-port "io_inFlightEntries*"', + config, + ) + self.assertIn( + 'public_flat_rw -module "OooIexExecutionPipeline" ' + '-port "io_issueEmpty"', + config, + ) + self.assertIn( + 'public_flat_rw -module "OooIexExecutionPipeline" ' + '-port "io_executionEmpty"', + config, + ) + self.assertIn( + 'public_flat_rw -module "OooIexIssue" ' + '-var "scheduleRows_1_*_sources_?_ready"', + config, + ) + harness = TB.read_text(encoding="utf-8") + self.assertIn('std::string("TOP.CoreTOPHarness.dut.")', harness) + self.assertLess( + harness.index('std::string("TOP.CoreTOPHarness.dut.")'), + harness.index('std::string("TOP.")'), + ) + + def test_runner_discards_nonreusable_pch_after_link(self) -> None: + source = RUNNER.read_text(encoding="utf-8") + build = source.index('--build-jobs "${BUILD_JOBS}"') + discard = source.find( + 'find "${OBJ_DIR}" -type f -name \'*.gch\' -delete', build + ) + self.assertNotEqual(discard, -1) + execute = source.index('"${OBJ_DIR}/top_natural_tb"', discard) + + self.assertLess(build, discard) + self.assertLess(discard, execute) + + def test_self_test_records_harness_ownership_without_an_oracle(self) -> None: + with tempfile.TemporaryDirectory() as temporary: + manifest = Path(temporary) / "manifest.json" + result = subprocess.run( + [str(RUNNER), "--self-test", "--manifest", str(manifest)], + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + payload = json.loads(manifest.read_text(encoding="utf-8")) + + self.assertEqual(payload["schema"], 1) + self.assertEqual(payload["top"], "TOP") + self.assertEqual(payload["task"], 18) + self.assertEqual( + payload["harness_owns"], + ["elf", "memory", "uart", "finisher", "manifest"], + ) + self.assertFalse(payload["instruction_oracle"]) + self.assertFalse(payload["commit_oracle"]) + self.assertEqual(payload["memory_size_encoding"]["Bytes64"], 6) + self.assertEqual(payload["build_jobs"], 1) + + def test_default_iteration_profile_bounds_generated_work(self) -> None: + source = RUNNER.read_text(encoding="utf-8") + + self.assertIn('WIDTH="2"', source) + self.assertIn('BUILD_JOBS="1"', source) + self.assertIn('MAX_CYCLES="20000"', source) + self.assertIn('HEARTBEAT_CYCLES="2000"', source) + self.assertIn('DEADLOCK_CYCLES="3000"', source) + + def test_self_test_records_explicit_parallel_build_jobs(self) -> None: + with tempfile.TemporaryDirectory() as temporary: + manifest = Path(temporary) / "manifest.json" + result = subprocess.run( + [str(RUNNER), "--self-test", "--manifest", str(manifest), + "--build-jobs", "3"], + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + payload = json.loads(manifest.read_text(encoding="utf-8")) + + self.assertEqual(payload["build_jobs"], 3) + source = RUNNER.read_text(encoding="utf-8") + self.assertIn('--build-jobs "${BUILD_JOBS}"', source) + self.assertIn('finalize_harness_status "${TB_STATUS}" "${MANIFEST}"', source) + + def test_finalizer_preserves_tb_failure_and_rejects_bad_manifest(self) -> None: + with tempfile.TemporaryDirectory() as temporary: + manifest = Path(temporary) / "manifest.json" + script = r''' +set -euo pipefail +runner="$1" +manifest="$2" +set -- +source "${runner}" +printf '%s\n' stale > "${manifest}" +prepare_harness_manifest "${manifest}" +test ! -e "${manifest}" +printf '%s\n' '{malformed' > "${manifest}" +set +e +finalize_harness_status 37 "${manifest}" +tb_status=$? +finalize_harness_status 0 "${manifest}" +record_status=$? +set -e +test "${tb_status}" -eq 37 +test "${record_status}" -ne 0 +''' + result = subprocess.run( + ["bash", "-c", script, "bash", str(RUNNER), str(manifest)], + cwd=ROOT, + env={ + **__import__("os").environ, + "LINX_TOP_NATURAL_SOURCE_FUNCTIONS_ONLY": "1", + }, + text=True, + capture_output=True, + check=False, + ) + + self.assertEqual(result.returncode, 0, result.stdout + result.stderr) + + def test_build_jobs_must_be_a_positive_integer(self) -> None: + with tempfile.TemporaryDirectory() as temporary: + manifest = Path(temporary) / "manifest.json" + result = subprocess.run( + [str(RUNNER), "--self-test", "--manifest", str(manifest), + "--build-jobs", "0"], + cwd=ROOT, + text=True, + capture_output=True, + check=False, + ) + + self.assertEqual(result.returncode, 2) + self.assertIn("--build-jobs must be a positive integer", result.stderr) + + def test_cpp_harness_has_no_replay_or_expected_commit_input(self) -> None: + source = TB.read_text(encoding="utf-8") + forbidden = ( + "expected_commit", + "expected_instruction", + "replay_rows", + "commit_replay", + "instruction_replay", + ) + for token in forbidden: + self.assertNotIn(token, source.lower()) + + self.assertIn("io_instructionMemoryRequest_ready", source) + self.assertIn("arguments.data_lanes", source) + self.assertIn("arguments.trace_width", source) + self.assertIn("arguments.stid_count * arguments.gpr_arch_regs", source) + self.assertIn("atag == arguments.sp_atag", source) + self.assertNotIn("constexpr int kDataLanes", source) + self.assertNotIn("constexpr int kTraceLanes", source) + self.assertIn("kUartAddress", source) + self.assertIn("kFinisherAddress", source) + self.assertIn('\\"activation\\"', source) + self.assertIn("top-vpi-port-validation=pass", source) + self.assertIn("top-vpi-bootstrap-validation=pass", source) + self.assertIn("pins.put(\"io_bootstrapComplete\", 1)", source) + self.assertIn("observed_bootstrap_ready", source) + self.assertIn('"port_validation_pass"', source) + self.assertIn("5 + entries + 1", source) + self.assertLess(source.index('"port_validation_pass"'), source.index("return 0;")) + + def test_instruction_translation_response_is_identity_mapped(self) -> None: + source = TB.read_text(encoding="utf-8") + + self.assertIn("kInstructionTranslationAccessKind", source) + self.assertIn('stem + "_bits_accessKind"', source) + self.assertIn("response.access_kind", source) + self.assertIn("response.address >> kPageOffsetBits", source) + + def test_system_issue_lane_count_is_metadata_driven_and_required(self) -> None: + runner = RUNNER.read_text(encoding="utf-8") + source = TB.read_text(encoding="utf-8") + emitter = ( + ROOT / "chisel/src/main/scala/linxcore/top/EmitTOP.scala" + ).read_text(encoding="utf-8") + + self.assertIn('s"systemIssueLanes=${p.iex.systemMulticycleQueues}"', emitter) + self.assertIn('systemIssueLanes) SYSTEM_ISSUE_LANES="${value}"', runner) + self.assertIn('--system-issue-lanes "${SYSTEM_ISSUE_LANES}"', runner) + self.assertIn("int system_issue_lanes = 0", source) + self.assertIn('option == "--system-issue-lanes"', source) + self.assertIn("lane < arguments.system_issue_lanes", source) + self.assertNotIn("lane < 8", source) + self.assertNotIn("catch (const std::runtime_error &) { break; }", source) + + def test_optional_commit_trace_observes_only_fired_public_prefix(self) -> None: + runner = RUNNER.read_text(encoding="utf-8") + source = TB.read_text(encoding="utf-8") + + self.assertIn('--commit-trace) COMMIT_TRACE="${2:-}"', runner) + self.assertIn('TB_ARGS+=(--commit-trace "${COMMIT_TRACE}")', runner) + self.assertIn('option == "--commit-trace"', source) + self.assertIn("const bool commit_fire", source) + self.assertIn("std::min", source) + self.assertIn("arguments.retire_width", source) + for field in ( + '"pc"', '"instructionBits"', '"resultValid"', '"result"', + '"memoryValid"', '"memoryStore"', + ): + self.assertIn(field, source) + self.assertNotIn('"storeData"', source) + self.assertNotIn('"mem_wdata"', source) + self.assertFalse("commit_trace" in source and "pins.put" in source[ + source.index("commit_trace"):source.index("commit_trace") + 400 + ]) + + def test_natural_ram_is_noncacheable_and_only_real_write_carries_data(self) -> None: + platform = ( + ROOT / "chisel/src/main/scala/linxcore/params/NaturalPlatformParams.scala" + ).read_text(encoding="utf-8") + source = TB.read_text(encoding="utf-8") + memory = ( + ROOT / "chisel/src/main/scala/linxcore/top/interface/Memory.scala" + ).read_text(encoding="utf-8") + + self.assertIn("normalMemoryAttributes", platform) + self.assertIn("cacheable = false, device = false", platform) + self.assertIn("defaultMemoryAttributes = normalMemoryAttributes", platform) + self.assertIn("val Read, Write, AcquireRead, AcquireWrite", memory) + self.assertIn("accepted_data[lane].command == 1", source) + self.assertIn("if (request.command == 1)", source) + self.assertNotIn("request.command == 3", source) + self.assertNotIn("accepted_data[lane].command == 3", source) + + def test_port_validation_samples_bootstrap_ready_after_completion_edge(self) -> None: + source = TB.read_text(encoding="utf-8") + completion_drive = source.index('pins.put("io_bootstrapComplete", 1)') + completion_edge = source.index( + "dut.clock = 1; dut.eval(); VerilatedVpi::callValueCbs();", + completion_drive, + ) + completion_sample = source.find( + 'pins.get("io_bootstrapReady")', completion_edge + ) + completion_clear = source.index( + 'pins.put("io_bootstrapComplete", 0)', completion_edge + ) + + self.assertNotEqual(completion_sample, -1) + self.assertLess(completion_edge, completion_sample) + self.assertLess(completion_sample, completion_clear) + + def test_watchdog_cli_and_progress_contract(self) -> None: + runner = RUNNER.read_text(encoding="utf-8") + source = TB.read_text(encoding="utf-8") + + self.assertIn("--heartbeat-cycles", runner) + self.assertIn("--deadlock-cycles", runner) + self.assertIn('--heartbeat-cycles "${HEARTBEAT_CYCLES}"', runner) + self.assertIn('--deadlock-cycles "${DEADLOCK_CYCLES}"', runner) + + self.assertIn("heartbeat_cycles = 10000", source) + self.assertIn("deadlock_cycles = 100000", source) + self.assertIn('option == "--heartbeat-cycles"', source) + self.assertIn('option == "--deadlock-cycles"', source) + self.assertIn('"top-natural-heartbeat cycle="', source) + self.assertIn("last_progress_cycle", source) + self.assertIn("arguments.heartbeat_cycles != 0", source) + self.assertIn("arguments.deadlock_cycles != 0", source) + self.assertIn('status = "deadlock"', source) + self.assertIn('"top-natural-deadlock cycle="', source) + self.assertIn('" last-trace-source="', source) + self.assertIn('" last-trace-kind="', source) + self.assertIn('" last-trace-pc=0x"', source) + self.assertIn('" last-trace-opcode=0x"', source) + self.assertIn('"top-natural-trace-event index="', source) + self.assertIn('"top-natural-rob-head stid="', source) + self.assertIn('" completed="', source) + self.assertIn('"top-natural-iex-state issue-empty="', source) + self.assertIn('"top-natural-bru-resident bank="', source) + self.assertIn('" resident="', source) + self.assertIn('" in-flight="', source) + self.assertIn("recent_trace", source) + self.assertIn("instruction_response_fire", source) + self.assertIn("data_response_fire", source) + self.assertIn("trace_fire", source) + self.assertIn("commit_fire", source) + self.assertIn('return status == "finisher_pass" && activated ? 0 : 1;', source) + + +if __name__ == "__main__": + unittest.main() diff --git a/tools/chisel/backend_c_addi_execute_probe_tb.cpp b/tools/chisel/backend_c_addi_execute_probe_tb.cpp deleted file mode 100644 index 2233d0ca..00000000 --- a/tools/chisel/backend_c_addi_execute_probe_tb.cpp +++ /dev/null @@ -1,537 +0,0 @@ -#include "VReducedScalarAluHlSdiPrProbe.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint32_t kOpAddi = 62; -constexpr std::uint32_t kOpCAdd = 564; -constexpr std::uint32_t kOpCAddi = 565; -constexpr std::uint64_t kPcBase = 0x00000000000113b8ULL; -constexpr std::uint8_t kDstArchT = 31; -constexpr std::uint8_t kSrcRArch = 9; -constexpr std::uint8_t kSrcRPhys = 19; -constexpr int kWaitCycles = 10; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint64_t src_l_data; - std::uint64_t src_r_data; - std::uint8_t src_l_arch; - std::uint8_t src_l_phys; - std::int8_t simm5; - std::uint8_t dst_arch; - std::uint8_t dst_phys; - std::uint8_t rid; - bool rid_wrap; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; - std::uint64_t expected; -}; - -struct RawCAddi { - std::uint8_t src_l; - std::uint8_t simm5_raw; -}; - -struct ExpectedEvent { - const char *name; - std::uint16_t raw; - std::uint8_t src_l; - std::int8_t simm5; - std::uint64_t src_l_data; - std::uint8_t dst_arch; - std::uint64_t expected; - bool accepted; - bool completion; - bool release; - bool writeback; - bool unsupported; - bool memory_side_effect; - bool branch_side_effect; - bool redirect_side_effect; -}; - -std::string hex64(std::uint64_t value) { - std::ostringstream os; - os << "0x" << std::hex << value << std::dec; - return os.str(); -} - -[[noreturn]] void fail(const std::string &message) { - std::cerr << "backend-c-addi-execute-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -bool current_red_mode() { - const char *value = std::getenv("EXPECT_CURRENT_RED"); - return value != nullptr && std::string(value) == "1"; -} - -std::uint64_t mask_bits(std::uint64_t value, unsigned width) { - if (width == 64) { - return value; - } - return value & ((1ULL << width) - 1ULL); -} - -std::uint64_t sign_extend(std::uint64_t raw, unsigned width) { - const std::uint64_t sign = 1ULL << (width - 1); - const std::uint64_t mask = (1ULL << width) - 1ULL; - const std::uint64_t value = raw & mask; - return (value & sign) == 0 ? value : value | ~mask; -} - -std::uint16_t encode_c_addi(std::uint8_t src_l, std::int8_t simm5) { - return static_cast( - 0x000cU | - (static_cast(src_l & 0x1fU) << 6) | - (static_cast(mask_bits(static_cast(simm5), 5)) << 11)); -} - -std::uint16_t encode_c_add(std::uint8_t src_l, std::uint8_t src_r) { - return static_cast( - 0x0008U | - (static_cast(src_l & 0x1fU) << 6) | - (static_cast(src_r & 0x1fU) << 11)); -} - -std::uint32_t encode_addi(std::uint8_t dst, std::uint8_t src, std::uint16_t uimm12) { - return 0x0015U | - (static_cast(dst & 0x1fU) << 7) | - (static_cast(src & 0x1fU) << 15) | - (static_cast(uimm12 & 0x0fffU) << 20); -} - -RawCAddi decode_c_addi(std::uint16_t raw) { - require((raw & 0x003fU) == 0x000cU, "C.ADDI decode mask/value rejected legal raw"); - return RawCAddi{ - static_cast((raw >> 6) & 0x1fU), - static_cast((raw >> 11) & 0x1fU)}; -} - -std::int8_t sext5_to_i8(std::uint8_t raw) { - return static_cast(static_cast(sign_extend(raw, 5))); -} - -std::uint64_t c_addi_value(std::uint64_t src_l_data, std::int8_t simm5) { - const std::uint64_t imm = sign_extend(mask_bits(static_cast(simm5), 5), 5); - return src_l_data + imm; -} - -std::uint64_t c_add_value(std::uint64_t src_l_data, std::uint64_t src_r_data) { - return src_l_data + src_r_data; -} - -std::uint64_t addi_value(std::uint64_t src_l_data, std::uint16_t uimm12) { - return src_l_data + (uimm12 & 0x0fffU); -} - -void check_expected_event(const ExpectedEvent &row) { - const auto decoded = decode_c_addi(row.raw); - require(decoded.src_l == row.src_l, std::string(row.name) + ": SrcL raw decode mismatch"); - require(sext5_to_i8(decoded.simm5_raw) == row.simm5, - std::string(row.name) + ": SIMM5 sign-extension mismatch"); - require(row.dst_arch == kDstArchT, - std::string(row.name) + ": C.ADDI destination is not fixed T/x31"); - require(row.expected == c_addi_value(row.src_l_data, row.simm5), - std::string(row.name) + ": expected arithmetic table mismatch"); - require(row.accepted && row.completion && row.release && row.writeback && !row.unsupported, - std::string(row.name) + ": future-green terminal table is inconsistent"); - require(!row.memory_side_effect && !row.branch_side_effect && !row.redirect_side_effect, - std::string(row.name) + ": C.ADDI table expects unrelated side effects"); -} - -void precheck_c_addi_oracles() { - const std::array, 5> simm_cases = {{ - {0, 0x0000000000000000ULL}, - {15, 0x000000000000000fULL}, - {-1, 0xffffffffffffffffULL}, - {-16, 0xfffffffffffffff0ULL}, - {7, 0x0000000000000007ULL}, - }}; - for (const auto &[simm, expected] : simm_cases) { - const std::uint16_t raw = encode_c_addi(12, simm); - require((raw & 0x003fU) == 0x000cU, "C.ADDI raw mask/value is not 0x003f/0x000c"); - const auto decoded = decode_c_addi(raw); - require(decoded.src_l == 12, "C.ADDI SrcL field did not round-trip"); - require(sext5_to_i8(decoded.simm5_raw) == simm, "C.ADDI SIMM5 field did not round-trip"); - require(sign_extend(decoded.simm5_raw, 5) == expected, - "C.ADDI sext5 mismatch for simm=" + std::to_string(static_cast(simm))); - } - - require(c_addi_value(0xffffffffffffffffULL, 1) == 0x0ULL, - "C.ADDI modulo-64 wrap precheck failed"); - require(c_addi_value(0x10ULL, -16) == 0x0ULL, - "C.ADDI negative boundary addition precheck failed"); - require(c_add_value(0x10ULL, 0x22ULL) == 0x32ULL, - "adjacent C.ADD arithmetic precheck failed"); - require(addi_value(0x100ULL, 0x7ffU) == 0x8ffULL, - "adjacent OP_ADDI arithmetic precheck failed"); - - const std::array table = {{ - {"c_addi_zero", encode_c_addi(1, 0), 1, 0, 0x20ULL, kDstArchT, 0x20ULL, - true, true, true, true, false, false, false, false}, - {"c_addi_positive_15", encode_c_addi(2, 15), 2, 15, 0x10ULL, kDstArchT, 0x1fULL, - true, true, true, true, false, false, false, false}, - {"c_addi_negative_one", encode_c_addi(3, -1), 3, -1, 0x0ULL, kDstArchT, 0xffffffffffffffffULL, - true, true, true, true, false, false, false, false}, - {"c_addi_negative_16", encode_c_addi(4, -16), 4, -16, 0x10ULL, kDstArchT, 0x0ULL, - true, true, true, true, false, false, false, false}, - {"c_addi_wrap", encode_c_addi(5, 1), 5, 1, 0xffffffffffffffffULL, kDstArchT, 0x0ULL, - true, true, true, true, false, false, false, false}, - {"c_addi_x31_alias", encode_c_addi(31, -1), 31, -1, 0x40ULL, kDstArchT, 0x3fULL, - true, true, true, true, false, false, false, false}, - }}; - for (const auto &row : table) { - check_expected_event(row); - } - - std::cerr << "backend-c-addi-execute-probe: precheck ok: C.ADDI builder, " - "raw decode, sext5, modulo arithmetic, fixed T/x31 destination, " - "adjacent arithmetic, and future-green event table\n"; -} - -void eval(VReducedScalarAluHlSdiPrProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluHlSdiPrProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -void idle(VReducedScalarAluHlSdiPrProbe &dut) { - dut.io_inValid = 0; - dut.io_flushValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnLen = 2; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_srcDData = 0; - dut.io_srcRData = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_srcDArchTag = 0; - dut.io_srcDPhysTag = 17; - dut.io_srcRArchTag = kSrcRArch; - dut.io_srcRPhysTag = kSrcRPhys; - dut.io_dstValid = 0; - dut.io_dstArchTag = 0; - dut.io_dstPhysTag = 0; -} - -void reset(VReducedScalarAluHlSdiPrProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -std::uint64_t raw_for_case(const Case &c) { - if (c.opcode == kOpCAddi) { - return encode_c_addi(c.src_l_arch, c.simm5); - } - if (c.opcode == kOpCAdd) { - return encode_c_add(c.src_l_arch, kSrcRArch); - } - if (c.opcode == kOpAddi) { - return encode_addi(c.dst_arch, c.src_l_arch, static_cast(mask_bits(c.simm5, 12))); - } - fail(std::string(c.name) + ": unknown opcode"); -} - -std::uint64_t imm_for_case(const Case &c) { - if (c.opcode == kOpCAddi) { - return sign_extend(mask_bits(static_cast(c.simm5), 5), 5); - } - if (c.opcode == kOpAddi) { - return mask_bits(static_cast(c.simm5), 12); - } - return 0; -} - -std::uint64_t expected_for_case(const Case &c) { - if (c.opcode == kOpCAddi) { - return c_addi_value(c.src_l_data, c.simm5); - } - if (c.opcode == kOpCAdd) { - return c_add_value(c.src_l_data, c.src_r_data); - } - if (c.opcode == kOpAddi) { - return addi_value(c.src_l_data, static_cast(mask_bits(c.simm5, 12))); - } - fail(std::string(c.name) + ": unknown opcode for expected value"); -} - -void drive_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, std::uint64_t pc) { - idle(dut); - dut.io_inValid = 1; - dut.io_opcode = c.opcode; - dut.io_pc = pc; - dut.io_insnLen = c.opcode == kOpCAddi || c.opcode == kOpCAdd ? 2 : 4; - dut.io_insnRaw = raw_for_case(c); - dut.io_imm = imm_for_case(c); - dut.io_srcDData = c.src_l_data; - dut.io_srcRData = c.src_r_data; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_srcDArchTag = c.src_l_arch; - dut.io_srcDPhysTag = c.src_l_phys; - dut.io_srcRArchTag = kSrcRArch; - dut.io_srcRPhysTag = kSrcRPhys; - dut.io_dstValid = 1; - dut.io_dstArchTag = c.dst_arch; - dut.io_dstPhysTag = c.dst_phys; - eval(dut); -} - -bool completion_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, std::uint64_t pc) { - const std::uint64_t expected = expected_for_case(c); - const bool has_src1 = c.opcode == kOpCAdd; - const bool gpr_dst = c.dst_arch < 24; - return dut.io_completeValid && dut.io_completeRobValue == c.rid && - dut.io_completeLsId == c.lsid && dut.io_completeDstPhysValid == gpr_dst && - (!gpr_dst || dut.io_completeDstPhysTag == c.dst_phys) && - dut.io_completeDstData == expected && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == c.src_l_phys && - dut.io_completeSrc1PhysValid == has_src1 && - (!has_src1 || dut.io_completeSrc1PhysTag == kSrcRPhys) && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == raw_for_case(c) && - dut.io_completeRowLen == (c.opcode == kOpCAddi || c.opcode == kOpCAdd ? 2 : 4) && - dut.io_completeRowSrc0Valid && dut.io_completeRowSrc0Reg == c.src_l_arch && - dut.io_completeRowSrc0Data == c.src_l_data && - dut.io_completeRowSrc1Valid == has_src1 && - (!has_src1 || (dut.io_completeRowSrc1Reg == kSrcRArch && - dut.io_completeRowSrc1Data == c.src_r_data)) && - dut.io_completeRowDstValid && dut.io_completeRowDstReg == c.dst_arch && - dut.io_completeRowDstData == expected && dut.io_completeRowWbValid && - dut.io_completeRowWbReg == c.dst_arch && dut.io_completeRowWbData == expected && - !dut.io_completeRowMemValid && !dut.io_branchConditionValid && - !dut.io_redirectValid; -} - -bool release_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - return dut.io_releaseValid && dut.io_releaseBidValid && - dut.io_releaseBidWrap == c.bid_wrap && dut.io_releaseBidValue == c.bid && - dut.io_releaseGidValid && dut.io_releaseGidWrap == c.gid_wrap && - dut.io_releaseGidValue == c.gid && dut.io_releaseRidValid && - dut.io_releaseRidWrap == c.rid_wrap && dut.io_releaseRidValue == c.rid && - dut.io_releaseStid == 0; -} - -void require_no_unrelated_side_effects(VReducedScalarAluHlSdiPrProbe &dut, const std::string &name) { - require(!dut.io_loadWaitHold && !dut.io_loadLookupValid && !dut.io_loadLiqEligible && - !dut.io_liqReleaseValid && !dut.io_branchConditionValid && !dut.io_redirectValid, - name + ": unexpected load/branch/redirect side effect"); -} - -bool has_unrelated_side_effects(VReducedScalarAluHlSdiPrProbe &dut) { - return dut.io_loadWaitHold || dut.io_loadLookupValid || dut.io_loadLiqEligible || - dut.io_liqReleaseValid || dut.io_branchConditionValid || dut.io_redirectValid; -} - -void require_no_terminal_or_side_effect(VReducedScalarAluHlSdiPrProbe &dut, - const Case &c, - const char *phase) { - if (dut.io_completeValid || dut.io_releaseValid || dut.io_unsupported || - has_unrelated_side_effects(dut)) { - fail(std::string(c.name) + ": unexpected terminal or side-effect pulse " + phase); - } -} - -void drain_for_duplicates(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - bool busy_cleared = !dut.io_busy; - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - idle(dut); - tick(dut); - eval(dut); - require_no_terminal_or_side_effect(dut, c, "during post-terminal drain"); - busy_cleared = busy_cleared || !dut.io_busy; - } - require(busy_cleared && !dut.io_busy, std::string(c.name) + ": busy did not clear after drain"); -} - -bool wait_for_completion(VReducedScalarAluHlSdiPrProbe &dut, - const Case &c, - std::uint64_t pc) { - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_unsupported) { - fail(std::string(c.name) + ": unexpected unsupported pulse in future-green case"); - } - if (dut.io_completeValid) { - require(completion_matches(dut, c, pc), - std::string(c.name) + ": completion/writeback identity mismatch"); - require(release_matches(dut, c), std::string(c.name) + ": release identity mismatch"); - require_no_unrelated_side_effects(dut, c.name); - drain_for_duplicates(dut, c); - return true; - } - if (dut.io_releaseValid) { - fail(std::string(c.name) + ": release without completion in future-green case"); - } - require_no_unrelated_side_effects(dut, c.name); - tick(dut); - idle(dut); - } - return false; -} - -bool wait_for_current_red_unsupported(VReducedScalarAluHlSdiPrProbe &dut, - const Case &c) { - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - fail(std::string(c.name) + ": current-red path saw completion before unsupported"); - } - if (dut.io_unsupported) { - require(dut.io_unsupportedOpcode == c.opcode, - std::string(c.name) + ": unsupported reported wrong opcode"); - require(release_matches(dut, c), std::string(c.name) + ": unsupported release identity mismatch"); - require_no_unrelated_side_effects(dut, c.name); - drain_for_duplicates(dut, c); - return true; - } - require_no_terminal_or_side_effect(dut, c, "before unsupported"); - tick(dut); - idle(dut); - } - return false; -} - -bool run_case(VReducedScalarAluHlSdiPrProbe &dut, - const Case &c, - unsigned index, - bool expect_current_red = false) { - reset(dut); - require(c.expected == expected_for_case(c), - std::string(c.name) + ": fixture expected value disagrees with independent oracle"); - if (c.opcode == kOpCAddi) { - require(c.dst_arch == kDstArchT, std::string(c.name) + ": C.ADDI fixture did not use fixed T/x31"); - } - const std::uint64_t pc = kPcBase + static_cast(index) * 8ULL; - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready before accept"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - require_no_terminal_or_side_effect(dut, c, "in accept cycle"); - - tick(dut); - idle(dut); - eval(dut); - require(!dut.io_inReady || !dut.io_busy, - std::string(c.name) + ": busy/inReady acceptance backpressure invariant failed"); - - if (expect_current_red) { - if (wait_for_current_red_unsupported(dut, c)) { - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after unsupported"); - return false; - } - fail(std::string(c.name) + ": current-red path produced neither unsupported nor completion"); - } - - if (wait_for_completion(dut, c, pc)) { - return true; - } - - if (dut.io_busy) { - drain_for_duplicates(dut, c); - } - fail(std::string(c.name) + ": accepted transaction produced no completion"); -} - -std::vector cases() { - return { - {"adjacent_c_add_preserved", kOpCAdd, 0x10ULL, 0x22ULL, 11, 31, 0, kDstArchT, 40, 2, false, 3, false, 4, true, 0x113b8001U, 0xcadd100000000001ULL, 0x32ULL}, - {"c_addi_zero_current_red", kOpCAddi, 0x20ULL, 0ULL, 6, 32, 0, kDstArchT, 41, 3, false, 4, true, 5, false, 0x113b8002U, 0xcadd100000000002ULL, 0x20ULL}, - {"c_addi_positive_15", kOpCAddi, 0x10ULL, 0ULL, 7, 33, 15, kDstArchT, 42, 4, true, 5, false, 6, true, 0x113b8003U, 0xcadd100000000003ULL, 0x1fULL}, - {"c_addi_negative_one", kOpCAddi, 0x0ULL, 0ULL, 8, 34, -1, kDstArchT, 43, 5, false, 6, true, 7, false, 0x113b8004U, 0xcadd100000000004ULL, 0xffffffffffffffffULL}, - {"c_addi_negative_16", kOpCAddi, 0x10ULL, 0ULL, 10, 35, -16, kDstArchT, 44, 6, true, 7, false, 8, true, 0x113b8005U, 0xcadd100000000005ULL, 0x0ULL}, - {"c_addi_overflow_wrap", kOpCAddi, 0xffffffffffffffffULL, 0ULL, 12, 36, 1, kDstArchT, 45, 7, false, 8, true, 9, false, 0x113b8006U, 0xcadd100000000006ULL, 0x0ULL}, - {"c_addi_src_l_x31_alias", kOpCAddi, 0x40ULL, 0ULL, 31, 37, -1, kDstArchT, 46, 8, true, 9, false, 10, true, 0x113b8007U, 0xcadd100000000007ULL, 0x3fULL}, - {"adjacent_addi_preserved", kOpAddi, 0x100ULL, 0ULL, 13, 38, 15, 14, 47, 9, false, 10, true, 11, false, 0x113b8008U, 0xcadd100000000008ULL, 0x10fULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - precheck_c_addi_oracles(); - - VReducedScalarAluHlSdiPrProbe dut; - const auto all_cases = cases(); - - require(run_case(dut, all_cases.front(), 0), - "adjacent C.ADD did not complete before current-red check"); - - const bool red_inverted = current_red_mode(); - const bool first_c_addi_completed = run_case(dut, all_cases[1], 1, red_inverted); - if (!first_c_addi_completed) { - if (red_inverted) { - std::cerr << "backend-c-addi-execute-probe: current-red ok: legal OP_C_ADDI " - "accepted and produced unsupported without completion\n"; - std::cout << "backend-c-addi-execute-probe: PASS current-red\n"; - return 0; - } - fail("current RTL accepted legal OP_C_ADDI but reported unsupported without completion"); - } - if (red_inverted) { - fail("EXPECT_CURRENT_RED=1 set, but OP_C_ADDI completed instead of reproducing current red"); - } - - for (unsigned idx = 2; idx < all_cases.size(); ++idx) { - require(run_case(dut, all_cases[idx], idx), - std::string(all_cases[idx].name) + ": future-green case did not complete"); - } - - std::cout << "backend-c-addi-execute-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_implicit_sp_order_probe_tb.cpp b/tools/chisel/backend_implicit_sp_order_probe_tb.cpp deleted file mode 100644 index 3d4d4aff..00000000 --- a/tools/chisel/backend_implicit_sp_order_probe_tb.cpp +++ /dev/null @@ -1,632 +0,0 @@ -#include "VLinxCoreFrontendFetchRfAluTraceTop.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint16_t kOpHlSdiPr = 217; -constexpr std::uint16_t kOpFentry = 429; -constexpr std::uint16_t kOpCMovi = 572; -constexpr std::uint64_t kBasePc = 0x1000; -constexpr std::uint64_t kSpSeed = 0x38850; - -std::uint64_t g_cycle = 0; - -std::uint64_t bits(std::int64_t value, unsigned width) { - if (width == 64) { - return static_cast(value); - } - return static_cast(value) & ((1ULL << width) - 1ULL); -} - -std::uint64_t encode_sdi_wb(std::uint32_t match, unsigned dst, unsigned srcd, unsigned srcr, - std::int32_t simm17) { - const std::uint64_t raw = bits(static_cast(simm17), 17); - std::uint64_t insn = match; - insn |= bits(dst, 5) << 11; - insn |= bits(raw >> 12, 5) << 6; - insn |= bits(raw >> 7, 5) << 23; - insn |= bits(srcd, 5) << 31; - insn |= bits(srcr, 5) << 36; - insn |= bits(raw, 7) << 41; - return insn; -} - -std::uint16_t encode_c_movi(unsigned dst, std::int32_t simm5) { - return static_cast(0x16U | (bits(simm5, 5) << 6) | - (bits(dst, 5) << 11)); -} - -std::string hex64(std::uint64_t value) { - std::ostringstream os; - os << "0x" << std::hex << value << std::dec; - return os.str(); -} - -struct DecodedSdiWb { - unsigned dst = 0; - unsigned srcd = 0; - unsigned srcr = 0; - std::int32_t simm17 = 0; -}; - -struct UopId { - bool rid_valid = false; - bool rid_wrap = false; - unsigned rid_value = 0; - bool bid_valid = false; - bool bid_wrap = false; - unsigned bid_value = 0; - unsigned stid = 0; -}; - -std::int32_t sign_extend_17(std::uint32_t raw) { - if ((raw & (1U << 16)) == 0) { - return static_cast(raw); - } - return static_cast(raw | 0xfffe0000U); -} - -DecodedSdiWb decode_sdi_wb_fields(std::uint64_t insn) { - const std::uint32_t imm_hi5 = static_cast((insn >> 6) & 0x1fU); - const std::uint32_t imm_mid5 = static_cast((insn >> 23) & 0x1fU); - const std::uint32_t imm_lo7 = static_cast((insn >> 41) & 0x7fU); - const std::uint32_t imm17 = (imm_hi5 << 12) | (imm_mid5 << 7) | imm_lo7; - return DecodedSdiWb{static_cast((insn >> 11) & 0x1fU), - static_cast((insn >> 31) & 0x1fU), - static_cast((insn >> 36) & 0x1fU), - sign_extend_17(imm17)}; -} - -bool precheck_sdi_encoder() { - const std::uint64_t dhrystone_raw = encode_sdi_wb(0x3059002eU, 1, 11, 1, -2); - if (dhrystone_raw != 0xfc15bfd90feeULL) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: HL.SDI.PR builder " - << "produced " << hex64(dhrystone_raw) << " want=0xfc15bfd90fee\n"; - return false; - } - const auto decoded = decode_sdi_wb_fields(dhrystone_raw); - if (decoded.dst != 1 || decoded.srcd != 11 || decoded.srcr != 1 || - decoded.simm17 != -2) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: decoded fields" - << " dst=" << decoded.dst << " srcd=" << decoded.srcd - << " srcr=" << decoded.srcr << " simm17=" << decoded.simm17 << "\n"; - return false; - } - const std::uint64_t t_src_raw = encode_sdi_wb(0x3059002eU, 1, 24, 1, -2); - const auto t_decoded = decode_sdi_wb_fields(t_src_raw); - if (t_decoded.dst != 1 || t_decoded.srcd != 24 || t_decoded.srcr != 1 || - t_decoded.simm17 != -2) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: local-source fields" - << " dst=" << t_decoded.dst << " srcd=" << t_decoded.srcd - << " srcr=" << t_decoded.srcr << " simm17=" << t_decoded.simm17 << "\n"; - return false; - } - std::cerr << "backend-implicit-sp-order-probe: precheck ok: HL.SDI.PR builder " - << "round-trips real raw 0xfc15bfd90fee and local-source variant\n"; - return true; -} - -enum class SpAccess : unsigned { - Preserve = 0, - Read = 1, - Write = 2, - ReadWrite = 3, -}; - -SpAccess classify_sp_access(std::uint16_t opcode, - const std::array, 3> &src, - std::optional dst) { - const bool implicit_frame = - opcode == 429 || opcode == 430 || opcode == 431 || opcode == 432; - bool read = implicit_frame; - for (const auto &tag : src) { - read = read || (tag.has_value() && *tag == 1); - } - const bool write = implicit_frame || (dst.has_value() && *dst == 1); - return static_cast((read ? 1U : 0U) | (write ? 2U : 0U)); -} - -bool precheck_access_arithmetic_and_identity_oracles() { - const std::array frame_opcodes = {429, 430, 431, 432}; - const std::array frame_matches = { - 0x41U, 0x1041U, 0x2041U, 0x3041U}; - const std::uint32_t frame_raw = 0x90a50041U; - for (std::size_t i = 0; i < frame_opcodes.size(); ++i) { - const std::uint32_t raw = - (frame_raw & ~0x707fU) | frame_matches[i]; - if ((raw & 0x707fU) != frame_matches[i] || - classify_sp_access(frame_opcodes[i], {}, std::nullopt) != - SpAccess::ReadWrite) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: frame " - "raw/classifier index=" - << i << "\n"; - return false; - } - } - - const std::array, 4> indexed_forms = {{ - {0x3059003eU, 216}, - {0x3059002eU, 217}, - {0x7059003eU, 219}, - {0x7059002eU, 220}, - }}; - for (const auto &[match, opcode] : indexed_forms) { - for (unsigned srcd_is_sp = 0; srcd_is_sp < 2; ++srcd_is_sp) { - for (unsigned srcr_is_sp = 0; srcr_is_sp < 2; ++srcr_is_sp) { - for (unsigned dst_is_sp = 0; dst_is_sp < 2; ++dst_is_sp) { - const unsigned srcd = srcd_is_sp ? 1 : 11; - const unsigned srcr = srcr_is_sp ? 1 : 10; - const unsigned dst = dst_is_sp ? 1 : 9; - const auto decoded = - decode_sdi_wb_fields(encode_sdi_wb(match, dst, srcd, srcr, -2)); - if (decoded.dst != dst || decoded.srcd != srcd || - decoded.srcr != srcr || decoded.simm17 != -2) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: " - "indexed-store raw round trip opcode=" - << opcode << "\n"; - return false; - } - const auto actual = classify_sp_access( - opcode, {srcd, srcr, std::nullopt}, dst); - const auto expected = static_cast( - ((srcd_is_sp || srcr_is_sp) ? 1U : 0U) | - (dst_is_sp ? 2U : 0U)); - if (actual != expected) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: " - "indexed-store classifier opcode=" - << opcode << " srcd_sp=" << srcd_is_sp - << " srcr_sp=" << srcr_is_sp - << " dst_sp=" << dst_is_sp << "\n"; - return false; - } - } - } - } - } - - if (classify_sp_access(kOpCMovi, {10, std::nullopt, std::nullopt}, 11) != - SpAccess::Preserve || - classify_sp_access(61, {10, 11, std::nullopt}, 12) != - SpAccess::Preserve) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: non-SP " - "rows consumed reservation capacity\n"; - return false; - } - - constexpr std::uint64_t initial_sp = 0x38850; - constexpr std::uint64_t indexed_sp = initial_sp - 0x10; - constexpr std::uint64_t frame_size = 0x50; - constexpr std::uint64_t frame_sp = indexed_sp - frame_size; - constexpr std::uint64_t save_addr = frame_sp + frame_size - 8; - constexpr std::uint64_t load_addr = frame_sp + frame_size - 8; - constexpr std::uint64_t restored_sp = frame_sp + frame_size; - if (indexed_sp != 0x38840 || frame_sp != 0x387f0 || - save_addr != 0x38838 || load_addr != save_addr || - restored_sp != 0x38840) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: " - "immediate-only arithmetic table\n"; - return false; - } - - struct ExpectedOrder { - unsigned epoch; - UopId id; - SpAccess access; - unsigned accept_count; - unsigned terminal_count; - unsigned commit_count; - unsigned publication_count; - }; - const std::array expected = {{ - {0, UopId{true, false, 0, true, false, 0, 0}, - SpAccess::Preserve, 1, 1, 1, 0}, - {0, UopId{true, false, 1, true, false, 0, 0}, - SpAccess::ReadWrite, 1, 1, 1, 1}, - {0, UopId{true, false, 2, true, false, 0, 0}, - SpAccess::ReadWrite, 1, 1, 1, 1}, - }}; - for (std::size_t i = 0; i < expected.size(); ++i) { - const auto &row = expected[i]; - if (!row.id.rid_valid || !row.id.bid_valid || row.id.rid_value != i || - row.accept_count != 1 || row.terminal_count != 1 || - row.commit_count != 1 || - row.publication_count != (row.access == SpAccess::Preserve ? 0U : 1U)) { - std::cerr << "backend-implicit-sp-order-probe: precheck failed: " - "identity/order table index=" - << i << "\n"; - return false; - } - } - - std::cerr << "backend-implicit-sp-order-probe: precheck ok: complete frame/" - "explicit classifier, immediate-only arithmetic, identity/order, " - "and non-SP capacity oracles\n"; - return true; -} - -struct FetchMemoryImage { - std::map bytes; - - void store_insn(std::uint64_t pc, std::uint64_t raw, unsigned length) { - for (unsigned i = 0; i < length; ++i) { - bytes[pc + i] = static_cast((raw >> (8 * i)) & 0xffU); - } - } - - std::uint64_t read_window(std::uint64_t pc) const { - std::uint64_t window = 0; - for (unsigned i = 0; i < 8; ++i) { - const auto it = bytes.find(pc + i); - if (it != bytes.end()) { - window |= static_cast(it->second) << (8 * i); - } - } - return window; - } -}; - -struct Event { - enum class Kind { IssueInput, IssueOutput, ExecuteAccepted, Commit } kind; - std::uint64_t cycle = 0; - std::uint64_t pc = 0; - std::uint16_t opcode = 0; - UopId id; -}; - -const char *kind_name(Event::Kind kind) { - switch (kind) { - case Event::Kind::IssueInput: - return "issue-input"; - case Event::Kind::IssueOutput: - return "issue-output"; - case Event::Kind::ExecuteAccepted: - return "execute-accepted"; - case Event::Kind::Commit: - return "commit"; - } - return "unknown"; -} - -std::string event_line(const Event &event) { - std::ostringstream os; - os << "cycle=" << event.cycle << " kind=" << kind_name(event.kind) - << " pc=" << hex64(event.pc) << " opcode=" << event.opcode - << " rid=" << event.id.rid_valid << ":" << event.id.rid_wrap << ":" - << event.id.rid_value << " bid=" << event.id.bid_valid << ":" - << event.id.bid_wrap << ":" << event.id.bid_value - << " stid=" << event.id.stid; - return os.str(); -} - -void clear_inputs(VLinxCoreFrontendFetchRfAluTraceTop &dut) { - dut.io_startValid = 0; - dut.io_startPc = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_bfuBodyValid = 0; - dut.io_bfuHeaderPc = 0; - dut.io_bfuHSizeBytes = 0; - dut.io_bfuBSizeBytes = 0; - dut.io_frontendFlushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 1; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_rfInitValid = 0; - dut.io_rfInitArchTag = 0; - dut.io_rfInitData = 0; - dut.io_deallocReady = 1; - dut.io_loadLookupData = 0; -} - -UopId input_id(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - return UopId{static_cast(dut.io_issueQueueInputRidValid), - static_cast(dut.io_issueQueueInputRidWrap), - static_cast(dut.io_issueQueueInputRidValue), - static_cast(dut.io_issueQueueInputBidValid), - static_cast(dut.io_issueQueueInputBidWrap), - static_cast(dut.io_issueQueueInputBidValue), - static_cast(dut.io_issueQueueInputStid)}; -} - -UopId output_id(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - return UopId{static_cast(dut.io_issueQueueOutputRidValid), - static_cast(dut.io_issueQueueOutputRidWrap), - static_cast(dut.io_issueQueueOutputRidValue), - static_cast(dut.io_issueQueueOutputBidValid), - static_cast(dut.io_issueQueueOutputBidWrap), - static_cast(dut.io_issueQueueOutputBidValue), - static_cast(dut.io_issueQueueOutputStid)}; -} - -UopId accepted_id(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - return UopId{static_cast(dut.io_executeAcceptedRidValid), - static_cast(dut.io_executeAcceptedRidWrap), - static_cast(dut.io_executeAcceptedRidValue), - static_cast(dut.io_executeAcceptedBidValid), - static_cast(dut.io_executeAcceptedBidWrap), - static_cast(dut.io_executeAcceptedBidValue), - static_cast(dut.io_executeAcceptedStid)}; -} - -void observe(const VLinxCoreFrontendFetchRfAluTraceTop &dut, std::vector &events) { - if (dut.io_issueQueueInputValid) { - events.push_back(Event{Event::Kind::IssueInput, g_cycle, dut.io_issueQueueInputPc, - static_cast(dut.io_issueQueueInputOpcode), - input_id(dut)}); - } - if (dut.io_issueQueueOutputValid) { - events.push_back(Event{Event::Kind::IssueOutput, g_cycle, dut.io_issueQueueOutputPc, - static_cast(dut.io_issueQueueOutputOpcode), - output_id(dut)}); - } - if (dut.io_executeAcceptedIdentityValid) { - events.push_back(Event{Event::Kind::ExecuteAccepted, g_cycle, dut.io_executeAcceptedPc, - static_cast(dut.io_executeAcceptedOpcode), - accepted_id(dut)}); - } - if (dut.io_commit_rows_0_valid) { - events.push_back(Event{Event::Kind::Commit, g_cycle, dut.io_commit_rows_0_pc, - 0, UopId{}}); - } - if (dut.io_commit_rows_1_valid) { - events.push_back(Event{Event::Kind::Commit, g_cycle, dut.io_commit_rows_1_pc, - 0, UopId{}}); - } -} - -void tick(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::vector &events) { - dut.clock = 0; - dut.eval(); - observe(dut, events); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); - ++g_cycle; -} - -void reset(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::vector &events) { - clear_inputs(dut); - dut.reset = 1; - tick(dut, events); - tick(dut, events); - dut.reset = 0; - dut.eval(); -} - -void init_rf(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::uint8_t arch_tag, std::uint64_t data, - std::vector &events) { - clear_inputs(dut); - dut.io_rfInitValid = 1; - dut.io_rfInitArchTag = arch_tag; - dut.io_rfInitData = data; - tick(dut, events); - clear_inputs(dut); - dut.eval(); -} - -void start_fetch(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::uint64_t pc, - std::vector &events) { - clear_inputs(dut); - dut.io_startValid = 1; - dut.io_startPc = pc; - tick(dut, events); - clear_inputs(dut); - dut.eval(); -} - -void run_fetch_loop(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemoryImage &mem, - std::vector &events, unsigned max_cycles) { - std::optional pending_resp_pc; - for (unsigned i = 0; i < max_cycles; ++i) { - clear_inputs(dut); - dut.io_fetchReqReady = 1; - if (pending_resp_pc.has_value()) { - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = mem.read_window(*pending_resp_pc); - pending_resp_pc.reset(); - } - dut.eval(); - if (dut.io_fetchReqValid && dut.io_fetchReqReady) { - pending_resp_pc = dut.io_fetchReqPc; - } - tick(dut, events); - if (dut.io_commitContractError || dut.io_rfStateError || dut.io_issueQueueProtocolError) { - break; - } - } - clear_inputs(dut); - dut.eval(); -} - -std::optional first_event(const std::vector &events, Event::Kind kind, - std::uint64_t pc, std::uint16_t opcode) { - for (const auto &event : events) { - if (event.kind == kind && event.pc == pc && event.opcode == opcode) { - return event; - } - } - return std::nullopt; -} - -void dump_events(const std::vector &events) { - for (const auto &event : events) { - std::cerr << " " << event_line(event) << "\n"; - } -} - -int run_case(unsigned srcd, const char *label, bool expect_current_red, - bool add_dependency_producer) { - g_cycle = 0; - std::vector events; - FetchMemoryImage mem; - - const std::uint64_t producer_pc = kBasePc; - const std::uint64_t older_pc = producer_pc + (add_dependency_producer ? 2 : 0); - const std::uint64_t younger_pc = older_pc + 6; - const std::uint16_t producer_raw = encode_c_movi(srcd, 5); - const std::uint64_t older_raw = encode_sdi_wb(0x3059002eU, 1, srcd, 1, -2); - const std::uint64_t younger_raw = 0x90a50041ULL; - if (add_dependency_producer) { - mem.store_insn(producer_pc, producer_raw, 2); - } - mem.store_insn(older_pc, older_raw, 6); - mem.store_insn(younger_pc, younger_raw, 4); - - VLinxCoreFrontendFetchRfAluTraceTop dut; - clear_inputs(dut); - dut.reset = 0; - reset(dut, events); - init_rf(dut, 1, kSpSeed, events); - init_rf(dut, 10, 0x4000, events); - start_fetch(dut, producer_pc, events); - run_fetch_loop(dut, mem, events, 180); - - std::cerr << "backend-implicit-sp-order-probe case=" << label - << " producer=" << add_dependency_producer - << " producer_pc=" << hex64(producer_pc) - << " producer_raw=" << hex64(producer_raw) - << " older_pc=" << hex64(older_pc) << " older_raw=" << hex64(older_raw) - << " younger_pc=" << hex64(younger_pc) << " younger_raw=" << hex64(younger_raw) - << "\n"; - dump_events(events); - - if (dut.io_commitContractError || dut.io_rfStateError || dut.io_issueQueueProtocolError) { - std::cerr << "backend-implicit-sp-order-probe: DUT protocol error" - << " commitContractError=" << static_cast(dut.io_commitContractError) - << " rfStateError=" << static_cast(dut.io_rfStateError) - << " issueQueueProtocolError=" - << static_cast(dut.io_issueQueueProtocolError) << "\n"; - return 2; - } - - const auto older_input = first_event(events, Event::Kind::IssueInput, older_pc, kOpHlSdiPr); - const auto younger_input = first_event(events, Event::Kind::IssueInput, younger_pc, kOpFentry); - const auto older_accepted = - first_event(events, Event::Kind::ExecuteAccepted, older_pc, kOpHlSdiPr); - const auto younger_accepted = - first_event(events, Event::Kind::ExecuteAccepted, younger_pc, kOpFentry); - if (add_dependency_producer) { - const auto producer_input = - first_event(events, Event::Kind::IssueInput, producer_pc, kOpCMovi); - const auto producer_accepted = - first_event(events, Event::Kind::ExecuteAccepted, producer_pc, kOpCMovi); - if (!producer_input.has_value() || !producer_accepted.has_value()) { - std::cerr << "backend-implicit-sp-order-probe: BLOCKED: legal C.MOVI dependency producer did not " - "traverse frontend/decode/rename/issue/execute for case " - << label << "\n"; - return 2; - } - } - - if (!older_input.has_value() || !younger_input.has_value()) { - std::cerr << "backend-implicit-sp-order-probe: BLOCKED: real frontend/decode/rename did not " - "enqueue both legal SP-touching uops through issueQueueInput for case " - << label << "\n"; - return 2; - } - if (older_input->cycle >= younger_input->cycle) { - std::cerr << "backend-implicit-sp-order-probe: BLOCKED: stimulus did not establish older " - "HL.SDI.PR allocation before younger FENTRY for case " - << label << "\n"; - return 2; - } - if (!younger_accepted.has_value()) { - std::cerr << "backend-implicit-sp-order-probe: BLOCKED: younger FENTRY never reached " - "executeAcceptedIdentity for case " - << label << "\n"; - return 2; - } - - if (!older_accepted.has_value()) { - std::cerr << "backend-implicit-sp-order-probe: BLOCKED: older HL.SDI.PR never reached " - "executeAcceptedIdentity, so the exact younger-before-older acceptance " - "predicate cannot be evaluated for case " - << label << "\n"; - return 2; - } - - const bool current_red = younger_accepted->cycle < older_accepted->cycle; - if (current_red) { - std::cerr << "backend-implicit-sp-order-probe: CURRENT_RED: scheduler accepted younger " - "FENTRY before older SP-producing HL.SDI.PR" - << " case=" << label - << " younger_cycle=" << younger_accepted->cycle - << " older_cycle=" - << (older_accepted.has_value() ? std::to_string(older_accepted->cycle) - : std::string("never")) - << "\n"; - if (expect_current_red) { - std::cerr << "backend-implicit-sp-order-probe: EXPECT_CURRENT_RED observed exact " - "DUT-issued predicate\n"; - return 0; - } - return 1; - } - - std::cerr << "backend-implicit-sp-order-probe: future-green observation: older SP writer " - "accepted before younger SP consumer for case " - << label << " older_cycle=" << older_accepted->cycle - << " younger_cycle=" << younger_accepted->cycle << "\n"; - return 3; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const bool expect_current_red = std::getenv("EXPECT_CURRENT_RED") != nullptr; - if (!precheck_sdi_encoder()) { - return 2; - } - if (!precheck_access_arithmetic_and_identity_oracles()) { - return 2; - } - - struct Case { - unsigned srcd; - const char *label; - bool add_dependency_producer; - }; - const std::array cases = {{ - {11, "gpr-srcd-x11-independent", false}, - {11, "gpr-srcd-x11-packed-producer", true}, - }}; - - bool saw_future_green = false; - int last_blocked = 2; - for (const auto &c : cases) { - const int status = - run_case(c.srcd, c.label, expect_current_red, c.add_dependency_producer); - if (status == 0 || status == 1) { - return status; - } - if (status == 3) { - saw_future_green = true; - continue; - } - last_blocked = status; - } - if (saw_future_green) { - if (expect_current_red) { - std::cerr << "backend-implicit-sp-order-probe: EXPECT_CURRENT_RED requested, but legal " - "integrated stimuli produced only future-green accepted ordering\n"; - return 1; - } - return 0; - } - return last_blocked; -} diff --git a/tools/chisel/backend_lui_execute_probe_tb.cpp b/tools/chisel/backend_lui_execute_probe_tb.cpp deleted file mode 100644 index 6acab6f1..00000000 --- a/tools/chisel/backend_lui_execute_probe_tb.cpp +++ /dev/null @@ -1,482 +0,0 @@ -#include "VReducedScalarAluHlSdiPrProbe.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint32_t kOpHlLui = 164; -constexpr std::uint32_t kOpLui = 268; -constexpr std::uint64_t kPcBase = 0x0000000000010fa4ULL; -constexpr std::uint8_t kSrcDArch = 8; -constexpr std::uint8_t kSrcRArch = 9; -constexpr std::uint8_t kSrcDPhys = 18; -constexpr std::uint8_t kSrcRPhys = 19; -constexpr int kWaitCycles = 10; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint32_t imm_raw; - unsigned imm_width; - std::uint8_t dst_arch; - std::uint8_t dst_phys; - std::uint8_t rid; - bool rid_wrap; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; - std::uint64_t expected; -}; - -struct ExpectedEvent { - const char *name; - std::uint32_t opcode; - std::uint32_t imm_raw; - unsigned imm_width; - std::uint8_t dst; - std::uint64_t raw; - std::uint64_t expected; - bool completion; - bool release; - bool writeback; - bool unsupported; - bool memory_side_effect; - bool branch_side_effect; - bool redirect_side_effect; -}; - -std::string hex64(std::uint64_t value) { - std::ostringstream os; - os << "0x" << std::hex << value << std::dec; - return os.str(); -} - -[[noreturn]] void fail(const std::string &message) { - std::cerr << "backend-lui-execute-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -bool current_red_mode() { - const char *value = std::getenv("EXPECT_CURRENT_RED"); - return value != nullptr && std::string(value) == "1"; -} - -std::uint64_t bits(std::uint64_t value, unsigned width) { - if (width == 64) { - return value; - } - return value & ((1ULL << width) - 1ULL); -} - -std::uint64_t sign_extend(std::uint64_t raw, unsigned width) { - const std::uint64_t sign = 1ULL << (width - 1); - const std::uint64_t mask = (1ULL << width) - 1ULL; - const std::uint64_t value = raw & mask; - if ((value & sign) == 0) { - return value; - } - return value | ~mask; -} - -std::uint64_t lui_value(std::uint32_t imm20) { - return (sign_extend(imm20, 20) << 12) & 0xffffffffffffffffULL; -} - -std::uint64_t hl_lui_value(std::uint32_t imm32) { - return sign_extend(imm32, 32); -} - -std::uint32_t encode_lui(std::uint8_t dst, std::uint32_t imm20) { - return 0x17U | (static_cast(dst & 0x1fU) << 7) | - ((imm20 & 0xfffffU) << 12); -} - -std::uint64_t encode_hl_lui(std::uint8_t dst, std::uint32_t imm32) { - return 0x17000eULL | (static_cast(dst & 0x1fU) << 23) | - (static_cast(imm32 & 0xfffU) << 4) | - (static_cast(imm32 >> 12) << 28); -} - -std::uint8_t decode_lui_dst(std::uint32_t raw) { - return static_cast((raw >> 7) & 0x1fU); -} - -std::uint32_t decode_lui_imm20(std::uint32_t raw) { - return (raw >> 12) & 0xfffffU; -} - -std::uint8_t decode_hl_lui_dst(std::uint64_t raw) { - return static_cast((raw >> 23) & 0x1fU); -} - -std::uint32_t decode_hl_lui_imm32(std::uint64_t raw) { - return static_cast(((raw >> 4) & 0xfffULL) | - (((raw >> 28) & 0xfffffULL) << 12)); -} - -std::uint64_t expected_value(std::uint32_t opcode, std::uint32_t imm_raw, unsigned imm_width) { - if (opcode == kOpLui) { - require(imm_width == 20, "OP_LUI event must use imm20"); - return lui_value(imm_raw); - } - if (opcode == kOpHlLui) { - require(imm_width == 32, "OP_HL_LUI event must use imm32"); - return hl_lui_value(imm_raw); - } - fail("unknown opcode in expected-value oracle"); -} - -std::uint64_t expected_raw(std::uint32_t opcode, std::uint8_t dst, std::uint32_t imm_raw) { - if (opcode == kOpLui) { - return encode_lui(dst, imm_raw); - } - if (opcode == kOpHlLui) { - return encode_hl_lui(dst, imm_raw); - } - fail("unknown opcode in raw-encoding oracle"); -} - -void check_expected_event(const ExpectedEvent &row) { - require(row.opcode == kOpLui || row.opcode == kOpHlLui, - std::string(row.name) + ": unexpected opcode in event table"); - require(row.dst < 24, std::string(row.name) + ": destination must classify as scalar GPR"); - require(row.completion && row.release && row.writeback && !row.unsupported, - std::string(row.name) + ": future-green terminal table is inconsistent"); - require(!row.memory_side_effect && !row.branch_side_effect && !row.redirect_side_effect, - std::string(row.name) + ": LUI table expects unrelated side effects"); - require(row.raw == expected_raw(row.opcode, row.dst, row.imm_raw), - std::string(row.name) + ": raw encoding disagrees with independent fixture"); - require(row.expected == expected_value(row.opcode, row.imm_raw, row.imm_width), - std::string(row.name) + ": expected value disagrees with independent semantic fixture"); - if (row.opcode == kOpLui) { - require(decode_lui_dst(static_cast(row.raw)) == row.dst, - std::string(row.name) + ": LUI destination decode mismatch"); - require(decode_lui_imm20(static_cast(row.raw)) == bits(row.imm_raw, 20), - std::string(row.name) + ": LUI imm20 decode mismatch"); - } else { - require(decode_hl_lui_dst(row.raw) == row.dst, - std::string(row.name) + ": HL.LUI destination decode mismatch"); - require(decode_hl_lui_imm32(row.raw) == bits(row.imm_raw, 32), - std::string(row.name) + ": HL.LUI imm32 decode mismatch"); - } -} - -void precheck_lui_oracles() { - const std::array, 5> imm_cases = {{ - {0x00000U, 0x0000000000000000ULL}, - {0x00001U, 0x0000000000001000ULL}, - {0x7ffffU, 0x000000007ffff000ULL}, - {0x80000U, 0xffffffff80000000ULL}, - {0xfffffU, 0xfffffffffffff000ULL}, - }}; - - for (const auto &[imm20, expected] : imm_cases) { - const std::uint32_t raw = encode_lui(13, imm20); - require((raw & 0x7fU) == 0x17U, "LUI raw opcode field is not 0x17"); - require(decode_lui_dst(raw) == 13, "LUI destination field did not round-trip"); - require(decode_lui_imm20(raw) == imm20, "LUI imm20 field did not round-trip"); - require(lui_value(imm20) == expected, - "LUI sext20<<12 mismatch for imm20=" + hex64(imm20)); - } - - const std::uint64_t hl_raw = encode_hl_lui(14, 0x80000001U); - require((hl_raw & 0x0000007f000fULL) == 0x00000017000eULL, - "HL.LUI raw mask/value precheck failed"); - require(decode_hl_lui_dst(hl_raw) == 14, "HL.LUI destination field did not round-trip"); - require(decode_hl_lui_imm32(hl_raw) == 0x80000001U, - "HL.LUI imm32 field did not round-trip"); - require(hl_lui_value(0x80000001U) == 0xffffffff80000001ULL, - "HL.LUI sext32 semantic precheck failed"); - - const std::array table = {{ - {"lui_zero", kOpLui, 0x00000U, 20, 5, encode_lui(5, 0x00000U), 0x0ULL, - true, true, true, false, false, false, false}, - {"lui_positive", kOpLui, 0x12345U, 20, 6, encode_lui(6, 0x12345U), 0x12345000ULL, - true, true, true, false, false, false, false}, - {"lui_sign_bit", kOpLui, 0x80000U, 20, 7, encode_lui(7, 0x80000U), 0xffffffff80000000ULL, - true, true, true, false, false, false, false}, - {"lui_negative_max", kOpLui, 0xfffffU, 20, 8, encode_lui(8, 0xfffffU), 0xfffffffffffff000ULL, - true, true, true, false, false, false, false}, - {"hl_lui_adjacent", kOpHlLui, 0x80000001U, 32, 9, encode_hl_lui(9, 0x80000001U), - 0xffffffff80000001ULL, true, true, true, false, false, false, false}, - }}; - for (const auto &row : table) { - check_expected_event(row); - } - - std::cerr << "backend-lui-execute-probe: precheck ok: LUI/HL.LUI raw decode, " - "destination extraction, sext materialization, boundaries, and " - "future-green event table\n"; -} - -void eval(VReducedScalarAluHlSdiPrProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluHlSdiPrProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -void idle(VReducedScalarAluHlSdiPrProbe &dut) { - dut.io_inValid = 0; - dut.io_flushValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnLen = 4; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_srcDData = 0; - dut.io_srcRData = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_srcDArchTag = kSrcDArch; - dut.io_srcDPhysTag = kSrcDPhys; - dut.io_srcRArchTag = kSrcRArch; - dut.io_srcRPhysTag = kSrcRPhys; - dut.io_dstValid = 0; - dut.io_dstArchTag = 0; - dut.io_dstPhysTag = 0; -} - -void reset(VReducedScalarAluHlSdiPrProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -std::uint64_t raw_for_case(const Case &c) { - if (c.opcode == kOpLui) { - return encode_lui(c.dst_arch, c.imm_raw); - } - if (c.opcode == kOpHlLui) { - return encode_hl_lui(c.dst_arch, c.imm_raw); - } - fail(std::string(c.name) + ": unknown opcode"); -} - -std::uint64_t imm_for_case(const Case &c) { - if (c.opcode == kOpLui) { - require(c.imm_width == 20, std::string(c.name) + ": LUI fixture must use imm20"); - return lui_value(c.imm_raw); - } - if (c.opcode == kOpHlLui) { - require(c.imm_width == 32, std::string(c.name) + ": HL.LUI fixture must use imm32"); - return hl_lui_value(c.imm_raw); - } - fail(std::string(c.name) + ": unknown opcode for immediate"); -} - -void drive_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, std::uint64_t pc) { - idle(dut); - dut.io_inValid = 1; - dut.io_opcode = c.opcode; - dut.io_pc = pc; - dut.io_insnLen = c.opcode == kOpHlLui ? 6 : 4; - dut.io_insnRaw = raw_for_case(c); - dut.io_imm = imm_for_case(c); - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_dstValid = 1; - dut.io_dstArchTag = c.dst_arch; - dut.io_dstPhysTag = c.dst_phys; - eval(dut); -} - -bool completion_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, std::uint64_t pc) { - return dut.io_completeValid && dut.io_completeRobValue == c.rid && - dut.io_completeLsId == c.lsid && dut.io_completeDstPhysValid && - dut.io_completeDstPhysTag == c.dst_phys && dut.io_completeDstData == c.expected && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == kSrcDPhys && - dut.io_completeSrc1PhysValid && dut.io_completeSrc1PhysTag == kSrcRPhys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == raw_for_case(c) && - dut.io_completeRowLen == (c.opcode == kOpHlLui ? 6 : 4) && - dut.io_completeRowSrc0Valid && dut.io_completeRowSrc0Reg == kSrcDArch && - dut.io_completeRowSrc0Data == 0 && - dut.io_completeRowSrc1Valid && dut.io_completeRowSrc1Reg == kSrcRArch && - dut.io_completeRowSrc1Data == 0 && - dut.io_completeRowDstValid && dut.io_completeRowDstReg == c.dst_arch && - dut.io_completeRowDstData == c.expected && dut.io_completeRowWbValid && - dut.io_completeRowWbReg == c.dst_arch && dut.io_completeRowWbData == c.expected && - !dut.io_completeRowMemValid && !dut.io_branchConditionValid && - !dut.io_redirectValid; -} - -bool release_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - return dut.io_releaseValid && dut.io_releaseBidValid && - dut.io_releaseBidWrap == c.bid_wrap && dut.io_releaseBidValue == c.bid && - dut.io_releaseGidValid && dut.io_releaseGidWrap == c.gid_wrap && - dut.io_releaseGidValue == c.gid && dut.io_releaseRidValid && - dut.io_releaseRidWrap == c.rid_wrap && dut.io_releaseRidValue == c.rid && - dut.io_releaseStid == 0; -} - -void drain_for_duplicates(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - idle(dut); - tick(dut); - eval(dut); - if (dut.io_completeValid || dut.io_releaseValid || dut.io_unsupported) { - fail(std::string(c.name) + ": duplicate terminal pulse before reset"); - } - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after drain"); -} - -bool wait_for_completion_or_unsupported(VReducedScalarAluHlSdiPrProbe &dut, - const Case &c, - std::uint64_t pc, - bool *unsupported_seen) { - *unsupported_seen = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require(completion_matches(dut, c, pc), - std::string(c.name) + ": completion/writeback identity mismatch"); - require(release_matches(dut, c), std::string(c.name) + ": release identity mismatch"); - require(!dut.io_unsupported, - std::string(c.name) + ": completion overlapped unsupported"); - require(!dut.io_loadWaitHold && !dut.io_loadLookupValid && !dut.io_loadLiqEligible && - !dut.io_liqReleaseValid, - std::string(c.name) + ": completion had unrelated load side effect"); - drain_for_duplicates(dut, c); - return true; - } - if (dut.io_unsupported) { - require(dut.io_unsupportedOpcode == c.opcode, - std::string(c.name) + ": unsupported reported wrong opcode"); - require(!dut.io_completeValid, - std::string(c.name) + ": unsupported overlapped a completion"); - require(release_matches(dut, c), std::string(c.name) + ": unsupported release identity mismatch"); - require(!dut.io_loadWaitHold && !dut.io_loadLookupValid && - !dut.io_loadLiqEligible && !dut.io_liqReleaseValid && - !dut.io_branchConditionValid && !dut.io_redirectValid, - std::string(c.name) + ": unsupported had unrelated side effect"); - *unsupported_seen = true; - } - tick(dut); - idle(dut); - } - return false; -} - -bool run_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, unsigned index) { - reset(dut); - require(c.expected == imm_for_case(c), - std::string(c.name) + ": fixture expected value disagrees with independent semantic oracle"); - const std::uint64_t pc = kPcBase + static_cast(index) * 8ULL; - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready before accept"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - - tick(dut); - idle(dut); - eval(dut); - require(!dut.io_inReady || !dut.io_busy, - std::string(c.name) + ": busy/inReady backpressure invariant failed"); - - bool unsupported_seen = false; - const bool completed = wait_for_completion_or_unsupported(dut, c, pc, &unsupported_seen); - if (completed) { - return true; - } - if (unsupported_seen) { - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after unsupported"); - drain_for_duplicates(dut, c); - return false; - } - fail(std::string(c.name) + ": accepted transaction produced neither completion nor unsupported"); -} - -std::vector cases() { - return { - {"adjacent_hl_lui_preserved", kOpHlLui, 0x80000001U, 32, 9, 41, 2, false, 3, false, 4, true, 0x10fa4001U, 0x8790000000000001ULL, 0xffffffff80000001ULL}, - {"lui_zero_current_red", kOpLui, 0x00000U, 20, 5, 42, 3, false, 4, true, 5, false, 0x10fa4002U, 0x8790000000000002ULL, 0x0000000000000000ULL}, - {"lui_positive", kOpLui, 0x12345U, 20, 6, 43, 4, true, 5, false, 6, true, 0x10fa4003U, 0x8790000000000003ULL, 0x0000000012345000ULL}, - {"lui_sign_bit_boundary", kOpLui, 0x80000U, 20, 7, 44, 5, false, 6, true, 7, false, 0x10fa4004U, 0x8790000000000004ULL, 0xffffffff80000000ULL}, - {"lui_negative_max", kOpLui, 0xfffffU, 20, 8, 45, 6, true, 7, false, 8, true, 0x10fa4005U, 0x8790000000000005ULL, 0xfffffffffffff000ULL}, - {"lui_max_positive", kOpLui, 0x7ffffU, 20, 10, 46, 7, false, 8, true, 9, false, 0x10fa4006U, 0x8790000000000006ULL, 0x000000007ffff000ULL}, - {"lui_high_gpr_destination_kind", kOpLui, 0x00001U, 20, 23, 47, 8, true, 9, false, 10, true, 0x10fa4007U, 0x8790000000000007ULL, 0x0000000000001000ULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - precheck_lui_oracles(); - - VReducedScalarAluHlSdiPrProbe dut; - const auto all_cases = cases(); - - require(run_case(dut, all_cases.front(), 0), - "adjacent HL.LUI did not complete before current-red check"); - - const bool red_inverted = current_red_mode(); - const bool first_lui_completed = run_case(dut, all_cases[1], 1); - if (!first_lui_completed) { - if (red_inverted) { - std::cerr << "backend-lui-execute-probe: current-red ok: legal OP_LUI " - "accepted and produced unsupported without completion\n"; - std::cout << "backend-lui-execute-probe: PASS current-red\n"; - return 0; - } - fail("current RTL accepted legal OP_LUI but reported unsupported without completion"); - } - if (red_inverted) { - fail("EXPECT_CURRENT_RED=1 set, but OP_LUI completed instead of reproducing current red"); - } - - for (unsigned idx = 2; idx < all_cases.size(); ++idx) { - require(run_case(dut, all_cases[idx], idx), - std::string(all_cases[idx].name) + ": future-green case did not complete"); - } - - std::cout << "backend-lui-execute-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_rob_completion_arbiter_behavior_probe_tb.cpp b/tools/chisel/backend_reduced_rob_completion_arbiter_behavior_probe_tb.cpp deleted file mode 100644 index 48bdf0b1..00000000 --- a/tools/chisel/backend_reduced_rob_completion_arbiter_behavior_probe_tb.cpp +++ /dev/null @@ -1,288 +0,0 @@ -#include -#include -#include -#include - -#include "VReducedRobCompletionArbiterBehaviorProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint64_t kExecuteToken = 0x1111222233334444ULL; -constexpr std::uint64_t kReplayToken = 0x5555666677778888ULL; -constexpr std::uint64_t kTemplateToken = 0x9999aaaabbbbccccULL; -constexpr std::uint64_t kSignatureXor = 0xa5a5a5a5a5a5a5a5ULL; - -struct Source { - bool valid; - std::uint8_t slot; - bool row_valid; - std::uint64_t token; -}; - -struct Expected { - bool valid; - std::uint8_t slot; - bool row_valid; - std::uint64_t token; - bool execute; - bool replay; - bool service; - bool templ; - std::uint8_t source_mask; - bool row_payload; -}; - -[[noreturn]] void fail(const std::string &message) { - std::cerr << "backend-reduced-rob-completion-arbiter-behavior-probe: FAIL: " - << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void drive(VReducedRobCompletionArbiterBehaviorProbe &dut, - const Source &execute, - const Source &replay, - const Source &service, - const Source &templ, - std::uint8_t template_parent_slot) { - dut.io_executeValid = execute.valid; - dut.io_executeSlot = execute.slot; - dut.io_executeRowValid = execute.row_valid; - dut.io_executeRowToken = execute.token; - dut.io_replayValid = replay.valid; - dut.io_replaySlot = replay.slot; - dut.io_replayRowValid = replay.row_valid; - dut.io_replayRowToken = replay.token; - dut.io_serviceValid = service.valid; - dut.io_serviceSlot = service.slot; - dut.io_serviceRowValid = service.row_valid; - dut.io_serviceRowToken = service.token; - dut.io_templateValid = templ.valid; - dut.io_templateSlot = templ.slot; - dut.io_templateRowValid = templ.row_valid; - dut.io_templateRowToken = templ.token; - dut.io_templateParentSlot = template_parent_slot; -} - -Expected expected_for( - const Source &execute, - const Source &replay, - const Source &service, - const Source &templ) { - if (execute.valid) { - return {true, execute.slot, execute.row_valid, execute.token, true, false, false, false, 1, true}; - } - if (replay.valid) { - return {true, replay.slot, replay.row_valid, replay.token, false, true, false, false, 2, true}; - } - if (service.valid) { - return {true, service.slot, service.row_valid, service.token, false, false, true, false, 4, true}; - } - if (templ.valid) { - return {true, templ.slot, templ.row_valid, templ.token, false, false, false, true, 8, true}; - } - return {false, 0, false, 0, false, false, false, false, 0, false}; -} - -void check_outputs(VReducedRobCompletionArbiterBehaviorProbe &dut, - const Source &execute, - const Source &replay, - const Source &service, - const Source &templ, - const std::string &label) { - dut.eval(); - const Expected expected = expected_for(execute, replay, service, templ); - const unsigned selection_count = - static_cast(dut.io_selectedExecute) + - static_cast(dut.io_selectedReplay) + - static_cast(dut.io_selectedService) + - static_cast(dut.io_selectedTemplate); - - require(dut.io_completeValid == expected.valid, label + ": complete-valid mismatch"); - require(dut.io_completeSlot == expected.slot, label + ": selected slot mismatch"); - require(dut.io_completeRowValid == expected.row_valid, label + ": row-valid mismatch"); - require(dut.io_completeRowToken == expected.token, label + ": row token mismatch"); - require(dut.io_completeRowSignature == - (expected.row_payload ? expected.token + 8 : 0), - label + ": row signature mismatch"); - require(dut.io_completeRowMemToken == - (expected.row_payload ? expected.token ^ kSignatureXor : 0), - label + ": row memory token mismatch"); - require(dut.io_selectedExecute == expected.execute, label + ": execute selection mismatch"); - require(dut.io_selectedReplay == expected.replay, label + ": replay selection mismatch"); - require(dut.io_selectedService == expected.service, label + ": service selection mismatch"); - require(dut.io_selectedTemplate == expected.templ, label + ": template selection mismatch"); - require(dut.io_selectedSourceMask == expected.source_mask, label + ": source-mask mismatch"); - require(selection_count == static_cast(expected.valid), - label + ": selection is not idle-or-one-hot"); - require(dut.io_replayBlockedByExecute == (replay.valid && execute.valid), - label + ": replay blocker mismatch"); - require(dut.io_serviceBlockedByExecute == (service.valid && execute.valid), - label + ": service execute-blocker mismatch"); - require(dut.io_serviceBlockedByReplay == - (service.valid && !execute.valid && replay.valid), - label + ": service replay-blocker mismatch"); - require(dut.io_templateBlockedByExecute == (templ.valid && execute.valid), - label + ": template execute-blocker mismatch"); - require(dut.io_templateBlockedByReplay == - (templ.valid && !execute.valid && replay.valid), - label + ": template replay-blocker mismatch"); -} - -void prove_all_valid_combinations(VReducedRobCompletionArbiterBehaviorProbe &dut) { - for (unsigned bits = 0; bits < 16; ++bits) { - const Source execute{(bits & 8U) != 0, 1, true, kExecuteToken}; - const Source replay{(bits & 4U) != 0, 3, false, kReplayToken}; - const Source service{(bits & 2U) != 0, 5, true, 0x0102030405060708ULL}; - const Source templ{(bits & 1U) != 0, 6, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "valid-combination-" + std::to_string(bits)); - } -} - -void prove_row_valid_forwarding(VReducedRobCompletionArbiterBehaviorProbe &dut) { - for (unsigned selected = 0; selected < 4; ++selected) { - for (unsigned row_valid = 0; row_valid < 2; ++row_valid) { - Source execute{selected == 0, 1, row_valid != 0, kExecuteToken}; - Source replay{selected == 1, 3, row_valid != 0, kReplayToken}; - Source service{selected == 2, 5, row_valid != 0, 0x0102030405060708ULL}; - Source templ{selected == 3, 6, row_valid != 0, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs( - dut, - execute, - replay, - service, - templ, - "row-valid-source-" + std::to_string(selected) + "-" + - std::to_string(row_valid)); - } - } -} - -void prove_unselected_payload_independence(VReducedRobCompletionArbiterBehaviorProbe &dut) { - Source execute{true, 1, true, kExecuteToken}; - Source replay{true, 3, false, kReplayToken}; - Source service{true, 5, true, 0x0102030405060708ULL}; - Source templ{true, 6, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "execute-before-unselected-mutation"); - replay = {true, 7, true, 0x0102030405060708ULL}; - service = {true, 4, true, 0x2222333344445555ULL}; - templ = {true, 2, false, 0xf0e0d0c0b0a09080ULL}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "execute-after-unselected-mutation"); - - execute = {false, 7, false, 0xdeadbeefdeadbeefULL}; - replay = {true, 3, true, kReplayToken}; - service = {true, 5, true, 0x0102030405060708ULL}; - templ = {true, 6, false, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "replay-before-unselected-mutation"); - execute = {false, 2, true, 0x1212121212121212ULL}; - service = {true, 4, true, 0x2222333344445555ULL}; - templ = {true, 5, true, 0x3434343434343434ULL}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "replay-after-unselected-mutation"); - - execute = {false, 1, true, kExecuteToken}; - replay = {false, 3, false, kReplayToken}; - service = {true, 5, true, 0x0102030405060708ULL}; - templ = {true, 6, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "service-before-template-mutation"); - templ = {true, 2, true, 0x7878787878787878ULL}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "service-after-template-mutation"); - - service = {false, 5, false, 0}; - templ = {true, 6, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "template-before-unselected-mutation"); - execute = {false, 7, false, 0x5656565656565656ULL}; - replay = {false, 2, true, 0x7878787878787878ULL}; - service = {false, 4, false, 0}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "template-after-unselected-mutation"); -} - -void prove_idle_sanitization(VReducedRobCompletionArbiterBehaviorProbe &dut) { - const Source execute{false, 7, true, 0x1111111111111111ULL}; - const Source replay{false, 5, true, 0x2222222222222222ULL}; - const Source service{false, 3, true, 0x4444444444444444ULL}; - const Source templ{false, 4, true, 0x3333333333333333ULL}; - drive(dut, execute, replay, service, templ, templ.slot); - check_outputs(dut, execute, replay, service, templ, "idle-with-stale-payloads"); -} - -void prove_contention_diagnostics(VReducedRobCompletionArbiterBehaviorProbe &dut) { - Source execute{true, 2, true, kExecuteToken}; - Source replay{true, 2, true, kReplayToken}; - Source service{true, 2, true, 0x0102030405060708ULL}; - Source templ{true, 2, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - dut.eval(); - require(dut.io_completionContended, "same-RID contention should be visible"); - require(dut.io_sameRobCompletionContention, "same-RID contention diagnostic mismatch"); - require(!dut.io_differentRobCompletionContention, "same-RID contention was marked different"); - require(!dut.io_protocolError, "same-RID contention should not be protocolError"); - - execute = {false, 2, true, kExecuteToken}; - replay = {true, 1, true, kReplayToken}; - service = {true, 3, true, 0x0102030405060708ULL}; - templ = {true, 3, true, kTemplateToken}; - drive(dut, execute, replay, service, templ, templ.slot); - dut.eval(); - require(dut.io_completionContended, "different-RID contention should be visible"); - require(!dut.io_sameRobCompletionContention, "different-RID contention was marked same"); - require(dut.io_differentRobCompletionContention, "different-RID diagnostic mismatch"); - require(dut.io_protocolError, "different-RID contention should be protocolError"); -} - -[[noreturn]] void trigger_parent_slot_assertion( - VReducedRobCompletionArbiterBehaviorProbe &dut) { - const Source execute{false, 1, true, kExecuteToken}; - const Source replay{false, 3, true, kReplayToken}; - const Source service{false, 5, true, 0x0102030405060708ULL}; - const Source templ{true, 6, true, kTemplateToken}; - dut.reset = 0; - dut.clock = 0; - drive(dut, execute, replay, service, templ, 5); - dut.eval(); - dut.clock = 1; - dut.eval(); - fail("parent-slot mismatch was silently accepted by the emitted hardware"); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedRobCompletionArbiterBehaviorProbe dut; - dut.clock = 0; - dut.reset = 0; - - if (argc == 2 && std::string(argv[1]) == "--trigger-parent-slot-mismatch") { - trigger_parent_slot_assertion(dut); - } - if (argc != 1) { - fail("unknown argument"); - } - - prove_all_valid_combinations(dut); - prove_row_valid_forwarding(dut); - prove_unselected_payload_independence(dut); - prove_idle_sanitization(dut); - prove_contention_diagnostics(dut); - - std::cout - << "backend-reduced-rob-completion-arbiter-behavior-probe: PASS " - << "(16 combinations, service rows, template rows, blockers, diagnostics, one-hot, idle)\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_addiw_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_addiw_probe_tb.cpp deleted file mode 100644 index 52563239..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_addiw_probe_tb.cpp +++ /dev/null @@ -1,277 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluAddiwProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpAddiw = 63; -constexpr std::uint64_t kPcBase = 0x0000000000013000ULL; -constexpr std::uint8_t kFirstSrcArch = 0; -constexpr std::uint8_t kDefaultSrcPhys = 17; -constexpr std::uint8_t kDefaultDstPhys = 41; -constexpr int kWaitCycles = 8; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint64_t src; - std::uint16_t uimm12; - std::uint8_t src_arch; - std::uint8_t src_phys; - std::uint8_t dst_arch; - std::uint8_t dst_phys; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-addiw-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void eval(VReducedScalarAluAddiwProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluAddiwProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -std::uint64_t sail_addiw(std::uint64_t src, std::uint16_t uimm12) { - const std::uint32_t low = static_cast(src & 0xffffffffULL); - const std::uint32_t imm = static_cast(uimm12 & 0x0fffU); - const std::uint32_t result = low + imm; - return static_cast(static_cast(static_cast(result))); -} - -std::uint64_t insn_for_case(const Case &c) { - return (static_cast(c.uimm12 & 0x0fffU) << 20) | - (static_cast(c.src_arch & 0x1fU) << 15) | - (static_cast(c.dst_arch & 0x1fU) << 7) | - 0x35ULL; -} - -void idle(VReducedScalarAluAddiwProbe &dut) { - dut.io_inValid = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_uimm12 = 0; - dut.io_src0Data = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_src0ArchTag = kFirstSrcArch; - dut.io_src0PhysTag = kDefaultSrcPhys; - dut.io_dstArchTag = 1; - dut.io_dstPhysTag = kDefaultDstPhys; -} - -void reset(VReducedScalarAluAddiwProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -void require_legal_encoding(const Case &c) { - require((c.uimm12 & ~0x0fffU) == 0, std::string(c.name) + ": uimm12 exceeded 12 bits"); - require((c.src_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcL exceeded encoding width"); - require((c.dst_arch & ~0x1fU) == 0, std::string(c.name) + ": RegDst exceeded encoding width"); - const std::uint64_t insn = insn_for_case(c); - require(((insn >> 20) & 0x0fffU) == c.uimm12, std::string(c.name) + ": uimm12 encoding mismatch"); - require(((insn >> 15) & 0x1fU) == c.src_arch, std::string(c.name) + ": SrcL encoding mismatch"); - require(((insn >> 12) & 0x7U) == 0, std::string(c.name) + ": funct3 encoding mismatch"); - require(((insn >> 7) & 0x1fU) == c.dst_arch, std::string(c.name) + ": RegDst encoding mismatch"); - require(((insn >> 4) & 0x7U) == 0x3, std::string(c.name) + ": ADDIW low funct encoding mismatch"); - require(((insn >> 1) & 0x7U) == 0x2, std::string(c.name) + ": ADDIW opcode class encoding mismatch"); - require((insn & 0x1U) == 1, std::string(c.name) + ": instruction low valid bit mismatch"); -} - -void drive_case(VReducedScalarAluAddiwProbe &dut, const Case &c, std::uint64_t pc) { - require_legal_encoding(c); - idle(dut); - dut.io_inValid = 1; - dut.io_pc = pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_uimm12 = c.uimm12; - dut.io_src0Data = c.src; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_src0ArchTag = c.src_arch; - dut.io_src0PhysTag = c.src_phys; - dut.io_dstArchTag = c.dst_arch; - dut.io_dstPhysTag = c.dst_phys; - eval(dut); -} - -bool completion_identity_matches(VReducedScalarAluAddiwProbe &dut, const Case &c, std::uint64_t pc) { - const std::uint64_t expected = sail_addiw(c.src, c.uimm12); - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - dut.io_completeDstPhysValid && dut.io_completeDstPhysTag == c.dst_phys && - dut.io_completeDstData == expected && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == c.src_phys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == insn_for_case(c) && - dut.io_completeRowLen == 4 && dut.io_completeRowSrc0Valid && - dut.io_completeRowSrc0Reg == c.src_arch && dut.io_completeRowSrc0Data == c.src && - !dut.io_completeRowSrc1Valid && - dut.io_completeRowDstValid && dut.io_completeRowDstReg == c.dst_arch && - dut.io_completeRowDstData == expected && - dut.io_completeRowWbValid && dut.io_completeRowWbReg == c.dst_arch && - dut.io_completeRowWbData == expected; -} - -bool release_identity_matches(VReducedScalarAluAddiwProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -void require_future_green_row(VReducedScalarAluAddiwProbe &dut, const Case &c, std::uint64_t pc) { - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion/writeback identity mismatch"); - require(!dut.io_branchConditionValid, std::string(c.name) + ": unexpected branchConditionValid"); - require(dut.io_releaseValid, std::string(c.name) + ": missing releaseValid"); - require(release_identity_matches(dut, c), std::string(c.name) + ": release identity mismatch"); -} - -void drain_for_duplicates(VReducedScalarAluAddiwProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - if (dut.io_completeValid || dut.io_branchConditionValid || dut.io_releaseValid) { - fail(std::string(c.name) + ": duplicate completion/branch/release pulse before reset"); - } - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after drain"); -} - -void run_future_green_case(VReducedScalarAluAddiwProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 4ULL; - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - tick(dut); - idle(dut); - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, pc); - drain_for_duplicates(dut, c); - return; - } - if (dut.io_branchConditionValid) { - fail(std::string(c.name) + ": branchConditionValid without completeValid"); - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": accepted transaction produced no completion"); -} - -bool prove_first_addiw_current_red_or_future_green(VReducedScalarAluAddiwProbe &dut, const Case &c) { - reset(dut); - require(c.src_arch == 0 && c.src == 0 && c.uimm12 == 40, - "first transaction must be natural OP_ADDIW SrcL zero plus uimm12 40"); - drive_case(dut, c, kPcBase); - require(dut.io_inReady, "first-red OP_ADDIW input was not ready"); - require(dut.io_accepted, "first-red OP_ADDIW was not accepted"); - require(!dut.io_completeValid, "first-red OP_ADDIW completed in accept cycle"); - require(!dut.io_branchConditionValid, "first-red OP_ADDIW produced branch condition in accept cycle"); - tick(dut); - idle(dut); - bool observed_unsupported = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, kPcBase); - drain_for_duplicates(dut, c); - return true; - } - if (dut.io_branchConditionValid) { - fail("first OP_ADDIW produced branchConditionValid without completeValid"); - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == kOpAddiw); - tick(dut); - idle(dut); - } - require(observed_unsupported, "first-red OP_ADDIW was accepted but did not report unsupported opcode 63"); - require(!dut.io_busy, "first-red OP_ADDIW busy did not clear after unsupported drain"); - std::cerr << "backend-reduced-scalar-alu-addiw-probe: first-red accepted OP_ADDIW 63 SrcL zero uimm12 40 but observed unsupported/no completeValid/no branchConditionValid\n"; - std::exit(1); - return false; -} - -std::vector cases() { - return { - {"addiw_zero_plus_40_first_red", 0x0000000000000000ULL, 0x028, 0, 17, 1, 41, 3, false, 4, true, 5, false, 0x13000001U, 0xadd1000000000001ULL}, - {"addiw_sign_transition", 0x000000007fffffffULL, 0x001, 2, 18, 3, 42, 6, false, 7, false, 8, true, 0x13000002U, 0xadd1000000000002ULL}, - {"addiw_wrap_to_zero", 0x00000000ffffffffULL, 0x001, 4, 19, 5, 43, 9, true, 10, false, 11, true, 0x13000003U, 0xadd1000000000003ULL}, - {"addiw_ignores_high_source_bits", 0x1234567800000027ULL, 0x001, 6, 20, 7, 44, 12, false, 13, true, 14, false, 0x13000004U, 0xadd1000000000004ULL}, - {"addiw_max_uimm12", 0x000000007ffff001ULL, 0xfff, 8, 21, 9, 45, 15, true, 16, true, 17, false, 0x13000005U, 0xadd1000000000005ULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluAddiwProbe dut; - - const std::vector all_cases = cases(); - const bool first_case_completed = prove_first_addiw_current_red_or_future_green(dut, all_cases.front()); - require(first_case_completed, "first OP_ADDIW neither completed future-green nor exited at current first-red"); - for (unsigned idx = 1; idx < all_cases.size(); ++idx) { - run_future_green_case(dut, all_cases[idx], idx); - } - - std::cout << "backend-reduced-scalar-alu-addiw-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_hl_sdi_pr_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_hl_sdi_pr_probe_tb.cpp deleted file mode 100644 index c2633aec..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_hl_sdi_pr_probe_tb.cpp +++ /dev/null @@ -1,475 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluHlSdiPrProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpHlSdiPo = 216; -constexpr std::uint32_t kOpHlSdiPr = 217; -constexpr std::uint32_t kOpHlSdiUpr = 220; -constexpr std::uint32_t kOpSdi = 390; -constexpr std::uint64_t kPcBase = 0x0000000000017000ULL; -constexpr int kWaitCycles = 10; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint64_t raw; - std::int32_t simm; - std::uint64_t data; - std::uint64_t base; - std::uint8_t src_d_arch; - std::uint8_t src_d_phys; - std::uint8_t src_r_arch; - std::uint8_t src_r_phys; - bool dst_valid; - std::uint8_t dst_arch; - std::uint8_t dst_phys; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-hl-sdi-pr-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void eval(VReducedScalarAluHlSdiPrProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluHlSdiPrProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -std::uint64_t mask64(std::uint64_t value) { - return value; -} - -std::uint64_t scaled_simm17(std::int32_t simm) { - return mask64(static_cast(static_cast(simm)) << 3); -} - -std::uint64_t expected_pr_address(const Case &c) { - return mask64(c.base + scaled_simm17(c.simm)); -} - -std::uint64_t sdi_raw(std::uint8_t src_d, std::uint8_t src_r, std::int16_t simm) { - const std::uint16_t imm = static_cast(simm) & 0x0fffU; - return (static_cast((imm >> 5) & 0x7fU) << 25) | - (static_cast(src_d & 0x1fU) << 20) | - (static_cast(src_r & 0x1fU) << 15) | - (static_cast(imm & 0x1fU) << 7) | - 0x3059ULL; -} - -std::uint64_t hl_sdi_raw(std::uint32_t opcode, std::uint8_t dst, std::uint8_t src_d, - std::uint8_t src_r, std::int32_t simm) { - const std::uint32_t imm = static_cast(simm) & 0x1ffffU; - std::uint64_t fixed = 0; - switch (opcode) { - case kOpHlSdiPo: - fixed = 0x3059003eULL; - break; - case kOpHlSdiPr: - fixed = 0x3059002eULL; - break; - case kOpHlSdiUpr: - fixed = 0x7059002eULL; - break; - default: - fail("unsupported HL.SDI raw builder opcode"); - } - return fixed | - (static_cast(imm & 0x1fU) << 6) | - (static_cast(dst & 0x1fU) << 11) | - (static_cast((imm >> 5) & 0x1fU) << 23) | - (static_cast(src_d & 0x1fU) << 35) | - (static_cast(src_r & 0x1fU) << 40) | - (static_cast((imm >> 10) & 0x7fU) << 41); -} - -void idle(VReducedScalarAluHlSdiPrProbe &dut) { - dut.io_inValid = 0; - dut.io_flushValid = 0; - dut.io_opcode = kOpHlSdiPr; - dut.io_pc = 0; - dut.io_insnLen = 6; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_srcDData = 0; - dut.io_srcRData = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_srcDArchTag = 2; - dut.io_srcDPhysTag = 20; - dut.io_srcRArchTag = 3; - dut.io_srcRPhysTag = 21; - dut.io_dstValid = 1; - dut.io_dstArchTag = 4; - dut.io_dstPhysTag = 22; -} - -void reset(VReducedScalarAluHlSdiPrProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -void require_legal_hl_encoding(const Case &c) { - require(c.opcode == kOpHlSdiPr || c.opcode == kOpHlSdiPo || c.opcode == kOpHlSdiUpr, - std::string(c.name) + ": not an HL.SDI adjacency opcode"); - require((c.src_d_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcD exceeded encoding width"); - require((c.src_r_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcR exceeded encoding width"); - require((c.dst_arch & ~0x1fU) == 0, std::string(c.name) + ": RegDst exceeded encoding width"); - require((c.raw & 0xffff0000707f003fULL) != 0, std::string(c.name) + ": empty HL.SDI raw instruction"); -} - -void drive_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, std::uint64_t pc) { - if (c.opcode == kOpHlSdiPr || c.opcode == kOpHlSdiPo || c.opcode == kOpHlSdiUpr) { - require_legal_hl_encoding(c); - } - idle(dut); - dut.io_inValid = 1; - dut.io_opcode = c.opcode; - dut.io_pc = pc; - dut.io_insnLen = c.opcode == kOpSdi ? 4 : 6; - dut.io_insnRaw = c.raw; - dut.io_imm = static_cast(static_cast(c.simm)); - dut.io_srcDData = c.data; - dut.io_srcRData = c.base; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_srcDArchTag = c.src_d_arch; - dut.io_srcDPhysTag = c.src_d_phys; - dut.io_srcRArchTag = c.src_r_arch; - dut.io_srcRPhysTag = c.src_r_phys; - dut.io_dstValid = c.dst_valid ? 1 : 0; - dut.io_dstArchTag = c.dst_arch; - dut.io_dstPhysTag = c.dst_phys; - eval(dut); -} - -bool release_identity_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -bool completion_identity_matches(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, - std::uint64_t pc) { - const std::uint64_t expected_addr = c.opcode == kOpSdi - ? mask64(c.base + scaled_simm17(c.simm)) - : expected_pr_address(c); - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - dut.io_completeDstPhysValid == c.dst_valid && - (!c.dst_valid || (dut.io_completeDstPhysTag == c.dst_phys && - dut.io_completeDstData == expected_addr)) && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == c.src_d_phys && - dut.io_completeSrc1PhysValid && dut.io_completeSrc1PhysTag == c.src_r_phys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == c.raw && dut.io_completeRowLen == (c.opcode == kOpSdi ? 4 : 6) && - dut.io_completeRowSrc0Valid && dut.io_completeRowSrc0Reg == c.src_d_arch && - dut.io_completeRowSrc0Data == c.data && dut.io_completeRowSrc1Valid && - dut.io_completeRowSrc1Reg == c.src_r_arch && dut.io_completeRowSrc1Data == c.base && - dut.io_completeRowDstValid == c.dst_valid && dut.io_completeRowWbValid == c.dst_valid && - (!c.dst_valid || (dut.io_completeRowDstReg == c.dst_arch && - dut.io_completeRowDstData == expected_addr && - dut.io_completeRowWbReg == c.dst_arch && - dut.io_completeRowWbData == expected_addr)) && - dut.io_completeRowMemValid && dut.io_completeRowMemIsStore && - dut.io_completeRowMemAddr == expected_addr && - dut.io_completeRowMemWdata == c.data && dut.io_completeRowMemRdata == 0 && - dut.io_completeRowMemSize == 8; -} - -void require_no_forbidden_side_effects(VReducedScalarAluHlSdiPrProbe &dut, const std::string &name) { - require(!dut.io_loadLookupValid, name + ": unexpected load lookup"); - require(!dut.io_loadWaitHold, name + ": unexpected load wait hold"); - require(!dut.io_loadLiqEligible, name + ": unexpected LIQ eligibility"); - require(!dut.io_branchConditionValid, name + ": unexpected branch condition"); - require(!dut.io_redirectValid, name + ": unexpected redirect"); - require(!dut.io_liqReleaseValid, name + ": unexpected LIQ release"); -} - -void observe_future_green_pulses(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, - std::uint64_t pc, unsigned &completion_count, - unsigned &release_count) { - require_no_forbidden_side_effects(dut, c.name); - require(!dut.io_unsupported, std::string(c.name) + ": future-green path reported unsupported"); - if (dut.io_completeValid) { - require(completion_count == 0, std::string(c.name) + ": duplicate completion"); - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion identity or semantics mismatch"); - ++completion_count; - } - if (dut.io_releaseValid) { - require(release_count == 0, std::string(c.name) + ": duplicate release"); - require(release_identity_matches(dut, c), std::string(c.name) + ": release identity mismatch"); - ++release_count; - } -} - -void require_no_late_pulse(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - if (dut.io_completeValid || dut.io_releaseValid || dut.io_unsupported || - dut.io_branchConditionValid || dut.io_redirectValid || dut.io_liqReleaseValid || - dut.io_loadLookupValid || dut.io_completeRowValid) { - fail(std::string(c.name) + ": duplicate or forbidden late pulse after success"); - } -} - -void drain_for_duplicates(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - require_no_late_pulse(dut, c); - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after duplicate drain"); -} - -void run_future_green_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 8ULL; - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - require(!dut.io_completeValid, std::string(c.name) + ": completed in accept cycle"); - require_no_forbidden_side_effects(dut, c.name); - unsigned completion_count = 0; - unsigned release_count = 0; - observe_future_green_pulses(dut, c, pc, completion_count, release_count); - tick(dut); - idle(dut); - - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - observe_future_green_pulses(dut, c, pc, completion_count, release_count); - if (completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": future-green completion/release did not complete exactly once"); -} - -bool prove_current_red_or_future_green(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - reset(dut); - require(c.opcode == kOpHlSdiPr, "first transaction must be OP_HL_SDI_PR"); - drive_case(dut, c, kPcBase); - require(dut.io_inReady, "first-red OP_HL_SDI_PR input was not ready"); - require(dut.io_accepted, "first-red OP_HL_SDI_PR was not accepted"); - require(!dut.io_completeValid, "first-red OP_HL_SDI_PR completed in accept cycle"); - require_no_forbidden_side_effects(dut, "first-red OP_HL_SDI_PR accept cycle"); - tick(dut); - idle(dut); - - bool observed_unsupported = false; - unsigned completion_count = 0; - unsigned release_count = 0; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - require_no_forbidden_side_effects(dut, "first-red OP_HL_SDI_PR"); - if (dut.io_releaseValid) { - require(release_count == 0, "first-red OP_HL_SDI_PR duplicate release"); - require(release_identity_matches(dut, c), "first-red OP_HL_SDI_PR release identity mismatch"); - ++release_count; - } - if (dut.io_completeValid) { - require(!dut.io_unsupported, "first OP_HL_SDI_PR completed while unsupported"); - require(completion_count == 0, "first OP_HL_SDI_PR duplicate completion"); - require(completion_identity_matches(dut, c, kPcBase), "first OP_HL_SDI_PR future-green completion mismatch"); - ++completion_count; - } - if (completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return true; - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == kOpHlSdiPr); - tick(dut); - idle(dut); - } - - require(observed_unsupported, "accepted OP_HL_SDI_PR did not report delayed unsupported opcode 217"); - require(completion_count == 0, "unsupported OP_HL_SDI_PR produced a completion before product support"); - require(release_count == 1, "unsupported OP_HL_SDI_PR did not produce exactly one same-identity normal release"); - require(!dut.io_busy, "unsupported OP_HL_SDI_PR busy did not clear after delayed terminal"); - fail("accepted OP_HL_SDI_PR 217 reached delayed unsupported/no-completion/no-memory-row first-red"); - return false; -} - -void run_flush_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - reset(dut); - drive_case(dut, c, kPcBase + 0x200ULL); - require(dut.io_accepted, std::string(c.name) + ": flush case was not accepted"); - tick(dut); - idle(dut); - dut.io_flushValid = 1; - eval(dut); - require(!dut.io_completeValid && !dut.io_releaseValid && !dut.io_unsupported && - !dut.io_completeRowValid && !dut.io_loadLookupValid && !dut.io_liqReleaseValid, - std::string(c.name) + ": killed operation produced completion/release/unsupported pulse"); - tick(dut); - idle(dut); - eval(dut); - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after flush"); -} - -void run_backpressure_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c) { - reset(dut); - drive_case(dut, c, kPcBase + 0x208ULL); - require(dut.io_accepted, std::string(c.name) + ": first backpressure operation was not accepted"); - tick(dut); - Case other = c; - other.name = "hl_sdi_pr_backpressure_second_input"; - other.rid = static_cast((c.rid + 1U) & 0x3fU); - other.bid = static_cast((c.bid + 1U) & 0x3fU); - drive_case(dut, other, kPcBase + 0x210ULL); - require(!dut.io_accepted, std::string(c.name) + ": accepted a second input while first ownership was live"); - require(!dut.io_inReady, std::string(c.name) + ": reported ready while first ownership was live"); - tick(dut); - idle(dut); - - unsigned completion_count = 0; - unsigned release_count = 0; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - observe_future_green_pulses(dut, c, kPcBase + 0x208ULL, completion_count, release_count); - if (completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": backpressure case did not reach future-green completion"); -} - -void run_adjacent_unsupported_case(VReducedScalarAluHlSdiPrProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + 0x300ULL + static_cast(index) * 8ULL; - drive_case(dut, c, pc); - require(dut.io_accepted, std::string(c.name) + ": adjacent unsupported case was not accepted"); - tick(dut); - idle(dut); - bool observed_unsupported = false; - unsigned completion_count = 0; - unsigned release_count = 0; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - require_no_forbidden_side_effects(dut, c.name); - if (dut.io_completeValid || dut.io_completeRowValid) { - ++completion_count; - } - if (dut.io_releaseValid) { - require(release_count == 0, std::string(c.name) + ": duplicate release"); - require(release_identity_matches(dut, c), std::string(c.name) + ": release identity mismatch"); - ++release_count; - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == c.opcode); - tick(dut); - idle(dut); - } - require(observed_unsupported, std::string(c.name) + ": adjacent opcode did not report unsupported"); - require(completion_count == 0, std::string(c.name) + ": adjacent unsupported opcode completed"); - require(release_count == 1, std::string(c.name) + ": adjacent unsupported opcode did not release exactly once"); -} - -std::vector hl_pr_cases() { - return { - {"hl_sdi_pr_real_dhrystone_raw_minus16_first_red", kOpHlSdiPr, 0xfc15bfd90feeULL, -2, 0x1122334455667788ULL, 0x0000004000001000ULL, 2, 20, 28, 21, true, 1, 22, 21, false, 31, true, 10, false, 0x21700001U, 0x8510000000000001ULL}, - {"hl_sdi_pr_zero_offset_regdst_diff", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 5, 6, 7, 0), 0, 0xa5a55a5ac3c33c3cULL, 0x0000000000008000ULL, 6, 23, 7, 24, true, 5, 25, 22, true, 32, false, 11, true, 0x21700002U, 0x8510000000000002ULL}, - {"hl_sdi_pr_positive_offset", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 8, 9, 10, 31), 31, 0x0102030405060708ULL, 0x0000000000009000ULL, 9, 26, 10, 27, true, 8, 28, 23, false, 33, false, 12, true, 0x21700003U, 0x8510000000000003ULL}, - {"hl_sdi_pr_negative_boundary", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 11, 12, 13, -65536), -65536, 0xfedcba9876543210ULL, 0x0000000000100000ULL, 12, 29, 13, 30, true, 11, 31, 24, true, 34, true, 13, false, 0x21700004U, 0x8510000000000004ULL}, - {"hl_sdi_pr_positive_boundary_wrap_regdst_equals_base", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 16, 15, 16, 65535), 65535, 0x8877665544332211ULL, 0xfffffffffffffff8ULL, 15, 32, 16, 33, true, 16, 34, 25, false, 35, true, 14, true, 0x21700005U, 0x8510000000000005ULL}, - }; -} - -std::vector adjacent_cases() { - return { - {"hl_sdi_po_adjacent_still_unsupported", kOpHlSdiPo, hl_sdi_raw(kOpHlSdiPo, 3, 4, 5, 7), 7, 0x1111111111111111ULL, 0x2000ULL, 4, 35, 5, 36, true, 3, 37, 26, false, 36, false, 15, false, 0x21700006U, 0x8510000000000006ULL}, - {"hl_sdi_upr_adjacent_still_unsupported", kOpHlSdiUpr, hl_sdi_raw(kOpHlSdiUpr, 17, 18, 19, -9), -9, 0x2222222222222222ULL, 0x3000ULL, 18, 38, 19, 39, true, 17, 40, 27, true, 37, true, 16, true, 0x21700007U, 0x8510000000000007ULL}, - }; -} - -Case sdi_case() { - return {"sdi_existing_supported_scaled_store", kOpSdi, sdi_raw(3, 4, -4), -4, 0x7766554433221100ULL, 0x0000000000005000ULL, 3, 41, 4, 42, false, 0, 0, 28, false, 38, false, 17, false, 0x21700008U, 0x8510000000000008ULL}; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluHlSdiPrProbe dut; - - const std::vector pr_cases = hl_pr_cases(); - const bool first_case_completed = prove_current_red_or_future_green(dut, pr_cases.front()); - if (!first_case_completed) { - return 1; - } - for (unsigned idx = 1; idx < pr_cases.size(); ++idx) { - run_future_green_case(dut, pr_cases[idx], idx); - } - run_flush_case(dut, pr_cases[1]); - run_backpressure_case(dut, pr_cases[2]); - - unsigned adjacent_index = 0; - for (const Case &c : adjacent_cases()) { - run_adjacent_unsupported_case(dut, c, adjacent_index++); - } - run_future_green_case(dut, sdi_case(), 20); - - std::cout << "backend-reduced-scalar-alu-hl-sdi-pr-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_lbu_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_lbu_probe_tb.cpp deleted file mode 100644 index 621d22c1..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_lbu_probe_tb.cpp +++ /dev/null @@ -1,487 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluLbuProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpLbu = 346; -constexpr std::uint64_t kPcBase = 0x0000000000014800ULL; -constexpr int kWaitCycles = 10; -constexpr int kDuplicateDrainCycles = 8; - -enum class Ownership { - Direct, - Liq, -}; - -struct Case { - const char *name; - std::uint64_t base; - std::uint64_t offset; - std::uint8_t src_r_type; - std::uint8_t shamt; - std::uint8_t load_byte; - Ownership ownership; - bool wait_block_first; - bool liq_hold_first; - std::uint8_t src_l_arch; - std::uint8_t src_l_phys; - std::uint8_t src_r_arch; - std::uint8_t src_r_phys; - std::uint8_t dst_arch; - std::uint8_t dst_phys; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-lbu-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void eval(VReducedScalarAluLbuProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluLbuProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -std::uint64_t mask64(std::uint64_t value) { - return value; -} - -std::uint64_t sext32(std::uint64_t value) { - const std::uint32_t low = static_cast(value & 0xffffffffULL); - return static_cast(static_cast(static_cast(low))); -} - -std::uint64_t zext32(std::uint64_t value) { - return value & 0xffffffffULL; -} - -std::uint64_t modifier(std::uint64_t value, std::uint8_t src_r_type) { - switch (src_r_type & 0x3U) { - case 0: - return sext32(value); - case 1: - return zext32(value); - case 2: - return mask64(0ULL - value); - default: - return value; - } -} - -std::uint64_t expected_address(const Case &c) { - return mask64(c.base + mask64(modifier(c.offset, c.src_r_type) << c.shamt)); -} - -std::uint64_t expected_result(const Case &c) { - return static_cast(c.load_byte); -} - -std::uint64_t insn_for_case(const Case &c) { - return (static_cast(c.shamt & 0x1fU) << 27) | - (static_cast(c.src_r_type & 0x3U) << 25) | - (static_cast(c.src_r_arch & 0x1fU) << 20) | - (static_cast(c.src_l_arch & 0x1fU) << 15) | - (4ULL << 12) | - (static_cast(c.dst_arch & 0x1fU) << 7) | - 0x4009ULL; -} - -void idle(VReducedScalarAluLbuProbe &dut) { - dut.io_inValid = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_srcLData = 0; - dut.io_srcRData = 0; - dut.io_loadLookupData = 0; - dut.io_loadLookupWaitBlocked = 0; - dut.io_loadLiqEnable = 0; - dut.io_loadLiqAccepted = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_srcLArchTag = 0; - dut.io_srcLPhysTag = 16; - dut.io_srcRArchTag = 1; - dut.io_srcRPhysTag = 17; - dut.io_dstArchTag = 2; - dut.io_dstPhysTag = 40; -} - -void reset(VReducedScalarAluLbuProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -void require_legal_encoding(const Case &c) { - require((c.shamt & ~0x1fU) == 0, std::string(c.name) + ": shamt exceeded encoding width"); - require((c.src_r_type & ~0x3U) == 0, std::string(c.name) + ": SrcRType exceeded encoding width"); - require((c.src_l_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcL exceeded encoding width"); - require((c.src_r_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcR exceeded encoding width"); - require((c.dst_arch & ~0x1fU) == 0, std::string(c.name) + ": RegDst exceeded encoding width"); - const std::uint64_t insn = insn_for_case(c); - require(((insn >> 27) & 0x1fU) == c.shamt, std::string(c.name) + ": shamt encoding mismatch"); - require(((insn >> 25) & 0x3U) == c.src_r_type, std::string(c.name) + ": SrcRType encoding mismatch"); - require(((insn >> 20) & 0x1fU) == c.src_r_arch, std::string(c.name) + ": SrcR encoding mismatch"); - require(((insn >> 15) & 0x1fU) == c.src_l_arch, std::string(c.name) + ": SrcL encoding mismatch"); - require(((insn >> 12) & 0x7U) == 4, std::string(c.name) + ": LBU funct3 encoding mismatch"); - require(((insn >> 7) & 0x1fU) == c.dst_arch, std::string(c.name) + ": RegDst encoding mismatch"); - require((insn & 0x7fU) == 0x09, std::string(c.name) + ": LBU low value 0x4009 encoding mismatch"); -} - -void drive_case(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc) { - require_legal_encoding(c); - idle(dut); - dut.io_inValid = 1; - dut.io_pc = pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_srcLData = c.base; - dut.io_srcRData = c.offset; - dut.io_loadLookupData = c.load_byte; - dut.io_loadLiqEnable = c.ownership == Ownership::Liq ? 1 : 0; - dut.io_loadLiqAccepted = (c.ownership == Ownership::Liq && !c.liq_hold_first) ? 1 : 0; - dut.io_loadLookupWaitBlocked = (c.ownership == Ownership::Direct && c.wait_block_first) ? 1 : 0; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_srcLArchTag = c.src_l_arch; - dut.io_srcLPhysTag = c.src_l_phys; - dut.io_srcRArchTag = c.src_r_arch; - dut.io_srcRPhysTag = c.src_r_phys; - dut.io_dstArchTag = c.dst_arch; - dut.io_dstPhysTag = c.dst_phys; - eval(dut); -} - -void continue_case_inputs(VReducedScalarAluLbuProbe &dut, const Case &c, bool direct_wait, bool liq_accepted) { - dut.io_loadLookupData = c.load_byte; - dut.io_loadLookupWaitBlocked = direct_wait ? 1 : 0; - dut.io_loadLiqEnable = c.ownership == Ownership::Liq ? 1 : 0; - dut.io_loadLiqAccepted = liq_accepted ? 1 : 0; -} - -bool lookup_identity_matches(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc) { - return dut.io_loadLookupValid && dut.io_loadLookupAddr == expected_address(c) && - dut.io_loadLookupSize == 1 && !dut.io_loadLookupReturnSignExtend && - dut.io_loadLiqEligible && dut.io_loadLookupPc == pc && - dut.io_loadLookupBidValid && dut.io_loadLookupBidWrap == c.bid_wrap && - dut.io_loadLookupBidValue == c.bid && dut.io_loadLookupGidValid && - dut.io_loadLookupGidWrap == c.gid_wrap && dut.io_loadLookupGidValue == c.gid && - dut.io_loadLookupRidValid && dut.io_loadLookupRidWrap == c.rid_wrap && - dut.io_loadLookupRidValue == c.rid && dut.io_loadLookupLsId == c.lsid && - dut.io_loadLookupDstValid && dut.io_loadLookupDstArchTag == c.dst_arch && - dut.io_loadLookupDstPhysTag == c.dst_phys && dut.io_loadLookupSourceTraceValid && - dut.io_loadLookupSource0Valid && dut.io_loadLookupSource0Reg == c.src_l_arch && - dut.io_loadLookupSource0Data == c.base && dut.io_loadLookupSource1Valid && - dut.io_loadLookupSource1Reg == c.src_r_arch && dut.io_loadLookupSource1Data == c.offset; -} - -bool completion_identity_matches(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc) { - const std::uint64_t expected = expected_result(c); - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - dut.io_completeDstPhysValid && dut.io_completeDstPhysTag == c.dst_phys && - dut.io_completeDstData == expected && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == c.src_l_phys && - dut.io_completeSrc1PhysValid && dut.io_completeSrc1PhysTag == c.src_r_phys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == insn_for_case(c) && dut.io_completeRowLen == 4 && - dut.io_completeRowSrc0Valid && dut.io_completeRowSrc0Reg == c.src_l_arch && - dut.io_completeRowSrc0Data == c.base && dut.io_completeRowSrc1Valid && - dut.io_completeRowSrc1Reg == c.src_r_arch && dut.io_completeRowSrc1Data == c.offset && - dut.io_completeRowDstValid && dut.io_completeRowDstReg == c.dst_arch && - dut.io_completeRowDstData == expected && dut.io_completeRowWbValid && - dut.io_completeRowWbReg == c.dst_arch && dut.io_completeRowWbData == expected && - dut.io_completeRowMemValid && !dut.io_completeRowMemIsStore && - dut.io_completeRowMemAddr == expected_address(c) && - dut.io_completeRowMemRdata == expected && dut.io_completeRowMemSize == 1; -} - -bool release_identity_matches(VReducedScalarAluLbuProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -bool liq_release_identity_matches(VReducedScalarAluLbuProbe &dut, const Case &c) { - return dut.io_liqReleaseBidValid && dut.io_liqReleaseBidWrap == c.bid_wrap && - dut.io_liqReleaseBidValue == c.bid && dut.io_liqReleaseRidValid && - dut.io_liqReleaseRidWrap == c.rid_wrap && dut.io_liqReleaseRidValue == c.rid && - dut.io_liqReleaseStid == 0; -} - -void require_no_sideband_duplicate(VReducedScalarAluLbuProbe &dut, const Case &c) { - if (dut.io_completeValid || dut.io_branchConditionValid || dut.io_releaseValid || dut.io_liqReleaseValid) { - fail(std::string(c.name) + ": duplicate completion/branch/direct release/LIQ release pulse"); - } -} - -void observe_direct_pulses(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc, - unsigned &completion_count, unsigned &release_count) { - if (dut.io_completeValid) { - require(completion_count == 0, std::string(c.name) + ": duplicate direct completion before success"); - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion/writeback identity mismatch"); - require(!dut.io_branchConditionValid, std::string(c.name) + ": unexpected branchConditionValid"); - ++completion_count; - } - if (dut.io_releaseValid) { - require(release_count == 0, std::string(c.name) + ": duplicate direct release before success"); - require(release_identity_matches(dut, c), std::string(c.name) + ": direct release identity mismatch"); - ++release_count; - } - require(!dut.io_liqReleaseValid, std::string(c.name) + ": direct case produced LIQ release"); -} - -void observe_liq_pulses(VReducedScalarAluLbuProbe &dut, const Case &c, unsigned &liq_release_count) { - if (dut.io_liqReleaseValid) { - require(liq_release_count == 0, std::string(c.name) + ": duplicate LIQ release before success"); - require(liq_release_identity_matches(dut, c), std::string(c.name) + ": LIQ release identity mismatch"); - ++liq_release_count; - } - require(!dut.io_completeValid, std::string(c.name) + ": LIQ case produced direct completion"); - require(!dut.io_releaseValid, std::string(c.name) + ": LIQ case produced direct release"); - require(!dut.io_branchConditionValid, std::string(c.name) + ": unexpected branchConditionValid"); -} - -void drain_for_duplicates(VReducedScalarAluLbuProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - require_no_sideband_duplicate(dut, c); - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after duplicate drain"); -} - -void run_direct_future_green_case(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc) { - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - require(!dut.io_completeValid, std::string(c.name) + ": completed in accept cycle"); - unsigned completion_count = 0; - unsigned release_count = 0; - observe_direct_pulses(dut, c, pc, completion_count, release_count); - tick(dut); - idle(dut); - - if (c.wait_block_first) { - continue_case_inputs(dut, c, true, false); - eval(dut); - require(dut.io_loadWaitHold, std::string(c.name) + ": missing direct load wait hold"); - require(lookup_identity_matches(dut, c, pc), std::string(c.name) + ": lookup identity changed under wait hold"); - require(!dut.io_completeValid && !dut.io_releaseValid && !dut.io_liqReleaseValid, - std::string(c.name) + ": early completion or release during direct wait hold"); - observe_direct_pulses(dut, c, pc, completion_count, release_count); - tick(dut); - idle(dut); - } - - bool saw_lookup = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - continue_case_inputs(dut, c, false, false); - eval(dut); - if (dut.io_loadLookupValid) { - saw_lookup = true; - require(lookup_identity_matches(dut, c, pc), std::string(c.name) + ": lookup identity mismatch"); - } - observe_direct_pulses(dut, c, pc, completion_count, release_count); - if (saw_lookup && completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": direct future-green lookup/completion/release did not complete"); -} - -void run_liq_future_green_case(VReducedScalarAluLbuProbe &dut, const Case &c, std::uint64_t pc) { - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - unsigned liq_release_count = 0; - observe_liq_pulses(dut, c, liq_release_count); - tick(dut); - idle(dut); - - if (c.liq_hold_first) { - continue_case_inputs(dut, c, false, false); - eval(dut); - require(dut.io_loadWaitHold, std::string(c.name) + ": missing LIQ acceptance hold"); - require(lookup_identity_matches(dut, c, pc), std::string(c.name) + ": lookup identity changed during LIQ hold"); - require(!dut.io_completeValid && !dut.io_releaseValid && !dut.io_liqReleaseValid, - std::string(c.name) + ": early completion or release before LIQ accepts"); - observe_liq_pulses(dut, c, liq_release_count); - tick(dut); - idle(dut); - } - - bool saw_lookup = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - continue_case_inputs(dut, c, false, true); - eval(dut); - if (dut.io_loadLookupValid) { - saw_lookup = true; - require(lookup_identity_matches(dut, c, pc), std::string(c.name) + ": lookup identity mismatch"); - } - observe_liq_pulses(dut, c, liq_release_count); - if (saw_lookup && liq_release_count == 1) { - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": LIQ future-green lookup/release did not complete"); -} - -void run_future_green_case(VReducedScalarAluLbuProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 4ULL; - if (c.ownership == Ownership::Direct) { - run_direct_future_green_case(dut, c, pc); - } else { - run_liq_future_green_case(dut, c, pc); - } -} - -bool prove_first_lbu_current_red_or_future_green(VReducedScalarAluLbuProbe &dut, const Case &c) { - reset(dut); - require(c.base == 0 && c.offset == 0 && c.load_byte == 0 && c.src_r_type == 3 && c.shamt == 0, - "first transaction must be architecture-generic OP_LBU zero-base zero-offset zero-byte"); - drive_case(dut, c, kPcBase); - require(dut.io_inReady, "first-red OP_LBU input was not ready"); - require(dut.io_accepted, "first-red OP_LBU was not accepted"); - require(!dut.io_completeValid, "first-red OP_LBU completed in accept cycle"); - require(!dut.io_branchConditionValid, "first-red OP_LBU produced branch condition in accept cycle"); - unsigned observed_direct_release_count = 0; - if (dut.io_releaseValid) { - require(release_identity_matches(dut, c), "first-red OP_LBU direct release identity mismatch"); - ++observed_direct_release_count; - } - tick(dut); - idle(dut); - - bool observed_unsupported = false; - bool observed_lookup = false; - unsigned observed_completion_count = 0; - bool observed_liq_release = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - continue_case_inputs(dut, c, false, false); - eval(dut); - observed_lookup = observed_lookup || dut.io_loadLookupValid; - observed_liq_release = observed_liq_release || dut.io_liqReleaseValid; - if (dut.io_releaseValid) { - require(release_identity_matches(dut, c), "first-red OP_LBU direct release identity mismatch"); - require(observed_direct_release_count == 0, "first-red OP_LBU produced duplicate direct release"); - ++observed_direct_release_count; - } - if (dut.io_completeValid) { - require(lookup_identity_matches(dut, c, kPcBase), "first OP_LBU future-green missing lookup identity"); - require(completion_identity_matches(dut, c, kPcBase), "first OP_LBU future-green completion mismatch"); - require(observed_completion_count == 0, "first OP_LBU future-green duplicate completion"); - ++observed_completion_count; - } - if (dut.io_branchConditionValid) { - fail("first OP_LBU produced branchConditionValid"); - } - if (observed_lookup && observed_completion_count == 1 && observed_direct_release_count == 1) { - drain_for_duplicates(dut, c); - return true; - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == kOpLbu); - tick(dut); - idle(dut); - } - require(observed_unsupported, "first-red OP_LBU was accepted but did not report unsupported opcode 346"); - require(!observed_lookup, "first-red OP_LBU produced a load lookup before product support"); - require(observed_completion_count == 0, "first-red OP_LBU produced a completion before product support"); - require(!observed_liq_release, "first-red OP_LBU produced LIQ release before product support"); - require(observed_direct_release_count == 1, "first-red OP_LBU did not produce exactly one normal direct issue release"); - require(!dut.io_busy, "first-red OP_LBU busy did not clear after unsupported drain"); - std::cerr << "backend-reduced-scalar-alu-lbu-probe: first-red accepted OP_LBU 346 but observed unsupported/no loadLookup/no completeValid/exactly-one normal direct release/no LIQ release\n"; - std::exit(1); - return false; -} - -std::vector cases() { - return { - {"lbu_zero_addr_zero_byte_direct_first_red", 0x0000000000000000ULL, 0x0000000000000000ULL, 3, 0, 0x00, Ownership::Direct, false, false, 0, 16, 1, 17, 2, 40, 3, false, 4, true, 5, false, 0x14800001U, 0x1b00000000000001ULL}, - {"lbu_nonzero_base_zero_offset_high_byte_direct_wait", 0x0000000000004080ULL, 0x0000000000000000ULL, 0, 1, 0x80, Ownership::Direct, true, false, 3, 18, 4, 19, 5, 41, 6, false, 7, false, 8, true, 0x14800002U, 0x1b00000000000002ULL}, - {"lbu_nonzero_addr_zero_byte_direct_zext32", 0x0000000000005000ULL, 0x0000000000000024ULL, 1, 0, 0x00, Ownership::Direct, false, false, 6, 20, 7, 21, 8, 42, 9, true, 10, false, 11, true, 0x14800003U, 0x1b00000000000003ULL}, - {"lbu_nonzero_addr_high_byte_direct_neg", 0x0000000000006100ULL, 0xffffffffffffffffULL, 2, 0, 0xff, Ownership::Direct, false, false, 9, 22, 10, 23, 11, 43, 12, false, 13, true, 14, false, 0x14800004U, 0x1b00000000000004ULL}, - {"lbu_srcrtype_unchanged_shamt_nonzero_direct", 0x0000000000006000ULL, 0x000000000000007fULL, 3, 1, 0x81, Ownership::Direct, false, false, 12, 24, 13, 25, 14, 44, 15, true, 16, true, 17, false, 0x14800005U, 0x1b00000000000005ULL}, - {"lbu_zero_addr_zero_byte_liq_hold", 0x0000000000000000ULL, 0x0000000000000000ULL, 3, 0, 0x00, Ownership::Liq, false, true, 1, 26, 2, 27, 3, 45, 18, false, 19, false, 20, true, 0x14800006U, 0x1b00000000000006ULL}, - {"lbu_nonzero_base_zero_offset_high_byte_liq", 0x0000000000004080ULL, 0x0000000000000000ULL, 0, 1, 0x80, Ownership::Liq, false, false, 4, 28, 5, 29, 6, 46, 21, true, 22, false, 23, true, 0x14800007U, 0x1b00000000000007ULL}, - {"lbu_nonzero_addr_zero_byte_liq_zext32", 0x0000000000005000ULL, 0x0000000000000024ULL, 1, 0, 0x00, Ownership::Liq, false, false, 7, 30, 8, 31, 9, 47, 24, false, 25, true, 26, false, 0x14800008U, 0x1b00000000000008ULL}, - {"lbu_nonzero_addr_high_byte_liq_neg", 0x0000000000006100ULL, 0xffffffffffffffffULL, 2, 0, 0xff, Ownership::Liq, false, false, 10, 32, 11, 33, 12, 48, 27, true, 28, true, 29, false, 0x14800009U, 0x1b00000000000009ULL}, - {"lbu_srcrtype_unchanged_shamt_nonzero_liq", 0x0000000000006000ULL, 0x000000000000007fULL, 3, 1, 0x81, Ownership::Liq, false, false, 13, 34, 14, 35, 15, 49, 30, false, 31, false, 32, true, 0x1480000aU, 0x1b0000000000000aULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluLbuProbe dut; - - const std::vector all_cases = cases(); - const bool first_case_completed = prove_first_lbu_current_red_or_future_green(dut, all_cases.front()); - require(first_case_completed, "first OP_LBU neither completed future-green nor exited at current first-red"); - for (unsigned idx = 1; idx < all_cases.size(); ++idx) { - run_future_green_case(dut, all_cases[idx], idx); - } - - std::cout << "backend-reduced-scalar-alu-lbu-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_sb_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_sb_probe_tb.cpp deleted file mode 100644 index c5e9bd56..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_sb_probe_tb.cpp +++ /dev/null @@ -1,415 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluSbProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpSb = 386; -constexpr std::uint64_t kPcBase = 0x0000000000015800ULL; -constexpr int kWaitCycles = 10; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint64_t data; - std::uint64_t base; - std::uint64_t offset; - std::uint8_t src_r_type; - std::uint8_t src_d_arch; - std::uint8_t src_d_phys; - std::uint8_t src_l_arch; - std::uint8_t src_l_phys; - std::uint8_t src_r_arch; - std::uint8_t src_r_phys; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-sb-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -bool explicit_current_inversion() { - const char *value = std::getenv("EXPECT_CURRENT_UNSUPPORTED"); - return value != nullptr && std::string(value) == "1"; -} - -void eval(VReducedScalarAluSbProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluSbProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -std::uint64_t sext32(std::uint64_t value) { - const std::uint32_t low = static_cast(value & 0xffffffffULL); - return static_cast(static_cast(static_cast(low))); -} - -std::uint64_t zext32(std::uint64_t value) { - return value & 0xffffffffULL; -} - -std::uint64_t modifier(std::uint64_t value, std::uint8_t src_r_type) { - switch (src_r_type & 0x3U) { - case 0: - return sext32(value); - case 1: - return zext32(value); - case 2: - return 0ULL - value; - default: - return value; - } -} - -std::uint64_t expected_address(const Case &c) { - return c.base + modifier(c.offset, c.src_r_type); -} - -std::uint64_t expected_wdata(const Case &c) { - return c.data & 0xffULL; -} - -std::uint64_t insn_for_case(const Case &c) { - return (static_cast(c.src_d_arch & 0x1fU) << 27) | - (static_cast(c.src_r_type & 0x3U) << 25) | - (static_cast(c.src_r_arch & 0x1fU) << 20) | - (static_cast(c.src_l_arch & 0x1fU) << 15) | - 0x49ULL; -} - -void idle(VReducedScalarAluSbProbe &dut) { - dut.io_inValid = 0; - dut.io_flushValid = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_srcDData = 0; - dut.io_srcLData = 0; - dut.io_srcRData = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_srcDArchTag = 1; - dut.io_srcDPhysTag = 20; - dut.io_srcLArchTag = 2; - dut.io_srcLPhysTag = 21; - dut.io_srcRArchTag = 3; - dut.io_srcRPhysTag = 22; -} - -void reset(VReducedScalarAluSbProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -void require_legal_encoding(const Case &c) { - require((c.src_r_type & ~0x3U) == 0, std::string(c.name) + ": SrcRType exceeded encoding width"); - require((c.src_d_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcD exceeded encoding width"); - require((c.src_l_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcL exceeded encoding width"); - require((c.src_r_arch & ~0x1fU) == 0, std::string(c.name) + ": SrcR exceeded encoding width"); - const std::uint64_t insn = insn_for_case(c); - require(((insn >> 25) & 0x3U) == c.src_r_type, std::string(c.name) + ": SrcRType encoding mismatch"); - require(((insn >> 20) & 0x1fU) == c.src_r_arch, std::string(c.name) + ": SrcR encoding mismatch"); - require(((insn >> 15) & 0x1fU) == c.src_l_arch, std::string(c.name) + ": SrcL encoding mismatch"); - require(((insn >> 27) & 0x1fU) == c.src_d_arch, std::string(c.name) + ": SrcD encoding mismatch"); - require((insn & 0x7fffU) == 0x49, std::string(c.name) + ": OP_SB low fixed pattern 0x49 encoding mismatch"); -} - -void drive_case(VReducedScalarAluSbProbe &dut, const Case &c, std::uint64_t pc) { - require_legal_encoding(c); - idle(dut); - dut.io_inValid = 1; - dut.io_pc = pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_srcDData = c.data; - dut.io_srcLData = c.base; - dut.io_srcRData = c.offset; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_srcDArchTag = c.src_d_arch; - dut.io_srcDPhysTag = c.src_d_phys; - dut.io_srcLArchTag = c.src_l_arch; - dut.io_srcLPhysTag = c.src_l_phys; - dut.io_srcRArchTag = c.src_r_arch; - dut.io_srcRPhysTag = c.src_r_phys; - eval(dut); -} - -bool release_identity_matches(VReducedScalarAluSbProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -bool completion_identity_matches(VReducedScalarAluSbProbe &dut, const Case &c, std::uint64_t pc) { - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - !dut.io_completeDstPhysValid && dut.io_completeDstData == 0 && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == c.src_d_phys && - dut.io_completeSrc1PhysValid && dut.io_completeSrc1PhysTag == c.src_l_phys && - dut.io_completeSrc2PhysValid && dut.io_completeSrc2PhysTag == c.src_r_phys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == insn_for_case(c) && dut.io_completeRowLen == 4 && - dut.io_completeRowSrc0Valid && dut.io_completeRowSrc0Reg == c.src_d_arch && - dut.io_completeRowSrc0Data == c.data && dut.io_completeRowSrc1Valid && - dut.io_completeRowSrc1Reg == c.src_l_arch && dut.io_completeRowSrc1Data == c.base && - !dut.io_completeRowDstValid && !dut.io_completeRowWbValid && - dut.io_completeRowMemValid && dut.io_completeRowMemIsStore && - dut.io_completeRowMemAddr == expected_address(c) && - (dut.io_completeRowMemWdata & 0xffULL) == expected_wdata(c) && - (dut.io_completeRowMemWdata & ~0xffULL) == 0 && - dut.io_completeRowMemRdata == 0 && dut.io_completeRowMemSize == 1; -} - -void require_no_forbidden_side_effects(VReducedScalarAluSbProbe &dut, const std::string &name) { - require(!dut.io_loadLookupValid, name + ": unexpected load lookup"); - require(!dut.io_loadWaitHold, name + ": unexpected load wait hold"); - require(!dut.io_loadLiqEligible, name + ": unexpected LIQ eligibility"); - require(!dut.io_branchConditionValid, name + ": unexpected branch condition"); - require(!dut.io_redirectValid, name + ": unexpected redirect"); - require(!dut.io_liqReleaseValid, name + ": unexpected LIQ release"); -} - -void observe_future_green_pulses(VReducedScalarAluSbProbe &dut, const Case &c, std::uint64_t pc, - unsigned &completion_count, unsigned &release_count) { - require_no_forbidden_side_effects(dut, c.name); - require(!dut.io_unsupported, std::string(c.name) + ": future-green path reported unsupported"); - if (dut.io_completeValid) { - require(completion_count == 0, std::string(c.name) + ": duplicate completion before success"); - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion store-row identity mismatch"); - ++completion_count; - } - if (dut.io_releaseValid) { - require(release_count == 0, std::string(c.name) + ": duplicate normal release before success"); - require(release_identity_matches(dut, c), std::string(c.name) + ": normal release identity mismatch"); - ++release_count; - } -} - -void require_no_late_pulse(VReducedScalarAluSbProbe &dut, const Case &c) { - if (dut.io_completeValid || dut.io_releaseValid || dut.io_unsupported || - dut.io_branchConditionValid || dut.io_redirectValid || dut.io_liqReleaseValid || - dut.io_loadLookupValid || dut.io_completeRowValid) { - fail(std::string(c.name) + ": duplicate or forbidden late pulse after success"); - } -} - -void drain_for_duplicates(VReducedScalarAluSbProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - require_no_late_pulse(dut, c); - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after duplicate drain"); -} - -void run_future_green_case(VReducedScalarAluSbProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 4ULL; - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - require(!dut.io_completeValid, std::string(c.name) + ": completed in accept cycle"); - require_no_forbidden_side_effects(dut, c.name); - unsigned completion_count = 0; - unsigned release_count = 0; - observe_future_green_pulses(dut, c, pc, completion_count, release_count); - tick(dut); - idle(dut); - - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - observe_future_green_pulses(dut, c, pc, completion_count, release_count); - if (completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": OP_SB future-green completion/release did not complete exactly once"); -} - -bool prove_first_sb_current_red_or_future_green(VReducedScalarAluSbProbe &dut, const Case &c) { - reset(dut); - require(c.data == 0 && c.base == 0 && c.offset == 0 && c.src_r_type == 0, - "first transaction must be architecture-generic zero OP_SB sext32 case"); - drive_case(dut, c, kPcBase); - require(dut.io_inReady, "first-red OP_SB input was not ready"); - require(dut.io_accepted, "first-red OP_SB was not accepted"); - require(!dut.io_completeValid, "first-red OP_SB completed in accept cycle"); - require_no_forbidden_side_effects(dut, "first-red OP_SB accept cycle"); - unsigned release_count = 0; - if (dut.io_releaseValid) { - require(release_identity_matches(dut, c), "first-red OP_SB normal release identity mismatch"); - ++release_count; - } - tick(dut); - idle(dut); - - bool observed_unsupported = false; - unsigned completion_count = 0; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - require_no_forbidden_side_effects(dut, "first-red OP_SB"); - if (dut.io_releaseValid) { - require(release_count == 0, "first-red OP_SB duplicate normal release"); - require(release_identity_matches(dut, c), "first-red OP_SB normal release identity mismatch"); - ++release_count; - } - if (dut.io_completeValid) { - require(!dut.io_unsupported, "first OP_SB future-green completed while unsupported"); - require(completion_count == 0, "first OP_SB future-green duplicate completion"); - require(completion_identity_matches(dut, c, kPcBase), "first OP_SB future-green completion mismatch"); - ++completion_count; - } - if (completion_count == 1 && release_count == 1) { - drain_for_duplicates(dut, c); - return true; - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == kOpSb); - tick(dut); - idle(dut); - } - - require(observed_unsupported, "first-red OP_SB was accepted but did not report unsupported opcode 386"); - require(completion_count == 0, "first-red OP_SB produced a completion before product support"); - require(release_count == 1, "first-red OP_SB did not produce exactly one same-identity normal release"); - require(!dut.io_busy, "first-red OP_SB busy did not clear after unsupported drain"); - if (!explicit_current_inversion()) { - fail("first-red accepted OP_SB 386 reported unsupported/no completion/no memory row; rerun with EXPECT_CURRENT_UNSUPPORTED=1 only for current-red inversion"); - } - std::cerr << "backend-reduced-scalar-alu-sb-probe: first-red accepted OP_SB 386 but observed unsupported/no completeValid/no memory row/exactly-one normal direct release/no load/branch/LIQ/writeback\n"; - return false; -} - -void run_flush_case(VReducedScalarAluSbProbe &dut, const Case &c) { - reset(dut); - drive_case(dut, c, kPcBase + 0x100ULL); - require(dut.io_accepted, std::string(c.name) + ": flush case was not accepted"); - tick(dut); - idle(dut); - dut.io_flushValid = 1; - eval(dut); - require(!dut.io_completeValid && !dut.io_releaseValid && !dut.io_unsupported && - !dut.io_completeRowValid && !dut.io_loadLookupValid && !dut.io_liqReleaseValid, - std::string(c.name) + ": killed operation produced completion/release/unsupported pulse"); - tick(dut); - idle(dut); - eval(dut); - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after flush"); -} - -void run_backpressure_case(VReducedScalarAluSbProbe &dut, const Case &c) { - reset(dut); - drive_case(dut, c, kPcBase + 0x104ULL); - require(dut.io_accepted, std::string(c.name) + ": first backpressure operation was not accepted"); - tick(dut); - Case other = c; - other.name = "sb_backpressure_second_input"; - other.rid = static_cast((c.rid + 1U) & 0x3fU); - drive_case(dut, other, kPcBase + 0x108ULL); - require(!dut.io_accepted, std::string(c.name) + ": accepted a second OP_SB while first ownership was live"); - require(!dut.io_inReady, std::string(c.name) + ": reported ready while first ownership was live"); - tick(dut); - idle(dut); - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_releaseValid) { - require(release_identity_matches(dut, c), std::string(c.name) + ": release changed identity under backpressure"); - } - if (dut.io_completeValid) { - require(completion_identity_matches(dut, c, kPcBase + 0x104ULL), - std::string(c.name) + ": completion changed identity under backpressure"); - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - if (!explicit_current_inversion()) { - fail(std::string(c.name) + ": backpressure case did not reach future-green completion"); - } -} - -std::vector cases() { - return { - {"sb_zero_addr_zero_data_sext32_first_red", 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0, 1, 20, 2, 21, 3, 22, 3, false, 4, true, 5, false, 0x15800001U, 0x2b00000000000001ULL}, - {"sb_nonzero_base_zero_offset_high_bit_raw", 0x0000000000000080ULL, 0x0000000000004100ULL, 0x0000000000000000ULL, 3, 4, 23, 5, 24, 6, 25, 6, true, 7, false, 8, true, 0x15800002U, 0x2b00000000000002ULL}, - {"sb_sign_extend_negative_offset_ff_data", 0xffff0000000000ffULL, 0x0000000000005000ULL, 0x00000000fffffff8ULL, 0, 7, 26, 8, 27, 9, 28, 9, false, 10, false, 11, true, 0x15800003U, 0x2b00000000000003ULL}, - {"sb_zero_extend_offset_upper_ignored", 0x1234567800000001ULL, 0x0000000000006000ULL, 0xffffffff00000024ULL, 1, 10, 29, 11, 30, 12, 31, 12, true, 13, true, 14, false, 0x15800004U, 0x2b00000000000004ULL}, - {"sb_negated_offset_wrap_data_80", 0x8000000000000080ULL, 0xfffffffffffffff0ULL, 0x0000000000000020ULL, 2, 13, 32, 14, 33, 15, 34, 15, false, 16, false, 17, true, 0x15800005U, 0x2b00000000000005ULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluSbProbe dut; - - const std::vector all_cases = cases(); - const bool first_case_completed = prove_first_sb_current_red_or_future_green(dut, all_cases.front()); - if (!first_case_completed) { - return 0; - } - for (unsigned idx = 1; idx < all_cases.size(); ++idx) { - run_future_green_case(dut, all_cases[idx], idx); - } - run_flush_case(dut, all_cases[1]); - run_backpressure_case(dut, all_cases[2]); - - std::cout << "backend-reduced-scalar-alu-sb-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_setc_compare_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_setc_compare_probe_tb.cpp deleted file mode 100644 index edc56f9a..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_setc_compare_probe_tb.cpp +++ /dev/null @@ -1,330 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluSetcCompareProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpSetcEq = 328; -constexpr std::uint32_t kOpSetcGe = 330; -constexpr std::uint32_t kOpSetcGeu = 332; -constexpr std::uint32_t kOpSetcLt = 334; -constexpr std::uint32_t kOpSetcLtu = 336; -constexpr std::uint32_t kOpSetcNe = 338; -constexpr std::uint64_t kPcBase = 0x0000000000012000ULL; -constexpr std::uint8_t kSrc0Arch = 5; -constexpr std::uint8_t kSrc1Arch = 6; -constexpr std::uint8_t kSrc0Phys = 17; -constexpr std::uint8_t kSrc1Phys = 18; -constexpr int kWaitCycles = 8; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint64_t lhs; - std::uint64_t rhs; - std::uint8_t src_r_type; - bool expected; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-setc-compare-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void eval(VReducedScalarAluSetcCompareProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluSetcCompareProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -void idle(VReducedScalarAluSetcCompareProbe &dut) { - dut.io_inValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_src0Data = 0; - dut.io_src1Data = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_src0ArchTag = kSrc0Arch; - dut.io_src0PhysTag = kSrc0Phys; - dut.io_src1ArchTag = kSrc1Arch; - dut.io_src1PhysTag = kSrc1Phys; -} - -void reset(VReducedScalarAluSetcCompareProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -std::uint64_t sanitize_rhs(std::uint8_t src_r_type, std::uint64_t rhs) { - switch (src_r_type & 0x3) { - case 0: - return rhs; - case 1: - return static_cast(static_cast(static_cast(rhs & 0xffffffffULL))); - case 2: - return rhs & 0xffffffffULL; - default: - return rhs; - } -} - -bool sail_condition(std::uint32_t opcode, std::uint64_t lhs, std::uint64_t rhs, std::uint8_t src_r_type) { - const std::uint64_t converted_rhs = sanitize_rhs(src_r_type, rhs); - switch (opcode) { - case kOpSetcEq: - return lhs == converted_rhs; - case kOpSetcNe: - return lhs != converted_rhs; - case kOpSetcLt: - return static_cast(lhs) < static_cast(converted_rhs); - case kOpSetcGe: - return static_cast(lhs) >= static_cast(converted_rhs); - case kOpSetcLtu: - return lhs < converted_rhs; - case kOpSetcGeu: - return lhs >= converted_rhs; - default: - fail("unknown SETC opcode in Sail oracle"); - return false; - } -} - -std::uint64_t opcode_match(std::uint32_t opcode) { - switch (opcode) { - case kOpSetcEq: - return 0x00000065ULL; - case kOpSetcNe: - return 0x00001065ULL; - case kOpSetcLt: - return 0x00004065ULL; - case kOpSetcGe: - return 0x00005065ULL; - case kOpSetcLtu: - return 0x00006065ULL; - case kOpSetcGeu: - return 0x00007065ULL; - default: - fail("unknown SETC opcode while constructing legal instruction"); - return 0; - } -} - -std::uint64_t insn_for_case(const Case &c) { - return opcode_match(c.opcode) | - (static_cast(c.src_r_type & 0x3) << 25) | - (static_cast(kSrc1Arch & 0x1f) << 20) | - (static_cast(kSrc0Arch & 0x1f) << 15); -} - -void drive_case(VReducedScalarAluSetcCompareProbe &dut, const Case &c, std::uint64_t pc) { - idle(dut); - dut.io_inValid = 1; - dut.io_opcode = c.opcode; - dut.io_pc = pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_src0Data = c.lhs; - dut.io_src1Data = c.rhs; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_src0ArchTag = kSrc0Arch; - dut.io_src0PhysTag = kSrc0Phys; - dut.io_src1ArchTag = kSrc1Arch; - dut.io_src1PhysTag = kSrc1Phys; - eval(dut); -} - -void require_no_success_pulses(VReducedScalarAluSetcCompareProbe &dut, const std::string &context) { - require(!dut.io_completeValid, context + ": unexpected completeValid"); - require(!dut.io_branchConditionValid, context + ": unexpected branchConditionValid"); -} - -bool completion_identity_matches(VReducedScalarAluSetcCompareProbe &dut, const Case &c, std::uint64_t pc) { - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - !dut.io_completeDstPhysValid && dut.io_completeDstData == 0 && - dut.io_completeSrc0PhysValid && dut.io_completeSrc0PhysTag == kSrc0Phys && - dut.io_completeSrc1PhysValid && dut.io_completeSrc1PhysTag == kSrc1Phys && - dut.io_completeRowValid && dut.io_completeRowBid == c.bid && - dut.io_completeRowGid == c.gid && dut.io_completeRowRid == c.rid && - dut.io_completeRowRobValid && dut.io_completeRowRobWrap == c.rid_wrap && - dut.io_completeRowRobValue == c.rid && dut.io_completeRowBlockBidValid && - dut.io_completeRowBlockBid == c.block_bid && dut.io_completeRowPc == pc && - dut.io_completeRowInsn == insn_for_case(c) && - dut.io_completeRowLen == 4 && dut.io_completeRowSrc0Valid && - dut.io_completeRowSrc0Reg == kSrc0Arch && dut.io_completeRowSrc0Data == c.lhs && - dut.io_completeRowSrc1Valid && dut.io_completeRowSrc1Reg == kSrc1Arch && - dut.io_completeRowSrc1Data == c.rhs && !dut.io_completeRowDstValid && - !dut.io_completeRowWbValid; -} - -bool release_identity_matches(VReducedScalarAluSetcCompareProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -void require_future_green_row(VReducedScalarAluSetcCompareProbe &dut, const Case &c, std::uint64_t pc) { - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion identity/no-dst mismatch"); - require(dut.io_branchConditionValid, std::string(c.name) + ": missing branchConditionValid"); - require(static_cast(dut.io_branchConditionTaken) == c.expected, - std::string(c.name) + ": branch condition disagreed with Sail oracle"); - require(dut.io_releaseValid, std::string(c.name) + ": missing releaseValid"); - require(release_identity_matches(dut, c), std::string(c.name) + ": release identity mismatch"); -} - -void drain_for_duplicates(VReducedScalarAluSetcCompareProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - if (dut.io_completeValid || dut.io_branchConditionValid || dut.io_releaseValid) { - fail(std::string(c.name) + ": duplicate completion/condition/release pulse before reset"); - } - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after drain"); -} - -void run_future_green_case(VReducedScalarAluSetcCompareProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 4ULL; - require(sail_condition(c.opcode, c.lhs, c.rhs, c.src_r_type) == c.expected, - std::string(c.name) + ": embedded Sail oracle fixture is inconsistent"); - drive_case(dut, c, pc); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - tick(dut); - idle(dut); - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, pc); - drain_for_duplicates(dut, c); - return; - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": accepted transaction produced no completion"); -} - -bool prove_first_geu_current_red_or_future_green(VReducedScalarAluSetcCompareProbe &dut, const Case &c) { - reset(dut); - require(c.opcode == kOpSetcGeu, "first transaction must be OP_SETC_GEU"); - require(c.expected, "first OP_SETC_GEU fixture must be Sail-true"); - drive_case(dut, c, kPcBase); - require(dut.io_inReady, "first-red OP_SETC_GEU input was not ready"); - require(dut.io_accepted, "first-red OP_SETC_GEU was not accepted"); - require_no_success_pulses(dut, "first-red OP_SETC_GEU accept cycle"); - tick(dut); - idle(dut); - bool observed_unsupported = false; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, kPcBase); - drain_for_duplicates(dut, c); - return true; - } - if (dut.io_branchConditionValid) { - fail("first OP_SETC_GEU produced branchConditionValid without completeValid"); - } - observed_unsupported = - observed_unsupported || (dut.io_unsupported && dut.io_unsupportedOpcode == kOpSetcGeu); - tick(dut); - idle(dut); - } - require(observed_unsupported, "first-red OP_SETC_GEU was accepted but did not report unsupported opcode 332"); - require(!dut.io_busy, "first-red OP_SETC_GEU busy did not clear after unsupported drain"); - std::cerr << "backend-reduced-scalar-alu-setc-compare-probe: first-red accepted OP_SETC_GEU 332 but observed unsupported/no completeValid/no branchConditionValid\n"; - std::exit(1); - return false; -} - -std::vector cases() { - return { - {"setc_geu_first_red_true", kOpSetcGeu, 0xffffffffffffffffULL, 0x0000000000000001ULL, 0, true, 3, false, 4, true, 5, false, 0x12000001U, 0xabc0000000000001ULL}, - {"setc_eq_true", kOpSetcEq, 0x1111222233334444ULL, 0x1111222233334444ULL, 0, true, 6, false, 7, true, 8, false, 0x12000002U, 0xabc0000000000002ULL}, - {"setc_eq_false", kOpSetcEq, 0x1111222233334444ULL, 0x1111222233334445ULL, 0, false, 9, true, 10, false, 11, true, 0x12000003U, 0xabc0000000000003ULL}, - {"setc_ne_true", kOpSetcNe, 0x0000000000000007ULL, 0x0000000000000008ULL, 0, true, 12, false, 13, false, 14, true, 0x12000004U, 0xabc0000000000004ULL}, - {"setc_ne_false", kOpSetcNe, 0x0000000000000008ULL, 0x0000000000000008ULL, 0, false, 15, true, 16, true, 17, false, 0x12000005U, 0xabc0000000000005ULL}, - {"setc_lt_true_signed_boundary", kOpSetcLt, 0x8000000000000000ULL, 0x0000000000000000ULL, 0, true, 18, false, 19, true, 20, false, 0x12000006U, 0xabc0000000000006ULL}, - {"setc_lt_false_equality", kOpSetcLt, 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0, false, 21, true, 22, false, 23, true, 0x12000007U, 0xabc0000000000007ULL}, - {"setc_ge_true_equality", kOpSetcGe, 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0, true, 24, false, 25, true, 26, false, 0x12000008U, 0xabc0000000000008ULL}, - {"setc_ge_false_signed_boundary", kOpSetcGe, 0x8000000000000000ULL, 0x0000000000000000ULL, 0, false, 27, true, 28, false, 29, true, 0x12000009U, 0xabc0000000000009ULL}, - {"setc_ltu_true_unsigned_boundary", kOpSetcLtu, 0x0000000000000000ULL, 0xffffffffffffffffULL, 0, true, 30, false, 31, true, 32, false, 0x1200000aU, 0xabc000000000000aULL}, - {"setc_ltu_false_equality", kOpSetcLtu, 0x00000000ffffffffULL, 0x00000000ffffffffULL, 0, false, 33, true, 34, false, 35, true, 0x1200000bU, 0xabc000000000000bULL}, - {"setc_geu_true_equality", kOpSetcGeu, 0x00000000ffffffffULL, 0x00000000ffffffffULL, 0, true, 36, false, 37, true, 38, false, 0x1200000cU, 0xabc000000000000cULL}, - {"setc_geu_false_unsigned_boundary", kOpSetcGeu, 0x0000000000000000ULL, 0xffffffffffffffffULL, 0, false, 39, true, 40, false, 41, true, 0x1200000dU, 0xabc000000000000dULL}, - {"srcrtype_raw_is_not_sign_extend", kOpSetcEq, 0x0000000080000001ULL, 0x0000000080000001ULL, 0, true, 42, false, 43, true, 44, false, 0x1200000eU, 0xabc000000000000eULL}, - {"srcrtype_sign_extend_low_word", kOpSetcEq, 0xffffffff80000001ULL, 0x0000000080000001ULL, 1, true, 45, true, 46, false, 47, true, 0x1200000fU, 0xabc000000000000fULL}, - {"srcrtype_zero_extend_low_word", kOpSetcEq, 0x0000000080000001ULL, 0xffffffff80000001ULL, 2, true, 48, false, 49, true, 50, false, 0x12000010U, 0xabc0000000000010ULL}, - {"srcrtype_three_sanitizes_to_raw", kOpSetcEq, 0x0000000000000005ULL, 0x0000000000000005ULL, 3, true, 51, true, 52, false, 53, true, 0x12000011U, 0xabc0000000000011ULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluSetcCompareProbe dut; - - const std::vector all_cases = cases(); - const bool first_case_completed = prove_first_geu_current_red_or_future_green(dut, all_cases.front()); - require(first_case_completed, "first OP_SETC_GEU neither completed future-green nor exited at current first-red"); - for (unsigned idx = 1; idx < all_cases.size(); ++idx) { - run_future_green_case(dut, all_cases[idx], idx); - } - - std::cout << "backend-reduced-scalar-alu-setc-compare-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb.cpp deleted file mode 100644 index 45b4b481..00000000 --- a/tools/chisel/backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb.cpp +++ /dev/null @@ -1,483 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedScalarAluSetcImmediateBehaviorProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpSetcAndi = 327; -constexpr std::uint32_t kOpSetcEqi = 329; -constexpr std::uint32_t kOpSetcGei = 331; -constexpr std::uint32_t kOpSetcGeui = 333; -constexpr std::uint32_t kOpSetcLti = 335; -constexpr std::uint32_t kOpSetcLtui = 337; -constexpr std::uint32_t kOpSetcNei = 339; -constexpr std::uint32_t kOpSetcOri = 341; -constexpr std::uint32_t kOpHlSetcAndi = 227; -constexpr std::uint32_t kOpHlSetcEqi = 228; -constexpr std::uint32_t kOpHlSetcGei = 229; -constexpr std::uint32_t kOpHlSetcGeui = 230; -constexpr std::uint32_t kOpHlSetcLti = 231; -constexpr std::uint32_t kOpHlSetcLtui = 232; -constexpr std::uint32_t kOpHlSetcNei = 233; -constexpr std::uint32_t kOpHlSetcOri = 234; -constexpr std::uint64_t kPcBase = 0x0000000000018000ULL; -constexpr std::uint8_t kSrc0Arch = 7; -constexpr std::uint8_t kSrc0Phys = 23; -constexpr int kWaitCycles = 8; -constexpr int kDuplicateDrainCycles = 8; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint64_t lhs; - std::uint32_t imm; - std::uint8_t shift; - bool expected; - std::uint8_t bid; - bool bid_wrap; - std::uint8_t gid; - bool gid_wrap; - std::uint8_t rid; - bool rid_wrap; - std::uint32_t lsid; - std::uint64_t block_bid; -}; - -void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-alu-setc-immediate-behavior-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void eval(VReducedScalarAluSetcImmediateBehaviorProbe &dut) { - dut.eval(); -} - -void tick(VReducedScalarAluSetcImmediateBehaviorProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -void idle(VReducedScalarAluSetcImmediateBehaviorProbe &dut) { - dut.io_inValid = 0; - dut.io_flushValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_src0Data = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_lsid = 0; - dut.io_blockBid = 0; - dut.io_src0ArchTag = kSrc0Arch; - dut.io_src0PhysTag = kSrc0Phys; -} - -void reset(VReducedScalarAluSetcImmediateBehaviorProbe &dut) { - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); -} - -bool is_unsigned_immediate_opcode(std::uint32_t opcode) { - return opcode == kOpSetcLtui || opcode == kOpSetcGeui || - opcode == kOpHlSetcLtui || opcode == kOpHlSetcGeui; -} - -bool is_hl_immediate_opcode(std::uint32_t opcode) { - return opcode == kOpHlSetcAndi || opcode == kOpHlSetcEqi || - opcode == kOpHlSetcGei || opcode == kOpHlSetcGeui || - opcode == kOpHlSetcLti || opcode == kOpHlSetcLtui || - opcode == kOpHlSetcNei || opcode == kOpHlSetcOri; -} - -std::uint64_t sign_extend(std::uint32_t imm, unsigned width) { - const std::uint64_t mask = (1ULL << width) - 1ULL; - const std::uint64_t sign_bit = 1ULL << (width - 1U); - const std::uint64_t raw = imm & mask; - return (raw & sign_bit) ? (raw | ~mask) : raw; -} - -std::uint64_t decoded_imm(const Case &c) { - const unsigned width = is_hl_immediate_opcode(c.opcode) ? 24U : 12U; - const std::uint64_t mask = (1ULL << width) - 1ULL; - return is_unsigned_immediate_opcode(c.opcode) ? (c.imm & mask) : sign_extend(c.imm, width); -} - -std::uint64_t shifted_imm(const Case &c) { - return decoded_imm(c) << (c.shift & 31U); -} - -bool setc_immediate_condition(const Case &c) { - const std::uint64_t rhs = shifted_imm(c); - switch (c.opcode) { - case kOpSetcEqi: - case kOpHlSetcEqi: - return c.lhs == rhs; - case kOpSetcNei: - case kOpHlSetcNei: - return c.lhs != rhs; - case kOpSetcAndi: - case kOpHlSetcAndi: - return (c.lhs & rhs) != 0; - case kOpSetcOri: - case kOpHlSetcOri: - return (c.lhs | rhs) != 0; - case kOpSetcLti: - case kOpHlSetcLti: - return static_cast(c.lhs) < static_cast(rhs); - case kOpSetcGei: - case kOpHlSetcGei: - return static_cast(c.lhs) >= static_cast(rhs); - case kOpSetcLtui: - case kOpHlSetcLtui: - return c.lhs < rhs; - case kOpSetcGeui: - case kOpHlSetcGeui: - return c.lhs >= rhs; - default: - fail("unknown SETC-immediate opcode in oracle"); - return false; - } -} - -std::uint64_t opcode_match(std::uint32_t opcode) { - switch (opcode) { - case kOpHlSetcEqi: - return 0x000000000075000eULL; - case kOpHlSetcNei: - return 0x000000001075000eULL; - case kOpHlSetcAndi: - return 0x000000002075000eULL; - case kOpHlSetcOri: - return 0x000000003075000eULL; - case kOpHlSetcLti: - return 0x000000004075000eULL; - case kOpHlSetcGei: - return 0x000000005075000eULL; - case kOpHlSetcLtui: - return 0x000000006075000eULL; - case kOpHlSetcGeui: - return 0x000000007075000eULL; - case kOpSetcEqi: - return 0x00000075ULL; - case kOpSetcNei: - return 0x00001075ULL; - case kOpSetcAndi: - return 0x00002075ULL; - case kOpSetcOri: - return 0x00003075ULL; - case kOpSetcLti: - return 0x00004075ULL; - case kOpSetcGei: - return 0x00005075ULL; - case kOpSetcLtui: - return 0x00006075ULL; - case kOpSetcGeui: - return 0x00007075ULL; - default: - fail("unknown SETC-immediate opcode while constructing instruction"); - return 0; - } -} - -std::uint64_t insn_for_case(const Case &c) { - if (is_hl_immediate_opcode(c.opcode)) { - const std::uint64_t imm = c.imm & 0x00ffffffU; - return opcode_match(c.opcode) | - ((imm >> 12) << 4) | - ((imm & 0x0fffU) << 36) | - (static_cast(kSrc0Arch & 0x1fU) << 31) | - (static_cast(c.shift & 0x1fU) << 23); - } - return opcode_match(c.opcode) | - (static_cast(c.imm & 0x0fffU) << 20) | - (static_cast(kSrc0Arch & 0x1fU) << 15) | - (static_cast(c.shift & 0x1fU) << 7); -} - -void drive_case(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c, std::uint64_t pc, bool flush) { - idle(dut); - dut.io_inValid = 1; - dut.io_flushValid = flush ? 1 : 0; - dut.io_opcode = c.opcode; - dut.io_pc = pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_imm = decoded_imm(c); - dut.io_src0Data = c.lhs; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_lsid = c.lsid; - dut.io_blockBid = c.block_bid; - dut.io_src0ArchTag = kSrc0Arch; - dut.io_src0PhysTag = kSrc0Phys; - eval(dut); -} - -void require_no_success_pulses(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const std::string &context) { - require(!dut.io_completeValid, context + ": unexpected completeValid"); - require(!dut.io_branchConditionValid, context + ": unexpected branchConditionValid"); - require(!dut.io_releaseValid, context + ": unexpected releaseValid"); -} - -void require_no_completion_branch_or_writeback(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const std::string &context) { - require(!dut.io_completeValid, context + ": unexpected completeValid"); - require(!dut.io_branchConditionValid, context + ": unexpected branchConditionValid"); - require(!dut.io_completeDstPhysValid, context + ": unexpected RF destination valid"); - require(dut.io_completeDstPhysTag == 0, context + ": unexpected RF destination tag"); - require(dut.io_completeDstData == 0, context + ": unexpected RF destination data"); - require(!dut.io_completeRowValid, context + ": unexpected commit row valid"); - require(!dut.io_completeRowDstValid, context + ": unexpected architectural destination valid"); - require(dut.io_completeRowDstReg == 0, context + ": unexpected architectural destination register"); - require(dut.io_completeRowDstData == 0, context + ": unexpected architectural destination data"); - require(!dut.io_completeRowWbValid, context + ": unexpected architectural writeback valid"); - require(dut.io_completeRowWbReg == 0, context + ": unexpected architectural writeback register"); - require(dut.io_completeRowWbData == 0, context + ": unexpected architectural writeback data"); -} - -bool completion_identity_matches(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c, std::uint64_t pc) { - return dut.io_completeRobValue == c.rid && dut.io_completeLsId == c.lsid && - !dut.io_completeDstPhysValid && dut.io_completeDstPhysTag == 0 && - dut.io_completeDstData == 0 && dut.io_completeSrc0PhysValid && - dut.io_completeSrc0PhysTag == kSrc0Phys && !dut.io_completeSrc1PhysValid && - dut.io_completeSrc1PhysTag == 0 && dut.io_completeRowValid && - dut.io_completeRowBid == c.bid && dut.io_completeRowGid == c.gid && - dut.io_completeRowRid == c.rid && dut.io_completeRowRobValid && - dut.io_completeRowRobWrap == c.rid_wrap && dut.io_completeRowRobValue == c.rid && - dut.io_completeRowBlockBidValid && dut.io_completeRowBlockBid == c.block_bid && - dut.io_completeRowPc == pc && dut.io_completeRowInsn == insn_for_case(c) && - dut.io_completeRowLen == (is_hl_immediate_opcode(c.opcode) ? 6 : 4) && dut.io_completeRowSrc0Valid && - dut.io_completeRowSrc0Reg == kSrc0Arch && dut.io_completeRowSrc0Data == c.lhs && - !dut.io_completeRowSrc1Valid && dut.io_completeRowSrc1Reg == 0 && - dut.io_completeRowSrc1Data == 0 && !dut.io_completeRowDstValid && - dut.io_completeRowDstReg == 0 && dut.io_completeRowDstData == 0 && - !dut.io_completeRowWbValid && dut.io_completeRowWbReg == 0 && - dut.io_completeRowWbData == 0; -} - -bool release_identity_matches(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c) { - return dut.io_releaseBidValid && dut.io_releaseBidWrap == c.bid_wrap && - dut.io_releaseBidValue == c.bid && dut.io_releaseGidValid && - dut.io_releaseGidWrap == c.gid_wrap && dut.io_releaseGidValue == c.gid && - dut.io_releaseRidValid && dut.io_releaseRidWrap == c.rid_wrap && - dut.io_releaseRidValue == c.rid && dut.io_releaseStid == 0; -} - -void require_current_red_release_row(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c) { - require(dut.io_unsupported, std::string(c.name) + ": missing unsupported pulse"); - require(dut.io_unsupportedOpcode == kOpSetcEqi, std::string(c.name) + ": unsupported opcode was not OP_SETC_EQI 329"); - require(dut.io_releaseValid, std::string(c.name) + ": missing mandatory unsupported releaseValid"); - require(release_identity_matches(dut, c), std::string(c.name) + ": unsupported release identity mismatch"); - require_no_completion_branch_or_writeback(dut, std::string(c.name) + " current-red row"); -} - -void require_future_green_row(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c, std::uint64_t pc) { - require(completion_identity_matches(dut, c, pc), std::string(c.name) + ": completion/source/no-writeback identity mismatch"); - require(dut.io_branchConditionValid, std::string(c.name) + ": missing branchConditionValid"); - require(static_cast(dut.io_branchConditionTaken) == c.expected, - std::string(c.name) + ": branch condition disagreed with QEMU/pyCircuit oracle"); - require(dut.io_releaseValid, std::string(c.name) + ": missing releaseValid"); - require(release_identity_matches(dut, c), std::string(c.name) + ": release identity mismatch"); - require(!dut.io_unsupported, std::string(c.name) + ": unsupported pulse on future-green row"); -} - -void drain_for_duplicates(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kDuplicateDrainCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - if (dut.io_completeValid || dut.io_branchConditionValid || dut.io_releaseValid || dut.io_unsupported) { - fail(std::string(c.name) + ": duplicate completion/condition/release/unsupported pulse before reset"); - } - } - require(!dut.io_busy, std::string(c.name) + ": busy did not clear after drain"); -} - -void wait_for_future_green_case(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c, std::uint64_t pc) { - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, pc); - return; - } - if (dut.io_branchConditionValid || dut.io_releaseValid) { - fail(std::string(c.name) + ": sideband pulse arrived without completeValid"); - } - if (dut.io_unsupported && dut.io_unsupportedOpcode == c.opcode) { - fail(std::string(c.name) + ": unsupported opcode " + std::to_string(c.opcode) + " before future-green completion"); - } - tick(dut); - idle(dut); - } - fail(std::string(c.name) + ": accepted transaction produced no completion"); -} - -void run_future_green_case(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c, unsigned index) { - reset(dut); - const std::uint64_t pc = kPcBase + static_cast(index) * 4ULL; - const unsigned shamt_lsb = is_hl_immediate_opcode(c.opcode) ? 23U : 7U; - require((c.shift == ((insn_for_case(c) >> shamt_lsb) & 0x1fU)), std::string(c.name) + ": encoded shift fixture mismatch"); - require(setc_immediate_condition(c) == c.expected, std::string(c.name) + ": embedded oracle fixture is inconsistent"); - drive_case(dut, c, pc, false); - require(dut.io_inReady, std::string(c.name) + ": input was not ready"); - require(dut.io_accepted, std::string(c.name) + ": transaction was not accepted"); - require_no_success_pulses(dut, std::string(c.name) + " accept cycle"); - tick(dut); - idle(dut); - wait_for_future_green_case(dut, c, pc); - drain_for_duplicates(dut, c); -} - -bool prove_first_current_red_or_future_green(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c) { - reset(dut); - require(c.opcode == kOpSetcEqi, "first transaction must be OP_SETC_EQI"); - require(c.expected, "first OP_SETC_EQI fixture must be oracle-true"); - drive_case(dut, c, kPcBase, false); - require(dut.io_inReady, "first-red OP_SETC_EQI input was not ready"); - require(dut.io_accepted, "first-red OP_SETC_EQI was not accepted"); - require_no_success_pulses(dut, "first-red OP_SETC_EQI accept cycle"); - tick(dut); - idle(dut); - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - eval(dut); - if (dut.io_completeValid) { - require_future_green_row(dut, c, kPcBase); - drain_for_duplicates(dut, c); - return true; - } - if (dut.io_unsupported || dut.io_releaseValid || dut.io_branchConditionValid) { - require_current_red_release_row(dut, c); - drain_for_duplicates(dut, c); - std::cerr << "backend-reduced-scalar-alu-setc-immediate-behavior-probe: first-red accepted OP_SETC_EQI 329 and observed unsupportedOpcode=329 with release BID=3/0 GID=4/1 RID=5/0 STID=0; no completeValid/no branchConditionValid/no writeback/no duplicate pulses\n"; - std::exit(1); - } - tick(dut); - idle(dut); - } - fail("first-red OP_SETC_EQI was accepted but produced no unsupported+release current-red row"); - return false; -} - -void run_back_to_back(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &first, const Case &second) { - reset(dut); - require(setc_immediate_condition(first) == first.expected, "back-to-back first oracle fixture is inconsistent"); - require(setc_immediate_condition(second) == second.expected, "back-to-back second oracle fixture is inconsistent"); - const std::uint64_t first_pc = kPcBase + 0x400; - const std::uint64_t second_pc = kPcBase + 0x404; - drive_case(dut, first, first_pc, false); - require(dut.io_inReady && dut.io_accepted, "back-to-back first transaction was not accepted"); - tick(dut); - idle(dut); - wait_for_future_green_case(dut, first, first_pc); - tick(dut); - drive_case(dut, second, second_pc, false); - require(dut.io_inReady && dut.io_accepted, "back-to-back second transaction was not accepted after first completion"); - tick(dut); - idle(dut); - wait_for_future_green_case(dut, second, second_pc); - drain_for_duplicates(dut, second); -} - -void run_flush_cancellation(VReducedScalarAluSetcImmediateBehaviorProbe &dut, const Case &c) { - reset(dut); - const std::uint64_t pc = kPcBase + 0x800; - drive_case(dut, c, pc, false); - require(dut.io_inReady && dut.io_accepted, "flush-cancel transaction was not accepted"); - tick(dut); - idle(dut); - dut.io_flushValid = 1; - for (int cycle = 0; cycle < kWaitCycles; ++cycle) { - tick(dut); - idle(dut); - eval(dut); - require_no_success_pulses(dut, "flush-cancel drain"); - require(!dut.io_unsupported, "flush-cancel produced unsupported after flush"); - } - require(!dut.io_busy, "flush-cancel busy did not clear"); -} - -std::vector cases() { - return { - {"setc_eqi_shift0_true_first_red", kOpSetcEqi, 0x0000000000000007ULL, 0x007, 0, true, 3, false, 4, true, 5, false, 0x22000001U, 0xbcd0000000000001ULL}, - {"setc_eqi_shift1_false", kOpSetcEqi, 0x000000000000000eULL, 0x008, 1, false, 6, false, 7, true, 8, false, 0x22000002U, 0xbcd0000000000002ULL}, - {"setc_nei_sign_boundary_false", kOpSetcNei, 0xfffffffffffff800ULL, 0x800, 0, false, 9, true, 10, false, 11, true, 0x22000003U, 0xbcd0000000000003ULL}, - {"setc_nei_shift31_wrap_true", kOpSetcNei, 0x0000000000000000ULL, 0x800, 31, true, 12, false, 13, false, 14, true, 0x22000004U, 0xbcd0000000000004ULL}, - {"setc_andi_zero_false", kOpSetcAndi, 0x00f0000000000000ULL, 0x00f, 8, false, 15, true, 16, true, 17, false, 0x22000005U, 0xbcd0000000000005ULL}, - {"setc_andi_nonzero_true", kOpSetcAndi, 0x0000000000000f00ULL, 0x00f, 8, true, 18, false, 19, true, 20, false, 0x22000006U, 0xbcd0000000000006ULL}, - {"setc_ori_zero_false", kOpSetcOri, 0x0000000000000000ULL, 0x000, 31, false, 21, true, 22, false, 23, true, 0x22000007U, 0xbcd0000000000007ULL}, - {"setc_ori_nonzero_true", kOpSetcOri, 0x0000000000000000ULL, 0x001, 31, true, 24, false, 25, true, 26, false, 0x22000008U, 0xbcd0000000000008ULL}, - {"setc_lti_signed_min_true", kOpSetcLti, 0x8000000000000000ULL, 0x000, 0, true, 27, true, 28, false, 29, true, 0x22000009U, 0xbcd0000000000009ULL}, - {"setc_lti_negative_imm_false", kOpSetcLti, 0xfffffffffffff800ULL, 0x800, 0, false, 30, false, 31, true, 32, false, 0x2200000aU, 0xbcd000000000000aULL}, - {"setc_gei_negative_imm_true", kOpSetcGei, 0xfffffffffffff800ULL, 0x800, 0, true, 33, true, 34, false, 35, true, 0x2200000bU, 0xbcd000000000000bULL}, - {"setc_gei_signed_min_false", kOpSetcGei, 0x8000000000000000ULL, 0x000, 0, false, 36, false, 37, true, 38, false, 0x2200000cU, 0xbcd000000000000cULL}, - {"setc_ltui_high_unsigned_true", kOpSetcLtui, 0x0000000000000001ULL, 0xfff, 31, true, 39, true, 40, false, 41, true, 0x2200000dU, 0xbcd000000000000dULL}, - {"setc_ltui_equality_false", kOpSetcLtui, 0x0000000000000fffULL, 0xfff, 0, false, 42, false, 43, true, 44, false, 0x2200000eU, 0xbcd000000000000eULL}, - {"setc_geui_equality_true", kOpSetcGeui, 0x0000000000000fffULL, 0xfff, 0, true, 45, true, 46, false, 47, true, 0x2200000fU, 0xbcd000000000000fULL}, - {"setc_geui_high_unsigned_false", kOpSetcGeui, 0x0000000000000001ULL, 0xfff, 31, false, 48, false, 49, true, 50, false, 0x22000010U, 0xbcd0000000000010ULL}, - {"hl_setc_eqi_shift2_true", kOpHlSetcEqi, 0x0000000000048d14ULL, 0x012345, 2, true, 51, true, 52, false, 53, true, 0x22000011U, 0xbcd0000000000011ULL}, - {"hl_setc_eqi_shift3_false", kOpHlSetcEqi, 0x0000000000091a28ULL, 0x012346, 3, false, 54, false, 55, true, 56, false, 0x22000012U, 0xbcd0000000000012ULL}, - {"hl_setc_nei_sign_boundary_false", kOpHlSetcNei, 0xffffffffff800000ULL, 0x800000, 0, false, 57, true, 58, false, 59, true, 0x22000013U, 0xbcd0000000000013ULL}, - {"hl_setc_nei_shift5_true", kOpHlSetcNei, 0x0000000000000000ULL, 0x800001, 5, true, 60, false, 61, true, 62, false, 0x22000014U, 0xbcd0000000000014ULL}, - {"hl_setc_andi_zero_false", kOpHlSetcAndi, 0x00000000f0000000ULL, 0x00000f, 4, false, 1, true, 2, true, 3, false, 0x22000015U, 0xbcd0000000000015ULL}, - {"hl_setc_andi_nonzero_true", kOpHlSetcAndi, 0x00000000000000f0ULL, 0x00000f, 4, true, 4, false, 5, true, 6, false, 0x22000016U, 0xbcd0000000000016ULL}, - {"hl_setc_ori_zero_false", kOpHlSetcOri, 0x0000000000000000ULL, 0x000000, 9, false, 7, true, 8, false, 9, true, 0x22000017U, 0xbcd0000000000017ULL}, - {"hl_setc_ori_nonzero_true", kOpHlSetcOri, 0x0000000000000000ULL, 0x000001, 9, true, 10, false, 11, true, 12, false, 0x22000018U, 0xbcd0000000000018ULL}, - {"hl_setc_lti_signed_min_true", kOpHlSetcLti, 0x8000000000000000ULL, 0x000000, 0, true, 13, true, 14, false, 15, true, 0x22000019U, 0xbcd0000000000019ULL}, - {"hl_setc_lti_negative_imm_false", kOpHlSetcLti, 0xffffffffff800000ULL, 0x800000, 0, false, 16, false, 17, true, 18, false, 0x2200001aU, 0xbcd000000000001aULL}, - {"hl_setc_gei_negative_imm_true", kOpHlSetcGei, 0xffffffffff800000ULL, 0x800000, 0, true, 19, true, 20, false, 21, true, 0x2200001bU, 0xbcd000000000001bULL}, - {"hl_setc_gei_signed_min_false", kOpHlSetcGei, 0x8000000000000000ULL, 0x000000, 0, false, 22, false, 23, true, 24, false, 0x2200001cU, 0xbcd000000000001cULL}, - {"hl_setc_ltui_high_unsigned_true", kOpHlSetcLtui, 0x0000000000000001ULL, 0xffffff, 8, true, 25, true, 26, false, 27, true, 0x2200001dU, 0xbcd000000000001dULL}, - {"hl_setc_ltui_equality_false", kOpHlSetcLtui, 0x0000000000ffffffULL, 0xffffff, 0, false, 28, false, 29, true, 30, false, 0x2200001eU, 0xbcd000000000001eULL}, - {"hl_setc_geui_equality_true", kOpHlSetcGeui, 0x0000000000ffffffULL, 0xffffff, 0, true, 31, true, 32, false, 33, true, 0x2200001fU, 0xbcd000000000001fULL}, - {"hl_setc_geui_high_unsigned_false", kOpHlSetcGeui, 0x0000000000000001ULL, 0xffffff, 8, false, 34, false, 35, true, 36, false, 0x22000020U, 0xbcd0000000000020ULL}, - }; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedScalarAluSetcImmediateBehaviorProbe dut; - - const std::vector all_cases = cases(); - const bool first_case_completed = prove_first_current_red_or_future_green(dut, all_cases.front()); - require(first_case_completed, "first OP_SETC_EQI neither completed future-green nor exited at current first-red"); - for (unsigned idx = 1; idx < all_cases.size(); ++idx) { - run_future_green_case(dut, all_cases[idx], idx); - } - run_back_to_back(dut, all_cases[1], all_cases[2]); - run_flush_cancellation(dut, all_cases[3]); - - std::cout << "backend-reduced-scalar-alu-setc-immediate-behavior-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/backend_reduced_scalar_writeback_arbiter_behavior_probe_tb.cpp b/tools/chisel/backend_reduced_scalar_writeback_arbiter_behavior_probe_tb.cpp deleted file mode 100644 index 573d0bcc..00000000 --- a/tools/chisel/backend_reduced_scalar_writeback_arbiter_behavior_probe_tb.cpp +++ /dev/null @@ -1,245 +0,0 @@ -#include -#include -#include -#include - -#include "VReducedScalarWritebackArbiterBehaviorProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint8_t kExecuteTag = 5; -constexpr std::uint8_t kReplayTag = 19; -constexpr std::uint8_t kTemplateTag = 42; -constexpr std::uint64_t kExecuteData = 0x1111222233334444ULL; -constexpr std::uint64_t kReplayData = 0x5555666677778888ULL; -constexpr std::uint64_t kTemplateData = 0x9999aaaabbbbccccULL; - -struct Source { - bool enable; - bool valid; - std::uint8_t tag; - std::uint64_t data; -}; - -struct Expected { - bool valid; - std::uint8_t tag; - std::uint64_t data; - bool execute; - bool replay; - bool templ; -}; - -[[noreturn]] void fail(const std::string &message) { - std::cerr << "backend-reduced-scalar-writeback-arbiter-behavior-probe: FAIL: " - << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -void drive(VReducedScalarWritebackArbiterBehaviorProbe &dut, - const Source &execute, - const Source &replay, - const Source &templ, - bool rf_port_ready) { - dut.io_executeValid = execute.valid; - dut.io_executeTag = execute.tag; - dut.io_executeData = execute.data; - dut.io_replayEnable = replay.enable; - dut.io_replayValid = replay.valid; - dut.io_replayTag = replay.tag; - dut.io_replayData = replay.data; - dut.io_templateEnable = templ.enable; - dut.io_templateValid = templ.valid; - dut.io_templateTag = templ.tag; - dut.io_templateData = templ.data; - dut.io_rfPortReady = rf_port_ready; -} - -Expected expected_for(const Source &execute, - const Source &replay, - const Source &templ) { - const bool replay_candidate = replay.enable && replay.valid; - const bool template_candidate = templ.enable && templ.valid; - if (execute.valid) { - return {true, execute.tag, execute.data, true, false, false}; - } - if (replay_candidate) { - return {true, replay.tag, replay.data, false, true, false}; - } - if (template_candidate) { - return {true, templ.tag, templ.data, false, false, true}; - } - return {false, 0, 0, false, false, false}; -} - -void check_outputs(VReducedScalarWritebackArbiterBehaviorProbe &dut, - const Source &execute, - const Source &replay, - const Source &templ, - bool rf_port_ready, - const std::string &label) { - dut.eval(); - const Expected expected = expected_for(execute, replay, templ); - const bool replay_candidate = replay.enable && replay.valid; - const bool template_candidate = templ.enable && templ.valid; - const unsigned selection_count = - static_cast(dut.io_selectedExecute) + - static_cast(dut.io_selectedReplay) + - static_cast(dut.io_selectedTemplate); - - require(dut.io_writeValid == expected.valid, label + ": write-valid mismatch"); - require(dut.io_writeTag == expected.tag, label + ": write-tag mismatch"); - require(dut.io_writeData == expected.data, label + ": write-data mismatch"); - require(dut.io_selectedExecute == expected.execute, label + ": execute selection mismatch"); - require(dut.io_selectedReplay == expected.replay, label + ": replay selection mismatch"); - require(dut.io_selectedTemplate == expected.templ, label + ": template selection mismatch"); - require(selection_count == static_cast(expected.valid), - label + ": selection is not idle-or-one-hot"); - - require(dut.io_replayBlockedByDisabled == (!replay.enable && replay.valid), - label + ": replay disabled-blocker mismatch"); - require(dut.io_replayBlockedByExecute == (replay_candidate && execute.valid), - label + ": replay execute-blocker mismatch"); - require(dut.io_templateBlockedByDisabled == (!templ.enable && templ.valid), - label + ": template disabled-blocker mismatch"); - require(dut.io_templateBlockedByExecute == (template_candidate && execute.valid), - label + ": template execute-blocker mismatch"); - require(dut.io_templateBlockedByReplay == - (template_candidate && !execute.valid && replay_candidate), - label + ": template replay-blocker mismatch"); - - require(dut.io_writeFire == (expected.valid && rf_port_ready), - label + ": RF-port fire mismatch"); - require(dut.io_templateAdvance == (expected.templ && rf_port_ready), - label + ": template advancement mismatch"); - require(!dut.io_templateAdvance || - (dut.io_selectedTemplate && dut.io_writeValid && rf_port_ready), - label + ": template advanced without selected RF-port fire"); -} - -void prove_all_enable_and_valid_combinations( - VReducedScalarWritebackArbiterBehaviorProbe &dut) { - for (unsigned bits = 0; bits < 32; ++bits) { - const Source execute{true, (bits & 16U) != 0, kExecuteTag, kExecuteData}; - const Source replay{ - (bits & 8U) != 0, (bits & 4U) != 0, kReplayTag, kReplayData}; - const Source templ{ - (bits & 2U) != 0, (bits & 1U) != 0, kTemplateTag, kTemplateData}; - for (unsigned ready = 0; ready < 2; ++ready) { - drive(dut, execute, replay, templ, ready != 0); - check_outputs( - dut, - execute, - replay, - templ, - ready != 0, - "enable-valid-combination-" + std::to_string(bits) + - "-ready-" + std::to_string(ready)); - } - } -} - -void prove_unselected_payload_independence( - VReducedScalarWritebackArbiterBehaviorProbe &dut) { - Source execute{true, true, kExecuteTag, kExecuteData}; - Source replay{true, true, kReplayTag, kReplayData}; - Source templ{true, true, kTemplateTag, kTemplateData}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "execute-before-payload-mutation"); - replay = {true, true, 63, 0x0102030405060708ULL}; - templ = {true, true, 1, 0xf0e0d0c0b0a09080ULL}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "execute-after-payload-mutation"); - - execute = {true, false, 62, 0xdeadbeefdeadbeefULL}; - replay = {true, true, kReplayTag, kReplayData}; - templ = {true, true, kTemplateTag, kTemplateData}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "replay-before-payload-mutation"); - execute = {true, false, 2, 0x1212121212121212ULL}; - templ = {true, true, 61, 0x3434343434343434ULL}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "replay-after-payload-mutation"); - - execute = {true, false, 60, 0x5656565656565656ULL}; - replay = {true, false, 59, 0x7878787878787878ULL}; - templ = {true, true, kTemplateTag, kTemplateData}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "template-before-payload-mutation"); - execute = {true, false, 3, 0x9191919191919191ULL}; - replay = {false, true, 4, 0xa2a2a2a2a2a2a2a2ULL}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "template-after-payload-mutation"); -} - -void prove_held_template_waits_for_selection_and_fire( - VReducedScalarWritebackArbiterBehaviorProbe &dut) { - const Source templ{true, true, kTemplateTag, kTemplateData}; - Source execute{true, true, kExecuteTag, kExecuteData}; - Source replay{true, true, kReplayTag, kReplayData}; - - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "template-held-under-execute"); - require(!dut.io_templateAdvance, "template advanced while execute blocked it"); - - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - check_outputs(dut, execute, replay, templ, true, "template-stable-after-execute-cycle"); - - execute.valid = false; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "template-held-under-replay"); - require(!dut.io_templateAdvance, "template advanced while replay blocked it"); - - replay.valid = false; - drive(dut, execute, replay, templ, false); - check_outputs(dut, execute, replay, templ, false, "template-selected-rf-not-ready"); - require(!dut.io_templateAdvance, "template advanced without RF-port readiness"); - - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "template-selected-rf-fire"); - require(dut.io_templateAdvance, "template did not advance on selected RF-port fire"); -} - -void prove_idle_zero(VReducedScalarWritebackArbiterBehaviorProbe &dut) { - const Source execute{true, false, 63, 0x1111111111111111ULL}; - const Source replay{false, true, 62, 0x2222222222222222ULL}; - const Source templ{false, true, 61, 0x3333333333333333ULL}; - drive(dut, execute, replay, templ, true); - check_outputs(dut, execute, replay, templ, true, "idle-disabled-stale-payloads"); - require(!dut.io_writeValid && dut.io_writeTag == 0 && dut.io_writeData == 0, - "idle outputs were not zero"); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - if (argc != 1) { - fail("unknown argument"); - } - - VReducedScalarWritebackArbiterBehaviorProbe dut; - dut.clock = 0; - dut.reset = 0; - - prove_all_enable_and_valid_combinations(dut); - prove_unselected_payload_independence(dut); - prove_held_template_waits_for_selection_and_fire(dut); - prove_idle_zero(dut); - - std::cout - << "backend-reduced-scalar-writeback-arbiter-behavior-probe: PASS " - << "(32 enable/valid combinations x 2 RF-ready states, priority, blockers, " - "one-hot, payload independence, held template, advancement, idle zero)\n"; - return 0; -} diff --git a/tools/chisel/bctrl_fentry_fret_natural_observation_probe_tb.cpp b/tools/chisel/bctrl_fentry_fret_natural_observation_probe_tb.cpp deleted file mode 100644 index 746dd2bf..00000000 --- a/tools/chisel/bctrl_fentry_fret_natural_observation_probe_tb.cpp +++ /dev/null @@ -1,1133 +0,0 @@ -#include "VLinxCoreBenchmarkAutonomousTop.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint64_t kOuterCallPc = 0x11eb4ULL; -constexpr std::uint32_t kOuterCallRaw32 = 0xfd2f4001U; -constexpr std::uint16_t kOuterCallSetretRaw16 = 0x5516U; -constexpr std::uint64_t kOuterReturnPc = 0x11ee0ULL; -constexpr std::uint64_t kFentryPc = 0x11370ULL; -constexpr std::uint32_t kFentryRaw = 0x29350041U; -constexpr std::uint64_t kFretPc = 0x11dbaULL; -constexpr std::uint32_t kFretRaw = 0x29353041U; -constexpr std::uint64_t kExpectedNewSp = 231248ULL; -constexpr std::uint64_t kExpectedUimm = 160ULL; -constexpr std::uint64_t kExpectedRaSlot = 231400ULL; -constexpr std::uint64_t kExpectedLastSlot = 231328ULL; -constexpr std::uint64_t kNestedRaSlot = 231240ULL; -constexpr std::uint64_t kNestedReturnPc = 0x113aeULL; -constexpr std::uint64_t kMaxTailCycles = 32ULL; -constexpr unsigned kSpReg = 1U; -constexpr unsigned kArchitecturalA0 = 2U; -constexpr unsigned kArchitecturalX3 = 23U; -constexpr unsigned kRegisterCount = 32U; - -std::uint64_t parse_u64_arg(const std::string &value, const std::string &name) { - errno = 0; - char *end = nullptr; - const unsigned long long parsed = std::strtoull(value.c_str(), &end, 0); - if (errno != 0 || end == value.c_str() || *end != '\0') { - throw std::runtime_error("invalid " + name + ": " + value); - } - return static_cast(parsed); -} - -std::string hex64(std::uint64_t value) { - std::ostringstream out; - out << "0x" << std::hex << value; - return out.str(); -} - -class SparseMemory { -public: - void store_byte(std::uint64_t addr, std::uint8_t value) { - bytes_[addr] = value; - } - - void load_sparse_hex(const std::string &path) { - std::ifstream in(path); - if (!in) { - throw std::runtime_error("failed to open sparse memory image: " + path); - } - std::string line; - std::uint64_t line_no = 0; - std::uint64_t count = 0; - while (std::getline(in, line)) { - ++line_no; - const auto comment = line.find('#'); - if (comment != std::string::npos) { - line.resize(comment); - } - std::istringstream iss(line); - std::string addr_token; - std::string byte_token; - std::string extra; - if (!(iss >> addr_token)) { - continue; - } - if (!(iss >> byte_token) || (iss >> extra)) { - throw std::runtime_error("invalid sparse memory line " + std::to_string(line_no)); - } - const auto addr = parse_u64_arg(addr_token, "sparse memory address"); - const auto byte = parse_u64_arg(byte_token, "sparse memory byte"); - if (byte > 0xffU) { - throw std::runtime_error("sparse memory byte out of range"); - } - store_byte(addr, static_cast(byte)); - ++count; - } - if (count == 0) { - throw std::runtime_error("sparse memory image is empty: " + path); - } - } - - std::uint64_t read_window(std::uint64_t pc) const { - std::uint64_t value = 0; - for (std::uint8_t i = 0; i < 8; ++i) { - std::uint8_t byte = 0xffU; - const bool found = read_byte(pc + i, byte); - if (!found && i == 0) { - throw std::runtime_error("fetch memory missing first byte at pc=" + hex64(pc)); - } - value |= static_cast(byte) << (i * 8U); - } - return value; - } - - std::uint32_t read_u32(std::uint64_t addr) const { - std::uint32_t value = 0; - for (std::uint8_t i = 0; i < 4; ++i) { - std::uint8_t byte = 0; - if (!read_byte(addr + i, byte)) { - throw std::runtime_error("memory missing byte at " + hex64(addr + i)); - } - value |= static_cast(byte) << (i * 8U); - } - return value; - } - - std::uint64_t read_u48(std::uint64_t addr) const { - std::uint64_t value = 0; - for (std::uint8_t i = 0; i < 6; ++i) { - std::uint8_t byte = 0; - if (!read_byte(addr + i, byte)) { - throw std::runtime_error("memory missing byte at " + hex64(addr + i)); - } - value |= static_cast(byte) << (i * 8U); - } - return value; - } - - std::uint64_t read_u64_or_zero(std::uint64_t addr) const { - std::uint64_t value = 0; - for (std::uint8_t i = 0; i < 8; ++i) { - std::uint8_t byte = 0; - (void)read_byte(addr + i, byte); - value |= static_cast(byte) << (i * 8U); - } - return value; - } - - void apply_store(std::uint64_t addr, std::uint64_t data, std::uint8_t size, - std::uint8_t mask) { - if (size == 0 || size > 8) { - throw std::runtime_error("unsupported committed store size"); - } - std::uint8_t effective_mask = mask; - if (effective_mask == 0) { - const auto low = static_cast(addr & 0x7U); - if (low + size > 8) { - throw std::runtime_error("committed store crosses observation lane"); - } - effective_mask = static_cast(((1U << size) - 1U) << low); - } - const std::uint64_t lane_base = addr & ~0x7ULL; - for (std::uint8_t i = 0; i < 8; ++i) { - if ((effective_mask & (1U << i)) != 0) { - store_byte(lane_base + i, - static_cast((data >> (i * 8U)) & 0xffU)); - } - } - } - -private: - bool read_byte(std::uint64_t addr, std::uint8_t &value) const { - const auto it = bytes_.find(addr); - if (it == bytes_.end()) { - return false; - } - value = it->second; - return true; - } - - std::map bytes_; -}; - -struct Args { - std::string memory_hex; - std::string report; - std::uint64_t reset_pc = 0; - std::uint64_t reset_sp = 0; - std::uint64_t max_cycles = 5000; - bool self_test_only = false; -}; - -struct Row { - bool valid = false; - std::uint64_t cycle = 0; - std::uint64_t trace_cycle = 0; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint64_t bid = 0; - std::uint64_t gid = 0; - std::uint64_t rid = 0; - bool wb_valid = false; - std::uint64_t wb_rd = 0; - std::uint64_t wb_data = 0; - bool src0_valid = false; - std::uint64_t src0_data = 0; - bool mem_valid = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint64_t mem_size = 0; - std::uint64_t next_pc = 0; - bool rob_valid = false; - std::uint64_t rob_value = 0; - bool rob_wrap = false; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; -}; - -struct AcceptEvent { - std::uint64_t cycle = 0; - bool identity_valid = false; - bool bid_valid = false; - std::uint64_t bid = 0; - bool rid_valid = false; - std::uint64_t rid = 0; - std::uint64_t stid = 0; - bool bid_wrap = false; - bool rid_wrap = false; -}; - -struct CompleteEvent { - std::uint64_t cycle = 0; - std::uint64_t rob = 0; -}; - -struct StoreObs { - std::uint64_t cycle = 0; - std::uint64_t pc = 0; - std::uint64_t addr = 0; - std::uint64_t data = 0; - std::uint64_t size = 0; - std::uint64_t bid = 0; - std::uint64_t gid = 0; - std::uint64_t rid = 0; - bool rob_valid = false; - std::uint64_t rob = 0; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; - bool rob_wrap = false; -}; - -struct LookupObs { - std::uint64_t cycle = 0; - std::uint64_t pc = 0; - std::uint64_t addr = 0; - std::uint64_t data = 0; -}; - -struct TerminalEvent { - std::uint64_t cycle = 0; - std::uint64_t pc = 0; -}; - -struct FrameSpec { - unsigned begin_reg = 10; - unsigned end_reg = 19; - std::uint64_t uimm = kExpectedUimm; - std::uint64_t return_pc = kOuterReturnPc; -}; - -struct Observations { - bool prechecks_ok = false; - std::uint32_t outer_call_raw32 = 0; - std::uint16_t outer_call_setret_raw16 = 0; - std::uint64_t decoded_call_target_pc = 0; - std::uint64_t decoded_call_return_pc = 0; - std::uint64_t old_sp = 0; - std::uint64_t new_sp = 0; - bool snapshot_valid = false; - std::vector snapshot_regs; - std::vector snapshot_values; - std::vector fentry_accepts; - std::vector fentry_completes; - std::vector fentry_commits; - std::vector fentry_stores; - std::vector fret_lookups; - std::vector fret_accepts; - std::vector fret_completes; - std::vector fret_commits; - std::vector markers; - std::vector restarts; - std::vector nested_nonmatches; - std::uint64_t commits = 0; - std::uint64_t cycles = 0; -}; - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --memory-hex --reset-pc --reset-sp " - << " --report [--max-cycles N] [--self-test-only]\n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--memory-hex" && i + 1 < argc) { - args.memory_hex = argv[++i]; - } else if (arg == "--reset-pc" && i + 1 < argc) { - args.reset_pc = parse_u64_arg(argv[++i], "--reset-pc"); - } else if (arg == "--reset-sp" && i + 1 < argc) { - args.reset_sp = parse_u64_arg(argv[++i], "--reset-sp"); - } else if (arg == "--max-cycles" && i + 1 < argc) { - args.max_cycles = parse_u64_arg(argv[++i], "--max-cycles"); - } else if (arg == "--report" && i + 1 < argc) { - args.report = argv[++i]; - } else if (arg == "--self-test-only") { - args.self_test_only = true; - } else if (arg == "--qemu" || arg == "--qemu-trace" || - arg == "--expected-rows" || arg == "--replay-rows" || - arg == "--result-hint") { - throw std::runtime_error("oracle/replay option is forbidden: " + arg); - } else { - usage(argv[0]); - } - } - if (args.memory_hex.empty() || args.report.empty()) { - usage(argv[0]); - } - return args; -} - -int decode_dst_begin(std::uint32_t raw) { - return static_cast((raw >> 15) & 0x1fU); -} - -int decode_dst_end(std::uint32_t raw) { - return static_cast((raw >> 20) & 0x1fU); -} - -int decode_uimm(std::uint32_t raw) { - return static_cast((((raw >> 7) & 0x1fU) << 10) | - (((raw >> 25) & 0x7fU) << 3)); -} - -std::int64_t sign_extend(std::uint64_t value, unsigned bits) { - const std::uint64_t sign = 1ULL << (bits - 1U); - const std::uint64_t mask = (1ULL << bits) - 1ULL; - value &= mask; - return static_cast((value ^ sign) - sign); -} - -std::uint64_t decode_call_target(std::uint64_t pc, std::uint32_t raw) { - if ((raw & 0x7fffU) != 0x4001U) { - throw std::runtime_error("outer CALL BSTART parcel precheck failed"); - } - return static_cast( - static_cast(pc) + sign_extend(raw >> 15U, 17U) * 2); -} - -std::uint64_t decode_call_return(std::uint64_t pc, std::uint16_t raw) { - if ((raw & 0xf83fU) != 0x5016U) { - throw std::runtime_error("outer CALL C.SETRET parcel precheck failed"); - } - return pc + 4ULL + ((raw >> 6U) & 0x1fU) * 2ULL; -} - -std::vector enumerate_registers(unsigned begin, unsigned end) { - if (begin < kArchitecturalA0 || begin > kArchitecturalX3 || - end < kArchitecturalA0 || end > kArchitecturalX3) { - throw std::runtime_error("template register is outside A0..X3"); - } - std::vector regs; - unsigned current = begin; - for (unsigned steps = 0; steps <= kArchitecturalX3 - kArchitecturalA0; - ++steps) { - regs.push_back(current); - if (current == end) { - return regs; - } - current = current == kArchitecturalX3 ? kArchitecturalA0 : current + 1U; - } - throw std::runtime_error("register range did not terminate"); -} - -std::vector expected_slots(std::uint64_t new_sp, - const FrameSpec &spec) { - std::vector slots; - const auto regs = enumerate_registers(spec.begin_reg, spec.end_reg); - for (std::size_t i = 0; i < regs.size(); ++i) { - slots.push_back(new_sp + spec.uimm - 8ULL - i * 8ULL); - } - return slots; -} - -Row read_row(const VLinxCoreBenchmarkAutonomousTop &dut, - std::uint64_t observation_cycle) { - Row row; - row.valid = dut.io_commit_rows_0_valid; - row.cycle = observation_cycle; - row.trace_cycle = dut.io_commit_rows_0_cycle; - row.pc = dut.io_commit_rows_0_pc; - row.insn = dut.io_commit_rows_0_insn; - row.bid = dut.io_commit_rows_0_identity_bid; - row.gid = dut.io_commit_rows_0_identity_gid; - row.rid = dut.io_commit_rows_0_identity_rid; - row.wb_valid = dut.io_commit_rows_0_wb_valid; - row.wb_rd = dut.io_commit_rows_0_wb_reg; - row.wb_data = dut.io_commit_rows_0_wb_data; - row.src0_valid = dut.io_commit_rows_0_src0_valid; - row.src0_data = dut.io_commit_rows_0_src0_data; - row.mem_valid = dut.io_commit_rows_0_mem_valid; - row.mem_addr = dut.io_commit_rows_0_mem_addr; - row.mem_wdata = dut.io_commit_rows_0_mem_wdata; - row.mem_rdata = dut.io_commit_rows_0_mem_rdata; - row.mem_size = dut.io_commit_rows_0_mem_size; - row.next_pc = dut.io_commit_rows_0_nextPc; - row.rob_valid = dut.io_commit_rows_0_rob_valid; - row.rob_value = dut.io_commit_rows_0_rob_value; - row.rob_wrap = dut.io_commit_rows_0_rob_wrap; - row.block_bid_valid = dut.io_commit_rows_0_blockBidValid; - row.block_bid = dut.io_commit_rows_0_blockBid; - return row; -} - -void clear_inputs(VLinxCoreBenchmarkAutonomousTop &dut) { - dut.io_startValid = 0; - dut.io_resetPc = 0; - dut.io_resetSp = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_restartSp = 0; - dut.io_flushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 0; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_loadLookupData = 0; -} - -void eval_with_memory(VLinxCoreBenchmarkAutonomousTop &dut, - const SparseMemory &memory) { - dut.eval(); - if (dut.io_loadLookupValid) { - dut.io_loadLookupData = memory.read_u64_or_zero(dut.io_loadLookupAddr); - dut.eval(); - } -} - -void tick(VLinxCoreBenchmarkAutonomousTop &dut, const SparseMemory &memory) { - dut.clock = 0; - eval_with_memory(dut, memory); - dut.clock = 1; - eval_with_memory(dut, memory); - dut.clock = 0; - eval_with_memory(dut, memory); -} - -void run_prechecks(const SparseMemory &memory) { - const auto call_raw = memory.read_u32(kOuterCallPc); - const auto setret = - static_cast(memory.read_u48(kOuterCallPc) >> 32U); - if (call_raw != kOuterCallRaw32 || setret != kOuterCallSetretRaw16 || - decode_call_target(kOuterCallPc, call_raw) != kFentryPc || - decode_call_return(kOuterCallPc, setret) != kOuterReturnPc || - memory.read_u32(kFentryPc) != kFentryRaw || - memory.read_u32(kFretPc) != kFretRaw || - decode_dst_begin(kFentryRaw) != 10 || - decode_dst_end(kFentryRaw) != 19 || - decode_uimm(kFentryRaw) != static_cast(kExpectedUimm) || - decode_dst_begin(kFretRaw) != 10 || - decode_dst_end(kFretRaw) != 19 || - decode_uimm(kFretRaw) != static_cast(kExpectedUimm)) { - throw std::runtime_error("natural ELF decode precheck failed"); - } - const auto slots = expected_slots(kExpectedNewSp, FrameSpec{}); - if (slots.front() != kExpectedRaSlot || slots.back() != kExpectedLastSlot || - kNestedRaSlot == kExpectedRaSlot || kNestedReturnPc == kOuterReturnPc) { - throw std::runtime_error("same-frame precheck failed"); - } -} - -AcceptEvent read_accept(const VLinxCoreBenchmarkAutonomousTop &dut, - std::uint64_t cycle) { - return AcceptEvent{ - cycle, - static_cast(dut.io_debugExecuteAcceptedIdentityValid), - static_cast(dut.io_debugExecuteAcceptedBidValid), - dut.io_debugExecuteAcceptedBidValue, - static_cast(dut.io_debugExecuteAcceptedRidValid), - dut.io_debugExecuteAcceptedRidValue, - dut.io_debugExecuteAcceptedStid, - static_cast(dut.io_debugExecuteAcceptedBidWrap), - static_cast(dut.io_debugExecuteAcceptedRidWrap)}; -} - -bool exact_accept_complete_commit(const std::vector &accepts, - const std::vector &completes, - const std::vector &commits) { - if (accepts.size() != 1 || completes.size() != 1 || commits.size() != 1) { - return false; - } - const auto &accept = accepts.front(); - const auto &complete = completes.front(); - const auto &commit = commits.front(); - return accept.identity_valid && accept.bid_valid && accept.rid_valid && - accept.stid == 0 && commit.rob_valid && - accept.bid == commit.bid && accept.rid == commit.rid && - accept.rid == complete.rob && accept.rid == commit.rob_value && - accept.rid_wrap == commit.rob_wrap && - accept.cycle <= complete.cycle && complete.cycle <= commit.cycle; -} - -bool store_identity_matches(const StoreObs &store, const Row &fentry) { - return store.pc == kFentryPc && store.rob_valid && fentry.rob_valid && - store.rob == fentry.rob_value && store.bid == fentry.bid && - store.gid == fentry.gid && store.rid == fentry.rid && - store.rob_wrap == fentry.rob_wrap && - store.block_bid_valid && fentry.block_bid_valid && - store.block_bid == fentry.block_bid; -} - -struct Check { - bool ok = false; - std::string reason; -}; - -Check validate_common(const Observations &obs, const FrameSpec &spec) { - if (!obs.prechecks_ok || !obs.snapshot_valid) { - return {false, "setup_or_snapshot"}; - } - if (obs.decoded_call_target_pc != kFentryPc || - obs.decoded_call_return_pc != spec.return_pc || - obs.old_sp < obs.new_sp || obs.old_sp - obs.new_sp != spec.uimm) { - return {false, "call_or_stack"}; - } - const auto regs = enumerate_registers(spec.begin_reg, spec.end_reg); - if (obs.snapshot_regs != regs || obs.snapshot_values.size() != regs.size() || - obs.snapshot_values.empty() || obs.snapshot_values.front() != spec.return_pc) { - return {false, "register_snapshot"}; - } - if (!exact_accept_complete_commit(obs.fentry_accepts, obs.fentry_completes, - obs.fentry_commits)) { - return {false, "fentry_identity"}; - } - if (!exact_accept_complete_commit(obs.fret_accepts, obs.fret_completes, - obs.fret_commits)) { - return {false, "fret_identity"}; - } - const auto &fentry = obs.fentry_commits.front(); - const auto &fret = obs.fret_commits.front(); - if (fentry.pc != kFentryPc || fentry.insn != kFentryRaw || - fentry.src0_data != spec.return_pc || - !fentry.wb_valid || fentry.wb_data != obs.new_sp || - fret.pc != kFretPc || fret.insn != kFretRaw || - !fret.block_bid_valid) { - return {false, "macro_commit"}; - } - return {true, "ok"}; -} - -Check validate_terminal(const Observations &obs, std::uint64_t target) { - if (obs.fret_completes.size() != 1) { - return {false, "terminal_without_complete"}; - } - const auto complete_cycle = obs.fret_completes.front().cycle; - std::size_t matching_markers = 0; - std::size_t immediate_restarts = 0; - for (const auto &event : obs.markers) { - if (event.pc == kFretPc) { - ++matching_markers; - if (event.cycle != complete_cycle) { - return {false, "wrong_terminal_cycle"}; - } - } - } - for (const auto &event : obs.restarts) { - if (event.cycle == complete_cycle + 1ULL) { - ++immediate_restarts; - if (event.pc != target) { - return {false, "wrong_terminal_target"}; - } - } - } - if (matching_markers != 1) { - return {false, "matching_terminal_count"}; - } - if (immediate_restarts != 1) { - return {false, "immediate_restart_count"}; - } - return {true, "ok"}; -} - -Check validate_future(const Observations &obs, const FrameSpec &spec) { - const Check common = validate_common(obs, spec); - if (!common.ok) { - return common; - } - const auto slots = expected_slots(obs.new_sp, spec); - const auto &fentry = obs.fentry_commits.front(); - if (obs.fentry_stores.size() != slots.size()) { - return {false, "store_count"}; - } - for (std::size_t i = 0; i < slots.size(); ++i) { - const auto &store = obs.fentry_stores[i]; - if (store.addr != slots[i]) { - return {false, "store_order_or_unknown"}; - } - if (store.data != obs.snapshot_values[i]) { - return {false, "store_data"}; - } - if (store.size != 8 || !store_identity_matches(store, fentry)) { - return {false, "store_identity"}; - } - if (obs.fret_lookups.empty() || - store.cycle >= obs.fret_lookups.front().cycle) { - return {false, "late_same_frame_store"}; - } - } - if (obs.fret_lookups.size() != slots.size()) { - return {false, "lookup_count"}; - } - for (std::size_t i = 0; i < slots.size(); ++i) { - const auto &lookup = obs.fret_lookups[i]; - if (lookup.pc != kFretPc || lookup.addr != slots[i] || - lookup.data != obs.snapshot_values[i]) { - return {false, "lookup_order_or_data"}; - } - } - const auto &fret = obs.fret_commits.front(); - if (fret.mem_addr != slots.front() || - fret.mem_rdata != spec.return_pc || - fret.wb_data != spec.return_pc || - fret.next_pc != spec.return_pc) { - return {false, "parent_return"}; - } - for (const auto &store : obs.fentry_stores) { - if (store.cycle >= obs.fret_lookups.front().cycle) { - return {false, "late_same_frame_store"}; - } - } - return validate_terminal(obs, spec.return_pc); -} - -Check validate_current_red(const Observations &obs, const FrameSpec &spec) { - const Check common = validate_common(obs, spec); - if (!common.ok) { - return common; - } - const auto slots = expected_slots(obs.new_sp, spec); - const auto &fentry = obs.fentry_commits.front(); - if (obs.fentry_stores.size() != 1 || - obs.fentry_stores.front().addr != slots.back() || - obs.fentry_stores.front().data != 0 || - obs.fentry_stores.front().size != 8 || - !store_identity_matches(obs.fentry_stores.front(), fentry)) { - return {false, "not_exact_current_store"}; - } - if (obs.fret_lookups.size() != 1 || - obs.fret_lookups.front().addr != slots.front() || - obs.fret_lookups.front().data != 0) { - return {false, "not_exact_current_lookup"}; - } - if (obs.fentry_stores.front().cycle >= obs.fret_lookups.front().cycle) { - return {false, "late_same_frame_store"}; - } - const auto &fret = obs.fret_commits.front(); - if (fret.mem_addr != slots.front() || fret.mem_rdata != 0 || - fret.wb_data != 0 || fret.next_pc != 0) { - return {false, "not_exact_current_return"}; - } - return validate_terminal(obs, 0); -} - -std::string classify(const Observations &obs) { - const Check current = validate_current_red(obs, FrameSpec{}); - if (current.ok) { - return "current_red_fentry_missing_ra_save"; - } - const Check future = validate_future(obs, FrameSpec{}); - if (future.ok) { - return "future_green_full_range_return"; - } - return "unexpected_observation:" + current.reason + ":" + future.reason; -} - -Observations make_future_case(const FrameSpec &spec) { - Observations obs; - obs.prechecks_ok = true; - obs.decoded_call_target_pc = kFentryPc; - obs.decoded_call_return_pc = spec.return_pc; - obs.old_sp = 4096; - obs.new_sp = obs.old_sp - spec.uimm; - obs.snapshot_valid = true; - obs.snapshot_regs = enumerate_registers(spec.begin_reg, spec.end_reg); - for (std::size_t i = 0; i < obs.snapshot_regs.size(); ++i) { - obs.snapshot_values.push_back(i == 0 ? spec.return_pc : 0x100ULL + i); - } - AcceptEvent fa{10, true, true, 4, true, 7, 0}; - Row fc; - fc.cycle = 12; - fc.pc = kFentryPc; - fc.insn = kFentryRaw; - fc.bid = 4; - fc.gid = 42; - fc.rid = 7; - fc.src0_valid = true; - fc.src0_data = spec.return_pc; - fc.wb_valid = true; - fc.wb_data = obs.new_sp; - fc.rob_valid = true; - fc.rob_value = 7; - fc.block_bid_valid = true; - fc.block_bid = 25; - obs.fentry_accepts.push_back(fa); - obs.fentry_completes.push_back(CompleteEvent{11, 7}); - obs.fentry_commits.push_back(fc); - const auto slots = expected_slots(obs.new_sp, spec); - for (std::size_t i = 0; i < slots.size(); ++i) { - obs.fentry_stores.push_back( - StoreObs{20 + i, kFentryPc, slots[i], obs.snapshot_values[i], 8, - fc.bid, fc.gid, fc.rid, true, fc.rob_value, true, - fc.block_bid}); - obs.fret_lookups.push_back( - LookupObs{50 + i, kFretPc, slots[i], obs.snapshot_values[i]}); - } - AcceptEvent ra{49, true, true, 6, true, 9, 0}; - Row rc; - rc.cycle = 70; - rc.pc = kFretPc; - rc.insn = kFretRaw; - rc.bid = 6; - rc.rid = 9; - rc.rob_valid = true; - rc.rob_value = 9; - rc.block_bid_valid = true; - rc.block_bid = 38; - rc.mem_addr = slots.front(); - rc.mem_rdata = spec.return_pc; - rc.wb_data = spec.return_pc; - rc.next_pc = spec.return_pc; - obs.fret_accepts.push_back(ra); - obs.fret_completes.push_back(CompleteEvent{69, 9}); - obs.fret_commits.push_back(rc); - obs.markers.push_back(TerminalEvent{69, kFretPc}); - obs.restarts.push_back(TerminalEvent{70, spec.return_pc}); - return obs; -} - -void require_self_test(const std::string &name, bool condition) { - if (!condition) { - throw std::runtime_error("classifier self-test failed: " + name); - } - std::cerr << "self-test PASS " << name << "\n"; -} - -void run_classifier_self_tests() { - const FrameSpec normal{}; - const Observations base = make_future_case(normal); - require_self_test("positive-normal", validate_future(base, normal).ok); - - const FrameSpec wrapped{22, 3, 64, 0x1234}; - const Observations wrapped_case = make_future_case(wrapped); - require_self_test("positive-wrapped", - enumerate_registers(22, 3) == - std::vector({22, 23, 2, 3}) && - validate_future(wrapped_case, wrapped).ok); - - auto reject = [&](const std::string &name, Observations candidate) { - require_self_test(name, !validate_future(candidate, normal).ok); - }; - auto candidate = base; - candidate.fentry_stores[1].data ^= 1; - reject("negative-wrong-data", candidate); - candidate = base; - candidate.fentry_stores[1].addr = 0xdeadbeef; - reject("negative-unknown-store", candidate); - candidate = base; - candidate.fentry_stores.push_back(candidate.fentry_stores.front()); - reject("negative-duplicate-store", candidate); - candidate = base; - std::swap(candidate.fentry_stores[0], candidate.fentry_stores[1]); - reject("negative-out-of-order-store", candidate); - candidate = base; - candidate.fentry_stores[0].rob ^= 1; - reject("negative-wrong-rob", candidate); - candidate = base; - candidate.fentry_stores[0].bid ^= 1; - reject("negative-wrong-bid", candidate); - candidate = base; - candidate.fentry_stores[0].block_bid ^= 1; - reject("negative-wrong-block", candidate); - candidate = base; - std::swap(candidate.fret_lookups[0], candidate.fret_lookups[1]); - reject("negative-lookup-order", candidate); - candidate = base; - candidate.fret_lookups[1].data ^= 1; - reject("negative-lookup-data", candidate); - candidate = base; - candidate.markers[0].pc = 0; - reject("negative-terminal-source", candidate); - candidate = base; - candidate.markers[0].cycle += 1; - reject("negative-terminal-cycle", candidate); - candidate = base; - candidate.restarts[0].pc = 0; - reject("negative-terminal-target", candidate); - candidate = base; - candidate.markers.push_back(candidate.markers.front()); - reject("negative-duplicate-terminal", candidate); - candidate = base; - candidate.fentry_stores[0].cycle = candidate.fret_lookups.front().cycle; - reject("negative-late-store", candidate); -} - -Observations run_probe(const Args &args, SparseMemory &memory) { - Observations obs; - run_prechecks(memory); - obs.prechecks_ok = true; - obs.outer_call_raw32 = memory.read_u32(kOuterCallPc); - obs.outer_call_setret_raw16 = - static_cast(memory.read_u48(kOuterCallPc) >> 32U); - obs.decoded_call_target_pc = - decode_call_target(kOuterCallPc, obs.outer_call_raw32); - obs.decoded_call_return_pc = - decode_call_return(kOuterCallPc, obs.outer_call_setret_raw16); - - std::array gpr{}; - gpr[kSpReg] = args.reset_sp; - VLinxCoreBenchmarkAutonomousTop dut; - bool pending_fetch = false; - std::uint64_t pending_fetch_pc = 0; - bool fret_committed = false; - std::uint64_t tail_cycles = 0; - - clear_inputs(dut); - dut.reset = 1; - tick(dut, memory); - tick(dut, memory); - dut.reset = 0; - - for (std::uint64_t cycle = 0; - cycle < args.max_cycles && !Verilated::gotFinish(); ++cycle) { - clear_inputs(dut); - dut.io_startValid = cycle == 0; - dut.io_resetPc = args.reset_pc; - dut.io_resetSp = args.reset_sp; - dut.io_fetchReqReady = pending_fetch ? 0 : 1; - if (pending_fetch) { - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = memory.read_window(pending_fetch_pc); - } - eval_with_memory(dut, memory); - - if (pending_fetch && dut.io_fetchRespValid && dut.io_fetchRespReady) { - pending_fetch = false; - } - if (!pending_fetch && dut.io_fetchReqValid && dut.io_fetchReqReady) { - pending_fetch = true; - pending_fetch_pc = dut.io_fetchReqPc; - } - - if (dut.io_debugExecuteAccepted) { - if (dut.io_debugExecuteAcceptedPc == kFentryPc) { - obs.fentry_accepts.push_back(read_accept(dut, cycle)); - } else if (dut.io_debugExecuteAcceptedPc == kFretPc) { - obs.fret_accepts.push_back(read_accept(dut, cycle)); - } - } - if (dut.io_debugLocalExecuteCompleteValid) { - if (dut.io_debugLocalCompletePc == kFentryPc) { - obs.fentry_completes.push_back( - CompleteEvent{cycle, dut.io_debugExecuteCompleteRobValue}); - } else if (dut.io_debugLocalCompletePc == kFretPc) { - obs.fret_completes.push_back( - CompleteEvent{cycle, dut.io_debugExecuteCompleteRobValue}); - } - } - if (dut.io_loadLookupValid && dut.io_loadLookupPc == kFretPc) { - obs.fret_lookups.push_back( - LookupObs{cycle, dut.io_loadLookupPc, dut.io_loadLookupAddr, - memory.read_u64_or_zero(dut.io_loadLookupAddr)}); - } - if (dut.io_debugMarkerRedirectFire && !obs.fret_accepts.empty()) { - obs.markers.push_back( - TerminalEvent{cycle, dut.io_debugMarkerRedirectPc}); - } - if (dut.io_sourceRestartValid && !obs.fret_accepts.empty()) { - obs.restarts.push_back(TerminalEvent{cycle, dut.io_sourceRestartPc}); - } - - if (dut.io_commit_rows_0_valid) { - const Row row = read_row(dut, cycle); - ++obs.commits; - if (row.pc == kFentryPc && row.insn == kFentryRaw) { - if (!obs.snapshot_valid) { - obs.old_sp = gpr[kSpReg]; - obs.new_sp = row.wb_data; - obs.snapshot_regs = enumerate_registers( - decode_dst_begin(kFentryRaw), decode_dst_end(kFentryRaw)); - for (const unsigned reg : obs.snapshot_regs) { - obs.snapshot_values.push_back(gpr[reg]); - } - obs.snapshot_valid = true; - } - obs.fentry_commits.push_back(row); - } else if (row.pc == kFretPc && row.insn == kFretRaw) { - obs.fret_commits.push_back(row); - fret_committed = true; - } - if (row.wb_valid && row.wb_rd < kRegisterCount) { - gpr[row.wb_rd] = row.wb_data; - } - } - - if (dut.io_storeObserveValid) { - StoreObs store{ - cycle, - dut.io_storeObservePc, - dut.io_storeObserveAddr, - dut.io_storeObserveData, - dut.io_storeObserveSize, - dut.io_storeObserveBid, - dut.io_storeObserveGid, - dut.io_storeObserveRid, - static_cast(dut.io_storeObserveRobValid), - dut.io_storeObserveRobValue, - static_cast(dut.io_storeObserveBlockBidValid), - dut.io_storeObserveBlockBid, - static_cast(dut.io_storeObserveRobWrap)}; - if (store.pc == kFentryPc && !obs.fentry_accepts.empty()) { - obs.fentry_stores.push_back(store); - } - if (store.addr == kNestedRaSlot || store.data == kNestedReturnPc) { - obs.nested_nonmatches.push_back(store); - } - memory.apply_store(store.addr, store.data, - static_cast(store.size), - dut.io_storeObserveMask); - } - - tick(dut, memory); - obs.cycles = cycle + 1; - if (fret_committed && ++tail_cycles >= kMaxTailCycles) { - break; - } - } - return obs; -} - -template -void emit_array(std::ostream &out, const std::vector &values, Emit emit) { - out << "["; - for (std::size_t i = 0; i < values.size(); ++i) { - if (i != 0) { - out << ","; - } - emit(out, values[i]); - } - out << "]"; -} - -void write_report(const Args &args, const Observations &obs, - const std::string &status, int exit_code) { - const std::string tmp = args.report + ".tmp"; - std::ofstream out(tmp); - if (!out) { - throw std::runtime_error("failed to open report tmp"); - } - out << "{\n" - << " \"schema\":\"linxcore.bctrl_fentry_fret_natural_observation.v2\",\n" - << " \"status\":\"" << status << "\",\n" - << " \"exit_code\":" << exit_code << ",\n" - << " \"self_tests\":\"pass\",\n" - << " \"prechecks_ok\":" << (obs.prechecks_ok ? "true" : "false") << ",\n" - << " \"decoded_call_target_pc\":" << obs.decoded_call_target_pc << ",\n" - << " \"decoded_call_return_pc\":" << obs.decoded_call_return_pc << ",\n" - << " \"old_sp\":" << obs.old_sp << ",\n" - << " \"new_sp\":" << obs.new_sp << ",\n" - << " \"frame_delta\":" << (obs.old_sp >= obs.new_sp ? obs.old_sp - obs.new_sp : 0) << ",\n" - << " \"snapshot\":{\"valid\":" << (obs.snapshot_valid ? "true" : "false") - << ",\"registers\":"; - emit_array(out, obs.snapshot_regs, - [](std::ostream &s, unsigned value) { s << value; }); - out << ",\"values\":"; - emit_array(out, obs.snapshot_values, - [](std::ostream &s, std::uint64_t value) { s << value; }); - out << "},\n" - << " \"public_io_unavailable\":[" - << "\"accept_raw\",\"complete_raw\",\"complete_bid\",\"complete_stid\"," - << "\"lookup_rob\",\"lookup_bid\",\"marker_rob\",\"restart_source_pc\"," - << "\"commit_trace_cycle_populated\"],\n" - << " \"fentry_accepts\":"; - emit_array(out, obs.fentry_accepts, [](std::ostream &s, const AcceptEvent &v) { - s << "{\"cycle\":" << v.cycle - << ",\"identity_valid\":" << (v.identity_valid ? "true" : "false") - << ",\"bid_valid\":" << (v.bid_valid ? "true" : "false") - << ",\"bid\":" << v.bid - << ",\"rid_valid\":" << (v.rid_valid ? "true" : "false") - << ",\"rid\":" << v.rid << ",\"stid\":" << v.stid - << ",\"bid_wrap\":" << (v.bid_wrap ? "true" : "false") - << ",\"rid_wrap\":" << (v.rid_wrap ? "true" : "false") << "}"; - }); - out << ",\n \"fentry_completes\":"; - emit_array(out, obs.fentry_completes, - [](std::ostream &s, const CompleteEvent &v) { - s << "{\"cycle\":" << v.cycle << ",\"rob\":" << v.rob << "}"; - }); - out << ",\n \"fentry_commits\":"; - emit_array(out, obs.fentry_commits, [](std::ostream &s, const Row &v) { - s << "{\"cycle\":" << v.cycle << ",\"trace_cycle\":" << v.trace_cycle - << ",\"pc\":" << v.pc - << ",\"raw\":" << v.insn << ",\"bid\":" << v.bid - << ",\"gid\":" << v.gid << ",\"rid\":" << v.rid - << ",\"rob\":" << v.rob_value << ",\"block_bid\":" << v.block_bid - << ",\"rob_wrap\":" << (v.rob_wrap ? "true" : "false") - << ",\"src0_valid\":" << (v.src0_valid ? "true" : "false") - << ",\"src0_data\":" << v.src0_data - << ",\"wb_valid\":" << (v.wb_valid ? "true" : "false") - << ",\"wb_data\":" << v.wb_data - << "}"; - }); - out << ",\n \"fret_accepts\":"; - emit_array(out, obs.fret_accepts, [](std::ostream &s, const AcceptEvent &v) { - s << "{\"cycle\":" << v.cycle - << ",\"identity_valid\":" << (v.identity_valid ? "true" : "false") - << ",\"bid_valid\":" << (v.bid_valid ? "true" : "false") - << ",\"bid\":" << v.bid - << ",\"rid_valid\":" << (v.rid_valid ? "true" : "false") - << ",\"rid\":" << v.rid << ",\"stid\":" << v.stid - << ",\"bid_wrap\":" << (v.bid_wrap ? "true" : "false") - << ",\"rid_wrap\":" << (v.rid_wrap ? "true" : "false") << "}"; - }); - out << ",\n \"fret_completes\":"; - emit_array(out, obs.fret_completes, - [](std::ostream &s, const CompleteEvent &v) { - s << "{\"cycle\":" << v.cycle << ",\"rob\":" << v.rob << "}"; - }); - out << ",\n \"fret_commits\":"; - emit_array(out, obs.fret_commits, [](std::ostream &s, const Row &v) { - s << "{\"cycle\":" << v.cycle << ",\"trace_cycle\":" << v.trace_cycle - << ",\"pc\":" << v.pc - << ",\"raw\":" << v.insn << ",\"bid\":" << v.bid - << ",\"gid\":" << v.gid << ",\"rid\":" << v.rid - << ",\"rob\":" << v.rob_value << ",\"block_bid\":" << v.block_bid - << ",\"rob_wrap\":" << (v.rob_wrap ? "true" : "false") - << ",\"mem_addr\":" << v.mem_addr << ",\"mem_rdata\":" << v.mem_rdata - << ",\"wb_data\":" << v.wb_data << ",\"next_pc\":" << v.next_pc - << "}"; - }); - out << ",\n \"fentry_stores\":"; - emit_array(out, obs.fentry_stores, [](std::ostream &s, const StoreObs &v) { - s << "{\"cycle\":" << v.cycle << ",\"pc\":" << v.pc - << ",\"addr\":" << v.addr << ",\"data\":" << v.data - << ",\"size\":" << v.size << ",\"bid\":" << v.bid - << ",\"gid\":" << v.gid << ",\"rid\":" << v.rid - << ",\"rob_valid\":" << (v.rob_valid ? "true" : "false") - << ",\"rob\":" << v.rob - << ",\"rob_wrap\":" << (v.rob_wrap ? "true" : "false") - << ",\"block_bid_valid\":" << (v.block_bid_valid ? "true" : "false") - << ",\"block_bid\":" << v.block_bid << "}"; - }); - out << ",\n \"fret_lookups\":"; - emit_array(out, obs.fret_lookups, [](std::ostream &s, const LookupObs &v) { - s << "{\"cycle\":" << v.cycle << ",\"pc\":" << v.pc - << ",\"addr\":" << v.addr << ",\"data\":" << v.data << "}"; - }); - out << ",\n \"markers\":"; - emit_array(out, obs.markers, [](std::ostream &s, const TerminalEvent &v) { - s << "{\"cycle\":" << v.cycle << ",\"source_pc\":" << v.pc << "}"; - }); - out << ",\n \"restarts\":"; - emit_array(out, obs.restarts, [](std::ostream &s, const TerminalEvent &v) { - s << "{\"cycle\":" << v.cycle << ",\"target_pc\":" << v.pc << "}"; - }); - out << ",\n \"nested_nonmatches\":"; - emit_array(out, obs.nested_nonmatches, - [](std::ostream &s, const StoreObs &v) { - s << "{\"cycle\":" << v.cycle << ",\"pc\":" << v.pc - << ",\"addr\":" << v.addr << ",\"data\":" << v.data << "}"; - }); - out << ",\n" - << " \"commits\":" << obs.commits << ",\n" - << " \"cycles\":" << obs.cycles << ",\n" - << " \"tail_cycles\":" << kMaxTailCycles << ",\n" - << " \"repair_packet\":\"first owner: block-control FENTRY template sequencing; downstream: backend, LSU, FRET recovery\",\n" - << " \"frame_policy\":\"Sail frame-size arithmetic remains separate\"\n" - << "}\n"; - out.close(); - if (!out || std::rename(tmp.c_str(), args.report.c_str()) != 0) { - throw std::runtime_error("failed to publish report: " + - std::string(std::strerror(errno))); - } -} - -} // namespace - -int main(int argc, char **argv) { - try { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - run_classifier_self_tests(); - if (args.self_test_only) { - Observations empty; - write_report(args, empty, "self_tests_pass", 0); - return 0; - } - - SparseMemory memory; - memory.load_sparse_hex(args.memory_hex); - Observations obs = run_probe(args, memory); - const std::string status = classify(obs); - const bool expect_current_red = - std::getenv("EXPECT_CURRENT_RED") != nullptr; - int exit_code = 2; - if (status == "future_green_full_range_return") { - exit_code = 0; - } else if (status == "current_red_fentry_missing_ra_save") { - exit_code = expect_current_red ? 0 : 1; - } - write_report(args, obs, status, exit_code); - std::cerr << "bctrl-fentry-fret-observation status=" << status - << " exit_code=" << exit_code - << " stores=" << obs.fentry_stores.size() - << " lookups=" << obs.fret_lookups.size() << "\n"; - return exit_code; - } catch (const std::exception &exc) { - std::cerr << "error: " << exc.what() << "\n"; - return 2; - } -} diff --git a/tools/chisel/bctrl_template_accepted_sidecar_handoff_probe_tb.cpp b/tools/chisel/bctrl_template_accepted_sidecar_handoff_probe_tb.cpp deleted file mode 100644 index 6d9033de..00000000 --- a/tools/chisel/bctrl_template_accepted_sidecar_handoff_probe_tb.cpp +++ /dev/null @@ -1,771 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include "VTemplateAcceptedSidecarHandoffProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint16_t kFentry = 429; -constexpr std::uint16_t kFexit = 430; -constexpr std::uint16_t kFretRa = 431; -constexpr std::uint16_t kFretStk = 432; -constexpr std::uint16_t kNonTemplate = 17; -constexpr std::uint64_t kReadyMask = ~0ULL; -constexpr int kArchRegs = 24; -constexpr int kKeyFaultCount = 12; - -struct Identity { - std::uint16_t generation = 0; - std::uint8_t stid = 0; - std::uint8_t pe_id = 3; - std::uint64_t pc = 0x10000; - std::uint64_t raw = 0x29350041ULL; - std::uint16_t opcode = kFentry; - bool bid_valid = true; - bool bid_wrap = true; - std::uint8_t bid_value = 11; - bool gid_valid = true; - bool gid_wrap = false; - std::uint8_t gid_value = 12; - bool rid_valid = true; - bool rid_wrap = true; - std::uint8_t rid_value = 13; - std::uint8_t rob_slot = 13; - bool block_bid_valid = true; - std::uint64_t block_bid = 0xabcddcbaULL; -}; - -struct Scenario { - const char *name; - Identity identity; - std::uint8_t range_m = 2; - std::uint8_t range_n = 4; - std::uint64_t imm = 0x80; - std::uint64_t old_sp = 0x8000; - std::array src_data{0x111, 0x222, 0x333}; -}; - -void require(bool condition, const std::string &message) { - if (!condition) { - throw std::runtime_error(message); - } -} - -void eval(VTemplateAcceptedSidecarHandoffProbe &dut) { - dut.eval(); -} - -void tick(VTemplateAcceptedSidecarHandoffProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); - dut.clock = 0; - eval(dut); -} - -#define DEFINE_MAP_READER(NAME, PREFIX) \ - std::uint8_t NAME(const VTemplateAcceptedSidecarHandoffProbe &dut, int index) { \ - switch (index) { \ - case 0: return dut.PREFIX##_0; case 1: return dut.PREFIX##_1; \ - case 2: return dut.PREFIX##_2; case 3: return dut.PREFIX##_3; \ - case 4: return dut.PREFIX##_4; case 5: return dut.PREFIX##_5; \ - case 6: return dut.PREFIX##_6; case 7: return dut.PREFIX##_7; \ - case 8: return dut.PREFIX##_8; case 9: return dut.PREFIX##_9; \ - case 10: return dut.PREFIX##_10; case 11: return dut.PREFIX##_11; \ - case 12: return dut.PREFIX##_12; case 13: return dut.PREFIX##_13; \ - case 14: return dut.PREFIX##_14; case 15: return dut.PREFIX##_15; \ - case 16: return dut.PREFIX##_16; case 17: return dut.PREFIX##_17; \ - case 18: return dut.PREFIX##_18; case 19: return dut.PREFIX##_19; \ - case 20: return dut.PREFIX##_20; case 21: return dut.PREFIX##_21; \ - case 22: return dut.PREFIX##_22; case 23: return dut.PREFIX##_23; \ - default: throw std::runtime_error("map index outside 24-entry snapshot"); \ - } \ - } - -DEFINE_MAP_READER(bridge_smap, io_bridgeTemplateSmap) -DEFINE_MAP_READER(bridge_cmap, io_bridgeTemplateCmap) -DEFINE_MAP_READER(sidecar_smap, io_sidecarSmap) -DEFINE_MAP_READER(sidecar_cmap, io_sidecarCmap) -DEFINE_MAP_READER(active_smap, io_activeSmap) -DEFINE_MAP_READER(active_cmap, io_activeCmap) - -#undef DEFINE_MAP_READER - -#define DEFINE_KEY_DRIVER(NAME, PREFIX) \ - void NAME(VTemplateAcceptedSidecarHandoffProbe &dut, const Identity &id) { \ - dut.PREFIX##_generation = id.generation; \ - dut.PREFIX##_stid = id.stid; \ - dut.PREFIX##_bidValid = id.bid_valid; \ - dut.PREFIX##_bidWrap = id.bid_wrap; \ - dut.PREFIX##_bidValue = id.bid_value; \ - dut.PREFIX##_gidValid = id.gid_valid; \ - dut.PREFIX##_gidWrap = id.gid_wrap; \ - dut.PREFIX##_gidValue = id.gid_value; \ - dut.PREFIX##_ridValid = id.rid_valid; \ - dut.PREFIX##_ridWrap = id.rid_wrap; \ - dut.PREFIX##_ridValue = id.rid_value; \ - dut.PREFIX##_robSlot = id.rob_slot; \ - } - -DEFINE_KEY_DRIVER(set_cancel_key, io_cancelKey) -DEFINE_KEY_DRIVER(set_decode_release_key, io_releaseDecodeKey) -DEFINE_KEY_DRIVER(set_issue_release_key, io_releaseIssueKey) -DEFINE_KEY_DRIVER(set_memory_release_key, io_releaseMemoryKey) -DEFINE_KEY_DRIVER(set_commit_key, io_parentCommitKey) -DEFINE_KEY_DRIVER(set_recovery_key, io_recoveryKey) - -#undef DEFINE_KEY_DRIVER - -Identity make_identity(std::uint16_t opcode, std::uint8_t stid, - std::uint8_t slot, std::uint8_t serial) { - Identity id; - id.opcode = opcode; - id.stid = stid; - id.rob_slot = slot; - id.rid_value = slot; - id.bid_value = static_cast((slot + 61) & 63); - id.gid_value = static_cast((slot + 62) & 63); - id.pc = 0x10000 + static_cast(serial) * 0x20; - id.raw = 0x29350041ULL + opcode + serial; - id.bid_wrap = (serial & 1U) != 0; - id.gid_wrap = (serial & 2U) != 0; - id.rid_wrap = (serial & 4U) != 0; - id.block_bid = 0xabcddcba00000000ULL | serial; - return id; -} - -Scenario make_scenario(const char *name, std::uint16_t opcode, std::uint8_t stid, - std::uint8_t slot, std::uint8_t serial) { - Scenario scenario; - scenario.name = name; - scenario.identity = make_identity(opcode, stid, slot, serial); - scenario.old_sp = stid == 0 ? 0x8000 : 0x9000; - scenario.src_data = { - 0x1000000000000000ULL | serial, - 0x2000000000000000ULL | serial, - 0x3000000000000000ULL | serial, - }; - return scenario; -} - -void drive_accept(VTemplateAcceptedSidecarHandoffProbe &dut, const Scenario &scenario) { - const Identity &id = scenario.identity; - dut.io_acceptValid = 1; - dut.io_acceptOpcode = id.opcode; - dut.io_acceptStid = id.stid; - dut.io_acceptPeId = id.pe_id; - dut.io_acceptPc = id.pc; - dut.io_acceptRaw = id.raw; - dut.io_acceptImm = scenario.imm; - dut.io_acceptRangeM = scenario.range_m; - dut.io_acceptRangeN = scenario.range_n; - dut.io_acceptBidValid = id.bid_valid; - dut.io_acceptBidWrap = id.bid_wrap; - dut.io_acceptBidValue = id.bid_value; - dut.io_acceptGidValid = id.gid_valid; - dut.io_acceptGidWrap = id.gid_wrap; - dut.io_acceptGidValue = id.gid_value; - dut.io_acceptRidValid = id.rid_valid; - dut.io_acceptRidWrap = id.rid_wrap; - dut.io_acceptRidValue = id.rid_value; - dut.io_acceptUid = 0x9000 + id.rob_slot; - dut.io_acceptBlockBidValid = id.block_bid_valid; - dut.io_acceptBlockBid = id.block_bid; - dut.io_scalarSpHeadBidValue_0 = id.bid_value; - dut.io_scalarSpHeadBidValue_1 = id.bid_value; - dut.io_scalarSpHeadRidValue_0 = id.rid_value; - dut.io_scalarSpHeadRidValue_1 = id.rid_value; - dut.io_scalarSpSnapshot_0 = scenario.old_sp; - dut.io_scalarSpSnapshot_1 = scenario.old_sp; - dut.io_readData_0 = scenario.src_data[0]; - dut.io_readData_1 = scenario.src_data[1]; - dut.io_readData_2 = scenario.src_data[2]; -} - -void clear_pulses(VTemplateAcceptedSidecarHandoffProbe &dut) { - dut.io_acceptValid = 0; - dut.io_pWakeupValid = 0; - dut.io_cancelValid = 0; - dut.io_releaseDecodeValid = 0; - dut.io_releaseIssueValid = 0; - dut.io_releaseMemoryValid = 0; - dut.io_selectedTemplate = 0; - dut.io_parentCommitValid = 0; - dut.io_storeGrant = 0; - dut.io_recoveryValid = 0; - dut.io_globalClear = 0; - dut.io_rfReadResponseValid = 0; - dut.io_loadResponseValid = 0; -} - -void initialize_inputs(VTemplateAcceptedSidecarHandoffProbe &dut) { - clear_pulses(dut); - Scenario initial = make_scenario("initial", kFentry, 0, 13, 0); - drive_accept(dut, initial); - dut.io_acceptValid = 0; - dut.io_robAllocReady = 1; - dut.io_readyMask = kReadyMask; - dut.io_pWakeupTag = 0; - dut.io_localTReadyMask = 0xf; - dut.io_localUReadyMask = 0xf; - dut.io_scalarSpHeadValid_0 = 1; - dut.io_scalarSpHeadValid_1 = 1; - dut.io_issueKeyFaultMask = 0; - dut.io_parentRequestReadyOverride = 1; - set_cancel_key(dut, initial.identity); - set_decode_release_key(dut, initial.identity); - set_issue_release_key(dut, initial.identity); - set_memory_release_key(dut, initial.identity); - set_commit_key(dut, initial.identity); - set_recovery_key(dut, initial.identity); - dut.io_recoveryKillsActive = 0; - dut.io_rfReadReady = 0; - dut.io_rfReadResponseChildIndex = 0; - dut.io_rfReadResponsePhysTag = 0; - dut.io_rfReadResponseData = 0; - dut.io_loadReady = 0; - dut.io_loadResponseChildIndex = 0; - dut.io_loadResponseAddr = 0; - dut.io_loadResponseData = 0; - dut.io_storeReady = 0; - dut.io_rfWriteReady = 0; -} - -void reset(VTemplateAcceptedSidecarHandoffProbe &dut) { - initialize_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - tick(dut); - require(!dut.io_sequencerActive, "reset left the sequencer active"); - require(dut.io_sidecarOccupiedMask == 0, "reset left a sidecar owner"); - require(dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 0 && - dut.io_sidecarMemoryFenceMask == 0, - "reset left sidecar fences asserted"); -} - -std::uint8_t expected_initial_map(std::uint8_t stid, int arch) { - return static_cast(stid * kArchRegs + arch); -} - -void check_accepted_maps(VTemplateAcceptedSidecarHandoffProbe &dut, - const Scenario &scenario) { - for (int arch = 0; arch < kArchRegs; ++arch) { - const auto expected = expected_initial_map(scenario.identity.stid, arch); - require(bridge_smap(dut, arch) == expected && - bridge_cmap(dut, arch) == expected, - std::string(scenario.name) + ": bridge actual map snapshot mismatch"); - require(sidecar_smap(dut, arch) == bridge_smap(dut, arch) && - sidecar_cmap(dut, arch) == bridge_cmap(dut, arch), - std::string(scenario.name) + ": sidecar did not carry accepted maps"); - } -} - -Identity accept_template(VTemplateAcceptedSidecarHandoffProbe &dut, - const Scenario &scenario) { - eval(dut); - const auto prior_occupied_mask = dut.io_sidecarOccupiedMask; - const auto prior_decode_fence_mask = dut.io_sidecarDecodeFenceMask; - const auto prior_issue_fence_mask = dut.io_sidecarIssueFenceMask; - const auto prior_memory_fence_mask = dut.io_sidecarMemoryFenceMask; - const auto accepted_mask = (1U << scenario.identity.stid); - drive_accept(dut, scenario); - eval(dut); - require(dut.io_bridgeInReady && dut.io_bridgeAccepted, - std::string(scenario.name) + ": template was not accepted"); - require(dut.io_bridgeTemplateSnapshotValid && dut.io_sidecarValid && - dut.io_sidecarReady && dut.io_sidecarFire, - std::string(scenario.name) + ": accepted template sidecar was not atomic"); - require(dut.io_sidecarStid == scenario.identity.stid && - dut.io_sidecarRaw == scenario.identity.raw && - dut.io_sidecarRangeM == scenario.range_m && - dut.io_sidecarRangeN == scenario.range_n && - dut.io_sidecarSrc0Imm == scenario.imm, - std::string(scenario.name) + ": accepted sidecar payload mismatch"); - require(dut.io_sidecarGeneration == dut.io_bridgeTemplateSnapshotGeneration, - std::string(scenario.name) + ": sidecar generation was reconstructed"); - check_accepted_maps(dut, scenario); - - Identity accepted = scenario.identity; - accepted.generation = dut.io_sidecarGeneration; - tick(dut); - dut.io_acceptValid = 0; - eval(dut); - require(dut.io_sidecarOccupiedMask == (prior_occupied_mask | accepted_mask), - std::string(scenario.name) + ": sidecar owner was not retained"); - require(dut.io_sidecarDecodeFenceMask == (prior_decode_fence_mask | accepted_mask) && - dut.io_sidecarIssueFenceMask == (prior_issue_fence_mask | accepted_mask) && - dut.io_sidecarMemoryFenceMask == (prior_memory_fence_mask | accepted_mask), - std::string(scenario.name) + ": accepted sidecar fences missing"); - return accepted; -} - -void global_clear(VTemplateAcceptedSidecarHandoffProbe &dut) { - clear_pulses(dut); - dut.io_globalClear = 1; - tick(dut); - clear_pulses(dut); - eval(dut); -} - -void wait_for_parent_valid(VTemplateAcceptedSidecarHandoffProbe &dut, - const std::string &name) { - for (int cycle = 0; cycle < 24; ++cycle) { - eval(dut); - if (dut.io_parentRequestValid) { - return; - } - tick(dut); - } - throw std::runtime_error(name + ": real issue path did not produce a parent request"); -} - -void check_active_payload(VTemplateAcceptedSidecarHandoffProbe &dut, - const Scenario &scenario, const Identity &accepted) { - const Identity &source = scenario.identity; - require(dut.io_sequencerActive, std::string(scenario.name) + ": no active owner"); - require(dut.io_activeGeneration == accepted.generation && - dut.io_activeStid == source.stid && - dut.io_activePeId == source.pe_id && - dut.io_activePc == source.pc && - dut.io_activeOpcode == source.opcode && - dut.io_activeRaw == source.raw, - std::string(scenario.name) + ": retained scalar identity mismatch"); - require(dut.io_activeBidValid == source.bid_valid && - dut.io_activeBidWrap == source.bid_wrap && - dut.io_activeBidValue == source.bid_value && - dut.io_activeGidValid == source.gid_valid && - dut.io_activeGidWrap == source.gid_wrap && - dut.io_activeGidValue == source.gid_value && - dut.io_activeRidValid == source.rid_valid && - dut.io_activeRidWrap == source.rid_wrap && - dut.io_activeRidValue == source.rid_value && - dut.io_activeRobSlot == source.rob_slot, - std::string(scenario.name) + ": retained full ROB identity mismatch"); - require(dut.io_activeBlockBidValid == source.block_bid_valid && - dut.io_activeBlockBid == source.block_bid && - dut.io_activeCommitBid == source.bid_value && - dut.io_activeCommitGid == source.gid_value && - dut.io_activeCommitRid == source.rid_value, - std::string(scenario.name) + ": retained block/commit identity mismatch"); - require(dut.io_activeOldSp == scenario.old_sp && - dut.io_activeSrcData_0 == scenario.src_data[0] && - dut.io_activeSrcData_1 == scenario.src_data[1] && - dut.io_activeSrcData_2 == scenario.src_data[2], - std::string(scenario.name) + ": retained SP/source payload mismatch"); - for (int arch = 0; arch < kArchRegs; ++arch) { - require(active_smap(dut, arch) == expected_initial_map(source.stid, arch) && - active_cmap(dut, arch) == expected_initial_map(source.stid, arch), - std::string(scenario.name) + ": sequencer retained map mismatch"); - } -} - -void transfer_parent(VTemplateAcceptedSidecarHandoffProbe &dut, - const Scenario &scenario, const Identity &accepted) { - wait_for_parent_valid(dut, scenario.name); - require(dut.io_issuedTemplateGenerationValid && - dut.io_issuedTemplateGeneration == accepted.generation, - std::string(scenario.name) + ": generation did not survive real issue"); - require(dut.io_issuedStid == accepted.stid && - dut.io_issuedRaw == scenario.identity.raw && - dut.io_issuedBidValue == scenario.identity.bid_value && - dut.io_issuedGidValue == scenario.identity.gid_value && - dut.io_issuedRidValue == scenario.identity.rid_value && - dut.io_issuedSrcData0 == scenario.src_data[0], - std::string(scenario.name) + ": issued payload mismatch"); - require(dut.io_parentRequestReady && dut.io_parentTransfer && - dut.io_issueValid && dut.io_issueReady && dut.io_issueFire, - std::string(scenario.name) + ": exact parent transfer did not fire"); - require(dut.io_sidecarOccupiedMask == (1U << accepted.stid) && - !dut.io_sequencerActive, - std::string(scenario.name) + ": pre-edge ownership was not sidecar-only"); - tick(dut); - eval(dut); - require(dut.io_sidecarOccupiedMask == 0 && dut.io_sequencerActive, - std::string(scenario.name) + ": transfer did not atomically change owner"); - require(dut.io_transferCount == 1 && dut.io_enqueueCount == 1, - std::string(scenario.name) + ": transfer/enqueue was not one-shot"); - require(dut.io_sidecarDecodeFenceMask == (1U << accepted.stid) && - dut.io_sidecarIssueFenceMask == (1U << accepted.stid) && - dut.io_sidecarMemoryFenceMask == (1U << accepted.stid) && - dut.io_decodeFence && dut.io_issueFence && dut.io_memoryFence, - std::string(scenario.name) + ": ownership transfer released a fence"); - check_active_payload(dut, scenario, accepted); -} - -std::vector legal_ring(std::uint8_t m, std::uint8_t n) { - std::vector result; - std::uint8_t value = m; - for (int guard = 0; guard < 22; ++guard) { - result.push_back(value); - if (value == n) { - return result; - } - value = value == 23 ? 2 : static_cast(value + 1); - } - throw std::runtime_error("test range did not terminate"); -} - -bool is_entry(const Scenario &scenario) { - return scenario.identity.opcode == kFentry; -} - -std::uint64_t expected_new_sp(const Scenario &scenario) { - const auto frame = scenario.imm & 0x7fffULL; - return is_entry(scenario) ? scenario.old_sp - frame : scenario.old_sp + frame; -} - -std::uint64_t expected_child_addr(const Scenario &scenario, std::size_t index) { - const auto offset = 8ULL * (index + 1); - if (is_entry(scenario)) { - return expected_new_sp(scenario) + (scenario.imm & 0x7fffULL) - offset; - } - return expected_new_sp(scenario) - offset; -} - -void gather_public_range(VTemplateAcceptedSidecarHandoffProbe &dut, - const Scenario &scenario) { - tick(dut); // CaptureParent -> GatherChildren - const auto ring = legal_ring(scenario.range_m, scenario.range_n); - for (std::size_t index = 0; index < ring.size(); ++index) { - clear_pulses(dut); - eval(dut); - const auto data = 0xa000000000000000ULL | index; - if (is_entry(scenario)) { - require(dut.io_rfReadRequestValid && - dut.io_rfReadRequestChildIndex == index && - dut.io_rfReadRequestArchReg == ring[index] && - dut.io_rfReadRequestPhysTag == - expected_initial_map(scenario.identity.stid, ring[index]), - std::string(scenario.name) + ": retained range/map RF request mismatch"); - dut.io_rfReadReady = 1; - tick(dut); - dut.io_rfReadReady = 0; - dut.io_rfReadResponseValid = 1; - dut.io_rfReadResponseChildIndex = index; - dut.io_rfReadResponsePhysTag = - expected_initial_map(scenario.identity.stid, ring[index]); - dut.io_rfReadResponseData = data; - tick(dut); - } else { - const auto address = expected_child_addr(scenario, index); - require(dut.io_loadRequestValid && - dut.io_loadRequestChildIndex == index && - dut.io_loadRequestArchReg == ring[index] && - dut.io_loadRequestAddr == address, - std::string(scenario.name) + ": retained range/imm load request mismatch"); - dut.io_loadReady = 1; - tick(dut); - dut.io_loadReady = 0; - dut.io_loadResponseValid = 1; - dut.io_loadResponseChildIndex = index; - dut.io_loadResponseAddr = address; - dut.io_loadResponseData = data; - tick(dut); - } - } - clear_pulses(dut); - eval(dut); - require(dut.io_completionValid && - dut.io_completionResult == expected_new_sp(scenario) && - dut.io_completionNewSp == expected_new_sp(scenario), - std::string(scenario.name) + ": retained immediate did not reach completion"); -} - -Identity mutate_key(Identity id, int field) { - switch (field) { - case 0: id.stid ^= 1; break; - case 1: id.bid_valid = !id.bid_valid; break; - case 2: id.bid_wrap = !id.bid_wrap; break; - case 3: id.bid_value ^= 1; break; - case 4: id.gid_valid = !id.gid_valid; break; - case 5: id.gid_wrap = !id.gid_wrap; break; - case 6: id.gid_value ^= 1; break; - case 7: id.rid_valid = !id.rid_valid; break; - case 8: id.rid_wrap = !id.rid_wrap; break; - case 9: id.rid_value ^= 1; break; - case 10: id.rob_slot ^= 1; break; - case 11: id.generation ^= 1; break; - default: throw std::runtime_error("invalid full-key mutation"); - } - return id; -} - -void run_opcode_classification(VTemplateAcceptedSidecarHandoffProbe &dut) { - const std::array opcodes{kFentry, kFexit, kFretRa, kFretStk}; - for (std::size_t index = 0; index < opcodes.size(); ++index) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - const auto scenario = make_scenario( - "template-opcode-classification", opcodes[index], index == 3 ? 1 : 0, - static_cast(8 + index), static_cast(index)); - (void)accept_template(dut, scenario); - require(dut.io_enqueueCount == 1, - "accepted template opcode did not enqueue exactly once"); - } -} - -void run_non_template_classification(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - auto scenario = make_scenario("non-template-classification", kNonTemplate, 0, 18, 8); - drive_accept(dut, scenario); - eval(dut); - require(dut.io_bridgeAccepted && dut.io_bridgeOutValid, - "non-template did not follow ordinary bridge acceptance"); - require(!dut.io_bridgeTemplateSnapshotValid && !dut.io_sidecarValid && - !dut.io_sidecarFire, - "non-template was classified as a template sidecar"); - tick(dut); - dut.io_acceptValid = 0; - for (int cycle = 0; cycle < 8; ++cycle) { - tick(dut); - } - require(dut.io_enqueueCount == 0 && dut.io_sidecarOccupiedMask == 0, - "non-template created sidecar ownership"); -} - -void run_sidecar_accept_backpressure(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - const auto first = make_scenario("sidecar-accept-backpressure", kFentry, 0, 19, 9); - (void)accept_template(dut, first); - auto blocked = first; - blocked.identity.pc += 4; - blocked.identity.raw ^= 0x100; - drive_accept(dut, blocked); - eval(dut); - require(!dut.io_sidecarReady && !dut.io_bridgeInReady && - !dut.io_bridgeAccepted && !dut.io_sidecarFire, - "occupied same-STID sidecar did not block rename acceptance"); - dut.io_acceptValid = 0; -} - -void run_issue_key_mismatch_matrix(VTemplateAcceptedSidecarHandoffProbe &dut) { - static const std::array names{ - "stid", "bid-valid", "bid-wrap", "bid-value", - "gid-valid", "gid-wrap", "gid-value", - "rid-valid", "rid-wrap", "rid-value", "rob-slot", "generation", - }; - for (int field = 0; field < kKeyFaultCount; ++field) { - reset(dut); - dut.io_issueKeyFaultMask = 1U << field; - const auto scenario = make_scenario(names[field], kFentry, 0, 20, 10); - (void)accept_template(dut, scenario); - bool rejected = false; - for (int cycle = 0; cycle < 24; ++cycle) { - eval(dut); - require(!dut.io_parentRequestValid && !dut.io_parentTransfer, - std::string(names[field]) + ": mismatched issue formed parent request"); - if (dut.io_issueValid && dut.io_issueReady) { - tick(dut); - rejected = true; - break; - } - tick(dut); - } - require(rejected, std::string(names[field]) + ": mismatched issue was not consumed"); - require(dut.io_mismatchDropCount == 1 && - dut.io_staleGenerationDropCount == (field == 11 ? 1 : 0), - std::string(names[field]) + ": mismatch counters were not isolated"); - require(dut.io_sidecarOccupiedMask == 1 && dut.io_transferCount == 0 && - !dut.io_sequencerActive, - std::string(names[field]) + ": mismatch destroyed or transferred owner"); - } -} - -void run_downstream_backpressure_and_retention( - VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - auto scenario = make_scenario("downstream-parent-backpressure", kFentry, 1, 21, 11); - scenario.range_m = 22; - scenario.range_n = 3; - scenario.imm = 0x98; - const Identity accepted = accept_template(dut, scenario); - wait_for_parent_valid(dut, scenario.name); - require(!dut.io_parentRequestReady && !dut.io_parentTransfer && - dut.io_issueValid && !dut.io_issueFire, - "downstream backpressure did not hold the real issue request"); - const auto held_generation = dut.io_issuedTemplateGeneration; - const auto held_raw = dut.io_issuedRaw; - const auto held_src0 = dut.io_issuedSrcData0; - tick(dut); - tick(dut); - require(dut.io_issueValid && !dut.io_issueFire && - dut.io_issuedTemplateGeneration == held_generation && - dut.io_issuedRaw == held_raw && - dut.io_issuedSrcData0 == held_src0 && - dut.io_sidecarOccupiedMask == 2 && !dut.io_sequencerActive, - "held issue valid/bits changed under parent backpressure"); - - dut.io_parentRequestReadyOverride = 1; - transfer_parent(dut, scenario, accepted); - set_recovery_key(dut, accepted); - dut.io_recoveryValid = 1; - dut.io_recoveryKillsActive = 1; - eval(dut); - require(dut.io_selfRestartObserved && !dut.io_cancelObserved, - "matching self restart was not observed after transfer"); - tick(dut); - clear_pulses(dut); - require(dut.io_sequencerActive && dut.io_sidecarOccupiedMask == 0 && - dut.io_enqueueCount == 1, - "self restart recreated or discarded sidecar ownership"); - check_active_payload(dut, scenario, accepted); - gather_public_range(dut, scenario); -} - -void run_pre_issue_cancel(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - const auto scenario = make_scenario("pre-issue-cancel", kFexit, 0, 22, 12); - const Identity accepted = accept_template(dut, scenario); - set_cancel_key(dut, accepted); - dut.io_cancelValid = 1; - tick(dut); - clear_pulses(dut); - require(dut.io_sidecarOccupiedMask == 0 && - dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 0 && - dut.io_sidecarMemoryFenceMask == 0 && - dut.io_transferCount == 0 && !dut.io_sequencerActive, - "pre-issue cancellation did not clear only the sidecar owner"); -} - -void run_same_cycle_cancel_dominance(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - const auto scenario = make_scenario("same-cycle-cancel-dominance", kFretRa, 0, 23, 13); - const Identity accepted = accept_template(dut, scenario); - wait_for_parent_valid(dut, scenario.name); - set_cancel_key(dut, accepted); - dut.io_cancelValid = 1; - dut.io_parentRequestReadyOverride = 1; - eval(dut); - require(!dut.io_parentRequestValid && !dut.io_parentTransfer && - !dut.io_issueFire, - "matching cancel lost same-cycle dominance to transfer"); - tick(dut); - clear_pulses(dut); - require(dut.io_sidecarOccupiedMask == 0 && !dut.io_sequencerActive && - dut.io_transferCount == 0, - "same-cycle cancel left or transferred an owner"); -} - -void pulse_release(VTemplateAcceptedSidecarHandoffProbe &dut, int fence, - const Identity &key) { - clear_pulses(dut); - if (fence == 0) { - set_decode_release_key(dut, key); - dut.io_releaseDecodeValid = 1; - } else if (fence == 1) { - set_issue_release_key(dut, key); - dut.io_releaseIssueValid = 1; - } else { - set_memory_release_key(dut, key); - dut.io_releaseMemoryValid = 1; - } - tick(dut); - clear_pulses(dut); -} - -void run_independent_fence_release_matrix(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - const auto scenario = make_scenario("independent-fence-release", kFretStk, 0, 24, 14); - const Identity accepted = accept_template(dut, scenario); - transfer_parent(dut, scenario, accepted); - - for (int fence = 0; fence < 3; ++fence) { - for (int field = 0; field < kKeyFaultCount; ++field) { - pulse_release(dut, fence, mutate_key(accepted, field)); - require(dut.io_sidecarDecodeFenceMask == 1 && - dut.io_sidecarIssueFenceMask == 1 && - dut.io_sidecarMemoryFenceMask == 1, - "wrong full-key fence release changed retained masks"); - } - } - - pulse_release(dut, 0, accepted); - require(dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 1 && - dut.io_sidecarMemoryFenceMask == 1, - "matching decode release was not independent"); - pulse_release(dut, 1, accepted); - require(dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 0 && - dut.io_sidecarMemoryFenceMask == 1, - "matching issue release was not independent"); - pulse_release(dut, 2, accepted); - require(dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 0 && - dut.io_sidecarMemoryFenceMask == 0, - "matching memory release was not independent"); - require(dut.io_decodeFence && dut.io_issueFence && dut.io_memoryFence && - dut.io_sequencerActive, - "sidecar releases altered the distinct sequencer fence owner"); -} - -void run_different_stid_and_global_clear(VTemplateAcceptedSidecarHandoffProbe &dut) { - reset(dut); - dut.io_parentRequestReadyOverride = 0; - const auto stid0 = make_scenario("stid0-owner", kFentry, 0, 25, 15); - const Identity accepted0 = accept_template(dut, stid0); - const auto stid1 = make_scenario("stid1-independent-owner", kFexit, 1, 26, 16); - const Identity accepted1 = accept_template(dut, stid1); - require(accepted1.generation == static_cast(accepted0.generation + 1) && - dut.io_sidecarOccupiedMask == 3 && - dut.io_sidecarDecodeFenceMask == 3 && - dut.io_sidecarIssueFenceMask == 3 && - dut.io_sidecarMemoryFenceMask == 3, - "two STIDs did not retain independent maps/generations/owners"); - - set_cancel_key(dut, accepted0); - dut.io_cancelValid = 1; - tick(dut); - clear_pulses(dut); - require(dut.io_sidecarOccupiedMask == 2 && - dut.io_sidecarDecodeFenceMask == 2 && - dut.io_sidecarIssueFenceMask == 2 && - dut.io_sidecarMemoryFenceMask == 2, - "STID0 cancel disturbed independent STID1 owner"); - - global_clear(dut); - require(dut.io_sidecarOccupiedMask == 0 && - dut.io_sidecarDecodeFenceMask == 0 && - dut.io_sidecarIssueFenceMask == 0 && - dut.io_sidecarMemoryFenceMask == 0 && - !dut.io_sequencerActive, - "global clear did not clear all sidecar/sequencer state"); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - try { - VTemplateAcceptedSidecarHandoffProbe dut; - run_opcode_classification(dut); - run_non_template_classification(dut); - run_sidecar_accept_backpressure(dut); - run_issue_key_mismatch_matrix(dut); - run_downstream_backpressure_and_retention(dut); - run_pre_issue_cancel(dut); - run_same_cycle_cancel_dominance(dut); - run_independent_fence_release_matrix(dut); - run_different_stid_and_global_clear(dut); - std::cout << "bctrl-template-accepted-sidecar-handoff-probe: PASS\n"; - return 0; - } catch (const std::exception &ex) { - std::cerr << "bctrl-template-accepted-sidecar-handoff-probe: FAIL: " - << ex.what() << "\n"; - return 1; - } -} diff --git a/tools/chisel/benchmark_autonomous_top_natural_tb.cpp b/tools/chisel/benchmark_autonomous_top_natural_tb.cpp deleted file mode 100644 index 5b1861c1..00000000 --- a/tools/chisel/benchmark_autonomous_top_natural_tb.cpp +++ /dev/null @@ -1,2352 +0,0 @@ -#include "commit_trace_jsonl.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef LINXCORE_BENCHMARK_AUTONOMOUS_NATURAL_SELF_TEST -#include "VLinxCoreBenchmarkAutonomousTop.h" -#include "verilated.h" -#endif - -namespace { - -constexpr std::uint64_t kUartDataAddr = 0x10000000ULL; -constexpr std::uint64_t kTestFinisherAddr = 0x10009000ULL; -constexpr std::uint16_t kFinisherPass = 0x5555U; -constexpr std::uint64_t kReducedServiceAcrcRequest = 1; -constexpr std::uint64_t kSysExit = 93; -constexpr std::uint64_t kSysSetTidAddress = 96; - -std::uint64_t clamp_hist_index(std::uint64_t value, std::uint64_t max_index) { - return value > max_index ? max_index : value; -} - -std::uint64_t parse_u64_arg(const std::string &value, const std::string &name) { - errno = 0; - char *end = nullptr; - const unsigned long long parsed = std::strtoull(value.c_str(), &end, 0); - if (errno != 0 || end == value.c_str() || *end != '\0') { - throw std::runtime_error("invalid " + name + ": " + value); - } - return static_cast(parsed); -} - -std::string json_escape(const std::string &value) { - std::ostringstream out; - for (const char ch : value) { - switch (ch) { - case '\\': out << "\\\\"; break; - case '"': out << "\\\""; break; - case '\n': out << "\\n"; break; - case '\r': out << "\\r"; break; - case '\t': out << "\\t"; break; - default: - if (static_cast(ch) < 0x20) { - out << "\\u" << std::hex << std::setw(4) << std::setfill('0') - << static_cast(static_cast(ch)); - } else { - out << ch; - } - } - } - return out.str(); -} - -class SparseMemory { -public: - void store_byte(std::uint64_t addr, std::uint8_t value) { - bytes_[addr] = value; - } - - void load_sparse_hex(const std::string &path) { - std::ifstream in(path); - if (!in) { - throw std::runtime_error("failed to open sparse memory image: " + path); - } - std::string line; - std::uint64_t line_no = 0; - std::uint64_t count = 0; - while (std::getline(in, line)) { - ++line_no; - const auto comment = line.find('#'); - if (comment != std::string::npos) { - line.resize(comment); - } - std::istringstream iss(line); - std::string addr_token; - std::string byte_token; - std::string extra; - if (!(iss >> addr_token)) { - continue; - } - if (!(iss >> byte_token) || (iss >> extra)) { - throw std::runtime_error("invalid sparse memory line at " + path + ":" + std::to_string(line_no)); - } - const std::uint64_t addr = parse_u64_arg(addr_token, "sparse memory address"); - const std::uint64_t byte = parse_u64_arg(byte_token, "sparse memory byte"); - if (byte > 0xffU) { - throw std::runtime_error("sparse memory byte out of range at " + path + ":" + std::to_string(line_no)); - } - store_byte(addr, static_cast(byte)); - ++count; - } - if (count == 0) { - throw std::runtime_error("sparse memory image is empty: " + path); - } - } - - std::uint64_t read_window(std::uint64_t pc) const { - std::uint64_t value = 0; - for (std::uint8_t i = 0; i < 8; ++i) { - std::uint8_t byte = 0xffU; - const bool found = read_byte(pc + i, byte); - if (!found && i == 0) { - throw std::runtime_error("fetch memory missing first byte at pc=0x" + hex(pc)); - } - value |= static_cast(byte) << (static_cast(i) * 8U); - } - return value; - } - - std::uint64_t read_u64_or_zero(std::uint64_t addr) const { - std::uint64_t value = 0; - for (std::uint8_t i = 0; i < 8; ++i) { - std::uint8_t byte = 0; - (void)read_byte(addr + i, byte); - value |= static_cast(byte) << (static_cast(i) * 8U); - } - return value; - } - - void apply_store(std::uint64_t addr, std::uint64_t data, std::uint8_t size, std::uint8_t mask) { - if (size == 0 || size > 8) { - throw std::runtime_error("unsupported committed store size: " + std::to_string(size)); - } - std::uint8_t effective_mask = mask; - if (effective_mask == 0) { - const std::uint8_t low = static_cast(addr & 0x7U); - if (low + size > 8) { - throw std::runtime_error("committed store crosses 8-byte observation lane"); - } - effective_mask = static_cast(((1U << size) - 1U) << low); - } - const std::uint64_t lane_base = addr & ~0x7ULL; - for (std::uint8_t i = 0; i < 8; ++i) { - if ((effective_mask & (1U << i)) == 0) { - continue; - } - store_byte( - lane_base + i, - static_cast((data >> (static_cast(i) * 8U)) & 0xffU)); - } - } - - static std::string hex(std::uint64_t value) { - std::ostringstream out; - out << std::hex << value; - return out.str(); - } - -private: - bool read_byte(std::uint64_t addr, std::uint8_t &value) const { - const auto it = bytes_.find(addr); - if (it == bytes_.end()) { - return false; - } - value = it->second; - return true; - } - - std::map bytes_; -}; - -struct ReducedServiceRobId { - bool valid = false; - bool wrap = false; - std::uint64_t value = 0; -}; - -struct ReducedServiceIdentity { - std::uint64_t stid = 0; - ReducedServiceRobId bid; - ReducedServiceRobId gid; - ReducedServiceRobId rid; -}; - -struct ReducedServiceRequest { - std::uint64_t request_type = 0; - ReducedServiceIdentity identity; - std::uint64_t a0 = 0; - std::uint64_t a1 = 0; - std::uint64_t a2 = 0; - std::uint64_t a3 = 0; - std::uint64_t a4 = 0; - std::uint64_t a5 = 0; - std::uint64_t a7 = 0; -}; - -struct ReducedServiceResponse { - std::uint64_t request_type = 0; - ReducedServiceIdentity identity; - std::uint64_t a0 = 0; -}; - -class ReducedServiceResponder { -public: - bool request_ready() const { - return !response_valid_ && !unsupported_ && !exit_observed_; - } - - bool response_valid() const { - return response_valid_; - } - - const ReducedServiceResponse &response() const { - return response_; - } - - std::uint64_t service_requests() const { - return service_requests_; - } - - std::uint64_t service_responses() const { - return service_responses_; - } - - bool have_last_service_nr() const { - return have_last_service_nr_; - } - - std::uint64_t last_service_nr() const { - return last_service_nr_; - } - - bool unsupported() const { - return unsupported_; - } - - std::uint64_t unsupported_service_nr() const { - return unsupported_service_nr_; - } - - bool exit_observed() const { - return exit_observed_; - } - - std::uint64_t exit_code() const { - return exit_code_; - } - - const ReducedServiceRequest &exit_request() const { - return exit_request_; - } - - void observe_cycle(bool request_fire, const ReducedServiceRequest &request, bool response_ready) { - const bool response_fire = response_valid_ && response_ready; - if (response_fire) { - response_valid_ = false; - ++service_responses_; - } - - if (!request_fire) { - return; - } - - ++service_requests_; - have_last_service_nr_ = true; - last_service_nr_ = request.a7; - - if (request.request_type == kReducedServiceAcrcRequest && - request.a7 == kSysSetTidAddress) { - response_.request_type = request.request_type; - response_.identity = request.identity; - response_.a0 = 1; - response_valid_ = true; - return; - } - - if (request.request_type == kReducedServiceAcrcRequest && - request.a7 == kSysExit) { - exit_observed_ = true; - exit_code_ = request.a0; - exit_request_ = request; - return; - } - - unsupported_ = true; - unsupported_service_nr_ = request.a7; - } - -private: - bool response_valid_ = false; - bool unsupported_ = false; - bool exit_observed_ = false; - bool have_last_service_nr_ = false; - std::uint64_t service_requests_ = 0; - std::uint64_t service_responses_ = 0; - std::uint64_t last_service_nr_ = 0; - std::uint64_t unsupported_service_nr_ = 0; - std::uint64_t exit_code_ = 0; - ReducedServiceResponse response_; - ReducedServiceRequest exit_request_; -}; - -struct Args { - std::string memory_hex; - std::string commit_trace; - std::string event_trace; - std::string uart_output; - std::string manifest; - std::uint64_t reset_pc = 0; - std::uint64_t reset_sp = 0; - std::uint64_t max_cycles = 1000000; - std::uint64_t event_sample_period = 1; - std::uint64_t commit_sample_period = 1; -}; - -std::string terminal_status( - bool finisher_write, - bool finisher_pass, - bool trap, - bool unsupported, - bool halted) { - if (finisher_write) { - return finisher_pass ? "finisher_pass" : "finisher_fail"; - } - if (trap) { - return "trap"; - } - if (unsupported) { - return "unsupported"; - } - if (halted) { - return "halted"; - } - return "timeout"; -} - -bool finisher_code_is_pass(std::uint16_t code) { - return code == kFinisherPass; -} - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --memory-hex --reset-pc --reset-sp " - << " --commit-trace --event-trace --uart-output " - << " --manifest [--max-cycles N] [--event-sample-period N]" - << " [--commit-sample-period N]\n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--memory-hex" && i + 1 < argc) { - args.memory_hex = argv[++i]; - } else if (arg == "--reset-pc" && i + 1 < argc) { - args.reset_pc = parse_u64_arg(argv[++i], "--reset-pc"); - } else if (arg == "--reset-sp" && i + 1 < argc) { - args.reset_sp = parse_u64_arg(argv[++i], "--reset-sp"); - } else if (arg == "--max-cycles" && i + 1 < argc) { - args.max_cycles = parse_u64_arg(argv[++i], "--max-cycles"); - } else if (arg == "--event-sample-period" && i + 1 < argc) { - args.event_sample_period = parse_u64_arg(argv[++i], "--event-sample-period"); - } else if (arg == "--commit-sample-period" && i + 1 < argc) { - args.commit_sample_period = parse_u64_arg(argv[++i], "--commit-sample-period"); - } else if (arg == "--commit-trace" && i + 1 < argc) { - args.commit_trace = argv[++i]; - } else if (arg == "--event-trace" && i + 1 < argc) { - args.event_trace = argv[++i]; - } else if (arg == "--uart-output" && i + 1 < argc) { - args.uart_output = argv[++i]; - } else if (arg == "--manifest" && i + 1 < argc) { - args.manifest = argv[++i]; - } else if (arg == "--qemu-trace" || arg == "--expected-rows" || arg == "--qemu" || - arg == "--replay-rows" || arg == "--result-hint") { - throw std::runtime_error("oracle/replay option is forbidden in natural mode: " + arg); - } else { - usage(argv[0]); - } - } - if (args.memory_hex.empty() || args.commit_trace.empty() || args.event_trace.empty() || - args.uart_output.empty() || args.manifest.empty()) { - usage(argv[0]); - } - return args; -} - -void write_manifest_atomic( - const Args &args, - const std::string &status, - std::uint64_t cycles, - std::uint64_t commits, - std::uint64_t fetch_requests, - std::uint64_t fetch_responses, - std::uint64_t service_requests, - std::uint64_t service_responses, - bool have_last_service_nr, - std::uint64_t last_service_nr, - bool have_unsupported_service_nr, - std::uint64_t unsupported_service_nr, - bool have_sys_exit_code, - std::uint64_t sys_exit_code, - std::uint16_t finisher_code, - bool finisher_pass, - const std::string &uart, - const std::string &performance_json = "{}") { - const std::string tmp = args.manifest + ".tmp"; - std::ofstream out(tmp); - if (!out) { - throw std::runtime_error("failed to open manifest tmp: " + tmp); - } - out << "{\n" - << " \"schema\":\"linxcore.benchmark_autonomous_natural.v1\",\n" - << " \"terminal_status\":\"" << status << "\",\n" - << " \"cycles\":" << cycles << ",\n" - << " \"commits\":" << commits << ",\n" - << " \"ipc\":" << std::setprecision(12) - << (cycles == 0 ? 0.0 : static_cast(commits) / static_cast(cycles)) - << ",\n" - << " \"fetch_requests\":" << fetch_requests << ",\n" - << " \"fetch_responses\":" << fetch_responses << ",\n" - << " \"service_requests\":" << service_requests << ",\n" - << " \"service_responses\":" << service_responses << ",\n" - << " \"last_service_nr\":"; - if (have_last_service_nr) { - out << last_service_nr; - } else { - out << "null"; - } - out << ",\n" - << " \"unsupported_service_nr\":"; - if (have_unsupported_service_nr) { - out << unsupported_service_nr; - } else { - out << "null"; - } - out << ",\n" - << " \"sys_exit_code\":"; - if (have_sys_exit_code) { - out << sys_exit_code; - } else { - out << "null"; - } - out << ",\n" - << " \"reset_pc\":" << args.reset_pc << ",\n" - << " \"reset_sp\":" << args.reset_sp << ",\n" - << " \"max_cycles\":" << args.max_cycles << ",\n" - << " \"event_sample_period\":" << args.event_sample_period << ",\n" - << " \"commit_sample_period\":" << args.commit_sample_period << ",\n" - << " \"finisher_code\":" << finisher_code << ",\n" - << " \"finisher_pass\":" << (finisher_pass ? "true" : "false") << ",\n" - << " \"uart\":\"" << json_escape(uart) << "\",\n" - << " \"performance\":" << performance_json << ",\n" - << " \"artifacts\":{\n" - << " \"memory_hex\":\"" << json_escape(args.memory_hex) << "\",\n" - << " \"commit_trace\":\"" << json_escape(args.commit_trace) << "\",\n" - << " \"event_trace\":\"" << json_escape(args.event_trace) << "\",\n" - << " \"uart_output\":\"" << json_escape(args.uart_output) << "\"\n" - << " }\n" - << "}\n"; - out.close(); - if (!out) { - throw std::runtime_error("failed to write manifest tmp: " + tmp); - } - if (std::rename(tmp.c_str(), args.manifest.c_str()) != 0) { - throw std::runtime_error("failed to publish manifest: " + std::string(std::strerror(errno))); - } -} - -} // namespace - -#ifdef LINXCORE_BENCHMARK_AUTONOMOUS_NATURAL_SELF_TEST -int run_terminal_self_test(int argc, char **argv) { - std::string self_test_case; - Args args; - std::string uart; - std::uint64_t cycles = 0; - std::uint64_t commits = 0; - std::uint64_t fetch_requests = 0; - std::uint64_t fetch_responses = 0; - std::uint64_t service_requests = 0; - std::uint64_t service_responses = 0; - bool have_last_service_nr = false; - std::uint64_t last_service_nr = 0; - bool have_unsupported_service_nr = false; - std::uint64_t unsupported_service_nr = 0; - bool have_sys_exit_code = false; - std::uint64_t sys_exit_code = 0; - std::uint16_t finisher_code = 0; - bool finisher_pass = false; - std::string status = "timeout"; - - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--self-test-case" && i + 1 < argc) { - self_test_case = argv[++i]; - } else if (arg == "--manifest" && i + 1 < argc) { - args.manifest = argv[++i]; - } else if (arg == "--uart-output" && i + 1 < argc) { - args.uart_output = argv[++i]; - } else { - usage(argv[0]); - } - } - if (self_test_case.empty() || args.manifest.empty() || args.uart_output.empty()) { - usage(argv[0]); - } - - args.memory_hex = "self-test.mem"; - args.commit_trace = "self-test.commit.jsonl"; - args.event_trace = "self-test.events.jsonl"; - args.reset_pc = 0x1000; - args.reset_sp = 0x2000; - args.max_cycles = 17; - - if (self_test_case == "uart") { - uart = "OK\n"; - status = terminal_status(false, false, false, false, true); - cycles = 7; - commits = 2; - fetch_requests = 3; - fetch_responses = 3; - } else if (self_test_case == "finisher-pass") { - finisher_code = kFinisherPass; - finisher_pass = finisher_code_is_pass(finisher_code); - status = terminal_status(true, finisher_pass, false, false, false); - cycles = 1; - commits = 1; - } else if (self_test_case == "finisher-fail") { - finisher_code = 0x3333U; - finisher_pass = finisher_code_is_pass(finisher_code); - status = terminal_status(true, finisher_pass, false, false, false); - cycles = 1; - commits = 1; - } else if (self_test_case == "exit-pass") { - have_sys_exit_code = true; - sys_exit_code = 0; - finisher_code = kFinisherPass; - finisher_pass = true; - status = terminal_status(true, finisher_pass, false, false, false); - service_requests = 1; - have_last_service_nr = true; - last_service_nr = kSysExit; - cycles = 2; - commits = 2; - } else if (self_test_case == "exit-fail") { - have_sys_exit_code = true; - sys_exit_code = 7; - finisher_pass = false; - status = terminal_status(true, finisher_pass, false, false, false); - service_requests = 1; - have_last_service_nr = true; - last_service_nr = kSysExit; - cycles = 2; - commits = 2; - } else if (self_test_case == "trap") { - status = terminal_status(false, false, true, false, false); - cycles = 4; - } else if (self_test_case == "timeout") { - status = terminal_status(false, false, false, false, false); - cycles = args.max_cycles; - fetch_requests = 5; - fetch_responses = 4; - } else { - throw std::runtime_error("unknown self-test case: " + self_test_case); - } - - std::ofstream uart_out(args.uart_output); - if (!uart_out) { - throw std::runtime_error("failed to open UART output: " + args.uart_output); - } - uart_out << uart; - uart_out.close(); - if (!uart_out) { - throw std::runtime_error("failed to write UART output: " + args.uart_output); - } - - write_manifest_atomic( - args, - status, - cycles, - commits, - fetch_requests, - fetch_responses, - service_requests, - service_responses, - have_last_service_nr, - last_service_nr, - have_unsupported_service_nr, - unsupported_service_nr, - have_sys_exit_code, - sys_exit_code, - finisher_code, - finisher_pass, - uart); - std::cout << "benchmark-autonomous-natural-self-test-case: " << self_test_case << "\n"; - return status == "finisher_pass" ? 0 : 1; -} - -int run_self_test() { - SparseMemory mem; - mem.store_byte(0x1000, 0x11); - mem.store_byte(0x1001, 0x22); - mem.store_byte(0x1002, 0x33); - if (mem.read_window(0x1000) != 0xffffffffff332211ULL) { - throw std::runtime_error("fetch window helper failed"); - } - mem.apply_store(0x1001, 0x0000000000bbaa00ULL, 2, 0x06); - if (mem.read_u64_or_zero(0x1000) != 0x0000000000bbaa11ULL) { - throw std::runtime_error("masked store helper failed"); - } - mem.apply_store(0x1004, 0x8877665544332211ULL, 4, 0); - if (mem.read_u64_or_zero(0x1000) != 0x8877665500bbaa11ULL) { - throw std::runtime_error("derived-mask store helper failed"); - } - if (terminal_status(true, true, true, true, true) != "finisher_pass") { - throw std::runtime_error("finisher pass priority helper failed"); - } - if (terminal_status(true, false, false, false, false) != "finisher_fail") { - throw std::runtime_error("finisher fail helper failed"); - } - if (terminal_status(false, false, true, true, true) != "trap") { - throw std::runtime_error("trap priority helper failed"); - } - if (terminal_status(false, false, false, true, true) != "unsupported") { - throw std::runtime_error("unsupported priority helper failed"); - } - if (terminal_status(false, false, false, false, false) != "timeout") { - throw std::runtime_error("timeout helper failed"); - } - if (!finisher_code_is_pass(kFinisherPass)) { - throw std::runtime_error("finisher pass code helper failed"); - } - if (finisher_code_is_pass(0x0001U)) { - throw std::runtime_error("finisher fail code helper failed"); - } - ReducedServiceResponder responder; - if (!responder.request_ready() || responder.response_valid()) { - throw std::runtime_error("service responder idle handshake failed"); - } - ReducedServiceRequest request; - request.request_type = kReducedServiceAcrcRequest; - request.identity.stid = 3; - request.identity.bid = {true, true, 17}; - request.identity.gid = {true, false, 9}; - request.identity.rid = {true, true, 4}; - request.a0 = 0x12345678ULL; - request.a7 = kSysSetTidAddress; - responder.observe_cycle(true, request, false); - if (!responder.response_valid() || responder.request_ready()) { - throw std::runtime_error("service responder next-cycle response/backpressure failed"); - } - const auto held = responder.response(); - responder.observe_cycle(false, request, false); - if (!responder.response_valid() || responder.response().a0 != held.a0 || - responder.response().identity.bid.value != 17 || - responder.service_requests() != 1 || responder.service_responses() != 0 || - !responder.have_last_service_nr() || responder.last_service_nr() != kSysSetTidAddress) { - throw std::runtime_error("service responder hold/identity failed"); - } - responder.observe_cycle(false, request, true); - if (responder.response_valid() || !responder.request_ready() || - responder.service_requests() != 1 || responder.service_responses() != 1) { - throw std::runtime_error("service responder response fire accounting failed"); - } - request.a7 = kSysExit; - request.a0 = 0; - request.identity.bid = {true, false, 23}; - responder.observe_cycle(true, request, false); - if (!responder.exit_observed() || responder.exit_code() != 0 || - responder.exit_request().a7 != kSysExit || - responder.exit_request().identity.bid.value != 23 || - responder.response_valid() || responder.request_ready() || - responder.service_requests() != 2 || responder.service_responses() != 1 || - !responder.have_last_service_nr() || responder.last_service_nr() != kSysExit) { - throw std::runtime_error("service responder exit syscall terminal latch failed"); - } - responder.observe_cycle(false, request, true); - if (responder.service_requests() != 2 || responder.service_responses() != 1 || - !responder.exit_observed() || responder.exit_request().identity.bid.value != 23 || - responder.response_valid() || responder.request_ready()) { - throw std::runtime_error("service responder exit identity/no-response failed"); - } - ReducedServiceResponder failing_exit_responder; - request.a7 = kSysExit; - request.a0 = 42; - failing_exit_responder.observe_cycle(true, request, true); - if (!failing_exit_responder.exit_observed() || failing_exit_responder.exit_code() != 42 || - failing_exit_responder.response_valid() || - failing_exit_responder.service_responses() != 0) { - throw std::runtime_error("service responder nonzero exit accounting failed"); - } - ReducedServiceResponder unknown_responder; - request.a7 = 9999; - unknown_responder.observe_cycle(true, request, false); - if (!unknown_responder.unsupported() || unknown_responder.unsupported_service_nr() != 9999 || - unknown_responder.response_valid() || unknown_responder.request_ready()) { - throw std::runtime_error("service responder unknown syscall fail-closed failed"); - } - Args args; - args.memory_hex = "memory.mem"; - args.commit_trace = "commit.jsonl"; - args.event_trace = "events.jsonl"; - args.uart_output = "uart.txt"; - args.manifest = "/tmp/linxcore-natural-self-test-manifest.json"; - args.reset_pc = 0x1000; - args.reset_sp = 0x2000; - args.max_cycles = 12; - write_manifest_atomic( - args, - "finisher_pass", - 9, - 3, - 4, - 4, - 1, - 1, - true, - kSysSetTidAddress, - false, - 0, - false, - 0, - kFinisherPass, - true, - "A\n"); - std::cout << "benchmark-autonomous-natural-self-test: ok\n"; - return 0; -} - -int main(int argc, char **argv) { - try { - if (argc == 2 && std::string(argv[1]) == "--self-test") { - return run_self_test(); - } - if (argc > 1 && std::string(argv[1]) == "--self-test-case") { - return run_terminal_self_test(argc, argv); - } - (void)parse_args(argc, argv); - std::cerr << "self-test build only supports --self-test and argument validation\n"; - return 2; - } catch (const std::exception &exc) { - std::cerr << "error: " << exc.what() << "\n"; - return 2; - } -} -#else -struct EventSample { - bool fetch_req_fire = false; - bool fetch_resp_fire = false; - bool commit_valid = false; - bool source_out_fire = false; - bool source_restart_valid = false; - bool source_blocked = false; - bool source_active = false; - bool source_waiting_response = false; - bool source_packet_valid = false; - bool block_marker_stop_redirect_valid = false; - bool marker_redirect_fire = false; - bool marker_redirect_pending = false; - bool source_out_ready = false; - bool dense_slot_in_ready = false; - bool dense_slot_out_ready = false; - bool path_decode_ready = false; - bool path_renamed_out_ready = false; - bool issue_in_ready = false; - bool local_incoming_blocked = false; - bool marker_retire_lifecycle_fire = false; - bool commit_head_valid = false; - bool dec_ren_head_rid_valid = false; - bool renamed_out_valid = false; - bool renamed_accepted = false; - bool tu_rename_blocked_by_t_alloc = false; - bool tu_rename_blocked_by_u_alloc = false; - bool tu_retire_command_valid = false; - bool tu_retire_command_fire = false; - bool tu_retire_local_block_commit_pending = false; - bool tu_retire_local_block_commit_valid = false; - bool tu_retire_local_block_commit_ready = false; - bool tu_retire_local_block_commit_fire = false; - bool tu_retire_accepted = false; - bool tu_retire_miss = false; - bool tu_retire_release_mismatch = false; - bool tu_retire_unsupported = false; - bool gpr_commit_accepted = false; - bool rob_rename_update_attempt_valid = false; - bool rob_rename_update_ready = false; - bool rob_rename_update_fire = false; - bool rob_rename_update_ignored = false; - bool issue_enqueue_fire = false; - bool issue_input_valid = false; - bool issue_input_bid_valid = false; - bool issue_input_bid_wrap = false; - bool issue_input_rid_valid = false; - bool issue_input_rid_wrap = false; - bool issue_pick_fire = false; - bool issue_fire = false; - bool issue_output_valid = false; - bool issue_output_bid_valid = false; - bool issue_output_bid_wrap = false; - bool issue_output_rid_valid = false; - bool issue_output_rid_wrap = false; - bool issue_head_valid = false; - bool issue_head_issued = false; - bool issue_head_bid_valid = false; - bool issue_head_bid_wrap = false; - bool issue_head_rid_valid = false; - bool issue_head_rid_wrap = false; - bool issue_all_sources_ready = false; - bool issue_selected_valid = false; - bool issue_selected_read_ready = false; - bool issue_scalar_sp_order_blocked = false; - bool scalar_sp_stid0_issue_head_valid = false; - bool scalar_sp_stid0_issue_head_bid_valid = false; - bool scalar_sp_stid0_issue_head_bid_wrap = false; - bool scalar_sp_stid0_issue_head_rid_valid = false; - bool scalar_sp_stid0_issue_head_rid_wrap = false; - bool p_wakeup_valid = false; - bool p_wakeup_head_match = false; - bool execute_accepted = false; - bool execute_accepted_identity_valid = false; - bool execute_accepted_bid_valid = false; - bool execute_accepted_bid_wrap = false; - bool execute_accepted_rid_valid = false; - bool execute_accepted_rid_wrap = false; - bool execute_busy = false; - bool execute_unsupported = false; - bool execute_complete_valid = false; - bool rob_dealloc_block_last_valid = false; - bool block_scalar_done_fire = false; - bool block_retire_fire = false; - bool scalar_lr_reservation_valid_stid0 = false; - bool scalar_lr_reservation_protocol_error = false; - bool scalar_lr_reservation_blocked_by_flush = false; - bool scalar_lr_reservation_committed_store_invalidate = false; - bool store_sta_queue_valid = false; - bool store_std_queue_valid = false; - bool store_sta_dequeue_fire = false; - bool store_std_dequeue_fire = false; - bool store_sta_insert_ready = false; - bool store_std_insert_ready = false; - bool store_selected_sta = false; - bool store_selected_std = false; - bool store_blocked_by_sta_exec = false; - bool store_blocked_by_std_exec = false; - bool store_stq_insert_valid = false; - bool store_stq_insert_accepted = false; - bool store_stq_insert_conflict = false; - bool store_stq_empty = false; - bool store_stq_full = false; - bool store_stq_stall = false; - std::uint64_t fetch_req_pc = 0; - std::uint64_t fetch_resp_pc = 0; - std::uint64_t commit_pc = 0; - std::uint64_t source_current_pc = 0; - std::uint64_t source_restart_pc = 0; - std::uint64_t block_marker_stop_redirect_pc = 0; - std::uint64_t marker_redirect_pc = 0; - std::uint64_t body_cut_advance_bytes = 0; - std::uint64_t f4_total_len_bytes = 0; - std::uint64_t fret_condition_bits = 0; - std::uint64_t continuation_bits = 0; - std::uint64_t local_pending_counts = 0; - std::uint64_t local_ready_masks = 0; - std::uint64_t decode_block_bits = 0; - std::uint64_t decode_ready_bits = 0; - std::uint64_t tu_rename_source_underflow_mask = 0; - std::uint64_t tu_rename_t_used_entries = 0; - std::uint64_t tu_rename_u_used_entries = 0; - std::uint64_t gpr_reservation_count = 0; - std::uint64_t gpr_reservation_need = 0; - std::uint64_t gpr_free_count = 0; - std::uint64_t gpr_mapq_valid_count = 0; - std::uint64_t gpr_mapq_free_count = 0; - std::uint64_t gpr_free_list_mismatch_count = 0; - std::uint64_t gpr_commit_block_bid = 0; - std::uint64_t gpr_committed_mapq_count = 0; - std::uint64_t gpr_released_phys_count = 0; - std::uint64_t commit_head_status = 0; - std::uint64_t commit_head_rob_value = 0; - std::uint64_t rob_occupied_mask = 0; - std::uint64_t rob_completed_mask = 0; - std::uint64_t rob_dealloc_valid_mask = 0; - std::uint64_t rob_dealloc_count = 0; - std::uint64_t rob_dealloc_block_last_block_bid = 0; - std::uint64_t block_scalar_done_bid = 0; - std::uint64_t block_retire_bid = 0; - std::uint64_t dec_ren_head_pc = 0; - std::uint64_t dec_ren_head_rid_value = 0; - std::uint64_t issue_head_pc = 0; - std::uint64_t issue_head_stid = 0; - std::uint64_t issue_head_bid_value = 0; - std::uint64_t issue_head_rid_value = 0; - std::uint64_t issue_input_pc = 0; - std::uint64_t issue_input_opcode = 0; - std::uint64_t issue_input_bid_value = 0; - std::uint64_t issue_input_rid_value = 0; - std::uint64_t issue_input_stid = 0; - std::uint64_t issue_output_pc = 0; - std::uint64_t issue_output_opcode = 0; - std::uint64_t issue_output_bid_value = 0; - std::uint64_t issue_output_rid_value = 0; - std::uint64_t issue_output_stid = 0; - std::uint64_t issue_head_src_valid_mask = 0; - std::uint64_t issue_head_src_phys_tag[3] = {}; - std::uint64_t issue_source_ready_mask = 0; - std::uint64_t issue_selected_index = 0; - std::uint64_t issue_stage_bits = 0; - std::uint64_t issue_blocked_bits = 0; - std::uint64_t issue_bank_scalar_sp_order_blocked_mask = 0; - std::uint64_t scalar_sp_stid0_issue_head_bid_value = 0; - std::uint64_t scalar_sp_stid0_issue_head_rid_value = 0; - std::uint64_t rf_ready_mask = 0; - std::uint64_t p_wakeup_tag = 0; - std::uint64_t execute_unsupported_opcode = 0; - std::uint64_t execute_accepted_pc = 0; - std::uint64_t execute_accepted_opcode = 0; - std::uint64_t execute_accepted_bid_value = 0; - std::uint64_t execute_accepted_rid_value = 0; - std::uint64_t execute_accepted_stid = 0; - std::uint64_t execute_complete_rob_value = 0; - std::uint64_t execute_complete_pc = 0; - std::uint64_t execute_complete_src_phys_valid_mask = 0; - std::uint64_t execute_complete_src_phys_tag[3] = {}; - std::uint64_t rob_complete_arbiter_bits = 0; - std::uint64_t rob_complete_result_bits = 0; - std::uint64_t scalar_lr_reservation_line_stid0 = 0; - std::uint64_t scalar_lr_reservation_count = 0; - std::uint64_t store_sta_queue_count = 0; - std::uint64_t store_std_queue_count = 0; - std::uint64_t store_stq_insert_index = 0; - std::uint64_t store_stq_occupied_mask = 0; - std::uint64_t store_stq_wait_mask = 0; - std::uint64_t store_stq_commit_mask = 0; - std::uint64_t store_stq_addr_ready_mask = 0; - std::uint64_t store_stq_data_ready_mask = 0; - std::uint64_t store_stq_resident_count = 0; - std::uint64_t store_stq_outstanding_wait_count = 0; -}; - -struct PerfCounters { - std::uint64_t fetch_req_fire = 0; - std::uint64_t fetch_resp_fire = 0; - std::uint64_t fetch_source_active_cycles = 0; - std::uint64_t fetch_source_blocked_cycles = 0; - std::uint64_t fetch_waiting_response_cycles = 0; - std::uint64_t fetch_packet_valid_cycles = 0; - std::uint64_t fetch_source_out_fire = 0; - std::uint64_t fetch_f4_valid_halfword_slots = 0; - std::uint64_t fetch_f4_total_len_bytes = 0; - - std::uint64_t decode_ready_cycles = 0; - std::uint64_t decode_blocked_cycles = 0; - std::array decode_block_bits_hist = {}; - std::uint64_t rename_valid_cycles = 0; - std::uint64_t rename_accepted = 0; - std::uint64_t rename_blocked_cycles = 0; - std::uint64_t rob_rename_update_attempts = 0; - std::uint64_t rob_rename_update_fire = 0; - std::uint64_t rob_rename_update_blocked = 0; - std::uint64_t rob_rename_update_ignored = 0; - - std::uint64_t issue_input_valid_cycles = 0; - std::uint64_t issue_enqueue_fire = 0; - std::uint64_t issue_selected_valid_cycles = 0; - std::uint64_t issue_pick_fire = 0; - std::uint64_t issue_fire = 0; - std::uint64_t issue_head_valid_cycles = 0; - std::uint64_t issue_head_issued_cycles = 0; - std::uint64_t issue_head_unissued_cycles = 0; - std::uint64_t issue_head_residency_runs = 0; - std::uint64_t issue_head_residency_max = 0; - std::uint64_t issue_head_current_run = 0; - std::uint64_t issue_head_last_key = 0; - bool issue_head_last_valid = false; - std::array issue_blocked_bits_hist = {}; - std::array issue_blocked_bit_cycles = {}; - - std::uint64_t execute_accepted = 0; - std::uint64_t execute_busy_cycles = 0; - std::uint64_t execute_complete_valid = 0; - std::uint64_t execute_unsupported = 0; - - std::uint64_t completion_accepted = 0; - std::uint64_t completion_ignored = 0; - std::uint64_t completion_selected_execute = 0; - std::uint64_t completion_selected_replay = 0; - std::uint64_t completion_replay_blocked_by_execute = 0; - std::uint64_t completion_selected_without_accept = 0; - - std::array commit_rows_per_cycle_hist = {}; - std::array rob_dealloc_count_hist = {}; - std::uint64_t commit_head_valid_cycles = 0; - std::uint64_t commit_head_invalid_cycles = 0; - std::array commit_head_status_hist = {}; - - std::uint64_t load_lookup_valid = 0; - std::uint64_t load_execute_granted = 0; - std::uint64_t load_replay_granted = 0; - std::uint64_t load_wait_cycles = 0; - - std::uint64_t store_observe = 0; - std::uint64_t store_observe_pair = 0; - std::uint64_t store_sta_dequeue = 0; - std::uint64_t store_std_dequeue = 0; - std::uint64_t store_stq_insert_valid = 0; - std::uint64_t store_stq_insert_accepted = 0; - std::uint64_t store_stq_insert_conflict = 0; - std::uint64_t store_stq_full_cycles = 0; - std::uint64_t store_stq_stall_cycles = 0; - std::uint64_t store_queue_wait_cycles = 0; - - std::uint64_t service_request_valid_cycles = 0; - std::uint64_t service_request_fire = 0; - std::uint64_t service_response_valid_cycles = 0; - std::uint64_t service_response_fire = 0; - std::uint64_t service_wait_cycles = 0; - - void observe( - const EventSample &sample, - std::uint64_t commit_rows, - std::uint64_t rob_dealloc_count, - bool load_lookup_valid, - bool load_execute_granted, - bool load_replay_granted, - bool store_observe_valid, - bool store_observe_pair_valid, - bool service_request_valid, - bool service_request_fire_now, - bool service_response_valid, - bool service_response_fire_now) { - fetch_req_fire += sample.fetch_req_fire ? 1 : 0; - fetch_resp_fire += sample.fetch_resp_fire ? 1 : 0; - fetch_source_active_cycles += sample.source_active ? 1 : 0; - fetch_source_blocked_cycles += sample.source_blocked ? 1 : 0; - fetch_waiting_response_cycles += sample.source_waiting_response ? 1 : 0; - fetch_packet_valid_cycles += sample.source_packet_valid ? 1 : 0; - fetch_source_out_fire += sample.source_out_fire ? 1 : 0; - fetch_f4_total_len_bytes += sample.f4_total_len_bytes; - fetch_f4_valid_halfword_slots += sample.f4_total_len_bytes / 2U; - - decode_ready_cycles += sample.path_decode_ready ? 1 : 0; - decode_blocked_cycles += sample.decode_block_bits != 0 ? 1 : 0; - decode_block_bits_hist[clamp_hist_index(sample.decode_block_bits, decode_block_bits_hist.size() - 1)]++; - rename_valid_cycles += sample.renamed_out_valid ? 1 : 0; - rename_accepted += sample.renamed_accepted ? 1 : 0; - rename_blocked_cycles += (sample.renamed_out_valid && !sample.renamed_accepted) ? 1 : 0; - rob_rename_update_attempts += sample.rob_rename_update_attempt_valid ? 1 : 0; - rob_rename_update_fire += sample.rob_rename_update_fire ? 1 : 0; - rob_rename_update_blocked += - (sample.rob_rename_update_attempt_valid && !sample.rob_rename_update_ready) ? 1 : 0; - rob_rename_update_ignored += sample.rob_rename_update_ignored ? 1 : 0; - - issue_input_valid_cycles += sample.issue_input_valid ? 1 : 0; - issue_enqueue_fire += sample.issue_enqueue_fire ? 1 : 0; - issue_selected_valid_cycles += sample.issue_selected_valid ? 1 : 0; - issue_pick_fire += sample.issue_pick_fire ? 1 : 0; - issue_fire += sample.issue_fire ? 1 : 0; - issue_blocked_bits_hist[clamp_hist_index(sample.issue_blocked_bits, issue_blocked_bits_hist.size() - 1)]++; - for (std::size_t bit = 0; bit < issue_blocked_bit_cycles.size(); ++bit) { - issue_blocked_bit_cycles[bit] += ((sample.issue_blocked_bits >> bit) & 1ULL) != 0 ? 1 : 0; - } - if (sample.issue_head_valid) { - ++issue_head_valid_cycles; - issue_head_issued_cycles += sample.issue_head_issued ? 1 : 0; - issue_head_unissued_cycles += sample.issue_head_issued ? 0 : 1; - const std::uint64_t key = - (sample.issue_head_pc << 16U) ^ - (sample.issue_head_stid << 12U) ^ - (sample.issue_head_bid_value << 6U) ^ - sample.issue_head_rid_value ^ - (sample.issue_head_issued ? (1ULL << 63U) : 0); - if (!issue_head_last_valid || key != issue_head_last_key) { - if (issue_head_last_valid) { - ++issue_head_residency_runs; - if (issue_head_current_run > issue_head_residency_max) { - issue_head_residency_max = issue_head_current_run; - } - } - issue_head_last_valid = true; - issue_head_last_key = key; - issue_head_current_run = 1; - } else { - ++issue_head_current_run; - } - } else if (issue_head_last_valid) { - ++issue_head_residency_runs; - if (issue_head_current_run > issue_head_residency_max) { - issue_head_residency_max = issue_head_current_run; - } - issue_head_last_valid = false; - issue_head_current_run = 0; - } - - execute_accepted += sample.execute_accepted ? 1 : 0; - execute_busy_cycles += sample.execute_busy ? 1 : 0; - execute_complete_valid += sample.execute_complete_valid ? 1 : 0; - execute_unsupported += sample.execute_unsupported ? 1 : 0; - - const bool complete_accepted = (sample.rob_complete_result_bits & 0x1U) != 0; - const bool complete_ignored = (sample.rob_complete_result_bits & 0x2U) != 0; - const bool selected_execute = (sample.rob_complete_arbiter_bits & 0x1U) != 0; - const bool selected_replay = (sample.rob_complete_arbiter_bits & 0x2U) != 0; - completion_accepted += complete_accepted ? 1 : 0; - completion_ignored += complete_ignored ? 1 : 0; - completion_selected_execute += selected_execute ? 1 : 0; - completion_selected_replay += selected_replay ? 1 : 0; - completion_replay_blocked_by_execute += (sample.rob_complete_arbiter_bits & 0x4U) != 0 ? 1 : 0; - completion_selected_without_accept += - ((selected_execute || selected_replay) && !complete_accepted) ? 1 : 0; - - commit_rows_per_cycle_hist[clamp_hist_index(commit_rows, commit_rows_per_cycle_hist.size() - 1)]++; - rob_dealloc_count_hist[clamp_hist_index(rob_dealloc_count, rob_dealloc_count_hist.size() - 1)]++; - if (sample.commit_head_valid) { - ++commit_head_valid_cycles; - commit_head_status_hist[clamp_hist_index(sample.commit_head_status, commit_head_status_hist.size() - 1)]++; - } else { - ++commit_head_invalid_cycles; - } - - this->load_lookup_valid += load_lookup_valid ? 1 : 0; - this->load_execute_granted += load_execute_granted ? 1 : 0; - this->load_replay_granted += load_replay_granted ? 1 : 0; - load_wait_cycles += (load_lookup_valid && !load_execute_granted && !load_replay_granted) ? 1 : 0; - - store_observe += store_observe_valid ? 1 : 0; - store_observe_pair += store_observe_pair_valid ? 1 : 0; - store_sta_dequeue += sample.store_sta_dequeue_fire ? 1 : 0; - store_std_dequeue += sample.store_std_dequeue_fire ? 1 : 0; - store_stq_insert_valid += sample.store_stq_insert_valid ? 1 : 0; - store_stq_insert_accepted += sample.store_stq_insert_accepted ? 1 : 0; - store_stq_insert_conflict += sample.store_stq_insert_conflict ? 1 : 0; - store_stq_full_cycles += sample.store_stq_full ? 1 : 0; - store_stq_stall_cycles += sample.store_stq_stall ? 1 : 0; - store_queue_wait_cycles += - ((sample.store_sta_queue_valid && !sample.store_sta_dequeue_fire) || - (sample.store_std_queue_valid && !sample.store_std_dequeue_fire)) ? 1 : 0; - - service_request_valid_cycles += service_request_valid ? 1 : 0; - service_request_fire += service_request_fire_now ? 1 : 0; - service_response_valid_cycles += service_response_valid ? 1 : 0; - service_response_fire += service_response_fire_now ? 1 : 0; - service_wait_cycles += - ((service_request_valid && !service_request_fire_now) || - (service_response_valid && !service_response_fire_now)) ? 1 : 0; - } - - void finish() { - if (issue_head_last_valid) { - ++issue_head_residency_runs; - if (issue_head_current_run > issue_head_residency_max) { - issue_head_residency_max = issue_head_current_run; - } - issue_head_last_valid = false; - issue_head_current_run = 0; - } - } -}; - -template -void write_json_array(std::ostringstream &out, const std::array &values) { - out << "["; - for (std::size_t i = 0; i < values.size(); ++i) { - if (i != 0) { - out << ","; - } - out << values[i]; - } - out << "]"; -} - -std::string perf_manifest_json(const PerfCounters &perf, std::uint64_t cycles, std::uint64_t commits) { - std::ostringstream out; - out << "{"; - out << "\"summary\":{" - << "\"cycles\":" << cycles - << ",\"commits\":" << commits - << ",\"ipc\":" << std::setprecision(12) - << (cycles == 0 ? 0.0 : static_cast(commits) / static_cast(cycles)) - << "}"; - out << ",\"frontend\":{" - << "\"fetch_req_fire\":" << perf.fetch_req_fire - << ",\"fetch_resp_fire\":" << perf.fetch_resp_fire - << ",\"source_active_cycles\":" << perf.fetch_source_active_cycles - << ",\"source_blocked_cycles\":" << perf.fetch_source_blocked_cycles - << ",\"waiting_response_cycles\":" << perf.fetch_waiting_response_cycles - << ",\"packet_valid_cycles\":" << perf.fetch_packet_valid_cycles - << ",\"source_out_fire\":" << perf.fetch_source_out_fire - << ",\"f4_valid_halfword_slots\":" << perf.fetch_f4_valid_halfword_slots - << ",\"f4_total_len_bytes\":" << perf.fetch_f4_total_len_bytes - << "}"; - out << ",\"decode_rename\":{" - << "\"decode_ready_cycles\":" << perf.decode_ready_cycles - << ",\"decode_blocked_cycles\":" << perf.decode_blocked_cycles - << ",\"decode_block_bits_hist\":"; - write_json_array(out, perf.decode_block_bits_hist); - out << ",\"rename_valid_cycles\":" << perf.rename_valid_cycles - << ",\"rename_accepted\":" << perf.rename_accepted - << ",\"rename_blocked_cycles\":" << perf.rename_blocked_cycles - << ",\"rob_rename_update_attempts\":" << perf.rob_rename_update_attempts - << ",\"rob_rename_update_fire\":" << perf.rob_rename_update_fire - << ",\"rob_rename_update_blocked\":" << perf.rob_rename_update_blocked - << ",\"rob_rename_update_ignored\":" << perf.rob_rename_update_ignored - << "}"; - out << ",\"issue\":{" - << "\"input_valid_cycles\":" << perf.issue_input_valid_cycles - << ",\"enqueue_fire\":" << perf.issue_enqueue_fire - << ",\"candidate_cycles\":" << perf.issue_selected_valid_cycles - << ",\"pick_fire\":" << perf.issue_pick_fire - << ",\"issue_fire\":" << perf.issue_fire - << ",\"head_valid_cycles\":" << perf.issue_head_valid_cycles - << ",\"head_issued_cycles\":" << perf.issue_head_issued_cycles - << ",\"head_unissued_cycles\":" << perf.issue_head_unissued_cycles - << ",\"head_residency_runs\":" << perf.issue_head_residency_runs - << ",\"head_residency_max\":" << perf.issue_head_residency_max - << ",\"blocked_bits_hist\":"; - write_json_array(out, perf.issue_blocked_bits_hist); - out << ",\"blocked_bit_cycles\":"; - write_json_array(out, perf.issue_blocked_bit_cycles); - out << "}"; - out << ",\"execute\":{" - << "\"accepted\":" << perf.execute_accepted - << ",\"busy_cycles\":" << perf.execute_busy_cycles - << ",\"complete_valid\":" << perf.execute_complete_valid - << ",\"unsupported\":" << perf.execute_unsupported - << "}"; - out << ",\"completion\":{" - << "\"accepted\":" << perf.completion_accepted - << ",\"ignored\":" << perf.completion_ignored - << ",\"selected_execute\":" << perf.completion_selected_execute - << ",\"selected_replay\":" << perf.completion_selected_replay - << ",\"replay_blocked_by_execute\":" << perf.completion_replay_blocked_by_execute - << ",\"selected_without_accept\":" << perf.completion_selected_without_accept - << "}"; - out << ",\"commit\":{" - << "\"rows_per_cycle_hist\":"; - write_json_array(out, perf.commit_rows_per_cycle_hist); - out << ",\"rob_dealloc_count_hist\":"; - write_json_array(out, perf.rob_dealloc_count_hist); - out << "}"; - out << ",\"rob_head\":{" - << "\"valid_cycles\":" << perf.commit_head_valid_cycles - << ",\"invalid_cycles\":" << perf.commit_head_invalid_cycles - << ",\"status_hist\":"; - write_json_array(out, perf.commit_head_status_hist); - out << "}"; - out << ",\"load_store_service\":{" - << "\"load_lookup_valid\":" << perf.load_lookup_valid - << ",\"load_execute_granted\":" << perf.load_execute_granted - << ",\"load_replay_granted\":" << perf.load_replay_granted - << ",\"load_wait_cycles\":" << perf.load_wait_cycles - << ",\"store_observe\":" << perf.store_observe - << ",\"store_observe_pair\":" << perf.store_observe_pair - << ",\"store_sta_dequeue\":" << perf.store_sta_dequeue - << ",\"store_std_dequeue\":" << perf.store_std_dequeue - << ",\"store_stq_insert_valid\":" << perf.store_stq_insert_valid - << ",\"store_stq_insert_accepted\":" << perf.store_stq_insert_accepted - << ",\"store_stq_insert_conflict\":" << perf.store_stq_insert_conflict - << ",\"store_stq_full_cycles\":" << perf.store_stq_full_cycles - << ",\"store_stq_stall_cycles\":" << perf.store_stq_stall_cycles - << ",\"store_queue_wait_cycles\":" << perf.store_queue_wait_cycles - << ",\"service_request_valid_cycles\":" << perf.service_request_valid_cycles - << ",\"service_request_fire\":" << perf.service_request_fire - << ",\"service_response_valid_cycles\":" << perf.service_response_valid_cycles - << ",\"service_response_fire\":" << perf.service_response_fire - << ",\"service_wait_cycles\":" << perf.service_wait_cycles - << "}"; - out << "}"; - return out.str(); -} - -void write_hex_field(std::ofstream &out, const char *name, std::uint64_t value) { - out << ",\"" << name << "\":\"0x" << std::hex << value << std::dec << "\""; -} - -bool sample_changed(const EventSample &a, const EventSample &b) { - return a.source_current_pc != b.source_current_pc || - a.source_blocked != b.source_blocked || - a.source_active != b.source_active || - a.source_waiting_response != b.source_waiting_response || - a.source_packet_valid != b.source_packet_valid || - a.source_restart_valid != b.source_restart_valid || - a.source_restart_pc != b.source_restart_pc || - a.source_out_ready != b.source_out_ready || - a.dense_slot_in_ready != b.dense_slot_in_ready || - a.dense_slot_out_ready != b.dense_slot_out_ready || - a.path_decode_ready != b.path_decode_ready || - a.path_renamed_out_ready != b.path_renamed_out_ready || - a.issue_in_ready != b.issue_in_ready || - a.local_incoming_blocked != b.local_incoming_blocked || - a.marker_retire_lifecycle_fire != b.marker_retire_lifecycle_fire || - a.block_marker_stop_redirect_valid != b.block_marker_stop_redirect_valid || - a.block_marker_stop_redirect_pc != b.block_marker_stop_redirect_pc || - a.marker_redirect_fire != b.marker_redirect_fire || - a.marker_redirect_pending != b.marker_redirect_pending || - a.marker_redirect_pc != b.marker_redirect_pc || - a.body_cut_advance_bytes != b.body_cut_advance_bytes || - a.f4_total_len_bytes != b.f4_total_len_bytes || - a.fret_condition_bits != b.fret_condition_bits || - a.continuation_bits != b.continuation_bits || - a.local_pending_counts != b.local_pending_counts || - a.local_ready_masks != b.local_ready_masks || - a.decode_block_bits != b.decode_block_bits || - a.decode_ready_bits != b.decode_ready_bits || - a.tu_rename_source_underflow_mask != b.tu_rename_source_underflow_mask || - a.tu_rename_blocked_by_t_alloc != b.tu_rename_blocked_by_t_alloc || - a.tu_rename_blocked_by_u_alloc != b.tu_rename_blocked_by_u_alloc || - a.tu_rename_t_used_entries != b.tu_rename_t_used_entries || - a.tu_rename_u_used_entries != b.tu_rename_u_used_entries || - a.tu_retire_command_valid != b.tu_retire_command_valid || - a.tu_retire_command_fire != b.tu_retire_command_fire || - a.tu_retire_local_block_commit_pending != b.tu_retire_local_block_commit_pending || - a.tu_retire_local_block_commit_valid != b.tu_retire_local_block_commit_valid || - a.tu_retire_local_block_commit_ready != b.tu_retire_local_block_commit_ready || - a.tu_retire_local_block_commit_fire != b.tu_retire_local_block_commit_fire || - a.tu_retire_accepted != b.tu_retire_accepted || - a.tu_retire_miss != b.tu_retire_miss || - a.tu_retire_release_mismatch != b.tu_retire_release_mismatch || - a.tu_retire_unsupported != b.tu_retire_unsupported || - a.gpr_reservation_count != b.gpr_reservation_count || - a.gpr_reservation_need != b.gpr_reservation_need || - a.gpr_free_count != b.gpr_free_count || - a.gpr_mapq_valid_count != b.gpr_mapq_valid_count || - a.gpr_mapq_free_count != b.gpr_mapq_free_count || - a.gpr_free_list_mismatch_count != b.gpr_free_list_mismatch_count || - a.gpr_commit_accepted != b.gpr_commit_accepted || - a.gpr_commit_block_bid != b.gpr_commit_block_bid || - a.gpr_committed_mapq_count != b.gpr_committed_mapq_count || - a.gpr_released_phys_count != b.gpr_released_phys_count || - a.rob_rename_update_attempt_valid != b.rob_rename_update_attempt_valid || - a.rob_rename_update_ready != b.rob_rename_update_ready || - a.rob_rename_update_fire != b.rob_rename_update_fire || - a.rob_rename_update_ignored != b.rob_rename_update_ignored || - a.commit_head_valid != b.commit_head_valid || - a.commit_head_status != b.commit_head_status || - a.commit_head_rob_value != b.commit_head_rob_value || - a.rob_occupied_mask != b.rob_occupied_mask || - a.rob_completed_mask != b.rob_completed_mask || - a.rob_dealloc_valid_mask != b.rob_dealloc_valid_mask || - a.rob_dealloc_count != b.rob_dealloc_count || - a.rob_dealloc_block_last_valid != b.rob_dealloc_block_last_valid || - a.rob_dealloc_block_last_block_bid != b.rob_dealloc_block_last_block_bid || - a.block_scalar_done_fire != b.block_scalar_done_fire || - a.block_scalar_done_bid != b.block_scalar_done_bid || - a.block_retire_fire != b.block_retire_fire || - a.block_retire_bid != b.block_retire_bid || - a.scalar_lr_reservation_valid_stid0 != b.scalar_lr_reservation_valid_stid0 || - a.scalar_lr_reservation_line_stid0 != b.scalar_lr_reservation_line_stid0 || - a.scalar_lr_reservation_count != b.scalar_lr_reservation_count || - a.scalar_lr_reservation_protocol_error != b.scalar_lr_reservation_protocol_error || - a.scalar_lr_reservation_blocked_by_flush != b.scalar_lr_reservation_blocked_by_flush || - a.scalar_lr_reservation_committed_store_invalidate != - b.scalar_lr_reservation_committed_store_invalidate || - a.store_sta_queue_valid != b.store_sta_queue_valid || - a.store_std_queue_valid != b.store_std_queue_valid || - a.store_sta_dequeue_fire != b.store_sta_dequeue_fire || - a.store_std_dequeue_fire != b.store_std_dequeue_fire || - a.store_sta_queue_count != b.store_sta_queue_count || - a.store_std_queue_count != b.store_std_queue_count || - a.store_sta_insert_ready != b.store_sta_insert_ready || - a.store_std_insert_ready != b.store_std_insert_ready || - a.store_selected_sta != b.store_selected_sta || - a.store_selected_std != b.store_selected_std || - a.store_blocked_by_sta_exec != b.store_blocked_by_sta_exec || - a.store_blocked_by_std_exec != b.store_blocked_by_std_exec || - a.store_stq_insert_valid != b.store_stq_insert_valid || - a.store_stq_insert_accepted != b.store_stq_insert_accepted || - a.store_stq_insert_conflict != b.store_stq_insert_conflict || - a.store_stq_insert_index != b.store_stq_insert_index || - a.store_stq_occupied_mask != b.store_stq_occupied_mask || - a.store_stq_wait_mask != b.store_stq_wait_mask || - a.store_stq_commit_mask != b.store_stq_commit_mask || - a.store_stq_addr_ready_mask != b.store_stq_addr_ready_mask || - a.store_stq_data_ready_mask != b.store_stq_data_ready_mask || - a.store_stq_resident_count != b.store_stq_resident_count || - a.store_stq_outstanding_wait_count != b.store_stq_outstanding_wait_count || - a.store_stq_empty != b.store_stq_empty || - a.store_stq_full != b.store_stq_full || - a.store_stq_stall != b.store_stq_stall || - a.dec_ren_head_rid_valid != b.dec_ren_head_rid_valid || - a.dec_ren_head_pc != b.dec_ren_head_pc || - a.dec_ren_head_rid_value != b.dec_ren_head_rid_value || - a.renamed_out_valid != b.renamed_out_valid || - a.renamed_accepted != b.renamed_accepted || - a.issue_enqueue_fire != b.issue_enqueue_fire || - a.issue_input_valid != b.issue_input_valid || - a.issue_input_pc != b.issue_input_pc || - a.issue_input_opcode != b.issue_input_opcode || - a.issue_input_bid_valid != b.issue_input_bid_valid || - a.issue_input_bid_wrap != b.issue_input_bid_wrap || - a.issue_input_bid_value != b.issue_input_bid_value || - a.issue_input_rid_valid != b.issue_input_rid_valid || - a.issue_input_rid_wrap != b.issue_input_rid_wrap || - a.issue_input_rid_value != b.issue_input_rid_value || - a.issue_input_stid != b.issue_input_stid || - a.issue_pick_fire != b.issue_pick_fire || - a.issue_fire != b.issue_fire || - a.issue_output_valid != b.issue_output_valid || - a.issue_output_pc != b.issue_output_pc || - a.issue_output_opcode != b.issue_output_opcode || - a.issue_output_bid_valid != b.issue_output_bid_valid || - a.issue_output_bid_wrap != b.issue_output_bid_wrap || - a.issue_output_bid_value != b.issue_output_bid_value || - a.issue_output_rid_valid != b.issue_output_rid_valid || - a.issue_output_rid_wrap != b.issue_output_rid_wrap || - a.issue_output_rid_value != b.issue_output_rid_value || - a.issue_output_stid != b.issue_output_stid || - a.issue_head_valid != b.issue_head_valid || - a.issue_head_issued != b.issue_head_issued || - a.issue_head_bid_valid != b.issue_head_bid_valid || - a.issue_head_bid_wrap != b.issue_head_bid_wrap || - a.issue_head_rid_valid != b.issue_head_rid_valid || - a.issue_head_rid_wrap != b.issue_head_rid_wrap || - a.issue_head_pc != b.issue_head_pc || - a.issue_head_stid != b.issue_head_stid || - a.issue_head_bid_value != b.issue_head_bid_value || - a.issue_head_rid_value != b.issue_head_rid_value || - a.issue_head_src_valid_mask != b.issue_head_src_valid_mask || - a.issue_head_src_phys_tag[0] != b.issue_head_src_phys_tag[0] || - a.issue_head_src_phys_tag[1] != b.issue_head_src_phys_tag[1] || - a.issue_head_src_phys_tag[2] != b.issue_head_src_phys_tag[2] || - a.issue_source_ready_mask != b.issue_source_ready_mask || - a.issue_all_sources_ready != b.issue_all_sources_ready || - a.issue_selected_valid != b.issue_selected_valid || - a.issue_selected_index != b.issue_selected_index || - a.issue_selected_read_ready != b.issue_selected_read_ready || - a.issue_stage_bits != b.issue_stage_bits || - a.issue_blocked_bits != b.issue_blocked_bits || - a.issue_scalar_sp_order_blocked != b.issue_scalar_sp_order_blocked || - a.issue_bank_scalar_sp_order_blocked_mask != b.issue_bank_scalar_sp_order_blocked_mask || - a.scalar_sp_stid0_issue_head_valid != b.scalar_sp_stid0_issue_head_valid || - a.scalar_sp_stid0_issue_head_bid_valid != b.scalar_sp_stid0_issue_head_bid_valid || - a.scalar_sp_stid0_issue_head_bid_wrap != b.scalar_sp_stid0_issue_head_bid_wrap || - a.scalar_sp_stid0_issue_head_bid_value != b.scalar_sp_stid0_issue_head_bid_value || - a.scalar_sp_stid0_issue_head_rid_valid != b.scalar_sp_stid0_issue_head_rid_valid || - a.scalar_sp_stid0_issue_head_rid_wrap != b.scalar_sp_stid0_issue_head_rid_wrap || - a.scalar_sp_stid0_issue_head_rid_value != b.scalar_sp_stid0_issue_head_rid_value || - a.rf_ready_mask != b.rf_ready_mask || - a.p_wakeup_valid != b.p_wakeup_valid || - a.p_wakeup_tag != b.p_wakeup_tag || - a.p_wakeup_head_match != b.p_wakeup_head_match || - a.execute_accepted != b.execute_accepted || - a.execute_accepted_identity_valid != b.execute_accepted_identity_valid || - a.execute_accepted_pc != b.execute_accepted_pc || - a.execute_accepted_opcode != b.execute_accepted_opcode || - a.execute_accepted_bid_valid != b.execute_accepted_bid_valid || - a.execute_accepted_bid_wrap != b.execute_accepted_bid_wrap || - a.execute_accepted_bid_value != b.execute_accepted_bid_value || - a.execute_accepted_rid_valid != b.execute_accepted_rid_valid || - a.execute_accepted_rid_wrap != b.execute_accepted_rid_wrap || - a.execute_accepted_rid_value != b.execute_accepted_rid_value || - a.execute_accepted_stid != b.execute_accepted_stid || - a.execute_busy != b.execute_busy || - a.execute_unsupported != b.execute_unsupported || - a.execute_unsupported_opcode != b.execute_unsupported_opcode || - a.execute_complete_valid != b.execute_complete_valid || - a.execute_complete_rob_value != b.execute_complete_rob_value || - a.execute_complete_pc != b.execute_complete_pc || - a.execute_complete_src_phys_valid_mask != b.execute_complete_src_phys_valid_mask || - a.execute_complete_src_phys_tag[0] != b.execute_complete_src_phys_tag[0] || - a.execute_complete_src_phys_tag[1] != b.execute_complete_src_phys_tag[1] || - a.execute_complete_src_phys_tag[2] != b.execute_complete_src_phys_tag[2] || - a.rob_complete_arbiter_bits != b.rob_complete_arbiter_bits || - a.rob_complete_result_bits != b.rob_complete_result_bits; -} - -void write_event( - std::ofstream &out, - std::uint64_t cycle, - const char *kind, - const EventSample &sample, - bool pending_fetch_valid, - std::uint64_t pending_fetch_pc) { - out << "{\"schema\":\"linxcore.benchmark_autonomous_natural_event.v1\"" - << ",\"cycle\":" << cycle - << ",\"kind\":\"" << kind << "\"" - << ",\"fetch_req_fire\":" << (sample.fetch_req_fire ? "true" : "false") - << ",\"fetch_resp_fire\":" << (sample.fetch_resp_fire ? "true" : "false") - << ",\"commit_valid\":" << (sample.commit_valid ? "true" : "false") - << ",\"source_out_fire\":" << (sample.source_out_fire ? "true" : "false") - << ",\"source_restart_valid\":" << (sample.source_restart_valid ? "true" : "false") - << ",\"source_blocked\":" << (sample.source_blocked ? "true" : "false") - << ",\"source_active\":" << (sample.source_active ? "true" : "false") - << ",\"source_waiting_response\":" - << (sample.source_waiting_response ? "true" : "false") - << ",\"source_packet_valid\":" << (sample.source_packet_valid ? "true" : "false") - << ",\"block_marker_stop_redirect_valid\":" - << (sample.block_marker_stop_redirect_valid ? "true" : "false") - << ",\"marker_redirect_fire\":" << (sample.marker_redirect_fire ? "true" : "false") - << ",\"marker_redirect_pending\":" - << (sample.marker_redirect_pending ? "true" : "false") - << ",\"source_out_ready\":" << (sample.source_out_ready ? "true" : "false") - << ",\"dense_slot_in_ready\":" - << (sample.dense_slot_in_ready ? "true" : "false") - << ",\"dense_slot_out_ready\":" - << (sample.dense_slot_out_ready ? "true" : "false") - << ",\"path_decode_ready\":" << (sample.path_decode_ready ? "true" : "false") - << ",\"path_renamed_out_ready\":" - << (sample.path_renamed_out_ready ? "true" : "false") - << ",\"issue_in_ready\":" << (sample.issue_in_ready ? "true" : "false") - << ",\"local_incoming_blocked\":" - << (sample.local_incoming_blocked ? "true" : "false") - << ",\"marker_retire_lifecycle_fire\":" - << (sample.marker_retire_lifecycle_fire ? "true" : "false") - << ",\"gpr_commit_accepted\":" - << (sample.gpr_commit_accepted ? "true" : "false") - << ",\"rob_rename_update_attempt_valid\":" - << (sample.rob_rename_update_attempt_valid ? "true" : "false") - << ",\"rob_rename_update_ready\":" - << (sample.rob_rename_update_ready ? "true" : "false") - << ",\"rob_rename_update_fire\":" - << (sample.rob_rename_update_fire ? "true" : "false") - << ",\"rob_rename_update_ignored\":" - << (sample.rob_rename_update_ignored ? "true" : "false") - << ",\"commit_head_valid\":" << (sample.commit_head_valid ? "true" : "false") - << ",\"dec_ren_head_rid_valid\":" - << (sample.dec_ren_head_rid_valid ? "true" : "false") - << ",\"renamed_out_valid\":" << (sample.renamed_out_valid ? "true" : "false") - << ",\"renamed_accepted\":" << (sample.renamed_accepted ? "true" : "false") - << ",\"tu_rename_blocked_by_t_alloc\":" - << (sample.tu_rename_blocked_by_t_alloc ? "true" : "false") - << ",\"tu_rename_blocked_by_u_alloc\":" - << (sample.tu_rename_blocked_by_u_alloc ? "true" : "false") - << ",\"tu_retire_command_valid\":" - << (sample.tu_retire_command_valid ? "true" : "false") - << ",\"tu_retire_command_fire\":" - << (sample.tu_retire_command_fire ? "true" : "false") - << ",\"tu_retire_local_block_commit_pending\":" - << (sample.tu_retire_local_block_commit_pending ? "true" : "false") - << ",\"tu_retire_local_block_commit_valid\":" - << (sample.tu_retire_local_block_commit_valid ? "true" : "false") - << ",\"tu_retire_local_block_commit_ready\":" - << (sample.tu_retire_local_block_commit_ready ? "true" : "false") - << ",\"tu_retire_local_block_commit_fire\":" - << (sample.tu_retire_local_block_commit_fire ? "true" : "false") - << ",\"tu_retire_accepted\":" - << (sample.tu_retire_accepted ? "true" : "false") - << ",\"tu_retire_miss\":" << (sample.tu_retire_miss ? "true" : "false") - << ",\"tu_retire_release_mismatch\":" - << (sample.tu_retire_release_mismatch ? "true" : "false") - << ",\"tu_retire_unsupported\":" - << (sample.tu_retire_unsupported ? "true" : "false") - << ",\"issue_enqueue_fire\":" << (sample.issue_enqueue_fire ? "true" : "false") - << ",\"issue_input_valid\":" << (sample.issue_input_valid ? "true" : "false") - << ",\"issue_input_bid_valid\":" << (sample.issue_input_bid_valid ? "true" : "false") - << ",\"issue_input_bid_wrap\":" << (sample.issue_input_bid_wrap ? "true" : "false") - << ",\"issue_input_rid_valid\":" << (sample.issue_input_rid_valid ? "true" : "false") - << ",\"issue_input_rid_wrap\":" << (sample.issue_input_rid_wrap ? "true" : "false") - << ",\"issue_pick_fire\":" << (sample.issue_pick_fire ? "true" : "false") - << ",\"issue_fire\":" << (sample.issue_fire ? "true" : "false") - << ",\"issue_output_valid\":" << (sample.issue_output_valid ? "true" : "false") - << ",\"issue_output_bid_valid\":" << (sample.issue_output_bid_valid ? "true" : "false") - << ",\"issue_output_bid_wrap\":" << (sample.issue_output_bid_wrap ? "true" : "false") - << ",\"issue_output_rid_valid\":" << (sample.issue_output_rid_valid ? "true" : "false") - << ",\"issue_output_rid_wrap\":" << (sample.issue_output_rid_wrap ? "true" : "false") - << ",\"issue_head_valid\":" << (sample.issue_head_valid ? "true" : "false") - << ",\"issue_head_issued\":" << (sample.issue_head_issued ? "true" : "false") - << ",\"issue_head_bid_valid\":" - << (sample.issue_head_bid_valid ? "true" : "false") - << ",\"issue_head_bid_wrap\":" - << (sample.issue_head_bid_wrap ? "true" : "false") - << ",\"issue_head_rid_valid\":" - << (sample.issue_head_rid_valid ? "true" : "false") - << ",\"issue_head_rid_wrap\":" - << (sample.issue_head_rid_wrap ? "true" : "false") - << ",\"issue_all_sources_ready\":" - << (sample.issue_all_sources_ready ? "true" : "false") - << ",\"issue_selected_valid\":" - << (sample.issue_selected_valid ? "true" : "false") - << ",\"issue_selected_read_ready\":" - << (sample.issue_selected_read_ready ? "true" : "false") - << ",\"issue_scalar_sp_order_blocked\":" - << (sample.issue_scalar_sp_order_blocked ? "true" : "false") - << ",\"scalar_sp_stid0_issue_head_valid\":" - << (sample.scalar_sp_stid0_issue_head_valid ? "true" : "false") - << ",\"scalar_sp_stid0_issue_head_bid_valid\":" - << (sample.scalar_sp_stid0_issue_head_bid_valid ? "true" : "false") - << ",\"scalar_sp_stid0_issue_head_bid_wrap\":" - << (sample.scalar_sp_stid0_issue_head_bid_wrap ? "true" : "false") - << ",\"scalar_sp_stid0_issue_head_rid_valid\":" - << (sample.scalar_sp_stid0_issue_head_rid_valid ? "true" : "false") - << ",\"scalar_sp_stid0_issue_head_rid_wrap\":" - << (sample.scalar_sp_stid0_issue_head_rid_wrap ? "true" : "false") - << ",\"p_wakeup_valid\":" << (sample.p_wakeup_valid ? "true" : "false") - << ",\"p_wakeup_head_match\":" - << (sample.p_wakeup_head_match ? "true" : "false") - << ",\"execute_accepted\":" << (sample.execute_accepted ? "true" : "false") - << ",\"execute_accepted_identity_valid\":" - << (sample.execute_accepted_identity_valid ? "true" : "false") - << ",\"execute_accepted_bid_valid\":" - << (sample.execute_accepted_bid_valid ? "true" : "false") - << ",\"execute_accepted_bid_wrap\":" - << (sample.execute_accepted_bid_wrap ? "true" : "false") - << ",\"execute_accepted_rid_valid\":" - << (sample.execute_accepted_rid_valid ? "true" : "false") - << ",\"execute_accepted_rid_wrap\":" - << (sample.execute_accepted_rid_wrap ? "true" : "false") - << ",\"execute_busy\":" << (sample.execute_busy ? "true" : "false") - << ",\"execute_unsupported\":" - << (sample.execute_unsupported ? "true" : "false") - << ",\"execute_complete_valid\":" - << (sample.execute_complete_valid ? "true" : "false") - << ",\"rob_dealloc_block_last_valid\":" - << (sample.rob_dealloc_block_last_valid ? "true" : "false") - << ",\"block_scalar_done_fire\":" - << (sample.block_scalar_done_fire ? "true" : "false") - << ",\"block_retire_fire\":" - << (sample.block_retire_fire ? "true" : "false") - << ",\"scalar_lr_reservation_valid_stid0\":" - << (sample.scalar_lr_reservation_valid_stid0 ? "true" : "false") - << ",\"scalar_lr_reservation_protocol_error\":" - << (sample.scalar_lr_reservation_protocol_error ? "true" : "false") - << ",\"scalar_lr_reservation_blocked_by_flush\":" - << (sample.scalar_lr_reservation_blocked_by_flush ? "true" : "false") - << ",\"scalar_lr_reservation_committed_store_invalidate\":" - << (sample.scalar_lr_reservation_committed_store_invalidate ? "true" : "false") - << ",\"store_sta_queue_valid\":" - << (sample.store_sta_queue_valid ? "true" : "false") - << ",\"store_std_queue_valid\":" - << (sample.store_std_queue_valid ? "true" : "false") - << ",\"store_sta_dequeue_fire\":" - << (sample.store_sta_dequeue_fire ? "true" : "false") - << ",\"store_std_dequeue_fire\":" - << (sample.store_std_dequeue_fire ? "true" : "false") - << ",\"store_sta_insert_ready\":" - << (sample.store_sta_insert_ready ? "true" : "false") - << ",\"store_std_insert_ready\":" - << (sample.store_std_insert_ready ? "true" : "false") - << ",\"store_selected_sta\":" - << (sample.store_selected_sta ? "true" : "false") - << ",\"store_selected_std\":" - << (sample.store_selected_std ? "true" : "false") - << ",\"store_blocked_by_sta_exec\":" - << (sample.store_blocked_by_sta_exec ? "true" : "false") - << ",\"store_blocked_by_std_exec\":" - << (sample.store_blocked_by_std_exec ? "true" : "false") - << ",\"store_stq_insert_valid\":" - << (sample.store_stq_insert_valid ? "true" : "false") - << ",\"store_stq_insert_accepted\":" - << (sample.store_stq_insert_accepted ? "true" : "false") - << ",\"store_stq_insert_conflict\":" - << (sample.store_stq_insert_conflict ? "true" : "false") - << ",\"store_stq_empty\":" - << (sample.store_stq_empty ? "true" : "false") - << ",\"store_stq_full\":" - << (sample.store_stq_full ? "true" : "false") - << ",\"store_stq_stall\":" - << (sample.store_stq_stall ? "true" : "false") - << ",\"pending_fetch_valid\":" << (pending_fetch_valid ? "true" : "false"); - write_hex_field(out, "source_current_pc", sample.source_current_pc); - write_hex_field(out, "source_restart_pc", sample.source_restart_pc); - write_hex_field(out, "block_marker_stop_redirect_pc", sample.block_marker_stop_redirect_pc); - write_hex_field(out, "marker_redirect_pc", sample.marker_redirect_pc); - write_hex_field(out, "body_cut_advance_bytes", sample.body_cut_advance_bytes); - write_hex_field(out, "f4_total_len_bytes", sample.f4_total_len_bytes); - write_hex_field(out, "fret_condition_bits", sample.fret_condition_bits); - write_hex_field(out, "continuation_bits", sample.continuation_bits); - write_hex_field(out, "local_pending_counts", sample.local_pending_counts); - write_hex_field(out, "local_ready_masks", sample.local_ready_masks); - write_hex_field(out, "decode_block_bits", sample.decode_block_bits); - write_hex_field(out, "decode_ready_bits", sample.decode_ready_bits); - write_hex_field( - out, "tu_rename_source_underflow_mask", sample.tu_rename_source_underflow_mask); - write_hex_field(out, "tu_rename_t_used_entries", sample.tu_rename_t_used_entries); - write_hex_field(out, "tu_rename_u_used_entries", sample.tu_rename_u_used_entries); - write_hex_field(out, "gpr_reservation_count", sample.gpr_reservation_count); - write_hex_field(out, "gpr_reservation_need", sample.gpr_reservation_need); - write_hex_field(out, "gpr_free_count", sample.gpr_free_count); - write_hex_field(out, "gpr_mapq_valid_count", sample.gpr_mapq_valid_count); - write_hex_field(out, "gpr_mapq_free_count", sample.gpr_mapq_free_count); - write_hex_field(out, "gpr_free_list_mismatch_count", sample.gpr_free_list_mismatch_count); - write_hex_field(out, "gpr_commit_block_bid", sample.gpr_commit_block_bid); - write_hex_field(out, "gpr_committed_mapq_count", sample.gpr_committed_mapq_count); - write_hex_field(out, "gpr_released_phys_count", sample.gpr_released_phys_count); - write_hex_field(out, "commit_head_status", sample.commit_head_status); - write_hex_field(out, "commit_head_rob_value", sample.commit_head_rob_value); - write_hex_field(out, "rob_occupied_mask", sample.rob_occupied_mask); - write_hex_field(out, "rob_completed_mask", sample.rob_completed_mask); - write_hex_field(out, "rob_dealloc_valid_mask", sample.rob_dealloc_valid_mask); - write_hex_field(out, "rob_dealloc_count", sample.rob_dealloc_count); - write_hex_field( - out, "rob_dealloc_block_last_block_bid", sample.rob_dealloc_block_last_block_bid); - write_hex_field(out, "block_scalar_done_bid", sample.block_scalar_done_bid); - write_hex_field(out, "block_retire_bid", sample.block_retire_bid); - write_hex_field(out, "dec_ren_head_pc", sample.dec_ren_head_pc); - write_hex_field(out, "dec_ren_head_rid_value", sample.dec_ren_head_rid_value); - write_hex_field(out, "issue_head_pc", sample.issue_head_pc); - write_hex_field(out, "issue_head_stid", sample.issue_head_stid); - write_hex_field(out, "issue_head_bid_value", sample.issue_head_bid_value); - write_hex_field(out, "issue_head_rid_value", sample.issue_head_rid_value); - write_hex_field(out, "issue_input_pc", sample.issue_input_pc); - write_hex_field(out, "issue_input_opcode", sample.issue_input_opcode); - write_hex_field(out, "issue_input_bid_value", sample.issue_input_bid_value); - write_hex_field(out, "issue_input_rid_value", sample.issue_input_rid_value); - write_hex_field(out, "issue_input_stid", sample.issue_input_stid); - write_hex_field(out, "issue_output_pc", sample.issue_output_pc); - write_hex_field(out, "issue_output_opcode", sample.issue_output_opcode); - write_hex_field(out, "issue_output_bid_value", sample.issue_output_bid_value); - write_hex_field(out, "issue_output_rid_value", sample.issue_output_rid_value); - write_hex_field(out, "issue_output_stid", sample.issue_output_stid); - write_hex_field(out, "issue_head_src_valid_mask", sample.issue_head_src_valid_mask); - write_hex_field(out, "issue_head_src0_phys_tag", sample.issue_head_src_phys_tag[0]); - write_hex_field(out, "issue_head_src1_phys_tag", sample.issue_head_src_phys_tag[1]); - write_hex_field(out, "issue_head_src2_phys_tag", sample.issue_head_src_phys_tag[2]); - write_hex_field(out, "issue_source_ready_mask", sample.issue_source_ready_mask); - write_hex_field(out, "issue_selected_index", sample.issue_selected_index); - write_hex_field(out, "issue_stage_bits", sample.issue_stage_bits); - write_hex_field(out, "issue_blocked_bits", sample.issue_blocked_bits); - write_hex_field( - out, "issue_bank_scalar_sp_order_blocked_mask", - sample.issue_bank_scalar_sp_order_blocked_mask); - write_hex_field( - out, "scalar_sp_stid0_issue_head_bid_value", - sample.scalar_sp_stid0_issue_head_bid_value); - write_hex_field( - out, "scalar_sp_stid0_issue_head_rid_value", - sample.scalar_sp_stid0_issue_head_rid_value); - write_hex_field(out, "rf_ready_mask", sample.rf_ready_mask); - write_hex_field(out, "p_wakeup_tag", sample.p_wakeup_tag); - write_hex_field(out, "execute_unsupported_opcode", sample.execute_unsupported_opcode); - write_hex_field(out, "execute_accepted_pc", sample.execute_accepted_pc); - write_hex_field(out, "execute_accepted_opcode", sample.execute_accepted_opcode); - write_hex_field(out, "execute_accepted_bid_value", sample.execute_accepted_bid_value); - write_hex_field(out, "execute_accepted_rid_value", sample.execute_accepted_rid_value); - write_hex_field(out, "execute_accepted_stid", sample.execute_accepted_stid); - write_hex_field(out, "execute_complete_rob_value", sample.execute_complete_rob_value); - write_hex_field(out, "execute_complete_pc", sample.execute_complete_pc); - write_hex_field( - out, "execute_complete_src_phys_valid_mask", sample.execute_complete_src_phys_valid_mask); - write_hex_field(out, "execute_complete_src0_phys_tag", sample.execute_complete_src_phys_tag[0]); - write_hex_field(out, "execute_complete_src1_phys_tag", sample.execute_complete_src_phys_tag[1]); - write_hex_field(out, "execute_complete_src2_phys_tag", sample.execute_complete_src_phys_tag[2]); - write_hex_field(out, "rob_complete_arbiter_bits", sample.rob_complete_arbiter_bits); - write_hex_field(out, "rob_complete_result_bits", sample.rob_complete_result_bits); - write_hex_field(out, "scalar_lr_reservation_line_stid0", - sample.scalar_lr_reservation_line_stid0); - write_hex_field(out, "scalar_lr_reservation_count", sample.scalar_lr_reservation_count); - write_hex_field(out, "store_sta_queue_count", sample.store_sta_queue_count); - write_hex_field(out, "store_std_queue_count", sample.store_std_queue_count); - write_hex_field(out, "store_stq_insert_index", sample.store_stq_insert_index); - write_hex_field(out, "store_stq_occupied_mask", sample.store_stq_occupied_mask); - write_hex_field(out, "store_stq_wait_mask", sample.store_stq_wait_mask); - write_hex_field(out, "store_stq_commit_mask", sample.store_stq_commit_mask); - write_hex_field(out, "store_stq_addr_ready_mask", sample.store_stq_addr_ready_mask); - write_hex_field(out, "store_stq_data_ready_mask", sample.store_stq_data_ready_mask); - write_hex_field(out, "store_stq_resident_count", sample.store_stq_resident_count); - write_hex_field(out, "store_stq_outstanding_wait_count", - sample.store_stq_outstanding_wait_count); - if (sample.fetch_req_fire) { - write_hex_field(out, "fetch_req_pc", sample.fetch_req_pc); - } - if (sample.fetch_resp_fire) { - write_hex_field(out, "fetch_resp_pc", sample.fetch_resp_pc); - } - if (sample.commit_valid) { - write_hex_field(out, "commit_pc", sample.commit_pc); - } - if (pending_fetch_valid) { - write_hex_field(out, "pending_fetch_pc", pending_fetch_pc); - } - out << "}\n"; -} - -void clear_inputs(VLinxCoreBenchmarkAutonomousTop &dut) { - dut.io_startValid = 0; - dut.io_resetPc = 0; - dut.io_resetSp = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_restartSp = 0; - dut.io_flushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 0; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_loadLookupData = 0; - dut.io_loadPairFirstLookupData = 0; - dut.io_reducedServiceRequest_ready = 0; - dut.io_reducedServiceResponse_valid = 0; - dut.io_reducedServiceResponse_bits_requestType = 0; - dut.io_reducedServiceResponse_bits_identity_stid = 0; - dut.io_reducedServiceResponse_bits_identity_bid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_bid_value = 0; - dut.io_reducedServiceResponse_bits_identity_bid_wrap = 0; - dut.io_reducedServiceResponse_bits_identity_gid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_gid_value = 0; - dut.io_reducedServiceResponse_bits_identity_gid_wrap = 0; - dut.io_reducedServiceResponse_bits_identity_rid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_rid_value = 0; - dut.io_reducedServiceResponse_bits_identity_rid_wrap = 0; - dut.io_reducedServiceResponse_bits_a0 = 0; -} - -ReducedServiceRequest read_service_request(const VLinxCoreBenchmarkAutonomousTop &dut) { - ReducedServiceRequest request; - request.request_type = dut.io_reducedServiceRequest_bits_requestType; - request.identity.stid = dut.io_reducedServiceRequest_bits_identity_stid; - request.identity.bid.valid = dut.io_reducedServiceRequest_bits_identity_bid_valid; - request.identity.bid.value = dut.io_reducedServiceRequest_bits_identity_bid_value; - request.identity.bid.wrap = dut.io_reducedServiceRequest_bits_identity_bid_wrap; - request.identity.gid.valid = dut.io_reducedServiceRequest_bits_identity_gid_valid; - request.identity.gid.value = dut.io_reducedServiceRequest_bits_identity_gid_value; - request.identity.gid.wrap = dut.io_reducedServiceRequest_bits_identity_gid_wrap; - request.identity.rid.valid = dut.io_reducedServiceRequest_bits_identity_rid_valid; - request.identity.rid.value = dut.io_reducedServiceRequest_bits_identity_rid_value; - request.identity.rid.wrap = dut.io_reducedServiceRequest_bits_identity_rid_wrap; - request.a0 = dut.io_reducedServiceRequest_bits_a0; - request.a1 = dut.io_reducedServiceRequest_bits_a1; - request.a2 = dut.io_reducedServiceRequest_bits_a2; - request.a3 = dut.io_reducedServiceRequest_bits_a3; - request.a4 = dut.io_reducedServiceRequest_bits_a4; - request.a5 = dut.io_reducedServiceRequest_bits_a5; - request.a7 = dut.io_reducedServiceRequest_bits_a7; - return request; -} - -void drive_service_responder( - VLinxCoreBenchmarkAutonomousTop &dut, - const ReducedServiceResponder &responder) { - dut.io_reducedServiceRequest_ready = responder.request_ready() ? 1 : 0; - dut.io_reducedServiceResponse_valid = responder.response_valid() ? 1 : 0; - if (!responder.response_valid()) { - return; - } - const auto &response = responder.response(); - dut.io_reducedServiceResponse_bits_requestType = response.request_type; - dut.io_reducedServiceResponse_bits_identity_stid = response.identity.stid; - dut.io_reducedServiceResponse_bits_identity_bid_valid = response.identity.bid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_bid_value = response.identity.bid.value; - dut.io_reducedServiceResponse_bits_identity_bid_wrap = response.identity.bid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_gid_valid = response.identity.gid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_gid_value = response.identity.gid.value; - dut.io_reducedServiceResponse_bits_identity_gid_wrap = response.identity.gid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_rid_valid = response.identity.rid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_rid_value = response.identity.rid.value; - dut.io_reducedServiceResponse_bits_identity_rid_wrap = response.identity.rid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_a0 = response.a0; -} - -void eval_with_memory(VLinxCoreBenchmarkAutonomousTop &dut, const SparseMemory &mem) { - dut.eval(); - if (dut.io_loadLookupValid) { - dut.io_loadLookupData = mem.read_u64_or_zero(dut.io_loadLookupAddr); - } - if (dut.io_loadPairFirstLookupValid) { - dut.io_loadPairFirstLookupData = - mem.read_u64_or_zero(dut.io_loadPairFirstLookupAddr); - } - dut.eval(); -} - -void tick(VLinxCoreBenchmarkAutonomousTop &dut, const SparseMemory &mem) { - dut.clock = 0; - eval_with_memory(dut, mem); - dut.clock = 1; - eval_with_memory(dut, mem); - dut.clock = 0; - eval_with_memory(dut, mem); -} - -linxcore::chisel::CommitTraceJsonRow read_commit_row( - const VLinxCoreBenchmarkAutonomousTop &dut, - int slot) { -#define COMMIT_FIELD(name) (slot == 0 ? dut.io_commit_rows_0_##name : dut.io_commit_rows_1_##name) - linxcore::chisel::CommitTraceJsonRow row; - row.valid = COMMIT_FIELD(valid); - row.seq = COMMIT_FIELD(seq); - row.cycle = COMMIT_FIELD(cycle); - row.slot = COMMIT_FIELD(slot); - row.bid = COMMIT_FIELD(identity_bid); - row.gid = COMMIT_FIELD(identity_gid); - row.rid = COMMIT_FIELD(identity_rid); - row.rob_valid = COMMIT_FIELD(rob_valid); - row.rob_wrap = COMMIT_FIELD(rob_wrap); - row.rob_value = COMMIT_FIELD(rob_value); - row.block_bid_valid = COMMIT_FIELD(blockBidValid); - row.block_bid = COMMIT_FIELD(blockBid); - row.pc = COMMIT_FIELD(pc); - row.insn = COMMIT_FIELD(insn); - row.len = COMMIT_FIELD(len); - row.wb_valid = COMMIT_FIELD(wb_valid); - row.wb_rd = COMMIT_FIELD(wb_reg); - row.wb_data = COMMIT_FIELD(wb_data); - row.src0_valid = COMMIT_FIELD(src0_valid); - row.src0_reg = COMMIT_FIELD(src0_reg); - row.src0_data = COMMIT_FIELD(src0_data); - row.src1_valid = COMMIT_FIELD(src1_valid); - row.src1_reg = COMMIT_FIELD(src1_reg); - row.src1_data = COMMIT_FIELD(src1_data); - row.dst_valid = COMMIT_FIELD(dst_valid); - row.dst_reg = COMMIT_FIELD(dst_reg); - row.dst_data = COMMIT_FIELD(dst_data); - row.mem_valid = COMMIT_FIELD(mem_valid); - row.mem_is_store = COMMIT_FIELD(mem_isStore); - row.mem_addr = COMMIT_FIELD(mem_addr); - row.mem_wdata = COMMIT_FIELD(mem_wdata); - row.mem_rdata = COMMIT_FIELD(mem_rdata); - row.mem_size = COMMIT_FIELD(mem_size); - row.trap_valid = COMMIT_FIELD(trap_valid); - row.trap_cause = COMMIT_FIELD(trap_cause); - row.trap_arg0 = COMMIT_FIELD(trap_arg0); - row.next_pc = COMMIT_FIELD(nextPc); -#undef COMMIT_FIELD - return row; -} - -int main(int argc, char **argv) { - try { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - SparseMemory memory; - memory.load_sparse_hex(args.memory_hex); - - std::ofstream trace(args.commit_trace); - std::ofstream uart_out(args.uart_output); - if (!trace) { - throw std::runtime_error("failed to open commit trace: " + args.commit_trace); - } - std::ofstream events(args.event_trace); - if (!events) { - throw std::runtime_error("failed to open event trace: " + args.event_trace); - } - if (!uart_out) { - throw std::runtime_error("failed to open UART output: " + args.uart_output); - } - - VLinxCoreBenchmarkAutonomousTop dut; - std::string uart; - std::uint64_t commits = 0; - std::uint64_t cycles = 0; - std::uint16_t finisher_code = 0; - bool finisher_pass = false; - std::string status = "timeout"; - bool have_pending_fetch = false; - std::uint64_t pending_fetch_pc = 0; - std::uint64_t fetch_requests = 0; - std::uint64_t fetch_responses = 0; - ReducedServiceResponder service_responder; - EventSample previous_sample; - bool have_previous_sample = false; - PerfCounters perf; - - clear_inputs(dut); - dut.reset = 1; - tick(dut, memory); - tick(dut, memory); - dut.reset = 0; - - for (; cycles < args.max_cycles && !Verilated::gotFinish(); ++cycles) { - const bool start_cycle = cycles == 0; - clear_inputs(dut); - dut.io_startValid = start_cycle ? 1 : 0; - dut.io_resetPc = args.reset_pc; - dut.io_resetSp = args.reset_sp; - dut.io_fetchReqReady = have_pending_fetch ? 0 : 1; - if (have_pending_fetch) { - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = memory.read_window(pending_fetch_pc); - } - drive_service_responder(dut, service_responder); - eval_with_memory(dut, memory); - - const bool fetch_resp_fire = - have_pending_fetch && dut.io_fetchRespValid && dut.io_fetchRespReady; - const bool service_request_valid = dut.io_reducedServiceRequest_valid; - const bool service_request_fire = - dut.io_reducedServiceRequest_valid && dut.io_reducedServiceRequest_ready; - const bool service_response_valid = dut.io_reducedServiceResponse_valid; - const bool service_response_ready = dut.io_reducedServiceResponse_ready; - const bool service_response_fire = service_response_valid && service_response_ready; - const ReducedServiceRequest service_request = - service_request_fire ? read_service_request(dut) : ReducedServiceRequest{}; - service_responder.observe_cycle(service_request_fire, service_request, service_response_ready); - EventSample sample; - sample.fetch_resp_fire = fetch_resp_fire; - sample.fetch_resp_pc = pending_fetch_pc; - const std::uint64_t commit_rows_this_cycle = - (dut.io_commit_rows_0_valid ? 1ULL : 0ULL) + - (dut.io_commit_rows_1_valid ? 1ULL : 0ULL); - sample.commit_valid = commit_rows_this_cycle != 0; - sample.commit_pc = - dut.io_commit_rows_0_valid ? dut.io_commit_rows_0_pc : dut.io_commit_rows_1_pc; - sample.source_out_fire = dut.io_sourceOutFire; - sample.source_restart_valid = dut.io_sourceRestartValid; - sample.source_blocked = dut.io_debugSourceBlocked; - sample.source_active = dut.io_debugSourceActive; - sample.source_waiting_response = dut.io_debugSourceWaitingResponse; - sample.source_packet_valid = dut.io_debugSourcePacketValid; - sample.source_restart_pc = dut.io_sourceRestartPc; - sample.block_marker_stop_redirect_valid = dut.io_debugBlockMarkerStopRedirectValid; - sample.block_marker_stop_redirect_pc = dut.io_debugBlockMarkerStopRedirectPc; - sample.marker_redirect_fire = dut.io_debugMarkerRedirectFire; - sample.marker_redirect_pending = dut.io_debugMarkerRedirectPending; - sample.marker_redirect_pc = dut.io_debugMarkerRedirectPc; - sample.body_cut_advance_bytes = dut.io_debugBodyCutAdvanceBytes; - sample.f4_total_len_bytes = dut.io_debugF4TotalLenBytes; - sample.fret_condition_bits = dut.io_debugFretConditionBits; - sample.continuation_bits = dut.io_debugContinuationBits; - const std::uint8_t readiness = dut.io_debugReadinessBits; - sample.source_out_ready = (readiness & 0x01U) != 0; - sample.dense_slot_in_ready = (readiness & 0x02U) != 0; - sample.dense_slot_out_ready = (readiness & 0x04U) != 0; - sample.path_decode_ready = (readiness & 0x08U) != 0; - sample.path_renamed_out_ready = (readiness & 0x10U) != 0; - sample.issue_in_ready = (readiness & 0x20U) != 0; - sample.local_incoming_blocked = (readiness & 0x40U) != 0; - sample.marker_retire_lifecycle_fire = (readiness & 0x80U) != 0; - sample.local_pending_counts = dut.io_debugLocalPendingCounts; - sample.local_ready_masks = dut.io_debugLocalReadyMasks; - sample.decode_block_bits = dut.io_debugDecodeBlockBits; - sample.decode_ready_bits = dut.io_debugDecodeReadyBits; - sample.tu_rename_source_underflow_mask = dut.io_debugTuRenameSourceUnderflowMask; - sample.tu_rename_blocked_by_t_alloc = dut.io_debugTuRenameBlockedByTAlloc; - sample.tu_rename_blocked_by_u_alloc = dut.io_debugTuRenameBlockedByUAlloc; - sample.tu_rename_t_used_entries = dut.io_debugTuRenameTUsedEntries; - sample.tu_rename_u_used_entries = dut.io_debugTuRenameUUsedEntries; - sample.tu_retire_command_valid = dut.io_debugTuRetireCommandValid; - sample.tu_retire_command_fire = dut.io_debugTuRetireCommandFire; - sample.tu_retire_local_block_commit_pending = - dut.io_debugTuRetireLocalBlockCommitPending; - sample.tu_retire_local_block_commit_valid = dut.io_debugTuRetireLocalBlockCommitValid; - sample.tu_retire_local_block_commit_ready = dut.io_debugTuRetireLocalBlockCommitReady; - sample.tu_retire_local_block_commit_fire = dut.io_debugTuRetireLocalBlockCommitFire; - sample.tu_retire_accepted = dut.io_debugTuRetireAccepted; - sample.tu_retire_miss = dut.io_debugTuRetireMiss; - sample.tu_retire_release_mismatch = dut.io_debugTuRetireReleaseMismatch; - sample.tu_retire_unsupported = dut.io_debugTuRetireUnsupported; - sample.gpr_reservation_count = dut.io_debugGprReservationCount; - sample.gpr_reservation_need = dut.io_debugGprReservationNeed; - sample.gpr_free_count = dut.io_debugGprFreeCount; - sample.gpr_mapq_valid_count = dut.io_debugGprMapQValidCount; - sample.gpr_mapq_free_count = dut.io_debugGprMapQFreeCount; - sample.gpr_free_list_mismatch_count = dut.io_debugGprFreeListMismatchCount; - sample.gpr_commit_accepted = dut.io_debugGprCommitAccepted; - sample.gpr_commit_block_bid = dut.io_debugGprCommitBlockBid; - sample.gpr_committed_mapq_count = dut.io_debugGprCommittedMapQCount; - sample.gpr_released_phys_count = dut.io_debugGprReleasedPhysCount; - sample.rob_rename_update_attempt_valid = dut.io_debugRobRenameUpdateAttemptValid; - sample.rob_rename_update_ready = dut.io_debugRobRenameUpdateReady; - sample.rob_rename_update_fire = dut.io_debugRobRenameUpdateFire; - sample.rob_rename_update_ignored = dut.io_debugRobRenameUpdateIgnored; - sample.commit_head_valid = dut.io_debugCommitHeadValid; - sample.commit_head_status = dut.io_debugCommitHeadStatus; - sample.commit_head_rob_value = dut.io_debugCommitHeadRobValue; - sample.rob_occupied_mask = dut.io_debugRobOccupiedMask; - sample.rob_completed_mask = dut.io_debugRobCompletedMask; - sample.rob_dealloc_valid_mask = dut.io_debugRobDeallocValidMask; - sample.rob_dealloc_count = dut.io_debugRobDeallocCount; - sample.rob_dealloc_block_last_valid = dut.io_debugRobDeallocBlockLastValid; - sample.rob_dealloc_block_last_block_bid = dut.io_debugRobDeallocBlockLastBlockBid; - sample.block_scalar_done_fire = dut.io_debugBlockScalarDoneFire; - sample.block_scalar_done_bid = dut.io_debugBlockScalarDoneBid; - sample.block_retire_fire = dut.io_debugBlockRetireFire; - sample.block_retire_bid = dut.io_debugBlockRetireBid; - sample.scalar_lr_reservation_valid_stid0 = dut.io_scalarLrReservationValidStid0; - sample.scalar_lr_reservation_line_stid0 = dut.io_scalarLrReservationLineStid0; - sample.scalar_lr_reservation_count = dut.io_scalarLrReservationCount; - sample.scalar_lr_reservation_protocol_error = - dut.io_scalarLrReservationProtocolError; - sample.scalar_lr_reservation_blocked_by_flush = - dut.io_scalarLrReservationBlockedByFlush; - sample.scalar_lr_reservation_committed_store_invalidate = - dut.io_scalarLrReservationCommittedStoreInvalidate; - sample.store_sta_queue_valid = dut.io_storeStaQueueValid; - sample.store_std_queue_valid = dut.io_storeStdQueueValid; - sample.store_sta_dequeue_fire = dut.io_storeStaDequeueFire; - sample.store_std_dequeue_fire = dut.io_storeStdDequeueFire; - sample.store_sta_queue_count = dut.io_storeStaQueueCount; - sample.store_std_queue_count = dut.io_storeStdQueueCount; - sample.store_sta_insert_ready = dut.io_storeStaInsertReady; - sample.store_std_insert_ready = dut.io_storeStdInsertReady; - sample.store_selected_sta = dut.io_storeSelectedSta; - sample.store_selected_std = dut.io_storeSelectedStd; - sample.store_blocked_by_sta_exec = dut.io_storeBlockedByStaExec; - sample.store_blocked_by_std_exec = dut.io_storeBlockedByStdExec; - sample.store_stq_insert_valid = dut.io_storeStqInsertValid; - sample.store_stq_insert_accepted = dut.io_storeStqInsertAccepted; - sample.store_stq_insert_conflict = dut.io_storeStqInsertConflict; - sample.store_stq_insert_index = dut.io_storeStqInsertIndex; - sample.store_stq_occupied_mask = dut.io_storeStqOccupiedMask; - sample.store_stq_wait_mask = dut.io_storeStqWaitMask; - sample.store_stq_commit_mask = dut.io_storeStqCommitMask; - sample.store_stq_addr_ready_mask = dut.io_storeStqAddrReadyMask; - sample.store_stq_data_ready_mask = dut.io_storeStqDataReadyMask; - sample.store_stq_resident_count = dut.io_storeStqResidentCount; - sample.store_stq_outstanding_wait_count = dut.io_storeStqOutstandingWaitCount; - sample.store_stq_empty = dut.io_storeStqEmpty; - sample.store_stq_full = dut.io_storeStqFull; - sample.store_stq_stall = dut.io_storeStqStall; - sample.dec_ren_head_rid_valid = dut.io_debugDecRenHeadRidValid; - sample.dec_ren_head_pc = dut.io_debugLocalHeadPc; - sample.dec_ren_head_rid_value = dut.io_debugDecRenHeadRidValue; - sample.renamed_out_valid = dut.io_debugRenamedOutValid; - sample.renamed_accepted = dut.io_debugRenamedAccepted; - sample.issue_enqueue_fire = dut.io_debugIssueEnqueueFire; - sample.issue_input_valid = dut.io_debugIssueInputValid; - sample.issue_input_pc = dut.io_debugIssueInputPc; - sample.issue_input_opcode = dut.io_debugIssueInputOpcode; - sample.issue_input_bid_valid = dut.io_debugIssueInputBidValid; - sample.issue_input_bid_wrap = dut.io_debugIssueInputBidWrap; - sample.issue_input_bid_value = dut.io_debugIssueInputBidValue; - sample.issue_input_rid_valid = dut.io_debugIssueInputRidValid; - sample.issue_input_rid_wrap = dut.io_debugIssueInputRidWrap; - sample.issue_input_rid_value = dut.io_debugIssueInputRidValue; - sample.issue_input_stid = dut.io_debugIssueInputStid; - sample.issue_pick_fire = dut.io_debugIssuePickFire; - sample.issue_fire = dut.io_debugIssueFire; - sample.issue_output_valid = dut.io_debugIssueOutputValid; - sample.issue_output_pc = dut.io_debugIssueOutputPc; - sample.issue_output_opcode = dut.io_debugIssueOutputOpcode; - sample.issue_output_bid_valid = dut.io_debugIssueOutputBidValid; - sample.issue_output_bid_wrap = dut.io_debugIssueOutputBidWrap; - sample.issue_output_bid_value = dut.io_debugIssueOutputBidValue; - sample.issue_output_rid_valid = dut.io_debugIssueOutputRidValid; - sample.issue_output_rid_wrap = dut.io_debugIssueOutputRidWrap; - sample.issue_output_rid_value = dut.io_debugIssueOutputRidValue; - sample.issue_output_stid = dut.io_debugIssueOutputStid; - sample.issue_head_valid = dut.io_debugIssueHeadValid; - sample.issue_head_issued = dut.io_debugIssueHeadIssued; - sample.issue_head_pc = dut.io_debugIssueHeadPc; - sample.issue_head_stid = dut.io_debugIssueHeadStid; - sample.issue_head_bid_valid = dut.io_debugIssueHeadBidValid; - sample.issue_head_bid_wrap = dut.io_debugIssueHeadBidWrap; - sample.issue_head_bid_value = dut.io_debugIssueHeadBidValue; - sample.issue_head_rid_valid = dut.io_debugIssueHeadRidValid; - sample.issue_head_rid_wrap = dut.io_debugIssueHeadRidWrap; - sample.issue_head_rid_value = dut.io_debugIssueHeadRidValue; - sample.issue_head_src_valid_mask = dut.io_debugIssueHeadSrcValidMask; - sample.issue_head_src_phys_tag[0] = dut.io_debugIssueHeadSrcPhysTag_0; - sample.issue_head_src_phys_tag[1] = dut.io_debugIssueHeadSrcPhysTag_1; - sample.issue_head_src_phys_tag[2] = dut.io_debugIssueHeadSrcPhysTag_2; - sample.issue_source_ready_mask = dut.io_debugIssueSourceReadyMask; - sample.issue_all_sources_ready = dut.io_debugIssueAllSourcesReady; - sample.issue_selected_valid = dut.io_debugIssueSelectedValid; - sample.issue_selected_index = dut.io_debugIssueSelectedIndex; - sample.issue_selected_read_ready = dut.io_debugIssueSelectedReadReady; - sample.issue_stage_bits = dut.io_debugIssueStageBits; - sample.issue_blocked_bits = dut.io_debugIssueBlockedBits; - sample.issue_scalar_sp_order_blocked = dut.io_debugIssueScalarSpOrderBlocked; - sample.issue_bank_scalar_sp_order_blocked_mask = - dut.io_debugIssueBankScalarSpOrderBlockedMask; - sample.scalar_sp_stid0_issue_head_valid = dut.io_debugScalarSpStid0IssueHeadValid; - sample.scalar_sp_stid0_issue_head_bid_valid = - dut.io_debugScalarSpStid0IssueHeadBidValid; - sample.scalar_sp_stid0_issue_head_bid_wrap = - dut.io_debugScalarSpStid0IssueHeadBidWrap; - sample.scalar_sp_stid0_issue_head_bid_value = - dut.io_debugScalarSpStid0IssueHeadBidValue; - sample.scalar_sp_stid0_issue_head_rid_valid = - dut.io_debugScalarSpStid0IssueHeadRidValid; - sample.scalar_sp_stid0_issue_head_rid_wrap = - dut.io_debugScalarSpStid0IssueHeadRidWrap; - sample.scalar_sp_stid0_issue_head_rid_value = - dut.io_debugScalarSpStid0IssueHeadRidValue; - sample.rf_ready_mask = dut.io_debugRfReadyMask; - sample.p_wakeup_valid = dut.io_debugPWakeupValid; - sample.p_wakeup_tag = dut.io_debugPWakeupTag; - sample.p_wakeup_head_match = - sample.p_wakeup_valid && - (((sample.issue_head_src_valid_mask & 0x1U) != 0 && - sample.issue_head_src_phys_tag[0] == sample.p_wakeup_tag) || - ((sample.issue_head_src_valid_mask & 0x2U) != 0 && - sample.issue_head_src_phys_tag[1] == sample.p_wakeup_tag) || - ((sample.issue_head_src_valid_mask & 0x4U) != 0 && - sample.issue_head_src_phys_tag[2] == sample.p_wakeup_tag)); - sample.execute_accepted = dut.io_debugExecuteAccepted; - sample.execute_accepted_identity_valid = dut.io_debugExecuteAcceptedIdentityValid; - sample.execute_accepted_pc = dut.io_debugExecuteAcceptedPc; - sample.execute_accepted_opcode = dut.io_debugExecuteAcceptedOpcode; - sample.execute_accepted_bid_valid = dut.io_debugExecuteAcceptedBidValid; - sample.execute_accepted_bid_wrap = dut.io_debugExecuteAcceptedBidWrap; - sample.execute_accepted_bid_value = dut.io_debugExecuteAcceptedBidValue; - sample.execute_accepted_rid_valid = dut.io_debugExecuteAcceptedRidValid; - sample.execute_accepted_rid_wrap = dut.io_debugExecuteAcceptedRidWrap; - sample.execute_accepted_rid_value = dut.io_debugExecuteAcceptedRidValue; - sample.execute_accepted_stid = dut.io_debugExecuteAcceptedStid; - sample.execute_busy = dut.io_debugExecuteBusy; - sample.execute_unsupported = dut.io_debugExecuteUnsupported; - sample.execute_unsupported_opcode = dut.io_debugExecuteUnsupportedOpcode; - sample.execute_complete_valid = dut.io_debugLocalExecuteCompleteValid; - sample.execute_complete_rob_value = dut.io_debugExecuteCompleteRobValue; - sample.execute_complete_pc = dut.io_debugLocalCompletePc; - sample.execute_complete_src_phys_valid_mask = dut.io_debugExecuteCompleteSrcPhysValidMask; - sample.execute_complete_src_phys_tag[0] = dut.io_debugExecuteCompleteSrcPhysTag_0; - sample.execute_complete_src_phys_tag[1] = dut.io_debugExecuteCompleteSrcPhysTag_1; - sample.execute_complete_src_phys_tag[2] = dut.io_debugExecuteCompleteSrcPhysTag_2; - sample.rob_complete_arbiter_bits = dut.io_debugRobCompleteArbiterBits; - sample.rob_complete_result_bits = dut.io_debugRobCompleteResultBits; - if (fetch_resp_fire) { - have_pending_fetch = false; - ++fetch_responses; - } - if (!have_pending_fetch && dut.io_fetchReqValid && dut.io_fetchReqReady) { - have_pending_fetch = true; - pending_fetch_pc = dut.io_fetchReqPc; - sample.fetch_req_fire = true; - sample.fetch_req_pc = dut.io_fetchReqPc; - ++fetch_requests; - } - sample.source_current_pc = dut.io_fetchCurrentPc; - perf.observe( - sample, - commit_rows_this_cycle, - sample.rob_dealloc_count, - dut.io_loadLookupValid, - dut.io_loadLookupExecuteGranted, - dut.io_loadLookupReplayGranted, - dut.io_storeObserveValid, - dut.io_storeObservePairValid, - service_request_valid, - service_request_fire, - service_response_valid, - service_response_fire); - const bool detailed_cycle_event = - cycles < 8 || sample.fetch_req_fire || sample.fetch_resp_fire || - sample.commit_valid || sample.source_out_fire || sample.source_restart_valid || - sample.block_marker_stop_redirect_valid || sample.marker_redirect_fire || - sample.marker_redirect_pending || !have_previous_sample || - sample_changed(sample, previous_sample); - const bool periodic_cycle_event = - args.event_sample_period > 1 && (cycles % args.event_sample_period) == 0; - const bool exceptional_cycle_event = - cycles < 8 || sample.execute_unsupported || dut.io_trapValid || - dut.io_finisherWriteValid || !have_previous_sample; - const bool write_cycle_event = - args.event_sample_period == 1 ? detailed_cycle_event - : (periodic_cycle_event || exceptional_cycle_event); - if (write_cycle_event) { - write_event(events, cycles, "cycle", sample, have_pending_fetch, pending_fetch_pc); - } - previous_sample = sample; - have_previous_sample = true; - - for (int slot = 0; slot < 2; ++slot) { - const auto row = read_commit_row(dut, slot); - if (row.valid) { - if (args.commit_sample_period == 1 || - (args.commit_sample_period > 1 && (commits % args.commit_sample_period) == 0)) { - linxcore::chisel::write_dut_commit_jsonl(trace, row); - } - ++commits; - } - } - - if (dut.io_storeObserveValid) { - memory.apply_store( - dut.io_storeObserveAddr, - dut.io_storeObserveData, - dut.io_storeObserveSize, - dut.io_storeObserveMask); - } - if (dut.io_storeObservePairValid) { - memory.apply_store( - dut.io_storeObservePairAddr, - dut.io_storeObservePairData, - dut.io_storeObservePairSize, - dut.io_storeObservePairMask); - } - if (dut.io_uartWriteValid) { - const char ch = static_cast(dut.io_uartWriteByte & 0xffU); - uart.push_back(ch); - uart_out << ch; - } - if (dut.io_finisherWriteValid) { - finisher_code = dut.io_finisherCode; - finisher_pass = finisher_code_is_pass(finisher_code); - status = terminal_status(true, finisher_pass, false, false, false); - tick(dut, memory); - ++cycles; - break; - } - if (dut.io_trapValid) { - status = terminal_status(false, false, true, false, false); - tick(dut, memory); - ++cycles; - break; - } - if (dut.io_unsupportedInstruction) { - status = terminal_status(false, false, false, true, false); - tick(dut, memory); - ++cycles; - break; - } - if (service_responder.unsupported()) { - status = terminal_status(false, false, false, true, false); - tick(dut, memory); - ++cycles; - break; - } - if (service_responder.exit_observed()) { - finisher_pass = service_responder.exit_code() == 0; - finisher_code = finisher_pass ? kFinisherPass : 0; - status = terminal_status(true, finisher_pass, false, false, false); - tick(dut, memory); - ++cycles; - break; - } - if (dut.io_halted) { - status = terminal_status(false, false, false, false, true); - tick(dut, memory); - ++cycles; - break; - } - tick(dut, memory); - } - - trace.close(); - EventSample terminal_sample = previous_sample; - perf.finish(); - write_event(events, cycles, "terminal", terminal_sample, have_pending_fetch, pending_fetch_pc); - events.close(); - uart_out.close(); - if (!trace || !events || !uart_out) { - throw std::runtime_error("failed to flush output artifacts"); - } - write_manifest_atomic( - args, - status, - cycles, - commits, - fetch_requests, - fetch_responses, - service_responder.service_requests(), - service_responder.service_responses(), - service_responder.have_last_service_nr(), - service_responder.last_service_nr(), - service_responder.unsupported(), - service_responder.unsupported_service_nr(), - service_responder.exit_observed(), - service_responder.exit_code(), - finisher_code, - finisher_pass, - uart, - perf_manifest_json(perf, cycles, commits)); - std::cerr << "benchmark-autonomous-natural status=" << status - << " cycles=" << cycles - << " commits=" << commits - << " fetch_requests=" << fetch_requests - << " fetch_responses=" << fetch_responses - << " service_requests=" << service_responder.service_requests() - << " service_responses=" << service_responder.service_responses() - << " finisher_code=0x" << std::hex << finisher_code << std::dec - << "\n"; - return status == "finisher_pass" ? 0 : 1; - } catch (const std::exception &exc) { - std::cerr << "error: " << exc.what() << "\n"; - return 2; - } -} -#endif diff --git a/tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh b/tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh deleted file mode 100755 index 20030afe..00000000 --- a/tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh +++ /dev/null @@ -1,240 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -LINX_ROOT="$(cd -- "${ROOT_DIR}/../.." && pwd)" -LLVM_BIN="${LLVM_BIN:-${LINX_ROOT}/compiler/llvm/build-linxisa-clang/bin}" -OUT_DIR="${OUT_DIR:-${ROOT_DIR}/generated/chisel-frontend-fetch-rf-alu-qemu-fixture}" -OUTPUT="" -TEXT_BASE="${TEXT_BASE:-0x10000}" -LONG_BODY=0 -REPLAY_LDI_SDI_LDI=0 -REPLAY_LDI_SDI_LDI_LOOP=0 -REPLAY_LDI_SDI_LDI_LDI_LOOP=0 -REPLAY_LDI_SDI_LDI_SDI_LDI_LOOP=0 -REPLAY_LDI_SDI_LDI_SDI_LDI_LDI_LOOP=0 -REPLAY_LDI_SDI_LDI_LDI_LDI_LDI_LOOP=0 - -usage() { - cat <] [--out-dir ] [--text-base ] [--long-body] [--replay-ldi-sdi-ldi] [--replay-ldi-sdi-ldi-loop] [--replay-ldi-sdi-ldi-ldi-loop] [--replay-ldi-sdi-ldi-sdi-ldi-loop] [--replay-ldi-sdi-ldi-sdi-ldi-ldi-loop] [--replay-ldi-sdi-ldi-ldi-ldi-ldi-loop] - -Builds a tiny legal-entry Linx ELF for the reduced live QEMU fetch RF/ALU gate: - C.BSTART.STD; ADD; ADDI; C.MOVR; C.BSTOP - -With --long-body, the scalar body is extended with additional ADDI, ADD, -C.MOVI, and C.MOVR rows that are already supported by the reduced Chisel ALU. - -With --replay-ldi-sdi-ldi, the scalar body is a minimal memory-order probe: - C.BSTART.STD; LDI; SDI; LDI; C.BSTOP - -With --replay-ldi-sdi-ldi-loop, the same probe is followed by a direct block -back to the first C.BSTART.STD, allowing bounded QEMU captures to include a -second dynamic instance of the same load PCs after MDB record learning. - -With --replay-ldi-sdi-ldi-ldi-loop, the loop probe adds a second younger load -after the store-dependent load to create denser replay-return occupancy for -W1/W2 same-cycle replacement gates. - -With --replay-ldi-sdi-ldi-sdi-ldi-loop, the loop probe repeats the -store/load dependency chain before the direct loop boundary to create denser -MDB/LIQ replay-return pressure for W1/W2 same-cycle replacement gates. - -With --replay-ldi-sdi-ldi-sdi-ldi-ldi-loop, the loop probe repeats the -store/load dependency chain and adds one more younger load after the second -store dependency to test whether a clustered second dependency can create a -different returned-load candidate near W2 live clear. - -With --replay-ldi-sdi-ldi-ldi-ldi-ldi-loop, the loop probe keeps one -store-dependent load and then appends additional consecutive younger loads to -test whether bursty returned-load phasing can overlap W1 refill with W2 clear. - -The scalar prefix starts two bytes after the entry block header. Use the printed -pc filter values with run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh until -the live frontend gate supports block headers. -USAGE -} - -while [[ $# -gt 0 ]]; do - case "$1" in - --output) OUTPUT="$2"; shift 2 ;; - --out-dir) OUT_DIR="$2"; shift 2 ;; - --text-base) TEXT_BASE="$2"; shift 2 ;; - --long-body) LONG_BODY=1; shift ;; - --replay-ldi-sdi-ldi) REPLAY_LDI_SDI_LDI=1; shift ;; - --replay-ldi-sdi-ldi-loop) REPLAY_LDI_SDI_LDI_LOOP=1; shift ;; - --replay-ldi-sdi-ldi-ldi-loop) REPLAY_LDI_SDI_LDI_LDI_LOOP=1; shift ;; - --replay-ldi-sdi-ldi-sdi-ldi-loop) REPLAY_LDI_SDI_LDI_SDI_LDI_LOOP=1; shift ;; - --replay-ldi-sdi-ldi-sdi-ldi-ldi-loop) REPLAY_LDI_SDI_LDI_SDI_LDI_LDI_LOOP=1; shift ;; - --replay-ldi-sdi-ldi-ldi-ldi-ldi-loop) REPLAY_LDI_SDI_LDI_LDI_LDI_LDI_LOOP=1; shift ;; - -h|--help) usage; exit 0 ;; - *) echo "error: unknown argument: $1" >&2; usage; exit 2 ;; - esac -done - -selected_fixture_count=$((LONG_BODY + REPLAY_LDI_SDI_LDI + REPLAY_LDI_SDI_LDI_LOOP + REPLAY_LDI_SDI_LDI_LDI_LOOP + REPLAY_LDI_SDI_LDI_SDI_LDI_LOOP + REPLAY_LDI_SDI_LDI_SDI_LDI_LDI_LOOP + REPLAY_LDI_SDI_LDI_LDI_LDI_LDI_LOOP)) -if (( selected_fixture_count > 1 )); then - echo "error: --long-body, --replay-ldi-sdi-ldi, --replay-ldi-sdi-ldi-loop, --replay-ldi-sdi-ldi-ldi-loop, --replay-ldi-sdi-ldi-sdi-ldi-loop, --replay-ldi-sdi-ldi-sdi-ldi-ldi-loop, and --replay-ldi-sdi-ldi-ldi-ldi-ldi-loop are mutually exclusive" >&2 - exit 2 -fi - -if [[ "${OUT_DIR}" != /* ]]; then - OUT_DIR="${ROOT_DIR}/${OUT_DIR}" -fi -mkdir -p "${OUT_DIR}" - -if [[ -z "${OUTPUT}" ]]; then - OUTPUT="${OUT_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" -elif [[ "${OUTPUT}" != /* ]]; then - OUTPUT="${ROOT_DIR}/${OUTPUT}" -fi -mkdir -p "$(dirname -- "${OUTPUT}")" - -LLVM_MC="${LLVM_BIN}/llvm-mc" -LD_LLD="${LLVM_BIN}/ld.lld" -LLVM_OBJDUMP="${LLVM_BIN}/llvm-objdump" -if [[ ! -x "${LLVM_MC}" || ! -x "${LD_LLD}" || ! -x "${LLVM_OBJDUMP}" ]]; then - echo "error: missing llvm-mc, ld.lld, or llvm-objdump under ${LLVM_BIN}" >&2 - exit 2 -fi - -ASM="${OUT_DIR}/frontend_fetch_rf_alu_qemu_fixture.s" -OBJ="${OUT_DIR}/frontend_fetch_rf_alu_qemu_fixture.o" -DISASM="${OUT_DIR}/frontend_fetch_rf_alu_qemu_fixture.objdump" - -if [[ "${REPLAY_LDI_SDI_LDI_LDI_LDI_LDI_LOOP}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0x21 - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - C.BSTART # C.BSTART.STD, assembler form - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Store-dependent younger LDI - ldi [r0, 0], ->r5 # Consecutive younger LDI - ldi [r0, 0], ->r6 # Consecutive younger LDI - ldi [r0, 0], ->r7 # Consecutive younger LDI -loop_back: - C.BSTART DIRECT, _start - C.BSTOP -ASM -elif [[ "${REPLAY_LDI_SDI_LDI_SDI_LDI_LDI_LOOP}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0x21 - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - C.BSTART # C.BSTART.STD, assembler form - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Younger LDI after the store - sdi r4, [r0, 0] # Second SDI to repeat the dependency chain - ldi [r0, 0], ->r5 # Younger LDI after the second store - ldi [r0, 0], ->r6 # Extra younger LDI to cluster the second dependency -loop_back: - C.BSTART DIRECT, _start - C.BSTOP -ASM -elif [[ "${REPLAY_LDI_SDI_LDI_SDI_LDI_LOOP}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0x1d - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - C.BSTART # C.BSTART.STD, assembler form - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Younger LDI after the store - sdi r4, [r0, 0] # Second SDI to repeat the dependency chain - ldi [r0, 0], ->r5 # Younger LDI after the second store -loop_back: - C.BSTART DIRECT, _start - C.BSTOP -ASM -elif [[ "${REPLAY_LDI_SDI_LDI_LDI_LOOP}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0x19 - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - C.BSTART # C.BSTART.STD, assembler form - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Younger LDI after the store - ldi [r0, 0], ->r5 # Second younger LDI to densify LRET occupancy -loop_back: - C.BSTART DIRECT, _start - C.BSTOP -ASM -elif [[ "${REPLAY_LDI_SDI_LDI_LOOP}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0x15 - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - C.BSTART # C.BSTART.STD, assembler form - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Younger LDI after the store -loop_back: - C.BSTART DIRECT, _start - C.BSTOP -ASM -elif [[ "${REPLAY_LDI_SDI_LDI}" -eq 1 ]]; then - SCALAR_PC_HI_OFFSET=0xf - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - .short 0x0800 # C.BSTART.STD - ldi [r0, 0], ->r3 # LDI from zero base - sdi r3, [r0, 0] # SDI to the same base - ldi [r0, 0], ->r4 # Younger LDI after the store - .short 0x0000 # C.BSTOP -ASM -elif [[ "${LONG_BODY}" -eq 0 ]]; then - SCALAR_PC_HI_OFFSET=0xb - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - .short 0x0800 # C.BSTART.STD - .word 0x00520185 # ADD r3, r4, r5 - .word 0x7ff18315 # ADDI r6, r3, 0x7ff - .short 0x2986 # C.MOVR r5, r6 - .short 0x0000 # C.BSTOP -ASM -else - SCALAR_PC_HI_OFFSET=0x17 - cat > "${ASM}" <<'ASM' -.section .text,"ax",@progbits -.globl _start -_start: - .short 0x0800 # C.BSTART.STD - .word 0x00520185 # ADD r3, r4, r5 - .word 0x7ff18315 # ADDI r6, r3, 0x7ff - .short 0x2986 # C.MOVR r5, r6 - .word 0x00130395 # ADDI r7, r6, 1 - .word 0x06338405 # ADD r8, r7, r3 - .short 0x4956 # C.MOVI r9, 5 - .short 0x3a06 # C.MOVR r7, r8 - .short 0x0000 # C.BSTOP -ASM -fi - -"${LLVM_MC}" -triple=linx64 -filetype=obj -o "${OBJ}" "${ASM}" -"${LD_LLD}" -Ttext="${TEXT_BASE}" -e _start -o "${OUTPUT}" "${OBJ}" -"${LLVM_OBJDUMP}" -d "${OUTPUT}" > "${DISASM}" - -python3 - "${TEXT_BASE}" "${SCALAR_PC_HI_OFFSET}" <<'PY' -import sys -base = int(sys.argv[1], 0) -hi_offset = int(sys.argv[2], 0) -print(f"fixture-elf-text-base=0x{base:x}") -print(f"fixture-elf-scalar-pc-lo=0x{base + 2:x}") -print(f"fixture-elf-scalar-pc-hi=0x{base + hi_offset:x}") -PY -echo "fixture-elf=${OUTPUT}" -echo "fixture-elf-objdump=${DISASM}" diff --git a/tools/chisel/build_replay_liq_activation_gap_report.py b/tools/chisel/build_replay_liq_activation_gap_report.py deleted file mode 100644 index aefeb224..00000000 --- a/tools/chisel/build_replay_liq_activation_gap_report.py +++ /dev/null @@ -1,307 +0,0 @@ -#!/usr/bin/env python3 -"""Build a replay-LIQ activation-gap report from R621 evidence. - -The report distinguishes a QEMU commit-stream store/load address cluster from a -generated-RTL stimulus that actually reaches resident-store overlap, ResolveQ, -MDB conflict, and LIQ allocation. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_activation_gap_report.v1" - -DEFAULT_R621_REPORT = ( - ROOT_DIR - / "generated/r621-replay-liq-selector-unskipped-prefix-report/report/replay_liq_selector_unskipped_prefix_report.json" -) -DEFAULT_SIDEBAND = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-rtl-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r622-replay-liq-activation-gap-report/report/replay_liq_activation_gap_report.json" -) - -COUNTERS = ( - "load_lookup_valid", - "load_lookup_execute_granted", - "load_lookup_execute_with_eligible_store", - "load_lookup_execute_with_wait_store", - "resident_store_eligible", - "resident_store_ready_forward", - "resident_store_wait_blocked", - "resident_store_wait_store_valid", - "store_stq_resident", - "store_sta_dequeue_fire", - "store_std_dequeue_fire", - "store_stq_addr_ready_not_data_ready", - "mdb_conflict_store_valid", - "mdb_conflict_store_with_resolve_queue_valid", - "mdb_conflict_store_without_resolve_queue_valid", - "resolve_queue_push_accepted", - "resolve_queue_valid", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "mdb_lookup_wait_plan_wait_intent_valid", - "wait_replay_capture_accepted", - "liq_alloc_accepted", -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def replay_counters(sideband: dict[str, Any]) -> dict[str, int | None]: - replay = sideband.get("replay_liq") - if not isinstance(replay, dict): - return {key: None for key in COUNTERS} - out: dict[str, int | None] = {} - for key in COUNTERS: - value = replay.get(key) - out[key] = value if isinstance(value, int) else None - return out - - -def positive(counters: dict[str, int | None], key: str) -> bool: - value = counters.get(key) - return isinstance(value, int) and value > 0 - - -def zero(counters: dict[str, int | None], key: str) -> bool: - value = counters.get(key) - return isinstance(value, int) and value == 0 - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - r621 = load_json(args.r621_report) - sideband = load_json(args.sideband) - counters = replay_counters(sideband) - - qemu_pair_present = bool( - r621.get("qemu_only_unskipped_prefix", {}).get("target_pair", {}).get("present") - ) - rtl_pair_present = bool( - r621.get("generated_rtl_unskipped_prefix", {}).get("target_pair", {}).get("present") - ) - manifest_summary = r621.get("generated_rtl_unskipped_prefix", {}).get("summary") - compare_pass = ( - r621.get("generated_rtl_unskipped_prefix", {}).get("manifest_status") == "pass" - and isinstance(manifest_summary, dict) - and manifest_summary.get("mismatch_count") == 0 - and isinstance(manifest_summary.get("compared_rows"), int) - and manifest_summary.get("compared_rows") > 0 - ) - - memory_path_active = ( - positive(counters, "load_lookup_valid") - and positive(counters, "store_stq_resident") - and positive(counters, "store_sta_dequeue_fire") - and positive(counters, "store_std_dequeue_fire") - ) - resident_overlap_absent = ( - zero(counters, "resident_store_eligible") - and zero(counters, "load_lookup_execute_with_eligible_store") - and zero(counters, "load_lookup_execute_with_wait_store") - and zero(counters, "resident_store_wait_store_valid") - ) - resolve_queue_absent = zero(counters, "resolve_queue_push_accepted") and zero(counters, "resolve_queue_valid") - mdb_absent = ( - positive(counters, "mdb_conflict_store_valid") - and zero(counters, "mdb_conflict_store_with_resolve_queue_valid") - and positive(counters, "mdb_conflict_store_without_resolve_queue_valid") - and zero(counters, "mdb_conflict_valid") - and zero(counters, "mdb_fanout_record_valid") - ) - liq_absent = zero(counters, "wait_replay_capture_accepted") and zero(counters, "liq_alloc_accepted") - - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "R621 reaches a QEMU and generated-RTL preview address cluster, but the generated-RTL " - "run never observes a load lookup with an eligible resident store. The activation gap " - "is before ResolveQ/MDB/LIQ proof, so later work needs a live resident-store overlap " - "stimulus or a focused replay fixture." - ), - "inputs": { - "r621_report": str(args.r621_report), - "sideband_report": str(args.sideband), - }, - "r621_candidate": { - "qemu_pair_present": qemu_pair_present, - "generated_rtl_pair_present": rtl_pair_present, - "compare_pass": compare_pass, - }, - "activation_stages": { - "memory_path_active": memory_path_active, - "resident_store_overlap_absent": resident_overlap_absent, - "resolve_queue_absent": resolve_queue_absent, - "mdb_absent": mdb_absent, - "liq_absent": liq_absent, - }, - "counters": counters, - "next_probe_contract": { - "must_find_or_construct": "load_lookup_execute_with_eligible_store > 0", - "positive_replay_proof_requires": [ - "load_lookup_execute_with_wait_store > 0 or equivalent retained replay fixture stimulus", - "resolve_queue_push_accepted > 0", - "mdb_conflict_valid > 0", - "mdb_fanout_record_valid > 0", - "wait_replay_capture_accepted > 0", - "liq_alloc_accepted > 0", - ], - }, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append(f"report: status is {report.get('status')!r}, expected 'pass'") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "before ResolveQ/MDB/LIQ proof" not in boundary: - errors.append("report: claim_boundary must identify the pre-ResolveQ activation gap") - candidate = report.get("r621_candidate") - if not isinstance(candidate, dict): - errors.append("r621_candidate: missing section") - else: - for key in ("qemu_pair_present", "generated_rtl_pair_present", "compare_pass"): - if candidate.get(key) is not True: - errors.append(f"r621_candidate: {key} must be true") - stages = report.get("activation_stages") - if not isinstance(stages, dict): - errors.append("activation_stages: missing section") - else: - expected_true = ( - "memory_path_active", - "resident_store_overlap_absent", - "resolve_queue_absent", - "mdb_absent", - "liq_absent", - ) - for key in expected_true: - if stages.get(key) is not True: - errors.append(f"activation_stages: {key} must be true") - counters = report.get("counters") - if not isinstance(counters, dict): - errors.append("counters: missing section") - else: - for key in COUNTERS: - if not isinstance(counters.get(key), int): - errors.append(f"counters: {key} is not an integer") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "gap is before ResolveQ/MDB/LIQ proof", - "r621_candidate": { - "qemu_pair_present": True, - "generated_rtl_pair_present": True, - "compare_pass": True, - }, - "activation_stages": { - "memory_path_active": True, - "resident_store_overlap_absent": True, - "resolve_queue_absent": True, - "mdb_absent": True, - "liq_absent": True, - }, - "counters": { - key: (1 if key in { - "load_lookup_valid", - "store_stq_resident", - "store_sta_dequeue_fire", - "store_std_dequeue_fire", - "mdb_conflict_store_valid", - "mdb_conflict_store_without_resolve_queue_valid", - } else 0) - for key in COUNTERS - }, - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["activation_stages"]["resident_store_overlap_absent"] = False - if not validate_report(failing): - raise AssertionError("resident-overlap classification violation was not detected") - failing = copy.deepcopy(passing) - failing["r621_candidate"]["compare_pass"] = False - if not validate_report(failing): - raise AssertionError("compare-pass violation was not detected") - failing = copy.deepcopy(passing) - failing["counters"]["liq_alloc_accepted"] = None - if not validate_report(failing): - raise AssertionError("missing counter violation was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--r621-report", type=Path, default=DEFAULT_R621_REPORT) - parser.add_argument("--sideband", type=Path, default=DEFAULT_SIDEBAND) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-activation-gap-report self-test: ok") - if args.validate_only is None and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-activation-gap-report: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-activation-gap-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_eligible_store_proof_report.py b/tools/chisel/build_replay_liq_eligible_store_proof_report.py deleted file mode 100644 index 7277ac13..00000000 --- a/tools/chisel/build_replay_liq_eligible_store_proof_report.py +++ /dev/null @@ -1,359 +0,0 @@ -#!/usr/bin/env python3 -"""Build a replay-LIQ eligible-store proof report from R622/R623 evidence. - -The report preserves the current claim boundary: R622 explains why the -CoreMark candidate-present prefix is pre-ResolveQ, while R623 proves that the -current generated RTL can activate the resident-store, ResolveQ, MDB, LIQ, and -retire-promotion path on a focused replay fixture. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_eligible_store_proof_report.v1" - -DEFAULT_R622_REPORT = ( - ROOT_DIR - / "generated/r622-replay-liq-activation-gap-report/report/replay_liq_activation_gap_report.json" -) -DEFAULT_R623_MANIFEST = ( - ROOT_DIR - / "generated/r623-replay-eligible-store-focused-xcheck/report/crosscheck_manifest.json" -) -DEFAULT_R623_SIDEBAND = ( - ROOT_DIR - / "generated/r623-replay-eligible-store-focused-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r623-replay-liq-eligible-store-proof-report/report/replay_liq_eligible_store_proof_report.json" -) - -REQUIRED_POSITIVE_COUNTERS = ( - "load_lookup_valid", - "load_lookup_execute_with_eligible_store", - "load_lookup_execute_with_wait_store", - "resident_store_eligible", - "resident_store_wait_store_valid", - "resolve_queue_push_accepted", - "resolve_queue_valid", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "wait_replay_capture_accepted", - "liq_alloc_accepted", - "replay_queue_out_fire", - "lret_w2_slot_accepted", - "w2_promotion_live", -) - -SELECTOR_ORIGIN_COUNTERS = ( - "w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate", - "w2_retire_record_physical_bundle_suppress_select_selected", - "w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "w2_retire_record_physical_bundle_suppress_boundary_capture", - "w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask", - "w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate", - "w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned", -) - -REQUIRED_ZERO_COUNTERS = ( - "w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask", - "w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch", -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def replay_counters(sideband: dict[str, Any], keys: tuple[str, ...]) -> dict[str, int | None]: - replay = sideband.get("replay_liq") - if not isinstance(replay, dict): - return {key: None for key in keys} - out: dict[str, int | None] = {} - for key in keys: - value = replay.get(key) - out[key] = value if isinstance(value, int) else None - return out - - -def positive(counters: dict[str, int | None], key: str) -> bool: - value = counters.get(key) - return isinstance(value, int) and value > 0 - - -def zero(counters: dict[str, int | None], key: str) -> bool: - value = counters.get(key) - return isinstance(value, int) and value == 0 - - -def manifest_pass(manifest: dict[str, Any]) -> bool: - summary = manifest.get("summary") - cbstop = summary.get("cbstop_counts") if isinstance(summary, dict) else None - comparator_status = manifest.get("comparator_status") - return ( - manifest.get("status") == "pass" - and comparator_status in (0, "pass") - and isinstance(summary, dict) - and isinstance(summary.get("compared_rows"), int) - and summary["compared_rows"] > 0 - and summary.get("mismatch_count") == 0 - and isinstance(cbstop, dict) - and cbstop.get("qemu") == 0 - and cbstop.get("dut") == 0 - ) - - -def manifest_summary(manifest: dict[str, Any]) -> dict[str, Any]: - summary = manifest.get("summary") - if not isinstance(summary, dict): - return {} - cbstop = summary.get("cbstop_counts") - return { - "status": manifest.get("status"), - "comparator_status": manifest.get("comparator_status"), - "compared_rows": summary.get("compared_rows"), - "mismatch_count": summary.get("mismatch_count"), - "cbstop_qemu": cbstop.get("qemu") if isinstance(cbstop, dict) else None, - "cbstop_dut": cbstop.get("dut") if isinstance(cbstop, dict) else None, - } - - -def r622_gap_still_pre_resolveq(r622: dict[str, Any]) -> bool: - stages = r622.get("activation_stages") - counters = r622.get("counters") - return ( - r622.get("schema") == "linxcore.replay_liq_activation_gap_report.v1" - and r622.get("status") == "pass" - and isinstance(stages, dict) - and stages.get("memory_path_active") is True - and stages.get("resident_store_overlap_absent") is True - and stages.get("resolve_queue_absent") is True - and isinstance(counters, dict) - and counters.get("load_lookup_execute_with_eligible_store") == 0 - ) - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - r622 = load_json(args.r622_report) - manifest = load_json(args.r623_manifest) - sideband = load_json(args.r623_sideband) - positive_counters = replay_counters(sideband, REQUIRED_POSITIVE_COUNTERS) - selector_counters = replay_counters(sideband, SELECTOR_ORIGIN_COUNTERS) - zero_counters = replay_counters(sideband, REQUIRED_ZERO_COUNTERS) - - activation_chain = { - "r622_coremark_gap_confirmed": r622_gap_still_pre_resolveq(r622), - "r623_manifest_pass": manifest_pass(manifest), - "resident_store_overlap_present": positive(positive_counters, "load_lookup_execute_with_eligible_store") - and positive(positive_counters, "resident_store_eligible"), - "wait_store_present": positive(positive_counters, "load_lookup_execute_with_wait_store") - and positive(positive_counters, "resident_store_wait_store_valid"), - "resolve_queue_active": positive(positive_counters, "resolve_queue_push_accepted") - and positive(positive_counters, "resolve_queue_valid"), - "mdb_active": positive(positive_counters, "mdb_conflict_valid") - and positive(positive_counters, "mdb_fanout_record_valid"), - "liq_active": positive(positive_counters, "wait_replay_capture_accepted") - and positive(positive_counters, "liq_alloc_accepted") - and positive(positive_counters, "replay_queue_out_fire"), - "retire_promotion_active": positive(positive_counters, "lret_w2_slot_accepted") - and positive(positive_counters, "w2_promotion_live"), - "selector_origin_active": all(positive(selector_counters, key) for key in SELECTOR_ORIGIN_COUNTERS) - and all(zero(zero_counters, key) for key in REQUIRED_ZERO_COUNTERS), - } - - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "R623 proves current-head focused-fixture replay-LIQ activation with eligible " - "resident-store overlap, ResolveQ, MDB, LIQ allocation, replay output, and W2 " - "promotion. It does not convert the R621/R622 CoreMark candidate-present prefix " - "into natural replay-LIQ replacement proof." - ), - "inputs": { - "r622_report": str(args.r622_report), - "r623_manifest": str(args.r623_manifest), - "r623_sideband": str(args.r623_sideband), - }, - "r623_manifest": manifest_summary(manifest), - "activation_chain": activation_chain, - "positive_counters": positive_counters, - "selector_origin_counters": selector_counters, - "required_zero_counters": zero_counters, - "git": manifest.get("git", {}), - "next_probe_contract": { - "coremark_replacement_needs": [ - "a generated-RTL CoreMark or natural workload command with load_lookup_execute_with_eligible_store > 0", - "nonzero ResolveQ/MDB/LIQ proof counters in that same run", - "zero architectural mismatches and zero QEMU/DUT CBSTOP rows", - ], - "focused_fixture_status": "positive current-head proof surface for replay-LIQ activation", - }, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append(f"report: status is {report.get('status')!r}, expected 'pass'") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "does not convert" not in boundary: - errors.append("report: claim_boundary must preserve the CoreMark replacement boundary") - manifest = report.get("r623_manifest") - if not isinstance(manifest, dict): - errors.append("r623_manifest: missing section") - else: - if manifest.get("status") != "pass" or manifest.get("comparator_status") not in (0, "pass"): - errors.append("r623_manifest: status fields must pass") - if not isinstance(manifest.get("compared_rows"), int) or manifest["compared_rows"] <= 0: - errors.append("r623_manifest: compared_rows must be positive") - if manifest.get("mismatch_count") != 0: - errors.append("r623_manifest: mismatch_count must be zero") - if manifest.get("cbstop_qemu") != 0 or manifest.get("cbstop_dut") != 0: - errors.append("r623_manifest: QEMU/DUT CBSTOP counts must be zero") - chain = report.get("activation_chain") - if not isinstance(chain, dict): - errors.append("activation_chain: missing section") - else: - for key, value in chain.items(): - if value is not True: - errors.append(f"activation_chain: {key} must be true") - positives = report.get("positive_counters") - if not isinstance(positives, dict): - errors.append("positive_counters: missing section") - else: - for key in REQUIRED_POSITIVE_COUNTERS: - if not positive(positives, key): - errors.append(f"positive_counters: {key} must be positive") - selector = report.get("selector_origin_counters") - if not isinstance(selector, dict): - errors.append("selector_origin_counters: missing section") - else: - for key in SELECTOR_ORIGIN_COUNTERS: - if not positive(selector, key): - errors.append(f"selector_origin_counters: {key} must be positive") - zeroes = report.get("required_zero_counters") - if not isinstance(zeroes, dict): - errors.append("required_zero_counters: missing section") - else: - for key in REQUIRED_ZERO_COUNTERS: - if not zero(zeroes, key): - errors.append(f"required_zero_counters: {key} must be zero") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "focused proof does not convert CoreMark replacement boundary", - "r623_manifest": { - "status": "pass", - "comparator_status": "pass", - "compared_rows": 18, - "mismatch_count": 0, - "cbstop_qemu": 0, - "cbstop_dut": 0, - }, - "activation_chain": { - "r622_coremark_gap_confirmed": True, - "r623_manifest_pass": True, - "resident_store_overlap_present": True, - "wait_store_present": True, - "resolve_queue_active": True, - "mdb_active": True, - "liq_active": True, - "retire_promotion_active": True, - "selector_origin_active": True, - }, - "positive_counters": {key: 1 for key in REQUIRED_POSITIVE_COUNTERS}, - "selector_origin_counters": {key: 1 for key in SELECTOR_ORIGIN_COUNTERS}, - "required_zero_counters": {key: 0 for key in REQUIRED_ZERO_COUNTERS}, - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["activation_chain"]["resolve_queue_active"] = False - if not validate_report(failing): - raise AssertionError("missing ResolveQ activation was not detected") - failing = copy.deepcopy(passing) - failing["positive_counters"]["load_lookup_execute_with_eligible_store"] = 0 - if not validate_report(failing): - raise AssertionError("missing eligible-store counter was not detected") - failing = copy.deepcopy(passing) - failing["required_zero_counters"][ - "w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch" - ] = 1 - if not validate_report(failing): - raise AssertionError("selector invalid-mask mismatch was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--r622-report", type=Path, default=DEFAULT_R622_REPORT) - parser.add_argument("--r623-manifest", type=Path, default=DEFAULT_R623_MANIFEST) - parser.add_argument("--r623-sideband", type=Path, default=DEFAULT_R623_SIDEBAND) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-eligible-store-proof-report self-test: ok") - if args.validate_only is None and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-eligible-store-proof-report: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-eligible-store-proof-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_natural_activation_probe_plan.py b/tools/chisel/build_replay_liq_natural_activation_probe_plan.py deleted file mode 100644 index 6638b37d..00000000 --- a/tools/chisel/build_replay_liq_natural_activation_probe_plan.py +++ /dev/null @@ -1,374 +0,0 @@ -#!/usr/bin/env python3 -"""Build the replay-LIQ natural-workload activation probe plan. - -R623 proves focused-fixture activation. R624 shows existing positive artifacts -are not CoreMark. This R625 plan widens the CoreMark candidate scan and records -which PC-filter preflights are still blocked before any further Verilator run. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_natural_activation_probe_plan.v1" - -DEFAULT_R622_REPORT = ( - ROOT_DIR - / "generated/r622-replay-liq-activation-gap-report/report/replay_liq_activation_gap_report.json" -) -DEFAULT_R624_SCAN = ( - ROOT_DIR - / "generated/r624-replay-liq-activation-artifact-scan/report/replay_liq_activation_artifact_scan.json" -) -DEFAULT_CANDIDATES = ( - ROOT_DIR - / "generated/r625-coremark-unskipped-1721-qemu-candidates-top100/report/replay_liq_qemu_candidates.json" -) -DEFAULT_R620_PREFLIGHT = ( - ROOT_DIR - / "generated/r620-replay-liq-selector-preflight-report/report/replay_liq_selector_preflight_report.json" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r625-replay-liq-natural-activation-probe-plan/report/replay_liq_natural_activation_probe_plan.json" -) - -TRIALS = ( - { - "label": "r625_pc_filter_400055f2_40005644", - "build_dir": "generated/r625-coremark-pc-filter-400055f2-40005644-qemu-preflight", - "pc_lo": "0x400055f2", - "pc_hi": "0x40005645", - "expected_store_pcs": ["0x400055f2"], - "expected_load_pcs": ["0x40005644"], - }, - { - "label": "r625_pc_filter_40005682_40005700", - "build_dir": "generated/r625-coremark-pc-filter-40005682-40005700-qemu-preflight", - "pc_lo": "0x40005682", - "pc_hi": "0x40005701", - "expected_store_pcs": ["0x40005682"], - "expected_load_pcs": ["0x40005700"], - }, - { - "label": "r625_pc_filter_400055b6_40005600", - "build_dir": "generated/r625-coremark-pc-filter-400055b6-40005600-qemu-preflight", - "pc_lo": "0x400055b6", - "pc_hi": "0x40005601", - "expected_store_pcs": ["0x400055b6"], - "expected_load_pcs": ["0x40005600"], - }, -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def count_jsonl_rows(path: Path) -> int: - if not path.exists(): - return 0 - with path.open("r", encoding="utf-8", errors="replace") as f: - return sum(1 for line in f if line.strip()) - - -def parse_int(value: Any) -> int: - if isinstance(value, int): - return value - if isinstance(value, str): - return int(value, 0) - raise ValueError(f"expected integer-like value, got {value!r}") - - -def r622_gap_confirmed(report: dict[str, Any]) -> bool: - stages = report.get("activation_stages") - counters = report.get("counters") - return ( - report.get("schema") == "linxcore.replay_liq_activation_gap_report.v1" - and report.get("status") == "pass" - and isinstance(stages, dict) - and stages.get("resident_store_overlap_absent") is True - and stages.get("resolve_queue_absent") is True - and isinstance(counters, dict) - and counters.get("load_lookup_execute_with_eligible_store") == 0 - ) - - -def r624_coremark_absent(report: dict[str, Any]) -> bool: - summary = report.get("summary") - return ( - report.get("schema") == "linxcore.replay_liq_activation_artifact_scan.v1" - and report.get("status") == "pass" - and isinstance(summary, dict) - and summary.get("coremark_positive_count") == 0 - ) - - -def candidate_summary(report: dict[str, Any]) -> dict[str, Any]: - candidates = report.get("top_candidates") - if not isinstance(candidates, list): - candidates = [] - narrow_exact = [] - for candidate in candidates: - if not isinstance(candidate, dict): - continue - span = parse_int(candidate.get("pc_hi")) - parse_int(candidate.get("pc_lo")) - if ( - candidate.get("kind") == "store_before_load" - and candidate.get("exact_overlap") is True - and span <= 256 - ): - narrow_exact.append( - { - "score": candidate.get("score"), - "row_distance": candidate.get("row_distance"), - "pc_span": span, - "store_pc": candidate.get("first", {}).get("pc"), - "load_pc": candidate.get("second", {}).get("pc"), - "raw_dynamic_window": candidate.get("probe_hint", {}).get("raw_dynamic_window"), - "pc_filter": candidate.get("probe_hint", {}).get("pc_filter"), - } - ) - return { - "schema": report.get("schema"), - "event_count": report.get("event_count"), - "store_count": report.get("store_count"), - "load_count": report.get("load_count"), - "candidate_count": report.get("candidate_count"), - "top_candidate_count": len(candidates), - "narrow_exact_store_before_load_count": len(narrow_exact), - "narrow_exact_store_before_load": narrow_exact, - } - - -def classify_trial(trial: dict[str, Any]) -> dict[str, Any]: - build_dir = ROOT_DIR / str(trial["build_dir"]) - raw_trace = build_dir / "traces/qemu.live.raw.jsonl" - preview = build_dir / "traces/qemu.live.expected.preview.jsonl" - raw_rows = count_jsonl_rows(raw_trace) - preview_rows = count_jsonl_rows(preview) - if raw_rows == 0: - status = "empty" - reason = "PC filter produced no QEMU rows" - elif preview_rows == 0: - status = "reducer_failed" - reason = "PC filter produced rows, but the reduced-row extractor did not produce a legal expected preview" - else: - status = "preview_present" - reason = "PC filter produced a reduced preview; inspect memory-PC guards before any generated-RTL run" - return { - **trial, - "raw_trace": str(raw_trace), - "preview": str(preview), - "raw_rows": raw_rows, - "preview_rows": preview_rows, - "status": status, - "reason": reason, - } - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - r622 = load_json(args.r622_report) - r624 = load_json(args.r624_scan) - candidates = load_json(args.candidates) - r620 = load_json(args.r620_preflight) - candidate_info = candidate_summary(candidates) - trials = [classify_trial(trial) for trial in TRIALS] - - top_pc_filter = r620.get("pc_filter_qemu_only") - top_status = top_pc_filter.get("status") if isinstance(top_pc_filter, dict) else None - all_trials_blocked = all(trial["status"] in {"empty", "reducer_failed"} for trial in trials) - - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "R625 is a natural-workload probe plan and QEMU-only preflight classifier. " - "It does not authorize a generated-RTL CoreMark replay-LIQ proof until a " - "non-skipped or legal PC-filter command shape passes expected-memory-PC guards." - ), - "inputs": { - "r622_report": str(args.r622_report), - "r624_scan": str(args.r624_scan), - "candidates": str(args.candidates), - "r620_preflight": str(args.r620_preflight), - }, - "evidence_checks": { - "r622_coremark_gap_confirmed": r622_gap_confirmed(r622), - "r624_coremark_positive_absent": r624_coremark_absent(r624), - "top_candidate_pc_filter_blocked": top_status != "pass", - "sampled_new_pc_filters_blocked": all_trials_blocked, - }, - "candidate_summary": candidate_info, - "known_top_candidate_preflight": { - "source": str(args.r620_preflight), - "pc_filter_status": top_status, - "generated_rtl_status": r620.get("generated_rtl", {}).get("status") - if isinstance(r620.get("generated_rtl"), dict) - else None, - }, - "pc_filter_trials": trials, - "generated_rtl": { - "status": "blocked", - "reason": ( - "The unskipped CoreMark prefix remains pre-ResolveQ, the known narrow top " - "candidate PC-filter preflight did not pass, and sampled untried narrow PC " - "filters are empty or illegal reduced prefixes." - ), - }, - "next_probe_contract": { - "do_not_spend_verilator_on": [ - "raw skipped windows, because skipped rows cannot reconstruct DUT state", - "PC filters whose QEMU-only preflight is empty or reducer_failed", - "wide PC spans that collect unrelated memory rows before exact memory-PC guards pass", - ], - "next_viable_paths": [ - "add checkpoint/state-replay support for skipped raw windows", - "construct a natural workload or benchmark shard whose unskipped prefix reaches eligible-store overlap", - "find a PC-filtered QEMU-only preflight that produces a legal reduced preview with exact expected memory PCs", - ], - }, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append("report: status must be pass") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "does not authorize" not in boundary: - errors.append("report: claim_boundary must keep generated RTL blocked") - checks = report.get("evidence_checks") - if not isinstance(checks, dict): - errors.append("evidence_checks: missing section") - else: - for key, value in checks.items(): - if value is not True: - errors.append(f"evidence_checks: {key} must be true") - candidate = report.get("candidate_summary") - if not isinstance(candidate, dict): - errors.append("candidate_summary: missing section") - else: - if not isinstance(candidate.get("candidate_count"), int) or candidate["candidate_count"] <= 0: - errors.append("candidate_summary: candidate_count must be positive") - if ( - not isinstance(candidate.get("narrow_exact_store_before_load_count"), int) - or candidate["narrow_exact_store_before_load_count"] <= 0 - ): - errors.append("candidate_summary: narrow exact store-before-load candidates must be present") - trials = report.get("pc_filter_trials") - if not isinstance(trials, list) or not trials: - errors.append("pc_filter_trials: missing trials") - else: - for trial in trials: - if not isinstance(trial, dict): - errors.append("pc_filter_trials: non-object trial") - continue - if trial.get("status") not in {"empty", "reducer_failed", "preview_present"}: - errors.append(f"pc_filter_trials: bad status {trial.get('status')!r}") - generated = report.get("generated_rtl") - if not isinstance(generated, dict) or generated.get("status") != "blocked": - errors.append("generated_rtl: must remain blocked") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "plan does not authorize generated RTL", - "evidence_checks": { - "r622_coremark_gap_confirmed": True, - "r624_coremark_positive_absent": True, - "top_candidate_pc_filter_blocked": True, - "sampled_new_pc_filters_blocked": True, - }, - "candidate_summary": { - "candidate_count": 2, - "narrow_exact_store_before_load_count": 1, - }, - "pc_filter_trials": [{"status": "empty"}], - "generated_rtl": {"status": "blocked"}, - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["generated_rtl"]["status"] = "ready" - if not validate_report(failing): - raise AssertionError("unblocked generated RTL was not detected") - failing = copy.deepcopy(passing) - failing["evidence_checks"]["r624_coremark_positive_absent"] = False - if not validate_report(failing): - raise AssertionError("failed evidence check was not detected") - failing = copy.deepcopy(passing) - failing["candidate_summary"]["narrow_exact_store_before_load_count"] = 0 - if not validate_report(failing): - raise AssertionError("missing candidate coverage was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--r622-report", type=Path, default=DEFAULT_R622_REPORT) - parser.add_argument("--r624-scan", type=Path, default=DEFAULT_R624_SCAN) - parser.add_argument("--candidates", type=Path, default=DEFAULT_CANDIDATES) - parser.add_argument("--r620-preflight", type=Path, default=DEFAULT_R620_PREFLIGHT) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-natural-activation-probe-plan self-test: ok") - if args.validate_only is None and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-natural-activation-probe-plan: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-natural-activation-probe-plan={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_pc_filter_activation_report.py b/tools/chisel/build_replay_liq_pc_filter_activation_report.py deleted file mode 100644 index 068431f3..00000000 --- a/tools/chisel/build_replay_liq_pc_filter_activation_report.py +++ /dev/null @@ -1,311 +0,0 @@ -#!/usr/bin/env python3 -"""Build the R626 replay-LIQ PC-filter activation attempt report. - -The report deliberately separates a passing QEMU-only PC-filter preflight from -the generated-RTL attempt. The latter failed in the top harness before the -common crosscheck manifest was emitted, so it is failure evidence rather than -replay-LIQ activation proof. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import re -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_pc_filter_activation_attempt.v1" - -DEFAULT_PREFLIGHT = ( - ROOT_DIR - / "generated/r626-replay-liq-pc-filter-preflight-search-v2/report/pc_filter_preflight_search.json" -) -DEFAULT_RTL_DIR = ROOT_DIR / "generated/r626-coremark-pc-filter-4000d7e6-4000d7f2-rtl-xcheck-abs" -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r626-replay-liq-pc-filter-activation-report/report/replay_liq_pc_filter_activation_report.json" -) - -MISMATCH_RE = re.compile( - r"frontend fetch RF ALU trace top dst/wb mismatch " - r"expected_pc=(?P0x[0-9a-fA-F]+) " - r"observed_pc=(?P0x[0-9a-fA-F]+) " - r"expected_insn=(?P0x[0-9a-fA-F]+) " - r"observed_insn=(?P0x[0-9a-fA-F]+) " - r"expected=\((?P\d+),(?P\d+)\) " - r"observed_dst=\((?P\d+),(?P\d+)\) " - r"observed_wb=\((?P\d+),(?P\d+)\)" -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def load_jsonl_first(path: Path) -> dict[str, Any] | None: - if not path.exists(): - return None - with path.open("r", encoding="utf-8", errors="replace") as f: - for line in f: - if line.strip(): - data = json.loads(line) - if isinstance(data, dict): - return data - raise ValueError(f"{path} first JSONL row was not an object") - return None - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def count_rows(path: Path) -> int: - if not path.exists(): - return 0 - with path.open("r", encoding="utf-8", errors="replace") as f: - return sum(1 for line in f if line.strip()) - - -def read_text(path: Path) -> str: - if not path.exists(): - return "" - return path.read_text(encoding="utf-8", errors="replace") - - -def parse_mismatch(stderr: str) -> dict[str, Any] | None: - match = MISMATCH_RE.search(stderr) - if match is None: - return None - groups = match.groupdict() - numeric = { - key: int(value) - for key, value in groups.items() - if key - in { - "expected_rd", - "expected_value", - "observed_dst_rd", - "observed_dst_value", - "observed_wb_rd", - "observed_wb_value", - } - } - out: dict[str, Any] = {key: value for key, value in groups.items() if key not in numeric} - out.update(numeric) - return out - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - preflight = load_json(args.preflight_report) - first_pass = preflight.get("summary", {}).get("first_pass") - if not isinstance(first_pass, dict): - first_pass = None - - report_dir = args.rtl_build_dir / "report" - trace_dir = args.rtl_build_dir / "traces" - stdout_path = report_dir / "generated-rtl-attempt.stdout.txt" - stderr_path = report_dir / "generated-rtl-attempt.stderr.txt" - stderr = read_text(stderr_path) - stdout = read_text(stdout_path) - mismatch = parse_mismatch(stderr) - - manifest_path = report_dir / "crosscheck_manifest.json" - sideband_path = report_dir / "frontend_fetch_rf_alu_sideband_stats.json" - preview_path = trace_dir / "qemu.live.expected.preview.jsonl" - raw_trace_path = trace_dir / "qemu.live.raw.jsonl" - dut_trace_path = trace_dir / "dut.chisel.jsonl" - qemu_reference_path = trace_dir / "qemu.reference.jsonl" - - return { - "schema": SCHEMA, - "status": "failed", - "claim_boundary": ( - "R626 found a QEMU-only PC-filter preflight that passed exact memory-PC " - "guards, but the generated-RTL attempt failed before crosscheck manifest " - "generation. This is not replay-LIQ activation proof and must not be " - "used as natural CoreMark replacement evidence." - ), - "preflight": { - "report": str(args.preflight_report), - "status": preflight.get("status"), - "generated_rtl_status": preflight.get("generated_rtl", {}).get("status"), - "first_pass": first_pass, - }, - "generated_rtl_attempt": { - "build_dir": str(args.rtl_build_dir), - "status": "failed_before_manifest", - "stdout": str(stdout_path), - "stderr": str(stderr_path), - "manifest": { - "path": str(manifest_path), - "exists": manifest_path.exists(), - }, - "sideband": { - "path": str(sideband_path), - "exists": sideband_path.exists(), - }, - "trace_rows": { - "qemu_live_raw": count_rows(raw_trace_path), - "qemu_live_expected_preview": count_rows(preview_path), - "dut_chisel": count_rows(dut_trace_path), - "qemu_reference": count_rows(qemu_reference_path), - }, - "first_expected_preview_row": load_jsonl_first(preview_path), - "verilator_built": "V e r i l a t i o n R e p o r t" in stdout, - "mismatch": mismatch, - }, - "next_actions": [ - "Do not promote R626 as generated-RTL replay-LIQ activation proof.", - "Classify the first-row dst/wb mismatch before rerunning wider CoreMark PC filters.", - "Continue with checkpoint/state replay, a legal natural workload shard, or a PC-filter shape whose generated-RTL first row matches QEMU.", - ], - "skill_evolve": { - "decision": "no-update", - "reason": ( - "The packet adds repo-local automation and records a failed PC-filter " - "launch boundary; it does not change a reusable LinxCore " - "microarchitecture invariant or mandatory external skill rule." - ), - }, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "failed": - errors.append("report: R626 activation report must remain failed") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "not replay-LIQ activation proof" not in boundary: - errors.append("report: claim boundary must reject activation proof") - - preflight = report.get("preflight") - if not isinstance(preflight, dict): - errors.append("preflight: missing section") - preflight = {} - if preflight.get("status") != "pass": - errors.append("preflight: expected QEMU-only search pass") - if preflight.get("generated_rtl_status") != "ready": - errors.append("preflight: expected generated_rtl ready authorization") - - rtl = report.get("generated_rtl_attempt") - if not isinstance(rtl, dict): - errors.append("generated_rtl_attempt: missing section") - rtl = {} - if rtl.get("status") != "failed_before_manifest": - errors.append("generated_rtl_attempt: expected failed_before_manifest") - if rtl.get("manifest", {}).get("exists") is not False: - errors.append("generated_rtl_attempt: manifest must be absent for this failure") - if rtl.get("sideband", {}).get("exists") is not False: - errors.append("generated_rtl_attempt: sideband must be absent for this failure") - rows = rtl.get("trace_rows", {}) - if not isinstance(rows, dict): - errors.append("generated_rtl_attempt: missing trace rows") - rows = {} - if rows.get("qemu_live_raw", 0) <= 0 or rows.get("qemu_live_expected_preview", 0) <= 0: - errors.append("generated_rtl_attempt: expected QEMU raw and preview rows") - if rows.get("dut_chisel") != 0: - errors.append("generated_rtl_attempt: DUT JSONL should be empty after harness mismatch") - mismatch = rtl.get("mismatch") - if not isinstance(mismatch, dict): - errors.append("generated_rtl_attempt: missing parsed mismatch") - else: - if mismatch.get("expected_pc") != mismatch.get("observed_pc"): - errors.append("generated_rtl_attempt: expected/observed PC should match in this failure") - if mismatch.get("expected_value") == mismatch.get("observed_dst_value"): - errors.append("generated_rtl_attempt: mismatch values unexpectedly match") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "failed", - "claim_boundary": "not replay-LIQ activation proof", - "preflight": {"status": "pass", "generated_rtl_status": "ready"}, - "generated_rtl_attempt": { - "status": "failed_before_manifest", - "manifest": {"exists": False}, - "sideband": {"exists": False}, - "trace_rows": { - "qemu_live_raw": 6, - "qemu_live_expected_preview": 5, - "dut_chisel": 0, - }, - "mismatch": { - "expected_pc": "0x4000d7e6", - "observed_pc": "0x4000d7e6", - "expected_value": 1342110568, - "observed_dst_value": 18446744073709551608, - }, - }, - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["generated_rtl_attempt"]["manifest"]["exists"] = True - if not validate_report(failing): - raise AssertionError("manifest-present failure was not detected") - failing = copy.deepcopy(passing) - failing["generated_rtl_attempt"]["mismatch"]["observed_dst_value"] = 1342110568 - if not validate_report(failing): - raise AssertionError("matching dst/wb value was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--preflight-report", type=Path, default=DEFAULT_PREFLIGHT) - parser.add_argument("--rtl-build-dir", type=Path, default=DEFAULT_RTL_DIR) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-pc-filter-activation-report self-test: ok") - if args.validate_only is None: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-pc-filter-activation-report: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-pc-filter-activation-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_selector_context_pack.py b/tools/chisel/build_replay_liq_selector_context_pack.py deleted file mode 100644 index 515aca34..00000000 --- a/tools/chisel/build_replay_liq_selector_context_pack.py +++ /dev/null @@ -1,416 +0,0 @@ -#!/usr/bin/env python3 -"""Build and validate the current replay-LIQ selector context pack. - -This manifest intentionally keeps three evidence classes separate: - -* a CoreMark generated-RTL/QEMU no-regression prefix with zero natural - replay-LIQ activity, -* a focused replay fixture with positive selector-origin sideband proof, and -* a QEMU-only candidate hint that may guide future stateful CoreMark work. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import subprocess -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] - -SCHEMA = "linxcore.replay_liq_selector_context_pack.v1" -EVIDENCE_KIND = "coremark_zero_natural_plus_focused_selector_origin_plus_qemu_hint" - -COREMARK_ZERO_COUNTERS = ( - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "lret_w2_slot_accepted", - "w2_promotion_live", - "w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "mdb_lookup_wait_plan_wait_intent_valid", -) - -FOCUSED_NONZERO_COUNTERS = ( - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "lret_w2_slot_accepted", - "w2_promotion_live", - "w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate", - "w2_retire_record_physical_bundle_suppress_select_selected", - "w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "w2_retire_record_physical_bundle_suppress_boundary_capture", - "w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask", - "w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate", - "w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned", -) - -FOCUSED_ZERO_COUNTERS = ( - "w2_retire_record_physical_bundle_suppress_probe_selected", - "w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask", - "w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch", -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def git_sha(path: Path) -> str: - try: - return subprocess.check_output( - ["git", "-C", str(path), "rev-parse", "HEAD"], - text=True, - stderr=subprocess.DEVNULL, - ).strip() - except subprocess.CalledProcessError: - return "unknown" - - -def crosscheck_summary(manifest: dict[str, Any]) -> dict[str, Any]: - summary = manifest.get("summary") - return dict(summary) if isinstance(summary, dict) else {} - - -def replay_liq_sideband(sideband: dict[str, Any], keys: tuple[str, ...]) -> dict[str, int | None]: - replay = sideband.get("replay_liq") - if not isinstance(replay, dict): - return {key: None for key in keys} - out: dict[str, int | None] = {} - for key in keys: - value = replay.get(key) - out[key] = value if isinstance(value, int) else None - return out - - -def first_candidate(candidate_report: dict[str, Any]) -> dict[str, Any]: - candidates = candidate_report.get("top_candidates") - if not isinstance(candidates, list) or not candidates: - return {} - candidate = candidates[0] - return dict(candidate) if isinstance(candidate, dict) else {} - - -def build_manifest(args: argparse.Namespace) -> dict[str, Any]: - coremark_manifest = load_json(args.coremark_manifest) - coremark_sideband = load_json(args.coremark_sideband) - focused_manifest = load_json(args.focused_manifest) - focused_sideband = load_json(args.focused_sideband) - candidate_report = load_json(args.candidate_report) - candidate = first_candidate(candidate_report) - - return { - "schema": SCHEMA, - "status": "pass", - "evidence_kind": EVIDENCE_KIND, - "claim_boundary": ( - "CoreMark prefix is zero-natural-replay no-regression evidence; " - "focused replay fixture is positive selector-origin proof; " - "QEMU candidate report is an address-cluster hint only, not DUT proof." - ), - "coremark_zero_natural": { - "manifest": str(args.coremark_manifest), - "sideband_report": str(args.coremark_sideband), - "status": coremark_manifest.get("status"), - "summary": crosscheck_summary(coremark_manifest), - "required_zero_sideband": replay_liq_sideband(coremark_sideband, COREMARK_ZERO_COUNTERS), - }, - "focused_selector_origin": { - "manifest": str(args.focused_manifest), - "sideband_report": str(args.focused_sideband), - "status": focused_manifest.get("status"), - "summary": crosscheck_summary(focused_manifest), - "required_nonzero_sideband": replay_liq_sideband(focused_sideband, FOCUSED_NONZERO_COUNTERS), - "required_zero_sideband": replay_liq_sideband(focused_sideband, FOCUSED_ZERO_COUNTERS), - }, - "qemu_candidate_hint": { - "candidate_report": str(args.candidate_report), - "status": "hint", - "row_space": candidate_report.get("row_space"), - "candidate_count": candidate_report.get("candidate_count"), - "first_candidate": candidate, - }, - "git": { - "linxcore": git_sha(ROOT_DIR), - "linxcore_model": git_sha(ROOT_DIR.parent.parent / "tools/LinxCoreModel"), - "qemu": git_sha(ROOT_DIR.parent.parent / "emulator/qemu"), - "superproject": git_sha(ROOT_DIR.parent.parent), - }, - } - - -def require_passed_crosscheck(name: str, section: Any) -> list[str]: - errors: list[str] = [] - if not isinstance(section, dict): - return [f"{name}: missing section"] - if section.get("status") != "pass": - errors.append(f"{name}: status is {section.get('status')!r}, expected 'pass'") - summary = section.get("summary") - if not isinstance(summary, dict): - return errors + [f"{name}: missing summary"] - compared = summary.get("compared_rows") - mismatches = summary.get("mismatch_count") - if not isinstance(compared, int) or compared <= 0: - errors.append(f"{name}: compared_rows must be positive, got {compared!r}") - if mismatches != 0: - errors.append(f"{name}: mismatch_count must be zero, got {mismatches!r}") - return errors - - -def check_counter_map( - section_name: str, - label: str, - values: Any, - keys: tuple[str, ...], - *, - require_nonzero: bool, -) -> list[str]: - if not isinstance(values, dict): - return [f"{section_name}: missing {label}"] - errors: list[str] = [] - for key in keys: - value = values.get(key) - if not isinstance(value, int): - errors.append(f"{section_name}: {label}.{key} is not an integer") - elif require_nonzero and value <= 0: - errors.append(f"{section_name}: {label}.{key} must be nonzero, got {value}") - elif not require_nonzero and value != 0: - errors.append(f"{section_name}: {label}.{key} must be zero, got {value}") - return errors - - -def validate_manifest(manifest: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if manifest.get("schema") != SCHEMA: - errors.append("manifest: unexpected schema") - if manifest.get("status") != "pass": - errors.append(f"manifest: status is {manifest.get('status')!r}, expected 'pass'") - if manifest.get("evidence_kind") != EVIDENCE_KIND: - errors.append("manifest: unexpected evidence_kind") - boundary = manifest.get("claim_boundary") - if not isinstance(boundary, str) or "zero-natural-replay" not in boundary or "address-cluster hint" not in boundary: - errors.append("manifest: claim_boundary must preserve evidence separation") - - coremark = manifest.get("coremark_zero_natural") - focused = manifest.get("focused_selector_origin") - candidate = manifest.get("qemu_candidate_hint") - errors.extend(require_passed_crosscheck("coremark_zero_natural", coremark)) - errors.extend(require_passed_crosscheck("focused_selector_origin", focused)) - - if isinstance(coremark, dict): - errors.extend( - check_counter_map( - "coremark_zero_natural", - "required_zero_sideband", - coremark.get("required_zero_sideband"), - COREMARK_ZERO_COUNTERS, - require_nonzero=False, - ) - ) - if isinstance(focused, dict): - errors.extend( - check_counter_map( - "focused_selector_origin", - "required_nonzero_sideband", - focused.get("required_nonzero_sideband"), - FOCUSED_NONZERO_COUNTERS, - require_nonzero=True, - ) - ) - errors.extend( - check_counter_map( - "focused_selector_origin", - "required_zero_sideband", - focused.get("required_zero_sideband"), - FOCUSED_ZERO_COUNTERS, - require_nonzero=False, - ) - ) - - if not isinstance(candidate, dict): - errors.append("qemu_candidate_hint: missing section") - else: - if candidate.get("status") != "hint": - errors.append("qemu_candidate_hint: status must be 'hint'") - count = candidate.get("candidate_count") - if not isinstance(count, int) or count <= 0: - errors.append(f"qemu_candidate_hint: candidate_count must be positive, got {count!r}") - first = candidate.get("first_candidate") - if not isinstance(first, dict) or not first: - errors.append("qemu_candidate_hint: missing first_candidate") - else: - hint = first.get("probe_hint") - raw_window = hint.get("raw_dynamic_window") if isinstance(hint, dict) else None - expected_pcs = hint.get("expected_memory_pcs") if isinstance(hint, dict) else None - if not isinstance(raw_window, dict): - errors.append("qemu_candidate_hint: missing probe_hint.raw_dynamic_window") - else: - skip = raw_window.get("qemu_skip_rows") - capture = raw_window.get("capture_rows") - if not isinstance(skip, int) or skip < 0: - errors.append(f"qemu_candidate_hint: qemu_skip_rows must be non-negative, got {skip!r}") - if not isinstance(capture, int) or capture <= 0: - errors.append(f"qemu_candidate_hint: capture_rows must be positive, got {capture!r}") - if not isinstance(expected_pcs, dict) or not expected_pcs.get("store_pcs") or not expected_pcs.get("load_pcs"): - errors.append("qemu_candidate_hint: expected memory PC lists must be present") - return errors - - -def sample_manifest() -> dict[str, Any]: - coremark_zero = {key: 0 for key in COREMARK_ZERO_COUNTERS} - focused_nonzero = {key: 1 for key in FOCUSED_NONZERO_COUNTERS} - focused_zero = {key: 0 for key in FOCUSED_ZERO_COUNTERS} - return { - "schema": SCHEMA, - "status": "pass", - "evidence_kind": EVIDENCE_KIND, - "claim_boundary": ( - "CoreMark prefix is zero-natural-replay no-regression evidence; " - "focused replay fixture is positive selector-origin proof; " - "QEMU candidate report is an address-cluster hint only, not DUT proof." - ), - "coremark_zero_natural": { - "status": "pass", - "summary": {"compared_rows": 4, "mismatch_count": 0}, - "required_zero_sideband": coremark_zero, - }, - "focused_selector_origin": { - "status": "pass", - "summary": {"compared_rows": 4, "mismatch_count": 0}, - "required_nonzero_sideband": focused_nonzero, - "required_zero_sideband": focused_zero, - }, - "qemu_candidate_hint": { - "status": "hint", - "candidate_count": 1, - "first_candidate": { - "probe_hint": { - "raw_dynamic_window": {"qemu_skip_rows": 1, "capture_rows": 2}, - "expected_memory_pcs": {"store_pcs": ["0x10"], "load_pcs": ["0x14"]}, - } - }, - }, - } - - -def run_self_test() -> None: - passing = sample_manifest() - if validate_manifest(passing): - raise AssertionError("valid sample manifest failed validation") - failing = copy.deepcopy(passing) - failing["coremark_zero_natural"]["required_zero_sideband"]["liq_alloc_accepted"] = 1 - if not validate_manifest(failing): - raise AssertionError("CoreMark nonzero violation was not detected") - failing = copy.deepcopy(passing) - failing["focused_selector_origin"]["required_nonzero_sideband"]["w2_promotion_live"] = 0 - if not validate_manifest(failing): - raise AssertionError("focused nonzero violation was not detected") - failing = copy.deepcopy(passing) - del failing["qemu_candidate_hint"]["first_candidate"]["probe_hint"]["raw_dynamic_window"] - if not validate_manifest(failing): - raise AssertionError("missing raw candidate hint was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument( - "--coremark-manifest", - type=Path, - default=ROOT_DIR / "generated/r611-coremark-promoted-selector-observation-4096-xcheck/report/crosscheck_manifest.json", - help="CoreMark no-regression crosscheck manifest", - ) - parser.add_argument( - "--coremark-sideband", - type=Path, - default=ROOT_DIR / "generated/r611-coremark-promoted-selector-observation-4096-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json", - help="CoreMark no-regression sideband stats", - ) - parser.add_argument( - "--focused-manifest", - type=Path, - default=ROOT_DIR / "generated/r616-replay-suppress-preset-xcheck/report/crosscheck_manifest.json", - help="focused selector-origin crosscheck manifest", - ) - parser.add_argument( - "--focused-sideband", - type=Path, - default=ROOT_DIR / "generated/r616-replay-suppress-preset-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json", - help="focused selector-origin sideband stats", - ) - parser.add_argument( - "--candidate-report", - type=Path, - default=ROOT_DIR / "generated/r617-coremark-qemu-memory-candidate-hints/replay_liq_qemu_candidates_with_raw_hints.json", - help="QEMU candidate report with raw-window hints", - ) - parser.add_argument( - "--output", - type=Path, - default=ROOT_DIR / "generated/r618-replay-liq-selector-context-pack/report/replay_liq_selector_context_pack.json", - help="output manifest path", - ) - parser.add_argument("--validate-only", type=Path, default=None, help="validate an existing context-pack manifest") - parser.add_argument("--self-test", action="store_true", help="run built-in validator checks") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-selector-context-pack self-test: ok") - if args.validate_only is None and not any( - flag in argv - for flag in ( - "--coremark-manifest", - "--coremark-sideband", - "--focused-manifest", - "--focused-sideband", - "--candidate-report", - "--output", - ) - ): - return 0 - - if args.validate_only is not None: - manifest = load_json(args.validate_only) - errors = validate_manifest(manifest) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-selector-context-pack: ok manifest={args.validate_only}") - return 0 - - manifest = build_manifest(args) - errors = validate_manifest(manifest) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, manifest) - print(f"replay-liq-selector-context-pack-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_selector_preflight_report.py b/tools/chisel/build_replay_liq_selector_preflight_report.py deleted file mode 100644 index ad135ad8..00000000 --- a/tools/chisel/build_replay_liq_selector_preflight_report.py +++ /dev/null @@ -1,265 +0,0 @@ -#!/usr/bin/env python3 -"""Build a replay-LIQ selector preflight report. - -This report records QEMU-only preflight results for the current CoreMark -candidate. It treats raw skipped windows as locator evidence and keeps -generated RTL blocked unless a non-skipped command shape is proven separately. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - -from build_replay_liq_selector_context_pack import validate_manifest as validate_context_pack - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_selector_preflight_report.v1" - -DEFAULT_CONTEXT_PACK = ( - ROOT_DIR - / "generated/r618-replay-liq-selector-context-pack/report/replay_liq_selector_context_pack.json" -) -DEFAULT_RAW_PREVIEW = ( - ROOT_DIR - / "generated/r620-coremark-candidate-raw1715-qemu-preflight/traces/qemu.live.expected.preview.jsonl" -) -DEFAULT_RAW_TRACE = ( - ROOT_DIR - / "generated/r620-coremark-candidate-raw1715-qemu-preflight/traces/qemu.live.raw.jsonl" -) -DEFAULT_PC_FILTER_TRACE = ( - ROOT_DIR - / "generated/r620-coremark-candidate-pc-filter-qemu-preflight/traces/qemu.live.raw.jsonl" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r620-replay-liq-selector-preflight-report/report/replay_liq_selector_preflight_report.json" -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def read_jsonl(path: Path) -> list[dict[str, Any]]: - if not path.exists(): - return [] - rows: list[dict[str, Any]] = [] - with path.open("r", encoding="utf-8", errors="replace") as f: - for line in f: - text = line.strip() - if not text: - continue - row = json.loads(text) - if not isinstance(row, dict): - raise ValueError(f"{path} contains a non-object JSONL row") - rows.append(row) - return rows - - -def memory_pcs(rows: list[dict[str, Any]]) -> dict[str, list[str]]: - stores: list[str] = [] - loads: list[str] = [] - for row in rows: - if row.get("mem_valid") != 1: - continue - pc = row.get("pc") - if not isinstance(pc, int): - continue - if row.get("mem_is_store") == 1: - stores.append(hex(pc)) - else: - loads.append(hex(pc)) - return {"store_pcs": stores, "load_pcs": loads} - - -def candidate_hint(context_pack: dict[str, Any]) -> dict[str, Any]: - section = context_pack.get("qemu_candidate_hint") - first = section.get("first_candidate") if isinstance(section, dict) else None - hint = first.get("probe_hint") if isinstance(first, dict) else None - if not isinstance(hint, dict): - raise ValueError("context pack does not contain qemu_candidate_hint.first_candidate.probe_hint") - return hint - - -def expected_pcs(context_pack: dict[str, Any]) -> dict[str, list[str]]: - expected = candidate_hint(context_pack).get("expected_memory_pcs") - if not isinstance(expected, dict): - raise ValueError("candidate hint does not contain expected_memory_pcs") - stores = expected.get("store_pcs") - loads = expected.get("load_pcs") - if not isinstance(stores, list) or not isinstance(loads, list): - raise ValueError("expected store/load PC lists must be present") - return { - "store_pcs": [str(item) for item in stores], - "load_pcs": [str(item) for item in loads], - } - - -def first_mem_addr(rows: list[dict[str, Any]]) -> str | None: - for row in rows: - if row.get("mem_valid") == 1 and isinstance(row.get("mem_addr"), int): - return hex(row["mem_addr"]) - return None - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - context_pack = load_json(args.context_pack) - context_errors = validate_context_pack(context_pack) - if context_errors: - raise ValueError("invalid context pack: " + "; ".join(context_errors)) - - expected = expected_pcs(context_pack) - raw_rows = read_jsonl(args.raw_trace) - raw_preview_rows = read_jsonl(args.raw_preview) - pc_filter_rows = read_jsonl(args.pc_filter_trace) - raw_preview_pcs = memory_pcs(raw_preview_rows) - pc_filter_pcs = memory_pcs(pc_filter_rows) - raw_pass = raw_preview_pcs == expected - pc_filter_status = "empty" if not pc_filter_rows else ("pass" if pc_filter_pcs == expected else "expected_pc_mismatch") - - return { - "schema": SCHEMA, - "status": "pass" if raw_pass else "fail", - "claim_boundary": ( - "Raw-window QEMU-only preflight can confirm the address-cluster candidate. " - "It cannot authorize generated RTL because skipped rows cannot reconstruct DUT state. " - "PC-filter preflight must pass expected memory PCs before a PC-filtered generated-RTL run is considered." - ), - "expected_memory_pcs": expected, - "raw_window_qemu_only": { - "status": "pass" if raw_pass else "fail", - "raw_trace": str(args.raw_trace), - "preview": str(args.raw_preview), - "raw_rows": len(raw_rows), - "preview_rows": len(raw_preview_rows), - "memory_pcs": raw_preview_pcs, - "first_memory_address": first_mem_addr(raw_preview_rows), - }, - "pc_filter_qemu_only": { - "status": pc_filter_status, - "raw_trace": str(args.pc_filter_trace), - "raw_rows": len(pc_filter_rows), - "memory_pcs": pc_filter_pcs, - }, - "generated_rtl": { - "status": "blocked", - "reason": ( - "Raw-window preflight uses --qemu-skip-rows, which is QEMU-only. " - f"PC-filter preflight status is {pc_filter_status!r}, not a passing expected-memory-PC preflight." - ), - }, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append("report: status must be 'pass'") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "cannot authorize generated RTL" not in boundary: - errors.append("report: claim_boundary must preserve generated-RTL block") - raw = report.get("raw_window_qemu_only") - if not isinstance(raw, dict) or raw.get("status") != "pass": - errors.append("raw_window_qemu_only: expected pass") - else: - if raw.get("raw_rows") != 6: - errors.append(f"raw_window_qemu_only: raw_rows expected 6, got {raw.get('raw_rows')!r}") - if raw.get("preview_rows") != 5: - errors.append(f"raw_window_qemu_only: preview_rows expected 5, got {raw.get('preview_rows')!r}") - pc_filter = report.get("pc_filter_qemu_only") - if not isinstance(pc_filter, dict): - errors.append("pc_filter_qemu_only: missing section") - elif pc_filter.get("status") not in {"empty", "expected_pc_mismatch", "pass"}: - errors.append("pc_filter_qemu_only: unexpected status") - generated = report.get("generated_rtl") - if not isinstance(generated, dict) or generated.get("status") != "blocked": - errors.append("generated_rtl: must remain blocked") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "Raw-window QEMU-only cannot authorize generated RTL.", - "raw_window_qemu_only": {"status": "pass", "raw_rows": 6, "preview_rows": 5}, - "pc_filter_qemu_only": {"status": "empty"}, - "generated_rtl": {"status": "blocked"}, - } - - -def run_self_test() -> None: - passing = sample_report() - if validate_report(passing): - raise AssertionError("valid sample report failed validation") - failing = copy.deepcopy(passing) - failing["generated_rtl"]["status"] = "ready" - if not validate_report(failing): - raise AssertionError("unblocked generated RTL was not detected") - failing = copy.deepcopy(passing) - failing["raw_window_qemu_only"]["raw_rows"] = 0 - if not validate_report(failing): - raise AssertionError("raw-window row-count violation was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--context-pack", type=Path, default=DEFAULT_CONTEXT_PACK) - parser.add_argument("--raw-preview", type=Path, default=DEFAULT_RAW_PREVIEW) - parser.add_argument("--raw-trace", type=Path, default=DEFAULT_RAW_TRACE) - parser.add_argument("--pc-filter-trace", type=Path, default=DEFAULT_PC_FILTER_TRACE) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-selector-preflight-report self-test: ok") - if args.validate_only is None and "--context-pack" not in argv and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-selector-preflight-report: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-selector-preflight-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/build_replay_liq_selector_unskipped_prefix_report.py b/tools/chisel/build_replay_liq_selector_unskipped_prefix_report.py deleted file mode 100644 index 28c35fcb..00000000 --- a/tools/chisel/build_replay_liq_selector_unskipped_prefix_report.py +++ /dev/null @@ -1,408 +0,0 @@ -#!/usr/bin/env python3 -"""Build a replay-LIQ selector unskipped-prefix report. - -R621 proves that the R617 CoreMark candidate can be reached without skipped -QEMU rows and that the matching generated-RTL/QEMU reduced prefix still passes. -It does not prove natural replay-LIQ replacement activity unless the replay-LIQ -and MDB sideband counters become positive. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_selector_unskipped_prefix_report.v1" - -TARGET_STORE_PC = 0x4000D7E6 -TARGET_LOAD_PC = 0x4000D7F2 -TARGET_ADDR = 0x4FFEFB68 -TARGET_SIZE = 8 - -DEFAULT_QEMU_ONLY_PREVIEW = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-qemu-preflight/traces/qemu.live.expected.preview.jsonl" -) -DEFAULT_QEMU_ONLY_RAW = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-qemu-preflight/traces/qemu.live.raw.jsonl" -) -DEFAULT_QEMU_ONLY_CANDIDATES = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-qemu-preflight/report/replay_liq_qemu_candidates.json" -) -DEFAULT_RTL_MANIFEST = ( - ROOT_DIR / "generated/r621-coremark-unskipped-1721-rtl-xcheck/report/crosscheck_manifest.json" -) -DEFAULT_RTL_SIDEBAND = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-rtl-xcheck/report/frontend_fetch_rf_alu_sideband_stats.json" -) -DEFAULT_RTL_PREVIEW = ( - ROOT_DIR - / "generated/r621-coremark-unskipped-1721-rtl-xcheck/traces/qemu.live.expected.preview.jsonl" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r621-replay-liq-selector-unskipped-prefix-report/report/replay_liq_selector_unskipped_prefix_report.json" -) - -ZERO_NATURAL_COUNTERS = ( - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "lret_w2_slot_accepted", - "w2_promotion_live", - "w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "mdb_fanout_record_accepted", - "mdb_lookup_wait_plan_wait_intent_valid", - "resolve_queue_push_accepted", -) - -ACTIVITY_CONTEXT_COUNTERS = ( - "load_lookup_valid", - "load_lookup_execute_with_eligible_store", - "load_lookup_execute_with_wait_store", - "mdb_conflict_store_valid", - "store_sta_dequeue_fire", - "store_std_dequeue_fire", - "store_stq_resident", -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def read_jsonl(path: Path) -> list[dict[str, Any]]: - rows: list[dict[str, Any]] = [] - with path.open("r", encoding="utf-8", errors="replace") as f: - for line in f: - text = line.strip() - if not text: - continue - row = json.loads(text) - if not isinstance(row, dict): - raise ValueError(f"{path} contains a non-object JSONL row") - rows.append(row) - return rows - - -def hx(value: int) -> str: - return hex(value) - - -def memory_events(rows: list[dict[str, Any]]) -> list[dict[str, Any]]: - events: list[dict[str, Any]] = [] - for index, row in enumerate(rows): - if row.get("mem_valid") != 1: - continue - pc = row.get("pc") - addr = row.get("mem_addr") - size = row.get("mem_size") - if not isinstance(pc, int) or not isinstance(addr, int) or not isinstance(size, int): - continue - events.append( - { - "row": index, - "pc": hx(pc), - "addr": hx(addr), - "size": size, - "op": "store" if row.get("mem_is_store") == 1 else "load", - } - ) - return events - - -def target_pair(rows: list[dict[str, Any]]) -> dict[str, Any]: - store: dict[str, Any] | None = None - load: dict[str, Any] | None = None - for event in memory_events(rows): - if ( - event["op"] == "store" - and event["pc"] == hx(TARGET_STORE_PC) - and event["addr"] == hx(TARGET_ADDR) - and event["size"] == TARGET_SIZE - ): - store = event - if ( - event["op"] == "load" - and event["pc"] == hx(TARGET_LOAD_PC) - and event["addr"] == hx(TARGET_ADDR) - and event["size"] == TARGET_SIZE - ): - load = event - present = store is not None and load is not None - return { - "present": present, - "store": store, - "load": load, - "row_distance": (load["row"] - store["row"]) if present else None, - } - - -def first_candidate(candidate_report: dict[str, Any]) -> dict[str, Any]: - candidates = candidate_report.get("top_candidates") - if not isinstance(candidates, list) or not candidates: - return {} - candidate = candidates[0] - return dict(candidate) if isinstance(candidate, dict) else {} - - -def sideband_counters(sideband: dict[str, Any], keys: tuple[str, ...]) -> dict[str, int | None]: - replay = sideband.get("replay_liq") - if not isinstance(replay, dict): - return {key: None for key in keys} - out: dict[str, int | None] = {} - for key in keys: - value = replay.get(key) - out[key] = value if isinstance(value, int) else None - return out - - -def manifest_summary(manifest: dict[str, Any]) -> dict[str, Any]: - summary = manifest.get("summary") - return dict(summary) if isinstance(summary, dict) else {} - - -def cbstop_clean(summary: dict[str, Any]) -> bool: - counts = summary.get("cbstop_counts") - return isinstance(counts, dict) and counts.get("qemu") == 0 and counts.get("dut") == 0 - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - qemu_only_raw = read_jsonl(args.qemu_only_raw) - qemu_only_preview = read_jsonl(args.qemu_only_preview) - qemu_only_candidates = load_json(args.qemu_only_candidates) - rtl_manifest = load_json(args.rtl_manifest) - rtl_sideband = load_json(args.rtl_sideband) - rtl_preview = read_jsonl(args.rtl_preview) - - qemu_pair = target_pair(qemu_only_preview) - rtl_pair = target_pair(rtl_preview) - summary = manifest_summary(rtl_manifest) - zero_counters = sideband_counters(rtl_sideband, ZERO_NATURAL_COUNTERS) - context_counters = sideband_counters(rtl_sideband, ACTIVITY_CONTEXT_COUNTERS) - zero_natural = all(isinstance(value, int) and value == 0 for value in zero_counters.values()) - candidate = first_candidate(qemu_only_candidates) - - generated_rtl_status = "pass_no_regression_with_candidate_present" - proof_kind = ( - "no_regression_with_candidate_present_not_replay_proof" - if zero_natural - else "candidate_present_with_replay_sideband_activity" - ) - - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "The unskipped CoreMark prefix reaches the R617 store/load candidate and the " - "matching generated RTL/QEMU reduced prefix passes. Because replay-LIQ, " - "selector, and MDB fanout counters remain zero, this is no-regression " - "coverage with a candidate present, not natural replay-LIQ replacement proof." - ), - "target": { - "store_pc": hx(TARGET_STORE_PC), - "load_pc": hx(TARGET_LOAD_PC), - "address": hx(TARGET_ADDR), - "size": TARGET_SIZE, - }, - "qemu_only_unskipped_prefix": { - "status": "pass" if qemu_pair["present"] else "fail", - "raw_trace": str(args.qemu_only_raw), - "preview": str(args.qemu_only_preview), - "candidate_report": str(args.qemu_only_candidates), - "raw_rows": len(qemu_only_raw), - "preview_rows": len(qemu_only_preview), - "target_pair": qemu_pair, - "candidate_count": qemu_only_candidates.get("candidate_count"), - "first_candidate": candidate, - }, - "generated_rtl_unskipped_prefix": { - "status": generated_rtl_status, - "proof_kind": proof_kind, - "manifest": str(args.rtl_manifest), - "sideband_report": str(args.rtl_sideband), - "preview": str(args.rtl_preview), - "manifest_status": rtl_manifest.get("status"), - "summary": summary, - "target_pair": rtl_pair, - "replay_liq_activity": "zero-natural-replay" if zero_natural else "nonzero-replay-liq-or-mdb", - "required_zero_sideband": zero_counters, - "activity_context_sideband": context_counters, - }, - } - - -def require_passed_manifest(section: dict[str, Any], errors: list[str]) -> None: - if section.get("manifest_status") != "pass": - errors.append(f"generated_rtl_unskipped_prefix: manifest_status is {section.get('manifest_status')!r}") - summary = section.get("summary") - if not isinstance(summary, dict): - errors.append("generated_rtl_unskipped_prefix: missing summary") - return - compared = summary.get("compared_rows") - mismatches = summary.get("mismatch_count") - if not isinstance(compared, int) or compared <= 0: - errors.append(f"generated_rtl_unskipped_prefix: compared_rows must be positive, got {compared!r}") - if mismatches != 0: - errors.append(f"generated_rtl_unskipped_prefix: mismatch_count must be zero, got {mismatches!r}") - if not cbstop_clean(summary): - errors.append("generated_rtl_unskipped_prefix: QEMU/DUT CBSTOP counts must be zero") - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append(f"report: status is {report.get('status')!r}, expected 'pass'") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "not natural replay-LIQ replacement proof" not in boundary: - errors.append("report: claim_boundary must preserve the no-replay-proof boundary") - - qemu = report.get("qemu_only_unskipped_prefix") - if not isinstance(qemu, dict): - errors.append("qemu_only_unskipped_prefix: missing section") - else: - if qemu.get("status") != "pass": - errors.append("qemu_only_unskipped_prefix: expected pass") - if qemu.get("raw_rows") != 1721: - errors.append(f"qemu_only_unskipped_prefix: raw_rows expected 1721, got {qemu.get('raw_rows')!r}") - pair = qemu.get("target_pair") - if not isinstance(pair, dict) or not pair.get("present"): - errors.append("qemu_only_unskipped_prefix: target pair must be present") - first = qemu.get("first_candidate") - if not isinstance(first, dict) or first.get("score") != 1186: - errors.append("qemu_only_unskipped_prefix: first candidate must be the R617 target") - - rtl = report.get("generated_rtl_unskipped_prefix") - if not isinstance(rtl, dict): - errors.append("generated_rtl_unskipped_prefix: missing section") - else: - if rtl.get("status") != "pass_no_regression_with_candidate_present": - errors.append("generated_rtl_unskipped_prefix: unexpected status") - if rtl.get("proof_kind") != "no_regression_with_candidate_present_not_replay_proof": - errors.append("generated_rtl_unskipped_prefix: proof kind must remain no-regression only") - require_passed_manifest(rtl, errors) - pair = rtl.get("target_pair") - if not isinstance(pair, dict) or not pair.get("present"): - errors.append("generated_rtl_unskipped_prefix: target pair must be present in preview") - counters = rtl.get("required_zero_sideband") - if not isinstance(counters, dict): - errors.append("generated_rtl_unskipped_prefix: missing required_zero_sideband") - else: - for key in ZERO_NATURAL_COUNTERS: - value = counters.get(key) - if not isinstance(value, int): - errors.append(f"generated_rtl_unskipped_prefix: {key} is not an integer") - elif value != 0: - errors.append(f"generated_rtl_unskipped_prefix: {key} must be zero, got {value}") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "candidate present, not natural replay-LIQ replacement proof", - "qemu_only_unskipped_prefix": { - "status": "pass", - "raw_rows": 1721, - "target_pair": {"present": True}, - "first_candidate": {"score": 1186}, - }, - "generated_rtl_unskipped_prefix": { - "status": "pass_no_regression_with_candidate_present", - "proof_kind": "no_regression_with_candidate_present_not_replay_proof", - "manifest_status": "pass", - "summary": {"compared_rows": 1169, "mismatch_count": 0, "cbstop_counts": {"qemu": 0, "dut": 0}}, - "target_pair": {"present": True}, - "required_zero_sideband": {key: 0 for key in ZERO_NATURAL_COUNTERS}, - }, - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["generated_rtl_unskipped_prefix"]["summary"]["mismatch_count"] = 1 - if not validate_report(failing): - raise AssertionError("mismatch violation was not detected") - failing = copy.deepcopy(passing) - failing["generated_rtl_unskipped_prefix"]["required_zero_sideband"]["liq_alloc_accepted"] = 1 - if not validate_report(failing): - raise AssertionError("nonzero replay-LIQ counter was not detected") - failing = copy.deepcopy(passing) - failing["qemu_only_unskipped_prefix"]["target_pair"]["present"] = False - if not validate_report(failing): - raise AssertionError("missing QEMU target pair was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--qemu-only-preview", type=Path, default=DEFAULT_QEMU_ONLY_PREVIEW) - parser.add_argument("--qemu-only-raw", type=Path, default=DEFAULT_QEMU_ONLY_RAW) - parser.add_argument("--qemu-only-candidates", type=Path, default=DEFAULT_QEMU_ONLY_CANDIDATES) - parser.add_argument("--rtl-manifest", type=Path, default=DEFAULT_RTL_MANIFEST) - parser.add_argument("--rtl-sideband", type=Path, default=DEFAULT_RTL_SIDEBAND) - parser.add_argument("--rtl-preview", type=Path, default=DEFAULT_RTL_PREVIEW) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-selector-unskipped-prefix-report self-test: ok") - if args.validate_only is None and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-selector-unskipped-prefix-report: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-selector-unskipped-prefix-report={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/check_crosscheck_wrapper_dependencies.py b/tools/chisel/check_crosscheck_wrapper_dependencies.py new file mode 100644 index 00000000..ce059704 --- /dev/null +++ b/tools/chisel/check_crosscheck_wrapper_dependencies.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +"""Check that current cross-check wrappers bind the one callable TOP.""" + +from __future__ import annotations + +import re +import sys +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[2] +RUNNER = ROOT / "tools/chisel/run_top_natural.sh" +EMITTER = ROOT / "chisel/src/main/scala/linxcore/top/EmitTOP.scala" +TOP = ROOT / "chisel/src/main/scala/linxcore/top/TOP.scala" +OLD_TOP = re.compile(r"LinxCore[A-Za-z0-9_]*Top") + + +def errors() -> list[str]: + result: list[str] = [] + required = { + RUNNER: ("linxcore.top.EmitTOP", "TOP", "top_natural_tb.cpp"), + EMITTER: ("object EmitTOP", "new TOP"), + TOP: ("class TOP", "new IFU", "new CTU", "new OOO", "new IEX", "new LSU", "new DTU"), + } + for path, tokens in required.items(): + if not path.is_file(): + result.append(f"missing canonical file: {path.relative_to(ROOT)}") + continue + source = path.read_text(encoding="utf-8") + for token in tokens: + if token not in source: + result.append(f"{path.relative_to(ROOT)} lacks {token}") + for root in (ROOT / "chisel/src/main/scala", ROOT / "tools/chisel", ROOT / "tests"): + for path in root.rglob("*"): + if not path.is_file() or path.suffix not in {".scala", ".sh", ".cpp", ".py"}: + continue + if path == Path(__file__): + continue + match = OLD_TOP.search(path.read_text(encoding="utf-8", errors="replace")) + if match: + result.append(f"legacy callable top reference {match.group(0)} in {path.relative_to(ROOT)}") + return result + + +def main() -> int: + failures = errors() + if failures: + for failure in failures: + print(f"crosscheck-wrapper: ERROR: {failure}", file=sys.stderr) + return 1 + print("canonical-emitter=linxcore.top.EmitTOP") + print("canonical-top=TOP") + print("canonical-runner=tools/chisel/run_top_natural.sh") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/chisel/check_deleted_ooo_doc_references.py b/tools/chisel/check_deleted_ooo_doc_references.py new file mode 100644 index 00000000..62c0b878 --- /dev/null +++ b/tools/chisel/check_deleted_ooo_doc_references.py @@ -0,0 +1,163 @@ +#!/usr/bin/env python3 +"""Reject live documentation references to deleted Task 11 OOO surfaces.""" + +from __future__ import annotations + +import argparse +import re +import sys +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[2] +# Exact deleted Scala basenames from 5f80ea0b..1375436f. Keep owners and +# suites separate because only test-runner command lines may omit `Spec`. +DELETED_TASK11_OWNERS = ( + "OooBrob", + "OooCtuIngressBridge", + "OooFrontendRecoveryBridge", + "OooIfuD1Ingress", + "OooIfuRawIngress", + "OooO3IexStorePipeline", + "OooO3RenameCoordinator", + "OooPRename", + "OooRobBrobPcCoordinator", + "OooRobStoreCommitOwner", + "OooS1GroupedRob", + "OooTURename", +) +DELETED_TASK11_SUITES = ( + "OooBrobSpec", + "OooCtuIngressBridgeSpec", + "OooD3ReservationAllocatorSpec", + "OooD3S1BrobIntegrationSpec", + "OooD3S1GroupedRobIntegrationSpec", + "OooDispatchSpec", + "OooFrontendCtuRecoveryIntegrationSpec", + "OooFrontendIfuRecoveryIntegrationSpec", + "OooFrontendRecoveryBridgeSpec", + "OooIfuD1IngressSpec", + "OooIfuRawIngressSpec", + "OooO3FastResolveIntegrationSpec", + "OooO3IexIntegrationSpec", + "OooO3IexStorePipelineSpec", + "OooO3RenameCoordinatorSpec", + "OooO3RenameRandomizedSpec", + "OooPRenameSpec", + "OooRobBrobPcCoordinatorSpec", + "OooRobStoreCommitOwnerSpec", + "OooRobStoreCommitStqIntegrationSpec", + "OooS1GroupedRobFaultSpec", + "OooS1GroupedRobSpec", + "OooTURenameSpec", +) +DELETED_TASK11_RUNNERS = tuple( + suite.removesuffix("Spec") for suite in DELETED_TASK11_SUITES +) +HISTORICAL_SECTION_ALLOWLIST = { + ( + "agent-loop.md", + "## Suggested Next Packets", + ), + ( + "mainline-loop-ledger.md", + "## Loop 9 — Canonical ROB, BROB, commit, and precise recovery authority", + ), + ( + "chisel/agent-loop.md", + "## Suggested Next Packets", + ), + ( + "chisel/mainline-loop-ledger.md", + "## Loop 9 — Canonical ROB, BROB, commit, and precise recovery authority", + ), + ( + "superpowers/plans/2026-07-31-core-mainline-restructure.md", + "### Task 8: Build RENU with separate P and T/U rename machines", + ), + ( + "superpowers/plans/2026-07-31-core-mainline-restructure.md", + "### Task 11: Atomically cut canonical OOO onto production D3/S1 mechanisms", + ), + ( + "superpowers/plans/2026-07-31-scalar-load-structural-block-policy.md", + "### Task 3: Install policy behind the OOO/IEX production boundary", + ), + ( + "superpowers/plans/2026-07-31-scalar-load-structural-block-policy.md", + "### Task 4: Documentation, full gates, push, and superproject pin", + ), + ( + "superpowers/specs/2026-08-01-production-owner-atomic-cutover-design.md", + "### 2.1 Preserve Tasks 1-9", + ), +} + + +def contains_identifier(line: str, identifier: str) -> bool: + return re.search( + rf"(? argparse.Namespace: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument( + "--doc-root", + type=Path, + help="documentation tree to scan (defaults to /docs)", + ) + parser.add_argument( + "--repo-root", + type=Path, + default=ROOT, + help="repository root used by the default documentation scan", + ) + return parser.parse_args() + + +def find_stale_references(doc_root: Path) -> list[str]: + stale: list[str] = [] + for path in sorted(doc_root.rglob("*.md")): + relative = path.relative_to(doc_root) + section = "" + for line_number, line in enumerate( + path.read_text(encoding="utf-8").splitlines(), 1 + ): + if line.startswith("#"): + section = line.strip() + if (relative.as_posix(), section) in HISTORICAL_SECTION_ALLOWLIST: + continue + matches = { + reference + for reference in (*DELETED_TASK11_OWNERS, *DELETED_TASK11_SUITES) + if contains_identifier(line, reference) + } + if "--only" in line: + matches.update( + reference + for reference in DELETED_TASK11_RUNNERS + if contains_identifier(line, reference) + ) + stale.extend( + f"{relative}:{line_number}: [{reference}] {line.strip()}" + for reference in sorted(matches) + ) + return stale + + +def main() -> int: + args = parse_args() + doc_root = args.doc_root or args.repo_root / "docs" + stale = find_stale_references(doc_root.resolve()) + if stale: + for item in stale: + print(f"deleted-ooo-doc-reference: ERROR: {item}") + return 1 + print("deleted-ooo-doc-reference: no live deleted Task 11 references") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/chisel/check_production_owner_manifest.py b/tools/chisel/check_production_owner_manifest.py new file mode 100644 index 00000000..b9cc94d1 --- /dev/null +++ b/tools/chisel/check_production_owner_manifest.py @@ -0,0 +1,1688 @@ +#!/usr/bin/env python3 +"""Validate the canonical LinxCore production-owner cutover manifest.""" + +from __future__ import annotations + +import argparse +import json +import re +import sys +from collections import Counter +from dataclasses import dataclass +from pathlib import Path +from typing import Any + + +ROOT = Path(__file__).resolve().parents[2] +DEFAULT_MANIFEST = ROOT / "docs/chisel/production-owner-manifest.md" +MANIFEST_BLOCK = re.compile( + r"```json\s+production-owner-manifest\s*\n(?P.*?)\n```", + re.DOTALL, +) +APP_ENTRY = re.compile(r"\bobject\s+(?P[A-Za-z_]\w*)\s+extends\s+App\b") +OBJECT_DECLARATION = re.compile(r"\bobject\s+(?P[A-Za-z_]\w*)\b") +DEF_MAIN = re.compile(r"\bdef\s+main\s*\(") +AT_MAIN_ENTRY = re.compile(r"@main\s+def\s+(?P[A-Za-z_]\w*)\s*\(") +ANY_DEFINITION = re.compile( + r"(?m)^[ \t]*(?:private(?:\[[^\]]+\])?[ \t]+)?(?:final[ \t]+)?" + r"(?Pclass|object)\s+(?P[A-Za-z_]\w*)\b" +) +INSTANTIATION = re.compile( + r"\bnew\s+(?P[A-Za-z_]\w*(?:\s*\.\s*[A-Za-z_]\w*)*)\b" +) +MODULE_INSTANTIATION = re.compile( + r"\bModule\s*\(\s*new\s+" + r"(?P[A-Za-z_]\w*(?:\s*\.\s*[A-Za-z_]\w*)*)\b" +) +PACKAGE_DECLARATION = re.compile(r"(?m)^[ \t]*package[ \t]+(?P[A-Za-z_]\w*(?:\.[A-Za-z_]\w*)*)") +STATE_TOKEN = re.compile( + r"\b(?:Reg|RegInit|RegNext|RegEnable|Mem|SyncReadMem)\s*\(|\bQueue\s*\(" +) +SYMBOL_DEFINITION = ( + r"(?m)^[ \t]*(?:private(?:\[[^\]]+\])?[ \t]+)?(?:final[ \t]+)?" + r"(?:class|object)\s+{symbol}\b" +) +REQUIRED_SUBSYSTEMS = {"IFU", "CTU", "OOO", "IEX", "LSU", "DTU"} +EVIDENCE_STATUSES = { + "public-box-verified", + "standalone-verified", + "mechanism-verified-cutover-pending", + "production-promoted", +} +PUBLIC_INTERFACES = { + box: f"chisel/src/main/scala/linxcore/top/interface/{box}IO.scala" + for box in REQUIRED_SUBSYSTEMS +} +PUBLIC_MODULES = { + "IFU": "chisel/src/main/scala/linxcore/ifu/IFU.scala", + "CTU": "chisel/src/main/scala/linxcore/ctu/CTU.scala", + "OOO": "chisel/src/main/scala/linxcore/ooo/OOO.scala", + "IEX": "chisel/src/main/scala/linxcore/iex/IEX.scala", + "LSU": "chisel/src/main/scala/linxcore/lsu/LSU.scala", + "DTU": "chisel/src/main/scala/linxcore/dtu/DTU.scala", +} + +# Closed inventory: the manifest may report these decisions but cannot invent, +# alias, omit, or redirect a state domain to a different primary owner. +STATE_DOMAINS: dict[str, tuple[str, str, str]] = { + "instruction_cache": ( + "IFU", + "ISideL1I", + "chisel/src/main/scala/linxcore/frontend/ISideL1I.scala", + ), + "predictor_history": ( + "IFU", + "BSide", + "chisel/src/main/scala/linxcore/ifu/BSide.scala", + ), + "ifu_recovery_redirect": ( + "IFU", + "IFURecovery", + "chisel/src/main/scala/linxcore/ifu/IFURecovery.scala", + ), + "instruction_buffer": ( + "CTU", + "InstructionBuffer", + "chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala", + ), + "rename_p": ( + "OOO", + "PRename", + "chisel/src/main/scala/linxcore/ooo/PRename.scala", + ), + "rename_tu": ( + "OOO", + "TURename", + "chisel/src/main/scala/linxcore/ooo/TURename.scala", + ), + "memory_order": ( + "OOO", + "OooMemoryOrderAllocator", + "chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala", + ), + "rob": ("OOO", "ROB", "chisel/src/main/scala/linxcore/ooo/ROB.scala"), + "brob": ("OOO", "BROB", "chisel/src/main/scala/linxcore/ooo/BROB.scala"), + "commit": ( + "OOO", + "CommitControl", + "chisel/src/main/scala/linxcore/ooo/CommitControl.scala", + ), + "recovery": ( + "OOO", + "RecoveryControl", + "chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala", + ), + "dispatch_reservation": ( + "OOO", + "OooD3ReservationAllocator", + "chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala", + ), + "issue_queue": ( + "IEX", + "OooIexIssue", + "chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala", + ), + "physical_register_data_readiness": ( + "IEX", + "OooIexOperandFiles", + "chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala", + ), + "execution_pipeline": ( + "IEX", + "OooIexExecutionPipeline", + "chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala", + ), + "memory_transaction_and_initial_attempt_serial": ( + "IEX", + "OooIexIssue", + "chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala", + ), + "lsu_pipeline": ( + "LSU", + "LSU", + "chisel/src/main/scala/linxcore/lsu/LSU.scala", + ), + "store_queue": ( + "LSU", + "STQEntryBank", + "chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala", + ), + "store_commit_buffer": ( + "LSU", + "SCBRowBank", + "chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala", + ), + "load_inflight_queue": ( + "LSU", + "LoadInflightQueue", + "chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala", + ), + "load_resolve_queue": ( + "LSU", + "LoadResolveQueue", + "chisel/src/main/scala/linxcore/lsu/LoadResolveQueue.scala", + ), + "memory_dependency": ( + "LSU", + "ScalarLSUMDBPath", + "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala", + ), + "cache": ( + "LSU", + "ScalarL1D", + "chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala", + ), + "data_translation": ( + "LSU", + "DSideTranslation", + "chisel/src/main/scala/linxcore/lsu/Translation.scala", + ), + "lower_memory_transactions": ( + "LSU", + "LSULowerTransactionRecovery", + "chisel/src/main/scala/linxcore/lsu/LSURecovery.scala", + ), + "lsu_recovery": ( + "LSU", + "LSU", + "chisel/src/main/scala/linxcore/lsu/LSU.scala", + ), + "trace_debug_performance_observation": ( + "DTU", + "DTU", + "chisel/src/main/scala/linxcore/dtu/DTU.scala", + ), +} + +# Each state-domain mechanism set is checker-owned. A manifest row may not +# widen a domain by appending a second implementation under a different name. +DOMAIN_MECHANISMS: dict[str, tuple[tuple[str, str], ...]] = { + "instruction_cache": (("ISideL1I", "chisel/src/main/scala/linxcore/frontend/ISideL1I.scala"),), + "predictor_history": ( + ("BSide", "chisel/src/main/scala/linxcore/ifu/BSide.scala"), + ("BSideHistoryQueue", "chisel/src/main/scala/linxcore/frontend/BSideHistoryQueue.scala"), + ("BSidePredictionPipeline", "chisel/src/main/scala/linxcore/frontend/BSidePredictionPipeline.scala"), + ), + "ifu_recovery_redirect": ( + ("IFURecovery", "chisel/src/main/scala/linxcore/ifu/IFURecovery.scala"), + ("IfuRedirectArbiter", "chisel/src/main/scala/linxcore/frontend/IfuRedirectArbiter.scala"), + ), + "instruction_buffer": ( + ("InstructionBuffer", "chisel/src/main/scala/linxcore/ctu/InstructionBuffer.scala"), + ("TemplateDecode", "chisel/src/main/scala/linxcore/ctu/TemplateDecode.scala"), + ("TemplateExpand", "chisel/src/main/scala/linxcore/ctu/TemplateExpand.scala"), + ), + "rename_p": (("PRename", "chisel/src/main/scala/linxcore/ooo/PRename.scala"),), + "rename_tu": (("TURename", "chisel/src/main/scala/linxcore/ooo/TURename.scala"),), + "memory_order": (("OooMemoryOrderAllocator", "chisel/src/main/scala/linxcore/ooo/OooMemoryOrderAllocator.scala"),), + "rob": (("ROB", "chisel/src/main/scala/linxcore/ooo/ROB.scala"),), + "brob": (("BROB", "chisel/src/main/scala/linxcore/ooo/BROB.scala"),), + "commit": (("CommitControl", "chisel/src/main/scala/linxcore/ooo/CommitControl.scala"),), + "recovery": (("RecoveryControl", "chisel/src/main/scala/linxcore/ooo/RecoveryControl.scala"),), + "dispatch_reservation": ( + ("OooD3ReservationAllocator", "chisel/src/main/scala/linxcore/ooo/OooD3ReservationAllocator.scala"), + ("OooHierarchicalFreeSlotSelect", "chisel/src/main/scala/linxcore/ooo/OooHierarchicalFreeSlotSelect.scala"), + ("OooDispatch", "chisel/src/main/scala/linxcore/ooo/OooDispatch.scala"), + ), + "issue_queue": ( + ("OooIexIssue", "chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala"), + ("OooIexIssueBlockMatrix", "chisel/src/main/scala/linxcore/ooo/OooIexIssueBlockMatrix.scala"), + ), + "physical_register_data_readiness": ( + ("OooIexOperandFiles", "chisel/src/main/scala/linxcore/ooo/OooIexOperandFiles.scala"), + ("OooIexPDataFile", "chisel/src/main/scala/linxcore/ooo/OooIexPDataFile.scala"), + ), + "execution_pipeline": ( + ("OooIexExecutionPipeline", "chisel/src/main/scala/linxcore/ooo/OooIexExecutionPipeline.scala"), + ("OooIexTerminalFabric", "chisel/src/main/scala/linxcore/ooo/OooIexTerminalFabric.scala"), + ), + "memory_transaction_and_initial_attempt_serial": ( + ("OooIexIssue", "chisel/src/main/scala/linxcore/ooo/OooIexIssue.scala"), + ), + "lsu_pipeline": ( + ("LSU", "chisel/src/main/scala/linxcore/lsu/LSU.scala"), + ("ScalarLSULoadPath", "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPath.scala"), + ("STQSCBCommitBackend", "chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala"), + ), + "store_queue": ( + ("STQEntryBank", "chisel/src/main/scala/linxcore/lsu/STQEntryBank.scala"), + ("STQDataBank", "chisel/src/main/scala/linxcore/lsu/STQDataBank.scala"), + ("STQCommitQueue", "chisel/src/main/scala/linxcore/lsu/STQCommitQueue.scala"), + ), + "store_commit_buffer": ( + ("SCBRowBank", "chisel/src/main/scala/linxcore/lsu/SCBRowBank.scala"), + ("STQSCBCommitBackend", "chisel/src/main/scala/linxcore/lsu/STQSCBCommitBackend.scala"), + ), + "load_inflight_queue": (("LoadInflightQueue", "chisel/src/main/scala/linxcore/lsu/LoadInflightQueue.scala"),), + "load_resolve_queue": (("LoadResolveQueue", "chisel/src/main/scala/linxcore/lsu/LoadResolveQueue.scala"),), + "memory_dependency": ( + ("ScalarLSUMDBPath", "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPath.scala"), + ("MDBConflictDetect", "chisel/src/main/scala/linxcore/lsu/MDBConflictDetect.scala"), + ("MDBSSIT", "chisel/src/main/scala/linxcore/lsu/MDBSSIT.scala"), + ), + "cache": ( + ("ScalarL1D", "chisel/src/main/scala/linxcore/lsu/ScalarL1D.scala"), + ("LoadMissQueue", "chisel/src/main/scala/linxcore/lsu/LoadMissQueue.scala"), + ("LoadRefillTransport", "chisel/src/main/scala/linxcore/lsu/LoadRefillTransport.scala"), + ), + "data_translation": ( + ("DSideTranslation", "chisel/src/main/scala/linxcore/lsu/Translation.scala"), + ), + "lower_memory_transactions": ( + ("LSULowerTransactionRecovery", "chisel/src/main/scala/linxcore/lsu/LSURecovery.scala"), + ), + "lsu_recovery": ( + ("LSU", "chisel/src/main/scala/linxcore/lsu/LSU.scala"), + ), + "trace_debug_performance_observation": ( + ("DTU", "chisel/src/main/scala/linxcore/dtu/DTU.scala"), + ("DebugControl", "chisel/src/main/scala/linxcore/dtu/DebugControl.scala"), + ("TraceExport", "chisel/src/main/scala/linxcore/dtu/TraceExport.scala"), + ("PerformanceCounters", "chisel/src/main/scala/linxcore/dtu/PerformanceCounters.scala"), + ), +} + +MANAGED_BOUNDARIES: tuple[tuple[str, str, str, bool, str, int, str], ...] = ( + ("linxcore.top.IfuWindowLineFillAdapter", "chisel/src/main/scala/linxcore/top/IfuWindowLineFillAdapter.scala", "legacy-state-owner", True, "instruction_cache", 17, "linxcore.top.IfuWindowLineFillAdapter"), + ("linxcore.ifu.ISideMemoryAdapter", "chisel/src/main/scala/linxcore/ifu/ISide.scala", "legacy-state-owner", True, "instruction_cache", 17, "linxcore.ifu.ISideMemoryAdapter"), + ("linxcore.frontend.IfuBackendFeedbackBridge", "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridge.scala", "legacy-state-owner", True, "ifu_recovery_redirect", 17, "linxcore.frontend.IfuBackendFeedbackBridge"), + ("linxcore.rename.ScalarDecodeRenameBridge", "chisel/src/main/scala/linxcore/rename/ScalarDecodeRenameBridge.scala", "legacy-state-owner", True, "rename_p", 11, "linxcore.rename.ScalarDecodeRenameBridge"), + ("linxcore.rename.ScalarTURenameBridge", "chisel/src/main/scala/linxcore/rename/ScalarTURenameBridge.scala", "legacy-state-owner", True, "rename_tu", 11, "linxcore.rename.ScalarTURenameBridge"), + ("linxcore.top.IfuLineMemoryBridge", "chisel/src/main/scala/linxcore/top/IfuLineMemoryBridge.scala", "legacy-state-owner", True, "instruction_cache", 17, "linxcore.top.IfuLineMemoryBridge"), +) + +# Exact elaboration entry-point inventory. Classification is intentionally +# data, not a name heuristic: adding "Reduced" or "Probe" to a new executable +# does not grant it a non-production exemption. +EMITTER_INVENTORY: dict[tuple[str, str], str] = { + ("linxcore.bctrl.EmitBrobOrderStateProbe", "chisel/src/main/scala/linxcore/bctrl/BrobOrderStateProbe.scala"): "probe", + ("linxcore.bctrl.EmitBrobStoreCountPublisherProbe", "chisel/src/main/scala/linxcore/bctrl/BrobStoreCountPublisherProbe.scala"): "probe", + ("linxcore.bctrl.EmitBrobStoreRangeStateProbe", "chisel/src/main/scala/linxcore/bctrl/BrobStoreRangeStateProbe.scala"): "probe", + ("linxcore.backend.EmitD1DecodeRenameROBIngress", "chisel/src/main/scala/linxcore/backend/D1DecodeRenameROBIngress.scala"): "fixture", + ("linxcore.frontend.EmitD1InstructionDecodeProbe", "chisel/src/main/scala/linxcore/frontend/D1InstructionDecodeProbe.scala"): "probe", + ("linxcore.backend.EmitDecodeLoadStoreIdAssignProbe", "chisel/src/main/scala/linxcore/backend/DecodeLoadStoreIdAssignProbe.scala"): "probe", + ("linxcore.rename.EmitGPRRenameStidProbe", "chisel/src/main/scala/linxcore/rename/GPRRenameStidProbe.scala"): "probe", + ("linxcore.frontend.EmitIfuBackendFeedbackBridgeProbe", "chisel/src/main/scala/linxcore/frontend/IfuBackendFeedbackBridgeProbe.scala"): "probe", + ("linxcore.top.EmitIfuLineMemoryBridgeProbe", "chisel/src/main/scala/linxcore/top/IfuLineMemoryBridgeProbe.scala"): "probe", + ("linxcore.top.EmitLinxCoreCompositionProbe", "chisel/src/main/scala/linxcore/top/LinxCoreCompositionProbe.scala"): "probe", + ("linxcore.top.EmitTOP", "chisel/src/main/scala/linxcore/top/EmitTOP.scala"): "production", + ("linxcore.frontend.EmitLinxCoreIfuThroughputProbe", "chisel/src/main/scala/linxcore/frontend/LinxCoreIfuThroughputProbe.scala"): "probe", + ("linxcore.lsu.EmitLoadMissQueueProbe", "chisel/src/main/scala/linxcore/lsu/LoadMissQueueProbe.scala"): "probe", + ("linxcore.lsu.EmitLoadRefillTransportProbe", "chisel/src/main/scala/linxcore/lsu/LoadRefillTransportProbe.scala"): "probe", + ("linxcore.recovery.EmitRecoveryClassMergeProbe", "chisel/src/main/scala/linxcore/recovery/RecoveryClassMergeProbe.scala"): "probe", + ("linxcore.recovery.EmitRecoveryCleanupROBProbe", "chisel/src/main/scala/linxcore/recovery/RecoveryCleanupROBProbe.scala"): "probe", + ("linxcore.recovery.EmitRecoveryProducerProbe", "chisel/src/main/scala/linxcore/recovery/RecoveryProducerProbe.scala"): "probe", + ("linxcore.rob.EmitReducedCommitROB", "chisel/src/main/scala/linxcore/rob/EmitReducedCommitROB.scala"): "reduced", + ("linxcore.lsu.EmitScalarL1DScbProbe", "chisel/src/main/scala/linxcore/lsu/ScalarL1DScbProbe.scala"): "probe", + ("linxcore.lsu.EmitScalarLSULoadPathReturnProbe", "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadPathReturnProbe.scala"): "probe", + ("linxcore.lsu.EmitScalarLSULoadReturnQueueProbe", "chisel/src/main/scala/linxcore/lsu/ScalarLSULoadReturnQueueProbe.scala"): "probe", + ("linxcore.lsu.EmitScalarLSUMDBPathProbe", "chisel/src/main/scala/linxcore/lsu/ScalarLSUMDBPathProbe.scala"): "probe", +} + + +@dataclass(frozen=True) +class ScalaUnit: + path: Path + relative: str + package: str + text: str + imports: dict[str, str] + wildcard_imports: tuple[str, ...] + import_errors: tuple[str, ...] + + +@dataclass(frozen=True) +class ScalaDefinition: + fqcn: str + simple: str + kind: str + path: Path + relative: str + body: str + start: int + body_start: int + end: int + imports: dict[str, str] + wildcard_imports: tuple[str, ...] + import_errors: tuple[str, ...] + + +@dataclass +class ScalaIndex: + units: dict[Path, ScalaUnit] + definitions: dict[str, ScalaDefinition] + definitions_by_path: dict[Path, list[ScalaDefinition]] + constructor_callers: dict[str, set[str]] + unresolved_constructors: dict[Path, set[str]] + module_edges: dict[str, set[str]] + unresolved_module_edges: dict[str, set[str]] + direct_stateful: set[str] + + +CallableKey = tuple[str, str] + + +@dataclass(frozen=True) +class ScalaCallable: + key: CallableKey + body: str + path: Path + relative: str + imports: dict[str, str] + wildcard_imports: tuple[str, ...] + definition: ScalaDefinition | None + + +def load_manifest(path: Path) -> dict[str, Any]: + try: + text = path.read_text(encoding="utf-8") + except OSError as error: + raise ValueError(f"cannot read manifest {path}: {error}") from error + match = MANIFEST_BLOCK.search(text) + if not match: + raise ValueError("missing fenced JSON production-owner-manifest block") + try: + value = json.loads(match.group("payload")) + except json.JSONDecodeError as error: + raise ValueError(f"invalid production-owner manifest JSON: {error}") from error + if not isinstance(value, dict): + raise ValueError("production-owner manifest root must be an object") + return value + + +def strip_scala_noncode(text: str) -> str: + """Replace comments and literals with spaces while preserving positions.""" + result = list(text) + index = 0 + block_depth = 0 + state = "code" + while index < len(text): + pair = text[index : index + 2] + triple = text[index : index + 3] + if state == "code": + if pair == "//": + state = "line" + result[index : index + 2] = " " + index += 2 + continue + elif pair == "/*": + state = "block" + block_depth = 1 + result[index : index + 2] = " " + index += 2 + continue + elif triple == '\"\"\"': + state = "triple" + result[index : index + 3] = " " + index += 3 + continue + elif text[index] == '"': + state = "string" + result[index] = " " + index += 1 + continue + elif text[index] == "'": + state = "char" + result[index] = " " + index += 1 + continue + else: + index += 1 + continue + if state == "line": + if text[index] == "\n": + state = "code" + index += 1 + continue + elif state == "block": + if pair == "/*": + block_depth += 1 + result[index : index + 2] = " " + index += 2 + continue + if pair == "*/": + block_depth -= 1 + result[index : index + 2] = " " + index += 2 + if block_depth == 0: + state = "code" + continue + elif state == "triple" and triple == '\"\"\"': + result[index : index + 3] = " " + index += 3 + state = "code" + continue + elif state in {"string", "char"}: + quote = '"' if state == "string" else "'" + if text[index] == "\\": + result[index] = " " + if index + 1 < len(text) and text[index + 1] != "\n": + result[index + 1] = " " + index += 2 + continue + elif text[index] == quote: + result[index] = " " + index += 1 + state = "code" + continue + if text[index] != "\n": + result[index] = " " + index += 1 + return "".join(result) + + +def contained_path(root: Path, value: Any, label: str, errors: list[str]) -> Path | None: + if not isinstance(value, str) or not value: + errors.append(f"{label} must be a non-empty path") + return None + candidate = Path(value) + if candidate.is_absolute() or ".." in candidate.parts: + errors.append(f"path escapes repository root: {value}") + return None + resolved = (root / candidate).resolve() + if not resolved.is_relative_to(root): + errors.append(f"path escapes repository root: {value}") + return None + if not resolved.is_file(): + errors.append(f"missing {label}: {value}") + return None + return resolved + + +def path_list( + root: Path, + value: Any, + label: str, + errors: list[str], +) -> list[str]: + if not isinstance(value, list) or not value: + errors.append(f"{label} must be a non-empty list") + return [] + result: list[str] = [] + for index, item in enumerate(value): + if contained_path(root, item, f"{label}[{index}]", errors): + result.append(item) + return result + + +def source_defines(path: Path, symbol: str) -> bool: + pattern = re.compile(SYMBOL_DEFINITION.format(symbol=re.escape(symbol))) + return bool(pattern.search(path.read_text(encoding="utf-8"))) + + +def source_defines_fqcn(path: Path, symbol: str) -> bool: + if "." not in symbol: + return False + package, simple = symbol.rsplit(".", 1) + text = path.read_text(encoding="utf-8") + package_match = PACKAGE_DECLARATION.search(text) + return ( + package_match is not None + and package_match.group("name") == package + and bool(re.search(SYMBOL_DEFINITION.format(symbol=re.escape(simple)), text)) + ) + + +def source_texts(root: Path) -> dict[Path, str]: + source_root = root / "chisel/src/main/scala" + if not source_root.is_dir(): + return {} + return { + path: strip_scala_noncode(path.read_text(encoding="utf-8")) + for path in sorted(source_root.rglob("*.scala")) + } + + +def _split_import_selectors(value: str) -> list[str]: + return [item.strip() for item in value.split(",") if item.strip()] + + +def canonical_scala_name(value: str) -> str: + normalized = re.sub(r"\s*\.\s*", ".", value.strip()) + return normalized.removeprefix("_root_.") + + +def parse_imports(text: str) -> tuple[dict[str, str], tuple[str, ...], tuple[str, ...]]: + imports: dict[str, str] = {} + wildcards: list[str] = [] + errors: list[str] = [] + for match in re.finditer(r"(?m)^[ \t]*import[ \t]+", text): + index = match.end() + depth = 0 + while index < len(text): + char = text[index] + if char == "{": + depth += 1 + elif char == "}": + depth -= 1 + if depth < 0: + break + elif char in "\n;" and depth == 0: + break + index += 1 + expression = text[match.end() : index].strip() + braced = re.fullmatch(r"([A-Za-z_]\w*(?:\.[A-Za-z_]\w*)*)\.\{(.*)\}", expression, re.DOTALL) + if braced: + prefix, selectors = braced.groups() + prefix = canonical_scala_name(prefix) + for selector in _split_import_selectors(selectors): + renamed = re.fullmatch( + r"([A-Za-z_]\w*)\s*(?:=>|\bas\b)\s*([A-Za-z_]\w*|_)", + selector, + ) + if renamed: + original, alias = renamed.groups() + if alias != "_": + imports[alias] = f"{prefix}.{original}" + continue + if re.fullmatch(r"[A-Za-z_]\w*", selector): + imports[selector] = f"{prefix}.{selector}" + elif selector in {"_", "*"}: + wildcards.append(prefix) + else: + errors.append(expression) + continue + wildcard = re.fullmatch( + r"([A-Za-z_]\w*(?:\.[A-Za-z_]\w*)*)\.(?:_|\*)", expression + ) + if wildcard: + wildcards.append(canonical_scala_name(wildcard.group(1))) + continue + exact = re.fullmatch(r"[A-Za-z_]\w*(?:\.[A-Za-z_]\w*)+", expression) + if exact: + canonical = canonical_scala_name(expression) + imports[canonical.rsplit(".", 1)[-1]] = canonical + elif expression: + errors.append(expression) + return imports, tuple(wildcards), tuple(errors) + + +def _mask_ranges(text: str, ranges: list[tuple[int, int]]) -> str: + result = list(text) + for start, end in ranges: + for index in range(max(start, 0), min(end, len(result))): + if result[index] != "\n": + result[index] = " " + return "".join(result) + + +def _definition_bodies(unit: ScalaUnit) -> list[ScalaDefinition]: + matches = list(ANY_DEFINITION.finditer(unit.text)) + result: list[ScalaDefinition] = [] + for position, match in enumerate(matches): + limit = matches[position + 1].start() if position + 1 < len(matches) else len(unit.text) + brace = unit.text.find("{", match.end(), limit) + body = "" + body_start = match.end() + end = match.end() + if brace >= 0: + depth = 0 + end = len(unit.text) + for index in range(brace, len(unit.text)): + if unit.text[index] == "{": + depth += 1 + elif unit.text[index] == "}": + depth -= 1 + if depth == 0: + end = index + 1 + break + body = unit.text[brace:end] + body_start = brace + simple = match.group("name") + fqcn = f"{unit.package}.{simple}" if unit.package else simple + result.append( + ScalaDefinition( + fqcn=fqcn, + simple=simple, + kind=match.group("kind"), + path=unit.path, + relative=unit.relative, + body=body, + start=match.start(), + body_start=body_start, + end=end, + imports={}, + wildcard_imports=(), + import_errors=(), + ) + ) + scoped: list[ScalaDefinition] = [] + for definition in result: + prior_bodies = [ + (item.body_start, item.end) + for item in result + if item.start < definition.start + ] + prefix = _mask_ranges(unit.text[: definition.start], prior_bodies) + outer_imports, outer_wildcards, outer_errors = parse_imports(prefix) + nested_bodies = [ + (item.body_start - definition.body_start, item.end - definition.body_start) + for item in result + if definition.start < item.start and item.end <= definition.end + ] + local = _mask_ranges(definition.body, nested_bodies) + local_imports, local_wildcards, local_errors = parse_imports(local) + scoped.append( + ScalaDefinition( + fqcn=definition.fqcn, + simple=definition.simple, + kind=definition.kind, + path=definition.path, + relative=definition.relative, + body=definition.body, + start=definition.start, + body_start=definition.body_start, + end=definition.end, + imports={**outer_imports, **local_imports}, + wildcard_imports=tuple(dict.fromkeys((*outer_wildcards, *local_wildcards))), + import_errors=(*outer_errors, *local_errors), + ) + ) + return scoped + + +def resolve_scala_name( + raw: str, + unit: ScalaUnit, + definitions: dict[str, ScalaDefinition], + definition: ScalaDefinition | None = None, +) -> str | None: + normalized = canonical_scala_name(raw) + imports = definition.imports if definition is not None else unit.imports + wildcard_imports = ( + definition.wildcard_imports if definition is not None else unit.wildcard_imports + ) + if "." in normalized: + head, tail = normalized.split(".", 1) + if head in imports: + normalized = f"{imports[head]}.{tail}" + return normalized if normalized in definitions else None + imported = imports.get(normalized) + if imported and imported in definitions: + return imported + same_package = f"{unit.package}.{normalized}" if unit.package else normalized + if same_package in definitions: + return same_package + wildcard_matches = [ + f"{package}.{normalized}" + for package in wildcard_imports + if f"{package}.{normalized}" in definitions + ] + if len(wildcard_matches) == 1: + return wildcard_matches[0] + return None + + +def build_scala_index(root: Path, sources: dict[Path, str] | None = None) -> ScalaIndex: + sources = sources if sources is not None else source_texts(root) + units: dict[Path, ScalaUnit] = {} + definitions_by_path: dict[Path, list[ScalaDefinition]] = {} + definitions: dict[str, ScalaDefinition] = {} + for path, text in sources.items(): + package_match = PACKAGE_DECLARATION.search(text) + package = package_match.group("name") if package_match else "" + preliminary = ScalaUnit( + path=path, + relative=path.relative_to(root).as_posix(), + package=package, + text=text, + imports={}, + wildcard_imports=(), + import_errors=(), + ) + unit_definitions = _definition_bodies(preliminary) + top_level = _mask_ranges( + text, + [(definition.body_start, definition.end) for definition in unit_definitions], + ) + imports, wildcards, import_errors = parse_imports(top_level) + unit = ScalaUnit( + path=preliminary.path, + relative=preliminary.relative, + package=package, + text=text, + imports=imports, + wildcard_imports=wildcards, + import_errors=import_errors, + ) + units[path] = unit + definitions_by_path[path] = unit_definitions + for definition in unit_definitions: + previous = definitions.get(definition.fqcn) + if previous is None: + definitions[definition.fqcn] = definition + else: + definitions[definition.fqcn] = ScalaDefinition( + fqcn=definition.fqcn, + simple=definition.simple, + kind="companion", + path=definition.path, + relative=definition.relative, + body=f"{previous.body}\n{definition.body}", + start=min(previous.start, definition.start), + body_start=min(previous.body_start, definition.body_start), + end=max(previous.end, definition.end), + imports={**previous.imports, **definition.imports}, + wildcard_imports=tuple( + dict.fromkeys( + (*previous.wildcard_imports, *definition.wildcard_imports) + ) + ), + import_errors=(*previous.import_errors, *definition.import_errors), + ) + + constructor_callers: dict[str, set[str]] = {} + unresolved_constructors: dict[Path, set[str]] = {} + module_edges: dict[str, set[str]] = {} + unresolved_module_edges: dict[str, set[str]] = {} + direct_stateful: set[str] = set() + for path, unit in units.items(): + for match in INSTANTIATION.finditer(unit.text): + raw = match.group("name") + scopes = [ + definition + for definition in definitions_by_path[path] + if definition.body_start <= match.start() < definition.end + ] + scope = min(scopes, key=lambda item: item.end - item.start) if scopes else None + resolved = resolve_scala_name(raw, unit, definitions, scope) + if resolved is None or resolved not in definitions: + unresolved_constructors.setdefault(path, set()).add( + canonical_scala_name(raw) + ) + else: + constructor_callers.setdefault(resolved, set()).add(unit.relative) + for definition in definitions_by_path[path]: + if STATE_TOKEN.search(definition.body): + direct_stateful.add(definition.fqcn) + for match in MODULE_INSTANTIATION.finditer(definition.body): + raw = match.group("name") + resolved = resolve_scala_name(raw, unit, definitions, definition) + if resolved is None or resolved not in definitions: + unresolved_module_edges.setdefault(definition.fqcn, set()).add(raw) + else: + module_edges.setdefault(definition.fqcn, set()).add(resolved) + return ScalaIndex( + units=units, + definitions=definitions, + definitions_by_path=definitions_by_path, + constructor_callers=constructor_callers, + unresolved_constructors=unresolved_constructors, + module_edges=module_edges, + unresolved_module_edges=unresolved_module_edges, + direct_stateful=direct_stateful, + ) + + +CALLABLE_DEFINITION = re.compile( + r"(?m)^(?P[ \t]*)(?:@[A-Za-z_]\w*(?:\([^\n)]*\))?[ \t]+)*" + r"(?:private(?:\[[^\]]+\])?[ \t]+)?" + r"(?:final[ \t]+)?def[ \t]+(?P[A-Za-z_]\w*)\b" +) + + +def _callable_regions(text: str) -> list[tuple[str, int, int]]: + matches = list(CALLABLE_DEFINITION.finditer(text)) + result: list[tuple[str, int, int]] = [] + for match in matches: + next_start = next( + (item.start() for item in matches if item.start() > match.start()), + len(text), + ) + equals = text.find("=", match.end(), next_start) + if equals < 0: + continue + base_indent = len(match.group("indent").expandtabs(2)) + depth = 0 + end = len(text) + index = equals + 1 + while index < len(text): + char = text[index] + if char in "([{": + depth += 1 + elif char in ")]}" and depth: + depth -= 1 + if char == "\n" and depth == 0: + line_start = index + 1 + line_end = text.find("\n", line_start) + line_end = len(text) if line_end < 0 else line_end + line = text[line_start:line_end] + if line.strip(): + indent = len(line) - len(line.lstrip(" \t")) + if indent <= base_indent: + end = line_start + break + index += 1 + result.append((match.group("name"), match.start(), end)) + return result + + +def _without_imports(text: str) -> str: + ranges: list[tuple[int, int]] = [] + for match in re.finditer(r"(?m)^[ \t]*import[ \t]+", text): + index = match.end() + depth = 0 + while index < len(text): + char = text[index] + if char == "{": + depth += 1 + elif char == "}": + depth -= 1 + elif char in "\n;" and depth == 0: + break + index += 1 + ranges.append((match.start(), index)) + return _mask_ranges(text, ranges) + + +def _merge_callable( + callables: dict[CallableKey, ScalaCallable], + callable_: ScalaCallable, +) -> None: + previous = callables.get(callable_.key) + if previous is None: + callables[callable_.key] = callable_ + return + callables[callable_.key] = ScalaCallable( + key=callable_.key, + body=f"{previous.body}\n{callable_.body}", + path=callable_.path, + relative=callable_.relative, + imports={**previous.imports, **callable_.imports}, + wildcard_imports=tuple( + dict.fromkeys((*previous.wildcard_imports, *callable_.wildcard_imports)) + ), + definition=callable_.definition or previous.definition, + ) + + +def build_callable_graph( + index: ScalaIndex, +) -> tuple[ + dict[CallableKey, ScalaCallable], + dict[CallableKey, set[CallableKey]], + set[CallableKey], +]: + callables: dict[CallableKey, ScalaCallable] = {} + for path, unit in index.units.items(): + definitions = index.definitions_by_path[path] + for definition in definitions: + if definition.kind != "object": + continue + regions = _callable_regions(definition.body) + object_body = _mask_ranges( + definition.body, + [(start, end) for _, start, end in regions], + ) + object_imports, object_wildcards, _ = parse_imports(object_body) + outer_imports = { + **unit.imports, + **object_imports, + } + outer_wildcards = tuple( + dict.fromkeys((*unit.wildcard_imports, *object_wildcards)) + ) + _merge_callable( + callables, + ScalaCallable( + key=(definition.fqcn, ""), + body=object_body, + path=path, + relative=unit.relative, + imports=outer_imports, + wildcard_imports=outer_wildcards, + definition=definition, + ), + ) + for name, start, end in regions: + body = definition.body[start:end] + local_imports, local_wildcards, _ = parse_imports(body) + _merge_callable( + callables, + ScalaCallable( + key=(definition.fqcn, name), + body=body, + path=path, + relative=unit.relative, + imports={**outer_imports, **local_imports}, + wildcard_imports=tuple( + dict.fromkeys((*outer_wildcards, *local_wildcards)) + ), + definition=definition, + ), + ) + + top_level = _mask_ranges( + unit.text, + [(definition.start, definition.end) for definition in definitions], + ) + for name, start, end in _callable_regions(top_level): + body = unit.text[start:end] + local_imports, local_wildcards, _ = parse_imports(body) + _merge_callable( + callables, + ScalaCallable( + key=(unit.package, name), + body=body, + path=path, + relative=unit.relative, + imports={**unit.imports, **local_imports}, + wildcard_imports=tuple( + dict.fromkeys((*unit.wildcard_imports, *local_wildcards)) + ), + definition=None, + ), + ) + + full_names = { + f"{owner}.{name}" if owner else name: key + for key in callables + for owner, name in [key] + if not name.startswith("<") + } + + def resolve_reference(raw: str, caller: ScalaCallable) -> CallableKey | None: + unit = index.units[caller.path] + normalized = canonical_scala_name(raw) + imported = caller.imports.get(normalized) + if imported in full_names: + return full_names[imported] + if "." in normalized: + head, tail = normalized.split(".", 1) + if head in caller.imports: + normalized = f"{caller.imports[head]}.{tail}" + if normalized in full_names: + return full_names[normalized] + owner_raw, name = normalized.rsplit(".", 1) + owner = resolve_scala_name( + owner_raw, + unit, + index.definitions, + caller.definition, + ) + qualified = (owner, name) if owner is not None else None + if qualified in callables: + return qualified + object_owner = resolve_scala_name( + normalized, + unit, + index.definitions, + caller.definition, + ) + apply = (object_owner, "apply") if object_owner is not None else None + return apply if apply in callables else None + local = (caller.key[0], normalized) + if local in callables: + return local + package_local = (unit.package, normalized) + if package_local in callables: + return package_local + owner = resolve_scala_name( + normalized, + unit, + index.definitions, + caller.definition, + ) + apply = (owner, "apply") if owner is not None else None + return apply if apply in callables else None + + edges: dict[CallableKey, set[CallableKey]] = {} + sinks: set[CallableKey] = set() + for key, callable_ in callables.items(): + code = _without_imports(callable_.body) + if "emitSystemVerilog" in code or "emitVerilog" in code: + sinks.add(key) + references = set( + re.findall(r"\b[A-Za-z_]\w*(?:\s*\.\s*[A-Za-z_]\w*)+", code) + ) + references.update(re.findall(r"\b([A-Za-z_]\w*)\s*\(", code)) + nullary_names = { + name + for name, target in callable_.imports.items() + if target in full_names + } + nullary_names.update( + name for owner, name in callables if owner == callable_.key[0] + ) + for name in nullary_names: + if re.search(rf"\b{re.escape(name)}\b", code): + references.add(name) + for raw in references: + resolved = resolve_reference(raw, callable_) + if resolved is not None and resolved != key: + edges.setdefault(key, set()).add(resolved) + return callables, edges, sinks + + +def scan_emitters( + root: Path, + sources: dict[Path, str] | None = None, + index: ScalaIndex | None = None, +) -> list[tuple[str, str]]: + sources = sources if sources is not None else source_texts(root) + index = index if index is not None else build_scala_index(root, sources) + callables, edges, emitting_callables = build_callable_graph(index) + changed = True + while changed: + changed = False + for caller, callees in edges.items(): + if caller not in emitting_callables and callees & emitting_callables: + emitting_callables.add(caller) + changed = True + + emitters: set[tuple[str, str]] = set() + for path, unit in index.units.items(): + relative = unit.relative + qualified = lambda name: f"{unit.package}.{name}" if unit.package else name + for match in APP_ENTRY.finditer(unit.text): + fqcn = qualified(match.group("name")) + if (fqcn, "") in emitting_callables: + emitters.add((fqcn, relative)) + for definition in index.definitions_by_path[path]: + if definition.kind == "object" and ( + definition.fqcn, + "main", + ) in emitting_callables: + emitters.add((definition.fqcn, relative)) + for match in AT_MAIN_ENTRY.finditer(unit.text): + if (unit.package, match.group("name")) in emitting_callables: + emitters.add((qualified(match.group("name")), relative)) + return sorted(emitters) + + +def scan_adapters( + root: Path, + sources: dict[Path, str] | None = None, + index: ScalaIndex | None = None, +) -> dict[tuple[str, str], bool]: + index = index if index is not None else build_scala_index(root, sources) + result: dict[tuple[str, str], bool] = {} + managed_root = root / "chisel/src/main/scala/linxcore" + candidates = [ + definition + for definitions in index.definitions_by_path.values() + for definition in definitions + if definition.path.is_relative_to(managed_root) + and re.fullmatch(r"[A-Za-z_]\w*(?:Adapter|Wrapper|Bridge)", definition.simple) + ] + stateful_symbols = set(index.direct_stateful) + changed = True + while changed: + changed = False + for owner, children in index.module_edges.items(): + if owner not in stateful_symbols and children & stateful_symbols: + stateful_symbols.add(owner) + changed = True + for definition in candidates: + stateful = definition.fqcn in stateful_symbols + if not definition.simple.endswith("Bridge") or stateful: + result[(definition.fqcn, definition.relative)] = stateful + return result + + +def discover_callers( + root: Path, + symbol: str, + sources: dict[Path, str] | None = None, + index: ScalaIndex | None = None, +) -> list[str]: + index = index if index is not None else build_scala_index(root, sources) + return sorted(index.constructor_callers.get(symbol, set())) + + +def instantiation_graph(sources: dict[Path, str]) -> dict[str, set[str]]: + graph: dict[str, set[str]] = {} + for text in sources.values(): + definitions = {match.group("name") for match in ANY_DEFINITION.finditer(text)} + instantiated = {match.group("name") for match in INSTANTIATION.finditer(text)} + for definition in definitions: + graph.setdefault(definition, set()).update(instantiated) + return graph + + +def reachable(graph: dict[str, set[str]], start: str, target: str) -> bool: + pending = [start] + visited: set[str] = set() + while pending: + current = pending.pop() + if current == target: + return True + if current in visited: + continue + visited.add(current) + pending.extend(graph.get(current, set()) - visited) + return False + + +def validate_ndf(ndf: Any, root: Path, errors: list[str]) -> None: + if not isinstance(ndf, dict): + errors.append("missing NDF mapping") + return + layers: dict[str, list[str]] = {} + for layer in ("L1", "L2", "L3"): + if layer not in ndf: + errors.append(f"missing NDF {layer}") + layers[layer] = [] + else: + layers[layer] = path_list(root, ndf[layer], f"NDF {layer}", errors) + for value in layers["L1"]: + path = Path(value) + if not value.startswith("docs/spec/") or path.suffix != ".md": + errors.append(f"NDF L1 path must be Markdown under docs/spec: {value}") + for value in layers["L2"]: + is_interface_source = ( + value.startswith("chisel/src/main/scala/linxcore/top/interface/") + and Path(value).suffix == ".scala" + ) + is_generated_manifest = value == "docs/chisel/generated/top-interface-manifest.json" + if not (is_interface_source or is_generated_manifest): + errors.append(f"NDF L2 path has invalid mechanism role: {value}") + for value in layers["L3"]: + is_scala_test = value.startswith("chisel/src/test/scala/") and value.endswith(".scala") + is_python_test = value.startswith("tests/") and value.endswith(".py") + if not (is_scala_test or is_python_test): + errors.append(f"NDF L3 path must be an executable test: {value}") + seen: dict[str, str] = {} + identities: dict[tuple[int, int], tuple[str, str]] = {} + for layer, values in layers.items(): + for value in values: + if value in seen and seen[value] != layer: + errors.append(f"NDF path reused across layer roles: {value}") + seen[value] = layer + lexical = root / value + if lexical.is_symlink(): + errors.append(f"NDF normative path must not be a symlink: {value}") + continue + try: + stat = lexical.stat() + except OSError: + continue + identity = (stat.st_dev, stat.st_ino) + previous = identities.get(identity) + if previous is not None and previous[0] != layer: + errors.append( + "NDF file identity reused across layer roles: " + f"{previous[1]} ({previous[0]}) and {value} ({layer})" + ) + else: + identities[identity] = (layer, value) + interface_manifest = ndf.get("interface_manifest") + if contained_path(root, interface_manifest, "NDF interface_manifest", errors): + if interface_manifest not in layers["L2"]: + errors.append("interface manifest must be an NDF L2 member") + if interface_manifest != "docs/chisel/generated/top-interface-manifest.json": + errors.append("interface manifest must use the canonical generated JSON path") + + +def validate_public_box(owner: dict[str, Any], root: Path, errors: list[str]) -> None: + state_key = owner["state_key"] + box = owner.get("public_box") + status = owner.get("public_box_status") + interface = owner.get("public_interface_file") + expected_interface = PUBLIC_INTERFACES.get(box) + if interface != expected_interface: + errors.append(f"public interface mismatch for {state_key}") + else: + contained_path(root, interface, f"public interface for {state_key}", errors) + if status == "module": + box_file = owner.get("public_box_file") + if box_file != PUBLIC_MODULES.get(box): + errors.append(f"public box {box} is not a Module definition") + return + resolved = contained_path(root, box_file, f"public box for {state_key}", errors) + if resolved: + pattern = re.compile( + rf"(?m)^\s*class\s+{re.escape(box)}\b[^\n]*extends\s+Module\b" + ) + if not pattern.search(resolved.read_text(encoding="utf-8")): + errors.append(f"public box {box} is not a Module definition") + elif status == "pending": + if box in PUBLIC_MODULES: + errors.append(f"existing public Module {box} cannot be marked pending") + if owner.get("public_box_file") not in (None, ""): + errors.append(f"pending public box {box} must not name an IO Bundle as a box") + else: + errors.append(f"invalid public_box_status for {state_key}") + + +def validate_evidence( + owner: dict[str, Any], + entry_points: dict[str, Any], + root: Path, + sources: dict[Path, str], + graph: dict[str, set[str]], + errors: list[str], +) -> None: + state_key = owner["state_key"] + fixtures = set(owner.get("verification_fixtures", [])) + evidence = owner.get("production_evidence") + if not isinstance(evidence, list) or not evidence: + errors.append(f"missing production evidence for {state_key}") + return + for item in evidence: + if not isinstance(item, dict): + errors.append(f"production evidence for {state_key} must be an object") + continue + fixture = item.get("fixture") + resolved_fixture = contained_path( + root, + fixture, + f"production evidence fixture for {state_key}", + errors, + ) + if fixture not in fixtures: + errors.append(f"evidence fixture for {state_key} is not a verification fixture") + case = item.get("case") + if case is not None: + if not isinstance(case, str) or not case: + errors.append(f"evidence case for {state_key} must be a non-empty string") + elif resolved_fixture: + pattern = re.compile( + rf'\btest\s*\(\s*"{re.escape(case)}"\s*\)' + ) + if not pattern.search(resolved_fixture.read_text(encoding="utf-8")): + errors.append(f"evidence case for {state_key} not found: {case}") + if item.get("level") != "L3": + errors.append(f"production evidence for {state_key} must be L3") + status = item.get("status") + if status not in EVIDENCE_STATUSES: + errors.append(f"invalid evidence status for {state_key}: {status}") + if status == "public-box-verified" and owner.get("public_box_status") != "module": + errors.append(f"public-box evidence for {state_key} lacks a public Module") + if status == "public-box-verified" and not reachable( + graph, + owner["public_box"], + owner["canonical_owner"], + ): + errors.append( + f"public-box evidence for {state_key} lacks box-to-owner reachability" + ) + if status == "production-promoted": + errors.append( + "production-promoted is disabled until Task 17 artifact schema " + "is checker-owned" + ) + errors.append( + f"production-promoted evidence for {state_key} lacks a " + "checker-owned activation artifact" + ) + + +def validate_deletion_targets( + owner: dict[str, Any], + root: Path, + sources: dict[Path, str], + index: ScalaIndex, + errors: list[str], +) -> None: + state_key = owner["state_key"] + targets = owner.get("deletion_targets") + if not isinstance(targets, list): + errors.append(f"deletion targets for {state_key} must be a list") + return + for target in targets: + if not isinstance(target, dict): + errors.append(f"deletion target for {state_key} must be an object") + continue + path = target.get("path") + symbol = target.get("symbol") + resolved = contained_path(root, path, f"deletion target for {state_key}", errors) + if not isinstance(symbol, str) or "." not in symbol: + errors.append(f"deletion target for {state_key} needs an exact FQCN symbol") + continue + if resolved and not source_defines_fqcn(resolved, symbol): + errors.append(f"deletion target {path} does not define {symbol}") + declared = target.get("active_callers") + if not isinstance(declared, list) or not all(isinstance(item, str) for item in declared): + errors.append(f"deletion target {symbol} active_callers must be a list") + continue + for caller in declared: + contained_path(root, caller, f"declared caller for {symbol}", errors) + discovered = discover_callers(root, symbol, sources, index) + if sorted(declared) != discovered: + errors.append( + f"deletion target {symbol} caller declaration mismatch: " + f"declared={sorted(declared)} discovered={discovered}" + ) + status = target.get("status") + if status == "planned-active": + if not discovered: + errors.append(f"planned-active deletion target {symbol} has no discovered callers") + elif status == "deletion-ready": + if discovered: + errors.append(f"deletion-ready target {symbol} still has discovered callers") + simple = symbol.rsplit(".", 1)[-1] + uncertain: set[str] = set() + for unit in index.units.values(): + if any(symbol in item or simple in item for item in unit.import_errors): + uncertain.add(unit.relative) + unresolved = index.unresolved_constructors.get(unit.path, set()) + if any( + reference == symbol or reference.rsplit(".", 1)[-1] == simple + for reference in unresolved + ): + uncertain.add(unit.relative) + if uncertain: + errors.append( + f"deletion-ready target {symbol} has unresolved Scala references: " + f"{sorted(uncertain)}" + ) + else: + errors.append(f"invalid deletion status for {symbol}") + + +def validate_adapters( + manifest: dict[str, Any], + root: Path, + sources: dict[Path, str], + index: ScalaIndex, + errors: list[str], +) -> None: + discovered = scan_adapters(root, sources, index) + declared_items = manifest.get("adapters") + if not isinstance(declared_items, list): + errors.append("adapters must be a root-level list") + declared_items = [] + declared: dict[tuple[str, str], dict[str, Any]] = {} + for item in declared_items: + if not isinstance(item, dict): + errors.append("adapter declaration must be an object") + continue + key = (item.get("symbol"), item.get("path")) + if not all(isinstance(value, str) and value for value in key): + errors.append("adapter declaration needs exact symbol and path") + continue + declared[key] = item + resolved = contained_path(root, key[1], f"adapter {key[0]}", errors) + simple = key[0].rsplit(".", 1)[-1] + if resolved and not source_defines(resolved, simple): + errors.append(f"adapter path {key[1]} does not define {key[0]}") + expected = { + (symbol, path): { + "symbol": symbol, + "path": path, + "role": role, + "stateful": stateful, + "status": "planned-deletion" if role == "legacy-state-owner" else "active", + "owner_domain": domain, + "cutover_task": cutover, + "deletion_target": deletion_target, + } + for symbol, path, role, stateful, domain, cutover, deletion_target in MANAGED_BOUNDARIES + } + normalized_declared = { + key: { + field: item.get(field) + for field in ( + "symbol", "path", "role", "stateful", "status", + "owner_domain", "cutover_task", "deletion_target", + ) + } + for key, item in declared.items() + } + if normalized_declared != expected: + errors.append("managed boundary inventory mismatch") + deletion_symbols_by_domain = { + owner.get("state_key"): { + target.get("symbol") + for target in owner.get("deletion_targets", []) + if isinstance(target, dict) + } + for owner in manifest.get("owners", []) + if isinstance(owner, dict) + } + for item in expected.values(): + if item["deletion_target"] not in deletion_symbols_by_domain.get( + item["owner_domain"], set() + ): + errors.append( + f"managed boundary {item['symbol']} lacks its exact deletion target" + ) + for key, stateful in discovered.items(): + simple = key[0].rsplit(".", 1)[-1] + item = declared.get(key) or declared.get((simple, key[1])) + if item is None: + label = "managed boundary" if key[0].endswith("Bridge") else "adapter" + errors.append(f"undeclared {label} {simple} in {key[1]}") + continue + if item.get("stateful") is not stateful: + errors.append(f"adapter {simple} stateful declaration mismatch") + role = item.get("role") + if role == "compatibility": + if stateful: + errors.append(f"stateful adapter {key[0]}") + for child in sorted(index.unresolved_module_edges.get(key[0], set())): + errors.append(f"adapter {simple} has unresolved child {child}") + elif role == "legacy-state-owner": + if item.get("status") != "planned-deletion": + errors.append(f"legacy adapter {key[0]} must be planned for deletion") + if item.get("owner_domain") not in STATE_DOMAINS: + errors.append(f"legacy adapter {key[0]} needs a closed owner domain") + if not isinstance(item.get("cutover_task"), int): + errors.append(f"legacy adapter {key[0]} needs a cutover task") + else: + errors.append(f"invalid adapter role for {key[0]}") + for key in sorted(set(declared) - set(discovered)): + errors.append(f"declared adapter not discovered: {key[0]} in {key[1]}") + + +def validate_entry_points( + manifest: dict[str, Any], + root: Path, + sources: dict[Path, str], + index: ScalaIndex, + errors: list[str], +) -> dict[str, Any]: + entry_points = manifest.get("entry_points") + if not isinstance(entry_points, dict): + errors.append("entry_points must be an object") + return {} + if "non_production_patterns" in entry_points: + errors.append("manifest-controlled emitter patterns are forbidden") + production = entry_points.get("production", []) + non_production = entry_points.get("non_production", []) + if not isinstance(production, list) or not isinstance(non_production, list): + errors.append("entry point registrations must be lists") + return entry_points + registrations: dict[tuple[str, str], str] = {} + for classification, entries in (("production", production), ("non-production", non_production)): + for entry in entries: + if not isinstance(entry, dict): + errors.append(f"{classification} entry point must be an object") + continue + name, path = entry.get("name"), entry.get("path") + contained_path(root, path, f"{classification} emitter {name}", errors) + if isinstance(name, str) and isinstance(path, str): + registrations[(name, path)] = entry.get("classification", "") + if (classification == "production" and + EMITTER_INVENTORY.get((name, path)) != "production"): + errors.append( + f"checker-owned non-production emitter cannot be promoted: {name}" + ) + if classification == "production" and not entry.get("production_evidence"): + errors.append(f"missing production evidence for emitter {name}") + discovered_emitters = set(scan_emitters(root, sources, index)) + for name, path in discovered_emitters: + expected_class = EMITTER_INVENTORY.get((name, path)) + registration = registrations.get((name, path)) + if expected_class is None: + errors.append(f"unknown emitter {name} in {path}") + errors.append(f"unknown emitter {name.rsplit('.', 1)[-1]} in {path}") + elif registration != expected_class: + errors.append( + f"emitter registration mismatch for {name}: " + f"expected {expected_class}, got {registration or 'missing'}" + ) + for name, path in sorted(set(registrations) - discovered_emitters): + errors.append(f"registered emitter not discovered: {name} in {path}") + if registrations != EMITTER_INVENTORY: + errors.append("emitter inventory mismatch") + return entry_points + + +def validate(manifest: dict[str, Any], root: Path) -> list[str]: + errors: list[str] = [] + sources = source_texts(root) + index = build_scala_index(root, sources) + graph = instantiation_graph(sources) + if manifest.get("schema_version") != 2: + errors.append("schema_version must be 2") + validate_ndf(manifest.get("ndf"), root, errors) + entry_points = validate_entry_points(manifest, root, sources, index, errors) + + owners = manifest.get("owners") + if not isinstance(owners, list) or not owners: + errors.append("owners must be a non-empty list") + owners = [] + completed_cutovers = manifest.get("completed_cutover_tasks", []) + if not isinstance(completed_cutovers, list) or not all( + isinstance(task, int) for task in completed_cutovers + ): + errors.append("completed_cutover_tasks must be a list of integers") + completed_cutovers = [] + state_keys = [owner.get("state_key") for owner in owners if isinstance(owner, dict)] + for state_key, count in Counter(state_keys).items(): + if state_key and count > 1: + errors.append(f"duplicate owner for state domain {state_key}") + for state_key in sorted(set(STATE_DOMAINS) - set(state_keys)): + errors.append(f"missing state domain {state_key}") + for state_key in sorted(set(state_keys) - set(STATE_DOMAINS)): + errors.append(f"unknown state domain {state_key}") + + for owner_index, owner in enumerate(owners): + if not isinstance(owner, dict): + errors.append(f"owner[{owner_index}] must be an object") + continue + state_key = owner.get("state_key") + if state_key not in STATE_DOMAINS: + continue + subsystem, canonical_symbol, _primary_file = STATE_DOMAINS[state_key] + if owner.get("subsystem") != subsystem: + errors.append(f"subsystem mismatch for {state_key}") + if owner.get("canonical_owner") != canonical_symbol: + errors.append(f"canonical owner mismatch for {state_key}") + mechanisms = path_list( + root, + owner.get("mechanism_files"), + f"mechanism files for {state_key}", + errors, + ) + expected_mechanisms = DOMAIN_MECHANISMS[state_key] + expected_paths = [path for _symbol, path in expected_mechanisms] + if mechanisms != expected_paths: + errors.append(f"mechanism set mismatch for {state_key}") + for symbol, mechanism in expected_mechanisms: + resolved = contained_path(root, mechanism, f"mechanism for {state_key}", errors) + if resolved and not source_defines(resolved, symbol): + errors.append( + f"mechanism {mechanism} does not define checker-owned symbol {symbol}" + ) + if owner.get("public_box") != subsystem: + errors.append(f"public box mismatch for {state_key}") + validate_public_box(owner, root, errors) + raw_callers = owner.get("active_callers") + if owner.get("public_box_status") == "pending" and raw_callers == []: + declared_callers = [] + else: + declared_callers = path_list( + root, + raw_callers, + f"active callers for {state_key}", + errors, + ) + primary = contained_path( + root, + _primary_file, + f"primary mechanism for {state_key}", + errors, + ) + canonical_definitions = { + definition.fqcn: definition + for definition in index.definitions_by_path.get(primary, []) + if definition.simple == canonical_symbol + } if primary else {} + if len(canonical_definitions) != 1: + errors.append( + f"canonical owner definition mismatch for {state_key}: " + f"{canonical_symbol}" + ) + else: + canonical_fqcn = next(iter(canonical_definitions)) + discovered_callers = discover_callers( + root, + canonical_fqcn, + sources, + index, + ) + if declared_callers != discovered_callers: + errors.append( + f"canonical owner {canonical_fqcn} caller declaration mismatch: " + f"declared={declared_callers}, discovered={discovered_callers}" + ) + path_list( + root, + owner.get("verification_fixtures"), + f"verification fixtures for {state_key}", + errors, + ) + validate_evidence(owner, entry_points, root, sources, graph, errors) + cutover_task = owner.get("cutover_task") + if not isinstance(cutover_task, int): + errors.append(f"missing cutover task for {state_key}") + elif cutover_task in completed_cutovers: + evidence = owner.get("production_evidence", []) + if any( + isinstance(item, dict) + and item.get("status") == "mechanism-verified-cutover-pending" + for item in evidence + ): + errors.append( + f"completed cutover task {cutover_task} cannot retain pending " + f"evidence for {state_key}" + ) + if owner.get("adapters") not in (None, []): + errors.append(f"owner-local adapters must be empty for {state_key}") + validate_deletion_targets(owner, root, sources, index, errors) + + subsystems = {owner.get("subsystem") for owner in owners if isinstance(owner, dict)} + missing_subsystems = sorted(REQUIRED_SUBSYSTEMS - subsystems) + if missing_subsystems: + errors.append(f"missing subsystem state categories: {', '.join(missing_subsystems)}") + validate_adapters(manifest, root, sources, index, errors) + return errors + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--root", type=Path, default=ROOT) + parser.add_argument("--manifest", type=Path, default=None) + args = parser.parse_args() + root = args.root.resolve() + manifest_path = ( + args.manifest.resolve() + if args.manifest + else root / DEFAULT_MANIFEST.relative_to(ROOT) + ) + try: + manifest = load_manifest(manifest_path) + except ValueError as error: + print(f"production-owner-manifest: ERROR: {error}", file=sys.stderr) + return 1 + errors = validate(manifest, root) + if errors: + for error in errors: + print(f"production-owner-manifest: ERROR: {error}", file=sys.stderr) + return 1 + owners = manifest["owners"] + emitters = sum(len(items) for items in manifest["entry_points"].values()) + adapters = len(manifest["adapters"]) + print( + f"production-owner-manifest: {len(owners)} closed owners, " + f"{emitters} classified emitters, {adapters} declared adapters, " + "NDF L1/L2/L3 roles mapped" + ) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/chisel/chisel_env.sh b/tools/chisel/chisel_env.sh index 88fc56b9..419e0933 100755 --- a/tools/chisel/chisel_env.sh +++ b/tools/chisel/chisel_env.sh @@ -24,7 +24,7 @@ if ! command -v sbt >/dev/null 2>&1; then exit 2 fi -LINX_CHISEL_SBT_MEM_MB="${LINX_CHISEL_SBT_MEM_MB:-4096}" +LINX_CHISEL_SBT_MEM_MB="${LINX_CHISEL_SBT_MEM_MB:-2048}" if [[ ! "${LINX_CHISEL_SBT_MEM_MB}" =~ ^[1-9][0-9]*$ ]]; then echo "error: LINX_CHISEL_SBT_MEM_MB must be a positive integer" >&2 exit 2 diff --git a/tools/chisel/chisel_test_supervisor.py b/tools/chisel/chisel_test_supervisor.py new file mode 100755 index 00000000..503e8d14 --- /dev/null +++ b/tools/chisel/chisel_test_supervisor.py @@ -0,0 +1,491 @@ +#!/usr/bin/env python3 +"""Supervise one Chisel/SBT command with observable liveness diagnostics.""" + +from __future__ import annotations + +import argparse +import dataclasses +import json +import os +from pathlib import Path +import signal +import stat +import subprocess +import sys +import time +from typing import Sequence + + +HEARTBEAT_PREFIX = "linx-chisel-heartbeat " +SUMMARY_PREFIX = "linx-chisel-summary " + + +@dataclasses.dataclass(frozen=True) +class ArtifactSnapshot: + bytes: int + latest_mtime_ns: int + file_count: int + largest: tuple[tuple[str, int], ...] + + +@dataclasses.dataclass(frozen=True) +class SupervisorConfig: + heartbeat_seconds: int = 30 + stall_seconds: int = 600 + wall_seconds: int = 0 + low_cpu_percent: float = 1.0 + artifact_root: Path | None = None + artifact_budget_bytes: int = 0 + log_path: Path | None = None + selector: str = "all" + jobs: int = 1 + + +@dataclasses.dataclass(frozen=True) +class _ProcessSnapshot: + count: int = 0 + cpu_percent: float = 0.0 + rss_bytes: int = 0 + most_active_command: str = "" + + +def parse_positive_int(name: str, text: str) -> int: + try: + value = int(text) + except (TypeError, ValueError) as error: + raise ValueError(f"{name} must be a positive integer") from error + if value <= 0 or str(value) != str(text).strip().lstrip("+"): + raise ValueError(f"{name} must be a positive integer") + return value + + +def parse_non_negative_int(name: str, text: str) -> int: + try: + value = int(text) + except (TypeError, ValueError) as error: + raise ValueError(f"{name} must be a non-negative integer") from error + if value < 0 or str(value) != str(text).strip().lstrip("+"): + raise ValueError(f"{name} must be a non-negative integer") + return value + + +def snapshot_artifacts(root: Path | None) -> ArtifactSnapshot: + if root is None or not root.exists(): + return ArtifactSnapshot(0, 0, 0, ()) + + total_bytes = 0 + latest_mtime_ns = 0 + files: list[tuple[str, int]] = [] + for directory, _, names in os.walk(root, followlinks=False): + base = Path(directory) + for name in names: + path = base / name + try: + stat_result = path.stat(follow_symlinks=False) + except (FileNotFoundError, PermissionError, OSError): + continue + if not stat.S_ISREG(stat_result.st_mode): + continue + relative = path.relative_to(root).as_posix() + total_bytes += stat_result.st_size + latest_mtime_ns = max(latest_mtime_ns, stat_result.st_mtime_ns) + files.append((relative, stat_result.st_size)) + + files.sort(key=lambda entry: (-entry[1], entry[0])) + return ArtifactSnapshot( + bytes=total_bytes, + latest_mtime_ns=latest_mtime_ns, + file_count=len(files), + largest=tuple(files[:5]), + ) + + +def _snapshot_processes(root_pid: int) -> _ProcessSnapshot: + try: + result = subprocess.run( + ["ps", "-axo", "pid=,ppid=,%cpu=,rss=,command="], + check=False, + capture_output=True, + text=True, + ) + except OSError: + return _ProcessSnapshot() + + rows: dict[int, tuple[int, float, int, str]] = {} + children: dict[int, list[int]] = {} + for line in result.stdout.splitlines(): + fields = line.strip().split(None, 4) + if len(fields) != 5: + continue + try: + pid = int(fields[0]) + ppid = int(fields[1]) + cpu = float(fields[2]) + rss_kib = int(fields[3]) + except ValueError: + continue + rows[pid] = (ppid, cpu, rss_kib * 1024, fields[4]) + children.setdefault(ppid, []).append(pid) + + descendants: set[int] = set() + pending = [root_pid] + while pending: + pid = pending.pop() + if pid in descendants: + continue + descendants.add(pid) + pending.extend(children.get(pid, ())) + + selected = [(pid, rows[pid]) for pid in descendants if pid in rows] + if not selected: + return _ProcessSnapshot() + most_active = max(selected, key=lambda entry: (entry[1][1], entry[0])) + return _ProcessSnapshot( + count=len(selected), + cpu_percent=sum(row[1] for _, row in selected), + rss_bytes=sum(row[2] for _, row in selected), + most_active_command=most_active[1][3], + ) + + +def _classify_phase(processes: _ProcessSnapshot, recent_output: str) -> str: + command = processes.most_active_command.lower() + output = recent_output.lower() + combined = f"{command}\n{output}" + if "verilator_bin" in command or "v3split" in combined: + return "verilation" + if any(token in command for token in ("clang++", "g++", "c++", " cc ")): + return "cxx-build" + if "make " in command and "verilated-sources" in command: + return "cxx-build" + if "simulation" in command and "verilator" not in command: + return "simulation" + if "firtool" in combined or "firrtl" in output: + return "firrtl" + if "elaborat" in output or "chiselsim" in combined: + return "elaboration" + if "scalac" in command or "compiling" in output: + return "scala-compile" + if "sbt" in combined or "java" in command: + return "sbt" + return "result" + + +def _artifact_payload(snapshot: ArtifactSnapshot) -> list[dict[str, object]]: + return [{"path": path, "bytes": size} for path, size in snapshot.largest] + + +def _record( + config: SupervisorConfig, + start: float, + now: float, + last_output: float, + last_artifact: float, + artifacts: ArtifactSnapshot, + processes: _ProcessSnapshot, + peak_rss_bytes: int, + recent_output: str, +) -> dict[str, object]: + return { + "selector": config.selector, + "jobs": config.jobs, + "phase": _classify_phase(processes, recent_output), + "elapsed_seconds": round(now - start, 3), + "output_quiet_seconds": round(now - last_output, 3), + "artifact_quiet_seconds": round(now - last_artifact, 3), + "artifact_bytes": artifacts.bytes, + "artifact_files": artifacts.file_count, + "process_count": processes.count, + "cpu_percent": round(processes.cpu_percent, 2), + "rss_bytes": processes.rss_bytes, + "peak_rss_bytes": peak_rss_bytes, + "most_active_command": processes.most_active_command, + } + + +def _emit(prefix: str, payload: dict[str, object]) -> None: + print(prefix + json.dumps(payload, sort_keys=True), flush=True) + + +def _signal_process_group(process: subprocess.Popen[bytes], signum: int) -> None: + try: + os.killpg(process.pid, signum) + except ProcessLookupError: + return + + +def _stop_process_group( + process: subprocess.Popen[bytes], signum: int, grace_seconds: float = 5.0 +) -> int: + _signal_process_group(process, signum) + deadline = time.monotonic() + grace_seconds + while process.poll() is None and time.monotonic() < deadline: + time.sleep(0.05) + if process.poll() is None: + _signal_process_group(process, signal.SIGKILL) + try: + return process.wait(timeout=1) + except subprocess.TimeoutExpired: + return -signal.SIGKILL + + +def supervise(config: SupervisorConfig, command: Sequence[str]) -> int: + if not command: + raise ValueError("supervised command must not be empty") + if config.heartbeat_seconds <= 0: + raise ValueError("heartbeat_seconds must be positive") + if config.stall_seconds < 0 or config.wall_seconds < 0: + raise ValueError("stall_seconds and wall_seconds must be non-negative") + if config.low_cpu_percent < 0: + raise ValueError("low_cpu_percent must be non-negative") + if config.artifact_budget_bytes < 0: + raise ValueError("artifact_budget_bytes must be non-negative") + if config.jobs <= 0: + raise ValueError("jobs must be positive") + + log_stream = None + if config.log_path is not None: + config.log_path.parent.mkdir(parents=True, exist_ok=True) + log_stream = config.log_path.open("w", encoding="utf-8") + + process = subprocess.Popen( + list(command), + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + start_new_session=True, + bufsize=0, + ) + assert process.stdout is not None + os.set_blocking(process.stdout.fileno(), False) + + caught_signal = 0 + + def catch_signal(signum: int, _frame: object) -> None: + nonlocal caught_signal + caught_signal = signum + + previous_handlers: dict[int, object] = {} + for signum in (signal.SIGINT, signal.SIGTERM): + previous_handlers[signum] = signal.getsignal(signum) + signal.signal(signum, catch_signal) + + start = time.monotonic() + now = start + next_heartbeat = start + config.heartbeat_seconds + probe_interval = min(1.0, max(0.2, config.heartbeat_seconds / 4.0)) + next_probe = start + probe_interval + last_output = start + last_artifact = start + last_cpu_active = start + artifacts = snapshot_artifacts(config.artifact_root) + processes = _snapshot_processes(process.pid) + peak_rss_bytes = processes.rss_bytes + recent_output = "" + reason = "child-exit" + return_status: int | None = None + + try: + while True: + while True: + try: + chunk = os.read(process.stdout.fileno(), 65536) + except BlockingIOError: + break + if not chunk: + break + text = chunk.decode("utf-8", errors="replace") + sys.stdout.write(text) + sys.stdout.flush() + if log_stream is not None: + log_stream.write(text) + log_stream.flush() + recent_output = (recent_output + text)[-8192:] + last_output = time.monotonic() + + now = time.monotonic() + if now >= next_probe: + current_artifacts = snapshot_artifacts(config.artifact_root) + if ( + current_artifacts.bytes != artifacts.bytes + or current_artifacts.latest_mtime_ns != artifacts.latest_mtime_ns + or current_artifacts.file_count != artifacts.file_count + ): + last_artifact = now + artifacts = current_artifacts + + current_processes = _snapshot_processes(process.pid) + if current_processes.count: + processes = current_processes + peak_rss_bytes = max(peak_rss_bytes, processes.rss_bytes) + if processes.cpu_percent >= config.low_cpu_percent: + last_cpu_active = now + while next_probe <= now: + next_probe += probe_interval + + if now >= next_heartbeat: + _emit( + HEARTBEAT_PREFIX, + _record( + config, + start, + now, + last_output, + last_artifact, + artifacts, + processes, + peak_rss_bytes, + recent_output, + ), + ) + while next_heartbeat <= now: + next_heartbeat += config.heartbeat_seconds + + child_status = process.poll() + if child_status is not None: + return_status = child_status + reason = "child-exit" + break + + if caught_signal: + _stop_process_group(process, caught_signal) + return_status = 128 + caught_signal + reason = "signal" + break + + if config.wall_seconds and now - start >= config.wall_seconds: + _stop_process_group(process, signal.SIGTERM) + return_status = 124 + reason = "wall-limit" + break + + if config.stall_seconds and min( + now - last_output, + now - last_artifact, + now - last_cpu_active, + ) >= config.stall_seconds: + _stop_process_group(process, signal.SIGTERM) + return_status = 124 + reason = "idle-stall" + break + + time.sleep(0.05) + + while True: + try: + chunk = os.read(process.stdout.fileno(), 65536) + except BlockingIOError: + break + if not chunk: + break + text = chunk.decode("utf-8", errors="replace") + sys.stdout.write(text) + sys.stdout.flush() + if log_stream is not None: + log_stream.write(text) + log_stream.flush() + recent_output = (recent_output + text)[-8192:] + last_output = time.monotonic() + + now = time.monotonic() + artifacts = snapshot_artifacts(config.artifact_root) + final_processes = _snapshot_processes(process.pid) + if final_processes.count: + processes = final_processes + peak_rss_bytes = max(peak_rss_bytes, processes.rss_bytes) + if ( + return_status == 0 + and config.artifact_budget_bytes + and artifacts.bytes > config.artifact_budget_bytes + ): + return_status = 2 + reason = "artifact-budget" + + summary = _record( + config, + start, + now, + last_output, + last_artifact, + artifacts, + processes, + peak_rss_bytes, + recent_output, + ) + summary.update( + { + "reason": reason, + "child_status": process.poll(), + "return_status": return_status, + "artifact_budget_bytes": config.artifact_budget_bytes, + "largest_artifacts": _artifact_payload(artifacts), + } + ) + _emit(SUMMARY_PREFIX, summary) + assert return_status is not None + return return_status + finally: + if process.poll() is None: + _stop_process_group(process, signal.SIGTERM) + for signum, handler in previous_handlers.items(): + signal.signal(signum, handler) + process.stdout.close() + if log_stream is not None: + log_stream.close() + + +def _parser() -> argparse.ArgumentParser: + parser = argparse.ArgumentParser( + description="Supervise one Chisel test command with heartbeats") + parser.add_argument("--heartbeat-seconds", default="30") + parser.add_argument("--stall-seconds", default="600") + parser.add_argument("--wall-seconds", default="0") + parser.add_argument("--low-cpu-percent", default="1.0") + parser.add_argument("--artifact-root", type=Path) + parser.add_argument("--artifact-budget-bytes", default="0") + parser.add_argument("--log", dest="log_path", type=Path) + parser.add_argument("--selector", default="all") + parser.add_argument("--jobs", default="1") + parser.add_argument("command", nargs=argparse.REMAINDER) + return parser + + +def main(argv: Sequence[str] | None = None) -> int: + parser = _parser() + args = parser.parse_args(argv) + command = list(args.command) + if command and command[0] == "--": + command.pop(0) + if not command: + parser.error("a command is required after --") + try: + heartbeat_seconds = parse_positive_int( + "heartbeat seconds", args.heartbeat_seconds) + stall_seconds = parse_non_negative_int("stall seconds", args.stall_seconds) + wall_seconds = parse_non_negative_int("wall seconds", args.wall_seconds) + artifact_budget_bytes = parse_non_negative_int( + "artifact budget bytes", args.artifact_budget_bytes) + jobs = parse_positive_int("jobs", args.jobs) + low_cpu_percent = float(args.low_cpu_percent) + if low_cpu_percent < 0: + raise ValueError("low CPU percent must be non-negative") + except ValueError as error: + parser.error(str(error)) + + return supervise( + SupervisorConfig( + heartbeat_seconds=heartbeat_seconds, + stall_seconds=stall_seconds, + wall_seconds=wall_seconds, + low_cpu_percent=low_cpu_percent, + artifact_root=args.artifact_root, + artifact_budget_bytes=artifact_budget_bytes, + log_path=args.log_path, + selector=args.selector, + jobs=jobs, + ), + command, + ) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/chisel/classify_task15_warning_matrix.py b/tools/chisel/classify_task15_warning_matrix.py new file mode 100755 index 00000000..92c5dbbf --- /dev/null +++ b/tools/chisel/classify_task15_warning_matrix.py @@ -0,0 +1,80 @@ +#!/usr/bin/env python3 +"""Classify the bounded Task-15 W2/W4/W6/W8 elaboration warning matrix.""" + +from __future__ import annotations + +import re +import sys +from pathlib import Path + + +WIDTHS = ("W2", "W4", "W6", "W8") +# No warning is accepted by default. Add an entry only for a narrowly scoped, +# reviewed warning whose exact code is unavoidable and documented. +ALLOWLIST_CODES: set[str] = set() +MARKER = re.compile(r"TASK15_WARNING_MATRIX_(BEGIN|END) (W[2468])") +WARNING = re.compile(r"\[(W\d{3})\]") + + +def classify(text: str) -> tuple[dict[str, list[str]], list[str]]: + active: str | None = None + sections = {width: [] for width in WIDTHS} + outside: list[str] = [] + seen_begin: set[str] = set() + seen_end: set[str] = set() + + for line in text.splitlines(): + marker = MARKER.search(line) + if marker: + action, width = marker.groups() + if action == "BEGIN": + if active is not None: + raise ValueError(f"nested matrix marker: {line}") + active = width + seen_begin.add(width) + else: + if active != width: + raise ValueError(f"unmatched matrix marker: {line}") + seen_end.add(width) + active = None + continue + if WARNING.search(line): + (sections[active] if active else outside).append(line) + + missing = [width for width in WIDTHS if width not in seen_begin or width not in seen_end] + if missing: + raise ValueError("missing completed matrix sections: " + ", ".join(missing)) + if active is not None: + raise ValueError(f"unterminated matrix section: {active}") + return sections, outside + + +def main() -> int: + if len(sys.argv) != 2: + raise SystemExit(f"usage: {Path(sys.argv[0]).name} ") + try: + sections, outside = classify(Path(sys.argv[1]).read_text(encoding="utf-8")) + except (OSError, ValueError) as error: + print(f"error: {error}", file=sys.stderr) + return 2 + + failed = False + for width in WIDTHS: + codes = [WARNING.search(line).group(1) for line in sections[width]] + allowed = [code for code in codes if code in ALLOWLIST_CODES] + rejected = [code for code in codes if code not in ALLOWLIST_CODES] + status = "fail" if rejected else "pass" + failed |= bool(rejected) + print( + f"task15-warning-matrix width={width} status={status} " + f"rejected={','.join(rejected) or 'none'} " + f"allowed={','.join(allowed) or 'none'}" + ) + outside_codes = [WARNING.search(line).group(1) for line in outside] + print(f"task15-warning-matrix outside={','.join(outside_codes) or 'none'}") + failed |= any(code not in ALLOWLIST_CODES for code in outside_codes) + return 1 if failed else 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/chisel/emit_verilog.sh b/tools/chisel/emit_verilog.sh index 77126d8f..36028974 100755 --- a/tools/chisel/emit_verilog.sh +++ b/tools/chisel/emit_verilog.sh @@ -5,5 +5,9 @@ ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" CHISEL_DIR="${ROOT_DIR}/chisel" bash "${ROOT_DIR}/tools/chisel/build_chisel.sh" +source "${ROOT_DIR}/tools/chisel/chisel_env.sh" cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.Elaborate" +LINX_TOP_WIDTH="${LINX_TOP_WIDTH:-4}" \ +LINX_TOP_SIMULATION_PROFILE="${LINX_TOP_SIMULATION_PROFILE:-1}" \ +sbt --server --batch --no-colors --mem "${LINX_CHISEL_SBT_MEM_MB}" \ + "runMain linxcore.top.EmitTOP --target-dir ${ROOT_DIR}/generated/chisel-verilog" diff --git a/tools/chisel/find_replay_liq_qemu_candidates.py b/tools/chisel/find_replay_liq_qemu_candidates.py deleted file mode 100644 index 1038dcbd..00000000 --- a/tools/chisel/find_replay_liq_qemu_candidates.py +++ /dev/null @@ -1,451 +0,0 @@ -#!/usr/bin/env python3 -"""Find QEMU memory-row clusters that may be useful replay-LIQ probes. - -This is a locator, not a proof. It scans QEMU-shaped commit rows for nearby -store/load address overlap and same-cacheline memory reuse so a later generated -RTL run can target a concrete CoreMark window with replay-LIQ sidebands. -""" - -from __future__ import annotations - -import argparse -import json -import sys -from dataclasses import dataclass -from pathlib import Path -from typing import Any, Iterable - - -@dataclass(frozen=True) -class MemoryEvent: - row: int - cycle: int - pc: int - insn: int - is_store: bool - addr: int - size: int - data: int - - @property - def end(self) -> int: - return self.addr + max(self.size, 0) - - @property - def line(self) -> int: - return self.addr // 64 - - -def parse_int(value: Any, default: int = 0) -> int: - if value is None: - return default - if isinstance(value, bool): - return int(value) - if isinstance(value, int): - return value - if isinstance(value, str): - return int(value, 0) - raise ValueError(f"unsupported integer value {value!r}") - - -def load_events(path: Path) -> list[MemoryEvent]: - events: list[MemoryEvent] = [] - with path.open("r", encoding="utf-8") as f: - for line_no, line in enumerate(f, 1): - if not line.strip(): - continue - row = json.loads(line) - if not isinstance(row, dict): - raise ValueError(f"{path}:{line_no}: expected JSON object") - if parse_int(row.get("mem_valid"), 0) == 0: - continue - is_store = parse_int(row.get("mem_is_store"), 0) != 0 - data_key = "mem_wdata" if is_store else "mem_rdata" - events.append( - MemoryEvent( - row=line_no - 1, - cycle=parse_int(row.get("cycle"), line_no - 1), - pc=parse_int(row.get("pc")), - insn=parse_int(row.get("insn")), - is_store=is_store, - addr=parse_int(row.get("mem_addr")), - size=parse_int(row.get("mem_size")), - data=parse_int(row.get(data_key), 0), - ) - ) - return events - - -def ranges_overlap(a: MemoryEvent, b: MemoryEvent) -> bool: - return a.addr < b.end and b.addr < a.end - - -def candidate_score(kind: str, first: MemoryEvent, second: MemoryEvent, distance: int) -> int: - score = 0 - if ranges_overlap(first, second): - score += 1000 - if first.line == second.line: - score += 100 - if kind == "store_before_load": - score += 50 - else: - score += 35 - if first.pc == second.pc: - score += 20 - score += max(0, 40 - min(distance, 40)) - return score - - -def find_candidates( - events: list[MemoryEvent], - *, - lookback_rows: int, - same_line: bool, - min_second_row: int, - max_second_row: int, - dedupe_pairs: bool, -) -> list[dict[str, Any]]: - out: list[dict[str, Any]] = [] - for index, event in enumerate(events): - if event.row < min_second_row: - continue - if max_second_row >= 0 and event.row > max_second_row: - continue - for prior in reversed(events[:index]): - distance = event.row - prior.row - if distance > lookback_rows: - break - if not same_line and not ranges_overlap(prior, event): - continue - if same_line and prior.line != event.line and not ranges_overlap(prior, event): - continue - if prior.is_store and not event.is_store: - kind = "store_before_load" - elif not prior.is_store and event.is_store: - kind = "load_before_store" - else: - continue - exact = ranges_overlap(prior, event) - line_match = prior.line == event.line - out.append( - { - "kind": kind, - "score": candidate_score(kind, prior, event, distance), - "exact_overlap": exact, - "same_line": line_match, - "row_distance": distance, - "first": event_dict(prior), - "second": event_dict(event), - "pc_lo": min(prior.pc, event.pc), - "pc_hi": max(prior.pc, event.pc) + 1, - } - ) - out.sort( - key=lambda item: ( - int(item["score"]), - int(item["exact_overlap"]), - -int(item["row_distance"]), - -int(item["second"]["row"]), - ), - reverse=True, - ) - if dedupe_pairs: - unique: list[dict[str, Any]] = [] - seen: set[tuple[Any, ...]] = set() - for item in out: - first = item["first"] - second = item["second"] - first_loc = first["addr"] if item["exact_overlap"] else first["line"] - second_loc = second["addr"] if item["exact_overlap"] else second["line"] - key = (item["kind"], first["pc"], second["pc"], first_loc, second_loc) - if key in seen: - continue - seen.add(key) - unique.append(item) - out = unique - return out - - -def event_key(event: MemoryEvent) -> tuple[int, int, bool, int, int, int]: - return (event.pc, event.insn, event.is_store, event.addr, event.size, event.data) - - -def raw_row_mapping(events: list[MemoryEvent], raw_events: list[MemoryEvent]) -> dict[int, int]: - raw_by_key: dict[tuple[int, int, bool, int, int, int], list[int]] = {} - for raw in raw_events: - raw_by_key.setdefault(event_key(raw), []).append(raw.row) - - next_index: dict[tuple[int, int, bool, int, int, int], int] = {} - out: dict[int, int] = {} - for event in events: - key = event_key(event) - index = next_index.get(key, 0) - raw_rows = raw_by_key.get(key, []) - if index < len(raw_rows): - out[event.row] = raw_rows[index] - next_index[key] = index + 1 - return out - - -def event_dict(event: MemoryEvent) -> dict[str, Any]: - return { - "row": event.row, - "cycle": event.cycle, - "pc": f"0x{event.pc:x}", - "insn": f"0x{event.insn:x}", - "op": "store" if event.is_store else "load", - "addr": f"0x{event.addr:x}", - "size": event.size, - "line": f"0x{event.line:x}", - "data": f"0x{event.data:x}", - } - - -def pc_histogram(events: Iterable[MemoryEvent]) -> list[dict[str, Any]]: - buckets: dict[tuple[int, bool], dict[str, Any]] = {} - for event in events: - key = (event.pc, event.is_store) - bucket = buckets.setdefault( - key, - { - "pc": f"0x{event.pc:x}", - "op": "store" if event.is_store else "load", - "count": 0, - "first_row": event.row, - "last_row": event.row, - }, - ) - bucket["count"] += 1 - bucket["last_row"] = event.row - rows = list(buckets.values()) - rows.sort(key=lambda item: (int(item["count"]), int(item["last_row"])), reverse=True) - return rows - - -def candidate_probe_hint( - candidate: dict[str, Any], - *, - row_space: str, - raw_rows_by_event_row: dict[int, int], -) -> dict[str, Any]: - first = candidate["first"] - second = candidate["second"] - first_row = int(first["row"]) - second_row = int(second["row"]) - pc_lo = int(candidate["pc_lo"]) - pc_hi = int(candidate["pc_hi"]) - stores = [first["pc"] if first["op"] == "store" else second["pc"]] - loads = [first["pc"] if first["op"] == "load" else second["pc"]] - hint: dict[str, Any] = { - "row_space": row_space, - "input_window": { - "start_row": first_row, - "end_row": second_row, - "capture_rows": second_row - first_row + 1, - }, - "pc_filter": { - "pc_lo": f"0x{pc_lo:x}", - "pc_hi": f"0x{pc_hi:x}", - "args": ["--pc-lo", f"0x{pc_lo:x}", "--pc-hi", f"0x{pc_hi:x}"], - "caveat": ( - "PC filtering can select an earlier dynamic occurrence of the same PC range. " - "Run a QEMU-only preflight with expected memory PCs before spending generated-RTL time." - ), - }, - "expected_memory_pcs": { - "store_pcs": stores, - "load_pcs": loads, - "args": ["--expect-store-pcs", ",".join(stores), "--expect-load-pcs", ",".join(loads)], - }, - } - if first_row in raw_rows_by_event_row and second_row in raw_rows_by_event_row: - raw_first = raw_rows_by_event_row[first_row] - raw_second = raw_rows_by_event_row[second_row] - hint["raw_dynamic_window"] = { - "qemu_skip_rows": raw_first, - "capture_rows": raw_second - raw_first + 1, - "args": ["--qemu-skip-rows", str(raw_first), "--capture-rows", str(raw_second - raw_first + 1)], - "claim_boundary": ( - "This reproduces the dynamic QEMU window only. Skipped raw rows are not " - "generated-RTL replacement evidence because the reduced DUT cannot " - "reconstruct skipped architectural state." - ), - } - else: - hint["raw_dynamic_window_unavailable"] = ( - "Candidate rows are not known raw QEMU row indices. Pass --raw-input with " - "the matching qemu.live.raw.jsonl before using --qemu-skip-rows." - ) - return hint - - -def annotate_candidates( - candidates: list[dict[str, Any]], - *, - top: int, - row_space: str, - raw_rows_by_event_row: dict[int, int], -) -> list[dict[str, Any]]: - annotated: list[dict[str, Any]] = [] - for item in candidates[:top]: - row = dict(item) - row["probe_hint"] = candidate_probe_hint( - item, - row_space=row_space, - raw_rows_by_event_row=raw_rows_by_event_row, - ) - annotated.append(row) - return annotated - - -def write_summary( - events: list[MemoryEvent], - candidates: list[dict[str, Any]], - top: int, - *, - row_space: str = "unknown", - raw_rows_by_event_row: dict[int, int] | None = None, -) -> dict[str, Any]: - store_count = sum(1 for event in events if event.is_store) - load_count = len(events) - store_count - raw_rows = raw_rows_by_event_row or {} - return { - "schema": "linxcore.replay_liq_qemu_candidate_locator.v1", - "row_space": row_space, - "event_count": len(events), - "store_count": store_count, - "load_count": load_count, - "candidate_count": len(candidates), - "claim_boundary": ( - "QEMU address clusters are candidate-selection hints only; replay-LIQ " - "evidence still requires generated-RTL sideband counters and a passing " - "QEMU/DUT comparator manifest." - ), - "top_candidates": annotate_candidates( - candidates, - top=top, - row_space=row_space, - raw_rows_by_event_row=raw_rows, - ), - "memory_pc_histogram": pc_histogram(events)[:top], - } - - -def run_self_test() -> None: - rows = [ - {"pc": 0x1000, "insn": 1, "mem_valid": 1, "mem_is_store": 1, "mem_addr": 0x2000, "mem_size": 8, "mem_wdata": 0xAA}, - {"pc": 0x1004, "insn": 2, "mem_valid": 1, "mem_is_store": 0, "mem_addr": 0x2000, "mem_size": 8, "mem_rdata": 0xAA}, - {"pc": 0x1008, "insn": 3, "mem_valid": 1, "mem_is_store": 0, "mem_addr": 0x2040, "mem_size": 8, "mem_rdata": 0}, - {"pc": 0x100C, "insn": 4, "mem_valid": 1, "mem_is_store": 1, "mem_addr": 0x2044, "mem_size": 4, "mem_wdata": 1}, - ] - tmp = Path("/tmp/linxcore-replay-liq-qemu-candidate-selftest.jsonl") - with tmp.open("w", encoding="utf-8") as f: - for row in rows: - f.write(json.dumps(row) + "\n") - events = load_events(tmp) - candidates = find_candidates( - events, - lookback_rows=8, - same_line=True, - min_second_row=0, - max_second_row=-1, - dedupe_pairs=True, - ) - if len(events) != 4: - raise AssertionError("self-test did not load memory events") - if not candidates: - raise AssertionError("self-test did not find candidates") - if candidates[0]["kind"] != "store_before_load" or not candidates[0]["exact_overlap"]: - raise AssertionError("self-test top candidate is not the exact store/load pair") - summary = write_summary( - events, - candidates, - 1, - row_space="raw", - raw_rows_by_event_row={event.row: event.row for event in events}, - ) - raw_window = summary["top_candidates"][0]["probe_hint"].get("raw_dynamic_window") - if raw_window is None or raw_window["qemu_skip_rows"] != 0 or raw_window["capture_rows"] != 2: - raise AssertionError("self-test did not annotate the raw dynamic window") - tmp.unlink(missing_ok=True) - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--input", type=Path, help="QEMU raw or reduced expected JSONL") - parser.add_argument( - "--raw-input", - type=Path, - default=None, - help="matching qemu.live.raw.jsonl used to annotate reduced-preview candidates with raw row windows", - ) - parser.add_argument("--output", type=Path, help="write JSON summary to this path") - parser.add_argument("--top", type=int, default=20, help="number of candidates to print/write") - parser.add_argument("--lookback-rows", type=int, default=512, help="maximum row distance between paired memory events") - parser.add_argument("--min-second-row", type=int, default=0, help="ignore candidates whose later memory row is before this raw/reduced row") - parser.add_argument("--max-second-row", type=int, default=-1, help="ignore candidates whose later memory row is after this raw/reduced row") - parser.add_argument("--exact-overlap-only", action="store_true", help="ignore same-line-only candidates") - parser.add_argument("--no-dedupe-pairs", action="store_true", help="show repeated dynamic instances of the same PC/address-pair shape") - parser.add_argument("--self-test", action="store_true", help="run built-in checks") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-qemu-candidate-locator self-test: ok") - if args.input is None: - return 0 - if args.input is None: - raise SystemExit("error: --input is required unless --self-test is the only action") - events = load_events(args.input) - row_space = "raw" if args.input.name == "qemu.live.raw.jsonl" else "reduced" - raw_rows_by_event_row: dict[int, int] = {} - if args.raw_input is not None: - raw_rows_by_event_row = raw_row_mapping(events, load_events(args.raw_input)) - elif row_space == "raw": - raw_rows_by_event_row = {event.row: event.row for event in events} - candidates = find_candidates( - events, - lookback_rows=args.lookback_rows, - same_line=not args.exact_overlap_only, - min_second_row=args.min_second_row, - max_second_row=args.max_second_row, - dedupe_pairs=not args.no_dedupe_pairs, - ) - summary = write_summary( - events, - candidates, - args.top, - row_space=row_space, - raw_rows_by_event_row=raw_rows_by_event_row, - ) - if args.output: - args.output.parent.mkdir(parents=True, exist_ok=True) - with args.output.open("w", encoding="utf-8") as f: - json.dump(summary, f, indent=2, sort_keys=True) - f.write("\n") - print( - "replay-liq-qemu-candidates " - f"events={summary['event_count']} stores={summary['store_count']} " - f"loads={summary['load_count']} candidates={summary['candidate_count']}" - ) - for item in summary["top_candidates"]: - first = item["first"] - second = item["second"] - raw_window = item.get("probe_hint", {}).get("raw_dynamic_window") - raw_filter = "" - if isinstance(raw_window, dict): - raw_filter = f" raw_skip={raw_window['qemu_skip_rows']} raw_capture={raw_window['capture_rows']}" - print( - f"score={item['score']} kind={item['kind']} exact={int(item['exact_overlap'])} " - f"same_line={int(item['same_line'])} rows={first['row']}->{second['row']} " - f"pcs={first['pc']}->{second['pc']} addrs={first['addr']}->{second['addr']} " - f"pc_filter={hex(int(item['pc_lo']))}..{hex(int(item['pc_hi']))}{raw_filter}" - ) - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/frontend_alu_trace_top_tb.cpp b/tools/chisel/frontend_alu_trace_top_tb.cpp deleted file mode 100644 index 1ba44919..00000000 --- a/tools/chisel/frontend_alu_trace_top_tb.cpp +++ /dev/null @@ -1,679 +0,0 @@ -#ifdef LINXCORE_RF_ALU_TRACE_TOP -#include "VLinxCoreFrontendRfAluTraceTop.h" -using Dut = VLinxCoreFrontendRfAluTraceTop; -#else -#include "VLinxCoreFrontendAluTraceTop.h" -using Dut = VLinxCoreFrontendAluTraceTop; -#endif -#include "verilated.h" - -#include "commit_trace_jsonl.h" - -#include -#include -#include -#include -#include -#include - -namespace { - -using linxcore::chisel::CommitTraceJsonRow; -using linxcore::chisel::write_dut_commit_jsonl; -using linxcore::chisel::write_qemu_commit_jsonl; - -struct Args { - std::string dut_trace; - std::string qemu_trace; -}; - -struct ExpectedRow { - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 4; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; -}; - -struct ObservedRow { - bool valid = false; - std::uint64_t seq = 0; - std::uint64_t cycle = 0; - std::uint8_t slot = 0; - std::uint32_t bid = 0; - std::uint32_t gid = 0; - std::uint32_t rid = 0; - bool rob_valid = false; - bool rob_wrap = false; - std::uint8_t rob_value = 0; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 0; - bool wb_valid = false; - std::uint8_t wb_reg = 0; - std::uint64_t wb_data = 0; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; - bool mem_valid = false; - bool mem_is_store = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint8_t mem_size = 0; - bool trap_valid = false; - std::uint32_t trap_cause = 0; - std::uint64_t trap_arg0 = 0; - std::uint64_t next_pc = 0; -}; - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --dut-trace --qemu-trace \n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--dut-trace" && i + 1 < argc) { - args.dut_trace = argv[++i]; - } else if (arg == "--qemu-trace" && i + 1 < argc) { - args.qemu_trace = argv[++i]; - } else { - usage(argv[0]); - } - } - if (args.dut_trace.empty() || args.qemu_trace.empty()) { - usage(argv[0]); - } - return args; -} - -std::uint64_t mask_insn(std::uint64_t insn, std::uint8_t len) { - if (len == 2) { - return insn & 0xffffULL; - } - if (len == 4) { - return insn & 0xffff'ffffULL; - } - if (len == 6) { - return insn & 0xffff'ffff'ffffULL; - } - return insn; -} - -void clear_inputs(Dut &dut) { - dut.io_in_valid = 0; - dut.io_in_peId = 0; - dut.io_in_threadId = 0; - dut.io_in_pc = 0; - dut.io_in_window = 0; - dut.io_in_pktUid = 0; - dut.io_in_checkpointId = 0; -#ifdef LINXCORE_RF_ALU_TRACE_TOP - dut.io_rfInitValid = 0; - dut.io_rfInitArchTag = 0; - dut.io_rfInitData = 0; -#else - dut.io_operandData_0 = 0; - dut.io_operandData_1 = 0; - dut.io_operandData_2 = 0; -#endif - dut.io_frontendFlushValid = 0; - dut.io_deallocReady = 1; -} - -void drive_operands(Dut &dut, const ExpectedRow &row) { -#ifdef LINXCORE_RF_ALU_TRACE_TOP - (void)dut; - (void)row; -#else - dut.io_operandData_0 = row.src0_data; - dut.io_operandData_1 = row.src1_data; - dut.io_operandData_2 = 0; -#endif -} - -void tick(Dut &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); -} - -void reset(Dut &dut) { - clear_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - dut.eval(); -} - -#ifdef LINXCORE_RF_ALU_TRACE_TOP -void init_rf(Dut &dut, std::uint8_t arch_tag, std::uint64_t data) { - clear_inputs(dut); - dut.io_rfInitValid = 1; - dut.io_rfInitArchTag = arch_tag; - dut.io_rfInitData = data; - tick(dut); - clear_inputs(dut); - dut.eval(); -} -#endif - -void expect_monitor_clean( - const Dut &dut, - const char *context, - std::uint8_t expected_mask, - std::uint8_t expected_count) { - if (dut.io_commitContractError || dut.io_commitSkippedSlot || - dut.io_commitDuplicateIdentity || dut.io_commitSlotMismatch || - dut.io_commitInvalidSideEffect) { - std::cerr << "commit monitor error during " << context - << " mask=" << static_cast(dut.io_commitMonitorValidMask) - << " count=" << static_cast(dut.io_commitMonitorValidCount) - << " skipped=" << static_cast(dut.io_commitSkippedSlot) - << " duplicate=" << static_cast(dut.io_commitDuplicateIdentity) - << " slot_mismatch=" << static_cast(dut.io_commitSlotMismatch) - << " invalid_side_effect=" << static_cast(dut.io_commitInvalidSideEffect) - << "\n"; - std::exit(1); - } - if (dut.io_commitMonitorValidMask != expected_mask || - dut.io_commitMonitorValidCount != expected_count) { - std::cerr << "commit monitor shape mismatch during " << context - << " expected_mask=" << static_cast(expected_mask) - << " observed_mask=" << static_cast(dut.io_commitMonitorValidMask) - << " expected_count=" << static_cast(expected_count) - << " observed_count=" << static_cast(dut.io_commitMonitorValidCount) - << "\n"; - std::exit(1); - } -} - -ObservedRow read_slot0(const Dut &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_0_valid; - row.seq = dut.io_commit_rows_0_seq; - row.cycle = dut.io_commit_rows_0_cycle; - row.slot = dut.io_commit_rows_0_slot; - row.bid = dut.io_commit_rows_0_identity_bid; - row.gid = dut.io_commit_rows_0_identity_gid; - row.rid = dut.io_commit_rows_0_identity_rid; - row.rob_valid = dut.io_commit_rows_0_rob_valid; - row.rob_wrap = dut.io_commit_rows_0_rob_wrap; - row.rob_value = dut.io_commit_rows_0_rob_value; - row.block_bid_valid = dut.io_commit_rows_0_blockBidValid; - row.block_bid = dut.io_commit_rows_0_blockBid; - row.pc = dut.io_commit_rows_0_pc; - row.insn = dut.io_commit_rows_0_insn; - row.len = dut.io_commit_rows_0_len; - row.wb_valid = dut.io_commit_rows_0_wb_valid; - row.wb_reg = dut.io_commit_rows_0_wb_reg; - row.wb_data = dut.io_commit_rows_0_wb_data; - row.src0_valid = dut.io_commit_rows_0_src0_valid; - row.src0_reg = dut.io_commit_rows_0_src0_reg; - row.src0_data = dut.io_commit_rows_0_src0_data; - row.src1_valid = dut.io_commit_rows_0_src1_valid; - row.src1_reg = dut.io_commit_rows_0_src1_reg; - row.src1_data = dut.io_commit_rows_0_src1_data; - row.dst_valid = dut.io_commit_rows_0_dst_valid; - row.dst_reg = dut.io_commit_rows_0_dst_reg; - row.dst_data = dut.io_commit_rows_0_dst_data; - row.mem_valid = dut.io_commit_rows_0_mem_valid; - row.mem_is_store = dut.io_commit_rows_0_mem_isStore; - row.mem_addr = dut.io_commit_rows_0_mem_addr; - row.mem_wdata = dut.io_commit_rows_0_mem_wdata; - row.mem_rdata = dut.io_commit_rows_0_mem_rdata; - row.mem_size = dut.io_commit_rows_0_mem_size; - row.trap_valid = dut.io_commit_rows_0_trap_valid; - row.trap_cause = dut.io_commit_rows_0_trap_cause; - row.trap_arg0 = dut.io_commit_rows_0_trap_arg0; - row.next_pc = dut.io_commit_rows_0_nextPc; - return row; -} - -bool slot1_valid(const Dut &dut) { - return dut.io_commit_rows_1_valid; -} - -void expect_row(const ObservedRow &observed, const ExpectedRow &expected) { - if (!observed.valid || - observed.slot != 0 || - observed.pc != expected.pc || - mask_insn(observed.insn, observed.len) != mask_insn(expected.insn, expected.len) || - observed.len != expected.len || - observed.mem_valid || - observed.trap_valid || - observed.src0_valid != expected.src0_valid || - observed.src1_valid != expected.src1_valid || - observed.dst_valid != expected.dst_valid || - observed.wb_valid != expected.dst_valid || - observed.next_pc != expected.pc + expected.len) { - std::cerr << "frontend ALU trace top commit row mismatch" - << " pc=0x" << std::hex << observed.pc - << " insn=0x" << observed.insn - << std::dec << " len=" << static_cast(observed.len) - << " wb_valid=" << observed.wb_valid - << " src0=(" << observed.src0_valid << "," - << static_cast(observed.src0_reg) << ")" - << " src1=(" << observed.src1_valid << "," - << static_cast(observed.src1_reg) << ")" - << " dst=(" << observed.dst_valid << "," - << static_cast(observed.dst_reg) << ")" - << " next_pc=0x" << std::hex << observed.next_pc << std::dec - << "\n"; - std::exit(1); - } - - if (observed.src0_valid && - (observed.src0_reg != expected.src0_reg || observed.src0_data != expected.src0_data)) { - std::cerr << "frontend ALU trace top src0 mismatch" - << " expected=(" << static_cast(expected.src0_reg) - << "," << expected.src0_data << ") observed=(" - << static_cast(observed.src0_reg) - << "," << observed.src0_data << ")\n"; - std::exit(1); - } - if (observed.src1_valid && - (observed.src1_reg != expected.src1_reg || observed.src1_data != expected.src1_data)) { - std::cerr << "frontend ALU trace top src1 mismatch" - << " expected=(" << static_cast(expected.src1_reg) - << "," << expected.src1_data << ") observed=(" - << static_cast(observed.src1_reg) - << "," << observed.src1_data << ")\n"; - std::exit(1); - } - if (observed.dst_valid && - (observed.dst_reg != expected.dst_reg || observed.dst_data != expected.dst_data || - observed.wb_reg != expected.dst_reg || observed.wb_data != expected.dst_data)) { - std::cerr << "frontend ALU trace top dst/wb mismatch" - << " expected=(" << static_cast(expected.dst_reg) - << "," << expected.dst_data << ") observed_dst=(" - << static_cast(observed.dst_reg) - << "," << observed.dst_data << ") observed_wb=(" - << static_cast(observed.wb_reg) - << "," << observed.wb_data << ")\n"; - std::exit(1); - } -} - -CommitTraceJsonRow to_json_row(const ObservedRow &row) { - CommitTraceJsonRow json; - json.valid = row.valid; - json.seq = row.seq; - json.cycle = row.cycle; - json.slot = row.slot; - json.bid = row.bid; - json.gid = row.gid; - json.rid = row.rid; - json.rob_valid = row.rob_valid; - json.rob_wrap = row.rob_wrap; - json.rob_value = row.rob_value; - json.block_bid_valid = row.block_bid_valid; - json.block_bid = row.block_bid; - json.pc = row.pc; - json.insn = row.insn; - json.len = row.len; - json.wb_valid = row.wb_valid; - json.wb_rd = row.wb_reg; - json.wb_data = row.wb_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.mem_valid = row.mem_valid; - json.mem_is_store = row.mem_is_store; - json.mem_addr = row.mem_addr; - json.mem_wdata = row.mem_wdata; - json.mem_rdata = row.mem_rdata; - json.mem_size = row.mem_size; - json.trap_valid = row.trap_valid; - json.trap_cause = row.trap_cause; - json.trap_arg0 = row.trap_arg0; - json.next_pc = row.next_pc; - return json; -} - -CommitTraceJsonRow to_json_row(const ExpectedRow &row) { - CommitTraceJsonRow json; - json.pc = row.pc; - json.insn = mask_insn(row.insn, row.len); - json.len = row.len; - json.wb_valid = row.dst_valid; - json.wb_rd = row.dst_reg; - json.wb_data = row.dst_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.next_pc = row.pc + row.len; - return json; -} - -void write_dut_row(std::ofstream &out, const ObservedRow &row) { - write_dut_commit_jsonl(out, to_json_row(row)); -} - -void write_qemu_row(std::ofstream &out, const ExpectedRow &row) { - write_qemu_commit_jsonl(out, to_json_row(row)); -} - -std::uint8_t enqueue_and_accept_execute( - Dut &dut, - const ExpectedRow &row, - std::uint64_t pkt_uid) { - clear_inputs(dut); - drive_operands(dut, row); - dut.io_in_valid = 1; - dut.io_in_pc = row.pc; - dut.io_in_window = mask_insn(row.insn, row.len); - dut.io_in_pktUid = pkt_uid; - dut.io_in_checkpointId = pkt_uid & 0x3fU; - dut.eval(); - -#ifdef LINXCORE_RF_ALU_TRACE_TOP - if (dut.io_rfStateError) { - std::cerr << "frontend RF ALU trace top reported RF state error before enqueue\n"; - std::exit(1); - } -#endif - if (!dut.io_decodeReady || !dut.io_selectedValid || ((dut.io_f4ValidMask & 0x1U) == 0)) { - std::cerr << "frontend row was not accepted by F4/decode path" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << " decodeReady=" << static_cast(dut.io_decodeReady) - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " f4Mask=0x" << std::hex << static_cast(dut.io_f4ValidMask) - << std::dec << "\n"; - std::exit(1); - } - const auto rob_value = static_cast(dut.io_selectedRobValue); - tick(dut); - - for (int cycle = 0; cycle < 16; ++cycle) { - clear_inputs(dut); - drive_operands(dut, row); - dut.eval(); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - if (dut.io_rfStateError) { - std::cerr << "frontend RF ALU trace top reported RF state error while waiting for execute\n"; - std::exit(1); - } - if (dut.io_issueQueueEnqueueFire && dut.io_robRenameUpdateFire) { - tick(dut); - return rob_value; - } -#else - if (dut.io_executeAccepted && dut.io_robRenameUpdateFire) { - tick(dut); - return rob_value; - } -#endif - tick(dut); - } - -#ifdef LINXCORE_RF_ALU_TRACE_TOP - std::cerr << "frontend row did not enqueue into the reduced issue queue" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; -#else - std::cerr << "frontend row did not reach ALU execute" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; -#endif - std::exit(1); -} - -void wait_for_execute_completion(Dut &dut, std::uint8_t rob_value) { - for (int cycle = 0; cycle < 16; ++cycle) { - clear_inputs(dut); - dut.eval(); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - if (dut.io_rfStateError) { - std::cerr << "frontend RF ALU trace top reported RF state error during execute completion\n"; - std::exit(1); - } -#endif - if (dut.io_executeUnsupported) { - std::cerr << "execute reported unsupported opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid) { - if (dut.io_executeCompleteRobValue != rob_value || dut.io_completeIgnored) { - std::cerr << "execute completion mismatch" - << " expected_rob=" << static_cast(rob_value) - << " observed_rob=" << static_cast(dut.io_executeCompleteRobValue) - << " ignored=" << static_cast(dut.io_completeIgnored) - << "\n"; - std::exit(1); - } - tick(dut); - return; - } - tick(dut); - } - - std::cerr << "ALU execute did not emit completion for rob_value=" - << static_cast(rob_value) << "\n"; - std::exit(1); -} - -void drain_empty(Dut &dut) { - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_empty && dut.io_size == 0 && !dut.io_executeBusy) { - return; - } - tick(dut); - } - std::cerr << "frontend ALU trace top did not drain after commit" - << " size=" << static_cast(dut.io_size) - << " outstanding=" << static_cast(dut.io_outstandingCount) - << " executeBusy=" << static_cast(dut.io_executeBusy) - << "\n"; - std::exit(1); -} - -void commit_expected_row( - Dut &dut, - const ExpectedRow &expected, - std::ofstream &dut_out, - std::ofstream &qemu_out, - bool drain_after_commit = true) { - for (int cycle = 0; cycle < 32; ++cycle) { - clear_inputs(dut); - dut.eval(); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - if (dut.io_rfStateError) { - std::cerr << "frontend RF ALU trace top reported RF state error while waiting for commit\n"; - std::exit(1); - } -#endif - if (dut.io_executeUnsupported) { - std::cerr << "execute reported unsupported opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid && dut.io_completeIgnored) { - std::cerr << "execute completion was ignored while waiting for commit" - << " rob=" << static_cast(dut.io_executeCompleteRobValue) - << "\n"; - std::exit(1); - } - if (dut.io_commit_rows_0_valid) { - const ObservedRow slot0 = read_slot0(dut); - expect_monitor_clean(dut, "frontend ALU trace top commit", 0x1, 1); - expect_row(slot0, expected); - if (slot1_valid(dut)) { - std::cerr << "frontend ALU trace top expected a single-row commit window\n"; - std::exit(1); - } - write_dut_row(dut_out, slot0); - write_qemu_row(qemu_out, expected); - tick(dut); - if (drain_after_commit) { - drain_empty(dut); - } - return; - } - expect_monitor_clean(dut, "frontend ALU trace top wait", 0x0, 0); - tick(dut); - } - - std::cerr << "frontend ALU trace top did not emit a commit row" - << " pc=0x" << std::hex << expected.pc << std::dec << "\n"; - std::exit(1); -} - -std::vector fixture_rows() { - const std::uint64_t add = - 0x00000005ULL | (3ULL << 7) | (4ULL << 15) | (5ULL << 20); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - const std::uint64_t addi = - 0x00000015ULL | (6ULL << 7) | (3ULL << 15) | (0x7ffULL << 20); - const std::uint64_t c_movr = - 0x0006ULL | (6ULL << 6) | (5ULL << 11); -#else - const std::uint64_t addi = - 0x00000015ULL | (6ULL << 7) | (7ULL << 15) | (0x7ffULL << 20); - const std::uint64_t c_movr = - 0x0006ULL | (4ULL << 6) | (5ULL << 11); -#endif - - ExpectedRow r0; - r0.pc = 0x1000; - r0.insn = add; - r0.len = 4; - r0.src0_valid = true; - r0.src0_reg = 4; - r0.src0_data = 10; - r0.src1_valid = true; - r0.src1_reg = 5; - r0.src1_data = 32; - r0.dst_valid = true; - r0.dst_reg = 3; - r0.dst_data = 42; - - ExpectedRow r1; - r1.pc = 0x1004; - r1.insn = addi; - r1.len = 4; - r1.src0_valid = true; -#ifdef LINXCORE_RF_ALU_TRACE_TOP - r1.src0_reg = 3; - r1.src0_data = 42; - r1.dst_valid = true; - r1.dst_reg = 6; - r1.dst_data = 2089; -#else - r1.src0_reg = 7; - r1.src0_data = 7; - r1.dst_valid = true; - r1.dst_reg = 6; - r1.dst_data = 2054; -#endif - - ExpectedRow r2; - r2.pc = 0x1008; - r2.insn = c_movr; - r2.len = 2; - r2.src0_valid = true; -#ifdef LINXCORE_RF_ALU_TRACE_TOP - r2.src0_reg = 6; - r2.src0_data = 2089; - r2.dst_valid = true; - r2.dst_reg = 5; - r2.dst_data = 2089; -#else - r2.src0_reg = 4; - r2.src0_data = 0x1234'5678ULL; - r2.dst_valid = true; - r2.dst_reg = 5; - r2.dst_data = 0x1234'5678ULL; -#endif - - return {r0, r1, r2}; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - - Dut dut; - reset(dut); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - init_rf(dut, 4, 10); - init_rf(dut, 5, 32); -#endif - - std::ofstream dut_out(args.dut_trace); - std::ofstream qemu_out(args.qemu_trace); - if (!dut_out || !qemu_out) { - std::cerr << "failed to open output traces\n"; - return 2; - } - - const auto rows = fixture_rows(); -#ifdef LINXCORE_RF_ALU_TRACE_TOP - for (std::size_t i = 0; i < rows.size(); ++i) { - (void)enqueue_and_accept_execute(dut, rows[i], i); - } - for (std::size_t i = 0; i < rows.size(); ++i) { - commit_expected_row(dut, rows[i], dut_out, qemu_out, false); - } - drain_empty(dut); -#else - for (std::size_t i = 0; i < rows.size(); ++i) { - const std::uint8_t rob_value = enqueue_and_accept_execute(dut, rows[i], i); - wait_for_execute_completion(dut, rob_value); - commit_expected_row(dut, rows[i], dut_out, qemu_out); - } -#endif - - dut.eval(); - if (!dut.io_idle || !dut.io_empty || dut.io_size != 0) { - std::cerr << "frontend ALU trace top did not finish idle" - << " idle=" << static_cast(dut.io_idle) - << " empty=" << static_cast(dut.io_empty) - << " size=" << static_cast(dut.io_size) - << "\n"; - return 1; - } - expect_monitor_clean(dut, "post-drain idle window", 0x0, 0); - - dut.final(); - return 0; -} diff --git a/tools/chisel/frontend_fetch_rf_alu_fixture_memory.py b/tools/chisel/frontend_fetch_rf_alu_fixture_memory.py deleted file mode 100755 index 92950868..00000000 --- a/tools/chisel/frontend_fetch_rf_alu_fixture_memory.py +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/env python3 -"""Emit the dense instruction bytes used by the frontend fetch RF/ALU xcheck.""" - -import argparse -from pathlib import Path - - -def put_le(buf: bytearray, offset: int, value: int, size: int) -> None: - end = offset + size - if end > len(buf): - buf.extend(b"\x00" * (end - len(buf))) - buf[offset:end] = value.to_bytes(size, "little") - - -def fixture_bytes() -> bytes: - add = 0x00000005 | (3 << 7) | (4 << 15) | (5 << 20) - addi = 0x00000015 | (6 << 7) | (3 << 15) | (0x7FF << 20) - c_movr = 0x0006 | (6 << 6) | (5 << 11) - - buf = bytearray() - put_le(buf, 0, add, 4) - put_le(buf, 4, addi, 4) - put_le(buf, 8, c_movr, 2) - return bytes(buf) - - -def main() -> int: - parser = argparse.ArgumentParser() - parser.add_argument("--output", required=True, help="binary image to write") - args = parser.parse_args() - - output = Path(args.output) - output.parent.mkdir(parents=True, exist_ok=True) - data = fixture_bytes() - output.write_bytes(data) - print(f"frontend-fetch-rf-alu-fixture-memory={output} bytes={len(data)}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main()) diff --git a/tools/chisel/frontend_fetch_rf_alu_marker_rows_trace_top_tb.cpp b/tools/chisel/frontend_fetch_rf_alu_marker_rows_trace_top_tb.cpp deleted file mode 100644 index 5f3beaf6..00000000 --- a/tools/chisel/frontend_fetch_rf_alu_marker_rows_trace_top_tb.cpp +++ /dev/null @@ -1,161 +0,0 @@ -#include "VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop.h" -#include "verilated.h" - -#include -#include -#include - -namespace { - -constexpr std::uint64_t kStartPc = 0x40005504ULL; -constexpr std::uint64_t kFirstWindow = 0x0000918710460800ULL; -constexpr std::uint64_t kInitialSp = 0x4fffddb0ULL; - -void clear_inputs(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - dut.io_startValid = 0; - dut.io_startPc = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_bfuBodyValid = 0; - dut.io_bfuHeaderPc = 0; - dut.io_bfuHSizeBytes = 0; - dut.io_bfuBSizeBytes = 0; - dut.io_frontendFlushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 0; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_rfInitValid = 0; - dut.io_rfInitArchTag = 0; - dut.io_rfInitData = 0; - dut.io_deallocReady = 1; - dut.io_loadLookupData = 0; -} - -void tick(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); -} - -void reset(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - clear_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - dut.eval(); -} - -[[noreturn]] void fail(const char *message, const VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - std::cerr << "marker-row smoke failed: " << message - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " selectedBlockBid=0x" << std::hex - << static_cast(dut.io_selectedBlockBid) - << " blockMarkerSkipFire=" << std::dec - << static_cast(dut.io_blockMarkerSkipFire) - << " decRenPushFire=" << static_cast(dut.io_decRenPushFire) - << " robAllocFire=" << static_cast(dut.io_robAllocFire) - << " decRenHeadPc=0x" << std::hex - << static_cast(dut.io_decRenHeadPc) - << std::dec - << " decRenCount=" << static_cast(dut.io_decRenCount) - << "\n"; - std::exit(1); -} - -void init_rf(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - clear_inputs(dut); - dut.io_rfInitValid = 1; - dut.io_rfInitArchTag = 1; - dut.io_rfInitData = kInitialSp; - tick(dut); -} - -void start_source(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - clear_inputs(dut); - dut.io_startValid = 1; - dut.io_startPc = kStartPc; - tick(dut); -} - -void accept_fetch_request(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - for (int cycle = 0; cycle < 16; ++cycle) { - clear_inputs(dut); - dut.io_fetchReqReady = 1; - dut.eval(); - if (dut.io_fetchReqValid) { - if (!dut.io_sourceReqFire || dut.io_fetchReqPc != kStartPc) { - fail("fetch request did not match start PC", dut); - } - tick(dut); - return; - } - tick(dut); - } - fail("fetch source did not request the start PC", dut); -} - -void accept_fetch_response(VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop &dut) { - clear_inputs(dut); - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = kFirstWindow; - dut.eval(); - if (!dut.io_fetchRespReady || !dut.io_sourceRespFire) { - fail("fetch response was not accepted", dut); - } - tick(dut); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - - VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop dut; - reset(dut); - init_rf(dut); - start_source(dut); - accept_fetch_request(dut); - accept_fetch_response(dut); - - int selected_rows = 0; - std::uint64_t marker_bid = 0; - - for (int cycle = 0; cycle < 128; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_rfStateError || dut.io_commitContractError) { - fail("top reported a state or commit contract error", dut); - } - - if (dut.io_denseSlotQueueOutFire && dut.io_selectedValid) { - if (dut.io_blockMarkerSkipFire) { - fail("marker-row wrapper still consumed the marker as a skip row", dut); - } - if (!dut.io_decRenPushFire || !dut.io_robAllocFire) { - fail("selected row did not reserve ROB state", dut); - } - if (selected_rows == 0) { - marker_bid = dut.io_selectedBlockBid; - } else if (selected_rows == 1) { - if (dut.io_selectedBlockBid != marker_bid) { - fail("following scalar row did not reuse marker BID", dut); - } - std::cout << "marker-row-smoke-status=pass" - << " marker_bid=0x" << std::hex - << static_cast(marker_bid) - << std::dec << "\n"; - return 0; - } - ++selected_rows; - } - tick(dut); - } - - fail("did not observe marker row followed by scalar row", dut); -} diff --git a/tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp b/tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp deleted file mode 100644 index 6005b7eb..00000000 --- a/tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp +++ /dev/null @@ -1,8337 +0,0 @@ -#if defined(LINXCORE_MARKER_ROWS_TRACE_TOP) -#include "VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop.h" -#define VLinxCoreFrontendFetchRfAluTraceTop VLinxCoreFrontendFetchRfAluMarkerRowsTraceTop -#elif defined(LINXCORE_REDUCED_STORE_TRACE_TOP) -#include "VLinxCoreFrontendFetchRfAluReducedStoreTraceTop.h" -#define VLinxCoreFrontendFetchRfAluTraceTop VLinxCoreFrontendFetchRfAluReducedStoreTraceTop -#elif defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) -#include "VLinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop.h" -#define VLinxCoreFrontendFetchRfAluTraceTop VLinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop -#elif defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) -#include "VLinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop.h" -#define VLinxCoreFrontendFetchRfAluTraceTop VLinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop -#else -#include "VLinxCoreFrontendFetchRfAluTraceTop.h" -#endif -#include "verilated.h" - -#include "commit_trace_jsonl.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace { - -using linxcore::chisel::CommitTraceJsonRow; -using linxcore::chisel::write_dut_commit_jsonl; -using linxcore::chisel::write_qemu_commit_jsonl; - -constexpr int kDenseRowDrainCycles = 64; - -template -std::string hex_port(const T &value) { - std::ostringstream out; - out << std::hex << static_cast(value); - return out.str(); -} - -template -std::string hex_port(const VlWide &value) { - std::ostringstream out; - out << std::hex; - bool seen = false; - for (std::size_t remaining = N; remaining > 0; --remaining) { - const std::uint32_t word = value.at(remaining - 1); - if (!seen) { - if (word == 0) { - continue; - } - out << word; - seen = true; - } else { - out << std::setw(8) << std::setfill('0') << word; - } - } - if (!seen) { - out << '0'; - } - return out.str(); -} - -struct Args { - std::string dut_trace; - std::string qemu_trace; - std::string memory_bin; - std::string memory_hex; - std::string expected_rows; - std::string rf_seed; - std::string sideband_stats; - std::uint64_t memory_base = 0x1000; - bool admit_marker_rows = false; - bool disable_store_memory_mutation = false; - bool allow_residual_replay_liq_wait = false; -}; - -struct ExpectedRow { - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 4; - std::uint64_t next_pc = 0; - bool skip = false; - std::string skip_kind; - bool block_boundary = false; - bool block_stop = false; - bool loop_reentry = false; - std::uint64_t loop_reentry_from_pc = 0; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; - bool mem_valid = false; - bool mem_is_store = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint8_t mem_size = 0; -}; - -struct ObservedRow { - bool valid = false; - std::uint64_t seq = 0; - std::uint64_t cycle = 0; - std::uint8_t slot = 0; - std::uint32_t bid = 0; - std::uint32_t gid = 0; - std::uint32_t rid = 0; - bool rob_valid = false; - bool rob_wrap = false; - std::uint8_t rob_value = 0; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 0; - bool wb_valid = false; - std::uint8_t wb_reg = 0; - std::uint64_t wb_data = 0; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; - bool mem_valid = false; - bool mem_is_store = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint8_t mem_size = 0; - bool trap_valid = false; - std::uint32_t trap_cause = 0; - std::uint64_t trap_arg0 = 0; - std::uint64_t next_pc = 0; - bool rf_write_valid = false; - std::uint8_t rf_write_tag = 0; - std::uint64_t rf_write_data = 0; - std::uint8_t src_phys_valid_mask = 0; - std::uint8_t src_phys_tag0 = 0; - std::uint8_t src_phys_tag1 = 0; - std::uint8_t src_phys_tag2 = 0; -}; - -struct IssueDebug { - std::uint8_t src_valid_mask = 0; - std::uint8_t src_phys_tag0 = 0; - std::uint8_t src_phys_tag1 = 0; - std::uint8_t src_phys_tag2 = 0; -}; - -struct PhysWriter { - bool valid = false; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t phys_tag = 0; - std::uint8_t wb_reg = 0; - std::uint64_t data = 0; -}; - -std::map g_issue_debug_by_rob; -std::map g_phys_writer_by_tag; -std::map g_arch_writer_by_reg; -std::uint64_t g_tb_cycle = 0; - -struct GprCommitHistory { - std::uint64_t dealloc_block_last_count = 0; - std::uint64_t block_scalar_done_count = 0; - std::uint64_t block_retire_count = 0; - std::uint64_t gpr_commit_count = 0; - std::uint64_t gpr_commit_hit_total = 0; - std::uint64_t gpr_release_total = 0; - std::uint64_t last_dealloc_block_last_bid = 0; - std::uint64_t last_scalar_done_bid = 0; - std::uint64_t last_block_retire_bid = 0; - std::uint64_t last_gpr_commit_bid = 0; - std::uint8_t last_gpr_commit_hits = 0; - std::uint8_t last_gpr_releases = 0; - std::uint64_t last_nonzero_gpr_commit_bid = 0; - std::uint8_t last_nonzero_gpr_commit_hits = 0; - std::uint8_t last_nonzero_gpr_releases = 0; -}; - -GprCommitHistory g_gpr_commit_history; - -struct ReplayLiqSidebandStats { - std::uint64_t cycles_sampled = 0; - std::uint64_t issue_simultaneous_pick = 0; - std::uint64_t issue_read_contention = 0; - std::uint64_t issue_read_arbitration_loss = 0; - std::uint64_t issue_cancel = 0; - std::uint64_t issue_i2_contention = 0; - std::uint64_t issue_control_fence_active = 0; - std::uint64_t issue_control_fence_blocked = 0; - std::uint64_t issue_store_order_blocked = 0; - std::uint64_t load_lookup_valid = 0; - std::uint64_t load_lookup_execute_granted = 0; - std::uint64_t load_lookup_execute_with_eligible_store = 0; - std::uint64_t load_lookup_execute_with_wait_store = 0; - std::uint64_t execute_load_wait_hold = 0; - std::uint64_t resident_store_eligible = 0; - std::uint64_t resident_store_ready_forward = 0; - std::uint64_t resident_store_wait_blocked = 0; - std::uint64_t resident_store_wait_store_valid = 0; - std::uint64_t store_stq_resident = 0; - std::uint64_t store_stq_addr_ready = 0; - std::uint64_t store_stq_data_ready = 0; - std::uint64_t store_stq_addr_ready_not_data_ready = 0; - std::uint64_t store_stq_addr_and_data_ready = 0; - std::uint64_t load_lookup_execute_with_addr_ready_not_data_ready = 0; - std::uint64_t load_lookup_execute_granted_first_cycle = 0; - std::uint64_t load_lookup_execute_granted_last_cycle = 0; - std::uint64_t store_stq_addr_ready_not_data_ready_first_cycle = 0; - std::uint64_t store_stq_addr_ready_not_data_ready_last_cycle = 0; - std::uint64_t store_stq_addr_and_data_ready_first_cycle = 0; - std::uint64_t store_stq_addr_and_data_ready_last_cycle = 0; - std::uint64_t load_lookup_execute_with_addr_ready_not_data_ready_first_cycle = 0; - std::uint64_t load_lookup_execute_with_addr_ready_not_data_ready_last_cycle = 0; - std::uint64_t store_sta_dequeue_fire_first_cycle = 0; - std::uint64_t store_sta_dequeue_fire_last_cycle = 0; - std::uint64_t store_std_dequeue_fire_first_cycle = 0; - std::uint64_t store_std_dequeue_fire_last_cycle = 0; - std::uint64_t store_sta_exec_valid_first_cycle = 0; - std::uint64_t store_sta_exec_valid_last_cycle = 0; - std::uint64_t store_std_exec_valid_first_cycle = 0; - std::uint64_t store_std_exec_valid_last_cycle = 0; - std::uint64_t store_sta_queue_valid = 0; - std::uint64_t store_std_queue_valid = 0; - std::uint64_t store_sta_queue_only_valid = 0; - std::uint64_t store_sta_dequeue_fire = 0; - std::uint64_t store_std_dequeue_fire = 0; - std::uint64_t store_sta_exec_valid = 0; - std::uint64_t store_std_exec_valid = 0; - std::uint64_t store_sta_exec_only_valid = 0; - std::uint64_t resident_store_wake_valid = 0; - std::uint64_t resident_store_wake_ready = 0; - std::uint64_t wait_replay_capture_accepted = 0; - std::uint64_t wait_replay_clear_valid = 0; - std::uint64_t wait_replay_relaunch_valid = 0; - std::uint64_t replay_queue_enqueue_accepted = 0; - std::uint64_t replay_queue_out_valid = 0; - std::uint64_t replay_queue_out_fire = 0; - std::uint64_t liq_alloc_valid = 0; - std::uint64_t liq_alloc_accepted = 0; - std::uint64_t liq_launch_valid = 0; - std::uint64_t liq_launch_accepted = 0; - std::uint64_t liq_return_complete_repick_mask_nonzero = 0; - std::uint64_t liq_return_complete_source_returned_mask_nonzero = 0; - std::uint64_t liq_return_complete_data_complete_mask_nonzero = 0; - std::uint64_t liq_return_complete_request_complete_mask_nonzero = 0; - std::uint64_t liq_return_complete_candidate_mask_nonzero = 0; - std::uint64_t liq_return_complete_mask_nonzero = 0; - std::uint64_t liq_return_complete_valid = 0; - std::uint64_t liq_return_complete_candidate_count_nonzero = 0; - std::uint64_t liq_return_complete_valid_w2_occupied = 0; - std::uint64_t liq_base_lookup_valid = 0; - std::uint64_t liq_base_lookup_granted = 0; - std::uint64_t liq_base_data_returned = 0; - std::uint64_t liq_base_line_valid_mask_nonzero = 0; - std::uint64_t launch_readiness_candidate_valid = 0; - std::uint64_t launch_readiness_base_data_ready = 0; - std::uint64_t launch_readiness_sources_returned = 0; - std::uint64_t launch_readiness_ready = 0; - std::uint64_t launch_readiness_enable = 0; - std::uint64_t launch_readiness_blocked_by_disabled = 0; - std::uint64_t launch_readiness_blocked_by_no_candidate = 0; - std::uint64_t launch_readiness_blocked_by_base_lookup = 0; - std::uint64_t launch_readiness_blocked_by_base_data = 0; - std::uint64_t launch_readiness_blocked_by_scb = 0; - std::uint64_t launch_readiness_blocked_by_return = 0; - std::uint64_t liq_wait_store_mask_nonzero = 0; - std::uint64_t liq_replay_wake_valid = 0; - std::uint64_t liq_replay_wake_active = 0; - std::uint64_t liq_replay_wake_wait_store_candidate = 0; - std::uint64_t liq_replay_wake_bid_match = 0; - std::uint64_t liq_replay_wake_lsid_match = 0; - std::uint64_t liq_replay_wake_pc_match = 0; - std::uint64_t liq_replay_wake_full_match = 0; - std::uint64_t liq_replay_wake_store_unit = 0; - std::uint64_t liq_replay_wake_store_unit_full_match = 0; - std::uint64_t liq_replay_wake_store_unit_full_match_active = 0; - std::uint64_t liq_replay_wake_store_unit_full_match_flush_blocked = 0; - std::uint64_t liq_replay_wake_wait_store_clear = 0; - std::uint64_t source_return_candidate_valid = 0; - std::uint64_t source_return_store_snapshot_ready = 0; - std::uint64_t source_return_store_source_returned = 0; - std::uint64_t source_return_scb_source_returned = 0; - std::uint64_t source_return_source_returned = 0; - std::uint64_t source_return_blocked_by_disabled = 0; - std::uint64_t source_return_blocked_by_no_candidate = 0; - std::uint64_t source_return_blocked_by_base_data = 0; - std::uint64_t source_return_blocked_by_store_snapshot = 0; - std::uint64_t source_return_blocked_by_scb = 0; - std::uint64_t source_return_store_snapshot_live_request_active = 0; - std::uint64_t source_return_store_snapshot_live_evidence_valid = 0; - std::uint64_t source_return_scb_live_active = 0; - std::uint64_t source_return_scb_live_request_active = 0; - std::uint64_t source_return_scb_live_evidence_valid = 0; - std::uint64_t source_return_scb_live_pending = 0; - std::uint64_t source_return_scb_live_returned = 0; - std::uint64_t source_return_scb_live_blocked_by_request_disabled = 0; - std::uint64_t source_return_scb_live_blocked_by_no_pending = 0; - std::uint64_t source_return_scb_live_blocked_by_scb_return = 0; - std::uint64_t source_return_query_issued = 0; - std::uint64_t source_return_response_apply_valid = 0; - std::uint64_t source_return_row_state_plan_valid = 0; - std::uint64_t source_return_candidate_w2_occupied = 0; - std::uint64_t source_return_store_snapshot_ready_w2_occupied = 0; - std::uint64_t source_return_query_issued_w2_occupied = 0; - std::uint64_t source_return_response_apply_w2_occupied = 0; - std::uint64_t source_row_mutation_candidate_valid = 0; - std::uint64_t source_row_mutation_live_permit = 0; - std::uint64_t source_row_mutation_request_valid = 0; - std::uint64_t source_row_mutation_blocked_by_head_proof = 0; - std::uint64_t source_row_mutation_blocked_by_live_disabled = 0; - std::uint64_t source_row_mutation_request_w2_occupied = 0; - std::uint64_t return_data_candidate_valid = 0; - std::uint64_t return_data_request_mask_nonzero = 0; - std::uint64_t return_data_bytes_complete = 0; - std::uint64_t return_data_cross_line = 0; - std::uint64_t return_data_size_supported = 0; - std::uint64_t return_data_valid = 0; - std::uint64_t return_data_blocked_by_disabled = 0; - std::uint64_t return_data_blocked_by_no_candidate = 0; - std::uint64_t return_data_blocked_by_zero_size = 0; - std::uint64_t return_data_blocked_by_unsupported_size = 0; - std::uint64_t return_data_blocked_by_cross_line = 0; - std::uint64_t return_data_blocked_by_incomplete_bytes = 0; - std::uint64_t return_publish_candidate_valid = 0; - std::uint64_t return_publish_data_ready = 0; - std::uint64_t return_publish_ready = 0; - std::uint64_t return_publish_blocked_by_no_candidate = 0; - std::uint64_t return_publish_blocked_by_data = 0; - std::uint64_t return_publish_blocked_by_consumer = 0; - std::uint64_t return_publish_candidate_w2_occupied = 0; - std::uint64_t return_publish_ready_w2_occupied = 0; - std::uint64_t lret_payload_candidate_valid = 0; - std::uint64_t lret_payload_valid = 0; - std::uint64_t lret_payload_wakeup_required = 0; - std::uint64_t lret_payload_blocked_by_no_candidate = 0; - std::uint64_t lret_payload_blocked_by_data = 0; - std::uint64_t lret_payload_candidate_w2_occupied = 0; - std::uint64_t lret_payload_valid_w2_occupied = 0; - std::uint64_t publish_control_candidate_valid = 0; - std::uint64_t publish_control_live_enable = 0; - std::uint64_t publish_control_armed = 0; - std::uint64_t publish_control_fire = 0; - std::uint64_t publish_control_blocked_by_no_payload = 0; - std::uint64_t publish_control_blocked_by_publish = 0; - std::uint64_t publish_control_blocked_by_side_effects = 0; - std::uint64_t publish_control_blocked_by_live_disabled = 0; - std::uint64_t publish_control_candidate_w2_occupied = 0; - std::uint64_t publish_control_live_enable_w2_occupied = 0; - std::uint64_t publish_control_armed_w2_occupied = 0; - std::uint64_t publish_control_fire_w2_occupied = 0; - std::uint64_t publish_request_valid = 0; - std::uint64_t publish_request_lret = 0; - std::uint64_t publish_request_writeback = 0; - std::uint64_t publish_request_wakeup = 0; - std::uint64_t publish_request_mask_nonzero = 0; - std::uint64_t publish_request_blocked_by_no_fire = 0; - std::uint64_t publish_request_invalid_fire_without_payload = 0; - std::uint64_t lret_sink_enqueue_ready = 0; - std::uint64_t lret_sink_enqueue_accepted = 0; - std::uint64_t lret_sink_enqueue_dropped = 0; - std::uint64_t lret_sink_drain_valid = 0; - std::uint64_t lret_sink_drain_fire = 0; - std::uint64_t lret_sink_pending = 0; - std::uint64_t lret_sink_full = 0; - std::uint64_t lret_sink_blocked_by_no_payload = 0; - std::uint64_t lret_sink_blocked_by_full = 0; - std::uint64_t lret_sink_blocked_by_drain = 0; - std::uint64_t lret_sink_enqueue_ready_w2_occupied = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_occupied = 0; - std::uint64_t lret_sink_enqueue_dropped_w2_occupied = 0; - std::uint64_t lret_sink_enqueue_accepted_same_cycle_drain_fire = 0; - std::uint64_t lret_sink_enqueue_accepted_same_cycle_drain_fire_w2_occupied = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_without_drain_fire = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_completion_clear_slot = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_clear_intent = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_side_effect_fire_complete = 0; - std::uint64_t lret_sink_enqueue_accepted_w2_live_clear = 0; - std::uint64_t lret_sink_followup_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_sink_followup_w2_still_occupied = 0; - std::uint64_t lret_sink_followup_w2_cleared = 0; - std::uint64_t lret_sink_followup_after_enqueue_completion_clear_slot = 0; - std::uint64_t lret_sink_followup_after_enqueue_completion_clear_slot_w2_cleared = 0; - std::uint64_t lret_sink_followup_after_enqueue_clear_intent = 0; - std::uint64_t lret_sink_followup_after_enqueue_clear_intent_w2_cleared = 0; - std::uint64_t lret_sink_followup_after_enqueue_side_effect_fire_complete = 0; - std::uint64_t lret_sink_followup_after_enqueue_side_effect_fire_complete_w2_cleared = 0; - std::uint64_t lret_sink_followup_after_enqueue_live_clear = 0; - std::uint64_t lret_sink_followup_after_enqueue_live_clear_w2_cleared = 0; - std::uint64_t lret_sink_pending_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_sink_drain_valid_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_sink_drain_fire_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_drain_permit_ready_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_drain_permit_pipe_free_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_drain_permit_pipe_full_after_enqueue_accepted_w2 = 0; - std::uint64_t lret_sink_pending_w2_occupied = 0; - std::uint64_t lret_sink_drain_valid_w2_occupied = 0; - std::uint64_t lret_sink_drain_fire_w2_occupied = 0; - std::uint64_t w2_retire_record_capture_candidate = 0; - std::uint64_t w2_retire_record_payload_valid = 0; - std::uint64_t w2_retire_record_capture_valid = 0; - std::uint64_t w2_retire_record_capture_ready = 0; - std::uint64_t w2_retire_record_capture_accepted = 0; - std::uint64_t w2_retire_record_capture_accepted_w2_occupied = 0; - std::uint64_t w2_retire_record_capture_dropped = 0; - std::uint64_t w2_retire_record_record_valid = 0; - std::uint64_t w2_retire_record_record_ready = 0; - std::uint64_t w2_retire_record_record_fire = 0; - std::uint64_t w2_retire_record_pending = 0; - std::uint64_t w2_retire_record_captured_with_lret_enqueue = 0; - std::uint64_t w2_retire_record_record_from_lret_enqueue = 0; - std::uint64_t w2_retire_record_blocked_by_invalid_payload = 0; - std::uint64_t w2_retire_record_blocked_by_full = 0; - std::uint64_t lret_commit_history_load_rows = 0; - std::uint64_t lret_shadow_enqueue = 0; - std::uint64_t lret_shadow_enqueue_after_prior_commit = 0; - std::uint64_t lret_shadow_drain = 0; - std::uint64_t lret_shadow_drain_missing = 0; - std::uint64_t lret_shadow_drain_after_prior_commit = 0; - std::uint64_t lret_shadow_free_after_prior_commit = 0; - std::uint64_t lret_drain_permit_any_pipe_free = 0; - std::uint64_t lret_drain_permit_ready = 0; - std::uint64_t lret_drain_permit_blocked_by_no_entry = 0; - std::uint64_t lret_drain_permit_blocked_by_pipe_full = 0; - std::uint64_t lret_drain_permit_pipe_occupied = 0; - std::uint64_t lret_iex_data_rob_row_valid = 0; - std::uint64_t lret_iex_data_rob_row_need_flush = 0; - std::uint64_t lret_iex_data_rob_row_blocked_by_invalid_rid = 0; - std::uint64_t lret_iex_data_rob_row_blocked_by_free = 0; - std::uint64_t lret_iex_data_rob_row_blocked_by_stale_rid = 0; - std::uint64_t lret_iex_data_candidate_valid = 0; - std::uint64_t lret_iex_data_would_drain = 0; - std::uint64_t lret_iex_data_set_mem_data_valid = 0; - std::uint64_t lret_iex_data_blocked_by_disabled = 0; - std::uint64_t lret_iex_data_blocked_by_flush = 0; - std::uint64_t lret_iex_data_blocked_by_no_entry = 0; - std::uint64_t lret_iex_data_blocked_by_invalid_entry = 0; - std::uint64_t lret_iex_data_blocked_by_drain = 0; - std::uint64_t lret_iex_data_blocked_by_rob_missing = 0; - std::uint64_t lret_iex_data_blocked_by_need_flush = 0; - std::uint64_t lret_rob_resolve_candidate_valid = 0; - std::uint64_t lret_rob_resolve_valid = 0; - std::uint64_t lret_rob_resolve_ready_for_pipe_insert = 0; - std::uint64_t lret_rob_resolve_mark_all_destinations_data_valid = 0; - std::uint64_t lret_rob_resolve_mark_destination_data_valid = 0; - std::uint64_t lret_rob_resolve_ret_lane_increment = 0; - std::uint64_t lret_rob_resolve_blocked_by_disabled = 0; - std::uint64_t lret_rob_resolve_blocked_by_flush = 0; - std::uint64_t lret_rob_resolve_blocked_by_no_set_mem_data = 0; - std::uint64_t lret_rob_resolve_blocked_by_unsupported_multi_lane = 0; - std::uint64_t lret_rob_resolve_blocked_by_invalid_rid = 0; - std::uint64_t lret_rob_resolve_blocked_by_no_destination = 0; - std::uint64_t lret_lane_completion_candidate_valid = 0; - std::uint64_t lret_lane_completion_complete_valid = 0; - std::uint64_t lret_lane_completion_ready_for_pipe_insert = 0; - std::uint64_t lret_lane_completion_requires_all_lanes = 0; - std::uint64_t lret_lane_completion_blocked_by_disabled = 0; - std::uint64_t lret_lane_completion_blocked_by_flush = 0; - std::uint64_t lret_lane_completion_blocked_by_no_resolve = 0; - std::uint64_t lret_lane_completion_blocked_by_zero_returned_lanes = 0; - std::uint64_t lret_lane_completion_blocked_by_invalid_real_req_cnt = 0; - std::uint64_t lret_lane_completion_blocked_by_scalar_load_pair_incomplete = 0; - std::uint64_t lret_lane_completion_blocked_by_vector_mem_incomplete = 0; - std::uint64_t lret_tload_completion_candidate_valid = 0; - std::uint64_t lret_tload_completion_tload_candidate_valid = 0; - std::uint64_t lret_tload_completion_tile_scb_send_valid = 0; - std::uint64_t lret_tload_completion_tile_scb_is_last = 0; - std::uint64_t lret_tload_completion_complete_valid = 0; - std::uint64_t lret_tload_completion_ready_for_pipe_insert = 0; - std::uint64_t lret_tload_completion_blocked_by_disabled = 0; - std::uint64_t lret_tload_completion_blocked_by_flush = 0; - std::uint64_t lret_tload_completion_blocked_by_no_lane_completion = 0; - std::uint64_t lret_tload_completion_blocked_by_invalid_sub_inst_cnt = 0; - std::uint64_t lret_tload_completion_blocked_by_tload_pending = 0; - std::uint64_t lret_final_metadata_candidate_valid = 0; - std::uint64_t lret_final_metadata_is_load_return_marked = 0; - std::uint64_t lret_final_metadata_load_branch_resolve_called = 0; - std::uint64_t lret_final_metadata_load_branch_resolve_side_effect_valid = 0; - std::uint64_t lret_final_metadata_pipe_cycle_sideband_valid = 0; - std::uint64_t lret_final_metadata_ready_for_pipe_insert = 0; - std::uint64_t lret_final_metadata_blocked_by_disabled = 0; - std::uint64_t lret_final_metadata_blocked_by_flush = 0; - std::uint64_t lret_final_metadata_blocked_by_no_tload_completion = 0; - std::uint64_t lret_timing_stats_candidate_valid = 0; - std::uint64_t lret_timing_stats_sideband_valid = 0; - std::uint64_t lret_timing_stats_iq_name_sideband_valid = 0; - std::uint64_t lret_timing_stats_ld_rnt_cycle_valid = 0; - std::uint64_t lret_timing_stats_update_valid = 0; - std::uint64_t lret_timing_stats_latency_underflow = 0; - std::uint64_t lret_timing_stats_ready_for_pipe_insert = 0; - std::uint64_t lret_timing_stats_blocked_by_disabled = 0; - std::uint64_t lret_timing_stats_blocked_by_flush = 0; - std::uint64_t lret_timing_stats_blocked_by_no_final_metadata = 0; - std::uint64_t lret_iex_insert_candidate_valid = 0; - std::uint64_t lret_iex_insert_valid = 0; - std::uint64_t lret_iex_insert_is_load_return = 0; - std::uint64_t lret_iex_insert_wakeup_required = 0; - std::uint64_t lret_iex_insert_blocked_by_no_set_mem_data = 0; - std::uint64_t lret_iex_insert_blocked_by_no_pipe = 0; - std::uint64_t lret_iex_insert_blocked_by_invalid_rid = 0; - std::uint64_t lret_iex_insert_candidate_w2_occupied = 0; - std::uint64_t lret_iex_insert_valid_w2_occupied = 0; - std::uint64_t lret_residency_candidate_valid = 0; - std::uint64_t lret_residency_write_valid = 0; - std::uint64_t lret_residency_live_enable = 0; - std::uint64_t lret_residency_blocked_by_live_disabled = 0; - std::uint64_t lret_residency_slot_accepted = 0; - std::uint64_t lret_residency_slot_occupied = 0; - std::uint64_t lret_residency_advance_candidate_valid = 0; - std::uint64_t lret_residency_advance_valid = 0; - std::uint64_t lret_residency_advance_blocked_by_advance_disabled = 0; - std::uint64_t lret_residency_candidate_w2_occupied = 0; - std::uint64_t lret_residency_write_w2_occupied = 0; - std::uint64_t lret_residency_slot_w2_occupied = 0; - std::uint64_t lret_residency_advance_candidate_w2_occupied = 0; - std::uint64_t lret_residency_advance_valid_w2_occupied = 0; - std::uint64_t lret_w1_slot_accepted = 0; - std::uint64_t lret_w1_slot_occupied = 0; - std::uint64_t lret_w1_advance_candidate_valid = 0; - std::uint64_t lret_w1_advance_valid = 0; - std::uint64_t lret_w1_advance_blocked_by_advance_disabled = 0; - std::uint64_t lret_w1_slot_w2_occupied = 0; - std::uint64_t lret_w1_advance_candidate_w2_occupied = 0; - std::uint64_t lret_w1_advance_valid_w2_occupied = 0; - std::uint64_t lret_w2_slot_accepted = 0; - std::uint64_t lret_w2_slot_occupied = 0; - std::uint64_t lret_w2_slot_blocked_by_no_write = 0; - std::uint64_t lret_w2_slot_source_trace_valid = 0; - std::uint64_t w2_atomic_live_active = 0; - std::uint64_t w2_atomic_request_active = 0; - std::uint64_t w2_atomic_evidence_valid = 0; - std::uint64_t w2_atomic_side_effect_live_requested = 0; - std::uint64_t w2_atomic_promotion_requested = 0; - std::uint64_t w2_atomic_blocked = 0; - std::uint64_t w2_atomic_blocked_by_request_disabled = 0; - std::uint64_t w2_atomic_blocked_by_no_evidence = 0; - std::uint64_t w2_atomic_blocked_by_mode_disabled = 0; - std::uint64_t w2_atomic_blocked_by_policy = 0; - std::uint64_t w2_atomic_blocked_by_no_side_effect_sink = 0; - std::uint64_t w2_atomic_blocked_by_no_clear_commit = 0; - std::uint64_t w2_atomic_blocked_by_no_row_fill_candidate = 0; - std::uint64_t w2_atomic_blocked_by_no_lifecycle_row = 0; - std::uint64_t w2_atomic_blocked_by_no_required_side_effect = 0; - std::uint64_t w2_side_effect_candidate_valid = 0; - std::uint64_t w2_side_effect_ready = 0; - std::uint64_t w2_side_effect_live_all_required_enabled = 0; - std::uint64_t w2_side_effect_fire_valid = 0; - std::uint64_t w2_side_effect_fire_complete = 0; - std::uint64_t w2_clear_intent = 0; - std::uint64_t w2_clear_commit_ready = 0; - std::uint64_t w2_promotion_live = 0; - std::uint64_t w2_promotion_live_clear = 0; - std::uint64_t w2_promotion_advance_live = 0; - std::uint64_t w2_promotion_blocked = 0; - std::uint64_t w2_promotion_blocked_by_promotion_disabled = 0; - std::uint64_t w2_promotion_blocked_by_clear_intent = 0; - std::uint64_t w2_promotion_invalid_clear_without_slot = 0; - std::uint64_t w2_refill_ready_empty = 0; - std::uint64_t w2_refill_ready_same_cycle_eligible = 0; - std::uint64_t w2_refill_ready_same_cycle_ready = 0; - std::uint64_t w2_refill_ready_future_advance = 0; - std::uint64_t w2_refill_ready_matches_current = 0; - std::uint64_t w2_refill_ready_blocked = 0; - std::uint64_t w2_refill_ready_invalid_live_clear_without_intent = 0; - std::uint64_t w2_slot_replace_empty_write_eligible = 0; - std::uint64_t w2_slot_replace_same_cycle_eligible = 0; - std::uint64_t w2_slot_replace_same_cycle_ready = 0; - std::uint64_t w2_slot_replace_future_write_accept = 0; - std::uint64_t w2_slot_replace_matches_current = 0; - std::uint64_t w2_slot_replace_blocked = 0; - std::uint64_t w2_slot_replace_blocked_by_current_storage = 0; - std::uint64_t w2_slot_replace_invalid_future_ready_without_live_clear = 0; - std::uint64_t w2_slot_replace_overlap_candidate_occupied = 0; - std::uint64_t w2_slot_replace_overlap_candidate_clear_intent = 0; - std::uint64_t w2_slot_replace_overlap_candidate_live_clear = 0; - std::uint64_t w2_slot_replace_overlap_live_clear_same_lsid = 0; - std::uint64_t w2_slot_replace_overlap_live_clear_different_lsid = 0; - std::uint64_t w2_slot_replace_overlap_live_clear_unknown_lsid = 0; - std::uint64_t w2_slot_replace_live_clear_without_w1_candidate = 0; - std::uint64_t w2_slot_replace_w1_candidate_without_live_clear = 0; - std::uint64_t w2_slot_replace_advance_valid_on_live_clear = 0; - std::uint64_t w2_slot_replace_w1_candidate_cycle_before_clear_intent = 0; - std::uint64_t w2_slot_replace_w1_candidate_cycle_before_live_clear = 0; - std::uint64_t w2_slot_replace_clear_intent_cycle_before_w1_candidate = 0; - std::uint64_t w2_slot_replace_live_clear_cycle_before_w1_candidate = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_gap2 = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_gap3 = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_gap4 = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_gap5_plus = 0; - std::uint64_t w2_slot_replace_w1_candidate_after_live_clear_gap2 = 0; - std::uint64_t w2_slot_replace_w1_candidate_after_live_clear_gap3 = 0; - std::uint64_t w2_slot_replace_w1_candidate_after_live_clear_gap4 = 0; - std::uint64_t w2_slot_replace_w1_candidate_after_live_clear_gap5_plus = 0; - std::uint64_t w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap2 = 0; - std::uint64_t w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap3 = 0; - std::uint64_t w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap4 = 0; - std::uint64_t w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap5_plus = 0; - std::uint64_t w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap2 = 0; - std::uint64_t w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap3 = 0; - std::uint64_t w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap4 = 0; - std::uint64_t w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap5_plus = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_same_lsid = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_different_lsid = 0; - std::uint64_t w2_slot_replace_live_clear_after_w1_candidate_unknown_lsid = 0; - std::uint64_t w2_advance_enable = 0; - std::uint64_t w2_advance_replace_on_clear = 0; - std::uint64_t w2_advance_uses_future_advance = 0; - std::uint64_t w2_advance_blocked = 0; - std::uint64_t w2_advance_blocked_by_live_promotion_disabled = 0; - std::uint64_t w2_advance_invalid_future_write_without_advance = 0; - std::uint64_t w2_commit_row_trace_source_ready = 0; - std::uint64_t w2_commit_row_trace_source_instruction_ready = 0; - std::uint64_t w2_commit_row_trace_source_source_ready = 0; - std::uint64_t w2_commit_row_trace_source_blocked = 0; - std::uint64_t w2_commit_row_trace_source_blocked_by_no_metadata = 0; - std::uint64_t w2_commit_row_trace_source_blocked_by_no_source_trace = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_row_valid = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_instruction_valid = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_blocked_by_need_flush = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_blocked_by_missing_instruction = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_disabled = 0; - std::uint64_t w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_before_completion = 0; - std::uint64_t w2_commit_row_candidate_valid = 0; - std::uint64_t w2_commit_row_fill_candidate = 0; - std::uint64_t w2_commit_row_complete_candidate = 0; - std::uint64_t w2_commit_row_candidate_blocked = 0; - std::uint64_t w2_commit_row_candidate_blocked_by_no_metadata = 0; - std::uint64_t w2_commit_row_candidate_blocked_by_no_source_trace = 0; - std::uint64_t w2_commit_row_candidate_blocked_by_invalid_size = 0; - std::uint64_t w2_commit_row_candidate_blocked_by_non_gpr_destination = 0; - std::uint64_t w2_commit_row_candidate_blocked_by_row_fill_disabled = 0; - std::uint64_t w2_retire_record_commit_row_candidate_valid = 0; - std::uint64_t w2_retire_record_commit_row_fill_candidate = 0; - std::uint64_t w2_retire_record_commit_row_complete_candidate = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_no_record = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_no_metadata = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_no_source_trace = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_invalid_size = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_non_gpr_destination = 0; - std::uint64_t w2_retire_record_commit_row_candidate_blocked_by_row_fill_disabled = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_intent = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_payload_rid_valid = 0; - std::uint64_t w2_retire_record_instruction_metadata_w2_rid_valid = 0; - std::uint64_t w2_retire_record_instruction_metadata_w2_rid_matches_capture = 0; - std::uint64_t w2_retire_record_instruction_metadata_w2_metadata_ready = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_from_w2 = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_from_drain = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_blocked_by_no_payload_rid = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_rid = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_blocked_by_rid_mismatch = 0; - std::uint64_t w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_metadata = 0; - std::uint64_t w2_retire_record_instruction_metadata_clear_accepted = 0; - std::uint64_t w2_retire_record_instruction_metadata_provider_valid = 0; - std::uint64_t w2_row_fill_candidate_valid = 0; - std::uint64_t w2_row_fill_prerequisites_ready = 0; - std::uint64_t w2_row_fill_enable = 0; - std::uint64_t w2_row_fill_blocked_by_request_disabled = 0; - std::uint64_t w2_row_fill_blocked_by_no_candidate = 0; - std::uint64_t w2_row_fill_blocked_by_no_side_effect_commit = 0; - std::uint64_t w2_row_fill_blocked_by_no_clear_commit = 0; - std::uint64_t w2_row_fill_blocked_by_live_clear_disabled = 0; - std::uint64_t w2_row_fill_blocked_by_no_replay_row_lifecycle = 0; - std::uint64_t w2_lifecycle_candidate_valid = 0; - std::uint64_t w2_lifecycle_slot_identity_valid = 0; - std::uint64_t w2_lifecycle_resolved_row_match = 0; - std::uint64_t w2_lifecycle_row_clear_ready = 0; - std::uint64_t w2_lifecycle_ready = 0; - std::uint64_t w2_lifecycle_blocked_by_no_resolved_row = 0; - std::uint64_t w2_lifecycle_blocked_by_multiple_resolved_rows = 0; - std::uint64_t w2_lifecycle_blocked_by_clear_disabled = 0; - std::uint64_t w2_lifecycle_clear_request_enable = 0; - std::uint64_t w2_lifecycle_clear_commit_enable = 0; - std::uint64_t w2_retire_record_lifecycle_candidate_valid = 0; - std::uint64_t w2_retire_record_lifecycle_slot_identity_valid = 0; - std::uint64_t w2_retire_record_lifecycle_resolved_row_match = 0; - std::uint64_t w2_retire_record_lifecycle_row_clear_ready = 0; - std::uint64_t w2_retire_record_lifecycle_blocked_by_no_resolved_row = 0; - std::uint64_t w2_retire_record_lifecycle_blocked_by_multiple_resolved_rows = 0; - std::uint64_t w2_retire_record_lifecycle_blocked_by_clear_disabled = 0; - std::uint64_t w2_retire_record_lifecycle_request_candidate = 0; - std::uint64_t w2_retire_record_lifecycle_live_promotion_candidate = 0; - std::uint64_t w2_retire_record_lifecycle_request_blocked_by_no_lifecycle_row = 0; - std::uint64_t w2_retire_record_lifecycle_request_blocked_by_no_atomic_request = 0; - std::uint64_t w2_retire_record_lifecycle_request_blocked_by_no_row_fill_candidate = 0; - std::uint64_t w2_retire_record_lifecycle_request_blocked_by_no_row_fill_enable = 0; - std::uint64_t w2_retire_record_atomic_request_evidence_valid = 0; - std::uint64_t w2_retire_record_atomic_request_row_fill_candidate_aligned = 0; - std::uint64_t w2_retire_record_atomic_request_row_fill_enable_aligned = 0; - std::uint64_t w2_retire_record_atomic_request_blocked_by_no_lifecycle_row = 0; - std::uint64_t w2_retire_record_atomic_request_blocked_by_no_row_fill_candidate = 0; - std::uint64_t w2_retire_record_atomic_request_blocked_by_no_row_fill_enable = 0; - std::uint64_t w2_retire_record_row_fill_enable_request_evidence_valid = 0; - std::uint64_t w2_retire_record_row_fill_enable_candidate_aligned = 0; - std::uint64_t w2_retire_record_row_fill_enable = 0; - std::uint64_t w2_retire_record_row_fill_enable_blocked_by_request_disabled = 0; - std::uint64_t w2_retire_record_row_fill_enable_blocked_by_no_lifecycle_row = 0; - std::uint64_t w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_capture_intent = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_capture_from_lifecycle = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_clear_accepted = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_provider_valid = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_provider_valid_without_record = 0; - std::uint64_t w2_retire_record_lifecycle_evidence_record_valid_without_provider = 0; - std::uint64_t w2_retire_record_lifecycle_clear_fallback_capture_physical_clear = 0; - std::uint64_t w2_retire_record_lifecycle_clear_fallback_candidate = 0; - std::uint64_t w2_retire_record_lifecycle_clear_fallback_duplicate_physical_clear = 0; - std::uint64_t w2_retire_record_lifecycle_clear_fallback_clear_valid = 0; - std::uint64_t w2_retire_record_rob_fallback_capture_physical_complete = 0; - std::uint64_t w2_retire_record_rob_fallback_candidate = 0; - std::uint64_t w2_retire_record_rob_fallback_duplicate_physical_complete = 0; - std::uint64_t w2_retire_record_rob_fallback_complete_valid = 0; - std::uint64_t w2_retire_record_rf_fallback_capture_physical_writeback = 0; - std::uint64_t w2_retire_record_rf_fallback_candidate = 0; - std::uint64_t w2_retire_record_rf_fallback_duplicate_physical_writeback = 0; - std::uint64_t w2_retire_record_rf_fallback_writeback_valid = 0; - std::uint64_t w2_retire_record_wakeup_fallback_capture_physical_wakeup = 0; - std::uint64_t w2_retire_record_wakeup_fallback_candidate = 0; - std::uint64_t w2_retire_record_wakeup_fallback_duplicate_physical_wakeup = 0; - std::uint64_t w2_retire_record_wakeup_fallback_wakeup_valid = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_candidate = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_all_candidates_ready = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_blocked_by_physical_duplicate = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_no_physical_probe_active = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_fallback_emit_probe_active = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_fallback_live_probe_active = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_retained_sole_owner_eligible = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_blocked_by_global_fallback_disabled = 0; - std::uint64_t w2_retire_record_fallback_owner_policy_side_effect_enable = 0; - std::uint64_t w2_retire_record_rob_fallback_live_complete_selected = 0; - std::uint64_t w2_retire_record_rf_fallback_live_writeback_selected = 0; - std::uint64_t w2_retire_record_wakeup_fallback_live_wakeup_selected = 0; - std::uint64_t w2_retire_record_lifecycle_clear_fallback_live_clear_selected = 0; - std::uint64_t w2_retire_record_model_order_record_candidate = 0; - std::uint64_t w2_retire_record_model_order_return_side_effects_ready = 0; - std::uint64_t w2_retire_record_model_order_retire_clear_evidence_ready = 0; - std::uint64_t w2_retire_record_model_order_return_then_retire_ready = 0; - std::uint64_t w2_retire_record_model_order_fallback_owner_eligible = 0; - std::uint64_t w2_retire_record_model_order_blocked_by_missing_return_side_effect = 0; - std::uint64_t w2_retire_record_model_order_blocked_by_missing_retire_clear_evidence = 0; - std::uint64_t w2_retire_record_model_order_blocked_by_owner_disabled = 0; - std::uint64_t w2_retire_record_default_promotion_record_candidate = 0; - std::uint64_t w2_retire_record_default_promotion_pre_arm_model_order_ready = 0; - std::uint64_t w2_retire_record_default_promotion_any_physical_duplicate = 0; - std::uint64_t w2_retire_record_default_promotion_ready = 0; - std::uint64_t w2_retire_record_default_promotion_blocked_by_no_record = 0; - std::uint64_t w2_retire_record_default_promotion_blocked_by_missing_fallback_candidate = 0; - std::uint64_t w2_retire_record_default_promotion_blocked_by_missing_lifecycle_evidence = 0; - std::uint64_t w2_retire_record_default_promotion_blocked_by_physical_duplicate = 0; - std::uint64_t w2_retire_record_default_promotion_blocked_by_probe_active = 0; - std::uint64_t w2_retire_record_duplicate_vector_valid = 0; - std::uint64_t w2_retire_record_duplicate_vector_return_side_effect_bundle = 0; - std::uint64_t w2_retire_record_duplicate_vector_model_order_bundle = 0; - std::uint64_t w2_retire_record_duplicate_vector_partial = 0; - std::uint64_t w2_retire_record_duplicate_vector_single = 0; - std::uint64_t w2_retire_record_duplicate_vector_multi = 0; - std::uint64_t w2_retire_record_duplicate_vector_count_sum = 0; - std::uint64_t w2_retire_record_duplicate_vector_next_requires_bundle_transfer = 0; - std::uint64_t w2_retire_record_duplicate_vector_blocked_by_no_record = 0; - std::uint64_t w2_retire_record_duplicate_vector_blocked_by_pre_arm_not_ready = 0; - std::uint64_t w2_retire_record_duplicate_vector_blocked_by_no_duplicate = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_candidate = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_pre_arm_ready = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_model_order_bundle = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_default_transfer_candidate = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_requires_physical_bundle_suppression = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_default_promotion_already_ready = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_blocked_by_no_record = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_blocked_by_pre_arm_not_ready = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_blocked_by_no_duplicate_vector = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_blocked_by_partial_duplicate = 0; - std::uint64_t w2_retire_record_bundle_transfer_plan_blocked_by_probe_active = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_transfer_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppression_required = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_physical_bundle_complete = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppress_rob_complete = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppress_rf_writeback = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppress_wakeup = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppress_lifecycle_clear = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_suppress_mask_sum = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_all_or_none_suppress = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_transfer_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_suppression_requirement = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_plan_blocked_by_incomplete_physical_bundle = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_enabled_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_selected = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_selected_mask_sum = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_all_or_none_input_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_blocked_by_probe_disabled = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_blocked_by_no_atomic_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_plan_promoted_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_selected = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_selected_mask_sum = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_all_or_none_input_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_selected_from_probe = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_selected_from_promotion = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_blocked_by_no_plan_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_capture = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_registered_valid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_registered_mask_sum = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_registered_full_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_blocked_by_no_selection = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_blocked_by_partial_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_boundary_cleared_by_flush = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_capture_identity = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_captured_identity_valid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_registered_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_retained_record_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_lifecycle_row_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_lifetime_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_eligible_registered_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_no_captured_identity = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_record = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_rid_mismatch = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_load_lsid_mismatch = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_lifecycle_evidence = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_lifecycle_row_mismatch = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_identity_blocked_by_not_full_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_capture_ownership = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_captured_ownership_valid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_registered_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_registered_rid_valid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_registered_load_lsid_valid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_registered_lifecycle_row_ready = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_registered_bundle_ready = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_blocked_by_no_captured_ownership = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_rid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_load_lsid = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_lifecycle_row = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_ownership_blocked_by_not_full_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_suppress_rob_complete = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_suppress_rf_writeback = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_suppress_wakeup = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_suppress_lifecycle_clear = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_suppress_mask_sum = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_all_or_none = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_live_mask_disabled = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_no_eligible_ownership = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_candidate = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_full_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_fire_complete_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_clear_intent_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_live_clear_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_row_fill_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_lifecycle_clear_suppressed = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_partial_mask = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_fire_complete = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_clear_intent = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_live_clear = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_row_fill = 0; - std::uint64_t w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_lifecycle_clear_still_enabled = 0; - std::uint64_t resolve_queue_push_accepted = 0; - std::uint64_t resolve_queue_valid = 0; - std::uint64_t resolve_queue_push_accepted_first_cycle = 0; - std::uint64_t resolve_queue_push_accepted_last_cycle = 0; - std::uint64_t resolve_queue_valid_first_cycle = 0; - std::uint64_t resolve_queue_valid_last_cycle = 0; - std::uint64_t mdb_conflict_store_valid = 0; - std::uint64_t mdb_conflict_store_valid_first_cycle = 0; - std::uint64_t mdb_conflict_store_valid_last_cycle = 0; - std::uint64_t mdb_conflict_store_with_resolve_queue_valid = 0; - std::uint64_t mdb_conflict_store_with_resolve_queue_valid_first_cycle = 0; - std::uint64_t mdb_conflict_store_with_resolve_queue_valid_last_cycle = 0; - std::uint64_t mdb_conflict_store_without_resolve_queue_valid = 0; - std::uint64_t mdb_conflict_active_candidate = 0; - std::uint64_t mdb_conflict_resolve_candidate = 0; - std::uint64_t mdb_conflict_resolve_candidate_first_cycle = 0; - std::uint64_t mdb_conflict_resolve_candidate_last_cycle = 0; - std::uint64_t mdb_conflict_valid = 0; - std::uint64_t mdb_fanout_record_valid = 0; - std::uint64_t mdb_fanout_record_accepted = 0; - std::uint64_t mdb_fanout_record_processed = 0; - std::uint64_t mdb_fanout_bmdb_report = 0; - std::uint64_t mdb_fanout_ssit_nonempty = 0; - std::uint64_t mdb_fanout_lookup_valid = 0; - std::uint64_t mdb_fanout_lookup_accepted = 0; - std::uint64_t mdb_fanout_lookup_processed = 0; - std::uint64_t mdb_fanout_lookup_table_hit = 0; - std::uint64_t mdb_fanout_lookup_first_after_nuke = 0; - std::uint64_t mdb_fanout_lookup_conf_blocked = 0; - std::uint64_t mdb_fanout_lookup_weight_blocked = 0; - std::uint64_t mdb_fanout_lu_out_valid = 0; - std::uint64_t mdb_fanout_lu_out_hit = 0; - std::uint64_t mdb_fanout_su_out_valid = 0; - std::uint64_t mdb_fanout_su_out_hit = 0; - std::uint64_t mdb_fanout_su_wakeup_valid = 0; - std::uint64_t mdb_lookup_wait_plan_lookup_hit = 0; - std::uint64_t mdb_lookup_wait_plan_wait_intent_valid = 0; - std::uint64_t mdb_lookup_wait_plan_request_valid = 0; - std::uint64_t mdb_lookup_wait_plan_blocked_by_no_target = 0; - std::uint64_t mdb_lookup_wait_plan_blocked_by_missing_store_index = 0; - std::uint64_t mdb_lookup_wait_plan_blocked_by_missing_store_lsid = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_active = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_valid = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_source_store_index_fits = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_blocked_by_disabled = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_blocked_by_flush = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_blocked_by_no_request = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_invalid_store_index_out_of_range = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_invalid_conflicting_status_write = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_invalid_wait_store_without_wait_status = 0; - std::uint64_t mdb_lookup_wait_plan_bridge_invalid_return_without_split_sources = 0; - std::uint64_t liq_row_mutation_bridge_valid = 0; - std::uint64_t liq_row_mutation_selected_source_return = 0; - std::uint64_t liq_row_mutation_selected_mdb_wait_plan = 0; - std::uint64_t liq_row_mutation_source_conflict = 0; - std::uint64_t mdb_wait_plan_row_mutation_write_enable = 0; - std::uint64_t liq_row_mutation_write_enable = 0; - std::uint64_t liq_row_mutation_apply_valid = 0; - std::uint64_t liq_row_mutation_blocked_by_bridge = 0; - std::uint64_t liq_row_mutation_blocked_by_control = 0; -}; - -ReplayLiqSidebandStats g_replay_liq_sideband_stats; -std::string g_replay_liq_sideband_stats_path; - -struct ReplayLretRobId { - bool valid = false; - bool wrap = false; - std::uint8_t value = 0; -}; - -std::vector g_replay_lret_shadow_queue; -std::vector g_replay_lret_committed_load_rob_ids; - -bool same_replay_lret_rob_id(const ReplayLretRobId &lhs, const ReplayLretRobId &rhs) { - return lhs.valid && rhs.valid && lhs.wrap == rhs.wrap && lhs.value == rhs.value; -} - -bool replay_lret_rob_id_seen(const std::vector &ids, const ReplayLretRobId &id) { - for (const auto &entry : ids) { - if (same_replay_lret_rob_id(entry, id)) { - return true; - } - } - return false; -} - -void remember_replay_lret_committed_load(const ReplayLretRobId &id) { - if (!id.valid || replay_lret_rob_id_seen(g_replay_lret_committed_load_rob_ids, id)) { - return; - } - g_replay_lret_committed_load_rob_ids.push_back(id); -} - -void observe_replay_lret_commit_history(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { -#if defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) || \ - defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) - if (dut.io_commit_rows_0_valid && dut.io_commit_rows_0_mem_valid && - !dut.io_commit_rows_0_mem_isStore && dut.io_commit_rows_0_rob_valid) { - ++g_replay_liq_sideband_stats.lret_commit_history_load_rows; - remember_replay_lret_committed_load({ - true, - static_cast(dut.io_commit_rows_0_rob_wrap), - static_cast(dut.io_commit_rows_0_rob_value) - }); - } - if (dut.io_commit_rows_1_valid && dut.io_commit_rows_1_mem_valid && - !dut.io_commit_rows_1_mem_isStore && dut.io_commit_rows_1_rob_valid) { - ++g_replay_liq_sideband_stats.lret_commit_history_load_rows; - remember_replay_lret_committed_load({ - true, - static_cast(dut.io_commit_rows_1_rob_wrap), - static_cast(dut.io_commit_rows_1_rob_value) - }); - } -#else - (void)dut; -#endif -} - -void observe_replay_lret_shadow_fifo(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { -#if defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) || \ - defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) - if (dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_shadow_drain; - if (g_replay_lret_shadow_queue.empty()) { - ++g_replay_liq_sideband_stats.lret_shadow_drain_missing; - } else { - const auto head = g_replay_lret_shadow_queue.front(); - g_replay_lret_shadow_queue.erase(g_replay_lret_shadow_queue.begin()); - const bool priorCommit = replay_lret_rob_id_seen(g_replay_lret_committed_load_rob_ids, head); - if (priorCommit) { - ++g_replay_liq_sideband_stats.lret_shadow_drain_after_prior_commit; - } - if (priorCommit && dut.io_reducedLoadReplayLiqLretIexDataRobRowBlockedByFree) { - ++g_replay_liq_sideband_stats.lret_shadow_free_after_prior_commit; - } - } - } - - if (dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted) { - ReplayLretRobId enqueued = { - static_cast(dut.io_reducedLoadReplayLiqLretPayloadRidValid), - static_cast(dut.io_reducedLoadReplayLiqLretPayloadRidWrap), - static_cast(dut.io_reducedLoadReplayLiqLretPayloadRidValue) - }; - ++g_replay_liq_sideband_stats.lret_shadow_enqueue; - if (replay_lret_rob_id_seen(g_replay_lret_committed_load_rob_ids, enqueued)) { - ++g_replay_liq_sideband_stats.lret_shadow_enqueue_after_prior_commit; - } - g_replay_lret_shadow_queue.push_back(enqueued); - } -#else - (void)dut; -#endif -} - -void observe_cycle(bool event, std::uint64_t cycle, std::uint64_t &first, std::uint64_t &last) { - if (event) { - if (first == 0) { - first = cycle; - } - last = cycle; - } -} - -void observe_replay_liq_sideband(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - ++g_replay_liq_sideband_stats.cycles_sampled; - if (dut.io_issueQueueSimultaneousPick) { - ++g_replay_liq_sideband_stats.issue_simultaneous_pick; - } - if (dut.io_issueQueueReadContention) { - ++g_replay_liq_sideband_stats.issue_read_contention; - } - if (dut.io_issueQueueReadArbitrationLoss) { - ++g_replay_liq_sideband_stats.issue_read_arbitration_loss; - } - if (dut.io_issueQueueCancelFire) { - ++g_replay_liq_sideband_stats.issue_cancel; - } - if (dut.io_issueQueueIssueContention) { - ++g_replay_liq_sideband_stats.issue_i2_contention; - } - if (dut.io_issueQueueControlFenceActive) { - ++g_replay_liq_sideband_stats.issue_control_fence_active; - } - if (dut.io_issueQueueControlFenceBlocked) { - ++g_replay_liq_sideband_stats.issue_control_fence_blocked; - } - if (dut.io_issueQueueStoreOrderBlocked) { - ++g_replay_liq_sideband_stats.issue_store_order_blocked; - } -#if defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) || \ - defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) - const std::uint64_t cycle = g_replay_liq_sideband_stats.cycles_sampled; - const std::uint64_t stq_occupied_mask = - static_cast(dut.io_storeStqOccupiedMask); - const std::uint64_t stq_addr_ready_mask = - static_cast(dut.io_storeStqAddrReadyMask); - const std::uint64_t stq_data_ready_mask = - static_cast(dut.io_storeStqDataReadyMask); - const std::uint64_t stq_addr_ready_resident_mask = - stq_occupied_mask & stq_addr_ready_mask; - const std::uint64_t stq_data_ready_resident_mask = - stq_occupied_mask & stq_data_ready_mask; - const std::uint64_t stq_addr_ready_not_data_ready_mask = - stq_addr_ready_resident_mask & ~stq_data_ready_mask; - const std::uint64_t stq_addr_and_data_ready_mask = - stq_addr_ready_resident_mask & stq_data_ready_mask; - const bool load_lookup_execute_granted = dut.io_loadLookupExecuteGranted; - const bool stq_addr_ready_not_data_ready = stq_addr_ready_not_data_ready_mask != 0; - const bool stq_addr_and_data_ready = stq_addr_and_data_ready_mask != 0; - const bool load_lookup_execute_with_addr_ready_not_data_ready = - load_lookup_execute_granted && stq_addr_ready_not_data_ready; - const bool w2_slot_occupied = dut.io_reducedLoadReplayLiqLretPipeW2SlotOccupied; - const bool w2_completion_clear_slot = - dut.io_reducedLoadReplayLiqLretPipeW2CompletionClearSlot; - const bool w2_clear_intent = - dut.io_reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent; - const bool w2_side_effect_fire_complete = - dut.io_reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete; - const bool w2_live_clear = - dut.io_reducedLoadReplayLiqLretPipeW2ClearIntentLiveClear; - static bool previous_lret_sink_enqueue_accepted_w2 = false; - static bool previous_lret_sink_enqueue_w2_completion_clear_slot = false; - static bool previous_lret_sink_enqueue_w2_clear_intent = false; - static bool previous_lret_sink_enqueue_w2_side_effect_fire_complete = false; - static bool previous_lret_sink_enqueue_w2_live_clear = false; - if (previous_lret_sink_enqueue_accepted_w2) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_accepted_w2; - if (w2_slot_occupied) { - ++g_replay_liq_sideband_stats.lret_sink_followup_w2_still_occupied; - } else { - ++g_replay_liq_sideband_stats.lret_sink_followup_w2_cleared; - } - if (previous_lret_sink_enqueue_w2_completion_clear_slot) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_completion_clear_slot; - if (!w2_slot_occupied) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_completion_clear_slot_w2_cleared; - } - } - if (previous_lret_sink_enqueue_w2_clear_intent) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_clear_intent; - if (!w2_slot_occupied) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_clear_intent_w2_cleared; - } - } - if (previous_lret_sink_enqueue_w2_side_effect_fire_complete) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_side_effect_fire_complete; - if (!w2_slot_occupied) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_side_effect_fire_complete_w2_cleared; - } - } - if (previous_lret_sink_enqueue_w2_live_clear) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_live_clear; - if (!w2_slot_occupied) { - ++g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_live_clear_w2_cleared; - } - } - if (dut.io_reducedLoadReplayLiqLretSinkPending) { - ++g_replay_liq_sideband_stats.lret_sink_pending_after_enqueue_accepted_w2; - } - if (dut.io_reducedLoadReplayLiqLretSinkDrainValid) { - ++g_replay_liq_sideband_stats.lret_sink_drain_valid_after_enqueue_accepted_w2; - } - if (dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_drain_fire_after_enqueue_accepted_w2; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitReady) { - ++g_replay_liq_sideband_stats.lret_drain_permit_ready_after_enqueue_accepted_w2; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitAnyPipeFree) { - ++g_replay_liq_sideband_stats.lret_drain_permit_pipe_free_after_enqueue_accepted_w2; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull) { - ++g_replay_liq_sideband_stats.lret_drain_permit_pipe_full_after_enqueue_accepted_w2; - } - } - observe_cycle( - load_lookup_execute_granted, - cycle, - g_replay_liq_sideband_stats.load_lookup_execute_granted_first_cycle, - g_replay_liq_sideband_stats.load_lookup_execute_granted_last_cycle); - observe_cycle( - stq_addr_ready_not_data_ready, - cycle, - g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready_first_cycle, - g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready_last_cycle); - observe_cycle( - stq_addr_and_data_ready, - cycle, - g_replay_liq_sideband_stats.store_stq_addr_and_data_ready_first_cycle, - g_replay_liq_sideband_stats.store_stq_addr_and_data_ready_last_cycle); - observe_cycle( - load_lookup_execute_with_addr_ready_not_data_ready, - cycle, - g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready_first_cycle, - g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready_last_cycle); - observe_cycle( - dut.io_storeStaDequeueFire, - cycle, - g_replay_liq_sideband_stats.store_sta_dequeue_fire_first_cycle, - g_replay_liq_sideband_stats.store_sta_dequeue_fire_last_cycle); - observe_cycle( - dut.io_storeStdDequeueFire, - cycle, - g_replay_liq_sideband_stats.store_std_dequeue_fire_first_cycle, - g_replay_liq_sideband_stats.store_std_dequeue_fire_last_cycle); - observe_cycle( - dut.io_reducedStoreStaExecValid, - cycle, - g_replay_liq_sideband_stats.store_sta_exec_valid_first_cycle, - g_replay_liq_sideband_stats.store_sta_exec_valid_last_cycle); - observe_cycle( - dut.io_reducedStoreStdExecValid, - cycle, - g_replay_liq_sideband_stats.store_std_exec_valid_first_cycle, - g_replay_liq_sideband_stats.store_std_exec_valid_last_cycle); - const bool resolve_queue_push_accepted = dut.io_reducedLoadReplayResolveQueuePushAccepted; - const bool resolve_queue_valid = dut.io_reducedLoadReplayResolveQueueValidMask != 0; - const bool mdb_conflict_store_valid = dut.io_reducedMdbConflictStoreValid; - const bool mdb_conflict_store_with_resolve_queue_valid = - mdb_conflict_store_valid && resolve_queue_valid; - const bool mdb_conflict_resolve_candidate = - dut.io_reducedMdbConflictResolveCandidateMask != 0; - observe_cycle( - resolve_queue_push_accepted, - cycle, - g_replay_liq_sideband_stats.resolve_queue_push_accepted_first_cycle, - g_replay_liq_sideband_stats.resolve_queue_push_accepted_last_cycle); - observe_cycle( - resolve_queue_valid, - cycle, - g_replay_liq_sideband_stats.resolve_queue_valid_first_cycle, - g_replay_liq_sideband_stats.resolve_queue_valid_last_cycle); - observe_cycle( - mdb_conflict_store_valid, - cycle, - g_replay_liq_sideband_stats.mdb_conflict_store_valid_first_cycle, - g_replay_liq_sideband_stats.mdb_conflict_store_valid_last_cycle); - observe_cycle( - mdb_conflict_store_with_resolve_queue_valid, - cycle, - g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid_first_cycle, - g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid_last_cycle); - observe_cycle( - mdb_conflict_resolve_candidate, - cycle, - g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate_first_cycle, - g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate_last_cycle); - if (dut.io_loadLookupValid) { - ++g_replay_liq_sideband_stats.load_lookup_valid; - } - if (load_lookup_execute_granted) { - ++g_replay_liq_sideband_stats.load_lookup_execute_granted; - } - if (load_lookup_execute_granted && dut.io_reducedStoreResidentEligibleMask != 0) { - ++g_replay_liq_sideband_stats.load_lookup_execute_with_eligible_store; - } - if (load_lookup_execute_granted && dut.io_reducedStoreResidentWaitStoreValid) { - ++g_replay_liq_sideband_stats.load_lookup_execute_with_wait_store; - } - if (dut.io_executeLoadWaitHold) { - ++g_replay_liq_sideband_stats.execute_load_wait_hold; - } - if (dut.io_reducedStoreResidentEligibleMask != 0) { - ++g_replay_liq_sideband_stats.resident_store_eligible; - } - if (dut.io_reducedStoreResidentReadyForward) { - ++g_replay_liq_sideband_stats.resident_store_ready_forward; - } - if (dut.io_reducedStoreResidentWaitBlocked) { - ++g_replay_liq_sideband_stats.resident_store_wait_blocked; - } - if (dut.io_reducedStoreResidentWaitStoreValid) { - ++g_replay_liq_sideband_stats.resident_store_wait_store_valid; - } - if (stq_occupied_mask != 0) { - ++g_replay_liq_sideband_stats.store_stq_resident; - } - if (stq_addr_ready_resident_mask != 0) { - ++g_replay_liq_sideband_stats.store_stq_addr_ready; - } - if (stq_data_ready_resident_mask != 0) { - ++g_replay_liq_sideband_stats.store_stq_data_ready; - } - if (stq_addr_ready_not_data_ready) { - ++g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready; - } - if (stq_addr_and_data_ready) { - ++g_replay_liq_sideband_stats.store_stq_addr_and_data_ready; - } - if (load_lookup_execute_with_addr_ready_not_data_ready) { - ++g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready; - } - if (dut.io_storeStaQueueValid) { - ++g_replay_liq_sideband_stats.store_sta_queue_valid; - } - if (dut.io_storeStdQueueValid) { - ++g_replay_liq_sideband_stats.store_std_queue_valid; - } - if (dut.io_storeStaQueueValid && !dut.io_storeStdQueueValid) { - ++g_replay_liq_sideband_stats.store_sta_queue_only_valid; - } - if (dut.io_storeStaDequeueFire) { - ++g_replay_liq_sideband_stats.store_sta_dequeue_fire; - } - if (dut.io_storeStdDequeueFire) { - ++g_replay_liq_sideband_stats.store_std_dequeue_fire; - } - if (dut.io_reducedStoreStaExecValid) { - ++g_replay_liq_sideband_stats.store_sta_exec_valid; - } - if (dut.io_reducedStoreStdExecValid) { - ++g_replay_liq_sideband_stats.store_std_exec_valid; - } - if (dut.io_reducedStoreStaExecValid && !dut.io_reducedStoreStdExecValid) { - ++g_replay_liq_sideband_stats.store_sta_exec_only_valid; - } - if (dut.io_reducedStoreResidentReplayWakeValid) { - ++g_replay_liq_sideband_stats.resident_store_wake_valid; - } - if (dut.io_reducedStoreResidentReplayWakeReady) { - ++g_replay_liq_sideband_stats.resident_store_wake_ready; - } - if (dut.io_reducedLoadWaitReplayCaptureAccepted) { - ++g_replay_liq_sideband_stats.wait_replay_capture_accepted; - } - if (dut.io_reducedLoadWaitReplayClearValid) { - ++g_replay_liq_sideband_stats.wait_replay_clear_valid; - } - if (dut.io_reducedLoadWaitReplayRelaunchValid) { - ++g_replay_liq_sideband_stats.wait_replay_relaunch_valid; - } - if (dut.io_reducedLoadReplayQueueEnqueueAccepted) { - ++g_replay_liq_sideband_stats.replay_queue_enqueue_accepted; - } - if (dut.io_reducedLoadReplayQueueOutValid) { - ++g_replay_liq_sideband_stats.replay_queue_out_valid; - } - if (dut.io_reducedLoadReplayQueueOutFire) { - ++g_replay_liq_sideband_stats.replay_queue_out_fire; - } - if (dut.io_reducedLoadReplayLiqAllocValid) { - ++g_replay_liq_sideband_stats.liq_alloc_valid; - } - if (dut.io_reducedLoadReplayLiqAllocAccepted) { - ++g_replay_liq_sideband_stats.liq_alloc_accepted; - } - if (dut.io_reducedLoadReplayLiqLaunchValid) { - ++g_replay_liq_sideband_stats.liq_launch_valid; - } - if (dut.io_reducedLoadReplayLiqLaunchAccepted) { - ++g_replay_liq_sideband_stats.liq_launch_accepted; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteRepickMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_repick_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteSourceReturnedMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_source_returned_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteDataCompleteMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_data_complete_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteRequestCompleteMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_request_complete_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteCandidateMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_candidate_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteMask != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteValid) { - ++g_replay_liq_sideband_stats.liq_return_complete_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqReturnCompleteValid) { - ++g_replay_liq_sideband_stats.liq_return_complete_valid_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqReturnCompleteCandidateCount != 0) { - ++g_replay_liq_sideband_stats.liq_return_complete_candidate_count_nonzero; - } - if (dut.io_reducedLoadReplayLiqBaseLookupValid) { - ++g_replay_liq_sideband_stats.liq_base_lookup_valid; - } - if (dut.io_reducedLoadReplayLiqBaseLookupGranted) { - ++g_replay_liq_sideband_stats.liq_base_lookup_granted; - } - if (dut.io_reducedLoadReplayLiqBaseDataReturned) { - ++g_replay_liq_sideband_stats.liq_base_data_returned; - } - if (dut.io_reducedLoadReplayLiqBaseLineValidMask != 0) { - ++g_replay_liq_sideband_stats.liq_base_line_valid_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessCandidateValid) { - ++g_replay_liq_sideband_stats.launch_readiness_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBaseDataReady) { - ++g_replay_liq_sideband_stats.launch_readiness_base_data_ready; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessSourcesReturned) { - ++g_replay_liq_sideband_stats.launch_readiness_sources_returned; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessReady) { - ++g_replay_liq_sideband_stats.launch_readiness_ready; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessEnable) { - ++g_replay_liq_sideband_stats.launch_readiness_enable; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByDisabled) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_base_lookup; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseData) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_base_data; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByScb) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_scb; - } - if (dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByReturn) { - ++g_replay_liq_sideband_stats.launch_readiness_blocked_by_return; - } - if (dut.io_reducedLoadReplayLiqWaitStoreMask != 0) { - ++g_replay_liq_sideband_stats.liq_wait_store_mask_nonzero; - } - const bool liq_replay_wake_valid = dut.io_reducedLoadReplayLiqReplayWakeValid; - const bool liq_replay_wake_flush = dut.io_reducedLoadReplayLiqReplayWakeFlush; - const bool liq_replay_wake_store_unit_full_match = - dut.io_reducedLoadReplayLiqReplayWakeStoreUnitFullMatchMask != 0; - if (liq_replay_wake_valid) { - ++g_replay_liq_sideband_stats.liq_replay_wake_valid; - } - if (liq_replay_wake_valid && !liq_replay_wake_flush) { - ++g_replay_liq_sideband_stats.liq_replay_wake_active; - } - if (dut.io_reducedLoadReplayLiqReplayWakeWaitStoreCandidateMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_wait_store_candidate; - } - if (dut.io_reducedLoadReplayLiqReplayWakeBidMatchMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_bid_match; - } - if (dut.io_reducedLoadReplayLiqReplayWakeLsIdMatchMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_lsid_match; - } - if (dut.io_reducedLoadReplayLiqReplayWakePcMatchMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_pc_match; - } - if (dut.io_reducedLoadReplayLiqReplayWakeFullMatchMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_full_match; - } - if (dut.io_reducedLoadReplayLiqReplayWakeStoreUnit) { - ++g_replay_liq_sideband_stats.liq_replay_wake_store_unit; - } - if (liq_replay_wake_store_unit_full_match) { - ++g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match; - } - if (liq_replay_wake_store_unit_full_match && !liq_replay_wake_flush) { - ++g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match_active; - } - if (liq_replay_wake_valid && liq_replay_wake_flush && liq_replay_wake_store_unit_full_match) { - ++g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match_flush_blocked; - } - if (dut.io_reducedLoadReplayLiqReplayWakeWaitStoreClearMask != 0) { - ++g_replay_liq_sideband_stats.liq_replay_wake_wait_store_clear; - } - if (dut.io_reducedLoadReplayLiqSourceReturnCandidateValid) { - ++g_replay_liq_sideband_stats.source_return_candidate_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqSourceReturnCandidateValid) { - ++g_replay_liq_sideband_stats.source_return_candidate_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotReady) { - ++g_replay_liq_sideband_stats.source_return_store_snapshot_ready; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotReady) { - ++g_replay_liq_sideband_stats.source_return_store_snapshot_ready_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSourceReturned) { - ++g_replay_liq_sideband_stats.source_return_store_source_returned; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbSourceReturned) { - ++g_replay_liq_sideband_stats.source_return_scb_source_returned; - } - if (dut.io_reducedLoadReplayLiqSourceReturnSourceReturned) { - ++g_replay_liq_sideband_stats.source_return_source_returned; - } - if (dut.io_reducedLoadReplayLiqSourceReturnBlockedByDisabled) { - ++g_replay_liq_sideband_stats.source_return_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqSourceReturnBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.source_return_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqSourceReturnBlockedByBaseData) { - ++g_replay_liq_sideband_stats.source_return_blocked_by_base_data; - } - if (dut.io_reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot) { - ++g_replay_liq_sideband_stats.source_return_blocked_by_store_snapshot; - } - if (dut.io_reducedLoadReplayLiqSourceReturnBlockedByScb) { - ++g_replay_liq_sideband_stats.source_return_blocked_by_scb; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveRequestActive) { - ++g_replay_liq_sideband_stats.source_return_store_snapshot_live_request_active; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveEvidenceValid) { - ++g_replay_liq_sideband_stats.source_return_store_snapshot_live_evidence_valid; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveActive) { - ++g_replay_liq_sideband_stats.source_return_scb_live_active; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveRequestActive) { - ++g_replay_liq_sideband_stats.source_return_scb_live_request_active; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveEvidenceValid) { - ++g_replay_liq_sideband_stats.source_return_scb_live_evidence_valid; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLivePending) { - ++g_replay_liq_sideband_stats.source_return_scb_live_pending; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveReturned) { - ++g_replay_liq_sideband_stats.source_return_scb_live_returned; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveBlockedByRequestDisabled) { - ++g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_request_disabled; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveBlockedByNoPending) { - ++g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_no_pending; - } - if (dut.io_reducedLoadReplayLiqSourceReturnScbLiveBlockedByScbReturn) { - ++g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_scb_return; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued) { - ++g_replay_liq_sideband_stats.source_return_query_issued; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued) { - ++g_replay_liq_sideband_stats.source_return_query_issued_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid) { - ++g_replay_liq_sideband_stats.source_return_response_apply_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid) { - ++g_replay_liq_sideband_stats.source_return_response_apply_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanValid) { - ++g_replay_liq_sideband_stats.source_return_row_state_plan_valid; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid) { - ++g_replay_liq_sideband_stats.source_row_mutation_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit) { - ++g_replay_liq_sideband_stats.source_row_mutation_live_permit; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid) { - ++g_replay_liq_sideband_stats.source_row_mutation_request_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid) { - ++g_replay_liq_sideband_stats.source_row_mutation_request_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof) { - ++g_replay_liq_sideband_stats.source_row_mutation_blocked_by_head_proof; - } - if (dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByLiveDisabled) { - ++g_replay_liq_sideband_stats.source_row_mutation_blocked_by_live_disabled; - } - if (dut.io_reducedLoadReplayLiqReturnDataCandidateValid) { - ++g_replay_liq_sideband_stats.return_data_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqReturnDataRequestByteMask != 0) { - ++g_replay_liq_sideband_stats.return_data_request_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqReturnDataBytesComplete) { - ++g_replay_liq_sideband_stats.return_data_bytes_complete; - } - if (dut.io_reducedLoadReplayLiqReturnDataCrossLine) { - ++g_replay_liq_sideband_stats.return_data_cross_line; - } - if (dut.io_reducedLoadReplayLiqReturnDataSizeSupported) { - ++g_replay_liq_sideband_stats.return_data_size_supported; - } - if (dut.io_reducedLoadReplayLiqReturnDataValid) { - ++g_replay_liq_sideband_stats.return_data_valid; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByDisabled) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByZeroSize) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_zero_size; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByUnsupportedSize) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_unsupported_size; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByCrossLine) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_cross_line; - } - if (dut.io_reducedLoadReplayLiqReturnDataBlockedByIncompleteBytes) { - ++g_replay_liq_sideband_stats.return_data_blocked_by_incomplete_bytes; - } - if (dut.io_reducedLoadReplayLiqReturnPublishCandidateValid) { - ++g_replay_liq_sideband_stats.return_publish_candidate_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqReturnPublishCandidateValid) { - ++g_replay_liq_sideband_stats.return_publish_candidate_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqReturnPublishDataReady) { - ++g_replay_liq_sideband_stats.return_publish_data_ready; - } - if (dut.io_reducedLoadReplayLiqReturnPublishReady) { - ++g_replay_liq_sideband_stats.return_publish_ready; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqReturnPublishReady) { - ++g_replay_liq_sideband_stats.return_publish_ready_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqReturnPublishBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.return_publish_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqReturnPublishBlockedByData) { - ++g_replay_liq_sideband_stats.return_publish_blocked_by_data; - } - if (dut.io_reducedLoadReplayLiqReturnPublishBlockedByConsumer) { - ++g_replay_liq_sideband_stats.return_publish_blocked_by_consumer; - } - if (dut.io_reducedLoadReplayLiqLretPayloadCandidateValid) { - ++g_replay_liq_sideband_stats.lret_payload_candidate_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPayloadCandidateValid) { - ++g_replay_liq_sideband_stats.lret_payload_candidate_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPayloadValid) { - ++g_replay_liq_sideband_stats.lret_payload_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPayloadValid) { - ++g_replay_liq_sideband_stats.lret_payload_valid_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPayloadWakeupRequired) { - ++g_replay_liq_sideband_stats.lret_payload_wakeup_required; - } - if (dut.io_reducedLoadReplayLiqLretPayloadBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.lret_payload_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPayloadBlockedByData) { - ++g_replay_liq_sideband_stats.lret_payload_blocked_by_data; - } - if (dut.io_reducedLoadReplayLiqPublishControlCandidateValid) { - ++g_replay_liq_sideband_stats.publish_control_candidate_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqPublishControlCandidateValid) { - ++g_replay_liq_sideband_stats.publish_control_candidate_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqPublishControlLiveEnable) { - ++g_replay_liq_sideband_stats.publish_control_live_enable; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqPublishControlLiveEnable) { - ++g_replay_liq_sideband_stats.publish_control_live_enable_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqPublishControlArmed) { - ++g_replay_liq_sideband_stats.publish_control_armed; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqPublishControlArmed) { - ++g_replay_liq_sideband_stats.publish_control_armed_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqPublishControlFire) { - ++g_replay_liq_sideband_stats.publish_control_fire; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqPublishControlFire) { - ++g_replay_liq_sideband_stats.publish_control_fire_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqPublishControlBlockedByNoPayload) { - ++g_replay_liq_sideband_stats.publish_control_blocked_by_no_payload; - } - if (dut.io_reducedLoadReplayLiqPublishControlBlockedByPublish) { - ++g_replay_liq_sideband_stats.publish_control_blocked_by_publish; - } - if (dut.io_reducedLoadReplayLiqPublishControlBlockedBySideEffects) { - ++g_replay_liq_sideband_stats.publish_control_blocked_by_side_effects; - } - if (dut.io_reducedLoadReplayLiqPublishControlBlockedByLiveDisabled) { - ++g_replay_liq_sideband_stats.publish_control_blocked_by_live_disabled; - } - if (dut.io_reducedLoadReplayLiqPublishRequestValid) { - ++g_replay_liq_sideband_stats.publish_request_valid; - } - if (dut.io_reducedLoadReplayLiqPublishRequestLret) { - ++g_replay_liq_sideband_stats.publish_request_lret; - } - if (dut.io_reducedLoadReplayLiqPublishRequestWriteback) { - ++g_replay_liq_sideband_stats.publish_request_writeback; - } - if (dut.io_reducedLoadReplayLiqPublishRequestWakeup) { - ++g_replay_liq_sideband_stats.publish_request_wakeup; - } - if (dut.io_reducedLoadReplayLiqPublishRequestMask != 0) { - ++g_replay_liq_sideband_stats.publish_request_mask_nonzero; - } - if (dut.io_reducedLoadReplayLiqPublishRequestBlockedByNoFire) { - ++g_replay_liq_sideband_stats.publish_request_blocked_by_no_fire; - } - if (dut.io_reducedLoadReplayLiqPublishRequestInvalidFireWithoutPayload) { - ++g_replay_liq_sideband_stats.publish_request_invalid_fire_without_payload; - } - if (dut.io_reducedLoadReplayLiqLretSinkEnqueueReady) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_ready; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkEnqueueReady) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_ready_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretSinkEnqueueDropped) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_dropped; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkEnqueueDropped) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_dropped_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretSinkDrainValid) { - ++g_replay_liq_sideband_stats.lret_sink_drain_valid; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkDrainValid) { - ++g_replay_liq_sideband_stats.lret_sink_drain_valid_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_drain_fire; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_drain_fire_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_same_cycle_drain_fire; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_same_cycle_drain_fire_w2_occupied; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - !dut.io_reducedLoadReplayLiqLretSinkDrainFire) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_without_drain_fire; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - w2_completion_clear_slot) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_completion_clear_slot; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - w2_clear_intent) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_clear_intent; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - w2_side_effect_fire_complete) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_side_effect_fire_complete; - } - if (w2_slot_occupied && - dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted && - w2_live_clear) { - ++g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_live_clear; - } - previous_lret_sink_enqueue_accepted_w2 = - w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkEnqueueAccepted; - previous_lret_sink_enqueue_w2_completion_clear_slot = - previous_lret_sink_enqueue_accepted_w2 && w2_completion_clear_slot; - previous_lret_sink_enqueue_w2_clear_intent = - previous_lret_sink_enqueue_accepted_w2 && w2_clear_intent; - previous_lret_sink_enqueue_w2_side_effect_fire_complete = - previous_lret_sink_enqueue_accepted_w2 && w2_side_effect_fire_complete; - previous_lret_sink_enqueue_w2_live_clear = - previous_lret_sink_enqueue_accepted_w2 && w2_live_clear; - if (dut.io_reducedLoadReplayLiqLretSinkPending) { - ++g_replay_liq_sideband_stats.lret_sink_pending; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretSinkPending) { - ++g_replay_liq_sideband_stats.lret_sink_pending_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPayloadValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_payload_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureAccepted) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_accepted; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureAccepted) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_accepted_w2_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCaptureDropped) { - ++g_replay_liq_sideband_stats.w2_retire_record_capture_dropped; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRecordValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_record_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRecordReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_record_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRecordFire) { - ++g_replay_liq_sideband_stats.w2_retire_record_record_fire; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPending) { - ++g_replay_liq_sideband_stats.w2_retire_record_pending; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCapturedWithLretEnqueue) { - ++g_replay_liq_sideband_stats.w2_retire_record_captured_with_lret_enqueue; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRecordFromLretEnqueue) { - ++g_replay_liq_sideband_stats.w2_retire_record_record_from_lret_enqueue; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByInvalidPayload) { - ++g_replay_liq_sideband_stats.w2_retire_record_blocked_by_invalid_payload; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBlockedByFull) { - ++g_replay_liq_sideband_stats.w2_retire_record_blocked_by_full; - } - if (dut.io_reducedLoadReplayLiqLretSinkFull) { - ++g_replay_liq_sideband_stats.lret_sink_full; - } - if (dut.io_reducedLoadReplayLiqLretSinkBlockedByNoPayload) { - ++g_replay_liq_sideband_stats.lret_sink_blocked_by_no_payload; - } - if (dut.io_reducedLoadReplayLiqLretSinkBlockedByFull) { - ++g_replay_liq_sideband_stats.lret_sink_blocked_by_full; - } - if (dut.io_reducedLoadReplayLiqLretSinkBlockedByDrain) { - ++g_replay_liq_sideband_stats.lret_sink_blocked_by_drain; - } - observe_replay_lret_shadow_fifo(dut); - observe_replay_lret_commit_history(dut); - if (dut.io_reducedLoadReplayLiqLretDrainPermitAnyPipeFree) { - ++g_replay_liq_sideband_stats.lret_drain_permit_any_pipe_free; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitReady) { - ++g_replay_liq_sideband_stats.lret_drain_permit_ready; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitBlockedByNoEntry) { - ++g_replay_liq_sideband_stats.lret_drain_permit_blocked_by_no_entry; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitBlockedByPipeFull) { - ++g_replay_liq_sideband_stats.lret_drain_permit_blocked_by_pipe_full; - } - if (dut.io_reducedLoadReplayLiqLretDrainPermitPipeOccupiedMask != 0) { - ++g_replay_liq_sideband_stats.lret_drain_permit_pipe_occupied; - } - if (dut.io_reducedLoadReplayLiqLretIexDataRobRowValid) { - ++g_replay_liq_sideband_stats.lret_iex_data_rob_row_valid; - } - if (dut.io_reducedLoadReplayLiqLretIexDataRobRowNeedFlush) { - ++g_replay_liq_sideband_stats.lret_iex_data_rob_row_need_flush; - } - if (dut.io_reducedLoadReplayLiqLretIexDataRobRowBlockedByInvalidRid) { - ++g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_invalid_rid; - } - if (dut.io_reducedLoadReplayLiqLretIexDataRobRowBlockedByFree) { - ++g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_free; - } - if (dut.io_reducedLoadReplayLiqLretIexDataRobRowBlockedByStaleRid) { - ++g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_stale_rid; - } - if (dut.io_reducedLoadReplayLiqLretIexDataCandidateValid) { - ++g_replay_liq_sideband_stats.lret_iex_data_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretIexDataWouldDrain) { - ++g_replay_liq_sideband_stats.lret_iex_data_would_drain; - } - if (dut.io_reducedLoadReplayLiqLretIexDataSetMemDataValid) { - ++g_replay_liq_sideband_stats.lret_iex_data_set_mem_data_valid; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByNoEntry) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_no_entry; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByInvalidEntry) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_invalid_entry; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByDrain) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_drain; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByRobMissing) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_rob_missing; - } - if (dut.io_reducedLoadReplayLiqLretIexDataBlockedByNeedFlush) { - ++g_replay_liq_sideband_stats.lret_iex_data_blocked_by_need_flush; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveCandidateValid) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveValid) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_valid; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveReadyForPipeInsert) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_ready_for_pipe_insert; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveMarkAllDestinationsDataValid) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_mark_all_destinations_data_valid; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveMarkDestinationDataValid) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_mark_destination_data_valid; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveRetLaneIncrement) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_ret_lane_increment; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByNoSetMemData) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_no_set_mem_data; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByUnsupportedMultiLane) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_unsupported_multi_lane; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByInvalidRid) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_invalid_rid; - } - if (dut.io_reducedLoadReplayLiqLretRobResolveBlockedByNoDestination) { - ++g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_no_destination; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionCandidateValid) { - ++g_replay_liq_sideband_stats.lret_lane_completion_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionCompleteValid) { - ++g_replay_liq_sideband_stats.lret_lane_completion_complete_valid; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionReadyForPipeInsert) { - ++g_replay_liq_sideband_stats.lret_lane_completion_ready_for_pipe_insert; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionRequiresAllLanes) { - ++g_replay_liq_sideband_stats.lret_lane_completion_requires_all_lanes; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByNoResolve) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_no_resolve; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByZeroReturnedLanes) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_zero_returned_lanes; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByInvalidRealReqCnt) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_invalid_real_req_cnt; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByScalarLoadPairIncomplete) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_scalar_load_pair_incomplete; - } - if (dut.io_reducedLoadReplayLiqLretLaneCompletionBlockedByVectorMemIncomplete) { - ++g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_vector_mem_incomplete; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionCandidateValid) { - ++g_replay_liq_sideband_stats.lret_tload_completion_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionTloadCandidateValid) { - ++g_replay_liq_sideband_stats.lret_tload_completion_tload_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionTileScbSendValid) { - ++g_replay_liq_sideband_stats.lret_tload_completion_tile_scb_send_valid; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionTileScbIsLast) { - ++g_replay_liq_sideband_stats.lret_tload_completion_tile_scb_is_last; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionCompleteValid) { - ++g_replay_liq_sideband_stats.lret_tload_completion_complete_valid; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionReadyForPipeInsert) { - ++g_replay_liq_sideband_stats.lret_tload_completion_ready_for_pipe_insert; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionBlockedByNoLaneCompletion) { - ++g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_no_lane_completion; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionBlockedByInvalidSubInstCnt) { - ++g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_invalid_sub_inst_cnt; - } - if (dut.io_reducedLoadReplayLiqLretTloadCompletionBlockedByTloadPending) { - ++g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_tload_pending; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataCandidateValid) { - ++g_replay_liq_sideband_stats.lret_final_metadata_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataIsLoadReturnMarked) { - ++g_replay_liq_sideband_stats.lret_final_metadata_is_load_return_marked; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveCalled) { - ++g_replay_liq_sideband_stats.lret_final_metadata_load_branch_resolve_called; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataLoadBranchResolveSideEffectValid) { - ++g_replay_liq_sideband_stats.lret_final_metadata_load_branch_resolve_side_effect_valid; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataPipeCycleSidebandValid) { - ++g_replay_liq_sideband_stats.lret_final_metadata_pipe_cycle_sideband_valid; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataReadyForPipeInsert) { - ++g_replay_liq_sideband_stats.lret_final_metadata_ready_for_pipe_insert; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretFinalMetadataBlockedByNoTloadCompletion) { - ++g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_no_tload_completion; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsCandidateValid) { - ++g_replay_liq_sideband_stats.lret_timing_stats_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsSidebandValid) { - ++g_replay_liq_sideband_stats.lret_timing_stats_sideband_valid; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsIqNameSidebandValid) { - ++g_replay_liq_sideband_stats.lret_timing_stats_iq_name_sideband_valid; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsLdRntCycleValid) { - ++g_replay_liq_sideband_stats.lret_timing_stats_ld_rnt_cycle_valid; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsUpdateValid) { - ++g_replay_liq_sideband_stats.lret_timing_stats_update_valid; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsLatencyUnderflow) { - ++g_replay_liq_sideband_stats.lret_timing_stats_latency_underflow; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsReadyForPipeInsert) { - ++g_replay_liq_sideband_stats.lret_timing_stats_ready_for_pipe_insert; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsBlockedByDisabled) { - ++g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_disabled; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsBlockedByFlush) { - ++g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretTimingStatsBlockedByNoFinalMetadata) { - ++g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_no_final_metadata; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertCandidateValid) { - ++g_replay_liq_sideband_stats.lret_iex_insert_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertValid) { - ++g_replay_liq_sideband_stats.lret_iex_insert_valid; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertIsLoadReturn) { - ++g_replay_liq_sideband_stats.lret_iex_insert_is_load_return; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertWakeupRequired) { - ++g_replay_liq_sideband_stats.lret_iex_insert_wakeup_required; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertBlockedByNoSetMemData) { - ++g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_no_set_mem_data; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertBlockedByNoPipe) { - ++g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_no_pipe; - } - if (dut.io_reducedLoadReplayLiqLretIexPipeInsertBlockedByInvalidRid) { - ++g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_invalid_rid; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyCandidateValid) { - ++g_replay_liq_sideband_stats.lret_residency_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyWriteValid) { - ++g_replay_liq_sideband_stats.lret_residency_write_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyLiveEnable) { - ++g_replay_liq_sideband_stats.lret_residency_live_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyBlockedByLiveDisabled) { - ++g_replay_liq_sideband_stats.lret_residency_blocked_by_live_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencySlotAccepted) { - ++g_replay_liq_sideband_stats.lret_residency_slot_accepted; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencySlotOccupied) { - ++g_replay_liq_sideband_stats.lret_residency_slot_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyAdvanceCandidateValid) { - ++g_replay_liq_sideband_stats.lret_residency_advance_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyAdvanceValid) { - ++g_replay_liq_sideband_stats.lret_residency_advance_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeResidencyAdvanceBlockedByAdvanceDisabled) { - ++g_replay_liq_sideband_stats.lret_residency_advance_blocked_by_advance_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW1SlotAccepted) { - ++g_replay_liq_sideband_stats.lret_w1_slot_accepted; - } - if (dut.io_reducedLoadReplayLiqLretPipeW1SlotOccupied) { - ++g_replay_liq_sideband_stats.lret_w1_slot_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPipeW1AdvanceCandidateValid) { - ++g_replay_liq_sideband_stats.lret_w1_advance_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW1AdvanceValid) { - ++g_replay_liq_sideband_stats.lret_w1_advance_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW1AdvanceBlockedByAdvanceDisabled) { - ++g_replay_liq_sideband_stats.lret_w1_advance_blocked_by_advance_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotAccepted) { - ++g_replay_liq_sideband_stats.lret_w2_slot_accepted; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotOccupied) { - ++g_replay_liq_sideband_stats.lret_w2_slot_occupied; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotBlockedByNoWrite) { - ++g_replay_liq_sideband_stats.lret_w2_slot_blocked_by_no_write; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotSourceTraceValid) { - ++g_replay_liq_sideband_stats.lret_w2_slot_source_trace_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestActive) { - ++g_replay_liq_sideband_stats.w2_atomic_live_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestRequestActive) { - ++g_replay_liq_sideband_stats.w2_atomic_request_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestEvidenceValid) { - ++g_replay_liq_sideband_stats.w2_atomic_evidence_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestSideEffectLiveRequested) { - ++g_replay_liq_sideband_stats.w2_atomic_side_effect_live_requested; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestPromotionRequested) { - ++g_replay_liq_sideband_stats.w2_atomic_promotion_requested; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlocked) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByRequestDisabled) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_request_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoEvidence) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_evidence; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByModeDisabled) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_mode_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByPolicy) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_policy; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoSideEffectSink) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_side_effect_sink; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoClearCommit) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_clear_commit; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRowFillCandidate) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoLifecycleRow) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_lifecycle_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AtomicLiveRequestBlockedByNoRequiredSideEffect) { - ++g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_required_side_effect; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SideEffectCandidateValid) { - ++g_replay_liq_sideband_stats.w2_side_effect_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SideEffectReady) { - ++g_replay_liq_sideband_stats.w2_side_effect_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SideEffectLiveControlAllRequiredLiveEnabled) { - ++g_replay_liq_sideband_stats.w2_side_effect_live_all_required_enabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SideEffectFireVectorFireValid) { - ++g_replay_liq_sideband_stats.w2_side_effect_fire_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SideEffectFireCompleteFireComplete) { - ++g_replay_liq_sideband_stats.w2_side_effect_fire_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ClearIntentClearIntent) { - ++g_replay_liq_sideband_stats.w2_clear_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ClearCommitGuardCommitClearReady) { - ++g_replay_liq_sideband_stats.w2_clear_commit_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlLivePromotion) { - ++g_replay_liq_sideband_stats.w2_promotion_live; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlLiveClearEnable) { - ++g_replay_liq_sideband_stats.w2_promotion_live_clear; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlAdvanceLivePromotion) { - ++g_replay_liq_sideband_stats.w2_promotion_advance_live; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlBlocked) { - ++g_replay_liq_sideband_stats.w2_promotion_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByPromotionDisabled) { - ++g_replay_liq_sideband_stats.w2_promotion_blocked_by_promotion_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlBlockedByClearIntent) { - ++g_replay_liq_sideband_stats.w2_promotion_blocked_by_clear_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2PromotionControlInvalidClearIntentWithoutSlot) { - ++g_replay_liq_sideband_stats.w2_promotion_invalid_clear_without_slot; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadyEmpty) { - ++g_replay_liq_sideband_stats.w2_refill_ready_empty; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadySameCycleEligible) { - ++g_replay_liq_sideband_stats.w2_refill_ready_same_cycle_eligible; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadySameCycleReady) { - ++g_replay_liq_sideband_stats.w2_refill_ready_same_cycle_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadyFutureAdvance) { - ++g_replay_liq_sideband_stats.w2_refill_ready_future_advance; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadyMatchesCurrent) { - ++g_replay_liq_sideband_stats.w2_refill_ready_matches_current; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadyBlocked) { - ++g_replay_liq_sideband_stats.w2_refill_ready_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RefillReadyInvalidLiveClearWithoutIntent) { - ++g_replay_liq_sideband_stats.w2_refill_ready_invalid_live_clear_without_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanEmptyWriteEligible) { - ++g_replay_liq_sideband_stats.w2_slot_replace_empty_write_eligible; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleEligible) { - ++g_replay_liq_sideband_stats.w2_slot_replace_same_cycle_eligible; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanSameCycleReady) { - ++g_replay_liq_sideband_stats.w2_slot_replace_same_cycle_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanFutureWriteAccept) { - ++g_replay_liq_sideband_stats.w2_slot_replace_future_write_accept; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanMatchesCurrent) { - ++g_replay_liq_sideband_stats.w2_slot_replace_matches_current; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlocked) { - ++g_replay_liq_sideband_stats.w2_slot_replace_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanBlockedByCurrentStorage) { - ++g_replay_liq_sideband_stats.w2_slot_replace_blocked_by_current_storage; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2SlotReplacePlanInvalidFutureReadyWithoutLiveClear) { - ++g_replay_liq_sideband_stats.w2_slot_replace_invalid_future_ready_without_live_clear; - } - const bool w1_advance_candidate = - dut.io_reducedLoadReplayLiqLretPipeW1AdvanceCandidateValid; - const bool w1_advance_valid = dut.io_reducedLoadReplayLiqLretPipeW1AdvanceValid; - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretIexPipeInsertCandidateValid) { - ++g_replay_liq_sideband_stats.lret_iex_insert_candidate_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretIexPipeInsertValid) { - ++g_replay_liq_sideband_stats.lret_iex_insert_valid_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeResidencyCandidateValid) { - ++g_replay_liq_sideband_stats.lret_residency_candidate_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeResidencyWriteValid) { - ++g_replay_liq_sideband_stats.lret_residency_write_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeResidencySlotOccupied) { - ++g_replay_liq_sideband_stats.lret_residency_slot_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeResidencyAdvanceCandidateValid) { - ++g_replay_liq_sideband_stats.lret_residency_advance_candidate_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeResidencyAdvanceValid) { - ++g_replay_liq_sideband_stats.lret_residency_advance_valid_w2_occupied; - } - if (w2_slot_occupied && dut.io_reducedLoadReplayLiqLretPipeW1SlotOccupied) { - ++g_replay_liq_sideband_stats.lret_w1_slot_w2_occupied; - } - if (w2_slot_occupied && w1_advance_candidate) { - ++g_replay_liq_sideband_stats.lret_w1_advance_candidate_w2_occupied; - } - if (w2_slot_occupied && w1_advance_valid) { - ++g_replay_liq_sideband_stats.lret_w1_advance_valid_w2_occupied; - } - static bool prev_w1_advance_candidate = false; - static bool prev_w2_clear_intent = false; - static bool prev_w2_live_clear = false; - static int cycles_since_w1_advance_candidate = -1; - static int cycles_since_w2_live_clear = -1; - static bool recent_w1_advance_lsid_valid = false; - static std::uint64_t recent_w1_advance_lsid_value = 0; - static bool recent_w2_live_clear_lsid_valid = false; - static std::uint64_t recent_w2_live_clear_lsid_value = 0; - if (cycles_since_w1_advance_candidate >= 0) { - ++cycles_since_w1_advance_candidate; - } - if (cycles_since_w2_live_clear >= 0) { - ++cycles_since_w2_live_clear; - } - if (w2_slot_occupied && w1_advance_candidate) { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_occupied; - } - if (w2_slot_occupied && w1_advance_candidate && w2_clear_intent) { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_clear_intent; - } - if (w2_slot_occupied && w1_advance_candidate && w2_live_clear) { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_live_clear; - const bool w1_lsid_valid = dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValid; - const std::uint64_t w1_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValue); - const bool w2_lsid_valid = dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValid; - const std::uint64_t w2_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValue); - if (w1_lsid_valid && w2_lsid_valid) { - if (w1_lsid_value == w2_lsid_value) { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_same_lsid; - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_different_lsid; - } - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_unknown_lsid; - } - } - if (w2_slot_occupied && w2_live_clear && !w1_advance_candidate) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_without_w1_candidate; - } - if (w2_slot_occupied && w1_advance_candidate && !w2_live_clear) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_without_live_clear; - } - if (w2_slot_occupied && w1_advance_valid && w2_live_clear) { - ++g_replay_liq_sideband_stats.w2_slot_replace_advance_valid_on_live_clear; - } - if (w2_slot_occupied && prev_w1_advance_candidate && w2_clear_intent) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_cycle_before_clear_intent; - } - if (w2_slot_occupied && prev_w1_advance_candidate && w2_live_clear) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_cycle_before_live_clear; - } - if (w2_slot_occupied && prev_w2_clear_intent && w1_advance_candidate) { - ++g_replay_liq_sideband_stats.w2_slot_replace_clear_intent_cycle_before_w1_candidate; - } - if (w2_slot_occupied && prev_w2_live_clear && w1_advance_candidate) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_cycle_before_w1_candidate; - } - if (w2_slot_occupied && w2_live_clear && !w1_advance_candidate && - cycles_since_w1_advance_candidate >= 2) { - const bool w2_lsid_valid = dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValid; - const std::uint64_t w2_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValue); - if (recent_w1_advance_lsid_valid && w2_lsid_valid) { - if (recent_w1_advance_lsid_value == w2_lsid_value) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_same_lsid; - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_different_lsid; - if (cycles_since_w1_advance_candidate == 2) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap2; - } else if (cycles_since_w1_advance_candidate == 3) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap3; - } else if (cycles_since_w1_advance_candidate == 4) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap4; - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap5_plus; - } - } - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_unknown_lsid; - } - if (cycles_since_w1_advance_candidate == 2) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap2; - } else if (cycles_since_w1_advance_candidate == 3) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap3; - } else if (cycles_since_w1_advance_candidate == 4) { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap4; - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap5_plus; - } - } - if (w2_slot_occupied && w1_advance_candidate && !w2_live_clear && - cycles_since_w2_live_clear >= 2) { - const bool w1_lsid_valid = dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValid; - const std::uint64_t w1_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValue); - const bool different_lsid = - recent_w2_live_clear_lsid_valid && w1_lsid_valid && - recent_w2_live_clear_lsid_value != w1_lsid_value; - if (cycles_since_w2_live_clear == 2) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap2; - if (different_lsid) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap2; - } - } else if (cycles_since_w2_live_clear == 3) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap3; - if (different_lsid) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap3; - } - } else if (cycles_since_w2_live_clear == 4) { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap4; - if (different_lsid) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap4; - } - } else { - ++g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap5_plus; - if (different_lsid) { - ++g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap5_plus; - } - } - } - prev_w1_advance_candidate = w1_advance_candidate; - prev_w2_clear_intent = w2_clear_intent; - prev_w2_live_clear = w2_live_clear; - if (w1_advance_candidate) { - cycles_since_w1_advance_candidate = 0; - recent_w1_advance_lsid_valid = - dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValid; - recent_w1_advance_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW1SlotLoadLsIdValue); - } - if (w2_live_clear) { - cycles_since_w2_live_clear = 0; - recent_w2_live_clear_lsid_valid = - dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValid; - recent_w2_live_clear_lsid_value = - static_cast(dut.io_reducedLoadReplayLiqLretPipeW2SlotLoadLsIdValue); - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlAdvanceEnable) { - ++g_replay_liq_sideband_stats.w2_advance_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlReplaceOnClear) { - ++g_replay_liq_sideband_stats.w2_advance_replace_on_clear; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlUsesFutureAdvance) { - ++g_replay_liq_sideband_stats.w2_advance_uses_future_advance; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlBlocked) { - ++g_replay_liq_sideband_stats.w2_advance_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlBlockedByLivePromotionDisabled) { - ++g_replay_liq_sideband_stats.w2_advance_blocked_by_live_promotion_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2AdvanceControlInvalidFutureWriteWithoutAdvance) { - ++g_replay_liq_sideband_stats.w2_advance_invalid_future_write_without_advance; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceReady) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceInstructionReady) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_instruction_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceSourceReady) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_source_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlocked) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoMetadata) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked_by_no_metadata; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceBlockedByNoSourceTrace) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked_by_no_source_trace; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupRowValid) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_row_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupInstructionValid) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_instruction_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByNeedFlush) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_need_flush; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedByMissingInstruction) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_missing_instruction; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceDisabled) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowTraceSourceRobLookupBlockedBySourceTraceBeforeCompletion) { - ++g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_before_completion; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateValid) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateRowFillValid) { - ++g_replay_liq_sideband_stats.w2_commit_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateCompleteRowValid) { - ++g_replay_liq_sideband_stats.w2_commit_row_complete_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlocked) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoMetadata) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_no_metadata; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNoSourceTrace) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_no_source_trace; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByInvalidSize) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_invalid_size; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByNonGprDestination) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_non_gpr_destination; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2CommitRowCandidateBlockedByRowFillDisabled) { - ++g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_row_fill_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateRowFillValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateCompleteRowValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_complete_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlocked) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoRecord) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoMetadata) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_metadata; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNoSourceTrace) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_source_trace; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByInvalidSize) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_invalid_size; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByNonGprDestination) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_non_gpr_destination; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordCommitRowCandidateBlockedByRowFillDisabled) { - ++g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_row_fill_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureIntent) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCapturePayloadRidValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_payload_rid_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_rid_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2RidMatchesCapture) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_rid_matches_capture; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataW2MetadataReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_metadata_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromW2) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_from_w2; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureFromDrain) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_from_drain; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoPayloadRid) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_payload_rid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Rid) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_rid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByRidMismatch) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_rid_mismatch; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataCaptureBlockedByNoW2Metadata) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_metadata; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataClearAccepted) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_clear_accepted; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordInstructionMetadataProviderValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_provider_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlCandidateValid) { - ++g_replay_liq_sideband_stats.w2_row_fill_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlPrerequisitesReady) { - ++g_replay_liq_sideband_stats.w2_row_fill_prerequisites_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlRowFillEnable) { - ++g_replay_liq_sideband_stats.w2_row_fill_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByRequestDisabled) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_request_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoCandidate) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoSideEffectCommit) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_side_effect_commit; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoClearCommit) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_clear_commit; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByLiveClearDisabled) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_live_clear_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RowFillEnableControlBlockedByNoReplayRowLifecycle) { - ++g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_replay_row_lifecycle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCandidateValid) { - ++g_replay_liq_sideband_stats.w2_lifecycle_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleSlotIdentityValid) { - ++g_replay_liq_sideband_stats.w2_lifecycle_slot_identity_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleResolvedRowMatch) { - ++g_replay_liq_sideband_stats.w2_lifecycle_resolved_row_match; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRowClearReady) { - ++g_replay_liq_sideband_stats.w2_lifecycle_row_clear_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleReady) { - ++g_replay_liq_sideband_stats.w2_lifecycle_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByNoResolvedRow) { - ++g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_no_resolved_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByMultipleResolvedRows) { - ++g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_multiple_resolved_rows; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleBlockedByLifecycleClearDisabled) { - ++g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_clear_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleRequestControlLifecycleClearRequestEnable) { - ++g_replay_liq_sideband_stats.w2_lifecycle_clear_request_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2ReplayRowLifecycleCommitPermitLifecycleClearCommitEnable) { - ++g_replay_liq_sideband_stats.w2_lifecycle_clear_commit_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleCandidateValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_candidate_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleSlotIdentityValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_slot_identity_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleResolvedRowMatch) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_resolved_row_match; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRowClearReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_row_clear_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByNoResolvedRow) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_no_resolved_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByMultipleResolvedRows) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_multiple_resolved_rows; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleBlockedByLifecycleClearDisabled) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_clear_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeLivePromotionCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_live_promotion_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoLifecycleRow) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_lifecycle_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoAtomicRequest) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_atomic_request; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleRequestProbeBlockedByNoRowFillEnable) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_row_fill_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeEvidenceValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_evidence_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillCandidateAligned) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_row_fill_candidate_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeRowFillEnableAligned) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_row_fill_enable_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoLifecycleRow) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_lifecycle_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordAtomicRequestProbeBlockedByNoRowFillEnable) { - ++g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_row_fill_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableRequestEvidenceValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_request_evidence_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableCandidateAligned) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_candidate_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnable) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByRequestDisabled) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_request_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoLifecycleRow) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_no_lifecycle_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRowFillEnableBlockedByNoRowFillCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureIntent) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureFromLifecycle) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_from_lifecycle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceCaptureBlockedByNoLifecycle) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceClearAccepted) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_clear_accepted; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_provider_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceProviderValidWithoutRecord) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_provider_valid_without_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleEvidenceRecordValidWithoutProvider) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_record_valid_without_provider; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCapturePhysicalClear) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_capture_physical_clear; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackDuplicatePhysicalClear) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_duplicate_physical_clear; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackClearValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_clear_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCapturePhysicalComplete) { - ++g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_capture_physical_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackDuplicatePhysicalComplete) { - ++g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_duplicate_physical_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackCompleteValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_complete_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCapturePhysicalWriteback) { - ++g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_capture_physical_writeback; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackDuplicatePhysicalWriteback) { - ++g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_duplicate_physical_writeback; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackWritebackValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_writeback_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCapturePhysicalWakeup) { - ++g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_capture_physical_wakeup; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackDuplicatePhysicalWakeup) { - ++g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_duplicate_physical_wakeup; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackWakeupValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_wakeup_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyAllCandidatesReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_all_candidates_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByPhysicalDuplicate) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_blocked_by_physical_duplicate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyNoPhysicalProbeActive) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_no_physical_probe_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackEmitProbeActive) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_fallback_emit_probe_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyFallbackLiveProbeActive) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_fallback_live_probe_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyRetainedSoleOwnerEligible) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_retained_sole_owner_eligible; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicyBlockedByGlobalFallbackDisabled) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_blocked_by_global_fallback_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordFallbackOwnerPolicySideEffectEnable) { - ++g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_side_effect_enable; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRobFallbackLiveCompleteSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_live_complete_selected; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordRfFallbackLiveWritebackSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_live_writeback_selected; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordWakeupFallbackLiveWakeupSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_live_wakeup_selected; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordLifecycleClearFallbackLiveClearSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_live_clear_selected; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRecordCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_record_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnSideEffectsReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_return_side_effects_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderRetireClearEvidenceReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_retire_clear_evidence_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderReturnThenRetireReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_return_then_retire_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderFallbackOwnerEligible) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_fallback_owner_eligible; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingReturnSideEffect) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_missing_return_side_effect; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByMissingRetireClearEvidence) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_missing_retire_clear_evidence; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordModelOrderBlockedByOwnerDisabled) { - ++g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_owner_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionRecordCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_record_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionPreArmModelOrderReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_pre_arm_model_order_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionAnyPhysicalDuplicate) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_any_physical_duplicate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByNoRecord) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_no_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingFallbackCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_missing_fallback_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByMissingLifecycleEvidence) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_missing_lifecycle_evidence; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByPhysicalDuplicate) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_physical_duplicate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDefaultPromotionBlockedByProbeActive) { - ++g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_probe_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorReturnSideEffectBundle) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_return_side_effect_bundle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorModelOrderBundle) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_model_order_bundle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorPartial) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_partial; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorSingle) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_single; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorMulti) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_multi; - } - g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_count_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorCount; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorNextRequiresBundleTransfer) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_next_requires_bundle_transfer; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoRecord) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_no_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByPreArmNotReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_pre_arm_not_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordDuplicateVectorBlockedByNoDuplicate) { - ++g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_no_duplicate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanPreArmReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_pre_arm_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanModelOrderBundle) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_model_order_bundle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultTransferCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_default_transfer_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanRequiresPhysicalBundleSuppression) { - ++g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_requires_physical_bundle_suppression; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanDefaultPromotionAlreadyReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_default_promotion_already_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoRecord) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_no_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPreArmNotReady) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_pre_arm_not_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByNoDuplicateVector) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_no_duplicate_vector; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByPartialDuplicate) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_partial_duplicate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordBundleTransferPlanBlockedByProbeActive) { - ++g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_probe_active; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanTransferCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_transfer_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressionRequired) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppression_required; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanPhysicalBundleComplete) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_physical_bundle_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAtomicSuppressCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRobComplete) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppress_rob_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressRfWriteback) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppress_rf_writeback; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressWakeup) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppress_wakeup; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressLifecycleClear) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppress_lifecycle_clear; - } - g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_suppress_mask_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanSuppressMask; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanAllOrNoneSuppress) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_plan_all_or_none_suppress; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoTransferCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_transfer_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByNoSuppressionRequirement) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_suppression_requirement; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressPlanBlockedByIncompletePhysicalBundle) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_incomplete_physical_bundle; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeEnabledCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_enabled_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_selected; - } - g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_selected_mask_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeSelectedMask; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeAllOrNoneInputMask) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_all_or_none_input_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByProbeDisabled) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_probe_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByNoAtomicCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_no_atomic_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressProbeBlockedByPartialMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectPlanPromotedCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_plan_promoted_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelected) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_select_selected; - } - g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_select_selected_mask_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedMask; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectAllOrNoneInputMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_all_or_none_input_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromProbe) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_selected_from_probe; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectSelectedFromPromotion) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_selected_from_promotion; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPromoteDisabled) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByNoPlanCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_no_plan_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectBlockedByPartialPlanMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressSelectInvalidProbePromotionMaskMismatch) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryCapture) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_boundary_capture; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredValid) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_boundary_registered_valid; - } - g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_boundary_registered_mask_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredMask; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryRegisteredFullMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_registered_full_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByNoSelection) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_blocked_by_no_selection; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryBlockedByPartialMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_blocked_by_partial_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressBoundaryClearedByFlush) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_cleared_by_flush; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCaptureIdentity) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_identity_capture_identity; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityCapturedIdentityValid) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_captured_identity_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRegisteredCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_registered_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityRetainedRecordAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_retained_record_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifecycleRowAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_lifecycle_row_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityLifetimeAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_lifetime_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityEligibleRegisteredMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_eligible_registered_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNoCapturedIdentity) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_no_captured_identity; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingRecord) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_record; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByRidMismatch) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_rid_mismatch; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLoadLsIdMismatch) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_load_lsid_mismatch; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByMissingLifecycleEvidence) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_lifecycle_evidence; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByLifecycleRowMismatch) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_lifecycle_row_mismatch; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressIdentityBlockedByNotFullMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_not_full_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCaptureOwnership) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_ownership_capture_ownership; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipCapturedOwnershipValid) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_captured_ownership_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredRidValid) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_rid_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLoadLsIdValid) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_load_lsid_valid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredLifecycleRowReady) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_lifecycle_row_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipRegisteredBundleReady) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_bundle_ready; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipEligibleRegisteredMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNoCapturedOwnership) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_no_captured_ownership; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingRid) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_rid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLoadLsId) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_load_lsid; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByMissingLifecycleRow) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_lifecycle_row; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressOwnershipBlockedByNotFullMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_not_full_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskEnabledCandidate) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRobComplete) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_rob_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressRfWriteback) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_rf_writeback; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressWakeup) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_suppress_wakeup; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressLifecycleClear) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_lifecycle_clear; - } - g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_suppress_mask_sum += - dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskSuppressMask; - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskAllOrNone) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_all_or_none; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByLiveMaskDisabled) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_live_mask_disabled; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressLiveMaskBlockedByNoEligibleOwnership) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_no_eligible_ownership; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofCandidate) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_clear_proof_candidate; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFullMask) { - ++g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_clear_proof_full_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofFireCompleteAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_fire_complete_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofClearIntentAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_clear_intent_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLiveClearAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_live_clear_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofRowFillAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_row_fill_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofLifecycleClearSuppressed) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_lifecycle_clear_suppressed; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofAllClearAligned) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByPartialMask) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_partial_mask; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoFireComplete) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_fire_complete; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoClearIntent) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_clear_intent; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoLiveClear) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_live_clear; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByNoRowFill) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_row_fill; - } - if (dut.io_reducedLoadReplayLiqLretPipeW2RetireRecordPhysicalBundleSuppressClearProofBlockedByLifecycleClearStillEnabled) { - ++g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_lifecycle_clear_still_enabled; - } - if (resolve_queue_push_accepted) { - ++g_replay_liq_sideband_stats.resolve_queue_push_accepted; - } - if (resolve_queue_valid) { - ++g_replay_liq_sideband_stats.resolve_queue_valid; - } - if (mdb_conflict_store_valid) { - ++g_replay_liq_sideband_stats.mdb_conflict_store_valid; - } - if (mdb_conflict_store_with_resolve_queue_valid) { - ++g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid; - } - if (mdb_conflict_store_valid && !resolve_queue_valid) { - ++g_replay_liq_sideband_stats.mdb_conflict_store_without_resolve_queue_valid; - } - if (dut.io_reducedMdbConflictActiveCandidateMask != 0) { - ++g_replay_liq_sideband_stats.mdb_conflict_active_candidate; - } - if (mdb_conflict_resolve_candidate) { - ++g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate; - } - if (dut.io_reducedMdbConflictValid) { - ++g_replay_liq_sideband_stats.mdb_conflict_valid; - } - if (dut.io_reducedMdbFanoutRecordValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_record_valid; - } - if (dut.io_reducedMdbFanoutRecordAccepted) { - ++g_replay_liq_sideband_stats.mdb_fanout_record_accepted; - } - if (dut.io_reducedMdbFanoutRecordProcessed) { - ++g_replay_liq_sideband_stats.mdb_fanout_record_processed; - } - if (dut.io_reducedMdbFanoutBmdbReportValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_bmdb_report; - } - if (dut.io_reducedMdbFanoutSsitValidMask != 0) { - ++g_replay_liq_sideband_stats.mdb_fanout_ssit_nonempty; - } - if (dut.io_reducedMdbFanoutLookupValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_valid; - } - if (dut.io_reducedMdbFanoutLookupAccepted) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_accepted; - } - if (dut.io_reducedMdbFanoutLookupProcessed) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_processed; - } - if (dut.io_reducedMdbFanoutLookupTableHit) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_table_hit; - } - if (dut.io_reducedMdbFanoutLookupFirstAfterNuke) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_first_after_nuke; - } - if (dut.io_reducedMdbFanoutLookupConfBlocked) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_conf_blocked; - } - if (dut.io_reducedMdbFanoutLookupWeightBlocked) { - ++g_replay_liq_sideband_stats.mdb_fanout_lookup_weight_blocked; - } - if (dut.io_reducedMdbFanoutLuOutValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_lu_out_valid; - } - if (dut.io_reducedMdbFanoutLuOutHit) { - ++g_replay_liq_sideband_stats.mdb_fanout_lu_out_hit; - } - if (dut.io_reducedMdbFanoutSuOutValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_su_out_valid; - } - if (dut.io_reducedMdbFanoutSuOutHit) { - ++g_replay_liq_sideband_stats.mdb_fanout_su_out_hit; - } - if (dut.io_reducedMdbFanoutSuWakeupValid) { - ++g_replay_liq_sideband_stats.mdb_fanout_su_wakeup_valid; - } - if (dut.io_reducedMdbLookupWaitPlanLookupHit) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_lookup_hit; - } - if (dut.io_reducedMdbLookupWaitPlanWaitIntentValid) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_wait_intent_valid; - } - if (dut.io_reducedMdbLookupWaitPlanRequestValid) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_request_valid; - } - if (dut.io_reducedMdbLookupWaitPlanBlockedByNoTarget) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_no_target; - } - if (dut.io_reducedMdbLookupWaitPlanBlockedByMissingStoreIndex) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_missing_store_index; - } - if (dut.io_reducedMdbLookupWaitPlanBlockedByMissingStoreLsId) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_missing_store_lsid; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_active) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_active; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_valid) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_valid; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_sourceStoreIndexFits) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_source_store_index_fits; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_blockedByDisabled) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_disabled; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_blockedByFlush) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_flush; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_blockedByNoRequest) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_no_request; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_invalidStoreIndexOutOfRange) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_store_index_out_of_range; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_invalidConflictingStatusWrite) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_conflicting_status_write; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_invalidWaitStoreWithoutWaitStatus) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_wait_store_without_wait_status; - } - if (dut.io_reducedMdbLookupWaitPlanBridge_invalidReturnWithoutSplitSources) { - ++g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_return_without_split_sources; - } - if (dut.io_reducedLoadReplayLiqRowMutationBridgeValid) { - ++g_replay_liq_sideband_stats.liq_row_mutation_bridge_valid; - } - if (dut.io_reducedLoadReplayLiqRowMutationSelectedSourceReturn) { - ++g_replay_liq_sideband_stats.liq_row_mutation_selected_source_return; - } - if (dut.io_reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan) { - ++g_replay_liq_sideband_stats.liq_row_mutation_selected_mdb_wait_plan; - } - if (dut.io_reducedLoadReplayLiqRowMutationSourceConflict) { - ++g_replay_liq_sideband_stats.liq_row_mutation_source_conflict; - } - if (dut.io_reducedLoadReplayLiqRowMutationSelectedMdbWaitPlan && - dut.io_reducedLoadReplayLiqRowMutationWriteEnable) { - ++g_replay_liq_sideband_stats.mdb_wait_plan_row_mutation_write_enable; - } - if (dut.io_reducedLoadReplayLiqRowMutationWriteEnable) { - ++g_replay_liq_sideband_stats.liq_row_mutation_write_enable; - } - if (dut.io_reducedLoadReplayLiqRowMutationApplyValid) { - ++g_replay_liq_sideband_stats.liq_row_mutation_apply_valid; - } - if (dut.io_reducedLoadReplayLiqRowMutationBlockedByBridge) { - ++g_replay_liq_sideband_stats.liq_row_mutation_blocked_by_bridge; - } - if (dut.io_reducedLoadReplayLiqRowMutationBlockedByControl) { - ++g_replay_liq_sideband_stats.liq_row_mutation_blocked_by_control; - } -#else - (void)dut; -#endif -} - -bool write_replay_liq_sideband_stats(const std::string &path) { - if (path.empty()) { - return true; - } - std::ofstream out(path); - if (!out) { - std::cerr << "failed to open sideband stats path: " << path << "\n"; - return false; - } - out << "{\n" - << " \"schema\": \"linxcore.frontend_fetch_rf_alu.sideband_stats.v58\",\n" -#if defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) || \ - defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) - << " \"reduced_store_replay_liq_top\": true,\n" -#else - << " \"reduced_store_replay_liq_top\": false,\n" -#endif - << " \"issue_fabric\": {\n" - << " \"simultaneous_pick\": " - << g_replay_liq_sideband_stats.issue_simultaneous_pick << ",\n" - << " \"read_contention\": " - << g_replay_liq_sideband_stats.issue_read_contention << ",\n" - << " \"read_arbitration_loss\": " - << g_replay_liq_sideband_stats.issue_read_arbitration_loss << ",\n" - << " \"cancel\": " - << g_replay_liq_sideband_stats.issue_cancel << ",\n" - << " \"i2_contention\": " - << g_replay_liq_sideband_stats.issue_i2_contention << ",\n" - << " \"control_fence_active\": " - << g_replay_liq_sideband_stats.issue_control_fence_active << ",\n" - << " \"control_fence_blocked\": " - << g_replay_liq_sideband_stats.issue_control_fence_blocked << ",\n" - << " \"store_order_blocked\": " - << g_replay_liq_sideband_stats.issue_store_order_blocked << "\n" - << " },\n" - << " \"replay_liq\": {\n" - << " \"cycles_sampled\": " << g_replay_liq_sideband_stats.cycles_sampled << ",\n" - << " \"load_lookup_valid\": " - << g_replay_liq_sideband_stats.load_lookup_valid << ",\n" - << " \"load_lookup_execute_granted\": " - << g_replay_liq_sideband_stats.load_lookup_execute_granted << ",\n" - << " \"load_lookup_execute_with_eligible_store\": " - << g_replay_liq_sideband_stats.load_lookup_execute_with_eligible_store << ",\n" - << " \"load_lookup_execute_with_wait_store\": " - << g_replay_liq_sideband_stats.load_lookup_execute_with_wait_store << ",\n" - << " \"execute_load_wait_hold\": " - << g_replay_liq_sideband_stats.execute_load_wait_hold << ",\n" - << " \"resident_store_eligible\": " - << g_replay_liq_sideband_stats.resident_store_eligible << ",\n" - << " \"resident_store_ready_forward\": " - << g_replay_liq_sideband_stats.resident_store_ready_forward << ",\n" - << " \"resident_store_wait_blocked\": " - << g_replay_liq_sideband_stats.resident_store_wait_blocked << ",\n" - << " \"resident_store_wait_store_valid\": " - << g_replay_liq_sideband_stats.resident_store_wait_store_valid << ",\n" - << " \"store_stq_resident\": " - << g_replay_liq_sideband_stats.store_stq_resident << ",\n" - << " \"store_stq_addr_ready\": " - << g_replay_liq_sideband_stats.store_stq_addr_ready << ",\n" - << " \"store_stq_data_ready\": " - << g_replay_liq_sideband_stats.store_stq_data_ready << ",\n" - << " \"store_stq_addr_ready_not_data_ready\": " - << g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready << ",\n" - << " \"store_stq_addr_and_data_ready\": " - << g_replay_liq_sideband_stats.store_stq_addr_and_data_ready << ",\n" - << " \"load_lookup_execute_with_addr_ready_not_data_ready\": " - << g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready << ",\n" - << " \"load_lookup_execute_granted_first_cycle\": " - << g_replay_liq_sideband_stats.load_lookup_execute_granted_first_cycle << ",\n" - << " \"load_lookup_execute_granted_last_cycle\": " - << g_replay_liq_sideband_stats.load_lookup_execute_granted_last_cycle << ",\n" - << " \"store_stq_addr_ready_not_data_ready_first_cycle\": " - << g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready_first_cycle << ",\n" - << " \"store_stq_addr_ready_not_data_ready_last_cycle\": " - << g_replay_liq_sideband_stats.store_stq_addr_ready_not_data_ready_last_cycle << ",\n" - << " \"store_stq_addr_and_data_ready_first_cycle\": " - << g_replay_liq_sideband_stats.store_stq_addr_and_data_ready_first_cycle << ",\n" - << " \"store_stq_addr_and_data_ready_last_cycle\": " - << g_replay_liq_sideband_stats.store_stq_addr_and_data_ready_last_cycle << ",\n" - << " \"load_lookup_execute_with_addr_ready_not_data_ready_first_cycle\": " - << g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready_first_cycle << ",\n" - << " \"load_lookup_execute_with_addr_ready_not_data_ready_last_cycle\": " - << g_replay_liq_sideband_stats.load_lookup_execute_with_addr_ready_not_data_ready_last_cycle << ",\n" - << " \"store_sta_dequeue_fire_first_cycle\": " - << g_replay_liq_sideband_stats.store_sta_dequeue_fire_first_cycle << ",\n" - << " \"store_sta_dequeue_fire_last_cycle\": " - << g_replay_liq_sideband_stats.store_sta_dequeue_fire_last_cycle << ",\n" - << " \"store_std_dequeue_fire_first_cycle\": " - << g_replay_liq_sideband_stats.store_std_dequeue_fire_first_cycle << ",\n" - << " \"store_std_dequeue_fire_last_cycle\": " - << g_replay_liq_sideband_stats.store_std_dequeue_fire_last_cycle << ",\n" - << " \"store_sta_exec_valid_first_cycle\": " - << g_replay_liq_sideband_stats.store_sta_exec_valid_first_cycle << ",\n" - << " \"store_sta_exec_valid_last_cycle\": " - << g_replay_liq_sideband_stats.store_sta_exec_valid_last_cycle << ",\n" - << " \"store_std_exec_valid_first_cycle\": " - << g_replay_liq_sideband_stats.store_std_exec_valid_first_cycle << ",\n" - << " \"store_std_exec_valid_last_cycle\": " - << g_replay_liq_sideband_stats.store_std_exec_valid_last_cycle << ",\n" - << " \"store_sta_queue_valid\": " - << g_replay_liq_sideband_stats.store_sta_queue_valid << ",\n" - << " \"store_std_queue_valid\": " - << g_replay_liq_sideband_stats.store_std_queue_valid << ",\n" - << " \"store_sta_queue_only_valid\": " - << g_replay_liq_sideband_stats.store_sta_queue_only_valid << ",\n" - << " \"store_sta_dequeue_fire\": " - << g_replay_liq_sideband_stats.store_sta_dequeue_fire << ",\n" - << " \"store_std_dequeue_fire\": " - << g_replay_liq_sideband_stats.store_std_dequeue_fire << ",\n" - << " \"store_sta_exec_valid\": " - << g_replay_liq_sideband_stats.store_sta_exec_valid << ",\n" - << " \"store_std_exec_valid\": " - << g_replay_liq_sideband_stats.store_std_exec_valid << ",\n" - << " \"store_sta_exec_only_valid\": " - << g_replay_liq_sideband_stats.store_sta_exec_only_valid << ",\n" - << " \"resident_store_wake_valid\": " - << g_replay_liq_sideband_stats.resident_store_wake_valid << ",\n" - << " \"resident_store_wake_ready\": " - << g_replay_liq_sideband_stats.resident_store_wake_ready << ",\n" - << " \"wait_replay_capture_accepted\": " - << g_replay_liq_sideband_stats.wait_replay_capture_accepted << ",\n" - << " \"wait_replay_clear_valid\": " - << g_replay_liq_sideband_stats.wait_replay_clear_valid << ",\n" - << " \"wait_replay_relaunch_valid\": " - << g_replay_liq_sideband_stats.wait_replay_relaunch_valid << ",\n" - << " \"replay_queue_enqueue_accepted\": " - << g_replay_liq_sideband_stats.replay_queue_enqueue_accepted << ",\n" - << " \"replay_queue_out_valid\": " - << g_replay_liq_sideband_stats.replay_queue_out_valid << ",\n" - << " \"replay_queue_out_fire\": " - << g_replay_liq_sideband_stats.replay_queue_out_fire << ",\n" - << " \"liq_alloc_valid\": " - << g_replay_liq_sideband_stats.liq_alloc_valid << ",\n" - << " \"liq_alloc_accepted\": " - << g_replay_liq_sideband_stats.liq_alloc_accepted << ",\n" - << " \"liq_launch_valid\": " - << g_replay_liq_sideband_stats.liq_launch_valid << ",\n" - << " \"liq_launch_accepted\": " - << g_replay_liq_sideband_stats.liq_launch_accepted << ",\n" - << " \"liq_return_complete_repick_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_repick_mask_nonzero << ",\n" - << " \"liq_return_complete_source_returned_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_source_returned_mask_nonzero << ",\n" - << " \"liq_return_complete_data_complete_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_data_complete_mask_nonzero << ",\n" - << " \"liq_return_complete_request_complete_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_request_complete_mask_nonzero << ",\n" - << " \"liq_return_complete_candidate_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_candidate_mask_nonzero << ",\n" - << " \"liq_return_complete_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_mask_nonzero << ",\n" - << " \"liq_return_complete_valid\": " - << g_replay_liq_sideband_stats.liq_return_complete_valid << ",\n" - << " \"liq_return_complete_candidate_count_nonzero\": " - << g_replay_liq_sideband_stats.liq_return_complete_candidate_count_nonzero << ",\n" - << " \"liq_return_complete_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.liq_return_complete_valid_w2_occupied << ",\n" - << " \"liq_base_lookup_valid\": " - << g_replay_liq_sideband_stats.liq_base_lookup_valid << ",\n" - << " \"liq_base_lookup_granted\": " - << g_replay_liq_sideband_stats.liq_base_lookup_granted << ",\n" - << " \"liq_base_data_returned\": " - << g_replay_liq_sideband_stats.liq_base_data_returned << ",\n" - << " \"liq_base_line_valid_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_base_line_valid_mask_nonzero << ",\n" - << " \"launch_readiness_candidate_valid\": " - << g_replay_liq_sideband_stats.launch_readiness_candidate_valid << ",\n" - << " \"launch_readiness_base_data_ready\": " - << g_replay_liq_sideband_stats.launch_readiness_base_data_ready << ",\n" - << " \"launch_readiness_sources_returned\": " - << g_replay_liq_sideband_stats.launch_readiness_sources_returned << ",\n" - << " \"launch_readiness_ready\": " - << g_replay_liq_sideband_stats.launch_readiness_ready << ",\n" - << " \"launch_readiness_enable\": " - << g_replay_liq_sideband_stats.launch_readiness_enable << ",\n" - << " \"launch_readiness_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_disabled << ",\n" - << " \"launch_readiness_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_no_candidate << ",\n" - << " \"launch_readiness_blocked_by_base_lookup\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_base_lookup << ",\n" - << " \"launch_readiness_blocked_by_base_data\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_base_data << ",\n" - << " \"launch_readiness_blocked_by_scb\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_scb << ",\n" - << " \"launch_readiness_blocked_by_return\": " - << g_replay_liq_sideband_stats.launch_readiness_blocked_by_return << ",\n" - << " \"liq_wait_store_mask_nonzero\": " - << g_replay_liq_sideband_stats.liq_wait_store_mask_nonzero << ",\n" - << " \"liq_replay_wake_valid\": " - << g_replay_liq_sideband_stats.liq_replay_wake_valid << ",\n" - << " \"liq_replay_wake_active\": " - << g_replay_liq_sideband_stats.liq_replay_wake_active << ",\n" - << " \"liq_replay_wake_wait_store_candidate\": " - << g_replay_liq_sideband_stats.liq_replay_wake_wait_store_candidate << ",\n" - << " \"liq_replay_wake_bid_match\": " - << g_replay_liq_sideband_stats.liq_replay_wake_bid_match << ",\n" - << " \"liq_replay_wake_lsid_match\": " - << g_replay_liq_sideband_stats.liq_replay_wake_lsid_match << ",\n" - << " \"liq_replay_wake_pc_match\": " - << g_replay_liq_sideband_stats.liq_replay_wake_pc_match << ",\n" - << " \"liq_replay_wake_full_match\": " - << g_replay_liq_sideband_stats.liq_replay_wake_full_match << ",\n" - << " \"liq_replay_wake_store_unit\": " - << g_replay_liq_sideband_stats.liq_replay_wake_store_unit << ",\n" - << " \"liq_replay_wake_store_unit_full_match\": " - << g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match << ",\n" - << " \"liq_replay_wake_store_unit_full_match_active\": " - << g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match_active << ",\n" - << " \"liq_replay_wake_store_unit_full_match_flush_blocked\": " - << g_replay_liq_sideband_stats.liq_replay_wake_store_unit_full_match_flush_blocked << ",\n" - << " \"liq_replay_wake_wait_store_clear\": " - << g_replay_liq_sideband_stats.liq_replay_wake_wait_store_clear << ",\n" - << " \"source_return_candidate_valid\": " - << g_replay_liq_sideband_stats.source_return_candidate_valid << ",\n" - << " \"source_return_store_snapshot_ready\": " - << g_replay_liq_sideband_stats.source_return_store_snapshot_ready << ",\n" - << " \"source_return_store_source_returned\": " - << g_replay_liq_sideband_stats.source_return_store_source_returned << ",\n" - << " \"source_return_scb_source_returned\": " - << g_replay_liq_sideband_stats.source_return_scb_source_returned << ",\n" - << " \"source_return_source_returned\": " - << g_replay_liq_sideband_stats.source_return_source_returned << ",\n" - << " \"source_return_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.source_return_blocked_by_disabled << ",\n" - << " \"source_return_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.source_return_blocked_by_no_candidate << ",\n" - << " \"source_return_blocked_by_base_data\": " - << g_replay_liq_sideband_stats.source_return_blocked_by_base_data << ",\n" - << " \"source_return_blocked_by_store_snapshot\": " - << g_replay_liq_sideband_stats.source_return_blocked_by_store_snapshot << ",\n" - << " \"source_return_blocked_by_scb\": " - << g_replay_liq_sideband_stats.source_return_blocked_by_scb << ",\n" - << " \"source_return_store_snapshot_live_request_active\": " - << g_replay_liq_sideband_stats.source_return_store_snapshot_live_request_active << ",\n" - << " \"source_return_store_snapshot_live_evidence_valid\": " - << g_replay_liq_sideband_stats.source_return_store_snapshot_live_evidence_valid << ",\n" - << " \"source_return_scb_live_active\": " - << g_replay_liq_sideband_stats.source_return_scb_live_active << ",\n" - << " \"source_return_scb_live_request_active\": " - << g_replay_liq_sideband_stats.source_return_scb_live_request_active << ",\n" - << " \"source_return_scb_live_evidence_valid\": " - << g_replay_liq_sideband_stats.source_return_scb_live_evidence_valid << ",\n" - << " \"source_return_scb_live_pending\": " - << g_replay_liq_sideband_stats.source_return_scb_live_pending << ",\n" - << " \"source_return_scb_live_returned\": " - << g_replay_liq_sideband_stats.source_return_scb_live_returned << ",\n" - << " \"source_return_scb_live_blocked_by_request_disabled\": " - << g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_request_disabled << ",\n" - << " \"source_return_scb_live_blocked_by_no_pending\": " - << g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_no_pending << ",\n" - << " \"source_return_scb_live_blocked_by_scb_return\": " - << g_replay_liq_sideband_stats.source_return_scb_live_blocked_by_scb_return << ",\n" - << " \"source_return_query_issued\": " - << g_replay_liq_sideband_stats.source_return_query_issued << ",\n" - << " \"source_return_response_apply_valid\": " - << g_replay_liq_sideband_stats.source_return_response_apply_valid << ",\n" - << " \"source_return_row_state_plan_valid\": " - << g_replay_liq_sideband_stats.source_return_row_state_plan_valid << ",\n" - << " \"source_return_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.source_return_candidate_w2_occupied << ",\n" - << " \"source_return_store_snapshot_ready_w2_occupied\": " - << g_replay_liq_sideband_stats.source_return_store_snapshot_ready_w2_occupied << ",\n" - << " \"source_return_query_issued_w2_occupied\": " - << g_replay_liq_sideband_stats.source_return_query_issued_w2_occupied << ",\n" - << " \"source_return_response_apply_w2_occupied\": " - << g_replay_liq_sideband_stats.source_return_response_apply_w2_occupied << ",\n" - << " \"source_row_mutation_candidate_valid\": " - << g_replay_liq_sideband_stats.source_row_mutation_candidate_valid << ",\n" - << " \"source_row_mutation_live_permit\": " - << g_replay_liq_sideband_stats.source_row_mutation_live_permit << ",\n" - << " \"source_row_mutation_request_valid\": " - << g_replay_liq_sideband_stats.source_row_mutation_request_valid << ",\n" - << " \"source_row_mutation_blocked_by_head_proof\": " - << g_replay_liq_sideband_stats.source_row_mutation_blocked_by_head_proof << ",\n" - << " \"source_row_mutation_blocked_by_live_disabled\": " - << g_replay_liq_sideband_stats.source_row_mutation_blocked_by_live_disabled << ",\n" - << " \"source_row_mutation_request_w2_occupied\": " - << g_replay_liq_sideband_stats.source_row_mutation_request_w2_occupied << ",\n" - << " \"return_data_candidate_valid\": " - << g_replay_liq_sideband_stats.return_data_candidate_valid << ",\n" - << " \"return_data_request_mask_nonzero\": " - << g_replay_liq_sideband_stats.return_data_request_mask_nonzero << ",\n" - << " \"return_data_bytes_complete\": " - << g_replay_liq_sideband_stats.return_data_bytes_complete << ",\n" - << " \"return_data_cross_line\": " - << g_replay_liq_sideband_stats.return_data_cross_line << ",\n" - << " \"return_data_size_supported\": " - << g_replay_liq_sideband_stats.return_data_size_supported << ",\n" - << " \"return_data_valid\": " - << g_replay_liq_sideband_stats.return_data_valid << ",\n" - << " \"return_data_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_disabled << ",\n" - << " \"return_data_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_no_candidate << ",\n" - << " \"return_data_blocked_by_zero_size\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_zero_size << ",\n" - << " \"return_data_blocked_by_unsupported_size\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_unsupported_size << ",\n" - << " \"return_data_blocked_by_cross_line\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_cross_line << ",\n" - << " \"return_data_blocked_by_incomplete_bytes\": " - << g_replay_liq_sideband_stats.return_data_blocked_by_incomplete_bytes << ",\n" - << " \"return_publish_candidate_valid\": " - << g_replay_liq_sideband_stats.return_publish_candidate_valid << ",\n" - << " \"return_publish_data_ready\": " - << g_replay_liq_sideband_stats.return_publish_data_ready << ",\n" - << " \"return_publish_ready\": " - << g_replay_liq_sideband_stats.return_publish_ready << ",\n" - << " \"return_publish_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.return_publish_blocked_by_no_candidate << ",\n" - << " \"return_publish_blocked_by_data\": " - << g_replay_liq_sideband_stats.return_publish_blocked_by_data << ",\n" - << " \"return_publish_blocked_by_consumer\": " - << g_replay_liq_sideband_stats.return_publish_blocked_by_consumer << ",\n" - << " \"return_publish_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.return_publish_candidate_w2_occupied << ",\n" - << " \"return_publish_ready_w2_occupied\": " - << g_replay_liq_sideband_stats.return_publish_ready_w2_occupied << ",\n" - << " \"lret_payload_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_payload_candidate_valid << ",\n" - << " \"lret_payload_valid\": " - << g_replay_liq_sideband_stats.lret_payload_valid << ",\n" - << " \"lret_payload_wakeup_required\": " - << g_replay_liq_sideband_stats.lret_payload_wakeup_required << ",\n" - << " \"lret_payload_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.lret_payload_blocked_by_no_candidate << ",\n" - << " \"lret_payload_blocked_by_data\": " - << g_replay_liq_sideband_stats.lret_payload_blocked_by_data << ",\n" - << " \"lret_payload_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_payload_candidate_w2_occupied << ",\n" - << " \"lret_payload_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_payload_valid_w2_occupied << ",\n" - << " \"publish_control_candidate_valid\": " - << g_replay_liq_sideband_stats.publish_control_candidate_valid << ",\n" - << " \"publish_control_live_enable\": " - << g_replay_liq_sideband_stats.publish_control_live_enable << ",\n" - << " \"publish_control_armed\": " - << g_replay_liq_sideband_stats.publish_control_armed << ",\n" - << " \"publish_control_fire\": " - << g_replay_liq_sideband_stats.publish_control_fire << ",\n" - << " \"publish_control_blocked_by_no_payload\": " - << g_replay_liq_sideband_stats.publish_control_blocked_by_no_payload << ",\n" - << " \"publish_control_blocked_by_publish\": " - << g_replay_liq_sideband_stats.publish_control_blocked_by_publish << ",\n" - << " \"publish_control_blocked_by_side_effects\": " - << g_replay_liq_sideband_stats.publish_control_blocked_by_side_effects << ",\n" - << " \"publish_control_blocked_by_live_disabled\": " - << g_replay_liq_sideband_stats.publish_control_blocked_by_live_disabled << ",\n" - << " \"publish_control_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.publish_control_candidate_w2_occupied << ",\n" - << " \"publish_control_live_enable_w2_occupied\": " - << g_replay_liq_sideband_stats.publish_control_live_enable_w2_occupied << ",\n" - << " \"publish_control_armed_w2_occupied\": " - << g_replay_liq_sideband_stats.publish_control_armed_w2_occupied << ",\n" - << " \"publish_control_fire_w2_occupied\": " - << g_replay_liq_sideband_stats.publish_control_fire_w2_occupied << ",\n" - << " \"publish_request_valid\": " - << g_replay_liq_sideband_stats.publish_request_valid << ",\n" - << " \"publish_request_lret\": " - << g_replay_liq_sideband_stats.publish_request_lret << ",\n" - << " \"publish_request_writeback\": " - << g_replay_liq_sideband_stats.publish_request_writeback << ",\n" - << " \"publish_request_wakeup\": " - << g_replay_liq_sideband_stats.publish_request_wakeup << ",\n" - << " \"publish_request_mask_nonzero\": " - << g_replay_liq_sideband_stats.publish_request_mask_nonzero << ",\n" - << " \"publish_request_blocked_by_no_fire\": " - << g_replay_liq_sideband_stats.publish_request_blocked_by_no_fire << ",\n" - << " \"publish_request_invalid_fire_without_payload\": " - << g_replay_liq_sideband_stats.publish_request_invalid_fire_without_payload << ",\n" - << " \"lret_sink_enqueue_ready\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_ready << ",\n" - << " \"lret_sink_enqueue_accepted\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted << ",\n" - << " \"lret_sink_enqueue_dropped\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_dropped << ",\n" - << " \"lret_sink_drain_valid\": " - << g_replay_liq_sideband_stats.lret_sink_drain_valid << ",\n" - << " \"lret_sink_drain_fire\": " - << g_replay_liq_sideband_stats.lret_sink_drain_fire << ",\n" - << " \"lret_sink_pending\": " - << g_replay_liq_sideband_stats.lret_sink_pending << ",\n" - << " \"lret_sink_full\": " - << g_replay_liq_sideband_stats.lret_sink_full << ",\n" - << " \"lret_sink_blocked_by_no_payload\": " - << g_replay_liq_sideband_stats.lret_sink_blocked_by_no_payload << ",\n" - << " \"lret_sink_blocked_by_full\": " - << g_replay_liq_sideband_stats.lret_sink_blocked_by_full << ",\n" - << " \"lret_sink_blocked_by_drain\": " - << g_replay_liq_sideband_stats.lret_sink_blocked_by_drain << ",\n" - << " \"lret_sink_enqueue_ready_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_ready_w2_occupied << ",\n" - << " \"lret_sink_enqueue_accepted_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_occupied << ",\n" - << " \"lret_sink_enqueue_dropped_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_dropped_w2_occupied << ",\n" - << " \"lret_sink_enqueue_accepted_same_cycle_drain_fire\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_same_cycle_drain_fire << ",\n" - << " \"lret_sink_enqueue_accepted_same_cycle_drain_fire_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_same_cycle_drain_fire_w2_occupied << ",\n" - << " \"lret_sink_enqueue_accepted_w2_without_drain_fire\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_without_drain_fire << ",\n" - << " \"lret_sink_enqueue_accepted_w2_completion_clear_slot\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_completion_clear_slot << ",\n" - << " \"lret_sink_enqueue_accepted_w2_clear_intent\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_clear_intent << ",\n" - << " \"lret_sink_enqueue_accepted_w2_side_effect_fire_complete\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_side_effect_fire_complete << ",\n" - << " \"lret_sink_enqueue_accepted_w2_live_clear\": " - << g_replay_liq_sideband_stats.lret_sink_enqueue_accepted_w2_live_clear << ",\n" - << " \"lret_sink_followup_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_accepted_w2 << ",\n" - << " \"lret_sink_followup_w2_still_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_followup_w2_still_occupied << ",\n" - << " \"lret_sink_followup_w2_cleared\": " - << g_replay_liq_sideband_stats.lret_sink_followup_w2_cleared << ",\n" - << " \"lret_sink_followup_after_enqueue_completion_clear_slot\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_completion_clear_slot << ",\n" - << " \"lret_sink_followup_after_enqueue_completion_clear_slot_w2_cleared\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_completion_clear_slot_w2_cleared << ",\n" - << " \"lret_sink_followup_after_enqueue_clear_intent\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_clear_intent << ",\n" - << " \"lret_sink_followup_after_enqueue_clear_intent_w2_cleared\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_clear_intent_w2_cleared << ",\n" - << " \"lret_sink_followup_after_enqueue_side_effect_fire_complete\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_side_effect_fire_complete << ",\n" - << " \"lret_sink_followup_after_enqueue_side_effect_fire_complete_w2_cleared\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_side_effect_fire_complete_w2_cleared << ",\n" - << " \"lret_sink_followup_after_enqueue_live_clear\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_live_clear << ",\n" - << " \"lret_sink_followup_after_enqueue_live_clear_w2_cleared\": " - << g_replay_liq_sideband_stats.lret_sink_followup_after_enqueue_live_clear_w2_cleared << ",\n" - << " \"lret_sink_pending_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_sink_pending_after_enqueue_accepted_w2 << ",\n" - << " \"lret_sink_drain_valid_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_sink_drain_valid_after_enqueue_accepted_w2 << ",\n" - << " \"lret_sink_drain_fire_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_sink_drain_fire_after_enqueue_accepted_w2 << ",\n" - << " \"lret_drain_permit_ready_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_drain_permit_ready_after_enqueue_accepted_w2 << ",\n" - << " \"lret_drain_permit_pipe_free_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_drain_permit_pipe_free_after_enqueue_accepted_w2 << ",\n" - << " \"lret_drain_permit_pipe_full_after_enqueue_accepted_w2\": " - << g_replay_liq_sideband_stats.lret_drain_permit_pipe_full_after_enqueue_accepted_w2 << ",\n" - << " \"lret_sink_pending_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_pending_w2_occupied << ",\n" - << " \"lret_sink_drain_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_drain_valid_w2_occupied << ",\n" - << " \"lret_sink_drain_fire_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_sink_drain_fire_w2_occupied << ",\n" - << " \"w2_retire_record_capture_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_candidate << ",\n" - << " \"w2_retire_record_payload_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_payload_valid << ",\n" - << " \"w2_retire_record_capture_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_valid << ",\n" - << " \"w2_retire_record_capture_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_ready << ",\n" - << " \"w2_retire_record_capture_accepted\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_accepted << ",\n" - << " \"w2_retire_record_capture_accepted_w2_occupied\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_accepted_w2_occupied << ",\n" - << " \"w2_retire_record_capture_dropped\": " - << g_replay_liq_sideband_stats.w2_retire_record_capture_dropped << ",\n" - << " \"w2_retire_record_record_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_record_valid << ",\n" - << " \"w2_retire_record_record_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_record_ready << ",\n" - << " \"w2_retire_record_record_fire\": " - << g_replay_liq_sideband_stats.w2_retire_record_record_fire << ",\n" - << " \"w2_retire_record_pending\": " - << g_replay_liq_sideband_stats.w2_retire_record_pending << ",\n" - << " \"w2_retire_record_captured_with_lret_enqueue\": " - << g_replay_liq_sideband_stats.w2_retire_record_captured_with_lret_enqueue << ",\n" - << " \"w2_retire_record_record_from_lret_enqueue\": " - << g_replay_liq_sideband_stats.w2_retire_record_record_from_lret_enqueue << ",\n" - << " \"w2_retire_record_blocked_by_invalid_payload\": " - << g_replay_liq_sideband_stats.w2_retire_record_blocked_by_invalid_payload << ",\n" - << " \"w2_retire_record_blocked_by_full\": " - << g_replay_liq_sideband_stats.w2_retire_record_blocked_by_full << ",\n" - << " \"lret_commit_history_load_rows\": " - << g_replay_liq_sideband_stats.lret_commit_history_load_rows << ",\n" - << " \"lret_shadow_enqueue\": " - << g_replay_liq_sideband_stats.lret_shadow_enqueue << ",\n" - << " \"lret_shadow_enqueue_after_prior_commit\": " - << g_replay_liq_sideband_stats.lret_shadow_enqueue_after_prior_commit << ",\n" - << " \"lret_shadow_drain\": " - << g_replay_liq_sideband_stats.lret_shadow_drain << ",\n" - << " \"lret_shadow_drain_missing\": " - << g_replay_liq_sideband_stats.lret_shadow_drain_missing << ",\n" - << " \"lret_shadow_drain_after_prior_commit\": " - << g_replay_liq_sideband_stats.lret_shadow_drain_after_prior_commit << ",\n" - << " \"lret_shadow_free_after_prior_commit\": " - << g_replay_liq_sideband_stats.lret_shadow_free_after_prior_commit << ",\n" - << " \"lret_drain_permit_any_pipe_free\": " - << g_replay_liq_sideband_stats.lret_drain_permit_any_pipe_free << ",\n" - << " \"lret_drain_permit_ready\": " - << g_replay_liq_sideband_stats.lret_drain_permit_ready << ",\n" - << " \"lret_drain_permit_blocked_by_no_entry\": " - << g_replay_liq_sideband_stats.lret_drain_permit_blocked_by_no_entry << ",\n" - << " \"lret_drain_permit_blocked_by_pipe_full\": " - << g_replay_liq_sideband_stats.lret_drain_permit_blocked_by_pipe_full << ",\n" - << " \"lret_drain_permit_pipe_occupied\": " - << g_replay_liq_sideband_stats.lret_drain_permit_pipe_occupied << ",\n" - << " \"lret_iex_data_rob_row_valid\": " - << g_replay_liq_sideband_stats.lret_iex_data_rob_row_valid << ",\n" - << " \"lret_iex_data_rob_row_need_flush\": " - << g_replay_liq_sideband_stats.lret_iex_data_rob_row_need_flush << ",\n" - << " \"lret_iex_data_rob_row_blocked_by_invalid_rid\": " - << g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_invalid_rid << ",\n" - << " \"lret_iex_data_rob_row_blocked_by_free\": " - << g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_free << ",\n" - << " \"lret_iex_data_rob_row_blocked_by_stale_rid\": " - << g_replay_liq_sideband_stats.lret_iex_data_rob_row_blocked_by_stale_rid << ",\n" - << " \"lret_iex_data_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_iex_data_candidate_valid << ",\n" - << " \"lret_iex_data_would_drain\": " - << g_replay_liq_sideband_stats.lret_iex_data_would_drain << ",\n" - << " \"lret_iex_data_set_mem_data_valid\": " - << g_replay_liq_sideband_stats.lret_iex_data_set_mem_data_valid << ",\n" - << " \"lret_iex_data_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_disabled << ",\n" - << " \"lret_iex_data_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_flush << ",\n" - << " \"lret_iex_data_blocked_by_no_entry\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_no_entry << ",\n" - << " \"lret_iex_data_blocked_by_invalid_entry\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_invalid_entry << ",\n" - << " \"lret_iex_data_blocked_by_drain\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_drain << ",\n" - << " \"lret_iex_data_blocked_by_rob_missing\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_rob_missing << ",\n" - << " \"lret_iex_data_blocked_by_need_flush\": " - << g_replay_liq_sideband_stats.lret_iex_data_blocked_by_need_flush << ",\n" - << " \"lret_rob_resolve_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_candidate_valid << ",\n" - << " \"lret_rob_resolve_valid\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_valid << ",\n" - << " \"lret_rob_resolve_ready_for_pipe_insert\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_ready_for_pipe_insert << ",\n" - << " \"lret_rob_resolve_mark_all_destinations_data_valid\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_mark_all_destinations_data_valid << ",\n" - << " \"lret_rob_resolve_mark_destination_data_valid\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_mark_destination_data_valid << ",\n" - << " \"lret_rob_resolve_ret_lane_increment\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_ret_lane_increment << ",\n" - << " \"lret_rob_resolve_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_disabled << ",\n" - << " \"lret_rob_resolve_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_flush << ",\n" - << " \"lret_rob_resolve_blocked_by_no_set_mem_data\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_no_set_mem_data << ",\n" - << " \"lret_rob_resolve_blocked_by_unsupported_multi_lane\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_unsupported_multi_lane << ",\n" - << " \"lret_rob_resolve_blocked_by_invalid_rid\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_invalid_rid << ",\n" - << " \"lret_rob_resolve_blocked_by_no_destination\": " - << g_replay_liq_sideband_stats.lret_rob_resolve_blocked_by_no_destination << ",\n" - << " \"lret_lane_completion_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_lane_completion_candidate_valid << ",\n" - << " \"lret_lane_completion_complete_valid\": " - << g_replay_liq_sideband_stats.lret_lane_completion_complete_valid << ",\n" - << " \"lret_lane_completion_ready_for_pipe_insert\": " - << g_replay_liq_sideband_stats.lret_lane_completion_ready_for_pipe_insert << ",\n" - << " \"lret_lane_completion_requires_all_lanes\": " - << g_replay_liq_sideband_stats.lret_lane_completion_requires_all_lanes << ",\n" - << " \"lret_lane_completion_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_disabled << ",\n" - << " \"lret_lane_completion_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_flush << ",\n" - << " \"lret_lane_completion_blocked_by_no_resolve\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_no_resolve << ",\n" - << " \"lret_lane_completion_blocked_by_zero_returned_lanes\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_zero_returned_lanes << ",\n" - << " \"lret_lane_completion_blocked_by_invalid_real_req_cnt\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_invalid_real_req_cnt << ",\n" - << " \"lret_lane_completion_blocked_by_scalar_load_pair_incomplete\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_scalar_load_pair_incomplete << ",\n" - << " \"lret_lane_completion_blocked_by_vector_mem_incomplete\": " - << g_replay_liq_sideband_stats.lret_lane_completion_blocked_by_vector_mem_incomplete << ",\n" - << " \"lret_tload_completion_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_tload_completion_candidate_valid << ",\n" - << " \"lret_tload_completion_tload_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_tload_completion_tload_candidate_valid << ",\n" - << " \"lret_tload_completion_tile_scb_send_valid\": " - << g_replay_liq_sideband_stats.lret_tload_completion_tile_scb_send_valid << ",\n" - << " \"lret_tload_completion_tile_scb_is_last\": " - << g_replay_liq_sideband_stats.lret_tload_completion_tile_scb_is_last << ",\n" - << " \"lret_tload_completion_complete_valid\": " - << g_replay_liq_sideband_stats.lret_tload_completion_complete_valid << ",\n" - << " \"lret_tload_completion_ready_for_pipe_insert\": " - << g_replay_liq_sideband_stats.lret_tload_completion_ready_for_pipe_insert << ",\n" - << " \"lret_tload_completion_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_disabled << ",\n" - << " \"lret_tload_completion_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_flush << ",\n" - << " \"lret_tload_completion_blocked_by_no_lane_completion\": " - << g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_no_lane_completion << ",\n" - << " \"lret_tload_completion_blocked_by_invalid_sub_inst_cnt\": " - << g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_invalid_sub_inst_cnt << ",\n" - << " \"lret_tload_completion_blocked_by_tload_pending\": " - << g_replay_liq_sideband_stats.lret_tload_completion_blocked_by_tload_pending << ",\n" - << " \"lret_final_metadata_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_final_metadata_candidate_valid << ",\n" - << " \"lret_final_metadata_is_load_return_marked\": " - << g_replay_liq_sideband_stats.lret_final_metadata_is_load_return_marked << ",\n" - << " \"lret_final_metadata_load_branch_resolve_called\": " - << g_replay_liq_sideband_stats.lret_final_metadata_load_branch_resolve_called << ",\n" - << " \"lret_final_metadata_load_branch_resolve_side_effect_valid\": " - << g_replay_liq_sideband_stats.lret_final_metadata_load_branch_resolve_side_effect_valid << ",\n" - << " \"lret_final_metadata_pipe_cycle_sideband_valid\": " - << g_replay_liq_sideband_stats.lret_final_metadata_pipe_cycle_sideband_valid << ",\n" - << " \"lret_final_metadata_ready_for_pipe_insert\": " - << g_replay_liq_sideband_stats.lret_final_metadata_ready_for_pipe_insert << ",\n" - << " \"lret_final_metadata_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_disabled << ",\n" - << " \"lret_final_metadata_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_flush << ",\n" - << " \"lret_final_metadata_blocked_by_no_tload_completion\": " - << g_replay_liq_sideband_stats.lret_final_metadata_blocked_by_no_tload_completion << ",\n" - << " \"lret_timing_stats_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_timing_stats_candidate_valid << ",\n" - << " \"lret_timing_stats_sideband_valid\": " - << g_replay_liq_sideband_stats.lret_timing_stats_sideband_valid << ",\n" - << " \"lret_timing_stats_iq_name_sideband_valid\": " - << g_replay_liq_sideband_stats.lret_timing_stats_iq_name_sideband_valid << ",\n" - << " \"lret_timing_stats_ld_rnt_cycle_valid\": " - << g_replay_liq_sideband_stats.lret_timing_stats_ld_rnt_cycle_valid << ",\n" - << " \"lret_timing_stats_update_valid\": " - << g_replay_liq_sideband_stats.lret_timing_stats_update_valid << ",\n" - << " \"lret_timing_stats_latency_underflow\": " - << g_replay_liq_sideband_stats.lret_timing_stats_latency_underflow << ",\n" - << " \"lret_timing_stats_ready_for_pipe_insert\": " - << g_replay_liq_sideband_stats.lret_timing_stats_ready_for_pipe_insert << ",\n" - << " \"lret_timing_stats_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_disabled << ",\n" - << " \"lret_timing_stats_blocked_by_flush\": " - << g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_flush << ",\n" - << " \"lret_timing_stats_blocked_by_no_final_metadata\": " - << g_replay_liq_sideband_stats.lret_timing_stats_blocked_by_no_final_metadata << ",\n" - << " \"lret_iex_insert_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_iex_insert_candidate_valid << ",\n" - << " \"lret_iex_insert_valid\": " - << g_replay_liq_sideband_stats.lret_iex_insert_valid << ",\n" - << " \"lret_iex_insert_is_load_return\": " - << g_replay_liq_sideband_stats.lret_iex_insert_is_load_return << ",\n" - << " \"lret_iex_insert_wakeup_required\": " - << g_replay_liq_sideband_stats.lret_iex_insert_wakeup_required << ",\n" - << " \"lret_iex_insert_blocked_by_no_set_mem_data\": " - << g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_no_set_mem_data << ",\n" - << " \"lret_iex_insert_blocked_by_no_pipe\": " - << g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_no_pipe << ",\n" - << " \"lret_iex_insert_blocked_by_invalid_rid\": " - << g_replay_liq_sideband_stats.lret_iex_insert_blocked_by_invalid_rid << ",\n" - << " \"lret_iex_insert_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_iex_insert_candidate_w2_occupied << ",\n" - << " \"lret_iex_insert_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_iex_insert_valid_w2_occupied << ",\n" - << " \"lret_residency_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_residency_candidate_valid << ",\n" - << " \"lret_residency_write_valid\": " - << g_replay_liq_sideband_stats.lret_residency_write_valid << ",\n" - << " \"lret_residency_live_enable\": " - << g_replay_liq_sideband_stats.lret_residency_live_enable << ",\n" - << " \"lret_residency_blocked_by_live_disabled\": " - << g_replay_liq_sideband_stats.lret_residency_blocked_by_live_disabled << ",\n" - << " \"lret_residency_slot_accepted\": " - << g_replay_liq_sideband_stats.lret_residency_slot_accepted << ",\n" - << " \"lret_residency_slot_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_slot_occupied << ",\n" - << " \"lret_residency_advance_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_residency_advance_candidate_valid << ",\n" - << " \"lret_residency_advance_valid\": " - << g_replay_liq_sideband_stats.lret_residency_advance_valid << ",\n" - << " \"lret_residency_advance_blocked_by_advance_disabled\": " - << g_replay_liq_sideband_stats.lret_residency_advance_blocked_by_advance_disabled << ",\n" - << " \"lret_residency_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_candidate_w2_occupied << ",\n" - << " \"lret_residency_write_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_write_w2_occupied << ",\n" - << " \"lret_residency_slot_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_slot_w2_occupied << ",\n" - << " \"lret_residency_advance_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_advance_candidate_w2_occupied << ",\n" - << " \"lret_residency_advance_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_residency_advance_valid_w2_occupied << ",\n" - << " \"lret_w1_slot_accepted\": " - << g_replay_liq_sideband_stats.lret_w1_slot_accepted << ",\n" - << " \"lret_w1_slot_occupied\": " - << g_replay_liq_sideband_stats.lret_w1_slot_occupied << ",\n" - << " \"lret_w1_advance_candidate_valid\": " - << g_replay_liq_sideband_stats.lret_w1_advance_candidate_valid << ",\n" - << " \"lret_w1_advance_valid\": " - << g_replay_liq_sideband_stats.lret_w1_advance_valid << ",\n" - << " \"lret_w1_advance_blocked_by_advance_disabled\": " - << g_replay_liq_sideband_stats.lret_w1_advance_blocked_by_advance_disabled << ",\n" - << " \"lret_w1_slot_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_w1_slot_w2_occupied << ",\n" - << " \"lret_w1_advance_candidate_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_w1_advance_candidate_w2_occupied << ",\n" - << " \"lret_w1_advance_valid_w2_occupied\": " - << g_replay_liq_sideband_stats.lret_w1_advance_valid_w2_occupied << ",\n" - << " \"lret_w2_slot_accepted\": " - << g_replay_liq_sideband_stats.lret_w2_slot_accepted << ",\n" - << " \"lret_w2_slot_occupied\": " - << g_replay_liq_sideband_stats.lret_w2_slot_occupied << ",\n" - << " \"lret_w2_slot_blocked_by_no_write\": " - << g_replay_liq_sideband_stats.lret_w2_slot_blocked_by_no_write << ",\n" - << " \"lret_w2_slot_source_trace_valid\": " - << g_replay_liq_sideband_stats.lret_w2_slot_source_trace_valid << ",\n" - << " \"w2_atomic_live_active\": " - << g_replay_liq_sideband_stats.w2_atomic_live_active << ",\n" - << " \"w2_atomic_request_active\": " - << g_replay_liq_sideband_stats.w2_atomic_request_active << ",\n" - << " \"w2_atomic_evidence_valid\": " - << g_replay_liq_sideband_stats.w2_atomic_evidence_valid << ",\n" - << " \"w2_atomic_side_effect_live_requested\": " - << g_replay_liq_sideband_stats.w2_atomic_side_effect_live_requested << ",\n" - << " \"w2_atomic_promotion_requested\": " - << g_replay_liq_sideband_stats.w2_atomic_promotion_requested << ",\n" - << " \"w2_atomic_blocked\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked << ",\n" - << " \"w2_atomic_blocked_by_request_disabled\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_request_disabled << ",\n" - << " \"w2_atomic_blocked_by_no_evidence\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_evidence << ",\n" - << " \"w2_atomic_blocked_by_mode_disabled\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_mode_disabled << ",\n" - << " \"w2_atomic_blocked_by_policy\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_policy << ",\n" - << " \"w2_atomic_blocked_by_no_side_effect_sink\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_side_effect_sink << ",\n" - << " \"w2_atomic_blocked_by_no_clear_commit\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_clear_commit << ",\n" - << " \"w2_atomic_blocked_by_no_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_row_fill_candidate << ",\n" - << " \"w2_atomic_blocked_by_no_lifecycle_row\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_lifecycle_row << ",\n" - << " \"w2_atomic_blocked_by_no_required_side_effect\": " - << g_replay_liq_sideband_stats.w2_atomic_blocked_by_no_required_side_effect << ",\n" - << " \"w2_side_effect_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_side_effect_candidate_valid << ",\n" - << " \"w2_side_effect_ready\": " - << g_replay_liq_sideband_stats.w2_side_effect_ready << ",\n" - << " \"w2_side_effect_live_all_required_enabled\": " - << g_replay_liq_sideband_stats.w2_side_effect_live_all_required_enabled << ",\n" - << " \"w2_side_effect_fire_valid\": " - << g_replay_liq_sideband_stats.w2_side_effect_fire_valid << ",\n" - << " \"w2_side_effect_fire_complete\": " - << g_replay_liq_sideband_stats.w2_side_effect_fire_complete << ",\n" - << " \"w2_clear_intent\": " - << g_replay_liq_sideband_stats.w2_clear_intent << ",\n" - << " \"w2_clear_commit_ready\": " - << g_replay_liq_sideband_stats.w2_clear_commit_ready << ",\n" - << " \"w2_promotion_live\": " - << g_replay_liq_sideband_stats.w2_promotion_live << ",\n" - << " \"w2_promotion_live_clear\": " - << g_replay_liq_sideband_stats.w2_promotion_live_clear << ",\n" - << " \"w2_promotion_advance_live\": " - << g_replay_liq_sideband_stats.w2_promotion_advance_live << ",\n" - << " \"w2_promotion_blocked\": " - << g_replay_liq_sideband_stats.w2_promotion_blocked << ",\n" - << " \"w2_promotion_blocked_by_promotion_disabled\": " - << g_replay_liq_sideband_stats.w2_promotion_blocked_by_promotion_disabled << ",\n" - << " \"w2_promotion_blocked_by_clear_intent\": " - << g_replay_liq_sideband_stats.w2_promotion_blocked_by_clear_intent << ",\n" - << " \"w2_promotion_invalid_clear_without_slot\": " - << g_replay_liq_sideband_stats.w2_promotion_invalid_clear_without_slot << ",\n" - << " \"w2_refill_ready_empty\": " - << g_replay_liq_sideband_stats.w2_refill_ready_empty << ",\n" - << " \"w2_refill_ready_same_cycle_eligible\": " - << g_replay_liq_sideband_stats.w2_refill_ready_same_cycle_eligible << ",\n" - << " \"w2_refill_ready_same_cycle_ready\": " - << g_replay_liq_sideband_stats.w2_refill_ready_same_cycle_ready << ",\n" - << " \"w2_refill_ready_future_advance\": " - << g_replay_liq_sideband_stats.w2_refill_ready_future_advance << ",\n" - << " \"w2_refill_ready_matches_current\": " - << g_replay_liq_sideband_stats.w2_refill_ready_matches_current << ",\n" - << " \"w2_refill_ready_blocked\": " - << g_replay_liq_sideband_stats.w2_refill_ready_blocked << ",\n" - << " \"w2_refill_ready_invalid_live_clear_without_intent\": " - << g_replay_liq_sideband_stats.w2_refill_ready_invalid_live_clear_without_intent << ",\n" - << " \"w2_slot_replace_empty_write_eligible\": " - << g_replay_liq_sideband_stats.w2_slot_replace_empty_write_eligible << ",\n" - << " \"w2_slot_replace_same_cycle_eligible\": " - << g_replay_liq_sideband_stats.w2_slot_replace_same_cycle_eligible << ",\n" - << " \"w2_slot_replace_same_cycle_ready\": " - << g_replay_liq_sideband_stats.w2_slot_replace_same_cycle_ready << ",\n" - << " \"w2_slot_replace_future_write_accept\": " - << g_replay_liq_sideband_stats.w2_slot_replace_future_write_accept << ",\n" - << " \"w2_slot_replace_matches_current\": " - << g_replay_liq_sideband_stats.w2_slot_replace_matches_current << ",\n" - << " \"w2_slot_replace_blocked\": " - << g_replay_liq_sideband_stats.w2_slot_replace_blocked << ",\n" - << " \"w2_slot_replace_blocked_by_current_storage\": " - << g_replay_liq_sideband_stats.w2_slot_replace_blocked_by_current_storage << ",\n" - << " \"w2_slot_replace_invalid_future_ready_without_live_clear\": " - << g_replay_liq_sideband_stats.w2_slot_replace_invalid_future_ready_without_live_clear << ",\n" - << " \"w2_slot_replace_overlap_candidate_occupied\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_occupied << ",\n" - << " \"w2_slot_replace_overlap_candidate_clear_intent\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_clear_intent << ",\n" - << " \"w2_slot_replace_overlap_candidate_live_clear\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_candidate_live_clear << ",\n" - << " \"w2_slot_replace_overlap_live_clear_same_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_same_lsid << ",\n" - << " \"w2_slot_replace_overlap_live_clear_different_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_different_lsid << ",\n" - << " \"w2_slot_replace_overlap_live_clear_unknown_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_overlap_live_clear_unknown_lsid << ",\n" - << " \"w2_slot_replace_live_clear_without_w1_candidate\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_without_w1_candidate << ",\n" - << " \"w2_slot_replace_w1_candidate_without_live_clear\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_without_live_clear << ",\n" - << " \"w2_slot_replace_advance_valid_on_live_clear\": " - << g_replay_liq_sideband_stats.w2_slot_replace_advance_valid_on_live_clear << ",\n" - << " \"w2_slot_replace_w1_candidate_cycle_before_clear_intent\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_cycle_before_clear_intent << ",\n" - << " \"w2_slot_replace_w1_candidate_cycle_before_live_clear\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_cycle_before_live_clear << ",\n" - << " \"w2_slot_replace_clear_intent_cycle_before_w1_candidate\": " - << g_replay_liq_sideband_stats.w2_slot_replace_clear_intent_cycle_before_w1_candidate << ",\n" - << " \"w2_slot_replace_live_clear_cycle_before_w1_candidate\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_cycle_before_w1_candidate << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_gap2\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap2 << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_gap3\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap3 << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_gap4\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap4 << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_gap5_plus\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_gap5_plus << ",\n" - << " \"w2_slot_replace_w1_candidate_after_live_clear_gap2\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap2 << ",\n" - << " \"w2_slot_replace_w1_candidate_after_live_clear_gap3\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap3 << ",\n" - << " \"w2_slot_replace_w1_candidate_after_live_clear_gap4\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap4 << ",\n" - << " \"w2_slot_replace_w1_candidate_after_live_clear_gap5_plus\": " - << g_replay_liq_sideband_stats.w2_slot_replace_w1_candidate_after_live_clear_gap5_plus << ",\n" - << " \"w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap2\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap2 << ",\n" - << " \"w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap3\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap3 << ",\n" - << " \"w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap4\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap4 << ",\n" - << " \"w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap5_plus\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap5_plus << ",\n" - << " \"w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap2\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap2 << ",\n" - << " \"w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap3\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap3 << ",\n" - << " \"w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap4\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap4 << ",\n" - << " \"w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap5_plus\": " - << g_replay_liq_sideband_stats.w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap5_plus << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_same_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_same_lsid << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_different_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_different_lsid << ",\n" - << " \"w2_slot_replace_live_clear_after_w1_candidate_unknown_lsid\": " - << g_replay_liq_sideband_stats.w2_slot_replace_live_clear_after_w1_candidate_unknown_lsid << ",\n" - << " \"w2_advance_enable\": " - << g_replay_liq_sideband_stats.w2_advance_enable << ",\n" - << " \"w2_advance_replace_on_clear\": " - << g_replay_liq_sideband_stats.w2_advance_replace_on_clear << ",\n" - << " \"w2_advance_uses_future_advance\": " - << g_replay_liq_sideband_stats.w2_advance_uses_future_advance << ",\n" - << " \"w2_advance_blocked\": " - << g_replay_liq_sideband_stats.w2_advance_blocked << ",\n" - << " \"w2_advance_blocked_by_live_promotion_disabled\": " - << g_replay_liq_sideband_stats.w2_advance_blocked_by_live_promotion_disabled << ",\n" - << " \"w2_advance_invalid_future_write_without_advance\": " - << g_replay_liq_sideband_stats.w2_advance_invalid_future_write_without_advance << ",\n" - << " \"w2_commit_row_trace_source_ready\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_ready << ",\n" - << " \"w2_commit_row_trace_source_instruction_ready\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_instruction_ready << ",\n" - << " \"w2_commit_row_trace_source_source_ready\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_source_ready << ",\n" - << " \"w2_commit_row_trace_source_blocked\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked << ",\n" - << " \"w2_commit_row_trace_source_blocked_by_no_metadata\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked_by_no_metadata << ",\n" - << " \"w2_commit_row_trace_source_blocked_by_no_source_trace\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_blocked_by_no_source_trace << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_row_valid\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_row_valid << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_instruction_valid\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_instruction_valid << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_blocked_by_need_flush\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_need_flush << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_blocked_by_missing_instruction\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_missing_instruction << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_disabled\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_disabled << ",\n" - << " \"w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_before_completion\": " - << g_replay_liq_sideband_stats.w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_before_completion << ",\n" - << " \"w2_commit_row_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_valid << ",\n" - << " \"w2_commit_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_commit_row_fill_candidate << ",\n" - << " \"w2_commit_row_complete_candidate\": " - << g_replay_liq_sideband_stats.w2_commit_row_complete_candidate << ",\n" - << " \"w2_commit_row_candidate_blocked\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked << ",\n" - << " \"w2_commit_row_candidate_blocked_by_no_metadata\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_no_metadata << ",\n" - << " \"w2_commit_row_candidate_blocked_by_no_source_trace\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_no_source_trace << ",\n" - << " \"w2_commit_row_candidate_blocked_by_invalid_size\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_invalid_size << ",\n" - << " \"w2_commit_row_candidate_blocked_by_non_gpr_destination\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_non_gpr_destination << ",\n" - << " \"w2_commit_row_candidate_blocked_by_row_fill_disabled\": " - << g_replay_liq_sideband_stats.w2_commit_row_candidate_blocked_by_row_fill_disabled << ",\n" - << " \"w2_retire_record_commit_row_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_valid << ",\n" - << " \"w2_retire_record_commit_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_fill_candidate << ",\n" - << " \"w2_retire_record_commit_row_complete_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_complete_candidate << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_no_record\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_record << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_no_metadata\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_metadata << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_no_source_trace\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_no_source_trace << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_invalid_size\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_invalid_size << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_non_gpr_destination\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_non_gpr_destination << ",\n" - << " \"w2_retire_record_commit_row_candidate_blocked_by_row_fill_disabled\": " - << g_replay_liq_sideband_stats.w2_retire_record_commit_row_candidate_blocked_by_row_fill_disabled << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_intent\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_intent << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_payload_rid_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_payload_rid_valid << ",\n" - << " \"w2_retire_record_instruction_metadata_w2_rid_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_rid_valid << ",\n" - << " \"w2_retire_record_instruction_metadata_w2_rid_matches_capture\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_rid_matches_capture << ",\n" - << " \"w2_retire_record_instruction_metadata_w2_metadata_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_w2_metadata_ready << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_from_w2\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_from_w2 << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_from_drain\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_from_drain << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_blocked_by_no_payload_rid\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_payload_rid << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_rid\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_rid << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_blocked_by_rid_mismatch\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_rid_mismatch << ",\n" - << " \"w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_metadata\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_metadata << ",\n" - << " \"w2_retire_record_instruction_metadata_clear_accepted\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_clear_accepted << ",\n" - << " \"w2_retire_record_instruction_metadata_provider_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_instruction_metadata_provider_valid << ",\n" - << " \"w2_row_fill_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_row_fill_candidate_valid << ",\n" - << " \"w2_row_fill_prerequisites_ready\": " - << g_replay_liq_sideband_stats.w2_row_fill_prerequisites_ready << ",\n" - << " \"w2_row_fill_enable\": " - << g_replay_liq_sideband_stats.w2_row_fill_enable << ",\n" - << " \"w2_row_fill_blocked_by_request_disabled\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_request_disabled << ",\n" - << " \"w2_row_fill_blocked_by_no_candidate\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_candidate << ",\n" - << " \"w2_row_fill_blocked_by_no_side_effect_commit\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_side_effect_commit << ",\n" - << " \"w2_row_fill_blocked_by_no_clear_commit\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_clear_commit << ",\n" - << " \"w2_row_fill_blocked_by_live_clear_disabled\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_live_clear_disabled << ",\n" - << " \"w2_row_fill_blocked_by_no_replay_row_lifecycle\": " - << g_replay_liq_sideband_stats.w2_row_fill_blocked_by_no_replay_row_lifecycle << ",\n" - << " \"w2_lifecycle_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_lifecycle_candidate_valid << ",\n" - << " \"w2_lifecycle_slot_identity_valid\": " - << g_replay_liq_sideband_stats.w2_lifecycle_slot_identity_valid << ",\n" - << " \"w2_lifecycle_resolved_row_match\": " - << g_replay_liq_sideband_stats.w2_lifecycle_resolved_row_match << ",\n" - << " \"w2_lifecycle_row_clear_ready\": " - << g_replay_liq_sideband_stats.w2_lifecycle_row_clear_ready << ",\n" - << " \"w2_lifecycle_ready\": " - << g_replay_liq_sideband_stats.w2_lifecycle_ready << ",\n" - << " \"w2_lifecycle_blocked_by_no_resolved_row\": " - << g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_no_resolved_row << ",\n" - << " \"w2_lifecycle_blocked_by_multiple_resolved_rows\": " - << g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_multiple_resolved_rows << ",\n" - << " \"w2_lifecycle_blocked_by_clear_disabled\": " - << g_replay_liq_sideband_stats.w2_lifecycle_blocked_by_clear_disabled << ",\n" - << " \"w2_lifecycle_clear_request_enable\": " - << g_replay_liq_sideband_stats.w2_lifecycle_clear_request_enable << ",\n" - << " \"w2_lifecycle_clear_commit_enable\": " - << g_replay_liq_sideband_stats.w2_lifecycle_clear_commit_enable << ",\n" - << " \"w2_retire_record_lifecycle_candidate_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_candidate_valid << ",\n" - << " \"w2_retire_record_lifecycle_slot_identity_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_slot_identity_valid << ",\n" - << " \"w2_retire_record_lifecycle_resolved_row_match\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_resolved_row_match << ",\n" - << " \"w2_retire_record_lifecycle_row_clear_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_row_clear_ready << ",\n" - << " \"w2_retire_record_lifecycle_blocked_by_no_resolved_row\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_no_resolved_row << ",\n" - << " \"w2_retire_record_lifecycle_blocked_by_multiple_resolved_rows\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_multiple_resolved_rows << ",\n" - << " \"w2_retire_record_lifecycle_blocked_by_clear_disabled\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_blocked_by_clear_disabled << ",\n" - << " \"w2_retire_record_lifecycle_request_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_candidate << ",\n" - << " \"w2_retire_record_lifecycle_live_promotion_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_live_promotion_candidate << ",\n" - << " \"w2_retire_record_lifecycle_request_blocked_by_no_lifecycle_row\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_lifecycle_row << ",\n" - << " \"w2_retire_record_lifecycle_request_blocked_by_no_atomic_request\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_atomic_request << ",\n" - << " \"w2_retire_record_lifecycle_request_blocked_by_no_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_row_fill_candidate << ",\n" - << " \"w2_retire_record_lifecycle_request_blocked_by_no_row_fill_enable\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_request_blocked_by_no_row_fill_enable << ",\n" - << " \"w2_retire_record_atomic_request_evidence_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_evidence_valid << ",\n" - << " \"w2_retire_record_atomic_request_row_fill_candidate_aligned\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_row_fill_candidate_aligned << ",\n" - << " \"w2_retire_record_atomic_request_row_fill_enable_aligned\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_row_fill_enable_aligned << ",\n" - << " \"w2_retire_record_atomic_request_blocked_by_no_lifecycle_row\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_lifecycle_row << ",\n" - << " \"w2_retire_record_atomic_request_blocked_by_no_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_row_fill_candidate << ",\n" - << " \"w2_retire_record_atomic_request_blocked_by_no_row_fill_enable\": " - << g_replay_liq_sideband_stats.w2_retire_record_atomic_request_blocked_by_no_row_fill_enable << ",\n" - << " \"w2_retire_record_row_fill_enable_request_evidence_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_request_evidence_valid << ",\n" - << " \"w2_retire_record_row_fill_enable_candidate_aligned\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_candidate_aligned << ",\n" - << " \"w2_retire_record_row_fill_enable\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable << ",\n" - << " \"w2_retire_record_row_fill_enable_blocked_by_request_disabled\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_request_disabled << ",\n" - << " \"w2_retire_record_row_fill_enable_blocked_by_no_lifecycle_row\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_no_lifecycle_row << ",\n" - << " \"w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate << ",\n" - << " \"w2_retire_record_lifecycle_evidence_capture_intent\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_intent << ",\n" - << " \"w2_retire_record_lifecycle_evidence_capture_from_lifecycle\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_from_lifecycle << ",\n" - << " \"w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle << ",\n" - << " \"w2_retire_record_lifecycle_evidence_clear_accepted\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_clear_accepted << ",\n" - << " \"w2_retire_record_lifecycle_evidence_provider_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_provider_valid << ",\n" - << " \"w2_retire_record_lifecycle_evidence_provider_valid_without_record\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_provider_valid_without_record << ",\n" - << " \"w2_retire_record_lifecycle_evidence_record_valid_without_provider\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_evidence_record_valid_without_provider << ",\n" - << " \"w2_retire_record_lifecycle_clear_fallback_capture_physical_clear\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_capture_physical_clear << ",\n" - << " \"w2_retire_record_lifecycle_clear_fallback_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_candidate << ",\n" - << " \"w2_retire_record_lifecycle_clear_fallback_duplicate_physical_clear\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_duplicate_physical_clear << ",\n" - << " \"w2_retire_record_lifecycle_clear_fallback_clear_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_clear_valid << ",\n" - << " \"w2_retire_record_rob_fallback_capture_physical_complete\": " - << g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_capture_physical_complete << ",\n" - << " \"w2_retire_record_rob_fallback_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_candidate << ",\n" - << " \"w2_retire_record_rob_fallback_duplicate_physical_complete\": " - << g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_duplicate_physical_complete << ",\n" - << " \"w2_retire_record_rob_fallback_complete_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_complete_valid << ",\n" - << " \"w2_retire_record_rf_fallback_capture_physical_writeback\": " - << g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_capture_physical_writeback << ",\n" - << " \"w2_retire_record_rf_fallback_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_candidate << ",\n" - << " \"w2_retire_record_rf_fallback_duplicate_physical_writeback\": " - << g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_duplicate_physical_writeback << ",\n" - << " \"w2_retire_record_rf_fallback_writeback_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_writeback_valid << ",\n" - << " \"w2_retire_record_wakeup_fallback_capture_physical_wakeup\": " - << g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_capture_physical_wakeup << ",\n" - << " \"w2_retire_record_wakeup_fallback_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_candidate << ",\n" - << " \"w2_retire_record_wakeup_fallback_duplicate_physical_wakeup\": " - << g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_duplicate_physical_wakeup << ",\n" - << " \"w2_retire_record_wakeup_fallback_wakeup_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_wakeup_valid << ",\n" - << " \"w2_retire_record_fallback_owner_policy_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_candidate << ",\n" - << " \"w2_retire_record_fallback_owner_policy_all_candidates_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_all_candidates_ready << ",\n" - << " \"w2_retire_record_fallback_owner_policy_blocked_by_physical_duplicate\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_blocked_by_physical_duplicate - << ",\n" - << " \"w2_retire_record_fallback_owner_policy_no_physical_probe_active\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_no_physical_probe_active << ",\n" - << " \"w2_retire_record_fallback_owner_policy_fallback_emit_probe_active\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_fallback_emit_probe_active - << ",\n" - << " \"w2_retire_record_fallback_owner_policy_fallback_live_probe_active\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_fallback_live_probe_active - << ",\n" - << " \"w2_retire_record_fallback_owner_policy_retained_sole_owner_eligible\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_retained_sole_owner_eligible - << ",\n" - << " \"w2_retire_record_fallback_owner_policy_blocked_by_global_fallback_disabled\": " - << g_replay_liq_sideband_stats - .w2_retire_record_fallback_owner_policy_blocked_by_global_fallback_disabled - << ",\n" - << " \"w2_retire_record_fallback_owner_policy_side_effect_enable\": " - << g_replay_liq_sideband_stats.w2_retire_record_fallback_owner_policy_side_effect_enable << ",\n" - << " \"w2_retire_record_rob_fallback_live_complete_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_rob_fallback_live_complete_selected << ",\n" - << " \"w2_retire_record_rf_fallback_live_writeback_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_rf_fallback_live_writeback_selected << ",\n" - << " \"w2_retire_record_wakeup_fallback_live_wakeup_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_wakeup_fallback_live_wakeup_selected << ",\n" - << " \"w2_retire_record_lifecycle_clear_fallback_live_clear_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_lifecycle_clear_fallback_live_clear_selected << ",\n" - << " \"w2_retire_record_model_order_record_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_record_candidate << ",\n" - << " \"w2_retire_record_model_order_return_side_effects_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_return_side_effects_ready << ",\n" - << " \"w2_retire_record_model_order_retire_clear_evidence_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_retire_clear_evidence_ready << ",\n" - << " \"w2_retire_record_model_order_return_then_retire_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_return_then_retire_ready << ",\n" - << " \"w2_retire_record_model_order_fallback_owner_eligible\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_fallback_owner_eligible << ",\n" - << " \"w2_retire_record_model_order_blocked_by_missing_return_side_effect\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_missing_return_side_effect - << ",\n" - << " \"w2_retire_record_model_order_blocked_by_missing_retire_clear_evidence\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_missing_retire_clear_evidence - << ",\n" - << " \"w2_retire_record_model_order_blocked_by_owner_disabled\": " - << g_replay_liq_sideband_stats.w2_retire_record_model_order_blocked_by_owner_disabled << ",\n" - << " \"w2_retire_record_default_promotion_record_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_record_candidate << ",\n" - << " \"w2_retire_record_default_promotion_pre_arm_model_order_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_pre_arm_model_order_ready << ",\n" - << " \"w2_retire_record_default_promotion_any_physical_duplicate\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_any_physical_duplicate << ",\n" - << " \"w2_retire_record_default_promotion_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_ready << ",\n" - << " \"w2_retire_record_default_promotion_blocked_by_no_record\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_no_record << ",\n" - << " \"w2_retire_record_default_promotion_blocked_by_missing_fallback_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_missing_fallback_candidate - << ",\n" - << " \"w2_retire_record_default_promotion_blocked_by_missing_lifecycle_evidence\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_missing_lifecycle_evidence - << ",\n" - << " \"w2_retire_record_default_promotion_blocked_by_physical_duplicate\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_physical_duplicate << ",\n" - << " \"w2_retire_record_default_promotion_blocked_by_probe_active\": " - << g_replay_liq_sideband_stats.w2_retire_record_default_promotion_blocked_by_probe_active << ",\n" - << " \"w2_retire_record_duplicate_vector_valid\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_valid << ",\n" - << " \"w2_retire_record_duplicate_vector_return_side_effect_bundle\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_return_side_effect_bundle << ",\n" - << " \"w2_retire_record_duplicate_vector_model_order_bundle\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_model_order_bundle << ",\n" - << " \"w2_retire_record_duplicate_vector_partial\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_partial << ",\n" - << " \"w2_retire_record_duplicate_vector_single\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_single << ",\n" - << " \"w2_retire_record_duplicate_vector_multi\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_multi << ",\n" - << " \"w2_retire_record_duplicate_vector_count_sum\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_count_sum << ",\n" - << " \"w2_retire_record_duplicate_vector_next_requires_bundle_transfer\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_next_requires_bundle_transfer - << ",\n" - << " \"w2_retire_record_duplicate_vector_blocked_by_no_record\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_no_record << ",\n" - << " \"w2_retire_record_duplicate_vector_blocked_by_pre_arm_not_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_pre_arm_not_ready << ",\n" - << " \"w2_retire_record_duplicate_vector_blocked_by_no_duplicate\": " - << g_replay_liq_sideband_stats.w2_retire_record_duplicate_vector_blocked_by_no_duplicate << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_candidate << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_pre_arm_ready\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_pre_arm_ready << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_model_order_bundle\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_model_order_bundle << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_default_transfer_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_default_transfer_candidate - << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_requires_physical_bundle_suppression\": " - << g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_requires_physical_bundle_suppression - << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_default_promotion_already_ready\": " - << g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_default_promotion_already_ready << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_blocked_by_no_record\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_no_record << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_blocked_by_pre_arm_not_ready\": " - << g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_blocked_by_pre_arm_not_ready << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_blocked_by_no_duplicate_vector\": " - << g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_blocked_by_no_duplicate_vector << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_blocked_by_partial_duplicate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_bundle_transfer_plan_blocked_by_partial_duplicate << ",\n" - << " \"w2_retire_record_bundle_transfer_plan_blocked_by_probe_active\": " - << g_replay_liq_sideband_stats.w2_retire_record_bundle_transfer_plan_blocked_by_probe_active - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_transfer_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_transfer_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppression_required\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppression_required << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_physical_bundle_complete\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_physical_bundle_complete << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppress_rob_complete\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppress_rob_complete << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppress_rf_writeback\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppress_rf_writeback << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppress_wakeup\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppress_wakeup << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppress_lifecycle_clear\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppress_lifecycle_clear << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_suppress_mask_sum\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_suppress_mask_sum << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_all_or_none_suppress\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_all_or_none_suppress << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_transfer_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_transfer_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_suppression_requirement\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_suppression_requirement << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_plan_blocked_by_incomplete_physical_bundle\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_plan_blocked_by_incomplete_physical_bundle - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_enabled_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_enabled_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_probe_selected << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_selected_mask_sum\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_selected_mask_sum << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_all_or_none_input_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_all_or_none_input_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_blocked_by_probe_disabled\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_probe_disabled << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_blocked_by_no_atomic_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_no_atomic_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_plan_promoted_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_plan_promoted_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_selected\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_select_selected << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_selected_mask_sum\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_selected_mask_sum << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_all_or_none_input_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_all_or_none_input_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_selected_from_probe\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_selected_from_probe << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_selected_from_promotion\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_selected_from_promotion << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_blocked_by_no_plan_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_no_plan_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_capture\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_boundary_capture << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_registered_valid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_registered_valid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_registered_mask_sum\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_registered_mask_sum << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_registered_full_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_registered_full_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_blocked_by_no_selection\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_blocked_by_no_selection << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_blocked_by_partial_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_blocked_by_partial_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_boundary_cleared_by_flush\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_boundary_cleared_by_flush - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_capture_identity\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_capture_identity << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_captured_identity_valid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_captured_identity_valid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_registered_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_registered_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_retained_record_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_retained_record_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_lifecycle_row_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_lifecycle_row_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_lifetime_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_lifetime_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_eligible_registered_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_eligible_registered_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_no_captured_identity\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_no_captured_identity << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_record\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_record << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_rid_mismatch\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_rid_mismatch << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_load_lsid_mismatch\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_load_lsid_mismatch << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_lifecycle_evidence\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_lifecycle_evidence << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_lifecycle_row_mismatch\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_lifecycle_row_mismatch << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_identity_blocked_by_not_full_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_identity_blocked_by_not_full_mask - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_capture_ownership\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_capture_ownership << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_captured_ownership_valid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_captured_ownership_valid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_registered_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_registered_rid_valid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_rid_valid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_registered_load_lsid_valid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_load_lsid_valid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_registered_lifecycle_row_ready\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_lifecycle_row_ready << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_registered_bundle_ready\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_registered_bundle_ready << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_blocked_by_no_captured_ownership\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_no_captured_ownership << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_rid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_rid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_load_lsid\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_load_lsid << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_lifecycle_row\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_lifecycle_row << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_ownership_blocked_by_not_full_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_ownership_blocked_by_not_full_mask - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_candidate\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_suppress_rob_complete\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_rob_complete << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_suppress_rf_writeback\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_rf_writeback << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_suppress_wakeup\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_wakeup << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_suppress_lifecycle_clear\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_lifecycle_clear << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_suppress_mask_sum\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_suppress_mask_sum << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_all_or_none\": " - << g_replay_liq_sideband_stats.w2_retire_record_physical_bundle_suppress_live_mask_all_or_none << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_live_mask_disabled\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_live_mask_disabled << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_no_eligible_ownership\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_no_eligible_ownership - << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_candidate\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_candidate << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_full_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_full_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_fire_complete_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_fire_complete_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_clear_intent_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_clear_intent_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_live_clear_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_live_clear_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_row_fill_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_row_fill_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_lifecycle_clear_suppressed\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_lifecycle_clear_suppressed << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_partial_mask\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_partial_mask << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_fire_complete\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_fire_complete << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_clear_intent\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_clear_intent << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_live_clear\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_live_clear << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_row_fill\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_row_fill << ",\n" - << " \"w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_lifecycle_clear_still_enabled\": " - << g_replay_liq_sideband_stats - .w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_lifecycle_clear_still_enabled - << ",\n" - << " \"resolve_queue_push_accepted\": " - << g_replay_liq_sideband_stats.resolve_queue_push_accepted << ",\n" - << " \"resolve_queue_valid\": " - << g_replay_liq_sideband_stats.resolve_queue_valid << ",\n" - << " \"resolve_queue_push_accepted_first_cycle\": " - << g_replay_liq_sideband_stats.resolve_queue_push_accepted_first_cycle << ",\n" - << " \"resolve_queue_push_accepted_last_cycle\": " - << g_replay_liq_sideband_stats.resolve_queue_push_accepted_last_cycle << ",\n" - << " \"resolve_queue_valid_first_cycle\": " - << g_replay_liq_sideband_stats.resolve_queue_valid_first_cycle << ",\n" - << " \"resolve_queue_valid_last_cycle\": " - << g_replay_liq_sideband_stats.resolve_queue_valid_last_cycle << ",\n" - << " \"mdb_conflict_store_valid\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_valid << ",\n" - << " \"mdb_conflict_store_valid_first_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_valid_first_cycle << ",\n" - << " \"mdb_conflict_store_valid_last_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_valid_last_cycle << ",\n" - << " \"mdb_conflict_store_with_resolve_queue_valid\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid << ",\n" - << " \"mdb_conflict_store_with_resolve_queue_valid_first_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid_first_cycle << ",\n" - << " \"mdb_conflict_store_with_resolve_queue_valid_last_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_with_resolve_queue_valid_last_cycle << ",\n" - << " \"mdb_conflict_store_without_resolve_queue_valid\": " - << g_replay_liq_sideband_stats.mdb_conflict_store_without_resolve_queue_valid << ",\n" - << " \"mdb_conflict_active_candidate\": " - << g_replay_liq_sideband_stats.mdb_conflict_active_candidate << ",\n" - << " \"mdb_conflict_resolve_candidate\": " - << g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate << ",\n" - << " \"mdb_conflict_resolve_candidate_first_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate_first_cycle << ",\n" - << " \"mdb_conflict_resolve_candidate_last_cycle\": " - << g_replay_liq_sideband_stats.mdb_conflict_resolve_candidate_last_cycle << ",\n" - << " \"mdb_conflict_valid\": " - << g_replay_liq_sideband_stats.mdb_conflict_valid << ",\n" - << " \"mdb_fanout_record_valid\": " - << g_replay_liq_sideband_stats.mdb_fanout_record_valid << ",\n" - << " \"mdb_fanout_record_accepted\": " - << g_replay_liq_sideband_stats.mdb_fanout_record_accepted << ",\n" - << " \"mdb_fanout_record_processed\": " - << g_replay_liq_sideband_stats.mdb_fanout_record_processed << ",\n" - << " \"mdb_fanout_bmdb_report\": " - << g_replay_liq_sideband_stats.mdb_fanout_bmdb_report << ",\n" - << " \"mdb_fanout_ssit_nonempty\": " - << g_replay_liq_sideband_stats.mdb_fanout_ssit_nonempty << ",\n" - << " \"mdb_fanout_lookup_valid\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_valid << ",\n" - << " \"mdb_fanout_lookup_accepted\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_accepted << ",\n" - << " \"mdb_fanout_lookup_processed\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_processed << ",\n" - << " \"mdb_fanout_lookup_table_hit\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_table_hit << ",\n" - << " \"mdb_fanout_lookup_first_after_nuke\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_first_after_nuke << ",\n" - << " \"mdb_fanout_lookup_conf_blocked\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_conf_blocked << ",\n" - << " \"mdb_fanout_lookup_weight_blocked\": " - << g_replay_liq_sideband_stats.mdb_fanout_lookup_weight_blocked << ",\n" - << " \"mdb_fanout_lu_out_valid\": " - << g_replay_liq_sideband_stats.mdb_fanout_lu_out_valid << ",\n" - << " \"mdb_fanout_lu_out_hit\": " - << g_replay_liq_sideband_stats.mdb_fanout_lu_out_hit << ",\n" - << " \"mdb_fanout_su_out_valid\": " - << g_replay_liq_sideband_stats.mdb_fanout_su_out_valid << ",\n" - << " \"mdb_fanout_su_out_hit\": " - << g_replay_liq_sideband_stats.mdb_fanout_su_out_hit << ",\n" - << " \"mdb_fanout_su_wakeup_valid\": " - << g_replay_liq_sideband_stats.mdb_fanout_su_wakeup_valid << ",\n" - << " \"mdb_lookup_wait_plan_lookup_hit\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_lookup_hit << ",\n" - << " \"mdb_lookup_wait_plan_wait_intent_valid\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_wait_intent_valid << ",\n" - << " \"mdb_lookup_wait_plan_request_valid\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_request_valid << ",\n" - << " \"mdb_lookup_wait_plan_blocked_by_no_target\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_no_target << ",\n" - << " \"mdb_lookup_wait_plan_blocked_by_missing_store_index\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_missing_store_index << ",\n" - << " \"mdb_lookup_wait_plan_blocked_by_missing_store_lsid\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_blocked_by_missing_store_lsid << ",\n" - << " \"mdb_lookup_wait_plan_bridge_active\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_active << ",\n" - << " \"mdb_lookup_wait_plan_bridge_valid\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_valid << ",\n" - << " \"mdb_lookup_wait_plan_bridge_source_store_index_fits\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_source_store_index_fits << ",\n" - << " \"mdb_lookup_wait_plan_bridge_blocked_by_disabled\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_disabled << ",\n" - << " \"mdb_lookup_wait_plan_bridge_blocked_by_flush\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_flush << ",\n" - << " \"mdb_lookup_wait_plan_bridge_blocked_by_no_request\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_blocked_by_no_request << ",\n" - << " \"mdb_lookup_wait_plan_bridge_invalid_store_index_out_of_range\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_store_index_out_of_range << ",\n" - << " \"mdb_lookup_wait_plan_bridge_invalid_conflicting_status_write\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_conflicting_status_write << ",\n" - << " \"mdb_lookup_wait_plan_bridge_invalid_wait_store_without_wait_status\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_wait_store_without_wait_status << ",\n" - << " \"mdb_lookup_wait_plan_bridge_invalid_return_without_split_sources\": " - << g_replay_liq_sideband_stats.mdb_lookup_wait_plan_bridge_invalid_return_without_split_sources << ",\n" - << " \"liq_row_mutation_bridge_valid\": " - << g_replay_liq_sideband_stats.liq_row_mutation_bridge_valid << ",\n" - << " \"liq_row_mutation_selected_source_return\": " - << g_replay_liq_sideband_stats.liq_row_mutation_selected_source_return << ",\n" - << " \"liq_row_mutation_selected_mdb_wait_plan\": " - << g_replay_liq_sideband_stats.liq_row_mutation_selected_mdb_wait_plan << ",\n" - << " \"liq_row_mutation_source_conflict\": " - << g_replay_liq_sideband_stats.liq_row_mutation_source_conflict << ",\n" - << " \"mdb_wait_plan_row_mutation_write_enable\": " - << g_replay_liq_sideband_stats.mdb_wait_plan_row_mutation_write_enable << ",\n" - << " \"liq_row_mutation_write_enable\": " - << g_replay_liq_sideband_stats.liq_row_mutation_write_enable << ",\n" - << " \"liq_row_mutation_apply_valid\": " - << g_replay_liq_sideband_stats.liq_row_mutation_apply_valid << ",\n" - << " \"liq_row_mutation_blocked_by_bridge\": " - << g_replay_liq_sideband_stats.liq_row_mutation_blocked_by_bridge << ",\n" - << " \"liq_row_mutation_blocked_by_control\": " - << g_replay_liq_sideband_stats.liq_row_mutation_blocked_by_control << "\n" - << " }\n" - << "}\n"; - return true; -} - -bool trace_top_debug_enabled() { - static const bool enabled = std::getenv("LINXCORE_TRACE_TOP_DEBUG") != nullptr; - return enabled; -} - -void trace_top_debug_pipeline( - const VLinxCoreFrontendFetchRfAluTraceTop &dut, - const char *context); - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --dut-trace --qemu-trace " - << " [--expected-rows ]" - << " [--memory-bin --memory-base ]" - << " [--memory-hex ]" - << " [--rf-seed ]" - << " [--sideband-stats ]" - << " [--admit-marker-rows]" - << " [--disable-store-memory-mutation]" - << " [--allow-residual-replay-liq-wait]\n"; - std::exit(2); -} - -std::uint64_t parse_u64_arg(const std::string &value, const std::string &name) { - errno = 0; - char *end = nullptr; - const unsigned long long parsed = std::strtoull(value.c_str(), &end, 0); - if (errno != 0 || end == value.c_str() || *end != '\0') { - std::cerr << "invalid " << name << ": " << value << "\n"; - std::exit(2); - } - return static_cast(parsed); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--dut-trace" && i + 1 < argc) { - args.dut_trace = argv[++i]; - } else if (arg == "--qemu-trace" && i + 1 < argc) { - args.qemu_trace = argv[++i]; - } else if (arg == "--memory-bin" && i + 1 < argc) { - args.memory_bin = argv[++i]; - } else if (arg == "--memory-hex" && i + 1 < argc) { - args.memory_hex = argv[++i]; - } else if (arg == "--expected-rows" && i + 1 < argc) { - args.expected_rows = argv[++i]; - } else if (arg == "--rf-seed" && i + 1 < argc) { - args.rf_seed = argv[++i]; - } else if (arg == "--sideband-stats" && i + 1 < argc) { - args.sideband_stats = argv[++i]; - } else if (arg == "--memory-base" && i + 1 < argc) { - args.memory_base = parse_u64_arg(argv[++i], "--memory-base"); - } else if (arg == "--admit-marker-rows") { - args.admit_marker_rows = true; - } else if (arg == "--disable-store-memory-mutation") { - args.disable_store_memory_mutation = true; - } else if (arg == "--allow-residual-replay-liq-wait") { - args.allow_residual_replay_liq_wait = true; - } else { - usage(argv[0]); - } - } - if (args.dut_trace.empty() || args.qemu_trace.empty()) { - usage(argv[0]); - } - if (!args.memory_bin.empty() && !args.memory_hex.empty()) { - std::cerr << "--memory-bin and --memory-hex are mutually exclusive\n"; - usage(argv[0]); - } - return args; -} - -std::string trim_copy(const std::string &value) { - const auto first = value.find_first_not_of(" \t\r\n"); - if (first == std::string::npos) { - return ""; - } - const auto last = value.find_last_not_of(" \t\r\n"); - return value.substr(first, last - first + 1); -} - -bool json_value_token(const std::string &line, const std::string &key, std::string &token) { - const std::string quoted_key = "\"" + key + "\""; - const std::size_t key_pos = line.find(quoted_key); - if (key_pos == std::string::npos) { - return false; - } - std::size_t pos = key_pos + quoted_key.size(); - while (pos < line.size() && std::isspace(static_cast(line[pos]))) { - ++pos; - } - if (pos >= line.size() || line[pos] != ':') { - return false; - } - ++pos; - while (pos < line.size() && std::isspace(static_cast(line[pos]))) { - ++pos; - } - if (pos >= line.size()) { - return false; - } - - if (line[pos] == '"') { - ++pos; - std::string value; - bool escaped = false; - for (; pos < line.size(); ++pos) { - const char ch = line[pos]; - if (escaped) { - value.push_back(ch); - escaped = false; - continue; - } - if (ch == '\\') { - escaped = true; - continue; - } - if (ch == '"') { - token = trim_copy(value); - return true; - } - value.push_back(ch); - } - return false; - } - - const std::size_t end = line.find_first_of(",}", pos); - if (end == std::string::npos) { - return false; - } - token = trim_copy(line.substr(pos, end - pos)); - return !token.empty(); -} - -bool json_has_key(const std::string &line, const std::string &key) { - std::string ignored; - return json_value_token(line, key, ignored); -} - -std::uint64_t json_u64( - const std::string &line, - const std::string &key, - std::uint64_t default_value, - const std::string &context) { - std::string token; - if (!json_value_token(line, key, token)) { - return default_value; - } - return parse_u64_arg(token, context + "." + key); -} - -std::uint8_t json_u8( - const std::string &line, - const std::string &key, - std::uint8_t default_value, - const std::string &context) { - const std::uint64_t value = json_u64(line, key, default_value, context); - if (value > 0xffU) { - std::cerr << "expected row field out of uint8 range: " - << context << "." << key << "=" << value << "\n"; - std::exit(2); - } - return static_cast(value); -} - -bool json_bool( - const std::string &line, - const std::string &key, - bool default_value, - const std::string &context) { - std::string token; - if (!json_value_token(line, key, token)) { - return default_value; - } - for (char &ch : token) { - ch = static_cast(std::tolower(static_cast(ch))); - } - if (token == "true" || token == "yes" || token == "1") { - return true; - } - if (token == "false" || token == "no" || token == "0") { - return false; - } - const std::uint64_t numeric = parse_u64_arg(token, context + "." + key); - return numeric != 0; -} - -ExpectedRow parse_expected_row_jsonl( - const std::string &line, - const std::string &path, - std::uint64_t line_no) { - const std::string context = path + ":" + std::to_string(line_no); - if (!json_has_key(line, "pc") || !json_has_key(line, "insn")) { - std::cerr << "expected row is missing pc or insn at " << context << "\n"; - std::exit(2); - } - - ExpectedRow row; - row.pc = json_u64(line, "pc", 0, context); - row.insn = json_u64(line, "insn", 0, context); - row.len = json_u8(line, "len", 4, context); - if (row.len != 2 && row.len != 4 && row.len != 6 && row.len != 8) { - std::cerr << "expected row has unsupported instruction length at " - << context << " len=" << static_cast(row.len) << "\n"; - std::exit(2); - } - row.skip = json_bool(line, "skip", false, context); - (void)json_value_token(line, "skip_kind", row.skip_kind); - row.block_boundary = json_bool(line, "block_boundary", false, context); - row.block_stop = json_bool(line, "block_stop", false, context); - row.loop_reentry = json_bool(line, "loop_reentry", false, context); - row.loop_reentry_from_pc = json_u64(line, "loop_reentry_from_pc", 0, context); - - row.src0_valid = json_bool(line, "src0_valid", false, context); - row.src0_reg = json_u8(line, "src0_reg", 0, context); - row.src0_data = json_u64(line, "src0_data", 0, context); - row.src1_valid = json_bool(line, "src1_valid", false, context); - row.src1_reg = json_u8(line, "src1_reg", 0, context); - row.src1_data = json_u64(line, "src1_data", 0, context); - - const bool has_dst_valid = json_has_key(line, "dst_valid"); - const bool has_dst_reg = json_has_key(line, "dst_reg"); - const bool has_dst_data = json_has_key(line, "dst_data"); - row.dst_valid = json_bool(line, "dst_valid", json_bool(line, "wb_valid", false, context), context); - row.dst_reg = json_u8(line, "dst_reg", json_u8(line, "wb_rd", 0, context), context); - row.dst_data = json_u64(line, "dst_data", json_u64(line, "wb_data", 0, context), context); - if (!has_dst_valid && json_has_key(line, "wb_valid")) { - row.dst_valid = json_bool(line, "wb_valid", false, context); - } - if (!has_dst_reg && json_has_key(line, "wb_rd")) { - row.dst_reg = json_u8(line, "wb_rd", 0, context); - } - if (!has_dst_data && json_has_key(line, "wb_data")) { - row.dst_data = json_u64(line, "wb_data", 0, context); - } - row.mem_valid = json_bool(line, "mem_valid", false, context); - row.mem_is_store = json_bool(line, "mem_is_store", false, context); - row.mem_addr = json_u64(line, "mem_addr", 0, context); - row.mem_wdata = json_u64(line, "mem_wdata", 0, context); - row.mem_rdata = json_u64(line, "mem_rdata", 0, context); - row.mem_size = json_u8(line, "mem_size", 0, context); - row.next_pc = json_u64(line, "next_pc", row.pc + row.len, context); - return row; -} - -std::vector load_expected_rows_jsonl(const std::string &path) { - std::ifstream in(path); - if (!in) { - std::cerr << "failed to open expected rows: " << path - << " error=" << std::strerror(errno) << "\n"; - std::exit(2); - } - - std::vector rows; - std::string line; - std::uint64_t line_no = 0; - while (std::getline(in, line)) { - ++line_no; - line = trim_copy(line); - if (line.empty() || line[0] == '#') { - continue; - } - if (line.find("\"type\"") != std::string::npos && - line.find("\"META\"") != std::string::npos) { - continue; - } - if (json_has_key(line, "valid") && - !json_bool(line, "valid", true, path + ":" + std::to_string(line_no))) { - continue; - } - rows.push_back(parse_expected_row_jsonl(line, path, line_no)); - } - if (rows.empty()) { - std::cerr << "expected row stream is empty: " << path << "\n"; - std::exit(2); - } - return rows; -} - -std::map load_rf_seed_jsonl(const std::string &path) { - std::ifstream in(path); - if (!in) { - std::cerr << "failed to open RF seed: " << path - << " error=" << std::strerror(errno) << "\n"; - std::exit(2); - } - - std::map seed; - std::string line; - std::uint64_t line_no = 0; - while (std::getline(in, line)) { - ++line_no; - line = trim_copy(line); - if (line.empty() || line[0] == '#') { - continue; - } - if (line.find("\"type\"") != std::string::npos && - line.find("\"META\"") != std::string::npos) { - continue; - } - const std::string context = path + ":" + std::to_string(line_no); - if (json_has_key(line, "valid") && !json_bool(line, "valid", true, context)) { - continue; - } - if (!json_has_key(line, "data")) { - std::cerr << "RF seed row is missing data at " << context << "\n"; - std::exit(2); - } - std::uint8_t reg = 0; - if (json_has_key(line, "arch_reg")) { - reg = json_u8(line, "arch_reg", 0, context); - } else if (json_has_key(line, "arch_tag")) { - reg = json_u8(line, "arch_tag", 0, context); - } else if (json_has_key(line, "reg")) { - reg = json_u8(line, "reg", 0, context); - } else { - std::cerr << "RF seed row is missing arch_reg/arch_tag/reg at " << context << "\n"; - std::exit(2); - } - if (reg >= 24) { - std::cerr << "RF seed row targets unsupported reduced GPR arch tag at " - << context << " reg=" << static_cast(reg) << "\n"; - std::exit(2); - } - const std::uint64_t data = json_u64(line, "data", 0, context); - const auto [it, inserted] = seed.emplace(reg, data); - if (!inserted && it->second != data) { - std::cerr << "RF seed has conflicting data for reg=" - << static_cast(reg) - << " first=" << it->second - << " later=" << data << "\n"; - std::exit(2); - } - } - return seed; -} - -void clear_inputs(VLinxCoreFrontendFetchRfAluTraceTop &dut) { - dut.io_startValid = 0; - dut.io_startPc = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_bfuBodyValid = 0; - dut.io_bfuHeaderPc = 0; - dut.io_bfuHSizeBytes = 0; - dut.io_bfuBSizeBytes = 0; - dut.io_frontendFlushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 0; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_rfInitValid = 0; - dut.io_rfInitArchTag = 0; - dut.io_rfInitData = 0; - dut.io_deallocReady = 1; - dut.io_loadLookupData = 0; -} - -void observe_gpr_commit_history(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - if (dut.io_robDeallocBlockLastValid) { - ++g_gpr_commit_history.dealloc_block_last_count; - g_gpr_commit_history.last_dealloc_block_last_bid = dut.io_robDeallocBlockLastBlockBid; - } - if (dut.io_blockScalarDoneFire) { - ++g_gpr_commit_history.block_scalar_done_count; - g_gpr_commit_history.last_scalar_done_bid = dut.io_blockScalarDoneBid; - } - if (dut.io_blockRetireFire) { - ++g_gpr_commit_history.block_retire_count; - g_gpr_commit_history.last_block_retire_bid = dut.io_blockRetireBid; - } - if (dut.io_gprCommitAccepted) { - ++g_gpr_commit_history.gpr_commit_count; - g_gpr_commit_history.last_gpr_commit_bid = dut.io_gprCommitBlockBid; - g_gpr_commit_history.last_gpr_commit_hits = dut.io_gprCommittedMapQCount; - g_gpr_commit_history.last_gpr_releases = dut.io_gprReleasedPhysCount; - g_gpr_commit_history.gpr_commit_hit_total += dut.io_gprCommittedMapQCount; - g_gpr_commit_history.gpr_release_total += dut.io_gprReleasedPhysCount; - if (dut.io_gprCommittedMapQCount || dut.io_gprReleasedPhysCount) { - g_gpr_commit_history.last_nonzero_gpr_commit_bid = dut.io_gprCommitBlockBid; - g_gpr_commit_history.last_nonzero_gpr_commit_hits = dut.io_gprCommittedMapQCount; - g_gpr_commit_history.last_nonzero_gpr_releases = dut.io_gprReleasedPhysCount; - } - } -} - -void dump_gpr_commit_history_line(const char *label) { - std::cerr << "frontend fetch RF ALU " << label - << " histDeallocBlockLast=" << g_gpr_commit_history.dealloc_block_last_count - << " histScalarDone=" << g_gpr_commit_history.block_scalar_done_count - << " histBlockRetire=" << g_gpr_commit_history.block_retire_count - << " histGprCommit=" << g_gpr_commit_history.gpr_commit_count - << " histGprCommitHits=" << g_gpr_commit_history.gpr_commit_hit_total - << " histGprReleases=" << g_gpr_commit_history.gpr_release_total - << " lastDeallocBlockLastBid=0x" << std::hex - << g_gpr_commit_history.last_dealloc_block_last_bid - << " lastScalarDoneBid=0x" << g_gpr_commit_history.last_scalar_done_bid - << " lastBlockRetireBid=0x" << g_gpr_commit_history.last_block_retire_bid - << " lastGprCommitBid=0x" << g_gpr_commit_history.last_gpr_commit_bid - << " lastNonzeroGprCommitBid=0x" << g_gpr_commit_history.last_nonzero_gpr_commit_bid - << std::dec - << " lastGprCommitHits=" << static_cast(g_gpr_commit_history.last_gpr_commit_hits) - << " lastGprReleases=" << static_cast(g_gpr_commit_history.last_gpr_releases) - << " lastNonzeroGprCommitHits=" - << static_cast(g_gpr_commit_history.last_nonzero_gpr_commit_hits) - << " lastNonzeroGprReleases=" - << static_cast(g_gpr_commit_history.last_nonzero_gpr_releases) - << "\n"; -} - -void tick(VLinxCoreFrontendFetchRfAluTraceTop &dut) { - dut.clock = 0; - dut.eval(); - observe_gpr_commit_history(dut); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); - ++g_tb_cycle; - observe_replay_liq_sideband(dut); -} - -void reset(VLinxCoreFrontendFetchRfAluTraceTop &dut) { - clear_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - dut.eval(); -} - -void init_rf(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::uint8_t arch_tag, std::uint64_t data) { - clear_inputs(dut); - dut.io_rfInitValid = 1; - dut.io_rfInitArchTag = arch_tag; - dut.io_rfInitData = data; - tick(dut); - clear_inputs(dut); - dut.eval(); -} - -std::map initial_rf_preloads( - const std::vector &rows, - const std::map &seed_preloads) { - std::map preloads = seed_preloads; - std::map produced; - - const auto observe_source = [&](bool valid, std::uint8_t reg, std::uint64_t data) { - if (!valid || produced[reg]) { - return; - } - const auto [it, inserted] = preloads.emplace(reg, data); - if (!inserted && it->second != data) { - std::cerr << "expected rows require conflicting initial RF data" - << " reg=" << static_cast(reg) - << " first=" << it->second - << " later=" << data << "\n"; - std::exit(2); - } - }; - - for (const ExpectedRow &row : rows) { - if (row.skip) { - continue; - } - observe_source(row.src0_valid, row.src0_reg, row.src0_data); - observe_source(row.src1_valid, row.src1_reg, row.src1_data); - if (row.dst_valid && row.dst_reg < 24) { - produced[row.dst_reg] = true; - } - } - return preloads; -} - -std::uint64_t mask_insn(std::uint64_t insn, std::uint8_t len) { - if (len == 2) { - return insn & 0xffffULL; - } - if (len == 4) { - return insn & 0xffff'ffffULL; - } - if (len == 6) { - return insn & 0xffff'ffff'ffffULL; - } - return insn; -} - -class FetchMemoryImage { -public: - void store_byte(std::uint64_t addr, std::uint8_t value) { - bytes_[addr] = value; - } - - void load_binary(const std::string &path, std::uint64_t base) { - std::ifstream in(path, std::ios::binary); - if (!in) { - std::cerr << "failed to open fetch memory image: " << path - << " error=" << std::strerror(errno) << "\n"; - std::exit(2); - } - - char ch = 0; - std::uint64_t offset = 0; - while (in.get(ch)) { - store_byte(base + offset, static_cast(static_cast(ch))); - ++offset; - } - if (offset == 0) { - std::cerr << "fetch memory image is empty: " << path << "\n"; - std::exit(2); - } - } - - void load_sparse_hex(const std::string &path) { - std::ifstream in(path); - if (!in) { - std::cerr << "failed to open sparse fetch memory image: " << path - << " error=" << std::strerror(errno) << "\n"; - std::exit(2); - } - - std::string line; - std::uint64_t loaded = 0; - std::uint64_t line_no = 0; - while (std::getline(in, line)) { - ++line_no; - const auto comment = line.find('#'); - if (comment != std::string::npos) { - line.resize(comment); - } - - std::istringstream iss(line); - std::string addr_token; - std::string byte_token; - std::string extra; - if (!(iss >> addr_token)) { - continue; - } - if (!(iss >> byte_token) || (iss >> extra)) { - std::cerr << "invalid sparse fetch memory line" - << " path=" << path - << " line=" << line_no << "\n"; - std::exit(2); - } - - const std::uint64_t addr = - parse_u64_arg(addr_token, "sparse memory address at " + path + ":" + std::to_string(line_no)); - const std::uint64_t byte = - parse_u64_arg(byte_token, "sparse memory byte at " + path + ":" + std::to_string(line_no)); - if (byte > 0xffU) { - std::cerr << "sparse fetch memory byte out of range" - << " path=" << path - << " line=" << line_no - << " value=0x" << std::hex << byte << std::dec << "\n"; - std::exit(2); - } - store_byte(addr, static_cast(byte)); - ++loaded; - } - - if (loaded == 0) { - std::cerr << "sparse fetch memory image is empty: " << path << "\n"; - std::exit(2); - } - } - - std::uint64_t read_window(std::uint64_t pc) const { - std::uint64_t window = 0; - for (std::uint8_t byte_index = 0; byte_index < 8; ++byte_index) { - std::uint8_t byte = 0xffU; - if (!read_byte(pc + byte_index, byte) && byte_index == 0) { - std::cerr << "fetch memory image missing first byte" - << " pc=0x" << std::hex << pc << std::dec << "\n"; - std::exit(1); - } - window |= static_cast(byte) << (static_cast(byte_index) * 8U); - } - return window; - } - - std::uint64_t read_u64_or_zero(std::uint64_t addr) const { - std::uint64_t value = 0; - for (std::uint8_t byte_index = 0; byte_index < 8; ++byte_index) { - std::uint8_t byte = 0; - (void)read_byte(addr + byte_index, byte); - value |= static_cast(byte) << (static_cast(byte_index) * 8U); - } - return value; - } - - void store_u64(std::uint64_t addr, std::uint64_t value) { - for (std::uint8_t byte_index = 0; byte_index < 8; ++byte_index) { - store_byte( - addr + byte_index, - static_cast((value >> (static_cast(byte_index) * 8U)) & 0xffU)); - } - } - - static FetchMemoryImage from_rows(const std::vector &rows) { - FetchMemoryImage image; - for (const ExpectedRow &row : rows) { - const std::uint64_t insn = mask_insn(row.insn, row.len); - for (std::uint8_t byte_index = 0; byte_index < row.len; ++byte_index) { - image.store_byte( - row.pc + byte_index, - static_cast((insn >> (static_cast(byte_index) * 8U)) & 0xffU)); - } - } - return image; - } - -private: - bool read_byte(std::uint64_t addr, std::uint8_t &value) const { - const auto it = bytes_.find(addr); - if (it == bytes_.end()) { - return false; - } - value = it->second; - return true; - } - - std::map bytes_; -}; - -void eval_with_load_lookup( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - const FetchMemoryImage &fetch_memory, - const char *context = "eval") { - dut.eval(); - if (dut.io_loadLookupValid) { - dut.io_loadLookupData = fetch_memory.read_u64_or_zero(dut.io_loadLookupAddr); - dut.eval(); - } - if (dut.io_executeCompleteValid) { - IssueDebug debug; - debug.src_valid_mask = dut.io_executeCompleteSrcPhysValidMask; - debug.src_phys_tag0 = dut.io_executeCompleteSrcPhysTag_0; - debug.src_phys_tag1 = dut.io_executeCompleteSrcPhysTag_1; - debug.src_phys_tag2 = dut.io_executeCompleteSrcPhysTag_2; - g_issue_debug_by_rob[dut.io_executeCompleteRobValue] = debug; - } - if (dut.io_rfWriteValid) { - PhysWriter writer; - writer.valid = true; - writer.pc = dut.io_executeCompletePc; - writer.insn = dut.io_executeCompleteInsn; - writer.phys_tag = dut.io_rfWriteTag; - writer.wb_reg = dut.io_executeCompleteWbReg; - writer.data = dut.io_rfWriteData; - g_phys_writer_by_tag[dut.io_rfWriteTag] = writer; - g_arch_writer_by_reg[writer.wb_reg] = writer; - } - trace_top_debug_pipeline(dut, context); -} - -void attach_issue_debug(ObservedRow &row) { - const auto it = g_issue_debug_by_rob.find(row.rob_value); - if (it == g_issue_debug_by_rob.end()) { - return; - } - row.src_phys_valid_mask = it->second.src_valid_mask; - row.src_phys_tag0 = it->second.src_phys_tag0; - row.src_phys_tag1 = it->second.src_phys_tag1; - row.src_phys_tag2 = it->second.src_phys_tag2; -} - -void dump_phys_writer_line(const char *label, std::uint8_t tag) { - const auto it = g_phys_writer_by_tag.find(tag); - if (it == g_phys_writer_by_tag.end() || !it->second.valid) { - std::cerr << "frontend fetch RF ALU " << label - << " tag=" << static_cast(tag) - << " writer=\n"; - return; - } - std::cerr << "frontend fetch RF ALU " << label - << " tag=" << static_cast(tag) - << " writer_pc=0x" << std::hex << it->second.pc - << " writer_insn=0x" << it->second.insn - << std::dec - << " writer_phys=" << static_cast(it->second.phys_tag) - << " writer_wb=" << static_cast(it->second.wb_reg) - << " writer_data=" << it->second.data << "\n"; -} - -void dump_arch_writer_line(const char *label, std::uint8_t reg) { - const auto it = g_arch_writer_by_reg.find(reg); - if (it == g_arch_writer_by_reg.end() || !it->second.valid) { - std::cerr << "frontend fetch RF ALU " << label - << " reg=" << static_cast(reg) - << " writer=\n"; - return; - } - std::cerr << "frontend fetch RF ALU " << label - << " reg=" << static_cast(reg) - << " writer_pc=0x" << std::hex << it->second.pc - << " writer_insn=0x" << it->second.insn - << std::dec - << " writer_phys=" << static_cast(it->second.phys_tag) - << " writer_data=" << it->second.data << "\n"; -} - -bool is_fentry_insn(std::uint64_t insn) { - return (insn & 0x707full) == 0x41ull; -} - -std::uint8_t fentry_begin_reg(std::uint64_t insn) { - return static_cast((insn >> 15) & 0x1f); -} - -void trace_top_debug_pipeline( - const VLinxCoreFrontendFetchRfAluTraceTop &dut, - const char *context) { - if (!trace_top_debug_enabled()) { - return; - } - const bool interesting = - dut.io_denseSlotQueueOutFire || - dut.io_decRenPushFire || - dut.io_decRenPopFire || - dut.io_renamedAccepted || - dut.io_issueQueueEnqueueFire || - dut.io_issueQueuePickFire || - dut.io_issueQueueIssueFire || - dut.io_issueQueueReleaseFire || - dut.io_executeAccepted || - dut.io_executeCompleteValid || - dut.io_completeAccepted || - dut.io_commit_rows_0_valid || - dut.io_blockMarkerStopRedirectValid || - dut.io_robMarkerRetireSourceLifecycleFire; - if (!interesting) { - return; - } - std::cerr << "[trace-top-debug]" - << " cycle=" << g_tb_cycle - << " context=" << context - << " dense_out=" << static_cast(dut.io_denseSlotQueueOutFire) - << " dense_head_slot=" << static_cast(dut.io_denseSlotQueueHeadSlot) - << " selected_rob=" << static_cast(dut.io_selectedRobValue) - << " dec_push=" << static_cast(dut.io_decRenPushFire) - << " dec_pop=" << static_cast(dut.io_decRenPopFire) - << " dec_count=" << static_cast(dut.io_decRenCount) - << " dec_head_pc=0x" << std::hex - << static_cast(dut.io_decRenHeadPc) - << std::dec - << " renamed=" << static_cast(dut.io_renamedAccepted) - << " rename_upd=" << static_cast(dut.io_robRenameUpdateFire) - << " issue_enq=" << static_cast(dut.io_issueQueueEnqueueFire) - << " issue_pick=" << static_cast(dut.io_issueQueuePickFire) - << " issue_fire=" << static_cast(dut.io_issueQueueIssueFire) - << " issue_rel=" << static_cast(dut.io_issueQueueReleaseFire) - << " issue_count=" << static_cast(dut.io_issueQueueCount) - << " issue_head_pc=0x" << std::hex - << static_cast(dut.io_issueQueueHeadPc) - << " exec_acc=" << std::dec << static_cast(dut.io_executeAccepted) - << " exec_done=" << static_cast(dut.io_executeCompleteValid) - << " exec_pc=0x" << std::hex - << static_cast(dut.io_executeCompletePc) - << " exec_insn=0x" - << static_cast(dut.io_executeCompleteInsn) - << std::dec - << " exec_rob=" << static_cast(dut.io_executeCompleteRobValue) - << " complete_acc=" << static_cast(dut.io_completeAccepted) - << " commit_mask=0x" << std::hex << static_cast(dut.io_commitValidMask) - << " commit0_pc=0x" - << static_cast(dut.io_commit_rows_0_pc) - << std::dec - << " commit0_rob=" << static_cast(dut.io_commit_rows_0_rob_value) - << " marker_redirect=" << static_cast(dut.io_blockMarkerStopRedirectValid) - << " marker_redirect_pc=0x" << std::hex - << static_cast(dut.io_blockMarkerStopRedirectPc) - << std::dec - << " marker_active=" << static_cast(dut.io_blockMarkerActiveValid) - << " marker_active_bid=0x" << std::hex - << static_cast(dut.io_blockMarkerActiveBid) - << " marker_active_target=0x" - << static_cast(dut.io_blockMarkerActiveTarget) - << " marker_target=0x" - << static_cast(dut.io_blockMarkerTarget) - << std::dec - << " marker_lifecycle_fire=" << static_cast(dut.io_robMarkerRetireSourceLifecycleFire) - << " marker_source_valid=" << static_cast(dut.io_robMarkerRetireSourceValid) - << " marker_source_bid=(" - << static_cast(dut.io_robMarkerRetireSourceBidValid) - << "," << static_cast(dut.io_robMarkerRetireSourceBidWrap) - << "," << static_cast(dut.io_robMarkerRetireSourceBidValue) - << ") marker_source_rid=(" - << static_cast(dut.io_robMarkerRetireSourceRidValid) - << "," << static_cast(dut.io_robMarkerRetireSourceRidWrap) - << "," << static_cast(dut.io_robMarkerRetireSourceRidValue) - << ") marker_source_stid=" << static_cast(dut.io_robMarkerRetireSourceStid) - << " marker_source_block_bid_valid=" - << static_cast(dut.io_robMarkerRetireSourceBlockBidValid) - << " marker_source_block_bid=0x" << std::hex - << static_cast(dut.io_robMarkerRetireSourceBlockBid) - << std::dec - << "\n"; -} - -void expect_monitor_clean( - const VLinxCoreFrontendFetchRfAluTraceTop &dut, - const char *context, - std::uint8_t expected_mask, - std::uint8_t expected_count) { - if (dut.io_commitContractError || dut.io_commitSkippedSlot || - dut.io_commitDuplicateIdentity || dut.io_commitSlotMismatch || - dut.io_commitInvalidSideEffect) { - std::cerr << "commit monitor error during " << context - << " mask=" << static_cast(dut.io_commitMonitorValidMask) - << " count=" << static_cast(dut.io_commitMonitorValidCount) - << " skipped=" << static_cast(dut.io_commitSkippedSlot) - << " duplicate=" << static_cast(dut.io_commitDuplicateIdentity) - << " slot_mismatch=" << static_cast(dut.io_commitSlotMismatch) - << " invalid_side_effect=" << static_cast(dut.io_commitInvalidSideEffect) - << "\n"; - std::exit(1); - } - if (dut.io_commitMonitorValidMask != expected_mask || - dut.io_commitMonitorValidCount != expected_count) { - std::cerr << "commit monitor shape mismatch during " << context - << " expected_mask=" << static_cast(expected_mask) - << " observed_mask=" << static_cast(dut.io_commitMonitorValidMask) - << " expected_count=" << static_cast(expected_count) - << " observed_count=" << static_cast(dut.io_commitMonitorValidCount) - << "\n"; - std::exit(1); - } -} - -ObservedRow read_slot0(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_0_valid; - row.seq = dut.io_commit_rows_0_seq; - row.cycle = dut.io_commit_rows_0_cycle; - row.slot = dut.io_commit_rows_0_slot; - row.bid = dut.io_commit_rows_0_identity_bid; - row.gid = dut.io_commit_rows_0_identity_gid; - row.rid = dut.io_commit_rows_0_identity_rid; - row.rob_valid = dut.io_commit_rows_0_rob_valid; - row.rob_wrap = dut.io_commit_rows_0_rob_wrap; - row.rob_value = dut.io_commit_rows_0_rob_value; - row.block_bid_valid = dut.io_commit_rows_0_blockBidValid; - row.block_bid = dut.io_commit_rows_0_blockBid; - row.pc = dut.io_commit_rows_0_pc; - row.insn = dut.io_commit_rows_0_insn; - row.len = dut.io_commit_rows_0_len; - row.wb_valid = dut.io_commit_rows_0_wb_valid; - row.wb_reg = dut.io_commit_rows_0_wb_reg; - row.wb_data = dut.io_commit_rows_0_wb_data; - row.src0_valid = dut.io_commit_rows_0_src0_valid; - row.src0_reg = dut.io_commit_rows_0_src0_reg; - row.src0_data = dut.io_commit_rows_0_src0_data; - row.src1_valid = dut.io_commit_rows_0_src1_valid; - row.src1_reg = dut.io_commit_rows_0_src1_reg; - row.src1_data = dut.io_commit_rows_0_src1_data; - row.dst_valid = dut.io_commit_rows_0_dst_valid; - row.dst_reg = dut.io_commit_rows_0_dst_reg; - row.dst_data = dut.io_commit_rows_0_dst_data; - row.mem_valid = dut.io_commit_rows_0_mem_valid; - row.mem_is_store = dut.io_commit_rows_0_mem_isStore; - row.mem_addr = dut.io_commit_rows_0_mem_addr; - row.mem_wdata = dut.io_commit_rows_0_mem_wdata; - row.mem_rdata = dut.io_commit_rows_0_mem_rdata; - row.mem_size = dut.io_commit_rows_0_mem_size; - row.trap_valid = dut.io_commit_rows_0_trap_valid; - row.trap_cause = dut.io_commit_rows_0_trap_cause; - row.trap_arg0 = dut.io_commit_rows_0_trap_arg0; - row.next_pc = dut.io_commit_rows_0_nextPc; - row.rf_write_valid = dut.io_rfWriteValid; - row.rf_write_tag = dut.io_rfWriteTag; - row.rf_write_data = dut.io_rfWriteData; - row.src_phys_valid_mask = dut.io_executeCompleteSrcPhysValidMask; - row.src_phys_tag0 = dut.io_executeCompleteSrcPhysTag_0; - row.src_phys_tag1 = dut.io_executeCompleteSrcPhysTag_1; - row.src_phys_tag2 = dut.io_executeCompleteSrcPhysTag_2; - attach_issue_debug(row); - return row; -} - -bool slot1_valid(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - return dut.io_commit_rows_1_valid; -} - -ObservedRow read_slot1(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_1_valid; - row.seq = dut.io_commit_rows_1_seq; - row.cycle = dut.io_commit_rows_1_cycle; - row.slot = dut.io_commit_rows_1_slot; - row.bid = dut.io_commit_rows_1_identity_bid; - row.gid = dut.io_commit_rows_1_identity_gid; - row.rid = dut.io_commit_rows_1_identity_rid; - row.rob_valid = dut.io_commit_rows_1_rob_valid; - row.rob_wrap = dut.io_commit_rows_1_rob_wrap; - row.rob_value = dut.io_commit_rows_1_rob_value; - row.block_bid_valid = dut.io_commit_rows_1_blockBidValid; - row.block_bid = dut.io_commit_rows_1_blockBid; - row.pc = dut.io_commit_rows_1_pc; - row.insn = dut.io_commit_rows_1_insn; - row.len = dut.io_commit_rows_1_len; - row.wb_valid = dut.io_commit_rows_1_wb_valid; - row.wb_reg = dut.io_commit_rows_1_wb_reg; - row.wb_data = dut.io_commit_rows_1_wb_data; - row.src0_valid = dut.io_commit_rows_1_src0_valid; - row.src0_reg = dut.io_commit_rows_1_src0_reg; - row.src0_data = dut.io_commit_rows_1_src0_data; - row.src1_valid = dut.io_commit_rows_1_src1_valid; - row.src1_reg = dut.io_commit_rows_1_src1_reg; - row.src1_data = dut.io_commit_rows_1_src1_data; - row.dst_valid = dut.io_commit_rows_1_dst_valid; - row.dst_reg = dut.io_commit_rows_1_dst_reg; - row.dst_data = dut.io_commit_rows_1_dst_data; - row.mem_valid = dut.io_commit_rows_1_mem_valid; - row.mem_is_store = dut.io_commit_rows_1_mem_isStore; - row.mem_addr = dut.io_commit_rows_1_mem_addr; - row.mem_wdata = dut.io_commit_rows_1_mem_wdata; - row.mem_rdata = dut.io_commit_rows_1_mem_rdata; - row.mem_size = dut.io_commit_rows_1_mem_size; - row.trap_valid = dut.io_commit_rows_1_trap_valid; - row.trap_cause = dut.io_commit_rows_1_trap_cause; - row.trap_arg0 = dut.io_commit_rows_1_trap_arg0; - row.next_pc = dut.io_commit_rows_1_nextPc; - row.rf_write_valid = dut.io_rfWriteValid; - row.rf_write_tag = dut.io_rfWriteTag; - row.rf_write_data = dut.io_rfWriteData; - row.src_phys_valid_mask = dut.io_executeCompleteSrcPhysValidMask; - row.src_phys_tag0 = dut.io_executeCompleteSrcPhysTag_0; - row.src_phys_tag1 = dut.io_executeCompleteSrcPhysTag_1; - row.src_phys_tag2 = dut.io_executeCompleteSrcPhysTag_2; - attach_issue_debug(row); - return row; -} - -void collect_commit_if_present( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - std::vector &pending, - const char *context) { - if (dut.io_executeUnsupported) { - std::cerr << context << " execute reported unsupported opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid && dut.io_completeIgnored) { - std::cerr << context << " execute completion was ignored" - << " rob=" << static_cast(dut.io_executeCompleteRobValue) - << "\n"; - std::exit(1); - } - if (!dut.io_commit_rows_0_valid) { - return; - } - const ObservedRow slot0 = read_slot0(dut); - const bool slot1 = slot1_valid(dut); - expect_monitor_clean(dut, context, slot1 ? 0x3 : 0x1, slot1 ? 2 : 1); - pending.push_back(slot0); - if (slot1) { - pending.push_back(read_slot1(dut)); - } -} - -void expect_row( - const ObservedRow &observed, - const ExpectedRow &expected, - const VLinxCoreFrontendFetchRfAluTraceTop *dut = nullptr) { - if (!observed.valid || - observed.slot > 1 || - observed.pc != expected.pc || - mask_insn(observed.insn, observed.len) != mask_insn(expected.insn, expected.len) || - observed.len != expected.len || - observed.mem_valid != expected.mem_valid || - observed.mem_is_store != expected.mem_is_store || - observed.trap_valid || - observed.src0_valid != expected.src0_valid || - observed.src1_valid != expected.src1_valid || - observed.dst_valid != expected.dst_valid || - observed.wb_valid != expected.dst_valid || - observed.next_pc != expected.next_pc) { - std::cerr << "frontend fetch RF ALU trace top commit row mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << observed.insn - << std::dec << " len=" << static_cast(observed.len) - << " wb_valid=" << observed.wb_valid - << " src0=(" << observed.src0_valid << "," - << static_cast(observed.src0_reg) << ")" - << " src1=(" << observed.src1_valid << "," - << static_cast(observed.src1_reg) << ")" - << " dst=(" << observed.dst_valid << "," - << static_cast(observed.dst_reg) << ")" - << " mem=(" << observed.mem_valid << "," - << observed.mem_is_store << ")" - << " next_pc=0x" << std::hex << observed.next_pc << std::dec - << " seq=" << observed.seq - << " cycle=" << observed.cycle - << " slot=" << static_cast(observed.slot) - << " rob=(" << observed.rob_valid - << "," << observed.rob_wrap - << "," << static_cast(observed.rob_value) << ")" - << "\n"; - if (dut != nullptr) { - std::cerr << "frontend fetch RF ALU commit debug" - << " commit_mask=0x" << std::hex << static_cast(dut->io_commitValidMask) - << " dealloc_mask=0x" << static_cast(dut->io_deallocValidMask) - << " occupied=0x" << hex_port(dut->io_occupiedMask) - << " completed=0x" << hex_port(dut->io_completedMask) - << " retired=0x" << hex_port(dut->io_retiredMask) - << std::dec - << " commit_count=" << static_cast(dut->io_commitCount) - << " dealloc_count=" << static_cast(dut->io_deallocCount) - << " commit_head_valid=" << static_cast(dut->io_commitHeadValid) - << " commit_head_status=" << static_cast(dut->io_commitHeadStatus) - << " commit_head_rob=" << static_cast(dut->io_commitHeadRobValue) - << " size=" << static_cast(dut->io_size) - << " outstanding=" << static_cast(dut->io_outstandingCount) - << " dec_ren_count=" << static_cast(dut->io_decRenCount) - << " dec_ren_valid=" << static_cast(dut->io_decRenValid) - << " dec_ren_head_pc=0x" << std::hex - << static_cast(dut->io_decRenHeadPc) - << std::dec - << " renamed_accepted=" << static_cast(dut->io_renamedAccepted) - << " rename_update_attempt=" << static_cast(dut->io_robRenameUpdateAttemptValid) - << " rename_update_fire=" << static_cast(dut->io_robRenameUpdateFire) - << " complete_accepted=" << static_cast(dut->io_completeAccepted) - << " execute_accepted=" << static_cast(dut->io_executeAccepted) - << " dense_count=" << static_cast(dut->io_denseSlotQueueCount) - << " marker_barrier=" << static_cast(dut->io_admittedMarkerDrainBarrier) - << "\n"; - } - if (!g_replay_liq_sideband_stats_path.empty()) { - write_replay_liq_sideband_stats(g_replay_liq_sideband_stats_path); - } - std::exit(1); - } - - if (observed.src0_valid && - (observed.src0_reg != expected.src0_reg || observed.src0_data != expected.src0_data)) { - std::cerr << "frontend fetch RF ALU trace top src0 mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << mask_insn(observed.insn, observed.len) - << std::dec - << " expected=(" << static_cast(expected.src0_reg) - << "," << expected.src0_data << ") observed=(" - << static_cast(observed.src0_reg) - << "," << observed.src0_data << ")" - << " src_phys_mask=0x" << std::hex << static_cast(observed.src_phys_valid_mask) - << std::dec - << " src_phys=(" << static_cast(observed.src_phys_tag0) - << "," << static_cast(observed.src_phys_tag1) - << "," << static_cast(observed.src_phys_tag2) << ")" - << " rf_write=(" << std::dec << observed.rf_write_valid - << "," << static_cast(observed.rf_write_tag) - << "," << observed.rf_write_data << ")\n"; - dump_phys_writer_line("src0 last writer", observed.src_phys_tag0); - dump_arch_writer_line("src0 arch last writer", expected.src0_reg); - dump_gpr_commit_history_line("src0 mismatch history"); - std::exit(1); - } - if (observed.src1_valid && - (observed.src1_reg != expected.src1_reg || observed.src1_data != expected.src1_data)) { - std::cerr << "frontend fetch RF ALU trace top src1 mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << mask_insn(observed.insn, observed.len) - << std::dec - << " expected=(" << static_cast(expected.src1_reg) - << "," << expected.src1_data << ") observed=(" - << static_cast(observed.src1_reg) - << "," << observed.src1_data << ")" - << " src_phys_mask=0x" << std::hex << static_cast(observed.src_phys_valid_mask) - << std::dec - << " src_phys=(" << static_cast(observed.src_phys_tag0) - << "," << static_cast(observed.src_phys_tag1) - << "," << static_cast(observed.src_phys_tag2) << ")" - << " rf_write=(" << std::dec << observed.rf_write_valid - << "," << static_cast(observed.rf_write_tag) - << "," << observed.rf_write_data << ")\n"; - dump_phys_writer_line("src1 last writer", observed.src_phys_tag1); - dump_arch_writer_line("src1 arch last writer", expected.src1_reg); - dump_gpr_commit_history_line("src1 mismatch history"); - std::exit(1); - } - if (observed.dst_valid && - (observed.dst_reg != expected.dst_reg || observed.dst_data != expected.dst_data || - observed.wb_reg != expected.dst_reg || observed.wb_data != expected.dst_data)) { - std::cerr << "frontend fetch RF ALU trace top dst/wb mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << mask_insn(observed.insn, observed.len) - << std::dec - << " expected=(" << static_cast(expected.dst_reg) - << "," << expected.dst_data << ") observed_dst=(" - << static_cast(observed.dst_reg) - << "," << observed.dst_data << ") observed_wb=(" - << static_cast(observed.wb_reg) - << "," << observed.wb_data << ")\n"; - std::exit(1); - } - if (observed.mem_valid && - (observed.mem_addr != expected.mem_addr || - observed.mem_wdata != expected.mem_wdata || - observed.mem_rdata != expected.mem_rdata || - observed.mem_size != expected.mem_size)) { - std::cerr << "frontend fetch RF ALU trace top mem mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << mask_insn(observed.insn, observed.len) - << " expected=(addr=0x" << std::hex << expected.mem_addr - << ",wdata=0x" << expected.mem_wdata - << ",rdata=0x" << expected.mem_rdata - << std::dec << ",size=" << static_cast(expected.mem_size) - << ") observed=(addr=0x" << std::hex << observed.mem_addr - << ",wdata=0x" << observed.mem_wdata - << ",rdata=0x" << observed.mem_rdata - << std::dec << ",size=" << static_cast(observed.mem_size) - << ")" - << " src_phys_mask=0x" << std::hex << static_cast(observed.src_phys_valid_mask) - << std::dec - << " src_phys=(" << static_cast(observed.src_phys_tag0) - << "," << static_cast(observed.src_phys_tag1) - << "," << static_cast(observed.src_phys_tag2) << ")" - << " visible_src0=(" << static_cast(observed.src0_reg) - << "," << observed.src0_data << ")" - << " visible_src1=(" << static_cast(observed.src1_reg) - << "," << observed.src1_data << ")\n"; - dump_phys_writer_line("mem src0 last writer", observed.src_phys_tag0); - dump_phys_writer_line("mem src1 last writer", observed.src_phys_tag1); - dump_phys_writer_line("mem src2 last writer", observed.src_phys_tag2); - if (is_fentry_insn(observed.insn)) { - dump_arch_writer_line("fentry save-source arch last writer", fentry_begin_reg(observed.insn)); - } - std::exit(1); - } -} - -CommitTraceJsonRow to_json_row(const ObservedRow &row) { - CommitTraceJsonRow json; - json.valid = row.valid; - json.seq = row.seq; - json.cycle = row.cycle; - json.slot = row.slot; - json.bid = row.bid; - json.gid = row.gid; - json.rid = row.rid; - json.rob_valid = row.rob_valid; - json.rob_wrap = row.rob_wrap; - json.rob_value = row.rob_value; - json.block_bid_valid = row.block_bid_valid; - json.block_bid = row.block_bid; - json.pc = row.pc; - json.insn = row.insn; - json.len = row.len; - json.wb_valid = row.wb_valid; - json.wb_rd = row.wb_reg; - json.wb_data = row.wb_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.mem_valid = row.mem_valid; - json.mem_is_store = row.mem_is_store; - json.mem_addr = row.mem_addr; - json.mem_wdata = row.mem_wdata; - json.mem_rdata = row.mem_rdata; - json.mem_size = row.mem_size; - json.trap_valid = row.trap_valid; - json.trap_cause = row.trap_cause; - json.trap_arg0 = row.trap_arg0; - json.next_pc = row.next_pc; - return json; -} - -CommitTraceJsonRow to_json_row(const ExpectedRow &row) { - CommitTraceJsonRow json; - json.pc = row.pc; - json.insn = mask_insn(row.insn, row.len); - json.len = row.len; - json.wb_valid = row.dst_valid; - json.wb_rd = row.dst_reg; - json.wb_data = row.dst_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.mem_valid = row.mem_valid; - json.mem_is_store = row.mem_is_store; - json.mem_addr = row.mem_addr; - json.mem_wdata = row.mem_wdata; - json.mem_rdata = row.mem_rdata; - json.mem_size = row.mem_size; - json.next_pc = row.next_pc; - return json; -} - -void write_dut_row(std::ofstream &out, const ObservedRow &row) { - write_dut_commit_jsonl(out, to_json_row(row)); - out.flush(); -} - -void write_qemu_row(std::ofstream &out, const ExpectedRow &row) { - write_qemu_commit_jsonl(out, to_json_row(row)); - out.flush(); -} - -void start_source(VLinxCoreFrontendFetchRfAluTraceTop &dut, std::uint64_t pc) { - clear_inputs(dut); - dut.io_startValid = 1; - dut.io_startPc = pc; - tick(dut); - clear_inputs(dut); - dut.eval(); - if (!dut.io_sourceActive) { - std::cerr << "frontend fetch RF ALU source did not arm at start pc=0x" - << std::hex << pc << std::dec << "\n"; - std::exit(1); - } -} - -std::size_t dense_window_end(const std::vector &rows, std::size_t start) { - const std::uint64_t start_pc = rows.at(start).pc; - std::uint64_t next_pc = start_pc; - std::size_t end = start; - while (end < rows.size()) { - const ExpectedRow &row = rows[end]; - if (row.pc != next_pc) { - break; - } - if ((row.pc + row.len) - start_pc > 8U) { - break; - } - next_pc = row.next_pc; - ++end; - if (row.next_pc != row.pc + row.len) { - break; - } - } - if (end == start) { - std::cerr << "dense window grouping could not fit first row" - << " pc=0x" << std::hex << start_pc << std::dec - << " len=" << static_cast(rows[start].len) << "\n"; - std::exit(1); - } - return end; -} - -std::uint8_t dense_window_mask(std::size_t count) { - if (count == 0 || count > 4) { - std::cerr << "unsupported dense window slot count=" << count << "\n"; - std::exit(1); - } - return static_cast((1U << count) - 1U); -} - -std::uint8_t dense_window_advance(const std::vector &rows, std::size_t start, std::size_t end) { - const std::uint64_t start_pc = rows.at(start).pc; - const ExpectedRow &last = rows.at(end - 1); - const std::uint64_t advance = (last.pc + last.len) - start_pc; - if (advance == 0 || advance > 8) { - std::cerr << "unsupported dense window advance=" << advance << "\n"; - std::exit(1); - } - return static_cast(advance); -} - -bool row_redirects(const ExpectedRow &row) { - return row.next_pc != row.pc + row.len; -} - -bool is_marker_row_shape(const ObservedRow &observed, const ExpectedRow &expected) { - return observed.valid && - observed.pc == expected.pc && - mask_insn(observed.insn, observed.len) == mask_insn(expected.insn, expected.len) && - observed.len == expected.len && - !observed.mem_valid && - !observed.trap_valid && - !observed.src0_valid && - !observed.src1_valid && - !observed.dst_valid && - !observed.wb_valid; -} - -bool is_observed_marker_commit(const ObservedRow &observed) { - return observed.valid && - !observed.mem_valid && - !observed.trap_valid && - !observed.src0_valid && - !observed.src1_valid && - !observed.dst_valid && - !observed.wb_valid; -} - -void expect_marker_commit(const ObservedRow &observed, const ExpectedRow &expected) { - if (!is_marker_row_shape(observed, expected)) { - std::cerr << "frontend fetch RF ALU marker commit mismatch" - << " expected_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << observed.pc - << " expected_insn=0x" << mask_insn(expected.insn, expected.len) - << " observed_insn=0x" << mask_insn(observed.insn, observed.len) - << std::dec - << " expected_len=" << static_cast(expected.len) - << " observed_len=" << static_cast(observed.len) - << " mem=" << observed.mem_valid - << " trap=" << observed.trap_valid - << " src0=" << observed.src0_valid - << " src1=" << observed.src1_valid - << " dst=" << observed.dst_valid - << " wb=" << observed.wb_valid - << "\n"; - std::exit(1); - } -} - -void filter_pending_marker_commits( - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count); - -struct BfuBodyGeometryHint { - bool valid = false; - std::uint64_t header_pc = 0; - std::uint64_t hsize_bytes = 0; - std::uint64_t bsize_bytes = 0; -}; - -struct BfuGeometryDiagnostics { - std::uint64_t comparable_count = 0; - std::uint64_t match_count = 0; - std::uint64_t resolved_accept_count = 0; - std::uint64_t cut_arm_comparable_count = 0; - std::uint64_t cut_arm_accept_count = 0; - std::uint64_t cut_arm_mismatch_count = 0; - std::uint64_t local_body_cut_prefix_count = 0; - std::uint64_t resolved_source_runtime_selected_count = 0; - std::uint64_t resolved_source_replay_selected_count = 0; - std::uint64_t resolved_source_runtime_feedback_count = 0; - std::uint64_t resolved_source_runtime_pending_count = 0; - std::uint64_t resolved_source_runtime_pending_consume_count = 0; - std::uint64_t resolved_source_runtime_pending_drop_mismatch_count = 0; - std::uint64_t resolved_source_runtime_pending_candidate_comparable_count = 0; - std::uint64_t resolved_source_runtime_pending_candidate_match_count = 0; - std::uint64_t resolved_source_runtime_pending_candidate_mismatch_count = 0; - std::uint64_t pending_runtime_candidate_valid_count = 0; - std::uint64_t pending_runtime_candidate_without_active_header_count = 0; - std::uint64_t pending_runtime_candidate_active_header_mismatch_count = 0; - std::uint64_t pending_runtime_candidate_replay_comparable_count = 0; - std::uint64_t pending_runtime_candidate_replay_match_count = 0; - std::uint64_t pending_runtime_candidate_replay_mismatch_count = 0; - std::uint64_t runtime_body_end_oracle_pending_count = 0; - std::uint64_t runtime_body_end_oracle_capture_count = 0; - std::uint64_t runtime_body_end_oracle_replay_comparable_count = 0; - std::uint64_t runtime_body_end_oracle_replay_match_count = 0; - std::uint64_t runtime_body_end_oracle_replay_mismatch_count = 0; - std::uint64_t runtime_body_end_oracle_overwrite_count = 0; - std::uint64_t resolved_source_runtime_replay_comparable_count = 0; - std::uint64_t resolved_source_runtime_replay_match_count = 0; - std::uint64_t resolved_source_runtime_replay_mismatch_count = 0; -}; - -struct FetchDenseWindowResult { - bool captured_tail_superset = false; - bool local_body_cut_prefix = false; - std::size_t captured_slots = 0; -}; - -void observe_bfu_geometry_diagnostics( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - BfuGeometryDiagnostics &stats, - const char *context) { - if (dut.io_bfuStaticExternalMismatch || - dut.io_bfuStaticExternalHeaderMismatch || - dut.io_bfuStaticExternalHSizeMismatch || - dut.io_bfuStaticExternalBSizeMismatch) { - std::cerr << "frontend fetch RF ALU BFU static/external geometry mismatch during " - << context - << " comparable=" << static_cast(dut.io_bfuStaticExternalComparable) - << " match=" << static_cast(dut.io_bfuStaticExternalMatch) - << " headerMismatch=" << static_cast(dut.io_bfuStaticExternalHeaderMismatch) - << " hsizeMismatch=" << static_cast(dut.io_bfuStaticExternalHSizeMismatch) - << " bsizeMismatch=" << static_cast(dut.io_bfuStaticExternalBSizeMismatch) - << "\n"; - std::exit(1); - } - if (dut.io_bfuResolvedBodyEndHeaderMismatch || - dut.io_bfuResolvedBodyEndInactiveDrop || - dut.io_bfuResolvedBodyEndFlushDrop || - dut.io_bfuResolvedBodyEndUnderflow) { - std::cerr << "frontend fetch RF ALU BFU resolved body-end owner rejected replay geometry during " - << context - << " accepted=" << static_cast(dut.io_bfuResolvedBodyEndAccepted) - << " headerMismatch=" << static_cast(dut.io_bfuResolvedBodyEndHeaderMismatch) - << " inactiveDrop=" << static_cast(dut.io_bfuResolvedBodyEndInactiveDrop) - << " flushDrop=" << static_cast(dut.io_bfuResolvedBodyEndFlushDrop) - << " underflow=" << static_cast(dut.io_bfuResolvedBodyEndUnderflow) - << "\n"; - std::exit(1); - } - if (dut.io_bfuResolvedBodyEndAccepted) { - ++stats.resolved_accept_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimeSelected) { - ++stats.resolved_source_runtime_selected_count; - } - if (dut.io_bfuResolvedBodyEndSourceReplaySelected) { - ++stats.resolved_source_replay_selected_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimeFeedbackFire) { - ++stats.resolved_source_runtime_feedback_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePending) { - ++stats.resolved_source_runtime_pending_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePendingConsumeFire) { - ++stats.resolved_source_runtime_pending_consume_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePendingDropMismatch) { - ++stats.resolved_source_runtime_pending_drop_mismatch_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePendingCandidateComparable) { - ++stats.resolved_source_runtime_pending_candidate_comparable_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePendingCandidateMatch) { - ++stats.resolved_source_runtime_pending_candidate_match_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimePendingCandidateMismatch) { - ++stats.resolved_source_runtime_pending_candidate_mismatch_count; - } - if (dut.io_bfuPendingRuntimeCandidateValid) { - ++stats.pending_runtime_candidate_valid_count; - } - if (dut.io_bfuPendingRuntimeCandidatePendingWithoutActiveHeader) { - ++stats.pending_runtime_candidate_without_active_header_count; - } - if (dut.io_bfuPendingRuntimeCandidateActiveHeaderMismatch) { - ++stats.pending_runtime_candidate_active_header_mismatch_count; - } - if (dut.io_bfuPendingRuntimeCandidateReplayComparable) { - ++stats.pending_runtime_candidate_replay_comparable_count; - if (dut.io_bfuPendingRuntimeCandidateReplayMismatch) { - ++stats.pending_runtime_candidate_replay_mismatch_count; - std::cerr << "frontend fetch RF ALU pending runtime candidate mismatched replay during " - << context << "\n"; - std::exit(1); - } - if (dut.io_bfuPendingRuntimeCandidateReplayMatch) { - ++stats.pending_runtime_candidate_replay_match_count; - } - } - if (dut.io_bfuRuntimeBodyEndOraclePending) { - ++stats.runtime_body_end_oracle_pending_count; - } - if (dut.io_bfuRuntimeBodyEndOracleCaptureFire) { - ++stats.runtime_body_end_oracle_capture_count; - } - if (dut.io_bfuRuntimeBodyEndOracleOverwritePending) { - ++stats.runtime_body_end_oracle_overwrite_count; - std::cerr << "frontend fetch RF ALU promoted runtime body-end oracle was overwritten before replay during " - << context << "\n"; - std::exit(1); - } - if (dut.io_bfuRuntimeBodyEndOracleReplayComparable) { - ++stats.runtime_body_end_oracle_replay_comparable_count; - if (dut.io_bfuRuntimeBodyEndOracleReplayMismatch) { - ++stats.runtime_body_end_oracle_replay_mismatch_count; - std::cerr << "frontend fetch RF ALU promoted runtime body-end oracle mismatched replay during " - << context << "\n"; - std::exit(1); - } - if (dut.io_bfuRuntimeBodyEndOracleReplayMatch) { - ++stats.runtime_body_end_oracle_replay_match_count; - } - } - if (dut.io_bfuResolvedBodyEndSourceRuntimeReplayComparable) { - ++stats.resolved_source_runtime_replay_comparable_count; - if (dut.io_bfuResolvedBodyEndSourceRuntimeReplayMismatch) { - ++stats.resolved_source_runtime_replay_mismatch_count; - } - if (dut.io_bfuResolvedBodyEndSourceRuntimeReplayMatch) { - ++stats.resolved_source_runtime_replay_match_count; - } - } - if (dut.io_bfuBodyCutArmComparable) { - ++stats.cut_arm_comparable_count; - if (dut.io_bfuBodyCutArmMismatch || - dut.io_bfuBodyCutArmHeaderMismatch || - dut.io_bfuBodyCutArmHSizeMismatch || - dut.io_bfuBodyCutArmBSizeMismatch) { - ++stats.cut_arm_mismatch_count; - } - } - if (dut.io_bfuBodyCutArmAccepted) { - ++stats.cut_arm_accept_count; - } - if (dut.io_bfuStaticExternalComparable) { - ++stats.comparable_count; - if (!dut.io_bfuStaticExternalMatch) { - std::cerr << "frontend fetch RF ALU BFU geometry was comparable without a match during " - << context << "\n"; - std::exit(1); - } - ++stats.match_count; - } -} - -BfuBodyGeometryHint dense_window_bfu_body_geometry(const std::vector &rows, std::size_t start, std::size_t end) { - BfuBodyGeometryHint hint; - if (end <= start || end >= rows.size()) { - return hint; - } - const ExpectedRow &next = rows[end]; - if (!next.loop_reentry || next.loop_reentry_from_pc == 0) { - return hint; - } - const std::uint64_t cut_pc = rows[end - 1].pc + rows[end - 1].len; - if (next.loop_reentry_from_pc != cut_pc) { - std::cerr << "loop re-entry metadata does not match dense window cut" - << " start_pc=0x" << std::hex << rows[start].pc - << " expected_cut=0x" << cut_pc - << " row_cut=0x" << next.loop_reentry_from_pc - << " restart=0x" << next.pc << std::dec << "\n"; - std::exit(1); - } - const std::uint64_t header_pc = next.pc; - const std::uint64_t body_base_pc = header_pc + 2; - if (cut_pc < body_base_pc) { - std::cerr << "loop re-entry metadata cuts before reduced BFU body base" - << " header_pc=0x" << std::hex << header_pc - << " body_base=0x" << body_base_pc - << " cut=0x" << cut_pc << std::dec << "\n"; - std::exit(1); - } - hint.valid = true; - hint.header_pc = header_pc; - hint.hsize_bytes = 0; - hint.bsize_bytes = cut_pc - body_base_pc; - return hint; -} - -void drive_bfu_body_geometry_hint(VLinxCoreFrontendFetchRfAluTraceTop &dut, const BfuBodyGeometryHint &hint) { - if (!hint.valid) { - return; - } - dut.io_bfuBodyValid = 1; - dut.io_bfuHeaderPc = hint.header_pc; - dut.io_bfuHSizeBytes = hint.hsize_bytes; - dut.io_bfuBSizeBytes = hint.bsize_bytes; -} - -bool is_suppressed_local_body_cut_marker(const std::vector &rows, std::size_t index) { - if (index + 1 >= rows.size()) { - return false; - } - const ExpectedRow &row = rows[index]; - return row.skip && - row.block_boundary && - !row.block_stop && - row_redirects(row) && - row.next_pc < row.pc && - rows[index + 1].pc == row.next_pc; -} - -FetchDenseWindowResult fetch_dense_window( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - const std::vector &rows, - std::size_t start, - std::size_t end, - const FetchMemoryImage &fetch_memory, - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count, - BfuGeometryDiagnostics &bfu_stats) { - const ExpectedRow &first = rows.at(start); - const std::size_t slot_count = end - start; - const std::uint8_t expected_mask = dense_window_mask(slot_count); - const std::uint8_t expected_advance = dense_window_advance(rows, start, end); - const bool redirect_tail = row_redirects(rows.at(end - 1)); - const bool capture_tail = end == rows.size(); - const BfuBodyGeometryHint body_cut = dense_window_bfu_body_geometry(rows, start, end); - const std::uint64_t bfu_match_count_before = bfu_stats.match_count; - - for (int cycle = 0; cycle < 8; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - clear_inputs(dut); - dut.io_fetchReqReady = 1; - drive_bfu_body_geometry_hint(dut, body_cut); - eval_with_load_lookup(dut, fetch_memory); - observe_bfu_geometry_diagnostics(dut, bfu_stats, "fetch request"); - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU fetch"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (dut.io_fetchReqValid) { - if (dut.io_fetchReqPc != first.pc || !dut.io_sourceReqFire) { - std::cerr << "frontend fetch RF ALU request mismatch" - << " expected_pc=0x" << std::hex << first.pc - << " observed_pc=0x" << dut.io_fetchReqPc << std::dec - << " sourceReqFire=" << static_cast(dut.io_sourceReqFire) - << "\n"; - std::exit(1); - } - tick(dut); - goto request_done; - } - tick(dut); - } - std::cerr << "frontend fetch RF ALU source did not request pc=0x" - << std::hex << first.pc << std::dec << "\n"; - std::exit(1); - -request_done: - clear_inputs(dut); - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = fetch_memory.read_window(first.pc); - drive_bfu_body_geometry_hint(dut, body_cut); - eval_with_load_lookup(dut, fetch_memory); - observe_bfu_geometry_diagnostics(dut, bfu_stats, "fetch response"); - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU fetch response"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!dut.io_fetchRespReady || !dut.io_sourceRespFire) { - std::cerr << "frontend fetch RF ALU response was not accepted" - << " pc=0x" << std::hex << first.pc << std::dec - << " respReady=" << static_cast(dut.io_fetchRespReady) - << " sourceRespFire=" << static_cast(dut.io_sourceRespFire) - << "\n"; - std::exit(1); - } - tick(dut); - - for (int cycle = 0; cycle < 8; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - clear_inputs(dut); - drive_bfu_body_geometry_hint(dut, body_cut); - eval_with_load_lookup(dut, fetch_memory); - observe_bfu_geometry_diagnostics(dut, bfu_stats, "dense packet drain"); - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU dense drain"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (dut.io_rfStateError) { - std::cerr << "frontend fetch RF ALU reported RF state error before enqueue\n"; - std::exit(1); - } - if (dut.io_sourceOutFire) { - const bool strict_dense_match = - dut.io_f4ValidMask == expected_mask && - dut.io_f4SlotCount == slot_count && - dut.io_denseSlotQueueInSlotCount == slot_count && - dut.io_sourceAdvanceBytes == expected_advance; - const bool relaxed_prefix_match = - (redirect_tail || capture_tail) && - (dut.io_f4ValidMask & expected_mask) == expected_mask && - dut.io_f4SlotCount >= slot_count && - dut.io_denseSlotQueueInSlotCount >= slot_count && - dut.io_sourceAdvanceBytes >= expected_advance; - const std::size_t observed_slots = static_cast(dut.io_denseSlotQueueInSlotCount); - const bool observed_strict_prefix = observed_slots > 0 && observed_slots < slot_count; - const bool local_body_cut_prefix = - observed_strict_prefix && - dut.io_reducedBodyCutFire && - dut.io_f4SlotCount == observed_slots && - dut.io_f4ValidMask == dense_window_mask(observed_slots) && - dut.io_sourceAdvanceBytes == dense_window_advance(rows, start, start + observed_slots) && - dut.io_reducedBodyCutAdvanceBytes == dut.io_sourceAdvanceBytes; - if (!dut.io_denseSlotQueueInFire || (!strict_dense_match && !relaxed_prefix_match && !local_body_cut_prefix)) { - std::cerr << "frontend fetch RF ALU dense packet was not captured" - << " pc=0x" << std::hex << first.pc << std::dec - << " expected_mask=0x" << std::hex << static_cast(expected_mask) - << " observed_mask=0x" << static_cast(dut.io_f4ValidMask) - << std::dec - << " expected_slots=" << slot_count - << " observed_f4_slots=" << static_cast(dut.io_f4SlotCount) - << " observed_queue_slots=" << static_cast(dut.io_denseSlotQueueInSlotCount) - << " expected_advance=" << static_cast(expected_advance) - << " observed_advance=" << static_cast(dut.io_sourceAdvanceBytes) - << "\n"; - std::exit(1); - } - FetchDenseWindowResult result; - result.captured_tail_superset = capture_tail && observed_slots > slot_count; - result.local_body_cut_prefix = local_body_cut_prefix; - result.captured_slots = local_body_cut_prefix ? observed_slots : slot_count; - if (local_body_cut_prefix) { - ++bfu_stats.local_body_cut_prefix_count; - } - if (body_cut.valid && bfu_stats.match_count == bfu_match_count_before) { - std::cerr << "frontend fetch RF ALU BFU body-geometry hint did not produce a static/external match" - << " header_pc=0x" << std::hex << body_cut.header_pc - << " hsize=0x" << body_cut.hsize_bytes - << " bsize=0x" << body_cut.bsize_bytes - << std::dec << "\n"; - std::exit(1); - } - tick(dut); - return result; - } - tick(dut); - } - - std::cerr << "frontend fetch RF ALU packet source did not emit dense packet" - << " pc=0x" << std::hex << first.pc << std::dec << "\n"; - std::exit(1); -} - -struct DrainDenseRowResult { - std::uint8_t rob_value = 0; - bool marker_redirect = false; -}; - -DrainDenseRowResult drain_dense_row( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - const ExpectedRow &row, - bool &active_block_valid, - std::uint64_t &active_block_bid, - const FetchMemoryImage &fetch_memory, - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count, - const BfuGeometryDiagnostics &bfu_stats, - bool admit_marker_rows, - bool local_body_cut_reentry_header = false) { - for (int cycle = 0; cycle < kDenseRowDrainCycles; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - clear_inputs(dut); - eval_with_load_lookup(dut, fetch_memory); - if (dut.io_rfStateError) { - std::cerr << "frontend fetch RF ALU reported RF state error before dense slot drain\n"; - std::exit(1); - } - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU dense slot drain"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (dut.io_denseSlotQueueOutFire) { - if (!dut.io_decodeReady) { - std::cerr << "frontend fetch RF ALU dense slot drained while decode was not ready" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; - std::exit(1); - } - if (row.skip) { - if (admit_marker_rows) { - if (row.block_stop && !active_block_valid) { - std::cerr << "frontend fetch RF ALU admitted marker stop had no active block" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << "\n"; - std::exit(1); - } - if (!dut.io_selectedValid || - dut.io_blockMarkerSkipFire || - dut.io_blockMarkerMixedPacket || - !dut.io_decRenPushFire || - !dut.io_robAllocFire) { - std::cerr << "frontend fetch RF ALU admitted marker dense slot mismatch" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " skipFire=" << static_cast(dut.io_blockMarkerSkipFire) - << " mixed=" << static_cast(dut.io_blockMarkerMixedPacket) - << " decRenPush=" << static_cast(dut.io_decRenPushFire) - << " robAlloc=" << static_cast(dut.io_robAllocFire) - << "\n"; - std::exit(1); - } - if (row.block_stop && dut.io_selectedBlockBid != active_block_bid) { - std::cerr << "frontend fetch RF ALU admitted marker stop used wrong active block BID" - << " pc=0x" << std::hex << row.pc - << " expected_bid=0x" << active_block_bid - << " observed_bid=0x" << dut.io_selectedBlockBid - << std::dec << "\n"; - std::exit(1); - } - const auto rob_value = static_cast(dut.io_selectedRobValue); - const auto selected_block_bid = static_cast(dut.io_selectedBlockBid); - if (trace_top_debug_enabled()) { - std::cerr << "[trace-top-debug]" - << " cycle=" << g_tb_cycle - << " reserve_marker pc=0x" << std::hex << row.pc - << " insn=0x" << mask_insn(row.insn, row.len) - << std::dec - << " len=" << static_cast(row.len) - << " rob=" << static_cast(rob_value) - << " dense_head_slot=" << static_cast(dut.io_denseSlotQueueHeadSlot) - << " barrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << "\n"; - } - filtered_marker_commits.push_back(row); - tick(dut); - if (row.block_boundary) { - active_block_valid = true; - active_block_bid = selected_block_bid; - } else if (row.block_stop) { - active_block_valid = false; - active_block_bid = 0; - } - DrainDenseRowResult result; - result.rob_value = rob_value; - return result; - } - - const bool expected_alloc = row.block_boundary; - const bool redirect_boundary = row.block_boundary && row_redirects(row); - const bool expected_done = active_block_valid && (row.block_boundary || row.block_stop); - const bool expected_alloc_fire = - expected_alloc && !redirect_boundary && !local_body_cut_reentry_header; - if (row.block_stop && !active_block_valid) { - std::cerr << "frontend fetch RF ALU marker stop had no active block" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << "\n"; - std::exit(1); - } - if (dut.io_selectedValid || - !dut.io_blockMarkerSkipFire || - dut.io_blockMarkerMixedPacket || - dut.io_blockMarkerPc != row.pc || - mask_insn(dut.io_blockMarkerInsn, dut.io_blockMarkerLen) != mask_insn(row.insn, row.len) || - dut.io_blockMarkerLen != row.len || - static_cast(dut.io_blockMarkerBoundary) != row.block_boundary || - static_cast(dut.io_blockMarkerStop) != row.block_stop || - static_cast(dut.io_blockMarkerAllocFire) != expected_alloc_fire || - static_cast(dut.io_blockScalarDoneFire) != expected_done || - dut.io_decRenPushFire || - dut.io_robAllocFire) { - std::cerr << "frontend fetch RF ALU marker dense slot mismatch" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " skipFire=" << static_cast(dut.io_blockMarkerSkipFire) - << " mixed=" << static_cast(dut.io_blockMarkerMixedPacket) - << " boundary=" << static_cast(dut.io_blockMarkerBoundary) - << " stop=" << static_cast(dut.io_blockMarkerStop) - << " allocFire=" << static_cast(dut.io_blockMarkerAllocFire) - << " activeValid=" << static_cast(dut.io_blockMarkerActiveValid) - << " activeBid=0x" << std::hex << dut.io_blockMarkerActiveBid - << " activeTarget=0x" << dut.io_blockMarkerActiveTarget - << " markerTarget=0x" << dut.io_blockMarkerTarget - << std::dec - << " scalarDone=" << static_cast(dut.io_blockScalarDoneFire) - << " decRenPush=" << static_cast(dut.io_decRenPushFire) - << " robAlloc=" << static_cast(dut.io_robAllocFire) - << "\n"; - std::exit(1); - } - if (expected_done && dut.io_blockScalarDoneBid != active_block_bid) { - std::cerr << "frontend fetch RF ALU marker scalar-done BID mismatch" - << " pc=0x" << std::hex << row.pc - << " expected_bid=0x" << active_block_bid - << " observed_bid=0x" << dut.io_blockScalarDoneBid - << std::dec << "\n"; - std::exit(1); - } - DrainDenseRowResult result; - result.marker_redirect = dut.io_blockMarkerStopRedirectValid; - const std::uint64_t allocated_bid = dut.io_blockMarkerAllocBid; - tick(dut); - if (redirect_boundary || local_body_cut_reentry_header) { - active_block_valid = false; - active_block_bid = 0; - } else if (row.block_boundary) { - active_block_valid = true; - active_block_bid = allocated_bid; - } else if (row.block_stop) { - active_block_valid = false; - active_block_bid = 0; - } - return result; - } - - if (!dut.io_selectedValid || - dut.io_blockMarkerMixedPacket || - dut.io_blockMarkerSkipFire || - !dut.io_decRenPushFire || - !dut.io_robAllocFire) { - std::cerr << "frontend fetch RF ALU scalar dense slot mismatch" - << " pc=0x" << std::hex << row.pc << std::dec - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " mixed=" << static_cast(dut.io_blockMarkerMixedPacket) - << " skipFire=" << static_cast(dut.io_blockMarkerSkipFire) - << " decRenPush=" << static_cast(dut.io_decRenPushFire) - << " robAlloc=" << static_cast(dut.io_robAllocFire) - << "\n"; - std::exit(1); - } - if (active_block_valid && dut.io_selectedBlockBid != active_block_bid) { - active_block_bid = dut.io_selectedBlockBid; - } - const auto rob_value = static_cast(dut.io_selectedRobValue); - const auto selected_block_bid = static_cast(dut.io_selectedBlockBid); - if (trace_top_debug_enabled()) { - std::cerr << "[trace-top-debug]" - << " cycle=" << g_tb_cycle - << " reserve_scalar pc=0x" << std::hex << row.pc - << " insn=0x" << mask_insn(row.insn, row.len) - << std::dec - << " len=" << static_cast(row.len) - << " rob=" << static_cast(rob_value) - << " dense_head_slot=" << static_cast(dut.io_denseSlotQueueHeadSlot) - << " barrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << "\n"; - } - tick(dut); - if (row_redirects(row)) { - active_block_valid = false; - active_block_bid = 0; - } else if (!active_block_valid) { - active_block_valid = true; - active_block_bid = selected_block_bid; - } - DrainDenseRowResult result; - result.rob_value = rob_value; - return result; - } - tick(dut); - } - - std::cerr << "frontend fetch RF ALU dense slot queue did not drain row" - << " pc=0x" << std::hex << row.pc << std::dec - << " queueEmpty=" << static_cast(dut.io_denseSlotQueueEmpty) - << " queueCount=" << static_cast(dut.io_denseSlotQueueCount) - << " headSlot=" << static_cast(dut.io_denseSlotQueueHeadSlot) - << " decodeReady=" << static_cast(dut.io_decodeReady) - << " admittedBarrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << " decodeQueueReady=" << static_cast(dut.io_decodeQueuePushReady) - << " decodeAllocReady=" << static_cast(dut.io_decodeAllocReady) - << " decodeGprReady=" << static_cast(dut.io_decodeGprReservationReady) - << " decodeClosesRedirect=" << static_cast(dut.io_decodeSelectedClosesActiveRedirect) - << " decodeNeedsGpr=" << static_cast(dut.io_decodeSelectedNeedsGprReservation) - << " gprReservationCount=" << static_cast(dut.io_gprReservationCount) - << " gprReservationNeed=" << static_cast(dut.io_gprReservationNeed) - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " decRenCount=" << static_cast(dut.io_decRenCount) - << " decRenValid=" << static_cast(dut.io_decRenValid) - << " decRenHeadPc=0x" << std::hex - << static_cast(dut.io_decRenHeadPc) - << std::dec - << " decodeBlockedByRename=" << static_cast(dut.io_decodeBlockedByRename) - << " decodeBlockedByRob=" << static_cast(dut.io_decodeBlockedByRob) - << " decodeBlockedByOutput=" << static_cast(dut.io_decodeBlockedByOutput) - << " decodeBlockedByTURename=" << static_cast(dut.io_decodeBlockedByTURename) - << " gprFree=" << static_cast(dut.io_gprFreeCount) - << " gprMapQValid=" << static_cast(dut.io_gprMapQValidCount) - << " gprMapQFree=" << static_cast(dut.io_gprMapQFreeCount) - << " gprSmapLive=" << static_cast(dut.io_gprSmapLiveCount) - << " gprCmapLive=" << static_cast(dut.io_gprCmapLiveCount) - << " gprMapQLive=" << static_cast(dut.io_gprMapQLiveCount) - << " gprLivePhys=" << static_cast(dut.io_gprLivePhysCount) - << " gprFreeFromLive=" << static_cast(dut.io_gprFreeFromLiveCount) - << " gprFreeMismatch=" << static_cast(dut.io_gprFreeListMismatchCount) - << " gprNextMapQValid=" << static_cast(dut.io_gprNextMapQValidCount) - << " gprNextMapQLive=" << static_cast(dut.io_gprNextMapQLiveCount) - << " gprNextLivePhys=" << static_cast(dut.io_gprNextLivePhysCount) - << " gprNextFreeFromLive=" << static_cast(dut.io_gprNextFreeFromLiveCount) - << " markerSkipValid=" << static_cast(dut.io_blockMarkerSkipValid) - << " markerMixed=" << static_cast(dut.io_blockMarkerMixedPacket) - << " markerBoundary=" << static_cast(dut.io_blockMarkerBoundary) - << " markerStop=" << static_cast(dut.io_blockMarkerStop) - << " markerAllocReady=" << static_cast(dut.io_blockMarkerAllocReady) - << " markerAllocBid=0x" << std::hex - << static_cast(dut.io_blockMarkerAllocBid) - << std::dec - << " markerLifecycleConflict=" << static_cast(dut.io_blockMarkerLifecycleConflict) - << " markerActiveValid=" << static_cast(dut.io_blockMarkerActiveValid) - << " markerActiveBid=0x" << std::hex - << static_cast(dut.io_blockMarkerActiveBid) - << " markerActiveTarget=0x" - << static_cast(dut.io_blockMarkerActiveTarget) - << std::dec - << " blockScalarDoneFire=" << static_cast(dut.io_blockScalarDoneFire) - << " blockScalarDoneBid=0x" << std::hex - << static_cast(dut.io_blockScalarDoneBid) - << std::dec - << " blockRetireFire=" << static_cast(dut.io_blockRetireFire) - << " robDeallocBlockLastValid=" << static_cast(dut.io_robDeallocBlockLastValid) - << " robDeallocBlockLastBid=0x" << std::hex - << static_cast(dut.io_robDeallocBlockLastBlockBid) - << std::dec - << " gprCommitAccepted=" << static_cast(dut.io_gprCommitAccepted) - << " gprCommitBlockBid=0x" << std::hex - << static_cast(dut.io_gprCommitBlockBid) - << std::dec - << " gprCommittedMapQCount=" << static_cast(dut.io_gprCommittedMapQCount) - << " gprReleasedPhysCount=" << static_cast(dut.io_gprReleasedPhysCount) - << " histDeallocBlockLast=" << g_gpr_commit_history.dealloc_block_last_count - << " histScalarDone=" << g_gpr_commit_history.block_scalar_done_count - << " histBlockRetire=" << g_gpr_commit_history.block_retire_count - << " histGprCommit=" << g_gpr_commit_history.gpr_commit_count - << " histGprCommitHits=" << g_gpr_commit_history.gpr_commit_hit_total - << " histGprReleases=" << g_gpr_commit_history.gpr_release_total - << " lastBlockRetireBid=0x" << std::hex - << g_gpr_commit_history.last_block_retire_bid - << " lastGprCommitBid=0x" << g_gpr_commit_history.last_gpr_commit_bid - << std::dec - << " lastGprCommitHits=" << static_cast(g_gpr_commit_history.last_gpr_commit_hits) - << " lastGprReleases=" << static_cast(g_gpr_commit_history.last_gpr_releases) - << " lastNonzeroGprCommitBid=0x" << std::hex - << g_gpr_commit_history.last_nonzero_gpr_commit_bid - << std::dec - << " lastNonzeroGprCommitHits=" - << static_cast(g_gpr_commit_history.last_nonzero_gpr_commit_hits) - << " lastNonzeroGprReleases=" - << static_cast(g_gpr_commit_history.last_nonzero_gpr_releases) - << " bfuStaticComparable=" << bfu_stats.comparable_count - << " bfuStaticMatches=" << bfu_stats.match_count - << " bfuResolvedAccepts=" << bfu_stats.resolved_accept_count - << " bfuCutArmComparable=" << bfu_stats.cut_arm_comparable_count - << " bfuCutArmAccepts=" << bfu_stats.cut_arm_accept_count - << " bfuCutArmMismatches=" << bfu_stats.cut_arm_mismatch_count - << " bfuLocalBodyCutPrefixes=" << bfu_stats.local_body_cut_prefix_count - << " bfuRuntimeSelected=" << bfu_stats.resolved_source_runtime_selected_count - << " bfuReplaySelected=" << bfu_stats.resolved_source_replay_selected_count - << " bfuRuntimeFeedback=" << bfu_stats.resolved_source_runtime_feedback_count - << " bfuRuntimePending=" << bfu_stats.resolved_source_runtime_pending_count - << " bfuRuntimePendingConsumes=" << bfu_stats.resolved_source_runtime_pending_consume_count - << " bfuRuntimePendingCandidateComparable=" - << bfu_stats.resolved_source_runtime_pending_candidate_comparable_count - << " bfuRuntimePendingCandidateMatch=" - << bfu_stats.resolved_source_runtime_pending_candidate_match_count - << " bfuRuntimePendingCandidateMismatch=" - << bfu_stats.resolved_source_runtime_pending_candidate_mismatch_count - << " bfuPendingRuntimeCandidateValid=" << bfu_stats.pending_runtime_candidate_valid_count - << " bfuPendingRuntimeCandidateHeaderMismatch=" - << bfu_stats.pending_runtime_candidate_active_header_mismatch_count - << " bfuRuntimeBodyEndOracleCaptures=" - << bfu_stats.runtime_body_end_oracle_capture_count - << " bfuRuntimeBodyEndOracleReplayComparable=" - << bfu_stats.runtime_body_end_oracle_replay_comparable_count - << " bfuRuntimeBodyEndOracleReplayMatch=" - << bfu_stats.runtime_body_end_oracle_replay_match_count - << " bfuRuntimeReplayComparable=" - << bfu_stats.resolved_source_runtime_replay_comparable_count - << " bfuRuntimeReplayMatch=" - << bfu_stats.resolved_source_runtime_replay_match_count - << " bfuRuntimeReplayMismatch=" - << bfu_stats.resolved_source_runtime_replay_mismatch_count - << " issueCount=" << static_cast(dut.io_issueQueueCount) - << " executeBusy=" << static_cast(dut.io_executeBusy) - << " occupiedMask=0x" << std::hex - << hex_port(dut.io_occupiedMask) - << " completedMask=0x" - << hex_port(dut.io_completedMask) - << " blockAllocatedMask=0x" - << hex_port(dut.io_blockAllocatedMask) - << " blockCompleteMask=0x" - << hex_port(dut.io_blockCompleteMask) - << " blockPendingMask=0x" - << hex_port(dut.io_blockPendingMask) - << std::dec << "\n"; - std::exit(1); -} - -void drain_empty(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemoryImage &fetch_memory) { - for (int cycle = 0; cycle < 16; ++cycle) { - clear_inputs(dut); - eval_with_load_lookup(dut, fetch_memory); - if (dut.io_idle && dut.io_empty && dut.io_size == 0 && !dut.io_executeBusy) { - return; - } - tick(dut); - } - std::cerr << "frontend fetch RF ALU trace top did not drain after commit" - << " idle=" << static_cast(dut.io_idle) - << " size=" << static_cast(dut.io_size) - << " outstanding=" << static_cast(dut.io_outstandingCount) - << " executeBusy=" << static_cast(dut.io_executeBusy) - << " sourceWaiting=" << static_cast(dut.io_sourceWaitingResponse) - << " sourcePacket=" << static_cast(dut.io_sourcePacketValid) - << " storeCommitPendingMarkMask=0x" << std::hex - << static_cast(dut.io_reducedStoreCommitPendingMarkMask) - << " storeCommitPendingFreeMask=0x" - << static_cast(dut.io_reducedStoreCommitPendingFreeMask) - << " storeCommitMarkValid=" << std::dec - << static_cast(dut.io_reducedStoreCommitMarkValid) - << " storeCommitMarkAccepted=" - << static_cast(dut.io_reducedStoreCommitMarkAccepted) - << " storeCommitMarkBlocked=" - << static_cast(dut.io_reducedStoreCommitMarkBlocked) - << " storeCommitPendingMarkCount=" - << static_cast(dut.io_reducedStoreCommitPendingMarkCount) - << " storeDrainEmpty=" - << static_cast(dut.io_reducedStoreDrainEmpty) - << " storeDrainQueueCount=" - << static_cast(dut.io_reducedStoreDrainQueueCount) - << " storeDrainIssueMask=0x" << std::hex - << static_cast(dut.io_reducedStoreDrainIssueValidMask) - << " storeStqCommitMask=0x" - << hex_port(dut.io_storeStqCommitMask) - << " storeStqOccupiedMask=0x" - << hex_port(dut.io_storeStqOccupiedMask) - << " replayLiqEmpty=" << std::dec - << static_cast(dut.io_reducedLoadReplayLiqEmpty) - << " replayLiqResidentCount=" - << static_cast(dut.io_reducedLoadReplayLiqResidentCount) - << " replayResolveQueueEmpty=" - << static_cast(dut.io_reducedLoadReplayResolveQueueEmpty) - << " replayResolveQueueCount=" - << static_cast(dut.io_reducedLoadReplayResolveQueueCount) - << " replayResolveQueueValidMask=0x" << std::hex - << static_cast(dut.io_reducedLoadReplayResolveQueueValidMask) - << " replayLiqHeadValid=" << std::dec - << static_cast(dut.io_reducedLoadReplayLiqHeadValid) - << " replayLiqHeadIndex=" - << static_cast(dut.io_reducedLoadReplayLiqHeadIndex) - << " replayLiqHeadStatus=" - << static_cast(dut.io_reducedLoadReplayLiqHeadStatus) - << " replayLiqHeadLoadId=" - << static_cast(dut.io_reducedLoadReplayLiqHeadLoadIdValid) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadLoadIdWrap) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadLoadIdValue) - << " replayLiqHeadBid=" - << static_cast(dut.io_reducedLoadReplayLiqHeadBidValid) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadBidWrap) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadBidValue) - << " replayLiqHeadGid=" - << static_cast(dut.io_reducedLoadReplayLiqHeadGidValid) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadGidWrap) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadGidValue) - << " replayLiqHeadRid=" - << static_cast(dut.io_reducedLoadReplayLiqHeadRidValid) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadRidWrap) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadRidValue) - << " replayLiqHeadLoadLsId=" - << static_cast(dut.io_reducedLoadReplayLiqHeadLoadLsIdValid) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadLoadLsIdWrap) - << "/" << static_cast(dut.io_reducedLoadReplayLiqHeadLoadLsIdValue) - << " replayLiqHeadPc=0x" << std::hex - << hex_port(dut.io_reducedLoadReplayLiqHeadPc) - << " replayLiqHeadAddr=0x" - << hex_port(dut.io_reducedLoadReplayLiqHeadAddr) - << " replayLiqHeadSize=" << std::dec - << static_cast(dut.io_reducedLoadReplayLiqHeadSize) - << " replayLiqHeadWaitStore=" - << static_cast(dut.io_reducedLoadReplayLiqHeadWaitStore) - << " replayLiqHeadStoreBypass=" - << static_cast(dut.io_reducedLoadReplayLiqHeadStoreBypass) - << " replayLiqHeadDataComplete=" - << static_cast(dut.io_reducedLoadReplayLiqHeadDataComplete) - << " replayLiqHeadSourcesReturned=" - << static_cast(dut.io_reducedLoadReplayLiqHeadSourcesReturned) - << " replayLiqHeadScbReturned=" - << static_cast(dut.io_reducedLoadReplayLiqHeadScbReturned) - << " replayLiqHeadStqReturned=" - << static_cast(dut.io_reducedLoadReplayLiqHeadStqReturned) - << " replayLiqLaunchWaitMask=0x" << std::hex - << static_cast(dut.io_reducedLoadReplayLiqLaunchWaitMask) - << " replayLiqLaunchUnblockedWaitMask=0x" - << static_cast(dut.io_reducedLoadReplayLiqLaunchUnblockedWaitMask) - << " replayLiqLaunchRequestCompleteMask=0x" - << static_cast(dut.io_reducedLoadReplayLiqLaunchRequestCompleteMask) - << " replayLiqLaunchDataHitMask=0x" - << static_cast(dut.io_reducedLoadReplayLiqLaunchDataHitMask) - << " replayLiqLaunchCandidateMask=0x" - << static_cast(dut.io_reducedLoadReplayLiqLaunchCandidateMask) - << " replayLiqLaunchMask=0x" - << static_cast(dut.io_reducedLoadReplayLiqLaunchMask) - << " replayLiqLaunchValid=" << std::dec - << static_cast(dut.io_reducedLoadReplayLiqLaunchValid) - << " replayLiqLaunchIndex=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchIndex) - << " replayLiqLaunchDriveValid=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchDriveValid) - << " replayLiqLaunchReady=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReady) - << " replayLiqLaunchAccepted=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchAccepted) - << " replayLiqLaunchCandidateCount=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchCandidateCount) - << " replayLiqLaunchReadinessCandidateValid=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessCandidateValid) - << " replayLiqLaunchReadinessBaseDataReady=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBaseDataReady) - << " replayLiqLaunchReadinessSourcesReturned=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessSourcesReturned) - << " replayLiqLaunchReadinessReady=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessReady) - << " replayLiqLaunchReadinessEnable=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessEnable) - << " replayLiqLaunchReadinessBlockedByDisabled=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByDisabled) - << " replayLiqLaunchReadinessBlockedByNoCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate) - << " replayLiqLaunchReadinessBlockedByBaseLookup=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup) - << " replayLiqLaunchReadinessBlockedByBaseData=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseData) - << " replayLiqLaunchReadinessBlockedByScb=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByScb) - << " replayLiqLaunchReadinessBlockedByReturn=" - << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByReturn) - << " replayLiqBaseLookupValid=" - << static_cast(dut.io_reducedLoadReplayLiqBaseLookupValid) - << " replayLiqBaseLookupGranted=" - << static_cast(dut.io_reducedLoadReplayLiqBaseLookupGranted) - << " replayLiqBaseDataReturned=" - << static_cast(dut.io_reducedLoadReplayLiqBaseDataReturned) - << " replayLiqBaseLineValidMask=0x" << std::hex - << hex_port(dut.io_reducedLoadReplayLiqBaseLineValidMask) - << " replayLiqBaseLookupBlockedByExecute=" << std::dec - << static_cast(dut.io_reducedLoadReplayLiqBaseLookupBlockedByExecute) - << " replayLiqSourceReturnCandidateValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnCandidateValid) - << " replayLiqSourceReturnStoreSnapshotReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotReady) - << " replayLiqSourceReturnStoreSnapshotLegacyReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLegacyReady) - << " replayLiqSourceReturnStoreSnapshotLiveReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveReady) - << " replayLiqSourceReturnStoreSnapshotBlockedByLegacySnapshot=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedByLegacySnapshot) - << " replayLiqSourceReturnStoreSnapshotBlockedBySnapshot=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotBlockedBySnapshot) - << " replayLiqSourceReturnStoreSnapshotPolicyRequestCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestCandidate) - << " replayLiqSourceReturnStoreSnapshotPolicyRequestEnable=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestEnable) - << " replayLiqSourceReturnStoreSnapshotPolicySinkReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkReady) - << " replayLiqSourceReturnStoreSnapshotPolicyReqBlockedNoLaunch=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByNoLaunch) - << " replayLiqSourceReturnStoreSnapshotPolicyReqBlockedRowMutation=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRowMutationDisabled) - << " replayLiqSourceReturnStoreSnapshotPolicyReqBlockedRequestQueue=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByRequestQueue) - << " replayLiqSourceReturnStoreSnapshotPolicyReqBlockedAcceptedToken=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyRequestBlockedByAcceptedToken) - << " replayLiqSourceReturnStoreSnapshotPolicySinkBlockedNoRequest=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByNoRequest) - << " replayLiqSourceReturnStoreSnapshotPolicySinkBlockedRawSink=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicySinkBlockedByRawSink) - << " replayLiqSourceReturnStoreSnapshotPolicyResponseBlockedQueueFull=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLiveArmPolicyResponseBlockedByQueueFull) - << " replayLiqSourceReturnStoreSnapshotEffectiveRequestEnable=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestEnable) - << " replayLiqSourceReturnStoreSnapshotEffectiveRequestQueueCanAccept=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveRequestQueueCanAccept) - << " replayLiqSourceReturnStoreSnapshotEffectiveSinkReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEffectiveSinkReady) - << " replayLiqSourceReturnStoreSnapshotRequestControlBlockedByToken=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestControlBlockedByToken) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenCanAccept=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCanAccept) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenValid) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenResidentValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenResidentValid) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureCandidate) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureAccepted=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenCaptureAccepted) - << " replayLiqSourceReturnStoreSnapshotAcceptedTokenBlockedByOutstanding=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotAcceptedTokenBlockedByOutstanding) - << " replayLiqSourceReturnStoreSnapshotQueryIssueCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueCandidate) - << " replayLiqSourceReturnStoreSnapshotQueryIssueValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueValid) - << " replayLiqSourceReturnStoreSnapshotQueryIssueIssued=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueIssued) - << " replayLiqSourceReturnStoreSnapshotQueryIssueBlockedByRequestDisabled=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByRequestDisabled) - << " replayLiqSourceReturnStoreSnapshotQueryIssueBlockedByNoLaunch=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedByNoLaunch) - << " replayLiqSourceReturnStoreSnapshotQueryIssueBlockedBySink=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotQueryIssueBlockedBySink) - << " replayLiqSourceReturnStoreSnapshotRequestPayloadValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadValid) - << " replayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoIssue=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoIssue) - << " replayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoSelected=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByNoSelected) - << " replayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByStaleRow=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestPayloadBlockedByStaleRow) - << " replayLiqSourceReturnStoreSnapshotRequestQueueHeadValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadValid) - << " replayLiqSourceReturnStoreSnapshotRequestQueueHeadConsumed=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueHeadConsumed) - << " replayLiqSourceReturnStoreSnapshotRequestQueuePending=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueuePending) - << " replayLiqSourceReturnStoreSnapshotRequestQueueFull=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueFull) - << " replayLiqSourceReturnStoreSnapshotRequestQueueEmpty=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueEmpty) - << " replayLiqSourceReturnStoreSnapshotRequestQueueCount=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueCount) - << " replayLiqSourceReturnStoreSnapshotRequestQueueBlockedByFull=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestQueueBlockedByFull) - << " replayLiqSourceReturnStoreSnapshotRequestSinkCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkCandidate) - << " replayLiqSourceReturnStoreSnapshotRequestSinkReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkReady) - << " replayLiqSourceReturnStoreSnapshotRequestSinkAccepted=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkAccepted) - << " replayLiqSourceReturnStoreSnapshotRequestSinkResponseValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkResponseValid) - << " replayLiqSourceReturnStoreSnapshotRequestSinkBlockedByNoRequest=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByNoRequest) - << " replayLiqSourceReturnStoreSnapshotRequestSinkBlockedByRawSink=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByRawSink) - << " replayLiqSourceReturnStoreSnapshotRequestSinkBlockedByResponse=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRequestSinkBlockedByResponse) - << " replayLiqSourceReturnStoreSnapshotResponseQueueEnqueueAccepted=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEnqueueAccepted) - << " replayLiqSourceReturnStoreSnapshotResponseQueueHeadValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadValid) - << " replayLiqSourceReturnStoreSnapshotResponseQueueHeadConsumed=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueHeadConsumed) - << " replayLiqSourceReturnStoreSnapshotResponseQueuePending=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueuePending) - << " replayLiqSourceReturnStoreSnapshotResponseQueueFull=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueFull) - << " replayLiqSourceReturnStoreSnapshotResponseQueueEmpty=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueEmpty) - << " replayLiqSourceReturnStoreSnapshotResponseQueueCount=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueCount) - << " replayLiqSourceReturnStoreSnapshotResponseQueueBlockedByFull=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseQueueBlockedByFull) - << " replayLiqSourceReturnStoreSnapshotResponseDrainDequeueReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainDequeueReady) - << " replayLiqSourceReturnStoreSnapshotResponseDrainOrderedConsumed=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainOrderedConsumed) - << " replayLiqSourceReturnStoreSnapshotResponseDrainStaleDropped=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainStaleDropped) - << " replayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoHead=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoHead) - << " replayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoAction=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseDrainBlockedByNoAction) - << " replayLiqSourceReturnStoreSnapshotLookupQueryValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLookupQueryValid) - << " replayLiqSourceReturnStoreSnapshotLookupWaitStoreValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLookupWaitStoreValid) - << " replayLiqSourceReturnStoreSnapshotLookupRawDataValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLookupRawDataValid) - << " replayLiqSourceReturnStoreSnapshotLookupResponseDataValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLookupResponseDataValid) - << " replayLiqSourceReturnStoreSnapshotLookupStoreBypassComplete=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotLookupStoreBypassComplete) - << " replayLiqSourceReturnStoreSnapshotEvidenceRequestValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceRequestValid) - << " replayLiqSourceReturnStoreSnapshotEvidenceQueryActive=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceQueryActive) - << " replayLiqSourceReturnStoreSnapshotEvidenceResponseAccepted=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceResponseAccepted) - << " replayLiqSourceReturnStoreSnapshotEvidenceSnapshotRequired=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotRequired) - << " replayLiqSourceReturnStoreSnapshotEvidenceSnapshotValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceSnapshotValid) - << " replayLiqSourceReturnStoreSnapshotEvidenceWaitStoreReplay=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceWaitStoreReplay) - << " replayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoQuery=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoQuery) - << " replayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoResponse=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByNoResponse) - << " replayLiqSourceReturnStoreSnapshotEvidenceBlockedByWaitStore=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotEvidenceBlockedByWaitStore) - << " replayLiqSourceReturnStoreSnapshotResponseApplyCandidate=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyCandidate) - << " replayLiqSourceReturnStoreSnapshotResponseApplyValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyValid) - << " replayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoOrderedResponse=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoOrderedResponse) - << " replayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNotRepick=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNotRepick) - << " replayLiqSourceReturnStoreSnapshotResponseApplyBlockedByWaitStore=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByWaitStore) - << " replayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoData=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotResponseApplyBlockedByNoData) - << " replayLiqSourceReturnStoreSnapshotRowStatePlanValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanValid) - << " replayLiqSourceReturnStoreSnapshotRowStatePlanBlockedByNoApply=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowStatePlanBlockedByNoApply) - << " replayLiqSourceReturnStoreSnapshotRowMutationCandidateValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationCandidateValid) - << " replayLiqSourceReturnStoreSnapshotRowMutationTargetReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationTargetReady) - << " replayLiqSourceReturnStoreSnapshotRowMutationRequestValid=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationRequestValid) - << " replayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationHeadProofReady) - << " replayLiqSourceReturnStoreSnapshotRowMutationLivePermit=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationLivePermit) - << " replayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadProof) - << " replayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadInvalidRow) - << " replayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadScbNotReturned) - << " replayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadNotRepick) - << " replayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSnapshotRowMutationBlockedByHeadTargetMismatch) - << " replayLiqSourceReturnStoreSourceReturned=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnStoreSourceReturned) - << " replayLiqSourceReturnScbSourceReturned=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnScbSourceReturned) - << " replayLiqSourceReturnSourceReturned=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnSourceReturned) - << " replayLiqSourceReturnBlockedByBaseData=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnBlockedByBaseData) - << " replayLiqSourceReturnBlockedByStoreSnapshot=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnBlockedByStoreSnapshot) - << " replayLiqSourceReturnBlockedByScb=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnBlockedByScb) - << " replayLiqSourceReturnScbLivePending=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnScbLivePending) - << " replayLiqSourceReturnScbLiveReturned=" - << static_cast(dut.io_reducedLoadReplayLiqSourceReturnScbLiveReturned) - << " replayLiqReturnConsumerReady=" - << static_cast(dut.io_reducedLoadReplayLiqReturnConsumerReady) - << " replayLiqReturnConsumerBlockedBySources=" - << static_cast(dut.io_reducedLoadReplayLiqReturnConsumerBlockedBySources) - << " replayLiqReturnConsumerBlockedByLretSink=" - << static_cast(dut.io_reducedLoadReplayLiqReturnConsumerBlockedByLretSink) - << " replayLiqReturnPipeBudgetAvailable=" - << static_cast(dut.io_reducedLoadReplayLiqReturnPipeBudgetAvailable) - << " replayLiqReturnPipeBudgetBlockedByConsumer=" - << static_cast(dut.io_reducedLoadReplayLiqReturnPipeBudgetBlockedByConsumer) - << " replayLiqReturnPipeAvailable=" - << static_cast(dut.io_reducedLoadReplayLiqReturnPipeAvailable) - << " replayLiqReturnPipeBlockedByNoPipe=" - << static_cast(dut.io_reducedLoadReplayLiqReturnPipeBlockedByNoPipe) - << " replayLiqReturnReadinessReady=" - << static_cast(dut.io_reducedLoadReplayLiqReturnReadinessReady) - << " replayLiqReturnReadinessBlockedBySources=" - << static_cast(dut.io_reducedLoadReplayLiqReturnReadinessBlockedBySources) - << " replayLiqReturnReadinessBlockedByReturnPipe=" - << static_cast(dut.io_reducedLoadReplayLiqReturnReadinessBlockedByReturnPipe) - << std::dec - << "\n"; - if (!g_replay_liq_sideband_stats_path.empty()) { - write_replay_liq_sideband_stats(g_replay_liq_sideband_stats_path); - } - std::exit(1); -} - -void filter_pending_marker_commits( - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count) { - while (!pending_commits.empty() && !filtered_marker_commits.empty()) { - bool filtered = false; - for (auto it = pending_commits.begin(); it != pending_commits.end(); ++it) { - if (!is_observed_marker_commit(*it)) { - continue; - } - expect_marker_commit(*it, filtered_marker_commits.front()); - pending_commits.erase(it); - filtered_marker_commits.erase(filtered_marker_commits.begin()); - ++marker_commit_filter_count; - filtered = true; - break; - } - if (!filtered) { - return; - } - } -} - -void wait_for_admitted_marker_redirect( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - const ExpectedRow &expected, - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count, - FetchMemoryImage &fetch_memory) { - bool saw_lifecycle_ready = false; - bool saw_lifecycle_fire = false; - bool saw_lifecycle_boundary_fire = false; - bool saw_lifecycle_stop_fire = false; - bool saw_retire_source_valid = false; - bool saw_retire_source_boundary = false; - bool saw_retire_source_stop = false; - bool saw_dealloc_block_last = false; - bool saw_redirect_valid = false; - std::uint64_t last_retire_source_block_bid = 0; - std::uint64_t last_retire_source_boundary_target = 0; - std::uint64_t last_dealloc_block_last_bid = 0; - std::uint64_t last_redirect_pc = 0; - for (int cycle = 0; cycle < 64; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!pending_commits.empty()) { - std::cerr << "frontend fetch RF ALU saw scalar commit while waiting for admitted marker redirect" - << " marker_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << pending_commits.front().pc << std::dec - << " admittedMarkerBarrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << "\n"; - std::exit(1); - } - - clear_inputs(dut); - eval_with_load_lookup(dut, fetch_memory); - saw_lifecycle_ready |= dut.io_robMarkerRetireSourceLifecycleReady; - saw_lifecycle_fire |= dut.io_robMarkerRetireSourceLifecycleFire; - saw_lifecycle_boundary_fire |= dut.io_robMarkerRetireSourceLifecycleBoundaryFire; - saw_lifecycle_stop_fire |= dut.io_robMarkerRetireSourceLifecycleStopFire; - saw_retire_source_valid |= dut.io_robMarkerRetireSourceValid; - saw_retire_source_boundary |= dut.io_robMarkerRetireSourceBoundary; - saw_retire_source_stop |= dut.io_robMarkerRetireSourceStop; - saw_dealloc_block_last |= dut.io_robDeallocBlockLastValid; - saw_redirect_valid |= dut.io_blockMarkerStopRedirectValid; - if (dut.io_robMarkerRetireSourceValid) { - last_retire_source_block_bid = dut.io_robMarkerRetireSourceBlockBid; - last_retire_source_boundary_target = dut.io_robMarkerRetireSourceBoundaryTarget; - } - if (dut.io_robDeallocBlockLastValid) { - last_dealloc_block_last_bid = dut.io_robDeallocBlockLastBlockBid; - } - if (dut.io_blockMarkerStopRedirectValid) { - last_redirect_pc = dut.io_blockMarkerStopRedirectPc; - } - if (dut.io_rfStateError) { - std::cerr << "frontend fetch RF ALU reported RF state error while waiting for marker redirect\n"; - std::exit(1); - } - if (dut.io_executeUnsupported) { - std::cerr << "execute reported unsupported opcode while waiting for marker redirect opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid && dut.io_completeIgnored) { - std::cerr << "execute completion was ignored while waiting for marker redirect" - << " rob=" << static_cast(dut.io_executeCompleteRobValue) - << "\n"; - std::exit(1); - } - - const bool observed_commit_window = dut.io_commit_rows_0_valid; - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU marker redirect wait"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!pending_commits.empty()) { - std::cerr << "frontend fetch RF ALU saw scalar commit after marker filtering while waiting for redirect" - << " marker_pc=0x" << std::hex << expected.pc - << " observed_pc=0x" << pending_commits.front().pc << std::dec - << " admittedMarkerBarrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << "\n"; - std::exit(1); - } - - if (dut.io_blockMarkerStopRedirectValid) { - if (dut.io_blockMarkerStopRedirectPc != expected.next_pc) { - std::cerr << "frontend fetch RF ALU admitted marker redirect mismatch" - << " marker_pc=0x" << std::hex << expected.pc - << " expected_pc=0x" << expected.next_pc - << " observed_pc=0x" << dut.io_blockMarkerStopRedirectPc - << std::dec << "\n"; - std::exit(1); - } - tick(dut); - return; - } - if (observed_commit_window) { - tick(dut); - continue; - } - expect_monitor_clean(dut, "frontend fetch RF ALU marker redirect wait", 0x0, 0); - tick(dut); - } - - std::cerr << "frontend fetch RF ALU admitted marker did not redirect" - << " marker_pc=0x" << std::hex << expected.pc - << " expected_pc=0x" << expected.next_pc << std::dec - << " pending_markers=" << filtered_marker_commits.size() - << " pending_commits=" << pending_commits.size() - << " lifecycle_ready=" << static_cast(dut.io_robMarkerRetireSourceLifecycleReady) - << " lifecycle_fire=" << static_cast(dut.io_robMarkerRetireSourceLifecycleFire) - << " lifecycle_boundary_fire=" << static_cast(dut.io_robMarkerRetireSourceLifecycleBoundaryFire) - << " lifecycle_stop_fire=" << static_cast(dut.io_robMarkerRetireSourceLifecycleStopFire) - << " retire_source_valid=" << static_cast(dut.io_robMarkerRetireSourceValid) - << " retire_source_boundary=" << static_cast(dut.io_robMarkerRetireSourceBoundary) - << " retire_source_stop=" << static_cast(dut.io_robMarkerRetireSourceStop) - << " retire_source_last=" << static_cast(dut.io_robMarkerRetireSourceLast) - << " retire_source_block_bid_valid=" << static_cast(dut.io_robMarkerRetireSourceBlockBidValid) - << " retire_source_block_bid=0x" << std::hex << dut.io_robMarkerRetireSourceBlockBid - << " retire_source_boundary_target=0x" << dut.io_robMarkerRetireSourceBoundaryTarget - << " dealloc_block_last_valid=" << std::dec << static_cast(dut.io_robDeallocBlockLastValid) - << " dealloc_block_last_block_bid=0x" << std::hex << dut.io_robDeallocBlockLastBlockBid - << " active_valid=" << std::dec << static_cast(dut.io_blockMarkerActiveValid) - << " active_bid=0x" << std::hex << dut.io_blockMarkerActiveBid - << " active_target=0x" << dut.io_blockMarkerActiveTarget - << " saw_lifecycle_ready=" << std::dec << static_cast(saw_lifecycle_ready) - << " saw_lifecycle_fire=" << static_cast(saw_lifecycle_fire) - << " saw_lifecycle_boundary_fire=" << static_cast(saw_lifecycle_boundary_fire) - << " saw_lifecycle_stop_fire=" << static_cast(saw_lifecycle_stop_fire) - << " saw_retire_source_valid=" << static_cast(saw_retire_source_valid) - << " saw_retire_source_boundary=" << static_cast(saw_retire_source_boundary) - << " saw_retire_source_stop=" << static_cast(saw_retire_source_stop) - << " saw_dealloc_block_last=" << static_cast(saw_dealloc_block_last) - << " saw_redirect_valid=" << static_cast(saw_redirect_valid) - << " last_retire_source_block_bid=0x" << std::hex << last_retire_source_block_bid - << " last_retire_source_boundary_target=0x" << last_retire_source_boundary_target - << " last_dealloc_block_last_bid=0x" << last_dealloc_block_last_bid - << " last_redirect_pc=0x" << last_redirect_pc << std::dec - << "\n"; - std::exit(1); -} - -void drain_tail_marker_commits( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count, - FetchMemoryImage &fetch_memory) { - for (int cycle = 0; cycle < 64; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (filtered_marker_commits.empty()) { - return; - } - if (!pending_commits.empty()) { - std::cerr << "frontend fetch RF ALU saw scalar commit while draining tail marker" - << " marker_pc=0x" << std::hex << filtered_marker_commits.front().pc - << " observed_pc=0x" << pending_commits.front().pc << std::dec - << "\n"; - std::exit(1); - } - - clear_inputs(dut); - eval_with_load_lookup(dut, fetch_memory); - if (dut.io_rfStateError) { - std::cerr << "frontend fetch RF ALU reported RF state error while draining tail marker\n"; - std::exit(1); - } - if (dut.io_executeUnsupported) { - std::cerr << "execute reported unsupported opcode while draining tail marker opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid && dut.io_completeIgnored) { - std::cerr << "execute completion was ignored while draining tail marker" - << " rob=" << static_cast(dut.io_executeCompleteRobValue) - << "\n"; - std::exit(1); - } - const std::uint64_t tail_marker_pc = filtered_marker_commits.front().pc; - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU tail marker drain"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!pending_commits.empty()) { - std::cerr << "frontend fetch RF ALU saw scalar commit after tail marker filtering" - << " marker_pc=0x" << std::hex << tail_marker_pc - << " observed_pc=0x" << pending_commits.front().pc << std::dec - << "\n"; - std::exit(1); - } - tick(dut); - } - - if (!filtered_marker_commits.empty()) { - std::cerr << "frontend fetch RF ALU tail marker did not retire" - << " marker_pc=0x" << std::hex << filtered_marker_commits.front().pc - << " next_pc=0x" << filtered_marker_commits.front().next_pc - << std::dec << "\n"; - std::exit(1); - } -} - -void commit_expected_row( - VLinxCoreFrontendFetchRfAluTraceTop &dut, - const ExpectedRow &expected, - std::vector &pending_commits, - std::vector &filtered_marker_commits, - std::uint64_t &marker_commit_filter_count, - FetchMemoryImage &fetch_memory, - std::ofstream &dut_out, - std::ofstream &qemu_out, - bool disable_store_memory_mutation) { - for (int cycle = 0; cycle < 32; ++cycle) { - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!pending_commits.empty()) { - const ObservedRow observed = pending_commits.front(); - pending_commits.erase(pending_commits.begin()); - expect_row(observed, expected, &dut); - write_dut_row(dut_out, observed); - write_qemu_row(qemu_out, expected); - if (!disable_store_memory_mutation && expected.mem_valid && expected.mem_is_store && expected.mem_size == 8) { - fetch_memory.store_u64(expected.mem_addr, expected.mem_wdata); - } - if (pending_commits.empty()) { - clear_inputs(dut); - tick(dut); - // A two-wide commit can make the following completed ROB row visible - // immediately after this edge. Preserve it before returning to the - // caller, which is about to advance the expected-row cursor. - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU trace top post-drain commit"); - } - return; - } - clear_inputs(dut); - eval_with_load_lookup(dut, fetch_memory); - if (dut.io_rfStateError) { - std::cerr << "frontend fetch RF ALU reported RF state error while waiting for commit\n"; - std::exit(1); - } - if (dut.io_executeUnsupported) { - std::cerr << "execute reported unsupported opcode=" - << static_cast(dut.io_executeUnsupportedOpcode) << "\n"; - std::exit(1); - } - if (dut.io_executeCompleteValid && dut.io_completeIgnored) { - std::cerr << "execute completion was ignored while waiting for commit" - << " rob=" << static_cast(dut.io_executeCompleteRobValue) - << "\n"; - std::exit(1); - } - const bool observed_commit_window = dut.io_commit_rows_0_valid; - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU trace top commit"); - filter_pending_marker_commits(pending_commits, filtered_marker_commits, marker_commit_filter_count); - if (!pending_commits.empty()) { - const ObservedRow observed = pending_commits.front(); - pending_commits.erase(pending_commits.begin()); - expect_row(observed, expected, &dut); - write_dut_row(dut_out, observed); - write_qemu_row(qemu_out, expected); - if (!disable_store_memory_mutation && expected.mem_valid && expected.mem_is_store && expected.mem_size == 8) { - fetch_memory.store_u64(expected.mem_addr, expected.mem_wdata); - } - tick(dut); - // `tick` evaluates the state after the active edge. Sample that - // commit window as well: otherwise a completed row immediately after a - // drained dual-commit window is retired without ever entering the - // harness's pending-commit queue. - collect_commit_if_present(dut, pending_commits, "frontend fetch RF ALU trace top post-drain commit"); - return; - } - if (observed_commit_window) { - tick(dut); - continue; - } - expect_monitor_clean(dut, "frontend fetch RF ALU trace top wait", 0x0, 0); - tick(dut); - } - - std::cerr << "frontend fetch RF ALU trace top did not emit a commit row" - << " pc=0x" << std::hex << expected.pc << std::dec - << " pendingCommits=" << pending_commits.size() - << " decRenCount=" << static_cast(dut.io_decRenCount) - << " decRenValid=" << static_cast(dut.io_decRenValid) - << " decRenHeadPc=0x" << std::hex - << static_cast(dut.io_decRenHeadPc) - << " decRenHeadRidValid=" << std::dec - << static_cast(dut.io_decRenHeadRidValid) - << " decRenHeadRidValue=" << static_cast(dut.io_decRenHeadRidValue) - << " renamedOutValid=" << static_cast(dut.io_renamedOutValid) - << " renamedAccepted=" << static_cast(dut.io_renamedAccepted) - << " decodeBlockedByRename=" << static_cast(dut.io_decodeBlockedByRename) - << " decodeBlockedByRob=" << static_cast(dut.io_decodeBlockedByRob) - << " decodeBlockedByOutput=" << static_cast(dut.io_decodeBlockedByOutput) - << " decodeBlockedByTURename=" << static_cast(dut.io_decodeBlockedByTURename) - << " admittedBarrier=" << static_cast(dut.io_admittedMarkerDrainBarrier) - << " decodeQueueReady=" << static_cast(dut.io_decodeQueuePushReady) - << " decodeAllocReady=" << static_cast(dut.io_decodeAllocReady) - << " decodeGprReady=" << static_cast(dut.io_decodeGprReservationReady) - << " decodeClosesRedirect=" << static_cast(dut.io_decodeSelectedClosesActiveRedirect) - << " decodeNeedsGpr=" << static_cast(dut.io_decodeSelectedNeedsGprReservation) - << " gprReservationCount=" << static_cast(dut.io_gprReservationCount) - << " gprReservationNeed=" << static_cast(dut.io_gprReservationNeed) - << " gprFree=" << static_cast(dut.io_gprFreeCount) - << " gprMapQValid=" << static_cast(dut.io_gprMapQValidCount) - << " gprMapQFree=" << static_cast(dut.io_gprMapQFreeCount) - << " gprSmapLive=" << static_cast(dut.io_gprSmapLiveCount) - << " gprCmapLive=" << static_cast(dut.io_gprCmapLiveCount) - << " gprMapQLive=" << static_cast(dut.io_gprMapQLiveCount) - << " gprLivePhys=" << static_cast(dut.io_gprLivePhysCount) - << " gprFreeFromLive=" << static_cast(dut.io_gprFreeFromLiveCount) - << " gprFreeMismatch=" << static_cast(dut.io_gprFreeListMismatchCount) - << " gprNextMapQValid=" << static_cast(dut.io_gprNextMapQValidCount) - << " gprNextMapQLive=" << static_cast(dut.io_gprNextMapQLiveCount) - << " gprNextLivePhys=" << static_cast(dut.io_gprNextLivePhysCount) - << " gprNextFreeFromLive=" << static_cast(dut.io_gprNextFreeFromLiveCount) - << " robRenameUpdateAttemptValid=" - << static_cast(dut.io_robRenameUpdateAttemptValid) - << " robRenameUpdateReady=" << static_cast(dut.io_robRenameUpdateReady) - << " robRenameUpdateFire=" << static_cast(dut.io_robRenameUpdateFire) - << " robRenameUpdateIgnored=" << static_cast(dut.io_robRenameUpdateIgnored) - << " tuUnderflow=0x" << std::hex - << static_cast(dut.io_tuRenameSourceUnderflowMask) - << " tuActiveBank=" << std::dec - << static_cast(dut.io_tuRenameActiveBankValid) - << " tuTBlocked=" << static_cast(dut.io_tuRenameBlockedByTAlloc) - << " tuUBlocked=" << static_cast(dut.io_tuRenameBlockedByUAlloc) - << " tuTUsed=" << static_cast(dut.io_tuRenameTUsedEntries) - << " tuUUsed=" << static_cast(dut.io_tuRenameUUsedEntries) - << " tuRetCmdValid=" << static_cast(dut.io_tuRetireCommandValid) - << " tuRetCmdFire=" << static_cast(dut.io_tuRetireCommandFire) - << " tuLocalCommitPending=" << static_cast(dut.io_tuRetireLocalBlockCommitPending) - << " tuLocalCommitValid=" << static_cast(dut.io_tuRetireLocalBlockCommitValid) - << " tuLocalCommitReady=" << static_cast(dut.io_tuRetireLocalBlockCommitReady) - << " tuLocalCommitFire=" << static_cast(dut.io_tuRetireLocalBlockCommitFire) - << " tuRetAccepted=" << static_cast(dut.io_tuRetireAccepted) - << " tuRetMiss=" << static_cast(dut.io_tuRetireMiss) - << " tuRetMismatch=" << static_cast(dut.io_tuRetireReleaseMismatch) - << " tuRetUnsupported=" << static_cast(dut.io_tuRetireUnsupported) - << " localT=0x" << std::hex << static_cast(dut.io_localTReadyMask) - << " localU=0x" << static_cast(dut.io_localUReadyMask) - << std::dec - << " localTPending=" << static_cast(dut.io_localTPendingCount) - << " localUPending=" << static_cast(dut.io_localUPendingCount) - << " localIncomingUsesLocal=" << static_cast(dut.io_localIncomingUsesLocal) - << " localIncomingBlocked=" << static_cast(dut.io_localIncomingBlocked) - << " storeDispatchReady=" << static_cast(dut.io_storeDispatchReady) - << " storeDispatchFire=" << static_cast(dut.io_storeDispatchFire) - << " storeDispatchSplit=" << static_cast(dut.io_storeDispatchSplit) - << " storeStaQ=" << static_cast(dut.io_storeStaQueueCount) - << " storeStdQ=" << static_cast(dut.io_storeStdQueueCount) - << " storeStaExecValid=" << static_cast(dut.io_reducedStoreStaExecValid) - << " storeStdExecValid=" << static_cast(dut.io_reducedStoreStdExecValid) - << " storeBlockedStaExec=" << static_cast(dut.io_storeBlockedByStaExec) - << " storeBlockedStdExec=" << static_cast(dut.io_storeBlockedByStdExec) - << " storeStaInsertReady=" << static_cast(dut.io_storeStaInsertReady) - << " storeStdInsertReady=" << static_cast(dut.io_storeStdInsertReady) - << " storeSelectedSta=" << static_cast(dut.io_storeSelectedSta) - << " storeSelectedStd=" << static_cast(dut.io_storeSelectedStd) - << " storeStqInsertValid=" << static_cast(dut.io_storeStqInsertValid) - << " storeStqInsertAccepted=" << static_cast(dut.io_storeStqInsertAccepted) - << " storeStqInsertAllocated=" << static_cast(dut.io_storeStqInsertAllocated) - << " storeStqInsertMerged=" << static_cast(dut.io_storeStqInsertMerged) - << " storeStqInsertConflict=" << static_cast(dut.io_storeStqInsertConflict) - << " reducedStoreExecStaMatch=" - << static_cast(dut.io_reducedStoreExecStaMatch) - << " reducedStoreExecStdMatch=" - << static_cast(dut.io_reducedStoreExecStdMatch) - << " storeStqWait=0x" << std::hex << hex_port(dut.io_storeStqWaitMask) - << " storeStqCommit=0x" << hex_port(dut.io_storeStqCommitMask) - << " storeStqAddrReady=0x" << hex_port(dut.io_storeStqAddrReadyMask) - << " storeStqDataReady=0x" << hex_port(dut.io_storeStqDataReadyMask) - << std::dec - << " storeStqResident=" << static_cast(dut.io_storeStqResidentCount) - << " storeStqOutstandingWait=" << static_cast(dut.io_storeStqOutstandingWaitCount) - << " storeStqFull=" << static_cast(dut.io_storeStqFull) - << " reducedStoreExecBuf=" << static_cast(dut.io_reducedStoreExecBufferCount) - << " reducedStoreExecMask=0x" << std::hex - << static_cast(dut.io_reducedStoreExecValidMask) - << std::dec - << " reducedStoreCommitSeen=" << static_cast(dut.io_reducedStoreCommitStoreSeen) - << " reducedStoreCommitMatched=" << static_cast(dut.io_reducedStoreCommitStoreMatched) - << " reducedStoreCommitUnmatched=" << static_cast(dut.io_reducedStoreCommitStoreUnmatched) - << " reducedStoreCommitMatchMask=0x" << std::hex - << static_cast(dut.io_reducedStoreCommitMatchMask) - << " reducedStoreCommitEarlySafeMatchMask=0x" - << static_cast(dut.io_reducedStoreCommitEarlySafeMatchMask) - << " reducedStoreCommitPendingIdentityMask=0x" - << static_cast(dut.io_reducedStoreCommitPendingIdentityMask) - << " reducedStoreCommitPendingEarlySafeMask=0x" - << static_cast(dut.io_reducedStoreCommitPendingEarlySafeMask) - << " reducedStoreCommitPendingMarkMask=0x" - << static_cast(dut.io_reducedStoreCommitPendingMarkMask) - << " reducedStoreCommitPendingFreeMask=0x" - << static_cast(dut.io_reducedStoreCommitPendingFreeMask) - << std::dec - << " reducedStoreCommitMarkValid=" - << static_cast(dut.io_reducedStoreCommitMarkValid) - << " reducedStoreCommitMarkAccepted=" - << static_cast(dut.io_reducedStoreCommitMarkAccepted) - << " reducedStoreCommitMarkBlocked=" - << static_cast(dut.io_reducedStoreCommitMarkBlocked) - << " reducedStoreCommitMarkPending=" - << static_cast(dut.io_reducedStoreCommitPendingMarkCount) - << " reducedStoreDrainQ=" << static_cast(dut.io_reducedStoreDrainQueueCount) - << " reducedStoreScbEntries=" << static_cast(dut.io_reducedStoreScbEntryCount) - << " reducedStoreMemoryLines=" << static_cast(dut.io_reducedStoreMemoryLineCount) - << " reducedStoreMemoryForwardMask=0x" << std::hex - << static_cast(dut.io_reducedStoreMemoryLoadForwardMask) - << " reducedStoreMemoryDropped=0x" - << static_cast(dut.io_reducedStoreMemoryStoreDroppedMask) - << std::dec - << " issueCount=" << static_cast(dut.io_issueQueueCount) - << " issueHeadValid=" << static_cast(dut.io_issueQueueHeadValid) - << " issueHeadIssued=" << static_cast(dut.io_issueQueueHeadIssued) - << " issueHeadPc=0x" << std::hex - << static_cast(dut.io_issueQueueHeadPc) - << " issueHeadOpcode=0x" - << static_cast(dut.io_issueQueueHeadOpcode) - << " issueHeadSrcValid=0x" - << static_cast(dut.io_issueQueueHeadSrcValidMask) - << " issueHeadSrc0=(cls=" << std::dec - << static_cast(dut.io_issueQueueHeadSrcClass_0) - << ",phys=" << static_cast(dut.io_issueQueueHeadSrcPhysTag_0) - << ",rel=" << static_cast(dut.io_issueQueueHeadSrcRelTag_0) - << ") issueHeadSrc1=(cls=" - << static_cast(dut.io_issueQueueHeadSrcClass_1) - << ",phys=" << static_cast(dut.io_issueQueueHeadSrcPhysTag_1) - << ",rel=" << static_cast(dut.io_issueQueueHeadSrcRelTag_1) - << ") issueHeadSrc2=(cls=" - << static_cast(dut.io_issueQueueHeadSrcClass_2) - << ",phys=" << static_cast(dut.io_issueQueueHeadSrcPhysTag_2) - << ",rel=" << static_cast(dut.io_issueQueueHeadSrcRelTag_2) - << ")" - << " issueSourceReady=0x" << std::hex - << static_cast(dut.io_issueQueueSourceReadyMask) - << std::dec - << " issueSelectedValid=" << static_cast(dut.io_issueQueueSelectedValid) - << " issueSelectedReadReady=" << static_cast(dut.io_issueQueueSelectedReadReady) - << " issueI1Valid=" << static_cast(dut.io_issueQueueI1Valid) - << " issueI2Valid=" << static_cast(dut.io_issueQueueI2Valid) - << " issueBlockedBySource=" << static_cast(dut.io_issueQueueBlockedBySource) - << " issueBlockedByRead=" << static_cast(dut.io_issueQueueBlockedByRead) - << " issueBlockedByOutput=" << static_cast(dut.io_issueQueueBlockedByOutput) - << " issueBlockedByIssued=" << static_cast(dut.io_issueQueueBlockedByIssued) - << " issueControlFenceActive=" - << static_cast(dut.io_issueQueueControlFenceActive) - << " issueControlFenceBlocked=" - << static_cast(dut.io_issueQueueControlFenceBlocked) - << " issueStoreOrderBlocked=" - << static_cast(dut.io_issueQueueStoreOrderBlocked) - << " executeBusy=" << static_cast(dut.io_executeBusy) - << " outstanding=" << static_cast(dut.io_outstandingCount) - << " robDeallocBlockLastValid=" << static_cast(dut.io_robDeallocBlockLastValid) - << " blockScalarDoneFire=" << static_cast(dut.io_blockScalarDoneFire) - << " blockRetireFire=" << static_cast(dut.io_blockRetireFire) - << " commitHeadValid=" << static_cast(dut.io_commitHeadValid) - << " commitHeadStatus=" << static_cast(dut.io_commitHeadStatus) - << " commitHeadRobValue=" << static_cast(dut.io_commitHeadRobValue) - << " occupiedMask=0x" << std::hex - << hex_port(dut.io_occupiedMask) - << " completedMask=0x" << std::hex - << hex_port(dut.io_completedMask) - << " retiredMask=0x" - << hex_port(dut.io_retiredMask) - << std::dec -#if defined(LINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP) || \ - defined(LINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP) - << " liqOccupied=0x" << std::hex - << static_cast(dut.io_reducedLoadReplayLiqOccupiedMask) - << " liqWait=0x" << static_cast(dut.io_reducedLoadReplayLiqWaitMask) - << " liqLaunchWait=0x" << static_cast(dut.io_reducedLoadReplayLiqLaunchWaitMask) - << " liqLaunchUnblocked=0x" << static_cast(dut.io_reducedLoadReplayLiqLaunchUnblockedWaitMask) - << " liqLaunchCandidate=0x" << static_cast(dut.io_reducedLoadReplayLiqLaunchCandidateMask) - << " liqLaunchMask=0x" << static_cast(dut.io_reducedLoadReplayLiqLaunchMask) - << std::dec - << " liqLaunchValid=" << static_cast(dut.io_reducedLoadReplayLiqLaunchValid) - << " liqLaunchDrive=" << static_cast(dut.io_reducedLoadReplayLiqLaunchDriveValid) - << " liqLaunchReady=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReady) - << " liqLaunchAccepted=" << static_cast(dut.io_reducedLoadReplayLiqLaunchAccepted) - << " liqBaseLookupValid=" << static_cast(dut.io_reducedLoadReplayLiqBaseLookupValid) - << " liqBaseLookupGranted=" << static_cast(dut.io_reducedLoadReplayLiqBaseLookupGranted) - << " liqBaseDataReturned=" << static_cast(dut.io_reducedLoadReplayLiqBaseDataReturned) - << " liqLaunchReadinessCandidate=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessCandidateValid) - << " liqLaunchReadinessBaseData=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBaseDataReady) - << " liqLaunchReadinessSources=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessSourcesReturned) - << " liqLaunchReadinessReady=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessReady) - << " liqLaunchEnable=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessEnable) - << " liqLaunchBlockNoCandidate=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByNoCandidate) - << " liqLaunchBlockLookup=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseLookup) - << " liqLaunchBlockData=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByBaseData) - << " liqLaunchBlockScb=" << static_cast(dut.io_reducedLoadReplayLiqLaunchReadinessBlockedByScb) - << " liqReturnValid=" << static_cast(dut.io_reducedLoadReplayLiqReturnCompleteValid) - << " liqReturnCandidate=0x" << std::hex - << static_cast(dut.io_reducedLoadReplayLiqReturnCompleteCandidateMask) - << std::dec -#endif - << "\n"; - if (!g_replay_liq_sideband_stats_path.empty()) { - write_replay_liq_sideband_stats(g_replay_liq_sideband_stats_path); - } - std::exit(1); -} - -std::vector fixture_rows() { - const std::uint64_t add = - 0x00000005ULL | (3ULL << 7) | (4ULL << 15) | (5ULL << 20); - const std::uint64_t addi = - 0x00000015ULL | (6ULL << 7) | (3ULL << 15) | (0x7ffULL << 20); - const std::uint64_t c_movr = - 0x0006ULL | (6ULL << 6) | (5ULL << 11); - - ExpectedRow r0; - r0.pc = 0x1000; - r0.insn = add; - r0.len = 4; - r0.src0_valid = true; - r0.src0_reg = 4; - r0.src0_data = 10; - r0.src1_valid = true; - r0.src1_reg = 5; - r0.src1_data = 32; - r0.dst_valid = true; - r0.dst_reg = 3; - r0.dst_data = 42; - - ExpectedRow r1; - r1.pc = 0x1004; - r1.insn = addi; - r1.len = 4; - r1.src0_valid = true; - r1.src0_reg = 3; - r1.src0_data = 42; - r1.dst_valid = true; - r1.dst_reg = 6; - r1.dst_data = 2089; - - ExpectedRow r2; - r2.pc = 0x1008; - r2.insn = c_movr; - r2.len = 2; - r2.src0_valid = true; - r2.src0_reg = 6; - r2.src0_data = 2089; - r2.dst_valid = true; - r2.dst_reg = 5; - r2.dst_data = 2089; - - return {r0, r1, r2}; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - g_replay_liq_sideband_stats_path = args.sideband_stats; - - const auto rows = args.expected_rows.empty() - ? fixture_rows() - : load_expected_rows_jsonl(args.expected_rows); - FetchMemoryImage fetch_memory; - if (!args.memory_hex.empty()) { - fetch_memory.load_sparse_hex(args.memory_hex); - } else if (!args.memory_bin.empty()) { - fetch_memory.load_binary(args.memory_bin, args.memory_base); - } else { - fetch_memory = FetchMemoryImage::from_rows(rows); - } - - VLinxCoreFrontendFetchRfAluTraceTop dut; - reset(dut); - const auto seed_preloads = args.rf_seed.empty() - ? std::map{} - : load_rf_seed_jsonl(args.rf_seed); - for (const auto &[arch_tag, data] : initial_rf_preloads(rows, seed_preloads)) { - init_rf(dut, arch_tag, data); - } - - std::ofstream dut_out(args.dut_trace); - std::ofstream qemu_out(args.qemu_trace); - if (!dut_out || !qemu_out) { - std::cerr << "failed to open output traces\n"; - return 2; - } - - start_source(dut, rows.front().pc); - bool active_block_valid = false; - std::uint64_t active_block_bid = 0; - bool captured_tail_superset = false; - bool next_local_body_cut_reentry_header = false; - std::uint64_t next_local_body_cut_reentry_pc = 0; - std::vector pending_commits; - std::vector filtered_marker_commits; - std::uint64_t marker_rows_admitted = 0; - std::uint64_t marker_commits_filtered = 0; - BfuGeometryDiagnostics bfu_stats; - for (std::size_t row_index = 0; row_index < rows.size();) { - const std::size_t window_end = dense_window_end(rows, row_index); - const FetchDenseWindowResult capture = - fetch_dense_window( - dut, - rows, - row_index, - window_end, - fetch_memory, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - bfu_stats); - captured_tail_superset |= capture.captured_tail_superset; - const std::size_t drain_end = row_index + capture.captured_slots; - - std::vector scalar_slots; - bool replay_local_body_cut_reentry_header = false; - for (std::size_t slot_index = row_index; slot_index < drain_end; ++slot_index) { - const ExpectedRow &row = rows[slot_index]; - const bool local_body_cut_reentry_header = - next_local_body_cut_reentry_header && - slot_index == row_index && - row.skip && - row.block_boundary && - row.pc == next_local_body_cut_reentry_pc; - if (next_local_body_cut_reentry_header && slot_index == row_index && !local_body_cut_reentry_header) { - std::cerr << "frontend fetch RF ALU expected a local-body-cut re-entry header" - << " expected_pc=0x" << std::hex << next_local_body_cut_reentry_pc - << " observed_pc=0x" << row.pc << std::dec - << " skip=" << static_cast(row.skip) - << " block_boundary=" << static_cast(row.block_boundary) - << "\n"; - return 1; - } - if (row.skip) { - const DrainDenseRowResult drain_result = drain_dense_row( - dut, - row, - active_block_valid, - active_block_bid, - fetch_memory, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - bfu_stats, - args.admit_marker_rows, - local_body_cut_reentry_header); - if (args.admit_marker_rows) { - ++marker_rows_admitted; - if ((row.block_boundary || row.block_stop) && row_redirects(row)) { - for (const auto pending_scalar_slot : scalar_slots) { - const ExpectedRow &pending_scalar = rows[pending_scalar_slot]; - commit_expected_row( - dut, - pending_scalar, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - fetch_memory, - dut_out, - qemu_out, - args.disable_store_memory_mutation); - } - scalar_slots.clear(); - wait_for_admitted_marker_redirect( - dut, - row, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - fetch_memory); - } - } - if (local_body_cut_reentry_header) { - next_local_body_cut_reentry_header = false; - next_local_body_cut_reentry_pc = 0; - if (drain_result.marker_redirect) { - replay_local_body_cut_reentry_header = true; - break; - } - } - continue; - } - (void)drain_dense_row( - dut, - row, - active_block_valid, - active_block_bid, - fetch_memory, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - bfu_stats, - args.admit_marker_rows); - scalar_slots.push_back(slot_index); - } - - for (const auto slot_index : scalar_slots) { - const ExpectedRow &row = rows[slot_index]; - commit_expected_row( - dut, - row, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - fetch_memory, - dut_out, - qemu_out, - args.disable_store_memory_mutation); - } - if (replay_local_body_cut_reentry_header) { - continue; - } - row_index = drain_end; - if (capture.local_body_cut_prefix) { - if (!is_suppressed_local_body_cut_marker(rows, row_index)) { - std::cerr << "frontend fetch RF ALU local body cut did not stop before a redirecting BSTART marker" - << " row_index=" << row_index; - if (row_index < rows.size()) { - const ExpectedRow &row = rows[row_index]; - std::cerr << " pc=0x" << std::hex << row.pc - << " next_pc=0x" << row.next_pc << std::dec - << " skip=" << static_cast(row.skip) - << " block_boundary=" << static_cast(row.block_boundary); - } - std::cerr << "\n"; - return 1; - } - next_local_body_cut_reentry_header = true; - next_local_body_cut_reentry_pc = rows[row_index].next_pc; - ++row_index; - } else { - row_index = window_end; - } - } - - if (!filtered_marker_commits.empty()) { - drain_tail_marker_commits( - dut, - pending_commits, - filtered_marker_commits, - marker_commits_filtered, - fetch_memory); - } - if (!filtered_marker_commits.empty()) { - std::cerr << "frontend fetch RF ALU trace top has unfiltered marker commits=" - << filtered_marker_commits.size() - << " pc=0x" << std::hex << filtered_marker_commits.front().pc - << std::dec << "\n"; - return 1; - } - if (!pending_commits.empty()) { - std::cerr << "frontend fetch RF ALU trace top has unconsumed commit rows=" - << pending_commits.size() << "\n"; - return 1; - } - const auto print_bfu_stats = [&]() { - std::cout << "bfu_static_external_comparable=" << bfu_stats.comparable_count - << " bfu_static_external_matches=" << bfu_stats.match_count - << " bfu_resolved_body_end_accepts=" << bfu_stats.resolved_accept_count - << " bfu_body_cut_arm_comparable=" << bfu_stats.cut_arm_comparable_count - << " bfu_body_cut_arm_accepts=" << bfu_stats.cut_arm_accept_count - << " bfu_body_cut_arm_mismatches=" << bfu_stats.cut_arm_mismatch_count - << " bfu_local_body_cut_prefixes=" << bfu_stats.local_body_cut_prefix_count - << " bfu_resolved_source_runtime_selected=" << bfu_stats.resolved_source_runtime_selected_count - << " bfu_resolved_source_replay_selected=" << bfu_stats.resolved_source_replay_selected_count - << " bfu_resolved_source_runtime_feedback=" << bfu_stats.resolved_source_runtime_feedback_count - << " bfu_resolved_source_runtime_pending=" << bfu_stats.resolved_source_runtime_pending_count - << " bfu_resolved_source_runtime_pending_consumes=" - << bfu_stats.resolved_source_runtime_pending_consume_count - << " bfu_resolved_source_runtime_pending_drop_mismatches=" - << bfu_stats.resolved_source_runtime_pending_drop_mismatch_count - << " bfu_resolved_source_runtime_pending_candidate_comparable=" - << bfu_stats.resolved_source_runtime_pending_candidate_comparable_count - << " bfu_resolved_source_runtime_pending_candidate_matches=" - << bfu_stats.resolved_source_runtime_pending_candidate_match_count - << " bfu_resolved_source_runtime_pending_candidate_mismatches=" - << bfu_stats.resolved_source_runtime_pending_candidate_mismatch_count - << " bfu_pending_runtime_candidate_valid=" - << bfu_stats.pending_runtime_candidate_valid_count - << " bfu_pending_runtime_candidate_without_active_header=" - << bfu_stats.pending_runtime_candidate_without_active_header_count - << " bfu_pending_runtime_candidate_active_header_mismatches=" - << bfu_stats.pending_runtime_candidate_active_header_mismatch_count - << " bfu_pending_runtime_candidate_replay_comparable=" - << bfu_stats.pending_runtime_candidate_replay_comparable_count - << " bfu_pending_runtime_candidate_replay_matches=" - << bfu_stats.pending_runtime_candidate_replay_match_count - << " bfu_pending_runtime_candidate_replay_mismatches=" - << bfu_stats.pending_runtime_candidate_replay_mismatch_count - << " bfu_runtime_body_end_oracle_pending=" - << bfu_stats.runtime_body_end_oracle_pending_count - << " bfu_runtime_body_end_oracle_captures=" - << bfu_stats.runtime_body_end_oracle_capture_count - << " bfu_runtime_body_end_oracle_replay_comparable=" - << bfu_stats.runtime_body_end_oracle_replay_comparable_count - << " bfu_runtime_body_end_oracle_replay_matches=" - << bfu_stats.runtime_body_end_oracle_replay_match_count - << " bfu_runtime_body_end_oracle_replay_mismatches=" - << bfu_stats.runtime_body_end_oracle_replay_mismatch_count - << " bfu_runtime_body_end_oracle_overwrites=" - << bfu_stats.runtime_body_end_oracle_overwrite_count - << " bfu_resolved_source_runtime_replay_comparable=" - << bfu_stats.resolved_source_runtime_replay_comparable_count - << " bfu_resolved_source_runtime_replay_matches=" - << bfu_stats.resolved_source_runtime_replay_match_count - << " bfu_resolved_source_runtime_replay_mismatches=" - << bfu_stats.resolved_source_runtime_replay_mismatch_count - << " marker_rows_admitted=" << marker_rows_admitted - << " marker_commits_filtered=" << marker_commits_filtered - << "\n"; - }; - if (captured_tail_superset) { - print_bfu_stats(); - if (!write_replay_liq_sideband_stats(args.sideband_stats)) { - dut.final(); - return 2; - } - dut.final(); - return 0; - } - if (args.allow_residual_replay_liq_wait) { - for (int cycle = 0; cycle < 8; ++cycle) { - eval_with_load_lookup(dut, fetch_memory, "residual replay-liq wait observe"); - tick(dut); - } - print_bfu_stats(); - if (!write_replay_liq_sideband_stats(args.sideband_stats)) { - dut.final(); - return 2; - } - dut.final(); - return 0; - } - drain_empty(dut, fetch_memory); - eval_with_load_lookup(dut, fetch_memory); - if (!dut.io_idle || !dut.io_empty || dut.io_size != 0) { - std::cerr << "frontend fetch RF ALU trace top did not finish idle" - << " idle=" << static_cast(dut.io_idle) - << " empty=" << static_cast(dut.io_empty) - << " size=" << static_cast(dut.io_size) - << "\n"; - return 1; - } - expect_monitor_clean(dut, "post-drain idle window", 0x0, 0); - - print_bfu_stats(); - if (!write_replay_liq_sideband_stats(args.sideband_stats)) { - dut.final(); - return 2; - } - dut.final(); - return 0; -} diff --git a/tools/chisel/frontend_fetch_trace_top_tb.cpp b/tools/chisel/frontend_fetch_trace_top_tb.cpp deleted file mode 100644 index 762abdb0..00000000 --- a/tools/chisel/frontend_fetch_trace_top_tb.cpp +++ /dev/null @@ -1,634 +0,0 @@ -#include "VLinxCoreFrontendFetchTraceTop.h" -#include "verilated.h" - -#include "commit_trace_jsonl.h" - -#include -#include -#include -#include -#include -#include - -namespace { - -using linxcore::chisel::CommitTraceJsonRow; -using linxcore::chisel::write_dut_commit_jsonl; -using linxcore::chisel::write_qemu_commit_jsonl; - -struct Args { - std::string dut_trace; - std::string qemu_trace; -}; - -struct ExpectedRow { - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 4; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; -}; - -struct ObservedRow { - bool valid = false; - std::uint64_t seq = 0; - std::uint64_t cycle = 0; - std::uint8_t slot = 0; - std::uint32_t bid = 0; - std::uint32_t gid = 0; - std::uint32_t rid = 0; - bool rob_valid = false; - bool rob_wrap = false; - std::uint8_t rob_value = 0; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 0; - bool wb_valid = false; - std::uint8_t wb_reg = 0; - std::uint64_t wb_data = 0; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; - bool mem_valid = false; - bool mem_is_store = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint8_t mem_size = 0; - bool trap_valid = false; - std::uint32_t trap_cause = 0; - std::uint64_t trap_arg0 = 0; - std::uint64_t next_pc = 0; -}; - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --dut-trace --qemu-trace \n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--dut-trace" && i + 1 < argc) { - args.dut_trace = argv[++i]; - } else if (arg == "--qemu-trace" && i + 1 < argc) { - args.qemu_trace = argv[++i]; - } else { - usage(argv[0]); - } - } - if (args.dut_trace.empty() || args.qemu_trace.empty()) { - usage(argv[0]); - } - return args; -} - -void clear_inputs(VLinxCoreFrontendFetchTraceTop &dut) { - dut.io_startValid = 0; - dut.io_startPc = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_frontendFlushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 0; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_completeValid = 0; - dut.io_completeRobValue = 0; - dut.io_deallocReady = 1; -} - -void tick(VLinxCoreFrontendFetchTraceTop &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); -} - -void reset(VLinxCoreFrontendFetchTraceTop &dut) { - clear_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - dut.eval(); -} - -std::uint64_t mask_insn(std::uint64_t insn, std::uint8_t len) { - if (len == 2) { - return insn & 0xffffULL; - } - if (len == 4) { - return insn & 0xffff'ffffULL; - } - if (len == 6) { - return insn & 0xffff'ffff'ffffULL; - } - return insn; -} - -std::uint64_t single_instruction_window(std::uint64_t insn, std::uint8_t len) { - std::uint64_t window = mask_insn(insn, len); - if (len < 8) { - window |= 0xfULL << (static_cast(len) * 8U); - } - return window; -} - -void expect_monitor_clean( - const VLinxCoreFrontendFetchTraceTop &dut, - const char *context, - std::uint8_t expected_mask, - std::uint8_t expected_count) { - if (dut.io_commitContractError || dut.io_commitSkippedSlot || - dut.io_commitDuplicateIdentity || dut.io_commitSlotMismatch || - dut.io_commitInvalidSideEffect) { - std::cerr << "commit monitor error during " << context - << " mask=" << static_cast(dut.io_commitMonitorValidMask) - << " count=" << static_cast(dut.io_commitMonitorValidCount) - << " skipped=" << static_cast(dut.io_commitSkippedSlot) - << " duplicate=" << static_cast(dut.io_commitDuplicateIdentity) - << " slot_mismatch=" << static_cast(dut.io_commitSlotMismatch) - << " invalid_side_effect=" << static_cast(dut.io_commitInvalidSideEffect) - << "\n"; - std::exit(1); - } - if (dut.io_commitMonitorValidMask != expected_mask || - dut.io_commitMonitorValidCount != expected_count) { - std::cerr << "commit monitor shape mismatch during " << context - << " expected_mask=" << static_cast(expected_mask) - << " observed_mask=" << static_cast(dut.io_commitMonitorValidMask) - << " expected_count=" << static_cast(expected_count) - << " observed_count=" << static_cast(dut.io_commitMonitorValidCount) - << "\n"; - std::exit(1); - } -} - -ObservedRow read_slot0(const VLinxCoreFrontendFetchTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_0_valid; - row.seq = dut.io_commit_rows_0_seq; - row.cycle = dut.io_commit_rows_0_cycle; - row.slot = dut.io_commit_rows_0_slot; - row.bid = dut.io_commit_rows_0_identity_bid; - row.gid = dut.io_commit_rows_0_identity_gid; - row.rid = dut.io_commit_rows_0_identity_rid; - row.rob_valid = dut.io_commit_rows_0_rob_valid; - row.rob_wrap = dut.io_commit_rows_0_rob_wrap; - row.rob_value = dut.io_commit_rows_0_rob_value; - row.block_bid_valid = dut.io_commit_rows_0_blockBidValid; - row.block_bid = dut.io_commit_rows_0_blockBid; - row.pc = dut.io_commit_rows_0_pc; - row.insn = dut.io_commit_rows_0_insn; - row.len = dut.io_commit_rows_0_len; - row.wb_valid = dut.io_commit_rows_0_wb_valid; - row.wb_reg = dut.io_commit_rows_0_wb_reg; - row.wb_data = dut.io_commit_rows_0_wb_data; - row.src0_valid = dut.io_commit_rows_0_src0_valid; - row.src0_reg = dut.io_commit_rows_0_src0_reg; - row.src0_data = dut.io_commit_rows_0_src0_data; - row.src1_valid = dut.io_commit_rows_0_src1_valid; - row.src1_reg = dut.io_commit_rows_0_src1_reg; - row.src1_data = dut.io_commit_rows_0_src1_data; - row.dst_valid = dut.io_commit_rows_0_dst_valid; - row.dst_reg = dut.io_commit_rows_0_dst_reg; - row.dst_data = dut.io_commit_rows_0_dst_data; - row.mem_valid = dut.io_commit_rows_0_mem_valid; - row.mem_is_store = dut.io_commit_rows_0_mem_isStore; - row.mem_addr = dut.io_commit_rows_0_mem_addr; - row.mem_wdata = dut.io_commit_rows_0_mem_wdata; - row.mem_rdata = dut.io_commit_rows_0_mem_rdata; - row.mem_size = dut.io_commit_rows_0_mem_size; - row.trap_valid = dut.io_commit_rows_0_trap_valid; - row.trap_cause = dut.io_commit_rows_0_trap_cause; - row.trap_arg0 = dut.io_commit_rows_0_trap_arg0; - row.next_pc = dut.io_commit_rows_0_nextPc; - return row; -} - -ObservedRow read_slot1(const VLinxCoreFrontendFetchTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_1_valid; - row.seq = dut.io_commit_rows_1_seq; - row.cycle = dut.io_commit_rows_1_cycle; - row.slot = dut.io_commit_rows_1_slot; - row.bid = dut.io_commit_rows_1_identity_bid; - row.gid = dut.io_commit_rows_1_identity_gid; - row.rid = dut.io_commit_rows_1_identity_rid; - row.rob_valid = dut.io_commit_rows_1_rob_valid; - row.rob_wrap = dut.io_commit_rows_1_rob_wrap; - row.rob_value = dut.io_commit_rows_1_rob_value; - row.block_bid_valid = dut.io_commit_rows_1_blockBidValid; - row.block_bid = dut.io_commit_rows_1_blockBid; - row.pc = dut.io_commit_rows_1_pc; - row.insn = dut.io_commit_rows_1_insn; - row.len = dut.io_commit_rows_1_len; - row.wb_valid = dut.io_commit_rows_1_wb_valid; - row.wb_reg = dut.io_commit_rows_1_wb_reg; - row.wb_data = dut.io_commit_rows_1_wb_data; - row.src0_valid = dut.io_commit_rows_1_src0_valid; - row.src0_reg = dut.io_commit_rows_1_src0_reg; - row.src0_data = dut.io_commit_rows_1_src0_data; - row.src1_valid = dut.io_commit_rows_1_src1_valid; - row.src1_reg = dut.io_commit_rows_1_src1_reg; - row.src1_data = dut.io_commit_rows_1_src1_data; - row.dst_valid = dut.io_commit_rows_1_dst_valid; - row.dst_reg = dut.io_commit_rows_1_dst_reg; - row.dst_data = dut.io_commit_rows_1_dst_data; - row.mem_valid = dut.io_commit_rows_1_mem_valid; - row.mem_is_store = dut.io_commit_rows_1_mem_isStore; - row.mem_addr = dut.io_commit_rows_1_mem_addr; - row.mem_wdata = dut.io_commit_rows_1_mem_wdata; - row.mem_rdata = dut.io_commit_rows_1_mem_rdata; - row.mem_size = dut.io_commit_rows_1_mem_size; - row.trap_valid = dut.io_commit_rows_1_trap_valid; - row.trap_cause = dut.io_commit_rows_1_trap_cause; - row.trap_arg0 = dut.io_commit_rows_1_trap_arg0; - row.next_pc = dut.io_commit_rows_1_nextPc; - return row; -} - -void expect_row(const ObservedRow &observed, const ExpectedRow &expected) { - if (!observed.valid || - observed.slot != 0 || - observed.pc != expected.pc || - mask_insn(observed.insn, observed.len) != mask_insn(expected.insn, expected.len) || - observed.len != expected.len || - observed.wb_valid || - observed.mem_valid || - observed.trap_valid || - observed.src0_valid != expected.src0_valid || - observed.src1_valid != expected.src1_valid || - observed.dst_valid != expected.dst_valid || - observed.next_pc != expected.pc + expected.len) { - std::cerr << "frontend fetch trace top commit row mismatch" - << " pc=0x" << std::hex << observed.pc - << " insn=0x" << observed.insn - << std::dec << " len=" << static_cast(observed.len) - << " src0=(" << observed.src0_valid << "," - << static_cast(observed.src0_reg) << ")" - << " src1=(" << observed.src1_valid << "," - << static_cast(observed.src1_reg) << ")" - << " dst=(" << observed.dst_valid << "," - << static_cast(observed.dst_reg) << ")" - << " next_pc=0x" << std::hex << observed.next_pc << std::dec - << "\n"; - std::exit(1); - } - - if (observed.src0_valid && - (observed.src0_reg != expected.src0_reg || observed.src0_data != 0)) { - std::cerr << "frontend fetch trace top src0 mismatch" - << " expected_reg=" << static_cast(expected.src0_reg) - << " observed_reg=" << static_cast(observed.src0_reg) - << " observed_data=" << observed.src0_data << "\n"; - std::exit(1); - } - if (observed.src1_valid && - (observed.src1_reg != expected.src1_reg || observed.src1_data != 0)) { - std::cerr << "frontend fetch trace top src1 mismatch" - << " expected_reg=" << static_cast(expected.src1_reg) - << " observed_reg=" << static_cast(observed.src1_reg) - << " observed_data=" << observed.src1_data << "\n"; - std::exit(1); - } - if (observed.dst_valid && - (observed.dst_reg != expected.dst_reg || observed.dst_data != 0)) { - std::cerr << "frontend fetch trace top dst mismatch" - << " expected_reg=" << static_cast(expected.dst_reg) - << " observed_reg=" << static_cast(observed.dst_reg) - << " observed_data=" << observed.dst_data << "\n"; - std::exit(1); - } -} - -CommitTraceJsonRow to_json_row(const ObservedRow &row) { - CommitTraceJsonRow json; - json.valid = row.valid; - json.seq = row.seq; - json.cycle = row.cycle; - json.slot = row.slot; - json.bid = row.bid; - json.gid = row.gid; - json.rid = row.rid; - json.rob_valid = row.rob_valid; - json.rob_wrap = row.rob_wrap; - json.rob_value = row.rob_value; - json.block_bid_valid = row.block_bid_valid; - json.block_bid = row.block_bid; - json.pc = row.pc; - json.insn = row.insn; - json.len = row.len; - json.wb_valid = row.wb_valid; - json.wb_rd = row.wb_reg; - json.wb_data = row.wb_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.mem_valid = row.mem_valid; - json.mem_is_store = row.mem_is_store; - json.mem_addr = row.mem_addr; - json.mem_wdata = row.mem_wdata; - json.mem_rdata = row.mem_rdata; - json.mem_size = row.mem_size; - json.trap_valid = row.trap_valid; - json.trap_cause = row.trap_cause; - json.trap_arg0 = row.trap_arg0; - json.next_pc = row.next_pc; - return json; -} - -CommitTraceJsonRow to_json_row(const ExpectedRow &row) { - CommitTraceJsonRow json; - json.pc = row.pc; - json.insn = mask_insn(row.insn, row.len); - json.len = row.len; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.next_pc = row.pc + row.len; - return json; -} - -void write_dut_row(std::ofstream &out, const ObservedRow &row) { - write_dut_commit_jsonl(out, to_json_row(row)); -} - -void write_qemu_row(std::ofstream &out, const ExpectedRow &row) { - write_qemu_commit_jsonl(out, to_json_row(row)); -} - -void start_source(VLinxCoreFrontendFetchTraceTop &dut, std::uint64_t pc) { - clear_inputs(dut); - dut.io_startValid = 1; - dut.io_startPc = pc; - tick(dut); - clear_inputs(dut); - dut.eval(); - if (!dut.io_sourceActive) { - std::cerr << "frontend fetch source did not arm at start pc=0x" - << std::hex << pc << std::dec << "\n"; - std::exit(1); - } -} - -std::uint8_t fetch_and_enqueue_row( - VLinxCoreFrontendFetchTraceTop &dut, - const ExpectedRow &row) { - bool saw_req = false; - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.io_fetchReqReady = 1; - dut.eval(); - if (dut.io_fetchReqValid) { - if (dut.io_fetchReqPc != row.pc || !dut.io_sourceReqFire) { - std::cerr << "frontend fetch request mismatch" - << " expected_pc=0x" << std::hex << row.pc - << " observed_pc=0x" << dut.io_fetchReqPc << std::dec - << " sourceReqFire=" << static_cast(dut.io_sourceReqFire) - << "\n"; - std::exit(1); - } - tick(dut); - saw_req = true; - break; - } - tick(dut); - } - if (!saw_req) { - std::cerr << "frontend fetch source did not issue request for pc=0x" - << std::hex << row.pc << std::dec << "\n"; - std::exit(1); - } - - clear_inputs(dut); - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = single_instruction_window(row.insn, row.len); - dut.eval(); - if (!dut.io_fetchRespReady || !dut.io_sourceRespFire) { - std::cerr << "frontend fetch response was not accepted" - << " pc=0x" << std::hex << row.pc << std::dec - << " respReady=" << static_cast(dut.io_fetchRespReady) - << " sourceRespFire=" << static_cast(dut.io_sourceRespFire) - << "\n"; - std::exit(1); - } - tick(dut); - - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_sourceOutFire) { - if (!dut.io_decodeReady || !dut.io_selectedValid || - dut.io_f4ValidMask != 0x1U || - dut.io_sourceAdvanceBytes != row.len) { - std::cerr << "frontend fetch packet was not accepted by F4/decode path" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << " decodeReady=" << static_cast(dut.io_decodeReady) - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " f4Mask=0x" << std::hex << static_cast(dut.io_f4ValidMask) - << std::dec - << " advanceBytes=" << static_cast(dut.io_sourceAdvanceBytes) - << "\n"; - std::exit(1); - } - const auto rob_value = static_cast(dut.io_selectedRobValue); - tick(dut); - - for (int rename_cycle = 0; rename_cycle < 8; ++rename_cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_renamedAccepted && dut.io_robRenameUpdateFire) { - tick(dut); - clear_inputs(dut); - dut.eval(); - return rob_value; - } - tick(dut); - } - std::cerr << "frontend fetch row did not reach rename/ROB update" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; - std::exit(1); - } - tick(dut); - } - - std::cerr << "frontend fetch packet source did not emit packet" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; - std::exit(1); -} - -void complete_rob_row(VLinxCoreFrontendFetchTraceTop &dut, std::uint8_t rob_value) { - clear_inputs(dut); - dut.io_completeValid = 1; - dut.io_completeRobValue = rob_value; - dut.eval(); - if (dut.io_completeIgnored) { - std::cerr << "completion surrogate was ignored for rob_value=" - << static_cast(rob_value) << "\n"; - std::exit(1); - } - tick(dut); - clear_inputs(dut); - dut.eval(); -} - -void drain_empty(VLinxCoreFrontendFetchTraceTop &dut) { - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_idle && dut.io_empty && dut.io_size == 0) { - return; - } - tick(dut); - } - std::cerr << "frontend fetch trace top did not drain after commit" - << " idle=" << static_cast(dut.io_idle) - << " empty=" << static_cast(dut.io_empty) - << " size=" << static_cast(dut.io_size) - << " outstanding=" << static_cast(dut.io_outstandingCount) - << " sourceWaiting=" << static_cast(dut.io_sourceWaitingResponse) - << " sourcePacket=" << static_cast(dut.io_sourcePacketValid) - << "\n"; - std::exit(1); -} - -void commit_expected_row( - VLinxCoreFrontendFetchTraceTop &dut, - const ExpectedRow &expected, - std::ofstream &dut_out, - std::ofstream &qemu_out) { - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_commit_rows_0_valid) { - const ObservedRow slot0 = read_slot0(dut); - const ObservedRow slot1 = read_slot1(dut); - expect_monitor_clean(dut, "frontend fetch trace top commit", 0x1, 1); - expect_row(slot0, expected); - if (slot1.valid) { - std::cerr << "frontend fetch trace top expected a single-row commit window\n"; - std::exit(1); - } - write_dut_row(dut_out, slot0); - write_dut_row(dut_out, slot1); - write_qemu_row(qemu_out, expected); - tick(dut); - drain_empty(dut); - return; - } - expect_monitor_clean(dut, "frontend fetch trace top wait", 0x0, 0); - tick(dut); - } - - std::cerr << "frontend fetch trace top did not emit a commit row" - << " pc=0x" << std::hex << expected.pc << std::dec << "\n"; - std::exit(1); -} - -std::vector fixture_rows() { - const std::uint64_t add = - 0x00000005ULL | (3ULL << 7) | (4ULL << 15) | (5ULL << 20); - const std::uint64_t addi = - 0x00000015ULL | (6ULL << 7) | (7ULL << 15) | (0x7ffULL << 20); - const std::uint64_t c_movr = - 0x0006ULL | (4ULL << 6) | (5ULL << 11); - - ExpectedRow r0; - r0.pc = 0x1000; - r0.insn = add; - r0.len = 4; - r0.src0_valid = true; - r0.src0_reg = 4; - r0.src1_valid = true; - r0.src1_reg = 5; - r0.dst_valid = true; - r0.dst_reg = 3; - - ExpectedRow r1; - r1.pc = 0x1004; - r1.insn = addi; - r1.len = 4; - r1.src0_valid = true; - r1.src0_reg = 7; - r1.dst_valid = true; - r1.dst_reg = 6; - - ExpectedRow r2; - r2.pc = 0x1008; - r2.insn = c_movr; - r2.len = 2; - r2.src0_valid = true; - r2.src0_reg = 4; - r2.dst_valid = true; - r2.dst_reg = 5; - - return {r0, r1, r2}; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - - VLinxCoreFrontendFetchTraceTop dut; - reset(dut); - - std::ofstream dut_out(args.dut_trace); - std::ofstream qemu_out(args.qemu_trace); - if (!dut_out || !qemu_out) { - std::cerr << "failed to open output traces\n"; - return 2; - } - - const auto rows = fixture_rows(); - start_source(dut, rows.front().pc); - for (const ExpectedRow &row : rows) { - const std::uint8_t rob_value = fetch_and_enqueue_row(dut, row); - complete_rob_row(dut, rob_value); - commit_expected_row(dut, row, dut_out, qemu_out); - } - - dut.eval(); - if (!dut.io_idle || !dut.io_empty || dut.io_size != 0) { - std::cerr << "frontend fetch trace top did not finish idle" - << " idle=" << static_cast(dut.io_idle) - << " empty=" << static_cast(dut.io_empty) - << " size=" << static_cast(dut.io_size) - << "\n"; - return 1; - } - expect_monitor_clean(dut, "post-drain idle window", 0x0, 0); - - dut.final(); - return 0; -} diff --git a/tools/chisel/frontend_trace_top_tb.cpp b/tools/chisel/frontend_trace_top_tb.cpp deleted file mode 100644 index d86f5e85..00000000 --- a/tools/chisel/frontend_trace_top_tb.cpp +++ /dev/null @@ -1,560 +0,0 @@ -#include "VLinxCoreFrontendTraceTop.h" -#include "verilated.h" - -#include "commit_trace_jsonl.h" - -#include -#include -#include -#include -#include -#include - -namespace { - -using linxcore::chisel::CommitTraceJsonRow; -using linxcore::chisel::write_dut_commit_jsonl; -using linxcore::chisel::write_qemu_commit_jsonl; - -struct Args { - std::string dut_trace; - std::string qemu_trace; -}; - -struct ExpectedRow { - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 4; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; -}; - -struct ObservedRow { - bool valid = false; - std::uint64_t seq = 0; - std::uint64_t cycle = 0; - std::uint8_t slot = 0; - std::uint32_t bid = 0; - std::uint32_t gid = 0; - std::uint32_t rid = 0; - bool rob_valid = false; - bool rob_wrap = false; - std::uint8_t rob_value = 0; - bool block_bid_valid = false; - std::uint64_t block_bid = 0; - std::uint64_t pc = 0; - std::uint64_t insn = 0; - std::uint8_t len = 0; - bool wb_valid = false; - std::uint8_t wb_reg = 0; - std::uint64_t wb_data = 0; - bool src0_valid = false; - std::uint8_t src0_reg = 0; - std::uint64_t src0_data = 0; - bool src1_valid = false; - std::uint8_t src1_reg = 0; - std::uint64_t src1_data = 0; - bool dst_valid = false; - std::uint8_t dst_reg = 0; - std::uint64_t dst_data = 0; - bool mem_valid = false; - bool mem_is_store = false; - std::uint64_t mem_addr = 0; - std::uint64_t mem_wdata = 0; - std::uint64_t mem_rdata = 0; - std::uint8_t mem_size = 0; - bool trap_valid = false; - std::uint32_t trap_cause = 0; - std::uint64_t trap_arg0 = 0; - std::uint64_t next_pc = 0; -}; - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 - << " --dut-trace --qemu-trace \n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--dut-trace" && i + 1 < argc) { - args.dut_trace = argv[++i]; - } else if (arg == "--qemu-trace" && i + 1 < argc) { - args.qemu_trace = argv[++i]; - } else { - usage(argv[0]); - } - } - if (args.dut_trace.empty() || args.qemu_trace.empty()) { - usage(argv[0]); - } - return args; -} - -void clear_inputs(VLinxCoreFrontendTraceTop &dut) { - dut.io_in_valid = 0; - dut.io_in_peId = 0; - dut.io_in_threadId = 0; - dut.io_in_pc = 0; - dut.io_in_window = 0; - dut.io_in_pktUid = 0; - dut.io_in_checkpointId = 0; - dut.io_frontendFlushValid = 0; - dut.io_completeValid = 0; - dut.io_completeRobValue = 0; - dut.io_deallocReady = 1; -} - -void tick(VLinxCoreFrontendTraceTop &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); -} - -void reset(VLinxCoreFrontendTraceTop &dut) { - clear_inputs(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - dut.eval(); -} - -std::uint64_t mask_insn(std::uint64_t insn, std::uint8_t len) { - if (len == 2) { - return insn & 0xffffULL; - } - if (len == 4) { - return insn & 0xffff'ffffULL; - } - if (len == 6) { - return insn & 0xffff'ffff'ffffULL; - } - return insn; -} - -void expect_monitor_clean( - const VLinxCoreFrontendTraceTop &dut, - const char *context, - std::uint8_t expected_mask, - std::uint8_t expected_count) { - if (dut.io_commitContractError || dut.io_commitSkippedSlot || - dut.io_commitDuplicateIdentity || dut.io_commitSlotMismatch || - dut.io_commitInvalidSideEffect) { - std::cerr << "commit monitor error during " << context - << " mask=" << static_cast(dut.io_commitMonitorValidMask) - << " count=" << static_cast(dut.io_commitMonitorValidCount) - << " skipped=" << static_cast(dut.io_commitSkippedSlot) - << " duplicate=" << static_cast(dut.io_commitDuplicateIdentity) - << " slot_mismatch=" << static_cast(dut.io_commitSlotMismatch) - << " invalid_side_effect=" << static_cast(dut.io_commitInvalidSideEffect) - << "\n"; - std::exit(1); - } - if (dut.io_commitMonitorValidMask != expected_mask || - dut.io_commitMonitorValidCount != expected_count) { - std::cerr << "commit monitor shape mismatch during " << context - << " expected_mask=" << static_cast(expected_mask) - << " observed_mask=" << static_cast(dut.io_commitMonitorValidMask) - << " expected_count=" << static_cast(expected_count) - << " observed_count=" << static_cast(dut.io_commitMonitorValidCount) - << "\n"; - std::exit(1); - } -} - -ObservedRow read_slot0(const VLinxCoreFrontendTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_0_valid; - row.seq = dut.io_commit_rows_0_seq; - row.cycle = dut.io_commit_rows_0_cycle; - row.slot = dut.io_commit_rows_0_slot; - row.bid = dut.io_commit_rows_0_identity_bid; - row.gid = dut.io_commit_rows_0_identity_gid; - row.rid = dut.io_commit_rows_0_identity_rid; - row.rob_valid = dut.io_commit_rows_0_rob_valid; - row.rob_wrap = dut.io_commit_rows_0_rob_wrap; - row.rob_value = dut.io_commit_rows_0_rob_value; - row.block_bid_valid = dut.io_commit_rows_0_blockBidValid; - row.block_bid = dut.io_commit_rows_0_blockBid; - row.pc = dut.io_commit_rows_0_pc; - row.insn = dut.io_commit_rows_0_insn; - row.len = dut.io_commit_rows_0_len; - row.wb_valid = dut.io_commit_rows_0_wb_valid; - row.wb_reg = dut.io_commit_rows_0_wb_reg; - row.wb_data = dut.io_commit_rows_0_wb_data; - row.src0_valid = dut.io_commit_rows_0_src0_valid; - row.src0_reg = dut.io_commit_rows_0_src0_reg; - row.src0_data = dut.io_commit_rows_0_src0_data; - row.src1_valid = dut.io_commit_rows_0_src1_valid; - row.src1_reg = dut.io_commit_rows_0_src1_reg; - row.src1_data = dut.io_commit_rows_0_src1_data; - row.dst_valid = dut.io_commit_rows_0_dst_valid; - row.dst_reg = dut.io_commit_rows_0_dst_reg; - row.dst_data = dut.io_commit_rows_0_dst_data; - row.mem_valid = dut.io_commit_rows_0_mem_valid; - row.mem_is_store = dut.io_commit_rows_0_mem_isStore; - row.mem_addr = dut.io_commit_rows_0_mem_addr; - row.mem_wdata = dut.io_commit_rows_0_mem_wdata; - row.mem_rdata = dut.io_commit_rows_0_mem_rdata; - row.mem_size = dut.io_commit_rows_0_mem_size; - row.trap_valid = dut.io_commit_rows_0_trap_valid; - row.trap_cause = dut.io_commit_rows_0_trap_cause; - row.trap_arg0 = dut.io_commit_rows_0_trap_arg0; - row.next_pc = dut.io_commit_rows_0_nextPc; - return row; -} - -ObservedRow read_slot1(const VLinxCoreFrontendTraceTop &dut) { - ObservedRow row; - row.valid = dut.io_commit_rows_1_valid; - row.seq = dut.io_commit_rows_1_seq; - row.cycle = dut.io_commit_rows_1_cycle; - row.slot = dut.io_commit_rows_1_slot; - row.bid = dut.io_commit_rows_1_identity_bid; - row.gid = dut.io_commit_rows_1_identity_gid; - row.rid = dut.io_commit_rows_1_identity_rid; - row.rob_valid = dut.io_commit_rows_1_rob_valid; - row.rob_wrap = dut.io_commit_rows_1_rob_wrap; - row.rob_value = dut.io_commit_rows_1_rob_value; - row.block_bid_valid = dut.io_commit_rows_1_blockBidValid; - row.block_bid = dut.io_commit_rows_1_blockBid; - row.pc = dut.io_commit_rows_1_pc; - row.insn = dut.io_commit_rows_1_insn; - row.len = dut.io_commit_rows_1_len; - row.wb_valid = dut.io_commit_rows_1_wb_valid; - row.wb_reg = dut.io_commit_rows_1_wb_reg; - row.wb_data = dut.io_commit_rows_1_wb_data; - row.src0_valid = dut.io_commit_rows_1_src0_valid; - row.src0_reg = dut.io_commit_rows_1_src0_reg; - row.src0_data = dut.io_commit_rows_1_src0_data; - row.src1_valid = dut.io_commit_rows_1_src1_valid; - row.src1_reg = dut.io_commit_rows_1_src1_reg; - row.src1_data = dut.io_commit_rows_1_src1_data; - row.dst_valid = dut.io_commit_rows_1_dst_valid; - row.dst_reg = dut.io_commit_rows_1_dst_reg; - row.dst_data = dut.io_commit_rows_1_dst_data; - row.mem_valid = dut.io_commit_rows_1_mem_valid; - row.mem_is_store = dut.io_commit_rows_1_mem_isStore; - row.mem_addr = dut.io_commit_rows_1_mem_addr; - row.mem_wdata = dut.io_commit_rows_1_mem_wdata; - row.mem_rdata = dut.io_commit_rows_1_mem_rdata; - row.mem_size = dut.io_commit_rows_1_mem_size; - row.trap_valid = dut.io_commit_rows_1_trap_valid; - row.trap_cause = dut.io_commit_rows_1_trap_cause; - row.trap_arg0 = dut.io_commit_rows_1_trap_arg0; - row.next_pc = dut.io_commit_rows_1_nextPc; - return row; -} - -void expect_row(const ObservedRow &observed, const ExpectedRow &expected) { - if (!observed.valid || - observed.slot != 0 || - observed.pc != expected.pc || - mask_insn(observed.insn, observed.len) != mask_insn(expected.insn, expected.len) || - observed.len != expected.len || - observed.wb_valid || - observed.mem_valid || - observed.trap_valid || - observed.src0_valid != expected.src0_valid || - observed.src1_valid != expected.src1_valid || - observed.dst_valid != expected.dst_valid || - observed.next_pc != expected.pc + expected.len) { - std::cerr << "frontend trace top commit row mismatch" - << " pc=0x" << std::hex << observed.pc - << " insn=0x" << observed.insn - << std::dec << " len=" << static_cast(observed.len) - << " src0=(" << observed.src0_valid << "," - << static_cast(observed.src0_reg) << ")" - << " src1=(" << observed.src1_valid << "," - << static_cast(observed.src1_reg) << ")" - << " dst=(" << observed.dst_valid << "," - << static_cast(observed.dst_reg) << ")" - << " next_pc=0x" << std::hex << observed.next_pc << std::dec - << "\n"; - std::exit(1); - } - - if (observed.src0_valid && - (observed.src0_reg != expected.src0_reg || observed.src0_data != 0)) { - std::cerr << "frontend trace top src0 mismatch" - << " expected_reg=" << static_cast(expected.src0_reg) - << " observed_reg=" << static_cast(observed.src0_reg) - << " observed_data=" << observed.src0_data << "\n"; - std::exit(1); - } - if (observed.src1_valid && - (observed.src1_reg != expected.src1_reg || observed.src1_data != 0)) { - std::cerr << "frontend trace top src1 mismatch" - << " expected_reg=" << static_cast(expected.src1_reg) - << " observed_reg=" << static_cast(observed.src1_reg) - << " observed_data=" << observed.src1_data << "\n"; - std::exit(1); - } - if (observed.dst_valid && - (observed.dst_reg != expected.dst_reg || observed.dst_data != 0)) { - std::cerr << "frontend trace top dst mismatch" - << " expected_reg=" << static_cast(expected.dst_reg) - << " observed_reg=" << static_cast(observed.dst_reg) - << " observed_data=" << observed.dst_data << "\n"; - std::exit(1); - } -} - -CommitTraceJsonRow to_json_row(const ObservedRow &row) { - CommitTraceJsonRow json; - json.valid = row.valid; - json.seq = row.seq; - json.cycle = row.cycle; - json.slot = row.slot; - json.bid = row.bid; - json.gid = row.gid; - json.rid = row.rid; - json.rob_valid = row.rob_valid; - json.rob_wrap = row.rob_wrap; - json.rob_value = row.rob_value; - json.block_bid_valid = row.block_bid_valid; - json.block_bid = row.block_bid; - json.pc = row.pc; - json.insn = row.insn; - json.len = row.len; - json.wb_valid = row.wb_valid; - json.wb_rd = row.wb_reg; - json.wb_data = row.wb_data; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src0_data = row.src0_data; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.src1_data = row.src1_data; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.dst_data = row.dst_data; - json.mem_valid = row.mem_valid; - json.mem_is_store = row.mem_is_store; - json.mem_addr = row.mem_addr; - json.mem_wdata = row.mem_wdata; - json.mem_rdata = row.mem_rdata; - json.mem_size = row.mem_size; - json.trap_valid = row.trap_valid; - json.trap_cause = row.trap_cause; - json.trap_arg0 = row.trap_arg0; - json.next_pc = row.next_pc; - return json; -} - -CommitTraceJsonRow to_json_row(const ExpectedRow &row) { - CommitTraceJsonRow json; - json.pc = row.pc; - json.insn = mask_insn(row.insn, row.len); - json.len = row.len; - json.src0_valid = row.src0_valid; - json.src0_reg = row.src0_reg; - json.src1_valid = row.src1_valid; - json.src1_reg = row.src1_reg; - json.dst_valid = row.dst_valid; - json.dst_reg = row.dst_reg; - json.next_pc = row.pc + row.len; - return json; -} - -void write_dut_row(std::ofstream &out, const ObservedRow &row) { - write_dut_commit_jsonl(out, to_json_row(row)); -} - -void write_qemu_row(std::ofstream &out, const ExpectedRow &row) { - write_qemu_commit_jsonl(out, to_json_row(row)); -} - -std::uint8_t enqueue_frontend_row( - VLinxCoreFrontendTraceTop &dut, - const ExpectedRow &row, - std::uint64_t pkt_uid) { - clear_inputs(dut); - dut.io_in_valid = 1; - dut.io_in_pc = row.pc; - dut.io_in_window = mask_insn(row.insn, row.len); - dut.io_in_pktUid = pkt_uid; - dut.io_in_checkpointId = pkt_uid & 0x3fU; - dut.eval(); - - if (!dut.io_decodeReady || !dut.io_selectedValid || ((dut.io_f4ValidMask & 0x1U) == 0)) { - std::cerr << "frontend row was not accepted by F4/decode path" - << " pc=0x" << std::hex << row.pc - << " insn=0x" << row.insn << std::dec - << " decodeReady=" << static_cast(dut.io_decodeReady) - << " selectedValid=" << static_cast(dut.io_selectedValid) - << " f4Mask=0x" << std::hex << static_cast(dut.io_f4ValidMask) - << std::dec << "\n"; - std::exit(1); - } - const auto rob_value = static_cast(dut.io_selectedRobValue); - tick(dut); - - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_renamedAccepted && dut.io_robRenameUpdateFire) { - tick(dut); - clear_inputs(dut); - dut.eval(); - return rob_value; - } - tick(dut); - } - - std::cerr << "frontend row did not reach rename/ROB update" - << " pc=0x" << std::hex << row.pc << std::dec << "\n"; - std::exit(1); -} - -void complete_rob_row(VLinxCoreFrontendTraceTop &dut, std::uint8_t rob_value) { - clear_inputs(dut); - dut.io_completeValid = 1; - dut.io_completeRobValue = rob_value; - dut.eval(); - if (dut.io_completeIgnored) { - std::cerr << "completion surrogate was ignored for rob_value=" - << static_cast(rob_value) << "\n"; - std::exit(1); - } - tick(dut); - clear_inputs(dut); - dut.eval(); -} - -void drain_empty(VLinxCoreFrontendTraceTop &dut) { - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_empty && dut.io_size == 0) { - return; - } - tick(dut); - } - std::cerr << "frontend trace top did not drain after commit" - << " size=" << static_cast(dut.io_size) - << " outstanding=" << static_cast(dut.io_outstandingCount) - << "\n"; - std::exit(1); -} - -void commit_expected_row( - VLinxCoreFrontendTraceTop &dut, - const ExpectedRow &expected, - std::ofstream &dut_out, - std::ofstream &qemu_out) { - for (int cycle = 0; cycle < 8; ++cycle) { - clear_inputs(dut); - dut.eval(); - if (dut.io_commit_rows_0_valid) { - const ObservedRow slot0 = read_slot0(dut); - const ObservedRow slot1 = read_slot1(dut); - expect_monitor_clean(dut, "frontend trace top commit", 0x1, 1); - expect_row(slot0, expected); - if (slot1.valid) { - std::cerr << "frontend trace top expected a single-row commit window\n"; - std::exit(1); - } - write_dut_row(dut_out, slot0); - write_dut_row(dut_out, slot1); - write_qemu_row(qemu_out, expected); - tick(dut); - drain_empty(dut); - return; - } - expect_monitor_clean(dut, "frontend trace top wait", 0x0, 0); - tick(dut); - } - - std::cerr << "frontend trace top did not emit a commit row" - << " pc=0x" << std::hex << expected.pc << std::dec << "\n"; - std::exit(1); -} - -std::vector fixture_rows() { - const std::uint64_t add = - 0x00000005ULL | (3ULL << 7) | (4ULL << 15) | (5ULL << 20); - const std::uint64_t addi = - 0x00000015ULL | (6ULL << 7) | (7ULL << 15) | (0x7ffULL << 20); - const std::uint64_t c_movr = - 0x0006ULL | (4ULL << 6) | (5ULL << 11); - - ExpectedRow r0; - r0.pc = 0x1000; - r0.insn = add; - r0.len = 4; - r0.src0_valid = true; - r0.src0_reg = 4; - r0.src1_valid = true; - r0.src1_reg = 5; - r0.dst_valid = true; - r0.dst_reg = 3; - - ExpectedRow r1; - r1.pc = 0x1004; - r1.insn = addi; - r1.len = 4; - r1.src0_valid = true; - r1.src0_reg = 7; - r1.dst_valid = true; - r1.dst_reg = 6; - - ExpectedRow r2; - r2.pc = 0x1008; - r2.insn = c_movr; - r2.len = 2; - r2.src0_valid = true; - r2.src0_reg = 4; - r2.dst_valid = true; - r2.dst_reg = 5; - - return {r0, r1, r2}; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - - VLinxCoreFrontendTraceTop dut; - reset(dut); - - std::ofstream dut_out(args.dut_trace); - std::ofstream qemu_out(args.qemu_trace); - if (!dut_out || !qemu_out) { - std::cerr << "failed to open output traces\n"; - return 2; - } - - const auto rows = fixture_rows(); - for (std::size_t i = 0; i < rows.size(); ++i) { - const std::uint8_t rob_value = enqueue_frontend_row(dut, rows[i], i); - complete_rob_row(dut, rob_value); - commit_expected_row(dut, rows[i], dut_out, qemu_out); - } - - dut.eval(); - if (!dut.io_idle || !dut.io_empty || dut.io_size != 0) { - std::cerr << "frontend trace top did not finish idle" - << " idle=" << static_cast(dut.io_idle) - << " empty=" << static_cast(dut.io_empty) - << " size=" << static_cast(dut.io_size) - << "\n"; - return 1; - } - expect_monitor_clean(dut, "post-drain idle window", 0x0, 0); - - dut.final(); - return 0; -} diff --git a/tools/chisel/load_miss_queue_probe_tb.cpp b/tools/chisel/load_miss_queue_probe_tb.cpp index 821e4ee5..12f7f32e 100644 --- a/tools/chisel/load_miss_queue_probe_tb.cpp +++ b/tools/chisel/load_miss_queue_probe_tb.cpp @@ -44,6 +44,10 @@ void clear_inputs(VLoadMissQueueProbe &dut) { dut.io_missStid = 0; dut.io_missBid = 0; dut.io_missLsIdFull = 0; + dut.io_missAttemptGeneration = 0; + dut.io_cancelValid = 0; + dut.io_cancelIndex = 0; + dut.io_cancelAttemptGeneration = 0; dut.io_requestReady = 0; dut.io_responseValid = 0; dut.io_responseMissValid = 0; @@ -56,13 +60,15 @@ void clear_inputs(VLoadMissQueueProbe &dut) { } void drive_miss(VLoadMissQueueProbe &dut, uint32_t index, uint64_t line, - uint32_t stid, uint32_t bid, uint64_t lsid) { + uint32_t stid, uint32_t bid, uint64_t lsid, + uint32_t attempt_generation = 0) { dut.io_missValid = 1; dut.io_missIndex = index; dut.io_missLineAddr = line; dut.io_missStid = stid; dut.io_missBid = bid; dut.io_missLsIdFull = lsid; + dut.io_missAttemptGeneration = attempt_generation; eval(dut); expect(dut.io_missReady, "miss must be ready"); expect(dut.io_missAccepted, "miss must be accepted"); @@ -143,6 +149,62 @@ int main(int argc, char **argv) { dut.io_responseMissValid = 0; expect(!dut.io_pending, "matching response must free entry"); + drive_miss(dut, 5, 0x1400, 0, 5, 0x505, 7); + const uint32_t old_attempt_slot = dut.io_requestMissSlot; + const bool old_attempt_generation = dut.io_requestMissGeneration; + dut.io_requestReady = 1; + eval(dut); + expect(dut.io_requestAccepted, "old-attempt request must issue"); + tick(dut); + dut.io_requestReady = 0; + + dut.io_cancelValid = 1; + dut.io_cancelIndex = 5; + dut.io_cancelAttemptGeneration = 7; + eval(dut); + expect(dut.io_cancelReady && dut.io_cancelAccepted, + "exact old attempt must cancel atomically"); + tick(dut); + dut.io_cancelValid = 0; + expect((dut.io_orphanMask & (1u << old_attempt_slot)) != 0, + "issued canceled attempt must remain as a response tombstone"); + + drive_miss(dut, 5, 0x1400, 0, 5, 0x505, 8); + expect(dut.io_requestValid, + "new attempt must allocate independently of the old tombstone"); + const uint32_t new_attempt_slot = dut.io_requestMissSlot; + const bool new_attempt_generation = dut.io_requestMissGeneration; + expect(new_attempt_slot != old_attempt_slot || + new_attempt_generation != old_attempt_generation, + "new attempt must use a distinct lower-memory identity"); + dut.io_requestReady = 1; + eval(dut); + expect(dut.io_requestAccepted, "new-attempt request must issue before old response"); + tick(dut); + dut.io_requestReady = 0; + + dut.io_responseValid = 1; + dut.io_responseMissValid = 1; + dut.io_responseMissSlot = old_attempt_slot; + dut.io_responseMissGeneration = old_attempt_generation; + dut.io_responseLineAddr = 0x1400; + eval(dut); + expect(dut.io_responseMatched && !dut.io_refillValid, + "old-attempt response must drain without refill"); + tick(dut); + expect((dut.io_issuedMask & (1u << new_attempt_slot)) != 0, + "old-attempt response must preserve the new request"); + + dut.io_responseMissSlot = new_attempt_slot; + dut.io_responseMissGeneration = new_attempt_generation; + eval(dut); + expect(dut.io_responseMatched && dut.io_refillValid, + "new-attempt response must publish the sole refill"); + tick(dut); + dut.io_responseValid = 0; + dut.io_responseMissValid = 0; + expect(!dut.io_pending, "new-attempt response must release the replay miss"); + dut.io_responseValid = 1; eval(dut); expect(dut.io_responseStale && dut.io_protocolError, diff --git a/tools/chisel/lrsc_natural_crosscheck.py b/tools/chisel/lrsc_natural_crosscheck.py index 08e06925..293db48a 100755 --- a/tools/chisel/lrsc_natural_crosscheck.py +++ b/tools/chisel/lrsc_natural_crosscheck.py @@ -19,7 +19,7 @@ LINX_ROOT = ROOT_DIR.parents[1] LLVM_BIN = LINX_ROOT / "compiler/llvm/build-linxisa-clang/bin" QEMU_TRACE_RUNNER = ROOT_DIR / "tools/qemu/run_qemu_commit_trace.sh" -NATURAL_RUNNER = ROOT_DIR / "tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh" +NATURAL_RUNNER = ROOT_DIR / "tools/chisel/run_top_natural.sh" TEXT_BASE = 0x10000 DATA_BASE = 0x11000 @@ -216,7 +216,24 @@ def summarize_trace(path: Path, engine: str) -> TraceSummary: if not path.exists() or path.stat().st_size == 0: return TraceSummary(engine, path, "fail", 0, 0, 0, 0, 0, None, None, ("missing or empty trace",)) - for row in iter_jsonl(path): + rows = list(iter_jsonl(path)) + memory_requests: dict[tuple[int, int], list[dict[str, Any]]] = {} + requests_by_value: dict[int, set[int]] = {} + for row in rows: + if row.get("event") != "memory_request" or row.get("command") != "Write": + continue + transaction = row.get("transaction") + if not isinstance(transaction, dict): + errors.append("memory request is missing transaction identity") + continue + key = (int(transaction.get("value", -1)), + int(transaction.get("generation", -1))) + memory_requests.setdefault(key, []).append(row) + requests_by_value.setdefault(key[0], set()).add(key[1]) + + for row in rows: + if row.get("event") == "memory_request": + continue pc = int(row.get("pc", -1)) if pc < PC_LO or pc > PC_HI: continue @@ -239,8 +256,36 @@ def summarize_trace(path: Path, engine: str) -> TraceSummary: else: errors.append(f"SC.W at pc=0x{pc:x} wrote unsupported status 0x{wb_data:x}") elif is_swi(insn) and int(row.get("mem_valid", 0)) and int(row.get("mem_is_store", 0)): + if row.get("event") != "commit": + # Legacy QEMU rows contain the committed store data directly. + ordinary_conflict_stores += 1 + final_memory = int(row.get("mem_wdata", 0)) & 0xFFFFFFFF + continue + transaction = row.get("transaction") + if not isinstance(transaction, dict): + errors.append(f"ordinary store at pc=0x{pc:x} is missing transaction identity") + continue + key = (int(transaction.get("value", -1)), + int(transaction.get("generation", -1))) + matches = memory_requests.get(key, []) + if not matches: + generations = requests_by_value.get(key[0], set()) + if generations: + errors.append( + f"memory request generation mismatch for transaction " + f"value={key[0]}: commit={key[1]}, requests={sorted(generations)}") + else: + errors.append( + f"missing memory request for transaction value={key[0]} " + f"generation={key[1]}") + continue + if len(matches) != 1: + errors.append( + f"duplicate memory request for transaction value={key[0]} " + f"generation={key[1]}: count={len(matches)}") + continue ordinary_conflict_stores += 1 - final_memory = int(row.get("mem_wdata", 0)) & 0xFFFFFFFF + final_memory = int(matches[0].get("data", 0)) & 0xFFFFFFFF if lr_w < 2: errors.append(f"expected at least 2 LR.W rows, saw {lr_w}") @@ -313,7 +358,8 @@ def run_qemu(elf: Path, build_dir: Path, qemu_seconds: int) -> tuple[dict[str, A def run_chisel(elf: Path, build_dir: Path, max_cycles: int) -> tuple[dict[str, Any], TraceSummary]: chisel_dir = build_dir / "chisel-natural" - trace = chisel_dir / "traces/dut.commit.jsonl" + manifest = chisel_dir / "report/natural_manifest.json" + trace = chisel_dir / "report/commit.jsonl" command = [ str(NATURAL_RUNNER), "--elf", @@ -322,10 +368,14 @@ def run_chisel(elf: Path, build_dir: Path, max_cycles: int) -> tuple[dict[str, A str(chisel_dir), "--max-cycles", str(max_cycles), + "--manifest", + str(manifest), + "--commit-trace", + str(trace), ] result = run(command) summary = summarize_trace(trace, "chisel") - if result.returncode != 0 and summary.row_count == 0: + if result.returncode != 0: summary = TraceSummary( engine="chisel", trace=trace, @@ -337,7 +387,8 @@ def run_chisel(elf: Path, build_dir: Path, max_cycles: int) -> tuple[dict[str, A ordinary_conflict_stores=summary.ordinary_conflict_stores, first_lr_wb_data=summary.first_lr_wb_data, final_memory=summary.final_memory, - errors=summary.errors + (f"natural runner failed with returncode {result.returncode}",), + errors=summary.errors + + (f"natural runner failed with returncode {result.returncode}",), ) meta = { "command": command, diff --git a/tools/chisel/lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb.cpp b/tools/chisel/lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb.cpp deleted file mode 100644 index 0fb3978e..00000000 --- a/tools/chisel/lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb.cpp +++ /dev/null @@ -1,418 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedStoreStaAddressExecHlSdiPrProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpHlSdiPo = 216; -constexpr std::uint32_t kOpHlSdiPr = 217; -constexpr std::uint32_t kOpHlSdiUpr = 220; -constexpr std::uint32_t kOpSb = 386; -constexpr std::uint32_t kOpSdi = 390; -constexpr std::uint8_t kStoreTypeAll = 0; -constexpr std::uint8_t kStoreTypeAddr = 1; -constexpr std::uint8_t kStoreTypeData = 2; -constexpr int kStableCycles = 5; - -struct Case { - const char *name; - std::uint32_t opcode; - std::uint64_t raw; - std::int32_t simm; - std::uint64_t base; - std::uint64_t src_d_data; - std::uint8_t src_d_arch; - std::uint8_t src_d_phys; - std::uint8_t src_r_arch; - std::uint8_t src_r_phys; - std::uint64_t pc; - std::uint8_t pe; - std::uint8_t thread; - bool bid_wrap; - std::uint8_t bid; - bool gid_wrap; - std::uint8_t gid; - bool rid_wrap; - std::uint8_t rid; - std::uint32_t lsid; -}; - -void fail(const std::string &message) { - std::cerr << "lsu-reduced-store-sta-address-exec-hl-sdi-pr-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -std::uint64_t mask64(std::uint64_t value) { - return value; -} - -std::int32_t sign_extend_17(std::uint32_t value) { - const std::uint32_t masked = value & 0x1ffffU; - return (masked & 0x10000U) != 0 ? static_cast(masked | 0xfffe0000U) - : static_cast(masked); -} - -std::uint32_t raw_simm17(std::uint64_t raw) { - return static_cast((((raw >> 6) & 0x1fULL) << 12) | - (((raw >> 23) & 0x1fULL) << 7) | - ((raw >> 41) & 0x7fULL)); -} - -std::uint64_t scaled_simm17(std::int32_t simm) { - return mask64(static_cast(static_cast(simm)) << 3); -} - -std::uint64_t expected_pr_address(const Case &c) { - require(sign_extend_17(raw_simm17(c.raw)) == c.simm, std::string(c.name) + ": raw simm17 decode mismatch"); - return mask64(c.base + scaled_simm17(c.simm)); -} - -std::uint64_t hl_sdi_raw(std::uint32_t opcode, std::uint8_t dst, std::uint8_t src_d, - std::uint8_t src_r, std::int32_t simm) { - const std::uint32_t imm = static_cast(simm) & 0x1ffffU; - std::uint64_t fixed = 0; - switch (opcode) { - case kOpHlSdiPo: - fixed = 0x3059003eULL; - break; - case kOpHlSdiPr: - fixed = 0x3059002eULL; - break; - case kOpHlSdiUpr: - fixed = 0x7059002eULL; - break; - default: - fail("unsupported HL.SDI raw builder opcode"); - } - return fixed | - (static_cast((imm >> 12) & 0x1fU) << 6) | - (static_cast(dst & 0x1fU) << 11) | - (static_cast((imm >> 7) & 0x1fU) << 23) | - (static_cast(src_d & 0x1fU) << 35) | - (static_cast(imm & 0x7fU) << 41); -} - -std::uint64_t sdi_raw(std::uint8_t src_d, std::uint8_t src_r, std::int16_t simm) { - const std::uint16_t imm = static_cast(simm) & 0x0fffU; - return (static_cast((imm >> 5) & 0x7fU) << 25) | - (static_cast(src_d & 0x1fU) << 20) | - (static_cast(src_r & 0x1fU) << 15) | - (static_cast(imm & 0x1fU) << 7) | - 0x3059ULL; -} - -std::uint64_t sb_raw(std::uint8_t src_d, std::uint8_t src_l, std::uint8_t src_r) { - return (static_cast(src_d & 0x1fU) << 20) | - (static_cast(src_l & 0x1fU) << 15) | - (static_cast(src_r & 0x1fU) << 7) | - 0x06000049ULL; -} - -void eval(VReducedStoreStaAddressExecHlSdiPrProbe &dut) { - dut.eval(); -} - -void idle(VReducedStoreStaAddressExecHlSdiPrProbe &dut) { - dut.io_enable = 0; - dut.io_queueValid = 0; - dut.io_payloadValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_storeType = kStoreTypeAddr; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_lsid = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_srcValid_0 = 0; - dut.io_srcValid_1 = 0; - dut.io_srcValid_2 = 0; - dut.io_srcReady_0 = 1; - dut.io_srcReady_1 = 1; - dut.io_srcReady_2 = 1; - dut.io_srcData_0 = 0; - dut.io_srcData_1 = 0; - dut.io_srcData_2 = 0; - dut.io_srcArchTag_0 = 1; - dut.io_srcArchTag_1 = 2; - dut.io_srcArchTag_2 = 3; - dut.io_srcPhysTag_0 = 21; - dut.io_srcPhysTag_1 = 22; - dut.io_srcPhysTag_2 = 23; -} - -void drive_case(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c, - std::uint32_t opcode = kOpHlSdiPr, std::uint8_t store_type = kStoreTypeAddr, - bool enable = true, bool queue_valid = true, bool payload_valid = true, - bool src0_valid = true, bool src0_ready = true, bool src1_valid = true, - bool src1_ready = true, bool src2_valid = false, bool src2_ready = true) { - idle(dut); - dut.io_enable = enable ? 1 : 0; - dut.io_queueValid = queue_valid ? 1 : 0; - dut.io_payloadValid = payload_valid ? 1 : 0; - dut.io_opcode = opcode; - dut.io_pc = c.pc; - dut.io_insnRaw = c.raw; - dut.io_imm = static_cast(static_cast(c.simm)); - dut.io_storeType = store_type; - dut.io_peId = c.pe; - dut.io_threadId = c.thread; - dut.io_lsid = c.lsid; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_srcValid_0 = src0_valid ? 1 : 0; - dut.io_srcReady_0 = src0_ready ? 1 : 0; - dut.io_srcData_0 = c.src_d_data; - dut.io_srcValid_1 = src1_valid ? 1 : 0; - dut.io_srcReady_1 = src1_ready ? 1 : 0; - dut.io_srcData_1 = c.base; - dut.io_srcValid_2 = src2_valid ? 1 : 0; - dut.io_srcReady_2 = src2_ready ? 1 : 0; - dut.io_srcData_2 = 0xfeedfacecafebeefULL; - dut.io_srcArchTag_0 = c.src_d_arch; - dut.io_srcArchTag_1 = c.src_r_arch; - dut.io_srcArchTag_2 = 3; - dut.io_srcPhysTag_0 = c.src_d_phys; - dut.io_srcPhysTag_1 = c.src_r_phys; - dut.io_srcPhysTag_2 = 33; - eval(dut); -} - -std::vector cases() { - return { - {"hl_sdi_pr_real_dhrystone_raw_minus16_first_red", kOpHlSdiPr, 0xfc15bfd90feeULL, -2, 0x0000004000001000ULL, 0x1122334455667788ULL, 2, 20, 28, 21, 0x100c8ULL, 1, 2, false, 21, true, 31, false, 10, 0x85700001U}, - {"hl_sdi_pr_zero_offset", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 5, 6, 7, 0), 0, 0x0000000000008000ULL, 0xa5a55a5ac3c33c3cULL, 6, 23, 7, 24, 0x17008ULL, 2, 3, true, 22, false, 32, true, 11, 0x85700002U}, - {"hl_sdi_pr_positive_offset", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 8, 9, 10, 31), 31, 0x0000000000009000ULL, 0x0102030405060708ULL, 9, 26, 10, 27, 0x17010ULL, 3, 4, false, 23, false, 33, true, 12, 0x85700003U}, - {"hl_sdi_pr_negative_boundary", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 11, 12, 13, -65536), -65536, 0x0000000000100000ULL, 0xfedcba9876543210ULL, 12, 29, 13, 30, 0x17018ULL, 4, 5, true, 24, true, 34, false, 13, 0x85700004U}, - {"hl_sdi_pr_positive_boundary_wrap", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 16, 15, 16, 65535), 65535, 0xfffffffffffffff8ULL, 0x8877665544332211ULL, 15, 32, 16, 33, 0x17020ULL, 5, 6, false, 25, true, 35, true, 14, 0x85700005U}, - }; -} - -void require_oracle_self_checks(const std::vector &all) { - require(!all.empty(), "oracle setup produced no HL.SDI.PR cases"); - require(all.front().raw == 0xfc15bfd90feeULL, "oracle real raw case bytes changed"); - require(all.front().simm == -2, "oracle real raw case expected simm changed"); - require(sign_extend_17(raw_simm17(all.front().raw)) == -2, - "oracle real raw bytes did not decode to simm -2"); - - for (const Case &c : all) { - require(c.opcode == kOpHlSdiPr, std::string(c.name) + ": non-HL.SDI.PR case in PR matrix"); - require(c.src_r_arch != c.src_d_arch, std::string(c.name) + ": source arch tags must distinguish SrcD/SrcR"); - require(c.src_r_phys != c.src_d_phys, std::string(c.name) + ": source phys tags must distinguish SrcD/SrcR"); - require(sign_extend_17(raw_simm17(c.raw)) == c.simm, std::string(c.name) + ": case raw/simm mismatch"); - require(expected_pr_address(c) == mask64(c.base + scaled_simm17(c.simm)), - std::string(c.name) + ": expected address calculator mismatch"); - } - - const std::int32_t round_trip_simms[] = {0, 1, -1, 31, -32, 65535, -65536, -2}; - for (std::int32_t simm : round_trip_simms) { - const std::uint64_t raw = hl_sdi_raw(kOpHlSdiPr, 3, 4, 5, simm); - require(sign_extend_17(raw_simm17(raw)) == simm, "oracle synthetic HL.SDI.PR raw round trip failed"); - } - - const Case scaled_cases[] = { - {"oracle_scaled_positive", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 1, 2, 3, 7), 7, - 0x1000ULL, 0, 2, 20, 3, 21, 0, 0, 0, false, 0, false, 0, false, 0, 0}, - {"oracle_scaled_negative", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 1, 2, 3, -2), -2, - 0x1000ULL, 0, 2, 20, 3, 21, 0, 0, 0, false, 0, false, 0, false, 0, 0}, - {"oracle_scaled_wrap", kOpHlSdiPr, hl_sdi_raw(kOpHlSdiPr, 1, 2, 3, 1), 1, - 0xfffffffffffffff8ULL, 0, 2, 20, 3, 21, 0, 0, 0, false, 0, false, 0, false, 0, 0}, - }; - require(expected_pr_address(scaled_cases[0]) == 0x1038ULL, "oracle positive scaled address mismatch"); - require(expected_pr_address(scaled_cases[1]) == 0xff0ULL, "oracle negative scaled address mismatch"); - require(expected_pr_address(scaled_cases[2]) == 0, "oracle wrapping scaled address mismatch"); -} - -void require_common_inputs(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c, const std::string &name) { - require(dut.io_queueOpcode == c.opcode, name + ": queue opcode mismatch"); - require(dut.io_queueInsnRaw == c.raw, name + ": raw instruction was not preserved"); - require(dut.io_queueImm == static_cast(static_cast(c.simm)), - name + ": sign-extended immediate was not preserved"); - require(dut.io_queueStoreType == kStoreTypeAddr, name + ": store type was not Addr"); - require(dut.io_queueSrcValid_0 && dut.io_queueSrcReady_0, name + ": SrcD source was not preserved"); - require(dut.io_queueSrcValid_1 && dut.io_queueSrcReady_1, name + ": SrcR/base source was not valid-ready"); - require(!dut.io_queueSrcValid_2 && dut.io_queueSrcReady_2, name + ": unexpected source 2 dependency"); - require(dut.io_queueSrcData_0 == c.src_d_data, name + ": SrcD data mismatch"); - require(dut.io_queueSrcData_1 == c.base, name + ": SrcR/base data mismatch"); - require(dut.io_queueSrcArchTag_0 == c.src_d_arch && dut.io_queueSrcArchTag_1 == c.src_r_arch, - name + ": source arch tag mismatch"); - require(dut.io_queueSrcPhysTag_0 == c.src_d_phys && dut.io_queueSrcPhysTag_1 == c.src_r_phys, - name + ": source phys tag mismatch"); -} - -void require_no_fabricated_exec(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const std::string &name) { - require(!dut.io_execValid, name + ": fabricated execValid before support"); - require(dut.io_execAddr == 0, name + ": fabricated exec address before support"); - require(dut.io_execData == 0, name + ": fabricated exec data before support"); - require(dut.io_execSize == 0, name + ": fabricated exec size before support"); -} - -void require_future_green_exec(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c) { - require(dut.io_candidate, std::string(c.name) + ": candidate was false"); - require(dut.io_supportedOpcode, std::string(c.name) + ": supportedOpcode was false"); - require(dut.io_addrSourceMask == 0x2, std::string(c.name) + ": addrSourceMask was not 0b010"); - require(dut.io_addrSourceReady, std::string(c.name) + ": addrSourceReady was false"); - require(!dut.io_blockedBySource, std::string(c.name) + ": blockedBySource was true"); - require(!dut.io_blockedByUnsupported, std::string(c.name) + ": blockedByUnsupported was true"); - require(dut.io_execValid, std::string(c.name) + ": execValid was false"); - require(dut.io_execAddr == expected_pr_address(c), std::string(c.name) + ": OP_HL_SDI_PR address mismatch"); - require(dut.io_execData == 0, std::string(c.name) + ": STA exec data must remain zero"); - require(dut.io_execSize == 8, std::string(c.name) + ": OP_HL_SDI_PR STA size must be eight bytes"); - require(dut.io_execPeId == c.pe, std::string(c.name) + ": PE identity mismatch"); - require(dut.io_execStid == c.thread && dut.io_execTid == c.thread, std::string(c.name) + ": thread identity mismatch"); - require(!dut.io_execStackValid, std::string(c.name) + ": stackValid mutated"); - require(dut.io_execScalarIex, std::string(c.name) + ": scalarIex was not preserved"); - require(dut.io_execSimtLane == 0, std::string(c.name) + ": simt lane mutated"); -} - -bool first_red_or_future_green(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c) { - drive_case(dut, c); - require_common_inputs(dut, c, c.name); - require(dut.io_candidate, "first-red OP_HL_SDI_PR was not an Addr candidate"); - if (dut.io_supportedOpcode) { - require_future_green_exec(dut, c); - return true; - } - require(dut.io_addrSourceMask == 0, "current-red OP_HL_SDI_PR source mask was not zero"); - require(dut.io_addrSourceReady, "current-red OP_HL_SDI_PR should be vacuously source-ready with mask zero"); - require(dut.io_blockedByUnsupported, "current-red OP_HL_SDI_PR did not assert blockedByUnsupported"); - require(!dut.io_blockedBySource, "current-red OP_HL_SDI_PR asserted blockedBySource"); - require_no_fabricated_exec(dut, "current-red OP_HL_SDI_PR"); - fail("current OP_HL_SDI_PR 217 is candidate=true but supported=false with no exec row; expected current-red wrapper should invert this nonzero status only for R857"); - return false; -} - -void require_stable_future_green(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kStableCycles; ++cycle) { - eval(dut); - require_future_green_exec(dut, c); - } -} - -void run_gating_case(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c, const std::string &name, - bool enable, bool queue_valid, bool payload_valid, std::uint8_t store_type) { - drive_case(dut, c, kOpHlSdiPr, store_type, enable, queue_valid, payload_valid); - require(!dut.io_candidate, name + ": disabled queue still reported candidate"); - require(!dut.io_execValid, name + ": disabled queue still reported execValid"); - require(!dut.io_blockedByUnsupported, name + ": disabled queue reported unsupported block"); -} - -void run_source_block_case(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c, - bool src1_valid, bool src1_ready) { - drive_case(dut, c, kOpHlSdiPr, kStoreTypeAddr, true, true, true, true, true, src1_valid, src1_ready); - if (dut.io_supportedOpcode) { - require(dut.io_candidate, "source block future path lost candidate"); - require(dut.io_addrSourceMask == 0x2, "source block future path lost OP_HL_SDI_PR source mask"); - require(!dut.io_addrSourceReady, "source block future path reported ready with missing selected source"); - require(dut.io_blockedBySource, "source block future path did not assert blockedBySource"); - require(!dut.io_blockedByUnsupported, "source block future path reported unsupported"); - require(!dut.io_execValid, "source block future path emitted exec with missing source"); - } else { - require(dut.io_blockedByUnsupported, "source block current path lost unsupported first-red"); - require(!dut.io_blockedBySource, "current unsupported path must not report source block before OP_HL_SDI_PR support"); - } -} - -void run_srcd_not_ready_case(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &c) { - drive_case(dut, c, kOpHlSdiPr, kStoreTypeAddr, true, true, true, true, false, true, true); - if (dut.io_supportedOpcode) { - require_future_green_exec(dut, c); - } -} - -void run_adjacent_case(VReducedStoreStaAddressExecHlSdiPrProbe &dut, const Case &base, std::uint32_t opcode, - std::uint64_t raw, std::int32_t simm, bool expect_supported, - std::uint64_t expected_addr, std::uint32_t expected_size, - std::uint32_t expected_mask) { - Case c = base; - c.name = "adjacent"; - c.opcode = opcode; - c.raw = raw; - c.simm = simm; - drive_case(dut, c, opcode, kStoreTypeAddr, true, true, true, true, true, true, true, - (expected_mask & 0x4U) != 0, true); - require(dut.io_candidate, "adjacent case lost candidate"); - require(dut.io_supportedOpcode == expect_supported, "adjacent supportedOpcode mismatch"); - if (expect_supported) { - require(dut.io_addrSourceMask == expected_mask, "adjacent source mask mismatch"); - require(dut.io_addrSourceReady, "adjacent supported case was source-blocked"); - require(!dut.io_blockedBySource, "adjacent supported case reported source block"); - require(!dut.io_blockedByUnsupported, "adjacent supported case reported unsupported"); - require(dut.io_execValid, "adjacent supported case did not emit exec"); - require(dut.io_execAddr == expected_addr, "adjacent address mismatch"); - require(dut.io_execSize == expected_size, "adjacent size mismatch"); - require(dut.io_execData == 0, "adjacent STA data changed"); - } else { - require(dut.io_addrSourceMask == 0, "adjacent unsupported source mask was not zero"); - require(dut.io_blockedByUnsupported, "adjacent unsupported case did not block as unsupported"); - require(!dut.io_execValid, "adjacent unsupported case emitted exec"); - } -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedStoreStaAddressExecHlSdiPrProbe dut; - - const std::vector all = cases(); - require_oracle_self_checks(all); - const bool first_completed = first_red_or_future_green(dut, all.front()); - if (!first_completed) { - return 1; - } - - for (const Case &c : all) { - drive_case(dut, c); - require_common_inputs(dut, c, c.name); - require_stable_future_green(dut, c); - } - - run_gating_case(dut, all[1], "enable false", false, true, true, kStoreTypeAddr); - run_gating_case(dut, all[1], "queueValid false", true, false, true, kStoreTypeAddr); - run_gating_case(dut, all[1], "payload valid false", true, true, false, kStoreTypeAddr); - run_gating_case(dut, all[1], "storeType All", true, true, true, kStoreTypeAll); - run_gating_case(dut, all[1], "storeType Data", true, true, true, kStoreTypeData); - run_source_block_case(dut, all[2], false, true); - run_source_block_case(dut, all[2], true, false); - run_srcd_not_ready_case(dut, all[3]); - - run_adjacent_case(dut, all[3], kOpSdi, sdi_raw(3, 4, -4), -4, true, - all[3].base + scaled_simm17(-4), 8, 0x2); - run_adjacent_case(dut, all[3], kOpSb, sb_raw(3, 4, 5), 0, true, - all[3].base + 0xfeedfacecafebeefULL, 1, 0x6); - run_adjacent_case(dut, all[3], kOpHlSdiPo, hl_sdi_raw(kOpHlSdiPo, 3, 4, 5, 7), 7, - false, 0, 0, 0); - run_adjacent_case(dut, all[3], kOpHlSdiUpr, hl_sdi_raw(kOpHlSdiUpr, 17, 18, 19, -9), -9, - false, 0, 0, 0); - - std::cout << "lsu-reduced-store-sta-address-exec-hl-sdi-pr-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/lsu_reduced_store_sta_address_exec_sb_probe_tb.cpp b/tools/chisel/lsu_reduced_store_sta_address_exec_sb_probe_tb.cpp deleted file mode 100644 index 6c6a70d1..00000000 --- a/tools/chisel/lsu_reduced_store_sta_address_exec_sb_probe_tb.cpp +++ /dev/null @@ -1,346 +0,0 @@ -#include -#include -#include -#include -#include - -#include "VReducedStoreStaAddressExecSbProbe.h" -#include "verilated.h" - -namespace { - -constexpr std::uint32_t kOpSb = 386; -constexpr std::uint32_t kOpSbi = 387; -constexpr std::uint32_t kOpSd = 389; -constexpr std::uint32_t kOpHlSbPcr = 442; -constexpr std::uint32_t kOpCSwi = 583; -constexpr std::uint32_t kOpUnsupported = 0xfff; -constexpr int kStableCycles = 5; -constexpr std::uint8_t kStoreTypeAll = 0; -constexpr std::uint8_t kStoreTypeAddr = 1; -constexpr std::uint8_t kStoreTypeData = 2; - -struct Case { - const char *name; - std::uint64_t base; - std::uint64_t offset; - std::uint8_t src_r_type; - std::uint64_t pc; - std::uint64_t insn; - std::uint8_t pe; - std::uint8_t thread; - bool bid_wrap; - std::uint8_t bid; - bool gid_wrap; - std::uint8_t gid; - bool rid_wrap; - std::uint8_t rid; - std::uint32_t lsid; -}; - -void fail(const std::string &message) { - std::cerr << "lsu-reduced-store-sta-address-exec-sb-probe: " << message << '\n'; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -bool explicit_current_inversion() { - const char *value = std::getenv("EXPECT_CURRENT_UNSUPPORTED"); - return value != nullptr && std::string(value) == "1"; -} - -std::uint64_t sext32(std::uint64_t value) { - const std::uint32_t low = static_cast(value & 0xffffffffULL); - return static_cast(static_cast(static_cast(low))); -} - -std::uint64_t zext32(std::uint64_t value) { - return value & 0xffffffffULL; -} - -std::uint64_t apply_src_r_type(std::uint64_t value, std::uint8_t src_r_type) { - switch (src_r_type & 0x3U) { - case 0: - return sext32(value); - case 1: - return zext32(value); - case 2: - return 0ULL - value; - default: - return value; - } -} - -std::uint64_t expected_address(const Case &c) { - return c.base + apply_src_r_type(c.offset, c.src_r_type); -} - -std::uint64_t insn_for_case(const Case &c) { - return (static_cast(c.src_r_type & 0x3U) << 25) | - 0x49ULL | - (static_cast(c.insn) & ~0x06000049ULL); -} - -void eval(VReducedStoreStaAddressExecSbProbe &dut) { - dut.eval(); -} - -void idle(VReducedStoreStaAddressExecSbProbe &dut) { - dut.io_enable = 0; - dut.io_queueValid = 0; - dut.io_payloadValid = 0; - dut.io_opcode = 0; - dut.io_pc = 0; - dut.io_insnRaw = 0; - dut.io_imm = 0; - dut.io_storeType = kStoreTypeAddr; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_lsid = 0; - dut.io_bidValid = 1; - dut.io_bidWrap = 0; - dut.io_bidValue = 0; - dut.io_gidValid = 1; - dut.io_gidWrap = 0; - dut.io_gidValue = 0; - dut.io_ridValid = 1; - dut.io_ridWrap = 0; - dut.io_ridValue = 0; - dut.io_srcValid_0 = 0; - dut.io_srcValid_1 = 0; - dut.io_srcValid_2 = 0; - dut.io_srcReady_0 = 1; - dut.io_srcReady_1 = 1; - dut.io_srcReady_2 = 1; - dut.io_srcData_0 = 0; - dut.io_srcData_1 = 0; - dut.io_srcData_2 = 0; - dut.io_srcArchTag_0 = 1; - dut.io_srcArchTag_1 = 2; - dut.io_srcArchTag_2 = 3; - dut.io_srcPhysTag_0 = 21; - dut.io_srcPhysTag_1 = 22; - dut.io_srcPhysTag_2 = 23; -} - -void drive_case(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, std::uint32_t opcode = kOpSb, - std::uint8_t store_type = kStoreTypeAddr, bool enable = true, bool queue_valid = true, - bool payload_valid = true, bool src1_valid = true, bool src1_ready = true, - bool src2_valid = true, bool src2_ready = true, bool src0_valid = false, - bool src0_ready = true, std::uint64_t src0_data = 0) { - idle(dut); - dut.io_enable = enable ? 1 : 0; - dut.io_queueValid = queue_valid ? 1 : 0; - dut.io_payloadValid = payload_valid ? 1 : 0; - dut.io_opcode = opcode; - dut.io_pc = c.pc; - dut.io_insnRaw = insn_for_case(c); - dut.io_imm = 0x14; - dut.io_storeType = store_type; - dut.io_peId = c.pe; - dut.io_threadId = c.thread; - dut.io_lsid = c.lsid; - dut.io_bidValid = 1; - dut.io_bidWrap = c.bid_wrap ? 1 : 0; - dut.io_bidValue = c.bid; - dut.io_gidValid = 1; - dut.io_gidWrap = c.gid_wrap ? 1 : 0; - dut.io_gidValue = c.gid; - dut.io_ridValid = 1; - dut.io_ridWrap = c.rid_wrap ? 1 : 0; - dut.io_ridValue = c.rid; - dut.io_srcValid_0 = src0_valid ? 1 : 0; - dut.io_srcReady_0 = src0_ready ? 1 : 0; - dut.io_srcData_0 = src0_data; - dut.io_srcValid_1 = src1_valid ? 1 : 0; - dut.io_srcReady_1 = src1_ready ? 1 : 0; - dut.io_srcData_1 = c.base; - dut.io_srcValid_2 = src2_valid ? 1 : 0; - dut.io_srcReady_2 = src2_ready ? 1 : 0; - dut.io_srcData_2 = c.offset; - dut.io_srcArchTag_0 = 1; - dut.io_srcArchTag_1 = 2; - dut.io_srcArchTag_2 = 3; - dut.io_srcPhysTag_0 = 31; - dut.io_srcPhysTag_1 = 32; - dut.io_srcPhysTag_2 = 33; - eval(dut); -} - -std::vector cases() { - return { - {"sb_zero_addr_zero_data_sext32_first_red", 0x0000000000000000ULL, 0x0000000000000000ULL, 0, 0x1298eULL, 0x49ULL, 1, 2, false, 3, true, 4, false, 5, 0x81300001U}, - {"sb_nonzero_base_zero_offset_raw", 0x0000000000004080ULL, 0x0000000000000000ULL, 3, 0x12992ULL, 0x6000049ULL, 2, 3, true, 6, false, 7, true, 8, 0x81300002U}, - {"sb_sign_extend_negative_offset", 0x0000000000005000ULL, 0x00000000fffffff8ULL, 0, 0x12996ULL, 0x49ULL, 3, 4, false, 9, false, 10, true, 11, 0x81300003U}, - {"sb_zero_extend_upper_ignored", 0x0000000000006000ULL, 0xffffffff00000024ULL, 1, 0x1299aULL, 0x2000049ULL, 4, 5, true, 12, true, 13, false, 14, 0x81300004U}, - {"sb_negated_offset_wrap", 0xfffffffffffffff0ULL, 0x0000000000000020ULL, 2, 0x1299eULL, 0x4000049ULL, 5, 6, false, 15, false, 16, true, 17, 0x81300005U}, - }; -} - -void require_common_inputs(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, const std::string &name) { - require(dut.io_queueOpcode == kOpSb, name + ": queue opcode was not OP_SB 386"); - require(dut.io_queueInsnRaw == insn_for_case(c), name + ": raw instruction was not preserved"); - require(dut.io_queueStoreType == kStoreTypeAddr, name + ": store type was not Addr"); - require(!dut.io_queueSrcValid_0, name + ": STA source 0 data owner should remain invalid"); - require(dut.io_queueSrcValid_1 && dut.io_queueSrcReady_1, name + ": SrcL was not valid-ready"); - require(dut.io_queueSrcValid_2 && dut.io_queueSrcReady_2, name + ": SrcR was not valid-ready"); - require(dut.io_queueSrcData_0 == 0, name + ": source 0 data was not zero"); - require(dut.io_queueSrcData_1 == c.base, name + ": SrcL data mismatch"); - require(dut.io_queueSrcData_2 == c.offset, name + ": SrcR data mismatch"); - require(dut.io_queueSrcArchTag_1 == 2 && dut.io_queueSrcArchTag_2 == 3, name + ": source arch tag mismatch"); - require(dut.io_queueSrcPhysTag_1 == 32 && dut.io_queueSrcPhysTag_2 == 33, name + ": source phys tag mismatch"); -} - -void require_no_fabricated_exec(VReducedStoreStaAddressExecSbProbe &dut, const std::string &name) { - require(!dut.io_execValid, name + ": fabricated execValid before support"); - require(dut.io_execAddr == 0, name + ": fabricated exec address before support"); - require(dut.io_execData == 0, name + ": fabricated exec data before support"); - require(dut.io_execSize == 0, name + ": fabricated exec size before support"); -} - -void require_future_green_exec(VReducedStoreStaAddressExecSbProbe &dut, const Case &c) { - require(dut.io_candidate, std::string(c.name) + ": candidate was false"); - require(dut.io_supportedOpcode, std::string(c.name) + ": supportedOpcode was false"); - require(dut.io_addrSourceMask == 0x6, std::string(c.name) + ": addrSourceMask was not 0b110"); - require(dut.io_addrSourceReady, std::string(c.name) + ": addrSourceReady was false"); - require(!dut.io_blockedBySource, std::string(c.name) + ": blockedBySource was true"); - require(!dut.io_blockedByUnsupported, std::string(c.name) + ": blockedByUnsupported was true"); - require(dut.io_execValid, std::string(c.name) + ": execValid was false"); - require(dut.io_execAddr == expected_address(c), std::string(c.name) + ": OP_SB address mismatch"); - require(dut.io_execData == 0, std::string(c.name) + ": STA exec data must remain zero"); - require(dut.io_execSize == 1, std::string(c.name) + ": OP_SB STA size must be one byte"); - require(dut.io_execPeId == c.pe, std::string(c.name) + ": PE identity mismatch"); - require(dut.io_execStid == c.thread && dut.io_execTid == c.thread, std::string(c.name) + ": thread identity mismatch"); - require(!dut.io_execStackValid, std::string(c.name) + ": stackValid mutated"); - require(dut.io_execScalarIex, std::string(c.name) + ": scalarIex was not preserved"); - require(dut.io_execSimtLane == 0, std::string(c.name) + ": simt lane mutated"); -} - -bool first_red_or_future_green(VReducedStoreStaAddressExecSbProbe &dut, const Case &c) { - drive_case(dut, c); - require_common_inputs(dut, c, c.name); - require(dut.io_candidate, "first-red OP_SB was not an Addr candidate"); - if (dut.io_supportedOpcode) { - require_future_green_exec(dut, c); - return true; - } - require(dut.io_addrSourceMask == 0, "current-red OP_SB source mask was not zero"); - require(dut.io_addrSourceReady, "current-red OP_SB should be vacuously source-ready with mask zero"); - require(dut.io_blockedByUnsupported, "current-red OP_SB did not assert blockedByUnsupported"); - require(!dut.io_blockedBySource, "current-red OP_SB asserted blockedBySource"); - require_no_fabricated_exec(dut, "current-red OP_SB"); - if (!explicit_current_inversion()) { - fail("current OP_SB 386 is candidate=true but supported=false with no exec row; rerun with EXPECT_CURRENT_UNSUPPORTED=1 only for current-red inversion"); - } - std::cerr << "lsu-reduced-store-sta-address-exec-sb-probe: first-red OP_SB 386 candidate true but supported false, source mask zero, exec invalid, blockedByUnsupported true\n"; - return false; -} - -void require_stable_future_green(VReducedStoreStaAddressExecSbProbe &dut, const Case &c) { - for (int cycle = 0; cycle < kStableCycles; ++cycle) { - eval(dut); - require_future_green_exec(dut, c); - } -} - -void run_gating_case(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, const std::string &name, - bool enable, bool queue_valid, bool payload_valid, std::uint8_t store_type) { - drive_case(dut, c, kOpSb, store_type, enable, queue_valid, payload_valid); - require(!dut.io_candidate, name + ": disabled queue still reported candidate"); - require(!dut.io_execValid, name + ": disabled queue still reported execValid"); - require(!dut.io_blockedByUnsupported, name + ": disabled queue reported unsupported block"); -} - -void run_source_block_case(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, bool src1_valid, - bool src1_ready, bool src2_valid, bool src2_ready) { - drive_case(dut, c, kOpSb, kStoreTypeAddr, true, true, true, src1_valid, src1_ready, src2_valid, src2_ready); - if (dut.io_supportedOpcode) { - require(dut.io_candidate, "source block future path lost candidate"); - require(dut.io_addrSourceMask == 0x6, "source block future path lost OP_SB source mask"); - require(!dut.io_addrSourceReady, "source block future path reported ready with a missing selected source"); - require(dut.io_blockedBySource, "source block future path did not assert blockedBySource"); - require(!dut.io_execValid, "source block future path emitted exec with missing source"); - } else { - require(dut.io_blockedByUnsupported, "source block current path lost unsupported first-red"); - require(!dut.io_blockedBySource, "current unsupported path must not report source block before OP_SB support"); - } -} - -void run_adjacent_case(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, std::uint32_t opcode, - bool expect_supported, std::uint64_t expected_addr, std::uint32_t expected_size, - std::uint32_t expected_mask, bool src0_valid = false, bool src0_ready = true, - std::uint64_t src0_data = 0) { - drive_case(dut, c, opcode, kStoreTypeAddr, true, true, true, true, true, true, true, src0_valid, - src0_ready, src0_data); - require(dut.io_candidate, "adjacent case lost candidate"); - require(dut.io_supportedOpcode == expect_supported, "adjacent supportedOpcode mismatch"); - if (expect_supported) { - require(dut.io_addrSourceMask == expected_mask, "adjacent source mask mismatch"); - require(dut.io_addrSourceReady, "adjacent supported case was source-blocked"); - require(!dut.io_blockedBySource, "adjacent supported case reported source block"); - require(dut.io_execValid, "adjacent supported case did not emit exec"); - require(dut.io_execAddr == expected_addr, "adjacent address mismatch"); - require(dut.io_execSize == expected_size, "adjacent size mismatch"); - require(dut.io_execData == 0, "adjacent STA data changed"); - } else { - require(dut.io_blockedByUnsupported, "adjacent unsupported case did not block as unsupported"); - require(!dut.io_execValid, "adjacent unsupported case emitted exec"); - } -} - -void run_compressed_source_block_case(VReducedStoreStaAddressExecSbProbe &dut, const Case &c, - const std::string &name, bool src0_valid, bool src0_ready) { - drive_case(dut, c, kOpCSwi, kStoreTypeAddr, true, true, true, true, true, true, true, src0_valid, - src0_ready, c.base); - require(dut.io_candidate, name + ": compressed store lost candidate"); - require(dut.io_supportedOpcode, name + ": compressed store lost support"); - require(dut.io_addrSourceMask == 0x1, name + ": compressed store source mask was not 0b001"); - require(!dut.io_addrSourceReady, name + ": compressed store reported ready with missing source0"); - require(dut.io_blockedBySource, name + ": compressed store did not assert source block"); - require(!dut.io_blockedByUnsupported, name + ": compressed store incorrectly reported unsupported"); - require(!dut.io_execValid, name + ": compressed store emitted exec with missing source0"); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedStoreStaAddressExecSbProbe dut; - - const std::vector all = cases(); - const bool first_completed = first_red_or_future_green(dut, all.front()); - if (!first_completed) { - return 0; - } - - for (const Case &c : all) { - drive_case(dut, c); - require_common_inputs(dut, c, c.name); - require_stable_future_green(dut, c); - } - - run_gating_case(dut, all[1], "enable false", false, true, true, kStoreTypeAddr); - run_gating_case(dut, all[1], "queueValid false", true, false, true, kStoreTypeAddr); - run_gating_case(dut, all[1], "payload valid false", true, true, false, kStoreTypeAddr); - run_gating_case(dut, all[1], "storeType Data", true, true, true, kStoreTypeData); - run_source_block_case(dut, all[2], false, true, true, true); - run_source_block_case(dut, all[2], true, false, true, true); - run_source_block_case(dut, all[2], true, true, false, true); - run_source_block_case(dut, all[2], true, true, true, false); - run_adjacent_case(dut, all[3], kOpSbi, true, all[3].base + 0x14ULL, 1, 0x2); - run_adjacent_case(dut, all[3], kOpSd, true, all[3].base + (all[3].offset << 3), 8, 0x6); - run_adjacent_case(dut, all[3], kOpHlSbPcr, true, all[3].pc + 0x14ULL, 1, 0x0); - run_adjacent_case(dut, all[3], kOpCSwi, true, all[3].base + (0x14ULL << 2), 4, 0x1, true, - true, all[3].base); - run_compressed_source_block_case(dut, all[3], "compressed source0 invalid", false, true); - run_compressed_source_block_case(dut, all[3], "compressed source0 not ready", true, false); - run_adjacent_case(dut, all[3], kOpUnsupported, false, 0, 0, 0); - - std::cout << "lsu-reduced-store-sta-address-exec-sb-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/ooo_iex_lsu_activation_tb.cpp b/tools/chisel/ooo_iex_lsu_activation_tb.cpp new file mode 100644 index 00000000..7fc4f49d --- /dev/null +++ b/tools/chisel/ooo_iex_lsu_activation_tb.cpp @@ -0,0 +1,559 @@ +#include "VOOOIEXLSUActivationProbe.h" +#include "verilated.h" + +#include +#include +#include +#include + +namespace { +struct Instruction { + const char* name; + uint64_t raw; + uint8_t length; + uint8_t stid; + uint64_t pc; +}; + +void tick(VOOOIEXLSUActivationProbe& dut) { + dut.clock = 0; + dut.eval(); + dut.clock = 1; + dut.eval(); +} + +void clear_program(VOOOIEXLSUActivationProbe& dut) { + dut.io_program_valid = 0; + dut.io_program_bits_count = 0; +} + +bool send(VOOOIEXLSUActivationProbe& dut, const Instruction& instruction, + uint64_t instruction_id, uint16_t epoch) { + clear_program(dut); + dut.io_program_bits_count = 3; +#define DRIVE_ENTRY(LANE, RAW, LENGTH, PC, ID) \ + dut.io_program_bits_entries_##LANE##_kind = 0; \ + dut.io_program_bits_entries_##LANE##_parent_identity_peId = 1; \ + dut.io_program_bits_entries_##LANE##_parent_identity_stid = \ + instruction.stid; \ + dut.io_program_bits_entries_##LANE##_parent_identity_instructionId = ID; \ + dut.io_program_bits_entries_##LANE##_parent_identity_epoch = epoch; \ + dut.io_program_bits_entries_##LANE##_parent_pc = PC; \ + dut.io_program_bits_entries_##LANE##_parent_instruction = RAW; \ + dut.io_program_bits_entries_##LANE##_parent_lengthBytes = LENGTH; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_valid = 1; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_predictionTag = \ + ID; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_transactionId = \ + ID; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_checkpointId = \ + ID & 3; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_requestPc = PC; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_taken = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_target = PC + 4; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_fallthroughPc = \ + PC + LENGTH; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_kind = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_provider = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_confidence = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_epoch = epoch; \ + dut.io_program_bits_entries_##LANE##_parent_fetchFault = 0; \ + dut.io_program_bits_entries_##LANE##_parent_fetchFaultCause = 0 + const uint64_t marker_id = instruction_id * 3; + DRIVE_ENTRY(0, 0x1001ULL, 4, instruction.pc - 4, marker_id); + DRIVE_ENTRY(1, instruction.raw, instruction.length, instruction.pc, + marker_id + 1); + DRIVE_ENTRY(2, 0x1ULL, 4, instruction.pc + instruction.length, + marker_id + 2); +#undef DRIVE_ENTRY + dut.io_program_valid = 1; + for (int cycle = 0; cycle < 80; ++cycle) { + dut.eval(); + if (dut.io_program_ready) { + tick(dut); + clear_program(dut); + return true; + } + tick(dut); + } + std::cerr << "timeout admitting " << instruction.name + << " ingress=" << dut.io_ingressCount + << " bootstrap=" << dut.io_bootstrapInitCount + << " alu=" << dut.io_aluCount << " bru=" << dut.io_bruCount + << " agu=" << dut.io_aguCount << " std=" << dut.io_stdCount + << " resolve=" << dut.io_resolveCount + << " rf=" << dut.io_rfWriteCount + << " branch=" << dut.io_branchCount + << " load=" << dut.io_loadCount + << " memory=" << dut.io_memoryCount + << " commit=" << dut.io_commitCount + << " stid0=" << dut.io_stid0Progress + << " stid1=" << dut.io_stid1Progress + << " dispatchStall=" << dut.io_dispatchStallCount + << " trace=" << dut.io_traceCount << '\n'; + clear_program(dut); + return false; +} + +bool send_system_cmd_block(VOOOIEXLSUActivationProbe& dut, + uint64_t instruction_id, uint16_t epoch) { + clear_program(dut); + dut.io_program_bits_count = 4; +#define DRIVE_SYSTEM_CMD_ENTRY(LANE, RAW, PC) \ + dut.io_program_bits_entries_##LANE##_kind = 0; \ + dut.io_program_bits_entries_##LANE##_parent_identity_peId = 1; \ + dut.io_program_bits_entries_##LANE##_parent_identity_stid = 0; \ + dut.io_program_bits_entries_##LANE##_parent_identity_instructionId = \ + instruction_id + LANE; \ + dut.io_program_bits_entries_##LANE##_parent_identity_epoch = epoch; \ + dut.io_program_bits_entries_##LANE##_parent_pc = PC; \ + dut.io_program_bits_entries_##LANE##_parent_instruction = RAW; \ + dut.io_program_bits_entries_##LANE##_parent_lengthBytes = 4; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_valid = 1; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_predictionTag = \ + instruction_id + LANE; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_transactionId = \ + instruction_id + LANE; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_checkpointId = \ + (instruction_id + LANE) & 3; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_requestPc = PC; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_taken = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_target = PC + 4; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_fallthroughPc = \ + PC + 4; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_kind = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_provider = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_confidence = 0; \ + dut.io_program_bits_entries_##LANE##_parent_prediction_epoch = epoch; \ + dut.io_program_bits_entries_##LANE##_parent_fetchFault = 0; \ + dut.io_program_bits_entries_##LANE##_parent_fetchFaultCause = 0 + DRIVE_SYSTEM_CMD_ENTRY(0, 0x1001ULL, 0x6000ULL); + DRIVE_SYSTEM_CMD_ENTRY(1, 0x30702bULL, 0x6004ULL); + DRIVE_SYSTEM_CMD_ENTRY(2, 0x33ULL, 0x6008ULL); + DRIVE_SYSTEM_CMD_ENTRY(3, 0x1ULL, 0x600cULL); +#undef DRIVE_SYSTEM_CMD_ENTRY + dut.io_program_valid = 1; + for (int cycle = 0; cycle < 80; ++cycle) { + dut.eval(); + if (dut.io_program_ready) { + tick(dut); + clear_program(dut); + return true; + } + tick(dut); + } + std::cerr << "timeout admitting System/CMD block\n"; + clear_program(dut); + return false; +} + +bool require_nonzero(const char* name, uint32_t value) { + if (value != 0) return true; + std::cerr << "missing activation: " << name << '\n'; + return false; +} + +struct LoadIdentity { + uint8_t pe_id; + uint8_t stid; + uint8_t rid_slot; + uint16_t rid_generation; + uint8_t member_index; + uint16_t resident_generation; + uint8_t bid; + uint16_t brob_generation; + uint64_t transaction; + uint16_t transaction_generation; + uint32_t lsid; + uint16_t attempt; + uint8_t pipe; +}; + +LoadIdentity current_load(const VOOOIEXLSUActivationProbe& dut) { + return {dut.io_lastLoadIssueIdentity_rob_peId, + dut.io_lastLoadIssueIdentity_rob_stid, + dut.io_lastLoadIssueIdentity_rob_ridSlot, + dut.io_lastLoadIssueIdentity_rob_ridGeneration, + dut.io_lastLoadIssueIdentity_rob_memberIndex, + dut.io_lastLoadIssueIdentity_rob_residentGeneration, + dut.io_lastLoadIssueIdentity_rob_bid, + dut.io_lastLoadIssueIdentity_rob_brobGeneration, + dut.io_lastLoadIssueIdentity_transaction_value, + dut.io_lastLoadIssueIdentity_transaction_generation, + dut.io_lastLoadIssueIdentity_lsid, + dut.io_lastLoadIssueIdentity_attemptGeneration, + dut.io_lastLoadIssueIdentity_pipeId}; +} + +LoadIdentity rebound_load(const VOOOIEXLSUActivationProbe& dut) { + return {dut.io_lastLoadRebindNext_rob_peId, + dut.io_lastLoadRebindNext_rob_stid, + dut.io_lastLoadRebindNext_rob_ridSlot, + dut.io_lastLoadRebindNext_rob_ridGeneration, + dut.io_lastLoadRebindNext_rob_memberIndex, + dut.io_lastLoadRebindNext_rob_residentGeneration, + dut.io_lastLoadRebindNext_rob_bid, + dut.io_lastLoadRebindNext_rob_brobGeneration, + dut.io_lastLoadRebindNext_transaction_value, + dut.io_lastLoadRebindNext_transaction_generation, + dut.io_lastLoadRebindNext_lsid, + dut.io_lastLoadRebindNext_attemptGeneration, + dut.io_lastLoadRebindNext_pipeId}; +} + +#define DRIVE_ID(DUT, PREFIX, ID) \ + DUT.PREFIX##_rob_peId = ID.pe_id; \ + DUT.PREFIX##_rob_stid = ID.stid; \ + DUT.PREFIX##_rob_ridSlot = ID.rid_slot; \ + DUT.PREFIX##_rob_ridGeneration = ID.rid_generation; \ + DUT.PREFIX##_rob_memberIndex = ID.member_index; \ + DUT.PREFIX##_rob_residentGeneration = ID.resident_generation; \ + DUT.PREFIX##_rob_bid = ID.bid; \ + DUT.PREFIX##_rob_brobGeneration = ID.brob_generation; \ + DUT.PREFIX##_transaction_value = ID.transaction; \ + DUT.PREFIX##_transaction_generation = ID.transaction_generation; \ + DUT.PREFIX##_lsid = ID.lsid; \ + DUT.PREFIX##_attemptGeneration = ID.attempt; \ + DUT.PREFIX##_pipeId = ID.pipe + +template +bool wait_until(VOOOIEXLSUActivationProbe& dut, int bound, + Predicate predicate) { + for (int cycle = 0; cycle < bound; ++cycle) { + dut.eval(); + if (predicate(dut)) return true; + tick(dut); + } + return false; +} +} // namespace + +int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); + VOOOIEXLSUActivationProbe dut; + clear_program(dut); + dut.io_commitReady = 1; + dut.io_trapReady = 1; + dut.io_cmdReady = 1; + dut.io_systemReady = 1; + dut.io_oooTraceReady = 1; + dut.io_iexTraceReady = 1; + dut.io_recoveryReady = 1; + dut.io_lsuTraceReady = 1; + dut.io_memoryReady_0 = 1; + dut.io_memoryReady_1 = 1; + dut.io_memoryReady_2 = 1; + dut.io_memoryReady_3 = 1; + dut.io_memoryResponseValid = 0; + dut.io_memoryResponseId = 0; + dut.io_memoryResponseGeneration = 0; + dut.io_memoryResponseAddress = 0; + dut.io_memoryResponseData = 0; + dut.io_loadReissueRequest_valid = 0; + dut.io_loadResultInject_valid = 0; + dut.reset = 1; + for (int cycle = 0; cycle < 4; ++cycle) tick(dut); + dut.reset = 0; + + const uint64_t addi = 0x15ULL | (5ULL << 7) | (7ULL << 20); + const uint64_t jump = 0x37ULL | (2ULL << 15); + const uint64_t load = 0x3019ULL | (6ULL << 7) | (0x80ULL << 20); + const uint64_t store = 0x3059ULL | (0x88ULL << 20); + uint64_t instruction_id = 1; + int mismatch_count = 0; + if (!send(dut, {"ADDI.stid0", addi, 4, 0, 0x1000}, instruction_id++, 1)) + return 2; + if (!wait_until(dut, 160, [](const auto& d) { return d.io_rfWriteCount == 1; })) + return 3; + if (dut.io_lastRfWriteValue != 7 || dut.io_lastRfWritePtag != 48 || + dut.io_lastRfWriteGeneration != 0) { + std::cerr << "ADDI RF mismatch value=" << dut.io_lastRfWriteValue + << " ptag=" << unsigned(dut.io_lastRfWritePtag) + << " generation=" << dut.io_lastRfWriteGeneration << '\n'; + ++mismatch_count; + } + if (!send(dut, {"ADDI.stid1", addi, 4, 1, 0x2000}, instruction_id++, 1)) + return 4; + for (int cycle = 0; cycle < 16; ++cycle) tick(dut); + + // Hold only the selected lower-memory sink, then release it and retain the + // first miss identity for the old-attempt tombstone response. + dut.io_memoryReady_0 = 0; + if (!send(dut, {"LDI", load, 4, 0, 0x1008}, instruction_id++, 1)) return 5; + if (!wait_until(dut, 192, [](const auto& d) { + return d.io_memoryStallCount > 0; + })) return 18; + if (dut.io_memoryCount != 0 || dut.io_memoryStallCount == 0) { + std::cerr << "memory request did not remain valid under selected-lane " + "backpressure\n"; + ++mismatch_count; + } + dut.io_memoryReady_0 = 1; + if (!wait_until(dut, 192, [](const auto& d) { + return d.io_loadCount == 1 && d.io_loadLaunchCount == 1 && + d.io_loadAttemptLaunchCount == 1 && d.io_memoryCount == 1; + })) return 6; + + const LoadIdentity old_attempt = current_load(dut); + const uint64_t allocation_value = dut.io_lastLoadAllocationId_value; + const uint16_t allocation_generation = dut.io_lastLoadAllocationId_generation; + const uint64_t load_address = dut.io_lastLoadAddress; + const uint64_t old_memory_id = dut.io_lastMemoryId; + const uint16_t old_memory_generation = dut.io_lastMemoryGeneration; + const uint64_t old_memory_address = dut.io_lastMemoryAddress; + dut.io_loadReissueRequest_bits_allocationId_value = allocation_value; + dut.io_loadReissueRequest_bits_allocationId_generation = allocation_generation; + DRIVE_ID(dut, io_loadReissueRequest_bits_currentIdentity, old_attempt); + dut.io_loadReissueRequest_bits_address = load_address; + dut.io_loadReissueRequest_valid = 1; + if (!wait_until(dut, 64, [](const auto& d) { + return d.io_loadReissueRequest_ready; + })) return 7; + tick(dut); + dut.io_loadReissueRequest_valid = 0; + const LoadIdentity new_attempt = rebound_load(dut); + if (new_attempt.transaction != old_attempt.transaction || + new_attempt.transaction_generation != old_attempt.transaction_generation || + new_attempt.attempt != old_attempt.attempt + 1) { + std::cerr << "LSU-authored replay identity mismatch oldAttempt=" + << old_attempt.attempt << " nextAttempt=" << new_attempt.attempt + << " oldTransaction=" << old_attempt.transaction + << " nextTransaction=" << new_attempt.transaction << '\n'; + ++mismatch_count; + } + if (!wait_until(dut, 128, [](const auto& d) { + return d.io_loadLaunchCount == 2 && + d.io_loadAttemptLaunchCount == 2 && d.io_memoryCount == 2; + })) return 8; + const uint64_t new_memory_id = dut.io_lastMemoryId; + const uint16_t new_memory_generation = dut.io_lastMemoryGeneration; + const uint64_t new_memory_address = dut.io_lastMemoryAddress; + if (new_memory_id == old_memory_id && + new_memory_generation == old_memory_generation) { + std::cerr << "replay reused old lower-memory identity\n"; + ++mismatch_count; + } + + const uint32_t resolve_before = dut.io_resolveCount; + const uint32_t rf_before = dut.io_rfWriteCount; + const uint32_t commit_before = dut.io_commitCount; + dut.io_memoryResponseId = old_memory_id; + dut.io_memoryResponseGeneration = old_memory_generation; + dut.io_memoryResponseAddress = old_memory_address; + dut.io_memoryResponseData = 0xdeadbeefULL; + dut.io_memoryResponseValid = 1; + if (!wait_until(dut, 64, [](const auto& d) { return d.io_memoryResponseReady; })) + return 9; + tick(dut); + dut.io_memoryResponseValid = 0; + for (int cycle = 0; cycle < 8; ++cycle) tick(dut); + + DRIVE_ID(dut, io_loadResultInject_bits_identity, old_attempt); + dut.io_loadResultInject_bits_allocationId_value = allocation_value; + dut.io_loadResultInject_bits_allocationId_generation = allocation_generation; + dut.io_loadResultInject_bits_data = 0xdeadbeefULL; + dut.io_loadResultInject_bits_destination_valid = dut.io_lastLoadDestination_valid; + dut.io_loadResultInject_bits_destination_kind = dut.io_lastLoadDestination_kind; + dut.io_loadResultInject_bits_destination_atag = dut.io_lastLoadDestination_atag; + dut.io_loadResultInject_bits_destination_ptag = dut.io_lastLoadDestination_ptag; + dut.io_loadResultInject_bits_destination_previousPtag = + dut.io_lastLoadDestination_previousPtag; + dut.io_loadResultInject_bits_destination_pGeneration = + dut.io_lastLoadDestination_pGeneration; + dut.io_loadResultInject_bits_destination_previousPGeneration = + dut.io_lastLoadDestination_previousPGeneration; + dut.io_loadResultInject_bits_destination_previousPtagValid = + dut.io_lastLoadDestination_previousPtagValid; + dut.io_loadResultInject_bits_destination_ptagValid = + dut.io_lastLoadDestination_ptagValid; + dut.io_loadResultInject_bits_destinationRelativeIndex = + dut.io_lastLoadDestinationRelativeIndex; + dut.io_loadResultInject_bits_trap_valid = 0; + dut.io_loadResultInject_valid = 1; + if (!wait_until(dut, 64, [](const auto& d) { return d.io_loadResultInject_ready; })) + return 10; + tick(dut); + dut.io_loadResultInject_valid = 0; + for (int cycle = 0; cycle < 8; ++cycle) tick(dut); + if (dut.io_resolveCount != resolve_before || dut.io_rfWriteCount != rf_before || + dut.io_commitCount != commit_before || dut.io_loadAttemptCancelCount != 1 || + dut.io_memoryCount != 2 || dut.io_loadLaunchCount != 2) { + std::cerr << "old attempt produced an architectural or duplicate effect\n"; + ++mismatch_count; + } + + dut.io_memoryResponseId = new_memory_id; + dut.io_memoryResponseGeneration = new_memory_generation; + dut.io_memoryResponseAddress = new_memory_address; + dut.io_memoryResponseData = 0x1122334455667788ULL; + dut.io_memoryResponseValid = 1; + if (!wait_until(dut, 64, [](const auto& d) { return d.io_memoryResponseReady; })) + return 11; + tick(dut); + dut.io_memoryResponseValid = 0; + if (!wait_until(dut, 192, [&](const auto& d) { + return d.io_resolveCount == resolve_before + 1 && + d.io_rfWriteCount == rf_before + 1 && + d.io_commitCount == commit_before + 1; + })) return 12; + if (dut.io_loadAttemptLaunchCount != 2 || dut.io_loadLaunchCount != 3 || + dut.io_memoryCount != 2 || dut.io_loadAttemptCancelCount != 1 || + dut.io_lastLoadLaunchIdentity_attemptGeneration != new_attempt.attempt || + dut.io_lastResolveValue != 0x1122334455667788ULL || load_address != 0x400) { + std::cerr << "Option-A replay terminal mismatch unique=" + << dut.io_loadAttemptLaunchCount + << " raw=" << dut.io_loadLaunchCount + << " memory=" << dut.io_memoryCount + << " cancel=" << dut.io_loadAttemptCancelCount + << " expectedAttempt=" << new_attempt.attempt + << " actualAttempt=" + << dut.io_lastLoadLaunchIdentity_attemptGeneration + << " resolveValue=" << dut.io_lastResolveValue + << " loadAddress=" << load_address << '\n'; + ++mismatch_count; + } + + const uint32_t system_count_before = dut.io_systemCount; + const uint32_t cmd_count_before = dut.io_cmdCount; + const uint32_t system_issue_before = dut.io_systemIssueCount; + const uint32_t cmd_issue_before = dut.io_cmdIssueCount; + const uint32_t dispatch_stall_before = dut.io_dispatchStallCount; + dut.io_systemReady = 0; + dut.io_cmdReady = 0; + if (!send_system_cmd_block(dut, instruction_id, 1)) return 14; + instruction_id += 4; + if (!wait_until(dut, 128, [&](const auto& d) { + return d.io_systemCount == system_count_before + 1 && + d.io_cmdCount == cmd_count_before + 1; + })) return 15; + if (!wait_until(dut, 128, [&](const auto& d) { + return d.io_dispatchStallCount > dispatch_stall_before; + })) return 24; + if (dut.io_systemIssueCount != system_issue_before || + dut.io_cmdIssueCount != cmd_issue_before || + dut.io_dispatchStallCount <= dispatch_stall_before) { + std::cerr << "System/CMD escaped closed sink backpressure\n"; + ++mismatch_count; + } + + dut.io_systemReady = 1; + if (!wait_until(dut, 128, [&](const auto& d) { + return d.io_systemIssueCount == system_issue_before + 1; + })) { + std::cerr << "timeout publishing System terminal system=" + << dut.io_systemCount << " cmd=" << dut.io_cmdCount + << " systemIssue=" << dut.io_systemIssueCount + << " cmdIssue=" << dut.io_cmdIssueCount + << " resolve=" << dut.io_resolveCount + << " commit=" << dut.io_commitCount << '\n'; + return 16; + } + for (int cycle = 0; cycle < 8; ++cycle) tick(dut); + if (dut.io_cmdIssueCount != cmd_issue_before) { + std::cerr << "CMD escaped independent backpressure\n"; + ++mismatch_count; + } + dut.io_cmdReady = 1; + if (!wait_until(dut, 256, [&](const auto& d) { + return d.io_cmdIssueCount == cmd_issue_before + 1; + })) return 17; + + const uint32_t bru_before = dut.io_bruCount; + const uint32_t recovery_event_before = dut.io_recoveryEventCount; + const uint32_t recovery_apply_before = dut.io_recoveryApplyCount; + dut.io_recoveryReady = 0; + if (!send(dut, {"J", jump, 4, 0, 0x1004}, instruction_id++, 1)) return 13; + if (!wait_until(dut, 128, [&](const auto& d) { + return d.io_bruCount == bru_before + 1; + })) return 19; + for (int cycle = 0; cycle < 8; ++cycle) tick(dut); + if (dut.io_recoveryEventCount != recovery_event_before || + dut.io_recoveryApplyCount != recovery_apply_before) { + std::cerr << "recovery escaped public backpressure\n"; + ++mismatch_count; + } + + dut.io_recoveryReady = 1; + if (!wait_until(dut, 256, [&](const auto& d) { + return d.io_recoveryEventCount == recovery_event_before + 1 && + d.io_recoveryApplyCount == recovery_apply_before + 1; + })) return 20; + const uint32_t stid1_after_apply = dut.io_stid1Progress; + if (!send(dut, {"ADDI.peer-after-apply", addi, 4, 1, 0x2004}, + instruction_id++, 1)) return 21; + if (!wait_until(dut, 192, [&](const auto& d) { + return d.io_stid1Progress > stid1_after_apply; + })) return 22; + + if (!send(dut, {"SDI", store, 4, 0, 0x100c}, instruction_id++, 1)) + return 23; + for (int cycle = 0; cycle < 32; ++cycle) tick(dut); + + bool ok = true; + ok &= require_nonzero("ALU", dut.io_aluCount); + ok &= require_nonzero("BRU", dut.io_bruCount); + ok &= require_nonzero("AGU", dut.io_aguCount); + ok &= require_nonzero("STD", dut.io_stdCount); + ok &= require_nonzero("load", dut.io_loadCount); + ok &= require_nonzero("store-address", dut.io_storeAddressCount); + ok &= require_nonzero("store-data", dut.io_storeDataCount); + ok &= require_nonzero("system", dut.io_systemCount); + ok &= require_nonzero("CMD", dut.io_cmdCount); + ok &= require_nonzero("system terminal", dut.io_systemIssueCount); + ok &= require_nonzero("CMD terminal", dut.io_cmdIssueCount); + ok &= require_nonzero("lower-memory request", dut.io_memoryCount); + ok &= require_nonzero("branch recovery", dut.io_branchCount); + ok &= require_nonzero("recovery event", dut.io_recoveryEventCount); + ok &= require_nonzero("common recovery apply", dut.io_recoveryApplyCount); + ok &= require_nonzero("STID0 progress", dut.io_stid0Progress); + ok &= require_nonzero("STID1 progress", dut.io_stid1Progress); + ok &= require_nonzero("blocked public dispatch/terminal cycles", + dut.io_dispatchStallCount); + ok &= require_nonzero("blocked lower-memory cycles", + dut.io_memoryStallCount); + + if (dut.io_recoveryEventCount != 1 || dut.io_recoveryApplyCount != 1) { + std::cerr << "recovery cardinality mismatch event=" + << dut.io_recoveryEventCount + << " apply=" << dut.io_recoveryApplyCount << '\n'; + ++mismatch_count; + } + + if (dut.io_lastBranchTarget != 0x1008) { + std::cerr << "branch target mismatch expected=4104 actual=" + << dut.io_lastBranchTarget << '\n'; + ++mismatch_count; + } + if (dut.io_lastStoreAddress != 0x20 || dut.io_lastStoreData != 0) { + std::cerr << "store mismatch address=" << dut.io_lastStoreAddress + << " data=" << dut.io_lastStoreData << '\n'; + ++mismatch_count; + } + std::cout << "activation ingress=" << dut.io_ingressCount + << " bootstrap=" << dut.io_bootstrapInitCount + << " alu=" << dut.io_aluCount << " bru=" << dut.io_bruCount + << " agu=" << dut.io_aguCount << " std=" << dut.io_stdCount + << " load=" << dut.io_loadCount + << " sta=" << dut.io_storeAddressCount + << " storeData=" << dut.io_storeDataCount + << " system=" << dut.io_systemCount << " cmd=" << dut.io_cmdCount + << " systemIssue=" << dut.io_systemIssueCount + << " cmdIssue=" << dut.io_cmdIssueCount + << " resolve=" << dut.io_resolveCount + << " rf=" << dut.io_rfWriteCount + << " branch=" << dut.io_branchCount + << " recoveryEvent=" << dut.io_recoveryEventCount + << " recoveryApply=" << dut.io_recoveryApplyCount + << " memory=" << dut.io_memoryCount + << " commit=" << dut.io_commitCount + << " trace=" << dut.io_traceCount + << " stid0=" << dut.io_stid0Progress + << " stid1=" << dut.io_stid1Progress + << " dispatchStall=" << dut.io_dispatchStallCount + << " memoryStall=" << dut.io_memoryStallCount + << " uniqueLoadAttempts=" << dut.io_loadAttemptLaunchCount + << " rawLoadPasses=" << dut.io_loadLaunchCount + << " mismatch_count=" << mismatch_count << '\n'; + dut.final(); + return ok && mismatch_count == 0 ? 0 : 1; +} diff --git a/tools/chisel/plan_replay_liq_selector_probe.py b/tools/chisel/plan_replay_liq_selector_probe.py deleted file mode 100644 index 831cad60..00000000 --- a/tools/chisel/plan_replay_liq_selector_probe.py +++ /dev/null @@ -1,293 +0,0 @@ -#!/usr/bin/env python3 -"""Plan safe replay-LIQ selector CoreMark probe commands from a context pack. - -The planner deliberately refuses to emit a generated-RTL command from a raw -QEMU row hint. Skipped rows are QEMU-only in the current wrapper because the -reduced Verilator top cannot reconstruct skipped architectural state. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - -from build_replay_liq_selector_context_pack import SCHEMA as CONTEXT_SCHEMA -from build_replay_liq_selector_context_pack import validate_manifest as validate_context_pack - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_selector_probe_plan.v1" - -DEFAULT_CONTEXT_PACK = ( - ROOT_DIR - / "generated/r618-replay-liq-selector-context-pack/report/replay_liq_selector_context_pack.json" -) -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r619-replay-liq-selector-probe-plan/report/replay_liq_selector_probe_plan.json" -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def candidate_hint(context_pack: dict[str, Any]) -> dict[str, Any]: - section = context_pack.get("qemu_candidate_hint") - first = section.get("first_candidate") if isinstance(section, dict) else None - hint = first.get("probe_hint") if isinstance(first, dict) else None - if not isinstance(hint, dict): - raise ValueError("context pack does not contain qemu_candidate_hint.first_candidate.probe_hint") - return hint - - -def first_str(values: Any, label: str) -> str: - if not isinstance(values, list) or not values: - raise ValueError(f"missing {label}") - value = values[0] - if not isinstance(value, str) or not value: - raise ValueError(f"invalid {label}") - return value - - -def qemu_base_args() -> list[str]: - return [ - "-nographic", - "-monitor", - "none", - "-machine", - "virt", - "-m", - "1280M", - "-kernel", - "tests/benchmarks/build/coremark_real.elf", - ] - - -def build_plan(context_pack: dict[str, Any]) -> dict[str, Any]: - context_errors = validate_context_pack(context_pack) - if context_errors: - raise ValueError("invalid context pack: " + "; ".join(context_errors)) - if context_pack.get("schema") != CONTEXT_SCHEMA: - raise ValueError("unexpected context pack schema") - - hint = candidate_hint(context_pack) - raw_window = hint.get("raw_dynamic_window") - pc_filter = hint.get("pc_filter") - expected = hint.get("expected_memory_pcs") - if not isinstance(raw_window, dict) or not isinstance(pc_filter, dict) or not isinstance(expected, dict): - raise ValueError("candidate hint must include raw window, PC filter, and expected memory PCs") - - skip_rows = raw_window.get("qemu_skip_rows") - capture_rows = raw_window.get("capture_rows") - pc_lo = pc_filter.get("pc_lo") - pc_hi = pc_filter.get("pc_hi", pc_filter.get("pc_hi_exclusive")) - store_pc = first_str(expected.get("store_pcs"), "expected store PC") - load_pc = first_str(expected.get("load_pcs"), "expected load PC") - if not isinstance(skip_rows, int) or skip_rows < 0: - raise ValueError("raw window qemu_skip_rows must be a non-negative integer") - if not isinstance(capture_rows, int) or capture_rows <= 0: - raise ValueError("raw window capture_rows must be a positive integer") - if not isinstance(pc_lo, str) or not isinstance(pc_hi, str): - raise ValueError("PC filter bounds must be strings") - - raw_build_dir = f"generated/r619-coremark-candidate-raw{skip_rows}-qemu-preflight" - pc_build_dir = "generated/r619-coremark-candidate-pc-filter-qemu-preflight" - raw_command = [ - "bash", - "tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh", - "--build-dir", - raw_build_dir, - "--elf", - "tests/benchmarks/build/coremark_real.elf", - "--expected-rows", - "0", - "--capture-rows", - str(capture_rows), - "--qemu-skip-rows", - str(skip_rows), - "--allow-block-markers", - "--allow-block-loop-reentry", - "--qemu-only", - "--expect-store-pcs", - store_pc, - "--expect-load-pcs", - load_pc, - "--max-seconds", - "45", - "--", - *qemu_base_args(), - ] - pc_filter_command = [ - "bash", - "tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh", - "--build-dir", - pc_build_dir, - "--elf", - "tests/benchmarks/build/coremark_real.elf", - "--expected-rows", - "0", - "--capture-rows", - "8", - "--pc-lo", - pc_lo, - "--pc-hi", - pc_hi, - "--allow-block-markers", - "--allow-block-loop-reentry", - "--qemu-only", - "--expect-store-pcs", - store_pc, - "--expect-load-pcs", - load_pc, - "--max-seconds", - "45", - "--", - *qemu_base_args(), - ] - - return { - "schema": SCHEMA, - "status": "planned", - "source_context_pack_schema": context_pack.get("schema"), - "claim_boundary": ( - "This plan emits QEMU-only preflights from the R618 address-cluster hint. " - "It intentionally withholds a generated-RTL command until the exact " - "generated-RTL command shape has a passing QEMU-only expected-memory-PC preflight." - ), - "candidate": { - "raw_window": {"qemu_skip_rows": skip_rows, "capture_rows": capture_rows}, - "pc_filter": {"pc_lo": pc_lo, "pc_hi": pc_hi}, - "expected_memory_pcs": {"store_pc": store_pc, "load_pc": load_pc}, - }, - "commands": { - "raw_window_qemu_only_preflight": raw_command, - "pc_filter_qemu_only_preflight": pc_filter_command, - "generated_rtl": { - "status": "blocked", - "reason": ( - "--qemu-skip-rows is QEMU-only, and the known PC-filter preflight for this " - "candidate reaches an earlier dynamic occurrence without the expected load." - ), - }, - }, - } - - -def validate_plan(plan: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if plan.get("schema") != SCHEMA: - errors.append("plan: unexpected schema") - if plan.get("status") != "planned": - errors.append("plan: status must be 'planned'") - boundary = plan.get("claim_boundary") - if not isinstance(boundary, str) or "QEMU-only preflights" not in boundary or "withholds a generated-RTL command" not in boundary: - errors.append("plan: claim_boundary must preserve the QEMU-only gate") - commands = plan.get("commands") - if not isinstance(commands, dict): - return errors + ["plan: missing commands"] - raw = commands.get("raw_window_qemu_only_preflight") - pc = commands.get("pc_filter_qemu_only_preflight") - generated = commands.get("generated_rtl") - for label, command in (("raw_window_qemu_only_preflight", raw), ("pc_filter_qemu_only_preflight", pc)): - if not isinstance(command, list) or "--qemu-only" not in command: - errors.append(f"commands.{label}: must be a QEMU-only command list") - if isinstance(command, list) and "--expect-load-pcs" not in command: - errors.append(f"commands.{label}: missing expected load PC guard") - if isinstance(command, list) and "--expect-store-pcs" not in command: - errors.append(f"commands.{label}: missing expected store PC guard") - if not isinstance(generated, dict) or generated.get("status") != "blocked": - errors.append("commands.generated_rtl: must remain blocked") - return errors - - -def sample_context_pack() -> dict[str, Any]: - from build_replay_liq_selector_context_pack import sample_manifest - - sample = sample_manifest() - hint = sample["qemu_candidate_hint"]["first_candidate"]["probe_hint"] - hint["pc_filter"] = {"pc_lo": "0x10", "pc_hi_exclusive": "0x18"} - return sample - - -def run_self_test() -> None: - plan = build_plan(sample_context_pack()) - if validate_plan(plan): - raise AssertionError("valid sample plan failed validation") - failing = copy.deepcopy(plan) - failing["commands"]["generated_rtl"]["status"] = "ready" - if not validate_plan(failing): - raise AssertionError("unblocked generated-RTL command was not detected") - failing = copy.deepcopy(plan) - failing["commands"]["raw_window_qemu_only_preflight"].remove("--qemu-only") - if not validate_plan(failing): - raise AssertionError("missing QEMU-only guard was not detected") - - -def shell_quote(argv: list[str]) -> str: - import shlex - - return " ".join(shlex.quote(arg) for arg in argv) - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--context-pack", type=Path, default=DEFAULT_CONTEXT_PACK) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - parser.add_argument("--print-commands", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-selector-probe-plan self-test: ok") - if args.validate_only is None and not args.print_commands and "--context-pack" not in argv and "--output" not in argv: - return 0 - - if args.validate_only is not None: - plan = load_json(args.validate_only) - errors = validate_plan(plan) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-selector-probe-plan: ok manifest={args.validate_only}") - return 0 - - plan = build_plan(load_json(args.context_pack)) - errors = validate_plan(plan) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, plan) - print(f"replay-liq-selector-probe-plan-report={args.output}") - if args.print_commands: - commands = plan["commands"] - print("raw-window-qemu-only:") - print(shell_quote(commands["raw_window_qemu_only_preflight"])) - print("pc-filter-qemu-only:") - print(shell_quote(commands["pc_filter_qemu_only_preflight"])) - print("generated-rtl: blocked") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/reduced_store_non_flush_gate_probe_tb.cpp b/tools/chisel/reduced_store_non_flush_gate_probe_tb.cpp deleted file mode 100644 index e2ffd298..00000000 --- a/tools/chisel/reduced_store_non_flush_gate_probe_tb.cpp +++ /dev/null @@ -1,141 +0,0 @@ -#include -#include - -#include "VReducedStoreNonFlushGateProbe.h" -#include "verilated.h" - -static void tick(VReducedStoreNonFlushGateProbe &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); -} - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "reduced-store-non-flush-gate-probe: " << message << '\n'; - std::exit(1); - } -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VReducedStoreNonFlushGateProbe dut; - dut.reset = 1; - dut.io_flushValid = 0; - dut.io_commitValid = 0; - dut.io_commitStore = 0; - dut.io_commitBlockBid = 0; - dut.io_commitLsId = 0; - dut.io_rowValid = 1; - dut.io_rowScalarIex = 1; - dut.io_nonFlushValid = 0; - dut.io_nonFlushHeadBid = 0; - dut.io_nonFlushPrefixCount = 0; - dut.io_oldestBlockValid = 0; - dut.io_oldestBlockBid = 0; - dut.io_oldestRobValid = 0; - dut.io_oldestRobBid = 0; - dut.io_oldestRobLsId = 0; - tick(dut); - tick(dut); - dut.reset = 0; - - // Block 9 is outside the safe [8, 8] prefix. Its commit is retained. - dut.io_commitValid = 1; - dut.io_commitStore = 1; - dut.io_commitBlockBid = 9; - dut.io_commitLsId = 1; - dut.io_nonFlushValid = 1; - dut.io_nonFlushHeadBid = 8; - dut.io_nonFlushPrefixCount = 1; - dut.eval(); - require(dut.io_blockedByNonFlush, "unsafe committed store was not blocked"); - require(dut.io_pendingMarkMask == 0, "unsafe committed store marked STQ early"); - tick(dut); - dut.io_commitValid = 0; - dut.io_commitStore = 0; - dut.eval(); - require(dut.io_pendingMarkMask == 0 && !dut.io_markValid, - "retained unsafe store escaped before frontier advance"); - - // Advancing the same STID prefix to [8, 9] releases the retained event. - dut.io_nonFlushPrefixCount = 2; - tick(dut); - dut.eval(); - require(dut.io_pendingMarkMask == 1 && dut.io_markValid && dut.io_markIndex == 0, - "retained store did not become markable inside the strong prefix"); - - // Accepted recovery clears retained and pending ownership. - dut.io_flushValid = 1; - tick(dut); - dut.io_flushValid = 0; - dut.eval(); - require(dut.io_pendingMarkMask == 0 && !dut.io_markValid, - "flush did not clear non-flush-gated store ownership"); - - // A later commit LSID in the exact oldest running Linx block makes the - // retained scalar store locally non-flushable without completing the block. - dut.io_nonFlushValid = 0; - dut.io_nonFlushPrefixCount = 0; - dut.io_oldestBlockValid = 1; - dut.io_oldestBlockBid = 9; - dut.io_commitValid = 1; - dut.io_commitStore = 1; - dut.io_commitBlockBid = 9; - dut.io_commitLsId = 1; - tick(dut); - dut.io_commitStore = 0; - dut.io_commitLsId = 2; - dut.io_rowValid = 0; - dut.eval(); - tick(dut); - dut.io_commitValid = 0; - dut.io_rowValid = 1; - dut.eval(); - require(dut.io_earlySafeMatchMask == 1, - "latched oldest-block LSID frontier did not authorize late scalar row"); - tick(dut); - dut.eval(); - require(dut.io_pendingMarkMask == 1 && dut.io_markValid, - "latched early-safe scalar store did not become markable"); - - // The same frontier must not authorize tile-owned store behavior. - dut.io_flushValid = 1; - tick(dut); - dut.io_flushValid = 0; - dut.io_rowScalarIex = 0; - dut.io_commitValid = 1; - dut.io_commitStore = 1; - dut.io_commitLsId = 1; - tick(dut); - dut.io_commitStore = 0; - dut.io_commitLsId = 2; - dut.io_rowValid = 0; - tick(dut); - dut.io_commitValid = 0; - dut.io_rowValid = 1; - dut.eval(); - require(dut.io_pendingMarkMask == 0 && !dut.io_markValid, - "scalar early-safe frontier authorized a tile store"); - - // The model PE-oldest-LSID fallback directly scans ready resident scalar - // rows and does not depend on an earlier ROB-store identity capture. - dut.io_flushValid = 1; - tick(dut); - dut.io_flushValid = 0; - dut.io_rowScalarIex = 1; - dut.io_oldestRobValid = 1; - dut.io_oldestRobBid = 1; - dut.io_oldestRobLsId = 2; - dut.eval(); - require(dut.io_residentEarlySafeMask == 1, - "oldest ROB LSID did not authorize older resident scalar store"); - tick(dut); - dut.eval(); - require(dut.io_pendingMarkMask == 1 && dut.io_markValid, - "resident early-safe scalar store did not become markable"); - - std::cout << "reduced-store-non-flush-gate-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/reduced_store_wait_replay_chisel_path_tb.cpp b/tools/chisel/reduced_store_wait_replay_chisel_path_tb.cpp deleted file mode 100644 index 185b0801..00000000 --- a/tools/chisel/reduced_store_wait_replay_chisel_path_tb.cpp +++ /dev/null @@ -1,914 +0,0 @@ -#include "VReducedStoreWaitReplayChiselPathProbe.h" -#include "verilated.h" - -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint8_t kStoreAll = 0; -constexpr std::uint8_t kStoreAddr = 1; -constexpr std::uint8_t kStoreData = 2; -constexpr std::uint64_t kStorePc = 0x4400; -constexpr std::uint64_t kLoadAddr = 0x3000; -constexpr std::uint64_t kLoadLineAddr = 0x3000; -constexpr std::uint64_t kStoreDataValue = 0x1122334455667788ULL; -constexpr std::uint64_t kBaseData = 0xffeeddccbbaa9988ULL; -constexpr std::uint64_t kRefillDataLow = 0x0123456789abcdefULL; -constexpr std::uint64_t kReplayWakeValidMask = 0xffULL; -constexpr std::uint8_t kReplayWakeScbSource = 1; -constexpr std::uint8_t kStoreBid = 1; -constexpr std::uint8_t kStoreLsId = 1; -constexpr std::uint8_t kLoadBid = 2; -constexpr std::uint8_t kLoadLsId = 3; -constexpr std::uint8_t kSecondStoreBid = 4; -constexpr std::uint8_t kSecondStoreLsId = 4; -constexpr std::uint8_t kSecondLoadBid = 5; -constexpr std::uint8_t kSecondLoadLsId = 6; - -struct Args { - std::string report_json; -}; - -[[noreturn]] void usage(const char *argv0) { - std::cerr << "usage: " << argv0 << " [--report-json ]\n"; - std::exit(2); -} - -Args parse_args(int argc, char **argv) { - Args args; - for (int i = 1; i < argc; ++i) { - const std::string arg(argv[i]); - if (arg == "--report-json" && i + 1 < argc) { - args.report_json = argv[++i]; - } else { - usage(argv[0]); - } - } - return args; -} - -void fail(const std::string &message) { - std::cerr << "reduced-store-wait-replay-chisel-path failure: " << message << "\n"; - std::exit(1); -} - -void expect(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -std::string mask_diag(VReducedStoreWaitReplayChiselPathProbe &dut) { - return " candidate_mask=" + std::to_string(dut.io_mdbLookupWaitPlanCandidateMask) + - " target_index=" + std::to_string(dut.io_mdbLookupWaitPlanTargetIndex) + - " occupied_mask=" + std::to_string(dut.io_liqOccupiedMask) + - " wait_mask=" + std::to_string(dut.io_liqWaitMask) + - " repick_mask=" + std::to_string(dut.io_liqRepickMask); -} - -void clear_inputs(VReducedStoreWaitReplayChiselPathProbe &dut) { - dut.io_flush = 0; - dut.io_storeInsertValid = 0; - dut.io_storeInsert_lsIdFull = 0; - dut.io_storeInsert_storeType = 0; - dut.io_storeInsert_peId = 0; - dut.io_storeInsert_stid = 0; - dut.io_storeInsert_tid = 0; - dut.io_storeInsert_bid_valid = 0; - dut.io_storeInsert_bid_wrap = 0; - dut.io_storeInsert_bid_value = 0; - dut.io_storeInsert_gid_valid = 0; - dut.io_storeInsert_gid_wrap = 0; - dut.io_storeInsert_gid_value = 0; - dut.io_storeInsert_rid_valid = 0; - dut.io_storeInsert_rid_wrap = 0; - dut.io_storeInsert_rid_value = 0; - dut.io_storeInsert_lsId_valid = 0; - dut.io_storeInsert_lsId_wrap = 0; - dut.io_storeInsert_lsId_value = 0; - dut.io_storeInsert_tSeq_valid = 0; - dut.io_storeInsert_tSeq_wrap = 0; - dut.io_storeInsert_tSeq_value = 0; - dut.io_storeInsert_uSeq_valid = 0; - dut.io_storeInsert_uSeq_wrap = 0; - dut.io_storeInsert_uSeq_value = 0; - dut.io_storeInsert_tuDstValid = 0; - dut.io_storeInsert_tuDstKind = 0; - dut.io_storeInsert_pc = 0; - dut.io_storeInsert_addr = 0; - dut.io_storeInsert_data = 0; - dut.io_storeInsert_size = 0; - dut.io_storeInsert_stackValid = 0; - dut.io_storeInsert_scalarIex = 0; - dut.io_storeInsert_simtLane = 0; - dut.io_loadValid = 0; - dut.io_loadLsIdFullValid = 0; - dut.io_loadLsIdFull = 0; - dut.io_loadAddr = 0; - dut.io_loadSize = 0; - dut.io_loadBid_valid = 0; - dut.io_loadBid_wrap = 0; - dut.io_loadBid_value = 0; - dut.io_loadLsId_valid = 0; - dut.io_loadLsId_wrap = 0; - dut.io_loadLsId_value = 0; - dut.io_baseLoadData = 0; - dut.io_captureEnable = 0; - dut.io_liqRefillValid = 0; - dut.io_liqRefillLineAddr = 0; - for (int word = 0; word < 16; ++word) { - dut.io_liqRefillData[word] = 0; - } - dut.io_liqLaunchEnable = 0; - dut.io_liqE2LoadDataReturned = 0; - dut.io_liqE2ScbReturned = 0; - dut.io_liqE2StqReturned = 0; - dut.io_liqE2ReturnReady = 0; - dut.io_liqReplayWakeValid = 0; - dut.io_liqReplayWake_storeLsIdFullValid = 0; - dut.io_liqReplayWake_storeLsIdFull = 0; - dut.io_liqReplayWake_source = 0; - dut.io_liqReplayWake_storeId_valid = 0; - dut.io_liqReplayWake_storeId_wrap = 0; - dut.io_liqReplayWake_storeId_value = 0; - dut.io_liqReplayWake_storeLsId_valid = 0; - dut.io_liqReplayWake_storeLsId_wrap = 0; - dut.io_liqReplayWake_storeLsId_value = 0; - dut.io_liqReplayWake_pc = 0; - dut.io_liqReplayWake_lineAddr = 0; - dut.io_liqReplayWake_validMask = 0; - for (int word = 0; word < 16; ++word) { - dut.io_liqReplayWake_data[word] = 0; - } - dut.io_resolveQueueRetireValid = 0; - dut.io_resolveQueueRetireBid_valid = 0; - dut.io_resolveQueueRetireBid_wrap = 0; - dut.io_resolveQueueRetireBid_value = 0; - dut.io_resolveQueueRetireLsId_valid = 0; - dut.io_resolveQueueRetireLsId_wrap = 0; - dut.io_resolveQueueRetireLsId_value = 0; - dut.io_mdbLookupValid = 0; - dut.io_mdbDeleteValid = 0; - dut.io_mdbDeleteWaitStorePc = 0; - dut.io_mdbStore_valid = 0; - dut.io_mdbStore_lsIdFullValid = 0; - dut.io_mdbStore_lsIdFull = 0; - dut.io_mdbStore_addrOnly = 0; - dut.io_mdbStore_isTile = 0; - dut.io_mdbStore_peId = 0; - dut.io_mdbStore_stid = 0; - dut.io_mdbStore_tid = 0; - dut.io_mdbStore_bid_valid = 0; - dut.io_mdbStore_bid_wrap = 0; - dut.io_mdbStore_bid_value = 0; - dut.io_mdbStore_gid_valid = 0; - dut.io_mdbStore_gid_wrap = 0; - dut.io_mdbStore_gid_value = 0; - dut.io_mdbStore_rid_valid = 0; - dut.io_mdbStore_rid_wrap = 0; - dut.io_mdbStore_rid_value = 0; - dut.io_mdbStore_lsId_valid = 0; - dut.io_mdbStore_lsId_wrap = 0; - dut.io_mdbStore_lsId_value = 0; - dut.io_mdbStore_pc = 0; - dut.io_mdbStore_addr = 0; - dut.io_mdbStore_size = 0; - dut.io_mdbLookupUseLiveLoad = 0; -} - -void tick(VReducedStoreWaitReplayChiselPathProbe &dut, std::uint64_t &cycle) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); - dut.clock = 0; - dut.eval(); - ++cycle; -} - -void reset(VReducedStoreWaitReplayChiselPathProbe &dut, std::uint64_t &cycle) { - clear_inputs(dut); - dut.reset = 1; - tick(dut, cycle); - tick(dut, cycle); - dut.reset = 0; - dut.eval(); - expect(dut.io_stqOccupiedMask == 0, "reset did not clear STQ occupancy"); - expect(!dut.io_waitSlotActive, "reset did not clear wait replay slot"); - expect(dut.io_liqResidentCount == 0, "reset did not clear LIQ residency"); -} - -void drive_store(VReducedStoreWaitReplayChiselPathProbe &dut, std::uint8_t store_type, - std::uint8_t bid = kStoreBid, std::uint8_t ls_id = kStoreLsId) { - dut.io_storeInsertValid = 1; - dut.io_storeInsert_storeType = store_type; - dut.io_storeInsert_bid_valid = 1; - dut.io_storeInsert_bid_wrap = 0; - dut.io_storeInsert_bid_value = bid; - dut.io_storeInsert_gid_valid = 1; - dut.io_storeInsert_gid_value = 0; - dut.io_storeInsert_rid_valid = 1; - dut.io_storeInsert_rid_value = 0; - dut.io_storeInsert_lsId_valid = 1; - dut.io_storeInsert_lsId_wrap = 0; - dut.io_storeInsert_lsId_value = ls_id; - dut.io_storeInsert_lsIdFull = ls_id; - dut.io_storeInsert_pc = kStorePc; - dut.io_storeInsert_addr = kLoadAddr; - dut.io_storeInsert_data = kStoreDataValue; - dut.io_storeInsert_size = 8; - dut.io_storeInsert_scalarIex = 1; -} - -void drive_load(VReducedStoreWaitReplayChiselPathProbe &dut, bool capture_enable, - std::uint8_t bid = kLoadBid, std::uint8_t ls_id = kLoadLsId) { - dut.io_loadValid = 1; - dut.io_loadAddr = kLoadAddr; - dut.io_loadSize = 8; - dut.io_loadBid_valid = 1; - dut.io_loadBid_wrap = 0; - dut.io_loadBid_value = bid; - dut.io_loadLsId_valid = 1; - dut.io_loadLsId_wrap = 0; - dut.io_loadLsId_value = ls_id; - dut.io_loadLsIdFullValid = 1; - dut.io_loadLsIdFull = ls_id; - dut.io_baseLoadData = kBaseData; - dut.io_captureEnable = capture_enable ? 1 : 0; -} - -void drive_live_lookup_load_identity(VReducedStoreWaitReplayChiselPathProbe &dut, - std::uint8_t bid = kSecondLoadBid, - std::uint8_t ls_id = kSecondLoadLsId) { - dut.io_mdbLookupUseLiveLoad = 1; - dut.io_mdbLookupValid = 1; - dut.io_loadAddr = kLoadAddr; - dut.io_loadSize = 8; - dut.io_loadBid_valid = 1; - dut.io_loadBid_wrap = 0; - dut.io_loadBid_value = bid; - dut.io_loadLsId_valid = 1; - dut.io_loadLsId_wrap = 0; - dut.io_loadLsId_value = ls_id; - dut.io_loadLsIdFullValid = 1; - dut.io_loadLsIdFull = ls_id; -} - -void drive_scb_replay_wake(VReducedStoreWaitReplayChiselPathProbe &dut) { - dut.io_liqReplayWakeValid = 1; - dut.io_liqReplayWake_source = kReplayWakeScbSource; - dut.io_liqReplayWake_lineAddr = kLoadLineAddr; - dut.io_liqReplayWake_validMask = kReplayWakeValidMask; - dut.io_liqReplayWake_data[0] = static_cast(kRefillDataLow); - dut.io_liqReplayWake_data[1] = static_cast(kRefillDataLow >> 32); -} - -void drive_mdb_store_probe(VReducedStoreWaitReplayChiselPathProbe &dut) { - dut.io_mdbStore_valid = 1; - dut.io_mdbStore_addrOnly = 0; - dut.io_mdbStore_isTile = 0; - dut.io_mdbStore_peId = 0; - dut.io_mdbStore_stid = 0; - dut.io_mdbStore_tid = 0; - dut.io_mdbStore_bid_valid = 1; - dut.io_mdbStore_bid_wrap = 0; - dut.io_mdbStore_bid_value = kStoreBid; - dut.io_mdbStore_gid_valid = 1; - dut.io_mdbStore_gid_value = 0; - dut.io_mdbStore_rid_valid = 1; - dut.io_mdbStore_rid_value = 0; - dut.io_mdbStore_lsId_valid = 1; - dut.io_mdbStore_lsId_wrap = 0; - dut.io_mdbStore_lsId_value = kStoreLsId; - dut.io_mdbStore_lsIdFullValid = 1; - dut.io_mdbStore_lsIdFull = kStoreLsId; - dut.io_mdbStore_pc = kStorePc; - dut.io_mdbStore_addr = kLoadAddr; - dut.io_mdbStore_size = 8; -} - -struct Report { - std::uint64_t cycles = 0; - bool ready_forward_observed = false; - bool sta_wait_capture = false; - bool not_ready_wake_blocked = false; - bool std_wake_clear = false; - bool relaunch_queue_fire = false; - bool liq_alloc = false; - bool liq_refill = false; - bool liq_launch_valid = false; - bool liq_launch_accepted = false; - bool liq_e4_update = false; - bool liq_lhq_record = false; - bool liq_resolved = false; - bool resolve_queue_push = false; - bool liq_clear_resolved = false; - bool mdb_resolve_conflict = false; - bool mdb_nuke_flush = false; - bool mdb_fanout_record_accepted = false; - bool mdb_fanout_record_processed = false; - bool mdb_bmdb_report = false; - bool mdb_fanout_record_reinforced = false; - bool mdb_lookup_first_suppressed = false; - bool mdb_lookup_hit = false; - bool mdb_su_wakeup = false; - bool mdb_lookup_wait_plan_no_target = false; - bool mdb_lookup_wait_plan_live_target = false; - bool mdb_lookup_wait_plan_request = false; - bool mdb_lookup_wait_plan_bridge = false; - bool mdb_lookup_wait_plan_control_blocked = false; - bool mdb_lookup_wait_plan_scb_evidence = false; - bool mdb_lookup_wait_plan_write = false; - bool mdb_lookup_wait_plan_apply = false; - bool mdb_lookup_wait_plan_wait_status_after_write = false; - bool mdb_delete_accepted = false; - bool mdb_delete_dropped_below_stall = false; - bool mdb_delete_released = false; - bool resolve_queue_retired = false; - std::uint32_t youngest_store_lsid = 0; - std::uint32_t launch_load_lsid = 0; - std::uint32_t resolve_queue_count = 0; - std::uint32_t resolve_queue_count_after_retire = 0; - std::uint32_t mdb_resolve_candidate_mask = 0; - std::uint32_t mdb_conflict_load_lsid = 0; - std::uint32_t mdb_fanout_ssit_valid_mask = 0; - std::uint32_t mdb_su_wakeup_store_index = 0; - std::uint32_t mdb_lookup_wait_plan_candidate_mask = 0; - std::uint32_t mdb_lookup_wait_plan_live_candidate_mask = 0; - std::uint32_t mdb_lookup_wait_plan_live_target_index = 0; - std::uint32_t liq_replay_wake_completed_mask = 0; - std::uint32_t liq_sources_returned_mask_before_mdb_write = 0; - std::uint32_t liq_scb_returned_mask_before_mdb_write = 0; - std::uint32_t liq_wait_mask_after_mdb_write = 0; - std::uint32_t liq_wait_store_mask_after_mdb_write = 0; - std::uint32_t e4_cycles_after_launch = 0; -}; - -void run_ready_store_negative(VReducedStoreWaitReplayChiselPathProbe &dut, std::uint64_t &cycle, Report &report) { - reset(dut, cycle); - drive_store(dut, kStoreAll); - dut.eval(); - expect(dut.io_storeInsertAccepted, "ready store insert was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - drive_load(dut, true); - dut.eval(); - expect(dut.io_forwardReady, "ready store did not produce ready forwarding"); - expect(!dut.io_forwardWaitBlocked, "ready store incorrectly blocked load on wait-store"); - expect(!dut.io_forwardWaitStoreValid, "ready store unexpectedly produced wait-store key"); - expect(!dut.io_waitSlotCaptureAccepted, "ready store unexpectedly captured wait replay slot"); - report.ready_forward_observed = true; -} - -void run_sta_only_replay_path(VReducedStoreWaitReplayChiselPathProbe &dut, std::uint64_t &cycle, Report &report) { - reset(dut, cycle); - drive_store(dut, kStoreAddr); - dut.eval(); - expect(dut.io_storeInsertAccepted, "STA insert was not accepted"); - tick(dut, cycle); - expect((dut.io_stqOccupiedMask & 0x1) != 0, "STA row was not resident"); - expect((dut.io_stqAddrReadyMask & 0x1) != 0, "STA row did not set address-ready"); - expect((dut.io_stqDataReadyMask & 0x1) == 0, "STA row set data-ready too early"); - - clear_inputs(dut); - drive_load(dut, true); - dut.eval(); - expect(dut.io_forwardWaitBlocked, "STA-only row did not block younger load"); - expect(dut.io_forwardWaitStoreValid, "STA-only row did not produce wait-store key"); - expect(dut.io_forwardWaitStoreIndex == 0, "STA-only wait-store key selected the wrong STQ index"); - expect(dut.io_waitSlotCaptureAccepted, "STA-only wait-store was not captured"); - tick(dut, cycle); - report.sta_wait_capture = true; - - clear_inputs(dut); - dut.eval(); - expect(dut.io_waitSlotActive, "captured wait replay slot is not active"); - expect(dut.io_wakeIdentityMatch, "not-ready resident store lost wait identity"); - expect(!dut.io_wakeSelectedRowReady, "not-ready resident store reported wake-ready"); - expect(!dut.io_wakeValid, "not-ready resident store emitted wakeup"); - report.not_ready_wake_blocked = true; - - drive_store(dut, kStoreData); - dut.eval(); - expect(dut.io_storeInsertAccepted, "STD merge was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_wakeIdentityMatch, "ready resident store lost wait identity"); - expect(dut.io_wakeSelectedRowReady, "ready resident store did not report wake-ready"); - expect(dut.io_wakeValid, "ready resident store did not emit wakeup"); - expect(dut.io_waitStoreClear, "store wakeup did not clear wait replay slot"); - tick(dut, cycle); - report.std_wake_clear = true; - - clear_inputs(dut); - dut.eval(); - expect(!dut.io_waitSlotActive, "wait slot remained active after wake clear"); - expect(dut.io_relaunchQueuePending, "relaunch queue did not retain the replay candidate"); - expect(dut.io_relaunchQueueOutValid, "relaunch queue head was not valid"); - expect(dut.io_liqCandidateConsumeReady, "LIQ path was not ready to consume relaunch candidate"); - expect(dut.io_relaunchQueueOutFire, "relaunch queue did not fire into LIQ path"); - expect(dut.io_liqAllocAccepted, "LIQ path did not accept relaunch candidate"); - tick(dut, cycle); - report.relaunch_queue_fire = true; - report.liq_alloc = true; - - clear_inputs(dut); - dut.eval(); - expect(dut.io_liqResidentCount == 1, "LIQ did not retain allocated replay row"); - expect((dut.io_liqOccupiedMask & 0x1) != 0, "LIQ row zero is not occupied"); - expect(dut.io_liqFirstYoungestStoreLsId_valid, "LIQ row did not preserve youngest-store LSID valid bit"); - expect(dut.io_liqFirstYoungestStoreLsId_value == kStoreLsId, "LIQ row did not preserve youngest-store LSID value"); - report.youngest_store_lsid = dut.io_liqFirstYoungestStoreLsId_value; - - clear_inputs(dut); - dut.io_liqRefillValid = 1; - dut.io_liqRefillLineAddr = kLoadLineAddr; - dut.io_liqRefillData[0] = static_cast(kRefillDataLow); - dut.io_liqRefillData[1] = static_cast(kRefillDataLow >> 32); - dut.eval(); - expect(dut.io_liqRefillAccepted, "LIQ refill wakeup was not accepted"); - expect((dut.io_liqRefillWakeMask & 0x1) != 0, "LIQ refill did not wake row zero"); - tick(dut, cycle); - report.liq_refill = true; - - clear_inputs(dut); - dut.eval(); - expect((dut.io_liqWaitMask & 0x1) != 0, "refilled LIQ row did not remain in Wait"); - expect(dut.io_liqLaunchValid, "refilled LIQ row did not become a launch candidate"); - expect(dut.io_liqLaunchReady, "refilled LIQ row was not launch-ready"); - expect(dut.io_liqLaunchIndex == 0, "LIQ launch selected the wrong row"); - expect(dut.io_liqLaunchSelectedLoadLsId_valid, "LIQ launch did not preserve selected load LSID valid bit"); - expect(dut.io_liqLaunchSelectedLoadLsId_value == kLoadLsId, "LIQ launch did not preserve selected load LSID value"); - report.liq_launch_valid = true; - report.launch_load_lsid = dut.io_liqLaunchSelectedLoadLsId_value; - - dut.io_liqLaunchEnable = 1; - dut.io_liqE2LoadDataReturned = 1; - dut.io_liqE2ScbReturned = 1; - dut.io_liqE2StqReturned = 1; - dut.io_liqE2ReturnReady = 1; - dut.eval(); - expect(dut.io_liqLaunchDriveValid, "LIQ launchEnable did not drive launch valid"); - expect(dut.io_liqLaunchAccepted, "LIQ launch was not accepted"); - tick(dut, cycle); - report.liq_launch_accepted = true; - - clear_inputs(dut); - bool saw_e4 = false; - std::uint32_t e4_latency = 0; - for (std::uint32_t wait = 0; wait < 4; ++wait) { - dut.eval(); - if (dut.io_liqE4UpdateValid) { - expect(dut.io_liqE4UpdateIndex == 0, "LIQ E4 update selected the wrong row"); - expect(dut.io_liqE4WakeupValid, "LIQ E4 update did not report wakeup-valid resolved data"); - expect(dut.io_liqLhqRecordValid, "LIQ E4 update did not publish an LHQ record"); - expect(dut.io_liqLhqRecordLoadLsId_valid, "LIQ LHQ record did not preserve load LSID valid bit"); - expect(dut.io_liqLhqRecordLoadLsId_value == kLoadLsId, "LIQ LHQ record did not preserve load LSID value"); - expect(dut.io_liqLhqRecordData[0] == static_cast(kRefillDataLow), - "LIQ LHQ record did not preserve refill data low word"); - expect(dut.io_resolveQueuePushAccepted, "ResolveQ did not accept the LIQ LHQ record"); - saw_e4 = true; - e4_latency = wait; - break; - } - tick(dut, cycle); - } - - expect(saw_e4, "launched LIQ row did not produce an E4 update"); - report.liq_e4_update = true; - report.liq_lhq_record = true; - report.resolve_queue_push = true; - report.e4_cycles_after_launch = e4_latency; - - tick(dut, cycle); - dut.eval(); - expect((dut.io_liqRepickMask & 0x1) != 0, "E4 hit must remain Repick until markResolved"); - tick(dut, cycle); - dut.eval(); - expect( - (dut.io_liqResolvedMask & 0x1) != 0, - "E4-resolved LIQ row did not enter Resolved" + mask_diag(dut)); - expect((dut.io_liqRepickMask & 0x1) == 0, "E4-resolved LIQ row remained in Repick"); - expect(dut.io_resolveQueueCount == 1, "ResolveQ did not retain the pushed LHQ record"); - expect((dut.io_resolveQueueValidMask & 0x1) != 0, "ResolveQ row zero is not valid after push"); - expect(dut.io_resolveQueueFirstLoadLsId_valid, "ResolveQ did not preserve load LSID valid bit"); - expect(dut.io_resolveQueueFirstLoadLsId_value == kLoadLsId, "ResolveQ did not preserve load LSID value"); - expect(dut.io_liqClearResolvedPending, "LIQ clear-resolved request was not pending after ResolveQ push"); - expect(dut.io_liqClearResolvedAccepted, "LIQ clear-resolved request was not accepted"); - report.liq_resolved = true; - report.resolve_queue_count = dut.io_resolveQueueCount; - - tick(dut, cycle); - dut.eval(); - expect(dut.io_liqResidentCount == 0, "LIQ resident count did not clear after ResolveQ push"); - expect(dut.io_liqOccupiedMask == 0, "LIQ row remained occupied after clear-resolved"); - expect(dut.io_liqResolvedMask == 0, "LIQ resolved mask remained set after clear-resolved"); - expect(!dut.io_liqClearResolvedPending, "LIQ clear-resolved request remained pending after acceptance"); - expect(dut.io_resolveQueueCount == 1, "ResolveQ lost the resolved record after LIQ clear"); - report.liq_clear_resolved = true; - - clear_inputs(dut); - drive_mdb_store_probe(dut); - dut.eval(); - expect(dut.io_mdbConflictValid, "MDB conflict detect did not see the ResolveQ row"); - expect(dut.io_mdbConflictFromResolveQueue, "MDB conflict did not come from ResolveQ"); - expect((dut.io_mdbResolveCandidateMask & 0x1) != 0, "MDB ResolveQ candidate mask did not select row zero"); - expect(dut.io_mdbConflictResolveIndex == 0, "MDB conflict selected the wrong ResolveQ index"); - expect(dut.io_mdbNukeFlush, "MDB conflict did not classify cross-BID conflict as nuke flush"); - expect(!dut.io_mdbInnerFlush, "MDB conflict incorrectly classified cross-BID conflict as inner flush"); - expect(dut.io_mdbConflictLoadLsId_valid, "MDB conflict record did not preserve load LSID valid bit"); - expect(dut.io_mdbConflictLoadLsId_value == kLoadLsId, "MDB conflict record did not preserve load LSID value"); - expect(dut.io_mdbConflictLoadPc == 0, "MDB conflict record load PC changed from fixture-owned zero PC"); - expect(dut.io_mdbFanoutRecordReady, "MDB fanout record queue was not ready"); - expect(dut.io_mdbFanoutRecordAccepted, "MDB fanout did not accept the conflict record"); - report.mdb_resolve_conflict = true; - report.mdb_nuke_flush = true; - report.mdb_fanout_record_accepted = true; - report.mdb_resolve_candidate_mask = dut.io_mdbResolveCandidateMask; - report.mdb_conflict_load_lsid = dut.io_mdbConflictLoadLsId_value; - - tick(dut, cycle); - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutRecordProcessed, "MDB fanout did not process the accepted conflict record"); - expect(dut.io_mdbFanoutBmdbReportValid, "MDB fanout did not publish BMDB report intent"); - expect(dut.io_mdbFanoutBmdbLoadBid_valid, "MDB fanout BMDB load BID did not preserve valid bit"); - expect(dut.io_mdbFanoutBmdbLoadBid_value == kLoadBid, "MDB fanout BMDB load BID did not match resolved load"); - expect(dut.io_mdbFanoutBmdbStoreBid_valid, "MDB fanout BMDB store BID did not preserve valid bit"); - expect(dut.io_mdbFanoutBmdbStoreBid_value == kStoreBid, "MDB fanout BMDB store BID did not match conflict store"); - expect(dut.io_mdbFanoutBmdbStoreStid == 0, "MDB fanout BMDB STID did not match fixture thread"); - expect((dut.io_mdbFanoutSsitValidMask & 0x1) != 0, "MDB fanout SSIT did not allocate a record row"); - report.mdb_fanout_record_processed = true; - report.mdb_bmdb_report = true; - report.mdb_fanout_ssit_valid_mask = dut.io_mdbFanoutSsitValidMask; - - clear_inputs(dut); - drive_mdb_store_probe(dut); - dut.eval(); - expect(dut.io_mdbConflictValid, "MDB second conflict record lost ResolveQ conflict"); - expect(dut.io_mdbFanoutRecordAccepted, "MDB fanout did not accept the reinforcing conflict record"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutRecordProcessed, "MDB fanout did not process the reinforcing conflict record"); - expect(dut.io_mdbFanoutBmdbReportValid, "MDB fanout did not report BMDB intent for reinforcing record"); - expect((dut.io_mdbFanoutSsitValidMask & 0x1) != 0, "MDB fanout lost SSIT row after reinforcing record"); - report.mdb_fanout_record_reinforced = true; - - clear_inputs(dut); - dut.io_mdbLookupValid = 1; - dut.eval(); - expect(dut.io_mdbFanoutLookupReady, "MDB fanout lookup queue was not ready for first lookup"); - expect(dut.io_mdbFanoutLookupAccepted, "MDB fanout did not accept first lookup"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutLookupProcessed, "MDB fanout did not process first lookup"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutLuOutDequeued, "MDB fanout did not dequeue first LU lookup result"); - expect(dut.io_mdbFanoutSuOutDequeued, "MDB fanout did not dequeue first SU lookup result"); - expect(!dut.io_mdbFanoutLuOutHit, "first MDB lookup after nuke unexpectedly hit"); - expect(!dut.io_mdbFanoutSuOutHit, "first MDB SU lookup after nuke unexpectedly hit"); - expect(!dut.io_mdbFanoutSuMatchedStore, "first suppressed MDB lookup matched a store"); - expect(!dut.io_mdbFanoutSuWakeupValid, "first suppressed MDB lookup emitted wakeup"); - report.mdb_lookup_first_suppressed = true; - - clear_inputs(dut); - dut.io_mdbLookupValid = 1; - dut.eval(); - expect(dut.io_mdbFanoutLookupReady, "MDB fanout lookup queue was not ready for second lookup"); - expect(dut.io_mdbFanoutLookupAccepted, "MDB fanout did not accept second lookup"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutLookupProcessed, "MDB fanout did not process second lookup"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutLuOutDequeued, "MDB fanout did not dequeue second LU lookup result"); - expect(dut.io_mdbFanoutSuOutDequeued, "MDB fanout did not dequeue second SU lookup result"); - expect(dut.io_mdbFanoutLuOutHit, "reinforced MDB lookup did not hit for LU"); - expect(dut.io_mdbFanoutSuOutHit, "reinforced MDB lookup did not hit for SU"); - expect(dut.io_mdbFanoutSuMatchedStore, "MDB SU lookup did not match resident STQ row"); - expect(!dut.io_mdbFanoutSuStorePending, "MDB SU lookup reported ready resident store as pending"); - expect(dut.io_mdbFanoutSuWakeupValid, "MDB SU lookup did not emit wakeup"); - expect(dut.io_mdbFanoutSuWakeupStoreIndex == 0, "MDB SU wakeup selected the wrong STQ row"); - expect(dut.io_mdbFanoutSuWakeupBid_valid, "MDB SU wakeup did not preserve store BID valid bit"); - expect(dut.io_mdbFanoutSuWakeupBid_value == kStoreBid, "MDB SU wakeup did not preserve store BID"); - expect(dut.io_mdbLookupWaitPlanLookupHit, "MDB lookup wait planner did not see the LU hit"); - expect(dut.io_mdbLookupWaitPlanBlockedByNoTarget, - "MDB lookup wait planner did not block after the source LIQ row had cleared"); - expect(!dut.io_mdbLookupWaitPlanWaitIntentValid, - "MDB lookup wait planner unexpectedly found a current LIQ target after clear-resolved"); - expect(!dut.io_mdbLookupWaitPlanRequestValid, - "MDB lookup wait planner emitted a mutation request without a current LIQ target"); - report.mdb_lookup_hit = true; - report.mdb_su_wakeup = true; - report.mdb_su_wakeup_store_index = dut.io_mdbFanoutSuWakeupStoreIndex; - report.mdb_lookup_wait_plan_no_target = true; - report.mdb_lookup_wait_plan_candidate_mask = dut.io_mdbLookupWaitPlanCandidateMask; - - clear_inputs(dut); - drive_store(dut, kStoreAddr, kSecondStoreBid, kSecondStoreLsId); - dut.eval(); - expect(dut.io_storeInsertAccepted, "second STA insert was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - drive_load(dut, true, kSecondLoadBid, kSecondLoadLsId); - dut.eval(); - expect(dut.io_forwardWaitBlocked, "second STA-only row did not block younger load"); - expect(dut.io_forwardWaitStoreValid, "second STA-only row did not produce wait-store key"); - expect(dut.io_forwardWaitStoreIndex == 1, "second STA-only wait-store key selected the wrong STQ index"); - expect(dut.io_waitSlotCaptureAccepted, "second STA-only wait-store was not captured"); - tick(dut, cycle); - - clear_inputs(dut); - drive_store(dut, kStoreData, kSecondStoreBid, kSecondStoreLsId); - dut.eval(); - expect(dut.io_storeInsertAccepted, "second STD merge was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_waitStoreClear, "second store wakeup did not clear wait replay slot"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_relaunchQueueOutFire, "second relaunch queue did not fire into LIQ path"); - expect(dut.io_liqAllocAccepted, "second LIQ path did not accept relaunch candidate"); - tick(dut, cycle); - - clear_inputs(dut); - dut.io_liqRefillValid = 1; - dut.io_liqRefillLineAddr = kLoadLineAddr; - dut.io_liqRefillData[0] = static_cast(kRefillDataLow); - dut.io_liqRefillData[1] = static_cast(kRefillDataLow >> 32); - dut.eval(); - expect(dut.io_liqRefillAccepted, "second LIQ refill wakeup was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - drive_scb_replay_wake(dut); - dut.eval(); - expect((dut.io_liqReplayWakeMergeMask & 0x2) != 0, - "second LIQ SCB replay wake did not merge row 1 before MDB mutation"); - expect((dut.io_liqReplayWakeCompletedMask & 0x2) != 0, - "second LIQ SCB replay wake did not complete row 1 before MDB mutation"); - report.liq_replay_wake_completed_mask = dut.io_liqReplayWakeCompletedMask; - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect((dut.io_liqScbReturnedMask & 0x2) != 0, - "second LIQ row did not retain SCB-return evidence after replay wake"); - expect((dut.io_liqSourcesReturnedMask & 0x2) != 0, - "second LIQ row did not retain sources-returned evidence after replay wake"); - report.mdb_lookup_wait_plan_scb_evidence = true; - report.liq_sources_returned_mask_before_mdb_write = dut.io_liqSourcesReturnedMask; - report.liq_scb_returned_mask_before_mdb_write = dut.io_liqScbReturnedMask; - - clear_inputs(dut); - drive_live_lookup_load_identity(dut); - dut.eval(); - expect(dut.io_mdbFanoutLookupReady, "MDB fanout lookup queue was not ready for live second lookup"); - expect(dut.io_mdbFanoutLookupAccepted, "MDB fanout did not accept live second lookup"); - tick(dut, cycle); - - clear_inputs(dut); - dut.io_liqLaunchEnable = 1; - dut.eval(); - expect(dut.io_mdbFanoutLookupProcessed, "MDB fanout did not process live second lookup"); - expect(dut.io_liqLaunchAccepted, "second LIQ launch was not accepted"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutLuOutDequeued, "MDB fanout did not dequeue live second LU lookup result"); - expect(dut.io_mdbFanoutSuOutDequeued, "MDB fanout did not dequeue live second SU lookup result"); - expect(dut.io_mdbFanoutLuOutHit, "live second MDB lookup did not hit for LU"); - expect(dut.io_mdbFanoutSuOutHit, "live second MDB lookup did not hit for SU"); - expect(dut.io_mdbLookupWaitPlanLookupHit, "MDB lookup wait planner did not see live second LU hit"); - expect(dut.io_mdbLookupWaitPlanCandidateMask == 0x2, - "MDB lookup wait planner did not find the live Repick LIQ row" + mask_diag(dut)); - expect(dut.io_mdbLookupWaitPlanTargetIndex == 1, - "MDB lookup wait planner selected the wrong live LIQ row" + mask_diag(dut)); - expect(dut.io_mdbLookupWaitPlanWaitIntentValid, - "MDB lookup wait planner did not produce live second wait intent"); - expect(dut.io_mdbLookupWaitPlanRequestValid, - "MDB lookup wait planner did not produce live second row mutation request"); - expect(dut.io_rowMutationBridgeValid, - "MDB lookup wait planner request did not reach the LIQ row-mutation bridge"); - expect(dut.io_rowMutationTargetEvidenceValid, - "live second row mutation did not see the SCB-returned target evidence"); - expect(!dut.io_rowMutationBlockedByControl, - "live second row mutation was blocked even after SCB source-return evidence"); - expect(dut.io_rowMutationWriteEnable, - "live second row mutation did not write after source-return evidence"); - expect(dut.io_rowMutationApplyValid, - "live second row mutation did not apply after source-return evidence"); - report.mdb_lookup_wait_plan_live_target = true; - report.mdb_lookup_wait_plan_request = true; - report.mdb_lookup_wait_plan_bridge = true; - report.mdb_lookup_wait_plan_control_blocked = false; - report.mdb_lookup_wait_plan_write = true; - report.mdb_lookup_wait_plan_apply = true; - report.mdb_lookup_wait_plan_live_candidate_mask = dut.io_mdbLookupWaitPlanCandidateMask; - report.mdb_lookup_wait_plan_live_target_index = dut.io_mdbLookupWaitPlanTargetIndex; - - tick(dut, cycle); - clear_inputs(dut); - dut.eval(); - expect((dut.io_liqWaitMask & 0x2) != 0, - "MDB wait mutation did not return live row 1 to Wait"); - expect((dut.io_liqWaitStoreMask & 0x2) != 0, - "MDB wait mutation did not arm wait-store state on live row 1"); - expect((dut.io_liqRepickMask & 0x2) == 0, - "MDB wait mutation left live row 1 in Repick"); - expect((dut.io_liqScbReturnedMask & 0x2) == 0, - "MDB wait mutation did not clear source-return state on live row 1"); - report.mdb_lookup_wait_plan_wait_status_after_write = true; - report.liq_wait_mask_after_mdb_write = dut.io_liqWaitMask; - report.liq_wait_store_mask_after_mdb_write = dut.io_liqWaitStoreMask; - - clear_inputs(dut); - dut.io_mdbDeleteValid = 1; - dut.io_mdbDeleteWaitStorePc = kStorePc; - dut.eval(); - expect(dut.io_mdbFanoutDeleteReady, "MDB fanout delete queue was not ready for first delete"); - expect(dut.io_mdbFanoutDeleteAccepted, "MDB fanout did not accept first delete"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutDeleteProcessed, "MDB fanout did not process first delete"); - expect(dut.io_mdbFanoutDeleteMatched, "MDB first delete did not match the learned SSIT row"); - expect(dut.io_mdbFanoutDeleteDroppedBelowStall, "MDB first delete did not report drop below stall threshold"); - expect(!dut.io_mdbFanoutDeleteReleased, "MDB first delete released the row too early"); - expect((dut.io_mdbFanoutSsitValidMask & 0x1) != 0, "MDB SSIT row was released after first delete"); - report.mdb_delete_accepted = true; - report.mdb_delete_dropped_below_stall = true; - - for (int delete_index = 0; delete_index < 2; ++delete_index) { - clear_inputs(dut); - dut.io_mdbDeleteValid = 1; - dut.io_mdbDeleteWaitStorePc = kStorePc; - dut.eval(); - expect(dut.io_mdbFanoutDeleteReady, "MDB fanout delete queue was not ready for release delete"); - expect(dut.io_mdbFanoutDeleteAccepted, "MDB fanout did not accept release delete"); - tick(dut, cycle); - - clear_inputs(dut); - dut.eval(); - expect(dut.io_mdbFanoutDeleteProcessed, "MDB fanout did not process release delete"); - expect(dut.io_mdbFanoutDeleteMatched, "MDB release delete did not match the learned SSIT row"); - if (delete_index == 0) { - expect(dut.io_mdbFanoutDeleteDroppedBelowStall, "MDB second delete did not retain below-stall diagnostic"); - expect(!dut.io_mdbFanoutDeleteReleased, "MDB second delete released before zero-weight retry"); - expect((dut.io_mdbFanoutSsitValidMask & 0x1) != 0, "MDB SSIT row released before zero-weight retry"); - } else { - expect(!dut.io_mdbFanoutDeleteDroppedBelowStall, "MDB release delete reported decay instead of release"); - expect(dut.io_mdbFanoutDeleteReleased, "MDB zero-weight delete did not release the SSIT row"); - expect((dut.io_mdbFanoutSsitValidMask & 0x1) == 0, "MDB SSIT row remained valid after release delete"); - report.mdb_delete_released = true; - } - } - - clear_inputs(dut); - dut.io_resolveQueueRetireValid = 1; - dut.io_resolveQueueRetireBid_valid = 1; - // This fixture does not carry a full retire LSID input. Use a cross-BID - // watermark so retirement never fabricates same-BID full-LSID authority. - dut.io_resolveQueueRetireBid_value = kLoadBid + 1; - dut.io_resolveQueueRetireLsId_valid = 1; - dut.io_resolveQueueRetireLsId_value = kLoadLsId + 1; - dut.eval(); - expect((dut.io_resolveQueueRetireMask & 0x1) != 0, "ResolveQ retire did not select the resolved row"); - expect(dut.io_resolveQueueRetireCount == 1, "ResolveQ retire count did not report one row"); - - tick(dut, cycle); - clear_inputs(dut); - dut.eval(); - expect(dut.io_resolveQueueCount == 0, "ResolveQ row remained resident after retire watermark"); - expect(dut.io_resolveQueueValidMask == 0, "ResolveQ valid mask remained set after retire watermark"); - report.resolve_queue_retired = true; - report.resolve_queue_count_after_retire = dut.io_resolveQueueCount; -} - -void write_report(const std::string &path, const Report &report) { - if (path.empty()) { - return; - } - std::ofstream out(path); - if (!out) { - fail("failed to open report JSON: " + path); - } - out << "{\n" - << " \"schema\": \"linxcore.reduced_store_wait_replay_chisel_path.v1\",\n" - << " \"cycles\": " << report.cycles << ",\n" - << " \"ready_forward_observed\": " << (report.ready_forward_observed ? "true" : "false") << ",\n" - << " \"sta_wait_capture\": " << (report.sta_wait_capture ? "true" : "false") << ",\n" - << " \"not_ready_wake_blocked\": " << (report.not_ready_wake_blocked ? "true" : "false") << ",\n" - << " \"std_wake_clear\": " << (report.std_wake_clear ? "true" : "false") << ",\n" - << " \"relaunch_queue_fire\": " << (report.relaunch_queue_fire ? "true" : "false") << ",\n" - << " \"liq_alloc\": " << (report.liq_alloc ? "true" : "false") << ",\n" - << " \"liq_refill\": " << (report.liq_refill ? "true" : "false") << ",\n" - << " \"liq_launch_valid\": " << (report.liq_launch_valid ? "true" : "false") << ",\n" - << " \"liq_launch_accepted\": " << (report.liq_launch_accepted ? "true" : "false") << ",\n" - << " \"liq_e4_update\": " << (report.liq_e4_update ? "true" : "false") << ",\n" - << " \"liq_lhq_record\": " << (report.liq_lhq_record ? "true" : "false") << ",\n" - << " \"liq_resolved\": " << (report.liq_resolved ? "true" : "false") << ",\n" - << " \"resolve_queue_push\": " << (report.resolve_queue_push ? "true" : "false") << ",\n" - << " \"liq_clear_resolved\": " << (report.liq_clear_resolved ? "true" : "false") << ",\n" - << " \"mdb_resolve_conflict\": " << (report.mdb_resolve_conflict ? "true" : "false") << ",\n" - << " \"mdb_nuke_flush\": " << (report.mdb_nuke_flush ? "true" : "false") << ",\n" - << " \"mdb_fanout_record_accepted\": " << (report.mdb_fanout_record_accepted ? "true" : "false") << ",\n" - << " \"mdb_fanout_record_processed\": " << (report.mdb_fanout_record_processed ? "true" : "false") << ",\n" - << " \"mdb_bmdb_report\": " << (report.mdb_bmdb_report ? "true" : "false") << ",\n" - << " \"mdb_fanout_record_reinforced\": " << (report.mdb_fanout_record_reinforced ? "true" : "false") << ",\n" - << " \"mdb_lookup_first_suppressed\": " << (report.mdb_lookup_first_suppressed ? "true" : "false") << ",\n" - << " \"mdb_lookup_hit\": " << (report.mdb_lookup_hit ? "true" : "false") << ",\n" - << " \"mdb_su_wakeup\": " << (report.mdb_su_wakeup ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_no_target\": " << (report.mdb_lookup_wait_plan_no_target ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_live_target\": " - << (report.mdb_lookup_wait_plan_live_target ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_request\": " - << (report.mdb_lookup_wait_plan_request ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_bridge\": " - << (report.mdb_lookup_wait_plan_bridge ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_control_blocked\": " - << (report.mdb_lookup_wait_plan_control_blocked ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_scb_evidence\": " - << (report.mdb_lookup_wait_plan_scb_evidence ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_write\": " - << (report.mdb_lookup_wait_plan_write ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_apply\": " - << (report.mdb_lookup_wait_plan_apply ? "true" : "false") << ",\n" - << " \"mdb_lookup_wait_plan_wait_status_after_write\": " - << (report.mdb_lookup_wait_plan_wait_status_after_write ? "true" : "false") << ",\n" - << " \"mdb_delete_accepted\": " << (report.mdb_delete_accepted ? "true" : "false") << ",\n" - << " \"mdb_delete_dropped_below_stall\": " << (report.mdb_delete_dropped_below_stall ? "true" : "false") << ",\n" - << " \"mdb_delete_released\": " << (report.mdb_delete_released ? "true" : "false") << ",\n" - << " \"resolve_queue_retired\": " << (report.resolve_queue_retired ? "true" : "false") << ",\n" - << " \"youngest_store_lsid\": " << report.youngest_store_lsid << ",\n" - << " \"launch_load_lsid\": " << report.launch_load_lsid << ",\n" - << " \"resolve_queue_count\": " << report.resolve_queue_count << ",\n" - << " \"resolve_queue_count_after_retire\": " << report.resolve_queue_count_after_retire << ",\n" - << " \"mdb_resolve_candidate_mask\": " << report.mdb_resolve_candidate_mask << ",\n" - << " \"mdb_conflict_load_lsid\": " << report.mdb_conflict_load_lsid << ",\n" - << " \"mdb_fanout_ssit_valid_mask\": " << report.mdb_fanout_ssit_valid_mask << ",\n" - << " \"mdb_su_wakeup_store_index\": " << report.mdb_su_wakeup_store_index << ",\n" - << " \"mdb_lookup_wait_plan_candidate_mask\": " << report.mdb_lookup_wait_plan_candidate_mask << ",\n" - << " \"mdb_lookup_wait_plan_live_candidate_mask\": " - << report.mdb_lookup_wait_plan_live_candidate_mask << ",\n" - << " \"mdb_lookup_wait_plan_live_target_index\": " - << report.mdb_lookup_wait_plan_live_target_index << ",\n" - << " \"liq_replay_wake_completed_mask\": " << report.liq_replay_wake_completed_mask << ",\n" - << " \"liq_sources_returned_mask_before_mdb_write\": " - << report.liq_sources_returned_mask_before_mdb_write << ",\n" - << " \"liq_scb_returned_mask_before_mdb_write\": " - << report.liq_scb_returned_mask_before_mdb_write << ",\n" - << " \"liq_wait_mask_after_mdb_write\": " << report.liq_wait_mask_after_mdb_write << ",\n" - << " \"liq_wait_store_mask_after_mdb_write\": " - << report.liq_wait_store_mask_after_mdb_write << ",\n" - << " \"e4_cycles_after_launch\": " << report.e4_cycles_after_launch << "\n" - << "}\n"; -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - const Args args = parse_args(argc, argv); - - VReducedStoreWaitReplayChiselPathProbe dut; - std::uint64_t cycle = 0; - Report report; - - run_ready_store_negative(dut, cycle, report); - run_sta_only_replay_path(dut, cycle, report); - report.cycles = cycle; - write_report(args.report_json, report); - - std::cout << "reduced-store-wait-replay-chisel-path: pass" - << " cycles=" << report.cycles - << " youngest_store_lsid=" << report.youngest_store_lsid - << " launch_load_lsid=" << report.launch_load_lsid - << " e4_cycles_after_launch=" << report.e4_cycles_after_launch << "\n"; - return 0; -} diff --git a/tools/chisel/render_top_interface_manifest.py b/tools/chisel/render_top_interface_manifest.py new file mode 100644 index 00000000..b9573e68 --- /dev/null +++ b/tools/chisel/render_top_interface_manifest.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python3 +"""Regenerate or verify the canonical TOP interface manifest.""" + +from __future__ import annotations + +import argparse +import os +import shutil +import subprocess +import tempfile +from pathlib import Path + + +ROOT = Path(__file__).resolve().parents[2] +CHISEL = ROOT / "chisel" +JSON_TARGET = ROOT / "docs/chisel/generated/top-interface-manifest.json" +MARKDOWN_TARGET = ROOT / "docs/chisel/generated/top-interface-manifest.md" + + +def emit(json_path: Path, markdown_path: Path) -> None: + command = ( + f"source {ROOT / 'tools/chisel/chisel_env.sh'} && " + f"cd {CHISEL} && " + "sbt --server --batch --no-colors " + '--mem "${LINX_CHISEL_SBT_MEM_MB}" ' + f"'runMain linxcore.top.interface.EmitInterfaceManifest " + f"--json {json_path} --markdown {markdown_path}'" + ) + subprocess.run(["bash", "-c", command], check=True, env=os.environ.copy()) + + +def same(left: Path, right: Path) -> bool: + return left.is_file() and right.is_file() and left.read_bytes() == right.read_bytes() + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument( + "--check", + action="store_true", + help="fail when checked-in generated files differ from the Bundle projection", + ) + args = parser.parse_args() + + with tempfile.TemporaryDirectory(prefix="linxcore-interface-manifest-") as tmp: + temporary = Path(tmp) + emitted_json = temporary / JSON_TARGET.name + emitted_markdown = temporary / MARKDOWN_TARGET.name + emit(emitted_json, emitted_markdown) + + if args.check: + stale = [] + if not same(JSON_TARGET, emitted_json): + stale.append(JSON_TARGET) + if not same(MARKDOWN_TARGET, emitted_markdown): + stale.append(MARKDOWN_TARGET) + if stale: + for path in stale: + print(f"stale generated interface manifest: {path}") + return 1 + print("top-interface-manifest: up to date") + return 0 + + JSON_TARGET.parent.mkdir(parents=True, exist_ok=True) + shutil.copyfile(emitted_json, JSON_TARGET) + shutil.copyfile(emitted_markdown, MARKDOWN_TARGET) + print(f"wrote {JSON_TARGET}") + print(f"wrote {MARKDOWN_TARGET}") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/chisel/report_scalar_instruction_coverage.py b/tools/chisel/report_scalar_instruction_coverage.py index b4177f4b..5b8e9a80 100755 --- a/tools/chisel/report_scalar_instruction_coverage.py +++ b/tools/chisel/report_scalar_instruction_coverage.py @@ -45,8 +45,8 @@ def _first_existing_path(candidates: tuple[Path, ...]) -> Path: / "main" / "scala" / "linxcore" - / "execute" - / "ReducedScalarAluExecute.scala" + / "ooo" + / "OooIexAluPipeline.scala" ) DEFAULT_SRC = ROOT / "src" @@ -320,6 +320,16 @@ def _parse_frontend_symbols(path: Path) -> set[str]: LEGACY_END_SIGNATURE = "private def ldiScaledOffset(imm: UInt): UInt =" SOURCE_SHAPE_CONTRACTS = { + "ooo_current": { + "start_signature": "object OooIexAluPipeline {", + "end_signature": "\n}\n\n/** One-cycle integer ALU", + "forbidden_private_def_between_markers": False, + "expected": { + "frontend_strict_decode": {"covered": 547, "denominator": 547}, + "reduced_scalar_alu_support": {"covered": 17, "denominator": 547}, + "cross_stack_aligned_support": {"covered": 17, "denominator": 547}, + }, + }, "expanded_current": { "start_signature": IS_SUPPORTED_SIGNATURE, "end_signature": EXPANDED_END_SIGNATURE, @@ -352,10 +362,14 @@ def _extract_is_supported_body(path: Path) -> tuple[str, str, dict[str, Any]]: text = path.read_text(encoding="utf-8") start = text.find(IS_SUPPORTED_SIGNATURE) if start < 0: - raise ValueError( - f"{path}: could not isolate isSupported source-shape contract " - f"({IS_SUPPORTED_SIGNATURE!r} not found)" - ) + contract = SOURCE_SHAPE_CONTRACTS["ooo_current"] + start = text.find(contract["start_signature"]) + end = text.find(contract["end_signature"], start) + if start < 0 or end < 0: + raise ValueError( + f"{path}: could not isolate a supported-opcode source-shape contract" + ) + return "ooo_current", text[start:end], contract expanded_end = text.find(EXPANDED_END_SIGNATURE, start + len(IS_SUPPORTED_SIGNATURE)) legacy_end = text.find(LEGACY_END_SIGNATURE, start + len(IS_SUPPORTED_SIGNATURE)) diff --git a/tools/chisel/run_chisel_backend_c_addi_execute_probe.sh b/tools/chisel/run_chisel_backend_c_addi_execute_probe.sh deleted file mode 100755 index 2a540e39..00000000 --- a/tools/chisel/run_chisel_backend_c_addi_execute_probe.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -BUILD_ARG="generated/chisel-verilator/backend-c-addi-execute-probe" -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - if [[ $# -lt 2 ]]; then - echo "error: --build-dir requires a value" >&2 - exit 2 - fi - BUILD_ARG="$2" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_ARG}" = /* ]]; then - BUILD_DIR="${BUILD_ARG}" -else - BUILD_DIR="${ROOT_DIR}/${BUILD_ARG}" -fi -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" - -rm -rf "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${OBJ_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluHlSdiPrProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no SystemVerilog sources emitted under ${SV_DIR}" >&2 - exit 2 -fi - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluHlSdiPrProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_c_addi_execute_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${OBJ_DIR}" \ - -o backend_c_addi_execute_probe_tb -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/backend_c_addi_execute_probe_tb" diff --git a/tools/chisel/run_chisel_backend_implicit_sp_order_probe.sh b/tools/chisel/run_chisel_backend_implicit_sp_order_probe.sh deleted file mode 100755 index 32339ec7..00000000 --- a/tools/chisel/run_chisel_backend_implicit_sp_order_probe.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r875-karnaugh-implicit-sp-order-probe" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-trace-top" - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - if [[ $# -lt 2 ]]; then - echo "error: --build-dir requires a value" >&2 - exit 2 - fi - BUILD_DIR="$2" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -OBJ_DIR="${BUILD_DIR}/obj_dir" -mkdir -p "${BUILD_DIR}" -rm -rf "${OBJ_DIR}" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -( - cd "${ROOT_DIR}/chisel" - sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendFetchRfAluTraceTop" -) - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no SystemVerilog files emitted under ${SV_DIR}" >&2 - exit 2 -fi - -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendFetchRfAluTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/backend_implicit_sp_order_probe_tb.cpp" \ - --build \ - --build-jobs 0 \ - -Mdir "${OBJ_DIR}" \ - -o backend_implicit_sp_order_probe_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/backend_implicit_sp_order_probe_tb" diff --git a/tools/chisel/run_chisel_backend_lui_execute_probe.sh b/tools/chisel/run_chisel_backend_lui_execute_probe.sh deleted file mode 100755 index f9b190e6..00000000 --- a/tools/chisel/run_chisel_backend_lui_execute_probe.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -BUILD_ARG="generated/chisel-verilator/backend-lui-execute-probe" -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - if [[ $# -lt 2 ]]; then - echo "error: --build-dir requires a value" >&2 - exit 2 - fi - BUILD_ARG="$2" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_ARG}" = /* ]]; then - BUILD_DIR="${BUILD_ARG}" -else - BUILD_DIR="${ROOT_DIR}/${BUILD_ARG}" -fi -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" - -rm -rf "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${OBJ_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluHlSdiPrProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no SystemVerilog sources emitted under ${SV_DIR}" >&2 - exit 2 -fi - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluHlSdiPrProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_lui_execute_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${OBJ_DIR}" \ - -o backend_lui_execute_probe_tb -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/backend_lui_execute_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_rob_completion_arbiter_behavior_probe.sh b/tools/chisel/run_chisel_backend_reduced_rob_completion_arbiter_behavior_probe.sh deleted file mode 100755 index 6e61d9b1..00000000 --- a/tools/chisel/run_chisel_backend_reduced_rob_completion_arbiter_behavior_probe.sh +++ /dev/null @@ -1,110 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r925-moore-behavior" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-1}" - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the completion-arbiter behavior probe" >&2 - exit 2 -fi - -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TOP_MODULE="ReducedRobCompletionArbiterBehaviorProbe" -EMIT_MAIN="linxcore.backend.EmitReducedRobCompletionArbiterBehaviorProbe" -TESTBENCH="${ROOT_DIR}/tools/chisel/backend_reduced_rob_completion_arbiter_behavior_probe_tb.cpp" -MISMATCH_LOG="${BUILD_DIR}/parent-slot-mismatch.log" - -rm -rf "${SV_DIR}" "${OBJ_DIR}" -mkdir -p "${SV_DIR}" "${OBJ_DIR}" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain ${EMIT_MAIN} --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${SV_DIR}/${source}") -done <"${SV_DIR}/filelist.f" -assert_sources=() -if [[ -d "${SV_DIR}/verification/assert" ]]; then - while IFS= read -r source; do - already_listed=false - for listed in "${sv_sources[@]}"; do - if [[ "${listed}" == "${source}" ]]; then - already_listed=true - break - fi - done - if [[ "${already_listed}" == false ]]; then - assert_sources+=("${source}") - fi - done < <(find "${SV_DIR}/verification/assert" -type f -name '*.sv' | sort) -fi -sv_sources+=("${assert_sources[@]}") -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no emitted SystemVerilog under ${SV_DIR}" >&2 - exit 2 -fi -if [[ "${#assert_sources[@]}" -eq 0 ]]; then - echo "error: emitted completion-arbiter probe did not produce an assert layer" >&2 - exit 1 -fi -if grep -R -i -q --include='*.sv' 'exactComplete' "${SV_DIR}"; then - echo "error: emitted completion-arbiter probe contains an exactComplete path" >&2 - exit 1 -fi - -verilator \ - --assert \ - --cc "${sv_sources[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${TESTBENCH}" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - "-I${SV_DIR}/verification" \ - "-I${SV_DIR}/verification/assert" \ - -Mdir "${OBJ_DIR}" \ - -o backend_reduced_rob_completion_arbiter_behavior_probe_tb \ - -CFLAGS '-std=c++17 -O2' - -PROBE="${OBJ_DIR}/backend_reduced_rob_completion_arbiter_behavior_probe_tb" -"${PROBE}" - -set +e -"${PROBE}" --trigger-parent-slot-mismatch >"${MISMATCH_LOG}" 2>&1 -mismatch_rc=$? -set -e -if [[ "${mismatch_rc}" -eq 0 ]]; then - echo "error: parent-slot mismatch was silently accepted" >&2 - exit 1 -fi -if ! grep -F -q 'template completion parent slot must match' "${MISMATCH_LOG}"; then - echo "error: mismatch failed without the real parent-slot hardware assertion" >&2 - cat "${MISMATCH_LOG}" >&2 - exit 1 -fi - -echo "backend-reduced-rob-completion-arbiter-parent-slot-assertion: PASS (rc=${mismatch_rc})" -echo "backend-reduced-rob-completion-arbiter-exact-complete-absence: PASS" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_addiw_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_addiw_probe.sh deleted file mode 100755 index d9c06174..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_addiw_probe.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/backend-reduced-scalar-alu-addiw-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/backend-reduced-scalar-alu-addiw-probe" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluAddiwProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluAddiwProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_addiw_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${BUILD_DIR}/obj_dir" \ - -o backend_reduced_scalar_alu_addiw_probe_tb -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/backend_reduced_scalar_alu_addiw_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_hl_sdi_pr_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_hl_sdi_pr_probe.sh deleted file mode 100755 index 268cdfa7..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_hl_sdi_pr_probe.sh +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -BUILD_ARG="generated/chisel-verilator/backend-reduced-scalar-alu-hl-sdi-pr-probe" -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_ARG="$2" - shift 2 - ;; - *) - echo "unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_ARG}" = /* ]]; then - BUILD_DIR="${BUILD_ARG}" -else - BUILD_DIR="${ROOT_DIR}/${BUILD_ARG}" -fi -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" - -rm -rf "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${OBJ_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluHlSdiPrProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluHlSdiPrProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_hl_sdi_pr_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${OBJ_DIR}" \ - -o backend_reduced_scalar_alu_hl_sdi_pr_probe_tb -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/backend_reduced_scalar_alu_hl_sdi_pr_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_lbu_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_lbu_probe.sh deleted file mode 100755 index 6cbf664f..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_lbu_probe.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/backend-reduced-scalar-alu-lbu-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/backend-reduced-scalar-alu-lbu-probe" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluLbuProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluLbuProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_lbu_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${BUILD_DIR}/obj_dir" \ - -o backend_reduced_scalar_alu_lbu_probe_tb -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/backend_reduced_scalar_alu_lbu_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_sb_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_sb_probe.sh deleted file mode 100755 index cc391c56..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_sb_probe.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/backend-reduced-scalar-alu-sb-probe-r811" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/backend-reduced-scalar-alu-sb-probe-r811" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluSbProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluSbProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_sb_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${BUILD_DIR}/obj_dir" \ - -o backend_reduced_scalar_alu_sb_probe_tb -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/backend_reduced_scalar_alu_sb_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_compare_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_compare_probe.sh deleted file mode 100755 index 2e6b7f4b..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_compare_probe.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/backend-reduced-scalar-alu-setc-compare-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/backend-reduced-scalar-alu-setc-compare-probe" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.execute.EmitReducedScalarAluSetcCompareProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedScalarAluSetcCompareProbe \ - --exe "${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_setc_compare_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${BUILD_DIR}/obj_dir" \ - -o backend_reduced_scalar_alu_setc_compare_probe_tb -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/backend_reduced_scalar_alu_setc_compare_probe_tb" diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_immediate_behavior_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_immediate_behavior_probe.sh deleted file mode 100755 index a6da9da9..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_alu_setc_immediate_behavior_probe.sh +++ /dev/null @@ -1,242 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r992-johnson-setc-immediate" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-1}" -EXPECT_CURRENT_RED="${EXPECT_CURRENT_RED:-0}" -SELF_TEST=0 - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - --self-test) - SELF_TEST=1 - shift - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -PROBE_SOURCE="${ROOT_DIR}/chisel/src/test/scala/linxcore/execute/ReducedScalarAluSetcImmediateBehaviorProbe.scala" -R965_SOURCE="${ROOT_DIR}/chisel/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala" -R965_EXPECTED_HASH="3a457c2447017396c63f3195b54d097b966e4888a6069f3bb10b90cc63e8e7f2" -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" -EMIT_LOG="${BUILD_DIR}/emit.log" -TB_LOG="${BUILD_DIR}/tb.log" -TOP_MODULE="ReducedScalarAluSetcImmediateBehaviorProbe" -EMIT_MAIN="linxcore.execute.EmitReducedScalarAluSetcImmediateBehaviorProbe" -TESTBENCH="${ROOT_DIR}/tools/chisel/backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb.cpp" -EXCLUDED_R965_LOG="${BUILD_DIR}/excluded-r965-sha256.txt" - -cleanup() { - rm -rf -- "${BUILD_DIR}" -} -trap cleanup EXIT - -hash_file() { - shasum -a 256 "$1" | awk '{print $1}' -} - -classify_exact_setc_immediate_current_red() { - local log="$1" - local tb_rc="$2" - local line_count total_count line - [[ "${tb_rc}" -eq 1 ]] || return 1 - total_count="$(wc -l <"${log}" | tr -d '[:space:]')" - [[ "${total_count}" == "1" ]] || return 1 - line_count="$(grep -E -c '^backend-reduced-scalar-alu-setc-immediate-behavior-probe:' "${log}" || true)" - [[ "${line_count}" == "1" ]] || return 1 - line="$(grep -E '^backend-reduced-scalar-alu-setc-immediate-behavior-probe:' "${log}" || true)" - [[ "${line}" == "backend-reduced-scalar-alu-setc-immediate-behavior-probe: first-red accepted OP_SETC_EQI 329 and observed unsupportedOpcode=329 with release BID=3/0 GID=4/1 RID=5/0 STID=0; no completeValid/no branchConditionValid/no writeback/no duplicate pulses" ]] -} - -run_self_test() { - local dir exact subset superset wrong wrong_release foreign timeout zero_rc duplicate reordered - dir="$(mktemp -d)" - exact="${dir}/exact.log" - subset="${dir}/subset.log" - superset="${dir}/superset.log" - wrong="${dir}/wrong.log" - wrong_release="${dir}/wrong-release.log" - foreign="${dir}/foreign.log" - timeout="${dir}/timeout.log" - zero_rc="${dir}/zero-rc.log" - duplicate="${dir}/duplicate.log" - reordered="${dir}/reordered.log" - - echo "backend-reduced-scalar-alu-setc-immediate-behavior-probe: first-red accepted OP_SETC_EQI 329 and observed unsupportedOpcode=329 with release BID=3/0 GID=4/1 RID=5/0 STID=0; no completeValid/no branchConditionValid/no writeback/no duplicate pulses" >"${exact}" - : >"${subset}" - { cat "${exact}"; echo "backend-reduced-scalar-alu-setc-immediate-behavior-probe: extra failure"; } >"${superset}" - sed 's/OP_SETC_EQI 329/OP_SETC_NEI 339/' "${exact}" >"${wrong}" - sed 's|BID=3/0|BID=3/1|' "${exact}" >"${wrong_release}" - echo "other-probe: first-red accepted OP_SETC_EQI 329 and observed unsupportedOpcode=329 with release BID=3/0 GID=4/1 RID=5/0 STID=0; no completeValid/no branchConditionValid/no writeback/no duplicate pulses" >"${foreign}" - { cat "${exact}"; echo "timed out waiting for verilator"; } >"${timeout}" - cp "${exact}" "${zero_rc}" - { cat "${exact}"; cat "${exact}"; } >"${duplicate}" - echo "backend-reduced-scalar-alu-setc-immediate-behavior-probe: observed unsupportedOpcode=329 before release identity for first-red accepted OP_SETC_EQI 329" >"${reordered}" - - classify_exact_setc_immediate_current_red "${exact}" 1 || - { rm -rf -- "${dir}"; echo "error: exact current-red classifier rejected its positive case" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${subset}" 1 || - { rm -rf -- "${dir}"; echo "error: subset passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${superset}" 1 || - { rm -rf -- "${dir}"; echo "error: superset passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${wrong}" 1 || - { rm -rf -- "${dir}"; echo "error: wrong opcode passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${wrong_release}" 1 || - { rm -rf -- "${dir}"; echo "error: wrong release identity passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${foreign}" 1 || - { rm -rf -- "${dir}"; echo "error: foreign failure passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${timeout}" 1 || - { rm -rf -- "${dir}"; echo "error: timeout contamination passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${duplicate}" 1 || - { rm -rf -- "${dir}"; echo "error: duplicate record passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${reordered}" 1 || - { rm -rf -- "${dir}"; echo "error: reordered text passed current-red classifier" >&2; return 1; } - ! classify_exact_setc_immediate_current_red "${zero_rc}" 0 || - { rm -rf -- "${dir}"; echo "error: zero return code passed current-red classifier" >&2; return 1; } - - rm -rf -- "${dir}" - echo "backend-reduced-scalar-alu-setc-immediate-behavior-runner-self-test: PASS" -} - -if [[ "${SELF_TEST}" -eq 1 ]]; then - run_self_test - exit 0 -fi - -if [[ "${EXPECT_CURRENT_RED}" != 0 && "${EXPECT_CURRENT_RED}" != 1 ]]; then - echo "error: EXPECT_CURRENT_RED must be 0 or 1" >&2 - exit 2 -fi -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the SETC-immediate behavior probe" >&2 - exit 2 -fi -if [[ ! -f "${R965_SOURCE}" ]]; then - echo "error: required R965 exclusion source is missing: ${R965_SOURCE}" >&2 - exit 2 -fi - -mkdir -p "${SV_DIR}" "${OBJ_DIR}" -R965_HASH_BEFORE="$(hash_file "${R965_SOURCE}")" -if [[ "${R965_HASH_BEFORE}" != "${R965_EXPECTED_HASH}" ]]; then - echo "error: R965 exclusion source hash changed before run: ${R965_HASH_BEFORE}" >&2 - exit 2 -fi -printf 'TemplateAcceptedSidecarHandoffProbe.scala %s\n' "${R965_HASH_BEFORE}" >"${EXCLUDED_R965_LOG}" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -set +e -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - 'set Test / unmanagedSources := (Test / unmanagedSources).value.filterNot(_.getName == "TemplateAcceptedSidecarHandoffProbe.scala")' \ - "Test / runMain ${EMIT_MAIN} --target-dir ${SV_DIR}" -) >"${EMIT_LOG}" 2>&1 -emit_rc=$? -set -e - -R965_HASH_AFTER="$(hash_file "${R965_SOURCE}")" -if [[ "${R965_HASH_AFTER}" != "${R965_HASH_BEFORE}" ]]; then - echo "error: R965 exclusion source hash changed during run: before=${R965_HASH_BEFORE} after=${R965_HASH_AFTER}" >&2 - exit 2 -fi -printf 'TemplateAcceptedSidecarHandoffProbe.scala %s\n' "${R965_HASH_AFTER}" >>"${EXCLUDED_R965_LOG}" - -if [[ "${emit_rc}" -ne 0 ]]; then - echo "error: emit failed before SETC-immediate behavior simulation" >&2 - cat "${EMIT_LOG}" >&2 - exit 2 -fi - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' -print | sort) -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no emitted SystemVerilog under ${SV_DIR}" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module ReducedScalarAluExecute' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real ReducedScalarAluExecute" >&2 - exit 2 -fi - -set +e -verilator \ - --cc "${sv_sources[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${TESTBENCH}" \ - --output-split 2000 \ - --output-split-cfuncs 2000 \ - -Mdir "${OBJ_DIR}" \ - -o backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb \ - -CFLAGS '-std=c++17 -O0 -g0' >"${BUILD_DIR}/verilator.log" 2>&1 -verilator_rc=$? -set -e -if [[ "${verilator_rc}" -ne 0 ]]; then - echo "error: Verilator generation failed before SETC-immediate behavior simulation" >&2 - cat "${BUILD_DIR}/verilator.log" >&2 - exit 2 -fi - -perl -0pi -e 's/\$\(VK_USER_OBJS\) \$\(VK_GLOBAL_OBJS\) \$\(VM_PREFIX\)__ALL\.a/\$\(VK_USER_OBJS\) \$\(VK_GLOBAL_OBJS\) \$\(VK_OBJS\)/' \ - "${OBJ_DIR}/VReducedScalarAluSetcImmediateBehaviorProbe.mk" - -set +e -make -C "${OBJ_DIR}" \ - -f VReducedScalarAluSetcImmediateBehaviorProbe.mk \ - -j "${VERILATOR_BUILD_JOBS}" \ - VM_PARALLEL_BUILDS=1 \ - OPT_FAST='-O0' \ - OPT_SLOW='-O0' \ - OPT_GLOBAL='-O0' \ - backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb >>"${BUILD_DIR}/verilator.log" 2>&1 -make_rc=$? -set -e -if [[ "${make_rc}" -ne 0 ]]; then - echo "error: Verilator build failed before SETC-immediate behavior simulation" >&2 - cat "${BUILD_DIR}/verilator.log" >&2 - exit 2 -fi - -set +e -"${OBJ_DIR}/backend_reduced_scalar_alu_setc_immediate_behavior_probe_tb" >"${TB_LOG}" 2>&1 -tb_rc=$? -set -e - -if [[ "${tb_rc}" -ne 0 ]]; then - if classify_exact_setc_immediate_current_red "${TB_LOG}" "${tb_rc}"; then - if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - cat "${TB_LOG}" - echo "backend-reduced-scalar-alu-setc-immediate-behavior-current-red: PASS (exact OP_SETC_EQI unsupported+release first-red; route=verilator-generate,archive-free-make,VM_PARALLEL_BUILDS=1,OPT=O0,jobs=${VERILATOR_BUILD_JOBS})" - exit 0 - fi - cat "${TB_LOG}" >&2 - echo "backend-reduced-scalar-alu-setc-immediate-behavior: RED (exact OP_SETC_EQI unsupported+release first-red)" >&2 - exit 1 - fi - echo "error: testbench failed outside the exact R992 current-red boundary" >&2 - cat "${TB_LOG}" >&2 - exit 2 -fi - -cat "${TB_LOG}" -if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - echo "error: current-red mode requested, but the real DUT satisfied the SETC-immediate behavior matrix" >&2 - exit 1 -fi diff --git a/tools/chisel/run_chisel_backend_reduced_scalar_writeback_arbiter_behavior_probe.sh b/tools/chisel/run_chisel_backend_reduced_scalar_writeback_arbiter_behavior_probe.sh deleted file mode 100755 index 92029f5c..00000000 --- a/tools/chisel/run_chisel_backend_reduced_scalar_writeback_arbiter_behavior_probe.sh +++ /dev/null @@ -1,234 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r935-moore-rf-arbiter" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-1}" -EXPECT_CURRENT_RED="${EXPECT_CURRENT_RED:-0}" -SELF_TEST=0 - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - --self-test) - SELF_TEST=1 - shift - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -PROBE_SOURCE="${ROOT_DIR}/chisel/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterBehaviorProbe.scala" -PROBE_DIAGNOSTIC_SUFFIX="/src/test/scala/linxcore/execute/ReducedScalarWritebackArbiterBehaviorProbe.scala" -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" -EMIT_LOG="${BUILD_DIR}/emit.log" -TOP_MODULE="ReducedScalarWritebackArbiterBehaviorProbe" -EMIT_MAIN="linxcore.execute.EmitReducedScalarWritebackArbiterBehaviorProbe" -TESTBENCH="${ROOT_DIR}/tools/chisel/backend_reduced_scalar_writeback_arbiter_behavior_probe_tb.cpp" - -cleanup() { - rm -rf -- "${BUILD_DIR}" -} -trap cleanup EXIT - -classify_exact_missing_interface() { - local log="$1" - local emit_rc="$2" - local field - local expected_count - local primary_diagnostics - local primary_diagnostic_count - local -a fields=( - templateEnable - templateValid - templateTag - templateData - selectedTemplate - templateBlockedByDisabled - templateBlockedByExecute - templateBlockedByReplay - ) - - [[ "${emit_rc}" -eq 1 ]] || return 1 - primary_diagnostics="$( - grep -E '^\[error\] .+\.scala:[0-9]+:[0-9]+:' "${log}" || - true - )" - primary_diagnostic_count="$( - grep -E -c '^\[error\] .+\.scala:[0-9]+:[0-9]+:' "${log}" || - true - )" - [[ "${primary_diagnostic_count}" -eq "${#fields[@]}" ]] || return 1 - for field in "${fields[@]}"; do - expected_count="$( - grep -F "${PROBE_DIAGNOSTIC_SUFFIX}:" <<<"${primary_diagnostics}" | - grep -F -c ": value ${field} is not a member of linxcore.execute.ReducedScalarWritebackArbiterIO" || - true - )" - [[ "${expected_count}" -eq 1 ]] || return 1 - done - ! grep -E -q 'OutOfMemoryError|StackOverflowError|timed out|timeout|Connection refused|server failed' "${log}" -} - -outcome_status() { - local outcome="$1" - local expect_red="$2" - case "${outcome}:${expect_red}" in - missing:1|green:0) - echo 0 - ;; - missing:0|green:1) - echo 1 - ;; - *) - echo 2 - ;; - esac -} - -run_self_test() { - local dir exact cached wrong foreign same_file timeout setup - dir="$(mktemp -d)" - exact="${dir}/exact.log" - cached="${dir}/cached.log" - wrong="${dir}/wrong.log" - foreign="${dir}/foreign.log" - same_file="${dir}/same-file.log" - timeout="${dir}/timeout.log" - setup="${dir}/setup.log" - { - local field - for field in \ - templateEnable templateValid templateTag templateData \ - selectedTemplate templateBlockedByDisabled \ - templateBlockedByExecute templateBlockedByReplay; do - echo "[error] ${PROBE_SOURCE}:1:1: value ${field} is not a member of linxcore.execute.ReducedScalarWritebackArbiterIO" - done - } >"${exact}" - sed "s#${PROBE_SOURCE}#\${BASE}${PROBE_DIAGNOSTIC_SUFFIX}#" "${exact}" >"${cached}" - sed 's/value templateTag/value wrongTemplateTag/' "${exact}" >"${wrong}" - { - cat "${exact}" - echo "[error] /tmp/Unrelated.scala:7:1: value boom is not a member of Other" - } >"${foreign}" - { - cat "${exact}" - echo "[error] ${PROBE_SOURCE}:99:1: type mismatch" - } >"${same_file}" - { - cat "${exact}" - echo "[error] timed out waiting for sbt server" - } >"${timeout}" - { - cat "${exact}" - echo "[error] Connection refused while initializing compiler bridge" - } >"${setup}" - - classify_exact_missing_interface "${exact}" 1 || - { rm -rf -- "${dir}"; echo "error: exact current-red classifier rejected its positive case" >&2; return 1; } - classify_exact_missing_interface "${cached}" 1 || - { rm -rf -- "${dir}"; echo "error: cached-path current-red classifier rejected its positive case" >&2; return 1; } - ! classify_exact_missing_interface "${exact}" 0 || - { rm -rf -- "${dir}"; echo "error: successful compilation passed missing-interface classifier" >&2; return 1; } - ! classify_exact_missing_interface "${exact}" 2 || - { rm -rf -- "${dir}"; echo "error: unexpected emit status passed missing-interface classifier" >&2; return 1; } - ! classify_exact_missing_interface "${wrong}" 1 || - { rm -rf -- "${dir}"; echo "error: wrong missing member passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${foreign}" 1 || - { rm -rf -- "${dir}"; echo "error: foreign compile failure passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${same_file}" 1 || - { rm -rf -- "${dir}"; echo "error: same-file compile failure passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${timeout}" 1 || - { rm -rf -- "${dir}"; echo "error: timeout contamination passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${setup}" 1 || - { rm -rf -- "${dir}"; echo "error: setup contamination passed current-red classifier" >&2; return 1; } - - [[ "$(outcome_status missing 1)" -eq 0 ]] - [[ "$(outcome_status missing 0)" -eq 1 ]] - [[ "$(outcome_status green 1)" -eq 1 ]] - [[ "$(outcome_status green 0)" -eq 0 ]] - [[ "$(outcome_status unexpected 0)" -eq 2 ]] - rm -rf -- "${dir}" - echo "backend-reduced-scalar-writeback-arbiter-runner-self-test: PASS" -} - -if [[ "${SELF_TEST}" -eq 1 ]]; then - run_self_test - exit 0 -fi - -if [[ "${EXPECT_CURRENT_RED}" != 0 && "${EXPECT_CURRENT_RED}" != 1 ]]; then - echo "error: EXPECT_CURRENT_RED must be 0 or 1" >&2 - exit 2 -fi -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the scalar writeback-arbiter behavior probe" >&2 - exit 2 -fi - -mkdir -p "${SV_DIR}" "${OBJ_DIR}" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -set +e -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain ${EMIT_MAIN} --target-dir ${SV_DIR}" -) >"${EMIT_LOG}" 2>&1 -emit_rc=$? -set -e - -if [[ "${emit_rc}" -ne 0 ]]; then - if classify_exact_missing_interface "${EMIT_LOG}" "${emit_rc}"; then - if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - echo "backend-reduced-scalar-writeback-arbiter-current-red: PASS (exact missing template IO)" - exit 0 - fi - echo "backend-reduced-scalar-writeback-arbiter: RED (exact missing template IO)" >&2 - exit 1 - fi - echo "error: emit failed for a reason other than the exact missing template IO" >&2 - cat "${EMIT_LOG}" >&2 - exit 2 -fi - -if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - echo "error: current-red mode requested, but the real DUT exposes the template interface" >&2 - exit 1 -fi - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${SV_DIR}/${source}") -done <"${SV_DIR}/filelist.f" -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no emitted SystemVerilog under ${SV_DIR}" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module ReducedScalarWritebackArbiter' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real ReducedScalarWritebackArbiter" >&2 - exit 2 -fi - -verilator \ - --cc "${sv_sources[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${TESTBENCH}" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o backend_reduced_scalar_writeback_arbiter_behavior_probe_tb \ - -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/backend_reduced_scalar_writeback_arbiter_behavior_probe_tb" diff --git a/tools/chisel/run_chisel_bctrl_fentry_fret_natural_observation_probe.sh b/tools/chisel/run_chisel_bctrl_fentry_fret_natural_observation_probe.sh deleted file mode 100755 index b1209fa4..00000000 --- a/tools/chisel/run_chisel_bctrl_fentry_fret_natural_observation_probe.sh +++ /dev/null @@ -1,193 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${CHISEL_DIR}/generated/chisel" -TOP_MODULE="LinxCoreBenchmarkAutonomousTop" -TOP_SV="${SV_DIR}/${TOP_MODULE}.sv" -EMIT_MAIN="linxcore.top.EmitLinxCoreBenchmarkAutonomousTop" -BUILD_DIR="${ROOT_DIR}/generated/r911-johnson-fentry-fret-observation" -ELF="" -MAX_CYCLES="5000" -RESET_PC="" -RESET_SP="" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-0}" - -while [[ $# -gt 0 ]]; do - case "$1" in - --elf) - ELF="${2:-}" - shift 2 - ;; - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - --max-cycles) - MAX_CYCLES="${2:-}" - shift 2 - ;; - --reset-pc) - RESET_PC="${2:-}" - shift 2 - ;; - --reset-sp) - RESET_SP="${2:-}" - shift 2 - ;; - --qemu|--qemu-trace|--expected-rows|--replay-rows|--result-hint) - echo "error: oracle/replay option is forbidden in natural mode: $1" >&2 - exit 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ -z "${ELF}" ]]; then - echo "error: --elf is required" >&2 - exit 2 -fi -if [[ "${ELF}" != /* ]]; then - ELF="${ROOT_DIR}/${ELF}" -fi -if [[ ! -f "${ELF}" ]]; then - echo "error: ELF does not exist: ${ELF}" >&2 - exit 2 -fi -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the FENTRY/FRET natural observation probe" >&2 - exit 2 -fi - -OBJ_DIR="${BUILD_DIR}/obj_dir" -REPORT_DIR="${BUILD_DIR}/report" -MEMORY_HEX="${BUILD_DIR}/elf.load.mem" -REPORT="${REPORT_DIR}/fentry_fret_natural_observation.json" -REVISION_MANIFEST="${REPORT_DIR}/revision_manifest.json" - -mkdir -p "${REPORT_DIR}" - -python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_elf_memory.py" \ - --elf "${ELF}" \ - --output "${MEMORY_HEX}" - -read -r ELF_ENTRY ELF_STACK < <(python3 - "${ELF}" <<'PY' -import struct -import sys -from pathlib import Path - -data = Path(sys.argv[1]).read_bytes() -hdr = struct.unpack_from("<16sHHIQQQIHHHHHH", data, 0) -entry = hdr[4] -phoff, phentsize, phnum = hdr[5], hdr[9], hdr[10] -stack_top = 0 -for index in range(phnum): - off = phoff + index * phentsize - p_type, _flags, _off, vaddr, paddr, _filesz, memsz, _align = struct.unpack_from("&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${ROOT_DIR}/tools/chisel/bctrl_fentry_fret_natural_observation_probe_tb.cpp" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_bctrl_fentry_fret_natural_observation_probe_tb \ - -CFLAGS "-std=c++17 -O2 -I${ROOT_DIR}/tools/chisel" - -set +e -PROBE_SELF_TEST_ARG="" -if [[ "${SELF_TEST_ONLY:-0}" == "1" ]]; then - PROBE_SELF_TEST_ARG="--self-test-only" -fi -"${OBJ_DIR}/linxcore_bctrl_fentry_fret_natural_observation_probe_tb" \ - --memory-hex "${MEMORY_HEX}" \ - --reset-pc "${RESET_PC}" \ - --reset-sp "${RESET_SP}" \ - --max-cycles "${MAX_CYCLES}" \ - --report "${REPORT}" \ - ${PROBE_SELF_TEST_ARG} -run_status=$? -set -e - -python3 - "${ROOT_DIR}" "${ELF}" "${MEMORY_HEX}" "${REPORT}" "${REVISION_MANIFEST}" <<'PY' -import hashlib -import json -import subprocess -import sys -from pathlib import Path - -root, elf, memory, report, out_path = map(Path, sys.argv[1:]) - -def sha256(path): - h = hashlib.sha256() - with path.open("rb") as f: - for chunk in iter(lambda: f.read(1024 * 1024), b""): - h.update(chunk) - return h.hexdigest() - -def git_info(path): - rev = subprocess.check_output(["git", "-C", str(path), "rev-parse", "HEAD"], text=True).strip() - dirty = subprocess.run(["git", "-C", str(path), "diff", "--quiet"]).returncode != 0 - untracked = subprocess.check_output(["git", "-C", str(path), "ls-files", "--others", "--exclude-standard"], text=True).splitlines() - return {"revision": rev, "dirty": bool(dirty or untracked)} - -payload = { - "schema": "linxcore.bctrl_fentry_fret_observation.revision_manifest.v1", - "git": { - "superproject": git_info(root.parent.parent), - "linxcore": git_info(root), - }, - "artifacts": { - "elf": {"path": str(elf), "sha256": sha256(elf)}, - "memory_hex": {"path": str(memory), "sha256": sha256(memory)}, - "report": {"path": str(report), "sha256": sha256(report)}, - }, -} -tmp = out_path.with_suffix(out_path.suffix + ".tmp") -tmp.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8") -tmp.replace(out_path) -PY - -echo "bctrl-fentry-fret-observation-report=${REPORT}" -echo "bctrl-fentry-fret-observation-revision-manifest=${REVISION_MANIFEST}" -exit "${run_status}" diff --git a/tools/chisel/run_chisel_bctrl_template_accepted_sidecar_handoff_probe.sh b/tools/chisel/run_chisel_bctrl_template_accepted_sidecar_handoff_probe.sh deleted file mode 100755 index f22b82ca..00000000 --- a/tools/chisel/run_chisel_bctrl_template_accepted_sidecar_handoff_probe.sh +++ /dev/null @@ -1,324 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r965-johnson-sidecar-handoff" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-1}" -EXPECT_CURRENT_RED="${EXPECT_CURRENT_RED:-0}" -SELF_TEST=0 - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - --self-test) - SELF_TEST=1 - shift - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -PROBE_SOURCE="${ROOT_DIR}/chisel/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala" -PROBE_DIAGNOSTIC_SUFFIX="/src/test/scala/linxcore/bctrl/TemplateAcceptedSidecarHandoffProbe.scala" -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" -EMIT_LOG="${BUILD_DIR}/emit.log" -TB_LOG="${BUILD_DIR}/tb.log" -TOP_MODULE="TemplateAcceptedSidecarHandoffProbe" -EMIT_MAIN="linxcore.bctrl.EmitTemplateAcceptedSidecarHandoffProbe" -TESTBENCH="${ROOT_DIR}/tools/chisel/bctrl_template_accepted_sidecar_handoff_probe_tb.cpp" - -cleanup() { - rm -rf -- "${BUILD_DIR}" -} -trap cleanup EXIT - -declare -a CACHED_STACK_LINES=( - $'[error] \tat sbt.util.CachedCompileFailure.toException(CachedCompileFailure.scala:23)' - $'[error] \tat sbt.util.ActionCache$.cache(ActionCache.scala:181)' - $'[error] \tat sbt.Defaults$.$init$$$anonfun$1(Defaults.scala:2310)' - $'[error] \tat scala.Function1.$anonfun$compose$1(Function1.scala:79)' - $'[error] \tat scala.Function1.$anonfun$compose$1(Function1.scala:79)' - $'[error] \tat sbt.std.Transform$$anon$3.work(Transform.scala:79)' - $'[error] \tat sbt.std.Transform$$anon$3.work(Transform.scala:79)' - $'[error] \tat sbt.Execute.submit$$anonfun$1$$anonfun$1(Execute.scala:283)' - $'[error] \tat sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:24)' - $'[error] \tat sbt.Execute.work(Execute.scala:294)' - $'[error] \tat sbt.Execute.submit$$anonfun$1(Execute.scala:283)' - $'[error] \tat sbt.ConcurrentRestrictions$$anon$4.$anonfun$2(ConcurrentRestrictions.scala:269)' - $'[error] \tat sbt.CompletionService$$anon$2.call(CompletionService.scala:75)' - $'[error] \tat sbt.CompletionService$$anon$2.call(CompletionService.scala:73)' - $'[error] \tat java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)' - $'[error] \tat java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:539)' - $'[error] \tat java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)' - $'[error] \tat java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1136)' - $'[error] \tat java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:635)' - $'[error] \tat java.base/java.lang.Thread.run(Thread.java:840)' -) - -classify_exact_missing_interface() { - local log="$1" - local emit_rc="$2" - local record state mode field_index triplet_phase expected_source primary_prefix primary_suffix location stack_index - local -a fields=( - "templateSidecar:linxcore.rename.ScalarDecodeRenameBridgeIO" - "templateGenerationValid:linxcore.common.RenamedUop" - "templateGeneration:linxcore.common.RenamedUop" - ) - local -a echoes=( - "[error] val acceptedTemplateSidecar = bridge.io.templateSidecar" - "[error] val issueTemplateGenerationValid = issued.templateGenerationValid" - "[error] val issueTemplateGeneration = issued.templateGeneration" - ) - local -a carets=( - "[error] ^" - "[error] ^" - "[error] ^" - ) - - [[ "${emit_rc}" -eq 1 ]] || return 1 - state=0 - mode="" - - while IFS= read -r record; do - if [[ "${state}" -lt 9 ]]; then - field_index=$((state / 3)) - triplet_phase=$((state % 3)) - case "${triplet_phase}" in - 0) - if [[ "${state}" -eq 0 ]]; then - if [[ "${record}" == "[error] ${PROBE_SOURCE}:"* ]]; then - mode="cold" - elif [[ "${record}" == "[error] \${BASE}${PROBE_DIAGNOSTIC_SUFFIX}:"* ]]; then - mode="cached" - else - return 1 - fi - fi - if [[ "${mode}" == "cold" ]]; then - expected_source="${PROBE_SOURCE}" - else - expected_source="\${BASE}${PROBE_DIAGNOSTIC_SUFFIX}" - fi - local member="${fields[${field_index}]%%:*}" - local owner="${fields[${field_index}]#*:}" - primary_prefix="[error] ${expected_source}:" - primary_suffix=": value ${member} is not a member of ${owner}" - [[ "${record}" == "${primary_prefix}"*"${primary_suffix}" ]] || return 1 - location="${record#"${primary_prefix}"}" - location="${location%"${primary_suffix}"}" - [[ "${location}" =~ ^[0-9]+:[0-9]+$ ]] || return 1 - ;; - 1) - [[ "${record}" == "${echoes[${field_index}]}" ]] || return 1 - ;; - 2) - [[ "${record}" == "${carets[${field_index}]}" ]] || return 1 - ;; - esac - state=$((state + 1)) - elif [[ "${mode}" == "cold" ]]; then - case "${state}" in - 9) [[ "${record}" == "[error] three errors found" ]] || return 1 ;; - 10) [[ "${record}" == "[error] (Test / compileIncremental) Compilation failed" ]] || return 1 ;; - 11) [[ "${record}" =~ ^\[error\]\ elapsed\ time:\ [0-9]+\ s,\ cache\ [0-9]+%,\ [0-9]+\ disk\ cache\ hits,\ [0-9]+\ onsite\ tasks?$ ]] || return 1 ;; - *) return 1 ;; - esac - state=$((state + 1)) - else - case "${state}" in - 9) [[ "${record}" == '[error] sbt.util.CachedCompileFailure$$anon$1: Compilation failed' ]] || return 1 ;; - 10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29) - stack_index=$((state - 10)) - [[ "${record}" == "${CACHED_STACK_LINES[${stack_index}]}" ]] || return 1 - ;; - 30) [[ "${record}" == '[error] (Test / compileIncremental) sbt.util.CachedCompileFailure$$anon$1: Compilation failed' ]] || return 1 ;; - 31) [[ "${record}" =~ ^\[error\]\ elapsed\ time:\ [0-9]+\ s,\ cache\ 100%,\ [0-9]+\ cached-failure\ cache\ hits?,\ [0-9]+\ disk\ cache\ hits$ ]] || return 1 ;; - *) return 1 ;; - esac - state=$((state + 1)) - fi - done < <(grep -E '^\[error\]' "${log}" || true) - - [[ "${mode}" == "cold" && "${state}" -eq 12 ]] || - [[ "${mode}" == "cached" && "${state}" -eq 32 ]] -} - -run_self_test() { - local dir exact cached subset superset wrong foreign same_file unlocated timeout setup duplicate reordered zero_rc - dir="$(mktemp -d)" - exact="${dir}/exact.log" - cached="${dir}/cached.log" - subset="${dir}/subset.log" - superset="${dir}/superset.log" - wrong="${dir}/wrong.log" - foreign="${dir}/foreign.log" - same_file="${dir}/same-file.log" - unlocated="${dir}/unlocated.log" - timeout="${dir}/timeout.log" - setup="${dir}/setup.log" - duplicate="${dir}/duplicate.log" - reordered="${dir}/reordered.log" - zero_rc="${dir}/zero-rc.log" - - emit_primary_records() { - local source_path="$1" - echo "[error] ${source_path}:198:43: value templateSidecar is not a member of linxcore.rename.ScalarDecodeRenameBridgeIO" - echo "[error] val acceptedTemplateSidecar = bridge.io.templateSidecar" - echo "[error] ^" - echo "[error] ${source_path}:230:45: value templateGenerationValid is not a member of linxcore.common.RenamedUop" - echo "[error] val issueTemplateGenerationValid = issued.templateGenerationValid" - echo "[error] ^" - echo "[error] ${source_path}:231:40: value templateGeneration is not a member of linxcore.common.RenamedUop" - echo "[error] val issueTemplateGeneration = issued.templateGeneration" - echo "[error] ^" - } - - { - emit_primary_records "${PROBE_SOURCE}" - echo "[error] three errors found" - echo "[error] (Test / compileIncremental) Compilation failed" - echo "[error] elapsed time: 3 s, cache 95%, 22 disk cache hits, 1 onsite task" - } >"${exact}" - { - emit_primary_records "\${BASE}${PROBE_DIAGNOSTIC_SUFFIX}" - echo '[error] sbt.util.CachedCompileFailure$$anon$1: Compilation failed' - printf '%s\n' "${CACHED_STACK_LINES[@]}" - echo '[error] (Test / compileIncremental) sbt.util.CachedCompileFailure$$anon$1: Compilation failed' - echo "[error] elapsed time: 1 s, cache 100%, 1 cached-failure cache hit, 22 disk cache hits" - } >"${cached}" - head -n 3 "${exact}" >"${subset}" - { cat "${exact}"; echo "[error] ${PROBE_SOURCE}:1:1: value extra is not a member of linxcore.rename.ScalarDecodeRenameBridgeIO"; } >"${superset}" - sed 's/templateGenerationValid/templateGenerationReady/' "${exact}" >"${wrong}" - { cat "${exact}"; echo "[error] /tmp/Other.scala:1:1: value boom is not a member of Other"; } >"${foreign}" - { cat "${exact}"; echo "[error] ${PROBE_SOURCE}:99:1: type mismatch"; } >"${same_file}" - { cat "${exact}"; echo "[error] value boom is not a member of Other"; } >"${unlocated}" - { cat "${exact}"; echo "[error] timed out waiting for sbt server"; } >"${timeout}" - { cat "${exact}"; echo "[error] Connection refused while initializing compiler bridge"; } >"${setup}" - { cat "${exact}"; sed -n '1p' "${exact}"; } >"${duplicate}" - { sed -n '4,6p' "${exact}"; sed -n '1,3p' "${exact}"; sed -n '7,$p' "${exact}"; } >"${reordered}" - cp "${exact}" "${zero_rc}" - - classify_exact_missing_interface "${exact}" 1 || - { rm -rf -- "${dir}"; echo "error: exact current-red classifier rejected its positive case" >&2; return 1; } - classify_exact_missing_interface "${cached}" 1 || - { rm -rf -- "${dir}"; echo "error: cached current-red classifier rejected its positive case" >&2; return 1; } - ! classify_exact_missing_interface "${subset}" 1 || - { rm -rf -- "${dir}"; echo "error: subset passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${superset}" 1 || - { rm -rf -- "${dir}"; echo "error: superset passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${wrong}" 1 || - { rm -rf -- "${dir}"; echo "error: wrong member passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${foreign}" 1 || - { rm -rf -- "${dir}"; echo "error: foreign failure passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${same_file}" 1 || - { rm -rf -- "${dir}"; echo "error: same-file extra failure passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${unlocated}" 1 || - { rm -rf -- "${dir}"; echo "error: unlocated failure passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${timeout}" 1 || - { rm -rf -- "${dir}"; echo "error: timeout contamination passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${setup}" 1 || - { rm -rf -- "${dir}"; echo "error: setup contamination passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${duplicate}" 1 || - { rm -rf -- "${dir}"; echo "error: duplicate record passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${reordered}" 1 || - { rm -rf -- "${dir}"; echo "error: reordered records passed current-red classifier" >&2; return 1; } - ! classify_exact_missing_interface "${zero_rc}" 0 || - { rm -rf -- "${dir}"; echo "error: zero return code passed current-red classifier" >&2; return 1; } - - rm -rf -- "${dir}" - echo "bctrl-template-accepted-sidecar-handoff-runner-self-test: PASS" -} - -if [[ "${SELF_TEST}" -eq 1 ]]; then - run_self_test - exit 0 -fi - -if [[ "${EXPECT_CURRENT_RED}" != 0 && "${EXPECT_CURRENT_RED}" != 1 ]]; then - echo "error: EXPECT_CURRENT_RED must be 0 or 1" >&2 - exit 2 -fi -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the accepted sidecar handoff probe" >&2 - exit 2 -fi - -mkdir -p "${SV_DIR}" "${OBJ_DIR}" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -set +e -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain ${EMIT_MAIN} --target-dir ${SV_DIR}" -) >"${EMIT_LOG}" 2>&1 -emit_rc=$? -set -e - -if [[ "${emit_rc}" -ne 0 ]]; then - if classify_exact_missing_interface "${EMIT_LOG}" "${emit_rc}"; then - if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - echo "bctrl-template-accepted-sidecar-handoff-current-red: PASS (exact missing bridge sidecar and issue generation interface)" - exit 0 - fi - echo "bctrl-template-accepted-sidecar-handoff: RED (exact missing bridge sidecar and issue generation interface)" >&2 - exit 1 - fi - echo "error: emit failed for a reason outside the exact R965 missing interface" >&2 - cat "${EMIT_LOG}" >&2 - exit 2 -fi - -if [[ "${EXPECT_CURRENT_RED}" -eq 1 ]]; then - echo "error: current-red mode requested, but the real DUT exposes the accepted sidecar handoff interface" >&2 - exit 1 -fi - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' -print | sort) -if [[ "${#sv_sources[@]}" -eq 0 ]]; then - echo "error: no emitted SystemVerilog under ${SV_DIR}" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module ScalarDecodeRenameBridge' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real ScalarDecodeRenameBridge" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module TemplateRenameSidecarTable' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real TemplateRenameSidecarTable" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module ScalarIssueFabric' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real ScalarIssueFabric" >&2 - exit 2 -fi -if ! grep -R -q --include='*.sv' 'module BlockControlTemplateSequencer' "${SV_DIR}"; then - echo "error: emitted probe does not bind the real BlockControlTemplateSequencer" >&2 - exit 2 -fi - -verilator \ - --cc "${sv_sources[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${TESTBENCH}" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o bctrl_template_accepted_sidecar_handoff_probe_tb \ - -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/bctrl_template_accepted_sidecar_handoff_probe_tb" >"${TB_LOG}" 2>&1 -cat "${TB_LOG}" diff --git a/tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh b/tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh deleted file mode 100755 index 06f8f34f..00000000 --- a/tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh +++ /dev/null @@ -1,202 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${CHISEL_DIR}/generated/chisel" -TOP_MODULE="LinxCoreBenchmarkAutonomousTop" -TOP_SV="${SV_DIR}/${TOP_MODULE}.sv" -EMIT_MAIN="linxcore.top.EmitLinxCoreBenchmarkAutonomousTop" -BUILD_DIR="${ROOT_DIR}/generated/chisel-benchmark-autonomous-top-natural" -ELF="" -MAX_CYCLES="1000000" -RESET_PC="" -RESET_SP="" -DIRECT_BOOT_SP="0x0000000007fefff0" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-0}" -SBT_JVM_HEAP_MB="${SBT_JVM_HEAP_MB:-8192}" -EVENT_SAMPLE_PERIOD="1" -COMMIT_SAMPLE_PERIOD="1" - -while [[ $# -gt 0 ]]; do - case "$1" in - --elf) - ELF="${2:-}" - shift 2 - ;; - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - --max-cycles) - MAX_CYCLES="${2:-}" - shift 2 - ;; - --reset-pc) - RESET_PC="${2:-}" - shift 2 - ;; - --reset-sp) - RESET_SP="${2:-}" - shift 2 - ;; - --event-sample-period) - EVENT_SAMPLE_PERIOD="${2:-}" - shift 2 - ;; - --commit-sample-period) - COMMIT_SAMPLE_PERIOD="${2:-}" - shift 2 - ;; - --qemu|--qemu-trace|--expected-rows|--replay-rows|--result-hint) - echo "error: oracle/replay option is forbidden in natural mode: $1" >&2 - exit 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ -z "${ELF}" ]]; then - echo "error: --elf is required" >&2 - exit 2 -fi -if [[ "${ELF}" != /* ]]; then - ELF="${ROOT_DIR}/${ELF}" -fi -if [[ ! -f "${ELF}" ]]; then - echo "error: ELF does not exist: ${ELF}" >&2 - exit 2 -fi -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for benchmark autonomous natural run" >&2 - exit 2 -fi - -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -MEMORY_HEX="${BUILD_DIR}/elf.load.mem" -COMMIT_TRACE="${TRACE_DIR}/dut.commit.jsonl" -EVENT_TRACE="${TRACE_DIR}/dut.events.jsonl" -UART_OUTPUT="${TRACE_DIR}/uart.txt" -MANIFEST="${REPORT_DIR}/natural_manifest.json" -REVISION_MANIFEST="${REPORT_DIR}/revision_manifest.json" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_elf_memory.py" \ - --elf "${ELF}" \ - --output "${MEMORY_HEX}" - -ELF_ENTRY="$(python3 - "${ELF}" <<'PY' -import struct -import sys -from pathlib import Path - -data = Path(sys.argv[1]).read_bytes() -hdr = struct.unpack_from("<16sHHIQQQIHHHHHH", data, 0) -entry = hdr[4] -print(hex(entry)) -PY -)" - -RESET_PC="${RESET_PC:-${ELF_ENTRY}}" -RESET_SP="${RESET_SP:-${DIRECT_BOOT_SP}}" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors -J-Xmx"${SBT_JVM_HEAP_MB}"M -J-Xss8M "runMain ${EMIT_MAIN}" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no benchmark autonomous SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${ROOT_DIR}/tools/chisel/benchmark_autonomous_top_natural_tb.cpp" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_benchmark_autonomous_top_natural_tb \ - -CFLAGS "-std=c++17 -O2 -I${ROOT_DIR}/tools/chisel" - -set +e -"${OBJ_DIR}/linxcore_benchmark_autonomous_top_natural_tb" \ - --memory-hex "${MEMORY_HEX}" \ - --reset-pc "${RESET_PC}" \ - --reset-sp "${RESET_SP}" \ - --max-cycles "${MAX_CYCLES}" \ - --event-sample-period "${EVENT_SAMPLE_PERIOD}" \ - --commit-sample-period "${COMMIT_SAMPLE_PERIOD}" \ - --commit-trace "${COMMIT_TRACE}" \ - --event-trace "${EVENT_TRACE}" \ - --uart-output "${UART_OUTPUT}" \ - --manifest "${MANIFEST}" -run_status=$? -set -e - -python3 - "${ROOT_DIR}" "${ELF}" "${MEMORY_HEX}" "${COMMIT_TRACE}" "${EVENT_TRACE}" "${UART_OUTPUT}" "${MANIFEST}" "${REVISION_MANIFEST}" <<'PY' -import hashlib -import json -import subprocess -import sys -from pathlib import Path - -root, elf, memory, commit, event, uart, manifest, out_path = map(Path, sys.argv[1:]) - -def sha256(path): - h = hashlib.sha256() - with path.open("rb") as f: - for chunk in iter(lambda: f.read(1024 * 1024), b""): - h.update(chunk) - return h.hexdigest() - -def git_info(path): - rev = subprocess.check_output(["git", "-C", str(path), "rev-parse", "HEAD"], text=True).strip() - dirty = subprocess.run(["git", "-C", str(path), "diff", "--quiet"]).returncode != 0 - untracked = subprocess.check_output(["git", "-C", str(path), "ls-files", "--others", "--exclude-standard"], text=True).splitlines() - return {"revision": rev, "dirty": bool(dirty or untracked)} - -payload = { - "schema": "linxcore.benchmark_autonomous_natural.revision_manifest.v1", - "git": { - "superproject": git_info(root.parent.parent), - "linxcore": git_info(root), - }, - "artifacts": { - "elf": {"path": str(elf), "sha256": sha256(elf)}, - "memory_hex": {"path": str(memory), "sha256": sha256(memory)}, - "commit_trace": {"path": str(commit), "sha256": sha256(commit)}, - "event_trace": {"path": str(event), "sha256": sha256(event)}, - "uart_output": {"path": str(uart), "sha256": sha256(uart)}, - "natural_manifest": {"path": str(manifest), "sha256": sha256(manifest)}, - }, -} -tmp = out_path.with_suffix(out_path.suffix + ".tmp") -tmp.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8") -tmp.replace(out_path) -PY - -echo "benchmark-autonomous-natural-manifest=${MANIFEST}" -echo "benchmark-autonomous-natural-revision-manifest=${REVISION_MANIFEST}" -exit "${run_status}" diff --git a/tools/chisel/run_chisel_dual_benchmark_ipc_gate.sh b/tools/chisel/run_chisel_dual_benchmark_ipc_gate.sh deleted file mode 100755 index d5d07e75..00000000 --- a/tools/chisel/run_chisel_dual_benchmark_ipc_gate.sh +++ /dev/null @@ -1,114 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -SUPERPROJECT_DIR="$(cd -- "${ROOT_DIR}/../.." && pwd)" -NATURAL_RUNNER="${LINXCORE_NATURAL_RUNNER:-${ROOT_DIR}/tools/chisel/run_chisel_benchmark_autonomous_top_natural.sh}" -EVALUATOR="${LINXCORE_IPC_EVALUATOR:-${ROOT_DIR}/tools/chisel/evaluate_natural_benchmark_ipc.py}" -COREMARK_ELF="${SUPERPROJECT_DIR}/workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/coremark/coremark.elf" -DHRYSTONE_ELF="${SUPERPROJECT_DIR}/workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/dhrystone/dhrystone.elf" -EXPECTED_COREMARK_SHA256="${LINXCORE_EXPECTED_COREMARK_SHA256:-9c734694793da5d3b3765bc45c7acff787a3ca1854ad1780897e1d5b8deb3cff}" -EXPECTED_DHRYSTONE_SHA256="${LINXCORE_EXPECTED_DHRYSTONE_SHA256:-617bd0985595ccf208dd2130809c1befc1605de1ee9188dbf3cfaf46fd9e9911}" -EXPECTED_NATURAL_RUNNER_SHA256="${LINXCORE_EXPECTED_NATURAL_RUNNER_SHA256:-91d84b3b300209bf5f384f185eb1ace4b5bfb81b3a8107fc8a6678e3a86bc1e3}" -BUILD_ROOT="${ROOT_DIR}/generated/perf-ipc2-evaluator" -MAX_CYCLES="3000000" -TARGET_IPC="1.90" -RESET_SP="0x0000000007fefff0" -EVENT_SAMPLE_PERIOD="1000" -COMMIT_SAMPLE_PERIOD="1000" - -while [[ $# -gt 0 ]]; do - case "$1" in - --coremark-elf) - COREMARK_ELF="${2:-}" - shift 2 - ;; - --dhrystone-elf) - DHRYSTONE_ELF="${2:-}" - shift 2 - ;; - --build-root) - BUILD_ROOT="${2:-}" - shift 2 - ;; - --max-cycles) - MAX_CYCLES="${2:-}" - shift 2 - ;; - --target-ipc) - TARGET_IPC="${2:-}" - shift 2 - ;; - --event-sample-period) - EVENT_SAMPLE_PERIOD="${2:-}" - shift 2 - ;; - --commit-sample-period) - COMMIT_SAMPLE_PERIOD="${2:-}" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_ROOT}" != /* ]]; then - BUILD_ROOT="${ROOT_DIR}/${BUILD_ROOT}" -fi -COREMARK_BUILD_DIR="${BUILD_ROOT}/coremark" -DHRYSTONE_BUILD_DIR="${BUILD_ROOT}/dhrystone" -COREMARK_MANIFEST="${COREMARK_BUILD_DIR}/report/natural_manifest.json" -DHRYSTONE_MANIFEST="${DHRYSTONE_BUILD_DIR}/report/natural_manifest.json" -SUMMARY="${BUILD_ROOT}/report/dual_benchmark_ipc.json" - -mkdir -p "${COREMARK_BUILD_DIR}/report" "${DHRYSTONE_BUILD_DIR}/report" -rm -f "${COREMARK_MANIFEST}" "${DHRYSTONE_MANIFEST}" - -set +e -bash "${NATURAL_RUNNER}" \ - --elf "${COREMARK_ELF}" \ - --build-dir "${COREMARK_BUILD_DIR}" \ - --max-cycles "${MAX_CYCLES}" \ - --reset-sp "${RESET_SP}" \ - --event-sample-period "${EVENT_SAMPLE_PERIOD}" \ - --commit-sample-period "${COMMIT_SAMPLE_PERIOD}" -coremark_status=$? - -bash "${NATURAL_RUNNER}" \ - --elf "${DHRYSTONE_ELF}" \ - --build-dir "${DHRYSTONE_BUILD_DIR}" \ - --max-cycles "${MAX_CYCLES}" \ - --reset-sp "${RESET_SP}" \ - --event-sample-period "${EVENT_SAMPLE_PERIOD}" \ - --commit-sample-period "${COMMIT_SAMPLE_PERIOD}" -dhrystone_status=$? -set -e - -set +e -python3 "${EVALUATOR}" \ - --coremark-manifest "${COREMARK_MANIFEST}" \ - --dhrystone-manifest "${DHRYSTONE_MANIFEST}" \ - --coremark-elf "${COREMARK_ELF}" \ - --dhrystone-elf "${DHRYSTONE_ELF}" \ - --expected-coremark-sha256 "${EXPECTED_COREMARK_SHA256}" \ - --expected-dhrystone-sha256 "${EXPECTED_DHRYSTONE_SHA256}" \ - --runner "${NATURAL_RUNNER}" \ - --expected-runner-sha256 "${EXPECTED_NATURAL_RUNNER_SHA256}" \ - --target-ipc "${TARGET_IPC}" \ - --expected-reset-sp "${RESET_SP}" \ - --output "${SUMMARY}" -evaluator_status=$? -set -e - -echo "coremark-run-status=${coremark_status}" -echo "dhrystone-run-status=${dhrystone_status}" -echo "dual-benchmark-ipc-summary=${SUMMARY}" -if [[ "${evaluator_status}" -ne 0 ]]; then - exit "${evaluator_status}" -fi -if [[ "${coremark_status}" -ne 0 || "${dhrystone_status}" -ne 0 ]]; then - exit 1 -fi -exit 0 diff --git a/tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh b/tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh deleted file mode 100755 index 3801dac1..00000000 --- a/tools/chisel/run_chisel_frontend_alu_trace_top_xcheck.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-alu-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendAluTraceTop.sv" -BUILD_DIR="${ROOT_DIR}/generated/chisel-frontend-alu-trace-top-xcheck" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend ALU trace top xcheck" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendAluTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend ALU trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendAluTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/frontend_alu_trace_top_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_alu_trace_top_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/linxcore_frontend_alu_trace_top_tb" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits 3 \ - --mode failfast - -echo "frontend-alu-trace-top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_frontend_fetch_rf_alu_marker_rows_smoke.sh b/tools/chisel/run_chisel_frontend_fetch_rf_alu_marker_rows_smoke.sh deleted file mode 100755 index b6da2f79..00000000 --- a/tools/chisel/run_chisel_frontend_fetch_rf_alu_marker_rows_smoke.sh +++ /dev/null @@ -1,51 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-marker-rows-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendFetchRfAluMarkerRowsTraceTop.sv" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-frontend-fetch-rf-alu-marker-rows-smoke}" -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -OBJ_DIR="${BUILD_DIR}/obj_dir" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel marker-row smoke" >&2 - exit 2 -fi - -mkdir -p "${BUILD_DIR}" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendFetchRfAluMarkerRowsTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted marker-row top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no marker-row top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendFetchRfAluMarkerRowsTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_marker_rows_trace_top_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_fetch_rf_alu_marker_rows_trace_top_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/linxcore_frontend_fetch_rf_alu_marker_rows_trace_top_tb" diff --git a/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh b/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh deleted file mode 100755 index 79356a4f..00000000 --- a/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh +++ /dev/null @@ -1,1105 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-frontend-fetch-rf-alu-qemu-elf-xcheck}" -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -ELF="" -FIXTURE="" -QEMU_BIN="" -EXPECTED_ROWS="${EXPECTED_ROWS:-3}" -CAPTURE_ROWS="${CAPTURE_ROWS:-}" -QEMU_SKIP_ROWS="${QEMU_SKIP_ROWS:-0}" -MAX_SECONDS="${MAX_SECONDS:-30}" -PC_LO="" -PC_HI="" -ALLOW_BLOCK_MARKERS=0 -ALLOW_BLOCK_LOOP_REENTRY=0 -MARKER_ROWS=0 -REDUCED_STORE_DISPATCH_STQ=0 -REDUCED_STORE_REPLAY_LIQ=0 -REDUCED_STORE_LIVE_LOAD_LIQ=0 -DISABLE_STORE_MEMORY_MUTATION=0 -ALLOW_RESIDUAL_REPLAY_LIQ_WAIT=0 -QEMU_ONLY=0 -QEMU_RAW_ONLY=0 -EXPECT_LOAD_PCS="" -EXPECT_STORE_PCS="" -RF_SEED="" -FETCH_REPLAY_LIQ_REQUIRE_PRESET="${FETCH_REPLAY_LIQ_REQUIRE_PRESET:-}" -FETCH_REPLAY_LIQ_REQUIRE_NONZERO="${FETCH_REPLAY_LIQ_REQUIRE_NONZERO:-}" -FETCH_REPLAY_LIQ_REQUIRE_ZERO="${FETCH_REPLAY_LIQ_REQUIRE_ZERO:-}" -FETCH_ELF_LOAD_BIAS="${FETCH_ELF_LOAD_BIAS:-}" -FINALIZE_ONLY=0 -FINALIZE_PHASE="generated-rtl" -FINALIZE_STATUS="pass" -FINALIZE_EXIT_STATUS=0 -ORIGINAL_ARGV_JSON="$(python3 - "$@" <<'PY' -import json -import sys - -print(json.dumps(sys.argv[1:])) -PY -)" -QEMU_ARGS_JSON="[]" - -usage() { - cat < [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi-loop [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi-ldi-loop [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi-sdi-ldi-loop [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi-sdi-ldi-ldi-loop [options] -- [qemu args] - $(basename "$0") --fixture replay-ldi-sdi-ldi-ldi-ldi-ldi-loop [options] -- [qemu args] - -Options: - --build-dir Output root (default: ${BUILD_DIR}) - --fixture Build a named fixture ELF before capture. - Supported: replay-ldi-sdi-ldi, - replay-ldi-sdi-ldi-loop, - replay-ldi-sdi-ldi-ldi-loop, - replay-ldi-sdi-ldi-sdi-ldi-loop, - replay-ldi-sdi-ldi-sdi-ldi-ldi-loop, - replay-ldi-sdi-ldi-ldi-ldi-ldi-loop - --qemu-bin QEMU binary. Defaults to the Chisel cross-check QEMU. - --expected-rows Reduced scalar rows to extract/compare (default: ${EXPECTED_ROWS}; 0 means all) - --capture-rows Filtered QEMU rows to capture before stopping QEMU - --qemu-skip-rows QEMU-only: discard this many filtered rows before - writing the bounded capture - --max-seconds Watchdog timeout for QEMU capture (default: ${MAX_SECONDS}) - --pc-lo Optional QEMU commit-trace PC filter low bound - --pc-hi Optional QEMU commit-trace PC filter high bound - --allow-block-markers Preserve legal BSTART/BSTOP rows as DUT-only skip rows - --allow-block-loop-reentry - Allow dynamic FALL-block re-entry rows in the QEMU reducer - --marker-rows Build the non-default marker-row top and admit legal - marker rows into ROB, then filter validated marker - commits from the scalar comparator stream - --reduced-store-dispatch-stq - Build the opt-in reduced-store top with store - dispatch routed through the reduced STQ/SCB path - --reduced-store-replay-liq - Build the opt-in reduced-store replay-LIQ top where - replay queue heads allocate into diagnostic LIQ state - --reduced-store-live-load-liq - Build the opt-in reduced-store top where every - ordinary scalar E1 load allocates into LIQ before - LRET/W1/W2 completion - --disable-store-memory-mutation - Do not mutate the harness sparse memory image after - matched store commits; reduced-store mode must supply - store-visible load data from RTL overlay state - --allow-residual-replay-liq-wait - Allow a residual replay-LIQ wait row after the - compared rows and emit sideband evidence instead of - requiring the final idle-drain check - --qemu-only Stop after QEMU capture and reduced-row preview; this - validates fixture/reducer shape only and does not - build or run generated RTL - --qemu-raw-only QEMU-only: stop after raw QEMU capture and do not run - the reduced-row extractor - --expect-load-pcs Require the reduced preview's load PC sequence to - equal a comma-separated hex/decimal list - --expect-store-pcs - Require the reduced preview's store PC sequence to - equal a comma-separated hex/decimal list - --rf-seed Explicit reduced scalar RF seed rows to pass to the - generated-RTL harness before source-derived preloads - -Environment: - FETCH_ELF_LOAD_BIAS= - Explicit PT_LOAD address bias for generated-RTL sparse - memory. Defaults to QEMU direct-loader policy: - 0x10000 for ET_DYN and zero for ET_EXEC. - FETCH_REPLAY_LIQ_REQUIRE_PRESET= - Pass named sideband validator presets through to the - generated-RTL runner. Supported presets are owned by - validate_frontend_fetch_rf_alu_sideband_stats.py. - -This wrapper captures a bounded QEMU commit JSONL prefix from a direct-boot ELF, -validates that the selected rows are inside the current reduced scalar -ADD/ADDI/ADDTPC/C.MOVI/C.MOVR envelope, extracts the same ELF into sparse fetch -memory, and then runs LinxCoreFrontendFetchRfAluTraceTop through the neutral comparator. -With --allow-block-markers, legal BSTART/BSTOP rows are consumed by the reduced -frontend/ROB path as skip rows and are not written to the comparator trace. -With --marker-rows, the same reduced expected stream still marks legal markers -as skip rows for comparator filtering, but the marker-row top must admit and -retire those rows before the following scalar rows compare. -With --reduced-store-dispatch-stq, the harness uses the same comparator stream -but emits the reduced-store top so store rows exercise the opt-in STQ lifecycle. -With --reduced-store-replay-liq, the harness emits the reduced-store replay-LIQ -top so queued replay candidates are consumed only by LIQ allocation acceptance. -With --reduced-store-live-load-liq, the harness emits the live-load LIQ top so -ordinary scalar E1 loads enter LIQ before their LRET/W1/W2 completion path. -With --disable-store-memory-mutation, later loads can observe committed stores -only through the reduced-store RTL memory overlay. -With --fixture replay-ldi-sdi-ldi, the wrapper builds the memory-order probe -inside the build directory and defaults to the bounded prefix -C.BSTART.STD/LDI/SDI/LDI. The C.BSTOP tail is excluded by default because the -current dense fetch checker cannot consume that trailing two-byte stop marker -as part of the same fixture window. -With --fixture replay-ldi-sdi-ldi-loop, the wrapper captures the first memory -probe, the direct loop boundary, and the second dynamic memory probe so MDB -lookup evidence can be collected after the first pass records the dependency. -With --fixture replay-ldi-sdi-ldi-ldi-loop, the loop probe includes one -additional younger load before the direct loop boundary, increasing replay -return density for W1/W2 same-cycle replacement evidence. -With --fixture replay-ldi-sdi-ldi-sdi-ldi-loop, the loop probe repeats the -same-address store/load dependency chain before the direct loop boundary, -targeting denser MDB/LIQ returned-load overlap for W1/W2 replacement evidence. -With --fixture replay-ldi-sdi-ldi-sdi-ldi-ldi-loop, the loop probe repeats the -same-address store/load dependency chain and adds a second younger load after -the second store dependency to test clustered returned-load phasing. -With --fixture replay-ldi-sdi-ldi-ldi-ldi-ldi-loop, the loop probe keeps one -store dependency and then emits a burst of consecutive younger loads before the -direct loop boundary to test returned-load W1/W2 phasing. -With --qemu-only, the wrapper still builds any requested fixture, captures the -bounded QEMU prefix, and runs the reduced-row extractor, then exits before the -Verilator harness. Do not use that mode as QEMU/DUT equivalence evidence. -With --qemu-skip-rows, the wrapper discards filtered QEMU rows before writing -the bounded capture. This is allowed only with --qemu-only because the reduced -Verilator top cannot reconstruct skipped architectural state. -With --qemu-raw-only, the wrapper exits after raw QEMU capture. Use it for -arbitrary skipped intervals that may not form a strict reduced-row prefix. -With --expect-load-pcs or --expect-store-pcs, the wrapper asserts the exact -memory PC sequence in the reduced preview before any optional RTL run. -USAGE -} - -QEMU_ARGS=() -EXPECTED_ROWS_SET=0 -CAPTURE_ROWS_SET=0 -while [[ $# -gt 0 ]]; do - case "$1" in - --elf) ELF="$2"; shift 2 ;; - --fixture) FIXTURE="$2"; shift 2 ;; - --build-dir) BUILD_DIR="$2"; shift 2 ;; - --qemu-bin) QEMU_BIN="$2"; shift 2 ;; - --expected-rows) EXPECTED_ROWS="$2"; EXPECTED_ROWS_SET=1; shift 2 ;; - --capture-rows) CAPTURE_ROWS="$2"; CAPTURE_ROWS_SET=1; shift 2 ;; - --qemu-skip-rows) QEMU_SKIP_ROWS="$2"; shift 2 ;; - --max-seconds) MAX_SECONDS="$2"; shift 2 ;; - --pc-lo) PC_LO="$2"; shift 2 ;; - --pc-hi) PC_HI="$2"; shift 2 ;; - --allow-block-markers) ALLOW_BLOCK_MARKERS=1; shift ;; - --allow-block-loop-reentry) ALLOW_BLOCK_LOOP_REENTRY=1; shift ;; - --marker-rows) MARKER_ROWS=1; shift ;; - --reduced-store-dispatch-stq) REDUCED_STORE_DISPATCH_STQ=1; shift ;; - --reduced-store-replay-liq) REDUCED_STORE_REPLAY_LIQ=1; shift ;; - --reduced-store-live-load-liq) REDUCED_STORE_LIVE_LOAD_LIQ=1; shift ;; - --disable-store-memory-mutation) DISABLE_STORE_MEMORY_MUTATION=1; shift ;; - --allow-residual-replay-liq-wait) ALLOW_RESIDUAL_REPLAY_LIQ_WAIT=1; shift ;; - --qemu-only) QEMU_ONLY=1; shift ;; - --qemu-raw-only) QEMU_RAW_ONLY=1; QEMU_ONLY=1; shift ;; - --expect-load-pcs) EXPECT_LOAD_PCS="$2"; shift 2 ;; - --expect-store-pcs) EXPECT_STORE_PCS="$2"; shift 2 ;; - --rf-seed) RF_SEED="$2"; shift 2 ;; - --finalize-only) - FINALIZE_ONLY=1 - FINALIZE_PHASE="$2" - FINALIZE_STATUS="$3" - FINALIZE_EXIT_STATUS="$4" - shift 4 - ;; - --) - shift - QEMU_ARGS=("$@") - break - ;; - -h|--help) usage; exit 0 ;; - *) echo "error: unknown argument: $1" >&2; usage; exit 2 ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -QEMU_TRACE="${TRACE_DIR}/qemu.live.raw.jsonl" -QEMU_FIFO="${TRACE_DIR}/qemu.live.raw.fifo" -EXPECTED_PREVIEW="${TRACE_DIR}/qemu.live.expected.preview.jsonl" -FRONTEND_REPORT="${REPORT_DIR}/frontend_fetch_rf_alu_qemu_elf_report.json" -FRONTEND_MANIFEST="${REPORT_DIR}/frontend_fetch_rf_alu_qemu_elf_manifest.json" -QEMU_TRACE_RUNNER="${ROOT_DIR}/tools/qemu/run_qemu_commit_trace.sh" -FETCH_RUNNER="${ROOT_DIR}/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh" -QEMU_CROSSCHECK_RUNNER="${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" -FIXTURE_BUILDER="${ROOT_DIR}/tools/chisel/build_frontend_fetch_rf_alu_qemu_fixture_elf.sh" -qemu_pid="" -reader_pid="" -watchdog_pid="" -producer_watch_pid="" -raw_rows=0 -if (( ${#QEMU_ARGS[@]} == 0 )); then - QEMU_ARGS_JSON="[]" -else - QEMU_ARGS_JSON="$(python3 - "${QEMU_ARGS[@]}" <<'PY' -import json -import sys - -print(json.dumps(sys.argv[1:])) -PY - )" -fi - -write_frontend_manifest() { - local phase="$1" - local status="$2" - local exit_status="$3" - local common_manifest="${REPORT_DIR}/crosscheck_manifest.json" - python3 - \ - "${FRONTEND_MANIFEST}" \ - "${FRONTEND_REPORT}" \ - "${common_manifest}" \ - "${phase}" \ - "${status}" \ - "${exit_status}" \ - "${ROOT_DIR}" \ - "${ELF}" \ - "${QEMU_BIN}" \ - "${QEMU_TRACE}" \ - "${EXPECTED_PREVIEW}" \ - "${REPORT_DIR}" \ - "${raw_rows}" \ - "${QEMU_SKIP_ROWS}" \ - "${EXPECTED_ROWS}" \ - "${CAPTURE_ROWS}" \ - "${FETCH_ELF_LOAD_BIAS}" \ - "${QEMU_ONLY}" \ - "${QEMU_RAW_ONLY}" \ - "${ORIGINAL_ARGV_JSON}" \ - "${QEMU_ARGS_JSON}" \ - "${PC_LO}" \ - "${PC_HI}" \ - "${ALLOW_BLOCK_MARKERS}" \ - "${ALLOW_BLOCK_LOOP_REENTRY}" \ - "${MARKER_ROWS}" \ - "${REDUCED_STORE_DISPATCH_STQ}" \ - "${REDUCED_STORE_REPLAY_LIQ}" \ - "${REDUCED_STORE_LIVE_LOAD_LIQ}" \ - "${DISABLE_STORE_MEMORY_MUTATION}" \ - "${ALLOW_RESIDUAL_REPLAY_LIQ_WAIT}" \ - "${EXPECT_LOAD_PCS}" \ - "${EXPECT_STORE_PCS}" \ - "${RF_SEED}" <<'PY' -import hashlib -import json -import os -import subprocess -import sys -import tempfile -from datetime import datetime, timezone -from pathlib import Path - -( - manifest_path, - report_path, - common_manifest_path, - phase, - status, - exit_status, - root_dir, - elf, - qemu_bin, - qemu_trace, - expected_preview, - report_dir, - raw_rows, - skipped_rows, - expected_rows, - capture_rows, - fetch_elf_load_bias, - qemu_only, - qemu_raw_only, - original_argv_json, - qemu_args_json, - pc_lo, - pc_hi, - allow_block_markers, - allow_block_loop_reentry, - marker_rows, - reduced_store_dispatch_stq, - reduced_store_replay_liq, - reduced_store_live_load_liq, - disable_store_memory_mutation, - allow_residual_replay_liq_wait, - expect_load_pcs, - expect_store_pcs, - rf_seed, -) = sys.argv[1:] - - -def read_json(path: str, default): - p = Path(path) - if not p.is_file(): - return default - return json.loads(p.read_text(encoding="utf-8")) - - -def count_jsonl(path: str) -> int: - p = Path(path) - if not p.is_file(): - return 0 - count = 0 - with p.open("r", encoding="utf-8", errors="replace") as handle: - for line in handle: - stripped = line.strip() - if stripped and not stripped.startswith("#"): - count += 1 - return count - - -def sha256_file(path: str) -> str: - p = Path(path) - if not p.is_file(): - return "" - digest = hashlib.sha256() - with p.open("rb") as handle: - for chunk in iter(lambda: handle.read(1024 * 1024), b""): - digest.update(chunk) - return digest.hexdigest() - - -def existing(path: str) -> str: - return path if path and Path(path).is_file() else "" - - -def git_rev(path: str) -> str: - try: - return subprocess.check_output( - ["git", "-C", path, "rev-parse", "HEAD"], - text=True, - stderr=subprocess.DEVNULL, - ).strip() - except subprocess.CalledProcessError: - return "" - - -def git_dirty(path: str) -> bool: - try: - out = subprocess.check_output( - ["git", "-C", path, "status", "--short"], - text=True, - stderr=subprocess.DEVNULL, - ) - return bool(out.strip()) - except subprocess.CalledProcessError: - return False - - -def git_context(path: Path) -> dict: - return {"path": str(path), "head": git_rev(str(path)), "dirty": git_dirty(str(path))} - - -def atomic_json(path: str, payload: dict) -> None: - target = Path(path) - target.parent.mkdir(parents=True, exist_ok=True) - fd = -1 - tmp_name = "" - try: - fd, tmp_name = tempfile.mkstemp( - prefix=f".{target.name}.", - suffix=".tmp", - dir=str(target.parent), - text=True, - ) - with os.fdopen(fd, "w", encoding="utf-8") as handle: - fd = -1 - json.dump(payload, handle, indent=2, sort_keys=True) - handle.write("\n") - handle.flush() - os.fsync(handle.fileno()) - os.replace(tmp_name, target) - finally: - if fd != -1: - os.close(fd) - if tmp_name and Path(tmp_name).exists(): - Path(tmp_name).unlink() - - -def artifact(path: str) -> dict | None: - if not path or not Path(path).is_file(): - return None - return { - "path": path, - "sha256": sha256_file(path), - "bytes": Path(path).stat().st_size, - "rows": count_jsonl(path) if path.endswith(".jsonl") else None, - } - - -common_manifest = read_json(common_manifest_path, {}) -common_reports = common_manifest.get("reports", {}) if isinstance(common_manifest, dict) else {} -common_inputs = common_manifest.get("inputs", {}) if isinstance(common_manifest, dict) else {} -common_normalized = common_manifest.get("normalized", {}) if isinstance(common_manifest, dict) else {} -common_report_path = common_reports.get("json") or str(Path(report_dir) / "crosscheck_report.json") -common_report = read_json(common_report_path, {}) -first_mismatch = common_report.get("first_mismatch") -mismatch_count = int(common_report.get("mismatch_count", 0) or 0) -compared_rows = int(common_report.get("compared_rows", 0) or 0) -dut_trace = common_inputs.get("dut_trace", "") -qemu_reference_trace = common_inputs.get("qemu_trace", "") -if not qemu_reference_trace: - qemu_reference_trace = qemu_trace - -artifacts = [] -for candidate in [ - qemu_trace, - expected_preview, - qemu_reference_trace, - dut_trace, - common_normalized.get("qemu_trace", ""), - common_normalized.get("dut_trace", ""), - common_report_path, - common_reports.get("mismatches", ""), - common_reports.get("markdown", ""), - common_manifest_path, -]: - item = artifact(candidate) - if item is not None and item["path"] not in {a["path"] for a in artifacts}: - artifacts.append(item) - -linx_root = Path(root_dir).resolve().parents[1] -counts = { - "qemu_live_raw_rows": count_jsonl(qemu_trace), - "expected_preview_rows": count_jsonl(expected_preview), - "qemu_reference_rows": count_jsonl(qemu_reference_trace), - "dut_captured_rows": count_jsonl(dut_trace), - "qemu_normalized_rows": count_jsonl(common_normalized.get("qemu_trace", "")), - "dut_normalized_rows": count_jsonl(common_normalized.get("dut_trace", "")), - "common_report_qemu_rows": int(common_report.get("qemu_rows", 0) or 0), - "common_report_dut_rows": int(common_report.get("dut_rows", 0) or 0), - "compared_rows": compared_rows, - "mismatch_count": mismatch_count, -} -selected = { - "original_argv": json.loads(original_argv_json), - "qemu_args": json.loads(qemu_args_json), - "elf": elf, - "qemu_bin": qemu_bin, - "expected_rows": int(expected_rows), - "capture_rows": int(capture_rows), - "qemu_skip_rows": int(skipped_rows), - "fetch_elf_load_bias": fetch_elf_load_bias, - "pc_lo": pc_lo, - "pc_hi": pc_hi, - "allow_block_markers": allow_block_markers == "1", - "allow_block_loop_reentry": allow_block_loop_reentry == "1", - "marker_rows": marker_rows == "1", - "reduced_store_dispatch_stq": reduced_store_dispatch_stq == "1", - "reduced_store_replay_liq": reduced_store_replay_liq == "1", - "reduced_store_live_load_liq": reduced_store_live_load_liq == "1", - "disable_store_memory_mutation": disable_store_memory_mutation == "1", - "allow_residual_replay_liq_wait": allow_residual_replay_liq_wait == "1", - "qemu_only": qemu_only == "1", - "qemu_raw_only": qemu_raw_only == "1", - "expect_load_pcs": expect_load_pcs, - "expect_store_pcs": expect_store_pcs, - "rf_seed": rf_seed, -} -report = { - "schema": "linxcore.chisel.frontend_fetch_rf_alu_qemu_elf_report.v2", - "phase": phase, - "status": status, - "exit_status": int(exit_status), - "counts": counts, - "mismatch_count": mismatch_count, - "first_mismatch": first_mismatch, - "selected": selected, - "artifacts": artifacts, - "common_crosscheck_manifest": existing(common_manifest_path), - "proof_boundary": "reduced generated-RTL/QEMU trace comparison only; not natural full-core execution", -} -manifest = { - "schema": "linxcore.chisel.frontend_fetch_rf_alu_qemu_elf_manifest.v2", - "generated_utc": datetime.now(timezone.utc).isoformat().replace("+00:00", "Z"), - "status": status, - "exit_status": int(exit_status), - "phase": phase, - "root_dir": root_dir, - "git": { - "linxcore": git_context(Path(root_dir)), - "linxcore_model": git_context(linx_root / "tools" / "LinxCoreModel"), - "qemu": git_context(linx_root / "emulator" / "qemu"), - "superproject": git_context(linx_root), - }, - "selected": selected, - "inputs": { - "qemu_trace": existing(qemu_trace), - "expected_preview": existing(expected_preview), - "qemu_reference_trace": existing(qemu_reference_trace), - "dut_trace": existing(dut_trace), - }, - "reports": { - "frontend_report": report_path, - "frontend_manifest": manifest_path, - "common_crosscheck_manifest": existing(common_manifest_path), - "common_crosscheck_report": existing(common_report_path), - "common_crosscheck_mismatches": existing(common_reports.get("mismatches", "")), - "common_crosscheck_markdown": existing(common_reports.get("markdown", "")), - }, - "counts": counts, - "mismatch_count": mismatch_count, - "first_mismatch": first_mismatch, - "artifacts": artifacts, - "proof_boundary": report["proof_boundary"], - "report_dir": report_dir, -} -atomic_json(report_path, report) -atomic_json(manifest_path, manifest) -print(f"frontend_manifest_json={manifest_path}") -print(f"frontend_report_json={report_path}") -PY -} - -if [[ "${FINALIZE_ONLY}" == "1" ]]; then - mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - raw_rows="$(awk 'END { print NR + 0 }' "${QEMU_TRACE}" 2>/dev/null || echo 0)" - write_frontend_manifest "${FINALIZE_PHASE}" "${FINALIZE_STATUS}" "${FINALIZE_EXIT_STATUS}" - exit "${FINALIZE_EXIT_STATUS}" -fi - -if [[ -n "${ELF}" && -n "${FIXTURE}" ]]; then - echo "error: --elf and --fixture are mutually exclusive" >&2 - usage - exit 2 -fi -if [[ -n "${FIXTURE}" ]]; then - case "${FIXTURE}" in - replay-ldi-sdi-ldi) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=4 - fi - ALLOW_BLOCK_MARKERS=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x1000b - fi - ;; - replay-ldi-sdi-ldi-loop) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi-loop" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi-loop - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=12 - fi - ALLOW_BLOCK_MARKERS=1 - ALLOW_BLOCK_LOOP_REENTRY=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x10015 - fi - ;; - replay-ldi-sdi-ldi-ldi-loop) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi-ldi-loop" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi-ldi-loop - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=16 - fi - ALLOW_BLOCK_MARKERS=1 - ALLOW_BLOCK_LOOP_REENTRY=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x10019 - fi - ;; - replay-ldi-sdi-ldi-sdi-ldi-loop) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi-sdi-ldi-loop" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi-sdi-ldi-loop - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=18 - fi - ALLOW_BLOCK_MARKERS=1 - ALLOW_BLOCK_LOOP_REENTRY=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x1001d - fi - ;; - replay-ldi-sdi-ldi-sdi-ldi-ldi-loop) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi-sdi-ldi-ldi-loop" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi-sdi-ldi-ldi-loop - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=21 - fi - ALLOW_BLOCK_MARKERS=1 - ALLOW_BLOCK_LOOP_REENTRY=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x10021 - fi - ;; - replay-ldi-sdi-ldi-ldi-ldi-ldi-loop) - FIXTURE_DIR="${BUILD_DIR}/fixture-replay-ldi-sdi-ldi-ldi-ldi-ldi-loop" - bash "${FIXTURE_BUILDER}" \ - --out-dir "${FIXTURE_DIR}" \ - --replay-ldi-sdi-ldi-ldi-ldi-ldi-loop - ELF="${FIXTURE_DIR}/frontend_fetch_rf_alu_qemu_fixture.elf" - if [[ "${EXPECTED_ROWS_SET}" == "0" ]]; then - EXPECTED_ROWS=0 - fi - if [[ "${CAPTURE_ROWS_SET}" == "0" ]]; then - CAPTURE_ROWS=21 - fi - ALLOW_BLOCK_MARKERS=1 - ALLOW_BLOCK_LOOP_REENTRY=1 - if [[ -z "${PC_LO}" ]]; then - PC_LO=0x10000 - fi - if [[ -z "${PC_HI}" ]]; then - PC_HI=0x10021 - fi - ;; - *) - echo "error: unsupported --fixture: ${FIXTURE}" >&2 - usage - exit 2 - ;; - esac -fi -if [[ -z "${ELF}" ]]; then - echo "error: --elf or --fixture is required" >&2 - usage - exit 2 -fi -if [[ "${ELF}" != /* ]]; then - ELF="${ROOT_DIR}/${ELF}" -fi -if [[ ! -f "${ELF}" ]]; then - echo "error: ELF not found: ${ELF}" >&2 - exit 2 -fi -if [[ -z "${FETCH_ELF_LOAD_BIAS}" ]]; then - FETCH_ELF_LOAD_BIAS="$( - python3 - "${ELF}" <<'PY' -import struct -import sys - -with open(sys.argv[1], "rb") as f: - header = f.read(18) -if len(header) != 18 or header[:4] != b"\x7fELF": - raise SystemExit(f"error: not an ELF file: {sys.argv[1]}") -etype = struct.unpack_from("&2 - exit 2 -fi -if [[ ! "${EXPECTED_ROWS}" =~ ^[0-9]+$ ]]; then - echo "error: --expected-rows must be a non-negative integer" >&2 - exit 2 -fi -if [[ ! "${QEMU_SKIP_ROWS}" =~ ^[0-9]+$ ]]; then - echo "error: --qemu-skip-rows must be a non-negative integer" >&2 - exit 2 -fi -if [[ "${QEMU_SKIP_ROWS}" -gt 0 && "${QEMU_ONLY}" != "1" ]]; then - echo "error: --qemu-skip-rows is allowed only with --qemu-only" >&2 - exit 2 -fi -if [[ "${QEMU_RAW_ONLY}" == "1" && ( -n "${EXPECT_LOAD_PCS}" || -n "${EXPECT_STORE_PCS}" ) ]]; then - echo "error: --qemu-raw-only cannot be combined with --expect-load-pcs or --expect-store-pcs" >&2 - exit 2 -fi -if [[ "${MARKER_ROWS}" == "1" && "${ALLOW_BLOCK_MARKERS}" != "1" ]]; then - echo "error: --marker-rows requires --allow-block-markers" >&2 - exit 2 -fi -selected_top_count=0 -for selected_top in "${MARKER_ROWS}" "${REDUCED_STORE_DISPATCH_STQ}" "${REDUCED_STORE_REPLAY_LIQ}" "${REDUCED_STORE_LIVE_LOAD_LIQ}"; do - if [[ "${selected_top}" == "1" ]]; then - selected_top_count=$((selected_top_count + 1)) - fi -done -if (( selected_top_count > 1 )); then - echo "error: --marker-rows, --reduced-store-dispatch-stq, --reduced-store-replay-liq, and --reduced-store-live-load-liq are mutually exclusive" >&2 - exit 2 -fi -if [[ -z "${CAPTURE_ROWS}" ]]; then - if [[ "${EXPECTED_ROWS}" -gt 0 ]]; then - CAPTURE_ROWS="${EXPECTED_ROWS}" - else - CAPTURE_ROWS=128 - fi -fi -if [[ ! "${CAPTURE_ROWS}" =~ ^[1-9][0-9]*$ ]]; then - echo "error: --capture-rows must be a positive integer" >&2 - exit 2 -fi - -qemu_pids_for_elf() { - ps -Ao pid=,command= | awk -v q="${QEMU_BIN}" -v e="-kernel ${ELF}" ' - index($0, q) && index($0, e) { print $1 } - ' -} - -stop_qemu_for_elf() { - local pids="" - pids="$(qemu_pids_for_elf || true)" - if [[ -n "${pids}" ]]; then - while IFS= read -r pid; do - [[ -z "${pid}" ]] && continue - kill "${pid}" >/dev/null 2>&1 || true - done <<< "${pids}" - sleep 0.2 - pids="$(qemu_pids_for_elf || true)" - if [[ -n "${pids}" ]]; then - while IFS= read -r pid; do - [[ -z "${pid}" ]] && continue - kill -9 "${pid}" >/dev/null 2>&1 || true - done <<< "${pids}" - fi - fi -} - -cleanup() { - if [[ -n "${watchdog_pid}" ]]; then kill "${watchdog_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${producer_watch_pid}" ]]; then kill "${producer_watch_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${qemu_pid}" ]]; then kill "${qemu_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${reader_pid}" ]]; then kill "${reader_pid}" >/dev/null 2>&1 || true; fi - stop_qemu_for_elf - rm -f "${QEMU_FIFO}" -} -trap cleanup EXIT INT TERM - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" -rm -f "${QEMU_TRACE}" "${QEMU_FIFO}" -mkfifo "${QEMU_FIFO}" - -qemu_cmd=( - bash "${QEMU_TRACE_RUNNER}" - --elf "${ELF}" - --out "${QEMU_FIFO}" - --qemu-bin "${QEMU_BIN}" - --max-seconds "${MAX_SECONDS}" -) -if [[ -n "${PC_LO}" ]]; then - qemu_cmd+=(--pc-lo "${PC_LO}") -fi -if [[ -n "${PC_HI}" ]]; then - qemu_cmd+=(--pc-hi "${PC_HI}") -fi -if [[ "${#QEMU_ARGS[@]}" -ne 0 ]]; then - qemu_cmd+=(-- "${QEMU_ARGS[@]}") -fi - -python3 - "${QEMU_FIFO}" "${QEMU_TRACE}" "${CAPTURE_ROWS}" "${QEMU_SKIP_ROWS}" <<'PY' & -import sys - -fifo_path, out_path, rows_s, skip_s = sys.argv[1:5] -max_rows = int(rows_s) -skip_rows = int(skip_s) - -try: - with open(fifo_path, "r", encoding="utf-8", errors="replace") as src: - with open(out_path, "w", encoding="utf-8") as dst: - written = 0 - for index, line in enumerate(src): - if index < skip_rows: - continue - if written >= max_rows: - break - dst.write(line) - written += 1 -except KeyboardInterrupt: - raise SystemExit(130) -except BrokenPipeError: - raise SystemExit(0) -except OSError: - raise SystemExit(1) -PY -reader_pid=$! -"${qemu_cmd[@]}" >/dev/null & -qemu_pid=$! - -( - while kill -0 "${qemu_pid}" >/dev/null 2>&1; do - sleep 0.1 - done - if [[ -n "${reader_pid}" ]] && kill -0 "${reader_pid}" >/dev/null 2>&1; then - kill "${reader_pid}" >/dev/null 2>&1 || true - fi -) & -producer_watch_pid=$! - -if [[ "${MAX_SECONDS}" =~ ^[1-9][0-9]*$ ]]; then - ( - sleep "${MAX_SECONDS}" - if kill -0 "${qemu_pid}" >/dev/null 2>&1; then - stop_qemu_for_elf - kill "${qemu_pid}" >/dev/null 2>&1 || true - fi - ) & - watchdog_pid=$! -fi - -set +e -wait "${reader_pid}" -reader_rc=$? -reader_pid="" -if [[ -n "${producer_watch_pid}" ]]; then - kill "${producer_watch_pid}" >/dev/null 2>&1 || true - producer_watch_pid="" -fi -if [[ -n "${watchdog_pid}" ]]; then - kill "${watchdog_pid}" >/dev/null 2>&1 || true - watchdog_pid="" -fi -if kill -0 "${qemu_pid}" >/dev/null 2>&1; then - stop_qemu_for_elf - kill "${qemu_pid}" >/dev/null 2>&1 || true -fi -wait "${qemu_pid}" -qemu_rc=$? -qemu_pid="" -set -e - -rm -f "${QEMU_FIFO}" -QEMU_FIFO="" -raw_rows="$(awk 'END { print NR + 0 }' "${QEMU_TRACE}" 2>/dev/null || echo 0)" -if [[ "${reader_rc}" -ne 0 && "${raw_rows}" -gt 0 ]]; then - echo "warn: QEMU prefix reader exited with status ${reader_rc}" >&2 -fi -if [[ "${qemu_rc}" -ne 0 && "${raw_rows}" -gt 0 ]]; then - if [[ "${raw_rows}" -ge "${CAPTURE_ROWS}" ]]; then - echo "info: QEMU producer exited with status ${qemu_rc} after bounded prefix capture" >&2 - else - echo "warn: QEMU producer exited with status ${qemu_rc}; continuing with captured prefix" >&2 - fi -fi -echo "qemu-live-capture-raw-rows=${raw_rows}" -if [[ "${QEMU_SKIP_ROWS}" -gt 0 ]]; then - echo "qemu-live-skip-raw-rows=${QEMU_SKIP_ROWS}" -fi - -if [[ ! -s "${QEMU_TRACE}" ]]; then - write_frontend_manifest "qemu-capture" "fail" 2 - echo "error: QEMU trace not found or empty: ${QEMU_TRACE}" >&2 - exit 2 -fi - -if [[ "${QEMU_RAW_ONLY}" == "1" ]]; then - write_frontend_manifest "qemu-raw-only" "pass" 0 - echo "frontend-fetch-rf-alu-qemu-elf-status=qemu-raw-only raw_rows=${raw_rows} skipped_rows=${QEMU_SKIP_ROWS}" - echo "qemu-live-trace=${QEMU_TRACE}" - echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" - exit 0 -fi - -row_args=( - --input "${QEMU_TRACE}" - --output "${EXPECTED_PREVIEW}" - --max-rows "${EXPECTED_ROWS}" -) -if [[ "${ALLOW_BLOCK_MARKERS}" == "1" ]]; then - row_args+=(--allow-block-markers) -fi -if [[ "${ALLOW_BLOCK_LOOP_REENTRY}" == "1" ]]; then - row_args+=(--allow-block-loop-reentry) -fi -set +e -python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_qemu_rows.py" "${row_args[@]}" -reducer_rc=$? -set -e -if [[ "${reducer_rc}" -ne 0 ]]; then - write_frontend_manifest "qemu-reduce" "fail" "${reducer_rc}" - echo "frontend-fetch-rf-alu-qemu-elf-status=fail phase=qemu-reduce rc=${reducer_rc}" - echo "qemu-live-trace=${QEMU_TRACE}" - echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" - exit "${reducer_rc}" -fi - -if [[ -n "${EXPECT_LOAD_PCS}" || -n "${EXPECT_STORE_PCS}" ]]; then - set +e - python3 - "${EXPECTED_PREVIEW}" "${EXPECT_LOAD_PCS}" "${EXPECT_STORE_PCS}" <<'PY' -import json -import sys - -preview, expected_loads_s, expected_stores_s = sys.argv[1:4] - - -def parse_pc_list(text): - if not text: - return [] - out = [] - for item in text.split(","): - item = item.strip() - if item: - out.append(int(item, 0)) - return out - - -expected_loads = parse_pc_list(expected_loads_s) -expected_stores = parse_pc_list(expected_stores_s) -loads = [] -stores = [] -with open(preview, "r", encoding="utf-8") as f: - for line in f: - row = json.loads(line) - if row.get("mem_valid") != 1: - continue - pc = int(row.get("pc", 0)) - if row.get("mem_is_store") == 1: - stores.append(pc) - else: - loads.append(pc) - -if expected_loads_s and loads != expected_loads: - print( - "error: reduced preview load PCs {observed} did not match expected {expected}".format( - observed=",".join(hex(pc) for pc in loads), - expected=",".join(hex(pc) for pc in expected_loads), - ), - file=sys.stderr, - ) - raise SystemExit(1) -if expected_stores_s and stores != expected_stores: - print( - "error: reduced preview store PCs {observed} did not match expected {expected}".format( - observed=",".join(hex(pc) for pc in stores), - expected=",".join(hex(pc) for pc in expected_stores), - ), - file=sys.stderr, - ) - raise SystemExit(1) - -print("qemu-live-load-pcs=" + ",".join(hex(pc) for pc in loads)) -print("qemu-live-store-pcs=" + ",".join(hex(pc) for pc in stores)) -PY - pc_expect_rc=$? - set -e - if [[ "${pc_expect_rc}" -ne 0 ]]; then - write_frontend_manifest "qemu-pc-expect" "fail" "${pc_expect_rc}" - echo "frontend-fetch-rf-alu-qemu-elf-status=fail phase=qemu-pc-expect rc=${pc_expect_rc}" - echo "qemu-live-trace=${QEMU_TRACE}" - echo "qemu-live-expected-preview=${EXPECTED_PREVIEW}" - echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" - exit "${pc_expect_rc}" - fi -fi - -if [[ "${QEMU_ONLY}" == "1" ]]; then - write_frontend_manifest "qemu-only" "pass" 0 - echo "frontend-fetch-rf-alu-qemu-elf-status=qemu-only raw_rows=${raw_rows} skipped_rows=${QEMU_SKIP_ROWS}" - echo "qemu-live-trace=${QEMU_TRACE}" - echo "qemu-live-expected-preview=${EXPECTED_PREVIEW}" - echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" - exit 0 -fi - -set +e -BUILD_DIR="${BUILD_DIR}" \ -FETCH_ELF="${ELF}" \ -FETCH_ELF_LOAD_BIAS="${FETCH_ELF_LOAD_BIAS}" \ -FETCH_QEMU_TRACE="${QEMU_TRACE}" \ -FETCH_QEMU_MAX_ROWS="${EXPECTED_ROWS}" \ -FETCH_QEMU_ALLOW_BLOCK_MARKERS="${ALLOW_BLOCK_MARKERS}" \ -FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY="${ALLOW_BLOCK_LOOP_REENTRY}" \ -FETCH_MARKER_ROWS_TRACE_TOP="${MARKER_ROWS}" \ -FETCH_REDUCED_STORE_DISPATCH_STQ="${REDUCED_STORE_DISPATCH_STQ}" \ -FETCH_REDUCED_STORE_REPLAY_LIQ="${REDUCED_STORE_REPLAY_LIQ}" \ -FETCH_REDUCED_STORE_LIVE_LOAD_LIQ="${REDUCED_STORE_LIVE_LOAD_LIQ}" \ -FETCH_DISABLE_STORE_MEMORY_MUTATION="${DISABLE_STORE_MEMORY_MUTATION}" \ -FETCH_ALLOW_RESIDUAL_REPLAY_LIQ_WAIT="${ALLOW_RESIDUAL_REPLAY_LIQ_WAIT}" \ -FETCH_REPLAY_LIQ_REQUIRE_PRESET="${FETCH_REPLAY_LIQ_REQUIRE_PRESET}" \ -FETCH_REPLAY_LIQ_REQUIRE_NONZERO="${FETCH_REPLAY_LIQ_REQUIRE_NONZERO}" \ -FETCH_REPLAY_LIQ_REQUIRE_ZERO="${FETCH_REPLAY_LIQ_REQUIRE_ZERO}" \ -FETCH_RF_SEED="${RF_SEED}" \ -bash "${FETCH_RUNNER}" -fetch_rc=$? -set -e - -MANIFEST="${REPORT_DIR}/crosscheck_manifest.json" -if [[ ! -s "${MANIFEST}" ]]; then - if [[ "${fetch_rc}" -eq 0 ]]; then - write_frontend_manifest "generated-rtl" "fail" 3 - echo "error: expected cross-check manifest was not produced: ${MANIFEST}" >&2 - exit 3 - fi - write_frontend_manifest "generated-rtl" "fail" "${fetch_rc}" - echo "warn: generated-RTL runner exited ${fetch_rc} before producing cross-check manifest: ${MANIFEST}" >&2 - echo "qemu-live-trace=${QEMU_TRACE}" - echo "qemu-live-expected-preview=${EXPECTED_PREVIEW}" - echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" - exit "${fetch_rc}" -fi - -if [[ "${fetch_rc}" -eq 0 ]]; then - write_frontend_manifest "generated-rtl" "pass" 0 -else - write_frontend_manifest "generated-rtl" "fail" "${fetch_rc}" -fi - -python3 - "${MANIFEST}" <<'PY' -import json -import sys - -with open(sys.argv[1], "r", encoding="utf-8") as f: - manifest = json.load(f) -summary = manifest.get("summary", {}) -print( - "frontend-fetch-rf-alu-qemu-elf-status={status} compared={compared} mismatches={mismatches}".format( - status=manifest.get("status"), - compared=summary.get("compared_rows"), - mismatches=summary.get("mismatch_count"), - ) -) -PY - -echo "qemu-live-trace=${QEMU_TRACE}" -echo "qemu-live-expected-preview=${EXPECTED_PREVIEW}" -echo "frontend-fetch-rf-alu-qemu-elf-xcheck-report=${REPORT_DIR}" -exit "${fetch_rc}" diff --git a/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh b/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh deleted file mode 100755 index fabf1c6d..00000000 --- a/tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh +++ /dev/null @@ -1,306 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -FETCH_MARKER_ROWS_TRACE_TOP="${FETCH_MARKER_ROWS_TRACE_TOP:-0}" -FETCH_REDUCED_STORE_DISPATCH_STQ="${FETCH_REDUCED_STORE_DISPATCH_STQ:-0}" -FETCH_REDUCED_STORE_REPLAY_LIQ="${FETCH_REDUCED_STORE_REPLAY_LIQ:-0}" -FETCH_REDUCED_STORE_LIVE_LOAD_LIQ="${FETCH_REDUCED_STORE_LIVE_LOAD_LIQ:-0}" -selected_top_count=0 -for selected_top in "${FETCH_MARKER_ROWS_TRACE_TOP}" "${FETCH_REDUCED_STORE_DISPATCH_STQ}" "${FETCH_REDUCED_STORE_REPLAY_LIQ}" "${FETCH_REDUCED_STORE_LIVE_LOAD_LIQ}"; do - if [[ "${selected_top}" == "1" ]]; then - selected_top_count=$((selected_top_count + 1)) - fi -done -if (( selected_top_count > 1 )); then - echo "error: FETCH_MARKER_ROWS_TRACE_TOP, FETCH_REDUCED_STORE_DISPATCH_STQ, FETCH_REDUCED_STORE_REPLAY_LIQ, and FETCH_REDUCED_STORE_LIVE_LOAD_LIQ are mutually exclusive" >&2 - exit 2 -fi -if [[ "${FETCH_MARKER_ROWS_TRACE_TOP}" == "1" ]]; then - SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-marker-rows-trace-top" - TOP_MODULE="LinxCoreFrontendFetchRfAluMarkerRowsTraceTop" - EMIT_MAIN="linxcore.top.EmitLinxCoreFrontendFetchRfAluMarkerRowsTraceTop" -elif [[ "${FETCH_REDUCED_STORE_REPLAY_LIQ}" == "1" ]]; then - SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-replay-liq-trace-top" - TOP_MODULE="LinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop" - EMIT_MAIN="linxcore.top.EmitLinxCoreFrontendFetchRfAluReducedStoreReplayLiqTraceTop" -elif [[ "${FETCH_REDUCED_STORE_LIVE_LOAD_LIQ}" == "1" ]]; then - SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-live-load-liq-trace-top" - TOP_MODULE="LinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop" - EMIT_MAIN="linxcore.top.EmitLinxCoreFrontendFetchRfAluReducedStoreLiveLoadLiqTraceTop" -elif [[ "${FETCH_REDUCED_STORE_DISPATCH_STQ}" == "1" ]]; then - SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-reduced-store-trace-top" - TOP_MODULE="LinxCoreFrontendFetchRfAluReducedStoreTraceTop" - EMIT_MAIN="linxcore.top.EmitLinxCoreFrontendFetchRfAluReducedStoreTraceTop" -else - SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-trace-top" - TOP_MODULE="LinxCoreFrontendFetchRfAluTraceTop" - EMIT_MAIN="linxcore.top.EmitLinxCoreFrontendFetchRfAluTraceTop" -fi -TOP_SV="${SV_DIR}/${TOP_MODULE}.sv" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-frontend-fetch-rf-alu-trace-top-xcheck}" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-0}" -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" -SIDEBAND_STATS="${REPORT_DIR}/frontend_fetch_rf_alu_sideband_stats.json" -DEFAULT_FETCH_MEMORY_BIN="${BUILD_DIR}/fixture.fetch.bin" -DEFAULT_FETCH_MEMORY_HEX="${BUILD_DIR}/elf.fetch.mem" -DEFAULT_EXPECTED_ROWS="${BUILD_DIR}/fixture.expected.jsonl" -DEFAULT_QEMU_EXPECTED_ROWS="${BUILD_DIR}/qemu.expected.jsonl" -FETCH_ELF="${FETCH_ELF:-}" -FETCH_ELF_LOAD_BIAS="${FETCH_ELF_LOAD_BIAS:-0}" -FETCH_MEMORY_BIN="${FETCH_MEMORY_BIN:-}" -FETCH_MEMORY_HEX="${FETCH_MEMORY_HEX:-}" -FETCH_MEMORY_BASE="${FETCH_MEMORY_BASE:-0x1000}" -FETCH_EXPECTED_ROWS="${FETCH_EXPECTED_ROWS:-}" -FETCH_RF_SEED="${FETCH_RF_SEED:-}" -FETCH_QEMU_TRACE="${FETCH_QEMU_TRACE:-}" -FETCH_QEMU_MAX_ROWS="${FETCH_QEMU_MAX_ROWS:-0}" -FETCH_QEMU_ALLOW_BLOCK_MARKERS="${FETCH_QEMU_ALLOW_BLOCK_MARKERS:-0}" -FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY="${FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY:-0}" -FETCH_DISABLE_STORE_MEMORY_MUTATION="${FETCH_DISABLE_STORE_MEMORY_MUTATION:-0}" -FETCH_ALLOW_RESIDUAL_REPLAY_LIQ_WAIT="${FETCH_ALLOW_RESIDUAL_REPLAY_LIQ_WAIT:-0}" -FETCH_REPLAY_LIQ_REQUIRE_PRESET="${FETCH_REPLAY_LIQ_REQUIRE_PRESET:-}" -FETCH_REPLAY_LIQ_REQUIRE_NONZERO="${FETCH_REPLAY_LIQ_REQUIRE_NONZERO:-}" -FETCH_REPLAY_LIQ_REQUIRE_ZERO="${FETCH_REPLAY_LIQ_REQUIRE_ZERO:-}" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend fetch RF ALU trace top xcheck" >&2 - exit 2 -fi - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -if [[ -n "${FETCH_EXPECTED_ROWS}" && -n "${FETCH_QEMU_TRACE}" ]]; then - echo "error: set only one of FETCH_EXPECTED_ROWS or FETCH_QEMU_TRACE" >&2 - exit 2 -fi - -if [[ -n "${FETCH_QEMU_TRACE}" ]]; then - if [[ "${FETCH_QEMU_TRACE}" != /* ]]; then - FETCH_QEMU_TRACE="${ROOT_DIR}/${FETCH_QEMU_TRACE}" - fi - if [[ ! -f "${FETCH_QEMU_TRACE}" ]]; then - echo "error: FETCH_QEMU_TRACE does not exist: ${FETCH_QEMU_TRACE}" >&2 - exit 2 - fi - FETCH_EXPECTED_ROWS="${DEFAULT_QEMU_EXPECTED_ROWS}" - qemu_row_args=( - --input "${FETCH_QEMU_TRACE}" - --output "${FETCH_EXPECTED_ROWS}" - --max-rows "${FETCH_QEMU_MAX_ROWS}" - ) - if [[ "${FETCH_QEMU_ALLOW_BLOCK_MARKERS}" == "1" ]]; then - qemu_row_args+=(--allow-block-markers) - fi - if [[ "${FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY}" == "1" ]]; then - qemu_row_args+=(--allow-block-loop-reentry) - fi - python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_qemu_rows.py" "${qemu_row_args[@]}" -elif [[ -z "${FETCH_EXPECTED_ROWS}" ]]; then - FETCH_EXPECTED_ROWS="${DEFAULT_EXPECTED_ROWS}" - python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_fixture_rows.py" \ - --output "${FETCH_EXPECTED_ROWS}" -else - if [[ "${FETCH_EXPECTED_ROWS}" != /* ]]; then - FETCH_EXPECTED_ROWS="${ROOT_DIR}/${FETCH_EXPECTED_ROWS}" - fi - if [[ ! -f "${FETCH_EXPECTED_ROWS}" ]]; then - echo "error: FETCH_EXPECTED_ROWS does not exist: ${FETCH_EXPECTED_ROWS}" >&2 - exit 2 - fi -fi - -EXPECTED_ROW_COUNT="$(python3 - "${FETCH_EXPECTED_ROWS}" <<'PY' -import json -import sys - -path = sys.argv[1] -count = 0 -with open(path, "r", encoding="utf-8", errors="replace") as f: - for line in f: - line = line.strip() - if not line or line.startswith("#"): - continue - row = json.loads(line) - if row.get("type") == "META": - continue - if row.get("valid", 1) in (0, False, "0", "false", "False"): - continue - if row.get("skip", 0) in (1, True, "1", "true", "True"): - continue - count += 1 -print(count) -PY -)" -if [[ "${EXPECTED_ROW_COUNT}" -le 0 ]]; then - echo "error: expected row stream is empty: ${FETCH_EXPECTED_ROWS}" >&2 - exit 2 -fi - -if [[ -n "${FETCH_MEMORY_BIN}" && -n "${FETCH_MEMORY_HEX}" ]]; then - echo "error: set only one of FETCH_MEMORY_BIN or FETCH_MEMORY_HEX" >&2 - exit 2 -fi - -if [[ -n "${FETCH_ELF}" && -n "${FETCH_MEMORY_BIN}" ]]; then - echo "error: FETCH_ELF produces sparse memory and cannot be combined with FETCH_MEMORY_BIN" >&2 - exit 2 -fi - -MEMORY_ARGS=() -if [[ -n "${FETCH_ELF}" ]]; then - if [[ "${FETCH_ELF}" != /* ]]; then - FETCH_ELF="${ROOT_DIR}/${FETCH_ELF}" - fi - if [[ ! -f "${FETCH_ELF}" ]]; then - echo "error: FETCH_ELF does not exist: ${FETCH_ELF}" >&2 - exit 2 - fi - FETCH_MEMORY_HEX="${FETCH_MEMORY_HEX:-${DEFAULT_FETCH_MEMORY_HEX}}" - python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_elf_memory.py" \ - --elf "${FETCH_ELF}" \ - --output "${FETCH_MEMORY_HEX}" \ - --load-bias "${FETCH_ELF_LOAD_BIAS}" -fi - -if [[ -n "${FETCH_MEMORY_HEX}" ]]; then - if [[ ! -f "${FETCH_MEMORY_HEX}" ]]; then - echo "error: FETCH_MEMORY_HEX does not exist: ${FETCH_MEMORY_HEX}" >&2 - exit 2 - fi - MEMORY_ARGS=(--memory-hex "${FETCH_MEMORY_HEX}") -else - FETCH_MEMORY_BIN="${FETCH_MEMORY_BIN:-${DEFAULT_FETCH_MEMORY_BIN}}" - if [[ "${FETCH_MEMORY_BIN}" == "${DEFAULT_FETCH_MEMORY_BIN}" ]]; then - python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_fixture_memory.py" \ - --output "${FETCH_MEMORY_BIN}" - elif [[ ! -f "${FETCH_MEMORY_BIN}" ]]; then - echo "error: FETCH_MEMORY_BIN does not exist: ${FETCH_MEMORY_BIN}" >&2 - exit 2 - fi - MEMORY_ARGS=(--memory-bin "${FETCH_MEMORY_BIN}" --memory-base "${FETCH_MEMORY_BASE}") -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -rm -rf "${SV_DIR}" -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain ${EMIT_MAIN}" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend fetch RF ALU trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -VERILATOR_CFLAGS="-std=c++17 -O2" -TB_ARGS=( - --dut-trace "${DUT_TRACE}" - --qemu-trace "${QEMU_TRACE}" - --expected-rows "${FETCH_EXPECTED_ROWS}" - --sideband-stats "${SIDEBAND_STATS}" - "${MEMORY_ARGS[@]}" -) -if [[ -n "${FETCH_RF_SEED}" ]]; then - if [[ "${FETCH_RF_SEED}" != /* ]]; then - FETCH_RF_SEED="${ROOT_DIR}/${FETCH_RF_SEED}" - fi - if [[ ! -f "${FETCH_RF_SEED}" ]]; then - echo "error: FETCH_RF_SEED does not exist: ${FETCH_RF_SEED}" >&2 - exit 2 - fi - TB_ARGS+=(--rf-seed "${FETCH_RF_SEED}") -fi -if [[ "${FETCH_MARKER_ROWS_TRACE_TOP}" == "1" ]]; then - VERILATOR_CFLAGS="${VERILATOR_CFLAGS} -DLINXCORE_MARKER_ROWS_TRACE_TOP" - TB_ARGS+=(--admit-marker-rows) -elif [[ "${FETCH_REDUCED_STORE_REPLAY_LIQ}" == "1" ]]; then - VERILATOR_CFLAGS="${VERILATOR_CFLAGS} -DLINXCORE_REDUCED_STORE_REPLAY_LIQ_TRACE_TOP" -elif [[ "${FETCH_REDUCED_STORE_LIVE_LOAD_LIQ}" == "1" ]]; then - VERILATOR_CFLAGS="${VERILATOR_CFLAGS} -DLINXCORE_REDUCED_STORE_LIVE_LOAD_LIQ_TRACE_TOP" -elif [[ "${FETCH_REDUCED_STORE_DISPATCH_STQ}" == "1" ]]; then - VERILATOR_CFLAGS="${VERILATOR_CFLAGS} -DLINXCORE_REDUCED_STORE_TRACE_TOP" -fi -if [[ "${FETCH_DISABLE_STORE_MEMORY_MUTATION}" == "1" ]]; then - TB_ARGS+=(--disable-store-memory-mutation) -fi -if [[ "${FETCH_ALLOW_RESIDUAL_REPLAY_LIQ_WAIT}" == "1" ]]; then - TB_ARGS+=(--allow-residual-replay-liq-wait) -fi -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module "${TOP_MODULE}" \ - --exe "${ROOT_DIR}/tools/chisel/frontend_fetch_rf_alu_trace_top_tb.cpp" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_fetch_rf_alu_trace_top_tb \ - -CFLAGS "${VERILATOR_CFLAGS}" - -"${OBJ_DIR}/linxcore_frontend_fetch_rf_alu_trace_top_tb" "${TB_ARGS[@]}" - -SIDEBAND_VALIDATOR_ARGS=("${SIDEBAND_STATS}") -if [[ "${FETCH_REDUCED_STORE_REPLAY_LIQ}" == "1" || "${FETCH_REDUCED_STORE_LIVE_LOAD_LIQ}" == "1" ]]; then - SIDEBAND_VALIDATOR_ARGS+=(--expect-reduced-store-replay-liq) -fi -if [[ -n "${FETCH_REPLAY_LIQ_REQUIRE_PRESET}" ]]; then - IFS=',' read -r -a replay_liq_required_presets <<< "${FETCH_REPLAY_LIQ_REQUIRE_PRESET}" - for replay_liq_required_preset in "${replay_liq_required_presets[@]}"; do - if [[ -n "${replay_liq_required_preset}" ]]; then - SIDEBAND_VALIDATOR_ARGS+=(--preset "${replay_liq_required_preset}") - fi - done -fi -if [[ -n "${FETCH_REPLAY_LIQ_REQUIRE_NONZERO}" ]]; then - IFS=',' read -r -a replay_liq_required_nonzero <<< "${FETCH_REPLAY_LIQ_REQUIRE_NONZERO}" - for replay_liq_required_counter in "${replay_liq_required_nonzero[@]}"; do - if [[ -n "${replay_liq_required_counter}" ]]; then - if [[ "${replay_liq_required_counter}" == replay_liq.* ]]; then - SIDEBAND_VALIDATOR_ARGS+=(--require-nonzero "${replay_liq_required_counter}") - else - SIDEBAND_VALIDATOR_ARGS+=(--require-nonzero "replay_liq.${replay_liq_required_counter}") - fi - fi - done -fi -if [[ -n "${FETCH_REPLAY_LIQ_REQUIRE_ZERO}" ]]; then - IFS=',' read -r -a replay_liq_required_zero <<< "${FETCH_REPLAY_LIQ_REQUIRE_ZERO}" - for replay_liq_required_counter in "${replay_liq_required_zero[@]}"; do - if [[ -n "${replay_liq_required_counter}" ]]; then - if [[ "${replay_liq_required_counter}" == replay_liq.* ]]; then - SIDEBAND_VALIDATOR_ARGS+=(--require-zero "${replay_liq_required_counter}") - else - SIDEBAND_VALIDATOR_ARGS+=(--require-zero "replay_liq.${replay_liq_required_counter}") - fi - fi - done -fi -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits "${EXPECTED_ROW_COUNT}" \ - --mode failfast - -python3 "${ROOT_DIR}/tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py" \ - "${SIDEBAND_VALIDATOR_ARGS[@]}" - -echo "frontend-fetch-rf-alu-trace-top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh b/tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh deleted file mode 100755 index 33722fc6..00000000 --- a/tools/chisel/run_chisel_frontend_fetch_trace_top_xcheck.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendFetchTraceTop.sv" -BUILD_DIR="${ROOT_DIR}/generated/chisel-frontend-fetch-trace-top-xcheck" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend fetch trace top xcheck" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendFetchTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend fetch trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendFetchTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/frontend_fetch_trace_top_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_fetch_trace_top_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/linxcore_frontend_fetch_trace_top_tb" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits 3 \ - --mode failfast - -echo "frontend-fetch-trace-top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh b/tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh deleted file mode 100755 index 69ea0ef5..00000000 --- a/tools/chisel/run_chisel_frontend_rf_alu_trace_top_xcheck.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-rf-alu-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendRfAluTraceTop.sv" -BUILD_DIR="${ROOT_DIR}/generated/chisel-frontend-rf-alu-trace-top-xcheck" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend RF ALU trace top xcheck" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendRfAluTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend RF ALU trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendRfAluTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/frontend_alu_trace_top_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_rf_alu_trace_top_tb \ - -CFLAGS "-std=c++17 -O2 -DLINXCORE_RF_ALU_TRACE_TOP" - -"${OBJ_DIR}/linxcore_frontend_rf_alu_trace_top_tb" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits 3 \ - --mode failfast - -echo "frontend-rf-alu-trace-top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_frontend_trace_top_lint.sh b/tools/chisel/run_chisel_frontend_trace_top_lint.sh deleted file mode 100755 index e49977f3..00000000 --- a/tools/chisel/run_chisel_frontend_trace_top_lint.sh +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendTraceTop.sv" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend trace top lint" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -verilator --lint-only --top-module LinxCoreFrontendTraceTop "${SV_FILES[@]}" diff --git a/tools/chisel/run_chisel_frontend_trace_top_xcheck.sh b/tools/chisel/run_chisel_frontend_trace_top_xcheck.sh deleted file mode 100755 index eb797b98..00000000 --- a/tools/chisel/run_chisel_frontend_trace_top_xcheck.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-trace-top" -TOP_SV="${SV_DIR}/LinxCoreFrontendTraceTop.sv" -BUILD_DIR="${ROOT_DIR}/generated/chisel-frontend-trace-top-xcheck" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for Chisel frontend trace top xcheck" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendTraceTop" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: missing emitted top: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no frontend trace top SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/frontend_trace_top_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_frontend_trace_top_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/linxcore_frontend_trace_top_tb" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits 3 \ - --mode failfast - -echo "frontend-trace-top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe.sh b/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe.sh deleted file mode 100755 index c056f06d..00000000 --- a/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe.sh +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -BUILD_ARG="generated/chisel-verilator/lsu-reduced-store-sta-address-exec-hl-sdi-pr-probe-r857" -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_ARG="$2" - shift 2 - ;; - *) - echo "unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_ARG}" = /* ]]; then - BUILD_DIR="${BUILD_ARG}" -else - BUILD_DIR="${ROOT_DIR}/${BUILD_ARG}" -fi -SV_DIR="${BUILD_DIR}/sv" -OBJ_DIR="${BUILD_DIR}/obj_dir" - -rm -rf "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${OBJ_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.lsu.EmitReducedStoreStaAddressExecHlSdiPrProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedStoreStaAddressExecHlSdiPrProbe \ - --exe "${ROOT_DIR}/tools/chisel/lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${OBJ_DIR}" \ - -o lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb -CFLAGS '-std=c++17 -O2' - -"${OBJ_DIR}/lsu_reduced_store_sta_address_exec_hl_sdi_pr_probe_tb" diff --git a/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_sb_probe.sh b/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_sb_probe.sh deleted file mode 100755 index 100f47b5..00000000 --- a/tools/chisel/run_chisel_lsu_reduced_store_sta_address_exec_sb_probe.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/lsu-reduced-store-sta-address-exec-sb-probe-r813" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/lsu-reduced-store-sta-address-exec-sb-probe-r813" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "Test / runMain linxcore.lsu.EmitReducedStoreStaAddressExecSbProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" --top-module ReducedStoreStaAddressExecSbProbe \ - --exe "${ROOT_DIR}/tools/chisel/lsu_reduced_store_sta_address_exec_sb_probe_tb.cpp" \ - --build --build-jobs 0 -Mdir "${BUILD_DIR}/obj_dir" \ - -o lsu_reduced_store_sta_address_exec_sb_probe_tb -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/lsu_reduced_store_sta_address_exec_sb_probe_tb" diff --git a/tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh b/tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh deleted file mode 100755 index 1c4fc1e1..00000000 --- a/tools/chisel/run_chisel_qemu_trace_replay_xcheck.sh +++ /dev/null @@ -1,338 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-qemu-trace-replay-xcheck}" -ELF="" -QEMU_TRACE="" -QEMU_BIN="" -MAX_COMMITS="${MAX_COMMITS:-32}" -REPLAY_ROWS="" -MAX_SECONDS="${MAX_SECONDS:-30}" -PC_LO="" -PC_HI="" -DRY_RUN=0 - -usage() { - cat < [options] -- [qemu args] - $(basename "$0") --qemu-trace [options] - $(basename "$0") --dry-run - -Options: - --build-dir Output root (default: ${BUILD_DIR}) - --qemu-bin QEMU binary. Defaults to the Chisel cross-check QEMU. - --max-commits Commit rows replayed/compared (default: ${MAX_COMMITS}) - --replay-rows Raw rows driven before metadata filtering - --max-seconds Timeout for QEMU trace collection (default: ${MAX_SECONDS}) - --pc-lo Optional QEMU commit-trace PC filter low bound - --pc-hi Optional QEMU commit-trace PC filter high bound - -The --elf mode collects a QEMU commit trace first, then replays the resulting -architectural rows through the current Chisel commit-surface harness. The ---qemu-trace mode skips QEMU execution and replays an existing QEMU JSONL trace. -In --elf mode, --replay-rows also bounds the raw QEMU prefix collected before -the wrapper stops QEMU. -USAGE -} - -QEMU_ARGS=() -while [[ $# -gt 0 ]]; do - case "$1" in - --elf) ELF="$2"; shift 2 ;; - --qemu-trace) QEMU_TRACE="$2"; shift 2 ;; - --build-dir) BUILD_DIR="$2"; shift 2 ;; - --qemu-bin) QEMU_BIN="$2"; shift 2 ;; - --max-commits) MAX_COMMITS="$2"; shift 2 ;; - --replay-rows) REPLAY_ROWS="$2"; shift 2 ;; - --max-seconds) MAX_SECONDS="$2"; shift 2 ;; - --pc-lo) PC_LO="$2"; shift 2 ;; - --pc-hi) PC_HI="$2"; shift 2 ;; - --dry-run) DRY_RUN=1; shift ;; - --) - shift - QEMU_ARGS=("$@") - break - ;; - -h|--help) usage; exit 0 ;; - *) echo "error: unknown argument: $1" >&2; usage; exit 2 ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -MANIFEST="${REPORT_DIR}/crosscheck_manifest.json" -QEMU_FIFO="" -qemu_pid="" -reader_pid="" -watchdog_pid="" -producer_watch_pid="" -QEMU_TRACE_RUNNER="${ROOT_DIR}/tools/qemu/run_qemu_commit_trace.sh" -TRACE_REPLAY_RUNNER="${ROOT_DIR}/tools/chisel/run_chisel_trace_replay_xcheck.sh" -QEMU_CROSSCHECK_RUNNER="${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" - -if [[ -z "${QEMU_BIN}" ]]; then - QEMU_BIN="$(bash "${QEMU_CROSSCHECK_RUNNER}" --print-qemu-bin)" -fi -if [[ -z "${REPLAY_ROWS}" ]]; then - REPLAY_ROWS="$((MAX_COMMITS * 32 + 1024))" -fi - -qemu_pids_for_elf() { - ps -Ao pid=,command= | awk -v q="${QEMU_BIN}" -v e="-kernel ${ELF}" ' - index($0, q) && index($0, e) { print $1 } - ' -} - -stop_qemu_for_elf() { - local pids="" - pids="$(qemu_pids_for_elf || true)" - if [[ -n "${pids}" ]]; then - while IFS= read -r pid; do - [[ -z "${pid}" ]] && continue - kill "${pid}" >/dev/null 2>&1 || true - done <<< "${pids}" - sleep 0.2 - pids="$(qemu_pids_for_elf || true)" - if [[ -n "${pids}" ]]; then - while IFS= read -r pid; do - [[ -z "${pid}" ]] && continue - kill -9 "${pid}" >/dev/null 2>&1 || true - done <<< "${pids}" - fi - fi -} - -cleanup() { - if [[ -n "${watchdog_pid}" ]]; then kill "${watchdog_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${producer_watch_pid}" ]]; then kill "${producer_watch_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${qemu_pid}" ]]; then kill "${qemu_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${reader_pid}" ]]; then kill "${reader_pid}" >/dev/null 2>&1 || true; fi - if [[ -n "${ELF}" ]]; then stop_qemu_for_elf; fi - if [[ -n "${QEMU_FIFO}" ]]; then rm -f "${QEMU_FIFO}"; fi -} -trap cleanup EXIT INT TERM - -if [[ "${DRY_RUN}" -eq 1 ]]; then - echo "qemu-bin=${QEMU_BIN}" - echo "max-commits=${MAX_COMMITS}" - echo "replay-rows=${REPLAY_ROWS}" - echo "qemu-trace-runner=${QEMU_TRACE_RUNNER}" - echo "trace-replay-runner=${TRACE_REPLAY_RUNNER}" - bash "${QEMU_CROSSCHECK_RUNNER}" --dry-run - exit 0 -fi - -if [[ -n "${ELF}" && -n "${QEMU_TRACE}" ]]; then - echo "error: choose either --elf or --qemu-trace, not both" >&2 - exit 2 -fi -if [[ -z "${ELF}" && -z "${QEMU_TRACE}" ]]; then - echo "error: --elf or --qemu-trace is required" >&2 - usage - exit 2 -fi -if [[ -n "${QEMU_TRACE}" && "${#QEMU_ARGS[@]}" -ne 0 ]]; then - echo "error: trailing QEMU args are only valid with --elf" >&2 - exit 2 -fi - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -if [[ -n "${ELF}" ]]; then - if [[ ! "${REPLAY_ROWS}" =~ ^[1-9][0-9]*$ ]]; then - echo "error: --replay-rows must be a positive integer for --elf capture" >&2 - exit 2 - fi - QEMU_TRACE="${TRACE_DIR}/qemu.raw.jsonl" - QEMU_FIFO="${TRACE_DIR}/qemu.raw.fifo" - rm -f "${QEMU_TRACE}" "${QEMU_FIFO}" - mkfifo "${QEMU_FIFO}" - - qemu_cmd=( - bash "${QEMU_TRACE_RUNNER}" - --elf "${ELF}" - --out "${QEMU_FIFO}" - --qemu-bin "${QEMU_BIN}" - --max-seconds "${MAX_SECONDS}" - ) - if [[ -n "${PC_LO}" ]]; then - qemu_cmd+=(--pc-lo "${PC_LO}") - fi - if [[ -n "${PC_HI}" ]]; then - qemu_cmd+=(--pc-hi "${PC_HI}") - fi - if [[ "${#QEMU_ARGS[@]}" -ne 0 ]]; then - qemu_cmd+=(-- "${QEMU_ARGS[@]}") - fi - - python3 - "${QEMU_FIFO}" "${QEMU_TRACE}" "${REPLAY_ROWS}" <<'PY' & -import sys - -fifo_path, out_path, rows_s = sys.argv[1:4] -max_rows = int(rows_s) - -try: - with open(fifo_path, "r", encoding="utf-8", errors="replace") as src: - with open(out_path, "w", encoding="utf-8") as dst: - for index, line in enumerate(src): - if index >= max_rows: - break - dst.write(line) -except KeyboardInterrupt: - raise SystemExit(130) -except BrokenPipeError: - raise SystemExit(0) -except OSError: - raise SystemExit(1) -PY - reader_pid=$! - "${qemu_cmd[@]}" >/dev/null & - qemu_pid=$! - - ( - while kill -0 "${qemu_pid}" >/dev/null 2>&1; do - sleep 0.1 - done - if [[ -n "${reader_pid}" ]] && kill -0 "${reader_pid}" >/dev/null 2>&1; then - kill "${reader_pid}" >/dev/null 2>&1 || true - fi - ) & - producer_watch_pid=$! - - if [[ "${MAX_SECONDS}" =~ ^[1-9][0-9]*$ ]]; then - ( - sleep "${MAX_SECONDS}" - if kill -0 "${qemu_pid}" >/dev/null 2>&1; then - stop_qemu_for_elf - kill "${qemu_pid}" >/dev/null 2>&1 || true - fi - ) & - watchdog_pid=$! - fi - - set +e - wait "${reader_pid}" - reader_rc=$? - reader_pid="" - if [[ -n "${producer_watch_pid}" ]]; then - kill "${producer_watch_pid}" >/dev/null 2>&1 || true - producer_watch_pid="" - fi - if [[ -n "${watchdog_pid}" ]]; then - kill "${watchdog_pid}" >/dev/null 2>&1 || true - watchdog_pid="" - fi - if kill -0 "${qemu_pid}" >/dev/null 2>&1; then - stop_qemu_for_elf - kill "${qemu_pid}" >/dev/null 2>&1 || true - fi - wait "${qemu_pid}" - qemu_rc=$? - qemu_pid="" - set -e - - rm -f "${QEMU_FIFO}" - QEMU_FIFO="" - raw_rows="$(awk 'END { print NR + 0 }' "${QEMU_TRACE}" 2>/dev/null || echo 0)" - if [[ "${reader_rc}" -ne 0 && "${raw_rows}" -gt 0 ]]; then - echo "warn: QEMU prefix reader exited with status ${reader_rc}" >&2 - fi - if [[ "${qemu_rc}" -ne 0 && "${raw_rows}" -gt 0 ]]; then - if [[ "${raw_rows}" -ge "${REPLAY_ROWS}" ]]; then - echo "info: QEMU producer exited with status ${qemu_rc} after bounded prefix capture" >&2 - else - echo "warn: QEMU producer exited with status ${qemu_rc}; continuing with captured prefix" >&2 - fi - fi - echo "qemu-capture-raw-rows=${raw_rows}" -fi - -if [[ ! -s "${QEMU_TRACE}" ]]; then - echo "error: QEMU trace not found or empty: ${QEMU_TRACE}" >&2 - exit 2 -fi - -WIDE_TRACE="${TRACE_DIR}/qemu.replay_input.wide.normalized.jsonl" -REPLAY_INPUT_TRACE="${TRACE_DIR}/qemu.replay_input.jsonl" -python3 "${ROOT_DIR}/tools/chisel/trace_schema_adapter.py" \ - --input "${QEMU_TRACE}" \ - --output "${WIDE_TRACE}" \ - --max-rows "${REPLAY_ROWS}" -python3 - "${ROOT_DIR}" "${WIDE_TRACE}" "${REPLAY_INPUT_TRACE}" "${MAX_COMMITS}" <<'PY' -import importlib.util -import sys -from pathlib import Path - -root = Path(sys.argv[1]) -wide = Path(sys.argv[2]) -out = Path(sys.argv[3]) -max_commits = int(sys.argv[4]) - -spec = importlib.util.spec_from_file_location( - "linxcore_xcheck", root / "tools" / "trace" / "crosscheck_qemu_linxcore.py" -) -if spec is None or spec.loader is None: - raise SystemExit("error: failed to load cross-check metadata classifier") -module = importlib.util.module_from_spec(spec) -sys.modules[spec.name] = module -spec.loader.exec_module(module) - -lines = [line for line in wide.read_text(encoding="utf-8").splitlines() if line] -rows = module._load_trace(wide, 0) -selected: list[str] = [] -arch_rows = 0 -for line, row in zip(lines, rows): - selected.append(line) - if not module._is_metadata_commit(row): - arch_rows += 1 - if max_commits > 0 and arch_rows >= max_commits: - break - -if max_commits > 0 and arch_rows < max_commits: - raise SystemExit( - f"error: QEMU trace has only {arch_rows} architectural rows within the replay window; need {max_commits}" - ) - -out.write_text("\n".join(selected) + ("\n" if selected else ""), encoding="utf-8") -print(f"qemu-replay-input={out}") -print(f"qemu-replay-raw-rows={len(selected)}") -print(f"qemu-replay-arch-rows={arch_rows}") -PY -QEMU_TRACE="${REPLAY_INPUT_TRACE}" - -bash "${TRACE_REPLAY_RUNNER}" \ - --input-trace "${QEMU_TRACE}" \ - --max-commits "${MAX_COMMITS}" \ - --replay-rows "${REPLAY_ROWS}" \ - --build-dir "${BUILD_DIR}" - -if [[ ! -s "${MANIFEST}" ]]; then - echo "error: expected cross-check manifest was not produced: ${MANIFEST}" >&2 - exit 3 -fi - -python3 - "${MANIFEST}" <<'PY' -import json -import sys - -with open(sys.argv[1], "r", encoding="utf-8") as f: - manifest = json.load(f) -summary = manifest.get("summary", {}) -print( - "qemu-trace-replay-status={status} compared={compared} mismatches={mismatches}".format( - status=manifest.get("status"), - compared=summary.get("compared_rows"), - mismatches=summary.get("mismatch_count"), - ) -) -PY - -echo "qemu-trace=${QEMU_TRACE}" -echo "qemu-trace-replay-xcheck-report=${REPORT_DIR}" -echo "qemu-trace-replay-xcheck-manifest=${MANIFEST}" diff --git a/tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh b/tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh deleted file mode 100755 index 8d996d17..00000000 --- a/tools/chisel/run_chisel_reduced_store_wait_replay_chisel_path.sh +++ /dev/null @@ -1,70 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/reduced-store-wait-replay-chisel-path" -SV_FILE="${SV_DIR}/ReducedStoreWaitReplayChiselPathProbe.sv" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-reduced-store-wait-replay-chisel-path}" -OBJ_DIR="${BUILD_DIR}/obj_dir" -REPORT_DIR="${BUILD_DIR}/report" -REPORT_JSON="${REPORT_DIR}/reduced_store_wait_replay_chisel_path.json" -REDUCED_STORE_WAIT_REPLAY_REQUIRE_TRUE="${REDUCED_STORE_WAIT_REPLAY_REQUIRE_TRUE:-mdb_lookup_wait_plan_scb_evidence,mdb_lookup_wait_plan_write,mdb_lookup_wait_plan_apply,mdb_lookup_wait_plan_wait_status_after_write}" -REDUCED_STORE_WAIT_REPLAY_REQUIRE_NONZERO="${REDUCED_STORE_WAIT_REPLAY_REQUIRE_NONZERO:-liq_replay_wake_completed_mask,liq_scb_returned_mask_before_mdb_write,liq_sources_returned_mask_before_mdb_write,liq_wait_mask_after_mdb_write,liq_wait_store_mask_after_mdb_write}" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.lsu.EmitReducedStoreWaitReplayChiselPathProbe" - -if [[ ! -f "${SV_FILE}" ]]; then - echo "error: reduced store wait/replay probe SystemVerilog was not emitted: ${SV_FILE}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no reduced store wait/replay SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module ReducedStoreWaitReplayChiselPathProbe \ - --exe "${ROOT_DIR}/tools/chisel/reduced_store_wait_replay_chisel_path_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o reduced_store_wait_replay_chisel_path_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/reduced_store_wait_replay_chisel_path_tb" \ - --report-json "${REPORT_JSON}" - -REPORT_VALIDATOR_ARGS=("${REPORT_JSON}") -if [[ -n "${REDUCED_STORE_WAIT_REPLAY_REQUIRE_TRUE}" ]]; then - IFS=',' read -r -a reduced_store_required_true <<< "${REDUCED_STORE_WAIT_REPLAY_REQUIRE_TRUE}" - for reduced_store_report_key in "${reduced_store_required_true[@]}"; do - if [[ -n "${reduced_store_report_key}" ]]; then - REPORT_VALIDATOR_ARGS+=(--require-true "${reduced_store_report_key}") - fi - done -fi -if [[ -n "${REDUCED_STORE_WAIT_REPLAY_REQUIRE_NONZERO}" ]]; then - IFS=',' read -r -a reduced_store_required_nonzero <<< "${REDUCED_STORE_WAIT_REPLAY_REQUIRE_NONZERO}" - for reduced_store_report_key in "${reduced_store_required_nonzero[@]}"; do - if [[ -n "${reduced_store_report_key}" ]]; then - REPORT_VALIDATOR_ARGS+=(--require-nonzero "${reduced_store_report_key}") - fi - done -fi -python3 "${ROOT_DIR}/tools/chisel/validate_reduced_store_wait_replay_chisel_path.py" \ - "${REPORT_VALIDATOR_ARGS[@]}" - -echo "reduced-store-wait-replay-chisel-path-report=${REPORT_JSON}" diff --git a/tools/chisel/run_chisel_replay_liq_coremark_context_pack.sh b/tools/chisel/run_chisel_replay_liq_coremark_context_pack.sh deleted file mode 100755 index 6de72489..00000000 --- a/tools/chisel/run_chisel_replay_liq_coremark_context_pack.sh +++ /dev/null @@ -1,245 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/r525-replay-liq-coremark-context-pack}" -COREMARK_ELF="${COREMARK_ELF:-${ROOT_DIR}/tests/benchmarks/build/coremark_real.elf}" -COREMARK_ROWS="${COREMARK_ROWS:-1024}" -COREMARK_MAX_SECONDS="${COREMARK_MAX_SECONDS:-30}" -REPLAY_CAPTURE_ROWS="${REPLAY_CAPTURE_ROWS:-18}" -REPLAY_MAX_SECONDS="${REPLAY_MAX_SECONDS:-8}" -RUN_FOCUSED=1 -ALLOW_NATURAL_COREMARK_REPLAY=0 - -usage() { - cat < Output root (default: ${BUILD_DIR}) - --coremark-elf CoreMark ELF (default: ${COREMARK_ELF}) - --coremark-rows Raw CoreMark QEMU rows to capture (default: ${COREMARK_ROWS}) - --coremark-max-seconds CoreMark capture watchdog (default: ${COREMARK_MAX_SECONDS}) - --replay-capture-rows Constructed replay-loop rows to capture (default: ${REPLAY_CAPTURE_ROWS}) - --replay-max-seconds Constructed replay-loop watchdog (default: ${REPLAY_MAX_SECONDS}) - --skip-focused Skip focused Chisel specs before generated-RTL gates - --allow-natural-coremark-replay - Do not require the CoreMark prefix replay-LIQ counters to stay zero - -Runs the focused replay-LIQ owner specs, a real CoreMark reduced-store -replay-LIQ prefix gate, and the R524 constructed replay-LIQ/MDB positive gate. -The combined manifest explicitly separates natural CoreMark no-regression -evidence from constructed replay-LIQ/MDB evidence; it is not full LSU or -natural CoreMark replay coverage. -USAGE -} - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) BUILD_DIR="$2"; shift 2 ;; - --coremark-elf) COREMARK_ELF="$2"; shift 2 ;; - --coremark-rows) COREMARK_ROWS="$2"; shift 2 ;; - --coremark-max-seconds) COREMARK_MAX_SECONDS="$2"; shift 2 ;; - --replay-capture-rows) REPLAY_CAPTURE_ROWS="$2"; shift 2 ;; - --replay-max-seconds) REPLAY_MAX_SECONDS="$2"; shift 2 ;; - --skip-focused) RUN_FOCUSED=0; shift ;; - --allow-natural-coremark-replay) ALLOW_NATURAL_COREMARK_REPLAY=1; shift ;; - -h|--help) usage; exit 0 ;; - *) echo "error: unknown argument: $1" >&2; usage; exit 2 ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -if [[ "${COREMARK_ELF}" != /* ]]; then - COREMARK_ELF="${ROOT_DIR}/${COREMARK_ELF}" -fi -if [[ ! -f "${COREMARK_ELF}" ]]; then - echo "error: CoreMark ELF not found: ${COREMARK_ELF}" >&2 - exit 2 -fi -for numeric in COREMARK_ROWS COREMARK_MAX_SECONDS REPLAY_CAPTURE_ROWS REPLAY_MAX_SECONDS; do - value="${!numeric}" - if [[ ! "${value}" =~ ^[1-9][0-9]*$ ]]; then - echo "error: ${numeric} must be a positive integer, got ${value}" >&2 - exit 2 - fi -done - -LOG_DIR="${BUILD_DIR}/logs" -REPORT_DIR="${BUILD_DIR}/report" -COREMARK_BUILD_DIR="${BUILD_DIR}/coremark-prefix" -REPLAY_BUILD_DIR="${BUILD_DIR}/constructed-replay-loop" -mkdir -p "${LOG_DIR}" "${REPORT_DIR}" - -run_logged() { - local label="$1" - shift - local log="${LOG_DIR}/${label}.log" - local cmd_log="${LOG_DIR}/${label}.cmd" - printf '%q ' "$@" > "${cmd_log}" - printf '\n' >> "${cmd_log}" - echo "r525-pack-run=${label}" - "$@" 2>&1 | tee "${log}" -} - -if [[ "${RUN_FOCUSED}" == "1" ]]; then - for spec in \ - ReducedStoreResidentForward \ - LoadForwardPipeline \ - LoadInflightQueue \ - LoadReplayWakeup \ - MDBConflictDetect \ - LinxCoreFrontendFetchRfAluTraceTop; do - run_logged "focused-${spec}" \ - bash "${ROOT_DIR}/tools/chisel/run_chisel_tests.sh" --only "${spec}" - done -fi - -COREMARK_ZERO_COUNTERS="wait_replay_capture_accepted,replay_queue_out_fire,liq_alloc_accepted,mdb_conflict_valid,mdb_lookup_wait_plan_request_valid,liq_replay_wake_wait_store_clear" -COREMARK_ENV=( - "FETCH_REPLAY_LIQ_REQUIRE_ZERO=${COREMARK_ZERO_COUNTERS}" -) -if [[ "${ALLOW_NATURAL_COREMARK_REPLAY}" == "1" ]]; then - COREMARK_ENV=() -fi - -run_logged "coremark-prefix-replay-liq" \ - env "${COREMARK_ENV[@]}" \ - bash "${ROOT_DIR}/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh" \ - --build-dir "${COREMARK_BUILD_DIR}" \ - --elf "${COREMARK_ELF}" \ - --expected-rows 0 \ - --capture-rows "${COREMARK_ROWS}" \ - --allow-block-markers \ - --allow-block-loop-reentry \ - --reduced-store-replay-liq \ - --disable-store-memory-mutation \ - --max-seconds "${COREMARK_MAX_SECONDS}" \ - -- \ - -nographic \ - -monitor none \ - -machine virt \ - -m 1280M \ - -kernel "${COREMARK_ELF}" - -REPLAY_NONZERO_COUNTERS="wait_replay_capture_accepted,wait_replay_clear_valid,wait_replay_relaunch_valid,replay_queue_enqueue_accepted,replay_queue_out_fire,liq_alloc_accepted,liq_base_lookup_granted,source_return_query_issued,source_return_response_apply_valid,source_row_mutation_request_valid,liq_row_mutation_write_enable,resolve_queue_push_accepted,resolve_queue_valid,mdb_conflict_store_valid,mdb_conflict_store_with_resolve_queue_valid,mdb_conflict_resolve_candidate,mdb_conflict_valid,mdb_fanout_record_valid,mdb_fanout_record_accepted,mdb_fanout_record_processed,mdb_fanout_bmdb_report,mdb_fanout_ssit_nonempty,mdb_fanout_lookup_valid,mdb_fanout_lookup_accepted,mdb_fanout_lookup_processed,mdb_fanout_lookup_table_hit,mdb_fanout_lu_out_valid,mdb_fanout_su_out_valid,mdb_fanout_lu_out_hit,mdb_fanout_su_out_hit,mdb_lookup_wait_plan_lookup_hit,mdb_lookup_wait_plan_wait_intent_valid,mdb_lookup_wait_plan_request_valid,mdb_lookup_wait_plan_bridge_valid,liq_row_mutation_selected_mdb_wait_plan,mdb_wait_plan_row_mutation_write_enable,liq_wait_store_mask_nonzero,liq_replay_wake_store_unit,liq_replay_wake_store_unit_full_match_active,liq_replay_wake_wait_store_clear" - -run_logged "constructed-replay-loop" \ - env \ - "FETCH_REPLAY_LIQ_REQUIRE_NONZERO=${REPLAY_NONZERO_COUNTERS}" \ - "FETCH_REPLAY_LIQ_REQUIRE_ZERO=mdb_fanout_su_wakeup_valid" \ - "LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS=1" \ - bash "${ROOT_DIR}/tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh" \ - --build-dir "${REPLAY_BUILD_DIR}" \ - --fixture replay-ldi-sdi-ldi-loop \ - --capture-rows "${REPLAY_CAPTURE_ROWS}" \ - --reduced-store-replay-liq \ - --disable-store-memory-mutation \ - --expect-load-pcs 0x10002,0x1000a,0x10002,0x1000a,0x10002,0x1000a \ - --expect-store-pcs 0x10006,0x10006,0x10006 \ - --max-seconds "${REPLAY_MAX_SECONDS}" - -python3 - \ - "${ROOT_DIR}" \ - "${BUILD_DIR}" \ - "${COREMARK_BUILD_DIR}" \ - "${REPLAY_BUILD_DIR}" \ - "${COREMARK_ELF}" \ - "${COREMARK_ROWS}" \ - "${REPLAY_CAPTURE_ROWS}" \ - "${ALLOW_NATURAL_COREMARK_REPLAY}" \ - "${RUN_FOCUSED}" <<'PY' -import json -import subprocess -import sys -from pathlib import Path - -root_dir = Path(sys.argv[1]) -build_dir = Path(sys.argv[2]) -coremark_dir = Path(sys.argv[3]) -replay_dir = Path(sys.argv[4]) -coremark_elf = sys.argv[5] -coremark_rows = int(sys.argv[6]) -replay_rows = int(sys.argv[7]) -allow_natural = sys.argv[8] == "1" -run_focused = sys.argv[9] == "1" - - -def load_json(path: Path) -> dict: - with path.open("r", encoding="utf-8") as f: - return json.load(f) - - -def git_sha(path: Path) -> str: - try: - return subprocess.check_output( - ["git", "-C", str(path), "rev-parse", "HEAD"], - text=True, - stderr=subprocess.DEVNULL, - ).strip() - except subprocess.CalledProcessError: - return "unknown" - - -def sideband_summary(path: Path) -> dict: - stats = load_json(path) - replay = stats.get("replay_liq", {}) - keys = [ - "cycles_sampled", - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "liq_base_lookup_granted", - "resolve_queue_push_accepted", - "mdb_conflict_valid", - "mdb_fanout_record_processed", - "mdb_fanout_lookup_table_hit", - "mdb_fanout_su_wakeup_valid", - "mdb_lookup_wait_plan_request_valid", - "liq_replay_wake_wait_store_clear", - ] - return {key: replay.get(key) for key in keys} - - -coremark_manifest = load_json(coremark_dir / "report" / "crosscheck_manifest.json") -replay_manifest = load_json(replay_dir / "report" / "crosscheck_manifest.json") -manifest = { - "schema": "linxcore.replay_liq_coremark_context_pack.v1", - "status": "pass", - "evidence_kind": "coremark_context_pack_plus_constructed_replay_liq", - "claim_boundary": ( - "CoreMark prefix is a reduced-store replay-LIQ no-regression gate; " - "the replay-LIQ/MDB positive path is forced by the constructed replay loop." - ), - "natural_coremark_replay_allowed": allow_natural, - "focused_specs_run": run_focused, - "coremark_prefix": { - "elf": coremark_elf, - "capture_rows": coremark_rows, - "manifest": str(coremark_dir / "report" / "crosscheck_manifest.json"), - "status": coremark_manifest.get("status"), - "summary": coremark_manifest.get("summary", {}), - "sideband": sideband_summary(coremark_dir / "report" / "frontend_fetch_rf_alu_sideband_stats.json"), - }, - "constructed_replay_loop": { - "fixture": "replay-ldi-sdi-ldi-loop", - "capture_rows": replay_rows, - "manifest": str(replay_dir / "report" / "crosscheck_manifest.json"), - "status": replay_manifest.get("status"), - "summary": replay_manifest.get("summary", {}), - "sideband": sideband_summary(replay_dir / "report" / "frontend_fetch_rf_alu_sideband_stats.json"), - }, - "git": { - "linxcore": git_sha(root_dir), - }, -} -out = build_dir / "report" / "replay_liq_coremark_context_pack.json" -out.parent.mkdir(parents=True, exist_ok=True) -with out.open("w", encoding="utf-8") as f: - json.dump(manifest, f, indent=2, sort_keys=True) - f.write("\n") -print(f"replay-liq-coremark-context-pack-report={out}") -PY diff --git a/tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh b/tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh deleted file mode 100755 index bc619fd7..00000000 --- a/tools/chisel/run_chisel_scalar_gpr_issue_wakeup_probe.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -TARGET_DIR="${ROOT_DIR}/generated/chisel-verilog/scalar-gpr-issue-wakeup-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/scalar-gpr-issue-wakeup-probe" -rm -rf "${TARGET_DIR}" "${BUILD_DIR}" -mkdir -p "${TARGET_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "runMain linxcore.execute.EmitScalarGPRIssueWakeupProbe --target-dir ${TARGET_DIR}" -) - -verilator --cc --exe --build --top-module ScalarGPRIssueWakeupProbe \ - -Mdir "${BUILD_DIR}" \ - -CFLAGS "-std=c++17 -O2" \ - "${TARGET_DIR}"/*.sv \ - "${ROOT_DIR}/tools/chisel/scalar_gpr_issue_wakeup_probe_tb.cpp" - -"${BUILD_DIR}/VScalarGPRIssueWakeupProbe" diff --git a/tools/chisel/run_chisel_scalar_issue_fabric_probe.sh b/tools/chisel/run_chisel_scalar_issue_fabric_probe.sh deleted file mode 100755 index eaafdcfb..00000000 --- a/tools/chisel/run_chisel_scalar_issue_fabric_probe.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -TARGET_DIR="${ROOT_DIR}/generated/chisel-verilog/scalar-issue-fabric-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/scalar-issue-fabric-probe" -rm -rf "${TARGET_DIR}" "${BUILD_DIR}" -mkdir -p "${TARGET_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "runMain linxcore.execute.ElaborateScalarIssueFabricProbe --target-dir ${TARGET_DIR}" -) - -verilator --cc --exe --build --top-module ScalarIssueFabricProbe \ - -Mdir "${BUILD_DIR}" \ - -CFLAGS "-std=c++17 -O2" \ - "${TARGET_DIR}"/*.sv \ - "${ROOT_DIR}/tools/chisel/scalar_issue_fabric_probe_tb.cpp" - -"${BUILD_DIR}/VScalarIssueFabricProbe" diff --git a/tools/chisel/run_chisel_scalar_l1d_probe.sh b/tools/chisel/run_chisel_scalar_l1d_probe.sh deleted file mode 100755 index eab90bfe..00000000 --- a/tools/chisel/run_chisel_scalar_l1d_probe.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -WORK_DIR="${ROOT_DIR}/build/chisel-scalar-l1d-probe" -RTL_DIR="${WORK_DIR}/rtl" -OBJ_DIR="${WORK_DIR}/obj" -rm -rf "${WORK_DIR}" -mkdir -p "${RTL_DIR}" "${OBJ_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors \ - "runMain linxcore.lsu.EmitScalarL1DProbe --target-dir ${RTL_DIR}" -) - -verilator --cc --exe --build --Mdir "${OBJ_DIR}" \ - --top-module ScalarL1DProbe \ - "${RTL_DIR}"/*.sv \ - "${ROOT_DIR}/tools/chisel/scalar_l1d_probe_tb.cpp" -"${OBJ_DIR}/VScalarL1DProbe" diff --git a/tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh b/tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh deleted file mode 100755 index 6fede921..00000000 --- a/tools/chisel/run_chisel_scalar_load_completion_rob_probe.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -TARGET_DIR="${ROOT_DIR}/generated/chisel-verilog/scalar-load-completion-rob-probe" -BUILD_DIR="${ROOT_DIR}/generated/chisel-verilator/scalar-load-completion-rob-probe" -rm -rf "${TARGET_DIR}" "${BUILD_DIR}" -mkdir -p "${TARGET_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "runMain linxcore.top.EmitScalarLoadCompletionROBProbe --target-dir ${TARGET_DIR}" -) - -verilator --cc --exe --build --top-module ScalarLoadCompletionROBProbe \ - -Mdir "${BUILD_DIR}" \ - -CFLAGS "-std=c++17 -O2" \ - "${TARGET_DIR}"/*.sv \ - "${ROOT_DIR}/tools/chisel/scalar_load_completion_rob_probe_tb.cpp" - -"${BUILD_DIR}/VScalarLoadCompletionROBProbe" diff --git a/tools/chisel/run_chisel_scalar_redirect_recovery_source_probe.sh b/tools/chisel/run_chisel_scalar_redirect_recovery_source_probe.sh deleted file mode 100755 index ae291645..00000000 --- a/tools/chisel/run_chisel_scalar_redirect_recovery_source_probe.sh +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/scalar-redirect-recovery-source-probe" -BUILD_DIR="${ROOT_DIR}/generated/scalar-redirect-recovery-source-probe" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - 'runMain linxcore.recovery.EmitScalarRedirectRecoverySourceProbe' -) - -mapfile_cmd=(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print) -if command -v mapfile >/dev/null 2>&1; then - mapfile -t sv_sources < <("${mapfile_cmd[@]}" | sort) -else - sv_sources=() - while IFS= read -r source; do - sv_sources+=("${source}") - done < <("${mapfile_cmd[@]}" | sort) -fi - -verilator --cc "${sv_sources[@]}" \ - --top-module ScalarRedirectRecoverySourceProbe \ - --exe "${ROOT_DIR}/tools/chisel/scalar_redirect_recovery_source_probe_tb.cpp" \ - --build --build-jobs 0 \ - -Mdir "${BUILD_DIR}/obj_dir" \ - -o scalar_redirect_recovery_source_probe_tb \ - -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/scalar_redirect_recovery_source_probe_tb" diff --git a/tools/chisel/run_chisel_store_non_flush_gate_probe.sh b/tools/chisel/run_chisel_store_non_flush_gate_probe.sh deleted file mode 100755 index 118eea2f..00000000 --- a/tools/chisel/run_chisel_store_non_flush_gate_probe.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)" -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/store-non-flush-gate-probe" -BUILD_DIR="${ROOT_DIR}/generated/store-non-flush-gate-probe" -rm -rf "${SV_DIR}" "${BUILD_DIR}" -mkdir -p "${SV_DIR}" "${BUILD_DIR}" - -( - cd "${ROOT_DIR}/chisel" - sbt --server --batch --no-colors --mem 4096 \ - "runMain linxcore.lsu.EmitReducedStoreNonFlushGateProbe --target-dir ${SV_DIR}" -) - -sv_sources=() -while IFS= read -r source; do - sv_sources+=("${source}") -done < <(find "${SV_DIR}" -maxdepth 1 -name '*.sv' -type f -print | sort) - -verilator --cc "${sv_sources[@]}" \ - --top-module ReducedStoreNonFlushGateProbe \ - --exe "${ROOT_DIR}/tools/chisel/reduced_store_non_flush_gate_probe_tb.cpp" \ - --build --build-jobs 0 \ - -Mdir "${BUILD_DIR}/obj_dir" \ - -o reduced_store_non_flush_gate_probe_tb \ - -CFLAGS '-std=c++17 -O2' - -"${BUILD_DIR}/obj_dir/reduced_store_non_flush_gate_probe_tb" diff --git a/tools/chisel/run_chisel_tests.sh b/tools/chisel/run_chisel_tests.sh index 320d55ff..2ecbf06e 100755 --- a/tools/chisel/run_chisel_tests.sh +++ b/tools/chisel/run_chisel_tests.sh @@ -3,19 +3,94 @@ set -euo pipefail ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" CHISEL_DIR="${ROOT_DIR}/chisel" -ONLY="" +ONLY=() ALL=false +TEST_NAME="" + +HEARTBEAT_SECONDS="${LINX_CHISEL_HEARTBEAT_SECONDS:-30}" +STALL_SECONDS="${LINX_CHISEL_STALL_SECONDS:-600}" +WALL_SECONDS="${LINX_CHISEL_WALL_SECONDS:-0}" +TEST_JOBS="${LINX_CHISEL_TEST_JOBS:-1}" +ARTIFACT_BUDGET_BYTES="${LINX_CHISEL_ARTIFACT_BUDGET_BYTES:-0}" +ARTIFACT_ROOT="${LINX_CHISEL_ARTIFACT_ROOT:-${CHISEL_DIR}/build}" +LOW_CPU_PERCENT="${LINX_CHISEL_LOW_CPU_PERCENT:-1.0}" + +require_value() { + local option="$1" + local value="${2:-}" + if [[ -z "${value}" ]]; then + echo "error: ${option} requires a value" >&2 + exit 2 + fi +} + +require_positive_integer() { + local name="$1" + local value="$2" + if [[ ! "${value}" =~ ^[1-9][0-9]*$ ]]; then + echo "error: ${name} must be a positive integer" >&2 + exit 2 + fi +} + +require_non_negative_integer() { + local name="$1" + local value="$2" + if [[ ! "${value}" =~ ^[0-9]+$ ]]; then + echo "error: ${name} must be a non-negative integer" >&2 + exit 2 + fi +} while [[ $# -gt 0 ]]; do case "$1" in --only) - ONLY="${2:-}" + require_value "$1" "${2:-}" + if [[ ! "${2}" =~ ^[A-Za-z0-9_.$]+$ ]]; then + echo "error: --only selector contains unsupported characters: ${2}" >&2 + exit 2 + fi + ONLY+=("${2}") shift 2 ;; --all) ALL=true shift ;; + --test-name) + require_value "$1" "${2:-}" + if [[ ! "${2}" =~ ^[A-Za-z0-9_.-]+$ ]]; then + echo "error: --test-name contains unsupported characters: ${2}" >&2 + exit 2 + fi + TEST_NAME="${2}" + shift 2 + ;; + --heartbeat-seconds) + require_value "$1" "${2:-}" + HEARTBEAT_SECONDS="${2}" + shift 2 + ;; + --stall-seconds) + require_value "$1" "${2:-}" + STALL_SECONDS="${2}" + shift 2 + ;; + --wall-seconds) + require_value "$1" "${2:-}" + WALL_SECONDS="${2}" + shift 2 + ;; + --jobs) + require_value "$1" "${2:-}" + TEST_JOBS="${2}" + shift 2 + ;; + --artifact-budget-bytes) + require_value "$1" "${2:-}" + ARTIFACT_BUDGET_BYTES="${2}" + shift 2 + ;; *) echo "error: unknown argument: $1" >&2 exit 2 @@ -23,13 +98,82 @@ while [[ $# -gt 0 ]]; do esac done +if [[ "${ALL}" == true && "${#ONLY[@]}" -ne 0 ]]; then + echo "error: --all and --only are mutually exclusive" >&2 + exit 2 +fi +if [[ -n "${TEST_NAME}" && ( "${ALL}" == true || "${#ONLY[@]}" -ne 1 ) ]]; then + echo "error: --test-name requires exactly one --only selector" >&2 + exit 2 +fi + +require_positive_integer "heartbeat seconds" "${HEARTBEAT_SECONDS}" +require_non_negative_integer "stall seconds" "${STALL_SECONDS}" +require_non_negative_integer "wall seconds" "${WALL_SECONDS}" +require_positive_integer "test jobs" "${TEST_JOBS}" +require_non_negative_integer "artifact budget bytes" "${ARTIFACT_BUDGET_BYTES}" + +export LINX_CHISEL_TEST_JOBS="${TEST_JOBS}" +# ROOT_DIR is resolved from this script at runtime. +# shellcheck disable=SC1091 source "${ROOT_DIR}/tools/chisel/chisel_env.sh" -cd "${CHISEL_DIR}" if [[ "${ALL}" == true ]]; then - sbt --server --batch --no-colors --mem "${LINX_CHISEL_SBT_MEM_MB}" "testOnly *" -elif [[ -n "${ONLY}" ]]; then - sbt --server --batch --no-colors --mem "${LINX_CHISEL_SBT_MEM_MB}" "testOnly *${ONLY}*" + TEST_COMMAND="testOnly *" + SELECTOR_SUMMARY="all" +elif [[ "${#ONLY[@]}" -ne 0 ]]; then + TEST_COMMAND="testOnly" + SELECTOR_SUMMARY="" + for selector in "${ONLY[@]}"; do + TEST_COMMAND+=" *${selector}*" + if [[ -n "${SELECTOR_SUMMARY}" ]]; then + SELECTOR_SUMMARY+="," + fi + SELECTOR_SUMMARY+="${selector}" + done + if [[ -n "${TEST_NAME}" ]]; then + TEST_COMMAND+=" -- -z ${TEST_NAME}" + SELECTOR_SUMMARY+=":${TEST_NAME}" + fi else - sbt --server --batch --no-colors --mem "${LINX_CHISEL_SBT_MEM_MB}" test + TEST_COMMAND="test" + SELECTOR_SUMMARY="default" fi + +SBT_COMMAND=( + sbt + --server + --batch + --no-colors + --mem + "${LINX_CHISEL_SBT_MEM_MB}" + "${TEST_COMMAND}" +) + +SUPERVISOR_COMMAND=( + python3 + "${ROOT_DIR}/tools/chisel/chisel_test_supervisor.py" + --selector + "${SELECTOR_SUMMARY}" + --jobs + "${TEST_JOBS}" + --heartbeat-seconds + "${HEARTBEAT_SECONDS}" + --stall-seconds + "${STALL_SECONDS}" + --wall-seconds + "${WALL_SECONDS}" + --low-cpu-percent + "${LOW_CPU_PERCENT}" + --artifact-root + "${ARTIFACT_ROOT}" + --artifact-budget-bytes + "${ARTIFACT_BUDGET_BYTES}" +) + +if [[ -n "${LINX_CHISEL_LOG_PATH:-}" ]]; then + SUPERVISOR_COMMAND+=(--log "${LINX_CHISEL_LOG_PATH}") +fi + +cd "${CHISEL_DIR}" +exec "${SUPERVISOR_COMMAND[@]}" -- "${SBT_COMMAND[@]}" diff --git a/tools/chisel/run_chisel_top_acrc_service_integration_probe.sh b/tools/chisel/run_chisel_top_acrc_service_integration_probe.sh deleted file mode 100755 index 86f487e1..00000000 --- a/tools/chisel/run_chisel_top_acrc_service_integration_probe.sh +++ /dev/null @@ -1,60 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -BUILD_DIR="${ROOT_DIR}/generated/r935-top-acrc-service-integration-probe" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/frontend-fetch-rf-alu-trace-top" -VERILATOR_BUILD_JOBS="${VERILATOR_BUILD_JOBS:-0}" - -while [[ $# -gt 0 ]]; do - case "$1" in - --build-dir) - BUILD_DIR="${2:-}" - shift 2 - ;; - *) - echo "error: unknown argument: $1" >&2 - exit 2 - ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi -OBJ_DIR="${BUILD_DIR}/obj_dir" -mkdir -p "${BUILD_DIR}" -rm -rf "${OBJ_DIR}" - -if ! command -v verilator >/dev/null 2>&1; then - echo "error: Verilator is required for the top ACRC service integration probe" >&2 - exit 2 -fi - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -( - cd "${ROOT_DIR}/chisel" - sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreFrontendFetchRfAluTraceTop" -) - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no SystemVerilog files emitted under ${SV_DIR}" >&2 - exit 2 -fi - -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreFrontendFetchRfAluTraceTop \ - --exe "${ROOT_DIR}/tools/chisel/top_acrc_service_integration_probe_tb.cpp" \ - --build \ - --build-jobs "${VERILATOR_BUILD_JOBS}" \ - -Mdir "${OBJ_DIR}" \ - -o top_acrc_service_integration_probe_tb \ - -CFLAGS "-std=c++17 -O2" - -"${OBJ_DIR}/top_acrc_service_integration_probe_tb" diff --git a/tools/chisel/run_chisel_top_xcheck.sh b/tools/chisel/run_chisel_top_xcheck.sh deleted file mode 100755 index 995a9603..00000000 --- a/tools/chisel/run_chisel_top_xcheck.sh +++ /dev/null @@ -1,58 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/top-xcheck" -TOP_SV="${SV_DIR}/LinxCoreTop.sv" -BUILD_DIR="${ROOT_DIR}/generated/chisel-top-xcheck" -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreTopXcheck" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: LinxCoreTop SystemVerilog was not emitted: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no LinxCoreTop SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreTop \ - --exe "${ROOT_DIR}/tools/chisel/reduced_rob_trace_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_top_trace_tb \ - -CFLAGS "-std=c++17 -O2 -DLINXCORE_COMMIT_TRACE_DUT_HEADER=\\\"VLinxCoreTop.h\\\" -DLINXCORE_COMMIT_TRACE_DUT_CLASS=VLinxCoreTop" - -"${OBJ_DIR}/linxcore_top_trace_tb" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits 3 \ - --mode failfast - -echo "top-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_trace_replay_xcheck.sh b/tools/chisel/run_chisel_trace_replay_xcheck.sh deleted file mode 100755 index ec523e4a..00000000 --- a/tools/chisel/run_chisel_trace_replay_xcheck.sh +++ /dev/null @@ -1,187 +0,0 @@ -#!/usr/bin/env bash -set -euo pipefail - -ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" -CHISEL_DIR="${ROOT_DIR}/chisel" -SV_DIR="${ROOT_DIR}/generated/chisel-verilog/top-xcheck" -TOP_SV="${SV_DIR}/LinxCoreTop.sv" -BUILD_DIR="${BUILD_DIR:-${ROOT_DIR}/generated/chisel-trace-replay-xcheck}" -RAW_INPUT_TRACE="" -MAX_COMMITS="4" -REPLAY_ROWS="" - -usage() { - cat <] [--max-commits ] [--replay-rows ] [--build-dir ] - -When --input-trace is omitted, this gate generates a small flat commit trace -fixture. Any provided input trace is normalized before the Verilator replay. ---max-commits bounds architectural comparison; --replay-rows bounds raw rows -driven through the replay harness before comparator metadata filtering. -USAGE -} - -while [[ $# -gt 0 ]]; do - case "$1" in - --input-trace) RAW_INPUT_TRACE="$2"; shift 2 ;; - --max-commits) MAX_COMMITS="$2"; shift 2 ;; - --replay-rows) REPLAY_ROWS="$2"; shift 2 ;; - --build-dir) BUILD_DIR="$2"; shift 2 ;; - -h|--help) usage; exit 0 ;; - *) echo "error: unknown argument: $1" >&2; usage; exit 2 ;; - esac -done - -if [[ "${BUILD_DIR}" != /* ]]; then - BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}" -fi - -if [[ -z "${REPLAY_ROWS}" ]]; then - REPLAY_ROWS="${MAX_COMMITS}" -fi - -OBJ_DIR="${BUILD_DIR}/obj_dir" -TRACE_DIR="${BUILD_DIR}/traces" -REPORT_DIR="${BUILD_DIR}/report" -INPUT_TRACE="${TRACE_DIR}/input.normalized.jsonl" -DUT_TRACE="${TRACE_DIR}/dut.chisel.jsonl" -QEMU_TRACE="${TRACE_DIR}/qemu.reference.jsonl" - -source "${ROOT_DIR}/tools/chisel/chisel_env.sh" - -mkdir -p "${TRACE_DIR}" "${REPORT_DIR}" - -if [[ -z "${RAW_INPUT_TRACE}" ]]; then - RAW_INPUT_TRACE="${TRACE_DIR}/input.fixture.jsonl" - python3 - "${RAW_INPUT_TRACE}" <<'PY' -import json -import sys -from pathlib import Path - -out = Path(sys.argv[1]) -rows = [ - { - "seq": 0, - "cycle": 20, - "pc": 0x1000, - "insn": 0x13, - "len": 4, - "bid": 9, - "gid": 0, - "rid": 0, - "block_bid": 0x300000090, - "wb_valid": 1, - "wb_rd": 5, - "wb_data": 0x44, - "next_pc": 0x1004, - }, - { - "seq": 1, - "cycle": 21, - "pc": 0x1004, - "insn": 0x23, - "len": 4, - "bid": 9, - "gid": 0, - "rid": 1, - "block_bid": 0x300000091, - "src0_valid": 1, - "src0_reg": 3, - "src0_data": 0x99, - "mem_valid": 1, - "mem_is_store": 1, - "mem_addr": 0x2000, - "mem_wdata": 0x99, - "mem_size": 8, - "next_pc": 0x1008, - }, - { - "seq": 2, - "cycle": 22, - "pc": 0x1008, - "insn": 0x3, - "len": 4, - "bid": 9, - "gid": 0, - "rid": 2, - "block_bid": 0x300000092, - "mem_valid": 1, - "mem_addr": 0x2000, - "mem_rdata": 0x99, - "mem_size": 8, - "wb_valid": 1, - "wb_rd": 6, - "wb_data": 0x99, - "next_pc": 0x100c, - }, - { - "seq": 3, - "cycle": 23, - "pc": 0x100c, - "insn": 0x6F, - "len": 4, - "bid": 9, - "gid": 0, - "rid": 3, - "block_bid": 0x300000093, - "trap_valid": 1, - "trap_cause": 0x45, - "traparg0": 0x100c, - "next_pc": 0x1010, - }, -] -with out.open("w", encoding="utf-8") as f: - for row in rows: - f.write(json.dumps(row, sort_keys=True, separators=(",", ":")) + "\n") -PY -fi - -python3 "${ROOT_DIR}/tools/chisel/trace_schema_adapter.py" \ - --input "${RAW_INPUT_TRACE}" \ - --output "${INPUT_TRACE}" \ - --max-rows "${REPLAY_ROWS}" - -cd "${CHISEL_DIR}" -sbt --batch --no-colors "runMain linxcore.top.EmitLinxCoreTopXcheck" - -if [[ ! -f "${TOP_SV}" ]]; then - echo "error: LinxCoreTop SystemVerilog was not emitted: ${TOP_SV}" >&2 - exit 2 -fi - -SV_FILES=() -while IFS= read -r sv_path; do - SV_FILES+=("${sv_path}") -done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) - -if [[ "${#SV_FILES[@]}" -eq 0 ]]; then - echo "error: no LinxCoreTop SystemVerilog files were emitted under ${SV_DIR}" >&2 - exit 2 -fi - -rm -rf "${OBJ_DIR}" -verilator \ - --cc "${SV_FILES[@]}" \ - --top-module LinxCoreTop \ - --exe "${ROOT_DIR}/tools/chisel/reduced_rob_trace_tb.cpp" \ - --build \ - -Mdir "${OBJ_DIR}" \ - -o linxcore_trace_replay_tb \ - -CFLAGS "-std=c++17 -O2 -DLINXCORE_COMMIT_TRACE_DUT_HEADER=\\\"VLinxCoreTop.h\\\" -DLINXCORE_COMMIT_TRACE_DUT_CLASS=VLinxCoreTop" - -"${OBJ_DIR}/linxcore_trace_replay_tb" \ - --input-trace "${INPUT_TRACE}" \ - --max-rows "${REPLAY_ROWS}" \ - --dut-trace "${DUT_TRACE}" \ - --qemu-trace "${QEMU_TRACE}" - -bash "${ROOT_DIR}/tools/chisel/run_chisel_qemu_crosscheck.sh" \ - --qemu-trace "${QEMU_TRACE}" \ - --dut-trace "${DUT_TRACE}" \ - --report-dir "${REPORT_DIR}" \ - --max-commits "${MAX_COMMITS}" \ - --normalize-rows "${REPLAY_ROWS}" \ - --mode failfast - -echo "trace-replay-xcheck-report=${REPORT_DIR}" diff --git a/tools/chisel/run_chisel_verilator_lint.sh b/tools/chisel/run_chisel_verilator_lint.sh index 6888aabd..f6fb3c6c 100755 --- a/tools/chisel/run_chisel_verilator_lint.sh +++ b/tools/chisel/run_chisel_verilator_lint.sh @@ -3,7 +3,7 @@ set -euo pipefail ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" SV_DIR="${ROOT_DIR}/generated/chisel-verilog" -TOP_SV="${SV_DIR}/LinxCoreTop.sv" +TOP_SV="${SV_DIR}/TOP.sv" if ! command -v verilator >/dev/null 2>&1; then echo "error: Verilator is required for Chisel RTL lint" >&2 @@ -17,8 +17,11 @@ if [[ ! -f "${TOP_SV}" ]]; then exit 2 fi +VERILATOR_SV="${SV_DIR}/CoreTOP.verilator.sv" +sed 's/^module TOP(/module CoreTOP(/' "${TOP_SV}" > "${VERILATOR_SV}" SV_FILES=() while IFS= read -r sv_path; do + [[ "${sv_path}" == "${TOP_SV}" ]] && continue SV_FILES+=("${sv_path}") done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) @@ -27,4 +30,5 @@ if [[ "${#SV_FILES[@]}" -eq 0 ]]; then exit 2 fi -verilator --lint-only --top-module LinxCoreTop "${SV_FILES[@]}" +verilator --lint-only --top-module CoreTOPHarness -Wno-PINMISSING \ + "${ROOT_DIR}/tools/chisel/top_verilator_harness.sv" "${SV_FILES[@]}" diff --git a/tools/chisel/run_dual_benchmark_gate.sh b/tools/chisel/run_dual_benchmark_gate.sh new file mode 100755 index 00000000..ea27a3e2 --- /dev/null +++ b/tools/chisel/run_dual_benchmark_gate.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" +BUILD_ROOT="${ROOT_DIR}/generated/top-mainline/dual" +COREMARK_ELF="${ROOT_DIR}/../../workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/coremark/coremark.elf" +DHRYSTONE_ELF="${ROOT_DIR}/../../workloads/generated/fishtoucher-c-workloads-ca3e11b-20260717-r1/benchmarks/dhrystone/dhrystone.elf" +MAX_CYCLES="3000000" + +while [[ $# -gt 0 ]]; do + case "$1" in + --build-root) BUILD_ROOT="${2:-}"; shift 2 ;; + --coremark-elf) COREMARK_ELF="${2:-}"; shift 2 ;; + --dhrystone-elf) DHRYSTONE_ELF="${2:-}"; shift 2 ;; + --max-cycles) MAX_CYCLES="${2:-}"; shift 2 ;; + *) echo "error: unknown argument: $1" >&2; exit 2 ;; + esac +done + +for benchmark in coremark dhrystone; do + if [[ "${benchmark}" == coremark ]]; then elf="${COREMARK_ELF}"; else elf="${DHRYSTONE_ELF}"; fi + bash "${ROOT_DIR}/tools/chisel/run_top_natural.sh" --elf "${elf}" \ + --build-dir "${BUILD_ROOT}/${benchmark}" --max-cycles "${MAX_CYCLES}" +done diff --git a/tools/chisel/run_interface_manifest.sh b/tools/chisel/run_interface_manifest.sh new file mode 100755 index 00000000..5f62489b --- /dev/null +++ b/tools/chisel/run_interface_manifest.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" +source "${ROOT_DIR}/tools/chisel/chisel_env.sh" + +cd "${ROOT_DIR}/chisel" +sbt --server --batch --no-colors --mem 4096 \ + "runMain linxcore.top.interface.EmitInterfaceManifest --json ${ROOT_DIR}/docs/chisel/generated/top-interface-manifest.json --markdown ${ROOT_DIR}/docs/chisel/generated/top-interface-manifest.md" diff --git a/tools/chisel/run_task15_warning_matrix.sh b/tools/chisel/run_task15_warning_matrix.sh new file mode 100755 index 00000000..d908580b --- /dev/null +++ b/tools/chisel/run_task15_warning_matrix.sh @@ -0,0 +1,23 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" +FIRTOOL_DIR="${LINX_TASK15_FIRTOOL_DIR:-/tmp/linxcore-firtool-arm64-1.154.0/firtool-1.154.0/bin}" +LOG="$(mktemp "${TMPDIR:-/tmp}/linxcore-task15-warning-matrix.XXXXXX.log")" +trap 'rm -f "${LOG}"' EXIT + +if [[ ! -x "${FIRTOOL_DIR}/firtool" ]]; then + echo "error: native arm64 firtool is missing: ${FIRTOOL_DIR}/firtool" >&2 + exit 2 +fi + +PATH="${FIRTOOL_DIR}:${PATH}" \ +LINX_CHISEL_TEST_JOBS=1 \ +LINX_CHISEL_ARTIFACT_BUDGET_BYTES=1073741824 \ +bash "${ROOT_DIR}/tools/chisel/run_chisel_tests.sh" \ + --jobs 1 \ + --wall-seconds 420 \ + --artifact-budget-bytes 1073741824 \ + --only Task15WarningMatrixSpec 2>&1 | tee "${LOG}" + +python3 "${ROOT_DIR}/tools/chisel/classify_task15_warning_matrix.py" "${LOG}" diff --git a/tools/chisel/run_top_natural.sh b/tools/chisel/run_top_natural.sh new file mode 100755 index 00000000..cb1a77c1 --- /dev/null +++ b/tools/chisel/run_top_natural.sh @@ -0,0 +1,242 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/../.." && pwd)" +CHISEL_DIR="${ROOT_DIR}/chisel" +TOP_MODULE="TOP" +EMIT_MAIN="linxcore.top.EmitTOP" +ELF="" +BUILD_DIR="${ROOT_DIR}/generated/top-natural" +MAX_CYCLES="20000" +HEARTBEAT_CYCLES="2000" +DEADLOCK_CYCLES="3000" +MANIFEST="" +SELF_TEST=0 +WIDTH="2" +RESET_SP="0x0000000007fefff0" +PORT_VALIDATION=0 +LINT=0 +COMMIT_TRACE="" +BUILD_JOBS="1" + +while [[ $# -gt 0 ]]; do + case "$1" in + --self-test) SELF_TEST=1; shift ;; + --manifest) MANIFEST="${2:-}"; shift 2 ;; + --elf) ELF="${2:-}"; shift 2 ;; + --build-dir) BUILD_DIR="${2:-}"; shift 2 ;; + --max-cycles) MAX_CYCLES="${2:-}"; shift 2 ;; + --heartbeat-cycles) HEARTBEAT_CYCLES="${2:-}"; shift 2 ;; + --deadlock-cycles) DEADLOCK_CYCLES="${2:-}"; shift 2 ;; + --width) WIDTH="${2:-}"; shift 2 ;; + --reset-sp) RESET_SP="${2:-}"; shift 2 ;; + --port-validation) PORT_VALIDATION=1; shift ;; + --lint) LINT=1; shift ;; + --commit-trace) COMMIT_TRACE="${2:-}"; shift 2 ;; + --build-jobs) BUILD_JOBS="${2:-}"; shift 2 ;; + --qemu|--qemu-trace|--expected-rows|--replay-rows|--result-hint) + echo "error: oracle/replay option is forbidden in natural mode: $1" >&2 + exit 2 + ;; + *) echo "error: unknown argument: $1" >&2; exit 2 ;; + esac +done + +if ! [[ "${BUILD_JOBS}" =~ ^[1-9][0-9]*$ ]]; then + echo "error: --build-jobs must be a positive integer" >&2 + exit 2 +fi + +write_contract_manifest() { + local output="$1" + mkdir -p "$(dirname -- "${output}")" + python3 - "${output}" "${BUILD_JOBS}" <<'PY' +import json +import sys +from pathlib import Path + +payload = { + "schema": 1, + "top": "TOP", + "task": 18, + "build_jobs": int(sys.argv[2]), + "harness_owns": ["elf", "memory", "uart", "finisher", "manifest"], + "instruction_oracle": False, + "commit_oracle": False, + "memory_size_encoding": { + "Bytes1": 0, "Bytes2": 1, "Bytes4": 2, "Bytes8": 3, + "Bytes16": 4, "Bytes32": 5, "Bytes64": 6, + }, +} +path = Path(sys.argv[1]) +temporary = path.with_suffix(path.suffix + ".tmp") +temporary.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8") +temporary.replace(path) +PY +} + +record_build_jobs() { + local output="$1" + python3 - "${output}" "${BUILD_JOBS}" <<'PY' +import json +import sys +from pathlib import Path + +path = Path(sys.argv[1]) +payload = json.loads(path.read_text(encoding="utf-8")) +payload["build_jobs"] = int(sys.argv[2]) +temporary = path.with_suffix(path.suffix + ".tmp") +temporary.write_text(json.dumps(payload, indent=2, sort_keys=True) + "\n", encoding="utf-8") +temporary.replace(path) +PY +} + +prepare_harness_manifest() { + local output="$1" + rm -f -- "${output}" "${output}.tmp" +} + +finalize_harness_status() { + local tb_status="$1" + local output="$2" + local record_status=0 + + if [[ -f "${output}" ]]; then + record_build_jobs "${output}" || record_status=$? + fi + if [[ "${tb_status}" -ne 0 ]]; then + return "${tb_status}" + fi + return "${record_status}" +} + +if [[ "${LINX_TOP_NATURAL_SOURCE_FUNCTIONS_ONLY:-0}" -eq 1 ]]; then + return 0 2>/dev/null || exit 0 +fi + +if [[ "${SELF_TEST}" -eq 1 ]]; then + if [[ -z "${MANIFEST}" ]]; then + echo "error: --manifest is required with --self-test" >&2 + exit 2 + fi + write_contract_manifest "${MANIFEST}" + python3 - "${MANIFEST}" <<'PY' +import json +import sys +from pathlib import Path + +payload = json.loads(Path(sys.argv[1]).read_text(encoding="utf-8")) +assert payload["top"] == "TOP" +assert payload["memory_size_encoding"]["Bytes64"] == 6 +assert payload["build_jobs"] > 0 +assert not payload["instruction_oracle"] +assert not payload["commit_oracle"] +PY + exit 0 +fi + +if [[ "${PORT_VALIDATION}" -eq 0 && ( -z "${ELF}" || ! -f "${ELF}" ) ]]; then + echo "error: --elf must name an existing ELF" >&2 + exit 2 +fi +if [[ "${BUILD_DIR}" != /* ]]; then BUILD_DIR="${ROOT_DIR}/${BUILD_DIR}"; fi +if [[ -z "${MANIFEST}" ]]; then MANIFEST="${BUILD_DIR}/report/natural_manifest.json"; fi + +MEMORY_HEX="${BUILD_DIR}/elf.load.mem" +SV_DIR="${BUILD_DIR}/sv" +OBJ_DIR="${BUILD_DIR}/obj_dir" +PROFILE_METADATA="${BUILD_DIR}/top-profile.env" +TOP_VPI_CONFIG="${ROOT_DIR}/tools/chisel/top_natural.vlt" +SYSTEM_ISSUE_LANES="" +RETIRE_WIDTH="" +mkdir -p "${SV_DIR}" "${BUILD_DIR}/report" +prepare_harness_manifest "${MANIFEST}" +if [[ "${PORT_VALIDATION}" -eq 1 ]]; then + printf '# linxcore.top.port-validation\n' > "${MEMORY_HEX}" + ELF_ENTRY="0x0" +else + python3 "${ROOT_DIR}/tools/chisel/frontend_fetch_elf_memory.py" \ + --elf "${ELF}" --output "${MEMORY_HEX}" + ELF_ENTRY="$(python3 - "${ELF}" <<'PY' +import struct +import sys +from pathlib import Path +print(hex(struct.unpack_from("<16sHHIQQQIHHHHHH", Path(sys.argv[1]).read_bytes(), 0)[4])) +PY +)" +fi + +source "${ROOT_DIR}/tools/chisel/chisel_env.sh" +( + cd "${CHISEL_DIR}" + LINX_TOP_WIDTH="${WIDTH}" LINX_TOP_RESET_PC="${ELF_ENTRY}" \ + LINX_TOP_PROFILE_METADATA="${PROFILE_METADATA}" \ + LINX_TOP_SIMULATION_PROFILE=1 \ + sbt --batch --no-colors "runMain ${EMIT_MAIN} --target-dir ${SV_DIR}" +) +if [[ ! -f "${SV_DIR}/${TOP_MODULE}.sv" ]]; then + echo "error: missing emitted ${SV_DIR}/${TOP_MODULE}.sv" >&2 + exit 2 +fi +VERILATOR_SV="${SV_DIR}/CoreTOP.verilator.sv" +sed 's/^module TOP(/module CoreTOP(/' "${SV_DIR}/${TOP_MODULE}.sv" > "${VERILATOR_SV}" +mkdir -p "${OBJ_DIR}" +find "${OBJ_DIR}" -mindepth 1 -delete +SV_FILES=() +while IFS= read -r source; do + [[ "${source}" == "${SV_DIR}/${TOP_MODULE}.sv" ]] && continue + SV_FILES+=("${source}") +done < <(find "${SV_DIR}" -maxdepth 1 -type f -name '*.sv' | sort) +verilator --cc "${ROOT_DIR}/tools/chisel/top_verilator_harness.sv" \ + "${TOP_VPI_CONFIG}" "${SV_FILES[@]}" \ + --top-module CoreTOPHarness -Wno-PINMISSING \ + --prefix VCoreTOP --vpi \ + --exe "${ROOT_DIR}/tools/chisel/top_natural_tb.cpp" --build \ + --build-jobs "${BUILD_JOBS}" \ + -Mdir "${OBJ_DIR}" -o top_natural_tb -CFLAGS "-std=c++17 -O2" +find "${OBJ_DIR}" -type f -name '*.gch' -delete + +TB_ARGS=(--memory-hex "${MEMORY_HEX}" --max-cycles "${MAX_CYCLES}" + --heartbeat-cycles "${HEARTBEAT_CYCLES}" + --deadlock-cycles "${DEADLOCK_CYCLES}" + --reset-sp "${RESET_SP}" --uart-output "${BUILD_DIR}/report/uart.txt" + --manifest "${MANIFEST}") +while IFS='=' read -r key value; do + case "${key}" in + stidCount) TB_ARGS+=(--stid-count "${value}") ;; + gprArchRegs) TB_ARGS+=(--gpr-arch-regs "${value}") ;; + spAtag) TB_ARGS+=(--sp-atag "${value}") ;; + traceWidth) TB_ARGS+=(--trace-width "${value}") ;; + retireWidth) RETIRE_WIDTH="${value}" ;; + systemIssueLanes) SYSTEM_ISSUE_LANES="${value}" ;; + loadLanes) LOAD_LANES="${value}" ;; + storeLanes) STORE_LANES="${value}" ;; + esac +done < "${PROFILE_METADATA}" +if [[ -z "${SYSTEM_ISSUE_LANES}" ]]; then + echo "error: missing systemIssueLanes in TOP profile metadata" >&2 + exit 2 +fi +if [[ -z "${RETIRE_WIDTH}" ]]; then + echo "error: missing retireWidth in TOP profile metadata" >&2 + exit 2 +fi +TB_ARGS+=(--data-lanes "$((LOAD_LANES + STORE_LANES))") +TB_ARGS+=(--system-issue-lanes "${SYSTEM_ISSUE_LANES}") +TB_ARGS+=(--retire-width "${RETIRE_WIDTH}") +if [[ -n "${COMMIT_TRACE}" ]]; then + TB_ARGS+=(--commit-trace "${COMMIT_TRACE}") +fi +if [[ "${PORT_VALIDATION}" -eq 1 ]]; then TB_ARGS+=(--validate-ports); fi +set +e +"${OBJ_DIR}/top_natural_tb" "${TB_ARGS[@]}" +TB_STATUS=$? +set -e +FINAL_STATUS=0 +finalize_harness_status "${TB_STATUS}" "${MANIFEST}" || FINAL_STATUS=$? +if [[ "${FINAL_STATUS}" -ne 0 ]]; then exit "${FINAL_STATUS}"; fi +if [[ "${LINT}" -eq 1 ]]; then + verilator --lint-only --top-module CoreTOPHarness -Wno-PINMISSING \ + "${ROOT_DIR}/tools/chisel/top_verilator_harness.sv" \ + "${TOP_VPI_CONFIG}" "${SV_FILES[@]}" +fi diff --git a/tools/chisel/scalar_gpr_issue_wakeup_probe_tb.cpp b/tools/chisel/scalar_gpr_issue_wakeup_probe_tb.cpp deleted file mode 100644 index 07068a93..00000000 --- a/tools/chisel/scalar_gpr_issue_wakeup_probe_tb.cpp +++ /dev/null @@ -1,96 +0,0 @@ -#include -#include - -#include "VScalarGPRIssueWakeupProbe.h" -#include "verilated.h" - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "scalar-gpr-issue-wakeup-probe: " << message << '\n'; - std::exit(1); - } -} - -static void eval(VScalarGPRIssueWakeupProbe &dut) { - dut.eval(); - require(!dut.io_protocolError, "GPR protocol error asserted"); -} - -static void tick(VScalarGPRIssueWakeupProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -static void idle(VScalarGPRIssueWakeupProbe &dut) { - dut.io_enqueueValid = 0; - dut.io_sourceTag = 40; - dut.io_writeRequest = 0; - dut.io_writeCommit = 0; - dut.io_writeTag = 40; - dut.io_writeData = 0; - dut.io_issueReady = 1; -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VScalarGPRIssueWakeupProbe dut; - - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - - idle(dut); - dut.io_enqueueValid = 1; - eval(dut); - require(dut.io_enqueueReady, "issue queue did not accept dependent row"); - tick(dut); - - idle(dut); - eval(dut); - require(!dut.io_sourceReady && !dut.io_selectedValid && !dut.io_pickFire, - "not-ready physical source became selectable before writeback"); - - dut.io_writeRequest = 1; - dut.io_writeCommit = 0; - dut.io_writeData = 0x12345678ULL; - eval(dut); - require(dut.io_writeReady && !dut.io_writeFire && !dut.io_wakeupMatched && - !dut.io_selectedValid, - "request-only write published readiness or issue wakeup"); - tick(dut); - - idle(dut); - dut.io_writeRequest = 1; - dut.io_writeCommit = 1; - dut.io_writeData = 0x12345678ULL; - eval(dut); - require(dut.io_writeFire && dut.io_wakeupMatched && - dut.io_wakeupMatchCount == 1 && !dut.io_selectedValid, - "committed P write did not match exactly one resident source"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_sourceReady && dut.io_selectedValid && dut.io_pickFire && - ((dut.io_readyMask >> 40) & 1ULL), - "committed P wakeup was not pick-visible on the next cycle"); - tick(dut); - - idle(dut); - eval(dut); - require(!dut.io_issueValid, "issue became valid before the RF read stage advanced"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_issueValid && dut.io_issueFire && - dut.io_issueData == 0x12345678ULL, - "woken issue row did not read committed physical GPR data"); - - std::cout << "scalar-gpr-issue-wakeup-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/scalar_issue_fabric_probe_tb.cpp b/tools/chisel/scalar_issue_fabric_probe_tb.cpp deleted file mode 100644 index 6badc33d..00000000 --- a/tools/chisel/scalar_issue_fabric_probe_tb.cpp +++ /dev/null @@ -1,331 +0,0 @@ -#include -#include - -#include "VScalarIssueFabricProbe.h" -#include "verilated.h" - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "scalar-issue-fabric-probe: " << message << '\n'; - std::exit(1); - } -} - -static void eval(VScalarIssueFabricProbe &dut) { - dut.eval(); - require(!dut.io_protocolError, "fabric protocol error asserted"); -} - -static void tick(VScalarIssueFabricProbe &dut) { - dut.clock = 0; - eval(dut); - dut.clock = 1; - eval(dut); -} - -static void idle(VScalarIssueFabricProbe &dut) { - dut.io_enqueueValid = 0; - dut.io_enqueueStid = 0; - dut.io_enqueueRid = 0; - dut.io_enqueuePc = 0; - dut.io_enqueueBru = 0; - dut.io_enqueueStore = 0; - dut.io_sourceTag = 40; - dut.io_wakeupValid = 0; - dut.io_issueReady = 0; - dut.io_flush = 0; - dut.io_releaseValid = 0; - dut.io_releaseStid = 0; - dut.io_releaseRid = 0; - dut.io_policyValidMask = 0; - dut.io_policyStid_0 = 0; - dut.io_policyStid_1 = 0; - dut.io_policyRid_0 = 0; - dut.io_policyRid_1 = 0; - dut.io_policyAdvance = 0; -} - -static void enqueue(VScalarIssueFabricProbe &dut, unsigned stid, unsigned rid, unsigned pc, - bool bru = false, bool store = false, unsigned source_tag = 40) { - idle(dut); - dut.io_enqueueValid = 1; - dut.io_enqueueStid = stid; - dut.io_enqueueRid = rid; - dut.io_enqueuePc = pc; - dut.io_enqueueBru = bru; - dut.io_enqueueStore = store; - dut.io_sourceTag = source_tag; - eval(dut); - require(dut.io_enqueueReady, "fabric did not accept an enqueue"); - tick(dut); -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VScalarIssueFabricProbe dut; - - dut.reset = 1; - idle(dut); - tick(dut); - tick(dut); - dut.reset = 0; - - idle(dut); - dut.io_policyValidMask = 3; - dut.io_policyStid_0 = 0; - dut.io_policyStid_1 = 0; - dut.io_policyRid_0 = 5; - dut.io_policyRid_1 = 2; - eval(dut); - require(dut.io_policyGrantMask == 2 && dut.io_policySelectedIndex == 1, - "same-STID arbitration did not choose the older RID"); - - dut.io_policyAdvance = 1; - tick(dut); - idle(dut); - dut.io_policyValidMask = 3; - dut.io_policyStid_0 = 0; - dut.io_policyStid_1 = 1; - dut.io_policyRid_0 = 7; - dut.io_policyRid_1 = 0; - eval(dut); - require(dut.io_policyGrantMask == 1, - "cross-STID arbitration compared unrelated RID ages"); - dut.io_policyAdvance = 1; - tick(dut); - idle(dut); - dut.io_policyValidMask = 3; - dut.io_policyStid_0 = 0; - dut.io_policyStid_1 = 1; - dut.io_policyRid_0 = 7; - dut.io_policyRid_1 = 0; - eval(dut); - require(dut.io_policyGrantMask == 2, - "cross-STID arbitration did not rotate fairly"); - - enqueue(dut, 0, 1, 0x100); - idle(dut); - eval(dut); - require(dut.io_enqueueBank == 1, - "least-occupied routing did not spill the second row to bank 1"); - enqueue(dut, 0, 2, 0x104); - - idle(dut); - eval(dut); - require(dut.io_count == 2 && dut.io_bankOccupancy_0 == 1 && - dut.io_bankOccupancy_1 == 1 && dut.io_bankPickMask == 0, - "blocked rows were not retained one per bank"); - - dut.io_wakeupValid = 1; - eval(dut); - require(dut.io_bankPickMask == 0, - "same-cycle wakeup incorrectly affected bank pick"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankPickMask == 3 && dut.io_simultaneousPick, - "wakeup did not expose simultaneous bank-local picks at N+1"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankReadAttemptMask == 3 && dut.io_readContention && - dut.io_readArbitrationLoss && dut.io_bankReadGrantMask == 1 && - dut.io_cancelFire, - "global I1 arbitration did not grant older bank and cancel loser"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankIssueValidMask == 1 && dut.io_bankPickMask == 2, - "denied row was not retained for retry while winner reached I2"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankReadAttemptMask == 2 && dut.io_bankReadGrantMask == 2, - "cancelled row did not retry and win a later I1 grant"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankIssueValidMask == 3 && dut.io_issueContention && - dut.io_bankIssueGrantMask == 1 && !dut.io_issueFire, - "two resident I2 rows did not arbitrate oldest-first under backpressure"); - - dut.io_issueReady = 1; - eval(dut); - require(dut.io_issueFire && dut.io_issueRid == 1 && dut.io_issueData == 0x128, - "older bank did not issue first with captured RF data"); - tick(dut); - - idle(dut); - dut.io_issueReady = 1; - eval(dut); - require(dut.io_issueFire && dut.io_issueRid == 2 && dut.io_issueData == 0x128, - "retried bank did not issue after the older row"); - tick(dut); - - idle(dut); - dut.io_flush = 1; - tick(dut); - enqueue(dut, 0, 3, 0x200, true); - enqueue(dut, 0, 4, 0x204); - idle(dut); - dut.io_wakeupValid = 1; - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_controlFenceActive && dut.io_bankPickMask == 3, - "resident BRU did not establish a control frontier before bank picks"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_controlFenceBlocked && dut.io_bankControlBlockedMask == 2 && - dut.io_bankReadGrantMask == 1 && dut.io_cancelFire, - "younger same-STID row crossed the unresolved control frontier"); - tick(dut); - - idle(dut); - dut.io_issueReady = 1; - eval(dut); - require(dut.io_issueFire && dut.io_issueRid == 3, - "control row did not issue ahead of its younger same-STID row"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_controlFenceActive && dut.io_controlFenceBlocked && - dut.io_bankReadGrantMask == 0, - "issued control row stopped fencing before exact release"); - - dut.io_releaseValid = 1; - dut.io_releaseStid = 0; - dut.io_releaseRid = 3; - tick(dut); - - idle(dut); - eval(dut); - require(!dut.io_controlFenceActive && !dut.io_controlFenceBlocked, - "exact control release did not remove the frontier"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankReadGrantMask == 2, - "younger same-STID row did not retry after control release"); - - idle(dut); - dut.io_flush = 1; - tick(dut); - enqueue(dut, 0, 5, 0x300, true); - enqueue(dut, 1, 0, 0x304); - idle(dut); - dut.io_wakeupValid = 1; - tick(dut); - idle(dut); - tick(dut); - idle(dut); - eval(dut); - require(dut.io_controlFenceActive && dut.io_bankControlBlockedMask == 0 && - dut.io_bankReadGrantMask != 0, - "one STID's control frontier blocked unrelated STID progress"); - - idle(dut); - dut.io_flush = 1; - tick(dut); - enqueue(dut, 0, 1, 0x400, false, true); - enqueue(dut, 0, 2, 0x404, false, true); - idle(dut); - dut.io_wakeupValid = 1; - tick(dut); - idle(dut); - tick(dut); - idle(dut); - eval(dut); - require(dut.io_storeOrderBlocked && dut.io_bankStoreOrderBlockedMask == 2 && - dut.io_bankReadGrantMask == 1, - "younger same-STID store crossed the oldest resident store frontier"); - tick(dut); - idle(dut); - dut.io_issueReady = 1; - tick(dut); - idle(dut); - dut.io_releaseValid = 1; - dut.io_releaseRid = 1; - tick(dut); - idle(dut); - tick(dut); - idle(dut); - eval(dut); - require(!dut.io_storeOrderBlocked && dut.io_bankReadGrantMask == 2, - "younger store did not retry after exact older-store release"); - - idle(dut); - dut.io_flush = 1; - tick(dut); - enqueue(dut, 0, 1, 0x500, true, false, 40); - enqueue(dut, 0, 2, 0x504, true, false, 41); - enqueue(dut, 0, 6, 0x508, false, false, 42); - enqueue(dut, 0, 7, 0x50c, false, false, 43); - idle(dut); - eval(dut); - require(dut.io_bankOccupancy_0 == 2 && dut.io_bankOccupancy_1 == 2, - "compaction regression did not create two resident rows per bank"); - - dut.io_sourceTag = 40; - dut.io_wakeupValid = 1; - tick(dut); - idle(dut); - eval(dut); - require(dut.io_bankPickMask == 1, - "bank A older control row was not the unique first pick"); - tick(dut); - idle(dut); - eval(dut); - require(dut.io_bankReadAttemptMask == 1 && dut.io_bankReadGrantMask == 1, - "bank A older control row did not reach I1 alone"); - tick(dut); - idle(dut); - dut.io_issueReady = 1; - eval(dut); - require(dut.io_issueFire && dut.io_issueRid == 1, - "bank A older control row did not become issued-resident"); - tick(dut); - - idle(dut); - dut.io_sourceTag = 42; - dut.io_wakeupValid = 1; - tick(dut); - idle(dut); - dut.io_releaseValid = 1; - dut.io_releaseStid = 0; - dut.io_releaseRid = 1; - eval(dut); - require(dut.io_bankPickMask == 1 && dut.io_bankOccupancy_0 == 2, - "bank A slot-1 target was not picked with slot-0 release"); - tick(dut); - - idle(dut); - dut.io_releaseValid = 1; - dut.io_releaseStid = 0; - dut.io_releaseRid = 5; - eval(dut); - require(dut.io_bankOccupancy_0 == 1 && dut.io_bankOccupancy_1 == 2 && - dut.io_controlFenceActive && dut.io_bankReadAttemptMask == 1 && - dut.io_bankControlBlockedMask == 1 && - dut.io_bankReadGrantMask == 0 && dut.io_cancelFire, - "compacted target was not cancelled by the older bank-B control frontier"); - tick(dut); - - idle(dut); - eval(dut); - require(dut.io_bankOccupancy_0 == 1 && dut.io_bankPickMask == 1, - "cancelled compacted target identity did not become selectable for retry"); - - std::cout << "scalar-issue-fabric-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/scalar_l1d_probe_tb.cpp b/tools/chisel/scalar_l1d_probe_tb.cpp deleted file mode 100644 index 29304a87..00000000 --- a/tools/chisel/scalar_l1d_probe_tb.cpp +++ /dev/null @@ -1,142 +0,0 @@ -#include -#include - -#include "VScalarL1DProbe.h" -#include "verilated.h" - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "scalar-l1d-probe: " << message << '\n'; - std::exit(1); - } -} - -static void tick(VScalarL1DProbe &dut) { - dut.clock = 0; - dut.eval(); - require(!dut.io_protocolError, "protocol error asserted"); - dut.clock = 1; - dut.eval(); -} - -static void idle(VScalarL1DProbe &dut) { - dut.io_hardFlush = 0; - dut.io_preciseFlush = 0; - dut.io_loadValid = 0; - dut.io_loadLineAddr = 0; - dut.io_refillValid = 0; - dut.io_refillLineAddr = 0; - dut.io_refillData = 0; - dut.io_refillWritable = 0; - dut.io_evictionReady = 0; - dut.io_storeLookupValid = 0; - dut.io_storeLineAddr = 0; - dut.io_storeUpdateValid = 0; - dut.io_grantWriteValid = 0; - dut.io_storeByteMask = 0; - for (unsigned word = 0; word < 16; ++word) dut.io_storeData[word] = 0; -} - -static void refill(VScalarL1DProbe &dut, uint64_t addr, uint64_t data, - bool writable) { - idle(dut); - dut.io_refillValid = 1; - dut.io_refillLineAddr = addr; - dut.io_refillData = data; - dut.io_refillWritable = writable; - dut.eval(); - require(dut.io_refillReady && dut.io_refillAccepted, - "refill was not accepted"); - tick(dut); -} - -static void require_hit(VScalarL1DProbe &dut, uint64_t addr, uint64_t data) { - idle(dut); - dut.io_loadValid = 1; - dut.io_loadLineAddr = addr; - dut.eval(); - require(dut.io_loadHit && dut.io_loadData == data, "load hit/data mismatch"); - tick(dut); -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VScalarL1DProbe dut; - idle(dut); - dut.reset = 1; - tick(dut); - tick(dut); - dut.reset = 0; - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadLineAddr = 0; - dut.eval(); - require(!dut.io_loadHit, "empty cache reported a hit"); - - refill(dut, 0, 0x1111111111111111ULL, false); - require_hit(dut, 0, 0x1111111111111111ULL); - - idle(dut); - dut.io_refillValid = 1; - dut.io_refillLineAddr = 0; - dut.io_refillData = 0x2222222222222222ULL; - dut.io_refillWritable = 0; - dut.eval(); - require(dut.io_refillAccepted && dut.io_refillDuplicate && - dut.io_refillReturnData == 0x1111111111111111ULL, - "duplicate refill overwrote resident data"); - tick(dut); - - idle(dut); - dut.io_storeLookupValid = 1; - dut.io_storeLineAddr = 0; - dut.eval(); - require(dut.io_storeTagHit && !dut.io_storeWriteHit, - "read-only line did not request an ownership upgrade"); - dut.io_grantWriteValid = 1; - tick(dut); - idle(dut); - dut.io_storeLookupValid = 1; - dut.io_storeLineAddr = 0; - dut.eval(); - require(dut.io_storeTagHit && dut.io_storeWriteHit, - "accepted ownership upgrade did not grant write permission"); - dut.io_storeUpdateValid = 1; - dut.io_storeByteMask = 1; - dut.io_storeData[0] = 0xaa; - tick(dut); - require_hit(dut, 0, 0x11111111111111aaULL); - require(dut.io_dirtyCount == 1, "store update did not mark the line dirty"); - - refill(dut, 128, 0x3333333333333333ULL, false); - idle(dut); - dut.io_refillValid = 1; - dut.io_refillLineAddr = 256; - dut.io_refillData = 0x4444444444444444ULL; - dut.io_evictionReady = 0; - dut.eval(); - require(dut.io_evictionValid && dut.io_evictionDirty && - dut.io_evictionLineAddr == 0 && - dut.io_evictionData == 0x11111111111111aaULL && - !dut.io_refillReady && !dut.io_refillAccepted, - "dirty victim was not retained under eviction backpressure"); - dut.io_evictionReady = 1; - dut.eval(); - require(dut.io_refillReady && dut.io_refillAccepted, - "refill did not proceed with accepted eviction"); - tick(dut); - require_hit(dut, 256, 0x4444444444444444ULL); - - idle(dut); - dut.io_hardFlush = 1; - tick(dut); - require_hit(dut, 256, 0x4444444444444444ULL); - idle(dut); - dut.io_preciseFlush = 1; - tick(dut); - require_hit(dut, 256, 0x4444444444444444ULL); - - std::cout << "scalar-l1d-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/scalar_load_completion_rob_probe_tb.cpp b/tools/chisel/scalar_load_completion_rob_probe_tb.cpp deleted file mode 100644 index 831a6f83..00000000 --- a/tools/chisel/scalar_load_completion_rob_probe_tb.cpp +++ /dev/null @@ -1,374 +0,0 @@ -#include -#include - -#include "VScalarLoadCompletionROBProbe.h" -#include "verilated.h" - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "scalar-load-completion-rob-probe: " << message << '\n'; - std::exit(1); - } -} - -static void tick(VScalarLoadCompletionROBProbe &dut) { - dut.clock = 0; - dut.eval(); - require(!dut.io_protocolError, "protocol error asserted"); - dut.clock = 1; - dut.eval(); -} - -static void idle(VScalarLoadCompletionROBProbe &dut) { - dut.io_allocValid = 0; - dut.io_externalCompleteValid = 0; - dut.io_loadValid = 0; - dut.io_loadRidValid = 0; - dut.io_loadRidWrap = 0; - dut.io_loadRidValue = 0; - dut.io_loadResolveEnable = 1; - dut.io_loadWritebackEnable = 1; - dut.io_loadWakeupEnable = 1; - dut.io_loadDstValid = 0; - dut.io_loadDstKind = 0; - dut.io_loadDstTag = 0; - dut.io_loadData = 0; - dut.io_loadSpecWakeup = 0; - dut.io_loadStackValid = 0; - dut.io_gprClearValid = 0; - dut.io_gprClearTag = 0; - dut.io_externalGprWriteValid = 0; - dut.io_externalGprWriteTag = 0; - dut.io_externalGprWriteData = 0; - dut.io_gprReadTag = 0; - dut.io_singlePortMode = 0; -} - -static unsigned allocate(VScalarLoadCompletionROBProbe &dut, unsigned tag, - unsigned &wrap) { - idle(dut); - dut.io_allocValid = 1; - dut.io_allocTag = tag; - dut.eval(); - require(dut.io_allocReady, "ROB allocation was not ready"); - const unsigned value = dut.io_allocRobValue; - wrap = dut.io_allocRobWrap; - tick(dut); - return value; -} - -static void external_complete_and_retire(VScalarLoadCompletionROBProbe &dut, - unsigned value) { - idle(dut); - dut.io_externalCompleteValid = 1; - dut.io_externalCompleteRobValue = value; - tick(dut); - idle(dut); - dut.eval(); - require(dut.io_commitValid && dut.io_commitRobValue == value, - "externally completed row did not become committable"); - tick(dut); -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VScalarLoadCompletionROBProbe dut; - - dut.reset = 1; - idle(dut); - dut.io_allocTag = 0; - dut.io_externalCompleteRobValue = 0; - dut.io_loadDstValid = 0; - dut.io_loadDstKind = 0; - dut.io_loadDstTag = 0; - dut.io_loadData = 0; - dut.io_loadSpecWakeup = 0; - dut.io_loadStackValid = 0; - dut.io_loadWritebackEnable = 1; - dut.io_loadWakeupEnable = 1; - dut.io_gprClearValid = 0; - dut.io_gprClearTag = 0; - dut.io_externalGprWriteValid = 0; - dut.io_externalGprWriteTag = 0; - dut.io_externalGprWriteData = 0; - dut.io_gprReadTag = 0; - dut.io_singlePortMode = 0; - tick(dut); - tick(dut); - dut.reset = 0; - - unsigned wrap0 = 0; - unsigned wrap1 = 0; - const unsigned row0 = allocate(dut, 1, wrap0); - const unsigned row1 = allocate(dut, 2, wrap1); - require(row0 == 0 && row1 == 1 && wrap0 == 0 && wrap1 == 0 && dut.io_size == 2, - "ROB allocation order is incorrect"); - - idle(dut); - dut.io_externalCompleteValid = 1; - dut.io_externalCompleteRobValue = row0; - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidValue = row1; - dut.eval(); - require(dut.io_lookupRowValid && dut.io_collision && - !dut.io_loadResolveReady && !dut.io_scalarLoadSelected, - "external completion did not hold the colliding scalar load"); - tick(dut); - - idle(dut); - dut.eval(); - require(dut.io_commitValid && dut.io_commitRobValue == row0, - "externally completed head row did not become committable"); - tick(dut); - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidValue = row1; - dut.eval(); - require(dut.io_lookupRowValid && dut.io_loadResolveReady && - dut.io_scalarLoadSelected && !dut.io_collision, - "held scalar load did not complete the exact live ROB row"); - tick(dut); - - idle(dut); - dut.eval(); - require(dut.io_commitValid && dut.io_commitRobValue == row1, - "scalar-load-completed row did not become committable"); - tick(dut); - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidValue = row1; - dut.eval(); - require(!dut.io_lookupRowValid && dut.io_lookupBlockedByFree && - !dut.io_scalarLoadSelected, - "retired ROB identity was accepted as a live scalar load"); - require(dut.io_size == 0, "ROB did not return to empty"); - - for (unsigned tag = 3; tag <= 8; ++tag) { - unsigned wrap = 1; - const unsigned value = allocate(dut, tag, wrap); - require(value == tag - 1 && wrap == 0, - "ROB did not advance through the pre-wrap slots"); - external_complete_and_retire(dut, value); - } - - unsigned wrapped = 0; - const unsigned wrappedRow = allocate(dut, 9, wrapped); - require(wrappedRow == 0 && wrapped == 1, - "ROB allocation did not expose the wrapped RID generation"); - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = 0; - dut.io_loadRidValue = wrappedRow; - dut.eval(); - require(!dut.io_lookupRowValid && dut.io_lookupBlockedByStaleRid && - !dut.io_loadResolveReady && !dut.io_scalarLoadSelected, - "stale pre-wrap RID was allowed to complete a reused ROB slot"); - - external_complete_and_retire(dut, wrappedRow); - - unsigned wrapped1 = 0; - const unsigned exactRow = allocate(dut, 10, wrapped1); - require(exactRow == 1 && wrapped1 == 1, - "post-wrap exact-completion row identity is incorrect"); - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = 1; - dut.io_loadRidValue = exactRow; - dut.eval(); - require(dut.io_lookupRowValid && dut.io_loadResolveReady && - dut.io_scalarLoadSelected, - "exact wrapped RID did not reach the scalar completion port"); - tick(dut); - idle(dut); - dut.eval(); - require(dut.io_commitValid && dut.io_commitRobValue == exactRow, - "exact wrapped scalar completion did not become committable"); - tick(dut); - require(dut.io_size == 0, "ROB did not drain after wrapped exact completion"); - - unsigned gprWrap = 0; - const unsigned gprRow = allocate(dut, 11, gprWrap); - require(gprRow == 2 && gprWrap == 1, - "GPR completion row identity is incorrect"); - idle(dut); - dut.io_gprClearValid = 1; - dut.io_gprClearTag = 40; - tick(dut); - - for (unsigned blockedSink = 0; blockedSink < 3; ++blockedSink) { - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = gprWrap; - dut.io_loadRidValue = gprRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 40; - dut.io_loadData = 0xbb; - dut.io_loadResolveEnable = blockedSink != 0; - dut.io_loadWritebackEnable = blockedSink != 1; - dut.io_loadWakeupEnable = blockedSink != 2; - dut.eval(); - require(dut.io_lookupRowValid && !dut.io_loadResolveReady && - !dut.io_scalarLoadSelected && !dut.io_loadWritebackSelected && - !dut.io_loadWakeupPublished, - "public completion allow did not hold resident scalar W2"); - tick(dut); - idle(dut); - dut.io_gprReadTag = 40; - dut.eval(); - require(!dut.io_gprReadReady && dut.io_size == 1, - "blocked public completion allow mutated GPR or ROB state"); - } - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = gprWrap; - dut.io_loadRidValue = gprRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 40; - dut.io_loadData = 0xbb; - dut.io_externalGprWriteValid = 1; - dut.io_externalGprWriteTag = 40; - dut.io_externalGprWriteData = 0xaa; - dut.eval(); - require(dut.io_lookupRowValid && !dut.io_loadResolveReady && - !dut.io_scalarLoadSelected && dut.io_loadBlockedByExternalWrite && - dut.io_externalGprWriteFire, - "same-tag external write did not hold scalar W2 before all side effects"); - tick(dut); - - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = gprWrap; - dut.io_loadRidValue = gprRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 40; - dut.io_loadData = 0xbb; - dut.eval(); - require(dut.io_loadResolveReady && dut.io_scalarLoadSelected && - dut.io_loadWritebackSelected && dut.io_loadWakeupPublished, - "scalar W2 did not atomically resolve, write back, and wake up"); - tick(dut); - idle(dut); - dut.io_gprReadTag = 40; - dut.eval(); - require(dut.io_gprReadReady && dut.io_gprReadData == 0xbb, - "scalar W2 data and ready-table state did not commit together"); - require(dut.io_commitValid && dut.io_commitRobValue == gprRow, - "GPR-completed scalar row did not become committable"); - tick(dut); - - unsigned dualWrap = 0; - const unsigned dualRow = allocate(dut, 12, dualWrap); - idle(dut); - dut.io_gprClearValid = 1; - dut.io_gprClearTag = 41; - tick(dut); - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = dualWrap; - dut.io_loadRidValue = dualRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 41; - dut.io_loadData = 0xcc; - dut.io_externalGprWriteValid = 1; - dut.io_externalGprWriteTag = 42; - dut.io_externalGprWriteData = 0xdd; - dut.eval(); - require(dut.io_loadResolveReady && dut.io_scalarLoadSelected && - dut.io_loadWritebackSelected && dut.io_loadWakeupPublished && - dut.io_externalGprWriteFire && !dut.io_loadBlockedByExternalWrite, - "independent external and scalar GPR write ports did not complete together"); - tick(dut); - idle(dut); - dut.io_gprReadTag = 41; - dut.eval(); - require(dut.io_gprReadReady && dut.io_gprReadData == 0xcc && - dut.io_commitValid && dut.io_commitRobValue == dualRow, - "dual-port scalar completion did not preserve GPR or ROB state"); - tick(dut); - require(dut.io_size == 0, "ROB did not drain after dual-port physical sink scenario"); - - unsigned singleWrap = 0; - const unsigned singleRow = allocate(dut, 13, singleWrap); - idle(dut); - dut.io_gprClearValid = 1; - dut.io_gprClearTag = 43; - tick(dut); - idle(dut); - dut.io_singlePortMode = 1; - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = singleWrap; - dut.io_loadRidValue = singleRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 43; - dut.io_loadData = 0xee; - dut.io_externalGprWriteValid = 1; - dut.io_externalGprWriteTag = 44; - dut.io_externalGprWriteData = 0xff; - dut.eval(); - require(!dut.io_loadResolveReady && !dut.io_scalarLoadSelected && - dut.io_loadBlockedByExternalWrite && dut.io_externalGprWriteFire, - "one-port sink did not serialize independent external and scalar writes"); - tick(dut); - idle(dut); - dut.io_singlePortMode = 1; - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = singleWrap; - dut.io_loadRidValue = singleRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 1; - dut.io_loadDstTag = 43; - dut.io_loadData = 0xee; - dut.eval(); - require(dut.io_loadResolveReady && dut.io_scalarLoadSelected && - dut.io_loadWritebackSelected && dut.io_loadWakeupPublished, - "one-port scalar W2 did not retry after external write released"); - tick(dut); - idle(dut); - dut.io_singlePortMode = 1; - dut.io_gprReadTag = 43; - dut.eval(); - require(dut.io_gprReadReady && dut.io_gprReadData == 0xee && - dut.io_commitValid && dut.io_commitRobValue == singleRow, - "one-port retry did not commit GPR and ROB state atomically"); - tick(dut); - - unsigned localWrap = 0; - const unsigned localRow = allocate(dut, 14, localWrap); - idle(dut); - dut.io_loadValid = 1; - dut.io_loadRidValid = 1; - dut.io_loadRidWrap = localWrap; - dut.io_loadRidValue = localRow; - dut.io_loadDstValid = 1; - dut.io_loadDstKind = 2; - dut.io_loadDstTag = 1; - dut.io_loadData = 0x1234; - dut.eval(); - require(dut.io_protocolError && !dut.io_loadResolveReady && - !dut.io_scalarLoadSelected && !dut.io_loadWritebackSelected && - !dut.io_loadWakeupPublished, - "unsupported T destination did not surface a blocking contract error"); - - std::cout << "scalar-load-completion-rob-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/scalar_redirect_recovery_source_probe_tb.cpp b/tools/chisel/scalar_redirect_recovery_source_probe_tb.cpp deleted file mode 100644 index 19c2dc23..00000000 --- a/tools/chisel/scalar_redirect_recovery_source_probe_tb.cpp +++ /dev/null @@ -1,163 +0,0 @@ -#include -#include -#include - -#include "VScalarRedirectRecoverySourceProbe.h" -#include "verilated.h" - -static void tick(VScalarRedirectRecoverySourceProbe &dut) { - dut.clock = 0; - dut.eval(); - dut.clock = 1; - dut.eval(); -} - -static void require(bool condition, const char *message) { - if (!condition) { - std::cerr << "scalar-redirect-recovery-source-probe: " << message << '\n'; - std::exit(1); - } -} - -static void set_id(uint8_t &valid, uint8_t &wrap, uint8_t &value, - bool next_valid, bool next_wrap, int next_value) { - valid = next_valid; - wrap = next_wrap; - value = next_value; -} - -static void drive_event(VScalarRedirectRecoverySourceProbe &dut, - int block_bid, bool bid_wrap, int bid_value, - bool rid_valid, bool rid_wrap, int rid_value, - int lsid_value, uint64_t lsid_full, int order) { - dut.io_eventValid = 1; - dut.io_blockBidValid = 1; - dut.io_blockBid = block_bid; - set_id(dut.io_bid_valid, dut.io_bid_wrap, dut.io_bid_value, - true, bid_wrap, bid_value); - set_id(dut.io_rid_valid, dut.io_rid_wrap, dut.io_rid_value, - rid_valid, rid_wrap, rid_value); - set_id(dut.io_lsId_valid, dut.io_lsId_wrap, dut.io_lsId_value, - true, false, lsid_value); - dut.io_lsIdFull = lsid_full; - dut.io_resolveLsIdValid = 1; - dut.io_orderValid = 1; - dut.io_order = order; -} - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - VScalarRedirectRecoverySourceProbe dut; - - dut.reset = 1; - dut.io_eventValid = 0; - dut.io_blockBidValid = 0; - dut.io_blockBid = 0; - set_id(dut.io_bid_valid, dut.io_bid_wrap, dut.io_bid_value, false, false, 0); - set_id(dut.io_rid_valid, dut.io_rid_wrap, dut.io_rid_value, false, false, 0); - set_id(dut.io_lsId_valid, dut.io_lsId_wrap, dut.io_lsId_value, false, false, 0); - dut.io_lsIdFull = 0; - dut.io_resolveLsIdValid = 0; - dut.io_orderValid = 0; - dut.io_order = 0; - dut.io_sourceReady = 0; - dut.io_sourceResolved = 0; - dut.io_payloadIntentConsumed = 0; - dut.io_cancel = 0; - tick(dut); - tick(dut); - dut.reset = 0; - - // 0x12 projects to wrap=0, slot=2 for an eight-entry ring. - drive_event(dut, 0x12, false, 2, true, false, 4, 5, - 0x123456789aULL, 0x155); - dut.eval(); - require(dut.io_eventReady && dut.io_eventAccepted, - "exact redirect was not accepted into an empty source"); - tick(dut); - dut.io_eventValid = 0; - dut.eval(); - require(dut.io_pending && dut.io_sourceValid && !dut.io_published, - "captured redirect was not retained for publication"); - require(dut.io_sourceBlockBid == 0x12 && dut.io_sourceRid_valid && - dut.io_sourceRid_value == 5, - "published redirect did not preserve block identity or restart RID"); - require(dut.io_sourceLsIdFullValid && - dut.io_sourceLsIdFull == 0x123456789aULL, - "published redirect truncated or lost the full LSID"); - require(!dut.io_cleanupOrderValid && !dut.io_cleanupResolveLsIdValid, - "private sidecars were exposed before matched payload consumption"); - - dut.io_sourceReady = 1; - dut.eval(); - require(dut.io_sourceAccepted, - "retained redirect did not publish when the fabric became ready"); - tick(dut); - dut.eval(); - require(dut.io_pending && dut.io_published && !dut.io_sourceValid && - !dut.io_cleanupOrderValid, - "publish-once state exposed sidecars without payload ownership"); - - // Matched payload consumption exposes old sidecars while source resolution - // atomically admits the next event. - // 0x1b projects to wrap=1, slot=3. - dut.io_sourceResolved = 1; - dut.io_payloadIntentConsumed = 1; - drive_event(dut, 0x1b, true, 3, true, true, 6, 7, - 0x0fedcba987ULL, 0x2aa); - dut.eval(); - require(dut.io_eventReady && dut.io_eventAccepted, - "resolve-and-replace did not accept the next redirect"); - require(dut.io_cleanupOrderValid && dut.io_cleanupOrder == 0x155 && - dut.io_cleanupResolveLsIdValid && dut.io_cleanupLsId_value == 5, - "matched payload consumption did not authorize retained sidecars"); - require(dut.io_cleanupLsIdFull == 0x123456789aULL, - "matched cleanup did not preserve the retained full LSID"); - tick(dut); - dut.io_eventValid = 0; - dut.io_sourceResolved = 0; - dut.io_payloadIntentConsumed = 0; - dut.eval(); - require(dut.io_pending && !dut.io_published && dut.io_sourceValid && - dut.io_sourceBlockBid == 0x1b && dut.io_cleanupOrder == 0x2aa, - "resolve-and-replace did not retain the replacement identity"); - require(dut.io_sourceLsIdFullValid && - dut.io_sourceLsIdFull == 0x0fedcba987ULL, - "resolve-and-replace truncated the replacement full LSID"); - - // Cancellation must suppress publication in the cancellation cycle. - dut.io_cancel = 1; - dut.eval(); - require(!dut.io_sourceValid && !dut.io_sourceAccepted, - "cancel leaked a retained redirect into the recovery fabric"); - tick(dut); - dut.io_cancel = 0; - dut.eval(); - require(!dut.io_pending && !dut.io_published, - "cancel did not clear retained redirect state"); - - // Mismatched projection remains blocked and cannot publish. - dut.io_sourceReady = 1; - drive_event(dut, 0x12, false, 3, true, false, 1, 2, 0x1020304050ULL, 0x33); - tick(dut); - dut.io_eventValid = 0; - dut.eval(); - require(dut.io_pending && dut.io_blockedByMissingIdentity && - !dut.io_sourceValid && !dut.io_sourceAccepted, - "projection mismatch was not retained as blocked identity"); - dut.io_cancel = 1; - tick(dut); - dut.io_cancel = 0; - - // A valid full BID and ring BID still cannot publish without source RID. - drive_event(dut, 0x12, false, 2, false, false, 1, 2, 0x1122334455ULL, 0x44); - tick(dut); - dut.io_eventValid = 0; - dut.eval(); - require(dut.io_pending && dut.io_blockedByMissingIdentity && - !dut.io_sourceValid, - "invalid source RID was not rejected"); - - std::cout << "scalar-redirect-recovery-source-probe-status=pass\n"; - return 0; -} diff --git a/tools/chisel/scan_replay_liq_activation_artifacts.py b/tools/chisel/scan_replay_liq_activation_artifacts.py deleted file mode 100644 index e10fa9f6..00000000 --- a/tools/chisel/scan_replay_liq_activation_artifacts.py +++ /dev/null @@ -1,292 +0,0 @@ -#!/usr/bin/env python3 -"""Scan generated replay-LIQ sideband artifacts for activation coverage. - -This is a cheap pre-Verilator triage tool. It does not create new proof; it -classifies existing generated artifacts so the next packet can avoid -rediscovering whether positive eligible-store activation is currently limited -to focused fixtures or already present in CoreMark/natural workload runs. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -SCHEMA = "linxcore.replay_liq_activation_artifact_scan.v1" -DEFAULT_GENERATED_DIR = ROOT_DIR / "generated" -DEFAULT_OUTPUT = ( - ROOT_DIR - / "generated/r624-replay-liq-activation-artifact-scan/report/replay_liq_activation_artifact_scan.json" -) - -REQUIRED_ACTIVATION_COUNTERS = ( - "load_lookup_execute_with_eligible_store", - "load_lookup_execute_with_wait_store", - "resident_store_eligible", - "resident_store_wait_store_valid", - "resolve_queue_push_accepted", - "resolve_queue_valid", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "wait_replay_capture_accepted", - "liq_alloc_accepted", - "replay_queue_out_fire", - "lret_w2_slot_accepted", - "w2_promotion_live", -) - -SUMMARY_COUNTERS = ( - "load_lookup_valid", - "store_stq_resident", - "store_sta_dequeue_fire", - "store_std_dequeue_fire", - *REQUIRED_ACTIVATION_COUNTERS, -) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def counter_map(sideband: dict[str, Any]) -> dict[str, int | None]: - replay = sideband.get("replay_liq") - if not isinstance(replay, dict): - return {key: None for key in SUMMARY_COUNTERS} - out: dict[str, int | None] = {} - for key in SUMMARY_COUNTERS: - value = replay.get(key) - out[key] = value if isinstance(value, int) else None - return out - - -def positive(counters: dict[str, int | None], key: str) -> bool: - value = counters.get(key) - return isinstance(value, int) and value > 0 - - -def classify_artifact(build_dir: Path) -> str: - name = build_dir.name.lower() - if "coremark" in name: - return "coremark" - if "fixture" in name or "replay" in name or "liq" in name: - return "focused_or_synthetic" - return "other" - - -def manifest_summary(manifest_path: Path) -> dict[str, Any]: - if not manifest_path.exists(): - return {"present": False} - manifest = load_json(manifest_path) - summary = manifest.get("summary") - cbstop = summary.get("cbstop_counts") if isinstance(summary, dict) else None - return { - "present": True, - "status": manifest.get("status"), - "comparator_status": manifest.get("comparator_status"), - "compared_rows": summary.get("compared_rows") if isinstance(summary, dict) else None, - "mismatch_count": summary.get("mismatch_count") if isinstance(summary, dict) else None, - "cbstop_qemu": cbstop.get("qemu") if isinstance(cbstop, dict) else None, - "cbstop_dut": cbstop.get("dut") if isinstance(cbstop, dict) else None, - "git": manifest.get("git", {}), - } - - -def scan_artifact(sideband_path: Path, generated_dir: Path) -> dict[str, Any]: - sideband = load_json(sideband_path) - counters = counter_map(sideband) - build_dir = sideband_path.parent.parent - activation_positive = all(positive(counters, key) for key in REQUIRED_ACTIVATION_COUNTERS) - return { - "build_dir": str(build_dir), - "relative_build_dir": str(build_dir.relative_to(ROOT_DIR)), - "kind": classify_artifact(build_dir), - "activation_positive": activation_positive, - "counters": counters, - "manifest": manifest_summary(build_dir / "report/crosscheck_manifest.json"), - } - - -def build_report(args: argparse.Namespace) -> dict[str, Any]: - generated_dir = args.generated_dir - sideband_paths = sorted(generated_dir.glob("*/report/frontend_fetch_rf_alu_sideband_stats.json")) - artifacts = [scan_artifact(path, generated_dir) for path in sideband_paths] - positive_artifacts = [artifact for artifact in artifacts if artifact["activation_positive"]] - coremark_positive = [ - artifact for artifact in positive_artifacts if artifact.get("kind") == "coremark" - ] - focused_positive = [ - artifact for artifact in positive_artifacts if artifact.get("kind") == "focused_or_synthetic" - ] - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "This scan classifies existing generated sideband artifacts only. It is not a new " - "generated-RTL proof and must not replace a fresh manifest-backed workload run." - ), - "inputs": {"generated_dir": str(generated_dir)}, - "summary": { - "artifact_count": len(artifacts), - "activation_positive_count": len(positive_artifacts), - "coremark_positive_count": len(coremark_positive), - "focused_or_synthetic_positive_count": len(focused_positive), - }, - "positive_artifacts": positive_artifacts, - "artifacts": artifacts, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append(f"report: status is {report.get('status')!r}, expected 'pass'") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "not a new generated-RTL proof" not in boundary: - errors.append("report: claim_boundary must preserve scan-vs-proof boundary") - artifacts = report.get("artifacts") - positives = report.get("positive_artifacts") - summary = report.get("summary") - if not isinstance(artifacts, list): - errors.append("artifacts: missing section") - artifacts = [] - if not isinstance(positives, list): - errors.append("positive_artifacts: missing section") - positives = [] - if not isinstance(summary, dict): - errors.append("summary: missing section") - summary = {} - positive_count = sum(1 for artifact in artifacts if artifact.get("activation_positive") is True) - coremark_count = sum( - 1 - for artifact in artifacts - if artifact.get("activation_positive") is True and artifact.get("kind") == "coremark" - ) - focused_count = sum( - 1 - for artifact in artifacts - if artifact.get("activation_positive") is True - and artifact.get("kind") == "focused_or_synthetic" - ) - if summary.get("artifact_count") != len(artifacts): - errors.append("summary: artifact_count mismatch") - if summary.get("activation_positive_count") != positive_count: - errors.append("summary: activation_positive_count mismatch") - if summary.get("coremark_positive_count") != coremark_count: - errors.append("summary: coremark_positive_count mismatch") - if summary.get("focused_or_synthetic_positive_count") != focused_count: - errors.append("summary: focused_or_synthetic_positive_count mismatch") - if len(positives) != positive_count: - errors.append("positive_artifacts: count mismatch") - for artifact in positives: - counters = artifact.get("counters") - if not isinstance(counters, dict): - errors.append(f"{artifact.get('relative_build_dir')}: missing counters") - continue - for key in REQUIRED_ACTIVATION_COUNTERS: - if not positive(counters, key): - errors.append(f"{artifact.get('relative_build_dir')}: {key} must be positive") - return errors - - -def sample_report() -> dict[str, Any]: - positive_artifact = { - "relative_build_dir": "generated/sample-focused", - "kind": "focused_or_synthetic", - "activation_positive": True, - "counters": {key: 1 for key in SUMMARY_COUNTERS}, - "manifest": {"present": True, "status": "pass"}, - } - coremark_artifact = { - "relative_build_dir": "generated/sample-coremark", - "kind": "coremark", - "activation_positive": False, - "counters": {key: 0 for key in SUMMARY_COUNTERS}, - "manifest": {"present": True, "status": "pass"}, - } - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "scanner only; not a new generated-RTL proof", - "summary": { - "artifact_count": 2, - "activation_positive_count": 1, - "coremark_positive_count": 0, - "focused_or_synthetic_positive_count": 1, - }, - "positive_artifacts": [positive_artifact], - "artifacts": [coremark_artifact, positive_artifact], - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["summary"]["activation_positive_count"] = 2 - if not validate_report(failing): - raise AssertionError("summary count mismatch was not detected") - failing = copy.deepcopy(passing) - failing["positive_artifacts"][0]["counters"]["resolve_queue_push_accepted"] = 0 - if not validate_report(failing): - raise AssertionError("missing positive activation counter was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--generated-dir", type=Path, default=DEFAULT_GENERATED_DIR) - parser.add_argument("--output", type=Path, default=DEFAULT_OUTPUT) - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-activation-artifact-scan self-test: ok") - if args.validate_only is None and "--output" not in argv: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-activation-artifact-scan: ok manifest={args.validate_only}") - return 0 - - report = build_report(args) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-activation-artifact-scan={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/scan_replay_liq_qemu_intervals.py b/tools/chisel/scan_replay_liq_qemu_intervals.py deleted file mode 100644 index c3dcba43..00000000 --- a/tools/chisel/scan_replay_liq_qemu_intervals.py +++ /dev/null @@ -1,331 +0,0 @@ -#!/usr/bin/env python3 -"""Scan skipped QEMU intervals for replay-LIQ candidate windows.""" - -from __future__ import annotations - -import argparse -import json -import os -import signal -import subprocess -import sys -from pathlib import Path -from typing import Any - -from find_replay_liq_qemu_candidates import ( - find_candidates, - load_events, - pc_histogram, - write_summary, -) - - -ROOT_DIR = Path(__file__).resolve().parents[2] -WRAPPER = ROOT_DIR / "tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh" - - -def parse_int_list(value: str) -> list[int]: - out: list[int] = [] - for item in value.split(","): - item = item.strip() - if not item: - continue - parsed = int(item, 0) - if parsed < 0: - raise argparse.ArgumentTypeError("skip rows must be non-negative") - out.append(parsed) - if not out: - raise argparse.ArgumentTypeError("at least one skip row is required") - return out - - -def parse_skip_range(value: str) -> list[int]: - parts = [part.strip() for part in value.split(":")] - if len(parts) != 3 or any(not part for part in parts): - raise argparse.ArgumentTypeError("skip ranges must use start:stop:step") - start, stop, step = (int(part, 0) for part in parts) - if start < 0 or stop < 0: - raise argparse.ArgumentTypeError("skip range bounds must be non-negative") - if step <= 0: - raise argparse.ArgumentTypeError("skip range step must be positive") - if stop < start: - raise argparse.ArgumentTypeError("skip range stop must be >= start") - return list(range(start, stop + 1, step)) - - -def dedupe_preserve_order(values: list[int]) -> list[int]: - out: list[int] = [] - seen: set[int] = set() - for value in values: - if value in seen: - continue - seen.add(value) - out.append(value) - return out - - -def count_rows(path: Path) -> int: - with path.open("r", encoding="utf-8") as f: - return sum(1 for line in f if line.strip()) - - -def default_qemu_args(elf: Path) -> list[str]: - return [ - "-nographic", - "-monitor", - "none", - "-machine", - "virt", - "-m", - "1280M", - "-kernel", - str(elf), - ] - - -def interval_name(skip_rows: int, capture_rows: int) -> str: - return f"skip{skip_rows}-rows{capture_rows}" - - -def run_interval(args: argparse.Namespace, skip_rows: int, qemu_args: list[str]) -> dict[str, Any]: - interval_dir = args.build_dir / interval_name(skip_rows, args.capture_rows) - trace_dir = interval_dir / "traces" - report_dir = interval_dir / "report" - report_dir.mkdir(parents=True, exist_ok=True) - - cmd = [ - "bash", - str(WRAPPER), - "--build-dir", - str(interval_dir), - "--elf", - str(args.elf), - "--expected-rows", - "0", - "--capture-rows", - str(args.capture_rows), - "--qemu-skip-rows", - str(skip_rows), - "--allow-block-markers", - "--allow-block-loop-reentry", - "--qemu-raw-only", - "--max-seconds", - str(args.max_seconds), - ] - if args.qemu_bin is not None: - cmd += ["--qemu-bin", str(args.qemu_bin)] - cmd += ["--"] + qemu_args - - timed_out = False - stdout = "" - stderr = "" - process = subprocess.Popen( - cmd, - cwd=ROOT_DIR, - text=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - start_new_session=True, - ) - try: - stdout, stderr = process.communicate(timeout=args.wrapper_timeout_seconds) - except subprocess.TimeoutExpired: - timed_out = True - os.killpg(process.pid, signal.SIGTERM) - try: - stdout, stderr = process.communicate(timeout=5) - except subprocess.TimeoutExpired: - os.killpg(process.pid, signal.SIGKILL) - stdout, stderr = process.communicate() - (report_dir / "scan-wrapper.stdout.txt").write_text(stdout, encoding="utf-8") - (report_dir / "scan-wrapper.stderr.txt").write_text(stderr, encoding="utf-8") - - raw_trace = trace_dir / "qemu.live.raw.jsonl" - raw_rows = count_rows(raw_trace) if raw_trace.exists() else 0 - capture_complete = raw_rows >= args.capture_rows - interval: dict[str, Any] = { - "skip_rows": skip_rows, - "capture_rows": args.capture_rows, - "build_dir": str(interval_dir), - "raw_trace": str(raw_trace), - "wrapper_returncode": process.returncode, - "wrapper_timed_out": timed_out, - "capture_complete": capture_complete, - } - if process.returncode != 0 and not capture_complete: - interval["error"] = "wrapper failed" - return interval - if not raw_trace.exists(): - interval["error"] = "wrapper did not produce qemu.live.raw.jsonl" - return interval - - events = load_events(raw_trace) - candidates = find_candidates( - events, - lookback_rows=args.lookback_rows, - same_line=not args.exact_overlap_only, - min_second_row=0, - max_second_row=-1, - dedupe_pairs=not args.no_dedupe_pairs, - ) - candidate_summary = write_summary( - events, - candidates, - args.top, - row_space="raw", - raw_rows_by_event_row={event.row: skip_rows + event.row for event in events}, - ) - candidate_path = report_dir / "replay_liq_qemu_candidates.json" - candidate_path.write_text(json.dumps(candidate_summary, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - interval.update( - { - "raw_rows": count_rows(raw_trace), - "event_count": candidate_summary["event_count"], - "store_count": candidate_summary["store_count"], - "load_count": candidate_summary["load_count"], - "candidate_count": candidate_summary["candidate_count"], - "candidate_report": str(candidate_path), - "top_candidates": candidate_summary["top_candidates"][: args.top], - "memory_pc_histogram": pc_histogram(events)[: args.top], - } - ) - return interval - - -def write_scan_summary(args: argparse.Namespace, intervals: list[dict[str, Any]]) -> dict[str, Any]: - load_intervals = [item for item in intervals if int(item.get("load_count", 0)) > 0] - candidate_intervals = [item for item in intervals if int(item.get("candidate_count", 0)) > 0] - summary = { - "schema": "linxcore.replay_liq_qemu_interval_scan.v1", - "claim_boundary": ( - "Skipped raw QEMU interval scans are candidate-selection hints only; " - "replay-LIQ evidence still requires generated-RTL sideband counters " - "and a passing QEMU/DUT comparator manifest from an unskipped state." - ), - "input": { - "elf": str(args.elf), - "build_dir": str(args.build_dir), - "skips": args.skips, - "skip_ranges": args.skip_ranges_raw, - "capture_rows": args.capture_rows, - "lookback_rows": args.lookback_rows, - "top": args.top, - }, - "scanned_interval_count": len(intervals), - "load_interval_count": len(load_intervals), - "candidate_interval_count": len(candidate_intervals), - "first_load_interval": load_intervals[0] if load_intervals else None, - "first_candidate_interval": candidate_intervals[0] if candidate_intervals else None, - "intervals": intervals, - } - args.build_dir.mkdir(parents=True, exist_ok=True) - args.output.write_text(json.dumps(summary, indent=2, sort_keys=True) + "\n", encoding="utf-8") - return summary - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--elf", type=Path, required=True, help="direct-boot ELF to run under QEMU") - parser.add_argument( - "--build-dir", - type=Path, - default=ROOT_DIR / "generated/replay-liq-qemu-interval-scan", - help="scan output root", - ) - parser.add_argument( - "--output", - type=Path, - default=None, - help="scan summary JSON path; default is /report/interval_scan_summary.json", - ) - parser.add_argument( - "--skips", - type=parse_int_list, - default=None, - help="comma-separated filtered-row skip offsets", - ) - parser.add_argument( - "--skip-range", - action="append", - default=[], - metavar="START:STOP:STEP", - help="inclusive filtered-row skip range; may be repeated", - ) - parser.add_argument("--capture-rows", type=int, default=2048, help="raw rows to capture per interval") - parser.add_argument("--max-seconds", type=int, default=60, help="QEMU watchdog per interval") - parser.add_argument( - "--wrapper-timeout-seconds", - type=int, - default=None, - help="hard scanner-side timeout per wrapper run; default is max(2*--max-seconds, --max-seconds+30)", - ) - parser.add_argument("--qemu-bin", type=Path, default=None, help="optional QEMU binary override") - parser.add_argument("--lookback-rows", type=int, default=2048, help="locator lookback rows") - parser.add_argument("--top", type=int, default=20, help="top candidates/histogram rows per interval") - parser.add_argument("--exact-overlap-only", action="store_true", help="drop same-line-only locator candidates") - parser.add_argument("--no-dedupe-pairs", action="store_true", help="keep repeated dynamic candidate instances") - parser.add_argument("--stop-on-load", action="store_true", help="stop scanning after the first interval with any loads") - parser.add_argument("--stop-on-candidate", action="store_true", help="stop scanning after the first interval with candidates") - parser.add_argument("qemu_args", nargs=argparse.REMAINDER, help="optional QEMU args after --") - args = parser.parse_args(argv) - - if args.capture_rows <= 0: - raise SystemExit("error: --capture-rows must be positive") - if args.max_seconds <= 0: - raise SystemExit("error: --max-seconds must be positive") - if args.wrapper_timeout_seconds is None: - args.wrapper_timeout_seconds = max(args.max_seconds * 2, args.max_seconds + 30) - if args.wrapper_timeout_seconds <= 0: - raise SystemExit("error: --wrapper-timeout-seconds must be positive") - if args.lookback_rows <= 0: - raise SystemExit("error: --lookback-rows must be positive") - if args.top <= 0: - raise SystemExit("error: --top must be positive") - args.skip_ranges_raw = list(args.skip_range) - skips = args.skips if args.skips is not None else parse_int_list("4096,16384,65536,262144") - for skip_range in args.skip_range: - skips.extend(parse_skip_range(skip_range)) - args.skips = dedupe_preserve_order(skips) - if args.output is None: - args.output = args.build_dir / "report/interval_scan_summary.json" - if args.output.parent != Path("."): - args.output.parent.mkdir(parents=True, exist_ok=True) - return args - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - qemu_args = args.qemu_args - if qemu_args and qemu_args[0] == "--": - qemu_args = qemu_args[1:] - if not qemu_args: - qemu_args = default_qemu_args(args.elf) - - intervals: list[dict[str, Any]] = [] - for skip_rows in args.skips: - interval = run_interval(args, skip_rows, qemu_args) - intervals.append(interval) - print( - "interval-scan " - f"skip={skip_rows} rc={interval['wrapper_returncode']} " - f"timeout={int(bool(interval.get('wrapper_timed_out', False)))} " - f"rows={interval.get('raw_rows', 0)} events={interval.get('event_count', 0)} " - f"stores={interval.get('store_count', 0)} loads={interval.get('load_count', 0)} " - f"candidates={interval.get('candidate_count', 0)}", - flush=True, - ) - if interval.get("error"): - break - if args.stop_on_candidate and int(interval.get("candidate_count", 0)) > 0: - break - if args.stop_on_load and int(interval.get("load_count", 0)) > 0: - break - - summary = write_scan_summary(args, intervals) - print(f"interval-scan-summary={args.output}", flush=True) - return 1 if any(item.get("error") for item in summary["intervals"]) else 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/scan_replay_liq_qemu_seeded_windows.py b/tools/chisel/scan_replay_liq_qemu_seeded_windows.py deleted file mode 100644 index f5f3a3f0..00000000 --- a/tools/chisel/scan_replay_liq_qemu_seeded_windows.py +++ /dev/null @@ -1,553 +0,0 @@ -#!/usr/bin/env python3 -"""Replay QEMU raw windows through generated RTL with matching RF seeds. - -This scanner consumes existing QEMU raw-prefix artifacts and candidate reports. -For each selected raw dynamic window it: - -1. builds an RF seed from rows before the window start, -2. slices the raw QEMU window into a replay trace, -3. runs the existing reduced-store replay-LIQ Verilator trace wrapper, and -4. classifies the generated manifest plus replay-LIQ sideband counters. - -The scanner is a proof orchestrator, not a new architectural oracle. A trial is -replay-LIQ activation proof only when the generated-RTL comparator manifest -passes and every required activation counter is nonzero. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import os -import signal -import subprocess -import sys -from pathlib import Path -from typing import Any - -from build_frontend_fetch_rf_seed import build_seed, load_jsonl, write_seed -from scan_replay_liq_activation_artifacts import ( - REQUIRED_ACTIVATION_COUNTERS, - SUMMARY_COUNTERS, - counter_map, - manifest_summary, - positive, -) - - -ROOT_DIR = Path(__file__).resolve().parents[2] -WRAPPER = ROOT_DIR / "tools/chisel/run_chisel_frontend_fetch_rf_alu_trace_top_xcheck.sh" -SCHEMA = "linxcore.replay_liq_qemu_seeded_window_scan.v1" - -DEFAULT_RAW_TRACE = ( - ROOT_DIR / "generated/r621-coremark-unskipped-1721-qemu-preflight/traces/qemu.live.raw.jsonl" -) -DEFAULT_CANDIDATES = ( - ROOT_DIR - / "generated/r625-coremark-unskipped-1721-qemu-candidates-top100/report/replay_liq_qemu_candidates.json" -) -DEFAULT_ELF = ROOT_DIR / "tests/benchmarks/build/coremark_real.elf" -DEFAULT_BUILD_DIR = ROOT_DIR / "generated/r630-replay-liq-qemu-seeded-window-scan" - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def parse_int(value: Any) -> int: - if isinstance(value, int): - return value - if isinstance(value, str): - return int(value, 0) - raise ValueError(f"expected integer-like value, got {value!r}") - - -def load_jsonl_lines(path: Path) -> list[str]: - lines: list[str] = [] - with path.open("r", encoding="utf-8", errors="replace") as f: - for line in f: - if line.strip(): - lines.append(line) - return lines - - -def write_window_slice(source: Path, output: Path, *, start: int, count: int) -> int: - lines = load_jsonl_lines(source) - output.parent.mkdir(parents=True, exist_ok=True) - selected = lines[start : start + count] - output.write_text("".join(selected), encoding="utf-8") - return len(selected) - - -def candidate_windows( - report: dict[str, Any], - *, - skip_windows: int, - max_trials: int, - max_capture_rows: int, -) -> list[dict[str, Any]]: - raw_candidates = report.get("top_candidates") - if not isinstance(raw_candidates, list): - return [] - selected: list[dict[str, Any]] = [] - seen: set[tuple[int, int]] = set() - eligible_index = 0 - for candidate in raw_candidates: - if not isinstance(candidate, dict): - continue - hint = candidate.get("probe_hint", {}).get("raw_dynamic_window") - if not isinstance(hint, dict): - continue - skip_rows = parse_int(hint.get("qemu_skip_rows")) - capture_rows = parse_int(hint.get("capture_rows")) - if capture_rows <= 0 or capture_rows > max_capture_rows: - continue - key = (skip_rows, capture_rows) - if key in seen: - continue - seen.add(key) - if eligible_index < skip_windows: - eligible_index += 1 - continue - selected.append( - { - "index": eligible_index, - "kind": candidate.get("kind"), - "exact_overlap": candidate.get("exact_overlap"), - "score": candidate.get("score"), - "row_distance": candidate.get("row_distance"), - "pc_lo": f"0x{parse_int(candidate.get('pc_lo')):x}", - "pc_hi": f"0x{parse_int(candidate.get('pc_hi')):x}", - "qemu_skip_rows": skip_rows, - "capture_rows": capture_rows, - "raw_dynamic_window": hint, - } - ) - eligible_index += 1 - if len(selected) >= max_trials: - break - return selected - - -def manifest_pass(summary: dict[str, Any]) -> bool: - if summary.get("present") is not True: - return False - return ( - summary.get("status") == "pass" - and summary.get("comparator_status") == 0 - and isinstance(summary.get("compared_rows"), int) - and summary.get("compared_rows") > 0 - and summary.get("mismatch_count") == 0 - and summary.get("cbstop_qemu") == 0 - and summary.get("cbstop_dut") == 0 - ) - - -def sideband_summary(sideband_path: Path) -> dict[str, Any]: - if not sideband_path.exists(): - return { - "present": False, - "activation_positive": False, - "counters": {key: None for key in SUMMARY_COUNTERS}, - } - sideband = load_json(sideband_path) - counters = counter_map(sideband) - activation_positive = all(positive(counters, key) for key in REQUIRED_ACTIVATION_COUNTERS) - return { - "present": True, - "schema": sideband.get("schema"), - "reduced_store_replay_liq_top": sideband.get("reduced_store_replay_liq_top"), - "activation_positive": activation_positive, - "counters": counters, - } - - -def run_window(args: argparse.Namespace, window: dict[str, Any], all_rows: list[dict[str, Any]]) -> dict[str, Any]: - label = ( - f"window{window['index']:02d}-skip{window['qemu_skip_rows']}" - f"-rows{window['capture_rows']}" - ) - build_dir = args.build_dir / label - trace_dir = build_dir / "traces" - report_dir = build_dir / "report" - seed_path = trace_dir / "rf_seed.jsonl" - raw_window = trace_dir / "qemu.window.raw.jsonl" - report_dir.mkdir(parents=True, exist_ok=True) - - state, corrections = build_seed( - all_rows, - stop_index=window["qemu_skip_rows"], - max_arch_reg=args.max_arch_reg, - ) - write_seed( - seed_path, - state=state, - source=args.input_raw, - stop_index=window["qemu_skip_rows"], - stop_pc=None, - ) - sliced_rows = write_window_slice( - args.input_raw, - raw_window, - start=window["qemu_skip_rows"], - count=window["capture_rows"], - ) - - env = os.environ.copy() - env.update( - { - "BUILD_DIR": str(build_dir), - "FETCH_ELF": str(args.elf), - "FETCH_QEMU_TRACE": str(raw_window), - "FETCH_QEMU_MAX_ROWS": "0", - "FETCH_QEMU_ALLOW_BLOCK_MARKERS": "1", - "FETCH_QEMU_ALLOW_BLOCK_LOOP_REENTRY": "1", - "FETCH_REDUCED_STORE_REPLAY_LIQ": "1", - "FETCH_DISABLE_STORE_MEMORY_MUTATION": "1", - "FETCH_RF_SEED": str(seed_path), - } - ) - if args.early_sta_address: - env["LINXCORE_REPLAY_LIQ_EARLY_STA_ADDRESS"] = "1" - if args.allow_residual_replay_liq_wait: - env["FETCH_ALLOW_RESIDUAL_REPLAY_LIQ_WAIT"] = "1" - - timed_out = False - process = subprocess.Popen( - ["bash", str(WRAPPER)], - cwd=ROOT_DIR, - text=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - start_new_session=True, - env=env, - ) - try: - stdout, stderr = process.communicate(timeout=args.wrapper_timeout_seconds) - except subprocess.TimeoutExpired: - timed_out = True - os.killpg(process.pid, signal.SIGTERM) - try: - stdout, stderr = process.communicate(timeout=5) - except subprocess.TimeoutExpired: - os.killpg(process.pid, signal.SIGKILL) - stdout, stderr = process.communicate() - - (report_dir / "seeded-window.stdout.txt").write_text(stdout, encoding="utf-8") - (report_dir / "seeded-window.stderr.txt").write_text(stderr, encoding="utf-8") - - manifest = manifest_summary(report_dir / "crosscheck_manifest.json") - sideband = sideband_summary(report_dir / "frontend_fetch_rf_alu_sideband_stats.json") - comparator_pass = manifest_pass(manifest) - activation_positive = comparator_pass and sideband.get("activation_positive") is True - rf_conflict = "expected rows require conflicting initial RF data" in stderr - local_source_missing = "reads empty" in stderr and "local source" in stderr - if activation_positive: - status = "activation_positive" - reason = "generated RTL comparator passed and all required replay-LIQ activation counters were nonzero" - elif comparator_pass: - status = "compare_pass_no_activation" - reason = "generated RTL comparator passed, but replay-LIQ activation counters were not all nonzero" - elif rf_conflict: - status = "rf_source_conflict" - reason = "reduced expected rows require conflicting initial RF source data inside one seeded launch window" - elif local_source_missing: - status = "local_source_missing" - reason = "reduced expected rows require hidden local T/U source state that the RF seed cannot reconstruct" - elif timed_out: - status = "timeout" - reason = "generated RTL wrapper timed out" - else: - status = "wrapper_failed" - reason = "generated RTL wrapper failed before a passing comparator manifest" - - return { - **window, - "label": label, - "status": status, - "reason": reason, - "build_dir": str(build_dir), - "raw_window": str(raw_window), - "rf_seed": str(seed_path), - "seed_register_count": len(state), - "seed_source_corrections": len(corrections), - "sliced_rows": sliced_rows, - "wrapper_returncode": process.returncode, - "wrapper_timed_out": timed_out, - "stdout": str(report_dir / "seeded-window.stdout.txt"), - "stderr": str(report_dir / "seeded-window.stderr.txt"), - "manifest": manifest, - "sideband": sideband, - } - - -def build_report(args: argparse.Namespace, windows: list[dict[str, Any]], trials: list[dict[str, Any]]) -> dict[str, Any]: - positives = [trial for trial in trials if trial.get("status") == "activation_positive"] - compare_passes = [trial for trial in trials if trial.get("status") in {"activation_positive", "compare_pass_no_activation"}] - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "A seeded raw-window trial is replay-LIQ activation proof only when " - "the generated-RTL comparator manifest passes and every required " - "eligible-store, ResolveQ, MDB, LIQ, replay-output, and W2-promotion " - "counter is nonzero. Comparator pass alone proves launch-state " - "reconstruction, not replay-LIQ replacement." - ), - "inputs": { - "candidate_report": str(args.candidates), - "input_raw": str(args.input_raw), - "elf": str(args.elf), - "build_dir": str(args.build_dir), - "skip_windows": args.skip_windows, - "max_trials": args.max_trials, - "max_capture_rows": args.max_capture_rows, - "early_sta_address": args.early_sta_address, - "allow_residual_replay_liq_wait": args.allow_residual_replay_liq_wait, - }, - "required_activation_counters": list(REQUIRED_ACTIVATION_COUNTERS), - "summary": { - "window_count": len(windows), - "trial_count": len(trials), - "compare_pass_count": len(compare_passes), - "activation_positive_count": len(positives), - "first_activation_positive": positives[0] if positives else None, - }, - "generated_rtl": { - "status": "activation_positive" if positives else "no_activation", - "reason": ( - "At least one seeded raw window produced full replay-LIQ activation proof" - if positives - else "No scanned seeded raw window produced the required positive replay-LIQ counter bundle" - ), - }, - "windows": windows, - "trials": trials, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if report.get("schema") != SCHEMA: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append("report: status must be pass") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "Comparator pass alone" not in boundary: - errors.append("report: claim_boundary must preserve comparator-vs-activation boundary") - summary = report.get("summary") - trials = report.get("trials") - windows = report.get("windows") - if not isinstance(summary, dict): - errors.append("summary: missing section") - summary = {} - if not isinstance(trials, list): - errors.append("trials: missing section") - trials = [] - if not isinstance(windows, list): - errors.append("windows: missing section") - windows = [] - if summary.get("window_count") != len(windows): - errors.append("summary: window_count mismatch") - if summary.get("trial_count") != len(trials): - errors.append("summary: trial_count mismatch") - compare_pass_count = sum( - 1 - for trial in trials - if isinstance(trial, dict) - and trial.get("status") in {"activation_positive", "compare_pass_no_activation"} - ) - activation_count = sum( - 1 for trial in trials if isinstance(trial, dict) and trial.get("status") == "activation_positive" - ) - if summary.get("compare_pass_count") != compare_pass_count: - errors.append("summary: compare_pass_count mismatch") - if summary.get("activation_positive_count") != activation_count: - errors.append("summary: activation_positive_count mismatch") - generated = report.get("generated_rtl") - if not isinstance(generated, dict) or generated.get("status") not in {"activation_positive", "no_activation"}: - errors.append("generated_rtl: unexpected status") - for trial in trials: - if not isinstance(trial, dict): - errors.append("trials: non-object trial") - continue - if trial.get("status") not in { - "activation_positive", - "compare_pass_no_activation", - "rf_source_conflict", - "local_source_missing", - "timeout", - "wrapper_failed", - }: - errors.append(f"{trial.get('label')}: unexpected trial status {trial.get('status')!r}") - if trial.get("status") == "activation_positive": - manifest = trial.get("manifest") - sideband = trial.get("sideband") - if not isinstance(manifest, dict) or not manifest_pass(manifest): - errors.append(f"{trial.get('label')}: activation-positive trial lacks passing manifest") - if not isinstance(sideband, dict): - errors.append(f"{trial.get('label')}: activation-positive trial missing sideband") - continue - counters = sideband.get("counters") - if not isinstance(counters, dict): - errors.append(f"{trial.get('label')}: activation-positive trial missing counters") - continue - for key in REQUIRED_ACTIVATION_COUNTERS: - if not positive(counters, key): - errors.append(f"{trial.get('label')}: {key} must be positive") - return errors - - -def sample_report() -> dict[str, Any]: - trial = { - "label": "window00-skip0-rows4", - "status": "activation_positive", - "manifest": { - "present": True, - "status": "pass", - "comparator_status": 0, - "compared_rows": 3, - "mismatch_count": 0, - "cbstop_qemu": 0, - "cbstop_dut": 0, - }, - "sideband": { - "present": True, - "activation_positive": True, - "counters": {key: 1 for key in SUMMARY_COUNTERS}, - }, - } - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "Comparator pass alone is not replay-LIQ activation proof", - "summary": { - "window_count": 1, - "trial_count": 1, - "compare_pass_count": 1, - "activation_positive_count": 1, - }, - "generated_rtl": {"status": "activation_positive"}, - "windows": [{"index": 0}], - "trials": [trial], - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample report failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["summary"]["activation_positive_count"] = 0 - if not validate_report(failing): - raise AssertionError("activation-positive summary mismatch was not detected") - failing = copy.deepcopy(passing) - failing["trials"][0]["sideband"]["counters"]["resolve_queue_push_accepted"] = 0 - if not validate_report(failing): - raise AssertionError("missing positive counter was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--candidates", type=Path, default=DEFAULT_CANDIDATES) - parser.add_argument("--input-raw", type=Path, default=DEFAULT_RAW_TRACE) - parser.add_argument("--elf", type=Path, default=DEFAULT_ELF) - parser.add_argument("--build-dir", type=Path, default=DEFAULT_BUILD_DIR) - parser.add_argument("--output", type=Path, default=None) - parser.add_argument( - "--skip-windows", - type=int, - default=0, - help="skip this many eligible candidate windows before running trials", - ) - parser.add_argument("--max-trials", type=int, default=1) - parser.add_argument("--max-capture-rows", type=int, default=160) - parser.add_argument("--max-arch-reg", type=int, default=24) - parser.add_argument("--wrapper-timeout-seconds", type=int, default=300) - parser.add_argument("--no-early-sta-address", action="store_true") - parser.add_argument("--allow-residual-replay-liq-wait", action="store_true") - parser.add_argument("--stop-on-activation", action="store_true") - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - args = parser.parse_args(argv) - if args.output is None: - args.output = args.build_dir / "report/seeded_window_scan.json" - if args.skip_windows < 0: - raise SystemExit("error: --skip-windows must be non-negative") - if args.max_trials <= 0: - raise SystemExit("error: --max-trials must be positive") - if args.max_capture_rows <= 0: - raise SystemExit("error: --max-capture-rows must be positive") - if args.max_arch_reg <= 0: - raise SystemExit("error: --max-arch-reg must be positive") - if args.wrapper_timeout_seconds <= 0: - raise SystemExit("error: --wrapper-timeout-seconds must be positive") - args.early_sta_address = not args.no_early_sta_address - return args - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-qemu-seeded-window-scan self-test: ok") - if args.validate_only is None: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-qemu-seeded-window-scan: ok manifest={args.validate_only}") - return 0 - - candidate_report = load_json(args.candidates) - windows = candidate_windows( - candidate_report, - skip_windows=args.skip_windows, - max_trials=args.max_trials, - max_capture_rows=args.max_capture_rows, - ) - all_rows = load_jsonl(args.input_raw) - trials: list[dict[str, Any]] = [] - for window in windows: - trial = run_window(args, window, all_rows) - trials.append(trial) - print( - "seeded-window " - f"label={trial['label']} status={trial['status']} " - f"seed_regs={trial['seed_register_count']} sliced_rows={trial['sliced_rows']} " - f"compared={trial.get('manifest', {}).get('compared_rows')} " - f"activation={trial.get('sideband', {}).get('activation_positive')}", - flush=True, - ) - if args.stop_on_activation and trial["status"] == "activation_positive": - break - - report = build_report(args, windows, trials) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-qemu-seeded-window-scan={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/search_replay_liq_pc_filter_preflights.py b/tools/chisel/search_replay_liq_pc_filter_preflights.py deleted file mode 100644 index 34bdec2e..00000000 --- a/tools/chisel/search_replay_liq_pc_filter_preflights.py +++ /dev/null @@ -1,536 +0,0 @@ -#!/usr/bin/env python3 -"""Search CoreMark replay-LIQ candidates for legal PC-filter preflights. - -The search is intentionally QEMU-only. A candidate can authorize Verilator time -only after the wrapper produces a legal reduced preview and the exact expected -memory-PC guards pass. -""" - -from __future__ import annotations - -import argparse -import copy -import json -import os -import signal -import subprocess -import sys -from pathlib import Path -from typing import Any - - -ROOT_DIR = Path(__file__).resolve().parents[2] -WRAPPER = ROOT_DIR / "tools/chisel/run_chisel_frontend_fetch_rf_alu_qemu_elf_xcheck.sh" -SCHEMA = "linxcore.replay_liq_pc_filter_preflight_search.v2" -LEGACY_SCHEMAS = {"linxcore.replay_liq_pc_filter_preflight_search.v1", SCHEMA} - -DEFAULT_CANDIDATES = ( - ROOT_DIR - / "generated/r625-coremark-unskipped-1721-qemu-candidates-top100/report/replay_liq_qemu_candidates.json" -) -DEFAULT_ELF = ROOT_DIR / "tests/benchmarks/build/coremark_real.elf" -DEFAULT_BUILD_DIR = ROOT_DIR / "generated/r626-replay-liq-pc-filter-preflight-search" - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def write_json(path: Path, data: dict[str, Any]) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(json.dumps(data, indent=2, sort_keys=True) + "\n", encoding="utf-8") - - -def count_rows(path: Path) -> int: - if not path.exists(): - return 0 - with path.open("r", encoding="utf-8", errors="replace") as f: - return sum(1 for line in f if line.strip()) - - -def load_preview_rows(path: Path) -> list[dict[str, Any]]: - rows: list[dict[str, Any]] = [] - if not path.exists(): - return rows - with path.open("r", encoding="utf-8", errors="replace") as f: - for line in f: - if not line.strip(): - continue - row = json.loads(line) - if isinstance(row, dict): - rows.append(row) - return rows - - -def parse_int(value: Any) -> int: - if isinstance(value, int): - return value - if isinstance(value, str): - return int(value, 0) - raise ValueError(f"expected integer-like value, got {value!r}") - - -def row_bool(row: dict[str, Any], key: str) -> bool: - value = row.get(key) - if isinstance(value, bool): - return value - if isinstance(value, int): - return value != 0 - if isinstance(value, str): - return value.lower() in {"1", "true", "yes"} - return False - - -def row_int(row: dict[str, Any], key: str) -> int: - value = row.get(key, 0) - try: - return parse_int(value) - except (TypeError, ValueError): - return 0 - - -def state_seed_audit(preview: Path) -> dict[str, Any]: - first_active = None - for row in load_preview_rows(preview): - if not row_bool(row, "skip"): - first_active = row - break - if first_active is None: - return { - "status": "unknown", - "reason": "no non-skipped reduced preview row was available for RF state audit", - } - - has_visible_source = row_bool(first_active, "src0_valid") or row_bool(first_active, "src1_valid") - memory_needs_state = row_bool(first_active, "mem_valid") and ( - row_int(first_active, "mem_addr") != 0 - or row_int(first_active, "mem_wdata") != 0 - or row_int(first_active, "mem_rdata") != 0 - ) - dst_needs_state = row_bool(first_active, "dst_valid") and row_int(first_active, "dst_data") != 0 - common = { - "first_pc": f"0x{row_int(first_active, 'pc'):x}", - "first_insn": f"0x{row_int(first_active, 'insn'):x}", - "mem_valid": row_bool(first_active, "mem_valid"), - "dst_valid": row_bool(first_active, "dst_valid"), - "src0_valid": row_bool(first_active, "src0_valid"), - "src1_valid": row_bool(first_active, "src1_valid"), - } - if (memory_needs_state or dst_needs_state) and not has_visible_source: - return { - **common, - "status": "insufficient", - "reason": ( - "first non-skipped reduced row has memory/destination data but no visible " - "source operands, so the Verilator harness cannot preload the architectural " - "RF state needed to start generated RTL at this PC filter" - ), - } - return { - **common, - "status": "ready", - "reason": "first reduced row exposes source operands or does not require hidden RF state", - } - - -def candidate_pc_list(candidate: dict[str, Any], op: str) -> list[str]: - first = candidate.get("first", {}) - second = candidate.get("second", {}) - out: list[str] = [] - for item in (first, second): - if isinstance(item, dict) and item.get("op") == op and isinstance(item.get("pc"), str): - out.append(item["pc"]) - return out - - -def candidate_rows(report: dict[str, Any], *, pc_span_limit: int, max_trials: int) -> list[dict[str, Any]]: - raw_candidates = report.get("top_candidates") - if not isinstance(raw_candidates, list): - return [] - rows: list[dict[str, Any]] = [] - seen: set[tuple[str, str, str, str]] = set() - for candidate in raw_candidates: - if not isinstance(candidate, dict): - continue - if candidate.get("kind") != "store_before_load" or candidate.get("exact_overlap") is not True: - continue - pc_lo = parse_int(candidate.get("pc_lo")) - pc_hi = parse_int(candidate.get("pc_hi")) - pc_span = pc_hi - pc_lo - if pc_span <= 0 or pc_span > pc_span_limit: - continue - stores = candidate_pc_list(candidate, "store") - loads = candidate_pc_list(candidate, "load") - if not stores or not loads: - continue - key = (f"0x{pc_lo:x}", f"0x{pc_hi:x}", ",".join(stores), ",".join(loads)) - if key in seen: - continue - seen.add(key) - rows.append( - { - "index": len(rows), - "score": candidate.get("score"), - "row_distance": candidate.get("row_distance"), - "pc_span": pc_span, - "pc_lo": f"0x{pc_lo:x}", - "pc_hi": f"0x{pc_hi:x}", - "expected_store_pcs": stores, - "expected_load_pcs": loads, - "raw_dynamic_window": candidate.get("probe_hint", {}).get("raw_dynamic_window"), - } - ) - rows.sort(key=lambda item: (int(item["pc_span"]), int(item.get("row_distance") or 0), -int(item.get("score") or 0))) - return rows[:max_trials] - - -def default_qemu_args(elf: Path) -> list[str]: - return [ - "-nographic", - "-monitor", - "none", - "-machine", - "virt", - "-m", - "1280M", - "-kernel", - str(elf), - ] - - -def run_preflight(args: argparse.Namespace, candidate: dict[str, Any], qemu_args: list[str]) -> dict[str, Any]: - label = f"candidate{candidate['index']:02d}-pc{candidate['pc_lo'][2:]}-{candidate['pc_hi'][2:]}" - build_dir = args.build_dir / label - report_dir = build_dir / "report" - trace_dir = build_dir / "traces" - report_dir.mkdir(parents=True, exist_ok=True) - - command = [ - "bash", - str(WRAPPER), - "--build-dir", - str(build_dir), - "--elf", - str(args.elf), - "--expected-rows", - "0", - "--capture-rows", - str(args.capture_rows), - "--pc-lo", - candidate["pc_lo"], - "--pc-hi", - candidate["pc_hi"], - "--allow-block-markers", - "--allow-block-loop-reentry", - "--qemu-only", - "--expect-store-pcs", - ",".join(candidate["expected_store_pcs"]), - "--expect-load-pcs", - ",".join(candidate["expected_load_pcs"]), - "--max-seconds", - str(args.max_seconds), - "--", - *qemu_args, - ] - - timed_out = False - process = subprocess.Popen( - command, - cwd=ROOT_DIR, - text=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - start_new_session=True, - ) - try: - stdout, stderr = process.communicate(timeout=args.wrapper_timeout_seconds) - except subprocess.TimeoutExpired: - timed_out = True - os.killpg(process.pid, signal.SIGTERM) - try: - stdout, stderr = process.communicate(timeout=5) - except subprocess.TimeoutExpired: - os.killpg(process.pid, signal.SIGKILL) - stdout, stderr = process.communicate() - - (report_dir / "pc-filter-preflight.stdout.txt").write_text(stdout, encoding="utf-8") - (report_dir / "pc-filter-preflight.stderr.txt").write_text(stderr, encoding="utf-8") - raw_trace = trace_dir / "qemu.live.raw.jsonl" - preview = trace_dir / "qemu.live.expected.preview.jsonl" - raw_rows = count_rows(raw_trace) - preview_rows = count_rows(preview) - seed_audit = state_seed_audit(preview) - - if process.returncode == 0: - status = "pass" - reason = "QEMU-only PC-filter preflight passed exact memory-PC guards" - elif timed_out: - status = "timeout" - reason = "wrapper timed out before producing a passing preflight" - elif raw_rows == 0: - status = "empty" - reason = "PC filter produced no QEMU rows" - elif preview_rows == 0: - status = "reducer_failed" - reason = "PC filter produced rows, but reduced-row extraction failed before memory-PC guards passed" - elif "did not match expected" in stderr: - status = "expected_pc_mismatch" - reason = "reduced preview memory PCs did not match expected guard sequence" - else: - status = "wrapper_failed" - reason = "wrapper failed before a passing guarded QEMU-only preflight" - - return { - **candidate, - "label": label, - "status": status, - "reason": reason, - "returncode": process.returncode, - "timed_out": timed_out, - "build_dir": str(build_dir), - "raw_trace": str(raw_trace), - "preview": str(preview), - "stdout": str(report_dir / "pc-filter-preflight.stdout.txt"), - "stderr": str(report_dir / "pc-filter-preflight.stderr.txt"), - "raw_rows": raw_rows, - "preview_rows": preview_rows, - "state_seed_audit": seed_audit, - } - - -def build_summary(args: argparse.Namespace, candidates: list[dict[str, Any]], trials: list[dict[str, Any]]) -> dict[str, Any]: - pass_trials = [trial for trial in trials if trial.get("status") == "pass"] - ready_trials = [ - trial - for trial in pass_trials - if isinstance(trial.get("state_seed_audit"), dict) - and trial["state_seed_audit"].get("status") == "ready" - ] - blocked_statuses = {"empty", "reducer_failed", "expected_pc_mismatch", "timeout", "wrapper_failed"} - if ready_trials: - generated_status = "ready" - generated_reason = "At least one QEMU-only PC-filter preflight passed exact memory-PC guards and RF state-seed audit" - elif pass_trials: - generated_status = "blocked" - generated_reason = "Passing QEMU-only PC-filter preflights lacked enough visible source state for generated-RTL RF preload" - else: - generated_status = "blocked" - generated_reason = "No scanned PC-filter candidate produced a passing guarded reduced preview" - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": ( - "This is a QEMU-only PC-filter preflight search. A passing trial only " - "authorizes spending generated-RTL time on the same command shape; it " - "is not replay-LIQ proof until a generated-RTL manifest and sideband " - "activation counters pass." - ), - "inputs": { - "candidate_report": str(args.candidates), - "elf": str(args.elf), - "build_dir": str(args.build_dir), - "pc_span_limit": args.pc_span_limit, - "max_trials": args.max_trials, - "capture_rows": args.capture_rows, - "max_seconds": args.max_seconds, - }, - "summary": { - "candidate_count": len(candidates), - "trial_count": len(trials), - "pass_count": len(pass_trials), - "state_seed_ready_count": len(ready_trials), - "blocked_count": sum(1 for trial in trials if trial.get("status") in blocked_statuses), - "first_pass": pass_trials[0] if pass_trials else None, - "first_generated_rtl_ready": ready_trials[0] if ready_trials else None, - }, - "generated_rtl": { - "status": generated_status, - "reason": generated_reason, - }, - "trials": trials, - } - - -def validate_report(report: dict[str, Any]) -> list[str]: - errors: list[str] = [] - schema = report.get("schema") - if schema not in LEGACY_SCHEMAS: - errors.append("report: unexpected schema") - if report.get("status") != "pass": - errors.append("report: status must be pass") - boundary = report.get("claim_boundary") - if not isinstance(boundary, str) or "QEMU-only" not in boundary or "not replay-LIQ proof" not in boundary: - errors.append("report: claim_boundary must preserve QEMU-only proof boundary") - summary = report.get("summary") - trials = report.get("trials") - if not isinstance(summary, dict): - errors.append("summary: missing section") - summary = {} - if not isinstance(trials, list): - errors.append("trials: missing section") - trials = [] - if summary.get("trial_count") != len(trials): - errors.append("summary: trial_count mismatch") - pass_count = sum(1 for trial in trials if isinstance(trial, dict) and trial.get("status") == "pass") - if summary.get("pass_count") != pass_count: - errors.append("summary: pass_count mismatch") - seed_ready_count = sum( - 1 - for trial in trials - if isinstance(trial, dict) - and trial.get("status") == "pass" - and isinstance(trial.get("state_seed_audit"), dict) - and trial["state_seed_audit"].get("status") == "ready" - ) - if schema == SCHEMA and summary.get("state_seed_ready_count") != seed_ready_count: - errors.append("summary: state_seed_ready_count mismatch") - generated = report.get("generated_rtl") - if not isinstance(generated, dict): - errors.append("generated_rtl: missing section") - elif generated.get("status") not in {"blocked", "ready"}: - errors.append("generated_rtl: unexpected status") - for trial in trials: - if not isinstance(trial, dict): - errors.append("trials: non-object trial") - continue - if trial.get("status") not in {"pass", "empty", "reducer_failed", "expected_pc_mismatch", "timeout", "wrapper_failed"}: - errors.append(f"trials: unexpected status {trial.get('status')!r}") - seed = trial.get("state_seed_audit") - if schema == SCHEMA and trial.get("status") == "pass": - if not isinstance(seed, dict): - errors.append("trials: passing v2 trial missing state_seed_audit") - elif seed.get("status") not in {"ready", "insufficient", "unknown"}: - errors.append(f"trials: unexpected state_seed_audit status {seed.get('status')!r}") - return errors - - -def sample_report() -> dict[str, Any]: - return { - "schema": SCHEMA, - "status": "pass", - "claim_boundary": "QEMU-only preflight, not replay-LIQ proof", - "summary": {"trial_count": 2, "pass_count": 1, "state_seed_ready_count": 1}, - "generated_rtl": {"status": "ready"}, - "trials": [{"status": "empty"}, {"status": "pass", "state_seed_audit": {"status": "ready"}}], - } - - -def run_self_test() -> None: - passing = sample_report() - errors = validate_report(passing) - if errors: - raise AssertionError(f"valid sample failed validation: {errors}") - failing = copy.deepcopy(passing) - failing["summary"]["pass_count"] = 0 - if not validate_report(failing): - raise AssertionError("pass-count mismatch was not detected") - failing = copy.deepcopy(passing) - failing["trials"][0]["status"] = "unknown" - if not validate_report(failing): - raise AssertionError("bad trial status was not detected") - failing = copy.deepcopy(passing) - failing["summary"]["state_seed_ready_count"] = 0 - if not validate_report(failing): - raise AssertionError("state-seed ready-count mismatch was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--candidates", type=Path, default=DEFAULT_CANDIDATES) - parser.add_argument("--elf", type=Path, default=DEFAULT_ELF) - parser.add_argument("--build-dir", type=Path, default=DEFAULT_BUILD_DIR) - parser.add_argument("--output", type=Path, default=None) - parser.add_argument("--pc-span-limit", type=int, default=256) - parser.add_argument("--max-trials", type=int, default=12) - parser.add_argument("--capture-rows", type=int, default=32) - parser.add_argument("--max-seconds", type=int, default=30) - parser.add_argument("--wrapper-timeout-seconds", type=int, default=None) - parser.add_argument("--stop-on-pass", action="store_true") - parser.add_argument("--stop-on-generated-ready", action="store_true") - parser.add_argument("--validate-only", type=Path, default=None) - parser.add_argument("--self-test", action="store_true") - parser.add_argument("qemu_args", nargs=argparse.REMAINDER) - args = parser.parse_args(argv) - if args.pc_span_limit <= 0: - raise SystemExit("error: --pc-span-limit must be positive") - if args.max_trials <= 0: - raise SystemExit("error: --max-trials must be positive") - if args.capture_rows <= 0: - raise SystemExit("error: --capture-rows must be positive") - if args.max_seconds <= 0: - raise SystemExit("error: --max-seconds must be positive") - if args.wrapper_timeout_seconds is None: - args.wrapper_timeout_seconds = max(args.max_seconds * 2, args.max_seconds + 15) - if args.output is None: - args.output = args.build_dir / "report/pc_filter_preflight_search.json" - return args - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-pc-filter-preflight-search self-test: ok") - if args.validate_only is None: - return 0 - - if args.validate_only is not None: - report = load_json(args.validate_only) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-pc-filter-preflight-search: ok manifest={args.validate_only}") - return 0 - - candidate_report = load_json(args.candidates) - candidates = candidate_rows( - candidate_report, - pc_span_limit=args.pc_span_limit, - max_trials=args.max_trials, - ) - qemu_args = args.qemu_args - if qemu_args and qemu_args[0] == "--": - qemu_args = qemu_args[1:] - if not qemu_args: - qemu_args = default_qemu_args(args.elf) - - trials: list[dict[str, Any]] = [] - for candidate in candidates: - trial = run_preflight(args, candidate, qemu_args) - trials.append(trial) - print( - "pc-filter-preflight " - f"label={trial['label']} status={trial['status']} " - f"raw_rows={trial['raw_rows']} preview_rows={trial['preview_rows']} " - f"state_seed={trial.get('state_seed_audit', {}).get('status', 'none')}", - flush=True, - ) - if ( - args.stop_on_generated_ready - and trial["status"] == "pass" - and isinstance(trial.get("state_seed_audit"), dict) - and trial["state_seed_audit"].get("status") == "ready" - ): - break - if args.stop_on_pass and trial["status"] == "pass": - break - - report = build_summary(args, candidates, trials) - errors = validate_report(report) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - write_json(args.output, report) - print(f"replay-liq-pc-filter-preflight-search={args.output}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/chisel/top_acrc_service_integration_probe_tb.cpp b/tools/chisel/top_acrc_service_integration_probe_tb.cpp deleted file mode 100644 index 25779281..00000000 --- a/tools/chisel/top_acrc_service_integration_probe_tb.cpp +++ /dev/null @@ -1,400 +0,0 @@ -#include "VLinxCoreFrontendFetchRfAluTraceTop.h" -#include "verilated.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace { - -constexpr std::uint64_t kBasePc = 0x1000; -constexpr std::uint32_t kAcrcRaw = 0x0010302bU; -constexpr std::uint16_t kCompressedBstop = 0x0000U; -constexpr std::uint16_t kOpAcrc = 546; -constexpr std::uint16_t kOpCMovr = 573; -constexpr std::uint64_t kA0Seed = 0x0102030405060708ULL; -constexpr std::uint64_t kA7SetTidAddress = 96; -constexpr std::uint64_t kServiceReturn = 0x8877665544332211ULL; - -std::uint64_t g_cycle = 0; - -[[noreturn]] void fail(const std::string &message) { - std::cerr << "top-acrc-service-integration-probe: FAIL: " << message << "\n"; - std::exit(1); -} - -void require(bool condition, const std::string &message) { - if (!condition) { - fail(message); - } -} - -std::string hex64(std::uint64_t value) { - std::ostringstream os; - os << "0x" << std::hex << value << std::dec; - return os.str(); -} - -std::uint64_t bits(std::int64_t value, unsigned width) { - return static_cast(value) & ((1ULL << width) - 1ULL); -} - -std::uint16_t encode_c_movi(unsigned dst, std::int32_t simm5) { - return static_cast(0x16U | (bits(simm5, 5) << 6) | - (bits(dst, 5) << 11)); -} - -std::uint16_t encode_c_movr(unsigned dst, unsigned src) { - return static_cast(0x06U | (bits(src, 5) << 6) | - (bits(dst, 5) << 11)); -} - -struct RobId { - bool valid = false; - bool wrap = false; - std::uint8_t value = 0; -}; - -struct ServiceIdentity { - std::uint8_t stid = 0; - RobId bid; - RobId gid; - RobId rid; -}; - -struct ServiceRequest { - std::uint8_t request_type = 0; - ServiceIdentity identity; - std::uint64_t a0 = 0; - std::uint64_t a1 = 0; - std::uint64_t a2 = 0; - std::uint64_t a3 = 0; - std::uint64_t a4 = 0; - std::uint64_t a5 = 0; - std::uint64_t a7 = 0; -}; - -class FetchMemory { -public: - void store_insn(std::uint64_t pc, std::uint64_t raw, unsigned len) { - for (unsigned i = 0; i < len; ++i) { - bytes_[pc + i] = static_cast((raw >> (i * 8U)) & 0xffU); - } - } - - void fill_compressed_nops(std::uint64_t pc, unsigned count) { - for (unsigned i = 0; i < count; ++i) { - store_insn(pc + i * 2ULL, encode_c_movi(4 + (i % 4), 0), 2); - } - } - - std::uint64_t read_window(std::uint64_t pc) const { - std::uint64_t window = 0; - for (unsigned i = 0; i < 8; ++i) { - std::uint8_t byte = 0xffU; - const auto it = bytes_.find(pc + i); - if (it == bytes_.end()) { - if (i == 0) { - fail("fetch memory missing first byte at " + hex64(pc)); - } - } else { - byte = it->second; - } - window |= static_cast(byte) << (i * 8U); - } - return window; - } - -private: - std::map bytes_; -}; - -void clear_inputs(VLinxCoreFrontendFetchRfAluTraceTop &dut) { - dut.io_startValid = 0; - dut.io_startPc = 0; - dut.io_restartValid = 0; - dut.io_restartPc = 0; - dut.io_bfuBodyValid = 0; - dut.io_bfuHeaderPc = 0; - dut.io_bfuHSizeBytes = 0; - dut.io_bfuBSizeBytes = 0; - dut.io_frontendFlushValid = 0; - dut.io_peId = 0; - dut.io_threadId = 0; - dut.io_fetchReqReady = 1; - dut.io_fetchRespValid = 0; - dut.io_fetchRespWindow = 0; - dut.io_rfInitValid = 0; - dut.io_rfInitArchTag = 0; - dut.io_rfInitData = 0; - dut.io_deallocReady = 1; - dut.io_loadLookupData = 0; - dut.io_loadPairFirstLookupData = 0; - dut.io_reducedServiceRequest_ready = 1; - dut.io_reducedServiceResponse_valid = 0; - dut.io_reducedServiceResponse_bits_requestType = 0; - dut.io_reducedServiceResponse_bits_identity_stid = 0; - dut.io_reducedServiceResponse_bits_identity_bid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_bid_value = 0; - dut.io_reducedServiceResponse_bits_identity_bid_wrap = 0; - dut.io_reducedServiceResponse_bits_identity_gid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_gid_value = 0; - dut.io_reducedServiceResponse_bits_identity_gid_wrap = 0; - dut.io_reducedServiceResponse_bits_identity_rid_valid = 0; - dut.io_reducedServiceResponse_bits_identity_rid_value = 0; - dut.io_reducedServiceResponse_bits_identity_rid_wrap = 0; - dut.io_reducedServiceResponse_bits_a0 = 0; -} - -void eval_with_loads(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemory &mem) { - dut.eval(); - if (dut.io_loadLookupValid) { - dut.io_loadLookupData = mem.read_window(dut.io_loadLookupAddr); - dut.eval(); - } - if (dut.io_loadPairFirstLookupValid) { - dut.io_loadPairFirstLookupData = mem.read_window(dut.io_loadPairFirstLookupAddr); - dut.eval(); - } -} - -void tick(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemory &mem) { - dut.clock = 0; - eval_with_loads(dut, mem); - dut.clock = 1; - eval_with_loads(dut, mem); - dut.clock = 0; - eval_with_loads(dut, mem); - ++g_cycle; -} - -void reset(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemory &mem) { - clear_inputs(dut); - dut.reset = 1; - tick(dut, mem); - tick(dut, mem); - dut.reset = 0; - eval_with_loads(dut, mem); -} - -void init_rf(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemory &mem, - std::uint8_t arch_tag, std::uint64_t data) { - clear_inputs(dut); - dut.io_rfInitValid = 1; - dut.io_rfInitArchTag = arch_tag; - dut.io_rfInitData = data; - tick(dut, mem); - clear_inputs(dut); - eval_with_loads(dut, mem); -} - -void start_fetch(VLinxCoreFrontendFetchRfAluTraceTop &dut, const FetchMemory &mem, - std::uint64_t pc) { - clear_inputs(dut); - dut.io_startValid = 1; - dut.io_startPc = pc; - tick(dut, mem); - clear_inputs(dut); - eval_with_loads(dut, mem); -} - -ServiceRequest read_request(const VLinxCoreFrontendFetchRfAluTraceTop &dut) { - ServiceRequest request; - request.request_type = dut.io_reducedServiceRequest_bits_requestType; - request.identity.stid = dut.io_reducedServiceRequest_bits_identity_stid; - request.identity.bid.valid = dut.io_reducedServiceRequest_bits_identity_bid_valid; - request.identity.bid.value = dut.io_reducedServiceRequest_bits_identity_bid_value; - request.identity.bid.wrap = dut.io_reducedServiceRequest_bits_identity_bid_wrap; - request.identity.gid.valid = dut.io_reducedServiceRequest_bits_identity_gid_valid; - request.identity.gid.value = dut.io_reducedServiceRequest_bits_identity_gid_value; - request.identity.gid.wrap = dut.io_reducedServiceRequest_bits_identity_gid_wrap; - request.identity.rid.valid = dut.io_reducedServiceRequest_bits_identity_rid_valid; - request.identity.rid.value = dut.io_reducedServiceRequest_bits_identity_rid_value; - request.identity.rid.wrap = dut.io_reducedServiceRequest_bits_identity_rid_wrap; - request.a0 = dut.io_reducedServiceRequest_bits_a0; - request.a1 = dut.io_reducedServiceRequest_bits_a1; - request.a2 = dut.io_reducedServiceRequest_bits_a2; - request.a3 = dut.io_reducedServiceRequest_bits_a3; - request.a4 = dut.io_reducedServiceRequest_bits_a4; - request.a5 = dut.io_reducedServiceRequest_bits_a5; - request.a7 = dut.io_reducedServiceRequest_bits_a7; - return request; -} - -void drive_response(VLinxCoreFrontendFetchRfAluTraceTop &dut, - const std::optional &pending) { - if (!pending.has_value()) { - return; - } - const ServiceRequest &request = *pending; - dut.io_reducedServiceResponse_valid = 1; - dut.io_reducedServiceResponse_bits_requestType = request.request_type; - dut.io_reducedServiceResponse_bits_identity_stid = request.identity.stid; - dut.io_reducedServiceResponse_bits_identity_bid_valid = request.identity.bid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_bid_value = request.identity.bid.value; - dut.io_reducedServiceResponse_bits_identity_bid_wrap = request.identity.bid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_gid_valid = request.identity.gid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_gid_value = request.identity.gid.value; - dut.io_reducedServiceResponse_bits_identity_gid_wrap = request.identity.gid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_rid_valid = request.identity.rid.valid ? 1 : 0; - dut.io_reducedServiceResponse_bits_identity_rid_value = request.identity.rid.value; - dut.io_reducedServiceResponse_bits_identity_rid_wrap = request.identity.rid.wrap ? 1 : 0; - dut.io_reducedServiceResponse_bits_a0 = kServiceReturn; -} - -struct Observation { - bool saw_enqueue = false; - bool saw_issue_candidate = false; - bool saw_snapshot_match = false; - bool saw_request = false; - bool saw_trap = false; - bool saw_service_writeback = false; - bool saw_service_rob_complete = false; - bool saw_consumer_issue = false; - bool saw_consumer_write = false; - std::optional request; -}; - -void observe_common(const VLinxCoreFrontendFetchRfAluTraceTop &dut, Observation &obs, - std::uint64_t consumer_pc) { - obs.saw_enqueue = obs.saw_enqueue || - (dut.io_issueQueueEnqueueFire && dut.io_issueQueueInputOpcode == kOpAcrc); - obs.saw_issue_candidate = obs.saw_issue_candidate || - (dut.io_issueQueueOutputValid && dut.io_issueQueueOutputOpcode == kOpAcrc); - obs.saw_snapshot_match = obs.saw_snapshot_match || dut.io_reducedServiceSnapshotLookupMatch; - obs.saw_trap = obs.saw_trap || dut.io_reducedServiceTrappedIllegalSequence; - obs.saw_service_writeback = obs.saw_service_writeback || - (dut.io_rfWriteValid && dut.io_robCompleteArbiterSelectedService && - dut.io_rfWriteData == kServiceReturn); - obs.saw_service_rob_complete = obs.saw_service_rob_complete || - dut.io_robCompleteArbiterSelectedService; - - obs.saw_consumer_issue = obs.saw_consumer_issue || - (dut.io_executeAcceptedIdentityValid && dut.io_executeAcceptedPc == consumer_pc && - dut.io_executeAcceptedOpcode == kOpCMovr); - obs.saw_consumer_write = obs.saw_consumer_write || - (dut.io_rfWriteValid && dut.io_executeCompletePc == consumer_pc && - dut.io_rfWriteData == kServiceReturn); -} - -Observation run_program(const FetchMemory &mem, std::uint64_t start_pc, - std::uint64_t consumer_pc, bool respond_to_service) { - VLinxCoreFrontendFetchRfAluTraceTop dut; - Observation obs; - std::optional pending_fetch_pc; - std::optional pending_response; - - reset(dut, mem); - init_rf(dut, mem, 2, kA0Seed); - init_rf(dut, mem, 3, 0x3333); - init_rf(dut, mem, 4, 0x4444); - init_rf(dut, mem, 5, 0x5555); - init_rf(dut, mem, 6, 0x6666); - init_rf(dut, mem, 7, 0x7777); - init_rf(dut, mem, 9, kA7SetTidAddress); - start_fetch(dut, mem, start_pc); - - for (unsigned i = 0; i < 360; ++i) { - clear_inputs(dut); - dut.io_fetchReqReady = pending_fetch_pc.has_value() ? 0 : 1; - if (pending_fetch_pc.has_value()) { - dut.io_fetchRespValid = 1; - dut.io_fetchRespWindow = mem.read_window(*pending_fetch_pc); - } - drive_response(dut, pending_response); - eval_with_loads(dut, mem); - - observe_common(dut, obs, consumer_pc); - const bool request_fire = - dut.io_reducedServiceRequest_valid && dut.io_reducedServiceRequest_ready; - const bool response_fire = - dut.io_reducedServiceResponse_valid && dut.io_reducedServiceResponse_ready; - if (request_fire) { - ServiceRequest request = read_request(dut); - obs.saw_request = true; - obs.request = request; - if (respond_to_service) { - pending_response = request; - } - } - if (response_fire) { - pending_response.reset(); - } - const bool fetch_resp_fire = - pending_fetch_pc.has_value() && dut.io_fetchRespValid && dut.io_fetchRespReady; - const bool fetch_req_fire = !pending_fetch_pc.has_value() && - dut.io_fetchReqValid && dut.io_fetchReqReady; - const std::uint64_t next_fetch_pc = dut.io_fetchReqPc; - - tick(dut, mem); - - if (fetch_resp_fire) { - pending_fetch_pc.reset(); - } - if (fetch_req_fire) { - pending_fetch_pc = next_fetch_pc; - } - if (dut.io_commitContractError || dut.io_rfStateError || dut.io_issueQueueProtocolError) { - fail("DUT protocol error"); - } - if (respond_to_service && obs.saw_consumer_write) { - return obs; - } - if (!respond_to_service && obs.saw_trap) { - return obs; - } - } - return obs; -} - -void prove_legal_acrc_path() { - FetchMemory mem; - mem.store_insn(kBasePc, kAcrcRaw, 4); - mem.store_insn(kBasePc + 4, kCompressedBstop, 2); - mem.store_insn(kBasePc + 6, encode_c_movr(3, 2), 2); - mem.fill_compressed_nops(kBasePc + 8, 64); - - Observation obs = run_program(mem, kBasePc, kBasePc + 6, true); - require(obs.saw_enqueue, "legal ACRC was not enqueued into service path"); - require(obs.saw_issue_candidate, "legal ACRC never became a service issue candidate"); - require(obs.saw_snapshot_match, "legal ACRC did not match service snapshot identity"); - require(obs.saw_request, "legal ACRC did not fire service request"); - require(obs.request.has_value(), "legal service request was not captured"); - require(obs.request->request_type == 1, "ACRC request type was not SCT_SYS"); - require(obs.request->a0 == kA0Seed, "service request a0 did not come from initial a0 RF mapping"); - require(obs.request->a7 == kA7SetTidAddress, "service request a7 did not come from initial a7 RF mapping"); - require(obs.saw_service_rob_complete, "service completion did not select ROB completion arbiter service source"); - require(obs.saw_service_writeback, "service writeback was not the selected RF write"); - require(obs.saw_consumer_issue, "dependent consumer after C.BSTOP did not issue"); - require(obs.saw_consumer_write, "dependent consumer did not observe service a0 writeback value"); -} - -void prove_wrong_pc_stop_rejected() { - FetchMemory mem; - mem.store_insn(kBasePc, kAcrcRaw, 4); - mem.store_insn(kBasePc + 4, encode_c_movi(4, 1), 2); - mem.store_insn(kBasePc + 6, kCompressedBstop, 2); - mem.fill_compressed_nops(kBasePc + 8, 64); - - Observation obs = run_program(mem, kBasePc, kBasePc + 8, false); - require(obs.saw_enqueue, "wrong-PC ACRC was not enqueued"); - require(obs.saw_issue_candidate, "wrong-PC ACRC never became a service issue candidate"); - require(!obs.saw_request, "illegal ACRC sequence fired an external service request"); - require(obs.saw_trap, "illegal ACRC sequence did not trap"); -} - -} // namespace - -int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); - prove_legal_acrc_path(); - prove_wrong_pc_stop_rejected(); - std::cout << "top-acrc-service-integration-probe: PASS\n"; - return 0; -} diff --git a/tools/chisel/top_natural.vlt b/tools/chisel/top_natural.vlt new file mode 100644 index 00000000..6db5186d --- /dev/null +++ b/tools/chisel/top_natural.vlt @@ -0,0 +1,21 @@ +`verilator_config +public_flat_rw -module "CoreTOP" -port "io_*" +public_flat_rw -module "ROB" -port "io_headStatus*" +public_flat_rw -module "OooIexExecutionPipeline" -port "io_residentEntries*" +public_flat_rw -module "OooIexExecutionPipeline" -port "io_inFlightEntries*" +public_flat_rw -module "OooIexExecutionPipeline" -port "io_issueEmpty" +public_flat_rw -module "OooIexExecutionPipeline" -port "io_executionEmpty" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_valid" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_inFlight" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_transactionId" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_member_group_ridSlot" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_member_memberIndex" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_member_residentGeneration" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_valid" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_ready" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_specReady" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_operandClass" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_ptag" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_ptagGeneration" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_localTag" +public_flat_rw -module "OooIexIssue" -var "scheduleRows_1_*_sources_?_localSequence*" diff --git a/tools/chisel/top_natural_tb.cpp b/tools/chisel/top_natural_tb.cpp new file mode 100644 index 00000000..01467890 --- /dev/null +++ b/tools/chisel/top_natural_tb.cpp @@ -0,0 +1,760 @@ +#include "VCoreTOP.h" +#include "verilated.h" +#include "verilated_vpi.h" +#include "vpi_user.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace { + +constexpr std::uint64_t kUartAddress = 0x10000000ULL; +constexpr std::uint64_t kFinisherAddress = 0x10009000ULL; +constexpr std::uint16_t kPassCode = 0x5555U; +constexpr std::uint64_t kInstructionTranslationAccessKind = 1; +constexpr int kPageOffsetBits = 12; + +struct Arguments { + std::string memory_hex; + std::string manifest; + std::string uart_output; + std::string commit_trace; + std::uint64_t reset_sp = 0x0000000007fefff0ULL; + std::uint64_t max_cycles = 1000000; + std::uint64_t heartbeat_cycles = 10000; + std::uint64_t deadlock_cycles = 100000; + bool validate_ports = false; + int stid_count = 0; + int gpr_arch_regs = 0; + int sp_atag = 1; + int trace_width = 0; + int data_lanes = 0; + int system_issue_lanes = 0; + int retire_width = 0; +}; + +struct Response { + bool valid = false; + std::uint64_t identity = 0; + std::uint64_t generation = 0; + std::uint64_t address = 0; + std::uint64_t access_kind = 0; +}; + +struct DataRequest { + Response response; + std::uint64_t command = 0; + std::uint64_t data = 0; + std::uint64_t mask = 0; +}; + +struct Activation { + std::array trace{}; + std::uint64_t instruction_requests = 0; + std::uint64_t data_requests = 0; + std::uint64_t commits = 0; +}; + +struct LastTraceEvent { + bool valid = false; + std::uint64_t cycle = 0; + std::uint64_t source = 0; + std::uint64_t kind = 0; + std::uint64_t pc = 0; + std::uint64_t opcode = 0; + std::uint64_t instruction_valid = 0; + std::uint64_t instruction_id = 0; + std::uint64_t instruction_epoch = 0; + std::uint64_t rob_valid = 0; + std::uint64_t rid_slot = 0; + std::uint64_t member_index = 0; +}; + +std::uint64_t trace_count(const Activation &activation) { + std::uint64_t total = 0; + for (const auto count : activation.trace) total += count; + return total; +} + +std::uint64_t parse_integer(const std::string &text) { + std::size_t consumed = 0; + const auto value = std::stoull(text, &consumed, 0); + if (consumed != text.size()) throw std::runtime_error("invalid integer: " + text); + return value; +} + +Arguments parse_arguments(int argc, char **argv) { + Arguments result; + for (int index = 1; index < argc; ++index) { + const std::string option(argv[index]); + if (option == "--memory-hex" && index + 1 < argc) { + result.memory_hex = argv[++index]; + } else if (option == "--manifest" && index + 1 < argc) { + result.manifest = argv[++index]; + } else if (option == "--uart-output" && index + 1 < argc) { + result.uart_output = argv[++index]; + } else if (option == "--commit-trace" && index + 1 < argc) { + result.commit_trace = argv[++index]; + } else if (option == "--reset-sp" && index + 1 < argc) { + result.reset_sp = parse_integer(argv[++index]); + } else if (option == "--max-cycles" && index + 1 < argc) { + result.max_cycles = parse_integer(argv[++index]); + } else if (option == "--heartbeat-cycles" && index + 1 < argc) { + result.heartbeat_cycles = parse_integer(argv[++index]); + } else if (option == "--deadlock-cycles" && index + 1 < argc) { + result.deadlock_cycles = parse_integer(argv[++index]); + } else if (option == "--validate-ports") { + result.validate_ports = true; + } else if (option == "--stid-count" && index + 1 < argc) { + result.stid_count = parse_integer(argv[++index]); + } else if (option == "--gpr-arch-regs" && index + 1 < argc) { + result.gpr_arch_regs = parse_integer(argv[++index]); + } else if (option == "--sp-atag" && index + 1 < argc) { + result.sp_atag = parse_integer(argv[++index]); + } else if (option == "--trace-width" && index + 1 < argc) { + result.trace_width = parse_integer(argv[++index]); + } else if (option == "--data-lanes" && index + 1 < argc) { + result.data_lanes = parse_integer(argv[++index]); + } else if (option == "--system-issue-lanes" && index + 1 < argc) { + result.system_issue_lanes = parse_integer(argv[++index]); + } else if (option == "--retire-width" && index + 1 < argc) { + result.retire_width = parse_integer(argv[++index]); + } else { + throw std::runtime_error("unknown or incomplete option: " + option); + } + } + if (result.memory_hex.empty() || result.manifest.empty() || result.uart_output.empty()) { + throw std::runtime_error("--memory-hex, --uart-output, and --manifest are required"); + } + if (result.stid_count <= 0 || result.gpr_arch_regs <= 0 || + result.trace_width <= 0 || result.data_lanes <= 0 || + result.system_issue_lanes <= 0 || result.retire_width <= 0) { + throw std::runtime_error("profile metadata arguments are required"); + } + return result; +} + +class SparseMemory { + public: + explicit SparseMemory(const std::string &path) { + std::ifstream input(path); + if (!input) throw std::runtime_error("cannot open memory image: " + path); + std::string address; + std::string byte; + while (input >> address) { + if (!address.empty() && address.front() == '#') { + std::getline(input, byte); + continue; + } + if (!(input >> byte)) throw std::runtime_error("truncated memory image"); + bytes_[parse_integer(address)] = static_cast(parse_integer(byte)); + } + } + + std::size_t size() const { return bytes_.size(); } + + std::uint8_t read_byte(std::uint64_t address) const { + const auto found = bytes_.find(address); + return found == bytes_.end() ? 0 : found->second; + } + + std::uint64_t read_word(std::uint64_t address) const { + std::uint64_t value = 0; + for (int byte = 0; byte < 8; ++byte) { + value |= static_cast(read_byte(address + byte)) << (8 * byte); + } + return value; + } + + std::array read_line(std::uint64_t address) const { + std::array words{}; + const auto base = address & ~std::uint64_t{63}; + for (int byte = 0; byte < 64; ++byte) { + words[byte / 4] |= static_cast(read_byte(base + byte)) << (8 * (byte % 4)); + } + return words; + } + + void write(std::uint64_t address, std::uint64_t data, std::uint64_t mask) { + for (int byte = 0; byte < 8; ++byte) { + if ((mask >> byte) & 1U) bytes_[address + byte] = (data >> (8 * byte)) & 0xffU; + } + } + + private: + std::map bytes_; +}; + +class Pins { + public: + std::optional try_get(const std::string &leaf) const { + const auto handle = try_find(leaf); + if (handle == nullptr) return std::nullopt; + s_vpi_value value{}; + value.format = vpiVectorVal; + vpi_get_value(handle, &value); + const auto low = static_cast(value.value.vector[0].aval); + const auto width = vpi_get(vpiSize, handle); + if (width <= 32) return low; + const auto high = static_cast(value.value.vector[1].aval); + return low | (static_cast(high) << 32); + } + + std::uint64_t get(const std::string &leaf) const { + const auto value = try_get(leaf); + if (value.has_value()) return *value; + throw std::runtime_error("missing TOP port in VPI model: " + leaf); + } + + void put(const std::string &leaf, std::uint64_t data) const { + auto handle = find(leaf); + std::array words{}; + words[0].aval = static_cast(data); + words[1].aval = static_cast(data >> 32); + s_vpi_value value{}; + value.format = vpiVectorVal; + value.value.vector = words.data(); + vpi_put_value(handle, &value, nullptr, vpiNoDelay); + } + + void put_wide(const std::string &leaf, const std::array &data) const { + auto handle = find(leaf); + std::array words{}; + for (std::size_t index = 0; index < words.size(); ++index) words[index].aval = data[index]; + s_vpi_value value{}; + value.format = vpiVectorVal; + value.value.vector = words.data(); + vpi_put_value(handle, &value, nullptr, vpiNoDelay); + } + + private: + static vpiHandle try_find(const std::string &leaf) { + for (const auto &prefix : { + std::string("TOP.CoreTOPHarness.dut."), + std::string("TOP."), + std::string("TOP.CoreTOP."), + std::string("CoreTOP."), + std::string("TOP.dut."), std::string("CoreTOPHarness.dut."), + std::string()}) { + const auto name = prefix + leaf; + if (auto handle = vpi_handle_by_name(reinterpret_cast(const_cast(name.c_str())), nullptr)) { + return handle; + } + } + return nullptr; + } + + static vpiHandle find(const std::string &leaf) { + if (const auto handle = try_find(leaf)) return handle; + throw std::runtime_error("missing TOP port in VPI model: " + leaf); + } +}; + +void report_deadlock_state(const Pins &pins, const Arguments &arguments) { + const std::string rob = "ooo.d3s1.rob.io_headStatus_"; + for (int stid = 0; stid < arguments.stid_count; ++stid) { + const auto stem = rob + std::to_string(stid) + "_"; + const auto valid = pins.try_get(stem + "valid"); + if (!valid.has_value()) continue; + std::cout << "top-natural-rob-head stid=" << stid + << " valid=" << *valid + << " completed=" << pins.get(stem + "completed") + << " retired=" << pins.get(stem + "retired") + << " transaction=" << pins.get(stem + "transactionId") + << " pc=0x" << std::hex << pins.get(stem + "pc") + << " instruction-bits=0x" << pins.get(stem + "instructionBits") + << " opcode=0x" << pins.get(stem + "opcode") << std::dec + << " instruction-id=" << pins.get(stem + "instruction_instructionId") + << " epoch=" << pins.get(stem + "instruction_epoch") + << " rid-slot=" << pins.get(stem + "rob_ridSlot") + << " rid-generation=" << pins.get(stem + "rob_ridGeneration") + << " member-index=" << pins.get(stem + "rob_memberIndex") + << " resident-generation=" << pins.get(stem + "rob_residentGeneration") + << std::endl; + } + + const std::string iex = "iex.owner.implementation.io_"; + const auto issue_empty = pins.try_get(iex + "issueEmpty"); + const auto execution_empty = pins.try_get(iex + "executionEmpty"); + if (!issue_empty.has_value() || !execution_empty.has_value()) return; + std::cout << "top-natural-iex-state issue-empty=" << *issue_empty + << " execution-empty=" << *execution_empty; + for (int issue_class = 0; issue_class < 8; ++issue_class) { + for (int bank = 0; bank < 2; ++bank) { + const auto suffix = std::to_string(issue_class) + "_" + + std::to_string(bank); + const auto resident = pins.try_get(iex + "residentEntries_" + suffix); + const auto in_flight = pins.try_get(iex + "inFlightEntries_" + suffix); + if (!resident.has_value() || !in_flight.has_value()) continue; + std::cout << " class=" << issue_class << " bank=" << bank + << " resident=" << *resident + << " in-flight=" << *in_flight; + } + } + std::cout << std::endl; + + const std::string bru = + "iex.owner.implementation.issue.issue.issue.issue.scheduleRows_1_"; + for (int bank = 0; bank < 2; ++bank) { + const auto stem = bru + std::to_string(bank) + "_0_"; + const auto valid = pins.try_get(stem + "valid"); + if (!valid.has_value()) continue; + std::cout << "top-natural-bru-resident bank=" << bank + << " valid=" << *valid + << " in-flight=" << pins.get(stem + "inFlight") + << " transaction=" << pins.get(stem + "transactionId") + << " rid-slot=" << pins.get(stem + "member_group_ridSlot") + << " member-index=" << pins.get(stem + "member_memberIndex") + << " resident-generation=" + << pins.get(stem + "member_residentGeneration"); + for (int source = 0; source < 2; ++source) { + const auto source_stem = stem + "sources_" + + std::to_string(source) + "_"; + std::cout << " source" << source << "-valid=" + << pins.get(source_stem + "valid") + << " source" << source << "-ready=" + << pins.get(source_stem + "ready") + << " source" << source << "-spec-ready=" + << pins.get(source_stem + "specReady") + << " source" << source << "-class=" + << pins.get(source_stem + "operandClass") + << " source" << source << "-ptag=" + << pins.get(source_stem + "ptag") + << " source" << source << "-p-generation=" + << pins.get(source_stem + "ptagGeneration") + << " source" << source << "-local-tag=" + << pins.get(source_stem + "localTag") + << " source" << source << "-sequence-valid=" + << pins.get(source_stem + "localSequence_valid") + << " source" << source << "-sequence-index=" + << pins.get(source_stem + "localSequence_index") + << " source" << source << "-sequence-generation=" + << pins.get(source_stem + "localSequence_generation"); + } + std::cout << std::endl; + } +} + +std::string data_port(int lane, const std::string &suffix) { + return "io_dataMemory" + suffix.substr(0, 1) + "_" + std::to_string(lane) + suffix.substr(1); +} + +void drive_idle_inputs(const Pins &pins, const Arguments &arguments) { + pins.put("io_interrupt_valid", 0); + pins.put("io_debugRequest_valid", 0); + pins.put("io_loadReissueRequest_valid", 0); + pins.put("io_maintenance_valid", 0); + pins.put("io_debugResponse_ready", 1); + pins.put("io_cmdIssue_ready", 1); + pins.put("io_memoryFault_ready", 1); + pins.put("io_maintenanceResult_ready", 1); + pins.put("io_commit_ready", 1); + pins.put("io_trap_ready", 1); + pins.put("io_trace_ready", 1); + for (int lane = 0; lane < arguments.system_issue_lanes; ++lane) { + pins.put("io_systemIssue_" + std::to_string(lane) + "_ready", 1); + } +} + +void drive_response(const Pins &pins, const std::string &stem, const Response &response, + const SparseMemory &memory) { + pins.put(stem + "_valid", response.valid); + pins.put(stem + "_bits_identity_value", response.identity); + pins.put(stem + "_bits_identity_generation", response.generation); + pins.put(stem + "_bits_address", response.address); + const auto response_data = + response.access_kind == kInstructionTranslationAccessKind + ? response.address >> kPageOffsetBits + : memory.read_word(response.address); + pins.put(stem + "_bits_data", response_data); + pins.put_wide(stem + "_bits_lineData", memory.read_line(response.address)); + pins.put(stem + "_bits_denied", 0); + pins.put(stem + "_bits_corrupt", 0); + pins.put(stem + "_bits_errorCause", 0); + pins.put(stem + "_bits_attributesValid", 1); + pins.put(stem + "_bits_readable", 1); + pins.put(stem + "_bits_writable", 1); + pins.put(stem + "_bits_cacheable", 1); + pins.put(stem + "_bits_device", 0); +} + +Response capture_request(const Pins &pins, const std::string &stem) { + Response response; + response.valid = true; + response.identity = pins.get(stem + "_bits_identity_value"); + response.generation = pins.get(stem + "_bits_identity_generation"); + response.address = pins.get(stem + "_bits_address"); + response.access_kind = pins.get(stem + "_bits_accessKind"); + return response; +} + +void validate_top_ports(const Pins &pins, const SparseMemory &memory, + const Arguments &arguments) { + Response empty; + drive_idle_inputs(pins, arguments); + pins.put("io_pInit_valid", 0); + pins.put("io_bootstrapComplete", 0); + pins.put("io_instructionMemoryRequest_ready", 1); + drive_response(pins, "io_instructionMemoryResponse", empty, memory); + (void)capture_request(pins, "io_instructionMemoryRequest"); + for (int lane = 0; lane < arguments.data_lanes; ++lane) { + const auto request = "io_dataMemoryRequest_" + std::to_string(lane); + const auto response = "io_dataMemoryResponse_" + std::to_string(lane); + pins.put(request + "_ready", 1); + drive_response(pins, response, empty, memory); + (void)capture_request(pins, request); + } + (void)pins.get("io_bootstrapReady"); + (void)pins.get("io_commit_valid"); + (void)pins.get("io_trace_valid"); + (void)pins.get("io_lsuQuiescent"); + (void)pins.get("io_lsuProtocolError"); +} + +void write_manifest(const Arguments &arguments, const SparseMemory &memory, + const Activation &activation, std::uint64_t cycles, + const std::string &status, std::uint16_t finisher, + std::uint64_t captured, std::uint64_t mismatches) { + std::filesystem::create_directories(std::filesystem::path(arguments.manifest).parent_path()); + std::ofstream output(arguments.manifest); + if (!output) throw std::runtime_error("cannot write manifest: " + arguments.manifest); + output << "{\n" + << " \"schema\": 1,\n \"top\": \"TOP\",\n \"task\": 18,\n" + << " \"terminal_status\": \"" << status << "\",\n" + << " \"cycles\": " << cycles << ",\n" + << " \"loaded_bytes\": " << memory.size() << ",\n" + << " \"finisher_code\": " << finisher << ",\n" + << " \"captured_prefix\": " << captured << ",\n" + << " \"captured_prefix_mismatch\": " << mismatches << ",\n" + << " \"comparison_kind\": \"none\",\n" + << " \"instruction_oracle\": false,\n \"commit_oracle\": false,\n" + << " \"activation\": {\n" + << " \"IFU\": " << (activation.trace[1] + activation.instruction_requests) << ",\n" + << " \"CTU\": " << activation.trace[2] << ",\n" + << " \"OOO\": " << (activation.trace[3] + activation.commits) << ",\n" + << " \"IEX\": " << activation.trace[4] << ",\n" + << " \"LSU\": " << (activation.trace[5] + activation.data_requests) << "\n" + << " }\n}\n"; +} + +} // namespace + +int main(int argc, char **argv) { + try { + Verilated::commandArgs(argc, argv); + const auto arguments = parse_arguments(argc, argv); + SparseMemory memory(arguments.memory_hex); + std::filesystem::create_directories(std::filesystem::path(arguments.uart_output).parent_path()); + std::ofstream uart(arguments.uart_output); + if (!uart) throw std::runtime_error("cannot write UART output"); + std::ofstream commit_trace; + if (!arguments.commit_trace.empty()) { + std::filesystem::create_directories( + std::filesystem::path(arguments.commit_trace).parent_path()); + commit_trace.open(arguments.commit_trace); + if (!commit_trace) + throw std::runtime_error("cannot write commit trace: " + + arguments.commit_trace); + } + + VCoreTOP dut; + dut.reset = 1; + dut.clock = 0; + dut.eval(); + VerilatedVpi::callValueCbs(); + Pins pins; + if (arguments.validate_ports) { + validate_top_ports(pins, memory, arguments); + dut.eval(); + } + drive_idle_inputs(pins, arguments); + pins.put("io_instructionMemoryResponse_valid", 0); + for (int lane = 0; lane < arguments.data_lanes; ++lane) { + pins.put("io_dataMemoryResponse_" + std::to_string(lane) + "_valid", 0); + } + pins.put("io_pInit_valid", 0); + pins.put("io_bootstrapComplete", 0); + for (int cycle = 0; cycle < 5; ++cycle) { + dut.clock = 0; dut.eval(); dut.clock = 1; dut.eval(); + } + dut.reset = 0; + + if (arguments.validate_ports) { + bool observed_bootstrap_ready = false; + const int entries = arguments.stid_count * arguments.gpr_arch_regs; + for (int index = 0; index < entries; ++index) { + drive_idle_inputs(pins, arguments); + pins.put("io_pInit_valid", 1); + const int stid = index / arguments.gpr_arch_regs; + const int atag = index % arguments.gpr_arch_regs; + pins.put("io_pInit_bits_stid", stid); + pins.put("io_pInit_bits_atag", atag); + pins.put("io_pInit_bits_epoch", 1); + pins.put("io_pInit_bits_ptag", index); + pins.put("io_pInit_bits_generation", 0); + pins.put("io_pInit_bits_value", + atag == arguments.sp_atag ? arguments.reset_sp : 0); + pins.put("io_bootstrapComplete", 0); + dut.clock = 0; dut.eval(); VerilatedVpi::callValueCbs(); + if (!pins.get("io_pInit_ready")) + throw std::runtime_error("bootstrap validation P-map backpressured"); + observed_bootstrap_ready |= pins.get("io_bootstrapReady") != 0; + dut.clock = 1; dut.eval(); VerilatedVpi::callValueCbs(); + } + pins.put("io_pInit_valid", 0); + pins.put("io_bootstrapComplete", 1); + dut.clock = 0; dut.eval(); VerilatedVpi::callValueCbs(); + observed_bootstrap_ready |= pins.get("io_bootstrapReady") != 0; + dut.clock = 1; dut.eval(); VerilatedVpi::callValueCbs(); + observed_bootstrap_ready |= pins.get("io_bootstrapReady") != 0; + pins.put("io_bootstrapComplete", 0); + if (!observed_bootstrap_ready) + throw std::runtime_error("bootstrap validation never observed bootstrapReady"); + std::cout << "top-vpi-port-validation=pass\n" + << "top-vpi-bootstrap-validation=pass entries=" << entries << "\n"; + write_manifest(arguments, memory, Activation{}, 5 + entries + 1, + "port_validation_pass", 0, 0, 0); + dut.final(); + return 0; + } + + Response instruction_response; + std::vector data_response(arguments.data_lanes); + Activation activation; + LastTraceEvent last_trace; + std::deque recent_trace; + int init_index = 0; + bool bootstrap_pulse = false; + std::uint16_t finisher = 0; + std::string status = "timeout"; + std::uint64_t cycle = 0; + std::uint64_t last_progress_cycle = 0; + + for (; cycle < arguments.max_cycles && status == "timeout"; ++cycle) { + drive_idle_inputs(pins, arguments); + const bool initializing = init_index < arguments.stid_count * arguments.gpr_arch_regs; + pins.put("io_pInit_valid", initializing); + if (initializing) { + const int stid = init_index / arguments.gpr_arch_regs; + const int atag = init_index % arguments.gpr_arch_regs; + pins.put("io_pInit_bits_stid", stid); + pins.put("io_pInit_bits_atag", atag); + pins.put("io_pInit_bits_epoch", 1); + pins.put("io_pInit_bits_ptag", init_index); + pins.put("io_pInit_bits_generation", 0); + pins.put("io_pInit_bits_value", atag == arguments.sp_atag ? arguments.reset_sp : 0); + } + pins.put("io_bootstrapComplete", bootstrap_pulse); + + pins.put("io_instructionMemoryRequest_ready", !instruction_response.valid); + drive_response(pins, "io_instructionMemoryResponse", instruction_response, memory); + for (int lane = 0; lane < arguments.data_lanes; ++lane) { + const auto request = "io_dataMemoryRequest_" + std::to_string(lane); + const auto response = "io_dataMemoryResponse_" + std::to_string(lane); + pins.put(request + "_ready", !data_response[lane].valid); + drive_response(pins, response, data_response[lane], memory); + } + + dut.clock = 0; + dut.eval(); + VerilatedVpi::callValueCbs(); + + const bool init_fire = initializing && pins.get("io_pInit_ready"); + const bool instruction_response_fire = instruction_response.valid && + pins.get("io_instructionMemoryResponse_ready"); + const bool instruction_request_fire = !instruction_response.valid && + pins.get("io_instructionMemoryRequest_valid"); + const Response next_instruction_response = instruction_request_fire + ? capture_request(pins, "io_instructionMemoryRequest") : Response{}; + std::vector data_response_fire(arguments.data_lanes); + std::vector data_request_fire(arguments.data_lanes); + std::vector accepted_data(arguments.data_lanes); + bool any_data_response_fire = false; + bool any_data_request_fire = false; + for (int lane = 0; lane < arguments.data_lanes; ++lane) { + data_response_fire[lane] = data_response[lane].valid && + pins.get("io_dataMemoryResponse_" + std::to_string(lane) + "_ready"); + data_request_fire[lane] = !data_response[lane].valid && + pins.get("io_dataMemoryRequest_" + std::to_string(lane) + "_valid"); + any_data_response_fire |= data_response_fire[lane]; + any_data_request_fire |= data_request_fire[lane]; + if (data_request_fire[lane]) { + const auto stem = "io_dataMemoryRequest_" + std::to_string(lane); + accepted_data[lane].response = capture_request(pins, stem); + accepted_data[lane].command = pins.get(stem + "_bits_command"); + accepted_data[lane].data = pins.get(stem + "_bits_data"); + accepted_data[lane].mask = pins.get(stem + "_bits_byteMask"); + if (commit_trace && accepted_data[lane].command == 1) { + const auto &request = accepted_data[lane]; + commit_trace + << "{\"event\":\"memory_request\",\"command\":\"Write\"" + << ",\"transaction\":{\"value\":" + << request.response.identity + << ",\"generation\":" << request.response.generation << "}" + << ",\"address\":" << request.response.address + << ",\"data\":" << request.data + << ",\"mask\":" << request.mask << "}\n"; + } + } + } + + const bool trace_fire = pins.get("io_trace_valid") && + pins.get("io_trace_ready"); + if (trace_fire) { + const auto count = pins.get("io_trace_bits_count"); + for (std::uint64_t lane = 0; lane < count && lane < static_cast(arguments.trace_width); ++lane) { + const auto stem = "io_trace_bits_entries_" + std::to_string(lane) + "_"; + const auto source = pins.get(stem + "source"); + if (source < activation.trace.size()) ++activation.trace[source]; + LastTraceEvent event; + event.valid = true; + event.cycle = cycle; + event.source = source; + event.kind = pins.get(stem + "kind"); + event.pc = pins.get(stem + "pc"); + event.opcode = pins.get(stem + "opcode"); + event.instruction_valid = pins.get(stem + "instructionValid"); + event.instruction_id = pins.get(stem + "instruction_instructionId"); + event.instruction_epoch = pins.get(stem + "instruction_epoch"); + event.rob_valid = pins.get(stem + "robValid"); + event.rid_slot = pins.get(stem + "rob_ridSlot"); + event.member_index = pins.get(stem + "rob_memberIndex"); + last_trace = event; + recent_trace.push_back(event); + if (recent_trace.size() > 128) recent_trace.pop_front(); + } + } + const bool commit_fire = pins.get("io_commit_valid") && + pins.get("io_commit_ready"); + if (commit_fire) { + const auto count = pins.get("io_commit_bits_count"); + activation.commits += count; + if (commit_trace) { + const auto bounded_count = std::min( + count, static_cast(arguments.retire_width)); + for (std::uint64_t lane = 0; lane < bounded_count; ++lane) { + const auto stem = "io_commit_bits_entries_" + + std::to_string(lane) + "_"; + commit_trace + << "{\"event\":\"commit\"" + << ",\"pc\":" << pins.get(stem + "pc") + << ",\"insn\":" << pins.get(stem + "instructionBits") + << ",\"wb_valid\":" << pins.get(stem + "resultValid") + << ",\"wb_data\":" << pins.get(stem + "result") + << ",\"mem_valid\":" << pins.get(stem + "memoryValid") + << ",\"mem_is_store\":" << pins.get(stem + "memoryStore") + << ",\"transaction\":{\"value\":" + << pins.get(stem + "memory_transaction_value") + << ",\"generation\":" + << pins.get(stem + "memory_transaction_generation") << "}" + << "}\n"; + } + } + } + const bool trap_fire = pins.get("io_trap_valid") && + pins.get("io_trap_ready"); + if (trap_fire) status = "trap"; + + dut.clock = 1; + dut.eval(); + VerilatedVpi::callValueCbs(); + dut.clock = 0; + dut.eval(); + + bootstrap_pulse = false; + if (init_fire) { + ++init_index; + if (init_index == arguments.stid_count * arguments.gpr_arch_regs) bootstrap_pulse = true; + } + if (instruction_response_fire) instruction_response.valid = false; + if (instruction_request_fire) { + instruction_response = next_instruction_response; + ++activation.instruction_requests; + } + bool finisher_fire = false; + for (int lane = 0; lane < arguments.data_lanes; ++lane) { + if (data_response_fire[lane]) data_response[lane].valid = false; + if (!data_request_fire[lane]) continue; + const auto &request = accepted_data[lane]; + const auto address = request.response.address; + if (request.command == 1) { + memory.write(address, request.data, request.mask); + if (address == kUartAddress) uart.put(static_cast(request.data & 0xffU)); + if (address == kFinisherAddress) { + finisher_fire = true; + finisher = request.data & 0xffffU; + status = finisher == kPassCode ? "finisher_pass" : "finisher_fail"; + } + } + data_response[lane] = request.response; + ++activation.data_requests; + } + if (pins.get("io_lsuProtocolError")) status = "lsu_protocol_error"; + const bool architectural_progress = init_fire || + instruction_request_fire || instruction_response_fire || + any_data_request_fire || any_data_response_fire || commit_fire || + trace_fire || trap_fire || finisher_fire; + if (architectural_progress) last_progress_cycle = cycle; + if (arguments.heartbeat_cycles != 0 && cycle != 0 && + cycle % arguments.heartbeat_cycles == 0) { + std::cout << "top-natural-heartbeat cycle=" << cycle + << " commit=" << activation.commits + << " instruction=" << activation.instruction_requests + << " data=" << activation.data_requests + << " trace=" << trace_count(activation) + << std::endl; + } + if (status == "timeout" && arguments.deadlock_cycles != 0 && + cycle - last_progress_cycle >= arguments.deadlock_cycles) { + status = "deadlock"; + std::cout << "top-natural-deadlock cycle=" << cycle + << " last-progress-cycle=" << last_progress_cycle + << " last-trace-valid=" << last_trace.valid + << " last-trace-source=" << last_trace.source + << " last-trace-kind=" << last_trace.kind + << " last-trace-pc=0x" << std::hex << last_trace.pc + << " last-trace-opcode=0x" << last_trace.opcode + << std::dec << std::endl; + report_deadlock_state(pins, arguments); + std::size_t trace_index = 0; + for (const auto &event : recent_trace) { + std::cout << "top-natural-trace-event index=" << trace_index++ + << " cycle=" << event.cycle + << " source=" << event.source + << " kind=" << event.kind + << " pc=0x" << std::hex << event.pc + << " opcode=0x" << event.opcode << std::dec + << " instruction-valid=" << event.instruction_valid + << " instruction-id=" << event.instruction_id + << " epoch=" << event.instruction_epoch + << " rob-valid=" << event.rob_valid + << " rid-slot=" << event.rid_slot + << " member-index=" << event.member_index + << std::endl; + } + } + } + + uart.close(); + write_manifest(arguments, memory, activation, cycle, status, finisher, + 0, 0); + dut.final(); + const bool activated = activation.instruction_requests != 0 && activation.trace[2] != 0 && + activation.commits != 0 && activation.trace[4] != 0 && activation.data_requests != 0; + return status == "finisher_pass" && activated ? 0 : 1; + } catch (const std::exception &error) { + std::cerr << "top natural harness: " << error.what() << '\n'; + return 2; + } +} diff --git a/tools/chisel/top_verilator_harness.sv b/tools/chisel/top_verilator_harness.sv new file mode 100644 index 00000000..1537da7c --- /dev/null +++ b/tools/chisel/top_verilator_harness.sv @@ -0,0 +1,9 @@ +module CoreTOPHarness( + input logic clock, + input logic reset +); + (* keep_hierarchy = "yes" *) CoreTOP dut( + .clock(clock), + .reset(reset) + ); +endmodule diff --git a/tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py b/tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py deleted file mode 100644 index 5811a782..00000000 --- a/tools/chisel/validate_frontend_fetch_rf_alu_sideband_stats.py +++ /dev/null @@ -1,909 +0,0 @@ -#!/usr/bin/env python3 -"""Validate frontend fetch/RF/ALU sideband stats reports.""" - -from __future__ import annotations - -import argparse -import json -import sys -from pathlib import Path - - -SCHEMA = "linxcore.frontend_fetch_rf_alu.sideband_stats.v58" - -PRESETS = { - "replay-physical-suppress-selector-origin": { - "nonzero": ( - "replay_liq.wait_replay_capture_accepted", - "replay_liq.replay_queue_out_fire", - "replay_liq.liq_alloc_accepted", - "replay_liq.lret_w2_slot_accepted", - "replay_liq.w2_promotion_live", - "replay_liq.w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_selected", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "replay_liq.w2_retire_record_physical_bundle_suppress_boundary_capture", - "replay_liq.w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask", - "replay_liq.w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate", - "replay_liq.w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned", - ), - "zero": ( - "replay_liq.w2_retire_record_physical_bundle_suppress_probe_selected", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask", - "replay_liq.w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch", - ), - }, -} - -REQUIRED_REPLAY_LIQ_KEYS = [ - "cycles_sampled", - "load_lookup_valid", - "load_lookup_execute_granted", - "load_lookup_execute_with_eligible_store", - "load_lookup_execute_with_wait_store", - "execute_load_wait_hold", - "resident_store_eligible", - "resident_store_ready_forward", - "resident_store_wait_blocked", - "resident_store_wait_store_valid", - "store_stq_resident", - "store_stq_addr_ready", - "store_stq_data_ready", - "store_stq_addr_ready_not_data_ready", - "store_stq_addr_and_data_ready", - "load_lookup_execute_with_addr_ready_not_data_ready", - "load_lookup_execute_granted_first_cycle", - "load_lookup_execute_granted_last_cycle", - "store_stq_addr_ready_not_data_ready_first_cycle", - "store_stq_addr_ready_not_data_ready_last_cycle", - "store_stq_addr_and_data_ready_first_cycle", - "store_stq_addr_and_data_ready_last_cycle", - "load_lookup_execute_with_addr_ready_not_data_ready_first_cycle", - "load_lookup_execute_with_addr_ready_not_data_ready_last_cycle", - "store_sta_dequeue_fire_first_cycle", - "store_sta_dequeue_fire_last_cycle", - "store_std_dequeue_fire_first_cycle", - "store_std_dequeue_fire_last_cycle", - "store_sta_exec_valid_first_cycle", - "store_sta_exec_valid_last_cycle", - "store_std_exec_valid_first_cycle", - "store_std_exec_valid_last_cycle", - "store_sta_queue_valid", - "store_std_queue_valid", - "store_sta_queue_only_valid", - "store_sta_dequeue_fire", - "store_std_dequeue_fire", - "store_sta_exec_valid", - "store_std_exec_valid", - "store_sta_exec_only_valid", - "resident_store_wake_valid", - "resident_store_wake_ready", - "wait_replay_capture_accepted", - "wait_replay_clear_valid", - "wait_replay_relaunch_valid", - "replay_queue_enqueue_accepted", - "replay_queue_out_valid", - "replay_queue_out_fire", - "liq_alloc_valid", - "liq_alloc_accepted", - "liq_launch_valid", - "liq_launch_accepted", - "liq_return_complete_repick_mask_nonzero", - "liq_return_complete_source_returned_mask_nonzero", - "liq_return_complete_data_complete_mask_nonzero", - "liq_return_complete_request_complete_mask_nonzero", - "liq_return_complete_candidate_mask_nonzero", - "liq_return_complete_mask_nonzero", - "liq_return_complete_valid", - "liq_return_complete_candidate_count_nonzero", - "liq_return_complete_valid_w2_occupied", - "liq_base_lookup_valid", - "liq_base_lookup_granted", - "liq_base_data_returned", - "liq_base_line_valid_mask_nonzero", - "launch_readiness_candidate_valid", - "launch_readiness_base_data_ready", - "launch_readiness_sources_returned", - "launch_readiness_ready", - "launch_readiness_enable", - "launch_readiness_blocked_by_disabled", - "launch_readiness_blocked_by_no_candidate", - "launch_readiness_blocked_by_base_lookup", - "launch_readiness_blocked_by_base_data", - "launch_readiness_blocked_by_scb", - "launch_readiness_blocked_by_return", - "liq_wait_store_mask_nonzero", - "liq_replay_wake_valid", - "liq_replay_wake_active", - "liq_replay_wake_wait_store_candidate", - "liq_replay_wake_bid_match", - "liq_replay_wake_lsid_match", - "liq_replay_wake_pc_match", - "liq_replay_wake_full_match", - "liq_replay_wake_store_unit", - "liq_replay_wake_store_unit_full_match", - "liq_replay_wake_store_unit_full_match_active", - "liq_replay_wake_store_unit_full_match_flush_blocked", - "liq_replay_wake_wait_store_clear", - "source_return_candidate_valid", - "source_return_store_snapshot_ready", - "source_return_store_source_returned", - "source_return_scb_source_returned", - "source_return_source_returned", - "source_return_blocked_by_disabled", - "source_return_blocked_by_no_candidate", - "source_return_blocked_by_base_data", - "source_return_blocked_by_store_snapshot", - "source_return_blocked_by_scb", - "source_return_store_snapshot_live_request_active", - "source_return_store_snapshot_live_evidence_valid", - "source_return_scb_live_active", - "source_return_scb_live_request_active", - "source_return_scb_live_evidence_valid", - "source_return_scb_live_pending", - "source_return_scb_live_returned", - "source_return_scb_live_blocked_by_request_disabled", - "source_return_scb_live_blocked_by_no_pending", - "source_return_scb_live_blocked_by_scb_return", - "source_return_query_issued", - "source_return_response_apply_valid", - "source_return_row_state_plan_valid", - "source_return_candidate_w2_occupied", - "source_return_store_snapshot_ready_w2_occupied", - "source_return_query_issued_w2_occupied", - "source_return_response_apply_w2_occupied", - "source_row_mutation_candidate_valid", - "source_row_mutation_live_permit", - "source_row_mutation_request_valid", - "source_row_mutation_blocked_by_head_proof", - "source_row_mutation_blocked_by_live_disabled", - "source_row_mutation_request_w2_occupied", - "return_data_candidate_valid", - "return_data_request_mask_nonzero", - "return_data_bytes_complete", - "return_data_cross_line", - "return_data_size_supported", - "return_data_valid", - "return_data_blocked_by_disabled", - "return_data_blocked_by_no_candidate", - "return_data_blocked_by_zero_size", - "return_data_blocked_by_unsupported_size", - "return_data_blocked_by_cross_line", - "return_data_blocked_by_incomplete_bytes", - "return_publish_candidate_valid", - "return_publish_data_ready", - "return_publish_ready", - "return_publish_blocked_by_no_candidate", - "return_publish_blocked_by_data", - "return_publish_blocked_by_consumer", - "return_publish_candidate_w2_occupied", - "return_publish_ready_w2_occupied", - "lret_payload_candidate_valid", - "lret_payload_valid", - "lret_payload_wakeup_required", - "lret_payload_blocked_by_no_candidate", - "lret_payload_blocked_by_data", - "lret_payload_candidate_w2_occupied", - "lret_payload_valid_w2_occupied", - "publish_control_candidate_valid", - "publish_control_live_enable", - "publish_control_armed", - "publish_control_fire", - "publish_control_blocked_by_no_payload", - "publish_control_blocked_by_publish", - "publish_control_blocked_by_side_effects", - "publish_control_blocked_by_live_disabled", - "publish_control_candidate_w2_occupied", - "publish_control_live_enable_w2_occupied", - "publish_control_armed_w2_occupied", - "publish_control_fire_w2_occupied", - "publish_request_valid", - "publish_request_lret", - "publish_request_writeback", - "publish_request_wakeup", - "publish_request_mask_nonzero", - "publish_request_blocked_by_no_fire", - "publish_request_invalid_fire_without_payload", - "lret_sink_enqueue_ready", - "lret_sink_enqueue_accepted", - "lret_sink_enqueue_dropped", - "lret_sink_drain_valid", - "lret_sink_drain_fire", - "lret_sink_pending", - "lret_sink_full", - "lret_sink_blocked_by_no_payload", - "lret_sink_blocked_by_full", - "lret_sink_blocked_by_drain", - "lret_sink_enqueue_ready_w2_occupied", - "lret_sink_enqueue_accepted_w2_occupied", - "lret_sink_enqueue_dropped_w2_occupied", - "lret_sink_enqueue_accepted_same_cycle_drain_fire", - "lret_sink_enqueue_accepted_same_cycle_drain_fire_w2_occupied", - "lret_sink_enqueue_accepted_w2_without_drain_fire", - "lret_sink_enqueue_accepted_w2_completion_clear_slot", - "lret_sink_enqueue_accepted_w2_clear_intent", - "lret_sink_enqueue_accepted_w2_side_effect_fire_complete", - "lret_sink_enqueue_accepted_w2_live_clear", - "lret_sink_followup_after_enqueue_accepted_w2", - "lret_sink_followup_w2_still_occupied", - "lret_sink_followup_w2_cleared", - "lret_sink_followup_after_enqueue_completion_clear_slot", - "lret_sink_followup_after_enqueue_completion_clear_slot_w2_cleared", - "lret_sink_followup_after_enqueue_clear_intent", - "lret_sink_followup_after_enqueue_clear_intent_w2_cleared", - "lret_sink_followup_after_enqueue_side_effect_fire_complete", - "lret_sink_followup_after_enqueue_side_effect_fire_complete_w2_cleared", - "lret_sink_followup_after_enqueue_live_clear", - "lret_sink_followup_after_enqueue_live_clear_w2_cleared", - "lret_sink_pending_after_enqueue_accepted_w2", - "lret_sink_drain_valid_after_enqueue_accepted_w2", - "lret_sink_drain_fire_after_enqueue_accepted_w2", - "lret_drain_permit_ready_after_enqueue_accepted_w2", - "lret_drain_permit_pipe_free_after_enqueue_accepted_w2", - "lret_drain_permit_pipe_full_after_enqueue_accepted_w2", - "lret_sink_pending_w2_occupied", - "lret_sink_drain_valid_w2_occupied", - "lret_sink_drain_fire_w2_occupied", - "w2_retire_record_capture_candidate", - "w2_retire_record_payload_valid", - "w2_retire_record_capture_valid", - "w2_retire_record_capture_ready", - "w2_retire_record_capture_accepted", - "w2_retire_record_capture_accepted_w2_occupied", - "w2_retire_record_capture_dropped", - "w2_retire_record_record_valid", - "w2_retire_record_record_ready", - "w2_retire_record_record_fire", - "w2_retire_record_pending", - "w2_retire_record_captured_with_lret_enqueue", - "w2_retire_record_record_from_lret_enqueue", - "w2_retire_record_blocked_by_invalid_payload", - "w2_retire_record_blocked_by_full", - "lret_commit_history_load_rows", - "lret_shadow_enqueue", - "lret_shadow_enqueue_after_prior_commit", - "lret_shadow_drain", - "lret_shadow_drain_missing", - "lret_shadow_drain_after_prior_commit", - "lret_shadow_free_after_prior_commit", - "lret_drain_permit_any_pipe_free", - "lret_drain_permit_ready", - "lret_drain_permit_blocked_by_no_entry", - "lret_drain_permit_blocked_by_pipe_full", - "lret_drain_permit_pipe_occupied", - "lret_iex_data_rob_row_valid", - "lret_iex_data_rob_row_need_flush", - "lret_iex_data_rob_row_blocked_by_invalid_rid", - "lret_iex_data_rob_row_blocked_by_free", - "lret_iex_data_rob_row_blocked_by_stale_rid", - "lret_iex_data_candidate_valid", - "lret_iex_data_would_drain", - "lret_iex_data_set_mem_data_valid", - "lret_iex_data_blocked_by_disabled", - "lret_iex_data_blocked_by_flush", - "lret_iex_data_blocked_by_no_entry", - "lret_iex_data_blocked_by_invalid_entry", - "lret_iex_data_blocked_by_drain", - "lret_iex_data_blocked_by_rob_missing", - "lret_iex_data_blocked_by_need_flush", - "lret_rob_resolve_candidate_valid", - "lret_rob_resolve_valid", - "lret_rob_resolve_ready_for_pipe_insert", - "lret_rob_resolve_mark_all_destinations_data_valid", - "lret_rob_resolve_mark_destination_data_valid", - "lret_rob_resolve_ret_lane_increment", - "lret_rob_resolve_blocked_by_disabled", - "lret_rob_resolve_blocked_by_flush", - "lret_rob_resolve_blocked_by_no_set_mem_data", - "lret_rob_resolve_blocked_by_unsupported_multi_lane", - "lret_rob_resolve_blocked_by_invalid_rid", - "lret_rob_resolve_blocked_by_no_destination", - "lret_lane_completion_candidate_valid", - "lret_lane_completion_complete_valid", - "lret_lane_completion_ready_for_pipe_insert", - "lret_lane_completion_requires_all_lanes", - "lret_lane_completion_blocked_by_disabled", - "lret_lane_completion_blocked_by_flush", - "lret_lane_completion_blocked_by_no_resolve", - "lret_lane_completion_blocked_by_zero_returned_lanes", - "lret_lane_completion_blocked_by_invalid_real_req_cnt", - "lret_lane_completion_blocked_by_scalar_load_pair_incomplete", - "lret_lane_completion_blocked_by_vector_mem_incomplete", - "lret_tload_completion_candidate_valid", - "lret_tload_completion_tload_candidate_valid", - "lret_tload_completion_tile_scb_send_valid", - "lret_tload_completion_tile_scb_is_last", - "lret_tload_completion_complete_valid", - "lret_tload_completion_ready_for_pipe_insert", - "lret_tload_completion_blocked_by_disabled", - "lret_tload_completion_blocked_by_flush", - "lret_tload_completion_blocked_by_no_lane_completion", - "lret_tload_completion_blocked_by_invalid_sub_inst_cnt", - "lret_tload_completion_blocked_by_tload_pending", - "lret_final_metadata_candidate_valid", - "lret_final_metadata_is_load_return_marked", - "lret_final_metadata_load_branch_resolve_called", - "lret_final_metadata_load_branch_resolve_side_effect_valid", - "lret_final_metadata_pipe_cycle_sideband_valid", - "lret_final_metadata_ready_for_pipe_insert", - "lret_final_metadata_blocked_by_disabled", - "lret_final_metadata_blocked_by_flush", - "lret_final_metadata_blocked_by_no_tload_completion", - "lret_timing_stats_candidate_valid", - "lret_timing_stats_sideband_valid", - "lret_timing_stats_iq_name_sideband_valid", - "lret_timing_stats_ld_rnt_cycle_valid", - "lret_timing_stats_update_valid", - "lret_timing_stats_latency_underflow", - "lret_timing_stats_ready_for_pipe_insert", - "lret_timing_stats_blocked_by_disabled", - "lret_timing_stats_blocked_by_flush", - "lret_timing_stats_blocked_by_no_final_metadata", - "lret_iex_insert_candidate_valid", - "lret_iex_insert_valid", - "lret_iex_insert_is_load_return", - "lret_iex_insert_wakeup_required", - "lret_iex_insert_blocked_by_no_set_mem_data", - "lret_iex_insert_blocked_by_no_pipe", - "lret_iex_insert_blocked_by_invalid_rid", - "lret_iex_insert_candidate_w2_occupied", - "lret_iex_insert_valid_w2_occupied", - "lret_residency_candidate_valid", - "lret_residency_write_valid", - "lret_residency_live_enable", - "lret_residency_blocked_by_live_disabled", - "lret_residency_slot_accepted", - "lret_residency_slot_occupied", - "lret_residency_advance_candidate_valid", - "lret_residency_advance_valid", - "lret_residency_advance_blocked_by_advance_disabled", - "lret_residency_candidate_w2_occupied", - "lret_residency_write_w2_occupied", - "lret_residency_slot_w2_occupied", - "lret_residency_advance_candidate_w2_occupied", - "lret_residency_advance_valid_w2_occupied", - "lret_w1_slot_accepted", - "lret_w1_slot_occupied", - "lret_w1_advance_candidate_valid", - "lret_w1_advance_valid", - "lret_w1_advance_blocked_by_advance_disabled", - "lret_w1_slot_w2_occupied", - "lret_w1_advance_candidate_w2_occupied", - "lret_w1_advance_valid_w2_occupied", - "lret_w2_slot_accepted", - "lret_w2_slot_occupied", - "lret_w2_slot_blocked_by_no_write", - "lret_w2_slot_source_trace_valid", - "w2_atomic_live_active", - "w2_atomic_request_active", - "w2_atomic_evidence_valid", - "w2_atomic_side_effect_live_requested", - "w2_atomic_promotion_requested", - "w2_atomic_blocked", - "w2_atomic_blocked_by_request_disabled", - "w2_atomic_blocked_by_no_evidence", - "w2_atomic_blocked_by_mode_disabled", - "w2_atomic_blocked_by_policy", - "w2_atomic_blocked_by_no_side_effect_sink", - "w2_atomic_blocked_by_no_clear_commit", - "w2_atomic_blocked_by_no_row_fill_candidate", - "w2_atomic_blocked_by_no_lifecycle_row", - "w2_atomic_blocked_by_no_required_side_effect", - "w2_side_effect_candidate_valid", - "w2_side_effect_ready", - "w2_side_effect_live_all_required_enabled", - "w2_side_effect_fire_valid", - "w2_side_effect_fire_complete", - "w2_clear_intent", - "w2_clear_commit_ready", - "w2_promotion_live", - "w2_promotion_live_clear", - "w2_promotion_advance_live", - "w2_promotion_blocked", - "w2_promotion_blocked_by_promotion_disabled", - "w2_promotion_blocked_by_clear_intent", - "w2_promotion_invalid_clear_without_slot", - "w2_refill_ready_empty", - "w2_refill_ready_same_cycle_eligible", - "w2_refill_ready_same_cycle_ready", - "w2_refill_ready_future_advance", - "w2_refill_ready_matches_current", - "w2_refill_ready_blocked", - "w2_refill_ready_invalid_live_clear_without_intent", - "w2_slot_replace_empty_write_eligible", - "w2_slot_replace_same_cycle_eligible", - "w2_slot_replace_same_cycle_ready", - "w2_slot_replace_future_write_accept", - "w2_slot_replace_matches_current", - "w2_slot_replace_blocked", - "w2_slot_replace_blocked_by_current_storage", - "w2_slot_replace_invalid_future_ready_without_live_clear", - "w2_slot_replace_overlap_candidate_occupied", - "w2_slot_replace_overlap_candidate_clear_intent", - "w2_slot_replace_overlap_candidate_live_clear", - "w2_slot_replace_overlap_live_clear_same_lsid", - "w2_slot_replace_overlap_live_clear_different_lsid", - "w2_slot_replace_overlap_live_clear_unknown_lsid", - "w2_slot_replace_live_clear_without_w1_candidate", - "w2_slot_replace_w1_candidate_without_live_clear", - "w2_slot_replace_advance_valid_on_live_clear", - "w2_slot_replace_w1_candidate_cycle_before_clear_intent", - "w2_slot_replace_w1_candidate_cycle_before_live_clear", - "w2_slot_replace_clear_intent_cycle_before_w1_candidate", - "w2_slot_replace_live_clear_cycle_before_w1_candidate", - "w2_slot_replace_live_clear_after_w1_candidate_gap2", - "w2_slot_replace_live_clear_after_w1_candidate_gap3", - "w2_slot_replace_live_clear_after_w1_candidate_gap4", - "w2_slot_replace_live_clear_after_w1_candidate_gap5_plus", - "w2_slot_replace_w1_candidate_after_live_clear_gap2", - "w2_slot_replace_w1_candidate_after_live_clear_gap3", - "w2_slot_replace_w1_candidate_after_live_clear_gap4", - "w2_slot_replace_w1_candidate_after_live_clear_gap5_plus", - "w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap2", - "w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap3", - "w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap4", - "w2_slot_replace_different_lsid_live_clear_after_w1_candidate_gap5_plus", - "w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap2", - "w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap3", - "w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap4", - "w2_slot_replace_different_lsid_w1_candidate_after_live_clear_gap5_plus", - "w2_slot_replace_live_clear_after_w1_candidate_same_lsid", - "w2_slot_replace_live_clear_after_w1_candidate_different_lsid", - "w2_slot_replace_live_clear_after_w1_candidate_unknown_lsid", - "w2_advance_enable", - "w2_advance_replace_on_clear", - "w2_advance_uses_future_advance", - "w2_advance_blocked", - "w2_advance_blocked_by_live_promotion_disabled", - "w2_advance_invalid_future_write_without_advance", - "w2_commit_row_trace_source_ready", - "w2_commit_row_trace_source_instruction_ready", - "w2_commit_row_trace_source_source_ready", - "w2_commit_row_trace_source_blocked", - "w2_commit_row_trace_source_blocked_by_no_metadata", - "w2_commit_row_trace_source_blocked_by_no_source_trace", - "w2_commit_row_trace_source_rob_lookup_row_valid", - "w2_commit_row_trace_source_rob_lookup_instruction_valid", - "w2_commit_row_trace_source_rob_lookup_blocked_by_need_flush", - "w2_commit_row_trace_source_rob_lookup_blocked_by_missing_instruction", - "w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_disabled", - "w2_commit_row_trace_source_rob_lookup_blocked_by_source_trace_before_completion", - "w2_commit_row_candidate_valid", - "w2_commit_row_fill_candidate", - "w2_commit_row_complete_candidate", - "w2_commit_row_candidate_blocked", - "w2_commit_row_candidate_blocked_by_no_metadata", - "w2_commit_row_candidate_blocked_by_no_source_trace", - "w2_commit_row_candidate_blocked_by_invalid_size", - "w2_commit_row_candidate_blocked_by_non_gpr_destination", - "w2_commit_row_candidate_blocked_by_row_fill_disabled", - "w2_retire_record_commit_row_candidate_valid", - "w2_retire_record_commit_row_fill_candidate", - "w2_retire_record_commit_row_complete_candidate", - "w2_retire_record_commit_row_candidate_blocked", - "w2_retire_record_commit_row_candidate_blocked_by_no_record", - "w2_retire_record_commit_row_candidate_blocked_by_no_metadata", - "w2_retire_record_commit_row_candidate_blocked_by_no_source_trace", - "w2_retire_record_commit_row_candidate_blocked_by_invalid_size", - "w2_retire_record_commit_row_candidate_blocked_by_non_gpr_destination", - "w2_retire_record_commit_row_candidate_blocked_by_row_fill_disabled", - "w2_retire_record_instruction_metadata_capture_intent", - "w2_retire_record_instruction_metadata_capture_payload_rid_valid", - "w2_retire_record_instruction_metadata_w2_rid_valid", - "w2_retire_record_instruction_metadata_w2_rid_matches_capture", - "w2_retire_record_instruction_metadata_w2_metadata_ready", - "w2_retire_record_instruction_metadata_capture_from_w2", - "w2_retire_record_instruction_metadata_capture_from_drain", - "w2_retire_record_instruction_metadata_capture_blocked_by_no_payload_rid", - "w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_rid", - "w2_retire_record_instruction_metadata_capture_blocked_by_rid_mismatch", - "w2_retire_record_instruction_metadata_capture_blocked_by_no_w2_metadata", - "w2_retire_record_instruction_metadata_clear_accepted", - "w2_retire_record_instruction_metadata_provider_valid", - "w2_row_fill_candidate_valid", - "w2_row_fill_prerequisites_ready", - "w2_row_fill_enable", - "w2_row_fill_blocked_by_request_disabled", - "w2_row_fill_blocked_by_no_candidate", - "w2_row_fill_blocked_by_no_side_effect_commit", - "w2_row_fill_blocked_by_no_clear_commit", - "w2_row_fill_blocked_by_live_clear_disabled", - "w2_row_fill_blocked_by_no_replay_row_lifecycle", - "w2_lifecycle_candidate_valid", - "w2_lifecycle_slot_identity_valid", - "w2_lifecycle_resolved_row_match", - "w2_lifecycle_row_clear_ready", - "w2_lifecycle_ready", - "w2_lifecycle_blocked_by_no_resolved_row", - "w2_lifecycle_blocked_by_multiple_resolved_rows", - "w2_lifecycle_blocked_by_clear_disabled", - "w2_lifecycle_clear_request_enable", - "w2_lifecycle_clear_commit_enable", - "w2_retire_record_lifecycle_candidate_valid", - "w2_retire_record_lifecycle_slot_identity_valid", - "w2_retire_record_lifecycle_resolved_row_match", - "w2_retire_record_lifecycle_row_clear_ready", - "w2_retire_record_lifecycle_blocked_by_no_resolved_row", - "w2_retire_record_lifecycle_blocked_by_multiple_resolved_rows", - "w2_retire_record_lifecycle_blocked_by_clear_disabled", - "w2_retire_record_lifecycle_request_candidate", - "w2_retire_record_lifecycle_live_promotion_candidate", - "w2_retire_record_lifecycle_request_blocked_by_no_lifecycle_row", - "w2_retire_record_lifecycle_request_blocked_by_no_atomic_request", - "w2_retire_record_lifecycle_request_blocked_by_no_row_fill_candidate", - "w2_retire_record_lifecycle_request_blocked_by_no_row_fill_enable", - "w2_retire_record_atomic_request_evidence_valid", - "w2_retire_record_atomic_request_row_fill_candidate_aligned", - "w2_retire_record_atomic_request_row_fill_enable_aligned", - "w2_retire_record_atomic_request_blocked_by_no_lifecycle_row", - "w2_retire_record_atomic_request_blocked_by_no_row_fill_candidate", - "w2_retire_record_atomic_request_blocked_by_no_row_fill_enable", - "w2_retire_record_row_fill_enable_request_evidence_valid", - "w2_retire_record_row_fill_enable_candidate_aligned", - "w2_retire_record_row_fill_enable", - "w2_retire_record_row_fill_enable_blocked_by_request_disabled", - "w2_retire_record_row_fill_enable_blocked_by_no_lifecycle_row", - "w2_retire_record_row_fill_enable_blocked_by_no_row_fill_candidate", - "w2_retire_record_lifecycle_evidence_capture_intent", - "w2_retire_record_lifecycle_evidence_capture_from_lifecycle", - "w2_retire_record_lifecycle_evidence_capture_blocked_by_no_lifecycle", - "w2_retire_record_lifecycle_evidence_clear_accepted", - "w2_retire_record_lifecycle_evidence_provider_valid", - "w2_retire_record_lifecycle_evidence_provider_valid_without_record", - "w2_retire_record_lifecycle_evidence_record_valid_without_provider", - "w2_retire_record_lifecycle_clear_fallback_capture_physical_clear", - "w2_retire_record_lifecycle_clear_fallback_candidate", - "w2_retire_record_lifecycle_clear_fallback_duplicate_physical_clear", - "w2_retire_record_lifecycle_clear_fallback_clear_valid", - "w2_retire_record_rob_fallback_capture_physical_complete", - "w2_retire_record_rob_fallback_candidate", - "w2_retire_record_rob_fallback_duplicate_physical_complete", - "w2_retire_record_rob_fallback_complete_valid", - "w2_retire_record_rf_fallback_capture_physical_writeback", - "w2_retire_record_rf_fallback_candidate", - "w2_retire_record_rf_fallback_duplicate_physical_writeback", - "w2_retire_record_rf_fallback_writeback_valid", - "w2_retire_record_wakeup_fallback_capture_physical_wakeup", - "w2_retire_record_wakeup_fallback_candidate", - "w2_retire_record_wakeup_fallback_duplicate_physical_wakeup", - "w2_retire_record_wakeup_fallback_wakeup_valid", - "w2_retire_record_fallback_owner_policy_candidate", - "w2_retire_record_fallback_owner_policy_all_candidates_ready", - "w2_retire_record_fallback_owner_policy_blocked_by_physical_duplicate", - "w2_retire_record_fallback_owner_policy_no_physical_probe_active", - "w2_retire_record_fallback_owner_policy_fallback_emit_probe_active", - "w2_retire_record_fallback_owner_policy_fallback_live_probe_active", - "w2_retire_record_fallback_owner_policy_retained_sole_owner_eligible", - "w2_retire_record_fallback_owner_policy_blocked_by_global_fallback_disabled", - "w2_retire_record_fallback_owner_policy_side_effect_enable", - "w2_retire_record_rob_fallback_live_complete_selected", - "w2_retire_record_rf_fallback_live_writeback_selected", - "w2_retire_record_wakeup_fallback_live_wakeup_selected", - "w2_retire_record_lifecycle_clear_fallback_live_clear_selected", - "w2_retire_record_model_order_record_candidate", - "w2_retire_record_model_order_return_side_effects_ready", - "w2_retire_record_model_order_retire_clear_evidence_ready", - "w2_retire_record_model_order_return_then_retire_ready", - "w2_retire_record_model_order_fallback_owner_eligible", - "w2_retire_record_model_order_blocked_by_missing_return_side_effect", - "w2_retire_record_model_order_blocked_by_missing_retire_clear_evidence", - "w2_retire_record_model_order_blocked_by_owner_disabled", - "w2_retire_record_default_promotion_record_candidate", - "w2_retire_record_default_promotion_pre_arm_model_order_ready", - "w2_retire_record_default_promotion_any_physical_duplicate", - "w2_retire_record_default_promotion_ready", - "w2_retire_record_default_promotion_blocked_by_no_record", - "w2_retire_record_default_promotion_blocked_by_missing_fallback_candidate", - "w2_retire_record_default_promotion_blocked_by_missing_lifecycle_evidence", - "w2_retire_record_default_promotion_blocked_by_physical_duplicate", - "w2_retire_record_default_promotion_blocked_by_probe_active", - "w2_retire_record_duplicate_vector_valid", - "w2_retire_record_duplicate_vector_return_side_effect_bundle", - "w2_retire_record_duplicate_vector_model_order_bundle", - "w2_retire_record_duplicate_vector_partial", - "w2_retire_record_duplicate_vector_single", - "w2_retire_record_duplicate_vector_multi", - "w2_retire_record_duplicate_vector_count_sum", - "w2_retire_record_duplicate_vector_next_requires_bundle_transfer", - "w2_retire_record_duplicate_vector_blocked_by_no_record", - "w2_retire_record_duplicate_vector_blocked_by_pre_arm_not_ready", - "w2_retire_record_duplicate_vector_blocked_by_no_duplicate", - "w2_retire_record_bundle_transfer_plan_candidate", - "w2_retire_record_bundle_transfer_plan_pre_arm_ready", - "w2_retire_record_bundle_transfer_plan_model_order_bundle", - "w2_retire_record_bundle_transfer_plan_default_transfer_candidate", - "w2_retire_record_bundle_transfer_plan_requires_physical_bundle_suppression", - "w2_retire_record_bundle_transfer_plan_default_promotion_already_ready", - "w2_retire_record_bundle_transfer_plan_blocked_by_no_record", - "w2_retire_record_bundle_transfer_plan_blocked_by_pre_arm_not_ready", - "w2_retire_record_bundle_transfer_plan_blocked_by_no_duplicate_vector", - "w2_retire_record_bundle_transfer_plan_blocked_by_partial_duplicate", - "w2_retire_record_bundle_transfer_plan_blocked_by_probe_active", - "w2_retire_record_physical_bundle_suppress_plan_transfer_candidate", - "w2_retire_record_physical_bundle_suppress_plan_suppression_required", - "w2_retire_record_physical_bundle_suppress_plan_physical_bundle_complete", - "w2_retire_record_physical_bundle_suppress_plan_atomic_suppress_candidate", - "w2_retire_record_physical_bundle_suppress_plan_suppress_rob_complete", - "w2_retire_record_physical_bundle_suppress_plan_suppress_rf_writeback", - "w2_retire_record_physical_bundle_suppress_plan_suppress_wakeup", - "w2_retire_record_physical_bundle_suppress_plan_suppress_lifecycle_clear", - "w2_retire_record_physical_bundle_suppress_plan_suppress_mask_sum", - "w2_retire_record_physical_bundle_suppress_plan_all_or_none_suppress", - "w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_transfer_candidate", - "w2_retire_record_physical_bundle_suppress_plan_blocked_by_no_suppression_requirement", - "w2_retire_record_physical_bundle_suppress_plan_blocked_by_incomplete_physical_bundle", - "w2_retire_record_physical_bundle_suppress_probe_candidate", - "w2_retire_record_physical_bundle_suppress_probe_enabled_candidate", - "w2_retire_record_physical_bundle_suppress_probe_selected", - "w2_retire_record_physical_bundle_suppress_probe_selected_mask_sum", - "w2_retire_record_physical_bundle_suppress_probe_all_or_none_input_mask", - "w2_retire_record_physical_bundle_suppress_probe_blocked_by_probe_disabled", - "w2_retire_record_physical_bundle_suppress_probe_blocked_by_no_atomic_candidate", - "w2_retire_record_physical_bundle_suppress_probe_blocked_by_partial_mask", - "w2_retire_record_physical_bundle_suppress_select_plan_promoted_candidate", - "w2_retire_record_physical_bundle_suppress_select_selected", - "w2_retire_record_physical_bundle_suppress_select_selected_mask_sum", - "w2_retire_record_physical_bundle_suppress_select_all_or_none_input_mask", - "w2_retire_record_physical_bundle_suppress_select_selected_from_probe", - "w2_retire_record_physical_bundle_suppress_select_selected_from_promotion", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_promote_disabled", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_no_plan_candidate", - "w2_retire_record_physical_bundle_suppress_select_blocked_by_partial_plan_mask", - "w2_retire_record_physical_bundle_suppress_select_invalid_probe_promotion_mask_mismatch", - "w2_retire_record_physical_bundle_suppress_boundary_capture", - "w2_retire_record_physical_bundle_suppress_boundary_registered_valid", - "w2_retire_record_physical_bundle_suppress_boundary_registered_mask_sum", - "w2_retire_record_physical_bundle_suppress_boundary_registered_full_mask", - "w2_retire_record_physical_bundle_suppress_boundary_blocked_by_no_selection", - "w2_retire_record_physical_bundle_suppress_boundary_blocked_by_partial_mask", - "w2_retire_record_physical_bundle_suppress_boundary_cleared_by_flush", - "w2_retire_record_physical_bundle_suppress_identity_capture_identity", - "w2_retire_record_physical_bundle_suppress_identity_captured_identity_valid", - "w2_retire_record_physical_bundle_suppress_identity_registered_candidate", - "w2_retire_record_physical_bundle_suppress_identity_retained_record_aligned", - "w2_retire_record_physical_bundle_suppress_identity_lifecycle_row_aligned", - "w2_retire_record_physical_bundle_suppress_identity_lifetime_aligned", - "w2_retire_record_physical_bundle_suppress_identity_eligible_registered_mask", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_no_captured_identity", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_record", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_rid_mismatch", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_load_lsid_mismatch", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_missing_lifecycle_evidence", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_lifecycle_row_mismatch", - "w2_retire_record_physical_bundle_suppress_identity_blocked_by_not_full_mask", - "w2_retire_record_physical_bundle_suppress_ownership_capture_ownership", - "w2_retire_record_physical_bundle_suppress_ownership_captured_ownership_valid", - "w2_retire_record_physical_bundle_suppress_ownership_registered_candidate", - "w2_retire_record_physical_bundle_suppress_ownership_registered_rid_valid", - "w2_retire_record_physical_bundle_suppress_ownership_registered_load_lsid_valid", - "w2_retire_record_physical_bundle_suppress_ownership_registered_lifecycle_row_ready", - "w2_retire_record_physical_bundle_suppress_ownership_registered_bundle_ready", - "w2_retire_record_physical_bundle_suppress_ownership_eligible_registered_mask", - "w2_retire_record_physical_bundle_suppress_ownership_blocked_by_no_captured_ownership", - "w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_rid", - "w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_load_lsid", - "w2_retire_record_physical_bundle_suppress_ownership_blocked_by_missing_lifecycle_row", - "w2_retire_record_physical_bundle_suppress_ownership_blocked_by_not_full_mask", - "w2_retire_record_physical_bundle_suppress_live_mask_candidate", - "w2_retire_record_physical_bundle_suppress_live_mask_enabled_candidate", - "w2_retire_record_physical_bundle_suppress_live_mask_suppress_rob_complete", - "w2_retire_record_physical_bundle_suppress_live_mask_suppress_rf_writeback", - "w2_retire_record_physical_bundle_suppress_live_mask_suppress_wakeup", - "w2_retire_record_physical_bundle_suppress_live_mask_suppress_lifecycle_clear", - "w2_retire_record_physical_bundle_suppress_live_mask_suppress_mask_sum", - "w2_retire_record_physical_bundle_suppress_live_mask_all_or_none", - "w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_live_mask_disabled", - "w2_retire_record_physical_bundle_suppress_live_mask_blocked_by_no_eligible_ownership", - "w2_retire_record_physical_bundle_suppress_clear_proof_candidate", - "w2_retire_record_physical_bundle_suppress_clear_proof_full_mask", - "w2_retire_record_physical_bundle_suppress_clear_proof_fire_complete_aligned", - "w2_retire_record_physical_bundle_suppress_clear_proof_clear_intent_aligned", - "w2_retire_record_physical_bundle_suppress_clear_proof_live_clear_aligned", - "w2_retire_record_physical_bundle_suppress_clear_proof_row_fill_aligned", - "w2_retire_record_physical_bundle_suppress_clear_proof_lifecycle_clear_suppressed", - "w2_retire_record_physical_bundle_suppress_clear_proof_all_clear_aligned", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_partial_mask", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_fire_complete", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_clear_intent", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_live_clear", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_no_row_fill", - "w2_retire_record_physical_bundle_suppress_clear_proof_blocked_by_lifecycle_clear_still_enabled", - "resolve_queue_push_accepted", - "resolve_queue_valid", - "resolve_queue_push_accepted_first_cycle", - "resolve_queue_push_accepted_last_cycle", - "resolve_queue_valid_first_cycle", - "resolve_queue_valid_last_cycle", - "mdb_conflict_store_valid", - "mdb_conflict_store_valid_first_cycle", - "mdb_conflict_store_valid_last_cycle", - "mdb_conflict_store_with_resolve_queue_valid", - "mdb_conflict_store_with_resolve_queue_valid_first_cycle", - "mdb_conflict_store_with_resolve_queue_valid_last_cycle", - "mdb_conflict_store_without_resolve_queue_valid", - "mdb_conflict_active_candidate", - "mdb_conflict_resolve_candidate", - "mdb_conflict_resolve_candidate_first_cycle", - "mdb_conflict_resolve_candidate_last_cycle", - "mdb_conflict_valid", - "mdb_fanout_record_valid", - "mdb_fanout_record_accepted", - "mdb_fanout_record_processed", - "mdb_fanout_bmdb_report", - "mdb_fanout_ssit_nonempty", - "mdb_fanout_lookup_valid", - "mdb_fanout_lookup_accepted", - "mdb_fanout_lookup_processed", - "mdb_fanout_lookup_table_hit", - "mdb_fanout_lookup_first_after_nuke", - "mdb_fanout_lookup_conf_blocked", - "mdb_fanout_lookup_weight_blocked", - "mdb_fanout_lu_out_valid", - "mdb_fanout_lu_out_hit", - "mdb_fanout_su_out_valid", - "mdb_fanout_su_out_hit", - "mdb_fanout_su_wakeup_valid", - "mdb_lookup_wait_plan_lookup_hit", - "mdb_lookup_wait_plan_wait_intent_valid", - "mdb_lookup_wait_plan_request_valid", - "mdb_lookup_wait_plan_blocked_by_no_target", - "mdb_lookup_wait_plan_blocked_by_missing_store_index", - "mdb_lookup_wait_plan_blocked_by_missing_store_lsid", - "mdb_lookup_wait_plan_bridge_active", - "mdb_lookup_wait_plan_bridge_valid", - "mdb_lookup_wait_plan_bridge_source_store_index_fits", - "mdb_lookup_wait_plan_bridge_blocked_by_disabled", - "mdb_lookup_wait_plan_bridge_blocked_by_flush", - "mdb_lookup_wait_plan_bridge_blocked_by_no_request", - "mdb_lookup_wait_plan_bridge_invalid_store_index_out_of_range", - "mdb_lookup_wait_plan_bridge_invalid_conflicting_status_write", - "mdb_lookup_wait_plan_bridge_invalid_wait_store_without_wait_status", - "mdb_lookup_wait_plan_bridge_invalid_return_without_split_sources", - "liq_row_mutation_bridge_valid", - "liq_row_mutation_selected_source_return", - "liq_row_mutation_selected_mdb_wait_plan", - "liq_row_mutation_source_conflict", - "mdb_wait_plan_row_mutation_write_enable", - "liq_row_mutation_write_enable", - "liq_row_mutation_apply_valid", - "liq_row_mutation_blocked_by_bridge", - "liq_row_mutation_blocked_by_control", -] - - -def parse_args() -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("stats", type=Path, help="sideband stats JSON report") - parser.add_argument( - "--expect-reduced-store-replay-liq", - action="store_true", - help="require reduced_store_replay_liq_top=true", - ) - parser.add_argument( - "--require-nonzero", - action="append", - default=[], - metavar="replay_liq.KEY", - help="require a validated counter to be greater than zero", - ) - parser.add_argument( - "--require-zero", - action="append", - default=[], - metavar="replay_liq.KEY", - help="require a validated counter to be exactly zero", - ) - parser.add_argument( - "--preset", - action="append", - choices=sorted(PRESETS), - default=[], - help="apply a named bundle of replay-LIQ counter requirements", - ) - return parser.parse_args() - - -def load_stats(path: Path) -> dict: - try: - with path.open("r", encoding="utf-8") as f: - return json.load(f) - except OSError as exc: - print(f"error: failed to read sideband stats {path}: {exc}", file=sys.stderr) - sys.exit(2) - except json.JSONDecodeError as exc: - print(f"error: malformed sideband stats {path}: {exc}", file=sys.stderr) - sys.exit(2) - - -def validate_replay_liq(stats: dict, expect_replay_liq: bool) -> dict[str, int]: - schema = stats.get("schema") - if schema != SCHEMA: - print(f"error: unexpected sideband stats schema {schema!r}", file=sys.stderr) - sys.exit(2) - - if stats.get("reduced_store_replay_liq_top") is not expect_replay_liq: - print( - "error: sideband stats reduced_store_replay_liq_top does not match " - f"expected value {expect_replay_liq}", - file=sys.stderr, - ) - sys.exit(2) - - replay_liq = stats.get("replay_liq") - if not isinstance(replay_liq, dict): - print("error: sideband stats missing replay_liq object", file=sys.stderr) - sys.exit(2) - - for key in REQUIRED_REPLAY_LIQ_KEYS: - value = replay_liq.get(key) - if not isinstance(value, int) or value < 0: - print(f"error: replay_liq.{key} must be a nonnegative integer", file=sys.stderr) - sys.exit(2) - - if replay_liq["cycles_sampled"] <= 0: - print("error: replay_liq.cycles_sampled must be positive", file=sys.stderr) - sys.exit(2) - - return replay_liq - - -def require_nonzero(replay_liq: dict[str, int], selectors: list[str]) -> None: - for selector in selectors: - if not selector.startswith("replay_liq."): - print( - f"error: unsupported nonzero selector {selector!r}; expected replay_liq.KEY", - file=sys.stderr, - ) - sys.exit(2) - key = selector.removeprefix("replay_liq.") - if key not in replay_liq: - print(f"error: unknown replay_liq counter {key!r}", file=sys.stderr) - sys.exit(2) - if replay_liq[key] <= 0: - print( - f"error: replay_liq.{key} must be nonzero, observed {replay_liq[key]}", - file=sys.stderr, - ) - sys.exit(1) - - -def require_zero(replay_liq: dict[str, int], selectors: list[str]) -> None: - for selector in selectors: - if not selector.startswith("replay_liq."): - print( - f"error: unsupported zero selector {selector!r}; expected replay_liq.KEY", - file=sys.stderr, - ) - sys.exit(2) - key = selector.removeprefix("replay_liq.") - if key not in replay_liq: - print(f"error: unknown replay_liq counter {key!r}", file=sys.stderr) - sys.exit(2) - if replay_liq[key] != 0: - print( - f"error: replay_liq.{key} must be zero, observed {replay_liq[key]}", - file=sys.stderr, - ) - sys.exit(1) - - -def main() -> int: - args = parse_args() - stats = load_stats(args.stats) - replay_liq = validate_replay_liq(stats, args.expect_reduced_store_replay_liq) - preset_nonzero: list[str] = [] - preset_zero: list[str] = [] - for preset_name in args.preset: - preset = PRESETS[preset_name] - preset_nonzero.extend(preset["nonzero"]) - preset_zero.extend(preset["zero"]) - require_nonzero(replay_liq, [*preset_nonzero, *args.require_nonzero]) - require_zero(replay_liq, [*preset_zero, *args.require_zero]) - print(f"sideband_stats_json={args.stats}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main()) diff --git a/tools/chisel/validate_reduced_store_wait_replay_chisel_path.py b/tools/chisel/validate_reduced_store_wait_replay_chisel_path.py deleted file mode 100755 index 7fdfcb07..00000000 --- a/tools/chisel/validate_reduced_store_wait_replay_chisel_path.py +++ /dev/null @@ -1,177 +0,0 @@ -#!/usr/bin/env python3 -"""Validate reduced store wait/replay generated-RTL reports.""" - -from __future__ import annotations - -import argparse -import json -import sys -from pathlib import Path -from typing import Any - - -SCHEMA = "linxcore.reduced_store_wait_replay_chisel_path.v1" - -REQUIRED_KEYS = [ - "cycles", - "ready_forward_observed", - "sta_wait_capture", - "not_ready_wake_blocked", - "std_wake_clear", - "relaunch_queue_fire", - "liq_alloc", - "liq_refill", - "liq_launch_valid", - "liq_launch_accepted", - "liq_e4_update", - "liq_lhq_record", - "liq_resolved", - "resolve_queue_push", - "resolve_queue_retired", - "mdb_resolve_conflict", - "mdb_nuke_flush", - "mdb_fanout_record_accepted", - "mdb_fanout_record_processed", - "mdb_bmdb_report", - "mdb_lookup_hit", - "mdb_su_wakeup", - "mdb_lookup_wait_plan_no_target", - "mdb_lookup_wait_plan_live_target", - "mdb_lookup_wait_plan_request", - "mdb_lookup_wait_plan_bridge", - "mdb_lookup_wait_plan_scb_evidence", - "mdb_lookup_wait_plan_write", - "mdb_lookup_wait_plan_apply", - "mdb_lookup_wait_plan_wait_status_after_write", - "liq_replay_wake_completed_mask", - "liq_scb_returned_mask_before_mdb_write", - "liq_sources_returned_mask_before_mdb_write", - "liq_wait_mask_after_mdb_write", - "liq_wait_store_mask_after_mdb_write", -] - - -def parse_args() -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("report", type=Path, help="reduced-store wait/replay JSON report") - parser.add_argument( - "--require-true", - action="append", - default=[], - metavar="KEY", - help="require a report boolean field to be true", - ) - parser.add_argument( - "--require-false", - action="append", - default=[], - metavar="KEY", - help="require a report boolean field to be false", - ) - parser.add_argument( - "--require-nonzero", - action="append", - default=[], - metavar="KEY", - help="require a report integer field to be greater than zero", - ) - parser.add_argument( - "--require-zero", - action="append", - default=[], - metavar="KEY", - help="require a report integer field to be exactly zero", - ) - return parser.parse_args() - - -def load_report(path: Path) -> dict[str, Any]: - try: - with path.open("r", encoding="utf-8") as f: - report = json.load(f) - except OSError as exc: - print(f"error: failed to read reduced-store report {path}: {exc}", file=sys.stderr) - sys.exit(2) - except json.JSONDecodeError as exc: - print(f"error: malformed reduced-store report {path}: {exc}", file=sys.stderr) - sys.exit(2) - - if not isinstance(report, dict): - print("error: reduced-store report must be a JSON object", file=sys.stderr) - sys.exit(2) - return report - - -def validate_schema(report: dict[str, Any]) -> None: - schema = report.get("schema") - if schema != SCHEMA: - print(f"error: unexpected reduced-store report schema {schema!r}", file=sys.stderr) - sys.exit(2) - - for key in REQUIRED_KEYS: - if key not in report: - print(f"error: reduced-store report missing required key {key!r}", file=sys.stderr) - sys.exit(2) - - cycles = report["cycles"] - if not isinstance(cycles, int) or cycles <= 0: - print("error: reduced-store report cycles must be a positive integer", file=sys.stderr) - sys.exit(2) - - -def get_key(report: dict[str, Any], key: str) -> Any: - if key not in report: - print(f"error: unknown reduced-store report key {key!r}", file=sys.stderr) - sys.exit(2) - return report[key] - - -def require_bool(report: dict[str, Any], selectors: list[str], expected: bool) -> None: - for key in selectors: - value = get_key(report, key) - if not isinstance(value, bool): - print(f"error: reduced-store report {key} must be a boolean", file=sys.stderr) - sys.exit(2) - if value is not expected: - print( - f"error: reduced-store report {key} must be {str(expected).lower()}, " - f"observed {str(value).lower()}", - file=sys.stderr, - ) - sys.exit(1) - - -def require_int(report: dict[str, Any], selectors: list[str], zero: bool) -> None: - for key in selectors: - value = get_key(report, key) - if not isinstance(value, int) or isinstance(value, bool): - print(f"error: reduced-store report {key} must be an integer", file=sys.stderr) - sys.exit(2) - if zero and value != 0: - print( - f"error: reduced-store report {key} must be zero, observed {value}", - file=sys.stderr, - ) - sys.exit(1) - if not zero and value <= 0: - print( - f"error: reduced-store report {key} must be nonzero, observed {value}", - file=sys.stderr, - ) - sys.exit(1) - - -def main() -> int: - args = parse_args() - report = load_report(args.report) - validate_schema(report) - require_bool(report, args.require_true, True) - require_bool(report, args.require_false, False) - require_int(report, args.require_nonzero, zero=False) - require_int(report, args.require_zero, zero=True) - print(f"reduced_store_wait_replay_chisel_path_json={args.report}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main()) diff --git a/tools/chisel/validate_replay_liq_coremark_context_pack.py b/tools/chisel/validate_replay_liq_coremark_context_pack.py deleted file mode 100755 index 590fd2f4..00000000 --- a/tools/chisel/validate_replay_liq_coremark_context_pack.py +++ /dev/null @@ -1,214 +0,0 @@ -#!/usr/bin/env python3 -"""Validate replay-LIQ CoreMark context-pack evidence boundaries.""" - -from __future__ import annotations - -import argparse -import copy -import json -import sys -from pathlib import Path -from typing import Any - - -COREMARK_ZERO_COUNTERS = ( - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "mdb_conflict_valid", - "mdb_lookup_wait_plan_request_valid", - "liq_replay_wake_wait_store_clear", -) - -CONSTRUCTED_NONZERO_COUNTERS = ( - "wait_replay_capture_accepted", - "replay_queue_out_fire", - "liq_alloc_accepted", - "liq_base_lookup_granted", - "resolve_queue_push_accepted", - "mdb_conflict_valid", - "mdb_fanout_record_processed", - "mdb_fanout_lookup_table_hit", - "mdb_lookup_wait_plan_request_valid", - "liq_replay_wake_wait_store_clear", -) - -CONSTRUCTED_ZERO_COUNTERS = ("mdb_fanout_su_wakeup_valid",) - - -def load_json(path: Path) -> dict[str, Any]: - with path.open("r", encoding="utf-8") as f: - data = json.load(f) - if not isinstance(data, dict): - raise ValueError(f"{path} did not contain a JSON object") - return data - - -def summary_value(section: dict[str, Any], key: str) -> int: - summary = section.get("summary") - if not isinstance(summary, dict): - raise AssertionError("missing summary object") - value = summary.get(key) - if not isinstance(value, int): - raise AssertionError(f"summary.{key} is not an integer") - return value - - -def sideband_value(section: dict[str, Any], key: str) -> int: - sideband = section.get("sideband") - if not isinstance(sideband, dict): - raise AssertionError("missing sideband object") - value = sideband.get(key) - if value is None: - manifest_path = section.get("manifest") - if isinstance(manifest_path, str): - raw_sideband_path = Path(manifest_path).with_name("frontend_fetch_rf_alu_sideband_stats.json") - if raw_sideband_path.is_file(): - raw_sideband = load_json(raw_sideband_path).get("replay_liq", {}) - if isinstance(raw_sideband, dict): - value = raw_sideband.get(key) - if not isinstance(value, int): - raise AssertionError(f"sideband.{key} is not an integer") - return value - - -def check_passed_section(name: str, section: Any) -> list[str]: - errors: list[str] = [] - if not isinstance(section, dict): - return [f"{name}: missing section object"] - if section.get("status") != "pass": - errors.append(f"{name}: status is {section.get('status')!r}, expected 'pass'") - try: - compared = summary_value(section, "compared_rows") - mismatches = summary_value(section, "mismatch_count") - except AssertionError as exc: - errors.append(f"{name}: {exc}") - else: - if compared <= 0: - errors.append(f"{name}: compared_rows must be positive") - if mismatches != 0: - errors.append(f"{name}: mismatch_count must be zero, got {mismatches}") - return errors - - -def validate_manifest(manifest: dict[str, Any]) -> list[str]: - errors: list[str] = [] - if manifest.get("schema") != "linxcore.replay_liq_coremark_context_pack.v1": - errors.append("manifest: unexpected schema") - if manifest.get("status") != "pass": - errors.append(f"manifest: status is {manifest.get('status')!r}, expected 'pass'") - boundary = manifest.get("claim_boundary") - if not isinstance(boundary, str) or "CoreMark prefix" not in boundary or "constructed replay loop" not in boundary: - errors.append("manifest: claim_boundary must name CoreMark prefix and constructed replay loop") - if manifest.get("evidence_kind") != "coremark_context_pack_plus_constructed_replay_liq": - errors.append("manifest: unexpected evidence_kind") - - coremark = manifest.get("coremark_prefix") - constructed = manifest.get("constructed_replay_loop") - errors.extend(check_passed_section("coremark_prefix", coremark)) - errors.extend(check_passed_section("constructed_replay_loop", constructed)) - if not isinstance(coremark, dict) or not isinstance(constructed, dict): - return errors - - allow_natural = bool(manifest.get("natural_coremark_replay_allowed", False)) - if not allow_natural: - for counter in COREMARK_ZERO_COUNTERS: - try: - value = sideband_value(coremark, counter) - except AssertionError as exc: - errors.append(f"coremark_prefix: {exc}") - continue - if value != 0: - errors.append(f"coremark_prefix: {counter} must be zero, got {value}") - - for counter in CONSTRUCTED_NONZERO_COUNTERS: - try: - value = sideband_value(constructed, counter) - except AssertionError as exc: - errors.append(f"constructed_replay_loop: {exc}") - continue - if value <= 0: - errors.append(f"constructed_replay_loop: {counter} must be nonzero, got {value}") - - for counter in CONSTRUCTED_ZERO_COUNTERS: - try: - value = sideband_value(constructed, counter) - except AssertionError as exc: - errors.append(f"constructed_replay_loop: {exc}") - continue - if value != 0: - errors.append(f"constructed_replay_loop: {counter} must be zero, got {value}") - - return errors - - -def sample_manifest() -> dict[str, Any]: - sideband_zero = {key: 0 for key in COREMARK_ZERO_COUNTERS} - constructed_sideband = {key: 1 for key in CONSTRUCTED_NONZERO_COUNTERS} - constructed_sideband["mdb_fanout_su_wakeup_valid"] = 0 - return { - "schema": "linxcore.replay_liq_coremark_context_pack.v1", - "status": "pass", - "evidence_kind": "coremark_context_pack_plus_constructed_replay_liq", - "claim_boundary": ( - "CoreMark prefix is no-regression evidence; " - "constructed replay loop is positive LIQ/MDB evidence." - ), - "natural_coremark_replay_allowed": False, - "coremark_prefix": { - "status": "pass", - "summary": {"compared_rows": 4, "mismatch_count": 0}, - "sideband": sideband_zero, - }, - "constructed_replay_loop": { - "status": "pass", - "summary": {"compared_rows": 3, "mismatch_count": 0}, - "sideband": constructed_sideband, - }, - } - - -def run_self_test() -> None: - passing = sample_manifest() - if validate_manifest(passing): - raise AssertionError("valid sample manifest failed validation") - failing = copy.deepcopy(passing) - failing["coremark_prefix"]["sideband"]["liq_alloc_accepted"] = 1 - if not validate_manifest(failing): - raise AssertionError("coremark natural replay violation was not detected") - failing = copy.deepcopy(passing) - failing["constructed_replay_loop"]["sideband"]["mdb_conflict_valid"] = 0 - if not validate_manifest(failing): - raise AssertionError("constructed nonzero violation was not detected") - failing = copy.deepcopy(passing) - failing["constructed_replay_loop"]["sideband"]["mdb_fanout_su_wakeup_valid"] = 1 - if not validate_manifest(failing): - raise AssertionError("constructed zero violation was not detected") - - -def parse_args(argv: list[str]) -> argparse.Namespace: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("manifest", nargs="?", type=Path, help="R525 context-pack manifest JSON") - parser.add_argument("--self-test", action="store_true", help="run built-in validator checks") - return parser.parse_args(argv) - - -def main(argv: list[str]) -> int: - args = parse_args(argv) - if args.self_test: - run_self_test() - print("replay-liq-coremark-context-pack-validator self-test: ok") - if args.manifest is None: - return 0 - manifest = load_json(args.manifest) - errors = validate_manifest(manifest) - if errors: - for error in errors: - print(f"error: {error}", file=sys.stderr) - return 1 - print(f"replay-liq-coremark-context-pack-validator: ok manifest={args.manifest}") - return 0 - - -if __name__ == "__main__": - raise SystemExit(main(sys.argv[1:])) diff --git a/tools/generate/opcode_catalog_lib.py b/tools/generate/opcode_catalog_lib.py index eeab7a83..f28f9744 100644 --- a/tools/generate/opcode_catalog_lib.py +++ b/tools/generate/opcode_catalog_lib.py @@ -79,6 +79,10 @@ OP_ID_CATEGORY_OVERRIDES = { # Preserve existing opcode IDs when repairing the product category. + "OP_C_LDI": "COMPRESSED", + "OP_C_LWI": "COMPRESSED", + "OP_C_SDI": "COMPRESSED", + "OP_C_SWI": "COMPRESSED", "OP_HL_SDI": "ALU_INT", "OP_HL_SDI_PO": "ALU_INT", "OP_HL_SDI_PR": "ALU_INT", @@ -197,6 +201,8 @@ def mnemonic_to_symbol(mnemonic: str) -> str: def classify_major_minor(mnemonic: str) -> tuple[str, str]: m = mnemonic.lower() + compact_loads = {"c_ldi", "c_lwi"} + compact_stores = {"c_sdi", "c_swi"} hl_sdi_immediate_stores = { "hl_sdi", "hl_sdi_u", @@ -219,6 +225,10 @@ def classify_major_minor(mnemonic: str) -> tuple[str, str]: return "STORE", "atomic" if m in {"casb", "cash", "casw", "casd", "dma"}: return "ALU_INT", "atomic" + if m in compact_loads: + return "LOAD", "compressed_load" + if m in compact_stores: + return "STORE", "compressed_store" if m.startswith("c_"): if m.startswith("c_bstart") or m == "c_bstop": return "BLOCK_BOUNDARY", "c_boundary" @@ -371,6 +381,8 @@ def block_kind_for_mnemonic(mnemonic: str) -> str: "OP_HL_DIV", "OP_HL_DIVU", "OP_HL_DIVUW", "OP_HL_DIVW", "OP_HL_REM", "OP_HL_REMU", "OP_HL_REMUW", "OP_HL_REMW", } +OOO_COMPACT_LOAD_SYMBOLS = {"OP_C_LDI", "OP_C_LWI"} +OOO_COMPACT_STORE_SYMBOLS = {"OP_C_SDI", "OP_C_SWI"} def _is_ooo_atomic_symbol(symbol: str) -> bool: @@ -573,7 +585,7 @@ def fast(recipe: str, fast_class: str, owner: str) -> None: return metadata if symbol in OOO_ENGINE_BOUNDARY_SYMBOLS: - dispatch("ENGINE_CMD", "CMD", "BCTRL") + dispatch("ENGINE_CMD", "CMD", "COMMIT") metadata.update({ "may_trap": True, "may_redirect": True, @@ -608,6 +620,12 @@ def fast(recipe: str, fast_class: str, owner: str) -> None: if major == "LOAD": dispatch("SCALAR_LOAD", "AGU", "LSU") metadata.update({"may_trap": True, "may_trap_late": True, "memory_request_count": 1}) + if symbol in OOO_COMPACT_LOAD_SYMBOLS: + metadata.update({ + "p_destination_count": 0, + "t_allocation_count": 1, + "reason": "compact scalar load allocates the next T destination", + }) return metadata if major == "STORE": @@ -627,6 +645,13 @@ def fast(recipe: str, fast_class: str, owner: str) -> None: "p_source_count": 3 if symbol in OOO_INDEXED_SCALAR_STORE_SYMBOLS else metadata["p_source_count"], }) + if symbol in OOO_COMPACT_STORE_SYMBOLS: + metadata.update({ + # The encoded base is a P source; T#1 is an architectural + # relative source inserted by FrontendOperandDecode. + "p_source_count": 2, + "reason": "compact scalar store consumes base plus relative T#1", + }) return metadata if major == "BRU_SETC_CMP": @@ -654,7 +679,8 @@ def fast(recipe: str, fast_class: str, owner: str) -> None: return metadata if major in {"BLOCK_ARGS_DESC", "CMD_PIPE"}: - dispatch("SINGLE", "CMD", "BCTRL") + dispatch("SINGLE", "CMD", "COMMIT") + metadata["nonspeculative"] = True return metadata if major == "MISC": diff --git a/tools/setup_superpowers.sh b/tools/setup_superpowers.sh new file mode 100755 index 00000000..7fb89280 --- /dev/null +++ b/tools/setup_superpowers.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")/.." && pwd)" +SUPERPOWERS_DIR="${ROOT_DIR}/tools/superpowers" +EXPECTED_TAG="v6.2.0" +EXPECTED_COMMIT="3dcbd5c4b48e02263fbf4a3c01e3fe4f81d584d9" + +git -C "${ROOT_DIR}" submodule update --init --recursive tools/superpowers + +actual_commit="$(git -C "${SUPERPOWERS_DIR}" rev-parse HEAD)" +if [[ "${actual_commit}" != "${EXPECTED_COMMIT}" ]]; then + echo "error: Superpowers pin ${actual_commit} does not match ${EXPECTED_COMMIT}" >&2 + exit 1 +fi + +actual_tag="$(git -C "${SUPERPOWERS_DIR}" describe --tags --exact-match)" +if [[ "${actual_tag}" != "${EXPECTED_TAG}" ]]; then + echo "error: Superpowers tag ${actual_tag} does not match ${EXPECTED_TAG}" >&2 + exit 1 +fi + +codex plugin marketplace add "${SUPERPOWERS_DIR}" --json +codex plugin add superpowers@superpowers-dev --json +codex plugin list | sed -n '/Marketplace `superpowers-dev`/,+4p' diff --git a/tools/spec/check_ndf_profile.py b/tools/spec/check_ndf_profile.py new file mode 100644 index 00000000..9479ddd1 --- /dev/null +++ b/tools/spec/check_ndf_profile.py @@ -0,0 +1,297 @@ +#!/usr/bin/env python3 +"""Validate the LinxCore NDF documentation profile.""" + +from __future__ import annotations + +import argparse +import hashlib +import re +import shlex +import subprocess +import sys +from dataclasses import dataclass, field +from pathlib import Path + + +CLAUSE_RE = re.compile(r"^#{2,6}\s+.+?\s+\{#([A-Z][A-Z0-9-]*)\}\s*$") +METADATA_RE = re.compile(r"") +CROSS_REFERENCE_RE = re.compile(r"\[\[([A-Z][A-Z0-9-]*)\]\]") +HEX40_RE = re.compile(r"^[0-9a-f]{40}$") +HEX64_RE = re.compile(r"^[0-9a-f]{64}$") +REQUIRED_METADATA = ("kind", "level", "layer", "status") +EDGE_KEYS = ( + "refines", + "depends-on", + "conflicts-with", + "couples-with", + "verifies", + "affects", + "blocks", +) +ORIGIN_STATUSES = {"verbatim", "paraphrase", "interpretation"} + + +@dataclass +class Clause: + identifier: str + path: Path + line: int + metadata: dict[str, str] = field(default_factory=dict) + text: list[str] = field(default_factory=list) + + +def parse_metadata(raw: str, clause: Clause, errors: list[str]) -> None: + try: + tokens = shlex.split(raw) + except ValueError as error: + errors.append( + f"{clause.path}:{clause.line}: invalid metadata for " + f"{clause.identifier}: {error}" + ) + return + + for token in tokens: + if "=" not in token: + errors.append( + f"{clause.path}:{clause.line}: invalid metadata token " + f"{token!r} for {clause.identifier}" + ) + continue + key, value = token.split("=", 1) + if key in clause.metadata and clause.metadata[key] != value: + errors.append( + f"{clause.path}:{clause.line}: conflicting metadata {key} " + f"for {clause.identifier}" + ) + continue + clause.metadata[key] = value + + +def load_clauses(spec_root: Path) -> tuple[list[Clause], list[str]]: + clauses: list[Clause] = [] + errors: list[str] = [] + + for path in sorted(spec_root.rglob("*.md")): + current: Clause | None = None + for line_number, line in enumerate( + path.read_text(encoding="utf-8").splitlines(), start=1 + ): + heading = CLAUSE_RE.match(line) + if heading: + current = Clause(heading.group(1), path, line_number) + clauses.append(current) + continue + if current is None: + continue + current.text.append(line) + for metadata in METADATA_RE.findall(line): + parse_metadata(metadata, current, errors) + + return clauses, errors + + +def split_targets(value: str) -> list[str]: + return [target for target in re.split(r"[,;]", value) if target] + + +def validate_local_reference(clause: Clause, errors: list[str]) -> None: + origin_kind = clause.metadata.get("origin-kind") + if origin_kind == "file": + origin = Path(clause.metadata["origin"]).expanduser() + if not origin.is_file(): + errors.append( + f"{clause.path}:{clause.line}: local reference missing for " + f"{clause.identifier}: {origin}" + ) + return + actual = hashlib.sha256(origin.read_bytes()).hexdigest() + if actual != clause.metadata["sha256"]: + errors.append( + f"{clause.path}:{clause.line}: local reference hash mismatch for " + f"{clause.identifier}" + ) + return + + if origin_kind == "git" and "checkout" in clause.metadata: + checkout = Path(clause.metadata["checkout"]).expanduser() + if not checkout.is_dir(): + errors.append( + f"{clause.path}:{clause.line}: local reference checkout missing for " + f"{clause.identifier}: {checkout}" + ) + return + result = subprocess.run( + [ + "git", + "-C", + str(checkout), + "cat-file", + "-t", + clause.metadata["revision"], + ], + text=True, + capture_output=True, + check=False, + ) + object_type = result.stdout.strip() + if result.returncode != 0 or object_type != "commit": + errors.append( + f"{clause.path}:{clause.line}: local reference revision mismatch for " + f"{clause.identifier}" + ) + + +def validate( + spec_root: Path, *, verify_local_references: bool +) -> tuple[list[Clause], list[str]]: + clauses, errors = load_clauses(spec_root) + by_identifier: dict[str, Clause] = {} + + for clause in clauses: + if clause.identifier in by_identifier: + errors.append( + f"{clause.path}:{clause.line}: duplicate clause id " + f"{clause.identifier}" + ) + else: + by_identifier[clause.identifier] = clause + + for key in REQUIRED_METADATA: + if key not in clause.metadata: + errors.append( + f"{clause.path}:{clause.line}: missing metadata {key} " + f"for {clause.identifier}" + ) + + for clause in clauses: + targets: list[str] = [] + for key in EDGE_KEYS: + if key in clause.metadata: + targets.extend(split_targets(clause.metadata[key])) + targets.extend( + match + for line in clause.text + for match in CROSS_REFERENCE_RE.findall(line) + ) + for target in sorted(set(targets)): + if target not in by_identifier: + errors.append( + f"{clause.path}:{clause.line}: dangling reference {target} " + f"from {clause.identifier}" + ) + + if not clause.identifier.startswith("REF-"): + continue + + reference_error_count = len(errors) + origin_kind = clause.metadata.get("origin-kind") + origin_status = clause.metadata.get("origin-status") + if origin_kind not in {"file", "git"}: + errors.append( + f"{clause.path}:{clause.line}: invalid origin-kind for " + f"{clause.identifier}" + ) + if origin_status not in ORIGIN_STATUSES: + errors.append( + f"{clause.path}:{clause.line}: invalid origin-status for " + f"{clause.identifier}" + ) + if origin_kind == "file": + if "origin" not in clause.metadata: + errors.append( + f"{clause.path}:{clause.line}: missing origin for " + f"{clause.identifier}" + ) + digest = clause.metadata.get("sha256", "") + if not HEX64_RE.fullmatch(digest): + errors.append( + f"{clause.path}:{clause.line}: invalid sha256 for " + f"{clause.identifier}" + ) + elif origin_kind == "git": + if "repository" not in clause.metadata: + errors.append( + f"{clause.path}:{clause.line}: missing repository for " + f"{clause.identifier}" + ) + revision = clause.metadata.get("revision", "") + if not HEX40_RE.fullmatch(revision): + errors.append( + f"{clause.path}:{clause.line}: invalid revision for " + f"{clause.identifier}" + ) + + if verify_local_references and len(errors) == reference_error_count: + validate_local_reference(clause, errors) + + verification_targets = { + target + for clause in clauses + if clause.metadata.get("kind") == "verif" + for target in split_targets(clause.metadata.get("verifies", "")) + } + l1_must = [ + clause + for clause in clauses + if clause.metadata.get("kind") == "req" + and clause.metadata.get("level") == "must" + and clause.metadata.get("layer") == "L1" + ] + for clause in l1_must: + if clause.identifier not in verification_targets: + errors.append( + f"{clause.path}:{clause.line}: missing verifies edge for L1 MUST " + f"{clause.identifier}" + ) + + return clauses, errors + + +def main() -> int: + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("spec_root", type=Path) + parser.add_argument( + "--verify-local-references", + action="store_true", + help="also compare pinned identities with available local sources", + ) + args = parser.parse_args() + + if not (args.spec_root / "ndf.yaml").is_file(): + print(f"{args.spec_root}: missing ndf.yaml", file=sys.stderr) + return 1 + + clauses, errors = validate( + args.spec_root, verify_local_references=args.verify_local_references + ) + if errors: + for error in errors: + print(error, file=sys.stderr) + return 1 + + l1_must = sum( + clause.metadata.get("kind") == "req" + and clause.metadata.get("level") == "must" + and clause.metadata.get("layer") == "L1" + for clause in clauses + ) + verification_targets = { + target + for clause in clauses + if clause.metadata.get("kind") == "verif" + for target in split_targets(clause.metadata.get("verifies", "")) + } + open_questions = sum( + clause.metadata.get("status") in {"open", "tbd"} for clause in clauses + ) + references = sum(clause.identifier.startswith("REF-") for clause in clauses) + print( + f"clauses={len(clauses)} l1_must={l1_must} " + f"verified={len(verification_targets)} " + f"open_questions={open_questions} references={references}" + ) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/superpowers b/tools/superpowers new file mode 160000 index 00000000..3dcbd5c4 --- /dev/null +++ b/tools/superpowers @@ -0,0 +1 @@ +Subproject commit 3dcbd5c4b48e02263fbf4a3c01e3fe4f81d584d9