Latch-based memories are significantly more efficient than FF-based memories. The ram module should be able to identify whether the -storage_cell is a flip-flop or a latch. If it is the former, the current structure is used. If the latter, a new latch-based array should be used.
A latch-based array is very similar to a flop-based array, except that an additional row of latches is required for each write port. Instead of the input data being connected to a bitcell of each word (usually through an input buffer), the data is instead connected to the D port of a negative (active low) latch first, and then the Q port of this latch is connected to the D port of each bitcell. The bitcell in this case is a positive latch.
I'm not sure if an input buffer should be before or after the latch (or both). It would take some timing analysis to figure that out, which can be a later enhancement.
Latch-based memories are significantly more efficient than FF-based memories. The ram module should be able to identify whether the
-storage_cellis a flip-flop or a latch. If it is the former, the current structure is used. If the latter, a new latch-based array should be used.A latch-based array is very similar to a flop-based array, except that an additional row of latches is required for each write port. Instead of the input data being connected to a bitcell of each word (usually through an input buffer), the data is instead connected to the D port of a negative (active low) latch first, and then the Q port of this latch is connected to the D port of each bitcell. The bitcell in this case is a positive latch.
I'm not sure if an input buffer should be before or after the latch (or both). It would take some timing analysis to figure that out, which can be a later enhancement.